HIGH-SPEED SEMICONDUCTOR DEVICE

Abstract: A high-speed semiconductor device including an emitter layer (18); a base layer (15); a collector layer (13); a potential-barrier layer (14) disposed between the base layer and the collector layer; and a superlattice (16) disposed between the emitter layer and the base layer. The superlat­ tice is formed with at least one quantum well therein and has a low impedance state for tunneling carriers therethrough. Preferably, the high-speed semiconductor device may further include a graded layer (17) disposed between the emitter layer and the superlattice. The graded layer has a conduction-energy level which is approximately equal to that of the emitter layer at one end and is approximately equal to a predetermined conduction-energy level of the superlattice at another end. In addition, the high-speed semiconductor device may act as a frequency multiplier.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed semiconductor device, more particularly to a hot electron transistor (HET) device which includes a heterojunction emitter, base, collector, and a superlattice means between the emitter and the base. 2. Description of the Related Art The principle of an HET has long been known (C.A. Mead, Proc. IRE48, 359, 1960). This old HET, however, was structured by stacked metal and oxide layers, thus could not be applied to actual semiconductor devices. Recently, due to advances in semiconductor processing technology, such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD), new HET's having, for example, n-type gallium-arsenic (GaAs) layers instead of the above metal layers and aluminum-gallium-arsenic (AlGaAs) layers instead of the above oxide layers have been developed (e.g., "Characterization of Double Heterojunction GaAs/AlGaAs Hot Electron Transistors", N. Yokoyama, et al. PROCEEDINGS OF THE IEEE INTERNATIONAL ELECTRON DEVICES MEETING, Dec. 1984, pp 532 to 535; see also J. Appl. Phys. vol. 54, no. 11, November 1983 p.6725-6731 disclosing a double heterojunction bipolar transistor with a superlattice interface). These new HET's, however, suffer from low current amplification of transistors. SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed semiconductor device with improved transistor current amplification. It is another object of the present invention to provide a high-speed semiconductor device outputting a multiplied frequency signal for a single input pulse signal. According to the present invention, there is provided a high-speed semiconductor device, comprising an emitter layer having a conduction band with a first energy level, a base layer formed under said emitter layer and having a conduction band with a second energy level, a collector layer, a collector side potential-barrier means disposed between said base layer and said collector semiconductor layer, and a superlattice construction through which carriers can tunnel, provided at least between said emitter layer and base layer, characterized in that said superlattice construction comprises : a first potential barrier layer forming a heterojunction with said emitter layer and having a conduction band with a third energy level, said third energy level being higher than said first energy level so that the conduction band of said emitter layer and the conduction band of said first potential barrier layer have a discontinuity therebetween; a quantum well layer forming a heterojunction with said first potential barrier layer and having a conduction band with a fourth energy level, said fourth energy level being lower than said third energy level; and a second potential barrier layer forming a heterojunction with said quantum well layer and said base layer and having a conduction band with a fifth energy level, said fifth energy level being higher than said fourth and second energy levels; said first and second barrier layers being sufficiently thin for tunneling carriers therethrough, and said quantum well layer being sufficiently thin so as to have a sub-band therein. Preferably, the high-speed semiconductor device may further include a graded layer disposed between the emitter layer and the superlattice and having a conduction-energy level which is approximately equal to that of the emitter layer at one end and is also approximately equal to a predetermined conduction-energy level of the superlattice at another end, for allowing tunneling of the carriers therethrough. The carriers in the emitter layer are transported along the graded conduction-energy level in the graded layer, tunneled through the superlattice with the predetermined conduction-energy level and injected into the base layer. In addition, the high-speed semiconductor device may be given a predetermined DC bias for a resonant tunneling phenomenon of the carriers at the superlattice, thus may output a signal having a 2 to the "n" power multiplied frequency when an input pulse signal having a predetermined voltage range and predetermined slopes is supplied to the base layer. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and features of the present invention will be described below in detail with reference to the accompanying drawings, in which: Fig. 1 is a conduction-energy-band diagram of a prior art HET device; Fig. 2 is a graph of a collector current I C and collector-emitter voltage V CE characteristic of the prior art HET device; Fig. 3 is a graph of a conduction-energy-band structure of GaAs; Fig. 4 is a sectional view of a semifinished HET device of an embodiment of the present invention; Fig. 5 is a sectional view of the HET device shown in Fig. 4; Fig. 6 is a conduction-energy-band diagram of the HET device shown in Fig. 5; Fig. 7 is a conduction-energy-band diagram of another embodiment of an HET device in accordance with the present invention; Fig. 8 is a graph explaining formation of a mini-energy band at a superlattice in Fig. 7; Fig. 9 is a sectional view of still another embodiment of an HET device in accordance with the present invention; Fig. 10 is a conduction-energy-band diagram of the HET device shown in Fig. 9; Fig. 11 is a sectional view of a further embodiment of an HET device in accordance with the present invention; Fig. 12 is a conduction-energy-band diagram of the HET device shown in Fig. 11; Fig. 13 is a conduction-energy-band diagram of another embodiment of an HET device in accordance with the present invention; Fig. 14a to 14c are views explaining a resonant tunneling phenomenon at a superlattice in the HET device in Fig. 13; Fig. 15 is a graph showing current-voltage curves for a resonant tunneling structure shown in Figs. 14a to 14c; Fig. 16 is a circuit diagram showing an application of the resonant-tunneling HET device shown in Fig. 13; Fig. 17 is a graph showing characteristic curves of a collector current I C and collector-emitter voltage V CE ; Fig. 18 is a graph showing characteristic curves of an input voltage V IN and an output voltage V OUT of the transistor shown in Fig. 16; Fig. 19a and 19b are graphs of signal waveforms of the transistor in Fig. 16; Figs. 20a and 20b are views explaining a resonant tunneling phenomenon for multiquantum wells; and Fig. 21 is a graph showing electron energy and transmission coefficient characteristics for multiquantum wells. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing preferred embodiments of the present invention, an explanation will be given of the prior art for reference. Figure 1 is a conduction-energy-band diagram of a prior art HET device. In Fig. 1, reference E FE represents a pseudo-Fermi level at an n-type GaAs emitter layer 1, E FB a pseudo-Fermi level at an n-type GaAs base layer 3, E FC a pseudo-Fermi level at an n-type GaAs collector layer 5, e a hot electron tunneling through an emitter-side non- doped AlGaAs potential barrier layer 2, ΔE a conduction-band energy difference between the energy level of the barrier layer 2 and the energy level of the base 3, and ø c a conduction-band discontinuity. Between the base 3 and the collector 5, there is provided a non impurity doped AlGaAs potential barrier 4. In the above HET, when a DC bias is applied between the collector layer 5 and the emitter layer 1 and a positive voltage is supplied to the base layer 3 as shown in Fig. 1, the gradient of energy barrier at the potential barrier layer 2 is changed, resulting in a thin energy barrier. Consequently, electrons injected from the emitter layer 1 may be tunneled (passed) through the potential barrier layer 2 to inject into the base layer 3. The potential energy of the hot electrons injected into the base layer 3 may be changed to a kinetic energy due to ΔE C . As a result, the electrons injected into the base layer 3 become high-speed hot electrons. High-speed hot electrons having an energy level greater than ø c at the potential barrier layer 4 can be injected into the collector layer 5 over ø c at the potential barrier layer 4, in principle, without scattering. However, when the energy level of the electrons in the emitter layer 1 is low, the number of the electrons injected into the base layer 3 is low due to the considerably thick barrier wall at the potential barrier layer 2, resulting in a low collector current I C of the transistor, as shown in Fig. 2, representing a collector current I C and collector-emitter voltage V CE characteristic of the prior art HET device. In order to increase the number of the electrons injected from the emitter layer 1 into the base layer 3 and accordingly to increase a current amplification factor α of the transistor, the application of a higher voltage between the base layer 3 and the emitter layer 1 is required. If a voltage higher than that mentioned above is supplied between the base layer 3 and the emitter layer 1, the gradient of the barrier at the potential barrier layer 2 is changed as shown by the dashed line in Fig. 1 and the energy level of the electrons is increased to ΔE C ' as shown in Fig. 1. As a result, the number of the electrons injected into the base layer 3 should be increased in principle. However, the energy-band structure of GaAs must be considered. Figure 3 is a graph of an example of the conduction-energy-band structure of GaAs (See "Physics of Semiconductor Devices" Second Edition, by S.M. Sze, John Wiley & Sons, p 13). The energy-band structure includes a so-called L-valley, Γ-valley, and X-valley. When an electron is at the Γ-valley, the effective mass thereof is small and the mobility thereof is high. On the other hand, when the electron is at the X-valley or L-valley, the effective mass thereof is large and the mobility thereof is low. If the energy level of the electrons at the Γ-valley is lifted as shown in Fig. 3, the electrons can be affected by intervalley scattering, that is, the electrons in the Γ-valley can be transferred to the L- or X-valley by phonons. Due to the intervalley scattering, the electrons injected into the base layer 3 and having a high-energy level can be scattered in a variety of directions, decreasing the number of electrons reaching the collector layer 5. Accordingly, the benefit of increasing the voltage between the emitter layer 1 and the base layer 3 cannot be obtained. In the prior art HET device mentioned above, the current amplification factor a under 77°K is, for example, approximately 0.5 when the base layer is grounded and approximately 1 when the emitter layer is grounded. Preferred embodiments of the present invention will now be explained. A first embodiment of the HET device will be explained referring to Figs. 4 to 6. Figure 4 is a sectional view of a semifinished HET device. In Fig. 4, the HET device consists of a semi-insulating GaAs substrate 11, an n-type GaAs collector contact layer 12, an n-type GaAs collector layer 13, a non impurity-doped Al 0.3 Ga 0.7 As collector-side potential barrier layer 14, an n-type GaAs base layer 15, a superlattice, i.e., emitter-side potential barrier layer 16, and an n⁺-type GaAs emitter layer 18. The superlattice consisting of the non impurity-doped AlAs layers 16A1 and 16A2 and a non impurity-doped GaAs layer 16B formed between the non impurity-doped AlAs layers 16A1 and 16A2 is disposed between the emitter layer 18 and the base layer 15, instead of the non impurity-doped AlGaAs potential barrier layer 2 in the prior art mentioned above. The above construction of the HET device is formed by the MBE process. The following parameters apply for the layers of the HET device shown in Fig. 4, where d represents an impurity density and t a layer thickness; A. n-type GaAs collector-contact layer 12 d: 2x10¹⁸ cm⁻³ (2x10²⁴ m⁻³) t: 5000 Å (500 nm) B. n-type GaAs collector layer 13 d: 5x10¹⁷ cm⁻³ (5x10²³ m⁻³) t: 2000 Å (200 nm) C. n-type base layer 15 d: 5x10¹⁷ cm⁻³ (5x10²³ m⁻³) t: 1000 Å (100 nm) D. AlAs layers 16A1, 16A2 t: 30 Å (3 nm) E. GaAs layer 16B t: 30 Å (3 nm) F. n⁺-type GaAs emitter layer 18 d: 2x10¹⁸ cm⁻³ (2x10²⁴ m⁻³) t: 5000 Å (500 nm) Figure 5 is a sectional view of the HET device shown in Fig. 4. The HET device in Fig. 5 is formed from the semi-finished HET device as shown in Fig. 4 by the following processes: A. Mesa-etching is performed by a normal photolithography process on the top of the HET device until the n-type GaAs collector-contact layer 12 is exposed. B. Mesa-etching is again performed by a normal photolithography process on the top of the HET device until the n-type GaAs base layer 15 is exposed. C. Gold (Au)·Germanium (Ge)/Au films are formed by a vapor deposition process on the above exposed portions. In addition, patterning is effected by a normal photolithography process on the above Au·Ge/Au films, resulting in collector electrodes 19, base electrodes 20, and an emitter electrode 21. Figure 6 is a conduction-energy-band diagram of the HET device shown in Fig. 5. In the superlattice 16, a so-called GaAs quantum well 7 is formed. By forming the heterojunction layer of the extra-thin non impurity-doped AlAs layers 16A1 and 16A2 and the extra-thin non impurity-doped GaAs layer 16B between them, the motion of the electrons which move in a direction perpendicular to the heterojunction surface is quantized, with a resultant formation of the quantum well 7. The thickness of the above layers 16A1, 16A2, 16B can be 1 to 10 nm (10 Å to 100 Å), preferably 3 to 5 nm (30 Å to 50 Å). Incidentally "superlattice" has various definitions. In this specification, "superlattice" is defined as a layer (or region) formed with at least one quantum well therein. By applying voltage having polarities as shown in Fig. 6 between the emitter layer 18 and the base layer 15, the electrons in the emitter layer 18 are tunneled through the first thin potential barrier wall 81, whereby the electrons reach the quantum well region. Electrons having an energy level equal to a sub-band 91 are further tunneled through the second thin potential barrier wall 82. As a result, the hot electrons e are injected into the base layer 15. The above sub-band 91 delines an energy level Ee of the hot electrons in the base layer 15. In the quantum well 7, there may be a plurality of discrete sub-bands. Each sub-band may provide a low impedance state, because the sub-band may trap electrons having an energy equal to the sub-band, which are injected into the base layer 15 tunneling through the second thin barrier layer 16A2. In the embodiment, consideration is given to a sub-band with an energy level higher than the conduction-band discontinuity ø c and with a level as low as possible for avoiding intervalley scattering. The above energy level Ee of the hot electrons e, i.e., the sub-band 91, may be selectively defined by selecting the thickness of the heterojunction layers 16A1, 16B, and 16A2 in the superlattice 16. Note that electrons having the above energy level Ee are not affected by the voltage level applied between the emitter layer 18 and the base layer 15. Accordingly, the hot electrons e injected into the base layer 15 are ballistically transported to the collector layer 13 with a high speed and without intervalley scattering. In other words, the current amplification factor α is increased due to the increase of arrival of hot electrons to the collector layer 13. Figure 7 is a conduction-energy-band diagram of another embodiment of an HET device in accordance with the present invention. The HET device includes a superlattice 16', which consists of non impurity-doped AlAs layers 16A1 to 16A4 and non impurity-doped GaAs layers 16B1 to 16B3, each of which has a thickness of 30 Å (3 nm) as mentioned above. That is, the superlattice 16' has a periodical structure of alternatively stacked AlAs layers 16A, which can capture the electrons therein, and GaAs layers 16B, which allow tunneling of the electrons therethrough. In the above heterojunction multilayer superlattice structure, the bond of adjacent quantum wells may be increased, resulting in formation of a mini-energy band 6. Formation of the mini-energy band 6 will be explained in brief referring to Fig. 8. When only one quantum well exists in the superlattice as mentioned above or when quantum wells separate, each sub-band (SB11 to SB31) quantum level is degenerated. In the above periodical structure, the thickness of the AlAs layers 16A2 and 16A3 between the GaAs layers 16B1, 16B2, and 16B3 formed with quantum wells QW1 to QW3 therein is extremely thin, and the decrease of electron waves in the AlAs layers is not sufficient. As a result, there is an increase of the bond of the quantum levels between adjacent GaAs layers. Consequently, the degenerated quantum levels in each sub-band are separated into a plurality of quantum levels forming the mini-energy band 6. As a result, the electrons may be propagated through the mini-energy band 6, which has an energy band width greater than that of the sub-band. The function of the mini-energy band 6 is similar to that of the sub-band 91. However, the mini-energy band 6 enables an increase in the electrons passing through the superlattice 16' rather than the sub-band. Other layers 13, 14, 15, and 18 are identical to those in Figs. 4, 5, and 6. According to the HET device shown in Fig. 7, at a temperature 77°K, a current amplification factor α of 0.75 is obtained when the base layer is grounded and of 3 when the emitter is grounded. Referring to Figs. 9 and 10, another embodiment of an HET device will be explained. In Fig. 9, the NET device further includes a non-doped impurity Al x Ga 1-x As graded layer 17, the suffix x designating the composition rate, provided between the emitter layer 18 and the superlattice 16 in addition to the HET device shown in Fig. 5. The parameters of the graded layer 17 are as follows: Thickness : 100 Å (10 nm) Composition rate x: 0.3 to 0.1 By provision of the graded layer 17 between the emitter layer 18 and the superlattice 16, the Conduction energy bands of the Pseudo-Fermi level E FE at the emitte layer 18 and the sub-band 91 in the superlattice 16 are joined with a gradient. As a result, the electrons in the emitter layer 18 may easily and surely reach an injection level IL of the superlattice 16, which is equal to the sub-band, along the graded energy level. Figure 11 is a sectional view of a further embodiment of an HET device in accordance with the present invention. Figure 12 is a conduction-energy-band diagram of the HET device shown in Fig. 11. The concept of provision of the graded layer 17 shown in Fig. 9 may be applied to the HET device including the superlattice 16' having the periodical structure as shown in Fig. 7. The HET device shown in Fig. 11 features an improved current amplification factor. An embodiment of a resonant tunneling type HET device will be explained referring to Figs. 13 to 19. Figure 13 shows a conduction-energy-band diagram of the resonant tunneling HET device. In Fig. 13, there is shown a superlattice 19 consisting of non impurity-doped AlAs layers 19A1 and 19A2 and a non impurity-doped GaAs layer 19B formed similarly to layers 16A1, 16A2, and 16B in Figs. 4 and 5. This corresponds to the superlattice 16 in Figs. 4 and 5. Figures 14a to 14c Show schematically how resonance occurs with an applied DC bias. The electrons originate near the Fermi-level E F to the left side of the first barrier of height ΔE, tunnel into the quantum well, and finally tunnel through the second barrier into unoccupied states. Resonance occurs when the electron wave function reflected at the first barrier is cancelled by the wave which is reflected from the second barrier or, equivalently, when the energy of the injected carrier becomes approximately equal to the energy level of the electrons confined in the quantum well. Figure 15 is a graph showing current-voltage curves for the resonant tunneling structure shown in Figs. 14a to 14c. With the above resonant tunneling phenomenon, a negative resistance having an "n" shape can be observed at a first quadrant of the graph in Fig. 15. Figure 16 is a circuit diagram showing an application of the resonant tunneling HET device shown in Fig. 13. In Fig. 16, the resonant tunneling HET device 30 has an emitter E which is grounded and a collector C connected to a resistor 31. By applying a suitable level of voltage V CE to the collector C through the resistor 31, with increasing the voltage V BE between a base B and the emitter E, i.e., an input voltage V IN , first, the collector current I C is increased up to a predetermined value defined by the voltage V CE . After passing a peak in the "n" shape resistance curve shown in Fig. 15, it is reduced. Figure 17 shows this characteristic of the circuit in Fig. 16. Accordingly, as shown in Fig. 18, when the input voltage V IN is changed from low-level to high-level, an output voltage V OUT at the collector C is changed to high-level V H , low-level V L , and again high-level V H . Then, when a pulse signal having predetermined gradients (slopes) over time, as shown in Fig. 19a, is applied as the input voltage V IN between the base B and the ground, two inverted pulses of output signal may be obtained, as shown in Fig. 19b. This means that the resonant tunneling HET device acts as a frequency multiplier. The high-speed nature of the HET device is naturally maintained. When the periodical structure of the SL is increased as shown in Fig. 7, a plurality of quantum wells are formed therein, resulting in a plurality of resonance points as shown in figures 20a, 20b and 21. Accordingly, the resonant tunneling HET device having an n-periodical structure superlattice may act as a 2 n -frequency multiplier. The HET device may be formed with any combination of the following materials : A. Emitter layer 18 : GaAs, In x Ga 1-x As (0 ≦ x ≦ 1) (In x As 1-x )m(GaAs)n (1 ≦ m 3, 1 ≦ n 3) B. Superlattice 16 : B1 : barrier layer 16A (Al x Ga 1-x )As, InP, (In x Al 1-x )As, insulator (e.g. Al₂O₃) B2 : QW layer 16B GaAs, (In x Ga 1-x )As C. Base layer 15 GaAs, (In x Ga 1-x )As, (In x As 1-x )m(GaAs)n, metal (e.g. Al) D. Potential barrier layer 14 (Al x Ga 1-x )As, InP, (In x Al 1-x )As E. Collector layer 13 GaAs, (In x Ga 1-x )As, (InAs)m(GaAs)n. Further more, in the present invention, the base layer 15 can be a metal layer e.g. aluminium. All the barrier layers 16A need not be the same material, that is, the same barrier height. Any one of or all of the barrier layers 16A can be an insulating layer, e.g., Al₂O₃. The potential barrier can be formed by a Schottky barrier, which comprises a Schottky junction between a metal base layer A1 and a semiconductor collector layer GaAs. The base layer 15 can be a p-type doped layer. The barrier layer 16A, quantum well layer 16B for the superlattice 16 does not have to be a non-doped semiconductor layer, but may be an n-or p-type doped semiconductor layer. As the metal base type, preferably, the emitter, quantum well, and collector layers are GaAs, the barrier layers 16A are Al₂O₃ , the base layer 15 is A1, and the potential barrier layer 14 is the Schottky junction.

Claims: A high-speed semiconductor device, comprising an emitter layer (18) having a conduction band with a first energy level, a base layer (15) formed under said emitter layer and having a conduction band with a second energy level, a collector layer (13) formed under said base layer, a collector side potential-barrier means disposed between said base layer and said collector semiconductor layer and a superlattice construction (16) through which carriers can tunnel, provided between said emitter layer and base layer, characterized in that said superlattice construction comprises : a first potential barrier layer (81) forming a heterojunction with said emitter layer and having a conduction band with a third energy level, said third energy level being higher than said first energy level so that the conduction band of said emitter layer and the conduction band of said first potential barrier layer have a discontinuity therebetween; a quantum well layer (7) forming a heterojunction with said first potential barrier layer and having a conduction band with a fourth energy level, said fourth energy level being lower than said third energy level; and a second potential barrier layer (82) forming a heterojunction with said quantum well layer and said base layer and having a conduction band with a fifth energy level, said fifth energy level being higher than said fourth and second energy levels; said first and second barrier layers being sufficiently thin for tunneling carriers therethrough, and said quantum well layer being sufficiently thin so as to have a sub-band (SB11, ..., SB31) therein. A high-speed semiconductor device according to claim 1, characterized in that said superlattice means (16) includes at least one set of quantum-well forming layer means having thin potential barrier layers (16A1 and 16A2) and a thin quantum-well layer (16B) therebetween, which layers are formed with a heterojunction structure and define said quantum well and a low impedance state for tunneling carriers therethrough. A high-speed semiconductor device according to claim 2, characterized in that thicknesses of said thin potential barrier layers (16A1 and 16A2) and said thin layer (16B) are approximately 3 to 5nm (30 to 50 Å). A high-speed semiconductor device according to claim 2, characterized in that said superlattice means (16) includes a plurality of sets of said quantum-well forming layer means which are stack-formed with a periodical structure and have at least one conduction mini-energy band for tunneling said carriers therethrough. A high-speed semiconductor device according to claim 2, characterized in that said high-speed semiconductor device is formed with any combination of the following materials : (a) said emitter layer (18) GaAs, In x Ga 1-x As (0 ≦ x ≦ 1), (In x As 1-x )m(GaAs)n (1 ≦ m 3, 1 ≦ n 3) (b) said superlattice means (16, 16') (b1) barrier layer (16A) (Al x Ga 1-x )As, InP, (In x Al 1-x )As, Al₂O₃ (b2) quantum well layer (16B) GaAs, (In x Ga 1-x )As (c) said base layer (15) GaAs, (In x Ga 1-x )As, (In x As 1-x )m(GaAs)n, Al (d) said potential barrier means (14) (Al x Ga 1-x )As, InP, (In x Al 1-x )As (e) said collector layer (13) GaAs, (In x Ga 1-x )As, (InAs) m (GaAs) n . A high-speed semiconductor device according to claim 1, further including a graded layer (17) disposed between said emitter layer (18) and said superlattice means (16) and having a conduction-energy level which is approximately equal to that of said emitter layer (18) at one end and is approximately equal to a predetermined conduction-energy level of said superlattice means (16) at another end, to enable tunneling of said carriers therethrough, said carriers in said emitter layer being transported along said graded conduction-energy level in said graded layer (17), tunneled through said superlattice means with said predetermined conduction-energy level, and injected into said base layer (15). A high-speed semiconductor device according to claim 6, characterized in that said graded layer is formed of non impurity-doped Al x Ga 1-x As (X : 0.3 to 0.1) having approximately 10nm (100 Å) thickness. A high-speed semiconductor device according to claim 1, characterized in that the number of sets of said quantum-well forming layer means in said superlattice means (16) is equal to "n", and in that it cooperates with means for applying a predetermined DC bias to result in a resonant tunneling phenomenon of said carriers at said superlattice means (16), whereby a signal is output having a 2 to the "n" power multiplied frequency when an input pulse signal having a predetermined voltage range and predetermined slopes is supplied to said base layer (15). A high-speed semiconductor device according to claim 1, characterized in that said base layer (15), said potential-barrier means (14), and said collector layer (13) are formed with a heterojunction structure. A high-speed semiconductor device according to claim 6, characterized in that said graded layer (17) is formed with a heterojunction structure.

Inventors: YOKOYAMA, NAOKI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H01L29
IPC codes: H01L29, H01L21