BIPOLAR-TRANSISTOR TYPE SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY CONFIGURATION

Abstract: A bipolar-transistor type semiconductor memory device includes a memory cell array (1), a redundancy memory cell array (10), a redundancy driving circuit (11), and a redundan­ cy address decision circuit (12,13). The redundancy driving circuit includes an emitter-coupled logic gate (Q20,Q21,R8,IS14) which compares the voltage level of an input signal with a reference voltage level to produce an enabling signal for the redundancy memory cell array. When the redundancy address decision circuit judges that the input address coincides with the address of a defective circuit portion of the memory device, the redundancy driving circuit operates to enable the redundancy memory cell array instead of the normal memory cell array.

Description: This invention relates to a semiconductor memory device, and in particular to a bipolar-transistor type semiconductor memory device having a redundancy circuit portion for replacing a defective circuit portion, such as a defective memory cell. In a random-access memory (RAM) device, a large number of memory cells are arranged along rows and columns. The density of defects generated in such a semiconductor memory device during the manufacture thereof is relatively independent of the integration density of the device. Rather, it derives from the semiconductor manufacturing technology. In general, the higher the integration density of the device, the greater the ratio of normal memory cells to defective memory cells. This is one of the advantages of increasing the integration density of a semiconductor memory device. Even if a device includes only one defective memory cell, however, the device cannot be operated normally and, therefore, must be scrapped. As a result, despite the lower ratio of defective memory cells, greater integration density means reduced manufacturing yield. In a metal-insulator-semiconductor (MIS) type RAM, in order to overcome the problem of defective memory cells, use is made of redundancy memory cells. When a defective memory cell is detected, a redundancy memory cell row or column is selected instead of the memory cell row or column including the defective memory cell. In general, one or two redundancy memory cell rows or columns are usually provided. EP-A-0087610 describes a bipolar redundancy arrangement with redundant and non redundant memory portions wherein the redundant memory portion is switched onto the circuit in response to a bad bit address occuring at the input of the compare circuit. With improvements in integration technology for bipolar-transistor type RAMs and the requirement for larger numbers of memory cells, however, bipolar-transistor type RAM devices having a large number of memory cells have come into demand. Accordingly, bipolar-transistor type RAMs having a redundancy configuration have come into demand. Accordingly, it is an object of the present invention to provide a bipolar-transistor type semiconductor memory device wherein a defective circuit portion can be replaced by a redundancy circuit portion by a simple circuit structure, thus improving the yield of the production of the memory device. According to the invention there is provided a bipolar-transistor type semiconductor memory device having a redundancy configuration, including a memory cell array; a redundancy memory cell array; a driving circuit a redundancy driving circuit and a redundancy address decision circuit for deciding whether an input address coincides with an address of a defective circuit portion and for outputting a switching signal in accordance with results of the decision, the switching signal being applied to the input of the redundancy driving circuit characterised in that the driving circuit includes an emitter-coupled logic gate for comparing a voltage level of an input signal with a voltage level of a reference signal to enable the memory cell array; in that the redundancy driving circuit includes an emitter-coupled logic gate for comparing a voltage level of an input signal with a voltage level of a reference signal to enable the redundancy memory cell array; and in that the switching signal is applied to the emitter-coupled logic gate of the redundancy driving circuit and to the reference signal input of the emitter-coupled logic gate of the driving circuit. In one example of the invention the device includes a decoding circuit for decoding an input address; and a redundancy selection circuit for placing all output signals of the decoding circuit in the non-selection state while driving the redundancy driving circuit to enable the redundancy memory cell array instead of the defective circuit portion on the basis of the switching signal output from the redundancy address decision circuit. In the device according to the invention, when the redundancy address decision circuit decides the input address coincides with the address of the defective circuit portion, the driving circuit is inhibited and the redundancy driving circuit is driven to enable the memory cell of the redundancy memory cell array. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which Fig. 1 is a partial block diagram of one example of a bipolar-transistor type semiconductor memory device according to the invention; Fig. 2 is a more detailed circuit diagram of the memory device of Fig. 1; Fig. 3 shows voltage levels of the signals of portions in the device of Fig. 2; Fig. 4 is a partial block diagram of another example of a memory device according to the invention; and Fig. 5 is a more detailed circuit diagram of the memory device of Fig. 4. Figure 1 illustrates a semiconductor memory device according to the invention. This semiconductor memory device is able to replace a defective circuit portion with a redundancy circuit portion in word line units. In Fig. 1, the semiconductor memory device includes a memory cell array, a word driver 2, an address buffer 4 for a word address, a decoder line 5, a redundancy memory cell array 10 connected to a redundancy word line, a redundancy word driver 11, a programmable read-only memory (PROM) 12 for storing an address of the redundancy circuit portion, and a comparison gate circuit 13 for comparing the input word address ADD with the data read out from the PROM 12. In Fig. 2, the address buffer for the bit address, the bit driver, the input-output circuit, etc. are omitted, for simplification of the drawing. In the memory device of Fig. 1, read and write operations are effected by applying a word address ADD and a bit address to the word address buffer 4 and bit address buffer (not shown), respectively. At this time, the word address ADD is fed into the comparison gate circuit 13 to be compared with the address data, such as a defective word output from the PROM 12 corresponding to the defective circuit portion. This address data of the defective circuit portion is written into the PROM 12, for example, when the defective circuit portion is found during testing of the goods. Such a PROM suitable for this purpose is disclosed, for example, in Japanese Patent Application 59-218707. If the comparison shows the two addresses do not coincide, no redundancy circuit selection signal (referred to as selection signal hereafter) SR is output. As a result, the memory cell array 1 is accessed and the read and write operations of the data are effected. On the contrary, if the input word address ADD coincides with the defective word address from the PROM 12, the selection signal SR is output from the comparison gate circuit 13 to each word driver 2 and the redundancy word driver 11. The word driver 2 is inhibited due to the application of the selection signal SR, so that the word line selection signal is cut off. On the other hand, the redundancy word driver 11 outputs the word line selection signal to the redundancy memory cell array 10 due to the application of the selection signal SR. The redundancy memory cell array 10 is thereby selected, so that the read and write operations of the data for the redundancy memory cell array 10 are carried out. Figure 2 shows the circuit constitution of the memory device of Fig. 1 in more detail. In Fig. 2, the device includes the memory cell array 1, the word driver 2, the word decoder 3, the address buffer 4 for the word address, the redundancy memory cell array 10, the redundancy word driver 11, the comparison gate circuit 13, etc. The memory cell array 1 includes a plurality of memory cells MC connected between a high voltage word line WL+ and a low voltage word line WL- and between bit lines BL and BL . The word driver 2 includes a plurality of word driver units 2₁ to 2 n each corresponding to a word line in the memory cell array 1. Each word driver unit is constituted in the same manner. For example, the word driver unit 2₁ includes two transistors Q1 and Q2, whose emitters are commonly connected,a constant current circuit IS1 connected between the commonly-connected emitters of these transistors and the low voltage power supply V ee , a load resistor R1 connected between the collector of the transistor Q1 and the high voltage power supply V cc , and a driver transistor Q3 whose base is connected to the collector of the transistor Q1. The transistors Q1 and Q2, the resistor R1, and the constant current circuit IS1 constitute an emitter-coupled logic (ECL) gate. The address buffer 4 includes a plurality of the address buffer units 4₁ to 4 m provided for every bit of the input word address ADD. As the typical constitution, the address buffer unit 4₁ includes two transistors Q7 and Q8, whose emitters are commonly connected, a constant current circuit IS3, two load resistors R3 and R4, a transistor Q9 and constant current circuit IS4 constituting an input emitter follower circuit, and a transistor Q10 and a constant current circuit IS5 constituting an emitter follower circuit to which the reference voltage VRF2 is applied. Further, the word decoder 3 includes two multiemitter transistors Q11 and Q12, which receive the output signal from the address buffer unit 4₁ , a decoder line 5 including a plurality of signal lines, to which each emitter of the multiemitter transistors are connected, and four constant current circuits IS6, IS7, IS8 and IS9, connected between each signal line of the decoder line 5 and the low voltage power supply V ee , respectively. The address buffer units, such as 4₁ , are provided for every bit of the word address. The outputs are suitably connected to each signal line of the decoder line 5 via two multiemitter transistors, respectively. Further, signal lines of the decoder line 5 are connected to the input terminals of the word driver units 2₁ to 2 n , respectively. The redundancy memory cell array 10 has a plurality of memory cells connected between a high voltage redundancy word line WL(R)+ and a low voltage redundancy word line WL(R)- and between a pair of bit lines BL and BL common to the memory cell array 1. The redundancy word driver 11 has the same constitution as the word driver units of the word driver 2 and includes transistors Q20, Q21, and Q22, a resistor R8, and a constant current circuit IS14. A reference voltage VRF5 is applied to the base of the transistor Q21. The comparison gate circuit 13 includes a plurality of comparison gate units 13₁ to 13 m provided for every bit of the word address ADD. As a typical constitution, the comparison gate unit 13₁ includes transistors Q13 to Q19, constant current circuits IS10 to IS13, a diode D1, and resistors R5, R6, and R7. The transistor Q13, the diode D1, and the constant current circuit IS10 constitute an input emitter follower circuit. The commonly-connected emitters of the transistors Q14 and Q15 are connected to the low voltage power supply V ee via the constant current circuit IS11. The commonly-connected emitters of the transistors Q16 and Q17 are also connected to the low voltage power supply V ee via the constant current circuit IS12. Further, the reference voltages VRF3 and VRF4 are applied to the bases of the transistors Q15 and Q16 respectively, and the output signal of the PROM, corresponding to one bit of the defective address, is applied to the base of the transistor Q17. The collectors of the transistors Q14 and Q16 are together connected to the base of the transistor Q19. Also, the collectors of the transistors Q15 and Q17 are together connected to the base of the transistor Q18. The transistors Q18 and Q19 and the constant current circuit IS13 constitute a logical add (OR) circuit. The output signals of the comparison gate units 13₁ and 13 m , i.e., the selection signal SR, are input to the reference voltage terminals of the word driver units 2₁ to 2 n of the word driver 2, i.e., the bases of the transistors Q2, Q5, etc., and the input terminal of the redundancy word driver 11, i.e., the base of the transistor Q20. The mode of operation of the above-described embodiment will now be described. First, the read and write operations in the normal state will be described. In this case, the word address ADD is applied to the word address buffer 4, while the bit address is applied to the bit address buffer (not shown). Each of the address buffer units 4₁ to 4 m outputs a high level or low level signal to a signal line of the decoder line 5 via the multiemitter transistors Q11 and Q12, etc., in accordance with the level of each bit of the word address ADD. The signal lines of the decoder line 5 are connected to the plural number of multiemitter transistors. If one or more of the output signals of the multiemitter transistors is high level, the voltage level of the signal line becomes high level. When, for example, the signal line connected to the base of the input transistor Q1 of the word driver unit 2₁ becomes low level, the word driver unit 2₁ outputs a high level word line selection signal to the high voltage word line WL+, whereby the word line is selected. Further, a pair of bit lines BL and BL are selected by the bit decoder, etc, (not shown). Thus, the read and write operations of data for the memory cell MC connected to the word line and a pair of the bit lines selected as described above are carried out. The mode of operation of the redundancy circuit portion will now be described. The comparison gate unit 13₁ constitutes an exclusive-OR circuit. Therefore, if the word address signal ADD input to the unit 13₁ and the defective address signal from the PROM are both high level or both low level, the unit 13₁ outputs a low level selection signal SR. On the other hand, if one of them is high level while the other is low level, the unit 13₁ outputs a high level selection signal SR. In more detail, when the word address signal ADD is high level, the transistor Q14 becomes ON while the transistor Q15 becomes OFF, whereby the base voltage of the output transistor Q19 becomes low level. At this time, if the defective word address signal output from the PROM to the base of the transistor Q17 is high level, the transistor Q17 becomes ON while the transistor Q16 becomes OFF, whereby the base voltage of the output transistor Q18 becomes low level. As a result, the selection signal SR becomes low level. When the word address signal ADD is high level and the defective word address signal is low level, the transistor Q17 becomes OFF and the transistor Q16 becomes ON, whereby the base voltage of the output transistor Q19 becomes low level and the base voltage of the output transistor Q18 becomes high level. Accordingly, the selection signal SR becomes high level. When the word address signal ADD is low level, the transistor Q14 becomes OFF and the transistor Q15 ON, whereby the base voltage of the output transistor Q18 becomes low level. At this time, if the defective word address signal is low level, the transistor Q17 becomes OFF and the transistor Q16 becomes ON, whereby the base voltage of the output transistor Q19 becomes low level so that the selection signal SR becomes low level. When the word address signal is low level and the defective word address signal is high level, the base voltage of the output transistor Q18 becomes low level while the base voltage of the output transistor Q19 becomes high level, whereby the selection signal SR becomes high level. As described above, the comparison gate unit 13₁ executes an exclusive logical add operation on the word address signal ADD and the defective word address signal from the PROM. Figure 3 shows the relationship between the signal level of the selection signal SR output from the comparison gate circuit 13 and the signal level of the input signal to the word driver. In Fig. 3, H1 and L1 indicate high and low logical levels of the input signal to the word driver 2, respectively. H2 and L2 indicate high and low levels of the selection signal SR, respectively. As clear from Fig. 4, the high and low levels H2 and L2 of the selection signal SR are shifted toward the low voltage side in comparison with the high and low levels H1 and L1 of the input signal. That is, the high level H2 of the selection signal SR is between the high and low levels H1 and L1 of the input signal, and the low level L2 is under the low level L1. Further, the reference voltage VRF5 applied to the base of the transistor Q21 is between the high voltage level H2 and the low voltage level L2 of the selection signal SR. In the circuit of Fig. 2, when the word address ADD does not coincide with a defective word address, accordingly, when the selection signal SR is high level H2, the output signal of the redundancy word driver 11 becomes low level, whereby the high voltage redundancy word line WL(R)+ of the redundancy memory cell array 10 becomes low level and the redundancy memory cell array 10 enter a non-selection state. In this case, the selection signal SR is utilized as the reference voltage of each word driver unit of the word driver 2, and the read and write operations of the data described before are carried out. On the other hand, when the word address ADD coincides with the defective word address from the PROM, all output signals of the comparison gate unit 13₁ to 13 m , corresponding to bits of the word address, become entirely low level, whereby the selection signal SR becomes low level. In this case, the low voltage level L2 of the selection signal SR becomes lower than the low voltage level L1 of the logical signal input to each word driver unit of the word driver 2, as described before. Accordingly, when the word address ADD indicates a defective circuit portion, the selection signal SR becomes the lowest voltage level L2, whereby the transistor Q2 and Q5, etc., of each word driver unit become OFF while the transistors Q1 and Q4, etc. become ON, so the voltages of all high voltage word lines WL+ become low level, i.e., the non-selection level. At this time, in the redundancy word driver 11, the transistor Q20 becomes OFF while the transistor Q21 becomes ON, whereby the redundancy word line WL(R)+ becomes high level and the redundancy memory cell array 10 is selected. In such a manner, the redundancy memory cell array 10 is accessed in place of the defective word address portion of the memory cell array 10. In addition, when the word address ADD does not coincide with the defective word address stored in the PROM, the selection signal SR becomes high level H2, as described before, whereby the output signal of the redundancy word driver 11 becomes low level and the redundancy memory cell array 10 enters the non-selection state. Figure 4 illustrates a further semiconductor memory device according to the present invention. The memory device of Fig. 4, in the same manner as that of Fig. 2, replaces a defective circuit portion with a redundancy circuit portion in word line units. The memory device includes a memory cell array 1, word driver 2, address buffer 4 for word address, decoder line 5, redundancy memory cell array 10 connected to the redundancy word line, redundancy word driver 11, PROM 12 for storing an address of the redundancy circuit portion, and comparison gate circuit 14 for comparing an input word address ADD with read-out data from the PROM 12. In Fig. 5, the address buffer for the bit address, bit driver, input-output circuit, etc. are not shown for simplification. In the memory device of Fig. 4, when the input word address ADD does not coincide with a defective word address from the PROM 12, the same read and write operations as those of the Fig. 2 device are performed. That is, the memory cell array 1 is accessed by the word driver 2 so that the read and write operations of the data are carried out. On the other hand, when the input word address ADD coincides with a defective word address from the PROM 12, the selection signal SR is output from the comparison gate circuit 14. Then, due to this selection signal SR, all signal lines of the decoder line 5 enter the non-selection state, whereby the word line selection signal to be applied to the memory cell array 1 is cut off. On the other hand, the redundancy word driver 11 outputs the word line selection signal to the redundancy memory cell array 10 due to the application of the selection signal SR. As a result, the redundancy memory cell array 10 is selected and the read and write operations for the redundancy memory cell array 10 are carried out. Figure 5 shows the circuit constitution of the memory device of Fig. 4 in more detail. In Fig. 5, elements the same as in Fig. 2 bear the same reference numerals. The differences are, first, in the comparison gate unit 14₁ , the collector of the transistor Q14 is connected to the base of the transistor Q18, and the collector of the transistor Q15 is connected to the base of the transistor Q19. Due to this constitution, the comparison gate unit 14₁ operates as an exclusive NOR circuit. Further, a plurality of diodes D2 to Dn and a resistor R10, for constituting an AND gate, and a multiemitter transistor Q23 are added. The diodes D2 to Dn are connected to the comparison gate units 14₁ to 14 m provided by each bit of the word address ADD, respectively. The emitters of the multiemitter transistor Q23 are connected to the signal lines of the decoder line 5 and the input terminal of the redundancy word driver 11, i.e., the base of the transistor Q20. The output signal from the comparison gate units 14₁ to 14 m are applied to the base of the multiemitter transistor Q23 via the diodes D2 to Dn, respectively. The reference voltage VRF1 is applied, respectively, to each reference signal input terminal of the ECL gate of the word driver 2 (i.e., the base of the transistors Q2, Q5, etc.) and the reference signal input terminal of the redundancy word driver 11 (i.e., the base of the transistor Q21). The mode of operation of the semiconductor memory device described above will now be described. The comparison gate unit 14₁ constitutes an exclusive-NOR circuit. Therefore, when the input word address signal ADD and the redundancy address signal from the PROM are both high level or both low level, the unit 14₁ outputs a high level output signal. On the other hand, when one of them is high level and the other low level, the unit 14₁ outputs a low level output signal. In more detail, when the word address signal ADD is high level, the transistor Q14 becomes ON while the transistor Q15 becomes OFF, whereby the base voltage of the output transistor Q18 becomes low level. At this time, if the defective word address signal output from the PROM to the base of the transistor Q17 is high level, the transistor Q17 becomes ON while the transistor Q16 becomes OFF, whereby the base voltage of the output transistor Q19 becomes high level. As a result, the output signal becomes high level. When the word address signal ADD is high level and the defective word address signal is low level, the transistor Q17 becomes OFF and the transistor Q16 becomes ON, whereby the base voltage of the output transistor Q19 becomes low level and the base voltage of the output transistor Q18 becomes low level as described above. Accordingly, the output signal becomes low level. When the word address signal ADD is low level, the transistor Q14 becomes OFF and the transistor Q15 ON, whereby the base voltage of the output transistor Q19 becomes low level. At this time, if the defective word address signal is low level, the transistor Q17 becomes OFF while the transistor Q16 becomes ON, whereby the base voltage of the output transistor Q18 becomes high level so that the output signal becomes high level. When the word address signal is low level and the defective word address signal is high level, the base voltage of the output transistor Q18 becomes low level while the base voltage of the output transistor Q19 becomes low level, whereby the output signal becomes low level. As described above, the comparison gate unit 14₁ executes an exclusive-NOR operation on the word address signal ADD and the defective word address signal from the PROM. All output signals of the comparison gate units 14₁ to 14 m are subjected to an AND operation by the AND circuit constituted by the diodes D2 to Dn and the resistor R10. The AND circuit outputs the selection signal SR to the multiemitter transistor. In the circuit of Fig. 5, when the word address ADD does not coincide with a defective word address, accordingly, when the selection signal SR is low level, the output signal of the redundancy word driver 11 becomes low level, whereby the high voltage redundancy word line WL(R)+ of the redundancy memory cell array 10 becomes low level and the redundancy memory cell array 10 enters the non-selection state. In this case, the normal read and write operations of data are carried out. On the contrary, when the word address ADD coincides with a defective word address from the PROM, all output signals of the comparison gate units 14₁ to 14 m , corresponding to bits of the word address, become entirely high level, whereby the selection signal SR becomes high level. Accordingly, all signal lines of the decoder line 5 are made a high voltage level by the multiemitter transistor Q23, whereby all high voltage word lines WL+ of the memory cell array 1 become low voltage level, i.e., the non-selection voltage level. Simultaneously, in the redundancy word driver 11, the transistor Q20 becomes ON while the transistor Q21 becomes OFF, whereby the redundancy word line WL(R)+ becomes high level and the redundancy memory cell array 10 is selected. In such a manner, the redundancy memory cell array 10 is accessed in place of the defective word address circuit portion. Although preferred embodiments have been described heretofore, various modifications and alterations are possible within the scope of the present invention. For example, although the above-described embodiments relate to a redundancy circuit for word lines, it is obvious that the redundancy exchange is also possible for bit lines. Furthermore, the number of redundancy memory cell arrays is not limited to one. For two redundancy addresses, the memory device may be provided with two sets of redundancy circuits, i.e., two redundancy memory cell arrays, redundancy word drivers, PROM's, comparison gate circuits, etc. Furthermore, in Fig. 5, it is possible to constitute the word driver by a diode matrix in place of the ECL gate.

Claims: A bipolar-transistor type semiconductor memory device having a redundancy configuration, including a memory cell array (1); a redundancy memory cell array (10); a driving circuit (2) a redundancy driving circuit (11) and a redundancy address decision circuit (12,13) for deciding whether an input address coincides with an address of a defective circuit portion and for outputting a switching signal (SR) in accordance with results of the decision, the switching signal being applied to the input of the redundancy driving circuit characterized in that the driving circuit (2) includes an emitter-coupled logic gate (Q1,Q2,R1,IS1) for comparing a voltage level of an input signal with a voltage level of a reference signal to enable the memory cell array; in that the redundancy driving circuit (11) includes an emitter-coupled logic gate (Q20,Q21,R8,IS14) for comparing a voltage level of an input signal with a voltage level of a reference signal to enable the redundancy memory cell array; and in that the switching signal is applied to the emitter-coupled logic gate of the redundancy driving circuit and to the reference signal input of the emitter-coupled logic gate of the driving circuit. A device according to claim 1, characterised in that the high and low voltage levels of the switching signal from the redundancy address decision circuit (12,13) are shifted in comparison with the high and low voltage levels of the input signal of the driving circuit (2), and the voltage level of the reference signal of the redundancy driving circuit (11) is between the high and low voltage levels of the switching signal. A device according to claim 2, characterised in that the high voltage level of the switching signal (SR) from the redundancy address decision circuit (12,13) is between the high and low levels of the input signal of the driving circuit (2), and the low voltage level of the switching signal is lower than the low voltage level of the input signal of the driving circuit. A device according to any preceding claim characterized by a decoding circuit (3) for decoding an input address; and a redundancy selection circuit (Q23) for placing all output signals of the decoding circuit in the non-selection state while driving the redundancy driving circuit to enable the redundancy memory cell array instead of the defective circuit portion on the basis of the switching signal output from the redundancy address decision circuit. A device according to claim 4, characterised in that the decoding circuit (3) comprises an address buffer circuit (4) and decoder lines (5) to which the output lines of the address buffer circuit are suitably connected. A device according to claim 4 or claim 5, characterised in that the redundancy selection circuit comprises a multiemitter transistor (Q23) driven by the switching signal (SR) from the redundancy address decision circuit (12,14), the emitters of the multiemitter transistor being connected to the decoder lines (5) and the input of the redundancy driving circuit (11), respectively. A device according to any preceding claim, characterized in that the redundancy address decision circuit comprises a memory circuit (12) for storing the address of the defective circuit portion, and a comparison gate (13, 14) for comparing the input address with the content of the memory circuit to decide the coincidence. A device according to claim 7, characterized in that the comparison gate (14) is an exclusive-NOR circuit. A device according to claim 7, characterised in that the comparison gate (13) is an exclusive-OR circuit. A device according to any one of claims 7 to claim 9, characterised in that the memory circuit (12) is a programmable read-only memory. A device according to any preceding claim, characterised in that the driving circuit (2) and the redundancy driving circuit (11) comprise emitter-coupled logic gates (Q1,Q2; Q4,Q5; Q20,Q21) and a driving transistor (Q3,Q6,Q22) driven by the emitter-coupled logic gate to enable the memory cell. A device according to any preceding claim, characterised in that the driving circuit (2) and the redundancy driving circuit (11) are constituted by diode matrices.

Inventors: AWAYA, TOMOHARU, FUKUSHI, ISAO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F11
IPC codes: G11C29