PROCESS FOR FORMING ISOLATION REGIONS IN A SEMICONDUCTOR SUBSTRATE

Abstract: In a process for forming dielectric isolation regions in a semiconductor substrate (10), trenches (13) are formed in the substrate (10), whereafter there are formed in turn a stress relief oxide layer (16), an etch-stop polysilicon layer (17), a nitride layer (18) and an isolation oxide layer (19) formed of doped silicon dioxide. The structure is heated to reflow the isolation oxide layer (19) thereby collapsing any voids (21) therein and planarizing the surface. The structure is then etched back to the polysilicon layer (17) outside the trenches (13) and the structure is heated to remove dopant from a surface adjacent region of the isolation oxide layer (19) remaining in the trenches (13).

Description: PROCESS FOR FORMING ISOLATION REGIONS IN A SEMICONDUCTOR SUBSTRATE Technical Field This invention relates to processes of the kind for forming dielectric isolation regions in a semiconductor substrate, including the steps of: forming trenches in a surface of said semiconductor substrate; forming an insulator layer over said surface, including the interior surfaces of said trenches, forming a layer of reflowable dielectric material over said insulator layer within and outside said trenches; and heating said reflowable dielectric material. The invention also relates to semiconductor substrates of the kind of provided with dielectric insulation regions in the form of trenches having interior surfaces including substantially vertical sidewalls and containing silicon dioxide dielectric material. Background Art Processes for forming dielectric isolation regions by etching trenches or grooves in a semiconductor substrate and filling the trenches with dielectric material are known. For example, an article by Rung et al. IEEE International Electron Devices Meeting (IEDM) , 1982, page 237-240 discloses a trench isolation process which involves oxidizing the silicon substrate trench sidewalls, filling the trench with polysilicone or deposited oxide, etching the poly/oxide, then capping the structure with oxide. It will be appreciated that trench isolation technology has the inherent potential advantages of small width-to-depth ratios, relative process simplicity, well-defined vertical-wall isolation regions and surface planarity. Like other VLSI features, however, the width of isolation trenches must be scaled downward to near micron and even submicron size to achieve the densities required in VLSI and future monolithic integrated circuit technologies. Unfortunately, it becomes increasingly difficult to completely fill the narrow, yet relatively deep trench configurations which are used for VLSI isolation. The resulting tendency to form voids is known and is shown, for example, in U.S. Patent No. 4,104,086, which discloses a process for eliminating voids by precisely tapering the walls of the trenches, which tapers vary in relation to the sizes of the trenches. Figure 1 of the present application illustrates the data of the U.S. Patent, and shows that for vertical sidewall trenches, the deposited silicon dioxide forms negative sloping sidewalls and, thus, voids. U.S. Patent No. 4,104.086 uses tapered trench sideswalls to control the depth of isolation oxide voids relative to the substrate surface in a silicon substrate which has a highly doped near-surface region. Briefly, the process involves (1) forming the trench to a tapered profile, as by the use of reactive ion etching (RIE); (2) growing a thin layer of thermal oxide in the trench outline; (3) depositing CVD oxide; (4) etching back the CVD oxide using RIE; and (5) optionally, annealing in steam at 900° to 950°C to enhance the "quality" of the silicon dioxide. The data disclosed in the U.S. patent indicate the vertical walls (which, of course, are desirable for density and resolution) inherently produce voids in the deposited silicon oxide (see Figure 1 herein) . Also, the voids are buried deeper in the oxide relative to the substrate surface as the trench width increases and the taper increases. Conversely, the voids are formed closer to the surface and to exposure by the planarization etch-back in the case of narrower, vertical grooves. A process of the kind specified hereinabove is known from U.S. -Patent No. 4,404,735, which discloses a process for forming trench isolation structures. Initially, dry etching such as plasma etching, reactive sputter etching or ion beam etching is used to form a trench. The trench is then covered with a thin layer of deposited silicon dioxide which is formed to a thickness of between 500 to 1,000 Angstroms to prevent substrate heating by the subsequent laser reflow process, prevent doping of the substrate from the isolation layer, and to isolate the silicon isolation layer from the substrate. Next, a CVD layer is formed to a thickness which is less than the trench depth and less than one-half the trench width using silicon or doped glass (phosphosilicate glass, PSG) . The PSG/silicon is subsequently reflowed by laser heating. Essentially, the known process is a laser reflow process for filling narrow trenches from a thin silicon or PSG layer. In other words, the trench-filling layer is formed to an initial shallow thickness within the trench and laser heating is used to redistribute material from outside the trenches into the trenches. Apparently, the 500 to 1,000 Angstrom thickness of the blocking silicon dioxide layer is critical in that a minimum thickness is required to perform the heat-shielding and dopant- blocking functions, while presumably, a maximum thickness is necessary for consistency with the stated depth and width dimensions. Furthermore, the dopant- blocking function of the silicon dioxide layer has limited effectiveness at the relatively high temperatures which may be utilized in processing the substrate to form devices therein. Disclosure of the Invention According to one aspect of the present invention, there is provided a process of the kind specified, characterized in that said layer of insulator material includes an etch-stop layer and an oxidation and dopant blocking layer; in that said layer of reflowable dielectric material is a silicon dioxide layer doped to approximately 3 to 9 weight per cent with n-type or p-type impurities; and further characterized by the steps of: heating said substrate for a sufficient time to reflow said silicon dioxide layer thereby collapsing voids therein and providing an substantially smooth upper surface thereon; etching the reflowed silicon dioxide layer to remove the deposited silicon dioxide outside said trenches utilizing said etch-stop layer as an etch stop; heating the resulting structure to remove impurity dopant from a surface adjacent region of the remaining portion of said silicon dioxide layer; removing said blocking layer from regions outside said trenches; and removing said etch-stop layer from regions outside said trenches. According. to another aspect of the present invention, there is provided a simiconductor substrate of the kind specified, characterized in that a multi- layered structure is disposed between said silicon dioxide dielectric material and the interior surfaces of said trenches, said multi-layered structure including a polysilicon layer and a silicon nitride layer. In brief summary of a preferred embodiment of the invention, described hereinafter, a trench isolation technology utilizes the reflow characteristics of doped silica glass at elevated temperatures to compensate for the tendency to form voids in the trenches of varying dimensions which are required for small geometry, high-density, monolithic integrated circuits. The process thereby provides a high-quality, void-free planar trench isolation structure. The preliminary formation of a silicon nitride barrier layer prevents doping and oxidation of the underlying structure, particularly the semiconductor substrate; an underlying polysilicon layer provides an etch-stop during the oxide planarization etchback; and an underlying silicon oxide layer decreases stress in the four-layer composite trench structure. The process enables the use of vertical sidewalls in trench structures of various widths. These vertical sidewalls minimize the effective wafer area allocated to the trenches. In addition, the process results in a planar wafer surface suitable for use with high resolution photolithography. Foremost, these objectives are obtained through the use of conventional fabrication techniques, and without imposing elaborate trench shape or dimensional controls. Brief Description of the Drawings Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 illustrates prior art data which demonstrates that formation of a dielectric such as silicon dioxide in vertical sidewall trenches produces a negatively sloped dielectric walls. and voids; Figure 2 through 7 are cross-sectional representations of a preferred process for fabricating the void-free silicon dioxide composit trench isolation structures of the present invention; Figure 3A and 3B are cross-sectional representations of alternative composite structures which may be used in the structure and process of the present invention; and Figure 8 is an exemplary IC structure based upon the trench isolation process and structure of the present invention. Best Mode for Carrying Out the Invention Referring to Figure 2, there is shown a semiconductor substrate 10, typically of silicon. As an example, for NMOS integrated circuits the substrate would be p- silicon having a resistivity of 1 to 20 ohms - centimeter. A typical CMOS starting structure would be an n~ epitaxial layer on an n+ substrate. The substrate 10 can be masked using any of a number and combinations thereof, as well as by the exemplary photoresist mask which is shaped by exposure to ultra¬ violet radiation. In addition, mask compositions suitable for X-Ray or ion beam exposure can be used. Using photoresist, a layer thereof is formed on the substrate 10, then is composed and developed to produce the etch mask 11 which has openings 12 corresponding to the desired trench width. Note that the dimensions of the drawings herein are chosen for convenience of representation, are not to scale, and are subject to variation. Subsequently, the trench is etched to a typical depth of 1 to 6 microns, preferably using an anisotropic etch process to produce a trench 13 having vertical sidewalls 14-14. One preferred etch process is reactive ion etching using a fluorine etchant gas such as nitrogen triflouride (NF3) . in reactive ion etching, the mechanical component or ion bombardment component 15 dominates the chemical reaction component and provides the vertical sidewalls which are desirable in order to provide sufficient dielectric width for effective isolation without lateral encroachment into active device regions. Referring to Figure 3, after the trench etching, the mask 11 is removed such as by a plasma ashing process. Next, a stress relief oxide layer 16 is formed to a thickness of about 300 to 1,000 Angstroms by thermal oxidation in steam at 950° to 1,150°C, or by chemical vapor deposition (CVD). The oxide layer 16 provides stress relief between the sil icon substrate 10 and the overlying layer, in this instance a polycrystalline silicon etch-stop layer 17 which is formed to a thickness of about 1 , 000 to 3 ,000 Angstroms , for example, by the LPCVD technique (low pressure chemical vapor deposition) using silane in argon and hydrogen at 600 °-800 °C. The poly layer 17 prevents etching of the underlying structure, particularly the substrate, during the planarization process . The primary purpose of the oxide layer 16 is stress relief of the substrate 10 , to preserve the electrical integrity of the substrate . Referring still further to Figure 3 , the sil icon nitride barrier layer 18 is then formed to a thickness of 1 , 000 to 2 , 500 Angstroms on the polysilicon layer 17 , preferably by low pressure chemical vapor deposition using silane and amonia and a reaction temperature of about 800 °C. The sil icon nitride layer 18 provides a barrier to doping and oxidation of the underlying structure, particularly substrate 10 , during subsequent processing. Thereby, sil icon nitride layer 18 permits f ormation and reflow of the doped isolation oxide and subsequent outgassing of the dopant in the isolation oxide without affecting the substrate or polysilicon or the rest of the underlying structure. Next , ref erring to Figure 4 , the doped silicon dioxide glass l ayer 19 can be formed to a thickness of about 2 .5 microns containing 3-9 weight percent of n-type or p-type impurities such as phosphorus or boron thereby prov iding the requisite reflow characteristics , e. g. , using the low pressure chemical vapor deposition technique . Typically , the reactants silane and oxygen are used, with phospine as the n-type dopant, and a reaction temperature of about 500 °-800 °C. As shown in Figure 4, the resulting silicon dioxide layer 19 includes voids 21-21, which is typical when silocon dioxide or other dielectric layers are formed in deep trenches. The voids occur because the arrival angles of the depositing silicon dioxide at the bottom 22 and sidewalls 14-14 of the trench are small in comparison to the arrival angle at the top edges 23-23 of the trench. This produces relatively low deposition growth rates at the bottom and sides in comparison to the top and edge. The deposition rate differential produces the negatively sloped sidewalls which are evidenced by the data of Figure 1, with the result that the fast growing oxide in the edge regions 23-23 closes up the opening of the trench before the bottom regions are filled. The resulting voids 21-21 are not filled in by subsequent oxide growth or by the application of planarization materials such as polymer layers. The voids would be exposed during the subsequent etchback which is used to planarize the doped glass, creating an open receptacle for process chemical or impurities and allowing subsequently deposited metallization to flow into the voids and short other devices and components along the trench. In the present process, the doped glass is melted and reflowed by applying a temperature of about 950° to 1,150°C in steam (oxidizing) or nitrogen (non- oxidizing) ambient for about 30 minutes to four hours depending upon the glass thickness and the trench dimensions. See Figure 5. The range of times results from the faster reflow which occurs as the process temperature is increased and from the requirement of longer proccessing times for thicker silicon dioxide layers 19. This process collapses the voids 21-21 and, for trench width dimensions of up to about 5 microns, reflows the upper surface 26 of the glass to a substantially level topography. During the glass deposition and reflow process steps, the silicon nitride layer 18 provides a barrier to oxidation and doping of the underlying polysilicon layer 17. For trench widths 5 microns, planarization is aided by depositing after the reflow a layer 27 of polymer such as PMMA to a thickness which is appropriate to the particular trench depth and width being used. It should be noted that one of the advantages of the present process is its adaptability to a wide range of trench dimensions, e.g., trench widths of one micron to 50 microns. According to this embodiment, planarization of the underlying glass is carried out by using an etch which removes PMMA and glass at substantially equal rates. Next, as shown in Figure 6, the silicon dioxide isolation layer 19 is etched back so that the surface 28 of the resulting glass field isolation regions 19-19 of the trench structure 29-29 is level with or below the surface of the polysilicon etch- stop/buffer layer 17. The etch can be done using a selective wet chemical etchant such as buffered hydrogen flouride, or using dry etching such as reactive ion etching with CHF3 etchant gas. As shown in Figure 6, the use of an RIE oxide etch also removes the silicon nitride layer 18 outside the trench confines. If the optional polymer layer has been used, it can be removed using the same reactive ion etching process which is applied to remove the silicon dioxide. Preferably, the etchant used does not attack poly, so that the polymer 27, oxide 19 and nitride 18 can be etched using the poly as an etch stop and thereby prevent overetching into regions such as the active regions 31. The next step is to outgas the phosphorus or boron dopant from the trench oxide 19-19 at a temperature of about 1,000° to 1,200°C in a nitrogen ambient for about two to eight hours. This step depletes the surface of the glass of the dopant and may also be used, for example, for the well drive-in of CMOS integrated circuits. During the outgassing thermal cycle, the silicon nitride layer again serves as a barrier to prevent doping or oxidation of the underlying trench structure including the substrate. It is no doubt recognized that even small amounts of dopant diffused through the barrier into silicon substrate 10 create parasitic current leakage paths. Next, and referring to Figure 7, the polysilicon layer 17 is removed from the active regions such as 31-31. The polysilicon can be removed using reactive ion etching or by wet chemical etching. Standard integrated circuit processing may then proceed. The resulting trench structures 29-29 shown in Figure 7 form the narrow, yet relatively deep, vertical sidewall , void-f ree structures which are necessary for small geometry, high-density, integrated ci rcuits. In addition, the silicon nitride blocking - l ayer 18 , the polysilicon etch-stop/buffe r layer 17 and the stress rel ief layer 16 remain in pl ace and contribute to the dielectric isolation. Foremost , the structure is created without critical rel iance on exotic equipment or highly ref ined trench shape control procedures . In the alternative embodiment of the invention shown in FIG . 3A, the polysilicon etch-stop layer 47 is formed on the sil icon nitride blocking layer 48 , rather than vice versa. This poly-over- nitride approach el iminates possible interaction between the glass isolation layer 19 and the nitide, which can occur when the nitride is formed on the poly (see FIGS. 3 and 4) . Typically, an oxidizing refl ow ambi ent is not used with the poly-on-nitride configuration of FIG. 3A, because the resulting polysil icon oxidation can consume the poly etch-stop layer 17. Otherwise, the fabrication process for the poly-nitride-oxide composite of FIG 3A is similar to that described relative to the nitride-poly-oxide composition of FIG. 3 with the exception that the nitride 48 is under the poly etch-stop layer 47 and thus typically cannot be removed during the etch back of glass 19. Instead, the etching sequence is glass 19, poly 47, and then nitride 48. The poly 47, nitride 48 and oxide 16 of FIG. 3A perform the same functions — etch-stop, oxidation ad dopant blocking, and stress relief — as do the poly 17, nitride 18 and oxide 16 of FIG. 3. Referring to FIG. 3B, in still another alternative embodiment of the present invention, a poly-nitride-poly-oxide sequence of layers is used. Here the outermost poly layer 47 acts as a barrier for the nitride 18 to eliminate any nitride reaction with the glass isolation layer 19, e.g., during the oxide reflow. Also, during reflow in an oxidizing ambient, oxidation of the poly 47 helps fill in and level the trench structures. The nitride 18 in turn blocks oxidation of the innermost poly layer 17 and thereby limits any poly consumption during the reflow step to the outermost poly layer 47. Thus, the nitride layer 18 preserves the innermost poly layer 17 and permits the use of an oxidizing ambient during reflow. The result is that the nitride 18 and poly 17 perform the same respective oxidation and dopant blocking and etch-stop functions as do the nitride 18 and poly 17 in FIG. 3. The fabrication process for the poly- nitride-poly-oxide composite structure involves obvious modifications of the nitride-poly fabrication of FIG. 3, involving primarily the addition of a second poly CVD step. Typically, if poly 47 is not consumed during the reflow step, the glass 19, poly 47, nitride 18 and poly 17 layers are removed sequentially. If the poly 47 is totally consumed during the reflow, the removal sequence f or the FIG. 3 structure can be used. Referring to FIG . 8 , there is shown one example of a MOSFET structure based upon the trench isolation structures 29 of the present invention. In the illustrated case, an NMOS FET of a complementary structure is shown formed in the p-well 33 of n-type epitaxial layer 34. The FET includes course and drain diffusions 36 and 37 and LDD implants 38 , all of which are self-aligned with the polysil icon gate 39 , as well as gate sidewall spacers 41 , interlevel dielectric 42 and aluminum interconnects 43. Quite obviously, this is only one possible appl ication among the various NMOS, PMOS, CMOS, bipolar and other applications off the present trench isolation structure and process.

Claims: CLAIMS : 1. A process for forming dielectric isolation regions (29) in a semiconductor substrate (10) , including the steps of forming trenches (13) in a surface of said semiconductor substrate (10) ; forming an insulator layer (16, 17, 18) over said surface, including the interior surfaces of said trenches (13); forming a layer of reflowable dielectric material over said insulator layer within and outside said trenches (13) ; and heating said reflowable dielectric material (19) , characterized in that said layer of insulator material includes an etch-stop layer (17) and an oxidation and dopant blocking layer (18) ; in that said layer is reflowable ' dielectric material in a silicon dioxide layer (19) doped to approximately 3 to 9 weight per cent with n- type or p-type impurities; and further characterized by the steps of: heating said substrate (10) for a sufficient time to reflow said silicon dioxide layer (19) thereby collapsing voids therein and providing a substantially smooth upper surface thereon; etching the reflowed silicon dioxide layer (19) to remove the deposited silicon dioxide outside said trenches (13) utilizing said etch-stop layer as an etch-stop; heating the resulting structure to remove impurity dopant from a surface adjacent region of the remaining portion of said silicon dioxide layer (19); removing said blocking layer (18) from regions outside said trenches (13); and removing said etch-stop layer (17) from regions outside said trenches (13) . 2. A process according to claim 1, characterized in that said step of removing said blocking layer (18) is effected prior to said step of heating to remove impurity dopant. 3. A process according to claim 1, characterized in that said insulator layer (16, 17, 18) includes a stress relief layer (16) formed of silicon dioxide at least on the interior surfaces of said trenches (13) . 4. A process according to claim 3, characterized in that said stress relief layer (16) of silicon dioxide has a thickness of about 300 to 1000 Angstroms. 5. A process according to claim 1, characterized in that said etch-stop layer (17) is formed of polycrystalline silicon and has a thickness of about 1000 to 3000 Angstroms. 6. A process according to claim 1, characterized in that said blocking layer (18) is formed of silicon nitride and has a thickness of about 1000 to 3000 Angstroms. 7. A process according to claim 1, characterized in that, said etch-stop layer (17) is formed prior to said blocking layer (18) . 8. A process according to claim 7, characterized by the step of forming a further etch- stop layer (47, Fig. 3B) after forming said blocking layer (18, Fig. 3B) . 9. A process according to claim 1, characterized in that said blocking layer (48, Fig. 3A) is formed prior to said etch-stop layer (47, Fig 3A). 10. A process according to claim 1, characterized in that said step of heating said substrate to reflow said silicon dioxide layer (19) is effected at a temperature in the range of about 950°C to 1150°C. 11. A process according to claim 1, wherein said step of heating to remove impurity dopant is effected at a temperature in the range of about 1000°C to 1200°C in a nitrogen ambient. 12. A process according to claim 1, characterized by the step of forming a planarization polymer layer (27) on said reflowed silicon dioxide layer (19) prior to said step of etching. 13. A semiconductor substrate provided with dielectric insulation regions in the form of trenches (13) having interior surfaces including substantially vertical sidewalls (14) and containing silicon dioxide dielectric material (19), characterized in that a multi-layered structure is diposed between said silicon dioxide dielectric material (19) and the interior surfaces of said trenches (13), said multi- layered structure including a polysilicon layer (17) and a silicon nitride layer (18). 14. A substrate according to claim 13, characterized in that said multi-layered structure includes a silicon dioxide layer (16) formed on the interior surfaces of said trenches (13). 15. A substrate according to claim 12 or claim 13, characterized in that said multi-layered structure includes a further silicon layer (47, Fig. 3B), said silicon nitride layer (18) being disposed between said silicon layer (17) and said further silicon layer (47).

Inventors: KAYA DENISE ANN, MUNDT RANDALL STEVEN, ROGERS STEVEN HILL, KAYA, DENISE, ANN, MUNDT, RANDALL, STEVEN, ROGERS, STEVEN, HILL
Applicants: NCR CO, NCR CORPORATION
Application year: 1985
Main classification: H01L21
IPC codes: H01L21