FIELD EFFECT TRANSISTOR TIMING SIGNAL GENERATOR CIRCUIT

Abstract: A circuit for generating accurate timing pulses which includes a timer means (10), a reference and feedback am­ plifier means (12), a feedback difference amplifier means (14), a difference amplifier means (16) and a pulse shaper means (18). The timer means (10) includes a constant current source which is triggered on by the input waveform signal and pro­ duces current i c . Reference and feedback amplifier means generates a voltage V ref which is proportional to current i c . Thus, if i c is too high or too low, V ref will represent the error value. The d.c. reference signal V ref , is applied to the feedback difference amplifier means (14) which is a typical dynamic detector circuit. Feedback difference amplifier circuit is trig­ gered and changes state when the voltage of the constant current timing circuit (which is proportional to i c ) equals the reference voltage V ref ′. The output signal from feedback difference amplifier means (14) is applied to the straightforward difference am­ plifer means (16) for further amplication. The amplified out­ put voltage signal is then applied to the pulse shaper circuit means (18) along with the original input signal such that the timing of the input signal is adjusted in accordance with the signal from the difference amplifier to produce an output timing pulse.

Description: The present invention relates to a circuit for generating accurate timing signals for computer clocking, and more particularly to a circuit including field effect transistor (FET) devices for producing accurate timing pulses. Description of the Prior Art The prior art contains numerous references describing circuits of various types for providing timing signals or pulses. For example, U. S. Patent 3,969,719 issued July 13, 1976 to Sirocka et al entitled ELECTRONIC WATCH shows a circuit including an oscillator which produces reference pulses which are divided down and then applied to level converters and shaper circuits. U.S. Patent 3,935,475 issued January 27, 1976 to Margolies entitled TWO-PHASE MOS SYNCHRONIZER describes an input circuit to a clock pulse circuit which includes an FET logic circuit and an output circuit which includes an inverter in series with an FET. U.S. Patent 4,072,932 issued February 7, 1978 to Kitagawa et al entitled CLOCK GENERATOR FOR SEMICONDUCTOR MEMORY describes a timing generator circuit including a differential read clock generator consisting of an FET bistable amplifier and a differential voltage sensor. The prior art does not teach an FET clock generating circuit including a constant current timing circuit which feeds a reference and feedback amplifier, an output of which is connected to a feedback difference amplifier providing an output through a pulse shaper. SUMMARY OF THE INVENTION Because of manufacturing processes, FET devices exhibit wide variations in parameters and tolerances, and it is therefore, difficult to utilize them in a clocking circuit where the generation of accurate timing pulses held to vary narrow tolerances is required. An object of the present invention is to provide a circuit using FET devices which will provide accurate timing pulses. Another object of the present invention is to provide an FET timing circuit including a constant current source that varies because of device variations and which further includes a reference voltage source which provides a compensating reference voltage that varies in level with the variations in the current source. Still another object of the present invention is to provide an FET timing circuit structure including a constant current source, a reference and feedback amplifier circuit for generating a varying reference voltage, a feedback difference amplifier for detecting the crossover between the constant current source signal and the reference voltage signal, and a pulse shaping circuit for providing an output timing signal adjusted in accordance with the crossover occurrence time. On Page 115 of EDN Volume 25, Number 2, published 20 January 1980, there is described a single-cycle timer integrated circuit connected to an external capacitor and resistor network. The capacitor and resistor are connected to a transistor switch to form a timing circuit responsive to a trigger pulse for producing a timing slope having a gradient depending on the values of circuit parameters and a supply voltage. A reference voltage generator in the form of a voltage divider generates a reference voltage having a magnitude proportional to the supply voltage. A detector connected to the timer circuit and the reference voltage generator produces a pulse signal representative of a cross-over time at which the magnitude of the timing slope is equal to that of the reference voltage. A flip flop is connected to the pulse signal and the trigger pulse for generating the output pulse. In accordance with the present invention, there is now provided a field effect transistor clock signal generator for providing an output clock signal adjusted in compensation for a variation in a transistor parameter comprising: a timer circuit responsive to an input clock pulse for producing a timing signal having a voltage slope which varies about a desired nominal slope in response to the variation in the transistor parameter; a reference voltage generator connected to the timer circuit for generating a reference voltage having a magnitude proportional to the difference between the voltage slope and the nominal slope; a difference amplifier connected to the timer circuit and the reference voltage generator for producing a pulse signal representative of a crossover time when the magnitude of the timing signal equals the magnitude of the reference voltage; a waveform shaper responsive to the input clock pulse and the pulse signal for producing an output clock pulse having an occurrence time determined by the input clock pulse and the crossover time; characterised in that: the timer circuit comprises a transistor current source connected between greater and lesser supply voltage levels for producing a current (Ic) in response to the input clock pulse, and a capacitor for generating the timing signal in response to the current (Ic); and the reference voltage generator comprises a first transistor matched to the transistor current source of the timer circuit and connected in series with a second transistor to form a voltage divider between the supply voltage levels for generating the reference voltage as a function of the current (Ic). The foregoing and other objects, features and advantages of this invention will be apparent from the following more particular description of the invention, as illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a timing signal generator according to the principles of the present invention. FIG. 2 is a schematic illustration of the constant current timer portion of the circuit of FIG. 1. FIG 3 is a waveform of voltage vs time useful in explaining the operation of the circuit of FIG. 1. DESCRIPTION FIG. 1 is a schematic diagram of a circuit for generating accurate timing pulses using FET devices which exhibit considerable parameter spreads as a result of manufacturing processes. The circuit includes a timer means 10, a reference and feedback amplifier means 12, a feedback difference amplifier means 14, a difference amplifier means 16 and a pulse shaper means 18. Timer means 10 includes an input transistor 20 connected to and triggered by a negative going waveform input signal. A depletion device 22 is connected between potential source V DD and transistor 20. This forms a constant current source which is triggered on by the input waveform signal and produces current i c . The current i c is applied to and charges capacitor 24 until a preset level is reached. For example, FIG. 2 illustrates the current i c charging capacitor 24 to provide a voltage V x across capacitor 24. FIG. 3 illustrates the time for charging capacitor 24 to given levels of V x . In a nominal time, capacitor 24 should charge to V x =N for a nominal current i c . However, because of device manufacturing spreads, the current i c will vary, and for a spread as illustrated in FIG.3, a low value of i c will charge capacitor 24 slowly such that V x will only be equal L after the nominal time period and it will take until time F for V x to reach the voltage line N. Likewise, a high value of i c will charge capacitor 24 rapidly such that V x will equal N at time S prior to the nominal time period and V x will continue to increase and be as high as H after the nominal time period has elapsed. This variation is compensated for in the present invention by varying a d.c. reference voltage level linearly with the variation of current i c such that the time at which the voltage V x across capacitor 24 intersects the reference voltage level is maintained at a nominal constant value. In other words, referring to FIG. 3, the nominal time as measured to the line H-N-L should be maintained. Therefore, for large values of i c (i.e., FAST), the d.c. reference voltage should be set high to intersect i c at point H on the same nominal time value line H-N-L whereas for smaller values of i c (i.e., SLOW) the d.c. reference voltage level should be set low to intersect i c at point L on the same nominal time value line H-N-L. Thus, as variations in the value of i c occur as a result of FET parameter spreads, a d.c. reference voltage V ref' will be generated to linearly vary with the changes in i c in order to maintain accurate (constant) timing. The varying reference voltage V ref' is generated by reference and feedback amplifier means 12. Reference and feedback amplifier means 12 includes a pair of transistors 26 and 28. Transistors 26 and 28 are connected between V DD and ground. Transistor 26 is electrically the same as transistor 22 which generates current i c , and the voltage V ref between transistors 26 and 28 is proportional to the current flowing through transistor 26. Thus, the voltage V ref is proportional to current i c . Thus, if i c is high as shown in FIG. 3, V ref will represent the error value H-N, whereas if i c is low, V ref will represent the error value N-L. The other five transistors 30, 32, 34, 36 and 38 of means 12 form a feedback amplifier to amplify V ref to a suitable value and provide stable gain and produces output d.c. voltage signal V ref' . The d.c. reference signal V ref' is applied to the gate of device 50 of feedback difference amplifier means 14. The output voltage signal of V x from constant current timing circuit 10 is applied to the gate of device 48 of feedback difference amplifier 14 which is a dynamic detector circuit including cross-coupled transistors 44 and 46, transistors 48 and 50 and transistor 52. Feedback difference amplifier circuit 14 is triggered and changes state when the voltage V x across capacitor 24 of constant current timing circuit 10 (which is proportional to i c ) equals the amplified reference voltage V ref' (i.e., the crossover point). The output signal from feedback difference amplifier means 14, which is the voltage at node 54 is applied to a straightforward difference amplifier means 16, including transistors 56, 58, 60, 62 and 64, for further amplification. The amplified output voltage signal from node 66 of difference amplifier means 16 is applied to a pulse shaper circuit means 18. Pulse shaper circuit means 18 includes a pair of depletion devices and transistors 72, 74 and 76. The same input signal applied to transistor 20 is also applied to the gate of transistor 72 and the output signal of difference amplifier 16 on node 66 is connected to the gate of transistor 76. Referring now to FIG. 1, the negative going input signal is applied to device 20, capacitor 24 charges in accordance with the rate of i c and an output voltage is provided from timer circuit 10 that is rising proportional to the rate of rise of i c . It may be faster than nominal or slower than nominal depending on the characteristics of the FET devices used. This rising voltage is appled to one side of difference amplifier 14 at the gate of device 48. Meanwhile, device 20 of reference and feedback means 12 is connected to device 22 of timer 10 and an error signal V ref proportional to the current i c is produced which indicates whether i c is rising faster (H-N) or slower (N-L) then the desired nominal rise. This V ref voltage is amplied and made stable in the feedback amplifier portion of means 12 and a d.c. output voltage V ref' is produced which is set high (i.e., at V x =H of FIG. 3) when i c rises faster than nominal or is set low (i.e., V x =L) when i c rises slower than nominal. In any case, V ref' is set such it is always at the same voltage value of the V x produced by i c at the end of the desired nominal time period, that is, for example, the time designated by the H-N-L line. This V ref' signal is applied to the other side of the difference amplifier 14 at the gate of device 50. Difference amplifier 50 will trigger when V x (due to i c from timer 10) is equal to the level of V ref' . The time when these voltages are equal is always the same time. If V x rises faster than nominal, then the V ref' produced is high, if V x rises slower than nominal then V ref' is low such that the two voltages are the same value along, for example, the H-N-L time line of FIG. 3. Difference amplifier triggers and produces a positive pulse at such time from device 48 and a corresponding negative pulse at this time from device 50 on node 54. Difference amplifier 14 is selected to have a wide input signal range and, therefore, has a low gain. The pulses from devices 48 and 50 are applied to another difference amplifier 16 to merely sharpen the pulse transitions and provide further amplification. Thus a sharp negative going pulse is produced on node 66 which is applied to the base of device 76 of pulse shaper means 18. The same input negative going input signal applied to device 20 of timer means 10 is applied to the base of device 72 of pulse shaper means 18. It should be recalled that the negative going pulse at node 66 occurs at the desired nominal time because is is produced when V x is equal to V ref' . The negative going input signal is inverted by device 72 and turns on device 74. When device 74 turns on the output voltage OUT from the pulse shaper means 18 goes low. Now the predetermined interval occurs corresponding to the signal at node 66 going negative. When the signal at node 66 goes negative, device 76 then goes off and the output voltage OUT goes high, completing the cycle. This provides an accurately timed clock pulse which always occurs at the same time regardless of variations in i c and V x due to variations in FET characteristics.

Claims: A field effect transistor clock signal generator for providing an output clock signal adjusted in compensation for a variation in a transistor parameter comprising: a timer circuit (10) responsive to an input clock pulse for producing a timing signal having a voltage slope which varies about a desired nominal slope in response to the variation in the transistor parameter; a reference voltage generator (12) connected to the timer circuit (10) for generating a reference voltage having a magnitude proportional to the difference between the voltage slope and the nominal slope; a difference amplifier (14) connected to the timer circuit (10) and the reference voltage generator (12) for producing a pulse signal representative of a crossover time when the magnitude of the timing signal equals the magnitude of the reference voltage; a waveform shaper (18) responsive to the input clock pulse and the pulse signal for producing an output clock pulse having an occurrence time determined by the input clock pulse and the crossover time; characterised in that: the timer circuit (10) comprises a transistor current source (22) connected between greater and lesser supply voltage levels for producing a current (Ic) in response to the input clock pulse, and a capacitor (24) for generating the timing signal in response to the current (Ic); and the reference voltage generator (12) comprises a first transistor (26) matched to the transistor current source (22) of the timer circuit (10) and connected in series with a second transistor (28) to form a voltage divider between the supply voltage levels for generating the reference voltage as a function of the current (Ic). A clock signal generator as claimed in Claim 1 wherein the reference voltage generator (12) increases the reference voltage in response to the timing slope becoming greater than the nominal slope. and decreases the reference voltage in response to the timing slope becoming less than the nominal slope. A clock signal generator as claimed in Claim 2 wherein the reference voltage generator (12) comprises an amplifier (30,32,34,36,38) for amplifying the voltage level to generate a reference voltage for maintaining stability of the clock signal generator. A clock signal generator as claimed in Claim 3 wherein the feedback difference amplifier (14) comprises a first switching transistor (50) responsive to the reference voltage and a second switching transistor (48) responsive to the timing signal; the first and second switching transistors (50,48) being interconnected for generating the pulse signal when the magnitude of the timing signal and the magnitude of reference voltage are equal. A clock signal generator as claimed in Claim 4 wherein the pulse shaper (18) comprises first and second output transistors, the first output transistor turning on in response to the pulse signal, and the second output transistor turning on in response to the input clock pulse; the output clock pulse being produced when both the first and the second output transistors are turned on.

Inventors: RAVER, NORMAN
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1985
Main classification: H03K5
IPC codes: H03K5