SEMICONDUCTOR PHOTODETECTOR

Abstract: A semiconductor photodetector such as a PIN photo­ diode or an avalanche photodiode comprising an InP substrate (1, 21), a first InP layer (2, 22), a GaInAs or GaInAsP light absorbing layer (3, 23), and a second InP layer (4; 25, 26). All of the layers are successively grown by a vapor phase epitaxial process wherein the lattice constant of the GaInAs (GaInAsP) layer (3, 23) is larger than that of the first InP layer (2, 22) at room temperature. Consequently the photodetector has a low dark current.

Description: The present invention relates to semiconductor photodetectors, such as a PIN photodiode and an avalanche photodiode. Photodetectors for optical fiber communication systems in the 1.3 to 1.6 µm wavelength region include PIN photodiodes and avalanche photodiodes made of a III-V alloy system, e.g., GaInAs/InP system. Such a photodiode comprises an InP substrate, an InP buffer layer, an GaInAs light absorbing layer, and an InP cap layer, these layers being epitaxially formed in succession on the InP substrate. Heterojunctions are formed at interfaces between the InP buffer layer and GaInAs layer, and between the GaInAs layer and InP cap layer. A PIN photodiode is produced, for example, in the following manner. First, an undoped (N⁻-type) InP buffer layer is epitaxially grown on a (100) oriented N⁺-type InP substrate; an undoped (N⁻-type) GaInAs light absorbing layer is epitaxially grown on the InP buffer layer; and an N-type InP cap layer is also epitaxially grown on the GaInAs layer. A P-type region is formed as a light receiving area in the InP cap layer by a thermal diffusion process; an antireflecting film is formed on the P-type region; and a protecting film is formed on the Inp cap layer. Finally, a P-side electrode and an N-side electrode are formed on the P⁺-type region and the InP substrate, respectively. During the epitaxial growth, the growing conditions are controlled so that the lattice constant of the grown layers matches that of the InP substrate, to decrease the possibility of lattice mismatching. It is easy to match the lattice constant of the InP layer to that of the InP substrate, since the InP layer and the InP substrate can have the same composition, but when the GaInAs layer is epitaxially grown on the InP layer, i.e. InP substrate, it is necessary to control the composition ratio of Ga to In in the GaInAs layer so that the lattice constant of the GaInAs matches that of the InP. The thermal expansion coefficient of GaInAs is 1.24 times larger than that of InP; i.e. the thermal expansion coefficient of InP is 4.56 x 10⁻⁶ K⁻¹ and that of GaInAs is 5.66 x 10⁻⁶ K⁻¹. Therefore, when the GaInAs layer is grown at a temperature of, typically, from 600°C to 700°C to obtain a lattice match with the InP layer, the shrinkage of the GaInAs layer is more than that of the InP layer, at room temperature, with the result that strain is generated, which causes mismatching between the layers. In another method, it is possible to grow the GaInAs layer in a mismatching condition so that the GaInAs and InP will match when cooled at room temperature. According to a first aspect of the present invention there is provided a semiconductor photodetector comprising an InP substrate, a first InP layer, a GaInAs (or GaInAsP) layer, and a second InP layer, which layers are successively epitaxially formed by a vapor phase epitaxial process on said InP substrate; characterised in that the lattice constant of said GaInAs (or GaInAsP) layer is larger than that of said first InP layer at room temperature such that the lattice mismatching degree between said GaInAs (or GaInAsP) layer and said first InP layer is within the range over 0 to 0.2%; wherein: According to a second aspect of the present invention there is provided a semiconductor photodetector comprising an InP substrate, a first InP layer, a GaInAs layer,a GaInAsP layer, and a second InP layer, which layers are successively epitaxially formed by a vapor phase epitaxial process on said InP substrate; characterised in that: the lattice constant of said GaInAs layer is larger than that of said first InP layer at room temperature such that the lattice mismatching degree (Δa/a) between said GaInAs layer and said first InP layer is within the range over 0 to 0.2%; wherein: and in that a lattice constant of said GaInAsP layer lies in the range between said InP layer lattice constant and said GaInAs layer lattice constant, inclusively. In accordance with the above-mentioned two growth methods two GaInAs light absorbing layers were each epitaxially grown in liquid-phase condition on the InP buffer layer, and each of the obtained GaInAs layers was measured by X-ray diffractometry, respectively. As a result, it was found that it is preferable to match GaInAs to InP at an epitaxial growth temperature, e.g. 600°C to 700°C, as in the former method above, since this growth method generates less mismatching than the latter growth method above. Therefore, a Ga 0.48 In 0.52 As layer is liquid-phase grown on the InP layer at a usual growing temperature, e.g. 650°C, under the lattice matching condition. In this case, at room temperature, the lattice constant of GaInAs is smaller than that of InP, due to the thermal expansion difference, by a lattice mismatching degree Δa/a of approximately -0-07%: wherein According to the above experience of the liquid-phase epitaxial growth it has been believed that, even in the vapor-phase epitaxial growth, the GaInAs layer growth under the lattice matching condition brings about the least mismatching at the heterointerface between the GaInAs and InP layers, notwithstanding the lattice mismatching degree (Δa/a) of -0.07% at a room temperature. Such a belief may be based on the fact that both the vapor-phase epitaxial growth and the liquid-phase epitaxial growth are epitaxial growths. However, although PIN photodiodes are produced at the same time by performing the vapor-phase epitaxial growth of the GaInAs layer under the above-mentioned preferable condition, the properties of the produced PIN photodiodes are not satisfactory, in particular, a problem of dark current in the photodiodes occurs frequently. An embodiment of the present invention may provide an improved photodetector made of a III-IV alloy system, such as GaInAs/InP, and GaInAsP/InP. An embodiment of the present invention may provide a photodetector, such as a PIN photodiode and an avalanche photodiode, having a GaInAs/InP or GaInAsP/InP system, with a low dark current. The present invention is based on the discovery of the inventors that at the lattice mismatching degree Δa/a between the GaInAs (or GaInAsP) light absorbing layer and the InP buffer layer in the positive (plus) range (especially, from 0 to 0.2%) the dark current is lower than the negative (minus) range (outside the range of 0 to 0.2%) at room temperature. The GaInAs (or GaInAsP) light absorbing layer having an energy bandgap smaller than the InP layer, being a dark current generating region, is under a tension stress at minus Δa/a, but is under a compression stress at plus Δa/a. Here the present inventors have assumed that the crystal state of the GaInAs (or GaInAsP) layer under a compression stress is more stable than that under a tension stress. According to the present invention, in a semiconductor photodetector comprising an InP substrate, a first InP layer, a GaInAs (or GaInAsP) layer, and a second InP layer, wherein the layers are successively epitaxially formed on the InP substrate, the lattice constance of the GaInAs (or GaInAsP) layer is larger than that of the first InP layer at room temperature. All of the layers are sequentially grown by a vapor phase epitaxial process. Reference is made, by way of example, to the accompanying drawings, in which: Fig. 1 is a sectional view of a PIN photodiode having a GaInAs/InP system to which the present invention may be applied; Fig. 2 is a graph showing the relationship between the lattice mismatching degree (Δa/a) and the dark current in PIN photodiodes in a GaInAs/InP system; Fig. 3 is a graph showing a lattice matching condition for InP in a GaInAsP system; Fig. 4 is a graph showing the relationship between the thickness of the GaInAs layer and the quantum efficiency; and Fig. 5 is a sectional view of an avalanche photodiode having a GaInAs/GaInAsP/InP system to which the present invention may be applied. Referring to Fig. 1, a PIN photodiode comprises, for example, an N⁺-type InP substrate 1, an undoped N⁻-type InP buffer layer 2, an undoped N⁻-type GaInAs (or GaInAsP) light absorbing layer 3, an N-type InP cap layer 4, and a passivation film 5. A P⁺-type region 6 is formed in the InP cap layer 4 and extends into the GaInAs (or GaInAsP) layer 3. An antireflecting film 7 is formed on the P⁺-type region 6, a P-side electrode 8 is formed on a portion of the P⁺-type region 6, and an N-side electrode 9 is formed on the InP substrate 1. The above structure is that of a PIN photodiode. A PIN photodiode to which the present invention may be applied, illustrated in Fig. 1, may be produced for example as follows. First, a (100) oriented N⁺-type InP wafer having an impurity concentration of approximately 4 x 10¹⁸ cm⁻³ is prepared as the substrate 1. On the InP substrate 1 an InP buffer layer 2 having a thickness of 3 µm and an impurity concentration of approximately 5 x 10¹⁴ cm⁻³ is grown by a vapor phase epitaxial process, under the following conditions. A carrier gas of H₂ is made to flow through PCl₃ liquid to feed an H₂ + PCl₃ gas at a flow rate of 300 cm³/min into a reactor. In the reactor, an In source and the InP substrate 1 are heated at 800°C and 670°C, respectively. An additional carrier gas of H₂ is fed into the reactor, so that the total H₂ flow rate at the growth region is 956 cm³/min. As a result, the InP layer 2 is grown at a growth rate of approximately 1.2 nm/sec (12 Å/sec). Then a GaInAs layer 3 having a thickness of 1.6 µm and an impurity concentration of approximately 1 x 10¹⁵ cm⁻³ is grown on the InP layer 2 by vapor phase epitaxy under the following conditions. A carrier gas of H₂ is made to flow through AsCl₃ liquid to feed an H₂ + AsCl₃ gas into the reactor. A portion of the H₂ + AsCl₃ gas is made to flow at a flow rate of 144 cm³/min over a Ga source heated at 750°C and the rest of the H₂ + AsCl₃ gas to flow at a flow rate of 312 cm³/min over another In source heated at 800°C. An additional carrier gas of H₂ is fed into the reactor, so that the total H₂ flow rate at the growth region in which the substrate 1 is heated at 670°C is 956 cm³/min. As a result, the Ga 0.45 In 0.55 As layer 3 is grown at a growth rate of approximately 0.3 nm/sec (3 Å/sec). In this kind of GaInAs epitaxy growth process, the atomic ratio "x" of In to Ga in Ga 1-x In x As can be varied by controlling a ratio of the flow rate of the H₂ + AsCl₃ gas over the In source to that of the H₂ + AsCl₃ gas over the Ga source. Therefore, the lattice constant of the GaInAs layer can be varied, so that the lattice mismatching degree Δa/a can also be varied. To grow a quaternary compound layer of GaInAsP, the H₂ + AsCl₃ gas flowing over either the Ga source or the In source is replaced with a flow of H₂ + PCl₃ gas. Thereafter an InP cap layer 4 having a thickness of 1 µm and an impurity concentration of approximately 1 x 10¹⁶ cm⁻³ is grown in a similar manner to that of the InP buffer layer 2, except that donor impurities (sulfur) are added. A passivation film 5 of silicon nitride having a thickness of approximately 0.18 µm is formed on the InP cap layer 4 by a plasma chemical vapor deposition (CVD). The silicon nitride film 5 is then selectively etched by conventional photo-lithography to form an opening for a photodetective region. The P⁺-type region 6 is formed by thermally diffusing zinc (Zn) into the InP cap layer 4 through the opening of the silicon nitride film 5 at 500°C. The diffused Zn reaches a portion of the GaInAs layer 3, so that the bottom of the P⁺-type region 6 is in the GaInAs layer 3, as shown in Fig. 1. The surface impurity concentration of the P⁺-type region 6 is approximately 4 x 10¹⁸ cm⁻³. Then the antireflection film 7 of silicon nitride having a thickness of 1.8 µm is formed on the exposed surface of the P⁺-type region 6 by plasma CVD. In this case, silicon nitride is also deposited on the formed silicon nitride film 5, so that the thickness of the passivation film 5 of silicon nitride is increased. The anti-reflection film 7 is selectively etched by conventional photo-lithography to form an opening for the electrode 8. The electrode 8 of AuZn may be formed by a conventional process, so that it comes into contact with the P⁺-type region 6. The diameter d of the photodetective region is 80 µm for example. The electrode 8 of AuGe may be formed on the InP substrate 1 by a conventional process. Thus, the PIN photodiode is obtained. A large number of PIN photodiodes produced in the above-mentioned manner were examined for the amount of dark current therein and the lattice mismatching degree Δa/a between the GaInAs layer and the InP layer at room temperature. The lattice mismatching degree was measured by the X-ray diffraction method. The obtained results of the amount of dark current and lattice mismatching degree Δa/a are shown in Fig. 2. Each cross indicates the range of Δa/a and dark current of PIN photodiodes produced in an InP wafer. As seen in Fig. 2, low dark current photodiodes are obtained on the plus side of Δa/a, preferably from 0 to +0.2%. A broken line in Fig. 2 indicates a lattice mismatching degree Δa/a (-0.07%) obtained when a Ga 0.48 In 0.52 As layer is liquid phase epitaxially grown under the lattice matching condition at the growth temperature. According to the present invention, the GaInAs layer is vapor phase epitaxially grown under the condition that the lattice constant of the grown GaInAs layer is larger than that of the InP layer at the growing temperature. Namely, as shown in Fig. 3, a lattice matching condition for InP in a GaInAsP quaternary system is indicated with a dot and dash line A, including Ga 0.47 In 0.53 As in a GaInAs ternary system. In a known case, a GaInAs layer having a composition at a point B is grown with Δa/a < 0, whereas in and embodiment of the present invention a GaInAs layer having a composition at a point C is grown under the limitation of 0 < Δa/a < 0.2. As to the thickness of the GaInAs layer, a thicker GaInAs layer having +Δa/a applies a stronger force on the heterojunction interface. Accordingly, it is preferable that the GaInAs layer be thin. However, too thin a GaInAs layer brings about a decrease of the quantum efficiency of the layer. Figure 4 shows a relationship between the GaInAs layer thickness and the quantum efficiency; the abscissa showing the thickness of the GaInAs layer and the ordinate showing the corresponding quantum efficiency. The quantum efficiency η at 1.3 µm is calculated by the following formula: η = 1 - e -αx wherein α is an optical absorption coefficient (1.4 x 10⁴ cm⁻¹ of GaInAs), and x is the thickness of the GaInAs layer. As seen from Fig. 4, when the GaInAs layer thickness is less than 1 µm, the quantum efficiency further decreases. Therefore, to attain a required quantum efficiency of a photodiode and the application of a low force on the heterojunction interface, the GaInAs layer preferably has a thickness of from 1 to 2 µm. Furthermore, a force applied on the heterojunction interface between the GaInAs layer and the InP cap layer is preferably decreased by making the InP cap layer thinner. In practice, the InP cap layer preferably had a thickness of from 1.0 to 0.3 µm. Referring to Fig. 5, an avalanche photodiode to which the present invention may be applied comprises, for example, a (100) N⁺-type InP substrate 21, an N-type InP layer 22, an undoped N⁻-type GaInAs light absorbing layer 23, an undoped N⁻-type GaInAsP thin layer 24, an N-type InP layer 25, and an N⁻-type InP layer 26. A passivation film 27 is formed on the N⁻-type InP layer 26, a P⁺-type region 28 is formed in the N⁻-type InP layer 26, and an antireflection film 29 is formed on the P⁺-type region 28. A P-side electrode 30 and an N-side electrode 31 are formed on a portion of the P⁺-type region 28 and on the InP substrate 21, respectively. According to the present invention, the lattice constant of the GaInAs layer 23 is larger than that of the InP layer 22 at room temperature. Preferably, the lattice constant of the GaInAsP layer lies in the range between the InP lattice constant and the GaInAs layer lattice constant, inclusively, at room temperature. It is also preferable that another undoped N⁻-type GaInAsP thin layer (not shown) be formed between the N-type InP layer 22 and the GaInAsP layer 23. The GaInAsP layer has an energy bandgap Eg having an intermediate value (0.9 eV) between that of InP (1.35 eV) and GaInAs (0.75 eV). The GaInAsP layer has intermediate energy bandgap and lattice constant values, and thus can improve the frequency property of an avalanche photodiode. An avalanche'photodiode illustrated in Fig. 5 embodying the present invention, photodiode illustrated in Fig. 5 may be produced, for example, in the following manner. A (100) oriented N⁺-type InP wafer having an impurity concentration of approximately 4 x 10¹⁸ cm⁻³ is prepared as the substrate 21. On the InP substrate, layers 22 to 26 having the thicknesses and impurity concentrations shown in Table 1 are successively grown by a vapor phase epitaxial process mentioned hereinbefore. In the formation of the N⁻-type GaInAs layer 23, the growth conditions are controlled so as to make the lattice constant of GaInAs larger than that of InP at room temperature. Similarly, the growth conditions for the GaInAsP layer 24 are controlled so as to make the lattice constant of GaInAsP not less than that of InP and not more than that of the formed GaInAs layer at room temperature. The passivation film 27 of silicon nitride with an opening is formed by a plasma CVD process and by conventional photo-lithography. Using the passivation film 27 as a mask, Zn is introduced into the N⁻-type InP layer 26 by a thermal diffusion process to form the P⁺-type region 28 having a surface impurity concentration of 4 x 10¹⁸ cm⁻³. Then the anti-reflection film 29 of silicon nitride having a thickness of 0.18 µm is formed on the P⁺-type region 28 by the plasma CVD process. The electrode 30 of AuZn and the electrode 31 of AuGe are formed on the P⁺-type region 28 and the InP substrate 21, respectively, as shown in Fig. 5. A light receiving area has a diameter d of 80 µm for example. Thus a low dark current avalanche photodiode embodying the present invention is obtained.

Claims: A semiconductor photodetector comprising an InP substrate (1,21), a first InP layer (2,22), a GaInAs (or GaInAsP) layer (3,23), and a second InP layer (4,26), which layers are successively epitaxially formed by a vapor phase epitaxial process on said InP substrate (1,21);characterised in that the lattice constant of said GaInAs (or GaInAsP) layer (3,23) is larger than that of said first InP layer (2,22) at room temperature such that the lattice mismatching degree (Δa/a) between said GaInAs (or GaInAsP) layer (3,23) and said first InP layer (2,22) is within the range over 0 to 0.2%; wherein: A semiconductor photodetector according to claim 1 , wherein said GaInAs (or GaInAsP) layer (3,23) has a thickness of from 1 to 2µm. A semiconductor photodetector according to claim 1 or 2, wherein said first InP layer (2,22) is an undoped N⁻-type layer, said GaInAs (or GaInAsP) layer (3,23) is an undoped N⁻-type layer, and said second InP layer (4,26) is an N -type layer, in which second InP layer (4,26) a P-type region (6,28) is formed. A semiconductor photodetector comprising an InP substrate (21), a first InP layer (22), a GaInAs layer (23), a GaInAsP layer (24), and a second InP layer (25,26), which layers are successively epitaxially formed by a vapor phase epitaxial process on said InP substrate (21); characterised in that:the lattice constant of said GaInAs layer (23) is larger than that of said first InP layer (22) at room temperature such that the lattice mismatching degree (Δa/a) between said GaInAs layer (23) and said first InP layer (22) is within the range over 0 to 0.2%; wherein: and in that : the lattice constant of said GaInAsP layer (24) lies in the range between said InP layer (22) lattice constant and said GaInAs layer (23) lattice constant, inclusively. A semiconductor photodetector according to claim 4, wherein said first InP layer (22) is an N-type layer, said GaInAs layer (23) is an undoped N⁻-type layer, and said GaInAsP layer (24) is an undoped N⁻-type layer, and said second InP layer (25,26) is an N-type layer, in which second InP layer a P-type region (28) is formed. A semiconductor photodetector according to claim 5, wherein another undoped GaInAsP layer is formed between said first InP layer (22) and said InGaAs layer (23).

Inventors: KAGAWA, SHUZO, KOMENO, JUNJI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H01L31
IPC codes: H01L21, H01L29, H01L31