PROTECTION DEVICE FOR A MOS TRANSISTOR

Abstract: A semiconductor integrated circuit includes a MOS transistor (TR13), and a transistor circuit (TR14, R1 in which one end of a current path is connected to a drain of this MOS transistor (TR13) and which has a breakdown voltage lower than an avalanche breakdown voltage of the MOS transistor (TR13).

Description: The present invention relates to a semiconductor integrated circuit having the function to prevent rupture of a MOS transistor. Erasable/programmable read only memories (EPROM) need an operating voltage of, e.g.,·5 V and a writing voltage of, e.g., 20 v, which is higher than this operating voltage in the data program mode or data writing mode. In order to get the higher drain avalanche breakdown voltage of a MOS transistor to which a voltage of 20 V is applied, various devices are adopted. Fig. 1 schematically shows a memory circuit including a floating gate type MOS transistor TR1 which constitutes a memory cell. One end of the current path of the MOS transistor TR1 is grounded and the other end is connected to a high voltage terminal VH through MOS transistors TR2 and TR3 in series. Row and column selection signals from row and column decoders (not shown) are supplied to the gates of the MOS transistors TR1 and TR2, while a data signal is supplied to the gate of the MOS transistor TR3 in the writing mode. When writing data, the row and column selection signals, with a voltage level of VH (20 V), are supplied to the gates of the MOS transistors TR1 and TR2, and the data signal at the VH level is supplied to the gate of the MOS transistor TR3. However, when no data is written in the MOS transistor TR1, the data signal of 0 V is supplied to the gate of the MOS transistor TR3, thereby making the MOS transistor TR3 non-conductive. It is generally known that MOS transistors have a lower drain avalanche breakdown voltage due to the electric field between the drain and the gate in the case where a gate voltage of 0 V is applied rather than the case where turn-on voltage is applied to the gate. On one hand, as the elements become fine, the gate insulation film becomes thin, so that the electric field between the drain and the gate becomes strong and this causes the breakdown voltage to be lowered. To prevent such a reduction in the breakdown voltage, as shown in Fig. 2, it has been hitherto considered a method whereby the impurity concentration of the portion of the drain close to the gate is made lower than that of the residual portion, thereby weakening the electric field between the gate and the drain. In Fig. 2, n + -type regions 1 and 2 are formed to face each other in the surface area of a p-type substrate 3. An n - -type region 4 is formed so as to come into contact with the n + -type region 2 and extend in the direction of the n + -type region 1. A gate insulation film 5 is formed on the partial area of the p-type substrate 3 between the n + -type region 1 and the n - -type region 4. A gate electrode 6 is further formed on the gate insulation film 5. The n + -type region 1 forms the source and the n + -type region 2 and n - -type region 4 cooperatively form the drain. A data signal is supplied to the gate electrode 6 and the n + -type region 2 is connected to the high voltage terminal VH and the n + -type region 1 is connected to, for example, the drain of the MOS transistor TR2. In such an arrangement, when a high voltage is applied to the high voltage terminal VH, a wider depletion layer is formed between the n - -type region 4 and the substrate 3, so that the electric field between the n - -type region 4 and the gate electrode 6 becomes weaker, thereby causing the breakdown voltage of this MOS transistor to be improved. However, if an abnormally high voltage is applied to the high voltage terminal VH due to the influence of static electricity or the like, a voltage higher than the dielectric breakdown voltage is applied to the gate insulation film 5 since the drain breakdown voltage is high, so that there is a possibility that this gate insulation film may be broken. This problem could easily occur as the elements become finer and the gate insulation film becomes thinner. Recently, a semiconductor integrated circuit having an output buffer circuit which is constituted by MOS transistors having similar structures as those shown in Fig. 2 has been provided. In operation, a voltage of 5 V is applied to drains of the MOS transistors of this output buffer circuit. However, there is a case such that when those drains are disconnected from a power source, an abnormally high voltage is applied to the drains due to the influence of static electricity. In such a case, there is a possibility that the gate insulation films of the MOS transistors of the output buffer circuit will be broken as in the foregoing case. A protection circuit is known from EP-A-0 05 85 57 which includes a type of lateral bipolar transistor connected in parallel to the device to be protected. The transistor is arranged so that its breakdown voltage is lower than the maximum allowable voltage which may be applied to the device to be protected. A further protection circuit is known from US-A-4 11 5709 and EP-A-0 03 49 29 in which a gate controlled diode (GCD) is arranged in parallel to the device to be protected. The breakdown voltage of the GCD is arranged so that it is lower than the maximum allowable operating voltage of the device to be protected. It is an object of the present invention to provide a semiconductor integrated circuit having the function to prevent rupture of a MOS transistor when a voltage over a predetermined value is applied to the drain of the MOS transistor. This object is solved by a semiconductor integrated circuit comprising: first and second potential terminals; a first MOS transistor having a current path connected, between said first and second potential terminals; and a protective transistor circuit including a transistor device having a current path with one end connected to said first potential terminal, and the other end of said current path being coupled to said second potential terminal, said transistor device having a breakdown voltage lower than that of said first MOS transistor; characterized in that said transistor device is a second MOS transistor having a source, a drain, a gate and a gate insulation film thicker than said first MOS transistor and whose drain is connected to the drain of said first MOS transistor and said protective transistor circuit further comprises a resistive means connected between said second potential terminal and the gate and source of said transistor device. In this invention, when a high voltage is applied to the drain of the MOS transistor, the transistor circuit is made conductive, thereby preventing this high voltage from being continuously applied to the drain of the MOS transistor. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a conventional memory circuit; Fig. 2 is a schematic cross sectional view of a MOS transistor which is used in the memory circuit shown in Fig. 1 and whose conduction state is controlled in response to a data signal; Fig. 3 shows a semiconductor integrated circuit according to one embodiment of the present invention; Fig. 4 is a schematic cross sectional view of a MOS transistor which is used in the semiconductor integrated circuit shown in Fig. 3 and is broken when a high voltage is applied to a high voltage terminal; Fig. 5 shows actual measurement data showing the relation between a value of the resistor in the semiconductor integrated circuit shown in Fig. 3 and the voltage which had been applied to the high voltage terminal when at least one MOS transistor in the semiconductor integrated circuit was broken; and Fig. 6 shows an example of a modified form of the semiconductor device shown in Fig. 4. Fig. 3 shows a semiconductor integrated circuit according to one embodiment of the present invention. This semiconductor integrated circuit includes a floating gate type MOS transistor TR11 and MOS transistors TR12 and TR13 which are connected between a high voltage terminal VH and a ground terminal and are constituted similarly to the MOS transistors TR1 to TR3 shown in Fig. 1; and a MOS transistor TR14 whose drain is connected to the high voltage terminal VH and whose gate and source are grounded through a resistor R1. The MOS transistor TR13 is constituted similarly to the transistor structure shown in Fig. 2. As shown in Fig. 4, the MOS transistor TR14 is constituted by n + -type regions 11 and 12 which are formed in the surface area of a p-type substrate 3 and serve as the source and drain, respectively; a gate insulation film 13 formed on a partial area of the p-type substrate 3 between the n + -type regions 11 and 12; and a gate electrode 14 formed on the insulation film 13. The n + -type region 11, which serves as the source, is electrically coupled to the gate electrode 14 and is also grounded through the resistor R1. The n + -type region 12, which serves as the drain, is connected to the high voltage terminal VH. Further, the gate insulation film 13 of the MOS transistor TR14 shown in Fig. 4 is formed thicker than the gate insulation film 5 (Fig. 2) of the MOS transistor TR13. In the case of employing the silicon gate technology to form the MOS transistor TR14 without increasing the number of manufacturing steps, it is convenient to form the MOS transistor TR14 by using a field oxide film as the gate insulation film on the partial area of the substrate between the n + -type regions 11 and 12 and by forming an aluminum layer on this oxide film. Since the gate insulation film 13 of the MOS transistor TR14 is thickly formed and the electric field between the gate and the drain is weak, in the case where the voltage at the high voltage terminal VH is gradually increased, breakdown of the pn junction between the n + -type region I2 near the field insulation film and the p-type substrate 3 occurs, before breakdown of the n + -type region 12 under the gate insulation film 13 occurs. A voltage VH1 at the high voltage terminal VH upon breakdown of the pn junction in the MOS transistor TR14 will be at a voltage level lower than a voltage VH2 being applied to the high voltage terminal VH when the gate insulation film 5 of the MOS transistor TR13 is broken. In the MOS transistor TR14 shown in Fig. 4, it is now assumed that between the n + -type regions 11 and 12 is, for instance, 4 µm and breakdown of the pn junction between the n + -type region l2 and the p-type substrate 3 would occur when a voltage of 26 V were applied to the high voltage terminal VH. Now, assume that a voltage over 26 V were applied to the high voltage terminal VH due to the influence of static electricity under a condition that the high voltage terminal VH were disconnected from a power source (not shown). Then, breakdown of the pn junction would occur and the potential of the substrate 3 increase and the npn transistor of which the substrate 3 and the n + -type regions 11 and 12 serve as the base, emitter and collector, respectively, were made conductive, causing the charges induced at the high voltage terminal VH, due to the static electricity, to be discharged through the n + -type region 12, p-type substrate 3, n + -type region 11, and resistor R1. Due to this, even if a high voltage were applied to the high voltage terminal VH, the MOS transistor TR13 would not be broken. According to the results of experiments by the inventors of the present invention, it has been found that as the channel width of the MOS transistor TR14 is large, the MOS transistor TR14 was not broken even if a higher voltage was applied to the high voltage terminal VH. In addition, in the case where the resistor R1 was experimentally set to zero ohm and a high voltage over a predetermined value was applied to the high voltage terminal VH due to the static electricity, it has been found from the experiment that the MOS transistor TR14 was broken but the MOS transistor TR13 operated normally. In this case, it was considered that the charges induced due to the static electricity flowed through the MOS transistor TR14 and the MOS transistor TR14 was broken due to heat generation or the like. So during further experiments the present inventors increased the value of the resistor R1 in order to reduce the current flowing through the MOS transistor TR14. For example, in the case where the value of the resistor R1 was set to 50 ohms and a high voltage was applied to the high voltage terminal VH, the MOS transistor TR13 was broken but the MOS transistor TR14 operated normally. Fig. 5 shows the voltages applied to the high voltage terminal VH when the MOS transistors TR13 and TR14 were broken when the value of the resistor R1 was set to 0, 10, 20, 30, 40, and 50 ohms (Ω). High voltage was charged in a capacitor of 200 pF, this capacitor was connected to the high voltage terminal VH by use of a switch, thereby allowing this high voltage to be applied to the high voltage terminal VH. In the experiments, this high voltage was changed by 25 V at a time. In the diagram, a black dot · indicates the voltage applied to the high voltage terminal VH when the MOS transistor TR14 of each sample was broken, while a mark x represents the voltage applied to the high voltage terminal VH when the MOS transistor TR13 of each sample was broken. As will be obviously understood from Fig. 5, when R1 = 0, five samples of MOS transistors TR14 were broken when a voltage of about 250 to 350 v was applied to the high voltage terminal VH. On the other hand, with the resistor R1 being set to 10 Ω, two samples of MOS transistors TR14 were broken when VH was about 350 V and three samples of MOS transistors TR13 were broken when VH was about 450 V. According to the measurement by the present inventors, the voltages at which the MOS transistors TR13 and TR14 were broken greatly increased when the resistor R1 was set to a value of 10 to 20 Ω in the case where: the breakdown voltage of the pn junction under the gate insulation film was 30 V when the gate voltage of the MOS transistor TRI3 was 0 V; the thickness of the gate film was 5 x 10 -6 cm; the resistance of the substrate was 20 Ω; the breakdown voltage of the pn junction near the field insulation film was 27 V; the thickness of the gate film of the MOS transistor TR14 was 12 x 10 -5 cm; and the channel width (W)/channel length (L) was 100 µm/4 µm. Fig. 6 shows a semiconductor device which might be used in place of the MOS transistor TR14 shown in Fig. 4. This semiconductor device is constituted similarly to that shown in Fig. 4 except that the gate electrode 14 is removed. In this semiconductor device as well, the p-type substrate 3 and n + -type regions 11 and 12 form the base, emitter and collector of a bipolar transistor, respectively. Although the present invention has been described above with respect to the embodiments, the invention is not limited to only those embodiments. For example, in the foregoing embodiments, the case where a high voltage is applied to the high voltage terminal VH due to the static electricity has been described. However, the invention can be also applied to a semiconductor integrated circuit without such a high voltage terminal VH. Namely, even in the MOS transistor having the structure shown in Fig. 2, in which the operation voltage of 5 V instead of the high voltage of 20 V is supplied to the drain, there is a case where when this drain is disconnected from the power source, an abnormally high voltage is applied to this drain due to the static electricity. However, in this case also, the use of the protecting circuits as shown in Fig. 3 makes it possible to prevent a similar breakdown of the MOS transistor in the manner as described above.

Claims: A semiconductor integrated circuit comprising: first and second potential terminals; a first MOS transistor (TR13) having a current path connected between said first and second potential terminals; and a protective transistor circuit (TR14, R1) including a transistor device (TR14) having a current path with one end connected to said first potential terminal, and the other end of said current path being coupled to said second potential terminal, said transistor device (TR14) having a breakdown voltage lower than that of said first MOS transistor (TR13); characterized in that said transistor device (TR14) is a second MOS transistor having a source (11), a drain (12), a gate (14), and a gate insulation film (13) thicker than said first MOS transistor (TR13), and whose drain (12) is connected to the drain of said first MOS transistor (TR13); and said protective transistor circuit (TR14- R1) further comprises a resistive means (R1) connected between said second potential terminal and the gate (14) and source (11) of said transistor device (TR14). A semiconductor integrated circuit according to claim 1, characterized in that said transistor device (TR14) has a substrate (3) of one conductivity type and first and second semiconductor regions (11 and 12) of an opposite conductivity type formed in the surface area of said substrate (3), and said first and second semiconductor regions (11 and 12) are connected to the drain of said first MOS transistor (TR13) and said resistive Means (R1), respectively. A semiconductor integrated circuit according to claim 1 or 2, characterized in that said first MOS transistor (TR13) comprises: a substrate of one conductivity type; drain and source regions of an opposite conductivity type formed in the surface area of said substrate (3), said drain region including a first region and a second region having an impurity concentration lower than that of said first region; a gate insulation film formed on the partial area of said substrate between said source region and said second region of said drain region; and a gate electrode formed on said gate insulation film.

Inventors: ASANO, MASAMICHI C/O PATENT DIVISION, HARADA, HIROSHI C/O PATENT DIVISION, IWAHASHI, HIROSHI C/O PATENT DIVISION, SUMIHARA, HIDEKI C/O PATENT DIVISION, TANAKA, SHINICHI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: H01L27
IPC codes: H01L27, G11C16