INTEGRATED CIRCUIT HAVING A COMMON INPUT TERMINAL

Abstract: An improved integrated circuit of the type having a plural­ ity of circuit blocks to which a common external terminal is coupled. A switch is inserted between the external terminal and at least one of the circuit blocks. The switch is controlled in such manner that it is rendered conductive when the at least one circuit block necessitates to take the signal at the external terminal and non-conductive when the at least one circuit block does not need to take the signal at the external terminal therein.

Description: The present invention relates to an integrated circuit having a common input terminal for a plurality of circuit blocks receiving signals via the common input terminal. The integration density of integrated circuits has been increased and the number of elements and functional circuits fabricated in the same integrated circuit chip has become large. On the other hand, the number of external terminals provided in one integrated circuit chip has been limited in view of topographical layout of the chip and yields of production. Under such circumstance, it has been proposed that one external terminal is commonly utilized by two or more circuit blocks included in the same chip. For example, in the multi-strobe type dynamic memory in which row address signals and column signals are taken through the same set of address terminals in response to a row address strobe ( RAS ) and a column address strobe ( CAS ) respectively, the column address strobe is also used to control refresh operation, data outputting operation and serial column selecting operation. In this case, the column address strobe is applied to the circuit blocks for achieving the above operations. Therefore, the external terminal receiving the column address signal is directly connected to the inputs of the respective circuit blocks. However, according to the above technique, since the common external terminal is directly connected to a plurality of circuit blocks, the capacitance associated to the common external terminal is inevitably very large, resulting in low speed operations. Moreover, each of the circuit blocks is provided with a special control circuit which prevents the circuit block from being affected by unnecessary input through the common external terminal after conducting it relevant function. This has made the respective circuit blocks complicated. An integrated circuit according to the preamble part of claim 1 is disclosed in FR-A-2 533 738. This integrated circuit comprises a dynamic memory in which one of four drivers is connected to an input buffer through one of four gate circuits, wherein selection of the gate circuits is made in accordance with address signals. Therefore, once the state of the address signals is established, the connection between the input buffer and the drivers is determined so that control of the gates according to the states of the respective functional circuits to which input signals are selectively applied is not performed. It is therefore an object of the invention to provide an integrated circuit in which a plurality of circuit blocks share the same external terminal which can operate at high speed and which can be fabricated an highly integrated structure. This object is achieved by an integrated circuit as defined by claim 1. According to the invention at least one circuit block is selectively isolated from the external terminal, wherein the gates are controlled by the states of the respective functional circuits to which input signals are selectively applied therethrough and hence the effective load capacitance associated to the external terminal is significantly reduced. Moreover since the circuit block is selectively isolated from the external terminal and the circuit block is not sensitive to the signal at the external terminal depending on the states of the respective functional circuit the signal at the external terminal does not adversely effect the circuit block. Fig. 1 is schematic block diagram showing an integrated circuit according to the prior art; Fig. 2 is a schematic block diagram of an integrated circuit comprising transfer gates; Fig. 3 is a diagram showing waveforms in the circuit of Fig. 2; Fig. 4 is a schematic block diagram of an embodiment of the present invention; Fig. 5 is a diagram showing waveforms of the circuit of Fig. 4; and Fig. 6 is a circuit diagram showing one example of the latch completion detection circuit 44' in Fig. 4. Referring to Fig. 1, an integrated circuit according to the prior art is briefly explained. A plurality of circuit blocks 11 to 1 n are provided in an integrated circuit. The circuit blocks 11 to 1 n have different functions and include input transistors Q₁ to Q n . To the gates of the input transistors Q₁ to Q n an external terminal 21 receiving a signal ψ is commonly connected via an input protecting circuit 22 composed of a resistor R₁ and a transistor Q 0 . Each of the circuit blocks 11 to 1 n is adapted to be controlled by the logic pattern of the signal ψ solely or with other signals such as  0 . For example, the circuit block 11 is enabled in response to a high level of the signal ψ while the circuit block 12 is enabled in response to a low level when the signal  0 is at high. Thus, the signal ψ controls the respective circuit blocks in their own ways. However, according to the prior art, the signal ψ is always applied to the inputs T₁ to T n of the circuit blocks even when some of the circuit blocks do not need the signal ψ temporarily. Thus, the capacitance associated to a node K to which the output end of the input protecting circuit 22 is very large. Therefore, the propagation time of the signal ψ from the terminal 21 to the respective inputs T₁ to T n of the circuit blocks is very large. This means that effective operation speeds of the respective circuit blocks are slow. Moreover, in order to drive the large capacitance associated to the node K, the signal ψ is required to have small internal impedance. Namely, the generator (not shown) of the signal ψ must have the large driving capability. Furthermore, since the signal ψ is always applied to the respective circuit blocks, each of the circuit blocks has to be provided with circuit means for rendering the internal circuit (not shown) included therein insensitive to the operation of the input transistor when the circuit block do not need the signal ψ. Thus, the circuit structures of the circuit blocks have become complicated. Referring to Fig. 2, the integrated circuit comprising transfer gates is described. Inputs T 1a to T na of the circuit blocks 11' to 1 n' are connected to the output node K of the input protecting circuit 22 via transfer gate transistors Q S1 to Q Sn' respectively, as illustrated. The transfer gate transistors Q S1 to Q Sn are controlled by control signals  1a to  na . The signals  1a to  na are generated by detection circuits D₁₁ to D 1n provided for the circuit blocks 11' to 1 n' , respectively. The detection circuit D₁₁ monitors the operating state of the circuit block 11' and sets the control signal  1a at high level to render the transistor Q S1 conductive when the circuit block needs to take the signal ψ therein while the detection circuit D₁₁ sets the control signal  1a at low level to render the transistor Q S1 non-conductive when the circuit block 11' does not need to receive the signal ψ . Other detection circuits D₁₂ to D 1n control the transfer gate transistors Q S2 to Q Sn in response to the states of the circuit blocks 12' to 1 n' , respectively in the same manner. One example of operation of the circuit shown in Fig. 2 is explained with reference to Fig. 3. In the followings, by way of example, the explanation is made on the circuit blocks 11' and 1 n' . At a time point t₁, the signal ψ changes from high level to low level while a clock signal ₁₁ applied to the circuit block 11' is high. In response to this states of the signals, the circuit block 11' starts its operation such as storing data or the like over the subsequent period T₁ without necessitating the signals ψ . Therefore, the detection circuit D₁₁ produces a low level of the signal  1a thereby to render the transistor Q S1 non-conductive so that the input T 1a is kept low during the period T₁. While, a clock signal ₁₂ applied to the circuit block 12' changes from low level to high level so that the circuit block 12' enters into its operating mode over the subsequent period T₂. During this period T₂, the detection circuit D₁₂ sets the control signal  2a high so that the transfer gate transistor Q S2 is rendered conductive. Accordingly, the signal ψ is transmitted to the input T 2a of the circuit block 12' during this period T₂. Thus, the circuit block 12' takes the signal ψ in and performs operations based on the signal ψ during the period T₂. While, the waveform of the signal ψ during the period does not affect the circuit block 11' because the transfer gate transistor Q S1 is not conducting. Thus, the signal ψ is rapidly transmitted to the input T 2a during the period T₂. At a time point t₃, the clock signal ₁₂ changes from high level to low level so that the circuit block 12' enters into non-operating state. Then, in response to this, the detection circuit D₁₂ changes the control signal  2a from high level to low level thereby to isolate the input T 2a of the circuit block 12' from the input terminal 22. Then, at a time point t₄, the signal ψ changes from low level to high level under the low level of the clock signal ₁₁. Then, in response to this, the detection circuit D₁₁ sets the signal  1a high level to render the transfer gate transistor Q S1 conductive. Thus, the circuit block 11' is rendered responsive to the signal ψ . As described above, the signal ψ is transmitted only to the circuit block or blocks which necessitate to take the signal ψ therein, and hence the load capacitance associated to the terminal for receiving the signal ψ is remarkably reduced. Referring to Figs. 4 and 5, a detailed embodiment of the present invention is described. This embodiment is the case where the principle according to Fig. 2 is applied to the multi-strobe type dynamic RAM. Fig. 4. shows a block diagram of the multi-strobe type RAM to which the present invention is applied. A memory cell array 43 includes a plurality of dynamic type memory cells MC each coupled to one of word lines WL and one of bit lines BL and sense amplifiers (not shown). A row address signal latch circuit 41 is connected to a set of address input terminals A₁ to A n and latches the signals at the terminals A₁ to A n in response to a control signal RAS 1 which is generated by a first row timing signal generator 49 receiving a row address strobe RAS . A row decoder 42 is coupled to the word lines and selects one of them in response to a control signal RAS 2 which is generated by a second row timing signal generator 50. A timing signal RAS 3 enables the sense amplifiers in the array. The respective bit lines BL are inputted to a column selection circuit 45 and the selection circuit 45 selectively connects the bit lines BL to a bus line IB which is coupled to an input/output circuit 48. The selection circuit 45 is controlled by a shift register 46 whose initial state is determined by column address decoder 47. The shift register 46 performs shift operations in response to a series of shift pulses  SR generated by a nibble mode control circuit 52. The column decoder 47 receives the row address signals latched by a row address latch circuit 44. An internal refresh control circuit 51 introduces self-refreshing operation into the memory when the CAS is first changed to low level and thereafter the RAS is changed to low level. The internal refresh control circuit 51 produces a chain of refresh pulses  REF which are applied to a refresh address counter 54 and the second timing signal generator 50. When the memory is in the self-refreshing mode, the address counter 54 provides the row decoder 42 with refresh address signal and the generator 50 generates the signals RAS 2 and RAS 3 in response to  REF . A control circuit 53 produces a control signal  OUT for enabling the circuit 48. In this arrangement the CAS is applied to the column latch circuit 44 via a transfer gate transistor Q₅₁ and an inverter composed of transistors Q₅₃ and Q₅₄. Also the CAS is applied to the refresh control circuit 51 via a transfer gate transistor Q₅₂ and an inverter composed of transistors Q₅₇ and Q₅₈. While, the CAS is applied to the control circuits 52 and 53 via an inverter composed of transistors Q₆₁ and Q₆₂ and an inverter composed of transistors Q₆₃ and Q₆₄, respectively. The transfer gate transistor Q₅₁ is located at the location close to the terminal CAS and the transfer gate transistor Q₅₂ is also located at the location close to the CAS terminal. Thus, the major wiring capacitance associated to the wiring connected to the gate of the transistor Q₅₃ and the major capacitance associated to the wiring connected to the gate of the transistor Q₅₇ are left behind the transfer gate transistors Q₅₁ and Q₅₂, respectively. Accordingly such major capacitances can be operatively isolated from the CAS terminal. The transfer gate transistor Q₅₁ is controlled by a latch completion detection circuit 44' and an inverter composed of the transistor Q₅₅ and Q₅₆. The circuit 44' generates a latch completion signal  LE when the latch circuit 44 completes its latching operation of column address signals. One example of the detection circuit 44' is shown in Fig. 6. In Fig. 6 one-bit structure of the column latch circuit 44 is shown. An address terminal A i is inputted to an inverter composed of transistors Q₆₁ and Q₆₂. Transistors Q₆₅ to Q₆₈ form a clocked type flip-flop circuit for holding the column address signal. The transistors Q₆₅ and Q₆₇ are of a depletion type and serve as gated-load in response to the signal RASO. Transfer gate transistors Q₆₃ and Q₆₄ transmit true and complementary signals of A i to the flip-flop in response to a signal  L generated by inverting CAS by the inverters of Q₅₃ and Q₅₄. Here an exclusive OR gate GX having inputs receiving true and complementary signals A i and A i is provided. The gate GX detects that the flip-flop completes its latching operation of A i and A i . Thus the transfer gate transistor Q₅₁ is rendered conductive before the latching of the column address signals and non-conductive after the latching of the column address signals. The transfer gate transistor Q₅₂ is controlled by an output of an inverter composed of Q₅₉ and Q₆₀ receiving a signal  CBR which is generated by a refresh detection circuit 51' when the operation of the memory entered into the self-refreshing mode. Fig. 5 shows waveforms showing operations of the memory of Fig. 4. At time point t₁, RAS changes from high level to low level. In response to this change of RAS , the signal RASO applied to the circuits 51 and 52 changes from low level to high level. Then, CAS changes high level to low level at time point t₂ so that the column latch circuit commences latch operation. In this instance, CAS is applied to the circuit 44 via the conductive transfer gate Q₅₁ because  LE is at low. Then at time point t₃, the signal  LE becomes high to render the transistor Q₅₁ non-conductive and the signal  OUT is once activated to achieve a first access operation. Then CAS is repeatedly changed between high and low levels from time point t₄ so that the memory into the nibble mode in which the signals  SR and  OUT are repeatedly generated in synchronism with the change of CAS . Thus, data at a plurality of bit lines are sequentially accessed by the shift register 46. Thus, the nibble mode operation is achieved. Then, operation is changed to the self-refreshing operation. Namely, CAS is changed from high level to low level at time point t₇ when RAS is at high. In response to this the control circuit 51, 51' introduces the self-refreshing mode into the memory and generates a high level of  CBR to render the transistor Q₅₂ non-conductive. Then, in response to change of RAS to low level, the refresh clock  REF is repeatedly generated to achieve self-refresh operations. As has been described above, by way of examples the present invention is advantageous in reduction of the load capacitance associated to a common external terminal.

Claims: An integrated circuit comprising a memory array (43) of memory cells arranged in rows and columns; a first terminal receiving a first control signal ( RAS ); a second terminal for receiving a second control signal ( CAS ); first means (41) responsive to said first control signal for holding row address signals; second means (42) for selecting the rows of said memory array; third means responsive to said first and second control signals for holding column address signals, said third means including a latch circuit (44) for holding column address signals, first connecting means (Q51, 44', Q55, Q56) coupled between said second terminal and a control input of said latch circuit (44); a refresh address counter (54) for operatively producing refresh address information; and a refresh control circuit (51, 51') responsive to said first and second control signals for enabling said refresh address counter, said refresh control circuit including, a refresh introducing circuit (51) and second connecting means (Q52, 51') coupled between said second terminal and said refresh introducing circuit, characterized in that said first connecting means includes a first switch (Q51) coupled between said second terminal and said control input of said latch circuit (44), means (44') coupled to said latch circuit for generating a latch completion signal (LE), and means (Q55, Q56) responsive to said latch completion signal for rendering said first switch non-conducting; and said second connecting means includes a second switch (Q52) coupled between said second terminal and said refresh introducing circuit (51), a refresh state detection circuit (51') coupled to said refresh introducing circuit (51) for detecting that said refresh introducing circuit introduces refresh mode of said refresh counter and means (Q59, Q6O) responsive to said refresh state detection circuit (51') for controlling said second switch. The integrated circuit, according to claim 1, characterized in that each of said first and second switches includes a field effect transistor.

Inventors: FUKUZO, YUKIO, INOUE, YASUKAZU
Applicants: NEC CORPORATION
Application year: 1985
Main classification: G11C5
IPC codes: G11C11, H03K17, G11C7, G11C5