CMOS TYPE INPUT-OUTPUT CIRCUIT

Abstract: In a CMOS type input-output circuit having an input control circuit, an output control circuit, a buffer circuit, a CMOS output buffer circuit and an input buffer circuit, said input-output circuit being capable of bidirectional transmis­ sion of information between a data bus and an I/O port, improvements on the control circuit are embodied by selecting a gate circuit in the input control circuit correspond­ ing to that in the output control circuit. The output control circuit is connected to the input control circuit and the CMOS output buffer circuit. The CMOS output buffer circuit is connected to the input control circuit and the I/O port. Upon inputting a signal to both control circuit, the output control circuit floats the CMOS output buffer circuit; the input control circuit outputs a level fixing signal regardless of a logic level of the I/O port.

Description: This invention relates to a data input-output circuit, and more particularly to a data input-output circuit, suitable for microprocessors, for controlling a bidirectional transmission of information between a data bus and an I/O port comprising an output control circuit, an external control circuit supplying control signals respectively composed of first and second logic levels and an output buffer circuit connected to said output control circuit, said I/O port transmitting said information from said output control circuit to said I/O port when the control signal received at said output control circuit is the first logic level and said output buffer circuit being capable of being floated. CMOS type input-output circuits are used in CMOS microprocessors or CMOS microcomputers which consume extremely little electrical power. The CMOS type input-output circuit is capable of bidirectional transmission of information between an I/O port and an internal data bus in both ways. The CMOS type input-output circuit, in general, has a CMOS output buffer circuit connected with the I/O port, a CMOS input buffer which receives signals from the I/O port and expands noise margins, and a circuit which receives signals from the CMOS input buffer and selects some of them and transfers selected signals to the internal data bus. An example of a conventional input-output circuit including one or more CMOS output buffers is described in "MICRO-CONTROLLOR HANDBOOK (INTEL,1983 ed.,Page 10-1 and 10-2)". With such conventional input-output circuits, however, it is impossible to have the I/O port floated. Accordingly, the logic level of an external circuit should be made to correspond with the output logic level from the I/O port, before these circuits are powered down. In power down mode, these CMOS type input-output circuits have been desired to electrically separate the internal data bus from the I/O port in order to avoid the effects of the external circuits. In this case, however, this causes a problem to consume a high electrical power. If the I/O port is turned off or has high input impedance, the I/O port is floated and PMOS and NMOS in the CMOS input buffer are simultaneously turned on. Therefore these MOS circuits consume electrical power in spite of the power down mode. In addition, the floating of the I/O port can be prevented if a pull-up or pull-down resistor is connected with the I/O port and the voltage of the input buffer is fixed at high or low level. But the resistor attached consumes electrical power. From the article "6805-uC I/O"of J. Thomas in Electrical Design News, Vol 26, No. 1, May 1981, page 107, Boston, MA, US, is known to have an output control circuit and an output buffer circuit, said buffer circuit being capable of being floated. In the known circuit a data direction register DDR is used which allows the bidrectional transmission of the information either from the I/O pin to an internal data bus or from the internal data bus to the I/O pin. Such a circuit, however, consumes much electrical power. The present invention has the object to provide a CMOS type input-output circuit which consumes very little electrical power in power down mode of a microprocessor and which requires no pull-up or pull-down resistors preventing an I/O port from floating. This object is solved by the circuit described in claim 1. Further advantageous embodiments of the invention are described in the subclaims 2 to 7. In data output mode, the output control circuit receives information from the buffer circuit which temporarily stores information on the data bus, and sends the information to the I/O port via the CMOS output buffer circuit. In data input mode, the input control circuit receives the information from the I/O port and sends it to the data bus via the input buffer circuit. In power down mode, the output control circuit and the input control circuit receive the control signals, and the output control circuit makes the CMOS output buffer circuit floated, and the input control circuit produces a level fixing output signal, which is "H" or "L" level, regardles of a logic level of the I/O port. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a block diagram of a CMOS type input-output circuit embodying the invention. Fig.2 is a connection diagram of a plurality of a CMOS type input-output circuit. Fig.3 is a waveform diagram to explain the operation in the output mode of the circuit of Fig.1. Fig.4 is a waveform diagram to explain the operation in the input mode of the circuit of Fig.1. Fig.5 is a waveform diagram to explain the operation in the power down mode of the circuit of Fig.1. Fig.6 is a circuit diagram of the input buffer circuit shown in Fig.1. Fig.7, and Fig.8 are circuit diagrams of the input control circuit shown in Fig.1. DESCRIPTION OF THE PREFERRED EMBODIMENT In Fig.2, each of one terminals of CMOS type input-output control circuits 102, 104, 106, 108 is respectively connected to bit lines B0, B1, B2, B3 of a data bus, and each of another terminals is respectively connected to I/O ports 1, 2, 3, 4. The CMOS circuits 102, 104, 106, 108 receive selectively "write" signal W,"read" signal R or "control" signal C. The write signal W causes the CMOS type input-output circuits 102, 104, 106, 108 to transmit information on the data bus 100 to the I/O port. The read signal R causes the CMOS type input-output circuits 102, 104, 106, 108 to transmit information on the I/O ports to the data bus 100. At power down mode of the microprocessor, the control signal C causes the I/O ports to float, and causes an output level of an internal control circuit to fix at "L" or "H". The internal control circuit does not turn on or off despite a fluctuation of the output level of the I/O ports. Accordingly, the CMOS type input-output circuits 102, 104, 106, 108 only consume very low electrical power. Fig.1 shows a preferred embodiment of such a CMOS type input-output circuit in accordance with the present invention. The CMOS type input-output circuit 102 comprises a latch circuit 200, a CMOS output buffer circuit 202, an output control circuit 204, an input buffer circuit 206, and an input control circuit 208. The latch circuit 200 temporarily stores a signal of the bit line B3 in the data bus 100 when receiving the write signal W. The CMOS output buffer circuit 202 comprises PMOS and NMOS transistors, the output of which is connected to the I/O port 1. The output control circuit 204 transmits the output signal of the latch circuit 200 to the output buffer circuit 202 and turns off the PMOS and NMOS transistors when receiving the control signal C. The input buffer circuit 206 transmits the signal of the I/O port 1 to the bit line B3 when receiving the read signal R. The input control circuit 208 transmits the signal of the I/O port 1 to the input buffer circuit 206 and disconnects electrically the I/O port 1 from the input control circuit 208 when receiving the control signal C. In detail,the latch circuit 200 is a data type flip-flop circuit, and the output control circuit 204 comprises, for example, a CMOS inverter 210, CMOS OR gate circuit 212 and CMOS NOR gate circuit 214. Fig.6 and Fig.7 show detailed circuit diagrams of the input circuits 206 and 208. The input buffer circuit 206 consists of two NMOS transistors connected in series shown in Fig.6. The input control circuit 208, for example, consists of a NMOS gate circuit 208 and is constructed with a CMOS circuit shown in Fig.7. In following ,the operation of the CMOS type input-output circuit 102 in accordance with the invention will be described with references to the timing charts shown in Fig.3 to Fig.5: (1) Data Output Mode Referring to Fig.3, the data output mode is described of transmitting a data of the bit line B3 of the data bus 100 to the I/O port 1. During a period of state S1, all logic levels of the bit line B3, the write signal W, the read signal R, control signal C and the I/O port 1 are assumed to be "L". During the period of state S2, the logic level of the bit line B3 turns to "H" level. When the latch circuit 200 receives the write signal W for transmitting the "H" level signal of the bit line B3 to the I/O port 1, the latch circuit 200 holds the "H" level signal of the bit line B3 and outputs a "H" level signal to the output control circuit 204. At the same time, because of the control signal C being holded as "L" level, the output control circuit 204 supplies "L" level signal to each of the PMOS and NMOS transistors of the output buffer circuit 202. Since the output signal of the output buffer circuit 202 turns to "H" level, "H" level signal of the bit line B3 is transmitted to the I/O port 1. (2) Data Input Mode Referring to Fig.4, the data input mode is described of transmitting a data of the I/O port 1 to the bit line B3. During the period of the state S1, all logic levels of the I/O port 1, the write signal W, the read signal R and the control signal C are assumed to be "L" level : the logic level of the bit line B3 and the input buffer circuit 206 are assumed to be "H" level. Because of the control signal C being "L" level, the input control circuit 208 outputs an "H" level signal which inverts the "L" level signal being applied to the I/O port to "H" level. During the period of state S2, when the "H" level read signal R is inputted the input buffer circuit 206 outputs a "L" level signal to the bit line B3. The "L" level signal may be stored, in for example, a memory in the microprocessor. Accordingly, when the "L" level read signal R is inputted during the period of state S3 the bit line B3 becomes "H" level. (3) Power Down Mode Referring to Fig.5, the operation of the CMOS type input-output circuit 102 in power down mode is described. During the period of state S1, the write signal W, the read signal R and control signal C are all assumed to be "L" logic level; the logic level of the bit line B3 is assumed to be "H" level and the logic level of the I/O port 1 is assumed to be "H" or "L" level. During the period of state S2, the "H" level control signal C is transmitted from a register(not shown) in a microprocessor or a microcomputer to the output control circuit 204 and the input control circuit 208. Then, the OR gate 212 and the NOR gate 214 in the output control circuit 204 outputs "H" and "L" level signals respectively to the PMOS and the NMOS transistors in the output buffer circuit 202 regardless of the logic level of the latch circuit 200. Since both PMOS and NMOS transistors in the output buffer circuit 202 turn off, the I/O port 1 becomes floating. Whereas, the output signal of the input control circuit 208 becomes "L" level regardless of output level of the I/O port 1. The input control circuit 208 can be constructed as is a CMOS NOR gate as shown in Fig.7 for example. Either of the PMOS transistors connected in series is fixed to be a cut-off mode, so that a power supply terminal Vdd in the input control circuit 208 is not grounded regardless of the voltage deviation of I/O port 1. The use of a CMOS NOR gate as shown in FIG.8 having a hysteresis characteristic as the input control circuit 208, provides high noise margins, so that more stable characteristic against fluctuation of the logic level of the I/O port in normal operation mode can be obtained

Claims: A data input-output circuit for bidirectional transmission of information between a data bus (B3) and an I/O port (1) comprising: an output control circuit (204) receiving input from said data bus (B3), receiving a first control signal from an external source, said first control signal having one of two logic levels and said output control circuit (204) also being connected to an output buffer circuit (202); said output buffer circuit (202) being further connected to said I/O port (1) with said output control circuit (204) and said output buffer circuit (202) being so arranged that when said first control signal is at a first logic level, said output buffer circuit supplies the signal received from the data bus (B3) to said I/O port (1) and when said first control signal is at its other logic level, the output of the output buffer circuit is floated, that is, it is electrically isolated from source voltage V DD and from ground; said input-output circuit further comprising a second circuit connecting said I/O port (1) to said data bus (B3), said second circuit including an input control circuit (208, 206) for the conveyance of the signal level at said I/O port (1) to said data bus (B3), characterised in that said output buffer circuit (202) is of CMOS type, consisting of an N-type and a P-type transistor connected in series with its output being taken from between said transistors and with the gate voltages being supplied by the outputs of said output control circuit (204), and further characterised in that said input control circuit (206, 208) has as inputs firstly the signal level on I/O port (1), secondly said first control signal and thirdly a second external control signal also being at one of two logic levels, so that when said second external control signal is at a first logic level, the output from said input control circuit (206, 208) to said data bus (B3) is floated, when said second external control signal is at its second logic level and said first control signal is at its first logic level, a fixed signal is supplied to the data bus (B3); and when both external control signals are at their respective second logic levels, the signal at said I/O port (1) is conveyed to the data bus (B3). Circuit according to claim 1 wherein said input from said data bus (B3) is supplied to said output control circuit (204) via a buffer circuit (200) for temporarily storing the information from said bus and supplying said information to said output control circuit (204). Circuit according to claims 1 or 2 wherein said CMOS output buffer circuit (202) comprises a PMOS transistor and an NMOS transistor connected in series between a supply voltage (V DD ) and an earth. Circuit according to one of claims 1 to 3 wherein said PMOS transistor further has a source connected to said supply voltage (V DD ) and has a drain connected to said I/O port (1), said NMOS transistor further has a source connected to said ground and has a drain connected to said I/O port (1). Circuit according to claims 3 or 4 wherein said output control circuit (204) comprises an OR gate circuit (212) having one inverted input (210) to receive information from said buffer circuit (200) and having an input to receive said control signals from said external source for supplying information to the gate of said PMOS transistor, and a NOR gate circuit (214) having two inputs to receive information from said buffer circuit (200) and to receive said control signals from said external source for supplying information to the gate of said NMOS transistor. Circuit according to claims 3 or 4 wherein said output control circuit (204) comprises an AND gate circuit having one inverted input to receive information from said buffer circuit (200) and another input to receive said control signals from said external source for supplying information to the gate of said NMOS transistor, and a NAND gate circuit having two inputs to receive information from said buffer circuit (200) and to receive said control signals from said external control source for supplying information to the gate of said PMOS transistor. Circuit according to one of claims 1 to 6 wherein said input control circuit (208) comprises a NOR gate circuit (218). Circuit according to one of claims 1 to 6 wherein said input control circuit (208) comprises an AND gate circuit.

Inventors: MIYAZAKI, KAZUHIKO, YOKOUCHI, HIROSHI
Applicants: OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1985
Main classification: G06F13
IPC codes: G06F15, G06F3, G06F13, H03K5, H03K19, G11C11