SPLIT GATE PREPROCESSOR

Abstract: Successive MLS signals are converted into correspond­ ing digital signals. The centroids of the digital signals are determined at two different levels by a digital processor. The centroids for each signal are averaged and the period of time between centroids is determined.

Description: The invention generally relates to receivers for receiving scanning signals and, in particular, to an apparatus which receives signals having a predetermined time varying format such as a microwave landing system (MLS) receiver for receiving scanning signals provided by an MLS ground system. The International Civil Aviation Organization (ICAO) has adopted a time reference scanning beam (TRSB) technique as the standard for civil microwave landing systems. MLS ground systems provide elevation (EL) and azimuth (AZ) scanning beams, each including a TO scan followed by a FRO scan, defining the area of coverage of the ground system. An MLS receiver located in an aircraft receives the EL scan and AZ scan and is able to determine the angular displacement of the MLS receiver in the aircraft with respect to the ground system. To do this, it is necessary to establish the centroids of the spatially swept EL and AZ scanning beams because the azimuth and elevation angles are a function of the time difference between the TO and FRO scans of each beam. It is an object of this invention to provide a receiver with a preprocessor for detecting the centroids of spatially swept scanning beams. EP-A-117662 describes apparatus for receiving recurring to and fro scanning signals comprising: (a) an antenna for receiving the scanning signals; (b) a converter for converting the received signals into intermediate frequency signals; (c) a detector for detecting the intermediate frequency signals; (d) an analog-to-digital converter for converting the detected intermediate frequency signals into digital signals; (e) a digital peak detector for detecting the peak amplitudes of the digital signals; and (f) a split gate processor. The present invention is characterized in that: (g) said split gate processor is operable to determine for each of the to and fro signals the respective first, second and third time periods for which the amplitude of the respective digital signal is greater than respective first, second and third predetermined levels below said detected peak amplitude; and (h) processing means is provided for averaging for each of the to and fro signals the mid points of said time periods to provide a signal representative of the centroid of the respective digital signals, whereby the time duration between the two centroid signals permits determination of the angular bearing of the apparatus relative to the source of the recurring to and fro scanning signals. An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a block diagram of an MLS receiver according to the invention. Figure 2 is a block diagram of a microprocessor controlled automatic gain control for a receiver such as the MLS receiver illustrated in Figure 1. Figure 3 is a block diagram illustrating a split gate processor as part of a digital processor of an MLS receiver as shown in Figure 1. Figure 4 is a block diagram of the split gate processor. Figure 5a and 5b are graphs illustrating the operation of the split gate processor of Figure 4. As illustrated in figure 1, the MLS receiver is provided with an antenna switch 1 which connects either the forward antenna or the rear antenna to front end 2. A control unit (not shown) provides channel selection information to frequency synthesizer 3 which, in turn, provides the appropriate reference frequency to front end 2 for down conversion of the received radio frequency (RF) signal to an intermediate frequency (IF). The control unit also provides power "on" information to power supply 4 which supplies voltages to the various components of the receiver. MLS receivers require an IF amplifier having a dynamic range which exceeds 80dB. In order to achieve such a dynamic range, the receiver according to figure 1 includes an IF amplifier chain including a first IF amplifier 5 followed by a second IF amplifier consisting of linear IF amplifier 6 and logarithmic IF amplifier 7. The chain is followed by a third IF amplifier 8. Linear IF amplifier 6 and third IF amplifier 8 are provided with local oscillator (LO) frequencies by synthesizer 3 depending on the channel selection. This chain of amplifiers is designed with a linear-logarithmic response so that the logarithmic IF amplifier properties may be used without the difficulties attendant with an amplifier having a particular characteristic over the entire range. For small signals, linear amplifiers 5 and 6 provide sufficient gain for the logarithmic IF amplifier 7 to operate within its range. As the signal level increases beyond an established level on an overall response curve of logarithmic IF amplifier 7, an AGC voltage is applied to linear IF amplifier 6 via line 9 to decrease the total gain of the linear amplifier so that logarithmic IF amplifier 7 is operating within its range. When the signal level provided by linear IF amplifier 6 decreases below an established level on the overall response curve of logarithmic IF amplifier 7, the AGC voltage remains constant and the gain of linear IF amplifier 6 is at a maximum. The result is that the first and linear IF amplifiers 5 and 6, respectively, maintain operation within the logarithmic response of the receiver characteristic as defined by logarithmic IF amplifier 7. According to the ICAO standard, the scanning signals detected by the receiver are encoded with differential phase shift keying (DPSK) data. The output of third IF amplifier 8 is provided to DPSK demodulator 10 which is followed by DPSK decoder 11 for demodulating and decoding the data provided to input/output 12. Localizer and glide slope select information from the control unit (not shown) along with the decoded data are provided to the input/output 12 which controls antenna switch 1 and the deviation or "flag" indicators of the receiver. Input/output 12 also provides digital information to the control unit and provides control information to digital processor 13. Logarithmic video information provided by logarithmic IF amplifier 7 is also provided to envelope processor 14. Since the receiver operates in a time division multiplexed mode in which the relative amplitudes of successive azimuth and elevation signals of interest may vary greatly but are predictable based on previously received signals, the previously received amplitude levels of the azimuth and elevation signals are stored for use in controlling the gain of linear IF amplifier 6. This allows the appropriate AGC voltage to be applied via line 9 prior to the anticipated detection of each angle function. Digital microprocessor 13 accomplishes this control. Figure 2 illustrates in detail the portions in digital processor 13 which achieve this result. The required AGC level is determined by noteing the peak amplitude of the received signal during each AZ and EL scan. The past several peaks corresponding to each beam scan, i.e. azimuth or elevation, are averaged after the received signal has been digitized. The appropriate AGC voltage is then selected and applied via line 9 to second IF amplifier 6. In the acquisition phase, when the signal level may be expected to deviate considerably from the desired level, the AGC correction is made gradually over several beam scans. When no signal is being received, the IF gain of linear IF amplifier 6 is fixed at a maximum by the supplied AGC voltage. It remains at a maximum as a beam is sensed until a first received signal has been decoded by decoder 11. At that time, the appropriate AGC voltage based on the previous signal strength, i.e. the second received signal strength, is applied to linear IF amplifier 6 so that the amplifier gain is established prior to the commencement of the angle scan. The IF gain remains unchanged until a second received signal has been decoded. In particular, as shown in figure 2, the logarithmic video information provided by logarithmic amplifier 7 is provided to envelope detector (processor) 14. The resulting detected signal is digitized by analog-to-digital converter 15 and this digitized information is provided to digital peak detector 16. Central processing unit 17 of digital microprocessor 13 controls switch 21 based on control information provided by input/output 12. During each "EL" scan period, switch 21 is in the A position so that the digital peak information detected by detector 16 is provided to EL averager 19. During the "AZ" scan period, CPU 17 places switch 21 in the B position so that the digital peak information for the received AZ scan period as detected by detector 16, is provided to AZ averager 20. The average peak amplitude of the elevation and azimuth scans is provided to CPU 17 which, in turn, determines the AGC voltage necessary to maintain operation of logarithmic amplifier 7 within the range of its logarithmic characteristic. CPU 17 provides a digital signal representing the required AGC voltage to digital-to-analog converter 18 which converts the digital signal into an analog AGC voltage for application to the control input of linear IF amplifier 6. The receiver may also be provided with a test generator 31, as shown in Figure 1, which is operated by input/output 12 in response to a test request from the control unit. Test generator 31 provides predetermined IF signals to the first IF amplifier 5 for initiating the test. Digital microprocessor 13 also provides digital data and clock information to input/output 12 and track gate information to envelope processor 14. Envelope processor 14 also provides split gate information to digital processor 13, and DPSK decoder 11 provides identification information to digital processor 13. Figure 3 illustrates in block diagram form the portions of digital microprocessor 13 which are associated with split gate processor 100 according to the invention. Incoming data is demodulated by DPSK demodulator 10 and decoded by Barker synchronization correlator 11. The demodulated data is provided to input/output 12 and the correlated data provides identification information to CPU 17 as well as clock information to real time clock 20. Log video information is converted to digital information by analog-to-digital converter 15 and is stored in first-in-first out (FIFO) memory 41 before processing by split gate processor 100. In a preferred environment in which multipath and other distortion effects are not present, it is possible to enable a counter when an incoming signal rises above a predetermined value below the peak amplitude of the signal. The counter may then be stopped when the amplitude falls below the same level on the other side of the peak. The centroid is then found by determining from the counter the time between rise and fall and relating it to a reference time. This is known as a dwell gate processing. An incoming signal which is not affected by multipath as illustrated in Figure 5a may be analyzed in this way. However, when the shape of the received signal within a dwell gate is distorted by a multipath return, as illustrated in Figure 5b, the apparent centroid is skewed from the true value. In order to minimize error due to multipath, the processor analyzes the wave shape of the received signal. One way to accomplish this analysis is to establish a number of dwell gates at different levels below the peak. In this manner, the centroid is determined by observing the time intervals at representative levels of the signal. Generally, three levels are sufficient to define the centroid effectively. This is known as a split gate processor. In order to fully understand the function of split gate processor 100 as illustrated in figure 4, it is necessary to describe the technique used in establishing the thresholds and determining the amplitudes of an incoming scanning signal. The analog detected signal is obtained by processing the incoming scanning signal through a linear/logarithmic amplifier chain as illustrated in figure 1 so that the output amplitude is maintained within the limits of the logarithmic transfer function. With such a transfer function, an incremental difference in the input signal is represented by a fixed level at the output at any point within the dynamic range of the system. As illustrated in figure 4, the received signal is digitized by the A/D converter 15 and the results are stored in FIFO memory 41. The peak of the received signal is determined by digital peak detector 101. The peak information is provided to AGC switch 21 for averaging and to threshold detectors 102, 103 and 104. The digitized signal is delayed by delay 120 to allow peak detector 101 to complete its detection cycle and provide the detected information to threshold detectors 102, 103, and 104. The digitized, delayed signal is then provided to the threshold detectors 102, 103, 104 which respectively examine the delayed signal for points 5db, 3db, and 1db below the peak by subtracting the respective numbers representing those relationships from the peak value. It is possible when performing these measurements, since each measurement is being performed in real time, to determine when the 5db point is acquired on the rise of the pulse and when it appears again at the decay. When acquisition is identified, a counter is enabled, and the rise times are marked. The corresponding delay times are similarly noted. In particular, threshold detector 102 detects amplitudes of the delayed, digitized signal which are 1db below the peak detected by digital peak detector 101. When a signal amplitude of 1db below the peak is detected, counter 105 is enabled and CPU 17 is signaled via control line to store the time at which counter 105 was enabled. When the signal is again detected on the decay at 1db below the peak, detector 102 disables counter 105. The total count from counter 105 indicates the time between the 1db below peak levels. Referring to figure 5a, counter 105 would be enabled at time t₃ and disabled at time t4 with CPU 17 storing time t₃ and counter 105 storing a count representing the total time between t₃ and t₄. Referring to figure 5b illustrating the multipath case, counter 105 would be enabled at time t₁₁ and disabled at time t₁₂ with CPU 17 storing the enabling time t₁₁. Thereafter, CPU 17 performs the necessary calculations to derive the midpoint in time of the period detected at the 1db below peak level. Eventually, CPU 17 averages the separate times to determine the result of the information provided by all three counters to determine the centroid of the received signal. Threshold detector 103 detects amplitudes of the delayed, digitized signal which are 3db below the peak detected by digital peak detector 101. When a signal amplitude of 3db below the peak is detected, counter 106 is enabled and CPU 17 is signaled via a control line to store the time at which counter 106 was enabled. When the signal is again detected on the decay at 3db below the peak, detector 103 disables counter 106. The total count from counter 106 indicates the time between the 3db below peak levels. Referring to figure 5a, counter 106 would be enabled at time t₂ and disabled at time t₅ with CPU 17 storing time t₂ and counter 106 storing a count representing the total time between t₂ and t₅. Referring to figure 5b illustrating the multipath case, counter 106 would be enabled at times t₈ and t₁₀ and disabled at times t₉ and t₁₃, respectively, with CPU 17 storing the enabling times t₈ and t₁₀. Thereafter, CPU 17 performs the necessary calculations to derive the midpoints in time of the periods detected at the 3db below peak levels. Preferably, CPU 17 is programmed with an algorithm which rejects the extra crossings observed at any level. The result of such rejection is that the total error due to multipath distortion is minimized by the averaging process. In particular, CPU 17 may be programmed to reject crossings t₈ and t₉ in the 3db below peak level. Based on such rejection, CPU 17 performs the necessary calculations to derive the midpoint in time of the unrejected period t₁₀ - t₁₃ detected at the 3db below peak level. Similarly, all levels below the detected level, i.e. the 5 db below peak level, would be adjusted by subtracting the period between the rejected crossings. Threshold detector 104 detects amplitudes of the delayed, digitized signal which are 5db below the peak detected by digital peak detector 101. When a signal amplitude of 5db below the peak is detected, counter 107 is enabled and CPU 17 is signaled via a control line to store the time at which counter 107 was enabled. When the signal is again detected on the decay at 5db below the peak, detector 104 disables counter 107. The total count from counter 107 indicates the time between the 5db below peak levels. Referring to figure 5a, counter 107 would be enabled at time t₁ and disabled at time t₆ with CPU 17 storing time t₁ and counter 107 storing a count representing the total time between t₁ and t₆. Referring to figure 5b illustrating the multipath case, counter 107 would be enabled at time t₇ and disabled at time t₁₄ with CPU 17 storing the enabling time t₇. Thereafter, CPU 17 subtracts period g from the total count and performs the necessary calculations to derive the midpoint in time of the corrected period detected at the 5db below peak level. Finally, CPU 17 averages the separate corrected times to determine the result of the information provided by all three counters to determine the centroid of the received signal.

Claims: Apparatus for receiving recurring to and fro scanning signals comprising: (a) an antenna for receiving the scanning signals; (b) a converter (2) for converting the received signals into intermediate frequency signals; (c) a detector (14) for detecting the intermediate frequency signals; (d) an analog-to-digital converter (15) for converting the detected intermediate frequency signals into digital signals; (e) a digital peak detector (101) for detecting the peak amplitudes of the digital signals; and (f) a split gate processor (102-107); characterized in that: (g) said split gate processor (102-107) is operable to determine for each of the to and fro signals the respective first, second and third time periods for which the amplitude of the respective digital signal is greater than respective first, second and third predetermined levels below said detected peak amplitude; and (h) processing means (17) is provided for averaging for each of the to and fro signals the mid points of said time periods to provide a signal representative of the centroid of the respective digital signals, whereby the time duration between the two centroid signals permits determination of the angular bearing of the apparatus relative to the source of the recurring to and fro scanning signals. Apparatus according to claim 1 characterized by means (17) for rejecting, according to a predetermined algorithm, all except one such time period determined at any individual one of said predetermined levels. Apparatus according to claim 1 or claim 2 characterized in that said split gate processor (102-107) includes delay means (120) for delaying the digital signal, a first threshold detector (102) for detecting the time points when the amplitude of the delayed digital signal moves across a first threshold representing said first predetermined level, a second threshold detector (103) for detecting the time points when the amplitude of the delayed digital signal moves across a second threshold representing said second predetermined level, and a third threshold detector (104) for detecting the time points when the amplitude of the delayed digital signal moves across a third threshold representing said third predetermined level. Apparatus according to claim 3 characterized in that said split gate processor (102-107) includes a first counter (105) connected to said first threshold detector (102) for making a first count representative of the first time period, a second counter (106) connected to said second threshold detector (103) for making a second count representative of the second time period, and a third counter (107) connected to said third threshold detector (104) for making a third count representative of the third time period.

Inventors: ENEIN, MOHAMED, STRICKLAND, EVERETT P.
Applicants: HAZELTINE CORPORATION
Application year: 1985
Main classification: G01S1
IPC codes: G01S1