METHOD FOR MAKING TRANSISTOR

Abstract: Manufacturing of a graft-base transistor is characterized by: first, forming a layer (8) of oxide of silicon with opening on an n-semiconductor layer (2), at a part to become a base region (3, 4, 3); then, forming a polycrystalline silicon layer (9) and an overriding silicon nitride layer (10) with an opening (11) thereon; selectively diffusing P or As to form an n-emitter region (5); forming a second silicon oxide layers (12, 13) only on the emitter region (5) and on peripheral regions thereabout, and removing the polycrystalline layer (9) and the silicon nitride layer (10), and implanting B⁺ ions, thereby to form deeper and higher concentration base contact regions (3, 3) and shallower and lower concentration active base region (4).

Description: BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION: The invention generally relates to a bipolar transistor, and particularly concerns an improvement in manufacturing of bipolar transistors having a low base resistance and an ideal graft-base configuration in the bipolar transistor. 2. DESCRIPTION OF THE PRIOR ART: In order to achieve low noise and high frequency operation of bipolar transistors, as one measure of improvement, lowering of base spreading resistance has been proposed. One prior art example to achieve this is a graft-base configuration,wherein an active base region is formed with low impurity concentration in order to improve the carrier injection efficiency and a base contact region connecting thereto is formed with high impurity concentration, thereby lowering the base spreading resistance. FIG. 1 shows a sectional configuration of the prior art bipolar transistor having the graft-base configuration, wherein on an n-type silicon substrate 1 of a high impurity concentration an n-type epitaxial layer 2 of a low impurity concentration is formed, and in the n-type epitaxial layer 2 p-type base contact region 3, 3 of a high impurity concentration and a p-type active base region 4 of a low impurity concentration are formed in sequence, and further, in the p-type active base region 4 of low impurity concentration an n-type emitter region 5 is formed, and finally, electrodes 6, 6''and 6' are formed on the base contact regions 3, 3 and on the emitter region 5 through openings of a silicon oxide film 7. Since, however, in the above-mentioned prior art method for manufacturing of the bipolar transistor impurity concentrations of the base contact regions 3, 3 and the active base region 4 are different from each other, the forming of the regions 3, 3 and 4 requires respective processes which require long time, many workers and much materials. Furthermore, on account of using mask resistrations in the above-mentioned two processes, gaps A between the periphery of the emitter region 5 and the periphery of the base contact region 3 become 2µm or larger. Such size of the gap is not sufficiently small for enabling lowering of base resistance, and the base spreading resistance cannot be sufficiently lowered. US-A-4381953 discloses a self-aligned polysilicon base process for a bipolar transistor, whereby oxide sidewalls on a polysilicon mask control the emmitter-base separation, the base implant being carried out before growth of said sidewalls, the emitter-region implant afterwards. In IBM Technical Disclosure Bulletin Vol. 24 no. 7B, p.3847, an external base region is formed by undercutting a polysilicon island. The other end of the island is used to form a self-aligned collector reach through. Control of the base-emitter separation is by growth of a sidewall on the polysilicon island. SUMMARY OF THE INVENTION Purpose of the present invention is to provide an improved method for manufacturing a bipolar transistor which can dissolve the above-mentioned problems. That is, the present invention is for providing a method whereby active base regions and a base contact region can be formed only by a single diffusion step, and furthermore, the gap between the periphery of the emitter region and the periphery of the base contact region can be decreased within 1 µm, thereby sufficiently decreasing the base spreading resistance. A Method for making a bipolar transistor in accordance with the present invention comprises the steps as outlined in claim 1. BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is the sectional elevation view of the transistor of graft-base structure of the prior art. FIG. 2(a), FIG. 2(b), FIG. 2(c), FIG. 2(d), FIG. 2(e) and FIG. 2(f) are sectional elevation views showing manufacturing steps of a transistor embodying the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention is elucidated in detail with regard to a preferred embodiment of a manufacturing method of a bipolar transistor with reference to FIG. 2(a), FIG. 2(b), FIG. 2(c), FIG. 2(d), FIG. 2(e) and FIG. 2(f). At first, on a principal surface of an n-conductivity type silicon substrate 1 of high impurity concentration, an n-conductivity type epitaxial layer 2 is formed to a thickness of 1 to 20 µm. And thereafter, a layer 8 of oxide of silicon is formed on a principal surface of said epitaxial layer 2 by a known method, such as thermal oxidation. Then, by the well-known photolithographic etching method, a part of the silicon oxide layer 8 at which a base region is to be formed, is removed. Then, a layer 9 of polycrystalline silicon and thereon a layer 10 of silicon nitride are formed as shown in FIG. 2(a). Then, by the known photolithographic method, the silicon nitride layer 10 and the underlying polycrystalline silicon layer 9, which are on such a region wherein a base region is to be formed and an emitter region is to be formed, are selectively removed to form an opening 11 as shown in FIG. 2(b). Thereafter, by ion implantations, P or As ions as impurity is implanted into the epitaxial layer 2. P or As can be diffused by the known thermal diffusuion using vapor deposition. Then, the implanted ions are diffused in an oxidizing atmosphere. By such a process, an emitter region 5 of the n-conductivity type is formed, and at the same time, the vertical ends of the polycrystalline silicon layer 9 exposed under the silicon nitride layer 10 around the opening 11 are oxidized, thereby forming walls 13, 13 of oxide of silicon. And also, the surface of the emitter region 5 is oxidized thereby forming a layer 12 of oxide of silicon. In this process, since the speed of lateral oxidation of the polycrystalline silicon layer 9 is larger than the speed of diffusion of the emitter region 5 laterally underneath the polycrystalline silicon layer 9, the configuration becomes such that the outer periphery of the wall part 13 made by the oxidation of the polycrystalline silicon layer 9 is situated outside the peripheries at the surface of the emitter region 5. The oxidation speed of the polycrystalline silicon layer 9 can be further considerably increased by adoption of an high pressure oxidation method, if desired, or by adding such impurity as boron in the polycrystalline silicon layer 9. As a result of the above-mentioned manner, in a preferable embodiment, the outside boundary of the wall part 13 of the silicon oxide layer is disposed projecting more outwards than the diffusion front at the surface, i.e., the periphery of the emitter region, as shown in FIG. 2(c). In the next step, the silicon nitride layer 10 and the polycrystalline silicon layer 9 are all removed by known methods, thereby exposing the region to form the base contacts, as shown in FIG. 2(d). Then, boron ions B⁺ are ion-implanted on all over the surface of the wafer, and a thermal treatment is carried out in an oxidizing atmosphere. By this thermal treatment, base contact regions 3, 3 having a high impurity concentration of p-conductivity type and a large diffusion depth are formed in the parts where no silicon oxide layer 12 on the surface is formed; and with respect to the part above the emitter region 5 covered by the silicon oxide layers 12 and the silicon oxide walls 13, an active base region 4 having a low impurity concentration of p-conductivity type and a smaller depth than the base regions 3, 3 is formed as shown in FIG. 2(e). Thereafter, silicon oxide layers are selectively removed of the parts above the emitter region 5 and the base contact regions 3, 3, to expose the surface of the wafer. Then, electrodes 6', 6 and 6''are formed respectively to contact the emitter region 5 and the base regions 3 and 3 , respectively, by utilizing high impurity aluminum or aluminum containing 1 wt % silicon, thereby completing the transistor as shown in FIG. 2(f). The transistor manufactured in the above-mentioned steps has a desirable graft configuration wherein gaps B, B between the outside periphery of the emitter region 5 and the base contact regions 3, 3 are smaller than 1 µm.

Claims: A method of making a bipolar transistor comprising the steps of: selectively forming a first layer of oxide (8) of silicon on a principal surface of a semiconductor layer (2) of a first conductivity type except on a surface portion to become a base region, forming a layer (9) of polycrystalline silicon and thereon a layer (10) of silicon nitride on the exposed portion of said principal surface and on said oxide layer (8), selectively removing said layer of polycrystalline silicon and said layer of silicon nitride to form an opening within said surface portion, selectively introducing an impurity of said first conductivity type to form an emitter region (5) through said opening, forming a second layer (12) of oxide of silicon on the surface of said emitter region, selectively oxidizing said layer of polycrystalline silicon in a lateral direction underneath said layer of silicon nitride to form side walls (13) of oxide of said polycrystalline silicon around said opening, removing said layer (10) of silicon nitride and said layer (9) of polycrystalline silicon, ion implanting impurity of a second conductivity type through said surface portion of the semiconductor layer into said semiconductor layer to form a base region, with a mask of said second layer (12) of oxide of silicon and of said side walls (13) of oxide of said polycrystalline semiconductor; and thermal treating the whole structure as defined above, thereby said base region having a configuration of a base contact region (3) which has a high impurity concentration and large diffusion depth, and of an active base region (4) which has a low impurity concentration and a small diffusion depth. Method of making a transistor in accordance with claim 1, wherein said semiconductor layer comprises a silicon substrate and an epitaxial layer of a first conductivity type formed thereon. Method of making a transistor in accordance with claim 2, wherein said first conductivity type is n-type, and said second conductivity type is p-type. Method of making a transistor in accordance with claim 3, wherein said impurity of said first conductivity type is P or As, and said impurity of said second conductivity type is B.

Inventors: SHIRAISHI, MASATOSHI, TOYOOKA, TETSUO
Applicants: MATSUSHITA ELECTRONICS CORPORATION
Application year: 1985
Main classification: H01L21
IPC codes: H01L29, H01L21