METHOD OF FORMING A SEMICONDUCTOR DEVICE COMPRISING AN OPTICAL AND AN ELECTRONIC ELEMENT

Abstract: A semiconductor device includes a substrate (1) having a low substrate surface (15) formed in the substrate with a first gentle slope (15a) from the substrate surface and a single crystalline layer formed on the low substrate surface nearly level with the substrate surface and having a gentle slope (15b) facing the first gentle slope. An optical semiconductor element (LD) is constructed using the single crystalline layer and an electronic semiconductor element (FET) is con­ structed using the substrate surface. A wiring layer (31a) con­ nects electrodes (25, 27) of the optical semiconductor element (LD) and the electronic semiconductor element (FET) through the first and the second gentle slopes, the slopes being gentle enough to reduce breakage of the wiring which can occur when steeper slopes, produced by conventional methods, are used.

Description: The present invention relates to the production of semiconductor devices. Recent advances in the technologies of crystal growth and device production have made it possible to combine optical and electronic elements into a single chip. Such an optoelectronic integrated circuit (OEIC) device is not only smaller and easier to use in various systems but speedier, more reliable, and less noisy than hybridized discrete devices. A particularly attractive and important OEIC device is one in which an optical semiconductor element, for example a laser diode or photo diode (PD), is monolithically integrated with a field effect transistor (FET) driver. Such an OEIC device is disclosed in Applied Physics Letters, 44(3), 1 February, 1984, at pages 325-327, in a paper entitled "Monolithic integration of an AlGaAs/GaAs multiquantum well laser and GaAs metal-semiconductor field-effect transistors on a semi-insulating GaAs substrate by molecular beam epitaxy". In fabricating a laser/FET unit or PD/FET unit, there is a problem in how to match the laser structure to the FET structure, as each component has a very different layer structure. A laser generally has a higher structure than an FET. As conventional photolithographic technology requires a wafer with an even surface, the laser may therefore have to be formed in an etched groove. A known method of producing the above-mentioned prior art OEIC device incorporating a laser/FET unit, also disclosed in the paper concerned, may be considered to comprise the steps of: providing a resist pattern on a main face of a single-crystalline substrate; subjecting the said substrate to an etching process to form a recess; forming a single-crystalline semiconductor layer on the bottom of the said recess; forming an optical semiconductor element, at least part of which is constituted by the said layer, and forming an electronic semiconductor element at a residual portion of the said main face adjacent to the recess; and forming a wiring portion connecting the said optical semiconductor element to the said electronic semiconductor element. In this method the etching process is a wet chemical etching process. Since in this prior art device the said substrate is a (100)-oriented semi-insulating GaAs substrate, when the chemical etching process in the above-described method is performed on the substrate a (01 1 ) face is exposed as a side wall, which (01 1 ) face forms a 55 o angle with respect to the (100) top surface, so that a groove having a sharp step is formed. This sharp step can make application of the photolithographic technology difficult. Thus, high integration of the laser/FET unit becomes difficult. Further, the sharp 55 o angle step often results in breakage of wiring and thus a reduced production yield. It is therefore desirable, in view of the above disadvantages of the prior art, to provide a method of producing a semiconductor device including both optical semiconductor elements, such as a laser diode, and ordinary electronic semiconductor elements, such as an FET, formed on a single substrate, in which the side walls of the recess have a gentle slope (as opposed to the sharp slope of the prior art) so that photolithography can be more readily performed at a desirably high integration density, and wiring can be provided with less danger of breakage. According to the present invention there is provided a method of producing a semiconductor device, comprising the steps of: providing a resist pattern on a main face of a single-crystalline substrate; subjecting the said substrate to an etching process to form a recess; forming a single-crystalline semiconductor layer on the bottom of the said recess, the top surface of the said semiconductor layer being substantially level with the said main face of the substrate; forming an optical semiconductor element, at least part of which is constituted by the said layer, and forming an electronic semiconductor element at a residual portion of the said main face adjacent to the recess; and forming a wiring portion connecting the said optical semiconductor element to the said electronic semiconductor element; characterised in that the said etching process is a dry etching process, and in that the resist pattern includes an edge-defining portion that overlies a peripheral region of the required recess, the thickness of that portion being caused to increase progressively in the outward direction from the recess, and in that etching is continued until the said edge-defining portion is removed thereby, so that substrate material originally underlying that portion is progressively etched away to leave the said peripheral region sloping gently upwards from the bottom of the recess to the said residual portion of the said main face, the said wiring portion being formed to extend over the said peripheral region of the recess. Reference will now be made, by way of example, to the accompanying drawings, in which: Figs. 1A to 1K show cross-sectional views illustrating steps in a method of producing a semiconductor device embodying the present invention; Figs. 2 and 3 are cross-sectional views, to a larger scale, showing respective parts of the finished device; Fig. 4 shows a perspective view of the finished device; Fig. 5 shows a circuit diagram of the device shown in Fig. 4; Fig. 6A shows a cross-sectional view, corresponding substantially to Fig. 3, but illustrating a modification to the part of the device shown in Fig. 3, and Fig. 6B illustrates a step in a method of producing the modified part of Fig. 6A; Fig. 7 shows a circuit diagram corresponding to Fig. 6A; Fig. 8 shows a cross-sectional view of another device embodying the present invention; Fig. 9 shows a perspective view corresponding to Fig. 8; Fig. 10 shows a circuit diagram of the device shown in Fig. 9; Fig. 11A and 11B show cross-sectional views illustrating a step in a first modification to the method of Fig. 1; Figs. 12A and 12B show cross-sectional views illustrating a step in a second modification to the method of Fig. 1; and Figs. 13A and 13B show cross-sectional views illustrating a step in a third modification to the method of Fig. 1. Figs 1A to 1K are cross-sectional views for explaining a method of producing a semiconductor device embodying the present invention. After providing a GaAs substrate 1 as shown in Fig. 1A, a photo resist 2, for example AZ4620 (produced by Hoechst), having a thickness of 5 to 15µm is formed over the surface of the GaAs substrate 1 and patterned in a stripe form, as shown in Fig. 1B. The width W of the stripes of the resist layer may be 50 to 200µm, preferably 100µm. And the thickness d may be 7 ∼ 8µm. Next, as shown in Fig. 1C, heat treatment for baking is carried out for 10 minutes at a temperature of 200 o C to change the edges of the resist layer 2 to gentle slopes and increase the thickness d' of the resist layer 2 to about 8 to 10µm. In this heat treatment, the temperature is 200 o C which is lower than the usual post baking temperature 120 o C. And the width W will not be changed so that the slope α of the edge of the mask 2 is approximately 5 o ∼ 15 o . The thickness d' of the resist mask should be larger than the total thickness of the semiconductor laser layer which will be formed in a groove (recess) later. There are some rules which decide the slope of the heated mask. Thus, the slope of the edge depends upon the relationship between W and d. As shown in Fig. 1D, a resist layer 3 is formed over the obtained structure and then patterned. The patterned resist layer 3 has a thickness of 5 to 15µm. Since the resist layer 2 had been heat-treated, it is not removed in the patterning process of the resist layer 3. Thus, the gentle slopes of the resist layer 2 facing the centre Fig. 1D are exposed, while the other slopes are protected by the resist layer 3. A slight heat-treatment is carried out to dry the patterned resist layer 3. As shown in Fig. 1E, an ion beam etching, for example argon ion (Ar⁺) beam etching, is used to etch a mesa while rotating the GaAs substrate 1. In this ion beam etching process, the ion beam irradiates the GaAs substrate 1 at an angle of about 70 o . When the mesa height h is about 10µm, the ion beam etching process is ended. Thus, a groove 4 having a slope 12 at an angle α of about 5 o to 15 o is formed in the GaAs substrate 1. The ion beam etching conditions are an acceleration voltage of 500 and an ion current density of 0.57 mA/cm². The ion beam etching process etches all of the exposed surfaces equally, irrespectively of the various materials thereof, so as to remove progressively edge-defining portions of the resist layer 2, and substrate material originally underlying those portions, to leave peripheral regions 12 of the groove 4 sloping gently upwards from the bottom of the groove to residual portions of the main face of the substrate 1. Thus, the initial slope of each edge-defining portion of the mask 2/3 as shown in Figure 1D is shifted downwardly into the etched substrate 1, so that the required groove 4 results as shown schematically in Fig. 1E. As shown in Fig. 1F, the residual resist layers 2 and 3 are then removed, resulting in the GaAs substrate 1 having a mesa type recess or groove 4 with a gentle slope 12. As shown in Fig. 1G, a semiconductor laser layer 5 consisting of an n⁺ type GaAs layer, n type Al 0.3 Ga 0.7 As layer, etc, is grown over the entire GaAs substrate 1 by molecular-beam epitaxy (MBE). The structure of the layers corresponds to that of the optical semiconductor element, i.e the laser diode LD, or photodiode PD. As shown in Fig. 1H, the semiconductor laser layer 5 is then patterned using two above-mentioned gentle-slope forming steps (represented schematically by mask 2,3 in Fig. 1G) to form two further slopes 13. As shown in Fig. 1I an SiO₂ layer 7 is formed over the obtained structure and then patterned so that the SiO₂ layer covers the layer 5 formed in the etched groove. Then an FET epitaxial layer 8 is grown on the substrate while forming a polycrystalline (Al)GaAs layer 9 on the SiO₂ layer 7. The structure of the FET epitaxial layer 8 corresponds to that of a FET the thickness of which is not so large as the semiconductor laser layer 5. As shown in Fig. 1J, the polycrystalline (Al)GaAs layer 9 is removed by a chemical etching process using a resist layer 10 as a mask. After that, the SiO₂ layer 7 is also etched and the resist layer 10 is removed. Then, various LD and FET electrodes and a wiring layer 11a, 11b are formed on the gentle slope 12 as shown in Fig. 1K. The reasons for making the gentle slope 12 depend on two main requirements which are necessary for making the OEIC. Firstly, in order to deposit the wiring layer on the slope between LD and FET, the slope should be gentle because it is quite difficult to deposit a thick enough wiring layer on a sharp slope as used conventionally. Secondly, in the patterning process of the wiring layer 11a, 11b formed on the entire surface of the substrate, a photo resist layer should be coated on the wiring layer. The thickness of the coating resist layer should be large enough to cover properly even on the sharp slope. This results in the portions of the resist layer coated on the upper surface where the FET's wiring is patterned becoming indesirably thick so that it may be impossible to produce a fine pattern for the FET IC because of the thick resist. In a device as described above embodying the present invention, however, since the slope is gentle, the coating resist can be thin and it is possible to make a fine pattern. A detailed explanation relating to Fig. 1K will be given below. Figure 2 shows a cross-sectional view, to a larger scale, of parts of the device shwon in Fig. 1K. In Fig. 2, reference numeral 1 represents the GaAs substrate, 14 the semiconductor laser layer structure which is multilayer, 15 a recess, 15a, 15b and 15c gentle slopes, 16 an n side contact layer of an n⁺ type GaAs, 17 an n side clad layer of n type Al 0.3 Ga 0.7 As, 18 an active layer of either n type or p-type GaAs, 19 a p side clad layer of p type Al 0.3 Ga 0.7 As, 20 a p side contact layer of p⁺ type GaAs, 21 an FET layer, 22 an undoped GaAs layer, 23 an n GaAs FET active layer, 25 a p side contact electrode of AuZn, 26 a source electrode of AuGe/Ni, 27 a drain electrode of AuGe/Ni, 28 a gate electrode of Al, 30 an insulating layer of SiO₂ , and 31 a wiring layer of Au/Cr. Although in Fig. 1K there is a step between the two left-hand gentle slopes 13, it is possible not to form such a step and in such a case a single gentle slope 15b may be provided, as shown in Fig. 2. A method of producing the structure of Fig. 2,in which the p side contact electrode 25 is connected to the drain electrode 27 through the wiring layer formed on the gentle slopes 15a and 15b, will be explained below in detail. After forming a recess 15 having the gentle slopes 15a as explained above, the n side contact layer 16, the n side clad layer 17, the active layer 18, the p side clad layer 19 and the p side contact layer 20 are successively formed. The multilayer 14 consisting of the n side contact layer 16 to the p side contact layer 20 is patterned by the above-mentioned gentle-slope forming process to form the gentle slope 15b. Then, the FET layer 21 consisting of the undoped GaAs layer 22 and n GaAs active layer 23 is formed by MBE, as explained above with reference to Figs. 1I, 1J. The p side contact electrode 25 for the LD is then formed on the p side contact layer 20 by a lift-off process. After that, the n side contact electrode 33 is formed on the n side contact by a lift-off process and an alloying. The source electrode 26 and the drain electrode 27 for the FET are also formed on the FET layer 21. The insulating layer 30 is formed over the obtained structure by a sputtering process and is patterned by photolithography. A wiring layer 31a is formed on the gentle slope 15a, 15b via the insulating layer 30 by a lift-off process. Thus, the structure of Fig. 2 can be formed on a single GaAs substrate. Fig. 3 shows a cross-sectional view, to a larger scale of further parts of the device shown in Fig. 1K. In Fig. 3, the same reference numerals as in Fig. 2 represent the same portions. As seen in Fig. 3, the source electrode 26 is connected to the n side contact electrode 33 through the wiring 31b formed on the insulator layer 30 overlying the gentle slope 15d. Figure 4 shows a perspective view corresponding to Fig. 1K, Fig. 1K being a cross-sectional view taken along the line AA in Fig. 4. Figure 5 is a circuit diagram of the device of Fig. 4. As easily understood from the accordance between the Fig. 4 and Fig. 5, the wiring 31a on the gentle slopes 15a, 15b connects between the LD and the FET Q₂ , and the wiring 31b on the gentle slope 15d connects between the LD and the FET Q₁. In this embodiment, the LD and Q₂ can be connected by the wiring 31a formed within the OEIC itself so that the characteristic of the OEIC is improved. Figure 6A shows a cross-sectional view of parts of another semiconductor device embodying the present invention. In Fig. 6A, the LD and FET are also formed on a GaAs substrate 1. The drain electrode 27 is connected to the p side contact electrode 25 via the wiring 31c formed on a substantially flat surface 32 extending between the electrodes. The process of producing the Fig. 6A device is almost the same as the process shown in Fig. 1A-1H. That is, as shown in Fig. 6B, after forming the semiconductor laser layer 5, the combination mask 2 and 3 is formed so that the edge of the mask 2,3 corresponds to the slope of the layer 5 (shown 5a). After that the flat surface 32 can be formed on the gentle slope 15a by performing the ion beam etching process as explained above. The same reference numerals as in Fig. 2 and 3 represent the same portions. Figure 7 is a schematic circuit diagram of the device of Fig. 6. Figure 8 shows a cross-sectional view of parts of yet another semiconductor device embodying the present invention. In Fig. 8, a pin photo-diode (PIN PD) and an FET are formed on a single semi-insulating GaAs substrate 1. In Fig. 8, reference numeral 40 is an n⁺ type GaAs layer, 41 an n⁻ type GaAs layer, 42 a high resistivity Al 0.3 Ga 0.7 As layer, 43 a Zn diffused region, 45 an Si₃N₄ layer, 46 an undoped GaAs layer, 47 an n type GaAs layer, 48 an Al electrode, 50 a wiring layer of Au/Ti, 51 an Au/AuGe electrode, and 52 an Au/Zn/Au electrode. As shown in Fig. 8, the Al electrode 48 is interconnected to the Au/Zn/Au electrode through an Au/Ti wiring layer 50 continuously laid on the gentle slopes 15a and 15b. Figure 9 shows a perspective view of the device of Fig. 8 (Fig. 8 presents the view as seen along line B-B in Fig. 9). Figure 10 is a circuit diagram of the device of Fig. 9. Other methods for forming a recess having a gentle slope in a semi-insulating GaAs substrate will now be explained. Figures 11A and 11B show cross-sectional views illustrating different stages of processing in one such method. As shown in Fig. 11A, a resist layer 61 having a thickness of, for example, 6 µm is formed. The resist layer 61 is then exposed through a mask of a photosensitive glass having a hole 64 with a taper wall and a glass fiber 63. The resist layer at the central position just under the glass fibre 63 is most exposed, and the amount of exposure is gradually reduced as the distance from that position on the resist layer increases. Thus, as shown in Fig. 11B, the resist layer has a pattern 66 having a gentle slope 65. After that, using ion etching or reactive ion etching, the entire surface of the obtained structure is etched. Thus, a recess having the same pattern 66 can be formed in the semi-insulating GaAs substrate 1. Figures 12A and 12B show cross-sectional views illustrating different stages of processing in another method of forming a gentle slope in a substrate. As shown in Fig. 12A, a polyimide layer having a thickness of, for example, 6 µm is formed on a semi-insulating GaAs substrate 1. The polyimide layer is heated by irradiation with a laser so that a portion of the polyimide in which a recess having a gentle slope is formed is irradiated less compared to the surrounding portion. The center of the recess forming portion may be not irradiated at all. After that, the recess forming process for the semi-insulating GaAs substrate is carried out as explained with Fig. 11B. Figures 13A and 13B show cross-sectional views illustrating different stages of processing in yet another method of forming a gentle slope in a substrate. As shown in Fig. 13A, a first polyimide resin layer 72₁ having a thickness of, for example, 6000Å (0.6µm) is formed on a semi-insulating GaAs substrate 1. Then, the first polyimide resin layer 72₁ is heat-treated at a first temperature T₁ of, for example, 200°C. A second polyimide resin layer 72₂ is formed on the first polyimide resin layer 72₁ and is heat-treated at a second temperature T₂ of, for example, 180°C, which is lower than the first temperature T₁. The process is repeated until the nth polyimide layer is formed on the (n-1)th polyimide layer and is heat-treated at a temperature T n lower than temperature T n-1 . Thus, a polyimide resin multi-layer 72 is formed on the semi-insulating GaAs substrate. When a polyimide resin is heat-treated at a higher temperature, the etching rate is decreased. Then, as shown in Fig. 13B the polyimide resin multilayer 72 is etched by an etchant, using a resist layer 73 having an opening 74 as a mask so that a recess 75 having a gentle slope 76 is formed in the polyimide multilayer 72. Then, the recess forming process as explained in Fig. 11B. is carried out for the semi-insulating GaAs substrate. Furthermore, in a further method, also explained with reference to Figs. 13A and 13B, the multi-layer 72₁, 72₂ ... 72 n comprises Al x Ga 1-x As layers in which the value of x is gradually increased from 72₁ to 72 n . Then, the wet etching process using a etchant containing HF is performed so that since the AlGaAs is etched faster than the GaAs or AlGaAs having a small quantity of Al, the etched pattern becomes shown in Fig. 13B having a gentle slope 76. After that, there are two alternative processes. The first process is that the ion beam etching is simply performed in the same manner as the previous explained process. The second process is that since the multi-layer 72 comprises a AlGaAs compound semiconductor, the FET structure is formed on or in the multi-layer 72.

Claims: A method of producing a semiconductor device, comprising the steps of: providing a resist pattern (2, 3) on a main face of a single-crystalline substrate (1); subjecting the said substrate (1) to an etching process to form a recess (4); forming a single-crystalline semiconductor layer (5) on the bottom of the said recess (4), the top surface of the said semiconductor layer (5) being substantially level with the said main face of the substrate (1); forming an optical semiconductor element (LD), at least part of which is constituted by the said layer (5), and forming an electronic semiconductor element (FET) at a residual portion of the said main face adjacent to the said recess; and forming a wiring portion (11b) connecting the said optical semiconductor element (LD) to the said electronic semiconductor element (FET); characterised in that the said etching process is a dry etching process, and in that the said resist pattern (2, 3) includes an edge-defining portion that overlies a peripheral region of the required recess (4), the thickness of that portion being caused to increase progressively in the outward direction from the recess, and in that etching is continued until the said edge-defining portion is removed thereby, so that substrate material originally underlying that portion is progressively etched away to leave the said peripheral region (12) sloping gently upwards from the bottom of the recess to the said residual portion of the said main face, the said wiring portion (11b) being formed to extend over the said peripheral region of the recess. A method as claimed in claim 1, wherein the said single-crystalline substrate is made of semi-insulating GaAs. A method as claimed in claim 1 or 2, wherein the said resist pattern (2, 3) is provided by forming a first resist layer on the said main face of the substrate (1), which layer includes a strip (2) that extends over the said peripheral region of the required recess, and by subjecting the said first resist layer to a heat-treatment to cause the edges of the strip (2) to become rounded, and by forming a second resist layer (3), extending over the said first resist layer, and patterning that second resist layer (3) to leave the said resist pattern, the said resist pattern (2, 3) being such that an exposed rounded edge part of the said strip, not covered by the said second resist layer (3), provides the said edge-defining portion. A method as claimed in claim 1 or 2, wherein the said resist pattern is provided by forming a resist layer (61) on the said main face of the substrate (1), and by exposing a selected portion of that layer (61), overlying the said peripheral region of the required recess (4), to light received via a mask (62), the mask having light transmission properties such that the amount of light received at the said selected portion decreases progressively in the outward direction from the required recess (4), and by developing the said resist layer (61) to leave the said resist pattern, the said edge-defining portion (65) being constituted by a residual portion of the said selected portion. A method as claimed in claim 4, wherein the said mask (62) comprises a sheet of photo-sensitive glass having therein a tapered hole (64) in which an optical fibre (63) is arranged. A method as claimed in claim 1 or 2, wherein the said resist pattern is provided by forming a polyimide resin resist layer (68) on the said substrate, and by subjecting that layer to a heat-treatment such that the heat applied to a selected portion of the layer, which portion overlies the said peripheral region of the required recess (4), increases progressively in the outward direction from the required recess, and by developing the heat-treated resist layer (68) to leave the said resist-pattern, the said edge-defining portion (69) being constituted by a residual portion of the said selected portion. A method as claimed in claim 1 or 2, wherein the said resist pattern is provided by forming a first polyimide resin layer (72₁) on the said main face of the substrate and by subjecting that layer (72₁) to a heat-treatment at a first temperature, and by forming a second polyimide resin resist layer (72₂) on the first resist layer (72₁) and subjecting that second resist layer to a heat-treatment at a second temperature, lower than the said first temperature, and by forming at least one further such resist layer (72 n ) over the last preceding resist layer (72 n-1 ) and heat-treating that further layer (72 n ) at a temperature lower than that at which the last preceding resist layer (72 n-1 ) was heat-treated, and by patterning the resulting layer structure (72) using a mask (73) having an opening (74) corresponding to the said region of the said main face that is to be etched away to form the recess. A method as claimed in any preceding claim, wherein the said optical semiconductor element (LD) comprises a plurality of semiconductor layers (17, 18, 19, 20) formed as a stack on the said single-crystalline semiconductor layer (16), which method includes the steps of: forming on the top layer (20) of the said stack (17-20) a further resist pattern, which pattern is formed to delimit parts of the said stack that are to be etched away by a further etching process and includes a further edge-defining portion the thickness of which decreases progressively in the said outward direction from the recess; and performing the said further etching process, wherein etching is continued until the said further edge-defining portion is removed thereby, so that material of the said stack originally underlying the said further edge-defining portion is progressively etched away to leave a wiring support region (15b) of the said stack sloping gently downwards into the said recess from a remaining portion of the said top layer (20) and facing the said peripheral region of the recess; the said wiring portion (31a) being formed to extend also over the said wiring support region (15b). A method as claimed in any preceding claim, wherein the said dry etching process is an ion beam etching process. A method as claimed in any one of claims 1 to 8, wherein the said dry etching process is a reactive ion etching process. A method as claimed in any preceding claim, wherein the said optical semiconductor element is a laser diode (LD). A method as claimed in any one of claims 1 to 10, wherein the said optical semiconductor element is a photodiode. A method as claimed in any preceding claim, wherein the said electronic semiconductor element is a field effect transistor (FET).

Inventors: MACHIDA, HIDEKI, MIURA, SHUICHI, SAKURAI, TERUO, SANADA, TATSUYUKI, WADA, OSAMU, YAMAKOSHI, SHIGENOBU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1985
Main classification: H01L21
IPC codes: H01S5, H01L21, H01L23, H01L27