PARITY CHECKING DEVICE

Abstract: Apparatus for distinguishing an applied control signal from extraneous signals according to the duration of said signals to establish parity thereof, and comprising the use of two serial monostable devices (10 and 11) a first (10) of which produces a first output pulse (T1) of a predetermined duration upon receipt of a signal and the second (11) of which produces a second output pulse (T2) at the end of the first output pulse, and an output circuit (12) receiving all of the applied signals and the second output pulse to relay any signal received simultaneously with the second output pulse.

Description: ■ IMPROVED PARITY CHECKING DEVICE' 1 The invention pertains to protective equipment safeguarding against false operation of electrical apparatus by extraneous signals. BACKGROUND ART Such equipment has for many years been utilized, for example, in the field of high speed telegraphy and has In man instances relied for discrimination upon the predictability o occurrence of message signals. Discrimination of this form cannot, however, be applied In the design of electronic control circuits which respond to manually operable control switches. For instance, motion picture theatres are extremel hostile electronic environments due to the use of ignition spark generators for Zenon projection lamps as well as the us of high tension gas-discharge lighting. It Is a characteristics of extraneous signals resulting therefrom tha they are of rather short duration, less than 1 mS. It is common practice in these theatres to provide at several locations switching facilities for selective control by an operator of many internal functions such as sound amplitude, lighting Intensity etc. In order to achieve parity checking on control lines to ensure response only to authentic switching signals it has been usual to utilize either mechanical Interlock switch buttons or electromagnetic relays. DISCLOSURE OF INVENTION One principal object of the invention is to provide a parity checking device for a control line or lines of electronic control circuits which employs solid-state components and is effectively and relatively inexpensive. According to one general form the invention consists of parity checking apparatus for distinguishing from extraneous signals a control signal which is of at least a predetermined time duration, comprising two serially connected monostable devices, means for applying all of said signals to a first of said monostable devices, said first monostable device producing a first output pulse of said predetermined time duration upon receipt of said signals and said second monostable device producing a second output pulse at the end of said first output pulse, an output unit which when operated relays said control signal or a representation thereof, and a multiple Input control device having one Input connected to receive said second output pulse and responding to simultaneous receipt of said second output pulse and said signals to operate said output unit. BRIEF DESCRIPTION OF DRAWING A more detailed description of the invention will follow hereafter with reference to an embodiment as illustrated in the accompanying drawing being a schematic diagram of a parity checking device constructed according to this invention. BEST MODE OF CARRYING OUT THE INVENTION Copending Patent Application No. PG3543 describes one of many forms of electronic control circuits employing controlling devices provided with a manually operable switch. Such a switch SW1 is shown connected to the input terminal IT of the parity checking device shown In the drawing. It is intended that all signals appearing at the Input terminal IT be automatically checked for parity before the control circuit responds to operation of switch SHI. In an environment such as a motion picture theatre many extraneous voltages will be received at terminal IT all of which Invariably are of a duration less than 1 mS. As will be seen hereafter the present checking device will not provide a parity checked output at output terminal U unless the input signal has persisted longer than l S. The switching circuit including switch SW1 is arranged when operated to produce a "0" at point (A) which is applied through NAND GATE Gl as a "1" at point CB). The capacitor Cl serves as a bypass for transients. Therefore, a pulse with a positive edge T is applied to the input of a first monostable 10 of two serially connected edge-triggered monostables preferably composed of 4528CMOS chips of the kind produced by Motorola Electronics Australia Pty Ltd. Monostable 10 senses the positive edge of the applied pulse and at its output (C) produces a pulse Tl of a predetermined duration. Second monostable 11 responds to the trailing negative edge of the pulse Tl and at its output (D) produces a pulse T2 applied to one input of the NAND GATE G2 as a "1" whi^e its other gate receives a "1" from the input of monostable 10 if the signal applied via GATE Gl from the input terminal IT still persists. In such an event a negative clock pulse is produce at point (E) which is applied to the latch device 12 to produce a latched-on output at terminal U which represents a parity checked output. It will be apparent that if in fact the signal appearing at point (B) is less than ImS in duratio then no clock pulse will be produced at point (E). thus providing for discrimination against extraneous signals. The operator, therefore. Is required, in order to obtain a parity checked output, to maintain closure of switch SWl for a perio at least as long as ImS. The latch device 12 may be a signal unit common to all parity check functions on the individual control lines 13a-13n. each provided with its own respective parity check device. The foregoing description has been confined to a single embodiment for the purpose of illustrating the principle of this invention. It will be appreciated that other forms, embodiments and modifications are feasible within the scope of this invention.

Claims: 1. Parity checking apparatus for distinguishing from extraneous signals a control signal which is of at least a predetermined time duration, comprising two serially connected monostable devices, means for applying all of said signals to a first of said monostable devices, said first monostable device producing a first output pulse of said predetermined time duration upon receipt of said signals and said second monostable device producing a second output pulse at the end of said first output pulse, an output unit which when operated relays said control signal or a representation thereof, and a multiple input control device having one input connected to receive said second output pulse and responding to simultaneous receipt of said second output pulse and said signals to operate said output unit. 2. Parity checking apparatus according to claim 1, wherein said control signal appears as a positive pulse at said first monostable device which responds to a positive edge of the pulse, and said second monostable device responds to the trailing negative edge of said first output pulse to produce a positive pulse as said second output pulse. 3. Parity checking apparatus according to claim 2. wherein said multiple input control device is a NAND GATE providing a negative clock pulse at its output to operate said output unit. 4. Parity checking apparatus according to claim 1. 2 or 3, wherein said signals appear on a signalling line, and said output unit is connected with a plurality of said signalling lines and is common equipment to a plurality of said parity checking apparatuses and when operated latches the respective one of said signalling lines to allow said control signal to pass. 5. Parity checking apparatus according to claim 4, wherein said control signal appears on said signalling line as a "0" and is inverted to provide a "1" at the Input to said first monostable. 6. Parity checking apparatus substantially as hereinbefore described with reference to the accompanying drawings.

Inventors: STOREY PHILLIP JAMES, STOREY, PHILLIP, JAMES
Applicants: GREATER UNION THEATRE SUPPLIES, STOREY PHILLIP JAMES, GREATER UNION THEATRE SUPPLIES PTY. LIMITED, STOREY, PHILLIP, JAMES
Application year: 1985
Main classification: G08C25
IPC codes: G06F11, G08C25, H03K5, H04L25, H04Q9