SEMICONDUCTOR MEMORY DEVICE

Abstract: The semiconductor memory device can continuously read or store a plurality of data therefrom or therein. The semiconductor memory device includes a memory unit having a plurality of memory cells (3,4), the memory cells being arranged in a matrix having rows and columns, and a reading storing circuit. The reading storing circuit can read or store data from or into the memory cell at an address corresponding to an address signal received therein in response to the reception of first and second control signals, respectively. The reading storing circuit also can consecu­ tively read or store data from or into the memory cell at another address subsequent to the address read or stored at the last time in response to the reception of the second control signal. Such a device can therefore have improved access time for continuous accessing of a plurality of data.

Description: The present invention relates to semiconductor memory devices. In one type of prior art computer system including a computer and a semiconductor memory device, in response to successive individual access requests from the computer to the memory device, successive individual data storage or data reading operations involving individual memory cells of the device can be effected. This system has a disadvantage in that when continuous accessing of a plurality of data items stored in consecutive memory cells of the memory device is required, address data individually designating such memory cells must be supplied to the memory device, as described later in detail with reference to a specific example. Because of the need to supply such address data, in the prior art semiconductor memory device concerned the access time per memory cell, for continuous accessing of a plurality of data items stored in consecutive memory cells, may be undesirably long. JP-A-59-135696 discloses a semiconductor memory device in which the access time for continuous accessing of data items in a predetermined group of four memory cells ("nibble") is reduced. The device concerned may be considered to include: a plurality of memory cells arranged in a matrix of columns, connected with respective column lines of the device, and rows connected with respective row lines of the device; row selection means connected for receiving externally-applied row selection data designating a selected one of the said row lines, and operable in dependence upon that data to activate that selected row line; input/output circuitry connected to the said column lines and having a plurality of control inputs associated respectively with predetermined different groups of the said column lines; and column group selection means connected for receiving externally-applied selection data designating a selected one of the said control inputs, and operable in dependence upon that data to apply a column group selection signal to the said selected one of the control inputs; the said input/output circuitry including a plurality of input/output lines, equal in number to the column lines of each of the said different groups, and being operable upon receipt of such a column group selection signal to connect the column lines of the particular group that is associated with the selected control input respectively to the said input/output lines, thereby to permit parallel transfer of data bits between the said input/output lines and those memory cells of the said plurality that are connected with the said selected row line and are also connected respectively with the column lines of the said particular group. In this device each of the said different groups of column lines is made up of four column lines so that when a "nibble" mode accessing operation is to be performed, involving four memory cells connected respectively with the column lines of a particular group, only a single item of address data, designating that particular group and the row line to which those cells are also connected, need be supplied to the device, thereby affording a reduction in the access time per memory cell. However, in this device the groups of column lines are mutually exclusive, no member of one group being also a member of another group. Thus, if it is desired to access data in four memory cells that are not connected respectively with the column lines of a particular group, for example in a case where there are two cells connected with the column lines of a first group and two cells connected with the column lines of a second group, two separate nibble-mode accessing operations must be performed, on the said first and second groups respectively, to access the required memory cells. According to the present invention there is provided a semiconductor memory device including: a plurality of memory cells arranged in a matrix of columns, connected with respective column lines of the device, and rows connected with respective row lines of the device; row selection means connected for receiving externally-applied row selection data designating a selected one of the said row lines, and operable in dependence upon that data to activate that selected row line; input/output circuitry connected to the said column lines and having a plurality of control inputs associated respectively with predetermined different groups of the said column lines; and column group selection means connected for receiving externally-applied selection data designating a selected one of the said control inputs, and operable in dependence upon that data to apply a column group selection signal to the said selected one of the control inputs; the said input/output circuitry including a plurality of input/output lines, equal in number to the column lines of each of the said different groups, and being operable upon receipt of such a column group selection signal to connect the column lines of the particular group that is associated with the selected control input respectively to the said input/output lines, thereby to permit parallel transfer of data bits between the said input/output lines and those memory cells of the said plurality that are connected with the said selected row line and are also connected respectively with the column lines of the said particular group; characterised in that each of the said input/output lines is provided with an individual set of gating units that can be activated, by application thereto of such column group selection signals, to connect respective column lines to the input/output line concerned, and each of the said control inputs is connected to an individual group of the said gating units, which group is made up of just one gating unit from each of the individual sets, thereby to define the group of column lines that is associated with the control input concerned, some of the column lines of that defined group being members also of another one of the said different groups of column lines but being connected to different input/output lines respectively when the control input associated with that other group is selected. In an embodiment of the present invention, since the column groups are not mutually exclusive, individual "nibbles" of data can be selected with greater freedom than in a prior art device. To enhance such freedom of choice, it may be desired to access a "nibble" of consecutive memory cells bridging two different row lines, but it will be appreciated that problems can arise if two row lines of a single matrix are activated simultaneously. To address this difficulty, in a preferred embodiment of the invention the memory cells of the device are arranged in two separate matrices of rows and columns, thereby permitting all the memory cells of a transitional group, some of which are connected with a row line of one matrix and the others of which are connected with an individually corresponding row line of the other matrix, to be accessed simultaneously. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional computer system including a conventional semiconductor memory device: Fig. 2 is a diagram illustrating addresses and operands stored in the addresses; Figs. 3a to 3d are timing charts showing the memory data read operation of the semiconductor memory device shown in Fig. 1; Fig. 4 is a circuit diagram of an address-multiplex type semiconductor memory device embodying the present invention; Figs. 5a to 5d are timing charts showing the memory data read operation of the semiconductor memory device shown in Fig. 4; Fig. 6 is a detailed circuit diagram of parts of the semiconductor memory device shown in Fig. 4; Fig. 7 is a circuit diagram of of a non-address-multiplex type semiconductor memory device embodying the present invention; and Figs. 8a to 8d are timing charts showing the memory data read operation of the semiconductor memory device shown in Fig. 7. Before describing preferred embodiments of the present invention, an explanation will be given of the prior art for reference. Figure 1 is a block diagram of a conventional computer system. The computer system includes a microprocessor 1 and a random access memory (RAM) 2. The microprocessor 1 is an 8 bits type. The RAM 2 consists of eight dynamic-random access memory device chips (D-RAMs) 2-1 to 2-8, each having a 64 K words x 1 bit memory capacity. Figure 2 is a view illustrating addresses in the RAM 2 of Fig. 1, and operands stored in the corresponding addresses. In Fig. 2, each address is defined by four digits, each being hexadecimal format, and thus is formed by 16 bits: A₀ to A₁₅. Note, in general, each digit may contain numerals 0 to 15, however, in this description, numerals 10 to 15 are represented by "A", "B", "C", "D", "E" and "F", for convenient representation as one digit. Each operand has a two digits-hexadecimal format and is formed by 8 bits. However, a complete operand for execution as an operation consists of a plurality of operands, such as a conbination of three operands "BB", "07", and "CD" as shown in Fig. 2. Accordingly, before executing an instruction, the microprocessor 1 must read a plurality of operands forming a complete operand to be just executed from the RAM 2. The above read operation will now be explained with reference to Figs. 3a to 3d. The microprocessor 1 transmits an address signal ADD, consisting of a row-address "3E" stored in bits A16 to A8 and a column-address "C2" stored in bits A₇ to A₀ , to the RAM 2 as shown in Fig. 3C. A D-RAM controller (not shown) provided in the RAM unit 2 transmits an inverted row-address strobe signal RAS , which is part of the control signal shown in Fig. 1, to the RAM 2 as shown in Fig. 3a, in response to the control signal from the microprocessor 1. In response to a trailing edge of the RAS signal, the RAM 2 reads the above row-address "3E" therein. The D-RAM controller also transmits an inverted column address strobe signal CAS , which is also a part of the control signal shown in Fig. 1, to the RAM 2 as shown in Fig. 3b. In response to a trailing edge of the CAS signal, the RAM 2 reads the above column address "C2" therein. In the RAM 2, an access operation is carried out in response to the input address signal of "3EC2", and operand data "BB" stored in the address "3EC2" is output from the RAM 2 as an output data D OUT , as shown in Fig. 3d. After completing the reading of the operand data, the D-RAM controller restores the RAS and CAS signals to a high level state. The above operations can be continuously effected to read the operand data "07" stored in the address "3EC3" and the operand data "CD" stored in the address "3EC4", into the microprocessor 1. The microprocessor 1 then combines the above read operand data and executes an instruction by the combined operand. The above read operation can be applied to a data read and store operation for continuously reading and storing a plurality of consecutive data. As can be understood from the above description, the requirement of a continuous plurality of operation sets for continuous data access, on one hand, results in a simple circuit construction in the computer system, but on other hand, limits high speed access for continuous data access. In the computer system, continuous accessing of a plurality of data upon one access request is required rather than a single data access. Accordingly, the conventional computer system cannot provide a high speed data access. Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Figure 4 is a circuit diagram of an address-multiplex type semiconductor memory device embodying the present invention. In Fig. 4, the semiconductor memory device includes two separate memory cell arrays 3 and 4 each having a 128 x 256 bits capacity, word decoders (row selection means) 5 and 6 cooperating with the memory cell arrays 3 and 4, and address increment circuits 7 and 8 provided at input portions of the word decoders 5 and 6. The semiconductor memory device also includes a column decoder (column group selection means) 9, an input and output (I/O) gate circuit 10 connected between the memory cell array 3 and the column decoder 9, an I/O gate circuit 11 connected between the memory cell array 4 and the column decoder 9, and a shift register 12 connected to the I/O gate circuits 10 and 11 through a data bus 13. The semiconductor memory device further includes a row control circuit 14 and a column control circuit 15. In Fig. 4, the microprocessor and the D-RAM controller are omitted. However, the semiconductor memory device receives an address signal consisting of a row-address (row selection data) expressed by two hexadecimal digits by using bits A₈ to A₁₅ , a column-address expressed by two hexadecimal digits by using bits A₀ to A₇ , an inverted row-address-strobe signal RAS , and an inverted column-address-strobe signal CAS , from a D-RAM controller (not shown). The row-address is supplied to the address increment circuits 7 and 8, and the column-address is supplied to the column decoder 9. The RAS signal is once received at the row control circuit 14 to control a row address system and to generate a plurality of internal timing control signals RAS1 to RAS4 for controlling the word decoders 5 and 6 and the address increment circuits 7 and 8, respectively. The CAS signal is also once received at the column control circuit 15 to control a column address system and to generate a plurality of internal timing control signals CAS1 to CAS4 for controlling the column decoder 9 and the I/O gate circuits 10 and 11. In the following description, to simplify the description, the above RAS1 to RAS4 signals are referred to as the RAS signal, and the above CAS1 to CAS4 signals are referred to as the CAS signal. The semiconductor memory device outputs data to the microprocessor through the shift register 12, when a read access request is received from the microprocessor. On the other hand, the semiconductor memory device inputs data at the Shift register 12 from the D-RAM controller when the microprocessor 1 requests a data store. In the embodiment of Fig. 4, the memory cell array 3 stores data for even row addresses, and the memory cell array 4 stores data for odd row addresses. When the lowest bit A₈ of the row address is low, indicating an even row address, for example when the row address is "3E", the row address "3E" is supplied to the word decoder 5 through the address increment circuit 7 as is, whereby a word line for the memory cell array 3, designated by the row address, i.e. a word address "3E", may be selected. At the same time, the row address "3E" is supplied to the address increment circuit 8 and is added by one therein. The added row address "3E + 1" is supplied to the word decoder 6. A word line for the memory cell array 4, designated by the word address "3E + 1 = 3F" may be selected. Conversely, when the lowest bit A₈ of the row address is high, indicating an odd row address, the above mentioned relation for word line selection is reversed. The operation of the semiconductor memory device will now be described with reference to Figs. 5a to 5d. In the following description, it is assumed that eight memory devices are used to form a memory unit as in Fig. 1, so that operand data as in Fig. 2 can be read out from the unit in accordance with the address as in Fig. 2, though only one memory device is illustrated in Fig. 4. The microprocessor transmits an address signal consisting of a row-address "3E" and a column-address "C2" to the semiconductor memory device, as shown in Fig. 5C. The D-RAM controller transmits a RAS signal to the semiconductor memory device, as shown in Fig. 5a. In response to a trailing edge of the RAS signal, the row address "3E" is received at the address increment circuit 7 and is transmitted to the word decoder 5. Simultaneously, the row address "3E" is received at the address increment circuit 8 and is added by one therein. The added row address "3E + 1 = 3F" is transmitted to the word decoder 6. The D-RAM controller also transmits a CAS signal to the semiconductor memory device, as shown in Fig. 5b. In response to the trailing edge of the CAS signal, the column address "C2" is received at the column decoder 9. In addition, the lowest bit A₈ of the row address is received at the column decoder 9. A word line corresponding to the row address "3E" in the word decoder 5 to the memory cell array 3 and a word line corresponding to the row address "3E + 1 = 3F" in the word decoder 6 to the memory cell array 4 are selected. A bit line to the memory cell array 3, corresponding to the column address "C2" is selected by the column decoder 9 and is connected to one signal (input/output) line of the data bus 13 by the I/O gate circuit 10. The I/O gate circuit 10 also connects a plurality of bit lines, e.g. 3 lines, subsequent to the above selected bit line to a plurality of subsequent data (input/output) lines, e.g. 3 lines, in the data bus 13. As a result, 4 bits of data stored in the address from "3EC2" to "3EC5" are read out in parallel and are stored in the shift register 12. The data obtained from the addressed column "C2" is output as one bit of the data "BB", while the CAS signal is maintained at a low level. Upon completion of this read operation for the data "BB", the D-RAM controller changes the CAS signal to a high level, as shown in Fig. 5b, whereby the one bit read out data of the data "BB" is reset and at the same time the data stored in the shift register 12 is serially shifted from the shift register 12 and received at the microprocessor as read-out data D OUT . In order to obtain the next column address data, the D-RAM controller changes the CAS signal to a low level state, as shown in Fig. 5b. Upon detecting the trailing edge of the CAS signal, the next column address data for "07" is output from the memory device. The succeeding two column data are similarly obtained by repetitively changing the CAS signal. The D-RAM controller then changes the RAS signal to a high level state to terminate the consecutive read operation. Comparing the embodiment with the prior art system set forth before, the embodiment substantially reduces the access time for a consecutive read operation due to the elimination of transmission of the address data and the RAS signal for every read operation from the microprocessor 1 and the D-RAM controller to the semiconductor memory device. By transmitting a first address signal and the RAS and CAS signals for a first read access request and only the CAS signal for the subsequent read access request, the microprocessor reads consecutive data until the RAS signal is changed to a high level state. The microprocessor 1, of course, reads only one set of data in the manner of the prior art shown in Figs. 3a to 3d. The above features of the embodiment can be applied to a data store operation to the semiconductor memory device. In this case, the data to be stored is applied to the shift register 12 from the microprocessor serially as input data D IN , and is stored to the corresponding address in the memory cell array 3 or 4 through the data bus 13, the I/O gate circuit 10 or 11, and the bit lines to the memory cell array 3 or 4. A more specific aspect of the above embodiment referred to in Figs. 4 and 5a to 5d will now be described with reference to Fig. 6. In Fig. 6, memory cell arrays 3 and 4, input and output (I/O) gate circuits 10 and 11, and a column decoder 9 correspond to those of Fig. 4. Other circuit elements shown in Fig. 4 are omitted here. The memory cell array 3 includes a plurality of memory cells MC connected between a plurality of bit lines (Column lines) BL₀ , BL₁ , ..., BL n and a plurality of word lines (row lines) WL₀, WL₂ , ..., WL m , WL m+2 ,... (m: even). The memory cell array 4 also includes a plurality of memory cells MC connected between a plurality of bit lines (further column lines) BL₀ , BL₁ , ..., Bl n and a plurality of word lines (further row lines) WL₁ , WL₃ , ..., WL m+1 , WL m+3 , .... Each four digits-hexadecimal number in each memory cell represents an address thereto. The data bus 13 includes four parallel data lines DB₀ , DB₁ , DB₂ and DB₃. The I/O gate circuit 10 includes a plurality of transfer-gate transistors (gating units) connected between the data lines DB₀ to DB₃ and the bit lanes BL₀ to BL n to the memory cell array 3 and controlled by the column decoder 9. The I/O gate circuit 11 also includes a plurality of transfer-gate transistors connected between the data lines DB₀ to DB₃ and the bit lines BL₀ to BL n to the memory cell array 4 and controlled by the column decoder 9. The column decoder 9 includes a plurality of column decoder units CDU₀ to CDU n provided correspondingly to columns, i.e., bit lines. In addition, the column decoder 9 includes three additional column decoder units CDU n+1 , CDU n+2 , and CDU n+3 . Each of the column decoder units CDU₀ to CDU n and CDU n+1 to CDU n+3 receives the A₈ bit of the address signal representing an odd or even row-address to select the corresponding transfer-gate transistors of the I/O gate circuit 10 or 11. However, the above selection of the additional column decoder units CDU n+1 to CDU n+3 by the A₈ bit of the address signal is the reverse of that of the column decoder units CDU₀ to CDU n , as shown in Fig. 6. When the word address bit A₈ is "0" and the column address is "00", the column decoder unit CDU₀ turns ON, by application thereto of a column group selection signal, a group of transfer-gate transistors made up of the transfer-gate transistor Q₀₋₀₀₋₀ in the I/O gate circuit 10 connected between the bit line BL₀ to the memory cell array 3 and the data line DB₀ , the transistor Q₀₋₀₀₋₁ between the bit line BL₁ and the data line DB₁ , the transistor Q₀₋₀₀₋₂ between the bit line BL₂ and the data line DB₂ , and the transistor Q₀₋₀₀₋₃ between the bit line BL₃ and the data line DB₃ , simultaneously On the other hand, when the word address bit A₈ is "1" and the column address is "00", the column decoder unit CDU₀ turns ON the transistors Q₁₋₀₀₋₀ , Q₁₋₀₀₋₁ , Q₁₋₀₀₋₂ and Q₁₋₀₀₋₃ in the I/O gate circuit 11. In this way, each of the column decoder units CDU₀ to CDU n connects a group of four bit (column) lines including the selected column, for example column "00", connected to the memory cell array 3 or 4 corresponding to the word address bit A₈ , to the corresponding data lines DB₀ to DB₃. The additional column decoder unit CDU n+1 controls the transistor Q 1-FD-3 in the I/O gate circuit 10, connected between the bit line BL₀ to the memory cell array 3 and the data line DB₃ , on the transistor Q 0-FD-3 in the I/O gate circuit 11, connected between the bit line BL₀ to the memory cell array 4 and the data line DB₃ , by the word address bit A₈. The additional column decoder unit CDU n+2 controls the transistors Q 1-FE-2 , i.e. Q₁₁, and Q 1-FE-3 , i.e. Q₁₂ , in the I/O gate circuit 10 or the transistors Q 0-FE-2 , i.e. Q₇, and Q 0-FE-3 , i.e., Q₈ , in the I/O gate circuit 11. The additional column decoder unit CDU n+3 controls the transistors Q 1-FF-1 , Q 1-FF-2 , and Q 1-FF-3 in the I/O gate circuit 10 or the transistors Q 0-FF-1 , Q 0-FF-2 , and Q 0-FF-3 in the I/O at circuit 11. In Fig. 6, note that certain ones of the column decoder units are activated in pairs, i.e. CDU n-2 and CDU n+1 for the column address "FD", CDU n-1 and CDU n+2 for the column address "FE", and CDU n and CDU n+3 for the column address "FF". Accordingly, when, for example, the column address is "FF", the column decoders CDU n and CDU n+3 operate simultaneously. In addition, when the word address bit A₈ is "0", the transfer-gate transistor Q 0-FF-0 in the I/O gate circuit 10 can be turned ON by the column decoder unit CDU n and three transfer-gate transistors Q 0-FF-1 , Q 0-FF-2 , and Q 0-FF-3 in the I/O gate circuit 11 can be turned ON by the column decoder unit CDU n+3 . As can be seen from the above, the additional column decoder units CDU n+1 to CDU n+3 are provided to take a continuation of column addresses from the memory cell array 3 to the memory cell array 4, and vice versa. In order to obtain the continuation of column addresses, a sequence of word lines is also defined alternatively between the memory cell arrays 3 and 4, i.e., as WL m , WL m+2 in the memory cell array 3 and WL m+1 , WL m+3 in the memory cell array 4 in Fig. 6. The operation of the circuit shown in Fig. 6 will now be described. When the start address is "E2FB", that is the word address is "E2" and the column address "FB", and thus the address bit A₈ is also "0", the word line WL (m = "E2") in the memory cell array 3 is selected in response to the trailing edge of the RAS signal. Also, the column decoder unit CDU n+4 is selected in response to the trailing edge of the CAS signal. The transfer-gate transistors Q₁ , Q₂ , Q₃ , and Q₄ in the I/O gate circuit 10, constituting a group of such transistors, are turned ON by the column decoder unit CDU n-4 . The bit lines BL n-4 , BL n-3 , BL n-2 , and BL n-1 to the memory cell array 3, constituting a group of bit lines, are respectively connected to the data lines DB₀ , DB₁ , DB₂ , and DB₃. As a result, data in four memory cell at the addresses "E2FB", "E2FC", "E2FD", and "E2FE" is read from the memory cell array 3 and is stored in the shift register 12, shown in Fig. 4, in parallel. The stored data is serially output to the microprocessor in response to the change of the CAS signal. Consequently, four consecutive pieces of data stored in the above consecutive addresses are read in the microprocessor. When the start address is "E2FE", i.e., the word address is "E2" and the column address is "FE", and accordingly, the address bit A₈ is "0", the word line WL m (m = "E2") in the memory cell array 3 is selected in response to the trailing edge of the RAS signal. The column decoder unit CDU n-1 is selected in response to the trailing edge of the CAS signal. At the same time, the additional column decoder unit CDU n+2 is also selected. The transfer-gate transistors Q₅ and Q₆ in the I/O gate circuit 10 are then turned ON by the column decoder unit CDU n-1 ; the transfer-gate transistor Q₇ , i.e., Q 0-FF-0 , and Q₈ , i.e., Q 0-FE-1 , in the I/O gate circuit 11 are turned ON by the column decoder unit CDU n+2 ; the transistors Q₅ to Q₈ constituting a transitional group of transistors made up of two transistors from the I/O circuit 10 and two transistors from the I/O circuit 11. Accordingly, the final bit lines BL n-1 and BL n in the memory cell array 3 are respectively connected to the data lines DB₀ and DB₁, and the initial two bit lines BL₀ and BL₁ in the memory cell array 4 are respectively connected to the data lines DB₂ and DB₃, the bit lines BL n-1 and BL n of the array 3 and the bit lines BL₀ and BL₁ of the array 4 constituting a transitional group of bit (column) lines. As a result, data stored in the addresses "E2FE" and "E2FF" in the memory cell array 3 is read to the shift register 12 through the data lines DB₀ and DB₁. Simultaneously, data stored in the addresses "E300" and "E301" in the memory cell array 4 is read to the shift register 12 through the data lines DB₂ and DB₃. Consequently, four consecutive pieces of data stored in the addresses "E2FE" and "E2FF" in the memory cell array 3 and "E300" and E301" in the memory cell array 4 are serially read in the microprocessor, in response to the change of the CAS signal. When the start address is "E3FE", i.e., the word address is "E3" and the column address is "FE", and accordingly, the address bit A₈ is "1", the word line WL m+1 (m+1= "E3") in the memory cell array 4 is selected in response to the trailing edge of the RAS signal. The column decoder units CDU n-1 and CDU n+2 are selected in response to the trailing edge of the CAS signal. The transfer-gate transistors Q₉ and Q₁₀ in the I/O gate circuit 11 are turned ON by the column decoder unit CDU n-1 , and the transistors Q₁₁, i.e., Q 1-FE-0 , and Q₁₂, i.e., Q 1-FE-1 , are also turned ON by the additional column decoder unit CDU n+2 , the transistors Q₉ to Q₁₂ constituting a further transitional group of transistors. The bit lines BL n+1 and BL n in the memory cell array 4 are connected to the data lines DB₀ and DB₁ , and the bit lines BL₀ and BL₁ in the memory cell array 3 are connected to the data lines DB₂ and DB₃, the two final bit lines BL n-1 and BL n of the array 4 and the two initial bit lines BL₀ and BL₁ of the array 3 constituting a further transitional group of bit lines. As a result, data stored in the addresses "E3FE" and "E3FF" in the memory cell array 4 is stored in the shift register 12 through the data lines DB₀ and DB₁. Simultaneously, data stored in the addresses "E400" and "E401" is stored in the shift register 12 through the data lines DB₂ and DB₃. Consequently, four consecutive pieces of data stored in the addresses "E3FE" and "E3FF" in the memory cell array 4 and "E400" and "E401" in the memory cell array 3 are serially read in the microprocessor in response to the change of the CAS signal. In the above embodiment, shown in Fig. 6, the address increment circuits 7 and 8 in Fig. 4 are not shown. However, the function of the address increment circuits 7 and 8 set forth before with reference to Fig. 4 is achieved by construction of the word lines WL in the memory cell arrays 3 and 4 and selection of the bit lines BL to the memory cell arrays 3 and 4 using the transfer-gate transistors in the I/O gate circuits 10 and 11, which are turned ON by the column decoder units CDU₀ to CDU n and CDU n+1 to CDU n+3 . In Fig. 6, four bit lines DB₀ to DB₃ are shown and the shift register 12 has a capacity for storing four pieces of data, and thus four consecutive read or write operations may be performed. The number of additional column decoder units is defined as "the number of data lines minus one". Figure 7 is a circuit diagram of a non-address multiplex type semiconductor memory device embodying the present invention. The semiconductor memory device shown in Fig. 7 has a similar construction to that shown in Fig. 4. The semiconductor memory device includes two divided memory cell arrays 3' and 4', word decoders 5' and 6', address increment circuits 7' and 8', a column decoder 9', input and output gate circuits 10' and 11', a shift register 12, and a data bus 13'. The operation of the semiconductor memory device shown in Fig. 7 will now be described with reference to Figs. 8a to 8d. The microprocessor transmits an address signal "3EC2" to the semiconductor memory device. The D-RAM controller changes an inverted chip enable signal CE to low level. In response to a trailing edge of the CE signal, the semiconductor memory device receives the address signal "3EC2" and starts the memory access operation. The D-RAM controller changes the state of an inverted output enable signal OE to low level. As a result, output data "BB" in the address "3EC2" is output as output data D OUT from the shift register 12'. The OE signal is a signal controlling data output operation. When the OE signal is low level, the read data D OUT from the memory cell array 3' and 4' is output. By changing the level of the OE signal between low and high, subsequent data "07" and "CD" is read to the microprocessor. The circuit shown in Fig. 6 may be applied to the semiconductor memory device shown in Fig. 7. Many widely different embodiments of the present invention may be constructed without departing from the scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.

Claims: A semiconductor memory device including: a plurality of memory cells arranged in a matrix (3) of columns, connected with respective column lines (BL) of the device, and rows connected with respective row lines (WL m ,WL m+2 ,...) of the device; row selection means (5) connected for receiving externally-applied row selection data designating a selected one of the said row lines, and operable in dependence upon that data to activate that selected row line; input/output circuitry (10) connected to the said column lines (BL) and having a plurality of control inputs associated respectively with predetermined different groups (BL₀-BL₃,BL₁-BL₄...,BL n-3 -BL n ) of the said column lines (BL); and column group selection means (9) connected for receiving externally-applied selection data (A₀-A₈) designating a selected one of the said control inputs, and operable in dependence upon that data to apply a column group selection signal to the said selected one of the control inputs; the said input/output circuitry (10) including a plurality of input/output lines (DB), equal in number to the column lines of each of the said different groups, and being operable upon receipt of such a column group selection signal to connect the column lines of the particular group that is associated with the selected control input respectively to the said input/output lines (DB), thereby to permit parallel transfer of data bits between the said input/output lines (DB) and those memory cells of the said plurality that are connected with the said selected row line and are also connected respectively with the column lines of the said particular group; characterised in that each of the said input/output lines (DB) is provided with an individual set of gating units (Q) that can be activated, by application thereto of such column group selection signals, to connect respective column lines to the input/output line concerned, and each of the said control inputs is connected to an individual group (for example Q₀₋₀₀₋₀, Q₀₋₀₀₋₁, Q₀₋₀₀₋₂, Q₀₋₀₀₋₃) of the said gating units, which group is made up of just one gating unit from each of the individual sets, thereby to define the group (BL₀-BL₃) of column lines that is associated with the control input concerned, some (for example BL₂,BL₃) of the column lines of that defined group (BL₀-BL₃) being members also of another one (for example BL₁-BL₄) of the said different groups of column lines but being connected to different input/output lines (DB₁,DB₂) respectively when the control input associated with that other group (BL₁-BL₄) is selected. A device as claimed in claim 1, including a further plurality of memory cells arranged in a second matrix (4) of columns, connected with respective further column lines (BL) of the device, and rows connected with respective further row lines (WL m+1 ,WL m+3 ,...) of the device, the said row selection means (5) being operable also to activate a selected one of the said further row lines; and further input/output circuitry (11) connected to the said further column lines and having a plurality of further control inputs associated respectively with predetermined different groups of the said further column lines, the further column lines of each of these groups being equal in number to the said input/output lines (DB); said column group selection means (9) being operable, upon receipt of such selection data (A₀-A₈) designating a selected one of the said further control inputs, to apply a column group selection signal to the said selected one of those inputs; and the said further input/output circuitry (11) being operable upon receipt of that column group selection signal to connect the further column lines of the particular group that is associated with the selected further control input respectively to the said input/output lines (DB), thereby to permit parallel transfer of data bits between the said input/output lines (DB) and those memory cells of the said further plurality that are connected with the selected further row line and are also connected respectively with the further column lines of the last-mentioned particular group; each of the said input/output lines (DB) being provided with a further individual set of gating units that can be activated, by application thereto of such column group selection signals, to connect respective further column lines to the input/output line concerned, and each of the said further control inputs being connected to an individual group of those gating units, which group is made up of just one gating unit from each of the said further individual sets, thereby to define the group of further column lines that is associated with the further control input concerned, some of those further column lines being members also of another one of the said different groups of further column lines but being connected to different input/output lines respectively when the further control input associated with that other group is selected; the row and column group selection means (5,9) being operable selectively to activate both a selected one of the row lines (WL m ) of claim 1 and a corresponding one of the said further row lines (WL m+1 ) and simultaneously to apply such a column group selection signal to a transitional group (Q₅,Q₆,Q₇,Q₈) of the gating units, made up of one or more gating units (Q₅,Q₆) from the said individual sets of claim 1 and one or more gating units (Q₇,Q₈) from the said further individual sets, thereby to cause a transitional group (BL n-1 ,BL n ,BL₀,BL₁) of column lines, equal in number to the said input/output lines (DB) and made up of one or more (BL n-1 ,BL n ) final column lines of the matrix (3) of claim 1 and one or more (BL₀,BL₁) initial further column lines of the said further matrix (4), to be connected respectively to the said input/output lines (DB). A device as claimed in claim 2, wherein each of the said different groups of column lines is made up of four consecutive column lines in the matrix (3) of claim 1, and each of the said different groups of further column lines is made up of four consecutive further column lines in the said further matrix (4); and wherein there are three such transitional groups of column lines made up respectively of the last three consecutive column lines (BL n-2 ,BL n-1 ,BL n ) of the matrix (3) of claim 1 and the first further column line (BL₀) of the said further matrix (4), the last two consecutive column lines (BL n-1 ,BL n ) of the matrix (3) of claim 1 and the first two consecutive further column lines (BL₀,BL₁) of the said further matrix (4), and the last column line (BL n ) of the matrix (3) of claim 1 and the first three consecutive further column lines (BL₀,BL₁,BL₂) of the said further matrix (4). A device as claimed in claim 2 or 3, wherein the row and column group selection means (5,9) are operable selectively to activate both a selected one of the said further row lines (WL m+1 ) of the said further matrix (4) and a corresponding one of the said row lines (WL m+2 ) of the matrix (3) of claim 1 and simultaneously to apply such a column group selection signal to a further transitional group (Q₉,Q₁₀,Q₁₁,Q₁₂) of the gating units, made up of one or more gating units (Q₉,Q₁₀) from the said further individual sets and one or more gating units (Q₁₁,Q₁₂) from the said individual sets of claim 1, thereby to cause a further transitional group (BL n-1 ,BL n ,BL₀,BL₁) of column lines, equal in number to the said input/output lines (DB) and made up of one or more (BL n-1 ,BL n ) final further column lines of the said further matrix (4) and one or more (BL₀,BL₁) initial column lines of the matrix (3) of claim 1, to be connected respectively to the said input/output lines (DB). A device as claimed in claim 4 read as appended to claim 3, wherein there are three such further transitional groups of column lines made up respectively of the last three consecutive further column lines (BL n-2 ,BL n-1 ,BL n ) of the said further matrix (4) and the first column line (BL₀) of the matrix (3) of claim 1, the last two consecutive further column lines (BL n-1 ,BL n ) of the said further matrix (4) and the first two consecutive column lines (BL₀,BL₁) of the matrix (3) of claim 1, and the last further column line (BL n ) of the said further matrix (4) and the first three consecutive column lines (BL₀,BL₁,BL₂) of the matrix (3) of claim 1. A device as claimed in claim 2, operable in such a manner that, as the row selection data is incremented repeatedly by a predetermined value, successively activated row lines are selected alternately from the matrix (3) of claim 1 and the said further matrix (4). A device as claimed in any preceding claim, wherein the said input/output lines (DB) are connected to serial data transfer means (12) operable in response to repeated application thereto of a predetermined control signal (CAS) to accept data bits in succession, for delivery to the said input/output lines respectively during a write operation, or to output data bits, received from the respective input/output lines during a read operation, in succession.

Inventors: TAKEMAE, YOSHIHIRO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G11C8
IPC codes: G11C11, G11C7, G11C8, G06F12, G06F9