CIRCUIT MEANS FOR EVALUATING THE MOVEMENT OF A CODE TRACK OF INCREMENTAL TYPE

Abstract: A circuit means for an encoder apparatus of an incre­ mental-type construction, including: a unit mechanically joined to a movable machine; a unit for outputting at least two signals having a phase shift and a periodic waveform in response to movement of the first unit; a battery-type po­ wer supply; and an electric circuit including a circuit for generating a timing pulse having predetermined frequency and pulse width, a circuit for detecting a change of the signal from the signal outputting circuit and for output­ ting a pulse signal in reponse to the change of signals, and a circuit for counting the pulse signal from the sig­ nal-change detecting circuit.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit means for evaluating the movement of a code track of incremental type. 2. Description of the Related Art Encoder apparatuses are extensively used for position detection in movable machines in numerical control (NC) systems, industrial robot systems, etc. There are two main types of encoder apparatuses: incremental encoder apparatuses and absolute encoder apparatuses. An optical incremental encoder apparatus includes a rotary shaft for connection to a movable work machine whose position is to be sensed and a rotary disk fixed to the rotary shaft and having a light-coding region provided along a circumferential line of the rotary disk. The light-coding region is formed with a plurality of light-intercept portions and a plurality of light-transparent portions or slits. The light-intercept portions and light-transparent portions have the same width along the circumferential line and are alternatively arranged. The incremental encoder apparatus further includes a light-emitting device, such as a light-emitting diode (LED), installed at a position opposing the light-coding region, and light-receiving devices, such as phototransistors or photodiodes (PD), located at another position opposing the light-coding region. The light-receiving devices face the light-emitting device across the light-coding region and slits of a fixed slit member installed between the light-receiving devices and the rotary disk. The encoder apparatus also includes an electric circuit for outputting either an incremental pulse or a decremental pulse as a rotational position pulse in response to signals received from the light-receiving devices. A power source for activating the electric circuit is normally placed in a control unit away from the encoder apparatus. The rotary shaft and the rotary disk rotate in response to movement of the work machine. The light emitted from the light-emitting device is received by the light-receiving devices through one of the light-transparent portions in the light-coding region and the slits in the fixed slit member. The electric circuit outputs an incremental pulse when the rotary shaft rotates in a forward direction and a decremental pulse when it rotates in a backward direction. As clear from the above, incremental encoder apparatuses have simple constructions and a low number of structural elements. This facilitates assembly work and adjustment thereof. On the other hand, incremental encoder apparatuses suffer from the problem that, in the event of a power failure, the electric circuit cannot output incremental or decremental pulses. Despite the power failure, the work machine may still move, resulting in a discrepancy between the position value stored in the control unit and the actual position of the work machine. In such cases, when the power is restored, it is necessary to adjust the encoder apparatus using a reference position before normal operation can be resumed. An optical absolute encoder apparatus includes a rotary shaft for connection to a movable work machine whose position is to be sensed and a rotary disk fixed to the rotary shaft and having a light-coding region. The light-coding region is formed with a plurality of concentric light-coding channels, each with a plurality of light-intercept portions and a plurality of light-transparent portions. Light-intercept portions and light-transparent portions are alternately arranged in each channel, the respective lengths of the intercept and transparent portions being defined by a predetermined relationship depending on the channel position. The light intercept-portions in the outermost channel on the rotary disk are usually equal in length to the light-transparent portions, so that a 1/2¹ division pattern is defined. Similarly, the channel just inside the outermost channel defines a 1/2² division pattern, and so on. The absolute angular position of the rotary disk is determined by the combination of transparent portions on a radial line in all channels. To obtain precise resolution of the angular position, concentric light-coding channels may be provided. The absolute encoder apparatus further includes a plurality of light-emitting devices arranged in a line opposing a radial line of the rotary disk, each device facing a light intercept-coding channel, and light-receiving devices opposing the rotary disk on the other side; each device also facing a corresponding light-emitting device. The encoder apparatus also includes an electric circuit for outputting an angular position signal in an absolute form. Even in the absolute encoder apparatus, a power source is normally placed in the control panel away from the encoder apparatus. Essentially, the signal output from the electric circuit represents the absolute angular position defined by the light received at the light-receiving devices through the transparent portions in the channels. This indicates the angular position of the rotary shaft and facilitates immediate restart after power failure without the troublesome reference position adjustment required in the incremental encoder apparatus. On the other hand, the absolute encoder apparatus has the disadvantages of a complex construction and troublesome assembly, meaning troublesome fine adjustment work. From the document Electrical Design News, Volume 27, Oct. 1982, Number 20, page 187, an arrangement is known, where a shaft is equipped with a position encoder providing in the form of a quadrature waveform information that indicates incremental clockwise or counterclockwise rotation of the shaft. A 2-chip circuit is used for decoding the quadrature waveform and to detect the direction of movement. Details of the position encoder are not given in this document. US-A-4,117,320 discloses a digital measuring instrument producing a continuous digital readout representative of the linear movement of a member positioned by a rotatable shaft. The instrument comprises equally spaced markings formed on an element carried by a bushing intended to be secured to the shaft. Sensing means cooperate with the markings and produce an output pulse in response to the passage of a marking past the sensing means. The output pulses are counted by a reversible digital counter, the count of the counter being displayed by digital display means. The sensing means are duplicated by further sensing means which cooperate with the same markings and which are disposed at a distance corresponding to a 90° phase shift based on the pitch of the associated markings. The output of the pair of sensing means being connected to a circuit which detects the direction of rotation of the markings to control up or downward counting by the counter. In addition to optical encoder apparatus, there are also magnetic encoder apparatus both incremental and absolute. These magnetic encoder apparatus, however, have the same disadvantages as mentioned above. In all prior art encoder apparatus where light-emitting devices are used, they are always energized. Thus, there are the further disadvantages of high power consumption and, thus, a short sevice live of the light-emitting devices. US-A-4,381,446 discloses a photoelectric switch comprising a light projecting segment including a pulse oscillator and a light-emitting element adapted to give a pulse light emission in response to an output pulse of the pulse oscillator, a light reception segment including a light reception element adapted to yield a light reception signal on incidence of light, a gate circuit adapted to gate the light reception signal according to the output pulse of the pulse oscillator and a control circuit for varying the pulse frequency by controlling the pulse oscillator on generation of a light reception signal from the light reception element. In this prior art the pulse frequency is switched between lower and upper fixed values, the lower value being set during a state of no light reception by the light reception element, and the upper frequency being set upon light reception by the light reception element. In this way, the power consumption of the switch is decreased and the degradation of the light-emitting devices prevented while the selectivity which requires a certain frequency value is not impaired. SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit means with reduced power consumption. This object is achieved with a circuit means as claimed in claim 1. According to the present invention, the circuit means may further include a circuit receiving the pulse signal from the signal-change detecting circuit, and generating a timing-pulse frequency control signal in accordance with a change of the received pulse signal with time. In this case, the timing-pulse generating circuit varies the frequency of the timing pulse in response to the timing-pulse frequency control signal. According to the present invention, the circuit means may further include a circuit for detecting illegal pulse generation from the signal-change detecting circuit and correcting the pulse received from the signal-change detecting circuit. This circuit may be provided between the signal-change detecting circuit and the pulse-counting circuit. In this case, the timing-pulse frequency control signal generating circuit temporarily varies the timing-pulse frequency control signal so that a timing pulse having a higher frequency is generated from the timing-pulse generating circuit. BRIEF DESCRIPTION OF THE DRAWINGS Other objectives and features of the present invention will be described below in detail with reference to the accompanying drawings, in which: Figs. 1A to 1C are schematic views of a rotary encoder apparatus; Fig. 2 is a fundamental block diagram of an embodiment of the present invention, Fig. 3 is a detailed circuit diagram of part of the electric circuit shown in Fig. 2; Figs. 4A to 4J are timing charts of the electric circuits shown in Fig. 2; Figs. 5A to 5J are other timing charts of the electric circuit shown in Fig. 2; Fig. 6 is a block diagram of another embodiment of a circuit means in accordance with the present invention Figs. 7A and 7B are timing charts of the electric circuit shown in Fig. 6; Figs. 8A to 8K are other timing charts of the electric circuit shown in Fig. 6; Fig. 9 is a block diagram of still another embodiment of a circuit means in accordance with the present invention; Fig. 10 is a block diagram of a pulse-correction circuit shown in Fig. 9; Fig. 11 is a detailed circuit diagram of the pulse-correction circuit shown in Fig. 10; and Figs. 12A to 12I are timing charts of the electric circuit shown in Fig. 9. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1A is a sectional view of a mechanism of an incremental encoder apparatus. In Fig. 1A, the encoder apparatus 1 includes a rotary shaft 2, mechanically connected to a work machine whose position is to be detected, such as an NC system, and rotatable in response to movement of the work machine, and a rotary disk 7, fixed to the rotary shaft 2 and cooperating therewith. Figure 1B is a plane view of the rotary disk 7. The rotary disk 7 has a light-coding region consisting of a plurality of, for example, 2500, light-intercept portions 72 and a plurality of, for example, 2500, light-transparent portions 71 provided along a circumferential line (shown by dotted line). The width of each light-intercept portion 72 is equal to that of each light-transparent portion. The portions 72 and 71 are alternately arranged, as shown in Fig. 1B. A printed circuit (PC) board 8 is provided at a position opposing the rotary disk 7 a predetermined distance away. A light-emitting device 9, such as an LED, is mounted on one side of the PC board 8 and facing the rotary disk 7 so that the light emitted therefrom (center line of beam emitted therefrom) strikes the light-coding region (center of region), i.e., strikes the dotted line in Fig. 1B. An electric circuit 10 and a battery 11 are mounted on the other side of the PC board 8. The encoder apparatus 1 further includes a base 3 provided at another position opposing the rotary disk 7 a predetermined distance away and having a hole for passage of the rotary shaft 2 therethrough. Two light-receiving devices 4 and 5, such as photodiodes (PD) or phototransistors, are provided on the base 3 and facing the LED 9. A fixed slit member 6 is provided between the PD's 4 and 5 and the light-coding region on the rotary disk 7. Figure 1C is a plane view of the fixed slit member 6. The fixed slit member 6 also has slits as shown in Fig. 1C. The slits face the light-coding region on the rotary disk 7 and allow passage of light from the rotary disk 7 to the PD's 4 and 5. The first PD 4 is arranged to receive the light transmitted through the slits 61 provided at the left side in Fig. 1C, while the second PD 5 is arranged to receive the light transmitted through the slits 62 provided at the right side. The arrangement of the PD's 4 and 5, the slits in the fixed slit member 6, the light coding region of the rotary disk 7 as well as the direction of the light from the LED 9 are defined to obtain signals from the PD's 4 and 5, which have periodic waveforms and a phase difference of approximately 90° ( π / 2 radian), in response to rotation of the rotary disk 7. When the rotary shaft 2 and thus the rotary disk 7 rotates in a forward direction, the signal from the PD 4 is 90° ahead in phase of that from the PD 5. When the rotary shaft 2 and the rotary disk 7 rotate in a backward direction, the signal from the PD 4 is 90° behind in phase from the PD 5. The structure mentioned above with reference to Figs. 1A to 1C is substantially similar to that of the conventional incremental encoder apparatus. Accordingly, the manufacture and assembly work are similar to that of the conventional apparatus. The fine adjustment work is also similar to that of the conventional apparatus. The base 3, the fixed slit member 6, and the PC board 8 are fixed in a housing (not shown). The rotary shaft 2 is rotatably supported on the base 2 by bearings (not shown) arranged in the hole of the base 3. Accordingly, the rotary disk 7 is rotatable between the fixed slit member 6 and the LED 9. The encoder apparatus includes an electric circuit. Figure 2 is a block diagram of an embodiment of the electric circuit of the present invention. In Fig. 2, the electric circuit 10 includes a timing pulse generator or a clock pulse generator 100, a monostable multivibrator 101, discriminating-amplifying circuits 102 and 103, a pulse rising/trailing edge detection circuit 104, OR gates 105 and 106, and an up/down (U/D) or universal counter 107. The pulse generator 100 generates a first clock pulse or a timing pulse CLK₀ having a predetermined frequency as shown in Fig. 4B and activating the LED 9 and the discriminating-amplifying circuits 102 and 103, respectively, connected to the PD's 4 and 5. The multivibrator 101 generates a second clock pulse CLK₁ in response to trailing edges of the clock pulse CLK₀ , as shown in Fig. 4C. The clock pulse CLK₁ is applied to the circuit elements 104 to 107. The discriminating-amplifying circuit 102 consists of a transistor Q₁ with an emitter connected to the ground and a resistor R₁ with one end connected to a collector of the transistor Q₁ and the other end to an output terminal of the pulse generator 100. The discriminating-amplifying circuit 102 is connected to the PD 4 in parallel, i.e., a cathode of the PD 4 is connected to the other end of the resistor R₁ and an anode to a base of the transistor Q₁. An electric output signal generated at the PD 4 normally has a sine-wave form due to the changing amplitude of light emitted from the LED 9, passed through one of light-transparent portions in the rotary disk 7 in rotation and the slits 61 in the fixed slit member 6, and received at the PD 4. However, its signal level is low. Receiving the output signal, the discriminating-amplifying circuit 102 discriminates the voltage level of the output signal with a predetermined voltage level, i.e., a threshold level of the transistor Q₁:V th , and amplifies the discriminated signal to a predetermined logic level, whereby there is provided an A-phase pulse signal SA having a predetermined logic level and a frequency in response to the rotational speed of the rotary shaft 2. Similarly, the discriminating-amplifying circuit 103 consists of a transistor Q₂ and a resistor R₂ and provides a B-phase pulse signal SB also having a predetermined logic level and a frequency in response to the rotational speed of the rotary shaft 2. As mentioned before, there is a 90° phase shift between the output signals of the PD's 4 and 5. Accordingly, there is also a 90° phase shift between the above A- and B- phase pulse signals SA and SB. This will be described later in detail with reference to the explanation of operation of the encoder apparatus. The pulse rising/trailing edge (R/T) detection circuit 104 includes tandem-connected D-type flip-flops (D-F/F) 104a and 104b, tandem-connected D-F/F's 104c and 104d, and a 4-16 decoder 104e for decoding a four-binary-coded-decimal (4-BCD) signal to 16 binary signals. Figure 3 is a detailed circuit diagram of a specific detection circuit 104. In Figs. 2 and 3, the first D-F/F 104a receives the A-phase signal SA at its D-input terminal and outputs an A-phase signal SAl delayed one clock by the clock signal CLK₁ to an input terminal A₀ of the 4-l6 decoder l04e and a D-input terminal of the second D-F/F l04b. The D-F/F l04b outputs an A-phase signal SA2 delayed one clock further to an input terminal A₁ of the 4-l6 decoder l04e. Inverted outputs SA₁ and SA₂ from the D-F/F's l04a and l04b are also applied to the 4-l6 decoder l04e. Similarly, the third and fourth D-F/F's l04c and l04d output B-phase signals SBl and SB2 delayed by three and four clocks from the A-phase signal SAl to input terminals A₂ and A₃ of the 4-l6 decoder l04e and inverted signals thereof SB1 and SB2 to the 4-l6 decoder l04e. The signals SAl, SA2, SBl, and SB2 are weighted to express 4-BCD numbers 0 to l5, i.e., the signal SAl is weighted to 2°(= l) when SAl is high, the SA2 is weighted 2¹ (= 2), the signal SBl is weighted 2² (= 4), and the signal SB2 is weighted 2³ (= 8). The 4-l6 decoder l04e consists of NAND gates Gl, G7, G8, and Gl4 and G2, G4, Gll, and Gl3. The NAND gates are connected to convert a 4-BCD signal into l6 binary signals on the basis of negative logic and a special relationship of signal timing of the signals SAl, SA2, SBl, and SB2 and SA1 , SA2 SB1 , and SB2 , which will be explained later. For example, the NAND gate Gl outputs a binary "l" signal having a low logic level when the input 4-BCD signal is "l". Output signals from the NAND gates Gl, G7, G8, and Gl4 indicate the forward directional rotation of the rotary shaft 2, while output signals from the NAND gates G2, G4, Gll, and Gl3 indicate the backward directional rotation. This will be explained later. As the significant logic levels of the NAND gates Gl to Gl4 are low, in Fig. 3, the OR gates l05 and l06 of Fig. 2 are replaced by NOR gates l05′ and l06′ to output an up- or incremental- and down- or decremental-pulse signals S U and S D having significant, high logic levels. In Fig. 3, there are no gates G3, G5, G6, G9, Gl0, Gl2, Gl5, and G0, since these are not required to output the above signals S U and S D . The up/down (U/D) counter l07 has a predetermined number of bits for counting the light-transparent portions in the rotary disk 7, i.e., 2500 in the embodiment, to directly indicate the absolute angular position for one revolution of the rotary disk 7. The U/D counter l07 increases in position count when the up signal S U is applied to an UP input terminal and decreases in position count when the down signal S D is applied to a DWN input terminal. The battery ll shown in Figs. lA and 2 supplies a direct-current (DC) power to the electric circuit l0, the LED 9, and the PD's 4 and 5. The battery ll may be a lithium battery, an alkaline-manganese battery, or the like in extensive use in industry and is not a special one. The operation of the encoder apparatus shown in Figs. lA to 3 will be explained below with reference to Figs. 4 and 5. First, the operation in the case of forward movement of the work machine will be explained with reference to Figs. 4A to 4J. The rotary shaft 2 as well as the rotary disk 7 are rotated in response to the speed of movement of the work machine. In the embodiment, it is supposed that the maximum rotational speed of the rotary shaft 2 is 2500 rpm. As mentioned above, the number of the light-transparent portions in the rotary disk 7 is 2500. Accordingly, the frequency of the light passing through the light-transparent portions is 50 KHz when the rotary shaft 2 rotates at maximum speed. If the LED 9 were always energized, as in the prior art encoder apparatus, the output signal SA of the discriminating-amplifying circuit l02 would be a pulse and have a 20 µsec period (τ) consisting of 50% high level and 50% low level, as shown by a dotted line in Fig. 4A. In the embodiment of the present invention, however, in order to minimize the power consumption on the battery ll, the power is not always applied to the LED 9 and the PD's 4 and 5. In other words, these devices are activated for the minimum time possible for detecting the rotational position and the rotational direction of the rotary shaft 2. The pulse-generating circuit 100 generates the clock pulse CLK₀ exciting the LED 9 and activating the discriminating-amplifying circuits 102 and 103. The clock pulse CLK₀ has a period t consisting of an on-time t₁ and an off-time t₂ , as shown in Fig. 4B. From the viewpoints of minimum power consumption of the battery 11, the on-time t₁ should be as short as possible. However, it must enable stable operation of the LED 9, the PD's 4 and 5, as well as the electric circuit 10. Considering this, the on-time t₁ is set to 1 µsec. Now, turning to the period t , in order to detect the light received at the PD's 4 and 5, the period t must be equal to or less than the period τ shown in Fig. 4A. In order to detect the rising edge and/or trailing edge of the signals SA and SB for determining the direction of the rotary shaft's rotation, it is necessary to generate four consecutive A-phase pulses and four consecutive B-phase pulses during the time τ. Accordingly, the time t is set to 2.5 µsec. The off-time t₂ is consequently defined as 1.5 µsec. In other words, the frequency of the clock pulse CLK₀ is 200 KHz. The frequency of the clock pulse CLK₁ from the multivibrator 101 is also 200 KHz. This enables a reduction in power consumption in the electric circuit 10, the LED 9, and the PD's 4 and 5. The power consumption in the embodiment may be reduced to 40% that of the prior art apparatus. This enables use of the battery 11 for the above electric elements instead of an external power supply normally placed in the control unit and eliminates the danger of power failure. Accordingly, the count in the counter 107 is never cleared by external power failure and always indicates the absolute rotational position. As the rotary shaft 2 rotates in the forward direction at maximum speed, the PD 4 receives light from the LED 9 through the light-transparent portion in the rotary disk 7 rotating with the rotary shaft 2 and the slits 6l on the fixed slit member 6 in response to on-pulses of the clock signal CLK₀. It outputs four cycles of sine wave signals. Receiving the four cycles of sine wave signals, the discriminating-amplifying circuit l02 outputs of four consecutive A-phase pulses SA as shown in Fig. 4D. Similarly, the PD 5 outputs four cycles of sine wave signal, whereby, the discriminating-amplifying circuit l03 outputs four consecutive B-phase pulses SB as shown in Fig. 4E. Note that a first pulse of the signal SA leads a first pulse of the signal SB by 90° in phase. The D-F/F l04a receives the signal SA, is set by the clock signal CLK₁, and outputs the signal SAl of high level at the Q-output terminal (Fig. 4F) and the signal SA1 of low level at the Q -output terminal. The D-F/F l04b receives the signal SAl, is set with a next clock signal CLK₁, and outputs a high level signal SA2 and low level signal SA2 . The signal SAl retains its high level when the pulses SA are applied to the D-F/F l04a, however, it changes to low level one clock pulse in time after the pulses SA no longer appear. The signal SA2 changes one clock pulse in time later. Similarly, the signals SBl and SB2 are generated as shown in Figs. 4H and 4I. The signals SAl, SA2, SBl, and SB2 as well as their inverted signals SA1 , SA2 , SB1 , and SB2 are applied to the 4-l6 decoder l04e. The 4-l6 decoder l04e, as shown in Fig. 3 in detail, outputs incremental pulses having "significant" low level at the NAND gates Gl, G7, G8, and Gl4 when the 4-BCD of the signals SAl, SA2, SBl and SB2 are "l", "7", "8", or "l4", respectively. On the other hand, the 4-l6 decoder l04e does not output decremental pulses at the NAND gates G2, G4, Gll and Gl3, because the 4-BCD signal is never "2", "4", "ll", and "l3" under forward rotation. The incremental pulses are applied to the UP terminal of the U/D counter l07 through the gate l05 for counting. Next, the operation in the case of backward movement of the work machine will be explained with reference to Figs. 5A to 5J. Figures 5A to 5J are timing charts of the encoder apparatus shown in Figs. 2 and 3 and correspond to Figs. 4A to 4J, respectively. The timing charts in Figs. 5A to 5C correspond to those in Figs. 4A to 4C. As the rotary shaft 2 rotates at maximum speed in the backward direction, the B-phase pulses SB are obtained prior to the A-phase pulses SA. A first pulse of the B-phase pulses SB leads a first pulse of the A-phase pulses SA by 90° in phase (Figs. 5D and 5E). As a result, the signals SAl, SA2, SBl, and SB2 as shown in Figs. 5F to 5I are generated from the D-F/F l04a to l04b and are applied to the 4-l6 decoder l04e. In this case, the down signal S D is output from the NAND gates G2, G4, Gll, and Gl3 in accordance with the timing relationship of the signals SAl, SA2, SBl, and SB2 and the inverted signals thereof and applied to the DWN terminal of the U/D counter l07 through the gate l06. The U/D counter l07 decreases in count in response to the pulse applied to the DWN terminal. As mentioned above, the count number in the U/D counter l07 is updated in response to the application of the up or down signals and indicates a current angular position of the rotary shaft 2, like the prior art absolute encoder apparatus. As clearly understood from the above explanation, the encoder apparatus of the embodiment has the structure of the prior art incremental encoder apparatus, but can provide an absolute-type rotation position signal. In addition, the encoder apparatus can output a rotation number signal by outputting a carry-over or carry-under signal from the U/D counter l07 every predetermined count number corresponding to the number of up or down signal pulses for one revolution of the rotary disk 7. The encoder apparatus can further output a rotation direction on the basis of the up signal S U or the down signal S D . If the U/D counter l07 has a greater number of bits, for example, l6 bits expressing 0 to 65,536 and enabling counting of the entire range of movement of the work machine, the count in the U/D counter l07 can directly indicate the absolute position of the work machine. In this case, a center portion of the work machine movement range may be preset as a center number of the full count of the U/D counter l07. This would facilitate the position adjustment normally required at an initial stage and simplifies the control unit which receives the position signal, since no pulse-accumulating circuit is needed in the control unit. The U/D counter l07 can be easily replaced by a counter, for the up signal, having a predetermined number of bits; a counter, for the down signal, having a predetermined number of bits; and an arithmetic circuit, connected to those counters, for arithmetic operations on the incremental and decremental number counted therefrom, to output the absolute-type rotation signal, the rotational direction signal, and/or the absolute-type position signal of the work machine. To further reduce the power consumption, it is preferable to form the electric circuit by a complementary metal-insulating semiconductor (C-MIS) device. In the above explanation, maximum rotation of the rotary shaft 2 was assured. However, the rotary shaft 2 rotates in response to the movement speed of the work machine and thus frequently is at rest. For example, when the rotary shaft 2 rotates at 600 rpm, the period τ mentioned above with reference to Fig. 4A becomes 40 µsec. This means a clock pulse CLK₀ of 200 KHz frequency is not necessary. The same result as mentioned before, can be obtained by a clock pulse CLK₀ of 100 KHz frequency. Of course, the time t₁ activating the electric elements is maintained as is, i.e., l µsec, and times t and t₂ , are changed to 5 µsec and 4 µsec. Figure 6 is a circuit diagram of another embodiment of the present invention. In Fig. 6, an electric circuit 10' further includes a revolution rate calculation circuit 108 and an OR gate 109. In addition, a clock-pulse generating circuit 100' is replaced by a variable-frequency type. The revolution rate calculation circuit 108 calculates the revolution rate of the rotary shaft 2 on the basis of the time between consecutive up or down signals S U or S D received through the gate 109 and outputs the revolution rate calculated therein to the clock-pulse generating circuit 100'. To improve the reliability of the revolution rate change, an average revolution rate can be obtained. The clock-pulse generating circuit 100' varies in output frequency in response to the revolution rate, the frequency being set to a maximum 200 KHz for a maximum revolution rate and a frequency, for example, 20 KHz minimum for a minimum revolution rate, which may be zero. Figures 7A and 7B are timing charts of the circuit 10'. In Figs. 7A and 7B, the times t', t₁ ′ and t₂ ′ are respectively 5 µsec, l µsec and 4 µsec. The electric circuit 10' contributes to significant reductions in the power consumption. Accordingly, the service life of the battery is significantly extended. In the embodiment shown in Fig. 6, however, there is a slight defect. Figures 8A to 8K are other timing charts of the embodiment in Figs. 6. Figures 8A to 81 correspond to Figs. 4A to 41. Figures 83 and 8K correspond to Figs. 43 and 53. The minimum frequency of the clock pulse CLK₀ is set with a predetermined margin to respond to a normal rotational speed change from low speed, for example, zero speed, to high speed without missing position detection. However, if an unexpectedly large, but short period rotational force, for example, due to a shock, were applied to the rotary shaft 2 when the frequency of the clock pulse CLK₀ were minimum, i.e., when there were no clock pulse CLK₀ or clock pulse CLK₁ for detecting the above signal change in the circuit l04, both the up and down signals S U and S D would rise in parallel, as shown in Figs. 8J and 8K. In the example, the signal S U is formed by a pulse output from the gate Gl and a pulse output from the gate G7, these pulses being continued as one long, high-level signal. The signal S D is output from the gate G4. In this case, the count value in the U/D counter l07 cannot be updated. As a result, error in position detection may arise. Another embodiment without this defect will now be explained. Figure 9 is a circuit diagram of still another embodiment of the present invention. An electric circuit l0″ in Fig. 9 further includes a pulse correction circuit ll0 between the gates l05 and l06 and the U/D counter l07. Other elements in Fig. 9 are similar to the corresponding elements in Fig. 6 and bear the same reference as in Fig. 6. The pulse correction circuit ll0 receives the up and down signals S U and S D and outputs corrected up and down signals CS U and CS D to the U/D counter l07 and an illegal pulse detection signal S ILL to the revolution rate calculation circuit l08. Figure l0 is a circuit diagram of an example of the pulse correction circuit ll0. In Fig. l0, the pulse correction circuit ll0 consists of AND gates l0 and ll, OR gates l2 and l3, an illegal pulse detection circuit l4, a timing detection circuit l5, a direction detection circuit l6, and a correction circuit l7. They are connected as shown in Fig. l0. Figure ll is a more concrete circuit diagram of the pulse correction circuit shown in Fig. l0. In Fig. ll, AND gates l0 and ll and OR gates l2 and l3 are equal to those in Fig. l0. The illegal pulse detection circuit l4 of Fig. l0 is represented by an AND gate l4l and an inverter l42 in Fig. ll. The timing detection circuit l5 is formed by an OR gate l5l. The direction detection circuit l6 is formed by a J-K type flip-flop (J-K F/F) l6l. The correction circuit l7 consists of J-K F/F's l7l to l73, AND gates l74, l75, and l77 to l79, and an inverter l76. They are connected as shown in Fig. ll. Figure ll also shows the revolution rate calculation circuit l08. The operation of the pulse correction circuit ll0 will now be explained. First, the operation in the case of a normal condition will be explained in brief. In this case, as either the signal S U or the signal S D is applied to the pulse correction circuit ll0, the output of the AND gate l4l is low level or "0" level. Thus, an output of the inverter l42 is high level. Accordingly, when the signal S U is applied, the uncorrected up signal S U is output at an output terminal of the OR gate l2 through the AND gate l0 when the signal S D is applied, the uncorrected down signal. S D is output at an output terminal of the OR gate l3. The illegal pulse detection signal S ILL of low level is also applied to the revolution rate calculation circuit l08. The circuit l08 is not subjected to the signal S ILL . In other words, the circuit l08 operates in a normal condition. Next, the correction operation of the pulse correction circuit ll0 will be explained with reference to Figs. l2A to l2I. Figures l2A to l2I are timing charts of the electric circuit l0″ shown in Fig. 9. The A-phase signal SAl (Fig. l2A) leads the B-phase signal SBl (Fig. l2B) by 90° in phase. Thus, these timing charts are of a forward rotation. When an unexpectedly large, but short period rotational force is applied to the rotary shaft 2 while rotating at a low speed, the rotary shaft 2 is abruptly rotated, whereby the light-receiving devices 4 and 5 output high frequency signals. When a change of the A-and B-phase signals SAl and SBl occurs between a time a and a time b as shown in Figs. l2A to l2C, if there were a clock pulse CLK₀ at a time a ′ between the times a and b , the signal-change detection circuit l04 would detect a forward rotation. Actually, the signal-change detection circuit l04, however, cannot discriminate the rotational direction, and thus, outputs both signals S U and S D at the time b (Figs. l2C to l2E). In this case, the output of the inverter l42 in the illegal pulse detection circuit l4 is low, thus neither corrected signals CS U and CS D are output at the time b . On the other hand, the illegal pulse detection signal S ILL becomes high and is applied to the revolution rate calculation circuit l08. The circuit l08 outputs the timing-pulse frequency control signal calling for an increase in the frequency of the timing signal to the timing-pulse generator l00′. The timing-pulse generator l00′ then outputs the timing pulse CLK₀ having a high frequency at a time d in Fig. l2C. Normal forward rotation can be correctly detected in the circuit l04 at a time c in Fig. l2C. In this case, the signal S U is high and the signal S D is low, thereby only a corrected signal CS U is output (Fig. l2H). The occurrence of the two signals S U and S D is stored in the J-K F/F l7l and an F3 thereof becomes high (Fig. l2F). As all inputs of the AND gate l74 are high at the time d , the J-K F/F l72 is set and an output F4 thereof becomes high (Fig. l2G). At a time e , the signal S U remains high level, therefore, the corrected signal CS U is output. As the output of the NOR gate is low, the output of the AND gate is low. Accordingly, the J-K F/F l73 is still reset. At a time f , as the signal S U becomes low level, an output of the OR gate l5l is low due to both signals S U and S D being low, whereby an output of the NOR gate l76 becomes high, an output of the AND gate l77 becomes high, and inputs of the AND gates l78 and l79 become high. On the other hand, as the signal S U was high and the signal S D was low at the time e , the J-K F/F l6l outputs a high level signal at a Q output terminal thereof. Thus, the corrected signal CS U is continuously output, as shown by cross lines in Fig. l2H, through the AND gate l78 and the OR gate l2. In this way, an illegal time is detected at the inverter l76, the occurrence of illegal pulse generation is stored in the J-K F/F s, and the content stored in the J-K F/F s is output in accordance with a direction signal from the J-K F/F l6l. As the output of the AND gate l77 is high, the J-K F/F l73 is set. The output of the AND gate l75 becomes high, whereby the J-K F/F s l7l and l72 are reset. This means illegal pulse processing is completed. After that, the revolution rate calculation circuit l08 can be restored to its normal operation condition. The electric circuits mentioned above with reference to the specific embodiments can also be applied to a magnetic encoder apparatus having an incremental rotation detecting construction. The magnetic-type encoder apparatus includes, for example, a rotary unit, having a rotary shaft joined to the movable machine and a rotary disk mechanically connected to the rotary shaft to cooperate therewith, and a signal output unit, having a plurality of magnetic flux generating members arranged at the circumferential portion of the rotary disk a predetermined distance away and two magnetic flux sensing devices provided at opposing positions of the magnetic flux generating members, both arranged a predetermined distance away from each other.

Claims: A circuit means for evaluating the movement of a code track of incremental type, comprising: means (4, 5, 9) for outputting at least two pulse signals which in response to the movement of the code track are amplitude modulated by a respective modulation signal of a periodic waveform, the modulation signals being phase-shifted with respect to each other; battery-type power supply means (11); and circuit means including means (100') for generating a timing pulse, means (102, 103, 104, 105, 106) for detecting an amplitude change of said signals from said signal outputting means (4, 5, 9) and for outputting, de pending on the direction of movement of the code track, a first or a second pulse signal in response to said change of signals, means (107) for counting up and down said first and second pulse signals, respectively, from the signal-change detecting means, and means (108) re ceiving the signals from said signal-change detecting means and generating a timing-pulse frequency control signal in accordance with a change of the received pulse signal with time wherein said timing-pulse generating means varies the frequency of the timing pulse in response to the timing-pulse frequency control signal. A circuit means according to claim 1, further including means (110) for detecting illegal pulse generation from said amplitude-change detecting means (102-106) and correcting a pulse received from said amplitude-change detecting means provided between said amplitude-change detecting means and said pulse signal counting means (107), wherein said timing-pulse frequency control signal generating means (108) varies temporarily the timing-pulse frequency control signal so that a timing pulse having a higher frequency is generated from the timing-pulse generating means (100'). A circuit means according to claim 2, wherein said pulse correction means (110) includes a illegal pulse detection circuit (14) receiving the first and second pulse signals and outputting an illegal pulse detection signal when both said signals are simultaneously of a significant level, a timing detection circuit (15) for outputting a timing signal when either one of said pulse signals is a significant level, a first AND gate (10) receiving the first pulse signal at one input terminal and the illegal pulse detection signat at another input terminal, a second AND (11) gate receiving the second pulse signal at one input terminal and the illegal pulse detection signal at another input terminal, a direction detection circuit (16) receiving outputs from the first and second AND gates and outputting directions signals, and a pulse correction circuit (17) storing occurrence of the illegal pulses in response to the illegal pulse detection signal and the timing signal and outputting up or down pulse signals in response to the direction signal and due to the stored contents. A circuit means according to claim 3, wherein said pulse correction means includes a first OR gate (12) receiving the output of the first AND gate (10) and the up signal from the pulse correction circuit (17) and a second OR gate (13) receiving the output of the second AND gate (11) and the down signal from the pulse correction circuit. A circuit means according to claim 3, wherein said illegal pulse detection circuit includes an AND gate (141) receiving the first and second pulse signals from the amplitude-change detection means and outputting the illegal pulse detection signal and an inverter (142) receiving the illegal pulse detection signal and outputting an inverted illegal pulse detection signal to the first and second AND gates (10, 11). A circuit means according to claim 3, wherein said direction circuit forms a J-K type flip-flop (161) having an input terminal receiving one of the outputs from the first and second AND gates (10, 11) and another input terminal receiving the other of said outputs. A circuit means according to claim 3, wherein said pulse correction circuit includes a first J-K flip-flop (171) receiving the illegal pulse detection signal at a J-input terminal, a third AND gate (174) receiving an output from a Q-output terminal of the first J-K flip-flop and the timing signal from the timing detection circuit (151), a second J-K flip-flop (172) receiving an output of the third AND gate, an inverter (176) inverting the timing signal, a fourth AND gate (177) receiving an inverted timing signal from said inverter and an output from a Q-output terminal of the second J-K flip-flop, a third J-K flip-flop (173) receiving an output from said fourth AND gate at a J-input terminal, a fifth AND gate (175) receiving an output from a Q-output terminal of said third J-K flip-flop and the output from said fourth AND gate (177) and outputting an output to K-input terminals of the first and second J-K flip-flops, a sixth AND gate (178) receiving one of the direction signals and the output of the fourth AND gate, and a seventh AND gate (179) receiving the other of the direction signals and the output of the fourth AND gate, an inverted output of the second J-K flip-flop (172) being applied to a third input terminal of the third AND gate (174) and a K-input of the third J-K flip-flop (173). A circuit means according to claim 1, wherein said pulse signal counting means (107) comprises a counter for counting the first pulse signal and having a predetermined count capacity, another counter for counting the second pulse signal and having a predetermined count capacity, and an arithmetic circuit connected to said counters for arithmetic operations on the incremental and decremental count therefrom. A circuit means according to claim 1, wherein said battery-type power supply means (11) is a lithium battery. A circuit means according to claim 1, wherein said battery-type power supply means (11) is an alkaline-manganese battery. A circuit means according to claim 1, wherein said circuit means is formed by a complementary metal-insulating semiconductor (C-MIS) device.

Inventors: HIROSHI, ISHIDA, MITSUYUKI, TANIGUCHI
Applicants: FANUC LTD.
Application year: 1985
Main classification: H03M1
IPC codes: G01D5, H03M1