PHASE MODULATED PULSE LOGIC FOR GALLIUM ARSENIDE

Abstract: A logic system preferably for gallium arsenide inte­ grated circuits uses dynamic pulsed logic gates which switch on each clock pulse, with the logical state of an output or data line being indicated by the phase of the pulsed output, which may be shifted or modulated with respect to a reference. An individual logic gate (1) has a first signal generator having a capacitor (30) which is either charged up or discharged during a set-up phase of a clock cycle, depending upon applied input logic signals. During a second, transmit phase of the clock signal, the signal developed on the capacitor is output from the gate. A second signal generator (112 - 131) is an inverting slave of the first, and outputs the inverse logic state during the succeeding set-up phase of the first generator. With each gate switching on every clock period, all switching noise appearing in the ground or power supplies is at or above the clock frequency and can simply be filtered out with small chip capacitors, providing improvements in noise immunity. The logic is preferably implemented in gallium arsenide metal oxide semiconductor technology, with the capacitors formed from reverse-biased Schottky diodes and all FET switches capacitively coupled and self biased.

Description: This invention pertains to the field of electronic digital computers, and specifically to improved high speed electronic logic circuitry for computers. Increased speed of operation has been a constant design goal in the development of digital computer systems, and efforts toward this goal have proceeded on all levels including improvements in central processor architecture, in input/output systems, and in the electronic logic circuits used. At the electronic logic circuit level, improvements over the years in integrated circuits have produced generations of logic circuits having shorter switching times, permitting higher clock speed operation in computers. However, as clock speed and computer system complexity increased, other problems were encountered which tended to limit the maximum speed of operation of computers. The problems of ground or power supply noise and the need for greater density to bring circuits physically closer have limited progress in increasing the speed and size of computers. The problem of ground noise is very serious, particularly for single ended logic gates which use a single conductor connecting the output of one gate to the input of another gate with the common system signal ground as the return path. In high speed operation, the ground at the circuit module level in the immediate vicinity of the integrated circuits may contain a significant amount of noise induced by the switching on and off of numerous nearby logic gates. This ground noise can cause unintended triggering of other gates, which of course cannot be tolerated and which effectively serves to limit the speed of such systems. It is difficult or impossible to filter out the types of ground noise and power supply noise encountered, since some of it is due to groups of circuits which may switch rather infrequently, i.e. only after a large number of clock pulses, which introduces a low frequency component to the noise which is very difficult to filter out, especially at the chip or module level. A related problem with prior art systems is difficulty in power supply regulation due to surges in demands as groups of devices switch. Ground return noise can be alleviated by using logic circuits which provide an output and its complement, requiring a pair of conductors to run from each gate to the input or inputs of a succeeding gate or gates. This greatly alleviates the ground return noise problem, although noise introduced through power supplies due to the low frequency component referred to above are still encountered. But the use of logic having a signal and complement creates a density problem, in terms of the number of pins available at the chip or module level, and the circuit board space required for all the conductors. This in turn leads to a physically larger computer with longer than desired path lengths between logic circuits. A related density problem with present-day designs is the relatively inefficient use of chip and circuit board space because of the need for a great number of latches. Present-day systems, which might be termed loosely synchronous, provide a number of levels of logic between successive latches. Typically eight levels of static logic gates may be interposed between successive clocked latches, although a greater or less number may be used. In such systems the clock period must be slow enough to ensure that the logic signals will propagate through the intervening levels of static gates to the next latch in time for the next clock pulse. It would therefore be desirable in terms of shortening the clock period to have more latches with fewer levels of static logic gates between them. However, each latch circuit typically will take up as much space as four or more static logic gates, and their financial cost is also proportionally higher. Therefore a compromise must be made as to numbers of latches and numbers of levels of static logic between them, and the clock period then must be made slow enough to allow for the required settling and propagation time between latches. In contrast to the above-described prior art computer logic systems, which might be termed static or direct coupled, loosely synchronous logic, some embodiments of this invention can be designed so as to provide dynamic pulsed logic that is tightly synchronous and which provides improvements in terms of operating speed, noise immunity and packing density. Embodiments of the present application can use Manchester Code which is primarily used in magnetic tape formats. In this code a half bit time positive pulse followed by a half bit time negative pulse represents one state and the reverse represents the opposite state. According to one aspect of the invention, there is provided a logic gate comprising a plurality of logic inputs to which input logic signals are to be applied, a logic output for outputting a signal which is a function of input logic signals applied to the logic input, and circuit means interconnecting said inputs and the output and controllable by clock pulses (A,B) defining a clock period having first and second portions, characterised in that the circuit means include means to switch the state of the output signal at the transition region from the first to the second portions of a clock period so that the output signal in said transition region is positive or negative going in dependence upon said function of the applied input signals. Some embodiments of the present invention can advantageously be implemented in gallium arsenide metal oxide semiconductor integrated circuits. In certain embodiments having a plurality of logic gates, each logic gate and its output signals are switched on each clock pulse, with the logical state of a signal being evidenced not by a "high" or "low" signal, but instead by the modulation or shifting of the phase of the pulse output signal with reference to the clock signal or some other pulsed reference signal. Logic signals are capacitively coupled to the inputs of gates rather than being direct coupled, which improves noise immunity. Further, since all gates switch at the clock frequency on all clock pulses, the noise present in the ground and power supplies is at the clock frequency with no lower frequency components, and the high clock frequency noise can easily be trapped and filtered by small filtering capacitors at the power pins of individual integrated circuits. The logic gates may also include a pair of signal generators each having a capacitor which is used to hold a signal level during a half cycle of the clock. During a first half period of a clock cycle, termed the set-up phase, the capacitor of the first signal generator is charged or discharged, depending upon logic signals applied to a diode input network which serves to bias a charging path for the capacitor according to the applied input signals. During the second half cycle of the clock period, termed the transmit phase, the signal thus developed on the capacitor is output to the logic output of the gate. Simultaneously the second signal generator develops on its capacitor a signal which is the inverse of the signal previously developed by the first signal generator, and that inverse signal is subsequently output to the logic output of the gate during the set-up phase of the succeeding clock period. In this manner the logic gate switches output during every clock period, but whether the output is "high" or "low" during its transmit phase is a logical function of the applied logic inputs. Thus during operation the gate continues to alternate its output signal between high and low states, but the phase of the pulsing output signal will be modulated, or shifted, with reference to the clock signal, as a logical function of the applied input signals. According to the logic system of embodiments of the present invention, no latch circuits in the conventional sense are required, both the latches and intervening levels of static gates of the prior art being replaced by dynamic pulsing gates. Thus the clock can be made very fast, since there are no intervening levels of static logic between clocked gates. A disadvantage of this system is the requirement for providing signals to each gate, but the advantages of higher speed, noise immunity and greater packing density far outweigh that disadvantage A further advantage of certain embodiments of the present invention is that since each gate switches on every clock pulse, all gates continually operate at a fifty percent (50%) duty cycle, which means that they can be designed physically smaller in terms of power dissipation. With prior art systems, since any particular gate or latch might remain in one state for a long period of time, all circuits had to be designed for one hundred percent (100%) duty cycle operation in terms of power dissipation. The fifty percent (50%) duty cycle operation results in a further reduction in size. A related advantage is in terms of simplification of power supply systems for a computer using the logic system of the present invention. Since all circuits switch on every clock pulse, the demands on the power supplies are predictable and uniform, and are not subject to sudden surges as in prior art systems when a large number of gates switch after a period of relative quiet. For a better understanding of the present invention and as to how the same may be carried into effect, reference will be made, by way of example, to the accompanying drawings in which:- Figure 1 is a schematic circuit diagram of a logic gate; Figure 2 is a graph of signal waveforms illustrating the operation of the circuit of Figure 1; FIGURE 3 is a schematic drawing of a portion of the circuit of FIGURE 1 illustrating inter-electrode capacitances associated with a FET; FIGURE 4 is a schematic diagram of a portion of the circuit of FIGURE 1 illustrating the self biasing of a FET; FIGURE 5 is a graph of characteristic curves of a FET in the embodiment of FIGURE 1; and FIGURE 6 is a schematic drawing showing the use of filtering capacitors in an integrated circuit using the logic gates of FIGURE 1. Referring now to FIGURE 1, a logic gate according to the present invention is shown in schematic form. Preferred forms of the invention are of course in integrated circuits, and it will be understood that the use of symbols for discrete components in FIGURE 1 is only for purposes of illustration of the operation of the gate. As illustrated in FIGURE 1, the gate has a group of logic inputs, identified by reference numbers 11a through lld. In addition, although not shown in FIGURE 1, additional groups of inputs could be provided as explained more fully hereinafter. Logic input 11a connects to the anode of a diode 12a, whose cathode connects to a conductor 13. In similar manner, logic inputs 11b, 11c and 11d connect through diodes 12b, 12c, 12d, respectively, to conductor 13. A switchable current path is established from conductor 13 to the negative power supply voltage, - V, through resistor 14 and field effect transistor (FET) 15. The source of FET 15 connects to - V, and the drain to resistor 14. A control signal "B", explained furtherbelow, is applied to the gate of FET 15. A capacitor 30 is provided, which is formed as a reverse-biased Schottky diode. One terminal of capacitor 30 connects to signal ground, and the other terminal connects to a conductor indicated by reference number 25. A diode 20 is connected for conducting current from conductor 25 to conductor 13. Three other diodes, 21, 22 and 23, are indicated in FIGURE 1 as having their anodes connected to conductor 25. Although not shown in the drawing, each of these diodes 21-23 can support an additional four inputs and a current path to -V in the same manner that diode 20 supports inputs 11a-11d, along with the current path 14, 15 to -V. These additional inputs and their current paths to -V have been omitted from FIGURE 1 for purposes of simplicity of the figure and clarity of explanation. A current path from +V, the positive voltage power supply, to conductor 25 is established through resistor 27 and diode 26. A further diode 28 connects from the junction of resistor 27 and diode 26 to the drain of an FET switch 29, whose source connects to -V. A control signal "A", explained below, is connected to operate the gate of FET 29. A branch of conductor 25 is connected to a gate of a further FET 31, whose source connects to signal ground, and whose drain connects to conductor 40. A second gate for FET 31 receives control signal "A". Although drawn as a dual gate FET, FET 31 can be implemented as two FETs connected in series. A branch of conductor 40, which is preferably shielded, connects as the logic output terminal 41. The circuit thus far described, from logic inputs 11 through FET 41, can be thought of as a first, or phase A, signal generator. A second, or phase B, signal generator is also provided, comprising com ponents 112 through 131. The second signal generator is substantially identical to the first one, and the corresponding components are identified by corresponding reference numbers with a 100 prefix. Thus, diode 112 corresponds to one of the diodes 12, conductor 113 corresponds to conductor 13, etc. Control signal "A" connects to the gate of FET 115, which connects through resistor 114 to conductor 113. Control signal "B" connects to the gate of FET 129, which connects from diode 128. Resistor 127 and diode 126 connect in series between +V and conductor 125. The anode of diode 128 connects to the junction between resistor 127 and the anode of diode 126. Capacitor 130 is provided, analogous to capacitor 30 of the first signal generator, and has one terminal connected to signal ground and the other terminal connected to conductor 125. Diode 120 connects from conductor 125 to conductor 113. Dual gate FET 131 has its source connected to signal ground, and its drain connected to a branch of conductor 40 and logic output terminal 41. One gate is controlled by conductor 125, and control signal "B" is applied to the other gate of FET 131. The control signals A and B are square waves, both having the same period as the clock but having opposite phase to each other so that when A is high B is low and vice versa. During a first phase of a clock period, which is termed the set-up phase, control signal B goes up to turn on FET 15, and control signal A goes down to turn off FET 29. With FET 29 off, the path through diode 28 is cut off, and a current path is established through resistor 27, diode 26, diode 20, resistor 14 and FET 15. The current path in the preferred embodiment delivers approximately one milliamp through resistor 27 and approximately two milliamps through resistor 14. However, the operation of the current path is altered depending on the data input at terminals 11a-11d. Capacitor 30, which connects to the current path at conductor 25, is either charged up at approximately one milliamp or charged down at approximately one milliamp, depending upon the data input, logic zero or logic one, applied through the inputs to conductor 13. The charging up or charging down of capacitor 30 takes place during the set-up phase, after which control signal B goes down to turn off FET 15, and control signal A goes up to turn on FET 29. This causes both diodes 20 and 26 to be back biased to isolate capacitor 30 from the current path. If additional input circuits are present, connecting through diodes 21-23 as described above, they are also back biased by the cutting off of their current paths corresponding to FET 15. During this phase, termed the transmission phase, capacitor 30 is isolated and serves as a memory for the voltage developed in the previous phase. The control gate to FET 31 goes up and the gate is enabled or not, depending on the control voltage existing at capacitor 30. The phase B generator operates in the same manner described for the phase A generator, but on the opposite half cycle, so that the logic level being output by FET 31 during the transmission phase is applied through input diode 112 to cause capacitor 130 to charge up or down depending on the value being input. At the end of this transmission phase, the next set-up phase begins and the switching of the control signals A and B causes diodes 120 and 126 to be back biased and the value thus developed at capacitor 130 is output through FET 131 to the logic output terminal 41. The process is repeated each clock cycle, with the phase A generator developing a signal during the set-up phase that is a logical function of the applied input signals, then transmitting the developed signal during the transmission phase, while the phase B generator develops the inverse thereof which is applied to the gate output during the set-up phase of the next succeeding cycle. The logic output signal at output 41 thus alternates every clock cycle, but the phase of the signal is modulated, i.e. may be shifted or reversed, as a logical function of the applied logic input signals. Specifically, it will be noted that the application of input signals through diodes 12a-12d serve a logical AND function at the junction, conductor 13. If more than one such input groups and current paths are provided through diodes 20-23, a logical OR function is provided at the junction of diodes 20-23, at conductor 25. It will be appreciated that these diodes are used for control of the current charging paths anyway, so the AND and OR logic functions in a sense come free without cost of additional components. Not all sixteen inputs may be required for specific applications, and if not needed some can be deleted as permitted by an overall logic design in order to simplify the circuit. FIGURE 2 is a waveform showing the alternating and phase modulated logic signals used by and output from a gate such as that in FIGURE 1. Specifically, the upper waveform, identified as "clock", shows an alternating square wave clock signal, having phases marked A and B, a complete cycle of which corresponds to a clock period. Three clock periods are shown, identified as C1, C2, and C3. The second waveform identified as "data" illustrates the modulating, or phase shifting of a waveform to illustrate the two different logic states. During the clock period C1, the data waveform matches the clock waveform, in both A and B phases thereof. During clock period C2, the data waveform has shifted or reversed its phase, so that it is of the opposite phase from the clock waveform. This represents the opposite logic state of the data from what it was in clock interval C1. In clock interval C3, the data waveform has returned to the same logical state as in C1. Thus, it can be seen that while a data stream continues to switch output levels during each clock period, the phase of a data waveform during a clock period may be the same as, or the reverse of, a reference signal to thereby represent the two logical states of the data signal. As previously mentioned, the preferred implementation of the logic system of the present invention is in gallium arsenide metal oxide semiconductor integrated circuits. This invention is well suited to realize the full potential speed of gallium arsenide devices, which speed cannot be fully realized with loosely synchronous static logic gates for the reasons outlined in the background section above. All capacitors are formed of Schottky diodes, and care should be exercised to maintain the bias on all Schottky diodes used as capacitors either at a negative voltage, or up to three-fourths of a volt positive. Above that voltage, of course, the diode is forward biased and the desired capacitance effect would be lost. The large capacitor in each cell, corresponding for example to capacitor 30 of FIGURE 1, takes up a considerable amount of the available area of an individual logic cell, for example thirty percent (30%). When considering high speed operation of devices it is necessary to consider the effect of inter-electrode capacitances. FIGURE 3 illustrates a capacitor 230, which would correspond to capacitor 30 of FIGURE 1, connected to conductor 225 which is connected to the gate of a FET 231, corresponding to FET 31 of FIGURE 1. In addition, inter-electrode capacitances 232 between the drain and gate, and inter-electrode capacitance 233 between the gate and source are also shown. These inter-electrode capacitances are inherently present in high speed operation of the device, and are usually considered undesirable as they limit high speed operation. In fact, inter-electrode capacitance 232 should be minimized as it does tend to slow down the operation of the device. However, an advantage of the logic gate of the present invention is that gate-source capacitance 233 is actually helpful. This is because it is in parallel with large capacitor 230, so that the effect of gate-source capacitance 233 is to reduce the amount of space required for capacitor 230. A property of this type of FET, which is used to advantage in this invention, is that gate-source capacitance 233 is present in larger amounts at an approximately four to one ratio over drain-gate capacitance 232. The layout of the FETs such as FET 231 can therefore be made to actually increase inter-electrode capacitance 233 without harm to circuit operation. FIGURE 5 shows typical drain current versus drain-source voltage at different gate-source voltages for a typical gallium arsenide FET in the circuit. Signal amplitude and device biasing should be adjusted to switch the gates of FETs between zero volts and the pinch-off voltage, which is approximately -2 volts in the example shown. If the voltage applied to a gate exceeds zero volts, it becomes a forward-biased Schottky diode and takes current and clips the waveform. On the other hand, if the voltage fails to go as low as the pinch-off voltage, the FET may not completely cut off the current as desired. To further compli cate matters, the pinch-off voltage may well vary for individual FETs across different zones of the integrated circuit due to tolerances and processing variables in the manufacturing process. For these reasons a self biasing technique is adopted for all FETs. This is suggested in FIGURE 4, which shows an individual FET 250. At a microscopic level, each FET has a capacitance 251 at the input to its gate. Thus, all input signals to FETs such as a signal applied at conductor 252, will be capacitively coupled to control the gate of the FET. A large bias resistor 253 is provided between the gate and source of FET 250. In reality, there is always a certain amount of Schottky diode leakage, indicated by arrow 254. This current, passing through resistor 253, and in conjunction with the input capacitance 251, establishes a bias for the gate which automatically adjusts to self regulate for bias level, i.e -V or ground as the normal state. Further, the self biasing technique always centers the device to compensate for variations in manufacturing tolerances in the characteristic curves for a given FET over the extent of the chip. As previously mentioned, a logic network or computer using the logic system of the present invention has all logic data lines and gates switching on each clock period, as illustrated in FIGURE 2. Thus, all switching noise reflected in the ground or power supplies will be at the clock frequency or higher, but there will be no lower frequency components to the switching noise, as is the case in direct coupled loosely synchronous logic, where a significant group of gates might switch simultaneously after having been quiet for a large number of cycles, thus introducing a low frequency component to the switching noise. In the present invention, since the switching noise is all high frequency, it can be simply filtered by chip capacitors as indicated in FIGURE 6. In FIGURE 6, reference number 260 indicates an integrated circuit using the logic system of the present invention. Small chip capacitors 261 and 262 are connected between the +V and ground, and -V and ground power supply pins, respectively, at the chip level. These chip capacitors filter out the high frequency switching noise that may be present on the power supplies and ground leads, thus preventing unwanted noise from affecting circuit operation. A related advantage of this invention is simplification of power supply regulation problems. Since all circuits switch on every clock cycle, the demand is uniform and predictable and sudden surges are eliminated. From the foregoing description it will be appreciated that the present invention provides a logic system using phase modulated pulse logic, that takes advantage of the speed potential of gallium arsenide integrated circuit technology, and provides improvements in packing density, speed and noise immunity over prior art logic systems.

Claims: A logic gate comprising a plurality of logic inputs (11a-11d) to which input logic signals are to be applied, a logic output (41) for outputting a signal which is a function of input logic signals applied to the logic input, and circuit means (12-40,112-140) interconnecting said inputs and the output and controllable by clock pulses (A,B) defining a clock period having first and second portions, characterised in that the circuit means include means (31, 131) to switch the state of the output signal at the transition region from the first to the second portions of a clock period so that the output signal in said transition region is positive or negative going in dependence upon said function of the applied input signals. A gate as claimed in Claim 1, wherein said circuit means includes: first and second signal generators (13-31 and 113-131 respectively), each operative when enabled to develop a logic signal in response to an input logic condition and operative when inhibited to hold the previously developed logic signal and apply it to the logic output of the gate; and means (31) coupling said second generator to said first signal generator to cause the second signal generator when enabled to develop a logic signal which is the inverse of the developed logic signal of said first signal generator. A logic gate as claimed in claim 2, and comprising switching and control means (15, 29, 115, 129) operative in a first clock period portion to enable said first signal generator to develop a logic signal that is a function of the input logic condition and to inhibit said second signal generator to cause it to output to the logic output (41) a previously developed logic signal and operative in a second clock period portion to inhibit said first signal generator to cause it to output to the logic output its logic signal developed in the immediately preceding clock period portion and to enable said second signal generator to cause to develop a logic signal which is the inverse of the logic signal of the first signal generator. A gate as claimed in claim 2 or 3, wherein at least one of said signal generators comprises: capacitance means (30,130); charging circuit means (14,15,20,26,27 or 114, 115, 120, 126, 127) responsive to the input logic condition and the clock pulses to be enabled in one clock period portion to charge or discharge said capacitance means according to the input logic condition and to be inhibited in the subsequent clock period portion to transmit to its logic output, as an output logic signal, the signal developed at said capacitance means. A gate as claimed in claim 4 wherein said capacitance means is a reverse-biased Schottky diode. A gate as claimed in claim 4 or 5, wherein said charging circuit means comprises a circuit portion connecting a supply point of first potential to said capacitance means and comprising a sequence of a resistor (27,127) and an isolation diode (26,126). A gate as claimed in Claim 6 wherein said charging circuit comprises a sequence of a second isolation diode (20,120), a resistance (14,114) and a first switch (15,115) connecting said capacitance means to a supply point of second, opposite, potential, the point at which the input logic condition occurs being coupled to the junction between the second isolation diode and said resistance. A gate as claimed in claim 6 or 7 and comprising a mode switching diode (28,128) connected by a second switch (29,129) to a supply point for said second potential, said mode switching diode being connected to said isolation diode (26,126) and operative when said second switch is turned on to back bias said isolation diode (26,126). A gate as claimed in claim 7 or 8, wherein at least one of said first and said second switch is an FET switch. A gate as claimed in any one of claims 3 to 9 wherein said means for switching state comprises a FET switch (31,131) having a first control electrode coupled to said capacitance means (30,130) for control by the voltage on said capacitance means and a second control electrode coupled to receive a clock control signal for selectively enabling and inhibiting the output of said FET switch. A gate as claimed in any one of the preceding claims, including diodes (12a-d) connecting each of said logic inputs to an input summing point (13). A gate as claimed in any one of the preceding claims and including means for the generation of said clock pulses defining contiguous and substantially equal clock period portions. A gate as claimed in claim 2, or any one of claims 3 to 12 claim when appended to claim 2, wherein said first signal generator includes a further plurality of logic inputs, whereby a logic OR function between the two groups of inputs is performed. A gate as claimed in claim 13, when appended to claim 4 or any one of claims 5 to 12 when appended to claim 4 wherein said further plurality of logic inputs are coupled to said capacitance means (30). A gate as claimed in claim 14, when appended to claims 6 or when appended to any one of claims 7 to 12 when appended to claim 6 and including further charging circuit means comprising a third isolation diode, a further resistance and a FET switch connecting said capacitance means to said second, opposite, potential supply point; the point at which a second input logic condition occurs being coupled to the junction between the third isolation diode and said further resistance. A logic gate as claimed in any one of the preceding claims wherein said gate is a gallium arsenide integrated circuit. A logic circuit comprising a plurality of gates as claimed in any one of Claims 1 to 16.

Inventors: CRAY, SEYMOUR
Applicants: CRAY COMPUTER CORPORATION
Application year: 1985
Main classification: H03K19
IPC codes: H03M5, H03K19, G06F7