TRANSISTOR INVERTER INTERLOCK CIRCUIT

Abstract: In an inverter (8), power switches (Q1, Q6) are connected in series across a DC source (EA, EB) and are operated in alternate fashion to produce an AC output at the junction between the switches. Occasionally, however, a condition known as ''shoot-through'' may occur wherein both switches are momentarily closed, resulting in short-circuiting of the DC source and/or destruction of the switches. This problem is solved by an interlock circuit (30) according to the present invention which prevents simultaneous conduction of first and second complementary power switches (Q1, Q2) connected in series across a voltage source. The circuit includes means (LED1, LED2) coupled to one of the power switches for generating a gating signal when the voltage across two of the electrodes (Q1B, Q1E or Q2B, Q2E) of the power switch indicates that such switch is off and means (Q7, Q8, 40, 44, PT1 or Q9, Q10, 50, 54, PT2) responsive to such signal for inhibiting turn-on of the complementary power switch until the gating signal is generated.

Description: Transistor Inverter Interlock Circuit Description Technical Field The present invention relates generally to pro- tection circuitry for power switches and more particular¬ ly to a circuit for preventing simultaneous conduction of series-connected power switches in a leg of an inverter. Background Art Transistorized power inverters typically in- elude one or more inverter legs coupled to a DC power source. Each leg includes a pair of switches which are alternately operated to connect the junction therebetween to the voltages developed by the DC source to in turn . "* . produce an alternating phase output. In such an inverter, it is important that one of the power switches is fully turned off before the other is turned on to prevent shorting of the DC power source. Such a condition, commonly called "shoot- through" or "cross conduction" can result in a degrada- tion of the output waveform or even destruction of one or both of the transistors. One prior attempt at minimizing the possibility of shoot-through in an inverter circuit is disclosed in Stobbe et al U.S. Patent No. 4,126,819. This patent dis- closes the use of current sensors, such as resistors, coupled in series with the emitter electrode of each of a plurality of power transistors. The voltage across each current sensor is coupled through a driver circuit to the base of the complementary transistor in the inverter leg so that one transistor is maintained in an off condition while the other transistor is conducting current above a specified level. Other patents disclosing circuits for maintain¬ ing one transistor in an inverter leg in an off condition until a specified condition is reached by a complementary transistor in the inverter leg are Gritter U.S. Patent No. 4,371,824; Rosswurm et al U.S. Patent No. 4,342,076; and Kelleher U.S. Patent No. 3,828,208. None of the above-noted patents discloses a completely satisfactory circuit for preventing cross con¬ duction or shoot-through. For example, the use of a re¬ sistor as a current sensor in the collector-emitter cir¬ cuit of the Stobbe et al patent reduces the maximum switching frequency which _ca-n be attained and results in an undesirable power loss. Further, the current sensors undesirably affect the ability of a snubber circuit con¬ nected across the collector and emitter electrodes of each power transistor to dissipate transient^ caused b.y switching of the transistors. The prior art does not disclose a circuit for preventing shoot-through or cross conduction which allows relatively fast switching rates and which does not in¬ crease transient dissipation. The prior art also does not disclose a circuit which provides a -minimum delay between turn-off of one transistor and turn-on of the complementary transistor. Disclosure of the Invention In accordance with the present invention, an interlock circuit for preventing simultaneous conduction of series-connected complementary power switches in an inverter leg includes means for generating a gating sig¬ nal when the voltage across two electrodes of one power switch reaches a selected level indicative of turn-off of such switch and means for inhibiting turn-on of the com¬ plementary switch until the gating signal is generated. More particularly, first and second complemen- tary power transistors includes main current path elec¬ trodes which are connected in series across first and second voltages provided by a DC voltage source. Each power transistor is controlled by drive circuitry which includes first and second inputs. The first input re- ceives one of two complementary drive signals while the second input is coupled to an LED which is connected across the base-emitter junction of the complementary power transistor. A phototransistor in the base drive circuitry receives the output of the LED and develops a signal when the complementary power transistor is com¬ pletely off. The phototransistor is coupled to gating means which operates .the power transistor in accordance with the base drive signal when the phototransistor sig¬ nal is developed. The above-described circuitry is effective to prevent shoot-through without interposing a substantial delay between turn-off of one transistor and turn-on of the complementary transistor. Hence, the introduction of harmonics in the output is minimized. Furthermore, the interlock circuit of the pre¬ sent invention does not require the use of circuit ele¬ ments in the collector or emitter circuits of the power transistors. This, in turn, minimizes the effect on the transient dissipating ability of snubber circuits con- nected across the collector-emitter circuits of the tran¬ sistors. Further, the present invention does not utilize circuit components which dissipate large amounts of power. Brief Description of the Drawings Fig. 1 is a simplified schematic diagram of a typical inverter output stage with which the interlock circuit of the present invention may be utilized; Fig. 2 is a series of waveform diagrams illus¬ trating the operation of a prior art interlock circuit; Fig. 3 is a schematic diagram of the interlock circuit of the present invention in conjunction with one of the legs of the inverter shown in Fig. 1; and Fig. 4 is a set of waveform diagrams illustrat¬ ing the operation of the circuitry shown in Fig. 3. Best Mode for Carrying out the Invention Referring now to Fig. 1, a typical inverter output stage 8 includes six transistors Q1-Q6 connected in a three-phase bridge configuration across a pair of rails 10,12. The rails 10,12 are in turn coupled to a source of DC power comprising DC power sources 14,16 which develop DC voltages E and E , respectively. A pair of capacitors C1,C2 are coupled across the rails 10,12, with the junction between the capacitors being connected to a neutral point 18 comprising the junction between the DC sources 14,16. Connected across each of the collector and emitter electrodes of the transistors Q1-Q6 is a free- wheeling diode D1-D6, respectively. -Also connected across each collector-emitter circuit is a snubber (not shown) for dissipating transients. The switches in each leg of the inverter are alternately operated to connect the junction therebetween to either of the rails 10 or 12 to produce an alternating output voltage V A ' V B' V C ' Tnese voltages are in turn cou¬ pled through filters comprising inductors L1-L3 and capa- citors C3-C5 to individual phases of a load represented by phase impedances Z τ i_A.,Z τ J_u__>,Z τ J_ι r (_, ; respectively. Fig. 2 illustrates the operation of a prior art circuit for preventing simultaneous conduction of series- connected power switches, such as the switches Ql and Q2 shown in Fig. 1. At t = t, , base drive current is applied to the base electrode of the transistor Ql. The current in the collector of the transistor Ql then begins to increase with a rise time t RISF representing the time required for the collector current to increase between particular val¬ ues, such as 10% to 90% of the final value. The voltage across the base-emitter junction of the transistor Ql also rises during this time to a specified value, such as one volt. A corresponding voltage rise also occurs at the phase output V until a time t_ when voltage equal to the voltage on the rail 10 minus the small voltage -drop across the collector-emitter circuit of the switch Ql is reached. At time t = t-, the base drive is removed from the transistor Ql. The collector current, however, does not begin to fall until after some length of time, desig¬ nated G , caused by storage effects within the transis- tor. Following this storage time, at t = t., the collec¬ tor current in the transistor Ql decreases with a fall time t_ AT _ representing the time required for the collec¬ tor current to decrease from 90% to 10% of the initial value. During this time, no base drive is applied to the transistor Q2. Between times t = t.. and t = t fi , neither of the transistors Ql or Q2 is on. At time t = t,, base drive is applied to the transistor Q2 which thereafter turns on to connect the phase output to the voltage on the rail 12. The time between t = t, and t = t g is referred to as the delay time, or t , which is selected to be longer than the longest anticipated turn-off time for the transistors which are being used. The delay t D must be longer than the worst case values for the times t__ r and t , discussed above. This delay typically results in an undesirable increase in the harmonic content of the output power. Referring now to Fig. 3, there is illustrated an interlock circuit 30 according to the present inven¬ tion in conjunction with the switches Ql and Q2 which together form one leg of the inverter shown in Fig. 1. The interlock circuitry shown in Fig. 3 minimizes the time between turn-off of one power transistor and turn-on of the complementary power transistor so that distortion in the output is minimized. Connected to the base electrode of each tran- sistor Ql and Q2 is a base drive or control circuit 32, 34, respectively. The circuit 32 includes a first input 33 which receives one of two complementary base drive signals. These base drive signals may be pulse width modulated signals or any other type of signal. The circuit 32 also includes a second input which is responsive to a gating signal developed by a light-emitting diode, or LED1. A phototransistor PTl is associated with and receives the gating signal from the LED1. The light-emitting diode LED1 is coupled across the base-emitter junction of the power transistor Q2 and is energized to produce a light output when the transistor Q2 is fully turned off, as noted more specifically below. The phototransistor PTl includes a collector which is coupled to a source of DC voltage V through a resistor Rl. The junction between the resistor Rl and the collector of the phototransistor PTl is coupled to an inverting input of an AND gate 40. The AND gate 40 in¬ cludes a further input which receives the base drive sig¬ nal for the transistor Ql. The output of the AND gate 40 is connected to the base electrode of a transistor Q7, the emitter of which is coupled to the base electrode QIB of the tran¬ sistor Ql. The base QIB of the transistor Ql is also connected to the collector of a transistor Q8 which re¬ ceives at its base input an inverted version of the base drive signal via an inverter 44. The transistors Q7 and Q8, AND gate 40, inver¬ ter 44 and phototransistor PTl together comprise means for inhibiting energization of the transistor Ql until the. transistor Q2 is fully off, such operation being de- * scribed more particularly below. A resistor R3, diode D7 and a light-emitting diode LED2 are connected in series between the emitter and base electrodes of the transistor Ql. The LED2 and an associated phototransistor PT2 in the base drive cir¬ cuit 34 together comprise an LED-phototransistor pair, as do the elements LED1 and PTl. LED1 and LED2 comprise means for sensing the voltage across the base and emitter electrodes of the transistors Q2 and Ql, respectively. The operation of the circuitry shown in Fig. 3 will be described in conjunction with the waveforms il- lustrated in Fig. 4. Assume that at time t = t Q ' the transistor Ql is fully on so that it conducts a current of, for example, 500 amps, while the transistor Q2 is fully off. At this time, the base-to-emitter voltage V D oil of the transistor Ql is at approximately 1.2 volts while the base-emitter junction of the transistor Q2 is reverse biased to a level of, for example, -6 volts. The reverse bias on the base-emitter junction of the transistor Q2 in turn causes the LEDl to illuminate and thereby generate or develop the gating signal to render the associated phototransistor PTl conductive. Conduction of the photo¬ transistor PTl, in conjunction with a high state base drive to the circuit 32, in turn causes the AND gate 40 to energize the transistor Q7 while the transistor Q8 is maintained in an off state due to the low state signal coupled to the base electrode thereof by the inverter 44. The low state base drive signal coupled to the circuit 34 is coupled to a transistor Q9 being turned off via an AND gate 50 and an inverter 54 to a pair of tran¬ sistors Q9 and Q10, respectively. Transistor Q9 is therefore off while transistor Q10 is on so that transis¬ tor Q2 is maintained in the off state. At time t = t ' , the base drive coupled to the circuit 32 switches from a high to a low state while the base drive signal coupled to the circuit 34 switches from a low to a high state. The transistors Q7 and Q10 are thereby turned off while the transistor Q8 is turned on, in turn drawing negative base current from the base elec- trode QlB of the transistor Ql. At a time t = t-, 1 following the time t-. ' , the base-emitter voltage of the transistor Ql has dropped to a particular level, such as -3 volts. At this time, the LED2 becomes forward biased and causes the phototransis- tor PT2 to become conductive. Also, the collector cur¬ rent in the transistor Ql is rapidly falling to zero dur¬ ing this time. Once the phototransistor PT2 has been rendered conductive, the AND gate 50 develops a high state signal which is coupled to the base of the transistor Q9, turn¬ ing this transistor on. The transistor Q10, as previous- ly mentioned, is already off so that the emitter current from the transistor Q9 is delivered to the base electrode of the transistor Q2. After a short time period following time t = t- ' , the transistor Q2 begins to conduct and, at time t = t-. 1 the base-emitter voltage of this transistor rises to -3 volts, thereby turning off the phototransistor PTl. The transistor Q7 is then turned on by the AND gate 40 so that base drive is applied to the transistor Ql. The transis-tor Ql, therefore, does not receive base drive until the base-emitter voltage of the transis¬ tor Q2 indicates that this transistor is fully off. At time t = t, 1 , both of the base drive siαnals to the circuits 32,34 change state. At this time, the transistor Q8 is turned off as is the transistor Q9 while the transistor Q10 is turned on. The transistor Q10 thereafter drains negative base current from the transis¬ tor Q2 to begin the turn-off sequence for this transis¬ tor. At time t = t 5 ' , the transistor Q2 has turned off sufficiently so that the voltage across the base- emitter junction thereof has reached the -3 volt level. This voltage in turn causes the LEDl to illuminate and render the phototransistor PTl conductive. The transis¬ tor Q7 is thereby turned on so that base current is de- livered to the transistor Ql . Subsequent to time t = t ' , the transistor Ql begins to conduct current. At time t = t , ' , the base- fa emitter voltage of the transistor Ql reaches -3 volts, thereby turning off the phototransistor PT2. Following the time t = t ' , the above-described sequence repeats so that an alternating current output is produced at the phase output V . It should be noted that analogous circuitry is provided for each of the remaining transistors Q3-Q6 in the inverter, with the phase outputs being displaced 120° relative to one another. In each case, one transistor is turned off before the complementary transistor in the inverter leg is turned on with a minimum delay between these switching transitions to minimize the introduction of harmonics which degrade the output waveform. It should be noted that the selected reverse bias voltage across the base-to-emitter electrodes at which each of the LED's is illuminated to cause conduc- tion of an associated phototransistor in the complement¬ ary base drive circuit can be varied by use of additional * diodes connected in series with the LED. The LED may therefore be illuminated at a base-to-emitter voltage level other than -3 volts, if desired. The interlock circuit of the present invention takes into account variations in turn-off times of power transistors and also automatically compensates for subse¬ quent changes in turn-off times resulting from various factors, such as temperature effects, load changes and the like. Of course, the turn-off times for the power transistors are a function of how far such transistors are driven into saturation, and hence the turn-off times illustrated in the figures may vary. It should be noted that the interlock circuit of the present invention can be used with other types of inverters, such as a proportional base drive inverter wherein a transformer is utilized as a feedback element to cause tracking of base drive with load, if desired. Furthermore, it should be noted that the tran¬ sistors Q8 and Q10 may be dispensed with and replaced with resistors, in which case the inverters 44 and 54 would not be used. In such a case, the time between re¬ moval of base drive by the transistors Q7 and Q9 and ac¬ tual turn-off of the power transistors Ql and Q2 would be increased over that shown in Fig. 4.

Claims: Clai s 1. An interlock circuit for preventing simul- taneous conduction of first and second power switches connected in series across a power source, each power switch including a first electrode which receives signals from control circuitry to control the conduction of cur- rent between second and third electrodes, comprising: means coupled to one of the power switches for generating a gating signal when the voltage across two of the electrodes thereof reaches a selected level; and means in the control circuitry and coupled to the generating means for inhibiting energization of the other power switch until the gating signal is generated. 2. The interlock circuit of claim 1, wherein the generating means includes an LED coupled across the two electrodes of the one power switch and wherein the inhibiting means includes an associated phototransistor coupled to the other power switch. 3. The interlock circuit of claim 1, wherein each power switch comprises a bipolar transistor having base, collector and emitter electrodes and wherein the generating means includes means for sensing the voltage across the base and emitter electrodes of the one power switch. 4. The interlock circuit of claim 3, wherein the sensing means comprises an LED coupled between the base and emitter electrodes of the one power switch and the inhibiting means further includes a phototransistor coupled to the other power switch whereby the LED is il¬ luminated when the base voltage is less than the emitter voltage by a certain amount to in turn cause conduction of the phototransistor and thereby cause generation of the gating signal. 5. The interlock circuit of claim 1, wherein the first and second switches are operated in accordance with first and second drive signals, respectively, and wherein the inhibiting means includes an AND gate having first and second inputs which receive the gating signal and a drive signal, respectively, and an output which controls the conduction of " the other power switch. 6. The interlock circuit of claim 5, wherein the inhibiting means further includes first and second transistors connected in series with the junction there¬ between being connected to the first electrode of the other power switch, the base of the first transistor be¬ ing connected to the output of the AND gate and the base of the second transistor receiving an inverted version of the drive signal. 7. In an inverter having first and second switches each having control electrodes and main current path electrodes, the switches being connected in series across a power source and being controlled in accordance with complementary drive signals to cause an alternating output to be developed at the junction between the switches, an interlock circuit for preventing a shoot- through condition resulting from simultaneous conduction of the switches, comprising: first and second means coupled to and asso¬ ciated with the first and second switches, respectively, for generating a gating signal when the voltage across two of the electrodes of the associated switch reaches a selected level indicative of turn-off of such switch; and means for inhibiting turn-on of the other switch by its drive signal until the gating signal is generated. 8. The interlock circuit of claim 7, wherein each generating means comprises an LED coupled across the two electrodes and wherein each inhibiting means includes a phototransistor coupled to the LED, the conduction of the phototransistor being controlled by the LED. 9. The interlock circuit of claim 7, wherein each switch comprises a power transistor having base, emitter and collector electrodes and wherein the generat- ing means includes means for developing the gating signal when the base-to-emitter voltage of the transistor reach- es a selected reverse bias. 10. The interlock circuit of claim 9, wherein the generating means includes an LED coupled across the base-emitter electrodes and wherein the inhibiting means includes a phototransistor coupled to the other switch which is controlled by the LED. 11. The interlock circuit of claim 10, further including a resistor and a diode connected in series with each LED between the base and emitter electrodes. 12. An interlock circuit for preventing simul- taneous conduction of first and second complementary power transistors in a leg of an inverter, each power transistor having base, emitter and collector electrodes, the transistors being connected in series across a DC power source and being controlled in accordance with com¬ plementary base drive signals to cause an alternating output to be developed at the junction between the tran¬ sistors, comprising: first and second LED's coupled across the base and emitter electrodes of the first and second transis- tors, respectively, each LED generating a gating signal when the voltage across the base and emitter electrodes of the associated transistor reaches a level indicative of turn-off of such transistor; and first and second base drive circuits coupled to the base electrodes of the first and second transistors, respectively, each of the first and second base drive circuits including an input which receives one of the base drive signals and means coupled to the LED that is associated with the complementary transistor for inhibit- ing control of the transistor by such base drive signal until the gating signal is generated by the LED. 13. The interlock circuit of claim 12, wherein the first and second base drive circuit inhibiting means each includes a phototransistor controlled by the second or first LED, respectively, and an AND gate having first and second inputs which receive the base drive signal and the output of the phototransistor, the AND gate further including an output coupled to the respective transistor. 14. The interlock circuit of claim 12, further including means for selecting the level of base-to-emit¬ ter voltage at which the gating signal is generated.

Inventors: GLENNON
Applicants: SUNDSTRAND CORP, SUNDSTRAND CORPORATION
Application year: 1985
Main classification: H02H7
IPC codes: H02H7, H02M1, H02M3, H03K17