METHOD AND APPARATUS FOR ERROR CORRECTION

Abstract: According to one aspect of the present invention, an apparatus for error correction is comprised of a data storing section (30) for storing data to be corrected which includes a data field and an error correction field comprised of a predetermined number of bits, a data readout section (100, 40, 90) for reading out, at a first timing, the data to be corrected from the data storing section (30) into a first line, and, at a second timing, into a second line, an error detection section (50, 60) for fetching the data to be corrected as read out into the first line, and for applying a predetermined operation to the data to be corrected, thereby generating, in synchronism with the second timing, correction data corres­ ponding to error data, a correction section (70) for periodical­ ly fetching both the data to be corrected as read out into the second line, and the correction data generated by the error detection section (50, 60), and for subjecting the data to a predetermined correction processing to thereby produce corrected data, and a data write section (100, 130, 80) for storing into the data storing section (30) the corrected data as output from the correction section (70).

Description: This invention relates to a method and apparatus for error correction, and, more particularly to a method and apparatus, suitable for use in, for example, a teletext system, for error correction. In a teletext system, a digital signal is superimposed on the horizontal scanning period in the vertical blanking period. The conventional television signal has no picture signal in this vertical blanking period of horizontal scanning. The character transmission system of this teletext system contains both a pattern transmission system in which character and picture are dissolved into picture elements, and a coded transmission system in which those pictorial information are transmitted in the form of coded data. The coded transmission system is superior to the pattern transmission system in terms of the amount of pictorial information transmitted per unit time. The coded transmission system, however, has a problem in that a code error occuring during transmitting data in the digital signal form is visualized as a miswritten or omitted word. To cope with this problem, it has been proposed that the code error be corrected, thereby improving the reliability of digital signal processing. One of the correction systems which utilizes such a proposal employs a (272,190) shortened (majority) difference set cyclic code system. This correction system is disclosed in the Report of the Radio Council (DENPA GIJUTSU SHINGIKAI) of Japan, Chapter 4, pp 171-190, and in Japan patent disclosure (KOKAI) No. 59-133751. In this correction system, a majority difference set cyclic code of (273,191) is reduced in its required number of bits by one bit, this correction system being capable of dealing with a code error of a maximum of 8 bits, while retaining a correction capability. More specifically, the data field of 190 bits is associatively followed by an error correction field of 82 bits, which is generated by a predetermined generator polynomial. A total of 272 bits for the data field and the error correction field are contained in one data packet for transmission. On the receiving side, the received data packet is stored into a RAM. Then, a CPU reads out and transfers the data to a syndrome register of a predetermined number of, for example, 82 bits, and also to a shift register of 272 bits which acts as a delay circuit to synchronize the data with the output of corrected data. In the syndrome register, the 272-bit data is syndrome operated several times. Incidentally, the syndrome operation is a kind of division in which, if no error is found in the data, the data is divided to provide "0". The results of the syndrome operations are classified into a predetermined number of groups which are then supplied to a majority logic circuit. On the basis of the operation results, the majority logic circuit decides whether the data is to be corrected or not. The decision signal output from the majority logic circuit, together with the synchronizing output signal of the 272-bit shift register, is transferred to a correction circuit. The correction circuit, if the decision signal requires error correction, corrects the error and then writes the corrected data into the RAM. As stated above, the correction system can correct a maximum of eight error bits, in 272-bit data, but it may fail to correct all the error bits in some cases. It is, therefore, necessary to check as to whether or not all the error bits have been corrected. This check is made in the following way. First, the contents of the 82 registers provided in the syndrome register are checked. If the 82 bits stored in these registers are all "0's, this means that all the error bits have been corrected. Otherwise, it is understood that all the error bits have not been corrected. Hence, the 82 bits from the syndrome register are ORed, and the CPU fetches the data showing this logical sum. The logical sum indicates correction of all the bits when its value is "0," and an incomplete correction of bits when its value is "1". In the prior art system, the data to be corrected is input from the RAM to the syndrome register, and the corrected data is input from the syndrome register back to the RAM. The CPU performs both data-inputting operations in accordance with a program designed (software) for this purpose. Therefore, the time taken for error correction depends largely on the input/output speed of the CPU. If, however, the processing time of the CPU is increased during the input/output operation, the CPU can not execute other processing, e.g. decoding processing of the received data. The CPU also often fails to follow up processing of the incoming data. Further, the prior error correction control circuit uses the 272-bit shift register for synchronizing the output of the correction signal with the data. Therefore, the error correction control circuit needs have, inevitably, a large circuit size, a grave disadvantage when the error correction control circuit is fabricated into an integrated circuit. For detecting a state of the error correction process, the outputs of the respective registers in the syndrome register are ORed. This large number, 82, of inputs requires extremely long wires, adding to the overall size of the circuit, and making difficult to fabricate the error correction control circuit by means of IC technology. Prior art document US-A-4 382 300 discloses an error corection system in which a cyclic code word of 17 bits is loaded into a syndrome former in parallel. The syndrome former executes parallel calculations of the cyclic code word, thereby detecting an error instanteously. Since the code word is only 17 bits long in this prior art error correction system, the syndrome former executing a parallel calculation can be realized. However, in a system apparatus in which a code word is much longer, a extraordinarily large device is required in order to execute a parallel calculation, so that it is practically impossible to provide such a system. Further, prior art document GB-A-2 075 730 also discloses an error correction system in which a word of 39 bits is loaded into a syndrome bit generator and which executes a syndrome calculation in parallel. The system does not require a shift register for synchronization. In this known error correction system, data is read out into a first line and a check bit is output to a second line simultaneously. Finally, prior art document GB-A-2 064 840 describes an apparatus in which data groups of 80 bits are divided into high order bits and low order bits, and loaded into an error detector unit and data holding register via first and second lines, respectively, by time sharing. The data holding register functions so as to synchronize the timing when corrected data is output from a syndrome register and the timing when uncorrected data is output. Thus, the function of this apparatus corresponds to that what is explained with reference to prior art above. In other words, the data holding register compensates for the delay time which is required for outputting the corrected data. It is an object of the present invention to provide a new and improved method and apparatus which, in addition to error correction, can correct a data error at a high speed, which requires no delay circuit for synchronizing the output of an error correction signal with the supply of the data to be corrected, thus leading to a reduction in the size of the circuit, and which can check whether the data correction is made normally or abnormally by means of both a relatively simple and small circuit. To solve this object the present invention provides an apparatus as stated in claim 1 or 5 and a method as stated in claim 9, respectively. The apparatus for error correction comprises especially a data storing section for storing data to be corrected which includes a data field and an error correction field comprised of a predetermined number of bits, a data readout section for reading out, at a first section into a first line, and, at a second timing, into a second line, an error detection section for fetching the data to be corrected as read out into said first line, and for applying a predetermined operation to the data to be corrected, thereby generating, in synchronism with said second timing, correction data corresponding to error data, a correction section for periodically fetching both the data to be corrected as read out into said second line, and the correction data generated by said error detection section, for subjecting said data to a predetermined correction processing to thereby produce corrected data, and a data write section for storing into said data storing section the corrected data as output from said correction section. These and other objects and features of the present invention can be understood by referring to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating a method and apparatus for error correction according to an embodiment of the present invention; Figs. 2 and 3 show circuit diagrams partially illustrating, in detail, the block diagram of Fig. 1; Fig. 4 shows timing charts useful in explaining the operation of the block diagram of Fig. 1; Fig. 5 is a circuit diagram partially illustrating, in detail, the block diagram of Fig. 1; Fig. 6 shows timing charts illustrating the operation of the circuit diagram of Fig. 5; and Fig. 7 shows the process of storing contents, explaining the operation of the circuit diagram of Fig. 5. An embodiment of a method and apparatus for error correction according to the present invention will be described with reference to the accompanying drawings. For ease of explanation, the error correction method and apparatus will be applied to a receiver in a teletext system based on a coded transmission system. Further, the method and apparatus for error correction according to this embodiment amploys, as a correction system, a (272, 190) shortened (majority) difference set cyclic code. A scheme of the method and apparatus for error correction will be described with reference to Fig. 1. In Fig. 1, a RAM 30, as already stated, stores data of 272 bits, consisting of a data field and an error correction field, which are contained in one data packet of a character broadcasting signal. After the correction operation ends, the corrected data is stored into the RAM 30 again. The input operation of data to the RAM 30 upon receiving the character broadcasting signal, and the input/output operation of data to and from the RAM 30 after the end of the correction operation, are both under control of a CPU and a program ROM. However, in the correction operation and correction state detecting operation, the input/output operation of data to and from the RAM 30 is out of the control of the CPU and the ROM. A parallel/serial (P/S) conversion shift register 40 converts parallel data of 8 bits, as read out of the RAM 30 every 8 bits, into serial data D. The serial data D is applied to a syndrome register 50 through a switch 90, whose movable contact is connected to fixed contact a in this condition, as described later. The syndrome register 50 constructed with a shift register of 82 bits applies a predetermined syndrome operation to the serial data D. A majority logic circuit 60 decides, on the basis of the syndrome data produced as a result of the syndrome operation, as to whether the serial data D is to be corrected or not. In the majority logic circuit 60, the syndrome data supplied from the syndrome register 50 is arranged into a predetermined number, i.e. 17, of groups. Each group of syndrome data is subjected to the exclusive OR operation. If a total number of "1", as the result of the operations of 17 groups of syndrome data, is 10 or more, the majority logic circuit 60 decides that the data contains an error, and produces a correcting signal C. The correcting signal C is applied to a correcting circuit 70 constructed with an exclusive OR gate, and is used to initiate correction of the serial data D output from the P/S conversion shift register 40. The correcting signal C is also applied, as a syndrome reset pulse, to the syndrome register 50, and serves to clear the syndrome register 50. The majority logic circuit 60 includes adders 61-1 to 61-17, an encoder 62, and a comparator 63 as shown in Fig. 2. The 82-bit shift register of the syndrome register 50 produces output signals S0 to S81. These 82 bit output signals are arranged into seventeen groups G1 to G17, as shown in Table 1. These groups are exclusively ORed by the adders 61-1 to 61-17. The one bit output signals of the adders 61-1 to 61-17 are bonded into a binary system, which corresponds to the number of logical "1's" in the output signals. For example, if the output signals of the adders are "10110011101010110", ten logical "1's" are present. For such outputs, the encoder 62 produces "1010" as an output signal. This encoder output is compared with "1010" by the comparator 63. If it is above "1010", the majority logic circuit 60 decides that the data contains an error, and produces the correcting signal C. The corrected data CD is supplied from the circuit 70 to a serial/parallel (S/P) conversion shift register 80 through a switch 130 which is turned to contact b in this condition. The shift register 80 converts the data CD into 8-bit parallel data. This parallel data is then stored in the RAM 30. In the meantime, the switch 90 has been turned to contact b , and the serial data D has been supplied from the P/S conversion shift register 40 to the correcting circuit 70. The data D, which is to be corrected, is thus syncronized with the correcting signal C. A timing generator 100 generates a clock signal CK, thus controlling the operation timings of the circuits when the error correction control circuit functions accurately. The provided correction state detecting circuit 120 is for checking whether or not the correction, as performed, is correct. The correction state detecting circuit 120 reads in bit by bit the syndrome data S. when detect-ing logical "1", the circuit 120 holds its state. The syndrome data S and the data SD-representing a detection state are stored into the RAM 30 through the switch 130, whose movable contact is connected to fixed contact a in this condition, as described later, and the S/P conversion shift register 80. The operation of the embodiment thus arranged will be given with reference to Figs. 3 and 4. As seen from the foregoing, the embodiment executes the correction operation and the correction state detecting operation without using the CPU. The correction operation includes two operations. In the first correction operation, the data of the 272 bits, which is intended for correction and which is stored in the RAM 30, is written into the syndrome register 50 by way of the P/S conversion shift register 40. The syndrome register 50 then performs the syndrome operation of the received data. Then, in the second correction operation, the majority logic circuit 60 decides, on the basis of the output data from the syndrome register 50, whether or not the data is to be corrected or not. Then, the uncorrected data is read out again from the RAM 30, and corrected by the correcting circuit 70. The corrected data is then stored into the RAM 30. In the correction state detecting operation, the syndrome data S stored in the syndrome register 50 is supplied to the correction state detecting circuit 120. The correction state detecting circuit 120 detects a correction state, and writes it into the RAM 30. The above correction operation starts upon the output of a start signal STR by a CPU (not shown) to the timing generator 100. This will be described referring to Fig. 3, which illustrates the detail of the timing generator 100, as well as to Fig. 4. The start signal STR (Fig. 4A) is applied to a set terminal S of an SR(set/reset) flip-flop (referred to as FF) 101. Upon receipt of this, the Q output (Fig. 4B) of the FF101 goes to high level of "H". The Q output (Fig. 4C) of a D(delay)-FF 102 at the next stage also goes to high level of "H" at the leading edge of a clock signal CK (Fig. 4J). The Q output of the high level of "H" is applied to AND gates 103 to 105 to remove the reset states of counters 106 to 108. As a result, these counters start to count the clock signal CK. The output signals Q1 to Q4 from the counter 106 are applied to a timing decoder 109. The decoder 109 decodes these output signals to generate various types of pulses LD , SCLK, and ( WE ) (Figs. 4G-I) for controlling the one-byte data, and a reset pulse Q5 for resetting the counter 106. The counter 107 counts the output signal Q5 as a clock signal CK, and produces output signals Q6 to Q11 of 6 bits, which are in turn applied to a timing decoder 110. Using these signals, the decoder 110 checks whether the control of 34 bytes has been completed or not. The timing decoder 110 produces signals Q12a and Q12b to specify the first and second correction operations and the correction state detecting operation. Either of these signals is selectively applied as a clock signal CK to the next stage counter 108 through a switch 115 to be given later. Specifically, the signal Q12a is produced when the count of the counter 107 reaches 34, to specify the first correction operation (period T1) which processes every 34 bytes. The signal Q12b is produced when the count of the counter 107 reaches 46, to specify the second correction operation and correction state detecting operation (periods T2 and T3) which processes every 46 bytes. The counter 108 counts with the clock of either of the outputs Q12a or Q12b. When the output Q13 of the counter 108 has a low level of "L", excecution of the first correction operation is allowed. At a high level of "H" of the output Q13, execution of the second correction operation and correction state detecting operation are allowed. The output Q13 serves as a switch signal (Fig. 4E) to drive a switch 90 and also switch 115 provided in the timing generator 100, to allow either of the signals Q12a and Q12b to pass as a clock CK to the counter 108. The timing decoder 110 produces a gate signal GATE (Fig. 4D) by which to distinguish the second correction operation and correction state detecting operation from one another. The gate signal GATE switches the switch 130. At the end of the second correction operation and correction state detecting operation, the output Q14 of the counter 108 (Fig. 4F) goes to high level of "H", and the FFs 101 and 102 are reset via an inverter 114, resulting in termination of all the operations. The first correction operation will now be described in more detail, using Figs. 4J to 4S, which are enlargements of the Figs. 4A to 4I waveforms. This operation starts in response to the start signal STR (Fig. 4K). The timing decoder 109 for controlling one byte data produces various pulse signals. The one byte operation is performed by eleven clocks CK (Fig. 4J). In response to a load pulse LD (Fig. 4N), one byte data, which is readout from the RAM 30, is loaded into the P/S conversion shift register 40 by way of the data bus. An address (Fig. 4R) of the RAM 30 is applied at this time in the form of the output signals Q6 to Q11 (collectively denoted as B0) of the counter 107 to effect control of 34 bytes. Then, nine shift clocks SCLK (Fig. 4O) are produced, so that the P/S conversion shift register 40 produces the serial data D. At this time, the output Q13 of the counter 108, i.e. the switch signal SW (Fig. 4E) is low; consequently the movable contact of the switch 90 is connected to contact a . Therefore, the serial data D goes to the syndrome register 50 where it is syndrome operated. Immediately upon the timing of the 8th shift clock SCLK, the decoder 109 produces a write pulse WE1 . This pulse, however, is blocked by the HAND gate 111 which is receiving the switch signal SW, thus a write pulse WE (Fig. 4P) is not produced. Therefore, data write into the RAM 30 is not performed. At the 11th clock, the decoder 109 produces the output Q5 (Fig. 4Q). With application of this output, the counter 107 is counted up. The output Q5 is also applied to the reset terminal R of the counter 106, through an inverter 112 and an AND gate 103. By this output Q5, the counter 106 is reset. The writing of one byte data for the 11 clock duration is repeated 34 times. When the data of 34 bytes (274 bits) has been input to the syndrome register 50, the decoder 110 produces the output signal Q12a. At this time, the switch 115 has been at the contact a since the output Q13 of the counter 108 became low. With connection of the switch contacts, the signal Q12a goes, as a signal Q12, to the counter 108. By this signal, the counter 108 is counted up. The counter 107 is reset by the output signal Q12 coming through the inverter 113 and the AND gate 104. The output signal Q13 of the counter 108 is high (Fig. 4E), and the switch 115 is turned to the contact b . Here, the first correction operation ends and the second correction operation begins. The second correction operation will be described with reference to Figs. 4J to 4S, which are enlargements of the Figs. 4A to 4I waveforms. As recalled, in this operation the majority logic circuit 60 using the operation result from the syndrome register 50 decides whether or not the data is to be corrected. Then, the data is again loaded into the RAM 30 through the correcting circuit 70. As in the first correction operation, the load pulse LD (Fig. 4N) is applied to the RAM 30 and the P/S conversion shift register 40. Data of one byte, stored at the memory location of the address B0 (Fig. 4R), is read out and loaded into the P/S conversion shift register 40. The parallel data of one byte is output, as loaded, as the serial data D which is responsive to the shift clock signal SCLK (Fig. 4O). At this time, the switch signal SW (Fig. 4E) has a high level, as already described. Accordingly, the switch 90 is turned to the contact b , and the serial data D is supplied to the correcting circuit 70. simultaneously, the result of the syndrome operation output from the syndrome register 50 is checked by the majority logic circuit 60. Responsive to the correcting signal C output bit by bit, the serial data D is corrected in the correcting circuit 70. The corrected data CD is stored bit by bit into the S/P conversion shift register 80 in synchronism with the shift clock signal SCLK. The method of writing the corrected data into the RAM 30 will be described. In the initial state, a total of 272 bits constituting the data field and the correction field in the character broadcasting signal have been stored in the RAM 30. These data are sequentially stored into the RAM 30 in the incoming order of the data, byte by byte, as shown Fig. 7a. The uncorrected data thus stored into the RAM 30 are read out and corrected as described above. The corrected data is again stored into another area of the RAM 30 in the following manner. The serial data D of 8 bits are corrected by the eight shift clocks SCLK and stored into the S/P conversion shift register 80. Then, the timing decoder 109 produces a write pulse WE1 . At this time, the switch signal SW (Fig. 4E) is high in level, and hence the NAND gate 111 produces a write pulse WE (Fig. 4P). The corrected data stored in the shift register 80 is written into the RAM 30, which is the data unit for processing in the manner of Fig. 7b. The address of the RAM 30 to which the corrected data is written (see Fig. 4R) is the address Bo', as composed by the outputs Q6 to Q11 of the counter 107 and the output Q4 of the counter 106 (Fig. 4S). In this way, the correction operation of one byte data, which continues for the duration of 11-clocks, is repeated 34 times to store the data D0 to D271 into the RAM 30, as shown in Fig. 7b. At this time, the output Q13 (Fig. 4E) is high, and, therefore, the movable contact of the switch 115 is connected to fixed contact b . Under this condition, the output Q12b, produced when the count of the counter 107 is 45, is allowed to be output as the output Q12. At this time, however, the output Q12 is not yet produced. Therefore, the counter 108 is not counted up and the output Q14 is not output. The instant the count of the counter 107 reaches 34, the gate signal GATE (Fig. 4D) goes high. Subsequently, the high level is sustained until the count of the counter 107 reaches 46. As a result, the switch 130 is turned to the contact a . Then, during the period T3 in Fig. 4, the correction state detecting operation is performed. The correction state detecting operation will be described with reference to Figs. 5 and 6. In Fig. 5, illustrating in detail the correction state detecting circuit 120, the output Q of an FF 121 produces a high level signal during the period that the gate signal GATE is low, that is, during the period other than that of the correction state detecting operation. The state of the syndrome data S is detected by a NAND gate 122 and an FF123. The FF121 retains its state, and a NAND gate 124 produces, as the syndrome data SD, the retained result, and applies it to the S/P conversion shift register 80. The operation of the correction state detecting circuit 120 will be described with reference to Fig. 6 which illustrates waveforms at respective portions of the correction state detecting circuit 120. As a first step, the gate signal GATE (Fig. 6A) goes high to remove the reset state of the FF121. The NAND gate 122 is enabled by the gate signal GATE to allow only syndrome data S1 representing error data (Fig. 6D) of the syndrome S (Fig. 6C) to pass through it. This data S1 is latched in the FF123 in response to the shift clock SCLK (Fig. 6G) to produce the output Q (Fig. 6E). If the syndrome S is logical "0", the FF121 continuously produces a high level signal, without being reset. The NAND gate 124 produces a correction state signal SD of logical "0" (Fig. 6F). When the syndrome data S of logical "1" is input to the correction state detecting circuit 120, the data S1 goes low. The data S1 is latched by the FF123. Then, the Q output of the FF123 becomes low in level, so that the FF 121 is reset. The Q output of the FF121 also becomes low. Subsequently, the output Q is retained without regard to the syndrome data S. Accordingly, the correction state signal SD is kept at a high level. The correction state signal SD is supplied through the switch 130 to the register 80. Then, the signal SD is stored into the memory locations B34' to B44' of the ROM30, as in the second correction operation. Fig. 7C illustrates the stored state of the signal SD in the RAM 30. Even after the syndrome data S of 82 bits is stored into the correction state detecting circuit 120, the shift clock SCLK is still supplied to store the correction state signal SD into the memory location of the address B45' in the RAM 30. At this time, if even one bit data is contained in the syndrome data of 82 bits, as described above, the correction state signal SD goes high. Accordingly, when the data is abnormally corrected as shown in Fig. 7d, all of the one byte data are stored in the address B45', with all 1's. Conversely, when it is normally corrected, all 0's are stored therein. Therefore, whether the correction was normal or abnormal can be detected by reffering to the contents of the address B45' by means of the CPU. When storage of the data of 46 bytes is completed, the decoder 110 produces the output Q12b. This output Q12b is applied as the output Q12 to the counter 108. Upon receipt of this, the counter 108 produces an output signal Q14 (Fig. 4F). The output Q14 is applied to the reset terminal R of the FFs 101 and 102 through the inverter 114 to reset the FFs101 and 102. Accordingly, the counters 106 to 108 are reset and stop its count operations. At this point, the first and second correction operations and correction state detecting operation end. As seen from the foregoing, the specially arranged hardware is employed for the writing of the data designated for correction into the syndrome register 50, as well as for the reading of the corrected data from the S/P conversion shift register 80. This feature reduces the time taken for outputting the data, and speeds up the error correction operation of the error correction control circuit. The timing of reading out the data D designated for correction into the P/S conversion shift register 40 from the RAM 30, is used for synchronizing the correcting signal C to decide whether or not the data D is to be corrected with that data D. This feature eliminates the shift register of 272 bits, which was essential to the prior art circuit. The fact that such a register is not needed simplifies the circuit arrangement of the error correction control circuit. The simplified circuit arrangement makes IC fabrication of the error correction control circuit easy. For detecting the error correction state, the correction state detecting circuit 120 reads out bit by bit the syndrome data S of 82 bits stored in the syndrome register 50. The same holds the change of the data S from logical "0" to logical "1", so as to record abnormal correction of the correction operation. Therefore, there is no need for OR circuits for 82 inputs. This feature also simplifies the circuit arrangement by reducing the number of necessary circuit components. Therefore, easy IC fabrication of the error correction control circuit can be realized. The necessity of the CPU for the correction operation is only to issue the start signal STR to start the error correction operation. Therefore, during the error correction operation, the CPU can be used for other processing. It is evident that the present invention is applicable not only to the character broadcasting receiver, but also to an ordinary error correction system. The error correction operation can be performed at a high speed. Further, there is no need for a delay circuit for synchronizing the outputting of the error correction signal with the supply of the data designated for correction. Consequently, the circuit size of the error correction control circuit can be reduced. Additionally, the check for error correction can be made without any increase in the size of the circuit.

Claims: An apparatus for error correction having data storing means (30) including first and second storage areas, the first storage area storing uncorrected code data as a data packet, the data packet having a data field and an error correction field including a predetermined number of bits, characterized in that said apparatus further comprises: timing signal generating means (100) for generating first and second timing signals, said second timing signal being generated a predetermined interval of time after said first timing signal; data readout means (40) for reading the uncorrected data from the first storage areas of the data storing means (30) in response to the first and second timing signals, the uncorrected data being successively read out in series; switching means (90) for switching between first and second lines, the first line being provided for transmitting the uncorrected data read out in response to the first timing signal, and the second line being provided for transmitting the uncorrected data read out in response to the second timing signal; error syndrome calculating means (50) for calculating error syndrome in the uncorrected data transmitted in series through the first line in response to the first timing signal and for generating an output representing the data errors; error detecting means (60) for determining whether the uncorrected data includes a predetermined quantity of data errors based on the output of the error syndrome calculating means (50) and for generating correction data representing a result of the determination while the second timing signal is being output; correction means (70) for synchronously fetching the correction data generated by the error detecting means (60) and the uncorrected data transmitted through the second line in response to the second timing signal and for correcting errors in the uncorrected data in accordance with the correction data to thereby generate corrected data; and write means (80) for receiving the corrected data output in series from the correction means (70) and for successively writing the corrected data into the second storage area of the data storing means (30) in response to the second timing signal. An apparatus according to claim 1, characterized in that the uncorrected data represents a majority difference set cyclic code. An apparatus according to claim 2, characterized in that the error syndrome calculating means (50) comprises a syndrome register including a shift register for shifting a predetermined number of bits, and the error detecting means (60) comprises a majority logic circuit which selects by a majority output bits of the syndrome register in predetermined combinations for generating said correction data in order to correct corresponding data errors in the uncorrected data. An apparatus according to claim 3, characterized in that said apparatus further comprises corrected state detecting means (120) for serially fetching, bit by bit, the contents of the syndrome register after the error correction has been performed by the correction means (70) and for detecting whether the error correction was performed correctly by the correction means (70). An apparatus for error correction having data storing means (30) including first, second and third storage areas, the first storage area storing uncorrected code data as a data packet, the data packet having a data field and an error correction field including a predetermined number of bits, characterized in that said apparatus further comprises: timing signal generating means (100) for generating first, second and third timing signals with predetermined time delays therebetween; data readout means (40) for reading the uncorrected data from the first storage area of the data storing means (30) in response to the first and second timing signals, the uncorrected data being successively read out in predetermined increments of bits; first switching means (90) for switching between first and second readout lines, the first readout line being provided for transmitting the uncorrected data read out in response to the first timing signal, and the second readout line being provided for transmitting the uncorrected data read out in response to the second timing signal; error syndrome calculating means (50) for calculating data errors in the uncorrected data transmitted through the first readout line and for generating an output representing the data errors; error detecting means (60) for determining whether the uncorrected data includes a predetermined quantity of errors based on the output of the error syndrome calculating means (50) and for generating correction data representing a result of the determination; correction means (70) for synchronously fetching the correction data generated by the error detecting means (60) and the uncorrected data transmitted through the second readout lines and for correcting errors in the uncorrected data in accordance with the correction data to thereby generate corrected data; correction state detecting means (120) responsive to the output of said error syndrome calculating means (50) for detecting whether the error correction was performed by the correction means (70) after the error correction has been performed by the correction means (70) and for generating an output representing the result of the detection; second switching means (130) for switching between first and second writing lines, the first writing line being provided for transmitting the corrected data supplied from the correction means (70) in response to the second timing signal, and the second writing line being provided for transmitting the output of the correction state detecting means (120) in response to the third timing signal; and write means (80) for successively writing into the second storage area of the data storing means (30) the corrected data supplied in series from the correction means (70) through the first writing line in response to the second timing signal and for writing in the third storage area of the data storing means (30) the output of the correction state detecting means (120) supplied in series through the second writing line in response to the third timing signal. An apparatus according to claim 5, characterized in that the uncorrected data represents a majority difference set cyclic code. An apparatus according to claim 6, wherein the error syndrome calculating means (50) comprises a syndrome register including a shift register for shifting a predetermined number of bits, and the error detecting means (60) comprises a majority logic circuit which selects by a majority output bits of the syndrome register in predetermined combinations for generating said correction data in order to correct corresponding data errors in the uncorrected data. An apparatus according to claim 7, characterized in that the corrected state detecting means (120) serially fetches, bit by bit, the contents of the syndrome register after the error correction has been performed by the correction means (70) and for detecting whether the error correction was performed correctly by the correction means (70). A method for error correction using a memory (30) including first and second storage areas, the first storage area storing uncorrected data as a data packet, the data packet having a data field and an error correction field including a predetermined number of bits, characterized in that said method comprises the steps of: generating a first timing signal; reading uncorrected code data out of the first area of the memory (30) in response to the first timing signal; converting and outputting the read-out uncorrected data in series; performing syndrome calculation for determining data errors in the uncorrected data output in series; generating a second timing signal after the first timing signal has been generated; reading the uncorrected code data out of the first area of the memory (30) in response to the second timing signal; converting and outputting the read-out uncorrected data in series; determining whether the uncorrected data includes data errors based on the syndrome calculation and generating correction data if data errors are determined while the second timing is being output; synchronously fetching both the correction data and the uncorrected data read out in response to the second timing signal; performing, bit by bit, in series, error correction on said uncorrected data with said correction data so as to generate corrected data; and writing the data, corrected in series, into the second area of the memory (30) in response to the second timing signal. A method according to claim 9, characterized in that said method further comprises the steps of: generating a third timing signal after the second timing signal has been generated; fetching the output of the syndrome calculation in series in response to the third timing signal for determining whether said error correction step was performed correctly; and writing data representing whether the error correction step was performed correctly into a third area of the memory (30).

Inventors: MATSUSHITA, AKIRA C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: H04N7
IPC codes: H04N7, H03M13