IMAGE DATA BUFFERING CIRCUITRY

Abstract: A memory access control apparatus comprises an address queueing circuit (CAQ) for storing a real address at which image data can be stored, a correspondence storing circuit (CAT) for storing a correspondence between a real address and a logical address, and a control circuit (IMC) for controlling a writing operation in such a way that, at a real address taken from the address queueing circuit, a next transfer unit of data is written, after the transfer unit of data previously stored at that real address has been read, by specifying the corresponding logical address, whereby a continuous reading can be effected without stopping due to a writing operation.

Description: The present invention relates to image data buffering circuitry. A laser printer, for example, is generally required to continuously print out image data at a high speed and accordingly high speed transmission of image data from an image memory to the laser printer is necessary. In order to continuously read image data, in image data buffering circuitry two image memories may be provided so that while one of the image memories is storing one page of image data, another page of image data can be read from the other image memory. This constitution, however, requires two image memories for simultaneously storing and reading one page of image data respectively, with the result that memory capacity as a whole must be large. It is possible to employ, in image data buffering circuitry, an image memory having a capacity for storing just one page of image data, wherein new image data may be sequentially written into an area from which the previous image data has been read. Such an image memory, however, cannot facilitate high speed reading when the written image data is written randomly, i.e. is not written in sequence from the top to the bottom of the page, as later described in more detail with reference to drawings. According to the present invention there is provided image data buffering circuitry comprising: a memory, having a plurality of individually addressable data storage locations, for storing data defining an image sub-divided into a plurality of spacial units; address storage means for storing addresses of such locations that are available for the storage of new data; an address correspondence store having storage areas corresponding respectively to the said spacial units and accessible by means of respective address codes; writing means for writing the image-defining data, if any, of any chosen one of the said spacial units into an individual one of such available locations, which available location has been selected by taking the address of that location from the address storage means, and for placing the address of that selected location in the individual storage area of the correspondence store that corresponds to the chosen spacial unit; and reading means for employing the address code appropriate to the storage area that corresponds to a selected one of the said spacial units to read out from the said memory the image-defining data, if any, of the selected spacial unit and for adding back to the said address storage means the address of the storage location from which that image-defining data has been read out. Preferably the circuitry has two such address correspondence stores for use respectively in reading/writing image-defining data of two different images, the operation of the writing and reading means being such that data defining one of the images can be written into the said memory while data defining the other image is being read out from that memory. The number of said storage areas in the said address correspondence store may be at least twice the number of the said data storage locations in the said memory. Each of the said storage areas in the correspondence store may have associated therewith an individual correspondence-indicating bit for indicating whether or not there is image-defining data, of the corresponding spacial unit, stored in the memory at a location whose address is held in the storage area concerned, the circuitry being such that when the image-defining data of a selected spacial unit is written into the memory the said correspondence-indicating bit associated with the corresponding storage area is set by the writing means, and such that when the image-defining data of that spacial unit is read out from the memory the said correspondence-indicating bit associated with the corresponding storage area is reset by the reading means. In an embodiment of the present invention, the said reading means, on detecting that the said correspondence-indicating bit associated with a storage area selected for reading is in the reset condition, generates a blank data signal as the image-defining data for the corresponding spacial unit. The said address storage means may be a first-in first-out circuit. The said correspondence store may also have individual correspondence-inhibiting bits, associated respectively with the said data storage areas, which bits can be set to prevent the image-defining data of the corresponding spacial units being written in the said memory. In an embodiment of the present invention, the said reading means, on detecting that the correspondence-inhibiting bit associated with a storage area selected for reading is set, generates a blank data signal as the image-defining data for the corresponding spacial unit. The writing means and the reading means preferably further comprise an address conversion means for converting the write address or the read address into a lateral accessing address or a vertical accessing address. Image data buffering circuitry embodying the invention can be constructed so as to be capable of high speed processing and can provide an improved virtual memory system, adapted to output data from a memory to a printer such as a laser printer. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram of a data processing system; Fig. 2 shows a block diagram of an example of image data buffering circuitry not embodying the present invention; Fig. 3A shows a schematic diagram of an image memory in another example of image data buffering circuitry not embodying the present invention; Fig. 3B shows a schematic view for illustrating data storage in a logical memory space of the Fig. 3A image memory; Fig. 4 is a block diagram of an image data processing device including image data buffering circuitry embodying the present invention; Fig. 5 is a block circuit diagram of image data buffering circuitry embodying the present invention; Fig. 6 shows states of a cell address translate table (CAT), a cell memory (CM), and a cell address queue (CAQ), which are included in the Fig. 5 circuitry, and also shows data storage in a logical memory defined within the cell memory (CM); Fig. 7A shows initial states of the two CATs and CAQ; Fig. 7B shows transitional states of the two CATs, the CAQ, and the logical memory, when new data is written in one page of the logical memory; Fig. 7C corresponds to Fig. 7B but illustrates such states when further new data is written in another page of the logical memory; Fig. 8 is a flow chart for explaining the operation of the circuitry shown in Fig. 5; Fig. 9 is a circuit diagram of an image memory control unit in the circuitry shown in Fig. 5; Fig. 10 shows the structure of the cell address translate table (CAT) in the Fig. 5 circuitry; Fig. 11 shows the structure of the cell memory (CM) in the Fig. 5 circuitry; Fig. 12 is a block diagram of further parts of the Fig. 5 circuitry, for explaining vertical and horizontal accessing modes thereof; Figs. 13A and 13B show respective schematic views illustrating a correspondence between locations in the above-mentioned logical memory and positions on printing paper; Figs. 14A and 14B show respective views illustrating the arrangement of printed characters on the printing papers shown in Figures 13A and 13B respectively; Fig. 15A is a flow chart for explaining a data flow from a channel controller (CHC) to image hardware (IMH) in the image data processing device shown in Fig. 4; Fig. 15B shows a data format of an instruction code transferred from a central processing unit (CPU) shown in Fig. 1 to a control processor (CTP) shown in Fig. 4; Fig. 15C shows a data format in a form-control buffer (FCB) shown in Fig. 4; Fig. 15D shows a process of the translation of a character code into the corresponding top address of the character; Fig. 15E shows a data format in a page buffer (PB) shown in Fig. 4; Fig. 15F diagrammatically shows a start position of each character; Fig. 16 is a block diagram showing in detail a character generator controller (CGC) shown in Fig. 4; Fig. 17 is a block diagram showing in detail a write circuit (WC) shown in Fig. 16; Fig. 18A is a flow chart for explaining a write control operation; Fig. 18B is a diagram for explaining a lateral access and a vertical access in the write control operation shown in Fig. 18A; Fig. 19 is a block diagram of a print controller in the Fig. 4 device; Fig. 20 is a detailed block diagram of part of the print controller shown in Fig. 19; Fig. 21A is a detailed block diagram of another part of the print controller shown in Fig. 19; and Fig. 21B is a circuit diagram of clock generating circuitry for generating clock signals used by the Fig. 19 print controller. Figure 1 shows a data processing system for explaining the background of the present invention. In Fig. 1, the data processing systems includes a host central processing unit (CPU) 1, main channel 2, an image data processing device 3, and an input/output unit (I/O) 4 such as a display unit. The image data processing device 3 includes an image data buffering circuitry 30 pertaining to the present invention and a printer (not shown in Fig. 1). The CPU 1 communicates through the main channel 2 with the image data processing device 3 or I/O unit 4. Character data of characters to be printed out from the image data processing device 3 or certain instructions for operating the image data processing device 3 are generated from the CPU 1 and are transferred through the channel 2 to the image data processing device 3. The image data buffering circuitry functions as a data buffer for transferring one page of image data to be output to a printer assembly (not shown in Fig. 1). The circuitry 30 may be regarded as a modification of a virtual memory system. Incidentally, a different example of the use of a virtual memory system in relation to image data is given in EP-A-0 099 989 which discloses image display control apparatus including an image memory for storing image data to be displayed (on a display screen). The image memory is organised on a virtual basis by employing a mapping memory (address correspondence store) having storage areas corresponding respectively to the spacial units (parts of the image) to be displayed and accessible by means of respective address codes. In this apparatus, however, the reading operation does not free the read storage location of the image memory for the storage of new image data. Figure 2 shows an example of image data buffering circuitry not embodying the invention. In Fig. 2, the circuitry includes to image memories (IMM₁ and IMM₂) 30a1 and 20a2, and a selector (SEL) 30a3. Each of the two image data memories 30a1 and 30a2 has a capacity for storing one page of image data. During reading of one page of image data from the first image memory 30a1 to a laser printer, for example, the selector selects the second image memory 30a2 for a writing operation. In the writing operation, the second image memory 30a2 is accessed for writing one page of data therein by specifying logical addresses LA corresponding to the logical address space of the second image memory 30a2. Similarly, during reading operation of the second image memory 30a1 for writing a next one page of image data. This constitution ensures a high speed reading operation because the image data can be continuously read without stoppage due to a write operation. The above-described image data buffering circuitry, however, needs the two image memories, or two pages of memory capacity, resulting in the disadvantage of needing a large memory capacity. In order to reduce the memory capacity, a single image memory having a memory capacity of one page may be provided as shown in Fig. 3A. In Fig. 3A, a portion A indicated by slash lines represents a logical space where image data has been read so that this portion A can be used to write data, and a portion B represents a logical space from which image data has not been read. If write data is written sequentially from the top to the bottom of the logical space, the single image memory can store data simultaneously with the reading operation. However, the logical addresses of the write data are not always supplied sequentially from the top to the bottom of the logical space. Assume an example, as shown in Fig. 3B, wherein image data of an X axis 1 ○ is first written into the image memory, and then image data of Y axis 2 ○ is written, and, finally, image data of a line 3 ○ is written. Then, the image data of the X axis can be written into the image memory only after the reading operation is finished from the top logical address (0, 0) of the logical space to the end logical address (X, Y) of the X axis. Therefore, simultaneous writing and reading operations cannot always be carried out. In this case, the next reading operation must often be started only after writing one page of image data. As a result, a continuous reading operation cannot be effected by this single image memory. Figure 4 is a block diagram generally showing in detail the image data processing device 3 of the Fig. 1 data processing system. In Fig. 4 the image memory control device includes the image data buffering circuitry 30 (Fig. 1), a control processor (CTP) 31, a channel controller (CHC) 32, a global memory (GLM) 33, an imaging hardware (IMH) 34, a print controller (PRC) 35, a control bus (C-BUS) 36, a memory bus (M-BUS) 37, and an image data bus (I-BUS) 38. Dash lines in Fig. 4 represent paths for transferring control signals. Solid lines represent paths for transferring data. The CTP 31 includes a local memory (LM) 310 consisting of a read only memory (ROM) and a random access memory (RAM) for storing a control program. The RAM also functions as a work area. The CTP 31 controls the whole of the device 3 and also carries out preprocessing for the IMH 34. The CTP 31 may be realized by a microprocessor. The CHC 32 is connected through the main channel 2 (Fig. 1) to the CPU 1 (Fig. 1), and carries out a transfer operation of character data or graphic data from the CPU 1 to the GLM 33 by a direct memory access method (DMA). The GLM 33 includes an intermediate buffer (IB) 330, a page buffer (PB) 331, a graph data buffer (GDB) 332, an image data buffer (IDB) 333, a form overlay memory (FOM) 334, a character generating memory (CG) 335, a form control buffer (FCB) 336, and a character translation table (TT) 337, some of which are described later in more detail. The GLM 33 has a memory capacity in the range, for example, from 0.5 megabytes to 2.5 megabytes. The IMH 34 is a hardware for converting code data or compacted data stored in the GLM 33 into bit pattern data, and for writing the bit pattern data into the IMM 30, under the control of the CTP 31. The IMH 34 includes a character generator controller (CGC) 340, a vector generator controller (VGC) 341, an overlay pattern controller (OVC) 342, and an image generator controller (IMC) 343. The CGC 340 is indispensable to and is always provided in the IMH 34. The CGC 340 has a function of imaging character codes stored in the CG 335 in the GLM 33. Each of the character codes is obtained by converting character data transferred from the CPU 1 (Fig. 1) into an internal expression, i.e., a code of four bytes per character. The character codes are supplied from the CG 335 in the GLM 33 through the M-BUS 37 to the CGC 340 by DMA when the CTP 31 activates the CGC 340. The other controllers, i.e., VGC 341, OVC 342, and IMC 342, are optionally provided. The VGC 341 has a function of imaging graphic data codes stored in the GDB 332 in the GLM 33. The data supplied to the VGC 341 are graphic codes which are obtained by converting graphic data transferred from the host CPU 1 (Fig. 1) into an internal expression. The VGC 341 also accesses the GDB 332 in the GLM 33 through the M-BUS 37 by DMA when the CTP 31 activates the VGC 341. The OVC 342 has a function of restoring compressed overlay data, and the IMC 343 has a function of restoring compressed image data. The C-BUS 36 is a bus which conforms with the CTP 31. As an example, the C-BUS 36 consists of a 24-bit address bus and a 16-bit data bus. All of the memories and registers in the image memory control device 3 can be mapped within the address space of the C-BUS 36. The C-BUS 36 can transfer 8-bit data or 16-bit data. The M-BUS 37 is a bus used only for DMA from the GLM 33 to the IMH 34, and can operate independently from the C-BUS 36. The M-BUS 37 consists of, for example, a 24-bit address bus and a 16-bit data bus. The M-BUS 37 always transfers 16-bit data. The IMM 30 functions as a buffer memory for storing image data output from the IMH 34. The image data output from the IMH 34 is bit pattern data. In order to facilitate continuous printing, in an embodiment of the invention the IMM 30 is capable of mapping two pages of logical memory into only one page of a real memory. The image data buffering circuitry 30 may consist, for example, of two individual memory buffering circuits or "planes" (IMM) 301 and 302. The first memory plane 301 (described in detail hereinafter) may be used for two pages of character image data developed by the CGC 340. The second memory plane 302 is optionally provided and may be used for two pages of graphic image data developed by the VGC 341. The PRC 35 controls an interface between the IMM 30 and a printing assembly (not shown in Fig. 4). Synchronously with a printing process timing in the printing assembly, the PRC 35 transfers the image data from the IMM 30 to the printing assembly. When the IMM 30 consists of two memory planes, the PRC 35 should be of correspondingly larger size. The operation of the image data processing device 3 shown in Fig. 4 is as follows. The CHC 32 receives character data from the host CPU 1 (Fig. 1) and then transfers it through the M-BUS 37 to the GLM 33 by DMA. The CTP 31 supervises this data transfer as well as forms the contents of the PB 331 in accordance with the received character data. Once one page of contents is formed in the PB 331, the CTP 31 generates an instruction to the CGC 340 so that the CGC 340 receives the character codes from the PB 331 and develops a bit pattern of the character data. The IMM 301 then stores the developed bit pattern of image data. When the development of the bit pattern is finished, the CGC 340 informs the CTP 31 that the development is ended. Then, the CTP 31 generates an instruction to the PRC 35 so as to read data from the IMM 301. In response to the instruction, the PRC 35 reads data from the IMM 301 and outputs it as video signals VS synchronously with the operation of the printing assembly. Simultaneously with the read and output operation of the PRC 35 for outputting the video signals VS, the next page of contents is formed in the PB 331; the CGC 340 develops a bit pattern of the next page of the character data; and the IMM 301 stores the next page of the developed bit pattern, in a manner similar to the above-mentioned operation for the first page. In a case in which the second memory buffering circuit IMM 302 is present, when graphic data is transferred from the host CPU 1 the CTP 31 activates the VGC 341 after one page of graphic data is stored in the PB 331 so that the VGC 341 develops a bit pattern of one page of the graphic data. The IMM 302 then receives the bit pattern of the graphic data. The simultaneous operation of reading the first page of the graphic data from the IMM 302 and storing the next page of the graphic data into the IMM 302 is similar to the operation for the character data. When the character data and the graphic data should be printed out on a same page, the PRC 35 takes a logical OR of the outputs from the IMMs 301 and 302. The operation of the device 3 shown in Fig. 4 will be described later in more detail with reference to Figs. 15 to 18. Fig. 5 is a block circuit diagram showing the image data buffering circuitry 301 according to an embodiment of the present invention. In Fig. 5 the IMM 301 is connected to the I-BUS 38 which is used only for accessing the IMM 301 or IMM 302 (Fig. 4). The IMM 301 includes a cell address translate table (CAT) 91, a cell memory (CM) 92, a cell address queue (CAQ) 93, a first address translate circuit (EORa) 94, a second address translate circuit (EORb) 95, a first multiplexer (MPXa) 96, a second multiplexer (MPXb) 97, a third multiplexer (MPXc) 98, and an image memory control circuit (IMC) 99. The CAT 91 is a logical memory for storing a table which is used to translate a logical address into a real address. The CM 92 is a real memory for storing bit image data. The CAQ 93 is a "first-in first-out" (FIFO) circuit for supervising real memory cells which are not being used. The EORa 94 and the EORb 95 are circuits for translating addresses and data sequences so as to realize lateral access, vertical access, or plane access. X₀ through X₁₁ , and Y₀ through Y₁₁ represent address lines for specifying a read or write logical address of the IMM 301 from the IMH 34 (Fig. 4). P represents an address line for specifying a page used for reading or writing. D₀ through D₁₅ are data lines for reading from or writing in data by the IMH 34. R/W is a signal for discriminating whether data is read from or data is written in the IMM by the IMH 34. RQ is an access request signal from the IMH 34. ACK is an access permission signal from the IMM 301 to the IMH 34. The other signals in Fig. 5 are described later. The principal operation of the IMM 301 shown in Fig. 5 is described with reference to Fig. 6 which shows certain states of the CAT 91, the CM 92, the CAQ 93, and a logical space LS corresponding to the state of the CAT 91. For the sake of simplicity, the logical space LS in this example has only nine logical cells LC each having an address space of 64 bits x 64 bits. Each logical cell is a unit of a virtual memory. Also, the CM 92 has nine real cells RC each having the same address space of 64 bits x 64 bits as that of the logical cell LC. The logical cells LC and the real cells RC may relate to each other in one to one correspondence. The CAT 91 has nine columns identified by logical addresses YX = 00 through 22. Each column includes an AOV bit, a NOCELL bit, and a real cell address. The AOV bit indicates whether or not the logical cell can be allocated with a logical cell address. That is, in the logical space LS, the slashed portion having logical addresses YX = 02, 12, 20, 21, and 22 is shown as an example of the allocation inhibit area, such as an area near the sides of a page. Any data in this area should not be printed out. Therefore, the logical cells LS in this area cannot be allocated logical addresses. To this end, the AOV bits in the columns 02, 12, 20, 21 and 22 in the CAT 91 are labelled "1", indicating that the logical cells LS in these addresses cannot be used for write or read operations. The other columns in the CAT 91 have the AOV bits of "0". The NOCELL bit indicates whether or not correspondence is established between the logical cell and a real cell. In the illustrated example the logical cell having the logical address 00 corresponds to the real cell having the logical address 00; the logical cell 01 corresponds to the real cell 01; the logical cell 10 corresponds to the real cell 02; and the logical cell 11 corresponds to the real cell 04. Thus, the NOCELL bits in the columns 00, 01, 10, and 11 are labelled "1". In this example, the CAQ 93 is an FIFO having nine columns. Each column stores a real address of a real cell which can be used to write data therein or to read data therefrom, i.e., which is not in use. The direction of data flow in the CAQ 93 is from the bottom to the top, as indicated in the figure by an arrow. Empty columns in the CAQ 93 mean that any real address except for the real addresses stored in the CAQ 93 may be made to correspond to a logical address. In the illustrated state, since the real cells 00, 01, 02, and 04 have been made to correspond to the logical cells 00, 01, 02, and 10, respectively, the remaining real cells 03, 05, 06, 07, 08, and 09 are free to be used for other read or write operations. Therefore, by providing another CAT in addition to the CAT 91, image data in another logical space can be written into the same CM 92. The writing operation of two pages into a single page of the real memory is further described with reference to Figs. 7A through 7C. Figure 7A shows the initial states of two CATs, i.e., CAT (P₀) for the first page and CAT (P₁) for the second page, and the CAQ. In this state, the CAQ stores all of the real cell addresses 00 through 08. Therefore, all of the real cells can be used for the write operation. Also, NOCELL bits in the CAT (P₀) and CAT (P₁) are all "0" indicating that no logical cell corresponds to any one of the real cells, even when each column in the CAT (P₀) and CAT (P₁) stores any real address. From this state shown in Fig. 7A, assume that image data as shown in Fig. 7B is to be written on the first page P₀ of the logical space in a sequence from 1 ○ through 4 ○ , i.e., in a sequence of the logical addresses 00, 01, 10, and 11 of the first page P₀. Then, the real addresses 00, 01, 02, and 03 stored in the CAQ are sequentially output. The output real addresses are then input into the columns 00, 01, 10, and 11 of the CAT (P₀), as illustrated in Fig. 7A by arrows. As a result, as shown in Fig. 7B, the CAT (P₀) stores the real addresses 00, 01, 02, and 03 in the columns 00, 01, 10 and 11, respectively. Simultaneously with the storing operation, the NOCELL bits in these columns 00, 01, 10, and 11 are turned to "1". In this state, the columns 02, 12, 20, 21 and 22 of the CAT (P₀) and all columns of the CAT (P₁) are free to store any real address. The CAQ stores the real addresses 04, 05, 06, 07 and 08 which are free to be used. From the state shown in Fig. 7B, further assume that another image data as shown in Fig. 7C is to be written in the second page P₀ of the logical space in a sequence from 1 ○ through 5 ○ , i.e., in a sequence of the logical addresses 10, 11, 20, 22, and 02 of the second pace P₁. Then, the real addresses 04 through 08 are sequentially read from the CAQ and stored into the columns 10, 11, 20, 21, and 02, respectively. Simultaneously, the NOCELL bits in these columns are turned to "1". Thus, two pages of image data are allocated to the real addresses of a single page of the CM 92. To read the image data from the CM 92, it is sufficient to specify the logical address. The image data in the corresponding real address allocated to the logical address is then read to the printer assembly. After reading the image data, the read real cell is opened to be used by changing the NOCELL bit in the CAT 91. Therefore, during the reading of one page, simultaneous writing in another page is possible. As a result, a continuous reading operation from the first page to the second page becomes possible. Further, as long as at least one real address is stored in the CAQ, and at least one column of the CAT (P₁) or CAT (P₂) has the NOCELL bit of "0", the real address can be stored in the column. Therefore, the writing of image data in the logical space is not limited to a from top to bottom operation. In Fig. 11C, a circle is written in a lower portion of the logical space, and then a rectangular is written in a upper portion of the logical space. Figure 8 is a flow chart for explaining the operation of the image data buffering circuitry shown in Fig. 5. Referring to Figs. 5 and 8, at step 1201, the logical address for accessing the CAT 91 is determined by the data X₆ through X₁₁ , Y₆ through Y₁₁ , and P. The low order six bits X₀ through X₅ and Y₀ through Y₅ are not taken into account in the description with reference to Fig. 8 because one logical cell consists of 64 bits x 64 bits. The data P represents the page P₀ or P₁. Then, by the determined logical address, the CAT 91 is accessed so that the AOV bit and the NOCELL bit corresponding to the logical address are read. At step 1202, the IMC 99 discriminates whether the AOV bit is "1" or "0". If the AOV bit is "1", the determined address is an inhibited area for writing. Therefore, if the IMC 99 discriminates, at step 1203, that the R/W signal from the I-BUS 38 is a write signal, no process is carried out. If the R/W signal is a read signal, then, at step 1204, the IMC 99 outputs "0" which is transferred through the multiplexers 98, 97, EORb 95, data bus D₀ through D₁₅ , and the I-BUS 38, to the PRC 35, so that a white space is printed. If the AOV bit is "0" at step 1202, IMC 99 discriminates the NOCELL bit. If the NOCELL bit is "0", this logical address can be allocated to a real address. If, at step 1206, the R/W signal is the read signal, a white space is printed at step 1204 because the real cell allocated to this logical address has been read and is not in use as the NOCELL bit is "0". If the R/W signal is the write signal, however, then, at step 1207, the IMC 99 discriminates whether or not CAQ 93 is empty by a signal EMP from the CAQ 93. If the CAQ 93 is empty, no real cell can be used so that, at step 1208, the IMC 99 sets the REJ to "1". The reject signal REJ is transferred through the I-BUS 38 to the IMH 34. In response to the reject signal REJ of "1", the IMH 34 again accesses the IMM 301. If the CAQ 93 stores at least one real cell at step 1207, then, at step 1209, the IMC 99 generates a read signal QR so that the real address is read from the CAQ 93. Then, at step 1210, the IMC 99 generates a write signal CATWT so that the taken out real address is stored in the logical address of the CAT 91. Simultaneously, the NOCELL bit in this logical address is turned to "1". Then, at step 1211, the IMC 99 generates a write signal CMWT so that, by the specified logical address, data from the IMH 34 through the I-BUS and data bus D₀ through D₁₅ is written into the real cell which is allocated to the specified logical address. If the NOCELL bit is "1" at step 1205, this means that a real cell has been allocated to the specified logical address. Therefore, at step 1212, the real address allocated to the specified logical address is read from the CAT 91. Then, at step 1213, if the R/W signal is the write signal, step 1211 is carried out. If the R/W signal is the read signal, then, at step 1214, data is read from the real address of the CM 92. The read data is transferred through the data bus D₀ through D₁₅ and the I-BUS 38 to the PRC 35. At step 1215, the IMC 99 discriminates whether or not a DUMP signal is transferred from the PRC 35. The DUMP signal is generated after each real cell is read. The DUMP signal signifies in lateral accessing (explained hereinafter with reference to Figures 12 and 13) that the data in one real cell having 64 horizontal lines (Y₀ - Y₅) is completely read. The DUMP signal also signifies, in vertical accessing (explained hereinafter with particular reference to Figure 18B) that the data in one real cell having 64 vertical lines (X₀ - X₅) is completely read. If the DUMP signal is received, the IMC 99 generates a write signal CAWT so that the real address of the real cell read at the step 1214 is written into the CAQ 93. Then at step 1217, the NOCELL bit in the specified logic address of the CAT 91 is turned to "0". Figure 9 is a logic circuit diagram of the IMC 99 in the IMM 301 shown in Fig. 5. In Fig. 13, the IMC 99 includes OR gates 131 and 136, and AND gates 132 through 135 and 137 and 138. The IMC 99 receives the signals NOCELL, AOV, R/W, DUMP, and EMP, and outputs the signals BLNK, QR, QWT, CATWT, CMWT, and REJ. The OR gate 131 and the AND gate 132 carry out the process of the steps 1203 through 1208 in the flow chart shown in Fig. 12. The AND gates 133 through 136 carry out the steps 1209 through 1211 and the steps 1215 through 1217. The AND gates 137 and 138 carry out the steps 1202, 1203, 1206, and 1207. Figure 10 shows the structure of the CAT 91 in the IMM 301 shown in Fig. 5. In Fig. 5, each logical address LOG.ADD of the CAT 91 consists of P, Y₁₁ through Y₆, and X₁₁ through X₆. The total number of bits in each logical address is thus 13. Each logical address LOG.ADD corresponds to one logical cell LC in the logical spaces LS. Each logical cell LC consists of 64 bits x 64 bits. One page of the logical space LS consists of 64 x 64 = 4096 logical cells LC. Therefore two pages of logical space consists of some 8 K logical cells. Accordingly, the number of logical addresses of the CAT 91 is 8 K words, each consisting of 13 bits. Thus the CAT 91 effectively comprises two address correspondence stores for use respectively in reading/writing image-defining data of two different images. Figure 11 shows the structure of the CM 92 in the IMM 301 shown in Fig. 5. In Fig. 11 each real address of the CM 92 consists of 19 bits, i.e., A₃ through A₀ from the EORa 94, A₇ through A₄ from the I-BUS 38, and A₁₈ through A₈ from the CAT 91 through the MPXa 96. In the foregoing description with reference to Fig. 8, the low order bits of the logical address or real address are not taken into account. However, in practice, the low order bits are used in order to develop the image data into a bit pattern in the CM 92, and, in particular, in order to realise the lateral accessing or vertical accessing, as later described in more detail. The CM 92 consists of 16 memory chips CP₀ through CP₁₅. Each memory chip consists of 512 K bits. Therefore, the CM 92 consists of 512 K x 16 = 8000 K bits, i.e. 512 K words, where one word consists of 16 bits. Since a real cell RC consists of 256 words, the CM 92 consists, in this example, of 2 K real cells. Remember that the logical space for one page consists of 4 K cells as described with reference to Fig. 10. The reason why the number of real cells is smaller than the number of logical cells is because the size of the printing page does not always require the same address space as the logical space. For example, when the printing paper has different longitudinal and horizontal side lengths, the real address space does not require the full square of the longer side. The high order address signals A₁₈ through A₈ are obtained by address conversion from the address signals X₆ through X₁₁, Y₆ through Y₁₁, and P by the CAT 91 and the CAQ 93, as described before with reference to Figs. 6 through 8. The middle order address signals A₇ through A₄ are directly obtained from the address signals X₄, X₅, Y₄, and Y₅. These addresses are commonly specified for all of the memory chips CP₀ through CP₁₅. The low order address signals A₃ through A₀, however, are different for respective memory chips CP₀ through CP₁₅. These address signals A₃ through A₀ are obtained by converting the addresses X₃ through X₀, and Y₃ through Y₀ by the EORa 94, as later described in detail. This conversion is necessary in order to carry out lateral accessing, vertical accessing, or plane accessing. A specific example of a vertical accessing operation performed by the Fig. 4 circuitry will be described later with reference to Fig. 18B, but briefly, if vertical accessing is carried out, an accessing operation is to be affected on an area of 1 bit in the X direction x 16 bits in the Y direction in the CM 92. However, as will be seen from the structure of the CM 92 shown in Fig. 11, the 16 bits in the Y direction are all included in the same memory chip, and it is impossible to simultaneously access plural addresses on the same memory chip. By performing the above-mentioned address conversion, accessing of one word becomes possible in the lateral, vertical or plane accessing modes. The lateral, vertical, and plane accessing operations per se are discussed in Japanese Patent Application No. 58-117405. Here, a brief explanation of the lateral accessing and vertical accessing is given with reference to Figs. 12 and 13. Figure 12 is a block diagram showing in detail the EORa 94 and the EORb 95 in the IMM 301 shown in Fig. 5. In Fig. 12, the EORa 94 includes a multiplexer 161 and an address arranging circuit (A) 162. The EORb 95 includes an address rearranging circuit (RAR) 163, and sixteen multiplexers 164-1 through 164-16. The multiplexer 161 receives the address signals X₀ through X₃ , Y₀ through Y₃ , and a function signal FUNK indicating whether the access to the CM is a vertical access (1 bit x 16 bits), horizontal access (16 bits x 1 bit), or plane access (4 bits x 4 bits). In response to the function signal FUNK, the multiplexer selects output signal R₀ through R₃. The relationship between the function signal FUNK and the output signals R₀ through R₃ is shown in a table in Fig. 12. That is, when the function signal FUNK is 00, indicating that vertical accessing should be carried out, then the multiplexer 161 selects the address signals X₀ through X₃ as the output signals R₀ through R₃. When the FUNK is 01, indicating that plane accessing should be carried out, the multiplexer 161 selects the address signals X₀ , X₁ , Y₀ , and Y₁ as the output signals R₀ through R₃. When the FUNK is 11, indicating that horizontal accessing should be carried out, the multiplexer 161 selects the Y₀ through Y₃ as the R₀ through R₃. The R₀ through R₃ are supplied to the AR 162 and to the RAR 163. The AR 162 generates, in accordance with a predetermined rule and in response to the FUNK, sixteen addresses as the low order addresses (A₀ through A₃) x 16 for accessing respective memory chips CP₀ through CP₁₅. The sixteen addresses (A₀ through A₃) x 16 differ from each other, as mentioned with reference to Fig. 11. Thus, the low order addresses (A₀ through A₃) x 16 are determined for the vertical, lateral, or plane accessing. To write data in or to read data from the CM 92, the RAR generates, in accordance with an another predetermined rule and in response to the FUNK, sixteen data selecting signals. Each of the data selecting signals consists of four bits. These data selecting signals are applied to the multiplexers 164-1 through 164-16 respectively. Thus, the multiplexers 164-1 through 164-16 respectively select corresponding data transferred from the MPXb 97 (Fig. 9), as data to be output. The data output from the multiplexers 164-1 through 164-16 is then transferred to the CM 92 to be written therein or to the I-BUS 38 as read data. By the above-described arrangement and rearrangement of the address signals R₀ through R₃ , the addresses of 16 bits for one accessing operation always construct one word from sixteen memory chips CP₀ through CP₁₅. Figure 13A is a diagram for explaining a feeding direction of a printing paper PA₁ , for printing a so-called portrait style. Figure 13B is a diagram for explaining another feeding direction of a printing paper PA₂ , for printing a so-called landscape style. The printing papers PA₁ and PA₂ often have different longitudinal and horizontal side lengths. The feeding direction in both cases is usually perpendicular to the shorter side of the printing paper because of the drum size of the printer assembly. For the portrait style, the characters and pictures are printed in the direction parallel to the shorter side of the printing paper PA₁ , as shown in Fig. 14A. For the landscape style, the characters and pictures are printed in the direction parallel to the longer side of the printing paper PA₂ , as shown in Fig. 14B. When writing data in the portrait style, horizontal accessing is preferable, and when writing data in the landscape style, vertical accessing is preferable. In Figs. 13A and 13B, the logical space LC is shown as a square. The point O on the upper left side of the logic space LS is the origin of the logical space LS. Since the side length of the printing page PA₁ or PA₂ is shorter than the side of the square logical space, the slashed area is not necessary. Therefore, the logical addresses in the slashed area are provided with the AOV = "1", as described before. By this simple method, no real address is allocated to these logical addresses provided with the AOV = "1". As a result, the real memory may have been a smaller address space that the logical space as mentioned before with reference to Fig. 11. In both the portrait and the landscape styles, the PRC 35 (Fig. 4) reads the CM 92 (Fig. 5) in the direction perpendicular to the paper feeding direction. Operation of the image data processing device 3 shown in Fig. 4 will now be described in detail with reference to Figs. 15 to 18. Figure 15A is a flow chart for explaining the data flow from the CHC 32 to the IMH 34 in the device 3 shown in Fig. 4. Referring to Figs. 4 and 15A, at step 501 the CTP 31 receives an instruction code IC and data D from the CPU 1 through the CHC 32. The instruction code IC has a format shown, as an example, in Fig. 15B. The instruction code in this example consists of one byte, i.e. 8 bits from 0 through 7. The main contents of the instruction code indicate whether the data from the CPU 1 is character date CD or graphic data GD, or constitutes an instruction to access the contents of FCB 336 (Fig. 4) which determines the vertical position and the line pitch on a page when the data from the CPU 1 is the character data. In Fig. 15B, when only the most significant bit 7 in the high order four bits is "1", the instruction code indicates that the data from the CPU 1 is character data. In this case, the low order four bits 0 through 3 represent a channel number CH.NO, which determines a line on a page, i.e. the vertical position of the character to be printed out on a page. When only the next significant bit 6 is "1", the instruction code indicates that the data from the CPU 1 is graphic data. When only the bit 5 is "1", the instruction code constitutes an instruction to access the FCB 334. An instruction code having another bit pattern can issue an instruction to operate the printer assembly. At step 502, the CTP 31 stores the data from the CPU 1 into the IB 330 in the GLM 33 without any modification of the received data. At step 503, the CTP 31 analyses the instruction code IC so as to determine whether the data is character data CD or graphic data GD. If the received data is graphic data GD, then, at step 504, graphic data processing is carried out by a graphic generator including the GDB 332, the VGC 341, and the IMM 302. If the received data is character data CD, then, at step 505, the vertical position of the character to be printed out on a line of one page is determined with reference to the FCB 334 based on the received instruction code. The format of the FCB 334 is shown as an example in Fig. 15C. The contents of the FCB 334 are previously determined in accordance with the desired printing format. Assume that the length of one page 50 is 12 inches, and that the minimum line pitch between adjacent lines is 12 lines/inch. Then the maximum line number on one page is 144 lines, 0 through 143. Accordingly, the FCB 334, which determines the vertical position of each line on the page, consists, at maximum, of 144 columns,"0" through "143", each column corresponding to one line on the page 50. Each column in the FCB 334 consists of a line pitch control data LP indicating the line pitch and a channel number CH.NO. indicating a line to be skipped. The channel number CH.NO is one of "0" through "12". The same channel numbers may be provided in different columns in accordance with the desired printing format. The CTP 31 counts up the number of times the same channel numbers are received. For example, when the instruction code specified at first the channel number "1" in the FCB 334 shown in Fig. 15C, the CTP 31 searches, starting from the column "0", the first "1" of the channel number. Since the first channel number "1" is stored in the column "3" in this example, the CTP 31 moves its pointer to control the line "3". Then, assume that the instruction code specifies the channel number "1" again, the CTP 31 searches the second "1" of the channel number. The second channel number "1" is stored in the column "5". Therefore, the CTP 31 skips its pointer from the column "3" to the column "5". If the next instruction code specifies the channel number "7", the CTP 31 moves its pointer from the column "5" to the column "143" if the columns "0" through "142" do not store the channel number "7". The line pitch LP is one of "0", "1", and "2", which respectively represent that the pitch between adjacent lines are 6 lines/inch, 8 lines/inch, and 12 lines/inch. Assume that the resolution of the printer is 240 dots/inch. Then the character data on the first line "0", if specified by the instruction code, is developed at the position vertically lower by 40 dots from the top of the page, because the first column "0" contains the line pitch "0", i.e., 6 lines/inch, and therefore, one line needs 40 dots in the vertical direction. Also, the character data on the second line "1", if specified by the instruction code, is developed at the position vertically lower by 30 dots from the first line "0", because the second column "1" contains the line pitch "1", i.e., 8 lines/inch, and therefore, one line needs 30 dots in the vertical direction. Referring back to Figs. 4 and 15A, after the step 505, the CTP 31 reads the character data byte by byte from the IB 330 in the GLM 33. The read data is processed as a hexadecimal Extended Binary-Coded Decimal Interchange Code (EBCDIC) of a character code. That is, at step 506, the read character code is translated into a top address of the character pattern stored in the CG 335 of the GLM 33, with reference to the character translation table (TT) 337 in the GLM 33. The relationship between the CG 335 and the TT 337 is shown in Fig. 5D. In Fig. 5D, the TT consists of 256 columns. Each column stores the top address of a character pattern corresponding to the character code (EBCDIC). The CG 365 stores character patterns for characters A, B, C, ... . As an example, when a character code C.C. of "01" in the hexadecimal expression is read from the IB 330, the CTP 31 searches the column "1" of the TT 337, with the result that the top address TA = a t1 of the character "A" is identified. The identified top address a t1 is stored at step 507, in the PB 331. Similarly, when a character code of "03" is specified, the top address TA = a t2 of the character B is identified and stored, at step 507, in the PB 331. Figure 15E shows the format of the page buffer (PB) 331. In Fig. 15E, other than the above-mentioned top addresses TA of the character patterns, movement amounts MA in the horizontal direction and addresses PMDA for accessing a printing-data memory (see Fig. 6) in the CGC 371 are also stored, at step 507, in the PB 331. The printing-data memory will be described later in more detail. The movement amounts MA are explained with reference to Fig. 15F. As shown in Fig. 15F, the movement amounts are the distances from the print start positions of characters on a page in the horizontal direction. The print start position for each line on a page is stored in the printing-data memory. For example, in Fig. 15F, the movement amount for the character "A" is "0"; the movement amount for the character "B" is "S₁"; and the movement amount for the character "C" is "S₂". When the size of a character in the horizontal direction is defined as 10 characters/inch, and when the resolution is 240 dots/inch, then the distance in the horizontal direction between a start address of one character and a start address of the next character is 24 dots. In this case, S₁ is 24 and S₂ is 48. After all of the character codes for one page are processed, by repeating the steps 506 to 508 in the manner mentioned above, the CTP 31 sets, at step 509, an end flag EF in the PB 331. In this state, the PB 331 stores the character information for all characters to be printed on one page, including the movement amounts MA, the top addresses TA of the character patterns, and the addresses PMDA for accessing the printing-data memory. Then, at step 510, the CTP 31 sets the necessary parameters in the CGC 340. These parameters are necessary for developing the character data into a bit pattern data. Finally, at step 511, the CTP 31 requests the CGC 340 to develop the character data into bit pattern data. The CGC 340 then starts to operate. Figure 16 shows a block diagram of the CGC 340 in the device 3 shown in Fig. 4. In Fig. 6, the CGC 340 includes the printing-data memory (PDM) 61 as mentioned before, a control register 62, a CGC controller (CONT) 63, a CG access circuit (ACS) 64, and a write circuit (WC) 65. The PDM 61 and the control register 62 store necessary parameters as described before with reference to Figs. 15A and 15E, and in particular, at step 510 in Fig. 15A. More specifically, the PDM 61 stores starting addresses of respective lines to be printed on one page, and a plurality of character parameters including a flag indicating whether the character to be printed should be rotated or not, a width, and a height, for each character. The control register 62 includes a command register (C.REG) 621 for storing a start command for starting the operation of the CGC 340, a status register (S.REG) 622 for storing status data of the CGC 340, a memory address register (MA.REG) 623 for indicating a top address TA in the PB 331, and a line address register (L.REG) 624 for storing a vertical position (see FCB in Fig. 15C) of the character to be printed. These data in the PDM 61 and in the control register 62 are set under the control of the CTP 31 in the device 3 shown in Fig. 4. After the CTP 31 sets the contents of the PB 331, provides the data in the PDM 61, sets the top address of the PB 331 in the M.A. REG 623, and sets the vertical position in the L.REG 624, then the CTP 31 writes a start command into the command register 621. In response to the start command from the command register 621, the CONT 63 starts to operate as follows: (1) By using the top address of the PB 331 stored in the memory address register 623, the CONT 63 reads the data stored in the PB 331. The PB 331 has previously stored the data including the top addresses TA of the character patterns in the CG 335, the movement amounts MA, and the addresses of the PDM 61, for one page, as described before with reference to Figs. 15D, 15E, and 15F. The data read from the PB 331 includes the same top address TA as the top address transferred from the memory address register 623. (2) The top address TA read from the PB 331 is transferred through the CONT 63 to the ACS 64. The CONT 63 calculates the position of the character to be written, based on the data of the starting address of a line stored in the PDM 61 and the movement amount MA included in the data read from the PB 331. Further, by using the address PDMA of the PDM 61, the address being included in the data read from the PB 331, the CONT 63 reads the corresponding character parameters from the PDM 61, and transfers the read character parameters to the WC 65. Then the CONT 63 activates the WC 65 to start its operation. (3) The WC 65 then sends a CG request signal to the ACS 64. The ACS 64 then accesses the CG 335 so as to read one line of the character pattern "A", for example, specified by the data from the PB 331. The read one line of the character pattern is written into the IMM 301. In the writing operation, a vertical writing or a horizontal writing is carried out as later described in more detail. After one line of the character pattern is read from the CG 335, the ACS 64 increments the address for accessing the CG 335. (4) The operation as described in the above item (3) is repeated for each line of the character pattern. When the character pattern is completely written into the IMM 301, the WC 65 informs the CONT 63 that the writing operation of the character pattern is finished. (5) Then, the CONT 63 again accesses the PB 331 so as to read subsequent data for the next character to be written, and the operation similar to that described above in items (1) through (4) is repeated. The above operation is sequentially repeated until the end flag EF is read from the PB 331 to the CONT 63. When the end flag EF is read, the CONT 63 informs the CTP 31 (Fig. 4) through the status register 622 that the writing operation for one page is finished. Figure 17 shows in detail the write circuit (WC) 65 included in the CGC shown in Fig. 16. In Fig. 17 the WC 65 includes a parallel-serial converting shift register (SRa) 650, a serial-parallel converting shift register (SRb) 651, an X counter 652, a Y counter 653, an H counter 654, a V counter 655, a write control circuit (WCC) 656, and a multiplexer 657. The X counter 652 is a counter for supervising the X addresses of the IMM 301; the Y counter 653 is a counter for supervising the Y addresses of the IMM 301; the H counter 654 is a counter for supervising the width of a character; and the V counter 655 is a counter for supervising the height of a character. Figure 18A is a flow chart for explaining the operation of the WC 656 shown in Fig. 17 In Fig. 18A, and in the following description of the operation of the WC 656, a horizontal accessing process is mainly described. In the flow chart, all vertical accessing processes are placed within parentheses. The operation is carried out in the following sequence. (1) At start-up, after the WCC 656 has received, from the CONT 63 (Fig. 16), a writing position X₁ and Y₁ (X₂ and Y₂ in a vertical accessing), a width H, and a height V of a character to be printed, and after the CONT 63 has activated the WC 656 to start its operation, then, at step 801, the WC 656 sets these values X₁ , Y₁ , H and V in the X, Y, H, and V counters 652 through 655, respectively. (2) When the SRa 650 is recognized as being empty by the WCC 656, then, at step 802, it sends a request signal REQ to the ACS 64 (Fig. 16) requesting character data in the CG 335. (3) At step 803, the WCC 656 delays its operation until 16 bits of the read character data are set in the SRa 650. When the read data is set in the SRa 650, the address of the ACS 64 (Fig. 16) for accessing the CG 335 is incremented. (4) At step 804, the WCC 656 clears the SRb 651. (5) At step 805, one bit of data serially output from the SRa 650 is shifted into the SRb 651 under the control of the WCC 656. (6) At step 806, the WCC 656 increments the X counter 652 (decrements the Y counter 653), and decrements the H counter 654. (7) At step 807, the WCC 656 discriminates whether or not the SRb 651 is full of data, i.e., whether or not the low order four bits of the X counter 652 are all "1" in the horizontal accessing process. That is, the WCC 656 discriminates whether or not 16 bits of data, i.e., one data unit, which is an accessing unit for accessing the IMM 301, are shifted into the SRb 651. At step 807 also, the WCC 656 discriminates whether or not the H counter 654 is empty, i.e., whether or not the amount of data transferred from the CG 335 reaches the full width H of the character. If both answers are "NO", then, the steps 805 through 807 are repeated. If at least one of the answers is "YES", then step 808 is executed. (8) At step 808, the WCC 656 discriminates whether or not the contents in the SRb 651 are all "0". If the contents are all "0", no accessing for writing is carried out, and the process goes to the step 814. Since no writing operation is carried out when the SRb 651 contents are all "0", a high speed processing is realized when the character pattern includes a large white area. If the SRb 651 contains at least one bit of "1", then step 809 is executed. (9) At step 809, the WCC 656 generates a request signal REQ for memory write accessing. The request signal REQ is supplied to the IMM 301. (10) At step 810, the WCC 656 waits until an access permission signal ACK is transferred from the IMM 301. This waiting is necessary only if another device is using the I-BUS 38 (Fig. 4). (11) At step 811, the data D₀ through D₁₅ in the SRb 651, the data X₀ through X₁₁ in the X counter 652, and the data Y₀ through Y₁₁ in the Y counter 653 are transferred through the I-BUS 38 to the IMM 301. Thus, 16 x 1 bits of data are written into the IMM 301 at a logical writing address determined based on the data X₀ through X₁₁ and Y₀ through Y₁₁ , as described hereinbefore in more detail. If, however, none of the logical addresses are opened for the writing operation, as was described hereinbefore in detail, then the logical writing address cannot be determined until at least one logical address is opened for writing. In this case, the IMM 301 generates a rejection signal. (12) At step 812, the WCC 656 discriminates whether or not the reject signal is transferred from the IMM 301. If transferred, the process goes to step 813; if not, the process goes to step 814. (13) At step 813, the process stops for an appropriate time period to avoid the occupation of the I-BUS 38. After that time period, the steps 810 through 812 are repeated. (14) At step 814, the WCC 656 discriminates whether or not the H counter is empty. If one line of the character is not processed, the process then goes to step 804. (15) If one line of the character has been processed, the process goes to step 815; at which the WCC 656 discriminates whether or not the V counter 655 is empty. If empty, the character has been completely written into the IMM 301. If not empty, the process goes to step 816. (16) At step 816, for the next line in the character, the X counter (Y counter) and the H counter are reset; the Y counter (X counter) is incremented; and the V counter is decremented. Then, the process goes to step 802. The reason why the two shift registers SRa 650 and SRb 651 are provided in the WC 65 will be understood with reference to Fig. 18B, in which write positions on the logical space of the IMM 301 are illustrated for both the lateral access and the vertical access. The width H of the character A is illustrated as 32 bits. The SRa 650 at first receives 16 bits from the CG 335, as indicated by slash lines. The top address of the character pattern A is (X₁ , Y₁) for the lateral access or (X₂ , Y₂) for the vertical access. As shown in Fig. 18B, the X address X₁ or the Y address Y₂ does not always coincide with the most significant bit MSB of the 16 bits. In the example, the X address X₁ or the Y address Y₂ is spaced from the MSB by 6 bits. Since the WCC 656 knows the X address X₁ or the Y address Y₂ , the SRb 651 does not store the high order 6 bits, and only the remaining 10 bits are sequentially shifted into the SRb 651, from the higher order bit, i.e., bit 9, to the lower order bit, i.e., bit 0. Thus, the SRb 651 outputs only 10 bits at the first writing operation. Since the high order 6 bits in the received 16 bits are neglected, the operating speed is increased. In the second writing operation, all 16 bits are shifted from the SRa 650 to the SRb 651. In the third writing operation, however, only the high order 6 bits in the received 16 bits are shifted into the SRb 651. Figure 19 is a block diagram showing the general constitution of the PRC 35 shown in Fig. 4. In Fig. 19, the PRC 35 includes an IMM interface control circuit (INT CONT) 191, an address control circuit 192, a mode control circuit (MOD CONT) 193, a video control AND gate 194, a shift register (SR) 195, and a data buffer register (DBR) 196. The PRC 35 sends various control signals from the INT CONT 191, the ADD CONT 192, and the MOD CONT 193 through the I-BUS 38 to the IMM 30 (Fig. 4). The DBR 196 receives image data (IMD) from the IMM 30 through the I-BUS 38. The data once stored in the DBR 196 is transferred to the SR 195. The SR 195 then converts the image data into serial data in accordance with a control signal from the INT CONT 191. The serial data from the SR 195 is gated by the AND gate 194. Thus, the video signal VS is obtained as a logical product of the serial data and a video control signal (VCS) from the INT CONT 191. The INT CONT 191 sends the dump signal DUM when the PRC has read one real cell, so as to open the real cell, i.e., to allow it to be used for writing new data therein. The MOD CONT 193 controls the reading direction, i.e., the portrait or the landscape by generating a mode signal MOD. The ADD CONT 192 controls the reading address. Figure 20 shows the constitution of the INT CONT 191. In Fig. 20, a line address counter (CNT) 201 counts one scanning line (64 counts). Based on the counting value, a signal generator (SIG GEN) 202 generates a timing data IBACC for transferring address signals and mode data, the timing data being supplied to the ADD CONT 192 and MOD CONT 193 (Fig. 19), the data request signal REQ, the video control signal VCS, and the data set timing signal DST being applied to the DBR 196 and the SR 195 (Fig. 19). Also, a dump instructing circuit (DUM) 203 generates the dump signal DUM based on the addresses X₀ through X₅ and Y₀ through Y₅ for accessing the IMM 30. Figure 21A shows the constitution of the address control circuit (ADD CONT) 192 shown in Fig. 19. In Fig. 21A, reading addresses X₀ through X₁₁ and Y₀ through Y₁₁ are obtained as follows. When the mode signal MOD specifies the portrait style as shown in Fig. 13A, a count value "0" is initially loaded from a multiplexer 211 into an up/down counter 212 for generating the X addresses X₀ through X₁₁. Then an up/down control signal U/D CONT controls the U/D CNT 211 so as to count up by sixteen in response to one clock signal CLK X which represent a data set timing (CLK 1). While, a counter (CNT) 213 counts up from zero by one in response to a one line (64 counts) scanning (CLK Y = CLK 2) . When the mode signal MOD specifies the landscape style as shown in Fig. 13B, a value representing the width in the X direction of the printing paper is loaded from a register (REG) 214 into the U/D CNT 212 for generating the X addresses. The value is transferred from the C-BUS 36 and is previously stored in the register 214. Then the U/D CNT 212 counts down by one in response to one line (64 counts) scanning (CLK X = CLK 2) . The CNT 213 for the Y addresses counts up by sixteen in response to the data set timing (CLK Y = CLK 1) . Figure 21B shows a logic circuit for generating the clock signals CLK X and CLK Y. As will be seen from Fig. 21B, when the portrait style printout takes place, MOD is "1" and *MOD is "0" so that the CLK X is equal to the CLK 1 and the CLK Y is equal to the CLK 2. When the landscape style printout takes place, *MOD is "1" and MOD is "0" so that the CLK X is equal to the CLK 2, and the CLK Y is equal to the CLK 1. The present invention is not restricted to the foregoing description of the embodiment, and various changes and modifications are possible within the scope of the invention. For example, although the explanation of the IMM 30 is mainly described with respect to the character generator controller (CGC) 340, the principal idea of the allocation of the real cells to logical addresses in an embodiment of the invention can be similarly applied when the vector generator controller (VGC) 341, the overlay pattern controller (OVC) 342, or the image generator controller (IMC) 343 is activated. Further, the unit of the real cell or logical cell is not restricted to the described example of 64 bits x 64 bits, but may be of any scale including 1 bit x 1 bit. Still further, in the foregoing description the CAQ 93 is described as a "first-in first-out" (FIFO) circuit. However, in place of the CAQ 93, any memory can be used for storing the real addresses which are not being used as long as its input sequence and output sequence are controlled under a certain acknowledgeable condition. Thus there can be provided image data buffering circuitry in which a single image memory plane can be used for simultaneous reading and writing of different pages even when writing is effected out of sequence. From the foregoing description, it will be apparent that an embodiment of the invention can provide improved data buffering circuitry in which the real memory storing capacity may be decreased without reducing the reading speed, and in which the writing of image data in one page of a logical space is not limited to a sequential (from-top-to-bottom) operation, so that new image data can be written in any position on the page as long as at least one real cell is not currently being used to store existing data. In a preferred embodiment of the invention, continuous reading of different pages in the logical space can be achieved using a single real memory space, i.e. without employing different real memory spaces. Accordingly embodiments of this invention may be particularly advantageous in the field of high speed transmission of image data from image memory to, for example, a laser printer.

Claims: Image data buffering circuitry comprising: a memory (CM 92), having a plurality of individually addressable data storage locations (RC), for storing data defining an image sub-divided into a plurality of spacial units (LC); address storage means (CAQ 93) for storing addresses (REAL ADD) of such locations (RC) that are available for the storage of new data; an address correspondence store (CAT 91) having storage areas corresponding respectively to the said spacial units (LC) and accessible by means of respective address codes (LOG ADD); writing means for writing the image-defining data, if any, of any chosen one of the said spacial units (LC) into an individual one of such available locations (RC), which available location has been selected by taking the address (REAL ADD) of that location (RC) from the address storage means (CAQ 93), and for placing the address (REAL ADD) of that selected location (RC) in the individual storage area of the correspondence store (CAT 91) that corresponds to the chosen spacial unit (LC); and reading means for employing the address code (LOG ADD) appropriate to the storage area that corresponds to a selected one of the said spacial units (LC) to read out from the said memory (CM 92) the image-defining data, if any, of the selected spacial unit (LC) and for adding back to the said address storage means (CAQ 93) the address (REAL ADD) of the storage location (RC) from which that image-defining data has been read out. Circuitry as claimed in claim 1, having two such address correspondence stores (CAT 91) for use respectively in reading/writing image-defining data of two different images, the operation of the writing and reading means being such that data defining one of the images can be written into the said memory (CM 92) while data defining the other image is being read out from that memory. Circuitry as claimed in claim 1, wherein the number of said storage areas in the said address correspondence store (CAT 91) is at least twice the number of the said data storage locations (RC) in the said memory (CM 92). Circuitry as claimed in claim 1, 2 or 3, wherein each of the said storage areas in the correspondence store (CAT 91) has associated therewith an individual correspondence-indicating bit (NOCELL) for indicating whether or not there is image-defining data, of the corresponding spacial unit (LC), stored in the memory (CM 92) at a location whose address is held in the storage area concerned, the circuitry being such that when the image-defining data of a selected spacial unit (LC) is written into the memory (CM 92) the said correspondence-indicating bit (NOCELL) associated with the corresponding storage area is set by the writing means, and such that when the image-defining data of that spacial unit (LC) is read out from the memory the said correspondence-indicating bit (NOCELL) associated with the corresponding storage area is reset by the reading means. Circuitry as claimed in claim 4, wherein the said reading means, on detecting that the said correspondence-indicating bit associated with a storage area selected for reading is in the reset condition, generates a blank data signal as the image-defining data for the corresponding spacial unit (LC). Circuitry as claimed in any preceding claim, wherein the said address storage means (CAQ 93) is a first-in first-out circuit. Circuitry as claimed in any preceding claim, wherein the said correspondence store (CAT 91) also has individual correspondence-inhibiting bits (AOV), associated respectively with the said data storage areas, which bits can be set to prevent the image-defining data of the corresponding spacial units being written in the said memory. Circuitry as claimed in claim 7, wherein the said reading means, on detecting that the correspondence-inhibiting bit (AOV) associated with a storage area selected for reading is set, generates a blank data signal as the image-defining data for the corresponding spacial unit (LC).

Inventors: ITOH, SUMIO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F3
IPC codes: G06F5, G06T1, G06K15, G06F12, G06F3