Multi-stage amplifier with frequency compensation

Abstract: A multi-stage amplifier (21) has three or more amplifier stages (A1, A2 and A3) arranged in a capacitatively nested configuration for frequency compensation. The technique consists of nesting two of the stages (A1, A2) together with a pole-splitting capacitor (C1) to forms stable device (11) and then nesting this device and a third (A3) of the stages together with another pole-splitting capacitor (C2) to form the amplifier (21).

Description: This invention relates to an amplifier for amplifying an input signal received at least partially at an inverting input thereof to produce an inverted output at an output thereof, the amplifier comprising: a composite amplifier section comprising: a first stage for amplifying an input signal received at least partially at an inverting input thereof to produce an output signal at an output thereof, a first capacitor coupled between the output and the inverting input of the first stage, and a transconductance second stage for amplifying an input signal received at least partially at a non-inverting input thereof to produce an output signal at an output thereof, the output of one of the first and second stages coupled to the input of the other of the first and second stages, the remaining input of the first and second stages coupled to an inverting input of the composite section, and the remaining output of the first and second stages coupled to an output of the composite section, a second capacitor coupled between the output and the inverting input of the composite section, and a transconductance third stage for amplifying an input signal received at least partially at a non-inverting input thereof to produce an output signal at an output thereof, the output of one of the composite section and the third stage is coupled to the input of the other of the composite section and the third stage, the remaining input of the composite section and the third stage coupled to the input of the amplifier, and the remaining output of the composite section and the third stage coupled to the output of the amplifier. An operational amplifier (or "op amp") having an inverting (or negative) input terminal, a non-inverting (or positive) input terminal, and an output terminal is typically employed in an amplifier system with a feedback network connected between the output and input terminals. The op amp amplifies an input signal received at the input terminals (or simply "inputs") to produce an output signal at the output terminal (or simply "output"). The gain in the negative feedback loop is µβ where µ is the forward gain of the op amp and β is the gain of the negative feedback network. Depending on the configuration, µ and β may be either voltage gain or current gain. When the input signal varies at some frequency, the output signal varies similarly. At low frequency, they are substantially in phase. As frequency increases, the phase of the output signal lags progressively behind the phase of the input signal. The loop gain µβ falls off. The system can become unstable. If the phase difference between the signals reaches 180° while µβ is greater than 1, the system oscillates because the feedback is positive. The minimum acceptable stability margin is considered to occur when the loop phase difference equals 135° at the point where µβ is 1. This roughly translates into the stability rule that the loop gain not fall off more than 9dB/octave out to the unity-gain frequency. A feedback network for a system utilizing an op amp is often provided after op amp design is completed. The precise amplitude characteristics of the network thus cannot be taken into account in designing the op amp. The design is typically based on the "worst-case" assumption that the negative feedback gain is one. The resulting stability criterion is that the forward gain µ of the op amp not roll off more than 9dB/oct. out to the frequency where µ is 1. Perhaps the easiest way to meet this stability criterion is with a single transconductance amplifier stage. Fig. 1 generally shows a conventional differential stage A of this type. Fig. 2 illustrates typical internal details for stage A which centers on emitter-coupled NPN transistors QX and QY. Their bases are connected to its inputs to receive voltages V I- and V I+ whose difference is the amplifier input signal V I . Although stage A is basically a transconductance amplifier -- i.e., a voltage-to-current converter, the load impedance converts stage A into a voltage amplifier. Its output signal is a voltage V O supplied at the QX collector. The frequency response of stage A is largely determined by its single dominant pole dependent on the parasitic capacitance CPO at the output. Referring to Fig. 3, it shows asymptotes for how µ varies with frequency f for stage A. The gain drops 6dB/oct. as the frequency f O of the dominant pole is passed and then 6dB/oct. more as the higher pole frequency f L that limits the bandwidth is passed. Bandwidth-limiting frequency f L , which is a characteristic of the overall amplifier system and cannot be altered easily, occurs beyond the unity-gain frequency f U . Stage A thus automatically satisfies the foregoing stability criterion since the gain roll-off is less than 9dB/oct. between f O and f U . No frequency compensation is needed. However, the maximum gain is typically on the order of 40dB. This is much too low for many applications. The gain can be increased by arranging two transconductance amplifier stages in cascade. Fig. 4 generally shows how this is done in a conventional 741 op amp as, for example, described by Gray et al in Analysis and Design of Analog Integrated Circuits (John Wiley and Sons), 1977, pages 420 - 426 and 515 - 521. In the 741, voltage V I is differentially supplied to the inputs of a differential stage A' whose output is connected to the inverting input of an inverting stage A". Its output provides voltage V O . A compensating capacitor C is connected between the A" input and output. This connection enables the combination A" and C to act as a current-to-voltage converter. The overall amplifier thereby provides voltage amplification. Two dominant poles largely determine the frequency response of this two-stage amplifier, one dependent on the parasitic capacitance CPO at the amplifier output and the other dependent on the parasitic capacitance CPA at the A" input. Fig. 5 depicts the asymptotic gain variation for Fig. 4. The upper curve I in Fig. 5 represents how the frequency response would appear if capacitor C were absent, while the lower curve represents the actual compensated response. The pole frequencies associated with capacitances CPO and CPA are respectively referred to as f O and f A . In passing each of frequencies f O , f A , and f L , the gain roll-off increases 6dB/oct. In the absence of capacitor C, f O and f A would be at respective starting points f OS and f AS where µ is greater than 1. The combination A' and A" would not meet the foregoing stability criterion since µ drops 12dB/oct. after f AS is passed. Capacitor C provides frequency compensation by splitting the dominant poles further apart. Lower pole f O moves down to final position f OF , while higher pole f A moves up to final position f AF beyond unity-gain frequency f U . The gain rolls off no more than 6dB/oct. out to f U to meet the stability criterion. The maximum gain is typically on the order of 80dB. Although an improvement, this is still too low for many applications. In U.S. Patent 4,243,943, E. Cherry approaches the gain/stability problem with an amplifier typically having three or more stages arranged in a nest of differentiating feedback loops for frequency compensation. The loops are normally centered on the output stage of the amplifier. The basic objective in Cherry is to maximize the return difference around the output stage. The compensation scheme in Cherry involves pole-zero cancellation in which frequency zeros are employed to shift frequency poles to acceptable locations. This is a complex process which severely limits the use of Cherry. It is therefore the object of the invention to provide a frequency compensated amplifier with a high gain in a relatively simple configuration. An amplifier of the kind mentioned in the preamble is according to the invention characterized in that each of the first, second and third stages has only one pole per signal path within the unity-gain frequency range that the cascaded stages would have in the absence of the first and second capacitors, the value of the first capacitor is selected to make the forward gain of the composite section roll off no more than 9 dB/octave out to its unity-gain frequency, and the value of the second capacitor is selected to make the forward gain of the amplifier roll off no more than 9 dB/octave out to its unity-gain frequency. In accordance with the invention, a multi-stage amplifier particularly suitable for use in op amps has three or more amplifier stages arranged in a capacitively nested configuration to achieve frequency compensation. The basic idea is to capacitively nest a pair of stages to form a stable device and then to do the same with this device and another stage. The forward gain of the amplifier normally falls off no more than 9dB/oct. out to its unity-gain frequency. This allows the amplifier to meet the foregoing stability rule for loop gain when the circuit is used with a negative feedback network having a gain of unity or less. The nesting in the amplifier centers on one of the stages here referred to as the first stage. This stage functions (at least) like an inverting amplifier. It has an inverting input and an output. As used herein, "inverting input" means a terminal of an amplifying device whose open-loop output signal is substantially inverse -- i.e., reversed in polarity ignoring phse lag -- either to a signal at the inverting input of the device or, if it has a "non-inverting input", to a signal at the inverting input relative to a signal at the non-inverting input. The remaining stages are referred to as the second stage, the third stage, and so on as necessary. Each of them is a transconductance stage (i.e., a voltage-to-current converter) that functions (at least) like a non-inverting amplifier. As such, each of the remaining stages has a non-inverting input and an output. As used herein, "non-inverting input" means a terminal of an amplifying device whose open-loop output signal is substantially in phase either with a signal at the non-inverting input of the device or, if it has an "inverting input", to a signal received at the non-inverting input relative to a signal received at the inverting input. The nesting begins with a composite amplifier section containing the first and second stages. The output of one of the first and second stages is coupled to the input of theother. The remaining input of these two stages is coupled to an inverting input of the composite amplifier section which has an output coupled to the remaining output of the two stages. A first compensating capacitor is coupled between the output and inverting input of the first stage. The value of the first capacitor is selected to make the forward gain of the composite section roll off no more than 9dB/oct. out to its unity-gain frequency. This meets the foregoing stability criterion to make the composite section suitable for further nesting. In the next-nesting level, the output of one of the composite section and the third stage is coupled to the input of the other of these two components. This creates a three-stage amplifier. It has an inverting input coupled to the remaining input of the composite section and the third stage. The remaining output of these two components is coupled to an output of the three-stage amplifier. A second compensating capacitor is coupled between the output and inverting input of the composite section. The value of the second capacitor is selected to make the forward gain of the three-stage samplifier fall of no more than 9dB/oct. out to its unity-gain frequency so as to meet the gain roll-off stability criterion. Numerous variations of the invention are possible. For example, there are four versions of the three-stage amplifier depending on how its stages are intercoupled. The invention may be embodied with various types of transistors such as bipolar transistors, field-effect transistors (FET's), or both. The FET's could be insulated-gate FET's or junction FET's. Each arrangement of the present amplifier provides high gain in a relatively simple configuration. The compensating capacitors achieve frequency compensation by pole splitting. There is no need to introduce frequency zeros to shift poles. This avoids the difficulty in dealing with pole-zero cancellation as in Cherry. Moreover, there is no particular preference for centering the nesting around the output stage as in Cherry. The present multi-stage amplifier is thus more flexible than Cherry and provides a large improvement over the prior art. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which Figs. 1, 2 and 3 show respectively a block diagram, a circuit diagram, and a logarithmic graph of qualitative asymptotic frequency response for a prior art one-stage amplifier, Fig. 4 and 5 show respectively a circuit diagram and a logarithmic graph of qualitative asymptotic frequency response for a prior art two-stage amplifier, Figs. 6a, 6b, 6c and 6d show block diagrams of embodiments of four versions of a three-stage amplifier having capacitive nesting for frequency compensation in accordance with the invention, Figs. 7a, 7b, 7c and 7d show circuit diagram of bipolar embodiments of the respective amplfiers of Figs. 6a - 6d, Figs. 8a, 8b, 8c and 8d show logarithmic graphs of qualitative asymptotic frequency response for the respective amplifiers of Figs. 6a-6d, Fig. 9, 10a and 10b show respective circuit diagrams for a more generalized embodiment of the amplifier of Fig. 7b, a typical current follower used in this embodiment, and a typical voltage follower used in this embodiment, Fig. 11 shows a circuit diagram of a more particular embodiment of the amplifier of Fig. 7d containing further inter-stage coupling, Fig. 12 shows a circuit diagram of a preferred bipolar embodiment of the amplifier of Fig. 6d, Fig. 13 shows a circuit diagram of an embodiment of a four-stage amplifier having capacitive nesting for frequency compensation in accordance with the invention, and Fig. 14 shows an FET embodiment of the amplifier of Fig. 6b. Like reference symbols are employed to identify the same or very similar item or items in the drawings and description of the preferred embodiments. Actual capacitors are indicated in solid lines in the drawings, whereas parasitic capacitances are indicated in dashed lines. "Parasitic capacitances are defined relative to a reference voltage V REF which is typically ground. Not shown are parasitic capacitances not relevent to the frequency compensation in this invention. Certain elements which appear in the drawings but whose operation or reason for employment is generally self-evident are largely not discussed below. In particular, resistors which are identified by the symbol "R" followed by a suitable subscript are generally not discussed. The resistors shown at the emitters of bipolar transistors or the sources of FET's may be actual resistors or intrinsic resistances. Current sources which are identified by the symbol "I" followed by a subscript containing "E", "C", "S" or "D" are generally not discussed. "E" and "C" respectively indicate emitter and collector current sources for bipolar transistors. "S" and "D" respectively indicate source and drain current sources for FET's. Each amplifier is connected between sources of a low supply voltage and a high supply voltage generally indicated respectively as "V EE " and "V CC " but indicated respectively as "V SS " and "V DD " for Fig. 14. Turning to Figs. 6a - 6d, they respectively illustrate four versions 21, 22, 23 and 24 of a frequency-compensated three-stage amplifier. Each of amplifiers 21 - 24 operates (at least) as an inverting amplifier having an inverting input for receiving voltage V I- and an output for providing voltage V O . Each of amplifiers 21 - 24 preferably also has a non-inverting input for receiving voltage V I+ . Voltages V B1 , V B2 , and V B3 which are typically, though not necessarily constant, are variously provided to amplifiers 21 - 24. The input signal to amplifier 21 or 23 is input current I I received at its inverting input. Amplifiers 21 or 23 amplifies current I I to produce an output current I O as its output signal at its output. The input signal to amplifier 22 or 24 is voltage V I which consists of voltage V I- taken relative to voltage V I+ if there is a non-inverting input. If amplifier 22 or 24 lacks a non-inverting input, voltage V I is voltage V I- taken relative to some reference voltage. Amplifier 22 or 24 amplifies voltage V I to produce voltage V O as its output signal. Amplifiers 21 - 24 are all arranged in the same basic way. Two transconductance stages are nested together with a compensating capacitor to form a combination which meets the stability criterion that the gain of the combination not roll off more than 9dB/oct. out to its unity-gain frequency. This combination and a third transconductance stage are nested together with another compensating capacitor to form a new combination -- i.e., amplifier 21, 22, 23 or 24 -- that satisfies the gain roll-off criterion. As shown in Figs. 6a and 6b, amplifiers 21 and 22 each contain a composite amplifier section 11 which amplifies an input signal current to produce an output signal current. Composite section 11 functions (at least) as an inverting amplifier having an inverting input for receiving the input current and an output for providing the output current. If amplifier 21 has a non-inverting input, it is connected to a non-inverting input of section 11. In amplifier 22, section 11 may have a non-inverting input for receiving voltage V B1 . Section 11 contains transconductance amplifier stages A1 and A2, each of which amplifies an input signal to produce an output signal at its output. Stage A1 functions (at least) as an inverting amplifier having an inverting input connected to the inverting input of section 11. If section 11 has a non-inverting input, it is connected to a non-inverting input of stage A1. Stage A2 operates (at least) as a non-inverting amplifier having a non-inverting input connected to the output of stage A1 to receive its output signal. Stage A2 may have an inverting input for receiving voltage V B2 . The A2 output is connected to the output of section 11. A compensating capacitor C1 is connected between the output and inverting input of stage Al to provide frequency compensation for amplifier 11. This connection makes the combination A1 and C1 into a current-to-voltage converter across the frequency range in which capacitor C1 dominates the transfer function. Since stage A2 is a transconductance device -- i.e., a voltage-to-current converter, section 11 is a current amplifier. In addition to section 11, amplifier 21 or 22 contains a compensating capacitor C2 and a transconductance amplifier stage A3 which amplifies an input signal to provide an output signal at its output. Stage A3 operates (at least) as a non-inverting amplifier having a non-inverting input. Capacitor C2 is connected between the output and inverting input of section 11 to provide frequency compensation for amplifier 21 or 22. In amplifier 21, the inverting input of section 11 is connected to the inverting input of amplifier 21 to receive signal current I I . The non-inverting A3 input is connected to the output of section 11 to receive its output amplifier 21 to provide signal current I O . Stage A3 in amplifier 21 may have an inverting input for receiving voltage V B3 . The connection of capacitor C2 across section 11 causes the combination 11 and C2 to operate as a current-to-voltage converter over the frequency range in which capacitor C2 dominates the transfer function. Since stage A3 is a voltage-to-current converter, amplifier 21 is a current amplifier. In amplifier 22, the output of section 11 is connected to the output of amplifier 22 to provide signal voltage V O . The inverting input of section 11 is connected to the output of stage A3 to receive its output signal. The non-inverting A3 input is connected to the inverting input of amplifier 22 to receive voltage V I- . Stage A3 in amplifier 22 preferably has an inverting input connected to the non-inverting input of amplifier 22 to receive voltage V I+ . Since stage A3 is a voltage-to-current converter and section 11 is a current-to-voltage converter, amplifier 22 acts as a voltage amplifier. As depicted in Figs. 6c and 6d, amplifiers 23 and 24 each contain transconductance stages A1 and A2 and compensating capacitor C1 interconnected to form a frequency-compensated composite amplifier section 12 which amplifies an input signal voltage to produce an output signal voltage. Composite section 12 functions (at least) as an inverting amplifier having an inverting input and an output. If amplifier 23 has a non-inverting input, it is connected to a non-inverting input of section 12. In amplifier 24, section 12 may have a non-inverting input which receives voltage V B2 . The inverting input of section 12 is connected to the non-inverting input of stage A2 whose output is connected to the inverting input of stage A1. Its output is connected to the output of amplifier 12. Stage A1 may have a non-inverting input for receiving voltage V B1 . Capacitor C1 is connected between the output and inverting input of stage A1 to frequency compensate amplifier 12. Since the combination A1 and C1 is thereby a current-to-voltage converter, section 12 is a voltage amplifier. As in amplifiers 21 and 22, the remaining elements in amplifiers 23 and 24 are capacitor C2 and transconductance stage A3. Capacitor C2 is connected between the output and inverting input of section 12 to provide frequency compensation for amplifier 23 or 24. This connection causes the combination 12 and C2 to operate as a current-to-voltage converter across the frequency range in which capacitor C2 dominates the transfer function . Stage A3 is interconnected with section 12 in amplifiers 23 and 24 the same as stage A3 is respectively interconnected with section 11 in amplifiers 21 and 22. Amplifier 23 thus acts as a current amplifier, while amplifier 24 acts as a voltage amplifier. Figs. 7a - 7d show respective bipolar embodiments of amplifiers 21 - 24. The main part of stage A1 is an NPN transistor QX1. Its base and collector are respectively connected to the inverting input and output of stage A1. Transistor QX1 is emitter coupled to an NPN transistor QY1 whose base is connected to the non-inverting A1 input. Transistors QX1 and QY1 operate as a conventional differential amplifier in combination with elements RX1, RY1, I E1 and I CX1 . Stage A2 centers on emitter-coupled NPN transistors QX2 and QY2. Their bases are respectively connected to the inverting and non-inverting inputs of stage A2 whose output comes from the QX2 collector. Transistors QX2 and QY2 operate as a conventional differential amplifier in conjunction with elements RX2, RY2, I E2 and I CX2 . Similarly, stage A3 centers on emitter-coupled NPN transistors QX3 and QY3. Their bases are respectively connected to the inverting and non-inverting inputs of stage A3 whose output comes from the QX3 collector. Transistors QX3 and QY3 operate as a conventional differential amplifier in conjunction with elements RX3, RY3, I E3 and I CX3 . Three dominant poles largely determine the frequency response of each of amplifiers 21 - 24. The asymptotic gains as a function of frequency for amplifiers 21 - 24 are respectively illustrated in Figs. 8a - 8d. The upper curves I in Figs. 8a - 8d respectively represent how the gain µ for the corresponding one of amplifiers 21 - 24 would asymptotically vary if neither capacitor C1 nor C2 were present. The middle curves II indicate how µ would vary if capacitor C1 were present but not capacitor C2. The lower curves III show the actual compensated asymptotic gain variations. The following convention is used in Figs. 8a - 8d and the accompanying analysis of pole splitting. The pole frequencies associated with parasitic capacitances CPI, CPO, CPA, CPB, CPC, and CPD are respectively indicated as f I , f O , f A , f B , f C and f D . They would be at respective starting frequencies f IS , f OS , f AS , f BS , f CS and f DS if capacitors C1 and C2 were absent and are at respective final frequencies f IF , f OF , f AF , f BF , f CF and f DF . As appropriate, poles f I , f D , f A and f O would be at intermediate frequencies f IM , f DM , f AM and f OM with capacitor C1 inserted to compensate composite section 11 or 12 but with capacitor C2 absent. Input and output capacitances CPI and CPO are (normally) greater than internal capacitances CPA - CPD. Accordingly, each starting frequency f IS or f OS is (presumed to be) less than each of starting frequencies f AS - f DS . In the equations below, C1 and C2 are the respective values of capacitors C1 and C2. C PI , C PO , C PA , C PB , C PC and C PD are the respective values of capacitances CPI, CPO and CPA - CPD. G M1 , G M2 and G M3 are the respective transconductances of stages A1 - A3. The unity-gain frequency f U for each of amplifiers 21 - 24 is approximately: f U = G M3 /2πC 2 This unity-gain frequency applies to all the lower curves in Figs. 8a - 8d. The overall amplification system for each of amplifiers 21 - 24 is characterized by bandwidth-limiting frequency f L which occurs beyond f U . The gain drops 6dB/oct. in passing the first dominant pole and then 6dB/ oct. more as each further pole including f L is passed. The final frequencies to which the dominant poles are moved for amplifiers 21 - 24 normally cannot exceed f L . If any final pole frequency calculated from the below equations exceeds f L , that final frequency is assumed to equal f L . The dominant poles for amplfier 21 depend on the parasitic capacitances CPI at the amplifier input, CPB at the A1 output, and CPC at the output of section 11. For the purpose of illustration, f BS is presumed to be less than f CS . The reverse could equally be well true. As indicated in Fig. 8a, f IS , f BS and f CS all occur where µ exceeds 1. If capacitors C1 and C2 were both absent, µ would fall more than 9dB/oct. after passing f BS but before reaching 1. The combination A1 - A3 without capacitors C1 and C2 would not meet the gain roll-off stability criterion. Insertion of capacitor C1 splits poles f I and f B further apart to enable section 11 of amplifier 21 to satisfy the stability criterion. Lowest pole f I moves down to f IM . Higher pole f B moves up to f BF beyond the point at which f U occurs in fully compensated amplifier 21. Section 11 would then be stable if used with negative feedback connecting the output of section 11 directly to its inverting input. With capacitor C1 present, insertion of capacitor C2 similarly splits poles f I and f C further apart in amplifier 21. Lowest pole f I moves further down to f IF . Highest pole f C moves up beyond f U to f CF . The gain does not fall off more than 9dB/oct. before reaching f U . Subject to the condition that f U < f CF ≤ f BF , amplifier 21 satisfies the gain roll-off stability criterion and would be unconditionally stable when used with negative feedback having a gain of 1 (or less). The C 1 and C 2 values needed to achieve the foregoing compensation in amplifier 21 can be approximately calculated from the following equations: f BF = G M1 /2πC PI (1+C PB /C 1 ) f CF = G M2 /2πC 1 (1+C PC /C 2 ) The foregoing equations hold whether f BS is less than f CS or not. The situation is similar but somewhat more complex for amplifier 22. Its dominant poles depend on the parasitic capacitances CPO at the amplifier output, CPB at the A1 output, and CPD at the input of section 11. For the purpose of illustration, f DS is presumed to be less than f BS , although the opposite could as well be true. Without capacitors C1 and C2, the combination A1 - A3 would again not meet the stability criterion as shown in Fig. 8b. Insertion of capacitor C1 splits poles f D and f B to enable section 11 of amplifier 22 to meet the stability criterion. Pole f D moves down to f DM lower than f OS -- i.e., f D crosses f O . The lowest pole is now f D . Highest pole f B moves up to f BF beyond the frequency for f U in fully compensated amplifier 22. Insertion of capacitor C2 similarly splits poles f D and f O . Lowest pole f D moves further down to f DF . Higher pole f O moves up beyond f U to f OF . Amplifier 22 meets the stability criterion subject to the condition that f U < f OF ≤ f BF . The C 1 and C 2 values for amplifier 22 can be approximately calculated from the following equations: f BF = G M1 /2πC PD (1+C PB /C 1 +C PB /C PD ) f OF = G M2 /2πC 1 (1+C PO /C 2 ) If f BS were less than f DS , one of poles f B and f D would move down to the position shown for f DF while the other would move up to the position indicated for f BF . The first of the two preceding equations still gives the value for the highest pole. The situations for amplifiers 23 and 24 are largely self-explanatory using the symbol convention given above for Figs. 8a - 8d. Amplifier 23 has dominant poles dependent on the parasitic capacitances CPI at the amplifier input, CPA at the A1 input, and CPC at the output of composite section 12. Amplifier 24 has dominant poles dependent on the parasitic capacitances CPO at the amplifier output, CPA at the A1 input, and CPD at the input of section 12. Without capacitors C1 and C2, the combination A1 - A3 would not meet the gain roll-off stability criterion as indicated in Figs. 8c and 8d. The compensation in amplifier 23 and its section 12 is basically the same as the compensation in amplifier 22 and its section 11. The compensation in amplifier 24 and its section 12 is basically the same as the compensation in amplifier 21 and its section 11. The stability condition for amplifier 23 is that f U < f IF ≤ f CF presuming, for example, that f AS is less than f CS . The following equations give approximate C 1 and C 2 values for amplifier 23: f CF = G M1 /2πC PC (1+C PA /C 1 +C PA /C PC ) f IF = G M2 /2πC 1 (1+C PI /C 2 ) If f CS were less than f AS , one of poles f A and f C would move down to the indicated position for f AF while the other would move up to the position shown for f CF . The first of the two preceding equations still gives the value for the highest pole. The stability condition for amplifier 24 is that f U < f DF ≤ f AF . The following equations likewise give approximate C 1 and C 2 values for amplifier 24: f AF = G M1 /2πC PO (1+C PA /C 1 ) f DF = G M2 /2πC 1 (1+C PD /C 2 ) These equations are valid if f AS is less than f DS or vice versa. The dominant pole frequencies for the types of amplifiers shown in Figs. 7a - 7d are not materially affected if voltage followers are placed at the stage inputs. Likewise, the dominant poles for these types of amplifiers do not significantly change if current followers are at the stage outputs. Fig. 9 shows a basic embodiment of amplifier 22 of Fig. 7b in which voltage and current followers are at the stage inputs and outputs. Each voltage follower is indicated by a symbol consisting of "VF" followerd by the last two letters of the symbol for the transistor whose base is connected to that voltage follower. Each current follower is similarly indicated by a symbol consisting of "CF" followerd by the last two letters of the symbol for the transistor whose collector is connected to that current follower. In addition to its regular or "non-inverting" output, each of stages A1 - A3 may also have an "inverting" output which provides a signal inverse to the output signal at the non-inverting output. This situation is shown in Fig. 9 where the signals from the non-inverting and inverting outputs are respectively differentiated by "+" and "-" signs. As illustrated in Fig. 9, collector current sources must also be provided for any of transistors QY1 - QY3 from which an inverting output signal is made available. Finally, Fig. 9 illustrates typical configurations for the emitter and collector current sources. Fig. 10a and 10b, which are largely self-explanatory, respectively depict typical current and voltage followers CFX and VFX suitable for the present bipolar amplifiers such as that of Fig. 9. Current follower CFX has input and output terminals which carry currents I IX and I OX and which are connected to the amplifier by way of the collector of the associated "QX" transistor and its collector current source. Voltage follower VFX has input and output terminals which are at voltages V IX and V OX and which are connected to the amplifier by way of the stage input and the base of the associated "QX" transistor. In the present amplifiers, the "leading" stage of a chain of amplifier stages is the stage that receives the input signal to the chain. The stage that supplies the output signal of the chain is its "trailing" stage. Each stage between the leading and trailing stages is an intermediate or "middle" stage. If the leading stage in any of amplifiers 21 - 24 has an inverting output and if the middle stage has both inverting and non-inverting inputs, the inverting output may be connected to the input of the middle stage not connected to the non-inverting output of the leading stage. The same thing may be done with the middle and trailing stages. This improves the balancing to increase the common-mode rejection ratio. Fig. 11 shows an embodiment of Fig. 7d in which the leading and middle stages are further connected to the middle and trailing stages in this way. In particular, the collector of transistor QY3 in leading stage A3 is connected to the base of transistor QX2 in middle stage A2. The collector of transistor QY2 in middle stage A2 is connected to the base of transistor QY1 in trailing stage A1. These connections introduce three other symmetrical poles, one dependent on the parasitic capacitance CPO' at the amplifier inverting output, another dependent on the parasitic capacitance CPA' at the non-inverting A1 input, and the third dependent on the parasitic capacitance CPD' at the non-inverting input to section 12 of amplifier 24. Accordingly, a further capacitor C1' is connected between the non-inverting input and inverting output of stage A1 to frequency compensate section 12 in the manner described above for capacitor C1. Likewise, a further capacitor C2' is connected between the non-inverting input and inverting output of section 12 to frequency compensate amplifier 24 in the way described above for capacitor C2. Additionally, the emitter current sources normally must operate at specified voltages which can be achieved by interconnecting the current sources as indicated in Fig. 11. The foregoing considerations also apply to the other amplifiers of the invention. Fig. 12 illustrates a preferred bipolar embodiment of amplifier 24. Stage A3 here provides non-inverting and inverting output Signals V 03+ and V 03- from folded current followers connected to the QX3 and QY3 collectors. These current followers consist of PNP transistors QFX and QFY which are collector coupled to current-source NPN transistors QSX and QSY. Signals V 03- and V 03+ are supplied to stage A2 at its inverting and non-inverting inputs which are coupled through voltage followers VFX2 and VFY2 (where stage A2 divides into a pair of substages) to its amplifying transistor pair QX2J and QY2J and its amplifying transistor pair QX2K and QY2K. Stage A2 provides a pair of non-inverting output signals V 02J and V 02K from the QX2J and QX2K collectors. Stage A1 here consists of a pair of parallel substages A1J and A1K, each having an inverting input. In substage A1J, its inverting input receives signal V 02J and is coupled through a voltage follower VFX1J to a PNP transistor QX1J. In substage A1K, its inverting input receives signal V 02K and is coupled through a voltage follower VFX1K to an NPN transistor QX1K. The QX1J and QX1K collectors, which provide the A1J and A1K output signals, are connected together to generate voltage V O . Aside from the dominant poles which depend on capacitances CPO and CPD and which are split by capacitor C2, amplifier 24 in Fig. 12 has a pair of dominant poles dependent on the parasitic capacitances CPAJ and CPAK at the inverting A1J and A1K inputs. Capacitors C1J and C1K are connected between the amplifier output and the respective A1J and A1K inputs to split the pole associated with capacitance CPO from the poles associated with capacitances CPAJ and CPAK. This provides frequency compensation for stages A1 and A2 in the manner described above. A capacitor C2" is connected between the V EE supply and the A2 inverting input to make it a virtual ground at high frequency. In Fig. 12, supply voltages V EE and V CC respectively are greater than 0.9 volt and less than -0.9 volt. Resistors R1X/R1Y, RCX3/RCY3, RSX/RSY, RX2J/RY2J, and RX2K/RY2K respectively are 3,000, 50,000, 50,000, 5,000 and 5,000 ohms. Current sources I E3 , I E2 and I CX2J /I CX2K respectively are 2, 20, and 5 microamperes. Capacitors C1J and C1K are each 3 picofarads. Capacitors C2 and C2" are each 10 picofarads. Capacitances CPO, CPAJ/CPAK, and CPD are respectively about 200, 3 and 3 picofarads. Gain µ is about 110dB at low frequency, while f U is about 1 megahertz. The frequency-compensation techniques used in amplifiers 21 - 24 may be extended to amplifiers having more than three stages to achieve higher gain. Each further stage adds another dominant pole which is suitably moved according to the present capacitive technique to provide frequency compensation. Fig. 13 illustrates a four-stage amplifier 34 consisting of three-stage amplifier 22, a transconductance amplifier stage A4, and a compensating capacitor C3. Stage A4 operates the same as stage A3 and is connected to internal amplifier 22 in the same way as stage A2 is connected to section 11. Likewise, capacitor C3 is connected between the inverting input and the output of internal amplifier 22 to provide frequency compensation for the dominant pole dependent on the parasitic capacitance CPG at the inverting input of amplifier 22 in the same manner as capacitor C2 frequency compensates amplifier 22. The present amplifiers may be partly or wholly embodied in technology other than bipolar. FET's of both the insulated-gate and junction types may be used. Each transistor then has a first flow electrode, a second flow electrode, and a control electrode which regulates current transmission between the flow electrodes. For a bipolar transistor, its base, emitter, and collector respectively are the first, second, and control electrodes. These electrodes are-respectively the gate, source, and drain for an FET. For example, Fig. 14 depicts an FET embodiment of Fig. 6b analogous to Fig. 7b. Each pair of emitter-coupled bipolar transistors in Fig. 7b is replaced with a corresponding pair of source-coupled insulated-gate FET's in Fig. 14 as indicated by the use of the prime notation in Fig. 14. Methods for manufacturing the various elements of the present amplifier are well known in the semiconductor art. Each amplifier is preferably fabricated as part of a monolithic integrated circuit using PN-junction isolation to separate active regions in a semiconductor wafer. While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, semiconductor elements of opposite polarity to those described above may be employed to accomplish the same results. If the characteristics of the negative feedback network to be used with one of the present amplifiers are known before that amplifier is designed, the values of its compensating capacitors may be suitably adjusted to satisfy the stability rule for loop gain without necessarily meeting the open-loop gain roll-off stability criterion.

Claims: An amplifier (21, 22, 23, 24) for amplifying an input signal (V I- , V I+) received at least partially at an inverting input (-) thereof to produce an inverted output (V 0 ) at an output thereof, the amplifier comprising: a composite amplifier section (11, 12) comprising: a first stage (A1) for amplifying an input signal received at least partially at an inverting input (-) thereof to produce an output signal at an output thereof, a first capacitor (C1) coupled between the output and the inverting input (-) of the first stage (A1), and a transconductance second stage (A2) for amplifying an input signal received at least partially at a non-inverting input (+) thereof to produce an output signal at an output thereof, the output of one of the first (A1) and second (A2) stages coupled to the input of the other of the first (A1) and second (A2) stages, the remaining input of the first (A1) and second (A2) stages coupled to an inverting input (-) of the composite section (11, 12), and the remaining output of the first (A1) and second (A2) stages coupled to an output of the composite section, a second capacitor (C2) coupled between the output and the inverting input of the composite section (11, 12), and a transconductance third stage (A3) for amplifying an input signal received at least partially at a non-inverting input (+) thereof to produce an output signal at an output thereof, the output of one of the composite section (11, 12) and the third stage (A3) is coupled to the input of the other of the composite section (11, 12) and the third stage (A3), the remaining input of the composite section (11, 12) and the third stage (A3) coupled to the input of the amplifier (21, 22, 23, 24), and the remaining output of the composite section (11, 12) and the third stage (A3) coupled to the output of the amplifier (21, 22, 23, 24), characterized in that: each of the first (A1), second (A2) and third (A3) stages has only one pole per signal path within the unity-gain frequency range that the cascaded stages (A1, A2, A3) would have in the absence of the first and second capacitors (C1, C2), the value of the first capacitor (C1) is selected to make the forward gain of the composite section (11, 12) roll off no more than 9 dB/octave out to its unity-gain frequency, and the value of the second capacitor (C2) is selected to make the forward gain of the amplifier (21, 22, 23, 24) roll off no more than 9 dB/octave out to its unity-gain frequency. An amplifier as claimed in Claim 1, characterized in that the output of the first stage (A1) is coupled to the non-inverting input (+) of the second stage (A2) whose output is coupled to the non-inverting input (+) of the third stage (A3). An amplifier as claimed in Claim 1, characterized in that the output of the third stage (A3) is coupled to the inverting input (-) of the first stage (A1) whose output is coupled to the non-inverting input (+) of the second stage (A2). An amplifier as claimed in Claim 1, characterized in that the output of the second stage (A2) is coupled to the inverting input (-) of the first stage (A1) whose output is coupled to the non-inverting input (+) of the third stage (A3). An amplifier as claimed in Claim 1, characterized in that the output of the third stage (A3) is coupled to the non-inverting input (+) of the second stage (A2) whose output is coupled to the inverting input (-) of the first stage (A1). An amplifier as claimed in any of the Claims 1 to 5, characterized in that the first stage is a transconductance stage. An amplifier as claimed in any of the Claims 1 to 6, characterized in that the amplifier is coupled between a first voltage supply (V EE ) and a second voltage supply (V CC ); each of the second (A2) and third (A3) stages has an inverting input (-); and each of the second (A2) and third (A3) stages comprises first (QX2,QX3) and second (QY2,QY3) like-polarity transistors each having a first flow electrode, a second flow electrode, and a control electrode for regulating current transmission between the flow electrodes, the first electrodes coupled together and to the first supply (V EE ), the control electrodes of the first (QX2,QX3) and second (QY2,QY3) transistors respectively coupled to the inverting (-) and non-inverting (+) inputs of that stage, the second electrode of the first transistor (QX2,QX3) coupled to the output of that stage, and the second electrode of the second (QY2,QY3) transistor coupled to the second supply (V CC ). An amplifier as claimed in Claim 7, characterized in that the first stage (A1) comprises: a first transistor (QX1) having a first flow electrode coupled to the first supply (V EE ), a second flow electrode coupled to the output of the first stage (A1), and a control electrode which regulates current transmission between the flow electrodes of the first transistor (QX1) in the first stage (A1) and is coupled to its inverting input (-). An amplifier as claimed in Claim 8, characterized in that the first stage (A1) includes: a second transistor (QY1) having a first flow electrode, a second flow electrode coupled to the second supply (V CC ), and a control electrode which regulates current transmission between the flow electrodes of the second transistor (QY1) in the first stage (A1) and is coupled to a non-inverting input (+) thereof, the transistors (QX1,QY1) in the first stage (A1) being of like polarity and having their first electrodes coupled together. An amplifier as claimed in Claim 1, characterized in that: each stage has a further input thereof which is a non-inverting input (+) for the first stage (A1) and which is an inverting input (-) for each of the second (A2) and third (A3) stages; each stage also amplifies its input signal to produce at a further output thereof a signal inverse to its output signal; the further output of the leading one of the stages is coupled to the further input of the middle one of the stages whose further output is coupled to the further input of the trailing one of the stages; a further first capacitor (C1') in the composite section (12) is coupled between the further output and further input of the first stage (A1); and a further second capacitor (C2') is coupled between the further input of the leading one of the first (A1) and second (A2) stages and the further output of the trailing one of the first (A1) and second (A2) stages. An amplifier as claimed in Claim 10, characterized in that the value of the further first capacitor (C1') is selected to make the forward gain of the composite section (12) roll off no more than 9dB/octave out to its unity-gain frequency; and the value of the further second capacitor (C2') is selected to make the forward gain of the amplifier roll off no more than 9dB/octave out to its unity-gain frequency. An amplifier as claimed in Claim 1, characterized in that the first stage (A1) comprises first and (A1J) second (A1K) substages for amplifying respective input signals received at least partially at respective separate inverting inputs (-) thereof to produce respective output signals at respective outputs thereof coupled to the output of the first stage, the first substage (A1J) and the first stage (A1) having their inputs coupled together; and the composite section includes an additional first capacitor (C1K) coupled between the inverting input (-) of the second substage (A1K) and the output of the first stage which is the trailing one of the first and second stages. An amplifier as claimed in Claim 12, characterized in that the value of the additional first (C1K) capacitor is selected to make the forward gain of the composite section roll off no more than 9dB/octave out to its unity-gain frequency. An amplifier as claimed in Claim 13, characterized in that each substage comprises a transistor (QX1J,QX1K) having a first flow electrode, a second flow electrode, and a control electrode for regulating current transmission between the flow electrodes, the transistors being of opposite polarity, each transistor having its control and second electrodes respectively coupled to the input and output of its substage. An amplifier as claimed in Claim 14, characterized in that the second stage (A2) also amplifies its input signal to produce an additional output signal (V O2K ) at an additional output coupled to the input of the second substage. An amplifier as claimed in Claim 8, characterized in that each transistor is a bipolar transistor having a base, an emitter, and a collector which are respectively the control, first, and second electrodes of that transistor. An amplifier as claimed in Claim 8, characterized in that each transistor is a field-effect transistor having a gate, a source, and a drain which are respectively the control, first, and second electrodes of that transistor.

Inventors: HUIJSING JOHAN HENDRIK, HUIJSING, JOHAN HENDRIK
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1985
Main classification: H03F1
IPC codes: H03F3, H03F1