A MICROPROCESSOR DEVICE WITH VARIABLE MEMORY CAPACITY

Abstract: A microprocessor having a bus cycle changeover circuit (10) between a command execution unit (1) and an address output logic (2), a data input/output logic (3), and a bus controller (4). The bus cycle changeover circuit (10) controls timing and address in order to transmit/receive data to/from a part of a data bus according to a data width selection signal and a data width selection instruction. In order to control timing and address, the cycle changeover circuit (10) comprises a cycle control circuit (11) which outputs a signal expressing a latter half access cycle and an upper/lower selection circuit (12) which selects upper/lower part of the data bus.

Description: This invention relates to a microprocessor comprising a command execution unit for executing various commands; address output logic for supplying memory addresses to be accessed to an address bus; data input/output logic for exchanging instructions and data between said command execution unit and a data bus; a bus controller for supplying control signals from said command execution unit to a control bus; and a means for changing the data bus width. Fig. 1 shows the interface part in a known microprocessor, which interfaces with buses including the data bus. The interface part comprises address output logic 2 which receives an address signal from a command execution unit 1 and outputs the address signal to one of the address buses, a data input/output logic 3 which exchanges data between the command execution unit 1 and the data bus, and a bus controller 4 which receives the memory access instruction and data width command for the memory from the command execution unit 1 and transmits them to the bus. In such a type of interface part, the bit width of the data bus is fixed and there is no provision for changing the bit width of the data bus. As a result, the memory may have excessive capacity, beyond that required for a given practical application. For example, as shown in Fig. 2, in order to form a memory which is connected to a 16 bit wide data bus using 64 kbit RAM chips, the memory capacity will be: 64 kbits x 16 = 1024 kbits =128 kbytes. Similarly, in the case of 32 bit wide microprocessor, to form the memory using 1 bit wide 256 kbit RAM chips, the memory capacity will be: 256 kbits x 32 = 8192 kbits = 1024 kbytes = 1 Mbyte. However, such a large capacity of the memory is not needed for a usual microcomputer system. That is, for the system using a microprocessor, it is sufficient to select the memory capacity adapted to the practical use. For example, there is a case where 64 kbyte memory is sufficient for 16 bit wide microprocessor. In this example, as described above, since the memory capacity formed by using 64 kbit RAMs is 128 kbytes, 64 kbyte memory capacity is not used and is excessive. As a result, there is a difficulty in decreasing the cost of the system. Therefore it is advantageous to provide a microprocessor which can change the data bus width automatically. A microprocessor known from FR-A-2 500 187 can change the data bus width, but is unable to address the same block of memory using different bus widths. This limits the utility and flexibility of the system. It is an object of the present invention to provide a microprocessor which can address a given block of memory using any of a plurality of bus widths. According to the invention, the microprocessor initially defined is characterized in that said changing means comprises a bus cycle changeover circuit connected between said command execution unit and each of said address output logic, said data input/output logic and said bus controller, and said bus cycle changeover circuit comprises: a cycle control circuit; and upper/lower selection circuit; a data bus changeover circuit; an address adder circuit; and an address shift circuit; said cycle control circuit having as inputs a signal for indicating when a memory access is required by the command execution unit (MACA), a signal for indicating the width of the access required by the command execution unit (DTWDA), a signal for indicating whether a narrow data bus is selected (DTWDS), and a signal for indicating when a memory access bus cycle has been successfully completed (MACC), and being arranged to generate as outputs signals for the bus controller indicating when a memory access is required (MACB) and the width of that access (DTWDB), as well as a "latter half access" signal (T2) indicating when a second bus access is required to satisfy the data width requirement of the command exectution unit, a narrow data bus having been selected, said latter half access signal (T2) being used as an input to said upper/lower selection circuit and to said address adder, said upper/lower selection circuit having as inputs said signal for indicating when a memory access is required by the command execution unit (MACA), said successful memory access completion signal (MACC) and said latter half access signal (T2) and being arranged to generate in response to the presence of these signals, a further signal for input to said data bus changeover circuit and to cause thereby data to be transferred between the upper half of the command execution unit data lines and the lower half of the data bus lines, and said address adder circuit having as inputs the address generated by the command execution unit, and said latter half access signal (T2), in whose presence the generated output address is incremented, said output address being supplied to said shift circuit, which also has as input said signal for indicating the selection of a narrow data bus (DTWDS) and in the presence of said signal causing the address output from said shift circuit and supplied to said address output logic to be shifted upwards. In the accompanying drawings: Fig. 1 illustrates the interface part of a microprocessor according to the prior art; Fig. 2 illustrates formation of a memory using 64 kbit RAM connected to a data bus; Fig. 3 is a block diagram of a microprocessor which illustrates the concept of the invention; Fig. 4 is a block diagram illustrating detailed structure of a bus cycle changeover circuit according to one embodiment of the invention; Fig. 5 is a circuit diagram of a cycle control circuit; Fig. 6 is a circuit diagram of an upper/lower selection circuit; Fig. 7 is a circuit diagram of a data bus changeover circuit; Fig. 8 is a circuit diagram of an address shift circuit; Fig. 9 is a circuit diagram of an address adder circuit; Fig. 10 is a timing chart of the operation of the bus changeover circuit when a 16 bit wide data bus is selected; Fig. 11 is a timing chart of the operation of the bus changeover circuit when an 8 bit wide data bus is selected; Fig. 12 is a block diagram which illustrates the system having two memory banks and the microprocessor according to an embodiment the invention; and Fig. 13 is a flow chart illustrating the procedure of data bus width determination when memory boards are mounted. Fig. 3 shows a block diagram of an embodiment of the present invention comprising a bus cycle changeover circuit 10 between a command execution unit 1 and an address output logic 2, a data input/output logic 3 and a bus controller 4. Since the functions of the address output logic 2, the data input/output logic 3 and the bus controller 4 are the same as described before, the detailed descriptions will be omitted. Address, data, memory access instructions and data width instructions which are transmitted from the command execution unit 1, are expressed with letter "A". On the other hand, address, data, memory access instructions and data width instructions which are output from the command execution unit 1 to the address output logic 2, the data input/output logic 3 and the bus controller 4 respectively, are expressed with letter "B". Data A and B are expressed as bidirectional data because they are transmitted and received (exchanged) between the command execution unit and the data bus. Fig. 4 shows the detailed structure of the bus changeover circuit 10. This bus changeover circuit comprises a cycle control circuit 11, an upper/lower selection circuit 12, an upper selection circuit 13, a lower selection circuit 14, a switching circuit 15, an address shift circuit 16, and an adder 17. The Memory ACcess instruction A (MACA), data width selection signal (DTWDS), DaTa WiDth instruction A (DTWDA) and Memory ACcess Completion signal (MACC) are input to the cycle control circuit 11. This circuit outputs Memory ACcess instruction B (MACB), DaTa WiDth instruction B (DTWDB) (data width selection control signal) and signal T₂ which denotes the latter half cycle for using a part of the bus. The T₂ signal is input to the address adder 17 and the upper/lower selection circuit 12, respectively. In the address adder 17, the address A is incremented by 1 upon every generation of T₂ signal and the added output address is shifted by the address shift circuit 16 which shifts the address input according to the data width selection signal (DTWDS) and finally outputs as address B. Data A is output as Data B via the data bus changeover circuit which comprises an upper selection circuit 13, lower selection circuit 14 and switching circuit 15, each circuit being operated by the output signal of the upper/lower selection circuit and the data A is finally output as Data B. Each circuit is now described in detail. In the following description, a 16-bit microprocessor uses the data bus changing between 16 bit width and 8 bit width. Fig. 5 is a circuit diagram of the cycle control circuit 11 which is designed as an asynchronous type. The DTWDA instruction which is "H" for 16 bit wide, the DTWDS signal which is "H" for 8 bit wide and MACC signal are input to the AND gate 101. Its output terminal is connected to an input terminal of a flip-flop (FF) circuit which is composed of two NOR circuits 102 and 103. The output of the FF is transferred as T₂ signal via two inverters 104 and 105. The T₂ signal is input to a NAND gate 108 directly and via a delay circuit 106 and inverter 107. The output of the NAND gate 108 and the MACA signal via inverter 110 are input to a NAND gate 109. Therefore when 8 bit wide data bus is selected, MACB signal is output from the NAND gate 109 upon generation of MACC signal. The FF is reset by the MACA signal or ANDed MACC signal and T₂ signal by an AND gate 111. The DaTa WiDth B (DTWDB) instruction is obtained by passing the DTWDS instruction and inverted to DTWDA by inverter 112 through an OR gate 113. Fig. 6 illustrates the detailed structure of the upper/lower selection circuit 12, which comprises 5 AND gates 121 to 125 and inverter 126. Since the data bus is bidirectional and Memory WriTe (MWT) signals and Memory ReaD (MRD) signals are utilized, MWT signals are input to AND gates 121 and 122 and MRD signals are input to AND gates 123 and 124. The T₂ signal which is generated when 8 bit width is selected, is input to the AND gates 122 and 124, the inverted T₂ signal which is inverted by the inverter 126 is input to AND gates 121 and 123, and the T₂ signal and MACC signal are input to AND gate 125. Consequently, 16 bit write (WT16) signal, 8 bit write (WT8) signal, 16 bit read (RD16) signal, 8 bit read (RD8) signal, and 8 bit read latch (RD8LCH) signal are output from the AND gates 121 to 125, respectively. Fig. 7 shows the detailed structure of the data bus changeover circuit which comprises the upper selection circuit 13, the lower selection circuit 14 and a switching circuit 15. The upper half of the data bus A (D n+8 A) and the upper half of the data bus B (D n+8 B) are connected via back-to-back connected three state gates 131 and 132 which are enabled by WT6 and RD16, respectively. Similarly, the lower half of the data bus A (D n A) and the lower half of the data bus B (D n B) are connected via back-to-back connected three state gates 135 and 136. In order to use the Data bus B as 8 bit wide, the upper half of the data bus A (D n+8 A) and the lower half of the data bus B (D n B) are connected via back-to-back connected three state gates 133 and 134 which are enabled by WT8 and RD8, respectively. Furthermore, there is provided a latch 137, which latches the read data by RD8LCH during 8 bit wide read cycle and a three state gate 138 which is enabled by RD8. Fig. 8 shows the detailed structure of the address shift circuit 16 which comprises a group of three state gates 141-0, 141-1, 141-2, ... which output addresses AD₀, AD₁, AD₂, .... of address B without any modification and which are enabled by DTWDS signal inverted by a inverter 140, and the other group of three state gates 142-0, 142-1, 142-2, .... The gate 142-0 outputs "0" to AD₀ when enabled by DTWDS signal and the gates 142-1, 142-2, ..... connect address lines of address C to +1 shifted address lines of address B. For example, gate 142-1 connects address line AD₀ of address C to address line AD₁ of address B. Fig. 9 shows the detailed structure for one bit of an address adder 17 which comprises a NAND gate 156 to which address A bit 0 and basic address bit 0 are input and which forms carry singal, an exclusive NOR gate 152 to which address A bit 0 and basic address bit 0 are input, an exclusive OR gate 153 to which T₂ signal inverted by an inverter 151 and the output signal of the EX-OR 152 are input. Also included is a three state gate 155 which controls the output of the inverter 151 according to the output of the EX-NOR gate 152 inverted by an inverter 154. The EX-OR gate outputs address C bit 0 and the gate 155 intercepts the transmission of carry signal when the address A bit 0 and basic address bit 0 coincide. The operation of the above-mentioned bus cycle changeover circuit 10 will now be described hereinbelow. First, when the ordinary 16 bit width is selected as the data width selection signal, Address A, Data A, Memory ACcess instruction A (MACA) and DaTa WiDth instruction A (DTWDA) are input to the bus cycle changeover circuit 10 and output to the system bus in the form of Address B, Data B, MACB and DTWDB without involving any change. A part of the operation is shown in the timing chart in Fig. 10. According to the chart, MACB is generated upon the generation of MACA and after a certain time T₁, MACC signal is generated and then the bus access cycle is finished. In this case, T₂ cycle will never be executed. Next, when, for example, 8 bit width is selected as the data width, it is required to output two memory access instructions B for one memory access instruction A. That is, the memory access instruction A is converted to the memory access instruction B which is output every time when intervals T₁ and T₂ are completed. The memory access instruction A is also input to the upper/lower selection circuit, and its output controls the data transmission. In the first half time interval T₁, since the lower selection circuit operates and the switching circuit 15 is switched to the lower side, the lower half of the data A is output as data B on the lower half of the data bus B. In the second half time interval T₂, the switching circuit 15 connects the upper half of the data A to the lower half of the data bus B. The memory address where data are stored must be changed every access cycle when the bus width is narrowed. For this purpose, in the time interval T2, basic address in time interval T₁ is added by one every time T₁ cycle is completed by address adder 17, and the added address is shifted to one higher bit by the shift circuit 16 which is enabled while the DTWDS signal is high. Thus the address control is performed. When an access cycle is completed, the Memory ACcess Completion (MACC) signal is output from the bus controller 4, and the MACC signal is input to the cycle control circuit 11 and the upper/lower selection circuit to execute transition operation to the next operation. Thus, the 16 bit wide data bus functions as 8 bit wide data bus. These operation are illustrated in the timing chart as shown in Fig. 11. It shows that DTWDS signal generates MACC signal after T₁ and consequently T₂ signals are generated and that the bus access cycle will be transferred to the latter half cycle. After time interval T₂, the MACC signal is generated and T₂ signal is transferred to "0". Accordingly, two MACB signals are output by an MACA signal. Fig. 12 illustrates the connection of two memory banks 23 and 24 to the microprocessor 20 according to the invention with address bus 21 and data bus 22. Each memory bank is composed of 64 kbit RAMS which are stacked for 8 bit width. That is, 8 bit wide D₀ to D₇ bus and 8 bit wide D₈ to D₁₅ bus are connected to 16 bits wide bus D₀ to D₁₅. The address bus 21 and A₀ are composed of 24 bit wide A₀ to A₂₃ bus lines. When data transmission is executed using 16 bit wide bus, data of odd number addresses are stored in the memory bank (1) 23, and data of even number addresses are stored in the memory bank (2) 24. According to the invention in which data bus width is narrowed to 8 bit wide, addresses in the memory bank must be in sequence. In the above embodiment, the least significant bit (LSB) A₀ is used to switch the memory banks (1) and (2), however, when the data bus width is selected to 8 bit wide, the LSB is fixed and the area stored is determined by the addresses A₁ to A₂₃. In this case, either of two memory banks may be selected, usually A₀ bit is set to "0" and the specified addresses are shifted to one higher bit. By using this memory structure, data bus width can be selected automatically according to the condition of mounted memory banks. Fig. 13 is a flowchart showing the procedure of automatic data bus width selection. After the system is reset (step 201), for example, hexadecimal data "1010" is written in a predetermined address, for example, address "0" (step 202), then data is read from the address "0" (step 203) and the data which is read is checked if it is "1010" (step 204) or not. If it is identified to "1010", data bus width is determined to 16 bits wide and if other data are obtained, the data bus width is determined to be 8 bits wide. Therefore, it is possible to know the data bus width of the mounted memory boards. In the above embodiment, the data bus is switched between 16 bit width and 8 bit width. However, any switching between ordinarily used data bus widths, such as between 32 bit width and 8 bit width and between 32 bit width and 16 bit width can be used. The number of divisions can be selected as required. Thus, there is provided a microprocessor comprising a command execution unit 1 which executes various commands, an address output logic 2 which outputs memory address to be accessed to an address bus, a data input/output logic 3 which exchanges instructions and data between said command execution unit and a data bus. Also provided is a bus controller 4 which outputs control signals from said command execution unit to a control bus, and a bus cycle changeover circuit 10 which is connected between the command execution unit 1 and each of the address output logic 2, the data input/output logic 3 and the bus controller 4. The bus cycle changeover circuit 10 controls timing and address in order to transmit/receive data to/from a part of data bus according to a data width selection signal for generating the data width selection control signal. Therefore, it is possible to increase the efficiency of the memory because there is no need to utilize a large number of memory devices for the whole data bus width. Further, high speed access is possible by using the full assembled memory for the whole data bus width. Moreover, since the changeover of data bus width can be performed automatically after an additional or exchanging memory board is mounted, no manual setting is required.

Claims: A microprocessor comprising: a command execution unit (1) for executing various commands; address output logic (2) for supplying memory addresses to be accessed to an address bus; data input/output logic (3) for exchanging instructions and data between said command execution unit (1) and a data bus; a bus controller (4) for supplying control signals from said command execution unit (1) to a control bus, and means for changing the data bus width, characterized in that said changing means comprises a bus cycle changeover circuit (10) connected between said command execution unit (1) and each of said address output logic (2), said data input/output logic (3) and said bus controller (4), and said bus cycle changeover circuit (10) comprises: a cycle control circuit (11); an upper/lower selection circuit (12); a data bus changeover circuit (13,14,15); an address adder circuit (17); and an address shift circuit (16); said cycle control circuit having as inputs a signal for indicating when a memory access is required by the command execution unit (MACA), a signal for indicating the width of the access required by the command execution unit (DTWDA), a signal for indicating whether a narrow data bus is selected (DTWDS), and a signal for indicating when a memory access bus cycle has been successfully completed (MACC), and being arranged to generate as outputs signals for the bus controller (4) indicating when a memory access is required (MACB) and the width of that access (DTWDB), as well as a "latter half access" signal (T2) indicating when a second bus access is required to satisfy the data width requirement of the command exectution unit, a narrow data bus having been selected, said latter half access signal (T2) being used as an input to said upper/lower selection circuit (12) and to said address adder (17), said upper/lower selection circuit (12) having as inputs said signal for indicating when a memory access is required by the command execution unit (MACA), said successful memory access completion signal (MACC) and said latter half access signal (T2) and being arranged to generate in response to the presence of these signals, a further signal for input to said data bus changeover circuit (13,14,15) and to cause thereby data to be transferred between the upper half of the command execution unit data lines and the lower half of the data bus lines, and said address adder circuit (17) having as inputs the address generated by the command execution unit, and said latter half access signal (T2), in whose presence the generated output address is incremented, said output address being supplied to said shift circuit (16), which also has as input said signal for indicating the selection of a narrow data bus (DTWDS) and in the presence of said signal causing the address output from said shift circuit (16) and supplied to said address output logic (2) to be shifted upwards. A microprocessor as claimed in claim 1, wherein said data bus changeover circuit comprises an upper selection circuit (13) which transmits/receives the upper data to/from the upper part of the data bus without any modification, a lower selection circuit (14) which transmits/receives the lower data to/from the lower part of the data bus without any modification, and a switching circuit (15) which permits data transfer between the upper part of the bus and the lower part of the bus when the data bus is used by narrowing. A microprocessor as claimed in claim 1 or 2 wherein the data bus width is switchable between the whole width and half of the width. A microprocessor as claimed in any preceding claim, wherein said data width selection signal depends on the data width recognized by writing predetermined data into a predetermined memory address, attempting reading of the data from the predetermined memory address, and checking success of the access operation.

Inventors: MIYOSHI, AKIO
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: G06F13
IPC codes: G06F15, G06F12, G06F13