NON-VOLATILE SEMICONDUCTOR STORAGE CELL

Abstract: A non-volatile storage cell uses two different areas (28A, 28B) for electron injection, allowing direct overwriting of previously stored data without an intervening erase cycle. A floating gate FET has duel programming gates (PG1, PG2) disposed on its floating gate (22). Each programming gate (PG1, PG2) includes a layer (28A, 28B) of dual electron injector structure (DEIS) and a polysilicon electrode (30, 32). When writing a "0", one of the programming gates PG1, PG2) removes charge from the floating gate (22). When writing "1", the other programming gate injects charge into the floating gate (22). This charge transfer does not take place if the previously stored logic state and the logic state to be written in are identical.

Description: The invention relates to the field of electrically erasable programmable read only memories (EEPROMs). Non-volatile floating-gate (metal-oxide-silicon) (MOS) memories are well known in the industry. In such devices, the conductive state of a field effect transistor (FET) is determined by the voltage on a "floating gate". This voltage is set by induced avalanche injection or tunneling of electrons from a depletion region formed in a semiconductor substrate, through a gate insulation layer, to the gate electrode. Previously, this preset logic state could only be altered by first removing (or "erasing") the accumulated charge by methods such as ultraviolet light irradiation. More recently, designs have been proposed which facilitate the erasure and resetting of the voltages on these floating gates. For example, in US-A-4,119,995 the floating gate is controlled by separate programming and erasure gates which are disposed above the floating gate and insulated therefrom by an oxide layer. The floating gate voltage is programmed in the manner discussed above. The charge on the floating gate is erased by causing electrons to flow from the floating gate up to the erasing gate. Other designs have been proposed which utilize charge transfer between the floating gate and one or more control gates to both erase and program the floating gate (i.e., in these designs, the tunnelling or avalanche of electrons from a structure other than a substrate region is used to set the voltage of the floating gate). See e.g. Lee, "A New Approach for the Floating-Gate MOS Nonvolatile Memory", Applied Physics Letters, Vol. 31, No. 7, October 1977, pp. 475-476. This paper discloses a single control gate separated from the floating gate by a poly-oxide layer. When the control gate is biased positively for writing, electron flow is induced from the floating gate to the control gate. Since this flow is greater than the flow of electrons from the substrate to the floating gate, the floating gate accumulates positive charge. When the control gate is ramped negative to erase, the floating gate accumulates negative charge. See also US-A-4,099,196, US-A-4,274,012, US-A-4,300,212 and US-A-4,314,265 which disclose erasable PROM's wherein a programming gate is disposed below the floating gate and an erasure gate is disposed above the floating gate. The devices are programmed by inducing electron flow from the program gate to the control gate and are erased by inducing electron flow from the floating gate to the erasing gate. In all four patents, the surface of one or more of the gates is roughened in order to enhance the induced electric fields. This promotes electron flow through the oxide layers separating the gates. Among the materials which have been used to enhance charge injection is the so-called dual electron injector structure (DEIS), which is a layer of SiO₂ having excess silicon crystals on its upper and lower surfaces. This structure is disclosed in US-A-4,104,675. A DEIS layer is generally formed by a chemical vapor deposition process which induces extra silicon crystal growth both prior and subsequent to the formation of an otherwise normal SiO₂ layer. Several patents specifically disclose the use of a DEIS layer as the injector structure for a non-volatile ROM. See e.g., US-A-4,336,603. This patent discloses a single control gate which injects electrons into the floating gate through the DEIS layer. A structure according to the first part of claim 1, employing dual electron injection is disclosed in IBM Technical Disclosure Bulletin, Vol. 24, No. 3, August 1981, pp. 1541-1543. A control gate and a reset gate are capacitively coupled to a floating gate via a common DEiS layer, the degree of coupling being determined by the respective sizes of the gates. To prevent electron current from flowing from the floating gate to the reset gate, the latter is designed with a larger area relative to the control gate. Accordingly, because of the larger capacity, the electric field in the region between the reset gate and the floating gate remains below the level at which a flow of electron current would be induced. It is an object of the present invention to provide an improved electrically erasable programmable memory cell. It is another object of the invention to provide a memory cell in which data can be written into the cell without first erasing the existing data stored therein. It is yet another object of the invention to provide a memory cell which is of a comparatively uncomplicated design, necessitating a minimum of support circuitry. These and other objects of the invention are realized by a memory cell as set out in the claims, including a semiconductor substrate having a plurality of diffusions formed therein, a floating gate insulated from the substrate, and a pair of programming gates disposed above the floating gate. Each programming gate includes a layer of DEIS material which is overlayed by a polysilicon layer. In operation, when a first binary logic state is to be written into the cell, electrons will flow from the floating gate to one of the programming gates. When a second binary logic state is to be written into the cell, electrons will be injected by the other of the programming gates into the floating gate. Due to the characteristics of the DEIS layer, the foregoing charge transfer will not occur if the logic state to be written in is the same as the logic state currently stored by the cell. Moreover, if a logic state to be written in is the opposite of the logic state currently stored, the logic state will be written in without any additional steps (i.e., there is no need to erase the old logic state prior to writing in the new logic state). The foregoing and other objects, features and advantages of the present invention will become more apparent upon a detailed description of the best mode for carrying out the invention. In the description to follow, reference will be made to the accompanying drawings, in which: Fig. 1 is a cross-sectional view of the memory cell of the invention; Figs. 2A and 2B are diagrams illustrating the conductive characteristics of the DEIS layer; and Fig. 3 is an equivalent circuit of the memory cell of the invention. With reference to Fig. 1, the structure of the memory cell will be described. A p-type substrate 10 has n-type diffusions 12, 14, 16 and 18 formed therein via typical implantation techniques. Note that these conductivity types can be reversed. The n-type diffusions 14 and 18 are the source and drain diffusions, respectively, of an FET having a floating gate electrode. Diffusion 16 serves as an extension of source diffusion 14 beneath the floating gate, such that diffusions 16 and 18 define the channel region of the floating gate FET therebetween. A source node is defined where diffusions 14 and 16 border on one another. Diffusion 12 is a diffused bit line which receives data signals from an external data source. Substrate 10 is covered by an insulator layer 20. Any sort of insulator (e.g., SiO₂) can be used. Insulator layer 20 is then covered by a first polycrystalline silicon layer, which is etched using conventional techniques to form floating gate electrode 22 and a word line electrode 24. The word line electrode 24, in conjunction with diffusion regions 12 and 14, forms a typical word line transistor device. A layer of DEIS material 28A and 28B is then formed on floating gate 24 using the techniques previously discussed. A second layer of polycrystalline silicon is then deposited. The second polysilicon layer and the DEIS layer are etched (using conventional techniques) to form first and second program gates PG1 and PG2. Program gate PG1 includes a first region 30 of the second polysilicon layer overlaying a first region 28A of the etched DEIS layer. Program gate PG2 includes a second region 32 of the second polysilicon layer overlaying a second region 28B of the etched DEIS layer. Although the two polysilicon regions 30 and 32 appear to be of similar area in Fig. 1, in practice region 30 is much larger than region 32. This size difference effects the respective capacitances of PG1 and PG2, as will be discussed in more detail below. Prior to discussing the operation of the cell, the characteristic of the DEIS layer will now be reviewed. Due to the electron flow enhancement properties of the surfaces of the DEIS layer with respect to the inner SiO₂, each surface of the DEIS layer has an inherent diode characteristic. Since the respective surfaces of the DEIS layer promote electron flow in different directions, the total layer acts as (i.e. has the electrical characteristic of) two back-to-back connected diodes, as shown in Fig. 2A. As shown in Fig. 2B, it is preferred that the DEIS layer be formed such that these diodes begin conduction at approximately ±10 volts. Thus, while the use of DEIS material is preferred, any sort of charge injector material or structure can be used which provides the above-described characteristics. The operation of the invention will now be described with reference to Fig. 3, which is an equivalent circuit of the cell of Fig. 1. C PG1 is the capacitance formed by DEIS region 28A between polysilicon region 30 and floating gate 22; C PG2 is the capacitance formed by DEIS region 28B between polysilicon region 32 and floating gate 22; C FGN is the capacitance formed by insulator layer 20 between floating gate 22 and N+ diffusion 16; and C I is the depletion capacitance formed between the N+ type diffusion 16 and the substrate 10 when both drain diffusion 18 and source diffusion 14 are brought high. S1 represents the word line device, which switches V BL onto the substrate when V WL on the word line electrode goes to +5 volts. Likewise, S2 represents the floating gate transistor itself, which connects the drain to the substrate when either the floating gate voltage is greater than V T or the program gate voltage V PG1 is greater than V DD (=+5V). For the sake of clarity, the various parasitic capacitances inherent in the memory cell have been deleted from the equivalent circuit of Fig. 3. This equivalent circuit has been found to present an accurate first order approximation of the performance of the memory cell. In the discussion of the operation of the memory cell, the following normalized capacitances will be assumed by way of example: C PG1 ≅ 1.0 C PG2 ≅ 0.2 C FGN ≅ 1.0 C I ≅ 0.1 The capacitance of C PG1 is much greater than that of C PG2 since the polysilicon region 30 (and hence the DEIS region 28A) is much larger than region 32. The operation of the memory cell of Fig. 1 will now be described with reference to Fig. 3. In general, a logic state is written into a cell via a two step process. First, the floating gate is charged to an initial voltage by injection/ removal of electrons. Then the various control voltages are dropped to their quiescent levels, setting the final voltage on the gate. Initially, if a "0" is to be written into the cell, the bit line is grounded (V BL = 0 volts) and the word line is then raised to V DD (V WL ≅ +5 volts). This causes source diffusion 14 and N+ diffusion 16 to be grounded. In the equivalent circuit, V WL = +5V causes the word line device "switch" to be closed, such that C FGN is connected to ground potential. Since drain diffusion 18 is at V DD = +5V, a channel forms between drain diffusion 18 and n-type diffusion 16. At the same time, PG2 is grounded (V PG2 = 0 volts). After a small delay to allow channel formation, the voltage on PG1 is raised to +20 volts. This delay is determined by monitoring the word line voltage (i.e., V PG1 is raised a predetermined time after V WL = 5V). In general, the initial voltage on floating gate due to these control voltage states is given by the equation V FG = χ w V PG1 (1) where χ W is the capacitive coupling of the equivalent circuit during the initial write operation. Under these circumstances (i.e. C PG2 and C FGN connected to ground), where C FGT"0" = C PG1 + C PG2 + C FGN (3) such that the capacitive coupling is approximately 0.45 and V FG = (0.45) (20) = 9.0 volts. With reference to Fig. 2B, recall that the DEIS layer will conduct only if the potential difference between the diode plates is greater than 10 volts. Thus, PG2 will not conduct, since the potential difference between the V FG and V PG2 (9V - 0V = 9 volts) is not greater than 10 volts. However, PG1 will conduct, since V PG1 - V FG = 20 - 9 = 11 volts. PG1 will thus remove electrons from the floating gate (since the electrons are attracted to the higher potential of +20V) to the point where the floating gate has received an effective charge of +1.0 volts. When this occurs, conduction stops since the potential difference is no longer greater than +10V. The final "0" voltage of the floating gate is now set when PG1 and PG2 are returned to their quiescent levels of +5V. At this juncture, the voltage on the floating gate can be expressed as V FG = χ no V PG1 + Q FG /C FGT' (4) where Q FG the charge removed from the floating gate during the above-described writing operation. Under these circumstances, (i.e. V PG2 = V PG1 = 5V): such that the capacitive coupling during the quiescent state is 0.54 and the final voltage on the floating gate = (0.54) (5.0)+(1.0)= +3.7V. When a "1" is to be written into the cell, the control voltages are the same as those used to write in a "0". The word line is brought up to V DD =5.0V, as is PG2, and PG1 is brought up to +20V after a delay. The main difference is that the bit line voltage V BL is raised to V DD , such that the source diffusion 14 and the n+ diffusion 16 are raised to V DD -V T , or approximately +5V. Since both the drain and source diffusions are at +5V, an inversion layer forms between n-type region 16 and substrate 10. This inversion layer has a depletion capacitance C I of approximately 0.1 normalized. Recalling from Equation 1 that V FG =χ w V PG1 , where such that χ "1" ≅ 0.77 and thus V FG =(0.77)(20) = +15.4V when a "1" is to be written. With reference to Fig. 2B, PG1 will not conduct since the potential difference (20 - 15.4) is not greater than 10 volts. However, PG2 will conduct, since the potential difference (15.4 - 0) is greater than 10V. In this case, electrons will be injected by PG2 into the floating gate, until the voltage on the floating gate decreases to 10 volts. Thus, the floating gate received -5.4 volts worth of charge from PG2. When the control voltages are then removed (i.e. V PG1 = V PG2 = 5.0V), the charge on the floating gate decreases to -3.2 volts, since the depletion capacitance is removed and hence C FGT rises from C FGT"1" (≅1.3) to C FGT"0" (≅2.2). Thus, with Q FG /C FGT = -3.2V, V PG = +5.0V, and χ no = 0.54, V FG = (0.54) (5.0) - 3.2 = -0.5 volts. Thus, with the capacitive values given above, the floating gate will store +3.7 volts when a "0" is written in and -0.5 volts when a "1" is written in. The cell is read in the ordinary manner. That is, the bit line is brought low and the drain is sensed. If a "0" is stored, the positive voltage on the floating gate will induce a channel, such that the device conducts and the charge on the drain will decrease. If a "1" is stored, the negative voltage on the floating gate will not induce a channel, and there will be no change in the charge on the drain. Thus, it is the state of the channel which indicates the stored data state. The foregoing description of the operation of the cell was made with the assumption that the floating gate was devoid of charge when the writing operation was initiated. An important feature of the invention is that the new data can be written over the old data without the need for an intervening erasure of the old data. This feature will now be discussed in more detail. During the discussion, reference will be made to the following two relationships: (A) V FGI = χ "0"/"1" V PG1 + Q FG /C FGT"0"/"1" where V FGI = the new voltage of the floating gate at the end of the initial writing step; χ "0"/"1" V PG1 = the voltage on the floating gate at the end of the initial step assuming no previous floating gate charge; and Q FG /C FGT"0"/"1" = voltage on the floating gate due to the previous charge storage; and where V FGO = the final voltage upon quiescent conditions (= -0.5V for a stored "1", +3.7V for a stored "0"); χ no V PG1 = the component of the final voltage which is due to the voltage on the first program gate (note that since V PG1 always = 5.0 volts upon quiescent conditions and χ no always = 0.54 with the given capacitive values, this term always = +2.7 volts); and (1) Cell at "0" state, write in a "0": Under these circumstances, the voltage on the floating gate V FGI = (+1.0) + (+9.0) = 10 volts. That is, the floating gate has +1 volts worth of charge on it due to the previous storage of a "0", and it acquires +9 volts during the present writing in of a "0". Thus there will not be any charge injection, and the voltage on the floating gate after the cell is returned to its quiescent state V FGQ = 2.7 + 0 + 1 = +3.7 volts. (2) Cell at "0" state, write in a "1": Here, V FGI = +15.4 + 1.7 = +17.1 volts. Note that the "Q FG /C FGT " term has risen from 1.0 as in (1) above to 1.7, since C FGT has dropped from C FG"0" to C FG"1" . Thus, -7.1 volts will be initially injected into the floating gate by PG2. Upon quiescent conditions, V FGQ = 2.7 - 4.2 + 1 = -0.5 volts. Note that the newly injected charge (= -4.2 volts) has dropped from -7.1 volts since the inversion capacitance C I is dropped upon quiescent conditions; the old injected charge (= +1 volt) is due to the fact that a "0" was previously stored on the floating gate. (3) Cell at "1" state, write in a "1": Here, V FGI = +15.4V - 5.4V = 10V. The -5.4 volts arises from the previous storage of a "1". Thus, there will be no charge injection and the voltage upon quiescent conditions V FGQ = 2.7 + 0 -3.2 = -0.5 volts. (4) Cell at "1" state, write in a "0": Under these circumstances, V FGI = 9.0 - 3.2 = +5.8 volts, such that +4.2 volts of charge will be removed from the floating gate and V FGQ = 2.7 + 4.2 - 3.2 = +3.7 volts. Thus, as discussed above, the memory cell of the invention has the ability to write new information over previously stored information without an intervening erasure step. Moreover, the operation of the memory cell is relatively simple, requiring a minimum of support and/or decode circuitry (e.g., the voltages on PG2 and the word line are equal to +V DD when writing in a "0" or a "1").

Claims: Electrically erasable programmable read-only memory cell comprising a silicon semiconductor substrate (10) having a defined channel region, said channel region having a conductive state indicative of a logic state stored by the cell, a floating gate electrode (22) disposed above and insulated from said channel region by an insulator layer (20), said floating gate electrode (22) determining the conductive state of said channel region, a pair of program gates (PG1, PG2) disposed on said floating gate electrode (22), each of said pair of program gates comprising a layer (28A, 28B) of charge injection material having an electrical characteristic analogous to two back-to-back connected diodes, characterized in that said layers (28A, 28B) of charge injection material are separated from each other by an etched recess exposing the floating gate electrode (22), and in that voltage means controlling said pair of program gates (PG1, PG2) are provided, each of said pair of program gates (PG1, PG2) receiving independent control signals (V PG1 , V PG2 ) such that one of said pair of program gates (PG1, PG2) injects charge into said floating gate electrode (22) to write a first logic state into the cell, and the other of said pair of program gates (PG1, PG2) removes charge from said floating gate electrode (22) to write another logic state into the cell, and said program gates (PG1, PG2) overwriting successive logic states into the cell without an intervening erasure step. Storage cell in accordance with claim 1, characterized in that each of said pair of program gates (PG1, PG2) comprises a first layer (30, 32) of polycrystalline silicon overlying said layer (28A, 28B) of charge injection material and in that said floating gate electrode consists of a second layer (22) of polycrystalline silicon. Storage cell in accordance with claim 1, characterized in that said channel region of the substrate (10) is defined by first and second diffusion regions (14, 18) formed in said substrate (10). Storage cell in accordance with claim 3, characterized by a third diffusion region (12) formed in said substrate (10) and comprising a diffused bit line. Storage cell in accordance with claim 3, characterized in that said first and second diffusion regions (14, 18) comprise the source and drain electrodes of a field-effect transistor, the channel region of the transistor occupying that surface region of said substrate (10) which is overlaid by at least part of said floating gate electrode (22). Storage cell in accordance with claim 1, characterized in that said semiconductor substrate (10) has a plurality of diffusion regions (14, 18, 16, 12) implanted therein, a first one (14) comprising a source region, a second one (18) comprising a drain region, a third one (16) abutting said source region (14) and extending toward said drain region (18), said channel region being bounded by said second and said third diffusion regions (18, 16), and a fourth region (12) comprising a diffused bit line. Storage cell in accordance with claim 6, characterized by a word line electrode (24) for coupling signals from said diffused bit line (12) to said drain region (18), said word line electrode being located above and insulated from the substrate region bounded by said first and fourth diffusion regions (14, 12) by said insulator layer (20). Storage cell in accordance with claims 2 and 6, characterized in that said second polysilicon layer (22), said insulator layer (20) and said third diffused region (16) constitute a first capacitor (C FGN ), that said first and second program gates (PG1, PG2) combine with said second polysilicon layer (22) to constitute second and third capacitors (C PG1 , C PG2 ), respectively, which are commonly connected to said first capacitor (C FGN ), and that means are provided for applying control signals (V PG1 , V PG2 ) to at least one of said diffusion regions (14, 18, 16, 12) and said second and third capacitors (C PG1 , C PG2 ) , said second capacitor (C PG1 ) removing charge from said second polysilicon layer (22), thus writing a first logic state into the cell, and said third capacitor (C PG2 ) injecting charge into said second polysilicon layer (22), thus writing a second logic state into the cell, said logic states being overwritten into the cell. Storage cell in accordance with claims 7 and 8, characterized in that said means for applying control signals (V PG1 , V PG2 ) to at least one of said diffusion regions (14, 18, 16, 12) comprise a terminal connected to said bit line diffusion region (12) implanted in said substrate (10) and a terminal connected to said word line electrode (24) for coupling data signals from said bit line diffusion region (12) onto at least one of said first and second diffusion regions (14, 18).

Inventors: KASOLD, JEFFREY PATRICK, LAM, CHUNG HON
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1985
Main classification: H01L29
IPC codes: F15B5, H01L29, H01L21, H01L27, G11C17, G11C16