THIN FILM TRANSISTOR AND METHOD OF MAKING THE SAME

Abstract: A thin film transistor has a layer (15) formed by the in­ terfacial reaction between amorphous silicon and metal, which is used as a central or base electrode (15, 11). The base electrode (15, 11) is in the shape of stripes or a flat surface. The base electrode (15, 11) is sandwiched between the em­ itter (4, 5, 14, 10) and collector (4, 5, 6, 12) of the transistor, which may each consist of an n-type hydrogenated amor­ phous silicon layer (5) and an intrinsic hydrogenated amor­ phous silicon layer (4), with the intrinsic hydrogenated amorphous silicon layer (4) being close to the base electrode (15, 11). There may be p-type hydrogenated amorphous sil­ icon layers between the base electrode (15, 11) and the in­ trinsic hydrogenated amorphous silicon layer.

Description: THIN FILM TRANSISTOR AND METHOD OF MAKING THE SAME The present invention relates to a thin film transistor (hereinafter referred to as a TFT), and may be, for example, a switching transistor which is suitable for use in a liquid crystal display panel. Thin film type field effect transistors (TFT's) are known from e.g. U.S. Patent 3,191,061 and U.S. Patent 4,351,856. Fig. 1 of the accompanying drawings shows a sectional view of an example of a thin film transistor (FET type) employing hydrogenated amorphous silicon (a Si). A method of making this TFT will now-be briefly explained. A glass substrate 1 has a gate electrode 2 formed thereon, on which electrode 2 is formed an insulator 3, an intrinsic (i) layer 4, and an n-type layer 5 of amorphous silicon. Thereafter, electrode metals such as Cr 6 and Al 7 are evaporated or deposited, and they are processed to form source and drain electrodes 8 and 7 respectively. Using the fabricated pattern as a mask, the n-type layer of a-Si is etched by dry etching. The TFT thus manufactured is an enhancement-mode FET, the drain current of which has an ON/OFF ratio reaching 6 orders of magnitude. The OFF current is also as low as 5 pA (at a gate width of 300 p and a gate length of 10 p), and the FET is very suitable for driving liquid crystal. Since, however, the mobility of amorphous silicon is low, the switching time of the TPT is as long as approximately 10 ps. When a TFT is used as a switching device to drive the matrix of a liquid crystal display, operation by one point at a time is difficult. Accordingly, the matrix is driven by operation one line at a time. It has been found that the TFT causes a drift during operation under the subtle influences of interface properties. More specifically, as the drain current is caused to flow, a shift on the threshold voltage VT is observed, and the OFF current increases. The reason is thought to be that charges are injected into the gate insulator and are trapped there to give rise to semi-fixed charges. The present invention seeks to provide a thin film transistor of high speed and high stability. It does this by providing a conductive layer, formed by an interfacial reaction between amorphous silicon and metal, between the emitter and collector. The conductive layer acts as a control electrode. The emitter and collector also may include amorphous silicon, preferably hydrogenated. Several arrangements are possible, e.g. n i- conductive layer-in, n i p - conductive layer - p i n where n and p are the conductivity types of amorphous silicon layers and i is intrinsic semiconductor. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Fig. 1 is a sectional view of a prior-art a-Si TFT and has already been described; Fig. 2 is a sectional view showing a first embodiment of a TFT according to the present invention: Fig. 3 is a sectional view of the transistor shown in Fig. 2 as seen in a direction orthogonal to the interdigitated electrode thereof; Fig. 4 is a connection diagram of the bias voltage of the transistor of Fig. 2; and Figs. 5 and 6 are sectional views of second and third embodiments of a TFT according to the present invention. Embodiment 1: Fig. 2 shows a first embodiment of the present invention. The structure of this TFT resembles the socalled permeable base transistor (PBT), and employs as its base a layer formed by the interfacial reaction between metals and a-Si. FABRICATION A method of fabrication of the TFT of Fig. 2 will be explained. A Ta lower electrode 14 is formed by sputter evaporation on a glass substrate 1 to a thickness of 0.3 pm, the atmosphere being e.g. Ar gas. A layer 5 of hydrogenated amorphous silicon containing P (a-Si:H(n)) is formed on the electrode 14 at a substrate temperature of 2300C by a plasma Chemical Vapour Deposition (CVD) process using a gas in which PH3 and SH, are mixed mixing ratio: PH3/SiH4 > 0.5 V%). 4 Subsequently, an a-Si:H(i) layer 4 is formed using only SH, gas. After the formation of the a-Si:H(i) layer 4, Cr is evaporated or deposited on the whole surface thereof to a thickness of 0.1 pm. Thus, a thin interfacial reaction layer 15 is formed by the interfacial reaction between a-Si and Cr. The substrate temperature during the evaporation is preferably between 100 and SOOOC. The reason for this is that the reaction rate is slow below 1000C, while hydrogen begins to get away from a-Si at above 300 C. The required heating time in this case is about 30 to 60 minutes. Even when Cr is evaporated at room temperature and then heat-treated under the same condition, the interfacial reaction between a-Si and Cr similarly takes place to form a thin interfacial reaction layer. The thickness of the interfacial reaction layer is 10 nm or less. After the heat treatment, the Cr is removed. The etchant used may be an aqueous solution containing 250 gr./lit. of ceric ammonium nitrate. After the removal of the Cr, the layer of the interfacial reaction between Cr and amorphous silicon is etched so as to be left in an interdigitated shape. The etchant used may be HF : HNO : H O at a relative concentration of 1 : 1 : 30. The interfacial reaction layer left is in the shape of stripes at pitches of 2 pm and widths of 1.5 pm as illustrated in Fig. 3. It is also possible to etch the interfacial reaction layer by such means as a plasma asher. Subsequently, an i-layer 4 and n-layer 5 of a-Si are deposited, and an electrode metal (Cr) 6 is evaporated. Then, the transistor is finished. OPERATION The operation of the transistor is as follows. As illustrated in Fig. 4, an emitter electrode 10 is earthed, a collector electrode 12 is positively biased, and a base electrode 11 is supplied with a control voltage V to be negatively or positively biased. The c interfacial reaction layer 15 and the i-layer of a-Si 4 form a Schottky barrier. Accordingly, an emitter-base section operates as a Schottky diode. By reversebiasing this diode, a reverse bias is applied to the Schottky barrier, and a depletion layer spreads in the vicinity of the striped base electrode. Since the width of the depletion layer is substantially equal to the gap of the layer of the interfacial reaction between Cr and amorphous silicon, the path through which electrons flow can be controlled by varying the voltage to be applied to the base, and in turn, the collector current can be controlled. Thus, the structure of this device can be called a solid state triode when the base is considered to be the grid of a triode, and the operation mechanism is also similar. It is advantageous to use the layer of the interfacial reaction between Cr and amorphous silicon for achieving this structure. More specifically, the interfacial reaction layer is preferably 10 nm or less, and virtually no obstable is involved in burying it into a-Si. Further, the interfacial reaction layer may have a low resistance of approximately 104 Qb in spite of being such a thin film and can satisfactorily function as a control electrode. Although, in the above drawings, the structure exploiting only the layer of the interfacial reaction between chromium Cr and amorphous silicon a-Si has been referred to, transistor operation is possible even when chromium Cr is left. In this case, after a thin Cr layer (100 nm or less) is evaporated, it is heat-treated and is processed into the shape of stripes, whereby the transistor is produced without removing the remaining Cr layer. Since Cr and a-Si also form a Schottky barrier, transistor operation occurs. However, it is sometimes the case that the section of the electrode becomes the shape of a trapezoid with its base being shorter than its top or the shape of a pent roof at the step of processing Cr or processing the reaction layer, and that voids appear when a-Si is deposited subsequently. In this case, the function of the effective control electrode may be lost, and the transistor operation become imperfect. Accordingly, the adhesion between the base and a-Si must be sufficiently good. Even when the emitter and collector of the present structure are reversed, a similar operation is possible. In the embodiment, Cr has been removed after the formation of the interfacial reaction layer, and the region of the removal has not been especially referred to. A transistor operation region-is important as the region where Cr is removed, and of course, it is more convenient to leave Cr in the other region because a series resistance can be reduced. Embodiment 2: Fig. 5 shows a second embodiment of the present invention. A collector electrode Ta 14 is deposited on a glass substrate 1 as in the foregoing embodiment, whereupon amorphous silicon a-Si is formed in the order of an n-type layer 5, an intrinsic (i) layer 4 and a p-type layer 17 by a plasma CVD process. The p-type layer is formed using a gas in which B2H6 gas and SiH4 gas are mixed (mixing ratio: B2H6/SiH4 > 0.5 V%). The thicknesses of the n-layer, i-layer and p-layer are 30 nm, 500 nm and 20 nm, respectively. Subsequently, nickel Ni is evaporated and heat-treated (at 2200 C for 30 minutes) to form a layer 16 of the interfacial reaction between Ni and a-Si, which is processed into the shape of stripes as illustrated. The interfacial reaction layer which remains after removing the Ni layer functions as a base electrode. An aqueous solution containing 300 gr./lit. of ferric chloride may be used for the etching of Ni. Using the CVD process again, a p-layer 17, an i-layer 4 and an n-layer 5 are successively formed this time. Lastly, a Cr layer 6 is evaporated as an emitted electrode. The thicknesses of the a-Si p-layer, i-layer and n-layer are 10 nm, 500 rim and 20 nm, respectively. As for an ordinary bipolar transistor, this transistor operates by applying a forward bias across the emitter and the base, and a reverse bias across the base and the collector. Unlike the electrode 6, the electrode 14 may be selected as the emitter electrode. This embodiment may produce an a-Si transistor whose collector current is controlled by the forward bias applied to the base and which has a high response speed. Although a-Si p-layers 21 and 22 are used in the present embodiment, similar results are attained even in the absence of either p-layer. Embodiment 3: Fig. 6 shows a third embodiment of the present invention. The fabricating method of this embodiment is similar to that of the structure shown in Fig. 5, and shall be therefore omitted. The point of difference is the configuration of the base electrode, which is not processed into stripes. In the second embodiment using an interdigitated electrode, the current passes through the semiconductor regions between the electrodes, and the transistor operation is effected by controlling this path. On the other hand, in the third embodiment, a layer of the interfacial reaction between a-Si and chromium is formed over the whole area, and carriers travel across this interfacial reaction layer. This is based on the'same operating principle as that-of the socalled metal base transistor. Practical"use of the ordinary metal base transistor has had to be abandoned because it is difficult to deposit a thin metal layer reliably and uniformly. The layer of the interfacial reaction between a-Si and metals as stated in the present invention is very suitable as the base material of the metal base transistor owing to, not only the extreme thinness of preferably not more than 10 nm, but also low electric resistance and chemical stability. The transistor operation is effected by applying a forward bias across the emitter 10 (or 12) and the base 15 and a reverse bias across the base and the collector 12 (or 10). As the thickness of the base is smaller, the transfer efficiency is higher and the base transit time is shorter, so that the transistor has excellent high speed performance. The thickness of the interfacial reaction layer may be 3 nm or less, and favorable characteristics are attained. While, in the present embodiment, the construction in which the p-i-n diodes are disposed on both the sides of the interfacial reaction layer has been explained, the purport of the present invention is not always restricted thereto Similar effects ars attained even with a structure in which n-i-p layers an interfacial reaction layer - i-n layers are disposed as viewed from the emitter electrode side. In this case, the Schottky barrier is utilized. Further, this holds true for a structure in which n-i layers - an interfacial reaction layer - i-n layers are disposed from the emitter side. One of the advantages of the present invention resides in that the amorphous silicon a-Si may be readily deposited on a metal or on an interfacial metal reaction layer. Another merit of a-Si is that the magnitude of band gap energy can be varied, and a widegap emitter transistor can be fabricated by making use of this. That is, a hetero-transistor of more enhanced injection efficiency can be fabricated by replacing the a-Si on the emitter side with a-SiC wholly or partly. In addition, the characteristics can be improved if the a-Si layers on the emitter and collector sides are made of layers containing e.g. carbon (C) or germanium (Ge). The foregoing embodiments have used Cr and Ni for forming layers of the interfacial reactions between the metals and a-Si, but metal used is not restricted to these specific uses. The same effects can be produced using a. conductor layer which is formed at the interface between the metal and a-Si by the interfacial reaction of the a-Si with a metal film that contains, as an alternative or in addition to Cr and Ni, at least one of Mo, W, Ti, V. Zr, Nb, Ta, Pt, Hf, Pd, Rh and Co.

Claims: CLAIMS: 1. An amorphous silicon thin film transistor having an emitter (4, 5, 14, 10), a control electrode (11, 15), and a collector (4, 5, 6, 12); characterised in that: the control electrode has a conductive layer (15) formed by an interfacial reaction between amorphous silicon and metal. 2. A transistor according to claim 1, wherein the emitter includes a first hydrogenated amorphous silicon layer (5) and a first intrinsic hydrogenated amorphous silicon layer (4), and the collector includes a second hydrogenated amorphous silicon layer (5) and a second intrinsic hydrogenated silicon layer (4), the hydrogenated silicon layer (5) being of the same conductivity type and each being further from the conductive layer (15) than the corresponding intrinsic semiconductor layer (4). 3. A thin film transistor comprising a glass substrate, a lower electrode on the substrate, an emitter terminal which is connected to said lower electrode, a first n-type hydrogenated amorphous silicon layer on said lower electrode, a first intrinsic hydrogenated amorphous silicon layer on the first n-type hydrogenated amorphous silicon layer, a layer which is formed by an interfacial reaction between metal and amorphous silicon and which is on the first intrinsic hydrogenated amorphous silicon layer, a base electrode which is connected to an interface between the metal and the amorphous silicon, a second intrinsic hydrogenated amorphous silicon layer on the interfacial reaction layer, a second n-type hydrogenated amorphous silicon layer on the second intrinsic hydrogenated amorphous silicon layer, and a collector electrode on the second n-type hydrogenated amorphous silicon layer. 4. A transistor according to claim 3, wherein the interfacial reaction layer is on a whole area of the first intrinsic hydrogenated amorphous silicon layer. 5. A thin film transistor comprising a glass substrate, a lower electrode on said substrate, a first n-type hydrogenated amorphous silicon layer on the lower electrode, a first intrinsic hydrogenated amorphous silicon layer on the first n-type hydrogenated amorphous silicon layer, a first p-type hydrogenated amorphous silicon layer on the first intrinsic hydrogenated amorphous silicon layer, a layer which is formed by an interfacial reaction between metal and amorphous silicon and which is on the first p-type hydrogenated amorphous silicon, a second p-type hydrogenated amorphous silicon on the interfacial reaction layer, a second intrinsic hydrogenated amorphous silicon layer on the second p-type hydrogenated amorphous silicon layer, a second n-type hydrogenated amorphous silicon layer on the second intrinsic hydrogenated amorphous silicon layer, and a metal layer on the second n-type hydrogenated amorphous silicon layer; I C I I ' the lower electrode acting as an emitter electrode, the interfacial reaction layer acting as a base electrode, and the metal layer acting as a collector electrode. 6. A transistor according to claim 5, wherein the interfacial reaction layer is on a whole area of the first p-type hydrogenated amorphous silicon layer. 7. A transistor according to any one of the preceding claims, wherein the metal includes at least one of Cr, Mo, W, Ta, Ti, Ni, Pt, V, Zr, Nbm, R$ Pd, Rh, and Co. 8. A transistor according to any one of the preceding claims, wherein the interfacial reaction layer is in the form of stripes. 9. A transistor according to any one of the preceding claims, wherein the thickness of the interfacial reaction layer is not more than 10 nm. 10. A method of making a thin film transistor, comprising the steps of: a) evaporating a lower electrode on a glass substrate, br providing a first n-type hydrogenated amorphous silicon layer on the lower electrode, c) providing a first intrinsic hydrogenated amorphous silicon layer on the first n-type hydrogenated amorphous silicon layer, d) providing a metal layer on a whole surface of the resultant structure, e) forming the metal layer and a layer of an interfacial reaction between the metal layer and the amorphous silicon layer into a desired shape, f) providing a second intrinsic hydrogenated amorphous silicon layer on the interfacial reaction layer, g) providing a second n-type hydrogenated amorphous silicon layer on the second intrinsic hydrogenated amorphous silicon layer, and h) providing desired electrode wiring. 11. A method according to claim 10, wherein the metal layer contains at least one of Cr, Mo, W, Ta, Ti, Ni, Pt, V, Zr, Nb, Hf, Pd, Rh and Co. 12. A method according to claim 10 or claim 11, wherein the thickness of the interfacial reaction layer is not more than 10 nm. 13. A method according to any one of claims 10 to 12, wherein the interfacial reaction layer is in the shape of stripes. 14. A method according to any one of claims 10 to 13, wherein the metal layer is evaporated at a temperature of 100 to 3000c.

Inventors: NAKANO, TOSHIO, SASANO, AKIRA, SEKI, KOICHI, TSUKADA, TOSHIHISA
Applicants: HITACHI, LTD.
Application year: 1985
Main classification: H01L29
IPC codes: H01L21, H01L29