IC MEMORY DEVICES

Abstract: The invention comprises an improved bipolar memory device having enhanced protection against the effects of alpha particles comprising at least one memory cell having a buried layer forming at least a portion of the collector of one of the transistors in the memory cell, said buried layer being located sufficiently close to a base layer in only the memory portion of the device to provide a sufficiently high capaci­ tance between said buried layer and said base layer to prevent the occurrence of a soft error caused by an alpha particle striking the structure without interfering with the speed of the device.

Description: IC MEMORY DEVICES Memory cells in integrated circuits, consisting of cross-coupled transistors forming a flip-flop circuit are subject to soft errors caused by parasitic charges generated by alpha particles striking the integrated circuit structure (alpha strike). Such alpha particles, which may come from the ceramics used in packaging the integrated circuit, generate electron-hole pairs in the incident path of the alpha particles due to their energy loss. These electron-hole pairs may generate a parasitic noise current which may result in turning on the off transistor in the flip-flop circuit of the memory cell to cause a soft error. It is known that the problem of alpha strike can be reduced or eliminated by reducing the thickness and/or resistivity of the epitaxial silicon layer separating the buried collector layer from the base which effectively raises the collector-base capacitance. Increasing the collector-base capacitance increases the time constant of the memory cell and, therefore, the time required for the flip-flop circuit of the memory cell to invert from one stable state to the other is increased. This increases the immunisation of the circuit to parasitic charges generated by alpha particles which tend to be instantaneous. However, this increased capacitance degrades performance of the integrated circuit structure or chip by slowing down the logic circuit portions due to the increased time constant resulting from the modification to the epitaxial layer. Kato et al U.S. Patent 4,314,359 addressed this problem by selective heavy doping of an N+ buried collector layer in only the memory portion of an integrated circuit structure with ion-implanted arsenic. This provides auto-deping of a region over the buried layer to effectively reduce the collector-base spacing and thereby increase the collector-base capacitance in only the memory cell area. However, it is difficult to grow epitaxial silicon over ion-implanted silicon without generating defects in the silicon. Furthermore, out diffusion or autodoping is difficult to control to obtain a precise desired level of capacitance. If the region is under doped, i.e., the out diffusionis not sufficient, the capacitance increase will not be sufficient to obtain the desired increased time constant, and the cell will still be prone to soft errors from alpha particles. On the other hand, if the out diffusion is large some of the dopant may get into the active base region above, increasing the beta of the transistor. It would, therefore, be desirable to provide an integrated circuit structure wherein the memory cell portion of the circuit was protected from alpha strike without degradation of the performance of the logic portion of the circuit in a manner, which is simple and easily controlled, and which does not cause silicon crystal defects. It is therefore an object of the invention to provide an integrated circuit memory structure having enhanced protection against the effects of alpha particles striking the structure. According to one aspect of the present invention there is provided an improved bipolar memory device having enhanced protection against the effects of alpha particles, the device comprising at least one memory cell having a buried layer forming at least a portion of the collector of one of the memory transistors in the memory cell, said buried layer being located sufficiently close to a base layer forming at least a portion of the base of said memory transistor to provide a sufficiently high capacitance between said buried layer and said base layer to prevent the occurrence of a soft error caused by an alpha particle striking the structure. Preferably the base-collector capacitance in the memory portion of the integrated circuit structure is selectively increased without increasing the capacitance in the logic portion of the structure to provide a memory structure which is substantially immune to the effects of alpha particles striking the structure without degradation of the speed of the associated logic circuits in the structure. According to a further aspect of the present invention there is provided a method of constructing an improved bipolar memory cell device having enhanced protection against the effects of alpha particles which comprises selectively eliminating at least a portion of the silicon separating the base region from the buried collector layer in the memory region of said device to thereby increase the collector-base capacitance of the memory transistors without changing the collector-base capacitance of the logic transistors whereby the device is protected against the effects of alpha particles striking the device without degrading the speed of the device. In the accompanying drawings., by way of example only: Figure 1 is a cross-sectional view of a portion of an integrated structure after formation of an N+ buried layer thereon, respectively, for formation of logic and memory transistors thereon. Figure 2 is a cross-sectional view of the structure of Figure 1 showing selective removal, by etching, of a portion of the N epitaxial silicon layer overlying the N+ buried layer in the memory region. Figure 3 is a cross-sectional view of the structure of Figure 1 showing the preferred selective removal, by oxidation and oxide removal, of a portion of the N epitaxial silicon layer overlying the N+ buried layer in the memory region. Figure 4A is a cross-section view of a portion of the structure of Figure 3 after construction of a logic transistor thereon. Figure 4B is a cross-section view of a portion of the structure of Figure 3 after construction of a memory transistor thereon. The illustrated structure provides enhanced immunity to the effects of alpha strike by selective increase of the collector-base capacitance in the memory transistors while retaining conventional collector-base capacitance in the logic transistor. Such an increase in capacitance in the memory portion of the structure only will not substantially affect the speed of the structure as would increased capacitance in the logic portion. Conversely, the effects of alpha strike, by changing the memory state of the memory cell, are much more severe in the memory portion of the structure than in the logic portion. Hence selective protection of the memory portion of the structure from the effects of alpha strike results in an improved bipolar memory cell structure without degradation of the performance of the structure. Referring now to Figure 1, an integrated structure is shown comprising a P-silicon substrate 10 on which is conventionally formed buried layer portions 16 and 18 which will respectively form the collectors of a logic transistor and a memory transistor. An N epitaxial layer 22 of silicon is then conventionally grown over buried layer portions 16 and 18. At this point, a dielectric film is formed which preferably comprises growing a thin silicon oxide layer 30 and forming a silicon nitride layer 32 over oxide layer 30 using, for example, ammonia and silane as is well known to those skilled in the art. The structure is then masked using photoresist 36 to provide an opening only in the memory area as shown in Figure 1. The nitride and oxide layers are etched away through the mask opening using, for example, a plasma etch or a phosphoric acid wet etch. After removal of the exposed nitride and oxide layers, and the photoresist layer,at least a portion of the epitaxial silicon layer 22 over buried layer portion 18 is removed. As previously stated, the purpose of the removal of at least some of the epitaxial silicon overlying the buried collector layer of the memory transistor is to reduce the depletion width between the collector region, and the base region which will be formed in the epitaxial silicon layer 22, sufficiently to provide the desired capacitance increase. Thus the epitaxial silicon removed is an amount which will leave remaining sufficient epitaxial silicon to permit the formation of a base region having a lower boundary ranging from just above the collector to partially diffused into the collector as will be discussed below. The buried layer to base spacing should not exceed 3 microns, and preferably, not exceed 2 microns. The removal of at least some of the exposed epitaxial silicon in layer 22 overlying buried layer portion 18, representing the memory area of the structure, may be accomplished by etching the silicon through the mask. The resulting structure is illustrated in Figure 2. The epitaxial silicon may be removed with a wet etch, such as chromic trioxide. However, in a preferred embodiment, as shown in Figure 3, the silicon is removed in a more precise and controlled manner by oxidizing the silicon and then selectively removing, with a conventional HF oxide etch, only the oxide grown through the mask. In this embodiment, a layer of silicon oxide is grown through the mask and then removed to provide the desired amount of silicon removal. The amount of silicon oxide grown will depend upon the amount of silicon layer 22 which one desires to remove, as previously discussed. Comparison of the geometry of the remaining structure shown in Figure 2 at 50 after removal of the epitaxial silicon by etching with that shown in Figure 3 at 50' after removal of the epitaxial silicon via the oxidation method shows that a smoother step results from the preferred oxide growth and removal form of thinning epitaxial silicon layer 22 in the memory area. As previously discussed, the actual amount of silicon in layer 22 which is removed in accordance with the practice of invention will vary depending upon the amount of increased capacitance needed to raise the time constant sufficiently to desensitize the memory circuit to instantaneous charges or noise generated from an alpha particle striking the structure. It has been found that removal of all but about 0.3 to 1.5 microns of epitaxial silicon layer 22 is usually adequate to provide the needed capacitance increase. Figures 4A and 4B shows the structure of Figure 3 after construction, respectively, of a logic transistor and a memory transistor. Figure 4A shows the logic transistor, which is of conventional construction, and comprises a base contact 60 overlying a portion of intrinsic base region 62; an emitter contact 70 overlying an emitter region 72; and a collector contact 80 overlying collector region 82. P+ extrinsic base regions are provided at 64 and 66. Silicon oxide is shown at 68. Figure 4B illustrates the memory transistor which, except for its location with respect to buried collector layer 18, may be constructed identically to the logic transistor of Figure 4A and, thus, is denoted with the same reference numerals. However, advantageously, intrinsic base region 62 of the memory transistor in Figure 4B is not spaced as far from the N+ buried collector layer 18 as is the logic transistor base region 62 in Figure 4A from its buried collector layer 16. Thus, the collector-base capacitance between memory base 62 and memory collector 18 of the memory transistor in Figure 4B is increased over the conventional base-collector capacitance which is present in the logic transistor construction. This selective increase in capacitance thus renders the memory portion of the cell more immune from the effects of alpha strike without, however, interfering with the collector-base capacitance of the logic portion of the cell. Thus, the speed of the device is not affected by the modification. It should be noted here, that while the memory transistor structure shown in Figure 4B illustrates intrinsic base region 62 as located immediately adjacent buried collector layer 18 with no epitaxial silicon 22 therebetween, it is within the purview of the invention that a thin layer of epitaxial silicon 22 may remain to separate intrinsic base 62 from buried collector 18 provided the layer 22 is thin enough to achieve the desired capacitance increase. It is also within the scope of the invention to permit some overlap, i.e., diffusion of the base region and the buried layer region into one another provided the diffusion overlap is not sufficient to result in an unacceptable increase in the beta of the memory transistor. To further illustrate the invention, a number of sample parts were constructed and tested, each having 1K memory cells. A first group of 10 parts, denoted as Group A in the table below, were constructed in accordance with the invention with epitaxial silicon removed, in the memory cell areas only, by growing and then removing a 1.5 micron oxide layer over the buried memory collector layer. A second group of 10 parts, denoted as Group B, consisted of 10 parts constructed similarly to Group A except that the thickness of the oxide formed over the buried collector was only 1.0 microns. Group C represents 10 1K parts having a 1.5 micron layer of oxide grown and removed across the entire structure, i.e., in both the memory and logic transistor areas. Group D represents a fourth group of 10 parts constructed using conventional collector-base spacing with no removal of epitaxial silicon between the intrinsic base and the buried collector layer. Each of the parts in each group was tested on an accelerated basis for about 5-6 minutes using a thorium foil source of alpha particles with a siren memory pattern written into each part. At the end of the test period, each cell was read to determine how many cells had changed from 1 to O (or O to 1) indicating a soft error due to alpha strike. The total elapsed testing time for all the parts in a group was then noted and a failure rate per hour calculated from the elapsed time and the total number of failures in all the parts tested for that group. The speed of the logic was also measured and recorded as an average for each group to provide a comparison between the conventional prior art construction (Group D); the construction in accordance with the invention (Groups A and B); and the construction of Group C wherein the logic capacitance was also increased. With respect to speed, it will be seen that the structure of the invention is essentially the same as that of the conventional cell. On the other hand, the Group C structures, having increased logic capacitance as well as memory capacitance, were much slower. With respect to soft error failures, Groups A and B, constructed in accordance with the invention, exhibit a radical improvement over the conventional prior art structures of Group D. TABLE I IEE TIME TIME NUMBER FAILURE 25 C 25 C 100 C OF TIME RATE GROUP (ma) (ns) (ns) FAILS (Minutes) (Fails/Hr) A 120 8.7 8.8 1 54 1.11 B 123 8.9 8.9 3 60 3 C 105 11.2 12.7 0 48 0 D 139 7.6 9.3 258 54 287 Accordingly, there is provided a novel bipolar memory cell structure having improved resistance to the effects of alpha strike without degradation of performance. The structure can be formed in a simple, yet accurate and easily controlled process and which does not result in silicon crystal defects.

Claims: CLAIMS 1. An improved bipolar memory device having enhanced protection against the effects of alpha particles comprising at least one memory cell having a buried layer forming at least a portion of the collector of one of the memory transistors in the memory cell, said buried layer being located sufficiently close to a base layer forming at least a portion of the base of said memory transistor to provide a sufficiently high capacitance between said buried layer and said base layer to prevent the occurrence of a soft error caused by an alpha particle striking the structure. 2. The bipolar memory device of claim 1 wherein said buried layer is spaced closer to said base layer in the memory portion of said cell than in the logic portion of said cell whereby the collector-base capacitance in the logic portion of said device is not as high as the collector-base capacitance in the memory portion of said device whereby said device is protected against the effects of alpha strike without materially interfering with the speed of the device. 3. The device of claim 2 wherein the spacing between said buried collector layer and said base layer ranges from substantially adjacent to one another to diffusion of one region into the other in the memory portion of said device to provide the desired capacitance. 4. The device of claim 2 wherein said buried collector layer and said base layer in the memory portion of said device are spaced apart a distance less than the collector-base depletion width of the logic transistors in said device to provide the desired capacitance. 5. A method of constructing an improved bipolar memory cell device having enhanced protection against the effects of alpha particles which comprises selectively eliminating at least a portion of the silicon separating the base region from the buried collector layer in the memory region of said device to thereby increase the collector-base capacitance of the memory transistors without changing the collector-base capacitance of the logic transistors whereby the device is protected against the effects of alpha particles striking the device without degrading the speed of the device. 6. The method of claim 5 wherein substantially all of the silicon separating said buried collector layer from said base region is eliminated in the memory portion of said device to provide said selective capacitance increase. 7. The method of claim 5 which includes eliminating a sufficient amount of the silicon separating said buried collector layer from said base region in said memory region of said device to provide a collector-base spacing in said memory region of not greater than 3 microns. 8. The method of claim 5 which includes selectively removing said silicon by selective etching of the silicon overlying said buried collector layer in said memory region of said device. 9. The method of claim 5 which includes the steps of selectively removing said silicon by selective growth of oxide of the silicon overlying said buried collector layer in said memory region of said device followed by removal of said oxide. 10. A method of constructing an improved bipolar memory cell device having enhanced protection against the effects of alpha particles which comprises selectively removing a sufficient amount of epitaxial silicon separating the base region from the buried collector layer of the memory transistors within said device to provide a maximum collector-base spacing of 2 microns to thereby increase the collector-base capacitance of the memory transistors without changing the collectorbase capacitance of the logic transistors whereby the device is protected against the effects of alpha particles striking the device without degrading the speed of the device.

Inventors: WANDERMAN, DREW, WEINBERG, MATTHEW
Applicants: ADVANCED MICRO DEVICES, INC.
Application year: 1985
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21