A CELLULAR FLOATING-POINT SERIAL-PIPELINED MULTIPLIER

Abstract: A cellular floating-point serial pipelined multiplier arranged to accept two synchronous digit serial data streams in floating-point format and output one identically formatted stream which is the floating-point product of the synchronous input members, comprising a delay circuit (1) for the X operand and a digit re-ordering/delay circuit (2) for the Y operand connected to a pipelined addition circuit (3) which outputs the product through a delay cell (6), a MODE control signal propagation and generation circuit (4) connected to the pipelined addition circuit (3) and to the digit re-ordering/delay circuit (2), and a cell differentiation circuit (5) connected to control the pipelined addition circuit (3) and the digit re-ordering/delay circuit (2) and the X operand delay circuit (1).

Description: A CELLULAR FLOATING-POINT SERIAL-PIPELINED MULTIPLIER This invention relates to a floating-point serial- pipelined multiplier. Architectures well-matched to the computationally intensive task of real-time SONAR signal processing have been proposed by Whitehouse 5. and SPEISER (1981) based on the systolic techniques of KUNG (1979). These architectures are characterised by arrays of identical, limited capability systolic processing elements (SPE's) with minimum complexity nearest neighbour interconnections which allow a large number of parallel 10. arithmetic operations to occur. However, direct handling of the large-order matrices typical of SONAR applications is difficult. Physically realisable systolic arrays are currently of limited size and partitioning of the matrix computation is mandatory. 15. This partitioning diminishes the benefits of the systolic approach. A design methodology which minimises the partitioning problem is the bit-serial approach proposed by LΫON (1981). It is based on minimum area serial data paths 20. and fixed-point serial processing elements and allows many more processing elements to be included in a systolic array. For SONAR however, the use of fixed-point arith¬ metic imposes unacceptable constraints. In particular, the large dynamic ranges typical of the application can only 25. be met indirectly by increasing the precision of the representation (i.e. the number of bits). This solution slows the achievable processing rate and incurs area overheads of 0(n) where n is the number of bits in -» the representation. Further, number overflows must 30. be prevented by periodic rescaling which increases quantum noise in intermediate values. The net effect is a degradation of processor throughput. To optimise system performance a floating-point format is required. This permits both precision and dynamic range to be independently optimised, and it is shown that it can be implemented with a methodology 5. related to the work of LYON. Bit serial data paths and processing elements are used and an associated mode bit differentiates between mantissa and exponent. Each multiply/accumulate SPE as defined by WHITEHOUSE and SPEISER is constructed from several registers and 10. a multiplier and accumulator. The major element is the multiplier. Current work on floating-point multipliers for systolic processor applications such as NASH (1984) uses parallel algorithms to implement the multiplication. The problem of implementing minimum complexity units is 15. addressed as an application of this invention. A study of the work on serial fixed-point multipliers, originally proposed by JACKSON et al. (1968), revealed many references to their inherent capability to perform concurrently the operation X x Y + Z. This patent 20. demonstrates a use for the addition operator which is applicable to the direct handling of time division multiplexed exponents in a serial floating-point data format. A canonic multiplication cell is described which when used in a linear array implements a serial- 25. pipelined floating-point multiplier. For an m-bit mantissa and e-bit exponent, the area of the multiplier is 0(m), independent of the exponent length. Further, the exponent length is arbitrary and allows the dynamic range to be varied during task execution. 30. The implications of this low complexity VLSI implemen¬ tation optimised for both precision and dynamic range for real-time signal processors with computation rates in excess of 1000 million floating-point operations per second are significant. The object of the present invention is the 5. implementation of a serial floating-point multiplier. SERIAL-PIPELINED MULTIPLIERS Serial-pipelined multipliers have attracted continuing attention for digital signal processing applications and reference may be had to a report of JACKSON, L.B., 10. -KAISER, J.F. and McDONALD, H.S. "An approach to the Implementation of Digital Filters", published in IEEE Trans, on Audio and Electroacoust. , Vol. AU-16, pp. 413-21, Sept. 1968. Further examples are LYON, R.F., "Two's Complement Pipeline Multipliers", IEEE Trans. 15. on Comm. COM-24, pp. 418-425, 1976, also BALDWIN, G.L., MORRIS, B'.L., FRASER, D.B. and TRETOLA, A.R., "A Modular, High-Speed Serial Pipeline Multiplier for Digital Signal Processing", IEEE J. Solid-State Circuits, SC-10, pp. 307-13, October 1975, and PEKMESTZI, K.Z. and PAPADOPOULIS, 20. G.D., "Cellular two's Complement Serial-Pipeline Multipliers", The Radio and Electronics Engineer, Vol. 49, No. 11, pp. 575-580, November 1979. Number representations have been restricted in these examples to sign-magnitude and two's complement 25. fixed point. However, the implementations have varied from the direct addition of partial products to a five level re-coded Booth's algorithm. Examination of these implementations indicated that a minimum complexity design which offered most in terms of modularity was 30. that proposed by PEKMESTZI and PAPADOPOULIS above. A brief description of a modification of this multiplier follows. Operands are represented in two's complement notation: n-1 i=l m-1 Y = -y 0 + ∑.y. 2 " J (2.2) j=l As the operands are less than one, the product is also less than one and can be written A = (X.Y + 2) mod 2 (2.3) 5. Substituting (2.1) and (2.2) and after some algebra, A = [ ∑ x i ,2- i ∑ y . 2 ~ J + y 0 (∑ x ± 2 "1 + 2 "n+1 ) + ( ∑ -,(yjX 0 > 2 ~j + 2 "m+1 ) + Λ ( -,x 0 y 0 ) ] mod 2 ( 2.4 ) where '"-' represents logical negation. Use of modulo.2 in equation (2.4) indicates that carries are not considered in the analysis. The algorithm of (2.4) is implemented with the 10. basic cell of figure 4. This figure differs somewhat from that presented by PEKMESTZI and PAPADOPOULIS. An additional delay element has been used for the partial product and carry terms to provide a simpler control structure. A further difference is the allow- 15. ance for both operands to be serial. A complete nxn serial-pipelined multiplier is constructed of n basic cells. Three cell types are required, corresponding to the last, second to last and other stages. Cell types are differentiated from each other by two links shown in figure 4. Link positions are given in Table 1. Table 1: Link positions for a k-stage multiplier array. STAGE 1..K-2 K-l K LINK A 1-2 1-3 1-3 LINK B 1-4 1-2 1-3 Operands are entered with the least significant bit first. A control signal is entered in parallel with the data such that it is low only during the entry of the most significant bit (MSB). This signal * 10. performs the following functions: (a) Latches Y. in cell (n-i) in order to invert the order of.,the bits in the Y operand. (b) Truncates the partial product sum from the preced¬ ing cell and substitutes the carry. 15- (c) Realises via the EXCLUSIVE-OR gate the third term of (2.4) . (d) Initialises all partial product terms to zero except in the final two stages. The second to last stage has a weight of 2 ~n added, and so effects rounding 20. instead of truncation and in the last stage the term (y 0 2 " ) is added. The term 2 ~m+1 of (2.4) ' is added to the first stage by setting the carry input to that stage high and holding the partial product input low. Terms 25 by inverting the x. in the second to last stage. A SERIAL-PIPELINED FLOATING-POINT MULTIPLIER The cellular floating-point serial pipelined multiplier according to this invention is arranged to accept two synchronous digit serial data streams in floating-point format and output one identically formatted stream which is the floating-point product 5. of the synchronous input members characterised by a delay circuit for the X operand and a digit re-ordering delay circuit for the Y operand connected to a pipelined addition circuit which outputs the product through a delay cell, further characterised 10. by a MODE control signal propagation and generation circuit connected to the pipelined addition circuit and the digit re-ordering/delay circuit, and by a cell differentiation circuit connected to control each of the said pipelined addition circuit and the 15. digit re-ordering/delay circuit and the X operand delay circuit. In the cellular floating-point serial-pipelined multiplier, differentiation between mantissa and exponent is achieved with an additional stream of 20. control digits in a multiplier having modules in which the number of modules defines the number of digits in the mantissa and the number of digits in the exponent is arbitrarily greater than one. The cell structure is arranged to allow both addition and multiplication 25. to be performed in one array of cells by use of a delay circuit for the Y operand, and the delay allows the exponent to propogate through the array unchanged in the addition mode and to support the re-ordering of the mantissa digits for the multiply mode. 30. To enable the invention to be fully appreciated the following description has reference to the accompanying drawings in which: Fig. 1 is a functional schematic of an arbitrary length floating-point multiplier array, 35. Fig. 2 shows the propagation of the MODE signal through a four cell array for operands consisting of a four bit mantissa and a three bit exponent, and Fig. 3 is a functional representation for the array of Fig. 2 drawn to the same MODE signal as Fig. 2 showing the time and space distribution of the 5« multiplication, addition and delay operations. Fig. 4 is a diagram showing a two's complement multiplier cell, this being the basic cell referred to earlier herein, Fig. 5 is a diagram showing a floating point-multi¬ 10 plier cell according to this invention, Fig. 6 is a fully modular floating-point multi¬ plier cell, Fig. 7 is a block schematic of an unnor alised parallel floating point multiplier, 15* Fig. 8 is a block schematic of a conventional approach to the construction of a bit-serial, floating¬ point multiplier, Fig. 9 is a block schematic of a cellular serial pipe-lined floating-point multiplier, and 20; Fig. 10 is a timing schematic for a four cell multiplier array. As will be seen from the illustrations, a floating¬ point number F is composed of two parts, a fractional mantissa M and an integral exponent E, and can be 25. represented as = (E S M (3.1) The real number representation R of this floating¬ point representation is R = M b E (3.2) where b is the base of the both M and E. The product P of two floating-point numbers F. 30. and F ? can be expressed. P = F 1 ( * ) F 2 ( 3 . 3 ) where (*) denotes a floating-point multiplication operation. Substituting (3.1) P __ E 15 M^ (*) ^E 2 , M 2 = |E 1 + E 2 , M 1 . M^ (3.4) where + represents addition 5. and . represents multiplication. Floating-point multipliers are typically con¬ structed in a manner detailed in fig. 7. This schematic shows the x and y integral exponents directed to a parallel adder 1-2 and the fractional X and Y mantissae 10. directed to a parallel multiplier 13. For number representations which are wider than the available data paths additional control circuitry is required to schedule the operands through the arithmetic units. Post-normalisation has not been considered. 15. A conventional approach to the -implementation of a multiplier for a serial floating-point format is shown in schematic form in fig. 8. Multiplexers 14 and 15 direct the integral X and Y exponents through a serial adder 16 and the X and Y fractional mantissae 20. through a serial-pipelined multiplier 17 with the serial pipelined multiplier 17 output directed to the serial result multiplexer 18 but with the serial adder 16 output directed to the multiplexer 18 through the delay 19, all under control of the control unit 25. 20 which receives instruction signals from the mode control 9. The spatial separation of the parallel implementation is translated to a time separation in the serial multiplier of fig. 8. The serial adder 16 and serial multiplier 17 of fig. 8 perform the 5. same functional roles as the parallel adder 12 and parallel multiplier 13 of fig. 7. Functional com¬ plexity for the serial case is increased by the distribution over both time and space of both exponent and mantissa. This increase in complexity is 10. illustrated by the additional functional elements 14,15,18,19 and 20 of fig. 8 which are required in addition to the serial equivalents of the parallel adder 12 and multiplier 13 of fig. 7. A new approach to the problem of implementing a * 15. serial floating-point multiplier is detailed in this patent and it demonstrates how using as a basis a . serial-pipelined multiplier, all of the additional • •functional elements 14,15,18,19 and 20 of fig. 8 can be integrated into a simple cellular structure. 20. Instead of multiplexers 14 and 15 separating exponent and mantissa for independent processing and subsequent combination of the result by multiplexer: 18 as in fig. 8, the multiplier structure 17 is modified to allow both the addition and multiplication operations 25. to be performed in one array of cells. This is possible in a serial floating-point format. The multiplier 17 cannot achieve full utilisation for arbitrary exponents as varying delays are introduced between successive mantissae as a function of the exponent 30. lengths as shown in the timing schematic fig. 10. During these delays the multiplier adders become idle in a pipe-lined sequence which propagates through the array. Use is made of the adder in the last cell during its idle state to perform exponent addition. 5. To efficiently utilise this adder in a dual role for both multiplication and addition a delay circuit is constructed for one operand to propagate an unchanged exponent through the array in the addition mode and to re-order and store the mantissa digits in the multi- lø , plication mode. An arbitrary length cascade of cells which directly handle a floating-point data format in this way is shown in a functional schematic form in Figure 1. Five functional circuits 1, 2, 3, 4 and 5 are con- * j _5 > structed. The X and _Y operands are input to the delay circuit 1 and the digit re-ordering/delay circuit 3 respectively and the outputs from each of these circuits are combined in the pipeline-d addition circuit 2 to form the floating-point product X x Y which is 20. output via the delay cell 6. The cell differentiation circuit 5 controls in¬ dividual cell function. Signals entering the circuit 5 are SELO and SELI and they are both held at a logic high. Interconnection of these signals between cells 25. provides three independent control states to define the three cell types required for ' correct multiplier operation. The different cell types invert the X operand in the last cell and correctly handle the carry signals for the pipelined adders. The MODE signal, which dif- 30. ferentiates at the multiplier input the operand man¬ tissae and exponents, is entered into a control signal propagation and generation circuit 4. When MODE is a logic high it defines the presence of a mantissa bit and a multiplication operation, and when low it defines an exponent and an addition. This use of the MODE bit to differentiate exponent and mantissa also allows the identification of the MSB's and is an exten¬ sion of the approach adopted by LYON in the fixed-point 5. case. The pipelined addition circuit 3 functions in two distributed modes which propagate across the array as a function of the MODE signal. The low to high transition of this signal at a cell boundary initialises 10. the carry inputs to the adders and begins a multipli¬ cation. Partial product information is transferred across cell boundaries in this mode. Carry information is transferred from each cell to its successor at the end of the multiplication phase when the MODE 15. signal undergoes a high to low transition. The addi¬ tional delay stage 6 at the end of the addition circuit 3 is required to re-synchronise the product with the MODE signal. The product is subject to 2k-l delays in a k-cell array while the MODE signal is subject 20. to 2k delays. This additional delay matches both delay paths. During the addition phase, when MODE is low, no information is transferred across cell boundaries and all cells function independently. This results 25. in a simple addition of the operands in the last cell as required for the exponents. The bit re-ordering/delay circuit 2 supports two data handling operations for the Y operand which are necessary to implement multiplication and addition 30. in one iterative array. The operations: (1) Mantissa bit reversal and storage (2) Exponent delay synchronised with the X operand. The delay circuit for the X operand provides two delay stages per cell and under the control of SELO 35. and SELI inverts the data used in the last cell. The principle of operation discussed above is illustrated by considering a particular implementation. Fig. 5 shows a floating-point multiplier cell. Multiplication of two n-bit mantissae is performed 5. by an array of n cells implementing the algorithm described in section 2. As before, three cell types are required in the array, and are constructed from the basic cell by the placement of the two links shown in fig. 5 and whose position is detailed in Table 10. 1 herein. During operation a MODE bit is entered in parallel with the data to identify the data type (mantissa or exponent) and to select both the operation required and the nature of the delay for the Y operand. A logic 15. high enables a multiplication operation and a logic low an addition. The delay structure of one or two delays per cell for the Y operand allows respectively the re-ordering of the Y mantissa during a multiplica¬ tion, and the synchronous delay of both X and Y expo- 20. nents during an addition. Exponent addition is performed by the carry-save adder in the last cell. Both modes are fully pipelined. In an NMOS implementation the time penalty of th_ s cell compared with the of PEKMESTZI and PAPADOPOULIS if due to one additional pass transis- 25. tor in the logic preceding the full adder. A further delay present in the cell shown is due to the internal identification of the MSB. Overall cell speed can be increased by the use of independent MODE and MSB control signals. 30. The fully pipelined, alternating exponent and mantissa format is preserved at the output of the multiplier with the qualification that the result is not normalised. The worst case normalisation required is one bit which presents no numeric problems when 35. the multiplier is followed by a floating-point adder as in an SPE. A fully modular floating-point multiplier cell as illustrated in Fig. 6 has the link structure of figs. 4 and 5 removed and replaced with multiplexers and two control lines. Logic highs are entered from 5. the last cell and propagate a maximum of two cells backwards along the array to perform the differentiation of cell function. The multiplexers incur a minor time penalty, but minimise the system complexity by allow¬ ing all cells to be identical. Operation of the array 10. is identical to the multiplier discussed above. Fig. 2 shows the propagation of the MODE signal through a four cell multiplier for the case of an operand with a four bit mantissa- and a three bit ex¬ ponent. There are two delay stages in each cell with 15. the arithmetic operation coinciding with the second delay. At any time instant a row of fig. 2 describes the contents of each cell in terms of an addition or multiply symbol (exponent or mantissa respectively).. As'there is 'only one arithmetic operation in each 20. cell, an additional diagram, Fig. 3 shows the distri¬ bution in time and position of the useful arithmetic operations carried out in the array. The delay stages are denoted by - either D+ or Dx to indicate ' whether an exponent or mantissa bit is stored, and the computa- 25. tion stages are denoted by a multiplication, addition or subtraction operator. The subtraction operator indicates that an operation which does not contribute to the result is carried out. It can be seen from this diagram that the 4x4 multiplication is carried 30. out with 16 multiplication operations pipe-lined across the array and the 3-bit exponent addition is carried out with 3 additions in the last cell. In the timing schematic shown in Fig. 10 the man¬ tissa length is equal to the number of cells, in this 35. case shown as four, while the exponent length is arbi¬ trarily greater than one and is shown as three for the purpose of illustration. Two phase clocking (φ 1 and Φ 2 ) has been assumed. The MODE input defines exponent and mantissa to the multiplier array, and the MODE output defines the product exponent and mantissa. A 5. single delay stage is required at the result output to properly synchronise result and MODE signals. The unlimited exponent range achieved with the circuit of Figs. 5 and 6 is achieved naturally. This is an advantage of the approach. 10. From the foregoing it will be seen that the inven¬ tion is concerned with the following: (1) In a serial floating-point data format the multi¬ plier for the mantissae cannot achieve full utilisation for arbitrary exponents as varying delays are introduced 15. ' between successive mantissae as a function of the exponent lengths. During these delays multiplier adders become idle in a pipelined sequence which propagates through the array. Use is made of the idle adder in the last cell to carry out the exponent addition. 20. (2) Use of this last cell in an efficient dual role for both multiplication and addition requires a new delay structure which supports both mantissa bit re-ordering and exponent delay. The bit re-ordering/delay circuit of Fig. 1 performs these functions. The two modes are 25. fully pipelined with no guard bits between them and are implemented with the minimum number of delay elements . (3) Recognition that idle adders in the multiplier structure can be used to carry out exponent addition with no separate adder, together with the design of the 30. bit re-ordering/delay circuit to implement the concept with an optimum number of delays effectively integrates the seven functional blocks in Fig. 8 into the single cellular structure of Fig. 9. This greatly simplifies the design task for a floating-point multiplier, as only 35. a single, small cell as shown in Fig. 6 need be designed, (4) The design of the cell differentiation circuit in Fig. 1 and associated structures in the cells to respond to the control signals provides advantages when design¬ ing arbitrary precision multipliers. The design task is 5. minimised by requiring only one cell to be replicated. (5) The multiplier has the unique attribute that arbitrary dynamic ranges are handled automatically and precision is controlled simply by the number of cells used. It therefore provides a minimum complexity 10. solution to the problem of designing floating-point multipliers for arbitrary precision and dynamic range. IMPLEMENTATION CHARACTERISTICS Floating-point arithmetic units designed for use in VLSI systolic arrays must be numerically robust. 15. This is a consequence of the inability to handle an exception condition in a primitive SPE. For the floating-point multiplier as discussed, no difficulties can arise during the processing of normalised mantissae. The only exceptions possible are due to inadequate 20. exponent range. The proposed cell provides a solution to this representation problem by allowing the number of bits in the exponent to be dynamically varied. Guard digits can be carried in the exponents, and the number of digits increased as required to prevent 25. overflow during computation. There is a lower limit of one digit with no upper limit. This dynamic exponent control allows optimisation of both computation time and storage requirements. CONCLUSIONS 30. From the foregoing it will be appreciated that a serial floating-point multiplier has been provided The area-time product of the bit-serial multiplier approaches the optimum, and the overall complexity is minimised by a fully modular design. An unlimited exponent range is a feature of the implementation which 5. offers an unusual ability to handle a class of numerical problems with large dynamic ranges.

Claims: THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS: 1. A cellular floating-point serial pipelined multi¬ plier arranged to accept two synchronous digit serial data streams in floating-point format and output one identically formatted stream which is the floating-point 5. product of the synchronous input members characterised by a delay circuit (1) for the X operand and a digit re-ordering/delay circuit (2) for the Y operand con¬ nected to a pipelined addition circuit (3) which outputs the product through a delay cell (6), further character- 10. ised by a MODE control signal propagation and generation circuit (4) connected to the pipelined addition circuit (3) and the digit re-ordering/delay circuit (2), and by a cell differentiation circuit (5) connected to control each of the said pipelined addition circuit (3) and the 15. digit re-ordering/delay circuit (2) and the X operand delay circuit (1)-. 2. A cellular floating-point serial-pipelined multiplier characterised in that differentiation between mantissa and exponent is achieved with an additional stream of control digits in a multiplier having modules 5. in which the number of modules defines the number of digits in the mantissa and the number of digits in the exponent is arbitrarily greater than one, and wherein the cell structure is arranged to allow both addition and multiplication to be performed in one array of cells 10. by use of a delay circuit for the Y operand, whereby the delay allows the exponent to propagate through the array unchanged in the addition mode and to support the re-ordering of the mantissa digits for the multiply mode. 3. A cellular floating-point serial-pipelined multiplier according to claim 2 in which all cells are identical but cell function is differentiated by signals entering from the output side of the array 5. being caused to propagate a limited distance backward through the cell structure. 4. A cellular floating-point serial-pipelined multiplier according to claim 3 in which the cell link structure is replaced by multiplexers. 5. A cellular floating-point serial-pipelined multiplier according to claim 2 in which function • is controlled by independent MODE and MSB signals arranged so that logic highs are entered from the 5. last cell and propagate a maximum of two cells backward along the array to perform the differentiation of cell function. 6. A cellular floating-point serial-pipelined multiplier according to claim 1 or 2 in which function of the cells is controlled by entering X and Y operands, with the least significant digit first, 5. characterised by an arrangement to enter a control signal in parallel with the data such that it is low only during the entry of the exponent. 7. A serial multiplexed floating-point multiplier according to claim 1 or 2 characterised by feeding the X and Y operands to multiplexers (14 and 15) respect¬ ively, channelling the output from each to a carry-save 5. adder (16) and also to a serial pipelined multiplier (17) channelling the output of the carry-save adder (16) through a delay (19) to a further multiplexer (18) to which multiplexer (18) is also channelled the output of the serial pipelined multiplier (17), 10. and controlling the said multiplexes (14, 15 and 18) and the carry-save adder (16), the delay (19) and the serial pipelined multiplier from a control unit (20) under control of a mode signal. 8. A cellular floating-point multiplier according to claim 1 wherein the format is arranged so that multiplier adders become idle in a pipelined sequence which propagates through the array and the idle adder in 5. _ the last cell is arranged to carry out the exponent addition. .9. A cellular floating-point multiplier according to claim 8 wherein the delay structure supports both mantissa digit re-ordering and exponent delay in a pipe¬ lined arrangement with no guard digits between them and 5. implemented with a minimum number of delay elements. 10. A cellular floating-point serial pipelined multiplier according to claim 1 arranged to accept two synchronous bit-serial NRZ-L streams in two's complement floating-point format and perform a floating-point 5. multiplication. 11. A floating point multiplier constructed substantially as described and illustrated in the accompanying drawings.

Inventors: MARWOOD WARREN, MARWOOD, WARREN
Applicants: COMMW OF AUSTRALIA, THE COMMONWEALTH OF AUSTRALIA CARE OF THE SECRETAR
Application year: 1985
Main classification: G06F7
IPC codes: G06F7