HIGH SPEED CMOS CIRCUITS

Abstract: Integrated circuit chips with two or more multielement logic paths (A, B) can be made to exhibit virtually skew-free operation by setting the sum of the pull-up delays in one path equal to the sum of the pull-up delays in the other and by setting the sum of the pull-down delays in one path equal to the sum in the other. As a result, analog clock systems become feasible, process dependent race conditions are avoided, countdown circuits have reduced sensitivity to parameter fluctuation, and skewless inversions of clock signals are feasible.

Description: HIGH SPEED CMOS CIRCUITS 1. Field of the Invention This invention relates to semiconductor integrated circuits (ICs) and more particularly to complementary-metal-oxide-semiconductor (CMOS) circuits (or bipolar circuits) in which signals are applied to two or more multiple-element paths for interaction at a later time. Background of the Invention CMOS integrated circuit chips including a plurality of multiple-element electrical paths to which signals are applied are well known in the art. A typical example of such an arrangement comprises two paths intended for a pair of clock signals (one being the complement of the other). Each path includes a plurality of inverters connected electrically in a cascaded arrangement. Signals are applied simultaneously to inputs to such paths for later recombination at a clocked gate. Multipath circuits of this type are characterized by delays which cause skew thus reducing the clock rate at which such circuits are capable of operating. In this connection, the term "skew" refers to the actual time of occurrence of a pulse with respect to the expected time of occurrence. At present, the sum of the delays of one path are set to equal the sum of the delays in the other under "worst-case" processing conditions to reduce skew. Setting the total delays of one path equal to the total in the other does not correct for process-induced variations in delays under all conditions. Brief Summary of the Invention This invention is based on the recognition that a significant reduction in skew normally introduced by process variations is achieved by setting the sizes of the inverters in each path so that the sums of the pull-up delays of the elements in the two paths are equal and the sums of the pull-down delays in the two paths are also equal (note that total delays also are equal in this case). The result is a multipath logic circuit relatively free not only of process-induced variations but voltage and temperature-induced variations as well. Devices made in accordance with the teachings of this invention are characterized by field effect transistors (PFETs and NFETs) chosen such that the widths of the PFETs and NFETs in one path are related functionally to the widths of the PFETs and NFETs in the other. In this connection, the term (gate) "length" refers to the length of the current path between a source and drain of a PFET or an NFET and the term (gate) "width" refers to the transverse dimension of the P or N channel region of the PFET or the NFET. Brief Description of the Drawing FIG. 1 is a circuit diagram of a prior art circuit which can be designed in accordance with the principles of this invention; and FIGS. 2 and 3 are graphical representations of the output waveforms of the circuit of FIG. 1 defining the delays of various elements in the circuit. Detailed Description FIG. 1 shows a fragment 10 of a semiconductor chip in which first and second logic paths A and B are shown with three and two inverter logic chains, respectively. The inverters of path A are designated 21, 22, and 23, as shown, and are connected between an internal node Q and the input to a load which may be inverter 24. Similarly, path B includes inverters 31 and 32 connected between node N Q and the input to a load comprising inverter 34. Node Q may comprise a connection to a clockbus of a microprocessor in which case the circuit of FIG. 1 comprises a portion of the input-output (I/O) frame of the microprocessor. It has been found that the signal delays in those paths can be expressed as a product of, basically, two functional terms. One of those terms is 2. function of dimensionless factors determined only by transistor sizes (widths) in the consecutive inverters of the chains of inverters of a pair of multi-element paths. Another of those terms is a function of processing, temperature and voltage dependent parameters. We can express the delays as the sum of two distinct terms because pull-up FETs are always PFETs and pull-down FETs are always NFETs, and because PFETs and NFETs are processed under different conditions yet both contribute to delay. More specifically, it has been realized that processing variations result in uncontrollable changes in the length of the current path between the source and drain (the gate length) of a transistor. Such variations manifest themselves as changes in conductance which determines the delay characteristic of the transistor. By representing the equation for the delay time as a sum of two terms where the first term includes only elements which represent PFETs and the second term includes only elements which represent NFETs, each term may be represented as a product of di ensionless factors and a factor influenced by processing temperature and voltage. If each product term of the delay equations for the two paths are set separately equal to one another, the pull-up and pull-down delays can be specified such that each of the process variable terms in the two equations track one another separately, so that the process variable terms influence those delays in exactly the same way. Actually, because the gate length of a transistor is affected in an uncontrollable manner by processing variations, the only significant factor for achieving essentially zero skew in a pair of circuits is the more controllable gate width and it is the adjustment of that width which provides a control over delay characteristics. Actually, gate length and width are equally affected by processing variations. But gate length is typically one percent of the gate width so that any charge due to processing affects the gate width insignificantly. The delay characteristic of a path including a chain of inverters is derived as follows: Consider an N- . stage chain of inverters and let us represent the size of the P and N field effect transistors (PFETs and NFETs) in the chain in microns as P^ and ^. We will assume (arbitrarily) that the (N + 1)th stage is the load and that the first stage is driven by a low impedance pulse source as is usually the case. For the case where the input voltage makes a low to high transition, the total delay of the chain can be represented as (P 2 +N 2 ) + f ^+N j ) d( +) = N (V DD ■ V THN' ) N« (1) ( if n is an odd number) or P n + 1 +N n + 1 > + f <W u p (V DD _V THP ) n (if n is an even number) where C is a universal proportionality constant, y N and U p are the electron and hole mobilities, and V_ H and V_ H _ are the threshold voltages of the NFETs and PFETs, respectively. The delay for a high to low transition of the input voltage can be written in the same way. The factor f_ in Equation 1 is a dimensionless factor specifying the ratio of drain capacitance to gate capacitance. Accordingly, T. may be represented as T d ( + ) = Q N x R + Q p x R 1 2 ( and) where C C ^ Λ = u U N " 7v V DD -v V THN T and ^p * = u y P~T V vDD ~v V THP T' are the process, temperature and voltage dependent parameters and where "--_. . , R 12 . R 21 and R 22 are dimensionless factors almost independent of these "physical" parameters, the only small dependence coming from factor f_. The delays of two circuits, say circuits A and B of FIG. 1, can be represented as T D (+) A = Q N R 11 (A) + Q P R 12 (A) T D (Ψ) A = Q N R 21 (A) + Q P R 22 (A) (3) and T D (t) B " Q N R 11 (B) + Q P R 12 ( B ) T D (+) B = Q N R 21 (B) + Q P R 22 (B) (4) If the circuits are designed such that R^(A) = R^tB), R 12 (A) -= R 12 (B), R 21 (A) = R 21 (B) and R 22 (A) = R 22 (B), the delays of the two circuits are equal, and also track each other. This result can be seen from Equations 3 and 4 because for the correct choice of transistor sizes, to satisfy conditions R^(A) s R..(B) ...., those terms of Equations 3 and 4 which are process, temperature or voltage dependent track one another exactly. As a consequence, analog clock systems become feasible, process dependent race conditions can be avoided, a countdown circuit will not have much sensitivity to parameter fluctuation, and skewless inversions of clock signals become feasible. The circuit of FIG. 1 supplies a pair of CMOS clock pulses. Nodes N 5 and 3 of FIG. 1 supply a clock pulse and its inversion. The voltage waveforms for nodes N Q -N 5 are shown in FIG. 2. Inversion delays T- j , T 2 , T 3 , T A and T B are also defined in that Figure and in FIG. 3. Prior art circuits of this type are designed so that τ 1+ τ 2+ τ 3 = τ A +τ B (5) for worst-case processing conditions. Consequently, skew is exhibited by prior art circuits made by "better-case" processing conditions. According to the principles of the present invention, the circuit having two paths is configured so that It is clear that in this latter case, the delays due to PFET and NFET devices are separately balanced between the two circuits. Two versions of the circuit of FIG. 1 were designed with the following FET sizes. where P and N are in like units where a unit is 3.75 microns. Version 1 satisfies Equation 5 only; but version 2 satisfies Equation 6 as well. Both versions are skew free at 5.0V supply voltage (V DD ). 1 °5 degrees C skew free at 5.0V supply voltage (V DD ), 105 degrees C and worst-case processing conditions. But version 1 shows skew for the other processing conditions (see table below). The circuit of version 2 does not. The skew parameters for versions 1 and 2 are shown in the following Table: It is clear that all skew can be compensated for by setting the pull-up delays in the two paths equal to one another and the pull-down delays equal to one another.

Claims: Claims 1. An integrated circuit chip including first and second logic circuits to which electrical signals are applied simultaneously, each of said circuits comprising a plurality of logic elements each having a characteristic pull-up and a pull-down delay, the delays of said signal being functions of dimensions which are controllable and dimensions which are not controllable, CHARACTERIZED IN THAT the sum of the pull-down delays of the elements (21-23) in said first circuit equals the sum of the pull-down delays of the elements (31, 32) in said second circuit and the sum of the pull-up delays of the elements in said first circuit equals the sum of the pull- up delays of the elements of said second circuit such that the effect of changes of dimensions in said first and second circuits which are not controllable track one another. 2. An integrated circuit chip in accordance with claim 1 wherein the dimensions which are controllable comprise the widths of said elements in said first and second circuits. 3. An integrated circuit chip in accordance with claim 2 wherein the numbers of elements in said first and second circuits are different. 4. An integrated circuit chip in accordance with claim 3 wherein all said pull-up and all said pull¬ down transistors are formed during first and second processing operations, respectively.

Inventors: SHOJI MASAKAZU, SHOJI, MASAKAZU
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1985
Main classification: H03K5
IPC codes: H01L21, H01L27, H03K5, H03K19