NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING AN IMPROVED WRITE CIRCUIT

Abstract: A non-volatile semiconductor device having an improv­ ed write voltage application circuit is disclosed. The memory device is of the type having a plurality of non-volatile memory elements each coupled to a row line and a column line, a row selection circuit provided for each row line, the row selection circuit providing the row line with a selection potential when the row line is to be selected and a reference potential when the row line is not selected, and a write voltage application circuit provided for each row line for operatively applying a regulated amount of a write cur­ rent to the row line in a write state. The write voltage appli­ cation circuit includes a P-channel MIS transistor which is adapted to take a conductive state of a large resistance at least in a write state, and a current flowing through the above P-channel MIS transistor is derived as the regulated amount of the write current.

Description: Background of the invention The present invention relates to a non-volatile semiconductor memory device according to the preamble part of claim 1. Non-volatile semiconductor memory devices such as Electrically Programmable Read Only Memories (EPROMs), memory contents of which are erasable by ultra-violet ray, have been widely utilized in many kinds of electronic systems. As a memory cell of such EPROMs, an MIS transistor having a stacked gate structure has been mainly employed. The above type MIS transistor has a floating gate located above a channel region via an insulating layer and a control gate located above the floating gate via an insulating layer, the control gate of each MIS transistor is connected to a word line while a drain thereof is connected to a digit line in a matrix form. Memory state of each MIS transistor is corresponded to a value of a threshold voltage which is determined by electric charge accumulated in its floating gate. Upon writing to a memory cell MIS transistor of the above type, potentials at its control gate and drain are raised with its source held at a ground potential so that avalanche breakdown is caused at the drain and hot electrons are injected to the floating gate, whereby a threshold voltage of the memory cell transistor is changed. A conventional write voltage supply circuit for applying a high write voltage V pp to a control gate of a memory cell transistor in writing is comprised of a series circuit of a switching MIS transistor and a current limiting MIS transistor of a depletion type. Through this series circuit, the high write voltage V pp is applied to a control gate of a memory cell MIS transistor to be written. The purpose of using the current limiting MIS transistor is to limit a value of a current flowing the V pp voltage to the ground potential. Such a non-volatile semiconductor memory for example is known from GB-A-2 094 086. This kind of non-volatile semiconductor memory would be described with respect to figure 1 later. However, the current limiting transistor is of a depletion type and therefore, steps in manufacturing the memory is inevitably increased, thus raising cost and reducing yield in manufacturing. In addition, the current limiting transistor must have a relatively large resistance and hence a channel length of the current limiting transistor must be large. This increased a size of a semiconductor chip on which a memory device is fabricated. SUMMARY OF THE INVENTION: It is an object of the present invention to provide a non-volatile memory device which can be easily fabricated. It is another object of the present invention to provide a non-volatile memory device having a large memory capacity and a high density structure. The non-volatile semiconductor memory device according to the present invention as set forth in claim 1 is of the type having a plurality of non-volatile memory cells each coupled to a row line and a column line, a row selection circuit for selecting one of the row lines, electric charges on the non-selected row lines being discharged to a reference potential, and a plurality of write voltage application circuits each provided for each row line to apply thereto a write voltage, and is featured in that the write voltage circuit includes a P-channel MIS transistor which is adapted to assume a shallow conductive state at least in a write state and a current flowing through the above P-channel MIS transistor is applied to the row line. In order to obtain the shallow conductive state of the above P-channel MIS transistor, the gate potential of the P-channel MIS transistor is adjust at the voltage which is lower than the write voltage V pp by 2 to 3 volts. According to the present invention, usage of a depletion MIS transistor in each write voltage application circuit is effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a schematic circuit diagram of a non-volatile memory device according to prior art; Fig. 2 is a schematic circuit diagram showing a major part of a non-volatile memory device according to the present invention; Fig. 3 is a timing chart showing operation of the memory of Fig. 2; Fig. 4 is a schematic circuit diagram showing a practical memory array according to the present invention; and Fig. 5 is a schematic circuit diagram showing a constant voltage generating circuit used in the memory of Figs. 3 and 4. DETAILED DESCRIPTION OF THE INVENTION: Referring to Fig. 1, a major part including a write voltage applying circuit of a non-volatile memory device according to prior art is explained. Although a plurality of memory cells are arranged in a matrix form in a practical product, one memory cell and a writing scheme for this memory cell are illustrated in Fig. 1 for easier understanding. The memory cell transistor M₁₁ is a so-called floating gate MIS transistor. Its floating gate is left unconnected to any circuit line while its control gate is connected to a word line X₁. A source of the transistor is connected to a ground potential while a drain of the transistor M₁₁ is connected to a digit line B₁₁ to which drains of other memory cell transistors in the same column (not shown) are connected. The digit line B₁₁ is connected to a load transistor Q L and an input of an output amplifier 14 through a column selection circuit 13 which is selected by a column selection signal Y i . A row driver circuit 11 is comprised of a P-channel MIS transistor Q₁₁, an N-channel MIS transistor Q₁₂ and an N-channel depletion type MIS transistor Q₁₄ which form and inverter circuit receiving a row decoder signal D₁₁. Throughout the explanation, MIS transistors which are not mentioned as depletion MIS transistors are enhancement MIS transistors. A write voltage supply circuit 12 is composed of an N-channel MIS transistor Q₁₃ and an N-channel depletion MIS transistor Q₁₅ connected in series between a write voltage V pp and the word line X₁. In a write operation for the memory cell transistor M₁₁, a control signal C₁₂ is made high to make the transistor Q₁₃ conductive, while a control signal C₁₁ is rendered low to made the transistors Q₁₄ in high resistance state and the row decoder signal D₁₁ is at high thereby to make the transistor Q₁₂ non-conductive. Therefore, a potential at the word line X₁ is made at nearly the write voltage V pp through the transistors Q₁₃ and Q₁₅. The write voltage V pp is higher than a power voltage V cc . For typical case, V cc is about 5 V and V pp is about 20 V. The column selection circuit 13 connects the digit line to V pp by a selected level of the column decoder signal Y i . Thus, hot-electrons are injected to the floating gate of the transistor M₁₁ to raise the threshold voltage of the transistor M₁₁. In the case where the memory cell transistor M₁₁ is not selected in a write operation, the row decoder signal D₁₁ assumes a low level to render the transistor Q₁₂ conductive so that the potential at the word line X₁ is made nearly the ground potential. In this instance, the transistor Q₁₅ serves as a current limiter for suppressing an electric current flowing to the ground through the transistor Q₁₂ from V pp . However, the transistor Q₁₅ is of a depletion type and hence manufacturing of the memory device has been complexed and prolonged. Furthermore, the transistor Q₁₅ must have a large on-resistance and therefore, the transistor Q₁₅ is required to have a long channel region, causing the enlargement of a chip size. Referring to Fig. 2, a major part of the non-volatile semiconductor memory according to the present invention will be described. Similarly to Fig. 1, one memory cell transistor M₂₁ is representatively illustrated with a write scheme for the memory cell transistor M₂₁. A write voltage circuit 22 is comprised of a P-channel MIS transistor Q₂₄ and a P-channel MIS transistor Q₂₅ connected in series between the write voltage V pp and the word line X₂ connected to the control gate of the cell transistor M₂₁. A word driver circuit 21 includes a CMOS type inverter composed of a P-channel MIS transistor Q₂₁ and an N-channel MIS transistor Q₂₂ receiving a word decoder signal D₂₁. An output of the inverter is coupled to the word line X₂ through a source-drain path of an N-channel MIS transistor Q₂₃ receiving a predetermined potential C₂₁ at its gate. A source of the memory cell transistor M₂₁ is connected to the ground potential while its drain is connected to a digit line B₂₁ which is connected to a common node N₃ of a read-write selection switch SW via a column selection circuit 24 controlled by a digit decoder signal Y i . The switch SW connects the common node N₃ to the write voltage V pp via a contact N₁ in a write state and to a node N₂ to which the power voltage V cc is applied through an N-channel MIS transistor Q₂₆ serving as a load element in a read state. An input of an output amplifier 25 is connected to the node N₂. In this arrangement, the significant feature resides in the write voltage apply circuit 22 made of P-channel MIS transistors Q₂₄ and Q₂₅. A voltage V₀ generated by a voltage generator 23 is applied to the gate of the transistor Q₂₄. This voltage has a value slightly lower than Vpp so that the transistor Q₂₄ assumes a shallow conductive state. In other words, the transistor Q₂₄ takes a conductive state, but its on-resistance is relatively large. Accordingly, the transistor Q₂₄ serves as a current limitter of a current flowing into the ground via the transistor Q₂₂ in a write state. The transistor Q₂₅ serves as a switch and assumes a conductive state in a write operation and a non-conductive state in a read operation in response to a control signal C₂₂. In a write state, the transistor Q₂₃ takes a high impedance and the word line X₂ becomes Vpp which is higher than C₂₁, i.e., Q₂₃ thereby isolates the word line X₂ from V cc . Fig. 5 shows an example of a circuit of the voltage generator 25. A P-channel MIS transistor Q₃₁, an N-channel depletion MIS transistor Q₃₃ and an N-channel MIS transistor Q 34 are connected in series between the write power voltage Vpp and the ground potential. A P-channel MIS transistor Q₃₂ is connected in parallel with the transistor Q₃₁. A control signal C₂₂ of the opposite phase with respect to the control signal C₂₂ is applied to the gates of the transistors Q₃₂ and Q₃₄. In a read state, the control signal C₂₂ assumes the ground potential so that the transistor Q₃₂ takes a conductive state while the transistor Q₃₄ takes a non-conductive state. Accordingly, the output voltage v₀ is approximately equal to Vpp. While in a write state, the control signal C₂₂ assumes a high level close to Vpp so that the transistor Q₃₄ is conductive and the transistor Q₃₂ is non-conductive. As a result, the voltage V₀ takes an intermediate value "Vpp-α" in which α is usually 2 to 3 volts for the case of Vpp = 20 V. Thus, the transistor Q₂₄ of the circuit takes a conductive state in a write state and a non-conductive state in a read state in response to the value of v₀. Fig. 3 shows waveforms in operations of the memory shown in Figs. 2 and 5. T₁ shows a read period in which a period T₁₋₁ shows the case where the memory cell transistor M₂₁ is not selected. During the period T₁₋₁, the row decoder signal D₂₁ is at high to make the transistor Q₂₂ conductive. The potential C₂₁ is kept at V cc throught the whole operation. While the control signal C₂₂ and the voltage V₀ are approximately at Vpp so that the transistors Q₂₄ and Q₂₅ are non-conductive. Accordingly, the word line X₂ is at low in level. A period T₁₋₂ shows the case where the cell transistor M₂₁ is selected in a read cycle. In this instance, the row decoder signal D₂₁ is the ground potential and the transistor Q₂₁ is conducting. While the transistors Q₂₄ and Q₂₅ are still non-conducting. Therefore, the word line X₂ is raised in potential close to V cc via the transistors Q₂₁ and Q₂₃, while the digit line B₂₁ is connected to the node N₂ via the circuit 24, and the switch SW. A write cycle is shown as T₂. A period T₂₋₁ shows the case where the cell transistor is not selected. During the period T₂₋₁, the control signal c₂₂ is approximately at the ground potential and-the voltage v₀ is at the intermediate level of (Vpp-α) so that the transistors Q₂₄ and Q₂₅ are conductive. However, the transistor Q₂₂ is conductive in response to the high level of D₂₁. Therefore, the word line X₂ is made approximately at the ground level through Q₂₂ and Q₂₃. In this instance, although there is a current path from Vpp to the ground level via Q₂₄ and Q₂₅, the transistor Q₂₄ operates to limit the current flowing therethrough. Thus, the potential of the word line X₂ is effectively set at the ground potential and the power consumption due to this current is also reduced. A period T₂₋₂ is the case where the cell transistor M₂₁ is selected. In this instance, the row decoder signal D₂₁ is at the low level to make the transistor Q₂₂ non-conductive and the transistor Q₂₁ conductive. Therefore, the potential of the word line is raised to Vpp via the transistors Q₂₄ and Q₂₅, achieving the selection of the word line x₂. During this period T₂₋₂, Vpp is also applied to the drain of M₂₁ via the circuit 24 and the switch SW. Fig. 4 shows a practical layout where a plurality of memory cell transistors are arranged in a matrix form. In Fig. 4, the portions corresponding to those in Fig. 2 are designated by similar references. Each consecutive four word lines, e.g. X₁₁ to X₁₄ and their word driving schemes are classified into blocks BL l to BL m . Each of the blocks BL l to BL m has the same structure and the block BL l is representatively illustrated. Main row decoders RD l to RD m receiving row address signals a₀ to a i , a₀ to a i provided for the blocks BL l to BL m . Each of the main row decoders RD l to RD m selects its corresponding block, e.g. BL l . For example, the low level of the output D₁ of the decoder RD₁ selects the block BL₁. A NOR type row address driver 21'-1 receives the output D₁ and a sub row decoded signal AX₁ and select the word line when both of D₁ and AX₁ are low. Other row address drivers 21'-2 to 21'-4 have the same structure as 21'-1 except different sub row decoded signals AX₂ , AX₃ and AX₄ are applied. The signals AX₁ to AX₄ are the signals obtained by decoding two bits of row address signals which are not applied to the decoders RD l to RD m . The write voltage apply circuit 23'-1 to 23'-4 are connected between the write voltage Vpp and the word lines X₁₁ to X₁₄ in the block BL₁. The signal C₂₂ and the voltage V₀ are applied to all the write voltage circuits in common. Although not shown in Fig. 4, column selection scheme such as the circuits 24, switch SW, the transistor Q₂₆ and the amplifier 25 in Fig. 2 is provided in a known way. As has been described above, according to the present invention, a non-volatile semiconductor memory having a high density structure can be fabricated without using depletion MIS transistors.

Claims: A non-volatile semiconductor memory device comprising a plurality of row lines (X11-X14), a plurality of column lines (B11-B21), a plurality of non-volatile memory cells (M11-M4m) each coupled to one of said row lines and one of said column lines, a row selection circuit (21, RD1, 21'-1-21'-4) responsive to row address information for selecting one of said row lines, the selected row line being allowed to assume a selection level, potentials at the non-selected row lines being discharged to a reference voltage, and a plurality of write voltage application circuits (22, 23'-1-23'-4) each coupled to each one of said row lines for applying a write voltage (Vpp) thereto in a write state, each of said write voltage application circuits including a current limiting MIS transistor (Q24) adapted to take a shallow conductive state and means (Q25) for connecting a source-drain path of said current limiting transistor between said row line and said write voltage, characterized in that said current limiting transistor is of an enhancement type. The memory device according to claim 1, characterized in that said current limiting transistor (Q24) is a first P-channel MIS transistor and a gate of said first P-channel transistor is supplied with a potential which is lower than said write voltage (Vpp). The memory device according to claim 1 or 2, characterized in that said connecting means includes a switching MIS transistor (Q25) having a source-drain path connected in series with the source-drain path of said current limiting transistor (Q24), and that said switching transistor is rendered conductive in a write state and non-conductive in a read state. The memory device according to any of claims 1 to 3, characterized in that said row selection circuit includes a plurality of driver circuits (21'-1 to 21'-4) each provided for each one of said row lines and a plurality of connecting MIS transistors (Q23) each coupled between the output of one of said driver circuits and one of said row lines. The memory device according to any of claims 1 to 4, characterized in that each of said memory cells (M11-M4m) includes a floating gate type MIS transistor having a floating gate and a control gate connected to one of said row lines.

Inventors: HIGUCHI, MISAO
Applicants: NEC CORPORATION
Application year: 1985
Main classification: G11C16
IPC codes: G11C16, G11C17