QUARTERNARY DIFFERENTIAL PSK DEMODULATOR

Abstract: In a quarternary differential PSK demodulator, a QPSK input signal is applied to first and second synchronous de­ tectors to which carriers with a 90-degree phase difference therebetween are respectively applied from a voltage-con­ trolled oscillator. A first double-balanced phase detector multiplies the outputs from the synchronous detectors. A second phase detector squares the output of the second synchronous detector. A third double-balanced phase de­ tector provides multiplication of the outputs of the first and second double-balanced phase detector to generate an out­ put having four times the frequency of the outputs of syn­ chronous detectors to cancel the information carried by the input PSK signal. A loop filter converts the output of the third phase detector to a DC phase control signal to be applied the voltage-controlled oscillator.

Description: The present invention relates to a quaternary differential phase shift keying demodulator according to the preamble of claim 1. A quaternary differential phase shift keying demodulator of that kind is known from US-A-4 336 500 . In this prior art document there is disclosed a quaternary differential phase shift keying or PSK demodulator which is comprising an input terminal and two output terminals, a demodulating means in the form of two multipliers and two filters, which means is responsive to an input signal S(t) applied to the input terminal and which is generating two output signals X i and X q being extracted from the input signal. Furthermore there are provided a variable frequency oscillator and a 90-degree phase shifter (hybrid circuit) for generating carrier frequency tracking signals which are applied to the demodulating means. An input signal in the form of a phase control signal is generated and fed back by a closed loop means which mainly consists of four multipliers, one adder, one subtractor and two networks. This known PSK demodulator suffers from the drawback that it will exhibit poor stability when being operated at frequencies higher than about 1 Megahertz. Another, even more important disadvantage lies therein that this known PSK demodulator is not free from temperature-dependant DC drift problems which affect the stability of the a.m. closed loop means; consequently, the quality of the demodulated output signals is deteriorated by changes in temperature. It therefore is the object of the present invention to improve a quaternary differential phase shift keying demodulator according to the preamble of claim 1 in such a way that it is exhibiting excellent output signal quality at high frequencies and irrespective of changes in temperature. According to the present invention this object is achieved by the advantageous measures as indicated in the characterizing portion of claim 1. By the provision of synchronous detectors in the demodulating means and by the further provision of four double-balanced phase detectors in the closed loop means it is possible to obtain a very high stability even then when the PSK demodulator is operated at very high frequencies above of 1 Megaherz. As a consequence, the demodulated output signals exhibit an excellent signal quality even at these high frequencies. When ambient temperature varies, the output signals of all four double-balanced phase detectors are affected in the same way. If these output signals would be processed by means of one adder and one subtractor - as it is the case in the PSK demodulator known from US-A-4 336 500 - a resultant output signal from the subtractor is not affected by temperature change due to subtraction of respective offset values; the resultant output signal from the adder, however, even exhibits a doubled offset value due to temperature change. Consequently, the phase control signal fed back to the VCO would be significantly changed so that the quality of the demodulated ouput signals is deteriorated. According to the advantageous measures as indicated in new claim 1 there are provided, however, two subtractors so that, in combination with the further provision of one inverted phase detector input signal temperature offset values are compensated completely; as a result, the phase control signal fed back to the VCO remains unchanged even at great temperature changes so that the quality of the demodulated ouput signals is always excellent. A further advantage of this excellent temperature compensation results in a simple implementation of the PSK demodulator in integrated circuits. Further advantageous features of the invention are subject matter of the subclaims. In the following the invention will be described in more detail with reference to the accompanying drawings in which: Fig .1 is a block diagram for explaining the function of a PSK demodulator; Fig. 2 is a block diagram of an embodiment of the invention; Fig. 3 is a waveform diagram associated with the Fig. 2 embodiment; Fig. 4 is a block diagram of a modified embodiment of the invention; and Fig. 5 is a waveform diagram associated with the modified embodiment. Referring now to Fig. 1, a quarternary differential PSK signal is applied through an input terminal 1 to the first inputs of synchronous detectors 2 and 3. A carrier is generated by a voltage-controlled oscillator 5 and applied to the second input of synchronous detector 2 and via a 90-degree phase shifter 4 to the second input of synchronous detector 3. The outputs of synchronous detectors 2 and 3 are passed through low-pass filters 6 and 7, respectively, to remove the carrier components which remains after the synchronous detection. The outputs of low-pass filters 6 and 7 are multiplied by a double-balanced phase detector 9 and fed to one input of a double-balanced phase detector 10. The output of low-pass filter 7 is squared by a double-balanced phase detector 9 and fed to the second input of double-balanced phase detector 10, the output of which is converted to a DC phase control signal by a loop filter 11 and fed to voltage-controlled oscillator 5. The output signals of the demodulator are withdrawn from terminals 40 and 41 coupled to the outputs of low-pass filters 6 and 7. The input signal at terminal 1 is represented by A2 cos (ωt + ) and the carrier from oscilaltor 5 A1 cos ωt (where  represents each of the phase values of the QPSK input signal, that is 0, π/2, π, 3π/2). Then, the output of low-pass filter 6 is given by (A1·A2 cos )/2 and the output of low-pass filter 7 is expressed by (A1·A2 sin )/2. The double-balanced phase detector 8 provides multiplication operation on the signal (A1·A2 cos )/2 from low-pass filer 6 and the signal (A1·A2 sin )/2 from low-pass filter 7 and provides a product signal having a phase sin 2 to the double-balanced phase detector 10. The double-balanced phase detector 9 provides a squaring operation on the signal (A1·A2 sin )/2 from filter 7 so that it provides a product having a phase -cos 2 to the double-balanced phase detector 10. The input signals sin 2 and -cos 2 to the double-balanced phase detector 10 are multiplied to derive an output signal -sin 4. Because of the quadrupled phase, the original phase information or modulating signal component is canceled in the phase detector 10. Phase error components synchronously detected by phase detectors 2 and 3 are thus derived from loop filter 11. Carriers supplied to synchronous detectors 2 and 3 are thus maintained in a definite phase relation with the original carrier. The double-balanced phase detectors operate successfully at frequencies higher than 1 Megaherz. An embodiment of the invention is shown in Fig. 2. A carrier-suppressed QPSK signal received at terminal 12 is applied to synchronous detectors 13 and 14. A second input signal to synchronous detector 13 is supplied from a voltage-controlled oscillator 16 and a second input to synchronous detector 14 is supplied from oscillator 16 via a 90-degree phase shifter 15. After synchronous detection, the outputs of synchronous detectors 13 and 14 are fed to carrier-rejection low-pass filters 17 and 18, respectively, to derive signals shown at a and b in Fig. 3. The outputs of filters 17 and 18 are coupled to the input terminals of a double-balanced phase detector 20 to generate an output signal shown at c, Fig. 3, which is representative of the product of the instantaneous values of the filter outputs. The output of filter 18 is coupled via inverter 24 to one input of a double-balanced phase detector 21 which receives a second input from the filter 17 to derive an output signal d, Fig. 3. The output of low-pass filter 18 is applied to input terminals of a double-balanced phase detector 22 to square the instantaneous value of the input signal to derive a signal f, Fig. 3. Similarly, the output of filter 17 is squared by a double-balanced phase detector 23 to derive an output signal g, Fig. 3. The waveform d is subtracted from the waveform c in a subtractor 25. The result is a generation of substantially rectangular pulses e which are fed to a comparator 27 to provide sharply defined rectangular pulses i having a repetition frequency twice the frequency of the outputs of low-pass filters 17, 18. Likewise, the waveform g is subtracted from the waveform f by a subtractor 26 to develop substantially triangular pulses h which are fed to a comparator 28 to generate rectangular pulses j having a repetition frequency twice the frequency of the outputs of low-pass filters 17, 18 with a phase difference of 90 degrees with respect to the output of comparator 27. The outputs of comparators 27 and 28 are supplied to an Exclusive-OR gate 29. The waveform shown at k represents the output of Exclusive-OR gate 29 which varies at a frequency four times higher than the frequencies of the outputs of low-pass filters 17, 18. Since the input PSK signal is at one of four phase values 0, π/2, π, 3π/2 radians, these phase values are converted by Exclusive-OR gate 29 to 0, 2π, 4π and 6π radians, respectively, thereby canceling the original modulating signal. The output of Exclusive-OR gate 26 thus exclusively contains a component representative of the phase errors detected by the synchronous detectors 13 and 14. The output of Exclusive-OR gate 29 is filtered by a loop filter 30 to extract the phase error component from the output of Exclusive-OR gate 26 and develop a DC phase control signal having a magnitude and polarity determined by the magnitude and direction, respectively, of the phase difference between the original carrier and the local carrier from oscillator 16. The phase control signal is applied to voltage-controlled oscillator 16 to maintain a definite phase relation between the two carriers. Because of the double-balanced structure, each of the output waveforms of phase detectors 20 to 23 is symmetrical with respect to zero voltage level. A further feature of the invention lies in the fact that undesirable DC drifts which occur with a temperature variation in phase detectors 20 and 21 are canceled by subtractor 25 and those in phase detectors 22 and 23 are cancelled by subtractor 26. The elimination of DC drifts allows the PSK demodulator to be implemented in integrated circuits. Terminals 40 and 41 are respectively coupled to the outputs of low-pass filters 17 and 18 to extract demodulator output signals. Quarternary ifferential outputs will be derived from the demodulator outputs in a circuit, not shown, by taking the difference between preceding and succeeding phase components. The differential outputs will then be translated into (0, 0), (0, 1), (1, 1) and (1, 0) which are interpreted as 0, π/2, π and 3π/2 radians, respectively. Fig. 4 is a modification of the PSK demodulator in which parts corresponding to those in Fig. 2 are marked by the same numerals as used in Fig. 2. In this modification, the output signal e of subtractor 25 is supplied to one input of a double-balanced phase detector 31 and through an inverter 32 to one input of a double-balanced phase detector 33, and the output signla h of subtractor 26 is supplied to the other inputs of double-balanced phase detectors 31 and 33. Therefore, the waveforms e and h are multiplied by phase detector 31 to derive a sawtooth wave which is a train of pulses with a nonlinearly varying amplitudes as shown at ℓ in Fig. 4 and the inverted waveform e and waveform h are multiplied to derive a sawtooth wave m which is a train of pulses having amplitudes nonlinearly varying in a direction opposite to the waveform ℓ. It is seen that these nonlinear sawtooth waves vary at a frequency four times higher than the outputs a and b of low-pass filters 17 and 18. The sawtooth wave m is subtracted from the sawtoothw wave ℓ in a subtractor 34 to produce sawtooth wave pulses n which are applied to loop filter 30. The sawtooth wave pulses n have a linearly varying amplitude having twice the amplitude of waveform ℓ.

Claims: A quaternary differential phase shift keying (PSK) demodulator comprising: [A] an input terminal (12) and two output terminals (40,41) ; [B] a demodulating means (13,14,17,18) responsive to an input signal applied to said input terminal (12) and generating two output signals (a,b) extracted from said input signal, each signal being supplied to one of said output terminals (40,41) ; [C] a variable frequency oscillator (16) and a 90-degree phase shifter (15) for generating carrier frequency tracking signals being applied to said demodulating means (13,14,17,18) ; and [D] closed loop means (20-30) responsive to said two output signals (a,b) for generating a phase control signal fed back to an input of said variable frequency oscillator (16) ; characterized in that [E] said demodulating means comprises first and second synchronous detectors (13,14) ; and in that said closed loop means comprises [F1] four double-balanced phase detectors (20-23) each having two input terminals and producing one output signal which is a product of signals applied to said input terminals, wherein [F2] a first double-balanced phase detector (20) receives said two output signals (a,b) , [F3] a second double-balanced phase detector (21) receives said first output signal (a) and said second output signal the polarity of which being inverted (-b) , and wherein [F4] third and fourth double-balanced phase detectors (22,23) each receive only said first (a) and respectively said second output signal (b) at both input terminals; [G] two subtractors (25,26) each responsive to said output signals (c,d,e,f) of said first and second (20,21) respectively of said third and fourth double-balanced phase detectors (22,23) and generating a difference signal (e,h) ; [H] and means (27-30) responsive to said two difference signals (e,f) for providing said phase control signal. A demodulator according to claim 1, characterized in that said means responsive to said two difference signals comprises [A] means (27) for shaping the waveform of said first difference signal (e) into rectangular pulses of a first train; [B] means (27) for shaping the waveform of said second difference signal (f) into rectangular pulses of a second train; [c] and an Exclusive-Or gate (29) responsive to said first and second pulse trains and providing output pulses (k) to a loop filter (30) . A demodulator according to claim 1, characterized in that said means responsive to said two difference signals comprises [A] a fifth double-balanced phase detector (31) responsive to said first and second difference signals (e, f) , respectively, for generating an output signal representative of a product of said difference signals (e, f) ; [B] a sixth double-balanced phase detector (33) responsive to a signal which is an inverted signal of said first difference signal (e) and responsive to said second difference signal (f) for generating an output signal representative of a product of said inverted first difference signal (e) and said second difference signal (f) ; [c] and a third subtractor (34) responsive to said output signals of said fifth and sixth double-balanced phase detectors (31, 33) for providing an output signal representative of a difference in magnitude between said fifth and sixth double-balanced phase detector output signals to a loop filter (30) . A demodulator according to one of claims 1 to 3, characterized by [A] a first low-pass filter (17) connected to an output terminal of said first synchronous detector (13) for rejecting carrier components and for applying a first filter output signal to said first, second and fourth double-balanced phase detectors (20, 21, 23) ; [B] and a second low-pass filter (18) connected to an output terminal of said second synchronous detector (14) for rejecting carrier components and for applying a second filter output signal to said first, second and third double-balanced phase detectors (20, 21, 22) .

Inventors: HIROHASHI, KAZUTOSHI, ISHIGAKI, YUKINOBU
Applicants: VICTOR COMPANY OF JAPAN, LIMITED
Application year: 1985
Main classification: H04L27
IPC codes: H04L27