DATA I/O CIRCUIT WITH HIGHER INTEGRATION DENSITY FOR DRAM

Abstract: A data input/output circuit operates in an operation cycle in which, when a first latch circuit connected to a first data bus issues 1-bit information to a data output buffer, next 1-bit information is latched in a second latch circuit connected to a second data bus and simultaneously the first data bus is precharged, and in an operation cycle in which, when 1-bit data stored in the second latch circuit is issued to the data output buffer, next 1-bit data is latched in the first latch circuit and simultaneously the second data bus is precharged. Therefore, when one of the latch circuits issues data to the data output buffer, the other latch circuit latches data and is in a standby condition. An access time in which to issue data from bit lines to the data buses is greatly reduced notwith­ standing that only two data buses are employed. According­ ly, the chip area occupied by the data buses can be reduced appreciably.

Description: BACKGROUND OF THE INVENTION The present invention relates to a data input/output circuit operable in a multibit mode, suitable for a MOS dynamic RAM. One method for shortening an access time of semiconductor DRAM ICs is to use a data input/output circuit operable in a multibit mode, e.g., a 4-bit (nibble) mode. When a memory address is specified once, the input/output circuit can transfer 4-bit data serially at a high speed from a memory cell to a data output buffer or from a data output buffer to a memory cell. Conventional data input/output circuits operating in the nibble mode are disclosed in, for example, "A 100 ns 256 K DRAM with Page-Nibble Mode" by K. Shimotori et al., ISSCC DIGEST OF TECHNICAL PAPERS, P228 - 229; Feb., 1983, and "A sub 100 ns 256Kb DRAM" by T. Nakano et al., ISSCC DIGEST OF TECHNICAL PAPERS, P224 - 225; Feb., 1983. The conventional data input/output circuits operate in a readout mode to transfer four bits of information from four bit lines to four data buses at a time, the four bits of information being amplified and latched respectively in four latch circuits. Then, the four bits of information are transferred one bit by one bit serially from the latch circuits to a data output buffer. After all data of the four data buses have been transmitted to a data output circuit, next 4-bit information is transferred to the data buses. With the prior nibble-mode data input/output circuit, however, while data is being issued from one latch circuit, the other latch circuits are kept simply in a standby condition. Therefore, the operation efficiency of the data buses and the latch circuits is not high. In particular, where a plurality of such prior data input/output circuits are employed to issue pieces of serial information in a parallel manner to a plurality of data output terminals, there are required as many data buses, precharge circuits, and latch circuits as a multiple of the data output terminals, and the area taken up by the data input/output circuits is greatly increased. For these reasons, it has been difficult to fabricate high-capacity DRAM IC devices. The conventional circuit arrangement has also been disadvantageous in that when multibit (four bits or more) data is to be accessed serially through the data output terminals, it is necessary to increase the number of data buses by the number of bits, with the result that the area occupied by the data buses makes it difficult to provide higher-density integration on semiconductor memory IC chips. It is an object of the present invention to provide a data input/output circuit with high integration density,operable in a multibit mode. Another object of the present invention is to provide a data input/output circuit capable of accessing at a high speed N-bit serial data through two data buses. The objects of the invention are achieved by the features of Claim 1. The objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of illustrative example. FIG. 1 is a circuit diagram, partly in block form, of a MOS DRAM IC including a data input/output circuit operable in a nibble mode according to the present invention; FIG. 2 is a timing chart of control signals in a readout mode of the memory circuit shown in FIG. 1; FIG. 3 is a timing chart of control signals in a write mode of the memory circuit shown in FIG. 1; and FIG. 4 is a set of data-flow diagrams illustrating data paths in the readout mode of the data input/output circuit of the present invention. FIG. 1 shows a MOS DRAM circuit including a data input/output circuit operable in a nibble mode according to the present invention. As shown in FIG. 1, the MOS DRAM circuit includes a memory array 100, an X decoder 102 responsive to a strobe signal RAS for receiving an X address signal to select one of word lines W L of the memory array 100, a plurality of sense amplifiers 104 for amplifying signals from bit lines B L of the memory array 100, a timing generator circuit 106 responsive to a strobe signal CAS for receiving a Y address signal to issue control signals ₁ through ₁₀,and a data input/output circut 108 to control the transmission of data (information) between data input/output terminals and the bit lines B L . The timing generator circuit 106 includes a Y address decoder for generating timing signals ₃ through ₆. The memory array 100 comprises a plurality of memory cells each composed of a switching MOS transistor Q and a memory capacitor C. The data input/output circuit 108 includes a data bus 110 composed of a pair of conductors, switch circuits 114, 118 for selectively coupling the bit lines B L1 , B L1 , B L3 , B L3 with the data bus 110 and controlled by the control signals ₃ and ₅, a data bus 112 composed of a pair of conductors, and switch circuits 116, 120 for selectively coupling the bit lines B L2 , B L2 , B L4 , B L4 with the data bus 112 and controlled by the control signals ₄ and ₆. Each of these switch circuits 114, 116,118,120 is composed of MOS transistors. The data input/output circuit 108 further includes a latch circuit 122 responsive to the control signal ₉ for amplifying and latching data of the data bus 110, a latch circuit 124 responsive to the control signal ₁₀ for amplifying and latching data of the data bus 112, a switch circuit 126 responsive to the control signal ₇ for issuing the data of the data bus 110, a switch circuit 128 responsive to the control signal ₈ for issuing the data of the data bus 112, and a data output buffer 130 responsive to an "H"-level write enable signal WE for issuing one of complementary signals from the data bus 110 or one of complementary signals from the data bus 112 to a data output terminal 132. The switch circuits 126, 128 are composed of MOS transistors Q₁₃, Q₁₄ and Q₁₅, Q₁₆, respectively. The data input/output circuit 108 also includes a switch circuit 134 connected to the data bus 110 and controlled by the control signal ₇, a switch circuit 136 connected to the data bus 112 and controlled by the control signal ₈, a data input buffer 138 responsive to an "L"-level write enable signal WE for converting data from a data input terminal 140 into complementary signals and transmitting these complementary signals to the switch circuit 134 or 136, a precharge circuit 142 for charging the data bus 110 up to a power supply potential V DD in response to the control signal ₁, and a precharge circuit 144 for charging the data bus 112 up to the power supply potential V DD in response to the control signal ₂. The switch circuits 134, 136 are composed of MOS transistors Q₁₇, Q₁₈ and Q₁₉, Q₂₀, respectively. The precharge circuits 142, 144 are composed of MOS transistors Q₁, Q₂ and Q₃, Q₄, respectively. Operation of the data input/output circuit according to the present invention will be described with reference to the timing diagrams of FIGS. 2 and 3. Readout mode : As shown in FIG. 2, when the control signals ₁, ₂ are of an "H" level, the MOS transistors Q₁, Q₂, Q₃, Q₄ are rendered conductive to charge the data buses 110, 112 to the power supply potential V DD . Since the write enable signal WE is of the "H" level at this time, the data output buffer 130 is enabled and the data input buffer 138 is disenabled. When the strobe signal RAS changes from the "H" level to the "L" level during a period t₀, the X address circuit 102 receives the X address signal to select the word line W L1 , for example. At the same time, the sense amplifiers 104 detect and amplify data from the bit lines B L , respectively. When the strobe signal CAS changes from the "H" level to the "L" level during a next period t₁, the Y address signal is applied to the timing generator circuit 106. The control signal ₇ is now caused to change from the "L" level to the "H" level to render the MOS transistors Q₁₃, Q₁₄ conductive. As the control signal ₈ is of the "L" level, the MOS transistors Q₁₅, Q₁₆ remain nonconductive. During a period t₂, the control signals ₁, ₂ change from the "H" level to the "L" level to render the MOS transistors Q₁ through Q₄ nonconductive. The control signals ₃, ₄ change from the "L" level to the "H" level to render the transistors Q₅, Q₆, Q₇, Q₈ conductive, to thereby transmit information from the bit lines BL₁, BL₁ and BL₂, BL₂ to the data buses 110, 112, respectively. The control signals ₅, ₆ are kept in the "L" level to maintain the transistors Q₉ through Q₁₂ non-conductive. The data buses 110, 112 are therefore disconnected from the bit lines BL₃, BL₃ and BL₄, BL₄ , respectively. Since the control signals ₉, ₁₀ change from the "L" level to the "H" level, the latch circuits 122, 124 are activated to latch and amplify the data from the data buses 110, 112. At this time, the transistors Q₃, Q₄ are energized, and the data from the data bus 110 is issued through the data output buffer 130 to the data output terminal 132 (see a in FIG. 2(O)). When the strobe signal CAS changes from the "L" level to the "H" level during a period t₃, the transistors Q₅, Q₆ are de-energized. Since the control signal ₁ changes from the "L" level to the "H" level, the transistors Q₁, Q₂ are energized to precharge the data bus 110. As the control signal ₉ goes from the "H" level to the "L" level, the latch circuit 122 is reset and an output of the data output buffer 130 becomes a high-impedance condition. When the strobe signal CAS goes from the "H" level to the "L" level during a period t₄, the control signal ₇ changes from the "H" level to the "L" level, and the control signal ₈ changes from the "L" level to the "H" level. Therefore, the data from the data bus 122 is issued through the data output buffer 130 to the data output terminal 132 (see b in FIG. 2(O)). Inasmuch as the control signal ₁ changes from the "H" level to the "L" level, the transistors Q₁, Q₂ are de-energized. The control signal ₅ changes from the "L" level to the "H" level, so that the transistors Q₉, Q₁₀ are energized to transfer the data from the bit lines B L3 , B L3 to the data bus 110. The control signal ₉ changes from the "L" level to the "H" level, activating the latch circuit 122 to latch and amplify the data of the data bus 110. In a period t₅, the strobe signal CAS goes from the "L" level to the "H" level and the control signal ₂ goes from the "L" level to the "H" level, whereupon the transistors Q₃, Q₄ are energized to precharge the data bus 112. Since the control signal ₄ changes from the "H" level to the "L" level to de-energize the transistors Q₇, Q₈, the bit lines B L2 , B L2 are disconnected from the data bus 112. As the control signal ₁₀ goes from the "H" level to the "L" level, the latch circuit 124 is reset. The control signal ₇ changes from the "L" level to the "H" level and the control signal ₈ changes from the "H" level to the "L" level during a period t₆, with the result that the data from the data bus 110 is issued via the data output buffer 130 to the data output terminal 132 (see c in FIG. 2(O)). Since the control signal ₆ changes from the "L" level to the "H" level the transistors Q₁₁, Q₁₂ are energized to transfer the data from the bit lines B L4 , B L4 to the data bus 112. When the control signal ₁₀ changes from the "L" level to the "H" level, the latch circuit 124 is activated to latch and amplify the data of the data bus 112. Likewise, the data items from the data buses 110, 112 are alternately and serially issued to the data output terminal 132 by the control signals ₃, ₄, ₅, ₆ and ₉, ₁₀. FIG. 4 shows flow diagrams of data flow in the readout mode of the data input/output circuit according to the present invention. Write mode : A write mode of the data input/output circuit of the present invention will be described with reference to FIG. 3. First, an "L"-level write enable signal WE is applied to disenable the data output buffer 130 and enable the data input buffer 138. When the strobe signal RAS goes from the "H" level to the "L" level during a period t₇, the X address circuit 102 receives an X address signal to select the word line W L1 , for example. At the same time, the sense amplifiers 104 detect and amplify data of the bit lines B L , respectively. When the strobe signal CAS changes from the "H" level to the "L" level during a period t₈, a Y address signal is impressed on the timing generator circuit 106. The control signal ₇ is now caused to change from the "L" level to the "H" level to thereby energize the MOS transistors Q₁₇, Q₁₈. Since the control signal ₈ is of the "L" level, the MOS transistors Q₁₉, Q₂₀ remain de-energized. A 1-bit signal applied to the data input terminal 140 is introduced into the data input buffer 138 which issues complementary signals (see e in FIG. 3(E)). Since the control signal ₇ goes from the "L" level to the "H" level at this time, the transistors Q₁₇, Q₁₈ are energized to connect the data input buffer 138 to the data bus 110. In a period t₉, the control signals ₁, ₂ change from the "H" level to the "L" level to de-energize the transistors Q₁, Q₂, Q₃, Q₄ for thereby interrupting the precharging of the data buses 110, 112. Since the control signals ₃, ₄ go from the "L" level to the "H" level, the bit lines B L1 , B L1 are connected to the data bus 110, and the bit lines B L2 , B L2 are connected to the data bus 112. Because the control signal ₉ is of the "L" level, the latch circuit 122 is disenabled. The control signal ₁₀ goes from the "L" level to the "H" level, the latch circuit 124 amplifies the data of the data bus 112 and refreshes information in the memory capacitor C₂₁ of the bit lines B L2 , B L2 . Simultaneously, the information to be written is delivered from the data input buffer 138 onto the data bus 110 and then written in the memory cell C₁₁ of the bit lines B L1 , B L1 . During a next period t₁₀, the strobe signal CAS varies from the "L" level to the "H" level and the control signal ₁ goes from the "L" level to the "H" level. The transistors Q₁, Q₂ are now energized to precharge the data bus 110 to the power supply potential. At the same time, the control signal ₃ changes from the "H" level to the "L" level to de-energize the transistors Q₅, Q₆ thus disconnecting the bit lines B L1 , B L1 from the data bus 110. During a period t₁₁, the strobe signal CAS varies from the "H" level to the "L" level and the control signal ₁ goes from the "H" level to the "L" level, thereby interrupting the precharging of the data bus 110. The data is then introduced from the data input terminal 140 into the data input buffer 138 (see f in FIG. 3(E)). The control signal ₇ goes from the "H" level to the "L" level to de-energize the transistors Q₁₇, Q₁₈, and simultaneously the control signal ₈ goes from the "L" level to the "H" level to energize the transistors Q₁₉, Q₂₀. The data from the data input buffer 138 is then delivered to the data bus 112. Since the control signal ₁₀ goes from the "H" level to the "L" level, the latch circuit 124 is disenabled. The control signal ₄ is of the "H" level for thereby writing the data of the data bus 112 in the memory cell C₂₁. The control signal ₅ changes from the "L" level to the "H" level to energize the transistors Q₉, Q₁₀ for transferring information from the bit lines B L3 , B L3 to the data bus 110. Inasmuch as the control signal ₉ goes from the "L" level to the "H" level, the latch circuit 122 is activated to latch and amplify the information on the data bus 110 and refresh information in the memory capacitor C₃₁. The control signal ₄ changes from the "H" level to the "L" level to de-energize the transistors Q₇, Q₈; the control signal ₂ goes to the "H" level to precharge the data bus 112; both during a period t₁₂. During a period t₁₃, the strobe signal CAS goes from the "H" level to the "L" level to introduce next data from the data input terminal 140 into the data input buffer 138 (see g in FIG. 3(E)). The control signal ₇ goes from the "L" level to the "H" level to energize the transistors Q₁₇, Q₁₈, and simultaneously the control signal ₈ goes from the "H" level to the "L" level to de-energize the transistors Q₁₉, Q₂₀. The data from the data input buffer 138 is then delivered to the data bus 110. Since the control signal ₅ is of the "H" level at this time, data from the data bus 110 is written into the memory capacitor C₃₁ of the bit lines B L3 , B L3 . The transistors Q₃, Q₄ are de-energized since the control signal ₂ goes from the "H" level to the "L" level. The control signal ₆ changes from the "L" level to the "H" level to energize the transistors Q₁₁, Q₁₂, thereby transferring data from the bit lines B L4 , B L4 to the data bus 112. As the control signal ₁₀ goes from the "L" level to the "H" level, the latch circuit 124 is activated to latch and amplify the information on the data bus 112 and refresh information in the memory capacitor C₄₁. Likewise, data items applied to the data input terminal 140 are transferred alternately to the data buses 110, 112 and written into memory cells. As described above, where data readout in response to a single addressing operation is to be carried out under timesharing control, the data input/output circuit of the present invention operates in an operation cycle in which, when the first latch circuit connected to the first data bus issues 1-bit information to the data output buffer, next 1-bit information is latched in the second latch circuit connected to the second data bus and simultaneously the first data bus is precharged, and in an operation cycle in which, when 1-bit data stored in the second latch circuit is issued to the data output buffer, next 1-bit data is latched in the first latch circuit and simultaneously the second data bus is precharged. Therefore, the data input/output circuit is advantageous in that, when one of the latch circuits issues data to the data output buffer, the other latch circuit latches data and is in a standby condition, and hence an access time in which to issue data from the bit lines to the data buses is greatly reduced notwithstanding the only two data buses are employed. Accordingly, the chip area occupied by the data buses can be reduced appreciably. The data input/output circuit according to the present invention is highly effective when used with large-capacity semiconductor DRAM IC devices. The data input/output circuit is conducive to miniaturization of IC chips since the number of required data buses can be greatly lowered when issuing serial data from each of a plurality of I/O buffers. Further, even if the number of bit lines connected to the two data buses is increased to increase the number of bits of serial data, a large-capacity, high-speed DRAM IC device can be realized according to the present invention without involving an increase in the number of data buses, through timing control of the switch means precharge means, and latch circuits between the bit lines and the data buses. Although a certain preferred embodiment has been shown and described, it should be understood that many changes and modifications may be made therein without departing from the scope of the appended claims.

Claims: A data bus input/output circuit for serially accessing N-bit data in a DRAM circuit, comprising: (a) a first data bus (110) having a pair of conductors for transferring data; (b) a second data bus (112) having a pair of conductors for transferring data; (c) a first precharge circuit (142) for charging said first data bus; (d) a second precharge circuit (144) for charging said second data bus; (e) a first group of complementary bit line pairs (BL₁, BL ₁, BL₃, BL ₃); (f) a second group of complementary bit line pairs (BL₂, BL ₂, BL₄, BL ₄); (g) a first group of N switches (Q₅, Q₆, Q₉, Q₁₀) coupling the first group of complementary bit line pairs (BL₁, BL ₁, BL₃, BL ₃) to the first data bus (110), for transferring 1-bit information to said first data bus (110) in response to first timing control signals (3, 5) each corresponding to one of the complementary bit line pairs of said first group; (h) a second group of N switches (Q₇, Q₈, Q₁₁, Q₁₂) coupling the second group of complementary bit line pairs (BL₂, BL ₂, BL₄, BL ₄) to the second data bus (112), for transferring 1-bit information to said second data bus (112) in response to second timing control signals (4, 6) each corresponding to one of the complementary bit line pairs of said second group; (i) a first latch circuit (122) for latching and amplifying the information on said first data bus (110); (j) a second latch circuit (124) for latching and amplifying the information on said second data bus (112); (k) first output switch means (126) for outputting the information through the first latch (122) in response to a third timing signal (7); (l) second output switch means (128) for outputting the information through the second latch (124) in response to a fourth timing signal (8); (m) a data output buffer (130) for receiving and outputting the information from the first and second output switch means (126, 128) under the control of one logic level of an enable signal; (n) a timing signal generator (106) for generating the first, second, third and fourth timing control signals (3, 5; 4, 6; 7; 8); the third and fourth timing control signals (7, 8) being generated alternately, one of the first timing control signals (3, 5) being generated when the fourth timing control signal (8) is generated, one of the second timing control signals (4, 6) being generated when the third timing control signal (7) is generated. A data bus input/output circuit according to claim 1, wherein the first precharge circuit (142) is activated in response to a fifth timing control signal (1) and the second precharge circuit (144) is activated in response to sixth timing control signal (2); and wherein the timing signal generator (106) further generates the fifth and sixth timing control signals (1, 2), the fifth timing control signal (1) being generated in advance of the generation of the first timing control signals (3, 5), the sixth timing control signal (2) being generated in advance of the generation of the second timing control signals (4, 6). A data bus input/output circuit according to claim 1 or 2, wherein the first latch circuit (122) is activated in response to a seventh timing control signal (9) and the second latch circuit (124) is activated in response to an eighth timing control signal (10); and wherein the timing signal generator (106) further generates the seventh and eighth timing control signals (9, 10), the seventh timing control signal (9) being generated when the first timing control signal (3, 5) is generated, the eighth timing control signal (10) being generated when the second timing control signal (4, 6) is generated. A data input/output circuit according to claim 1, wherein each of said first and second precharge circuits (142, 144), said first and second groups of N switches (Q₅, Q₆, Q₉, Q₁₀; Q₇, Q₈, Q₁₁, Q₁₂), and said first and second output switch means (126, 128) comprises MOS transistors. A data input/output circuit according to claim 3, wherein said first group of N switches (Q₅, Q₆, Q₉, Q₁₀) comprises four first switches, and said second group of N switches (Q₇, Q₈, Q₁₁, Q₁₂) comprises four second switches. A data input/output circuit according to claim 1, further includes fifth switch means (134) coupled to said first data bus (110) and controllable by said third timing control signal (7), sixth switch means (136) coupled to said second data bus (112) and controllable by said fourth timing control signal (8), and a data input buffer (138) for converting 1-bit input information into complementary signals and transferring the same to said fifth and sixth switch means (134, 136) under the control of another logic level of said enable signal.

Inventors: TAKASUGI, ATSUSHI OKI ELECTRIC INDUSTRY CO., LTD.
Applicants: OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1985
Main classification: G11C11
IPC codes: G11C11