MEMORY CIRCUIT WITH IMPROVED POWER-DOWN CONTROL

Abstract: An improved memory circuit having power-down mode is disclosed. The memory is of the type having a memory cell matrix and a peripheral circuit for achieving access operation to the memory cell matrix under control of at least one control signal and is featured in that a power supply to at least a part of the peripheral circuit is stopped only when the control signal is kept inactive for a predetermined period or more, reducing the power consumption in the memory.

Description: BACKGROUND OF THE INVENTION: The present invention relates to a memory circuit and particularly to a memory circuit having a power-down mode in which a power consumption is reduced in non-selected state. Access mode and stand-by mode of memory circuits are controlled by a chip selection signal. In access mode, peripheral circuits such as address decoders, output circuits are enabled as well as memory cells, and access operations to memory cells are conducted. In stand-by mode, power supply to peripheral circuit is stopped while maintaining power supply to memory cells so that access to the memory cell is inhibited. This feature of the stand-by mode contributes to power reduction when the memory circuit is not accessed. In this sense, this stand-by mode is also referred to as "power-down mode". In addition to the reduction of power consumption, many efforts have been paid to improve access time. Access time has been discussed in two categories. One is the so-called address access time which is the access time from a time point when address information to the memory circuit is established under the state that the memory circuit is enabled by a chip selection signal. The other is the so-called chip selection access time which is the access time from a time point when the memory circuit is switched to the enabled state by the chip selection signal while address information has been established prior to the enabled state. In recent microcomputer systems, it has been routine to apply address information and a chip selection signal to a memory employed therein in such manner that address information is first applied to the memory and thereafter the memory is enabled by the chip selection signal. Therefore, access time to the memory is substantially determined by the chip selection access time. Thus, when a memory circuit is used in such system, the chip selection access time has significance and is required to be faster than the address access time. However, in conventional memory circuits, it has been difficult to achieve desired chip selection access time because the peripheral circuits of the memory circuit are changed from a non-powered state to a powered, enabled state a predetermined time after from the control of the chip selection signal. Thus, it has been difficult to provide a memory circuit which consumes less power in stand-by mode and simultaneously, has the feature that the chip selection access time is faster than the address access time. A memory circuit according to the preamble part of claim 1 is disclosed in EP-A-17990. In this circuit a control signal is generated for controlling peripheral circuits when any of the address signals is changed in level. As in this memory the peripheral circuits are solely controlled based on the control signal without using a write enable signal for controlling the peripheral circuits together with a state of the control signal the control signal is not generated when the write enable signal is active without changing the address signals. Thus, the memory cannot perform a write operation in this instance. Furthermore, this circuit is of the non-synchronous type which does not receive the chip selection signal from the external and it is therefore not apparent in which way a synchronous type memory circuit receiving a chip selection signal from the outside of the memory can be improved. It is therefore an object of the invention to provide a memory circuit having faster chip selection access time than address access time. This object is achieved by a memory circuit comprising an array of memory cells and a peripheral circuit for performing an access operation to said array in response to a detection signal fed to said peripheral circuit, wherein said detection signal is produced by a detection circuit depending on input signals of said memory circuit and renders at least a part of said peripheral circuit via an operation control circuit in the operating state when the dection signal is active and in the non-operating state when the detection signal is not active, respectively, wherein said detection circuit receives at least one control signal and inactivates said detection signal when an inactive level of the control signal equal or longer than a predetermined period is detected. According to the invention the memory circuit is put in complete non-selection state when the control signal is kept at inactive level for a predetermined period of time as in this state the possibility that the memory circuit will be selected soon is very small. On the other hand where a chip selection signal, a write enable signal and an output enable signal are used to control the memory circuit, the detection circuit detects the state of the three signals. In that case, when all of the above signals are kept at inactive level, the power supply to at least part of the peripheral circuit is stopped. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a schematic block diagram of a memory circuit according to a prior art; Fig. 2 is a schematic circuit diagram of an address buffer employed in the memory of Fig. 1; Fig. 3 is a schematic block diagram of a memory according to one embodiment of the present invention; Fig. 4 is a schematic circuit diagram of an address buffer control circuit employed in the memory of Fig. 3; Figs. 5 and 6 are schematic circuit diagrams of the address buffer employed in the memory of Fig. 3; Fig. 7 is a schematic block diagram of an application system of the memory according to the invention; and Fig. 8 is a timing chart showing operation of the system of Fig. 6. DETAILED DESCRIPTION OF THE INVENTION: Referring to Fig. 1, an example of a prior art memory circuit is explained. The memory is basically composed of an array 3 of memory cells, a row address buffer 1, a row decoder 2, a sense amplifier section 4, a column address buffer 6, a column decoder 7, an I/O switch section 5 and an I/O buffer 8 in a known manner. To the row address buffer 1, the column address buffer 6, the column decoder 7, the sense amplifier section 4 and the I/O buffer 8, a chip selection signal CS is applied. The signal CS is of the low active type signal and enables the circuit blocks 1, 6, 7, 4 and 8 when it is low and disenables them when it is high in level. The sense amplifier section 4, the I/O switch 5 and the I/O buffer 8 are also controlled by a write enable signal WE between a read mode and a write mode. The write mode is introduced in response to a low level of WE while the read mode is introduced in response to a high level of WE . Furthermore, the I/O buffer 8 is controlled by an output enable signal OE . The buffer 8 operates in the read mode when OE is low. Selection and non-selection of the memory are achieved by enabling and disenabling operation of each functional blocks in accordance with the low and high levels of the chip selection signals CS . Power consumption of the memory is reduced at the time of the non-selection is accomplished by stopping the supply of power to each peripheral blocks, and this control is performed by the high level of CS . This structure is directed particularly to accomplish low power consumption. One bit structure of the row address buffer 1 is illustrated in Fig. 2. The one bit adders buffer 1 -i is composed of field effect transistors Q₁₁ , to Q₂₁. The transistors Q₁₁ to Q₁₃ form a first stage of inverter, and transistors Q₁₄ to Q₁₇ and Q₁₈ to Q₂₁ form second and third stages of inverters, respectively. The transistors Q₁₁, Q₁₄ and Q₁₈ are controlled by a control signal CS complementary to the chip selection signal CS and serve as power supply switches to the first to third stages of inverters. The transistors Q₁₇ and Q₂₁ controlled by CS serve as reset transistors for outputs A' i and In the non-selection mode, the signals CS and CS are rendered high and low so that the transistors Q₁₁, Q₁₄ and Q₁₈ are rendered non-conductive to cut the power supply to the first to third stage inverters. When the mode is switched from the non-selection mode to the selection mode, the power supply V CC to the first to third stage inverters is initiated and a predetermined time after the first to the third stage inverters are laid in operating state. Then, in response to the input A i , the outputs A' i and are produced after operation times of first to third stage inverters in cascade. Thus, the outputs A' i and are produced after a relatively large period of time has elapsed from the application of the low level of CS . On the contrary, it is possible to eliminate the delay time due to the switching of the switching to the first to third stage inverters by directly connecting drains of the transistors Q₁₂, Q₁₅ and Q₁₉ to V CC . However, in such case, the address buffers always consume power even in the non-selection mode, failing to reduce the power consumption. As described above, it has been difficult to provide a memory circuit which consumes the reduced power in non-selection or stand-by mode and which has at the same time, the feature that the chip selection access time is faster than the address access time. Referring to Figs. 3 and 4, the memory according to the present invention is explained. Fig. 3 shows a block diagram of the memory of the invention, in which portions corresponding to those in Fig. 1 are designated by the same reference numerals. The present embodiment is achieved by controlling the row address buffer 1 by a control signal PD which is generated by the address buffer control circuit 10, instead of CS . Namely, the address buffer control circuit 10 receives the signals CS , WE and OE and produces a high level of the signal PD when at least one of the signals CS, WE and OE assumes its active level, i.e. low level to enable the row address buffer 1. On the contrary, when all of the signals CS , WE and OE assume their inactive levels i.e. high level, the circuit 10 produces a low level of the signal PD. Accordingly, the address buffer 1 is laid in non-operating state. In this case, as the buffer 1, the circuit of Fig. 2 is employed and instead of CS, the signal PD is applied to the gates of the transistors Q₁₁, Q₁₄ and Q₁₈, as illustrated in Fig. 5. The structure of the control circuit 10 is shown in Fig. 4. The signals CS , WE and OE are applied directly to inputs of a NAND gates 14 and also inputted to other inputs of the NAND gate 14 via delay circuit 11, 12 and 14, respectively. The operation of this embodiment is explained below. When the period that all of the chip selection signal CS , the write enable signal WE and the output enable signal OE are inactive high level, is longer than the delay time of the delay circuits 11 to 13, the NAND gate 14 produces a low level as PD. In response to the low level of PD, the power supply to the address buffer 1 is stopped. In contrast, if at least one of the signals CS , WE and OE is at active low level, or all of them are high but such period is shorter than the delay time of the delay circuits 11 to 13, the signal PD is at high and therefore the power is applied to the buffer 1. Namely, when all of the signals CS , WE and OE are at the inactive (high) level, the memory is laid in complete non-selection state and there is no prospect to turn the memory in selection state. Therefore, in this instance, the address buffer 1 can be set in non-operating state. On the contrary, when at least one of the signals CS , WE and OE is rendered active (low), there is possibility that the memory will be brought into the selection mode soon. Therefore, in this instance, the power is applied to the buffer 1 and one address buffer can respond to the application of the input signals rapidly. Therefore, when the signal CS is changed to low, the address buffer 1 immediately produces its output. Thus, the chip selection access time can be faster than the address access time without increasing power consumption. Fig. 6 shows another example of the address buffer 1. In this example, first to third stage inverters are of the so called CMOS type, in which transistors Q P1 to Q P4 are P-channel transistors and transistors Q n1 to Q n4 are N-channel transistors. The effect of the memory circuit of the present invention can be easily understood when the operation on a memory board is considered. Fig. 7 is a block diagram of a memory board having a plurality (four) of memory devices M₁ to M₄, which is useful for explaining the effect of the present invention. The four memory devices 21 to 24 (M₁ to M₄) use an I/O bus 25 in common, and the address input A i , the write enable signal WE and the output enable signal OE are applied in common to these memory devices. The chip selection signals CS 1 to CS 4 for selecting these memory devices 21 to 24 are prepared by decoding the high-order address of an ordinary system, and are supplied to the memory devices, respectively. Fig. 8 is a timing chart showing the operation of the memory board shown in Fig. 7. In the period T1, only the chip selection signal CS 1 and the signal WE are Low, so that the memory device 21 is selected and is under the write state. Similarly, in the periods T2, T3 and T4, the memory devices 22, 23 and 24 are selected and under the read state, the write state and the read state, respectively. In the subsequent period T5, since all the chip selection signals CS 1 to CS 4 are High, none of the memory devices are selected and the memory board is in the non-selection state. In such a case, the write enable signal WE and the signal OE are generally HIGH. In contrast, in the periods T1, T2, T3, T4, in which any of the memory devices is selected, or the period in which the memory board is selected, either one of the signal WE and the signal OE is essentially Low. Since the signal WE and the signal OE are supplied in common to the memory devices, at least one of the chip selection signal, the signal WE and the signal OE supplied to the memory devices is Low. The above explains the outline of the operation of the memory boards in general. The present invention pays specific attention to the fact that when the memory board is in the selection state, at least one of the control signals is LOW, and when the memory board is in the non-selection state, all the control signals are High. In other words, when the memory board is in the non-selection state, all of the chip selection signal CS , the write enable signal WE and the signal OE are High and the period has generally a certain length. Particularly in the case of a battery back-up system using a low voltage data retention function, the period ranges from several milli-seconds to several days, and low power consumption is held for such an elongated non-selection period. Therefore, control may be made in such a fashion that the supply of power to the address buffer 1 is cut off in the non-selection state lasting more than several milli-seconds. This several msec period is formed by a delay circuit, and is suitably from 1 to 5 msec. Besides the power to the address buffer described in this embodiment, the present invention can also stop the power to the other blocks except the power that is necessary for the data retention by the memory cells. Hence, the effect of the present invention is remarkable. If the non-selection period is shorter than the period set by the delay elements, the power supply to the address buffer is continued, so that the chip selection access time is the access from the row decoder, and is faster than the address access time. As described with reference to the embodiment, the present invention can provide a memory circuit which has low power consumption at the time of non-selection and yet has a faster chip selection access time than an address access time. Incidentally, the present invention can be applied to various applications in addition to the embodiment described above. When the invention is applied to a CMOS memory, for example, its address buffer is constituted in the manner such as shown in Fig. 5, for example. Since the initial input stage is controlled by the control signal PD, the level of the address input need not be fixed by pull-up or the like, and system design becomes extremely easy.

Claims: A memory circuit comprising an array (3) of memory cells and a peripheral circuit (1, 2, 5, 6, 7, 8) for performing an access operation to said array in response to a detection signal (PD) fed to said peripheral circuit, wherein said detection signal is produced by a detection circuit (10) depending on input signals of said memory circuit and renders at least a part (1) of said peripheral circuit via an operation control circuit (Q₁₁, Q₁₄, Q₁₈)in the operating state when the detection signal is active and in the non-operating state when the detection signal is not active, respectively, characterized in that said detection circuit (10) receives at least one control signal (CS, WE, OE) and inactivates said detection signal when an inactive level of the control signal equal or longer than a predetermined period is detected. The memory circuit according to claim 1, characterized in that said detection circuit (10)further comprises means for receiving a write enable signal (WE) a chip selection signal (CS) and an output enable signal (OE), said peripheral circuit conducting a write operation when said chip selection signal and said write enable signal are present, and that said detection circuit (10)includes a NAND circuit (14) receiving said chip selection signal, said write enable signal and said output enable signal. The memory circuit according to claim 2, characterized in that said detection circuit (10) includes first to third delay elements (11, 12, 13) receiving said chip selection signal, said write enable signal and said output enable signal, respectively, wherein said NAND circuit (14) further receives outputs of said first to third delay elements.

Inventors: AKATSUKA, YASUO
Applicants: NEC CORPORATION
Application year: 1985
Main classification: G11C7
IPC codes: G11C8, G11C7