SEMICONDUCTOR MEMORY WITH BIT LINES DIVIDED INTO BLOCKS

Abstract: The memory device has each pair of bit lines divided into blocks (BK iO ,---, BK ik ) each comprising memory cells (C iOO , ---, C iOm ; ---; C ikO , ---, C ikm ), switching elements (S iO , S iO ; ---) S ik , S ik ) inserted into the bit lines, and a block sense amplifier (VSA iO , ---, VSA ik ). Means responsive to the selection of a memory cell are provided to activate only the sense amplifier of the block containing the selected memory cell, and the switching elements are controlled to make ON only the ones of the selected block and of each block located between the selected block and the data bus. The sense amplifiers (VSA iO , ---, VSA ik ) have different driving abilities, such that the driving ability increases as the distance between the corres­ ponding blocks and the data bus increases. The differences in driving ability can be obtained by using MOS transistors of different channel sizes in the different blcok sense amplifiers.

Description: The present invention relates to a semiconductor memory device having a plurality of memory cells arranged in a matrix formed by word lines and bit lines connected to a data bus, and more particularly to a semiconductor memory device wherein the bit lines are divided into a plurality of blocks each including a plurality of memory cells, a sense amplifier and a switching element inserted into each bit line. Memory devices having a still larger memory capacity are proposed, with the result that the number of memory cells increases considerably with many word lines and bit lines connected to the memory cells. Accordingly, the stray capacitance distributed along the word and bit lines increases, which lowers the operation speed of the memory device. In order to solve this problem, it has been proposed to divide the bit lines or, more usually, the pairs of bit lines into a plurality of blocks, as disclosed in the Japanese Laid-Open Patent Application No. 84-101093. Each block includes a plurality of memory cells, a sense amplifier and a switching element inserted into each bit line. Means are provided which are responsive to the selection of a memory cell to be accessed for activating only the sense amplifier of the block containing the selected memory cell. The switching elements are controlled after activation of the sense amplifier of the selected block (i.e. the block containing the selected memory cell) to make ON only the switching elements of the selected block and of each other block eventually located between the selected block and the data bus. The object of the invention is to improve such semiconductor memory devices by allowing a high operation speed while reducing the power consumption. Another object of the invention is also to increase the operation reliability of the semiconductor memory device. The above objects are achieved according to the invention by providing sense amplifiers having respective driving abilities which are different from each other and which increase as the distance between the corresponding blocks and the data bus increases. Thus, the sense amplifiers in the farthest blocks from the data bus have the highest driving ability to amplify the voltage difference in enough short time despite the load capacitance along the bit lines, while the nearest blocks from the data bus have the lowest driving ability to avoid unnecessary power consumption. Sense amplifiers having different driving abilities can be obtained by using MOS (metal-oxide-semiconductor) transistors having different channel sizes. The particulars and advantages of the invention will become more readily apparent from the following description made with reference to the accompanying drawings wherein: FIG.1 is a circuit diagram of a prior art memory device with non divided bit lines; FIG.2 is a circuit diagram of a column part of a prior art memory device divided into blocks; FIG.3(a) is a circuit diagram of a conventional precharge circuit which can be used in connection with a block of a column part of the memory device of Fig.2 or of the memory device according to the invention; FIG.3(b) and 3(c) are circuit diagrams of two conventional switching elements which can be used in a block of a column part of the memory device of Fig.2 or of the memory device according to the invention; FIG.4 is a circuit diagram of a column part of a memory device according to the present invention; FIG.5 is a circuit diagram of a modified clock signal generator for use in a memory device according to the present invention; FIG.6 is a circuit diagram of a block sense amplifier in a memory device according to the present invention; FIG. 7(a) and 7(b) are plan views showing patterns of block sense amplifiers in blocks located respectively far and near of the data bus in a memory device according to the present invention; and FIG.8 is a time chart for illustrating the operation of a memory device according to the present invention. A description of semiconductor memory devices according to the prior art will first be made. In a conventional memory device having a memory capacity of 64 kilo (K) bits or 256 K bits, the memory cells are arranged in a matrix as shown in Fig.1. In this figure, reference symbols C₀₀, C₀₁, ---, C on designate the memory cells in 0-th column; C₁₀, C₁₁,---, C 1n the memory cells in the 1-st column; C io , C i1 , ---, C in the memory cells in the i-th column; and C no , C n1 ,---, C nn the memory cells in the n-th column. Each memory cell is located at the cross point of respective word line and pair of bit lines. The reference symbols WD₀, WD₁, ---, and WD n denote the 0-th, 1-st, ---, and n-th word line, respectively, and BL O , BL ₀; BL₁, BL ₁; ---; BL i , BL i ; ---; BL n , BL n denote the 0-th, 1-st, ---, i-th, ---, and n-th pair of bit lines, respectively. The pairs of bit lines have respective comumn decoders CD₀, CD₁, ---, CD i , ---, CD n . Similarly, the word lines have respective word decoders WD₀, WD₁, ---, WD n . When the memory device is in the read mode and word line select signals X₀, X₁, ---, and X n and column select signals Y₀, Y₁, ---, and Y n are applied to the word and to the column decoders, a designated memory cell is selected and the data signal stored in the designated memory cell is read out. For example, when the word decoder WD i and the column decoder CD i are controlled at the same time by the word line and column select signals X i and Y i ' respectively, the data signal stored in memory cell C ii is read out and column decoder CD i operates for sending the read out data signal to a pair of data bus DB, DB . The read out data sent to the data bus DB, DB is amplified by a sense amplifier SA placed in data bus DB and DB . However, when the memory capacity of the memory device increases to reach as much as a mega (M) bits, the number of memory cells also increases, and the stray capacitance distributed along each pair of bit lines increases compared with the memory capacitance provided in each memory cell. Therefore, the operation speed of the memory device for writing a data signal into a memory cell or reading a data signal from the memory cell is lowered; and it becomes difficult to obtain a good signal to noise ratio, which causes a reduction in the operation reliability of the memory device. To solve this problem, it has been proposed to divide each pair of bit lines into a plurality of blocks. Fig. 2 shows a column part of a memory device with the i-th pair of bit lines BL i , BL i divided into k blocks BK i0 , BK i1 , ---, and BK ik . Each block comprises a pair of divided bit lines, a plurality of memory cells, a block sense amplifier, and a pair of switching elements. For example, block BK ik has a pair of divided bit lines BL ik , BL ik , a plurality of memory cells C ik0 , C ik1 , ---, and C ikm , a block sense amplifier SA ik , and a pair of switching elements S ik , S ik . With reference to the embodiment of Fig.1 where each column has "n" memory cells, the number "m" is such that n=k.m. In Fig. 2, when one of the memory cells is selected by one of the word select signals, a corresponding one of block select signals BS i0 , BS i1 , ---, and BS ik is applied to the block sense amplifier of the block containing the selected memory cell in order to activate said block amplifier of the selected block. Then, the selected block sense amplifier amplifies the data signal stored in the selected memory cell. Pairs of switching elements S i0 , S i0; S i1 , S i1 ; ---; and S ik , S ik are inserted in the pairs of bit lines in the blocks B i0 , B i1 , --, B ik , respectively, for connecting the blocks in series. Column decoder CD i is inserted between the block (BK ik ) which is nearest to the pair of bus lines DB, DB ,and the pair of bus lines DB, DB . When the i-th column is selected by signal Y i , transfer gates Q i1 and Q i2 provided in the column decoder CD i are set to the ON state for sending the data signal which is amplified by the selected block sense amplifier to the pair of bus lines DB, DB . Further details of the block circuits and of their operation when the memory device is in the read mode will be explained referring to Figs. 3(a) to 3(c) relating to block BK i0 . Fig. 3(a) shows a pre-charge circuit PRE i0 which comprises transistors Q i01 , Q i02 , and Q i03 for applying equal pre-charging potential (V cc - V th ) to the pair of bit lines BL i0 , BL i0 when a pre-charge signal p is applied to the gates of transistors Q i01 , Q i02 , and Q i03 . The transistor Q i04 shown in Fig.3(b) forms the switching element S i0 or S i0 shown in Fig. 2; transistor Q i04 becomes ON when a clock signal  is applied to its gate. Fig. 3(c) shows another type of switching element which consists of a transistor Q i04 which is similar to that in Fig. 3(b) and of a transistor Q i05 which is connected in parallel to transistor Q i04 and is of a conduction type reverse to the one of transistor Q i04 ; the switching element of Fig. 3(c) becomes ON when clock signals ,  are simultaneously applied to the gates of the transistors Q i04 and Q iO5 , respectively. The operation of the circuit of Fig. 2 includes the following sequential steps: (1) one word line is selected by a word line select signal X₀, X₁, ---, or X n (see Fig. 1); for example, word WL₀ is selected by the word line select signal X O ; (2) one column is selected by a column select signal Y O , Y₁, ---, or Y n ; for example, column i is selected by the column select signal Y i ; (3) the memory cell located at the cross point of the selected word line and column is selected; for example, memory cell C i00 in block BK i0 is selected; (4) one block select signal is provided when a word line and a column have been selected, corresponding to the block containing the selected cell; for example, block select signal BS i0 is provided; (5) the block sense amplifier of the selected block is activated by the block select signal, so that a voltage difference appearing between the bit lines in the selected block is amplified; for example, block sense amplifier SA i0 is activated by block select signal BS i0 , so that the voltage difference appearing between the bit lines BL i0 , BL i0 is amplified; (6) after the voltage difference has been amplified by the selected block sense amplifier, all the switching elements in the selected column are made ON so that all blocks of the selected column are connected in series; for example, after the voltage difference appearing between bit lines BL i0 , BL i0 has been amplified by block sense amplifier SA i0 , all the switching elements S i0 , S i0 ; S i1 , S i1 ; ---; and S ik , S ik are made ON so that all blocks BK i0 , BK il , ---, and BK ik are connected in series; and (7) the transfer gates in the column decoder belonging to the selected column are made ON by a column select signal for transferring the amplified data signal onto data bus DB, DB ; for example, the transfer gates Q il , Q il in column decoder CD i are made ON by the column select signal Y i for transferring the amplified data signal onto data bus DB, DB . In the above step (6), it is not necessary that "all switching elements" be made ON. As already known, it is sufficient to set in the ON state the switching elements in the selected block and in the blocks located between the selected block and the column decoder CD i . In addition, also as already known, all other block sense amplifiers may be activated after the selected block sense amplifier has been activated and the switching elements have been made ON. Thus, in the known memory device of Fig.2, the load capacitance for the sense amplifier can be kept small at the first time when the block sense amplifier in the selected block is activated. However,when the blocks located between the selected block and the column decoder CD i are serially connected by the closing of the switching elements, the load capacitance for the selected block sense amplifier increases; for example in Fig. 2, when block BK i0 is selected and sense amplifier SA i0 is activated and the switching elements serially connect all the blocks, the load capacitance becomes the total capacitance along the whole bit lines in column i. Accordingly, the sense amplifier in the farthest block from the data bus, for example sense amplifier SA i0 in block BK i0 , must have a great enough driving ability to amplify the voltage difference in a short enough time. However, all the sense amplifiers have an equal driving ability,and if the sense amplifier in the nearest block from the data bus, for example sense amplifier SA ik in block Bk ik , is selected, this sense amplifier (SA ik ) wastes too much power. This drawback is eliminated according to the present invention by providing block sense amplifiers having different driving abilities. Fig. 4 is a block and circuit diagram of a column part of a memory device embodying the present invention. The block and circuit diagram in Fig.4 has the same constitution as that of the block and circuit diagram of Fig.2, and, in Figs. 2 and 4, the parts having the same reference symbols function equally. In Fig. 4, VSA i0 , VSA il , ---, VSA ik designate the block sense amplifiers which are similar to the block sense amplifiers in Fig.2 but have individual driving abilities different from each other such that the block sense amplifier in the farthest block from column decoder CD i or data bus DB, DB has the maximum driving ability and the block sense amplifier in the block nearest to data bus DB, DB has the minimum driving ability. In Fig. 4, for example, when a data signal stored in memory cell C i10 located in the i-th column and block BK il is read out, the memory device functions as follows. (1) the i-th column is selected when column select signal Y i is applied to column decoder CD i (see Fig. 1); (2) a word line WL m+1 corresponding to memory cell C i10 is selected and block select signal BS i1 is provided, so that sense amplifier VSA i1 is activated by block select signal BS i1 , and the voltage difference appearing between bit lines BL i1 , BL i1 due to the data signal stored in memory cell C i10 is amplified; and (3) the switching elements S i1 , S i1 ; S i2 , S i2 ; ---, and S ik , S ik in the selected block BK i1 and in the blocks BK i2 , BK i3 , ---, and BK ik located between the selected block BK i1 and the column decoder CD i are set to the ON state for connecting bit lines BL i1 , BL i1 to data bus DB, DB through column decoder CD i . (Switching elements S ik , S ik in the block BK ik nearest to the data bus can be omitted because they are always used.) The above control of the switching elements is performed by modified clock signals generated by a modified clock signal generator such as the one shown in Fig. 5. The modified clock signal generator shown in Fig. 5 generates modified clock signals  0 ,  1 , ---, and  k for controlling the setting of the respective switching elements S i0 , S i0 ; S i1 , S i1 ; ---, and S ik , S ik to the ON or OFF state. The modified clock signals are similar to the clock signal  shown in Figs. 3(a) and (b) but they control the switching elements as follows: all of the modified clock signals are required only when the farthest block (block BK i0 ) from data bus DB, DB is selected; when a block nearer than block BK i0 to the data bus is selected, modified clock signals for the blocks farther than the selected block from the data bus become unnecessary; for example, when block BK i1 is selected, the modified clock signal  ₀ for controlling the switching elements S i0 , S i0 in block BK i0 is not necessary, and when block BK ik is selected, the clock signal  k only is necessary. The above selection of the modified clock signals is made in the modified clock signal generator by combining properly the block select signals BS i0 , BS i1 , ---, and BS ik . In Fig. 5, OR gates OG₁, ---, OG k perform the above logic functions, and AND gates AG₀, AG₁, ---, and AG k produce the modified clock signals every time when clock signal  is applied to said AND gates. The OR gate OG j has a plurality of inputs receiving respectively the block select signals BS i0 to BS ij (j being an integer having any value from 1 to k). The AND gate AG₀ has two inputs receiving respectively the clock signals and the block select signal while the AND gate AG j has two inputs receiving respectively the clock signal  and the output of the OR gate OG j . Thus, applying the modified clock signal generator to the memory device, the bit lines in the selected block and the blocks located between the selected block and the data bus can be connected. Thus, the load capacitance of the activated sense amplifier can be reduced as much as possible; for example, when block BK i1 is selected, the stray capacitance appearing along bit lines BL i0 , BL i0 in block BK i0 has no influence upon sense amplifier SA i0 . When the upper blocks, i.e. the blocks farther from the data bus than the selected block, are not used, the pre-charge circuits (or bit line reset circuits) of Fig. 3(a) in said upper blocks can be controlled to be non-operative, which also contributes to saving power consumption. As hereinbefore explained, the sense amplifier in the selected block first operates, and then the switching elements in lower blocks, i. e. the blocks located between the selected block and the data bus are set to the ON state. Accordingly, when the pairs of bit lines in the lower blocks are connected to the pair of bit lines in the selected block, the voltage difference which has appeared between the bit lines in the selected block decreases due to the stray capacitance and the potential of the bit lines in the lower blocks, which causes the increase of the access time to the memory device. Accordingly, it can be said that the access time depends on the location of the selected block; for example, when the distance between the selected block and the data bus increases, the access time increases. The load capacitance for the sensing amplifier in the selected block is actually the sum of the stray capacitance of the lower blocks and the data bus. Therefore, when the sensing amplifier in each block has the same driving ability, as in the prior art, it becomes difficult for a sensing amplifier in a block placed far from the data bus to drive its load capacitance in a short access time. If the driving ability of the block which is the farthest from the data bus is made large enough to sufficiently shorten the access time, and if each sense amplifier must have the same large driving ability as the sense amplifier in the farthest block, this causes a waste of power when the sense amplifiers in the blocks located near the data bus are selected. The present invention solves this problem by providing block sense amplifiers with different driving abilities as a function of their location with respect to the data bus, the farthest block from the data bus having the highest driving ability; for example, in Fig. 4, sense amplifier VSA i0 has the maximum driving ability and the driving ability becomes smaller and smaller as the distance between the block and the data bus decreases. Then, the increase in the load capacitance can be compensated by the increase in the driving ability so that the access time for all the blocks can be equalized. Fig. 6 shows a circuit diagram of a block sense amplifier with a pair of switching elements, for example in block BK i0 . Q₁ and Q₂ are p-channel MOS (Metal Oxide Semiconductor) transistors, while Q₃, Q₄, and Q₅ are n-channel MOS transistors. V SS is a low power supply voltage (usually ground (GND)) and V CC is a high power supply voltage. BS is a block select terminal, and BL i0 , BL i0 , BL i1 , BL i1 ; are divided bit lines as in Fig.2. Transistors Q₁ and Q₃, and transistors Q₂ and Q₄ compose two CMOS (Complementary MOS) inverters, respectively, and the two CMOS invertors intersect each other to form a flop-flop circuit. The circuit formed by the two parallel connected CMOS invertors is serially connected with transistor Q₅ between V CC and V SS . Transistor Q₅ is set to the ON state upon reception of a block select signal on the terminal BS, activating the sense amplifier. Q₆ and Q₇ are n-channel MOS transistors which form the switching elements into the bit lines and similar to the ones shown in Fig.3(b). The differences in the driving ability of the block sense amplifiers can be obtained by changing the channel size of transistors Q₁, Q₂, Q₃, and Q₄. Figs. 7(a) and (b) show plan views of the IC (Integrated semiconductor Circuit) pattern for the circuit of Fig.6, respectively when the block sense amplifier has the maximum driving ability, and when the block sense amplifier has the minimum driving ability. In Figs. 7(a) and (b), each dotted area is a pattern for a limited diffusion zone, each shadowed area is a pattern for a gate material made of Poly-Silicon, each X marked portion shows a window for Al (Aluminum) contact, and each area enclosed by a thick line is a pattern for an Al wiring. In Figs. 7(a) and (b), w₁ is the channel size for transistors Q₁ and Q₂, w₂ is the channel size for transistors Q₃ and Q₄, and w₃ is the channel size for transistor Q₅. For example, when the memory device is in the class having M-bit memory capacity and the channel size for the transistors of a middle block sense amplifier, i.e. the block sense amplifier of the block located at the middle of the column, is set as a standard size, the ratio between each channel size and the respective standard size may be as follows: when the driving ability has its maximum value,w₁, w₂, and w₃ are longer than the respective standard sizes by as much as forty percent and when the driving ability has its minimum value, w₁, w₂, and w₃ are smaller than the respective standard sizes by sixty percent. Fig.8 is a time chart illustrating the operation of the memory device shown in Fig. 4. When the amplitude of an address signal A dd changes at time t₀, a pre-charge signal p is generated so that all the pairs of bit lines BL i0 , BL i0 ; BL i1 , BL i1 ; ---; and BL ik , BL ik shown in Fig.4 are charged to an equal value, such as V cc - V th for example. Then, when word line WL₀ is selected (see Figs. 3 and 4) at time t₁, memory cell C i00 in the column i is selected, and a small voltage difference between bit lines BL i0 , BL i0 in block BK i0 appears due to the data signal stored in memory cell C i00 . At time t₂, block select signal BS i0 becomes high (H) thus activating sense amplifier VSA₁₀ (transistor Q₅ becomes ON in Fig.6) for amplifying the small voltage difference. After the voltage difference on bit lines BL i0 , BL i0 has been sufficiently amplified by sense amplifier VSA i0 , clock signals  ₀,  ₁, ---, and  k become high (H) at time t₃ and all switch elements S i0 , S i0 ; S i1 , S i1 ; ---, and S ik , S ik become ON (because the farthest block BK i0 from the data bus is selected in this example). In the above example, at the time immediately after all switch elements have been made ON, the potential on the bit lines in all other non-selected blocks is a middle value of the pre-charge potential; accordingly, the H side of the bit lines BL i0 , BL i0 in selected block BK i0 decreases while the T thereof increases. However, since the driving ability of sense amplifier VSA i0 is great, the voltage difference appearing on bit lines BL i0 , BL i0 (and also on the other bit lines in the non-selected blocks) rapidly returns back to the value it had just before t₃ though the load for sense amplifier BSA i0 has the maximum value. The dotted lines in Fig. 8 represent the voltage differences on the bit lines in the prior art memory device of Fig.2, which shows the merits of the present invention. As a result, the time t₅ for changing the address signal Add can be hastened, which is effective to raise the operation speed of the memory device. It could have been imagined to activate the sense amplifiers in the non-selected blocks, after the corresponding switching elements have been made ON, if the selected block is far from the data bus. However, the control of the sense amplifiers in the non-selected blocks would have become too complicated, whereas, in the memory device of the present invention, the control of the sense amplifiers can be simply realized. It can be noted also that if all sense amplifiers were driven when the nearest block to the data bus is selected, this would result in a waste of power and in electrical noise because the amplification of the voltage difference would be made too quickly and the noise would produce a wrong operation of the memory device. While the above description has been made with respect to a static RAM, it is quite apparent that the present invention can also be applied to a dynamic RAM.

Claims: A semiconductor memory device having a plurality of memory cells arranged in a matrix formed by word lines and bit lines connected to a data bus (DB, DB ), and comprising: a plurality of blocks (BK i0 , ---, BK ik ) provided by dividing each bit line (BL i , BL i ) into divided bit lines (BL ik , BL ik ) and each including a plurality of memory cells (C i00 , ---, C i0m ; ---; C ik0 ,---,C ikm ),a sense amplifier (VSA i0 , ---, VSA im ), and a switching element (S i0 , S i0 ; ---; S ik , S ik ) connecting divided bit lines (BL i0 , BL i1 ) means responsive to the selection of a memory cell to be accessed for activating only the sense amplifier of the block containing the selected memory cell; and means controlling the switching elements after activation of the sense amplifier of said selected block containing the selected memory cell, to make ON only the switching elements of the selected block and of each block eventually located between the selected block and the data bus, characterised in that the driving abilities of the sense amplifiers (VSA i0 , ---; VSA in ) are different from each other and increase as the distance between the corresponding blocks and the data bus increases. A semiconductor memory device according to claim 1, characterized in that each sense amplifier comprises a plurality of MOS (Metal Oxide Semiconductor) transistors with a channel size which increases as the distance between the corresponding blocks and the data bus increases, whereby the transistors in the farthest block have the widest channel size to confer to the sense amplifier in said farthest block the highest driving ability whereas the transistors in the nearest block have the smallest channel size to confer to the sense amplifier in said nearest block the lowest driving ability.

Inventors: AOYAMA, KEIZO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G11C8
IPC codes: G11C11