SIGNAL TRANSMISSION CIRCUIT AND STORAGE DEVICE USING SUCH A CIRCUIT

Abstract: The circuit has a plurality of input terminals (T₀-T₃) jointly connected to a common output terminal (T S ). Each input terminal has a transfer MOS transistor (Q₄, Q₅, Q₆, Q₇) isolating this input terminal from other terminals at non-­ active state, and is connected to the common output terminal when an input signal is applied to the input terminal. A buffer circuit (I₀, I₁, I₂, I₃) is inserted between the input terminal and the gate of the MOS transistor, is driven by the input signal itself and provides a driving signal to the gate electrode of the MOS transistor, to make the MOS transistor conductive so as to transmit the inputed signal with almost perfectly preser­ ved signal profile and extremely small time lag. This trans­ mission circuit is applicable to transmit word line signals (ø₀, ø₁, ø₂, ø₃) to rows of storage cells in a storage device, in particular to transmit a word line signal simultaneously to a selected row of a real cell, to rows of reference cells and to a row of dummy cells in a multi-state ROM.

Description: The present invention relates to a signal transmission circuit having a plurality of input terminals and a common output terminal for transmitting an input signal pulse without substantial deformation of the inputed signal pulse profile. Particularly, it relates to a simplified signal transmission circuit for use in a semiconductor storage device for comparing an output of a real storage cell with that of a reference cell. Due to the rapid development of electronic devices, such as semiconductor storage devices, there occurs a demand for a signal transmission circuit having multi-input terminals and a common output terminal to transmit an input signal without any distortion of the pulse profile and with satisfactory timing. This is in particular the case for a multi-state read only memory (ROM), wherein the output voltage of a real storage cell is compared with output voltages of associated reference cells to detect the level of the stored information. A more detailed description of a multi-state ROM is given in the following. Recently, the demand for a storage device having high capacity has been increasing. A character generator for KANJI, for example, requires a MASK ROM having a capacity of 1 to 2 M bits. Accordingly, the direction of evolution for semiconductor storage devices has been to increase the number of storage elements per unit area on a semiconductor chip. For this purpose, various technologies for metal-oxide-semiconductor (MOS) devices have been developed to minimize the dimension of elementary devices such as MOS field effect transistors (FETs), conducting paths and the like, but there is a technical limitation. In order to overcome this limitation, multi-state storage cells come to be used instead of prior art binary storage cells, because a four state, quaternary, FET ROM, for example, is capable of storing twice as much information per unit area as a conventional binary ROM having the same number of storage devices per unit area on a semi-conductor chip. Multi-state storage devices having multi-state FETs are reported in Electronics, October 9, 1980, page 39 by John G. Posa, and Electronics, June 30, 1982 by J. Robert Lineback. Fig. 1 is a partial circuit diagram showing how the quaternary storage information is detected. The FETs Q₃ used for the four state storage cells MC (hereinafter real cells) have each one of four different conductances, gm₀ to gm₃, storing four different storage states, "0", "1", "2" and "3" respectively. These different conductances gms are provided by varying the resistance of channels of the FETs Q₃. There are several ways for varying the conductance gm of a FET. Throughout this document, FETs of different conductances are obtained by providing different channel widths W, including the channel W=O. Three different reference voltages are produced by reference FETs Q R . One reference FET Q R composes one reference cell MC R . The conductances of the reference FETs Q R1 to Q R3 are respectively gm₁ ',gm₂',and gm₃', with gm₀<gm₁'<gm₁<gm₂'<gm₂<gm₃'<gm₃ The corresponding channel widths W₀ to W₃ and W₁ to W₃, satisfy the relation expressed by W₀<W₁,<W₁<W₂,W₂<W₃,<W₃ Fig. 2 illustrates the relation between the outputs O of the cells and the channel widths W. It can be seen that the three outputs O₁' to O₃' of the reference cells Q R1 to Q R3 divide the output range from O₀ to O₃ into four portions. When reading out the storage information, the real cell and the corresponding reference cells are selected by applying a column selection signal V COL to the gates of transfer FETs Q₁ and Q₂ to make the FETs Q₁ and Q₂ conductive, and Q₃ and QR are connected to the corresponding load resistors R₁ and R₂ through column lines. Then, selection signals V WL and V RWL are applied to the gates of the FETs Q₃ and Q R through the word line WL and the reference word line RWL, respectively. Thus, the outputs O and O' of the cells are available at the nodes P₁ and P₂. The output of a real cell is thus compared simultaneously with the outputs from three reference cells Q R1 to Q R3 by means of three sense amplifiers SA₁ to SA₃ respectively (not shown), and a set of the three outputs of the sense amplifiers discriminates the level of the output O of the real cell. The FETs used for real cells and reference cells are assumed to have almost the same characteristics except their conductances, namely their channel widths. As a result, the reference cells serve to provide reference outputs, namely reference voltages, as long as the same gate voltage is applied to the gates of the FETs in the real cells and reference cells at any moment. As stated before, the real cell and the corresponding reference cell are selected by a word line signal rising from zero level, whereby the word line signal votage should be applied to the gates of the FETs of both cells exactly in the same way : maintaining the same change with time, namely the same signal shape (a wave profile). Usually the word lines are formed of poly-crystalline silicon, having a relatively high resistivity. As a result, due to a distributed parasitic capacitance along the word line, there is a significantly large time delay in the transmission of signals to each of the storage cells along the word line. This time delay is inevitable. In order to eliminate the gap of time delay between the respective word line signals at a reference cell and at the corresponding real cell, both of which belong to the same column, each row of the reference cells has a same number of cells and a similar word line as those of the corresponding row of real cells. The row of reference cells including its word line is formed as if it was a duplicate of a row of real cells. With this configuration, almost the same time delay occurs at a real cell and at the corresponding reference cell which are located at the same column. In addition, the profile of the word line signals is not the same, the reason of which will be described later. These are the reasons why almost the similar circuit elements, word lines and cell FETs, have been formed in the prior art reference and dummy cell arrays to avoid distortion, decay and time lag of the transmitting word line signals. This almost doubled configuration of the reference circuits occupies a large surface area of the substrate, adversely affecting the high packaging density of the storage device. Of course, a fixed voltage, a power source voltage Vcc for instance, can be applied to the gate of the FETs of the reference cells to create a fixed reference voltage. In this case, the rising word line signal should be applied to the gates of the FETs of the real cell until the signal reaches its final value, nearly Vcc, utilizing a strobe signal. This requires a relatively long time resulting in a longer access time. SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal transmission circuit having a plural input terminal and a common output terminal, for transmitting an input signal without any change of signal profile and with practically negligible time delay. It is another object of the present invention to provide a storage device such as a masked read only memory having multi state storage cells with a high packing density by reducing the number of the reference cells and associated word lines. It is still another object of the present invention to provide a storage device such as a binary level read only memory having reference cells for detecting low level output signals of its storage cells with a higher packing density by reducing the number of the reference cells and associated word lines. These objects, features and advantages of the present invention are accomplished by an improved signal transmission circuit comprising, according to the invention, a common output terminal, wherein each of said input circuits comprises : an input terminal ; a buffer circuit ; and a metal insulator semiconductor (MIS) transistor, the source region and drain region of said MIS transistor being connected to said input terminal and said output terminal, said buffer circuit being inserted between said input terminal and the gate electrode of said MIS transistor, and being driven by an input signal applied selectively to said input terminal, and said MIS transistor being driven by said buffer circuit to be made conductive, thereby allow ing input signal to be transmitted from said input terminal to said output terminal selectively. As mentioned hereinbefore, in electronic devices, such as a MOS read only memory, there is a demand for a signal transmission circuit having multi-input signal terminals and a common output terminal, so that an input signal applied to one of multi-input signal terminals can be transmitted to the common output terminal with the least possible deformation and delay, without any outside interference. A typical example is a quaternary-state MOS ROM, wherein a signal pulse is applied simultaneously to a gate of a FET of a real memory cell and to the gates of reference cells to compare the values of the outputs of the cells. These two pulse signals transmitted along word lines, should be completely identical with respect to time and signal magnitude, otherwise the reference cell cannot provide a correct reference voltage, as described before. Therefore, in a prior art four state ROM, for instance, three blocks of reference cells are provided having the complete duplicated construction of a real storage block, and therefore occupying a considerable large area on the chip. It is desirable that the number of word lines and the number of rows of reference cells and dummy cells be minimized, such as by having a common word line and a common row of reference cells or dummy cells, in order to save the surface area of the substrate of the ROM (a block of dummy cells comprising several rows is used for checking the arrival of a transmitting input signal at the end of the row). A signal transmission circuit making it possible to realize this arrangement is now discussed. With a transmission circuit comprising multi input terminals simply connected to a common output terminal, interference will occur between an input signal applied to one of the input terminals and other signals applied to another terminal, and the output signal profile will be deformed. With another circuit wherein multi input terminals are connected through respectively diodes to a common output terminal, the interference between input signals can be eliminated but the output signal profile is distorted by the diodes. If each of the multi input terminals is connected to the common output terminal through a respective MOS FET instead of a diode, the problem described above can be eliminated, however, additional control signals to be applied to the gates of the FETs are necessary, resulting in a more complicated circuit configuration and a cost increase of the device. The above-mentioned problem is solved by the signal transmission circuit according to the present invention. In the circuit of the present invention, each input terminal is connected to the output terminal through a MIS transistor (in particular a MOS FET such as an enhanced p-type MOS FET), which is kept non-conductive when no input signal is applied to the input terminal, whereby the input terminal is isolated from other input and output terminals. When an input signal is applied to one of the input terminals, the associated MIS transistor is made conductive, namely, is opened, by the input signal itself. It should be noted that the MIS transistor must be fully opened immediately after the arrival of the input signal. If the input signal is directly applied to the gate of the MIS transistor, the latter cannot be opened immediately, due to its threshold voltage, and is not conductive until the gate voltage exceeds the threshold voltage. Furthermore, the input signal applied to the gate may be not sufficiently high to make the MIS transistor fully conductive. In order to provide a definitely high input signal with lesser time delay to the gate of the MIS transistor to open the latter, a buffer circuit is inserted forming a wave shaping circuit. The buffer circuit is for example in the form of one or several c-MOS inverters. With the aid of the buffer circuit, the signal pulse applied to the gate of the MIS transistor is sufficiently low to make this transistor substantially conductive. Thus, the signal pulse can be transmitted from the input terminal to the output terminal keeping almost the same signal profile and having a negligible time delay. The signal transmission circuit according to the present invention is also applicable to a binary state storage device, wherein output signals from real cells are compared with reference signals provided by reference cells, in order to obtain a high sensing speed. As described above, a transmission circuit according to the present invention makes it possible to transmit a signal applied to one of plural input terminals to a common output terminal, without providing or receiving any influence to or from other input terminals, and while maintaining the profile of the signal throughout the transmission with practically negligible time delay. Accordingly, the transmission circuit can be applied to electronic devices, particularly to storage devices, resulting in a vast saving of circuits and elementary devices such as word lines and reference storage cells. This leads to a cost reduction and an improvement for obtaining a higher packing density of a storage device. The present invention will be more readily understood from a reading of the following description made with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing schematically a storage cell and a corresponding reference cell to explain how a multi-state storage information is detected, Fig. 2 is a diagram illustrating the relation between the channel width and the output of a field effect transistor, Fig. 3 is a circuit diagram of an embodiment of a signal transmission circuit, according to the present invention, Fig. 4 is a time chart showing a clock signal and input and output signals of the transmission circuit of Fig. 3, Fig. 5 is a circuit diagram of another embodiment of a signal transmission circuit according to the present invention, Fig. 6 is a functional block diagram of a four-state MOS read only memory (ROM), having blocked storage cells and reference cells, Fig. 7 is a circuit diagram of one of the real storage block of the ROM shown in Fig. 6, Fig. 8 is a circuit diagram of a prior art reference cell block of the ROM of Fig. 6, and Fig. 9 is a schematic circuit diagram of a reference block of the ROM shown in Fig. 6, having a signal transmission circuit according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 3 is a circuit diagram of an embodiment of the present invention. For sake of simplicity, it is assumed that, in this embodiment, the circuit has four CMOS inverters I₀ to I₃, four MIS transistors such as p-type MOS FETs Q₄ to Q₇ and an n-type MOS FET Q₈. The reference letters ø₀ to ø₃ denote input signals applied to input terminals T₀ to T₃ which correspond to the four word lines of a storage block, which will be described later. The inverters I₀, I₁, I₂, I₃ connect this input terminals T₀, T₁, T₂, T₃ respectively to the sources of the FETs Q₄ to Q₇. The drains of the FETs Q₄ to Q₇ are jointly connected to a common output line Lc, which is connected to an output terminal T S and to a power source Vss (usually a ground source) through the transistor Q₈. When all input signals are at low level, the outputs of the inverters I₀ to I₃ are at high level and the transistors Q₄ to Q₇ are non-conductive. A clock signal ø issued from a reset circuit is at high level, as shown in the time chart of Fig. 4, making the transistor Q8 conductive to discharge residual charges on the output terminal Ts to the ground. As a result, the output terminal Ts is at low level. When the reset signal ø is turned to active state (low level) and the transistor Q₈ becomes non-conductive, the circuit is ready for transmitting signals. When the input terminal T₁, for instance, is selected and other terminals are left non-selected, the gate voltage of the inverter I₁ and the source voltage of the transistor Q₅ start to rise. The output of only the inverter I₁ decreases to a low level and the outputs of the other inverters remain at high level. This leads to make the transistor Q₅ definitely conductive and the other transistors Q₄, Q₆ and Q₇ non-conductive, resulting in the transmission of the input signal ø₁ from the input terminal T₁ to the output terminal T s , producing an output signal ø s . The output signal ø s keeps almost the same profile as that of the input signal ø₁. This is because the driving action of the inverters I₁ is substantially quick and the output voltage is sufficiently low. The output signal ø s is slightly delayed due to a threshold voltage of the inverter I₁ but it is negligibly small as shown in the time chart of Fig. 4. Thus, the input signal ø₁ is transmitted to the output terminal T s with the almost same signal profile and a negligible time lag. After transmission of the signal, the potential of the terminal T₁ falls to low level and the output of the inverter I₁ returns to high level. Thus, the transistor Q₅ becomes again non-conductive. In the same way, other input signals ø₀, Q₂, Q₃ applied to the respective input terminals T₀, T₂, T₃, can be transmitted individually. This transmission circuit is applicable to a storage device such as a read only memory having a plurality of rows of reference storage cells and their associated word lines. By the use of the above-mentioned transmission circuit, a single word line and a single row of reference cells are sufficient to create a reference signal, resulting in a remarkable saving of word lines and reference storage cells. The case is the same with the dummy storage block. The above-mentioned gate transistors Q₄, Q₅,.... are p-type transistors. When n-type transistors are used instead of the above p-type transistors, the inverters used in the transmission circuit must be doubled in order to provide the gate of the n-type transistor with a positive signal to make it conductive. The circuit configuration is shown in Fig. 5. Transistors Q₁₁, Q₁₂ are depletion type FETs with commonly connected gate-source region, and transistors Q₁₃, Q₁₄ are enhanced type FETs. The pairs of two transistors, Q₁₁, Q₁₃ and Q₁₂, Q₁₄ compose two double inverters. This is regarded as a buffer denoted as B₁. The other buffers B₀, B₂,... are built in the same way. Q₁₀, Q₁₅, Q₁₆ and Q₁₇ denote n-type FETs. Fig. 6 is a functional block diagram of a modern four-state storage device of 2 M bits capacity. The device illustrated in Fig. 6 has a two bits output. For eight bits output, four devices as the one of Fig. 6 are formed on a substrate. The illustrated storage device comprises a real cell array divided into 256 blocks MCB 1 to MCB 256, and a reference array of three blocks MCB R 1 to MCB R 3, for creating three reference voltages. A circuit configuration of the real cell block and its block decoder is shown in Fig. 7. Each block comprises four rows of storage cells MC, four associated word lines WL₁ to WL₄ and 256 bit lines BL₁ to BL₂₅₆. To one bit line, 256X4 real cells MC belonging to one column are connected. To each real cell block MCB is connected a respective block decoder, comprising four drivers DV₁ to DV₄ and a NAND-gate G. The four drivers DV₁ to DV₄ are driven by four input signals ø₀ to ø₃ respectively fed from a common decoder (shown in Fig. 6), which commonly drives three reference block decoders, one of 256 real block decoders and one dummy cell block decoder. The common decoder is composed of four AND-gates g₀ to g₃. To each AND-gate, as shown in Fig. 6, address signals A₀, A ₀, A₁ and A₁ are inputed and, depending upon the combination of the four inputed signals, one of output signals ø₀ to ø3 is outputed. Accordingly, corresponding to a combination of the four address signals, one of the signals ø₀ to ø₃ is selected to be of high level. The operation of the real cell block will be now briefly discussed with reference to Fig. 6 and Fig. 7. At first, a real cell block is selected by an address signal through the NAND-gate G, setting the output of the gate at a low level. Then by other address signals A₀ to A ₁, one of the AND-gates g₀ to g₃ is selected and the output of the selected gate, ø₀ for example, is set at high level while the others are all at low level. The low level output of the NAND-gate G is applied to the gates of the p-type FET Q p and n-type FET Q n of each one of the cell real block drivers DV₁ to DV₄, causing the FET Q p to be conductive and the FET Q n to be non-conductive. At this state, the signal ø₀ which is rising up, is transmitted to the word line WL₁. Thus, the potential of the word line WL₁ rises up, and the row is selected. Of course, the other three FETs Q p are conductive, but the applied signals ø₁ to ø₃ are at low level, and the word lines WL₂ to WL₄ remain at low level, non-selected. The output of the non-selected NAND gates of the other real cell blocks is kept at high level, and each p-type FET Q p is non-conductive, isolating the associated word line from the other word lines. Each n-type FET Q n is conductive forcing down the associated word line to the ground potential. A block diagram of a prior art reference cell block is illustrated in Fig. 8. Each reference cell block has four word lines and four rows of reference cells like the real cell block described above. The three reference cell blocks provide three different reference voltages by using each four rows of reference FETs. The FETs of each row have each a respective channel width corresponding to the reference voltage to be created. However, except the channel width of the reference FETs, all other elements of the word lines and reference cells are formed quite the same as those of the real cell blocks. This is because the input signals ø₀ to ø₃ are not the same but show some small differences due to the following facts. The word line signals ø₀ to ø₃ are created by using a different combination of address signals A₀, A ₀ , A₁ and A ₁ , as described before. In addition, the AND-gates g₀ to g₃ are not formed quite identically because of the limita tion of space on the substrate. Therefore, the selection of a real cell and of the three reference cells should be performed by using the same word line signal. For example, the real word line WL₁ and the reference word line RWL₁ should be selected by using the same word line signal ø₀. Thus, for both real and reference cell blocks, four word lines and four rows of cells are formed in a similar arrangement. The three reference cell blocks, of course, should be selected every time a real cell block is selected. Therefore, adress signals, A₂ and A₃ , for example, are always allotted for the reference block. The dummy cell block has a single word line and four rows of dummy cells, having the same configuration as that of a real cell block, except that all the dummy cells have a widest channel, because the dummy cell block is used for simulating the rising condition of the word line signal voltage under the worst circumstances, for checking the completion of the transmission of the signal along the word line. The operation of the four-state storage device having prior art reference blocks, partially shown in Fig. 6, will now be described. By a combination of address signals, one of the real cell blocks MCB 1 to MCB 256 is selected. By causing the level of one of ø₀ to ø₃ signals to rise, one of the word lines of the selected real cell block is selected, whereby the outputs of the selected real cells are outputed to the bit lines BL₁ to BL₂₅₆, one of which being selected by a column decoder (shown at the bottom side of Fig. 6) and fed to three sense amplifiers SA₁, SA₂ and SA₃. At the same time, all the reference cell blocks are selected, because the three reference voltages are always necessary. Then, the word lines and bit lines of the reference cell blocks corresponding to that of the real cell block are selected. The three selected reference signals V R1 to V R3 are respectively fed to the three sense amplifiers. The two signals inputed to each sense amplifier are compared to each other to output a signal representative of the difference between the two inputed signals, in order to discriminate the level of the output of each selected real cell. Similarly, the dummy cell block is always selected and the selection of four word lines is performed in the same way as in the case of the reference cell blocks. A detector DET is connected at the end of the dummy word line for sensing the rising up to a predetermined of the potential at the end of the dummy word line. Once this rising sensed by the detector, a clock signal CK is outputed to activate the sense amplifiers SA₁ to SA₃ and cause the amplifiers to issue outputs O₁, O₂ and O₃, respectively. These outputs correspond to the FET of the real cell selected, denoting the states "0", "1", "2" or "3" : "000", "100", "110" or "111". The outputs O₁, O₂ and O₃ are processed by a logic circuit to be converted to binary-state signals. As described in detail, almost a duplicated circuit configuration is used for the three reference cell blocks and the dummy cell block in a prior art four-state read only device. As a result, significantly large area is devoted to these circuits. Now, the transmission circuit according to the present invention is applied to the reference storage blocks and dummy blocks of the four-state read only memory to reduce the four word lines and four rows of cells to a single word line and a single row of cells. Fig. 9 is a schematic wiring diagram of a reference storage block using a transmission circuit according to the present invention as shown in Fig. 3. Same reference letters and numerals denote same parts in Fig. 8 and Fig. 9. The four input terminals shown in Fig. 3 correspond to the four word lines of each of the three reference blocks or of one dummy block. As it is clearly apparent from Fig. 9, a single row of reference storage cells MC R and a single word line WL R are used instead of four rows of cells and four word lines. When any of input signals ø₀ to ø₃ is caused to rise, the same driving signals are applied simultaneously to a selected real cell and to corresponding (at the same column) reference cells MC R of the three reference blocks. Mutually corresponding real cell MC and three reference cells MC R located at the same column, are driven by respective driving signals. It is clear that the selected driving signals have almost no distortion and that the signals are transmitted along the word lines in the selected row of real cells, in the three rows of reference cells and in the row of dummy cells with the same speed, producing no time gap between the transmitted signals. By applying the present invention to the read only memory shown in Fig. 6, nine word lines for the reference blocks and three word lines for the dummy block can be omitted. In addition, 256X12 pieces of storage cells can be saved. These provides the read only memory with a significantly improved high packing density and cost reduction. So far, the application of the transmission circuit according to the present invention has been described with regards to storage devices, but it is obvious to those skilled in the art that the use of the transmission circuit is not confined to the devices described above, but can be extended to various other apparatuses.

Claims: A signal transmission circuit comprising a common output terminal (Ts) and a plurality of input circuits being jointly connected to said common terminal, wherein each of said input circuits comprises : an input terminal (T₀, T₁, T₂, T₃) a buffer circuit (I₀, I₁, I₂, I₃); and a metal insulator semiconductor (MIS) transistor (Q₄, Q₅, Q₆, Q₇), the source region and drain region of said MIS transistor being connected to said input terminal and said output terminal, said buffer circuit being inserted between said input terminal and the gate electrode of said MIS transistor, and being driven by an input signal (₀, ₁, ₂, ₃) applied selectively to said input terminal, and said MIS transistor being driven by said buffer circuit to be made conductive, thereby allowing said input signal to be transmitted from said input terminal to said output terminal selectively. A signal transmission circuit according to Claim 1, wherein said MIS transistor (Q₄, Q₅, Q₆, Q₇) is of p-type channel type and said buffer circuit comprises a cMOS inverter (I₀, I₁, I₂, I₃). A signal transmission circuit according to Claim 1, wherein said MIS transistor (Q₁₀, Q₁₅, Q₁₆, Q₁₇) is of n-type channel type and said buffer circuit (B₀, B₁, B₂, B₃) comprises two cMOS inverters connected in series. A storage device comprising : a real storage cell array forming a matrix comprising a plurality of rows of real storage cells, (MC) for storing information; a reference storage cell array comprising a plurality of rows of reference storage cells (MCR) for creating reference signals (V r1 , V r2 , V R3 ), each reference row creating one of a predetermined number of reference signals ; a row of dummy storage cells each for simulating the transmission of a word line signal (₀, ₁, ₂, ₃) applied to said row of real storage cells and said row of reference cells; and a signal transmission circuit for transmitting said word line signal (₀, ₁, ₂, ₃) simultaneously to a selected row of real storage cells, all rows of said reference storage cells and said row of dummy storage cells, characterized in that said signal transmission circuit (Fig. 9) comprises a common output terminal (TS) and a plurality of input circuits being jointly connected to said common output terminal, each of said input circuits comprising : an input terminal(T₀, T₁, T₂, T₃),a buffer circuit (I₀, I₁, I₂, I₃) and a metal insulator semi-conductor (MIS) transistor (Q₄, Q₅, Q₆, Q₇), the source region and drain region of said MIS transistor being connected to said input terminal and said output terminal, said buffer circuit being inserted between said input terminal and the gate electrode of said MIS transistor said buffer circuit being driven by said word line signal (₀, ₁, ₂, ₃) applied selectively to said input terminal, and said MIS transistor being driven by said buffer circuit to be made conductive, thereby causing said word line signal to be transmitted from said input terminal to said output terminal selectively.

Inventors: SUZUKI, YASUO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G11C11
IPC codes: G11C8, G11C7, G11C11