DIGITAL COMMUNICATION SYSTEM INCLUDING AN ERROR CORRECTING ENCODER/DECODER AND A SCRAMBLER/DESCRAMBLER

Abstract: The error correction code data communication system comprises a transmitter scrambling both non-coded data and coded data and a receiver descrambling both nondecoded data and decoded data using the same code process. The frequency of occurrence of an error correction pulse in a decoder is monitored to set up synchronization for descrambling. This digital communication system is capable of synchronizing a scrambler and a descrambler to each other without the need for a special synchronizing bit, and descrambling a signal without enhancing data errors developed in a transmission path.

Description: Background of the Invention The present invention relates to a digital communication system of the type using error correction codes and, more particularly, to a digital communication system which includes an improved scrambler/descrambler. In a digital communication system of the type described, a transmitter station passes an input data signal through a scrambler to randomize it and then through an encoder to error-correction encode the scrambler output, the encoder output being sent to a receiver station over a transmission path. The receiver station in turn routes the received data signal through a decoder to error-correction decode it and then through a descrambler to randomize the decoder output to thereby recover the original data signal. As will be described later in detail, the descrambler comprises a shift register, an inhibit circuit connected to intermediate taps of the shift register, and an Exclusive-OR gate (modulo 2 adder) connected to intermediate taps of the shift register and an output of the inhibit circuit. The incoming data signal is applied to the shift register by way of the Exclusive-OR gate. Also, the intermediate tap output of the shift register is fed back to the shift register via the Exclusive-OR gate. The problem encountered with such a construction is that data errors developed in the transmission path are magnified by the descrambler at the receiver station. W. W. Peterson, E. J. weldon, "Error-Correcting Codes", 2nd edition, MIT, 1972, ninth printing, 1988, pages 376-381, deals with the problem of recovering from lack of synchronization, particularly if cyclic blocks are used. G. C. Clark, J. B. Cain, "Error-Correction Coding for digital communications", Plenum Press, 1981, pages 278-279, describe encoders/decoders with an enhanced error rate indicating a de-synchronization. JP-A-58-218 252 discloses a scrambling system, where the scrambling is performed prior to the encoding. NTZ, 1974, No. 12, pages 475-479, also describes a scheme of synchronization recovery for scramblers. It is therefore an object of the present invention to provide a digital communication system capable of synchronizing a scrambler and a descrambler to each other without the need for a special synchronizing bit, and descrambling a signal without enhancing data errors developed in a transmission path. This object is solved with the features of the claims. Brief Description of the Drawings Fig. 1 is a block diagram of a prior art error correction code data communication system; Fig. 2 is a circuit diagram showing an example of prior art scramblers or descramblers; Fig. 3 is a schematic block diagram of an error correction code data communication system in accordance with the present invention; Fig. 4 is a block diagram representative of a transmitter forming part of the communication system of the present invention; and Fig. 5 is a block diagram of a receiver forming the other part of the system of the present invention. Reference will now be made to the accompanying drawings for describing the present invention in detail. Detailed Description of the Invention Referring to Fig. 1 of the drawings, a prior art data communication system of the kind concerned is shown. At a transmitter, an input data signal 100 to be transmitted is randomized by a scrambler 1, then provided with an error correction code by a convolutional encoder 2, and then transmitted over a transmission path 3 as a transmit data signal 101. At a receiver station, on the other hand, a received input data signal 102 coming in from the transmission path 3 is decoded by a convolutional decoder 4, then turned into the original signal by a descrambler 5 with a code error corrected, and then outputted as a received output data signal 103. Desirably, an error correction code transmission system constructed as described above should readily set up synchronization between the scrambler 1 at the transmitter and the descrambler 5 at the receiver without resorting to a special synchronizing bit. Referring to Fig. 2, there is shown in a block diagram a prior art scrambler or a descrambler. The circuitry shown in Fig. 2 represents a scrambler or a descrambler presented in CCITT Recommendation V-35. The circuitry in a scrambler mode operation receives an input data signal at a terminal A and produces a scrambled data signal at a terminal B, while in a descrambler mode operation receiving an input data signal at the terminal B and producing a descrambled data signal at the terminal A. Outputs of a twenty-stage shift register 10 appearing at intermediate taps T₃ and T₂₀ are applied to an adder 12 to be modulo 2 added thereby. Meanwhile, outputs of the twenty-stage shift register 10 appearing at taps T₁ and T₉ are delivered to an inhibit circuit 11. An output of the inhibit circuit 11 and that of the adder 12 are routed to an adder 13 also for modulo 2 addition, thereby inhibiting an occurrence that the data signal become all ZEROs. An output of the adder 13 and the transmit input data signal 100 or a receive input data signal are summed modulo 2 by an adder 14 the output of which is applied to the terminal B (or A). The output of the adder 14 is also fed to the twenth-stage shift register 10 for a synchronizing function. With the construction shown and described, the scrambler or the descrambler allows a transmitter and a receiver to be automatically brought into synchronization and, therefore, needs no special bit or timing otherwise required for synchronization. Due to such a nature, this type of circuitry is generally referred to as a self-synchronizing scrambler/descrambler and extensively used with ordinary data transmission systems. The prior art circuitry, however, has left the following problem unsolved. Since the input data signal is applied to the shift register and an output signal of intermediate taps of the shift register is fed back to the shift register, any error introduced into the data while the latter propagates through the transmission path 3 is undesirably magnified by the descrambler. In the construction shown in Fig. 2, the twenty-stage shift register 10 has two intermediate taps and, hence, the error probability of the data output from the descrambler is at maximum three times greater than that associated with the transmission path. Referring to Fig. 3, a digital communication system embodying the present invention which is free from the problems discussed above is shown in an extremely skeletonized diagram. In a transmitter, a scrambler 1a comprises a pseudo random generator 23, a convolutional encoder 33, and modulo-2 adders 21 and 22. The pseudo random generator 23 and convolutional encoder 33 are commonly interconnected to the adders 21 and 22. An output of the adder 22 is coupled to a transmission path 3. A data signal received over the transmission path 3 is applied to an adder 24 of a descrambler 5a. A convolutional decoder 4a and a pseudo random generator 26 of the descrambler 5a are commonly interconnected to modulo-2 adders 24 and 25. An output 110 of the decoder 4a is adapted to control the descrambler 5a. First, the construction of the transmitter will be described. A transmit input data signal 100 and an output of the pseudo random generator 23 are applied to the adder 21 which then sums them modulo 2. An output of the adder 21 in turn is fed to a convolutional encoder 2 which then produces an error correction code. Specifically, an output of the encoder 2 includes a data signal and a parity signal. The output of the encoder 2 and that of the pseudo random generator 23 are modulo 2 added by the adder 22, while an output of the adder 22 is sent to the transmission path 3 as a transmit output data signal 101a. Next will be described the construction of the receiver. A receiver input data signal 102a coming in from the transmission path 3 and an output of the pseudo random generator 26 are routed to the adder 24 to be summed modulo 2. An output of the adder 24 is demodulated by the convolutional decoder 4a. An output of the decoder 4a and that of the pseudo random generator 26 are subjected to modulo 2 addition at the adder 25 the output of which is delivered as a receive output data signal 103. The synchronizing timing for the generator 26 is accomplished by monitoring the output 110 of the decoder 4a, i.e. an error correction pulse signal 110. Details of the error correction code data communication system of the present invention will be presented. In the illustrative embodiment, the encoder 2 comprises a convolutional encoder having an encoding/decoding rate (R) of 3/4, while the decoder 4a comprises a convolutional decoder with R = 3/4. Referring to Fig. 4, a construction of the transmitter in accordance with the illustrative embodiment is shown in a block diagram. As shown in Fig. 4, the transmitter includes a serial-to-parallel (S/P) converter 31 which is connected to three adders 32a, 32b and 32c which in turn are connected to a convolutional encoder 33 with R = 3/4 (corresponding to the encoder 2 of Fig. 3). The encoder 33 consists of a twenty-stage shift registers 38a, 38b and 38c, modulo-2 adders 39a, 39b and 39c, and an inverter 40, which are interconnected as illustrated. The construction and operation of the encoder 33 per se are well known in the art and, therefore, detailed description thereof will be omitted for simplicity. Outputs of the encoder 33 are applied to four modulo-2 adders 34a, 34b, 34c and 34d which are connected to a parallel-to-serial (P/S) converter 35. A 1/3 frequency converter 36 has an output connecting to the S/P converter 31, pseudo random generator 23 and convolutional encoder 33. A 4/3 frequency converter 37 has an output connecting to the P/S converter 35. The pseudo random generator 23 comprises, for example, a twenty-stage shift register, an inhibit circuit and an Exclusive OR gate and forms part of the scrambler 1a; outputs (e.g. first to third stage outputs and seventeenth to twentieth stage outputs) of the twenty-stage shift register are connected to three adders 32a, 32b and 32c and four adders 34a-34d, respectively. A data signal flows through the transmitter described above as will be explained hereinbelow. A transmit input data signal 100 is applied to the P/S converter 31 to be thereby converted to a three parallel streams of data. The parallel data streams respectively are coupled to the three adders 32a-32c to be thereby modulo 2 added each to an output of the pseudo random generator 23. The outputs of the adders 32a-32c are applied in parallel to the convolutional encoder 33 which then error-correction codes them to provide four streams of parallel data. The four parallel data streams respectively are routed to the four adders 34a-34d to be thereby summed modulo 2 each with an output of the pseudo random generator 23. The parallel data output from the adders 34a-34d are converted by the P/S converter 35 to a serial transmit output data signal 101a. The various sections of the transmitter are operated at individual timings which will be described. Transmit input pulses 104, an input sync signal associated with the data signal 100, have their frequency reduced to 1/3 by the 1/3 frequency converter 36 in order to set up synchronization between the output of the S/P converter 31 and that of the pseudo random generator 23. Simultaneously, the clock pulses 104 are applied to the 4/3 frequency converter 37 to have their frequency reduced to 4/3, whereby a transmit output data signal 105 is provided. The signal 105 serves as a sync signal for synchronizing the output of the P/S converter 35 and, also, for sending it to the transmission path 3. Referring to Fig. 5, the receiver in accordance with the system of the present invention is shown in a block diagram. As shown, the receiver includes a serial-to-parallel (S/P) converter 41 which is interconnected to four modulo-2 adders 42a, 42b, 42c and 42d, which in turn are connected to a convolutional decoder 43. The decoder 43, corresponding to the decoder 4a of Fig. 3, comprises twenty-stage shift registers 51a, 51b and 51c, Exclusive OR gates 52a, 52b and 52c, Exclusive-OR gates 53a, 53b and 53c, an Exclusive-OR gate 54, an inverter 55, an OR gate 56, a syndrome register 57, and a threshold detector 58, which are interconnected as illustrated. The convolutional decoder 43 is of the well known type and, therefore, details thereof will not be described for simplicity. The encoder 43 is connected to three modulo-2 adders 44a, 44b and 44c which in turn are connected to a parallel-to-serial (P/S) converter 45. A 1/4 frequency converter 46 is connected to the S/P converter 41, and a 3/4 frequency converter 47 to the P/S converter 45. A pseudo random generator 48 is connected to the four adders 42a-42d and three adders 44a-44c. A sync monitor counter 49 is connected to the OR gate 56 of the convolutional decoder 43. The input of a logic circuit 50 is connected to the output of the sync monitor counter 49 and that of the 1/4 frequency converter 46. The output of the logic circuit 50 is connected to a clock input terminal CLK of the pseudo random generator 48. The pseudo random generator 48, sync monitor counter 49, and adders 42a-42d and 44a-44c constitute a descrambler 5a in combination. The flow of a data signal through the receiver constructed as above will be described. A receive input data signal 102a is applied to the S/P converter 41 to be converted to four parallel streams of data. The four adders 42a-42d modulo 2 add respectively the four parallel data to outputs of the pseudo random generator 48 (e.g. twentieth to seventheenth outputs of a twenty-stage shift register built in the generator 48). Then, the convolutional decoder 43 error-correction decodes the outputs of the pseudo random generator 48, thereby producing three parallel streams of data. These three parallel data streams are summed modulo 2 with outputs of the pseudo random generator 48 (e.g. third to first outputs of the twenty-stage shift register inside the generator 48), the resulting parallel data being turned by the P/S converter 45 to a serial receive output signal 103. It will be noted that the pseudo random generator 48 is identical with the pseudo random generator 23 of the previously described transmitter. The various sections of the receiver will be operated at individual timings presented hereinbelow. Receive input pulses 106, an input sync signal associated with the receive input data signal 102a, are reduced in frequency to 1/4 by the 1/4 frequency converter 46 in order to provide synchronization between an output of the S/P converter 41 and that of the pseudo random generator 48. The frequency of the receive input pulses is also reduced to 3/4 by the 3/4 frequency converter 47 to provide a receive output data signal 107, which functions to synchronize the output of the P/S converter 45. Now, synchronization between the transmitter and the receiver in accordance with the present invention will be presented. As a received input signal 102a begins to come in the receiver and while the pseudo random generator 48 is not synchronized, the threshold detector 58 of the convolutional decoder 43 generates a number of error correction pulses C i , C j and C k and applies them to the sync monitor counter 49. The counter 49 in turn generates an inhibit pulse if the number of the correction pulses is generater than a predetermined threshold value. The logics 50 provides AND of an inverted version of the inhibit pulse and an output of the 1/4 frequency converter 46, while the pseudo random generator 48 shifts the sync timing in response to an output of the logics 50. As a result, synchronization of the pseudo random generator 48 is set up only when the number of the error correction pulses has decreased below the threshold value, desirably to the minimum. In the illustrative embodiment, the output stages of the pseudo random generators 23 and 48 to be selected are open to choice so long as they satisfy a random condition of a data sequence required of the associated generator. While the present invention has been shown and described as employing convolutional error codes with R = 3/4, it is readily applicable to any other convolutional error codes, generally with R = n/m, as well as to block codes. It will be seen from the above that the present invention provides an error correction code data communication system which allows a scrambler of a transmitter and a descrambler of a receiver to be synchronized without resorting to the transmission of a special sync signal and, in addition, prevents an input data signal from being applied to the generator 23 or 48 and, thereby, prevents a data error developed in a transmission path from being magnified at the receiver. With the above advantageous features, the present invention simplifies a digital communications system of the type using error correction codes while eliminating the need for transmitting additional control signals or sync signals.

Claims: An error-correction code communication system of apparatus comprising a first scrambling means (21) for scrambling a data signal into a scrambled data signal, an encoder (2,33) for error-correction encoding the scrambled data signal to an error-correction code signal, a decoder (4a,43) for error-correction decoding a reproduction signal of the error-correction code signal to an error-corrected signal, and a first descrambling means (25) for descrambling the error-corrected signal into a descrambled data signal, characterized in that a) the system comprises a second scrambling means (23, 22) for scrambling the error-correction code signal into a scrambled error-correction code signal, and a second descrambling means (24, 26) for descrambling a received signal indicative of the scrambled error-correction code signal to produce the reproduction signal of the error-correction code signal, b) the second scrambling means including a first pseudo-random signal generator (23) for generating a first random signal in a repetitive pattern having a predetermined period, and a logic circuit (22) for modulo-2 adding the first random signal and the error-correction code signal to produce the scrambled error-correction code signal, c) the second descrambling means including a second pseudo-random signal generator (26,48) for generating a first random signal having the same repetitive pattern and period as those of the first pseudo-random signal generator (23) and a logic circuit (24) for modulo-2 adding the received signal and the first random signal of the second pseudo-random signal generator to provide the reproduction signal of the error-correction code signal to the input of the decoder (4a,43), and synchronization of the second pseudo-random signal generator being set up based on an code error in the decoder (4a) in such a manner as to reduce the code error; d) the first scrambling means comprises a logic circuit (21) for modulo-2 adding the data signal and a second random signal having the same repetitive pattern and period as those of the first random signal of the first pseudo-random signal generator to produce the scrambled data signal, and e) first descrambling means comprises a logic circuit (25) for modulo-2 adding the error-corrected signal and a second pseudo-random signal having the same repetitive pattern and period as those of the first random signal of the second random signal generator to produce the descrambled data signal. An error-correction code communication system of apparatus according to claim 1, with a transmitter and a receivers: the transmitter comprising a scrambler (1a) responsive to a data signal (100) for scrambling the data signal and the encoder (33) coupled to the scrambler (1a) for error-correction encoding; the receiver comprising the decoder (43) for error-correction decoding and a descrambler (5a) coupled to the decoder (43) for descrambling to produce a reproduction signal of the data signal (100); wherein the transmitter comprises the first pseudo-random signal generator (23) for generating a first set of random signals and a second set of random signals each having a repetitive pattern and a predetermined period, a serial-to-parallel converter (31) responsive to the data signal for producing a set of n parallel bit sequences, a pre-stage scrambling means (32a, 32b, 32c) responsive to the second set of random signals for scrambling the set of n parallel bit sequences into a set of n parallel scrambled bit sequences, the encoder (33) responsive to the set of n parallel scrambled bit sequences for error-correction encoding to a set of m parallel bit sequences of error-correction code, a post-stage scrambling means (34a, 34b, 34c, 34d) responsive to the first set of random signals for scrambling the set of m parallel bit sequences of error-correction code into a set of m parallel scrambled bit sequences of error-correction code, and a parallel-to-serial converter (35) for converting the set of m parallel scrambled bit sequences of error-correction code to a serial signal, the receiver comprises a serial-to-parallel converter (41) for converting the serial signal to a set of m parallel bit sequences, the second pseudo-random signal generator (48) for generating a first set of random signals and a second set of random signals each having the same repetitive pattern and period of those of the first pseudo-random signal generator, a pre-stage descrambling means (42a, 42b, 42c, 42d) responsive to the first set of random signal of the second pseudo-random signal generator (48) for descrambling the set of m parallel bit sequences into a set of m parallel descrambled bit sequences of error-correction code, the decoder (43) for error-correction decoding the set of m parallel descrambled bit sequences of error-correction code to a set of n parallel bit sequences, a post-stage descrambling means (44a, 44b, 44c) responsive to the second set of random signals of the second pseudo-random signal generator for descrambling the set of n parallel bit sequences from the decoder into a set of n parallel descrambled bit sequences, and a parallel-serial converter (45) responsive to the set of n parallel descrambled bit sequences to produce an output signal which is s reproduction of the data sinal, the receiver further comprises a monitoring means (49) for monitoring a code error in the decoder (43) and means (50) for setting up synchronization of the second pseudo-random signal generator in response to an output of said monitoring means (49) in such a manner as to reduce the code error.

Inventors: KATO, KOTARO C/O NEC CORPORATION, OSHIMA, GORO C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1985
Main classification: H03M13
IPC codes: H04L25, H03M13, H04L1, H04L7