SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device, in which mamy mem­ ory cells (1) formed by transistors (1a, 1b) having a Schottky barrier transistor as a load are arranged along word lines (2a) and the memory cells are driven from one ends of the word lines by word drivers (12). Wherein dummy cells are formed between the word drivers and the memory cells adja­ cent to the word drivers, so that a forward voltage of the memory cells adjacent to the word drivers is now affected by polycrystalline silicon (14) in the word drivers.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device as known from US-A-3 886 531 in which a plurality of memory cells formed by transistors having a Schottky barrier diode (SBD) as a load are arranged along word lines and the memory cells are driven from one end of the word lines by word drivers. 2. Description of the Related Art Actual memory devices include many word lines. The potential of one of those word lines is made high level so as to select the same. The word drivers include polycrystalline silicon layers, while the memory cells do not; this affects the memory cells adjacent to word drivers and with SBD's as loads. The forward voltage V F of the SBD's in turn heavily affects the characteristics of the semiconductor device. Further, while cells adjacent to word drivers are positioned between a word driver and another cell, other cells are positioned between one cell and another, having the same construction. Therefore, peripheral portions around cells adjacent to word drivers are nonsymmetrical in construction, so that special relationships such as between the amount of aluminum and windows of bulk silicon are spoiled. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device in which memory cells adjacent to word drivers are not affected by polycrystalline silicon layers included in the word drivers. Another object of the present invention is to provide a semiconductor memory device in which memory cells adjacent to word drivers are symmetrical in construction in the peripheral portions. A further object of the present invention is to provide a semiconductor memory device in which a stable forward voltage is obtained for SBD's included in memory cells adjacent to word drivers. The above-mentioned objects can be achieved by a semiconductor memory device, in which a plurality of memory cells formed by transistors having a Schottky barrier diode as a load are arranged along word lines and the memory cells are driven from one end of the word lines by word drivers, characterized in that dummy cells connected to said word lines are formed between the word drivers and memory cells adjacent to the word drivers, so that the forward voltage V F of the Schottky barrier diodes of the memory cells adjacent to the word drivers is not affected by polycrystalline silicon in the word drivers. BRIEF DESCRIPTION OF THE DRAWINGS Further features and advantages of the present invention will be apparent from the ensuing description with reference to the accompanying drawings, in which: Fig. 1 shows the layout of a conventional semiconductor memory device; Fig. 2 is a circuit diagram of a conventional semiconductor memory device; Figs. 3(a) and 3(b) are a plan view and sectional views of the circuit shown in Fig. 2; Fig. 4 shows the layout of an embodiment according to the present invention; Fig. 5 is a circuit diagram of an essential portion of the semiconductor memory device according to an embodiment of the present invention; Figs. 6(a) and 6(b) are a plan view and sectional view of the essential portion of the circuit of the semiconductor memory device shown in Fig. 5; and Fig. 7 is a plan view of the semiconductor memory device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 shows the layout of a conventional semiconductor device. In Fig. 1, reference numeral 1 designates memory cells arranged in row and column directions and reference numeral 12 word drivers. In Fig. 1, memory cells arranged adjacent to the word drivers 12 are indicated by hatching. These are affected by the polycrystalline silicon layers in the word drivers and are not symmetrical in the peripheral portions. This will be further explained by Fig. 2. In Fig. 2, reference numeral 1 shows memory cells, 2a, 2b word lines, 3a, 3b bit lines and SBD Schottky barrier diodes. In Fig. 2, when data is held, a hold transistor T 2h is in the ON state. Therefore, data holding current flows in the collector of the hold transistor T 2h , SBD is placed in the ON state, and the potential at the collector of the transistor T 2h becomes lower than that of the word line by the forward voltage V F of the SBD to become "L". As the base of the transistor T 1h is connected to the "L" level, the transistor T 1h is placed in the OFF state, so that the potential at the collector of the transistor T 1h becomes substantially equal to that of the word line. In this holding state, the potential of the bit lines is such that no current flows in the transistors T₁ and T₂ which have emitters connected to the bit lines 3a, 3b respectively. When the transistors T₁ and T 1h are placed in the ON state from the data held state in the writing state, the potential of the bit line connected to an emitter of the transistor T₁ is made lower than that of collector of the transistor T₂ by V BE of the transistor so as to pass the writing current in the transistor T₁. Then, the transistors T₁ and T 1h are placed in the ON state, the collector of the transistor T₁ becomes "L" level, the transistors T₂ and T 2h enter the OFF state, and the collectors of the transistors T₂ and T 2h become "H" level. When the potential of the bit line is placed from this writing state to a hold state, the hold current I H in place of I W flows in the transistor T 1h , so that the written data is held. An actual memory device includes many word lines. The potential of one is made "H" level so as to select one of the same. Now, assume that the difference of the potential on the selected word line V WS and the nonselected word lines V WN is ΔV W = V WS - V WN . The current I W flows so that the transistor T₁ in the memory cell to be selected is in the ON state and the transistor T₂ is in the OFF state. In this state, assume that all memory cells on the same bit line as the cell to be selected have inverted data compared to the selected cell (that is, the transistor T 4h is in the ON state). At this time, when the forward voltage V F of the SBD connected to the collector of the transistor T₁ is large, and has a value near ΔV W , the potential of the collector of the transistor T₁ , that is, V WS - V F , in the selected cell approaches the potential of the collector of the OFF state transistor T 3h that is, V WN = V WS - ΔV W in the non-selected cell, so that the current I d flows in the transistor T₄. If the number of the memory cells connected to one bit line is N, the current I d is multiplied by (N - 1). Thus, the current I W passed in the selected cell becomes {I W - I d (N - 1)} so that the time for writing the data to the selected cell increases. Therefore the uniformity of the forward voltage V F of the SBDs in the memory cells is very important from the viewpoint of writing speed. A plan view and a sectional view of the semiconductor device shown in Fig. 2 are given in Figs. 3(a) and 3(b), respectively. In Fig. 3, 12 is a word line driver portion, 1 is a memory cell, 1a, 1b are transistors included in a memory cell, and 13 is an isolation layer. In the transistors 1a and 1b, C is a collector contact, B is a base contact, E is an emitter contact, and SBD is a Schottky barrier diode. Further, 14 shows a polycrystalline silicon layer and 15 an aluminum wiring layer. Here, note that the left side of line 11 includes the polycrystalline silicon layer 14, while the right side does not. In memory cells having SBD's as loads, as explained above, the V F of the SBD has a very large affect on the characteristics of the semiconductor memory device. Therefore, it is desired to obtain a stable V F in a chip. However, as shown in Fig. 3, the SBD's near the word line drivers 12 can be affected by the polycrystalline silicon of the emitter of the word line driver 12, so that the V F may vary. Furthermore, the SBD's adjacent to the word line drivers 12 do not have the symmetrical pattern layout around them, unlike the SBD's in the other memory cells. Therefore, a tendency occurs in that the V F of the SBDs is not uniformly formed between the memory cells. Further, if a series of V F 's on the word driver side is large, the writing time becomes longer than other memory cell portions and there is the danger that specifications cannot be satisfied. For the purpose of resolving this problem, it is possible to increase V W . However, if V W is larger, there is the drawback of an increased readout time. The difference of V F between the terminal SBD and the other SBD's is more than 100 mV due to manufacturing variations, so it is difficult to set the optimum value. In the present invention, other dummy SBD's 20 are provided separate from the memory cells 1 adjacent to the transistors of the word drivers 12 as shown in Fig. 4, to prevent the SBD's of the memory cells 20 from being affected by the polycrystalline silicon of the transistors in the word line drivers 12. Embodiments of the invention will now be explained in detail referring to the drawings. Figure 5 is a circuit diagram of an embodiment of the present invention. As shown in Fig. 5, the feature of the present invention is to insert dummy SBD's 20 between the word drivers 12 and the memory cells 1 adjacent to the word drivers 12. According to the insertion of such dummy SBD's 20, the SBD having a large V F are limited to the dummy SBDs 20 not the SBDs in the memory cells 1. Therefore, a constant value of V F of the SBD's of the memory cells 1 can be obtained. Figure 6 shows the essential portion of a semiconductor integrated circuit including circuit shown in Fig. 5. In Fig. 6, 1 is a memory cell, 1a, 1b are transistors included therein, 12 is a word driver, and 13 is an isolation layer. The left side of a barrier line 11 shows portions where polycrystalline silicon 14 is formed, and the right side portions where no polycrystalline silicon is formed. 2a is a word line formed by an aluminum layer and connected to the n epitaxial layer so as to form the SBDs in the memory cells 1. Since many memory cells are connected to the word line 2a, a plurality of SBD's couplings are provided along the word line 2a. As shown in Fig. 6, the dummy SBD's 20 are provided adjacent to the word driver transistor 12, so the effect of the polycrystalline silicon layer of the transistor 12 is stopped at the dummy SBD's 20 and does not reach the SBD's of the memory cells 1. This enables stabilization of the characteristics of V F in the memory cells 1. Figure 7 is a plan view of a semiconductor memory device according to the present invention. The plan view shows a region including two word lines and two columns and clarifies the relationship among the memory cell portion 1, the dummy cell portion 20, and the word driver portion 12. There appear to be two reasons why the dummy SBDs 20 can prevent the change of V F of SBDs in the peripheral memory cells 1. First, the length between the polycrystalline silicon layer 14 in word driver transistor 12 and the SBD in peripheral memory cells 1 becomes larger than the prior art, so that there is a smaller effect from the polycrystalline silicon layer 14. Second, according to the dummy SBD insertion, even the SBDs of the peripheral memory cells have a symmetrical layout pattern along the word line layer 2a. Note that the final V F of the SBD sometimes depends upon the alloy between the aluminum of the word line 2a and the silicon of the n epitaxial layer in the bulk. As mentioned above in detail, according to the present invention, the value of V F of the SBD's used in the memory cells becomes stabilized. Thus, circuit design can be optimized and the manufacturing yield can be improved.

Claims: A semiconductor memory device, in which a plurality of memory cells (1)formed by transistors having a Schottky barrier diode (SBD) as a load are arranged along word lines (2a, 2b) and said memory cells are driven from one end of said word lines by word drivers (12), characterized by dummy cells (20) connected to said word lines and formed between said word drivers and said memory cells adjacent to said word drivers, whereby the forward voltage of the Schottky barrier diodes of said memory cells adjacent to said word drivers is not affected by polycrystalline silicon (14) in said word drivers. A semiconductor memory device according to claim 1, wherein said memory cells are separated by isolation layers (13) provided between them, said word drivers are provided with isolation layers (13) at both sides thereof, and said dummy cells (20) are formed between the isolation layers of said memory cells and the isolation layers of said word drivers as Schottky barrier diodes.

Inventors: FUKUMA, HIROYUKI, SATO, MASASHI 208, HIJIRI-SO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G11C11
IPC codes: G11C8, H01L27, G11C11, H01L21, G11C7