SEMICONDUCTOR MEMORY DEVICE WITH INFORMATION STORAGE VERTICAL TRENCH CAPACITOR AND METHOD OF MANUFACTURING THE SAME

Abstract: A semiconductor memory device includes a substrate of semiconductor material, and a plurality of programmable memory cells formed at the substrate. Each memory cell comprises one switching transistor formed in the substrate and isolated from adjacent memory cells in the substrate by a trench of a given depth formed in the substrate at the side of the switching transistor. Each switching transistor is associated with one storage capacitor formed in the trench at the side of the associated switching transistor. The storage capacitor includes a first vertical electrode provided on the insulator coated inner side wall of the trench and laterally ohmic-contacted to one conductive region of the switching transistor through a opening formed in the insulator coating on the inner side wall of the trench, an vertical insulative layer provided on the first vertical electrode, and a second vertical electrode provided on the vertical insulative layer.

Description: Background of the Invention Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device of so-called one-transistor type in which each memory cell comprises one information storage capacitor and one switching transistor connected thereto for writing and reading information on the storage capacitor. The present invention also relates to a method of manufacturing such a semiconductor memory device. Description of related art Heretofore, different type semiconductor devices, which can store binary information or data in terms of electric charges, have been developed and are at present used in various memories such as static random access memories (SRAMs), dynamic random access memories (DRAMs), read only memories (ROMs), etc. The reason for this is that a semiconductor memory of high integration density and large storage capacity can be easily obtained because each memory cell can be formed in a very small area. Among these semiconductor memories, a so-called one-transistor type semiconductor memory has been widely used as the DRAMs. In the one transistor type memory, each memory cell consists of one transistor and one capacitor, and therefore, is small in the number of electric components and in the cell area required to store one bit of information. Accordingly, the one-transistor type semiconductor memory is most excellent in possibility of high integration density. In integrated circuits, on the other hand, there is a ceaseless demand for increase of integration density or electric components per chip. To increase the integration density, it is necessary to reduce the memory cell size. This means the decrease of the area which can be used for the capacitor in the one-transistor type semiconductor memory cells. However, the decrease of the capacitor area result in decrease in the amount of charge which can be stored in the capacitor. This would lead to frequent occurrence of α-ray soft error and shortage of sensitivity of an associated sense amplifier. In order to avoid the above disadvantages, there have been proposed some capacitor structures for the one-transistor type memory cell, which can have a large charge storage capacity even with reduction of the memory cell area. One of the proposed capacitor structures is a so-called "stacked capacitor cell" which has been proposed by Koyanagi, M. et al. "Novel high density, stacked capacitor MOS RAM", 1978 IEDM, pp 348-351 (December 1978). In this stacked capacitor, the capacitor cell is formed above the switching transistor. Briefly, a first polycrystalline silicon layer is deposited on a insulator coating covering a switching field effect transistor formed in a substrate, and is electrically connected to the source region of the field effect transistor through a vertical contact hole formed in the insulator coating. An intermediate insulative film is deposited on the first silicon layer, and a second polycrystalline silicon layer is deposited on the intermediate insulative film to cooperate with the first silicon layer so as to form a capacitor. In the memory cell having such a capacitor, the amount of charge stored in the memory cell is determined by the capacitance constituted by the first and second polycrystalline layers. To increase the capacitance to as large as possible, the two polycrystalline layers would have to be extended to cover all the area available to each memory cell. However, as mentioned above, the increase of the integration density leads to decrease of the cell area, and this inclination cannot be avoided even in the case of the stacked capacitor cell. Therefore, although the stacked capacitor cell can have a charge storage capacitance larger than that of the further prior one-transistor type memory cell in the condition of the same memory cell area, it cannot have a sufficient capacitance when the integration density is further increased. In addition, the contact hole is required to connect between the source of the switching transistor and one electrode of the stacked capacitor cell. However, the vertical contact hole is a large obstacle to fineness of the memory cell, because the vertical contact hole has a horizontal sectional area and needs an insulator horizontally extending around the contact hole for preventing short-circuit with other wirings. Therefore, in the case of the stacked capacitor cell, it is very difficult to increase the integration density beyond a certain limit. Further, when the stacked capacitor covers the whole of the switching transistor to obtain a possible maximum capacitance, there is required to stack on the surface of the substrate at least three horizontal conductive layers, i.e., a gate electrode of the switching transistors, and the first and second polycrystalline silicon layers of the stacked capacitor. These stacked conductive layers will introduce large steps on the surface of the semiconductor memory chip, which will be a large cause of break of interconnection wiring on the substrate. Another proposed capacitor structure is a so-called "corrugated capacitor cell" formed at a trench in an active region of a semiconductor substrate, proposed by Sunami, H. et al. "A corrugated capacitor cell (CCC) for megabit dynamic MOS memories", 1982 IEDM, pp. 806-808 (December 1982). In this case, the trench is coated with an insulator film used as the dielectric film of the capacitor. The trench is then refilled with a conductive material, which is used as one electrode of the capacitor. With this construction, if the substrate is applied with a substrate bias voltage, an inversion layer is generated in the substrate along the surface of the trench. This inversion layer constitutes the other electrode of the capacitor. As seen from the above, in the case of the corrugated capacitor cell, the trench has to be formed in the active region, and therefore, a high integration density cannot be expected. In addition, the active region including the trench must be isolated by any isolation means such as a field oxide. This is also an obstacle to increase of the integration density. A semiconductor memory device according to the preamble part of claim 1 is disclosed in JP-A-59 141 262 and Patents Abstracts of Japan, Vol. 8, No. 272 (E-284) (1709). In this device the connection between the source electrode of the switching transistor and the charge storage electrode is realized on the top of the trench by an additional connection layer. From EP-A-0 164 829 which has been cited under article 54 (3) EPC a memory device is disclosed in which the gate electrode overlaps the first charge storage electrode so that the switching transistor is influenced by the charge storage electrode. It is the object of the present invention to provide a semiconductor memory device of the above type which can have a sufficient charge storage capacitance irrespectively of the increase of the integration density. Another object of the present invention is to provide a semiconductor memory device of the above type which allows to increase the integration density by reducing the memory cell area, while ensuring a sufficiently information storage capacity. A further object of the present invention is to provide a semiconductor memory device of the above type in which the storage capacitor is electrically connected to the switching transistor without the intermediary of a contact hole and without forming a further step on the semiconductor chip surface. A still further object of the present invention is to provide a semiconductor memory device of the above type in which a storage capacitor is formed without two or more conductive horizontal layers which are deposited on the substrate surface and which provide large steps on the semiconductor chip surface. An even further object of the present invention is to provide a semiconductor memory device of the above type having the storage capacitor of a sufficient capacitance without providing a trench in an active region of the substrate. Still another object of the present invention is to provide a semiconductor memory device of the above type which can have the storage capacitor of a sufficient capacitance even if an isolation trench is narrowed because of the increase of integration density. A further object of the present invention is to provide a method of manufacturing the aforementioned semiconductor memory device. A still further object of the present invention is to provide a semiconductor device including a capacitor which has a sufficient capacitance without restricting the areas of other electric components formed on the same substrate, and irrespectively of the increase of integration density. These objects are achieved by a semiconductor memory device which includes a substrate of semiconductor material, and a plurality of programmable memory cells formed on the substrate, each memory cell containing at least one switching transistor comprising a gate electrode which is connected to a word line, said switching transistor being formed in the substrate and isolated from adjacent electric components in the substrate by a trench of a given depth formed in the substrate at the side of the switching transistor, the trench having an inner surface coated with an insulator, and one storage capacitor connected to the switching transistor and formed in the trench at the side of the associated switching transistor, wherein said storage capacitor includes a first vertical electrode provided on the insulator coated inner side wall of the trench and being connected to one conductive region of the switching transistor, wherein the gate electrode does not overlap said first vertical electrode, wherein a vertical insulative layer is provided on the first vertical electrode, and a second vertical electrode is provided on the vertical insulative layer, wherein an opening is formed in the insulator coating on the inner side wall of the trench for connecting the first vertical electrode and the one conductive region, wherein the opening is formed on the upper edge of the insulator coating on the trench side wall, and is filled with a portion of the first vertical electrode so that the first vertical electrode is ohmic-contacted to the one conductive region of the switching transistor through a region of the substrate adjacent to the opening. With the semiconductor memory device mentioned above, the storage capacitor is vertically formed in the isolation trench which can separate and isolate the memory cell from the adjacent electric component such as another memory cell. Therefore, it can have a sufficient charge storage capacity by deepening the trench, irrespectively of the integration density. Thus, even if the semiconductor memory device is fabricated at higher integration density or to have narrower trenches, the vertical storage capacitor can have a necessary capacitance which can give a sufficiently high degree of α-ray soft error immunity and which does not cause the shortage of the sensitivity of an associated sense amplifier. Furthermore, the first vertical electrode of the storage capacitor is connected to the one conductive region of the switching transistor through the intermediary of the opening formed in the insulator coating on the trench side wall. Accordingly, since no vertical contact hole is required for the above connection, it is possible to reduce the area of each memory cell without restriction caused by the contact hole. In addition, the isolation trench is maintained at the same potential as that of the substrate, and cooperates with a channel stopper region of high impurity density formed under the bottom of the isolation trench, so as to surely isolate the memory cells. Therefore, there is not required a large active region in which a trench is formed as in the corrugated capacitor cell, nor is it necessary to provide a field oxide for isolation between adjacent memory cells. Accordingly, the semiconductor memory device of the present invention can has an integration density greatly higher than of the case using the corrugated capacitor cell. Moreover, the flatness of the semiconductor chip surface is greatly improved, because the capacitor electrodes are merged in the isolation trench and because the interconnection between the switching transistor and the storage capacitor is realized through the opening formed in the insulator coating of the trench side wall so that there is not needed to deposit a conductive layer on the substrate for such a interconnection. Accordingly, there will be less possibility of break of wirings, particularly metallic wirings made on the substrate surface. Thus, the semiconductor memory device in accordance with the present invention can have a large storage capacity at a high integration density. In the embodiment of the semiconductor memory device in accordance with the present invention, the opening is formed on the upper edge of the insulator coating on the trench side wall, and is filled with a portion of the first vertical electrode so that the first vertical electrode is ohmic-contacted to the one conductive region of the switching transistor through a region of the substrate adjacent to the opening. In addition, the trench is formed to substantially surround the switching transistor, and the storage capacitor is formed in a trench portion adjacent to the above mentioned conductive region of the switching transistor. Preferably, the trench is of a rectangular shape in a plan view and the storage capacitor is formed to extend over a substantial entire wall of one side of the rectangular shaped trench adjacent to the above mentioned conductive region of the switching transistor Furthermore, the above mentioned one side portion of the trench is completely refilled with the first and second vertical electrodes and the vertical insulative layer which constitute the storage capacitor. In the preferred embodiment of the semiconductor memory device, at least one pair of adjacent memory cells include a pair of switching transistors, which are isolated from each other by the trench formed between the one pair of transistors. In this embodiment, the first vertical electrode is provided on each of opposite insulator coated side walls of the trench and is electrically connected to one conductive region of the adjacent switching transistor through a opening formed in the insulator coating on each inner side wall of the trench. The vertical insulative layer is provided on each of the first vertical electrodes in the same trench, and a common second electrode is provided between the vertical insulative layers. As a result, one pair of vertical storage capacitors are formed in the trench between the one pair of switching transistors and each of the capacitors is associated to an adjacent one of the two transistors. Specifically, each switching transistor is an insulated-gate field effect transistor, and one of the source and drain regions of the field effect transistor is contacted to the first vertical electrode through the opening formed in the insulator coating on the trench side wall. In addition, the substrate of semiconductor material is of one conduction type, and the first and second vertical electrodes are formed from a semiconductor material of the conduction type opposite to that of the substrate. In a disclosed embodiment, the substrate of semiconductor material is a p-type single-crystalline silicon substrate, and the first and second vertical electrodes are formed of n-type polycrystalline silicon which is doped with material selected from a group consisting of phosphorus and arsenic. Further, the insulator coating on the side wall of the trench is formed of silicon dioxide, and the vertical insulative layer between the first and second vertical electrodes is constituted of a single layer of insulative material such as silicon dioxide or silicon nitride, a double layer of two insulative materials consisting of for example a silicon dioxide layer formed on the first vertical electrode and a silicon nitride layer deposited on the silicon dioxide layer, or a single layer of dielectric material such as tantalum oxide. According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device which includes a plurality of programmable memory cells, each of which contains at least one storage capacitor and one switching transistor connected thereto, comprising the steps of: forming in a substrate of semiconductor material a trench having an inner surface coated with an insulator film; forming a opening in the insulator coating in the proximity of the upper edge portion of the trench; depositing a conductive material on the side wall of the trench to form a first vertical electrode; providing a vertical insulative layer on the first vertical electrode; depositing a conductive material on the vertical insulative layer to fill up the remaining trench space and to form a second vertical electrode which cooperates with the first vertical electrode and the vertical insulative layer so as to constitute one vertical capacitor; and forming one switching transistor adjacent to the opening of the insulator coating in such a manner that one conductive region of the switching transistor is electrically and laterally connected to the first vertical electrode through the opening formed in the trench side wall insulator coating. Preferably, before the switching transistor is formed, the substrate is heated so that a portion of impurities contained in the first vertical electrode is diffused to the substrate through the opening of the insulator coating on the trench inner wall so as to form a contact region in the substrate adjacent to an upper portion of the first vertical electrode, so that the diffused contact region will be continuous to the one conductive region of the switching transistor when it is formed. In the specific embodiment, the substrate is a single-crystalline silicon substrate, and the trench is formed by the steps of: forming a first silicon dioxide coating, a silicon nitride coating and a second silicon dioxide coating on the upper surface of the substrate in the mentioned order; depositing a resist pattern on the second silicon dioxide coating excluding an area in which a trench is to be formed; etching the second silicon dioxide coating, the silicon nitride coating and the first silicon dioxide coating by using the resist pattern as a mask; also etching the silicon substrate by using the resist pattern and the second silicon dioxide coating as a mask to from a trench in the silicon substrate; removing the second silicon dioxide coating; and thermally oxidizing the inner surface of the trench thus formed by using the silicon nitride coating as oxidation protecting mask, so that the inner surface of the trench is coated with the silicon dioxide. Further, the opening is formed in the insulator coating on the trench side wall in accordance with the step of: depositing a resist material on the substrate to perfectly refill the silicon dioxide coated trench and to cover the upper surface of the silicon nitride coating; depositing an insulative material on the resist cover; forming on the insulative material layer a resist pattern having an opening in alignment with the trench and not smaller than the trench; etching the insulative material layer by using the resist pattern as a mask so as to form an opening in the insulative material layer corresponding to the opening of the resist pattern; removing the resist pattern and the resist materials by using the insulative material layer as a mask, to perfect remove the resist pattern and at the same time to remove the resist material on and in the trench so that the trench is filled with the resist material to leave the side wall of the trench upper edge portion in the exposed condition and the substrate is covered with the resist coating having the opening corresponding to the trench; and removing the exposed silicon dioxide coating on the trench side wall by using as the mask the remaining resist material in the trench and on the substrate upper surface, so that the substrate is exposed at the side wall of the upper edge portion of the trench. Thereafter, the first vertical electrode is formed by the steps of: removing the remaining insulative material layer on the substrate and the remaining resist material; depositing on the substrate a polycrystalline silicon of the conduction type opposite to that of the substrate so as to form on the side wall of the trench a polycrystalline silicon layer which has a thickness not greater than one-third of the gap of the trench and which is directly contacted to the exposed substrate through the opening formed in the upper edge of the silicon dioxide coating on the trench wall; and removing the polycrystalline silicon on the upper surface of the substrate and on the bottom of the trench by a reactive sputter etching so that a first vertical polycrystalline silicon layer remains only on each side wall of the trench so as to form the first vertical electrode. The insulative layer is formed on the first vertical electrode, for example, by thermally oxidizing the surface of the first vertical polycrystalline silicon layer, and then depositing a silicon nitride film on the substrate and the oxidized surface of the first polycrystalline silicon layer. In addition, the second vertical electrode is formed by depositing on the surface of the substrate a polycrystalline silicon of the conduction type opposite to that of the substrate so as to perfectly fill the remaining space of the trench, and removing the deposited polycrystalline silicon on the substrate so that the polycrystalline silicon remains only in the trench to constitute a second vertical electrode. Subsequently, there is thermally oxidized an upper oxidized an upper portion of the first and second vertical polycrystalline silicon layers by using the remaining silicon nitride coating on the substrate as oxidation protection mask, so that a silicon dioxide cover of a substantial thickness is formed on the top end of the first and second vertical polycrystalline silicon layers for protection of these vertical silicon layers. In the course of this thermal oxidation, the impurities contained in the first vertical polycrystalline silicon layer are diffused to the substrate through the opening of the insulator coating on the trench inner wall so as to form a contact region in the substrate adjacent to an upper portion of the first vertical polycrystalline silicon, so that the contact region will be continuous to the one conductive region of the switching transistor when the transistor is formed. In the succeeding switching transistor forming process, the above mentioned one conductive region of the switching transistor is formed to overlap with the diffused contact region in the substrate adjacent to the upper portion of the first vertical polycrystalline silicon. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a circuit diagram showing a portion of a memory cell matrix circuit in a semiconductor memory of the one-transistor type; Figure 2 is a sectional view of a pair of conventional semiconductor memory cells incorporated with stacked capacitor cells; Figure 3 is a view similar to Figure 2 but showing a conventional semiconductor memory cell incorporated with a corrugated capacitor cell; Figure 4 is a sectional view of one memory cell in the semiconductor memory device constructed in accordance with the present invention; Figure 5 is a sectional view taken along the line V-V in figure 4; and Figures 6A to 6J are sectional views illustrating the method of manufacturing the semiconductor memory device in accordance with the present invention. Description of the Preferred Embodiments Referring now to Figure 1 of the drawings, there is shown a partial circuit diagram of the memory cell matrix in the one-transistor type semiconductor memory device. The disclosed memory device includes a plurality of column lines or bit lines 10 and a plurality of row lines or word lines 12 intersecting the bit lines 10. At each intersection of the bit lines 10 and the word lines 12, one switching field effect transistor (MOS) 14 is located in such a manner that one terminal of the source-drain path of the MOS transistor 14 is connected to the bit line 10 and the gate is connected to the word line 12. The other terminal of the source-drain path of each switching transistor is connected to one electrode of a storage capacitor 16, whose other electrode is grounded. With this arrangement, each storage capacitor 16 acts to hold logical information as an electric charge, i.e., a potential, and read-out and write-in of such logical information is effected between the storage capacitor and the bit line 10 through the associated switching MOS transistor 14 by energizing or deenergizing the word line 12 connected to the gate of the same MOS transistor 14. Thus, one memory cell is formed by one switching transistor 14 and one associated capacitor 16. Each memory cell of the above mentioned one-transistor type semiconductor memory is constructed as shown in Figure 2 in the case of using a stacked capacitor cell. In this type of memory cell, a pair of MOS transistor are formed in a silicon substrate 20 and isolated from each other by a selectively oxidized isolation region 22. Each MOS transistor comprises a diffused source and drain regions 24 and 26 formed in the surface portion of the substrate 20 separately from each other. An insulator film 28 is deposited on a substrate region or channel region between the source and drain regions 24 and 26 to overlap those source and drain regions 24 and 26. On the insulator film 28 is deposited a gate electrode 30 in alignment with the channel region between the source and drain regions 24 and 26. This gate electrode 30 serves as a word line. A lower insulator layer 32 is deposited to cover the gate electrode 30, and a first polycrystalline silicon layer 34 is formed on the lower insulator layer 32 and a portion of the isolation region 22, so as to form one electrode of the capacitor. This first polycrystalline silicon layer 34 is contacted to the source region 24 through a contact hole 36 formed in the insulator film 28 positioning on the source region 24. An intermediate insulator film 38 is coated on the first silicon layer 34 and then a second polycrystalline silicon layer 40 is deposited on the intermediate insulator film 38 so as to form the other electrode of the capacitor which is to be connected to a predetermined potential. Furthermore, an upper insulator layer 42 is deposited to cover the second silicon layer 40 and the MOS transistor, and a conductive layer 44 is deposited on the upper insulator layer 42 to constitute a bit line. This conductive layer 44 is contacted to the drain region 26 through a contact hole 46 formed in the insulator film 28 on the drain region 26. As seen from the above description with reference to Figure 2, the stacked capacitor cell is formed above the associated MOS transistor. The capacitance of the stacked capacitor cell which determines the information storage capacity in the memory cell, is mainly determined by the area of the capacitor electrodes (34 and 40), namely, the area of the memory cell on which the stacked capacitor cell can be formed. Therefore, if the memory cell area is greatly reduced with a remarkable increase of the integration density, the stacked capacitor cell can no longer have a sufficient capacitance. The contact hole 36 for interconnecting the source region 24 of the MOS transistor and the one electrode 34 of the stacked capacitor has a horizontal sectional area and needs an insulator film portion 28 and a lower insulator layer portion 32 around the contact hole 36 for preventing the short-circuit with the gate electrode 30 and other wirings. Namely, for the contact hole 36, there has to be retained within each memory cell region a horizontal area larger than the horizontal section of the contact hole. This is a large obstacle to the scale reduction of the memory cell. As mentioned hereinbefore, therefore, if the stacked capacitor is formed in each memory cell, it is very difficult to increase the integration density beyond a certain limit. Furthermore, the stacked capacitor cell has the gate electrode 30 and the first and second polycrystalline silicon layers 34 and 40 on the upper surface of the substrate 20. These three layers produces a large step 48 at the side of the gate electrode 30 as seen from Figure 2. The bit line wiring 44 extending over the stacked capacitor is apt to be broken at the large step 48. Turning to Figure 3, there is shown a sectional view of one memory cell associated with the corrugated capacitor cell, which can constitute each one-transistor type memory cell shown in Figure 1. As seen from Figure 3, this memory cell is formed in an active region 70 of a silicon substrate 50 defined by a thick field insulator layer 72. One MOS transistor is formed in the active region 70 to have diffused regions 52 and 54 separately from each other so as to form source and drain regions. An insulator film 56 is formed on the substrate, and a gate electrode and word line wiring 58 is deposited on a channel region between the pair of diffused regions 52 and 54. At the side of the MOS transistor thus formed, there is formed a trench 60 coated with a insulator film 62. This trench 60 has polycrystalline silicon layers 64 and 66 deposited on the insulator coated wall surface. Thus, a storage capacitor is formed by the silicon layer 64, the insulating film 62 and an inversion layer 78 which is produced to extend along the trench 60 in the substrate 50 of the active region 74 and is connected to the region 54. Furthermore, an insulative coating 74 is provided to cover the MOS transistor. On the insulator coating 74, a bit line wiring 76 is formed to contact the diffused region 52 through a contact hole. In addition, another word line wiring 58 is formed within the insulative coating 74 above the trench 60. In the corrugated capacitor having the above mentioned structure, since the trench 60 is formed in the active region 70 of the substrate 50, a large active region is needed, and therefore, it is difficult to increase the integration density. In addition, it is necessary to provide the thick field insulator layer 72 for element isolation. Accordingly, in order to realize a large storage capacity of memory device using the corrugated capacitor cells, a memory chip will inevitably become large. Now referring to Figures 4 and 5, a one-transistor type memory cell, which embodies the present invention, is formed in a substrate 80 of semiconductor material such as a p-type single-crystalline silicon substrate. The memory cell includes one switching MOS transistor composed of a pair of n-type diffused regions 82 and 84 separately from each other to constitute source and drain regions, respectively, and to form a channel region 86 therebetween. An insulator layer 88 such as a silicon dioxide (SiO₂) layer is deposited on the diffused regions 82 and 84 and the channel region 86 therebetween, and a gate electrode 90, which also serves as a word line wiring, is formed on the silicon dioxide layer 88 above the channel region 86. Thus, one MOS transistor is formed. Further, a coating 92 of an insulator such as silicon dioxide is deposited to cover the MOS transistor, and a bit line wiring 94 is formed on the insulator coating 92 and is contacted to the diffused region 82, that is, one of source and drain regions, through a contact hole 96, which is formed in a portion of the insulator coating 92 on the diffused region 82. The switching MOS transistor thus formed is isolated from adjacent MOS transistors (not shown) of other memory cells by a vertical trench 98 of a given depth, which is formed in a rectangular shape in a plan view to surround the MOS transistor as shown in Figure 5 and to vertically downwardly extend into the substrate 80 as shown in Figure 4. This trench 98 has an inner surface coated with an insulator 100 such as silicon dioxide, and a substrate portion 102 under the trench 98 is strongly doped with p-type impurities such as boron to emphasize the p-type in that portion 102. Accordingly, this portion 102 constitutes a channel stopper. In such a trench structure, a first vertical electrode 104, 104A of for example an n-type polycrystalline silicon is formed on the insulator coating 98 of each trench side wall to substantially cover the entire of each side wall as shown in Figures 4 and 5. A insulator film 106, 106A is formed on the first vertical electrode 104, 104A and the remaining trench space is refilled with a conductive material such as an n-type polycrystalline silicon, so that a common second vertical electrode 108 is formed between the pair of first vertical electrode 104. Further, an opening 110 is formed at each upper edge portion of the trench side wall insulator coating 100 to cause an upper end portion of the first electrode 104, 104A to directly contact with an exposed substrate portion, i.e., the diffused region 84. Specifically, a contact region 112 is formed to continue the diffused region 84, that is, the other of source and drain regions and to contact the first electrode 104 through the opening 110 in the upper end portion of the insulator coating 100. In addition, a cap of insulator such as silicon dioxide is provided on the upper end of the first and second electrodes 104 and 108. Thus, one vertical storage capacitor is constituted by each first vertical electrode 104 and the common second electrode 108, and one electrode of such a storage capacitor, i.e., the electrode 104 is laterally connected to one conductive region 84 of the MOS transistor. Thus, one memory cell 200 is constituted by one MOS transistor composed of the diffused regions 82 and 84 and the gate 90 and one vertical storage capacitor formed by the vertical electrodes 104 and 108 and the insulator film 106 interposed therebetween. Additionally, another memory cell 300 is constituted by one MOS transistor including the region 84A and another vertical storage capacitor formed in the same isolation trench 98 by the vertical electrodes 104A and 108 and the insulator film 106A therebetween. In this structure, the second electrode 108 is common as one electrode of capacitors respectively incorporated in a large number of memory cells including the left and right memory cells 200 and 300 formed at opposite sides of the trench 98 as shown in Figure 4. Therefore, this common second electrode is connected to a fixed potential such as ground potential. The vertical capacitor constructed as mentioned above can have a capacitance in proportion to the length and the depth of the trench 98. Therefore, it can a sufficient charge storage capacitance by deepening the trench 98, irrespectively of the integration density. In addition, if the insulator film 106 can have the thickness of 100-150A, the vertical capacitor can be constructed without a fear of short-circuit between the capacitor electrodes 104 and 108, Accordingly, this vertical capacitor can be assembled in a trench having the width W of 1 µm or less. Thus, even if the semiconductor memory device is fabricated to have narrower trenches to realize higher integration density, the vertical storage capacitor can have a necessary capacitance which can give a sufficiently high degree of α-ray soft error immunity and which does not cause the shortage of the sensitivity of an associated sense amplifier. In addition, the left and right memory cells 200 and 300 are isolated from each other with a high reliability by means of a suitable thickness of insulator coating 100 and the strongly doped channel shopper region 102. Furthermore, the first vertical electrode 104 of the storage capacitor is connected to the diffused region 84 of the MOS transistor through the intermediary of the opening 110 formed in the insulator coating 100 on the trench side wall. Accordingly, since no vertical contact hole is required for the a above connection, it is possible to reduce the area of each memory cell without restriction given by the contact hole. In addition, since the capacitor electrodes 104 and 108 are merged in the isolation trench 98, it is not necessary to provide the conductive layers 34 and 38 above the switching transistor as shown in Figure 2. Thus, the semiconductor memory device in accordance with the present invention can have a large storage capacity at a high integration density with less possibility of interconnection wiring on the substrate by substrate surface steps. A pair of memory cells of the above mentioned structure can be manufactured in the following process. Namely, there is prepared a p-type single-crystalline silicon substrate 80 as shown in Figure 6A. A first silicon dioxide coating 120, a silicon nitride (Si₃N₄) coating 122 and a second silicon dioxide coating 124 are formed on the upper surface of the substrate 80 in the mentioned order, and then, a resist pattern 126 are deposited on the second silicon dioxide coating 124 to coat the surface excluding an area in which a trench is to be formed, as shown in Figure 6A. In this condition, the second silicon dioxide coating 124, the silicon nitride coating 122 and the first silicon dioxide coating 120 are removed by means of anisotropic etching while using the resist pattern 126 as a mask. Further, the silicon substrate 80 is also etched by anisotropic etching process using the resist pattern 126 and the second silicon dioxide coating 124 as a mask, to form a trench 98 in the silicon substrate, as shown in Figure 6B. Thereafter, the second silicon dioxide coating 124 is removed by etching, and the inner surface of the trench 98 thus formed is thermally oxidized by using the silicon nitride coating 122 as oxidation protecting mask, so that the inner surface of the trench is coated with a silicon dioxide 128. Then, boron ions are implanted to the bottom of the trench 98 by means of ion implantation method using the silicon nitride coating 122 as a mask, so that a p-type emphasized region 130 is formed in a substrate region under the bottom of the trench 98. This condition is shown in Figure 6B. Subsequently, a resist material 132 is deposited on the substrate to perfectly refill the silicon dioxide coated trench 98 and to cover the upper surface of the silicon nitride coating 122, and then, an insulative layer 134 is formed on the resist layer 132 for example by coating and drying a silicon dioxide dispersed solution. On the insulative material layer 134, there is deposited a resist pattern 136 having an opening 138 in alignment with the trench 98 and slightly larger than the trench, as shown in Figure 6C. Thereafter, the insulative material layer 134 is etched by using the resist pattern 136 as a mask, so as to form an opening 140 in the insulative material layer 134 corresponding to the opening 138 of the second resist pattern 136. Succeedingly, the resist pattern 136 and the resist materials 132 are etched by using the insulative material layer 134 as a mask, so as to perfect remove the resist pattern 136 and at the same time to remove the resist material 132 on and in the trench 98 so that the remaining resist 132A in the trench has an upper surface lower than the upper surface of the substrate 80. Thus, the trench is filled with the resist material 132A to leave the side wall 142 of the trench upper edge portion in an exposed condition and the substrate 80 is covered with the resist coating 132B having an opening 144 corresponding to but slightly larger than the trench 98, as shown in Figure 6D. In this condition, the exposed silicon dioxide coating 128 on the trench side wall is etched by using as the mask the resist materials 132A and 132B in the trench 98 and on the substrate upper surface, so that the coating 128 has an opening 146 at the upper edge portion of the trench side wall and the substrate is exposed at the opening 146, as seen from Figure 6E. Then, there are removed the remaining insulative material layer 132B on the substrate 80 and the remaining resist material 132A in the trench 98. On the whole surface of such a substrate 80, there is deposited a polycrystalline silicon layer 148 of the n-type opposite to the p-type substrate as shown in Figure 6E. This polycrystalline silicon layer 148 has a thickness not greater than one-third of the gap of the trench 98 and is directly contacted to the exposed substrate through the opening 146 formed in the upper edge of the silicon dioxide coating 128 on the trench wall. This n-type polycrystalline silicon layer 148 can be formed by growing a polycrystalline silicon layer on the substrate upper surface and the trench inner surface with chemical vapor deposition (CVD) technique, and then by diffusing n-type impurities such as phosphorus into the grown polycrystalline silicon layer with thermal diffusion method. But, in the thermal diffusion, arsenic or other n-type impurities can be used in place of the phosphorus. Further, the growth of the polycrystalline silicon layer and the succeeding thermal diffusion of n-type impurities can be replaced by a single step of growing a polycrystalline silicon in a condition including the n-type impurities by the CVD technique. Thereafter, the polycrystalline silicon 148 on the upper surface of the substrate and on the bottom of the trench is removed by a reactive sputter etching, so that a first vertical polycrystalline silicon layer 104 remains only on each side wall of the trench so as to form the first vertical electrode 104. Then, the first vertical polycrystalline silicon layer 104 is thermally oxidized to form a silicon dioxide film 150 thereon, as shown in Figure 6F. Further, a silicon nitride film 152 is deposited on the substrate 80 and the oxidized surface of the first polycrystalline silicon layer 104 by for example the CVD process. On the whole surface of the substrate thus prepared, there is deposited a polycrystalline silicon 154 of the n-type opposite to the p-type substrate so as to perfectly fill the remaining space of the trench and to coat the upper surface of the substrate, as shown in Figure 6G. For deposition of this polycrystalline silicon 154, various methods used for forming the first electrode 104 can be used. Therefore, the polycrystalline silicon 154 is doped with phosphorus or arsenic or other n-type impurities. Then, the deposited polycrystalline silicon 154 is removed from the upper surface of the substrate so that the polycrystalline silicon remains only in the trench to constitute a second vertical electrode 108. Thereafter, there is thermally oxidized an upper portion of the first and second vertical polycrystalline silicon layers 104 and 108 by using the remaining silicon nitride coating 122 on the substrate as oxidation protection mask, so that a silicon dioxide cover 156 of a substantial thickness is formed on the top end of the first and second vertical polycrystalline silicon layers 104 and 108 for protection of these vertical silicon layers, as shown in Figure 6H. At the same time, the impurities contained in the first vertical polycrystalline silicon layer 104 are diffused to the substrate 80 through the opening 146 of the insulator coating 128 on the trench inner wall, so as to form a contact region 158 in the substrate adjacent to an upper portion of the first vertical polycrystalline silicon layer 104. This contact region will be continuous to the one conductive region of the switching transistor when it is formed. In addition, the ion implanted borons under the trench bottom are also diffused in the substrate. Next. one switching MOS transistor is formed at each side of the trench 98. Namely, as shown in Figure 6I, n-type diffused regions 82 and 84 and the gate insulator film 88 are formed and a gate electrode 90 is deposited in conventional manners. At this time, the diffused region 84 is formed in an overlapped relation to the diffused contact region 158 in the substrate continuous to the upper portion of the vertical polycrystalline silicon layer 104. Thereafter, necessary wirings are made as shown in Figure 6J to complete each memory cell of the one-transistor type. In the above mentioned manufacturing process, the insulative film 106 is constituted of a double layer of two insulative materials such as a silicon dioxide layer 150 and a silicon nitride layer 152. However, the insulative film 106 can be formed of a single layer of insulative material such as silicon dioxide or silicon nitride, or a single layer of dielectric material such as tantalum oxide. In accordance with the above mentioned manufacturing process, semiconductor memory devices have been actually fabricated such that each memory cell has an area of 9 µm² and a vertical storage capacitor is formed in a trench portion of the depth 7.2 µm, the length 2 µm and the width 1 µm, by providing the insulator film 106 of the thickness 100A. As a result, the capacitance of capacitor thus formed was 50 fF. The invention has thus been shown and described with reference to specific embodiments. However, it should be noted that the invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A semiconductor memory device which includes a substrate (80) of semiconductor material, and a plurality of programmable memory cells formed on the substrate (80), each memory cell containing at least one switching transistor comprising a gate electrode (90) which is connected to a word line, said switching transistor being formed in the substrate (80) and isolated from adjacent electric components in the substrate by a trench (98) of a given depth formed in the substrate (80) at the side of the switching transistor, the trench (98) having an inner surface coated with an insulator (100), and one storage capacitor connected to the switching transistor and formed in the trench (98) at the side of the associated switching transistor, wherein said storage capacitor includes a first vertical electrode (104) provided on the insulator coated inner side wall of the trench (98) and being connected to one conductive region (84) of the switching transistor, wherein the gate electrode (90) does not overlap said first vertical electrode, wherein a vertical insulative layer (106) is provided on the first vertical electrode, and a second vertical electrode (108) is provided on the vertical insulative layer (106), characterized in that an opening (110) is formed in the insulator coating (100) on the inner side wall of the trench (98) for connecting the first vertical electrode (104) and the one conductive region (84), wherein the opening (110) is formed on the upper edge of the insulator coating (100) on the trench side wall, and is filled with a portion (112) of the first vertical electrode (104) so that the first vertical electrode (104) is ohmic-contacted to the one conductive region (84) of the switching transistor through a region of the substrate adjacent to the opening. A semiconductor memory device claimed in claim 1, wherein the trench (98) is formed to substantially surround the switching transistor, and wherein the storage capacitor is formed in a trench portion adjacent to the conductive region (84) of the switching transistor. A semiconductor memory device claimed in claim 2, wherein the trench (98) is of a rectangular shape in a plan view and wherein the storage capacitor is formed to extend over a substantial entire wall of one side of the rectangular shaped trench (98) adjacent to the conductive region (84) of the switching transistor. A semiconductor memory device claimed in claim 3, wherein the above mentioned one side portion of the trench (98) is completely refilled with the first and second vertical electrodes (104,108) and the vertical insulative layer (106) which constitute the storage capacitor. A semiconductor memory device claimed in claim 1, wherein at least one pair of adjacent memory cells include a pair of switching transistors which are isolated from each other by the trench (98) formed between the one pair of transistors, and wherein the first vertical electrode (104) is provided on each of opposite insulator coated side walls of the trench (98) and is electrically connected to one conductive region (84) of the adjacent switching transistor through an opening formed in the insulator coating on each inner side wall of the trench (98), the vertical insulative layer being provided on each of the first vertical electrodes (104) in the same trench, and a common second electrode (108) being provided between the vertical insulative layers (106), whereby one pair of vertical storage capacitors are formed in the trench between the one pair of switching transistors and each of the capacitors is associated to an adjacent one of the two transistors. A semiconductor memory device claimed in claim 5, wherein the opening (110) is formed on the upper edge of the insulator coating on each trench side wall, and is filled with a portion of the first vertical electrode so that each first vertical electrode is ohmic-contacted to the one conductive region of the adjacent switching transistor through a region of the substrate adjacent to the opening. A semiconductor memory device claimed in claim 6, wherein the trench between the one pair of switching transistors is completely refilled with the first and second vertical electrodes (104,108) and the vertical insulative layers (106) which constitute the above mentioned one pair of storage capacitors, and wherein each of the first vertical electrodes has a thickness not greater than one-third of the gap of the trench. A semiconductor memory device claimed in claim 1, wherein each switching transistor is an insulated-gate field effect transistor, one of the source and drain regions of the field effect transistor being contacted to the first vertical electrode (104) through the opening (110) formed in the insulator coating on the side wall of the trench. A semiconductor memory device claimed in claim 1, wherein the substrate of semiconductor material is of one conduction type, and therein the first and second vertical electrodes (104,108) are formed from a semiconductor material of the conduction type opposite to that of the substrate. A semiconductor memory device claimed in claim 1, wherein the substrate of semiconductor material is a p-type single-crystalline silicon substrate, and wherein the first and second vertical electrodes (104,108) are formed of n-type polycrystalline silicon which is doped with material selected from a group consisting of phosphorus and arsenic. A semiconductor memory device claimed in claim 10, wherein the insulator coating on the side wall of the trench is formed of silicon dioxide, and wherein the vertical insulative layer (106) between the first and second vertical electrodes is constituted of a silicon dioxide layer formed on the first vertical electrode (104) and a silicon nitride layer deposited on the silicon dioxide layer. A semiconductor memory device claimed in claim 11, wherein each switching transistor is an insulated-gate field effect transistor, one of the source and drain regions of the field effect transistor being contacted to the first vertical electrode through the opening (110) formed in the insulator coating on the side wall of the trench. A semiconductor memory device claimed in claim 12, further including a plurality of column lines (10) and a plurality of row lines (12) intersecting the column lines and wherein the plurality of memory cells are disposed at the intersections of the column lines (10) and the row lines (12) in such a manner that each switching field effect transistor (14) has a gate connected to the corresponding one of the row lines, and the other of the source and drain regions is connected to the corresponding one of the column (10). A method of manufacturing a semiconductor memory device according to any of the preceding claims which includes a plurality of programmable memory cells, each of which contains at least one storage capacitor and one switching transistor connected thereto, comprising the step of: Forming in a substrate (80) of semiconductor material a trench (98) having an inner surface coated with an insulator film; forming an opening (110) in the insulator coating in the proximity of the upper edge portion of the trench; depositing a conductive material on the side wall of the trench to form a first vertical electrode (104); providing a vertical insulative layer (150) on the first vertical electrode; depositing a conductive material (154) on the vertical insulative layer to fill up the remaining trench space and to form a second vertical electrode (108) which cooperates with the first vertical electrode (104) and the vertical insulative layer so as to constitute one vertical capacitor; and forming one switching transistor adjacent to the opening (110) of the insulator coating in such a manner that one conductive region (84) of the switching transistor is electrically and laterally connected to the first vertical electrode (104) through the opening (110) formed in the trench side wall insulator coating. A method claimed in claim 14, wherein before the switching transistor is formed, the substrate (80) is heated so that a portion of impurities contained in the first vertical electrode (104) is diffused to the substrate through the opening of the insulator coating on the trench inner wall so as to form a contact region in the substrate adjacent to an upper portion of the first vertical electrode, so that the diffused contact region will be continuous to the one conductive region of the switching when it is formed. A method claimed in claim 14, wherein the step of forming the opening includes: Filling the trench with a resist material (132A) while leaving the side wall of the upper edge portion of the trench in an exposed condition; forming on the upper surface of the substrate a layer of resist material (132B) having an opening corresponding to and not smaller than the trench so as to leave the upper edge portion of the trench in an exposed condition; and removing the exposed insulator film on the trench side wall by using as the mask the resist material (132A,B) in the trench and on the substrate upper surface, so that the substrate is exposed at the side wall of the upper edge portion of the trench. A method claimed in claim 16, wherein the filling of the resist material (132A,B) of the trench and the formation of the resist material layer leaving the side wall of the trench upper edge portion in the exposed condition are achieved by: Depositing the resist material on the substrate to perfectly fill the trench and to coat the overall upper surface of the substrate; depositing an insulative material (140) on the resist coating; forming on the insulative material layer a resist pattern having an opening in alignment with the trench and not smaller than the trench; removing the insulative material layer by using the resist pattern as a mask so as to form an opening in the insulative material layer corresponding to the opening of the second resist film; and removing the resist pattern and the resist materials by using the insulative material layer as a mask, so as to perfectly remove the resist pattern and at the same time to remove the resist material on and in the trench is removed with the result that the trench is filled with the resist material (132A) to leave the side wall of the trench upper edge portion in the exposed condition and the substrate is covered with the resist coating having the opening corresponding to the trench opening to leave the trench. A method claimed in claim 17, wherein before the switching transistor is formed, the substrate (80) is heated so that a portion of impurities contained in the first vertical electrode (104) is diffused to the substrate through the opening of the insulator coating on the trench inner wall so as to form a contact region in the substrate adjacent to an upper portion of the first vertical electrode, so that the contact region will be continuous to the one conductive region of the switching transistor when it is formed in the substrate. A method claimed in claim 14, wherein the substrate is a single-crystalline silicon substrate and wherein the step of forming the trench includes: Forming a first silicon dioxide coating, a silicon nitride coating and a second silicon dioxide coating on the upper surface of the substrate in the mentioned order; depositing a resist pattern on the second silicon dioxide coating excluding an area in which a trench is to be formed; etching the second silicon dioxide coating, the silicon nitride coating and the first silicon dioxide coating by using the resist pattern as a mask; also etching the silicon substrate by using the resist pattern and the second silicon dioxide coating as a mask to form a trench in the silicon substrate; removing the second silicon dioxide coating; and thermally oxidizing the inner surface of the trench thus formed by using the silicon nitride coating as oxidation protecting mask, so that the inner surface of the trench is coated with the silicon dioxide. A method claimed in claim 19, wherein the step of forming the opening in the insulator coating on the trench side wall includes: Depositing a resist material on the substrate to perfectly fill the silicon dioxide coated trench and to cover the upper surface of the silicon nitride coating; depositing an insulative material on the resist cover; forming on the insulative material layer a resist pattern having an opening in alignment with the trench and not smaller than the trench; removing the insulative material layer by using the resist pattern as a mask so as to form an opening in the insulative material layer corresponding to the opening of the second resist film; removing the resist pattern and the resist materials by using the insulative material layer as a mask, to perfect remove the resist pattern and at the same time to remove the resist material on and in the trench so that the trench is filled with the resist material to leave the side wall of the trench upper edge portion in the exposed condition and the substrate is covered with the resist coating having the opening corresponding to the trench; and removing the exposed silicon dioxide coating on the trench side wall by using as the mask the remaining resist material in the trench and on the substrate upper surface, so that the substrate is exposed at the side wall of the upper edge portion of the trench. A method claimed in claim 20, wherein the removal of the resist pattern and the resist material by using the insulative material layer as the mask is achieved by a reactive sputter etching. A method claimed in claim 20, wherein the step of forming the first vertical electrode (104) includes: Removing the remaining insulative material layer on the substrate (80) and the remaining resist material; depositing on the substrate a polycrystalline silicon of the conduction type opposite to that of the substrate so as to form on the side wall of the trench a polycrystalline silicon layer which has a thickness not greater than one-third of the gap of the trench and which is directly contacted to the exposed substrate through the opening formed in the upper edge of the silicon dioxide coating on the trench wall; and removing the polycrystalline silicon on the upper surface of the substrate and on the bottom of the trench by a reactive sputter etching so that a first vertical polycrystalline silicon layer remains only on each side wall of the trench so as to form the first vertical electrode. A method claimed in claim 22, wherein the provision of the insulative layer on the first vertical electrode (104) is realized by thermally oxidizing the surface of the first vertical polycrystalline silicon layer, and then depositing a silicon nitride film on the substrate and the oxidized surface of the first polycrystalline silicon layer. A method claimed in claim 23, wherein the step of forming the second vertical electrode (108) includes: Depositing on the surface of the substrate (80) a polycrystalline silicon of the conduction type opposite to that of the substrate so as to perfectly fill the remaining space of the trench; and removing the deposited polycrystalline silicon on the substrate so that the polycrystalline silicon remains only in the trench to constitute a second vertical polycrystalline layer for the second vertical electrode. A method claimed in claim 24, wherein before the switching transistor is formed, there is thermally oxidized an upper portion of the first and second vertical polycrystalline silicon layers by using the remaining silicon nitride coating on the substrate as oxidation protection mask, so that a silicon dioxide cover of a substantial thickness is formed on the top end of the first and second vertical polycrystalline silicon layers for protection of these vertical silicon layers, and at the same time, the impurities contained in the first vertical polycrystalline silicon layer are diffused to the substrate through the opening of the insulator coating on the trench inner wall so as to form a contact region in the substrate (80) adjacent to an upper portion of the first vertical polycrystalline silicon whereby the contact region will be continuous to the one conductive region of the switching transistor when it is formed. A method claimed in claim 25, wherein the step of forming the switching transistor includes a formation of the above mentioned one conductive region of the switching transistor in an overlapped relation to the diffused contact region in the substrate continuous to the upper portion of the vertical polycrystalline silicon.

Inventors: ISHIJIMA, TOSHIYUKI C/O NEC CORPORATION, YOSHIDA, MASAAKI C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1985
Main classification: H01L27
IPC codes: H01L27, H01L21, H01L29