VIDEO SIGNAL RECORDING AND REPRODUCING APPARATUS

Abstract: The present invention relates to a color difference signal processing circuit of a video taperecorder (VTR) by a time plex system. The color phase of the picture face is adapted not to change with variation in amplitude and variation in DC level during the reproduction of the tape recorded by the VTR.

Description: The present invention relates to a video signal recording and reproducing apparatus, wherein conversion video signals are formed, in which brilliance signals and color difference signals have been inserted in time sharing during each one horizontal period, the brilliance signals and the color difference signals being compressed in time axis through the respective time axis compressing and time-sharing inserting operations of the brilliance signals, including the synchronizing signals, and the color difference signals of the recording video signals during the recording operation. The conversion video signals are recorded on a record medium, the brilliance signals, including the synchronizing signals, and the color difference signals of the video signals reproduced from the record medium are respectively extended in time axis during the reproducing operation. The brilliance (or luminance) signals, the color difference signals which are the same in the time axis as the brilliance signals, the color difference signals of the recording video signals are respectively reproduced and formed during each one horizontal period so as to effect the outputting operation. Conventionally in a video tape recorder of a timeplex system which is one example of this type of video signal recording and reproducing apparatus, the brilliance signal of each one horizotal period (hereinafter the horizontal period is referred to as H) including the synchronizing signal of the video signal to be recorded is compressed in time axis to 4/5 during the recording operation, two types of color difference signals of R-Y, B-Y (R; red color signal, B; blue color signal, Y; brilliance signal) of the video signal to be recorded are compressed in time axis to 1/5 alternately for each 1H. In addition, conversion video signals, in which the brilliance signal compressed in time axis to 4/5 and the color difference signal of the R-Y or B-Y compressed in time axis to 1/5 are inserted in time sharing in each 1H, i. e., timeplex signals are formed through the time-sharing inserting operation of the brilliance signal compressed in time axis to 4/5 and of the color difference signal of the R-Y or B-Y compressed in the time axis to 1/5. The timeplex signals are recorded on the tape which is a record medium. Also, during the reproducing operation, the brilliance signal, the color difference signal, compressed in time axis, of the video signals obtained by the reproduction of the tape, namely, the reproduction time plex signals which are the reproduced video signals are respectively extended in the time axis. The brilliance signal, the color difference signal which are the same in the time axis as the brilliance signal, the color difference signal of the recording video signals are respectively reproduced and formed in each 1H to perform the outputting operation. And the above described time axis compression and time sharing inserting operation, time axis extending operation are digitally performed by the use of A/D converter, memory, D/A converter, etc. In this case, an analog filter or the like is not used as in the conventional video tape recorder so that no interference is provided between the brilliance signal and the color difference signal so as to improve the S/N and resolving degree of the color recording and reproducing. When the digital time-axis compressing operation is performed, the brilliance signal and the color difference signal are respectively converted in A/D generally in accordance with a given speed of clock signal, the brilliance, the chroma data provided by the A/D conversion are respectively written in the memory and are once retained. The brilliance, chroma data are respectively read from the memory in accordance with the clock signal of a speed higher than the given speed and are converted in the D/A to provide the brilliance signal and the color difference signal compressed in time axis with a compression rate established by the speed difference between the stored clock signal of the memory and the reading clock signal. And in a video tape recorder of the above described time plex system, the brilliance signal, the color difference of each 1H of the video signals to be recorded by the clock signals of 16 MHz, 4 MHz during the recording operation are respectively converted in A/D to respectively form the brilliance data, the chroma data. The brilliance data of each 1H are stored in a random access memory (hereinafter referred to as RAM) on the brilliance side by the clock signal of 16 MHz. And the chroma data of the R-Y or the B-Y of each 1H is stored for each 1H in the RAM on the chroma side by the clock signal of 4 MHz. It is to be noted that the chroma data of the R-Y, B-Y of each 1H in the video signal to be recorded are stored, in the RAM on the chroma side, alternately for each 1H. In addition, the RAM on the side of the brilliance is read by the clock signal of 20 MHz. The time-axis compressing operation is effected, at a ratio between the storing clock signal of the RAM on the brilliance side and the reading clock signal. The time axis of the brilliance signal of the video signal to be recorded is compressed into the 4/5. Also, the RAM on the chroma side is read by the clock signal of 20 MHz after the storing operation. The time-axis compressing operation is effected, at a ratio between the storing clock signal of the RAM on the side of the chroma and the reading clock signal, and the time axis of the color difference signal in the video signal to be recorded is compressed into the 1/5. It is to be noted that the reading operation of the chroma data becomes a blanking period of the brilliance signal and the brilliance data, the chroma data are sequentially read in each 1H. And the brilliance data, the chroma data which have read in each 1H and the achromatic level data secured to the level of 50 IRE are composed by the time-sharing inserting operation, in the order of the brilliance data, the achromatic level data, the chroma data and are converted in the D/A by the clock signal of 20 MHz. And the brilliance signal of 1H, which has been compressed in time axis 4/5, the achromatic level signal, and the color difference signal of R-Y or B-Y compressed in time axis to 1/5, have been inserted in time sharing in each 1H, so the timeplex signal is formed. It is to be noted that the formed time plex signal is compressed in time axis even in the synchronizing signal portion of the brilliance signal. The waveform of the vertical synchronizing signal portion becomes one wherein the achromatic level signals of 50 IRE are piled up, as shown in Fig. 7, respectively for a horizontal synchronizing pulse period, an equivalent pulse period, a vertical synchronizing pulse period. The reference character 0 in the drawing shows a pedestal level. On the other hand, the digital time axis extending operation is required to be processed reversely to the time axis compressing operation. In the case of the video tape recorder or a time plex system, the brilliance signal, the color difference signal, compressed in time axis, of regenerative time plex signals are respectively converted in the A/D by the clock signal of 20 MHz and thereafter are stored respectively in the RAM on the brilliance side and in the RAM on the chroma side by the clock signal of 20 MHz. Furthermore the RAM on the side of the brilliance is read by the clock signal of 16 MHz, the RAM on the chroma side is read by the clock signal of 4 MHz, the data which has been read from both the RAMs are respectively converted in the D/A, and the time axis of the brilliance signal, the color difference signal to be converted in A/D are respectively extended into 5/4, 5 times. The brilliance signal, the color difference signal which are the same in the time axis as the brilliance signal, the color difference signal of the video signals to be recorded are reproduced and formed in each 1H. The various timings such as the storing and reading timings in the RAMs on the brilliance side, the chroma side during the recording time and the reproducing time are determined with the respective horizontal synchronizing signals of the recorded video signal, the reproduced video signal as a reference. In the case, the various clock signals such as clock signals of both the RAMs are formed in correctly synchronous relation with the phases of the respective horizontal synchronizing signal of the recorded video signal and the reproduced video signal. The variable control operation is required from 16 MHz or 4 MHz to 20 MHz, from 20 MHz to 16 MHz or 4 MHz at a given timing with the horizontal synchronizing signal as a reference. There is a time plex system as one of the recording systems of picture signals. In this system, the brilliance signal of such as SECAM, PAL signals is compressed in time axis to 4/5 or the color difference signal is compressed in time axis to 1/5 so that both the signals are inserted within one horizontal period at the time sharing, are FM modulated and are recorded on the magnetic tape. It is to be noted that this time plex system is described at page 134 through page 138 of November issue, 1983 in Radio Wave Science (Japanese Broadcast Publication Association Issue). However, in the above-described conventional example, the level of the color difference signal to be obtained changes, when the signal during the reproduction is different in amplitude, DC level from during the recording operation, to change the color phase of the reproduction picture face. And the Radio Wave Science, November 11, 1983 describes the provision of a digital synchronism detaching circuit in its page 134 through page 138 for the recording, reproducing operations of the above-described time plex system. In this case, the horizontal, vertical synchronizing signal is detected to perform the synchronizing detaching operation, from the digital conversion signals of the brilliance signals among the video signals to be recorded, the video signals reproduced, by the digital synchronism detaching circuit. The various clock signals such as clock signals on the RAMs on the brilliance side, the chroma side in accordance with the horizontal synchronizing signal obtained by the synchronism detachment. When the horizontal, vertical synchronizing signals are detected from the digital conversion signals of the brilliance signals of the video signals to be recorded, the reproduced video signals and are detached in synchronism by the use of the digital synchronism detachment circuit, the sampling space of the A/D conversion for forming the digital conversion signal is limited. In this case, one sampling space, i. e., about one clock period of detection timing shift may be cause for each 1H. And the detection timing shift varies the edge of the synchronizing signal to be detached in synchronism and changes in the edge varies the clock signal. Furthermore, when the color difference signal is sampled with 4 MHz in this circuit construction, the stage of the shift register becomes 52 µs ÷ 1/4 MHz = 208, when the scanning period is 52 µs, thus requiring 208 stages. As the quantization number of the color difference signal is generally 6 bits, a shift register of a great number of elements is required in such a circuit construction thus resulting in higher circuit cost, more consumption power. An apparatus which additionally comprises an analog synchronism detaching circuit and an indicating signal indicating the type of the color difference signal, and which represents an apparatus according to the preambel part of claim 1 is known from US-A-4 335 393. However, even in this apparatus the above-mentioned drawbacks are present. It is therefore the object of the invention to provide a video signal recording and reproducing apparatus having a colour signal processing circuit which is inexpensive and which has less power consumption. This object is achieved by a video signal recording and reproducing apparatus, the brilliance signals, including the synchronizing signal, and the color difference signals of said video signal to be recorded during the recording operation are respectively compressed in time axis and inserted in time sharing, in accordance with clock signals controlled in synchronous relation with the phases of the synchronizing signals of the video signals to be recorded to form a conversion video signal into which the brilliance, either a first color difference signal or a second color difference signal, and an indication signal for indicating the kinds of said color difference signal have been inserted in time sharing in each 1 horizontal period and to record said conversion video signal on the recording medium, the brilliance signals, including the synchronizing signal, and the color difference signals of said reproduced video signal which has been provided by the reproduction of said medium during the reproducing operation are respectively extended in time axis, in accordance with clock signals controlled in synchronous relation with the phases of the synchronizing signals of the reproduced video signals, the brilliance signals, the color difference signals which are the same in time axis as the brilliance signals, the color difference signals of said video signals to be recorded are respectively reproduced in each 1 horizontal period and are outputted, including a color difference signal processing, which comprises an A/D converter for inputting the reproduced video signalsfurther comprising a latch circuit (31) for recording the achromatic signals level of said A/D converter output and a subtracting circuit (32) for providing the difference between said A/D converter output and said latch circuit output as a color difference signal processing circuit, wherein the output of said latch circuit (31) is adapted to latch A/D conversion output at the timing of a certain period from the leading edge of the horizontal synchronizing signal by a controlling signal (M). Also an analog synchronism detaching circuit, instead of the digital synchronism detaching circuit, is used so that the respective horizontal, vertical synchronizing signals of the video signals to be recorded, the reproduced video signals are detected without being converted in A/D. In this case, the shift of the detection timing because of the sampling interval when the digital synchronism detaching circuit is used is prevented from being caused. On the other hand, in a case where the analog synchronism detaching circuit is simply provided, it becomes difficult for the reproduction time plex signal such as the reproduced video signal to detect the horizontal, vertical synchronizing signals and to detach them in synchronism during the reproducing operation, because the achromatic level signals are piled upon the vertical synchronizing signal portion, as referred to Fig. 7. However, in this invention, the time axis compressing and the time-sharing inserting of the vertical synchronizing signal portion of the brilliance signal of the video signals to be recorded are stopped during the recording time, and the brilliance signal of the video signals to be recorded is outputted as it is so that the vertical syncronizing signal of the conversion video signal is formed by the vertical synchronizing signal portion of the video signal to be recorded. In this case, the horizontal, vertical synchronizing signals are correctly detected by the analog synchronism detaching circuit during the reproducing operation to perform the synchronism detachment. As the horizontal, vertical synchronizing signals of the video signals to be recorded by the use of the analog synchronism detaching circuit, the reproduced video signals are detected correctly and stably without detection shift, the edges of the horizontal, vertical synchronizing signals detached in synchronism are prevented from being varied. The clock signals to be used in the time axis compressing and time-sharing inserting operations during the recording operation, the time-axis extending operation during the reproducing operation are controlled in synchronism by the phase of the horizontal synchronizing signal detached correctly and stably in synchronism and are variably controlled, and the time-axis compressing and time-sharing operations during the recording operation, the time-axis extending operation during the reproducing operation are correctly and stably performed. Furthermore, the present invention is characterized in that in a color signal processing circuit wherein the two color difference signals of the color signal into which two color difference signals compressed in a given period with the horizontal synchronizing signal as a time reference are alternately inserted for each 1H, an indicating signal which indicates the type of the color difference signal is also inserted are rendered simultaneous and processed, two memories, a first memory for storing a first color difference signal and a second memory for storing a second color difference signal, are used, a linearly subsequent compression color different signals are alternately stored in these memories at a high speed for each 1H by the output of a means for identifying the type of the color difference signal of the line, the low speed reading of two memories are simultaneously performed to render the color difference simultaneous. The objects and features of the present invention will become apparent from the following description taken in conjunction with the preferred embodiment thereof with reference to the accompanying drawings in which; Fig. 1 through Fig. 3 show one embodiment of a video signal processing apparatus of the present invention, Fig. 1 is a block diagram, Fig. 2 is a detailed block diagram of one portion of Fig. 1, Fig. 3(a) through (g) are timing charts for describing the operation of Fig. 2, Fig. 4 is a waveform chart showing a time plex signal waveform, Fig. 5 is a block diagram showing the modified example of Fig. 1, and Fig. 6 is a detailed block circuit diagram of the block of Fig. 5. Fig. 7 is a waveform chart showing a vertical synchronizing signal portion of a conventional time plex signal waveform. Before the description of the present invention proceeds, it is to be noted that like parts are designated by like reference numerals throughout the accompanying drawings. The present invention will be described in detail with reference to Fig. 1 through Fig. 4 showing one embodiment. During the recording operation, the brilliance signals (hereinafter referred to as record brilliance signal) including the synchronizing signal of the video signals to be recorded as shown in Fig. 1 are inputted into an analog synchronism detaching circuit 3 and an A/D converter 4 on the side of the brilliance through the record contact r of a record rechange-over first switch 2 from the brilliance input terminal 1. Also, the color difference signals (hereinafter referred to as record color difference signals of R-Y, B-Y) of R-Y, B-Y of the video signals to be recorded are respectively inputted into a pair of contacts a, b of the chroma change-over switch 7 through the first, second chroma input terminals 5, 6. At this time, the switch 7 is alternately switched into contacts a, b for each 1H of the video signals to be recorded, so that the record color difference signals of R-Y, B-Y through the switch 7 are alternately inputted for each 1H into the A/D converter 8 on the side of the chroma. And the horizontal, vertical synchronizing signals of the video signals to be recorded by the synchronism detaching circuit 3 are detected without the A/D conversion and are detached in synchronism. The horizontal synchronizing signals provided by the synchronism detachment are outputted into a prohibition gate signal forming circuit 9 and a clock controlling circuit 10 from the synchronism detaching circuit 3 and composite synchronizing signals with the horizontal, vertical synchronizing signals being mixed therein are outputted into a framing circuit 9. Furthermore, the framing circuit 9 is composed as shown in Fig. 2, the horizontal synchronizing signal from the synchronism detaching circuit 3 shown in Fig. 3(a) is inputted into a first monomulti 9a, the monomulti 9a is triggered by the falling of the horizontal synchronizing signal so that a first monomulti pulse of a period Ma, which is longer than 1 H/2 and shorter than 1H from the falling of the horizontal synchronizing signal is outputted from the monomulti 9a to an AND circuit 9b. Also, a composite synchronizing signal from the synchronism detaching circuit 3 shown in Fig. 3(c) is inputted into the AND circuit 9b, the logical product of the first monomulti pulse and the composite synchronous signal is operated by the AND circuit 9b, an AND gate signal wherein the pulse of the logic 1 (hereinafter referred to as "1") exists only during an equivalent pulse period and a vertical synchronizing pulse period as shown in Fig. 3d is outputted from the AND circuit 9b to a second monomulti 9c which can be retriggered. It is to be noted that the composite synchronizing signal is composed of a vertical synchronizing pulse period in which six wide vertical synchronizing pulses for each 0.5 H, exists, front, rear equivalent pulse periods of a vertical synchronizing pulse period in which the narrow six equivalent pulses for 0.5 H, a horizontal synchronizing pulse period in which the horizontal synchronizing pulse for each 1H exists during each 1 vertical period, the vertical synchronizing signal is formed of each vertical synchronizing pulse of the vertical synchronizing pulse period, the horizontal synchronizing signal of Fig. 3(b) is formed of the pulse for each 1H of each pulse period, Fig. 3(c) shows a vertical synchronizing pulse period portion. Also, the AND gate signal to be inputted to a second monomulti 9c becomes 1H or lower in pulse space in the equivalent pulse period and the vertical synchronizing pulse period. And the second monomulti 9c is triggered for each rise of the AND gate signal. As at this time, the metastable period of the second monomulti 9c is set in a period a little longer than 1H, a second monomulti pulse, in which "1" is provided during a time period, as shown in Fig. 3(e), from a time ta when an AND gate signal rises at first to a time tc after the metastable period of the second monomulti 9c from the lastly rising time tb, is outputted to a gate signal outputting circuit 9d from the second monomulti 9c. In addition, a timing signal from a clock controlling circuit 10, i. e., a take-in start timing signal, which is a horizontal synchronizing signal, of Fig. 3(a), reversed as shown in Fig. 3(f), is inputted, together with the second monomulti pulse, into a gate signal outputting circuit 9d. A prohibition gate signal, in which "1" is provided for a period from the falling of the take-in start timing signal next to the rising of the second monomulti pulse to the falling of the take-in start timing signal next to the falling of the second monomulti pulse, that is to say, only during a prohibition period which prohibits the compression, extension to a time ty after the time tc from a time tx after the time ta as shown in Fig. 3(g), is formed by the outputting circuit 9d. The prohibition gate signal is outputted from the output circuit 9d to the control circuit 10. It is to be noted that the take-in start timing signal is a signal showing a start timing of the compression, extension. A period of the compression, the extension is set by the time from the rising of the leading edge of the horizontal synchronizing signal. Also, the prohibition gate signal becomes "1" in the vertical synchronizing signal portion composed of an approximate vertical synchronizing pulse period and the front, rear equivalent pulse period of the period. And a controlling circuit 10 is provided with a PLL controlling circuit and so on, to which a horizontal synchronizing signal is inputted, to form the various clock signals synchronized with the phase of the horizontal synchronizing signal. A clock signal of 16 MHz is outputted into an A/D converter 4 and a clock signal of 4 MHz is outputted into an A/D converter 8. It is to be noted that a clock signal for changing over a switch 7 is also formed by the controlling circuit 10. The switch 7 is changed over by the clock signal. The record brilliance signal is converted in A/D with a sampling frequency of 16 MHz by the A/D converter 4. The digital data of the record brilliance signal, i. e., the record brilliance data are outputted into first, second RAMs 11, 12 on the side of the brilliance and an input switching circuit 13 from the A/D converter 4. Also, the record color difference signals of R-Y, B-Y are alternately converted in A/D with the sampling frequency of 4 MHz by the A/D converter 8. The digital data of the record color difference signal of the R-Y, B-Y, i. e., the record chrome data are alternately outputted into the input switching circuit 13. And the input switching circuit 13 selectively outputs the data of the A/D converter 8 during the recording operation in accordance with the mode signal from a system controlling circuit through a switch signal input terminal 14. Accordingly, the record chroma data of the A/D converter 8 are outputted into the first, second RAMs 15, 16 on the chroma side through the input switching circuit 13 during the recording operation. And the clock signals from the controlling circuit 10 are respectively inputted into the first, second RAMS 11, 12 on the brilliance side and the first, second RAMs 15, 16 on the chroma side. During the recording operation, the first, second RAMs 11, 12 on the side of the brilliance are reciprocally controlled into store and read for each 1H, and the first RAM 15 on the side of the chroma is controlled alternately into the store and the read during the 1H. The controlling circuit 10 varies the clock signals outputting into the first, second RAMs 11, 12 to 16 MHz when stored, to 20 MHz when read while the prohibition gate signal during the recording operation is a logic 0 (hereinafter referred to as "0"), i. e., during the non-output period of the prohibition gate signal, and varies the clock signal outputting into the first RAM 15 on the side of the chroma to 4 MHz when stored, to 20 MHz when read. And the record brilliance data compressed in time axis to 4/5 are alternately read for each 1H from the first, second RAMs 11, 12, the record chrome data compressed in time axis to 1/5 are read during a blanking period of the record brilliance signal. In addition, the record brilliance data alternately read from the first, second RAMs 11, 12 on the side of the brilliance and the record chroma data read from the first RAM 15 on the side of the chroma are inputted into an output switching circuit 17, and the achromatic level data of 50 IRE from the achromatic level producing circuit 18 are inputted into the output switching circuit 17. It is to be noted that the achromatic level data are the achromatic signals of the 50 IRE. Also, a pair of output signals of a ternary counter 19 are inputted into the output switching circuit 17 and digital control signals from the controlling circuit 10 are inputted into the counter 19. And the counter 19 becomes 0 in its digital contents while the record brilliance data are outputted in a non-output period of the prohibition gate signal in accordance with a digital control signal, becomes 1 in its digital contents in a period from the output completion of the record brilliance data to the start of the output of chroma data, and becomes 2 in its digital while the record chroma data. Also, the output switching circuit 17 selectively outputs the data read from the first, second RAMs 11, 12 on the side of the brilliance while the digital contents of the counter 19 are 0 in accordance with a pair of digital control signals of the counter 19, selectively outputs the achromatic level data while the digital contents of the counter 19 are 1, and selectively outputs the data read from the first RAM 15 on the side of the chroma while the digital contents of the counter 19 are 2. And during the non-output period of the prohibition gate signal during the recording operation, the record brilliance data, the achromatic data, the record chroma data respectively compressed in the time axis are sequentially outputted for each 1H into a common-use D/A converter 20 from the output switching circuit 17. At this time, the D/A converter 20 converts in D/A the record brilliance data, the achromatic data, the record chroma data in accordance with the clock signal of 20 MHz outputted from the control circuit 10, compresses the record brilliance signal in time axis to the 4/5 from the D/A converter 20, compresses the record color difference signals of R-Y, B-Y in the time axis to 1/5, and a conversion video signal, i. e., a time plex signal similar to the conventional one is outputted, the conversion video signal into which the record brilliance signal of 1H compressed in time axis to 4/5 and the color difference signal of R-Y or B-Y compressed in time axis to 1/5 have been inserted in time sharing for each 1H. As the time plex signal of the D/A converter 20 is inputted into a record rechange-over second switch 21, and the second switch 21 is changed over into a record contact r during the recording operation, the time plex signal of the second switch 21 is inputted into an FM modulator 22 through the complex r. The time plex signal is modulated in FM because of the record by the modulator 22 and a modulation time plex signal which is an FM modulated time plex signal is outputted into the tape 24, which is a record medium, through a record amplifier 23 from the modulator 22 so that the modulated time plex signal is recorded on the tape 24. The changes, with respect to the frequency 20 MHz, of the clock signal to be outputted to the first, second RAMs 11, 12 on the side of the brilliance during the reading operation in the controlling circuit 10 are controllingly prohibited in a period of the vertical synchronizing signal portion during which a prohibition gate signal of "1" is outputted, i. e., in an output period of the prohibition gate signal. The frequency of the clock signal to be outputted to the first, second RAMs 11, 12 on the side of the brilliance is controlled by 16 MHz which is a stop frequency of the time axis compression and the time sharing, i. e., by the frequency of the clock signal of the A/D converter 4 during the writing operation and the reading operation, and the digital instruction signal to be outputted into the counter 19 is controlled by a reset signal of the digital contents. The time axis compressing operation of the record brilliance data by the first, second RAMs 11, 12 is stopped during the outputting period of the prohibition gate, the record brilliance data of the time axis non-compression are outputted into the output switching circuit 17 from the first, second RAMs 11, 12, the output switching circuit 17 is retained by the selection outputs of the first, second RAMs 11, 12 in accordance with the reset of the counter 19 to stop the time sharing, the record brilliance data of the non-compression are outputted into the D/A converter 20 from the output switching circuit 17, the record brilliance signal inputted into the A/D converter 4 is outputted as it is from the D/A converter 20. And as the record brilliance signal, during the output period of the prohibition gate signal, becomes the signal of the vertical synchronizing portion of the video signal to be recorded, i. e., the signal of the vertical synchronizing pulse, the equivalent pulse, the time plex signal is formed of the signal of the vertical synchronizing signal portion of the video signal to be recorded during the output period of the prohibition gate signal. Accordingly, the vertical synchronizing signal portion of the video signal to be recorded is recorded, as it is, on the tape 24 in its non-compression, and the portion except for the vertical synchronizing signal portion is recorded by the time-axis compressing and the time sharing operations of the record brilliance signal and the record color difference signal as before. Then, the reproduction will be described hereinafter. The reproduction signal of the tape 24 is inputted into an FM demadulator 26 through a reproduction amplifier 25. The reproduced video signal to be provided by the FM demodulation of the reproduction signal is outputted into the reproduction contact p of a first switch 2 from the demodulator 26. As the first switch 2 is changed over into a reproduction contact p at this time, the reproduced video signals are inputted into the synchronism detaching circuit 3 and the A/D converter 4. And the synchronism detachment is performed as the horizontal, vertical synchronizing signals of the video signals reproduced by the synchronism detaching circuit 3 are detected. The vertical synchronizing portion of the video signals reproduced at this time becomes the same in waveform as the vertical synchronizing portion of the record brilliance signal, i. e., the same in waveform as the vertical synchronizing signal portion of the normal video signal. Accordingly the edge of the vertical synchronizing signal is detected by the synchronism detaching circuit 3 to allow the horizontal, vertical synchronizing signals to be detected and to be detached in synchronism. In this case, the horizontal, vertical synchronizing signals may be correctly and stably detached in synchronism without causing the shift in such a detection timing as in the use of the digital synchronism detaching circuit. And a horizontal synchronized signal detached in synchronism by the synchronism detaching circuit 3, i. e., the horizontal synchronizing signal of the video signal reproduced is inputted into the controlling circuit 10, and a composite synchronizing signal and a horizontal synchronizing signal of the reproduced video signals are outputted into a framing circuit 9 from the synchronism detaching circuit 3. Although the brilliance signal of the reproduction video signal is compressed in time axis to 4/5, the horizontal synchronizing signal becomes the same in the pulse distance as during the record period, because only the brilliance signal of 1H exists for each 1H. Furthermore, the framing circuit 9 operates as in the recording operation to output into a controlling circuit 10 a prohibition gate signal, which becomes "1" in the vertical synchronizing signal portion of the reproduced video signal. And the controlling circuit 10 forms various kinds of clock signals which are synchronized in phase with the inputted horizontal synchronizing signals and turns into 20 MHz the clock signals, to be outputted into the A/D converter 4, while the prohibition gate signal is "0", i. e., during a non-output period of the prohibition gate signal. Accordingly, the reproduced video signal is sampled at the same sampling speed as in the D/A conversion of the D/A converter 20 during the recording operation and is converted in A/D. The reproduction brilliance data, the achromatic level data, the reproduction chroma data, which all data are respectively similar to the record brilliance data, the achromatic level data and the record chroma data to be inputted into the D/A converter 20 during the recording operation, are outputted into the first, second RAMs 11, 12 on the side of the brilliance, and the input switching circuit 13 for each 1H in the same sequence as during the recording operation. And as the input switching circuit 13 selectively outputs the data of the A/D converter 4 in accordance with a mode signal through an input terminal 14 during the reproducing operation, the data similar to those inputted into the first, second RAMs 11, 12 on the side of the brilliance are inputted even into the first, second RAMs 15, 16. In addition, the first, second RAMS 11, 12 on the side of the brilliance are controlled, reciprocal to the storing, reading operations for each 1H of the reproduced video signal, the clock signal from the controlling circuit 10 becomes 20 MHz only during the 4/5 period of each 1H, during which the brilliance data are inputted, in each 1H controlled in the storing operation. The clock signal from the controlling circuit 10 is varied into 16 MHz in each 1H controlled in the reading operation. Also, in the first, second RAMs 15, 16 on the side of the chroma, the clock signals to be inputted from the controlling circuit 10 become 20 MHz alternately for each 1H only in a period, in which the chroma data of each 1H of the reprocuced video signal are inputted, and the clock signals to be inputted in the other period are varied into 4 MHz. In the first, second RAMs 11, 12 on the side of the brilliance, the reproduction brilliance data are alternately stored for each 1H, the stored reproduction brilliance data are alternately extended into 5/4 for each 1H and are read, and the reproduction brilliance data extended in time axis, i. e., in the same time axis of the record brilliance data outputted from the A/D converter 4 during the recording operation, are alternately outputted into the output switching circuit 17 from the first, second RAMs 11,12. Also, in the first, second RAMs 15, 16 on the side of the chroma, the reproduction chroma data are altenately stored for each 1H and the chroma data stored are extended five times as much and are repeatedly read two times during the 2H. At this time, the reproduction chroma data of the R-Y in accordance with the color difference signal of such as R-Y is stored in the first RAM 15, the reproduction chroma data of the B-Y in accordance with the color difference signal of such as B-Y are stored in the second RAM 16. And the reproduction chroma data of the R-Y, B-Y extended in the time axis, i. e., in the same time axis of the record chroma data outputted from the A/D converter 8 during the recording operation, are repeatedly outputted twice respectively into the first, second D/A converters 27, 28 on the side of the chroma from the first, second RAMs 15, 16. The digital contents of the counter 19 is retained at 0 in accordance with the digital instruction signal during the reproduction operation, the output switching circuit 17 is retained at the selection output of the data read from the first, second RAMs 11, 12 on the side of the brilliance side and the reproduction brilliance data read from the first, second RAMs 11, 12 are inputted into the D/A converter 20. And the clock signal to be outputted into the D/A converter 20 from the controlling circuit 10 is controlled at 16 MHz during the reproduction time, the frequency of the clock signal to be outputted into the D/A converters 27, 28 from the controlling circuit 10 is controlled at 4 MHz. Accordingly, a reproduction brilliance signal which is the same in the time axis as the record brilliance signal is reproduced and is outputted into the second switch 21 from the D/A converter 20. As the second switch 21 is switched into a reproduction contact p at this time, the reproduction brilliance signal of the D/A converter 20 is outputted from the reproduction contact p of the second switch 21. Also, the reproduction color difference signals of the R-Y, B-Y which are the same in the time axis as the record color difference signals of the R-Y, B-Y are reproduced and outputted from the D/A converters 27, 28. Namely, in the example, the time axis compressing and the time-sharing inserting operations of the record brilliance signal and the record color defference signal are respectively performed as in the video taperecorder of the conventional time plex system during the non-output period of the prohibition gate signal during the recording operation in accordance with the various clock signals to be outputted from the controlling circuit 10 by a signal processing unit 29, which is composed of the A/D converters 4, 8, the first, second RAMs 11, 12 on the side of the brilliance, the switching circuit 13 on the side of the input, the first, second RAMS 15, 16 on the side of the chroma, the output switching circuit 17, the D/A converters 20, 27, 28, and so on. The time axis compressing and time-sharing inserting operations are stopped during the output period of the prohibition gate signal during the recording operation, and the conversion video signal, which is formed by stop-operation for compressing the time axis and inserting the time sharing only on the vertical synchronizing portion of the video signal to be recorded, is recorded on the tape 24. The brilliance signal, the color difference signal of the video signal reproduced from the tape 24 are extended in time axis as in the video taperecorder of the conventional time plex system during the non-output of the prohibition gate signal in the reproduction time, and the extending operation on the time axis is stopped during the output period of the prohibition gate signal in the reproduction time to reproduce and form, respectively for each 1h, the reproduction brilliance signal, the reproduction color defferece signal which are the same in the time axis as the record brilliance signal, the recored color difference signal. As the inserting operation is effected into the conversion video signal to be recorded on the tape 24, as it is without the time-axis compressing and time-sharing inserting operations only on the vertical synchronizing signal portion of the record brilliance signal, the vedeo signal to be recorded and the video signal reproduced are detached in analog synchronism without being converted in A/D. Thus the horizontal, vertical synchronizing signals can be detected correctly and stably without the shift of the detection timing, by the synchronism detaching circuit 3, to allow the synchronism detachment to be performed. In this case, changes in the edge of the horizontal synchronizing signal to be inputted into the controlling circuit 10 are not caused. Each clock signal to be outputted into the signal processing unit 29 from the controlling circuit 10 is controlled in synchronous relation with the phase of the horizontal synchronizing signal which is correctly and stably detached in synchronism and is variably controlled so that the time axis compressing and time sharing operations during the recording operation, the time axis extending operation during the reproducing operation are correctly and stably performed. An achromatic signal level latch circuit 31 is adapted to latch A/D conversion output at the timing of t2 + (TA2/2) from the leading edge of the horizontal synchronizing signal by a controlling signal M. A subtracting circuit 32 is adapted to subtract the digital output of the latch circuit 31 from the digital output of the A/D converter 4. Further detailed description will be given in accordance with the time plex signal of Fig. 4. The linear consecutive signals of R-Y and B-Y are compressed in time axis and are piled upon the level of 50 IRE of the brilliance signal including the synchronizing signal. An achromatic signal, which is to identify the B-Y/R-Y, is inserted before the color difference signal, the level being also 50 IRE. And, in Fig. 4, E1, E2 are respectively indicating signals representing the kind of color difference signals which are inserted into lines, Y1, Y2 are brilliance signals, respectively, and S1, S2 are respectively R-Y and B-Y signals. An achromatic signal of a period from the time t1 to the TA1 is inserted from the leading edge of the horizontal synchronizing signal into the position before the compressed R-Y signal and an achromatic signal of the TA2 period from a time t2 (t2>t1) is inserted from the leading edge of the synchronizing signal into the position before the compressed B-Y signal. It is to be noted that there is the relationship of t1 + TA1 = t2 + TA2 . And the detection of the B-Y/R-Y is performed by either 50 IRE or 0 IRE in the level of the timing of the (t1 + t2)/2 from the leading edge of the synchronizing signal. The reproduced color difference signal is extended in time axis and the level of the 50 IRE portion is subtracted into the original color difference signal. At this time, the addition and the subtraction of the level of the 50 IRE portion are performed by the addition and the subtraction of the fixed digital value of the 50 IRE portion from the A/D converted color difference signal. In the recording, for instance, by means of the DC offset circuit 34, as shown in Fig. 6, the level of 50 IRE is added to the output of A/D converter 8. This is because the digital value of the 50 IRE portion is determined if the input amplitude and the DC level of the A/D converter are provided. According to the present invention, the digital value after the A/D conversion corresponding to the achromatic signal to be inserted during the recording operation is latched by a latching circuit 31. The digital value corresponding to this achromatic signal is subtracted, by a subtraction circuit 32, from the digital value of the time plex color difference signal. The correct color difference signal is guided by the extension on the time axis. Namely, the output of the subtraction circuit 32 is stored, by the clock of 20 MHz, in the RAMs 15, 16 and is read by the clock of 4 MHz to perform the extending operation on the time axis. Also, the controlling circuit 10 frames the control signal M in accordance with the horizontal synchronizing signal from the synchronism detecting circuit 3, and frames the clock of the A/D converter 4, the clock of the RAMs 15, 16. The reproduction time plex signal inputted into the terminal 1 is converted into the digital value by the A/D converter 4. As the output of the A/D converter 4 is latched at the timing of t2 + (TA2/2) from the leading edge of the horizontal synchronizing signal in Fig. 4 in the latching circuit 31, the level of the achromatic signal immediately before the R-Y signal and B-Y signal is adopted to be correctly memorized. The time plex signal to be inputted into the A/D converter 4 has some fear of bringing amplitude changes and DC level changes, as described hereinabove, during the reproduction operation. For example, the output of the A/D converter 4 is in the range of the (+ xc + xg + Δx) through (-xc + xg + Δx), xg being a digital value corresponding to 50 IRE. As the output existed in the range of the (+ xc + xg) through (- xc + xg) during the recording operation, the error of (+ Δx) is caused. On the other hand, the output of the latching circuit 31 also receives the changes likewise so that the output becomes (xg + Δx). As the output of the latching circuit 31 is subtracted from the output of the A/D converter 4 in the subtraction circuit 32, the change portion (+ Δx) is offset. The output of the subtractor 32 exists in the range of (+ xc) through (- xc), thus resulting in the non-occurrence of the color phase error. Namely, the digital value after the A/D conversion of the achromatic signal changes because of changes in the amplitude and the DC level of the time plex signal to be inputted by the A/D converter during the reproduction operation. As the level of the achromatic signal is set in the level of the 50 IRE portion, the latch level of the achromatic signal is subtracted from the digital value of the time plex color difference signal so that the changes in the amplitude, the DC level during the reproduction operation are offset. As described hereinabove, according to the present invention, the color phase of the reproduction picture face does not change because of the DC level changes, the amplitude changes of the time plex signal, thus resulting in better effect. As shown in Fig. 1, the output (+ xc through - xc) of such a subtractor 32 is inputted into the input switching circuit 13 disposed in front of the first RAM 15 and the second RAM 16. Also, the subtractor 32 may be provided, as a pair 32a, 32b as shown in Fig. 5, respectively between the first RAM 15 and the first D/A converter 27, the second RAM 16 and the second converter 28 so that the operation effect similar to that of Fig. 1 may be provided. Fig. 6 examplary shows an actual detailed block diagram of Fig. 5. In Fig. 6, the blocks which have no reference numerals of the blocks of Fig. 5 have their names written in the drawing. An identification circuit 33 identifies whether the line includes the R-Y signal or includes the B-Y signal. Namely, it is adapted to discriminate the type of the color difference signals by the low level or the high level of the output of the A/D converter 4 for 1 µs of 7.4 µs through 8.4 µs from the falling t0 of the horizontal synchronizing signals P1, P2. A control signal generating circuit 10 generates a storing control signal for 10.4 µs of 10.8 µs through 21.2 µs (TB1, TB2) from the falling t0 of the horizontal synchronizing signal to be fed from the synchronism detaching circuit 3, and generates a read controlling signal for the Tc1, Tc2 of Fig. 4 continued after it. The storing control signal is fed into the first, second memories 15, 16, and the reading control signal is fed directly into the first, second memories 15, 16. When the color television signal of Fig. 4 is fed into the input terminal 1, the identification circuit 33 is adapted to examine the level of the timing of the (t1 + t2)/2 from the leading edge of the synchronizing signal (t0). When it is judged that this is the high level, the A/D converted color television is fed into the first memory 15 so that the R-Y signal of the TB period of Fig. 4 is read at a high speed by a high speed storing control signal from the control signal generating circuit 10. Needless to say, as the color television signal of Fig. 4 shows only the wave form before it is converted in A/D, it is to be understood that what is recorded is the R-Y signal as a digital value. Assume that the digital value is 6. After the TB period is over, the reading operation is performed in the first, second memories 15, 16 by a low-speed reading signal from the control signal generating circuit 10. At the time, the reading output of the first memory 15 is a R-Y signal stored in the line and the reading output of the second memory 16 is a B-Y signal stored in the line before 1H. When the horizontal synchronizing signal comes after the reading operation, the similar operation is performed. In this case, the identification circuit detects the low level to judge it as the B-Y signal line, so that the storing control signal from the control signal generating circuit 10 is fed only to the second memory 16, but is not fed to the first memory 15. Accordingly, the first memory 15 retains the contents, at they are, of the R-Y signal stored at the previous time, and the second memory 16 stores the B-Y signal of the present line instead of the B-Y signal before 2H stored up to that time. Then, when the reading control signal is fed, the R-Y signal from the first memory 15 and the B-Y signal from the second memory 16 are simultaneously at the low speed and are time-extended signals so that they are fed into the next-stage of D/A converters 27, 28 and they are outputted as analog signals. A static RAM which is formed of MOSIC of for example 6 × 208 bits of element number is used as the memories 15, 16. According to the present invention, as described hereinabove, the shift register is not required to be used, an inexpensive color signal processing circuit can be provided. Also, as the MOS memory can be used, the consumption power will be made less. Also, as two same memories may be used, and the addresses may be completely the same in timing, the driving system becomes simpler in terms of the circuit.

Claims: A video signal recording and reproducing apparatus, the brilliance signals, including the synchronizing signal, and the color difference signals of said video signal to be recorded during the recording operation are respectively compressed in time axis and inserted in time sharing, in accordance with clock signals controlled in synchronous relation with the phases of the synchronizing signals of the video signals to be recorded to form a conversion video signal into which the brilliance, either a first color difference signal or a second color difference signal, and an indication signal for indicating the kinds of said color difference signal have been inserted in time sharing in each 1 horizontal period (1H) and to record said conversion video signal on the recording medium, the brilliance signals, including the synchronizing signal, and the color difference signals of said reproduced video signal which has been provided by the reproduction of said medium during the reproducing operation are respectively extended in time axis, in accordance with clock signals controlled in synchronous relation with the phases of the synchronizing signals of the reproduced video signals, the brilliance signals, the color difference signals which are the same in time axis as the brilliance signals, the color difference signals of said video signals to be recorded are respectively reproduced in each 1 horizontal period and are outputted, including a color difference signal processing, which comprises an A/D converter (4) for inputting the reproduced video signals, characterized by a latch circuit (31) for recording the achromatic signals level of said A/D converter output and a subtracting circuit (32) for providing the difference between said A/D converter output and said latch circuit output as a color difference signal processing circuit, wherein the output of said latch circuit (31) is adapted to latch A/D conversion output at the timing of a certain period from the leading edge of the horizontal synchronizing signal by a controlling signal (M). A video signal recording and reproducing apparatus in accordance with claim 1, comprising an analog synchronism detaching circuit (3) which is adapted to the respective synchronizing signal of said video signal to be recorded, said reproduced video signal to perform the synchronous detachment, a prohibition gate signal forming circuit (9) which forms and outputs a prohibition gate signal of the compression, the extension in a period of the vertical synchronizing signal portion of said video signal to be recorded, said video signal reproduced in accordance with the synchronizing signal outputted from said synchronism detaching circuit, a clock controlling circuit (10) for forming a clock signal, which is synchronized in phase with the synchronizing signal outputted from said synchronism detaching circuit, is rendered variable in frequency in accordance with said time-axis compressing and time-sharing inserting operations, said time-axis extending operation during the non-output period of said prohibition gate signal, and is controlled by the stop frequency of said time-axis compressing and time-sharing inserting operations and said time-axis extending operation in the output period of said prohibition gate signal, a signal processing unit (29) which is adapted to respectively perform said time-axis compressing and time-sharing inserting operations, said time-axis extending operation in the non-output period of said prohibition gate signal in accordance with the clock signal outputted from said controlling circuit, to respectively stop said time-axis compressing and time-sharing inserting operations, said time-axis extending operation in the output period of said prohibition gate signal so as to no-process outputting the brilliance signal of said video signal to be recorded, said reproduced video signal. A video signal recording and reproducing apparatus in accordance with claim 1, comprising a first memory (11, 15) for memorizing a first color difference signal, a second memory (12, 16) for memorizing a second color difference signal, a control signal generating means which is adapted to output a high-speed storing control signal and a low-speed reading control signal at a given timing in response to said horizontal synchronizing signal. A video signal recording and reproducing apparatus in accordance with claim 3, wherein the first color difference signal to be memorized in the first memory is a R-Y signal, the second color difference signal is a B-Y signal.

Inventors: ITOU, KOUJI, SHIMOMURA, KAZUO
Applicants: SANYO ELECTRIC CO., LTD.
Application year: 1985
Main classification: H04N9
IPC codes: H04N9