APPARATUS FOR GENERATING DIGITAL TIMING WAVEFORMS

Abstract: A programmable event generator for generating digital timing waveforms in response to a triggering signal includ­ ing one programmable read only memory for storing and outputting data words corresponding to the digital timing waveforms and next address words to address another of the data words, a storage register for temporarily storing and outputting any one of the data words and next address words, another mapping programmable read only memory for storing and outputting starting address words to start the addressing of the one programmable read only memory, a multiplexer to select either a starting address word or a next address word to address the one programmable read only memory, and a programmable control circuit, responsive to the triggering signal, for clocking the storage register at a programmed clock frequency.

Description: The present invention relates generally to apparatus for generating digital timing waveforms and, preferably, to general purpose timing signal generators for generating complex digital timing waveforms. Timing waveforms or signals are used in a wide variety of digital systems to control the processing of data. For example, computer memory systems typically have components such as a memory, bus buffer, error detection and correction unit, and memory timing controller, which must utilise precise timing waveforms to read, write and correct the data accurately. One computer memory system may require different timing waveforms than another computer memory stem depending, for example, on the particular applications or uses of each. A prior device that has been used to produce timing waveforms is known as a delay line. Typically, the delay line has a plurality of output taps spaced in series along the line. In operation generally, an input signal is conducted through the delay line and at each tap an output timing signal may be taken. Each output timing signal is synchronized to the input signal, but delayed relative to the time at which the input signal is received. One problem with a delay line is that errors can be accumulative. Thus, if there is a delay error at the first tap in the series of taps, this error will accumulate as the delayed input signal is taken out as a timing signal at the succeeding taps. In addition, the delay line is a relatively expensive device to manufacture, resulting in part from the need to adjust manually the taps to provide the precise delay. Yet another problem with the delay line is that the timing signals outputted at the respective taps always resemble the input signal. That is, these timing signals are the same as the input signal, but merely delayed, so that the timing edges of the outputted signals, i.e., the leading or trailing edges, are related to the timing edges of the input signal. This is disadvantageous for many digital systems which require synthesized timing signals, i.e., timing signals whose timing edges are not so related to the timing edges of the input signal. Timing signals can be synthesized by coupling the signals outputted from the taps of the delay line to a combinatory logic circuit which then logically combines these output signals to generate the desired synthesized timing signals. However, the use of combinatory logic circuit adds to the cost of the overall timing signal generator and undesirably reduces the speed by which the synthesized timing signals are outputted relative to the time at which the intput signal is received by the delay line. French Patent Specifications 2450006 and 2417892 describe particular forms of apparatus for generating digital timing waveforms in response to a triggering signal. The present invention provides a circuit for generating at an output a sequence of digital timing waveforms T each of which is in the form of a binary data word DW, in response to a triggering signal TRIG, comprising: storage means for storing the data words in respective addresses; output means for outputting the data words as the timing waveforms from that storage means to said output; address means for addressing a stored data word in that storage means to be transferred to that output means; starting means responsive to an externally applied address for selecting in that storage means with a starting address word SAW a first data word to occur in said sequence; and control means which is responsive to said trigger signal and an external clock signal to provide start and stop signals for the output of said sequence, and to control the output of said sequence from that output means; characterised in that; said storage means is arranged to store an address word NAW of the next data word in said sequence distinct from but in association with the content of the digital waveform at each said respective address therein, and selection means is provided to supply initially said starting address and subsequently said address of the next data word in the sequence to said addressing means in response to a select control signal MUXSEL from said control means. Thus the present invention, by storing and controlling the output of the data words, a large number of different and complex timing waveforms can be synthesized to provide the timing required for a given digital system. In addition, while the timing waveforms may be synchronized to the triggering signal, the former need not resemble the latter. Thus, for example, the apparatus of the present invention may be used to replace a delay line or a delay line coupled to a combinatory logic circuit to produce the digital timing waveforms. Brief Description of the Drawings Fig. 1 is a block diagram of one embodiment of the present invention; Fig. 2 is a timing diagram showing one example of many digital timing waveforms that may be produced by the embodiment of Fig. 1; Fig. 3 illustrates one example of a digital word used in accordance with the principles of the present invention; Fig. 4 shows a more detailed block diagram of a clock control circuit of the embodiment of Fig. 1; and Fig. 5 illustrates a block diagram of other apparatus of the present invention used for testing purposes. Detailed Description of the Drawings Fig. 1 shows an apparatus 10 for generating a plurality of digital timing waveforms indicated generally as T on a plurality of output lines shown generally at 12. These timing waveforms T are generated in response to a triggering signal TRIG on an input line 14. As indicated in Fig. 2, the present invention will be described based on producing twelve timing waveforms T₀-T₁₁ on twelve parallel output lines 12 respectively; however, the principles of the present invention may be used to generate any number of timing waveforms T on any number of lines 12, in parallel or in series. Furthermore, Fig. 2 shows only one example of the many different timing waveforms T₀-T₁₁ that may be generated by the apparatus 10, as will be further described below. Also, Fig. 2 shows in solid lines one polarity of the signal TRIG and in dotted lines another polarity of the signal TRIG. For each polarity of the signal TRIG there is a leading edge LE and a trailing edge TE. As will be described below, the apparatus 10 may respond to either polarity of the signal TRIG, with the leading edge LE commencing the generation of the timing waveforms T₀-T₁₁. In addition, Fig. 2 shows the timing waveforms T₀-T₁₁ as continuing to be generated subsequent to the occurrence of the trailing edge TE; however, the apparatus 10 may respond to the latter to inhibit further generation of the timing waveforms T₀-T₁₁. In one particular embodiment, the apparatus 10 is a programmable event generator 16 in which each pulse of the timing waveforms T₀-T₁₁ corresponds to an event that should occur in an overall system (not shown) in which the generator 16 might be used. The generator 16 includes state machine means shown generally at 18 for outputting the timing waveforms T₀-T₁₁ on line 12, together with control means shown generally at 20 for controlling the state machine means 18 in response to the signal TRIG on line 14 to output the timing waveforms T₀-T₁₁. The programmable event generator 16 also includes initialization means shown generally at 22 and coupled to the state machine means 18 for initializing the outputting of the timing waveforms T₀-T₁₁. The state machine means 18 has an addressable memory 24, such as a programmable read only memory (PROM) 26, for storing a plurality of words W. For example, the PROM 26 may store thirty-two words W, each of 18-bit length. As one example, Fig. 3 shows the content of each word W, which includes a data word DW of twelve bits, a next address word NAW of five bits and a stop word SW of one bit. The twelve bits of the data word DW correspond, respectively, to the twelve timing waveforms T₀-T₁₁ produced on the parallel output lines 12. The next address word NAW defines an address to any other of the words W that is stored in the PROM 26. The stop word SW, if at one logic level, e.g., logic 1, is used to stop or inhibit the generation of the timing waveforms T₀-T₁₁, as will be further described. As mentioned above, alternatively the trailing edge TE of the signal TRIG may be used to so inhibit the timing waveforms T₀-T₁₁. With reference again to Fig. 1, each data word DW and next address word NAW are read from the PROM 26 on output lines 28, while the stop word SW is read from the PROM 26 on an output line 30. A storage register 32 is coupled to the lines 28 to receive and temporarily store the data word DW and next address word NAW of any one word W stored in the PROM 26. The storage register 32 is clocked by an internal clock ICLK on a line 34 to output the data word DW on twelve parallel lines 36 that are coupled to the lines 12 via a similar number of output drivers 38, respectively. The storage register 32 also outputs the next address word NAW on lines 40 to address another of the words W stored in the PROM 26. One reason for using the storage register 32 is to provide registered or "glitch-free" outputs on lines 36 and lines 40. However, if such glitch-free outputs are not necessary, the storage register 32 need not be used, with each data word DW being clocked directly from the PROM 26 onto lines 36 along with each next address word NAW onto lines 40. The state machine means 18 also includes a multiplexer 42 having an address input coupled to the lines 40 to receive the next address word NAW, another address input coupled to lines 44 to receive a starting address word SAW from the initialization means 22, and an output coupled to lines 46 which are coupled to an address decoder 48. The multiplexer 42 also has a select input coupled to a line 50 carrying a signal MUXSEL. The multiplexer 42 responds to the signal MUXSEL to couple either lines 40 or lines 44 to lines 46, whereby lines 46 carry either a starting address word SAW or a next address word NAW, as will be further described. The address decoder 48 decodes the starting address word SAW or the next address word NAW on lines 46 to access a word W stored in PROM 26, which is then read onto lines 28 and line 30. Thus, to describe generally the operation of the state machine means 18, assume that the PROM 26 has been programmed with words W. As will be further described, the multiplexer 42 will first couple lines 44 to lines 46, whereby address decoder 48 will decode a "start address" defined by the SAW to access a first or starting word W in the PROM 26. Then, as the storage register 32 is clocked by a pulse of the internal clock ICLK on line 34, the next address word NAW and the data word DW are temporarily stored in the storage register 32 via lines 28, with the stop word SW being outputted on line 30. Thus, the data word DW of this first word W is outputted onto lines 36 and driven onto lines 12, whereby respective pulses of the timing waveforms T₀-T₁₁ are produced in accordance with the logic 1 or logic 0 state of the twelve bits of the data word DW. Also, the next address word NAW is fed back over lines 40 to the multiplexer 42, which has now been set with the signal MUXSEL on line 50 to couple lines 40 to lines 46. Therefore, the address decoder 48 now decodes the next address word NAW to access another word W stored in the PROM 26. Then, upon the next clock pulse of the internal clock ICLK, this other word W is read from the PROM 26, so that the corresponding next address word NAW and data word DW are temporarily stored in the storage register 36 while the stop word SW is provided on line 30. Consequently, for this next pulse of the internal clock ICLK, pulses of the timing waveforms T₀-T₁₁ are produced on lines 12 via drivers 38 in accordance with the logic 1 or logic 0 of the bits of the data word DW. Also, the next address word NAW is fed back via lines 40 and coupled through the multiplexer 42 onto lines 46 to repeat the process by accessing another word W. This process continues, until the stop word SW of, for example, a logic 1 is produced on line 30, or until the trailing edge TE of the signal TRIG is provided on line 14, as will be further described. The control means 20 includes a programmable trigger polarity circuit 52 which receives the signal TRIG on line 14 and, in response, produces any one of several control signals on an output line 54. The circuit 52 has a polarity fuse F₁ and a stop-trig fuse F₂. If not "blown", the fuse F₁ will enable the circuit to respond to the leading edge LE of one polarity of the signal TRIG, while if blown or programmed, the fuse F₁ will enable the circuit 52 to respond to the leading edge LE of the other polarity of the signal TRIG. The stop-trig fuse F₂, if blown, will enable the circuit 52 to respond to the trailing edge TE of the signal TRIG to inhibit the generation of the timing waveforms T₀-T₁₁; otherwise, the trailing edge TE has no effect. The circuit 52, in response to the leading edge LE of the signal TRIG, also produces a latch enable signal on an output line 56 for use as will be described below. The control means 20 also includes a control logic circuit 58 having an input coupled to the line 30 carrying the stop word SW, an input coupled to the line 34 carrying the internal clock ICLK, and an input coupled to the line 54 carrying the control signals produced by the trigger polarity circuit 52. The control logic circuit 58 is used to generate the signal MUXSEL on the line 50 and a signal START/STOP on a line 60. The control logic circuit 58 has a flip-flop FF₁ which responds to the control signals on line 54 or the stop word SW on line 30 to produce the signal START/STOP on line 60, while another flip-flop FF₂ is clocked by the internal clock ICLK on line 34 to produce a logic 1 signal MUXSEL on line 50, as will be further described. A programmable clock control circuit 62, to be described more fully in relation to Fig. 4, is controlled by the signal START/STOP on line 60 to produce the internal clock ICLK on line 34. The clock control circuit 62 has two inputs coupled to respective lines CLK/X₁ and X₂ for receiving either an external reference clock CLK on line CLK/X₁ or on external reference clock from a crystal (not shown) coupled across lines CLK/X₁, and X₂, from which the internal clock ICLK is produced. The programmable clock control circuit 62 is coupled to an external capacitor over a line 64 and may output a system clock CLKOUT on an output line 66 to provide system timing for an overall system (not shown) in which the programmable event generator 16 might be used. Thus, in the operation generally of the control means 20, in response to the leading edge LE of the signal TRIG, the programmable trigger polarity circuit 52 produces a control signal on line 54 and the latch enable signal on line 56. In response to the control signal on line 54, the flip-flop FF₁ of the control logic circuit 58 will produce the signal START/STOP, e.g., a logic 1, on line 60, whereby the programmable clock control circuit 62 will then be enabled to provide the internal clock ICLK on line 34, as well as the signal CLKOUT on line 66. In response to the internal clock ICLK on line 34, the flip-flop FF₂ of the control logic circuit 58 will clock in a logic 1 to produce a logic 1 signal MUXSEL on line 50. Furthermore, at an appropriate time, the flip-flop FF₁ of the control logic circuit 58 will produce the signal START/STOP, e.g., logic 0, on line 60 to stop the generation of the internal clock ICLK in response to the logic 1 stop word SW on line 30. Alternatively, if so programmed, the programmable trigger polarity circuit 52 will respond to the trailing edge TE of the signal TRIG to produce a control signal on line 54, whereby the flip-flip FF₁ will respond to produce the signal START/STOP of logic 0 to inhibit the internal clock ICLK. The initialization means 22 has a latch 68 for latching an externally received address of, for example, three bit length A₀-A₂ over three respective lines 70. The latch 68 latches the external address A₀-A₂ in response to the latch enable signal on line 56 and outputs this latched address over three lines 72 to an address decoder 74. An addressable memory 76, such as a mapping programmable read only memory or PROM 78, is used for storing a number of starting address words SAW that may be read onto the lines 44. For example, the mapping PROM 76 may be an 8 x 5 mapping PROM 78 for storing eight starting address words SAW each of 5-bit length. In the operation generally of the initialization means 22, when a given external address A₀-A₂ is received on the lines 70, the latch 68 outputs this address A₀-A₂ onto lines 72. Consequently, the address decoder 74 decodes this address A₀-A₂ to access a specified starting address word SAW in the PROM 76, whereby this SAW is then read onto lines 44. In the overall operation of the programmable event generator 16, assume that the state machine PROM 26 has been programmed with up to thirty-two words W, that the mapping PROM 78 has been programmed with up to eight starting address words SAW, and that the programmable trigger polarity circuit 52 has been programmed to respond to the leading edge LE of the signal TRIG of the desired polarity, but has not been programmed to respond to the trailing edge TE of the signal TRIG to inhibit the generation of the timing waveforms T₀-T₁₁. As will be described below, also assume that the programmable clock control circuit 62 has been programmed to produce an internal clock ICLK of, for example, 100 MHz or a 10 ns period in response to the external clock CLK on line CLK/X₁. Furthermore, assume that the programmable event generator 16 has been reset, so that the signal MUXSEL is a logic 0, whereby the multiplexer 42 is coupling lines 44 to lines 46. Then, in operation, first the external address A₀-A₂ is supplied on the lines 70 to latch 68, whereby the address decoder 74 decodes this address A₀-A₂ to access a desired starting address word SAW in the mapping PROM 78. Accordingly, this starting address word SAW is read onto lines 44 and, via multiplexer 42, onto lines 46, so that address decoder 48 at this time decodes this SAW to access one of the thirty-two words W stored in the PROM 26. Then, the signal TRIG is supplied to the programmable trigger polarity circuit 52. Upon the occurrence of the leading edge LE of the signal TRIG, the latch enable signal on line 56 is produced to latch the external address A₀-A₂ in latch 68. This latching stabilizes the stored address A₀-A₂, so that a stabilized starting address word SAW is read from the PROM 78, resulting in a stabilized word W being read from the PROM 26. At this time also, the programmable trigger polarity circuit 52 produces a control signal on line 54 that is stored in the flip-flop FF₁, resulting in a logic 1 signal START/STOP on line 60 being generated. In response to the logic 1 signal START/STOP, the programmable clock control circuit 62 produces the internal clock ICLK on the line 34, which then clocks the storage register 32, whereby the timing waveforms T₀-T₁₁ begin to be generated pursuant to the data word DW currently stored in the register 32. The internal clock ICLK also is fed back to the control logic circuit 58 to clock the logic 1 into the flip-flop FF₂, so that the logic 1 signal MUXSEL is produced on the line 50 to set the multiplexer 42. Therefore, now the multiplexer 42 couples the next address word NAW on the lines 40 to the lines 46. Then, as each clock pulse of the internal clock ICLK is produced on the line 34, a word W will be read from the PROM 26, resulting in the continued production of the timing waveforms T₀-T₁₁ via the data word DW and the accessing of another word W via the next address word NAW. The above process continues until a stop word SW of logic 1 is provided on the line 30. In response, the flip-flop FF₁ produces a logic 0 signal START/STOP on the line 60, whereby the internal clock ICLK is inhibited. Consequently, the clocking of the storage register 32 ceases, resulting in the timing waveforms T₀-T₁₁ remaining in the states corresponding to the data word DW then stored in the register 32 until the programmable event register 16 is reset. Alternatively, if the programmable trigger polarity circuit 52 is so programmed, the occurrence of the trailing edge TE of the signal TRIG results in a control signal on line 54 being generated, whereby in response the flip-flop FF₁ produces the logic 0 signal START/STOP to inhibit the internal clock ICLK. Fig. 4 shows a more detailed block diagram of one embodiment of the programmable clock control circuit 62. This circuit 62 includes a portion of a phase locked loop 80 that responds to, for example, the externally applied clock CLK on line CLK/X₁ to produce a frequency signal on a line 82. The phase locked loop 80 has a voltage controlled oscillator 84 producing the frequency signal on line 82 and which is, for example, designed to run at a nominal frequency of 100 MHz. The phase locked loop 80 also has, for example, a programmable multiplication factor of 5 or 10 which is provided by programming a feedback divider 86 to divide by 5 or 10. Thus, if the external clock CLK on line CLK/X₁ is at 10 MHz, the divider 86 will be programmed to divide the 100 MHz signal on line 82 by 10, to output on a line 88 a 10 MHz signal that is phase compared with the 10 MHz signal on line CLK/X₁ by a phase comparator 90 in accordance with conventional phase locked loop principles. If the external clock CLK is at 20 MHz, the divider 86 will be programmed to divide the 100 MHz signal on line 82 by 5, to output on line 88 a 20 MHz signal for phase comparison purposes. The divider 86 may be programmed by providing a fuse F₃ which is blown or not blown, depending on the desired multiplication factor. The programmable clock control circuit 62 also has a programmable divider 92 which divides the 100 MHz signal on line 82 to produce the internal clock ICLK on the line 34. For example, the programmable divider 88 can have two fuses F₄ and F₅ which, if blown or not, will cause the divider 88 to divide the 100 MHz signal on line 82 by 1 of 4 values. Furthermore, the programmable clock control circuit 62 has a programmable divider 94 for dividing the 100 MHz signal on line 82 to produce the signal CLKOUT on line 66. For example, the divider 94 has a fuse F₆ to divide the 100 MHz signal on line 82 by 5 or 10. If the fuse F₆ is not blown, the divider 94 will, for example, divide by 5 to output on the line 66 the signal CLKOUT of 20 MHz, whereas, if the fuse F₆ is blown, the divider 94 will divide by 10 to produce the signal CLKOUT of 10 MHz. As also shown, a portion of the phase locked loop 80, particularly a capacitor C which stores a phase error signal produced by the output of the phase detector 90, is externally coupled over the line 64 to drive the VCO 84 via a filter 96. The reason for this external connection of the capacitor C is that the overall programmable event generator 16 can be implemented as an integrated circuit, but for conventional reasons it is possible, but not advantageous, to include the capacitor C as part of the integrated circuit. The programmable event generator 16 typically may be manufactured and sold to a user in an unprogrammed state. That is, the PROM 26 and the PROM 78 will not be programmed with the words W and starting address words SAW, nor will the fuses F₁-F₆ be blown. The user may then program the PROM 26 and the PROM 78, as well as selectively blow the fuses F₁-F₆ to configure the programmable event generator 16 and generate the timing waveforms T₀-T₁₁, as desired. Fig. 5 shows the same programmable event generator 16 as in Fig. 1, except that the generator 16 also may be manufactured and sold with a test PROM 26' and associated address decoder 48', coupled to lines 28, 30 and lines 46 as shown, bypassing the PROM 26 and address decoder 48. The generator 16 also then has a test mapping PROM 78' and corresponding address decoder 74' coupled to lines 44 and lines 72 as shown, bypassing the mapping PROM 78 and address decoder 74. The purpose of providing these additional components is to test the programmable event generator 16 by simulating, prior to programming, the operation of the generator 16 as if it had been programmed as described above. Two tests that may be performed are a functional test of the overall programmable event generator 16 and a high-frequency test of the phase-locked loop 80, as will now be described. The test PROM 26' may, for example, be programmed with six test words W' (not shown) each of 18-bit length having a 12-bit data word DW', a 5-bit next address word NAW' and a 1-bit stop word SW', in which one stop word SW' has a logic 1. The test mapping PROM 78' may, for example, be programmed with two starting address words SAW' (not shown) each of 3-bit length. To test if the programmable event generator 16 will function correctly after it is programmed, a relatively slow clock is used on line CLK/X₁ to bypass the phase-locked loop 80 (see Fig. 4) and, thereby, provide a slow internal clock ICLK on line 34. Also, one bit of the external address A₀-A₂, e.g, bit A₀, is provided on lined 70 at a very high voltage to drive off the address decoder 74 and mapping PROM 78, while bits A₁-A₂ are in their normal voltage state to address the test mapping PROM 78' via the address decoder 74'. Consequently, when the leading edge LE of the signal TRIG is then applied to line 14, the data words DW' will be outputted on lines 12 at a slow rate set by the internal clock ICLK in a manner previously described, whereby test timing waveforms T'₀-T'₁₁ (not shown) can be detected. When the logic 1 stop word SW' is produced on line 30, this operation of the programmable event generator 16 will stop. Thus, by detecting the test timing waveforms T'₀-T'₁₁ and determining if they are the expected waveforms T'₀-T'₁₁, the basic functioning of the programmable event generator 16 can be tested before it is programmed. As previously mentioned the phase-locked loop operates at a high frequency, e.g., 100 MHz. Therefore, to test this high-frequency operation, a crystal (not shown) of appropriate frequency is coupled to lines CLK/X₁ and X₂. Then, the signal CLKOUT may be detected to determine if proper frequency multiplication is being performed by the phase-locked loop 80. In addition, overall high-frequency operation of the programmable event generator 16 can be tested by again supplying the external address A₀-A₂ on lines 70 with bit A₀ at a very high voltage and supplying the signal TRIG to line 14, whereby the test timing waveforms T'₀-T'₁₁ outputted on lines 12 can be detected.

Claims: A circuit for generating at an output (12) a sequence of digital timing waveforms (T) each of which is in the form of a binary data word (DW), in response to a triggering signal (TRIG), comprising: storage means (24) for storing the data words in respective addresses; output means (32) for outputting the data words as the timing waveforms from that storage means to said output; address means (48) for addressing a stored data word in that storage means to be transferred to that output means; starting means (22) responsive to an externally applied address for selecting in that storage means with a starting address word (SAW) a first data word to occur in said sequence; and control means (20) which is responsive to said trigger signal and an external clock signal (CLK/X) to provide start and stop signals for the output of said sequence, and to control the output of said sequence from that output means; characterised in that; said storage means is arranged to store an address word (NAW) of the next data word in said sequence distinct from but in association with the content (DW) of the digital waveform at each said respective address therein, and selection means (42) is provided to supply initially said starting address and subsequently said address of the next data word in the sequence to said addressing means in response to a select control signal (MUXSEL) from said control means. A circuit according to Claim 1, characterised in that output means comprises a storage register arranged to receive a data word and the associated address of the next word in said sequence from said storage means, arranged to supply the data word to said output and the address to said selection means. A circuit according to Claim 1 or 2, characterised in that the digital timing waveforms (T) are generated in synchronization with the triggering signal (TRIG). A circuit according to Claim 1, 2 or 3, characterised in that the triggering signal (TRIG) has a specific waveform and wherein the digital timing waveforms (T) do not necessarily resemble the waveform of the triggering signal (TRIG). A circuit according to any preceding claim characterised in that said storage means (24) comprises a programmable read only memory (26). A circuit according to any preceding claim characterised in that said starting means (22) comprises: an addressable memory (78) for storing and outputting any one of a plurality of such starting address words (SAW) and means (74) for receiving and decoding an externally supplied address word (A₀, A₁, A₂) to access the addressable memory to output one of the plurality of starting address words to said selection means. A circuit according to any preceding claim, characterised in that said control means (20) comprises: means (58) for generating a start signal in response to the triggering signal (TRIG); and means (62) for generating a clock signal (ICLK) to clock said storage and output means (24, 32) in response to the start signal. A circuit according to any one of Claims 1 to 6, characterised in that the triggering signal (TRIG) has a leading edge and a trailing edge, and wherein said control means (20) comprises: means (58) for generating said start signal in response to the leading edge and said stop signal in response to the trailing edge; and means (62) for generating a clock signal (ICLK) in response to the start signal to clock said storage and output means (24, 32) and for inhibiting the clock signal (ICLK) in response to the stop signal. A circuit according to any preceding claim, characterised in that at least one stop word (SW) is stored at an address in said storage means as the last data word in the sequence, and said control means (20) controls said storage and output means (24, 32) in response to the stop word (SW) to inhibit the supply of data words to said output. A circuit according to any preceding claim, characterised in that said control means (20) comprises programmable means (62) for generating a clock signal (ICLK) of a selection frequency to clock said storage and output means (24, 32). A circuit according to Claim 10, as dependent upon Claim 8, characterised in that said programmable means is responsive to said start signal to enable said clock signal and to said stop signal to inhibit said clock signal. A circuit according to any preceding Claim characterised by holding means (68) for temporarily holding said starting address. A circuit according to Claim 12, characterised in that said holding means comprises a latch circuit. A circuit according to Claim 12 or 13 characterised in that said control means includes trigger circuit means (52), responsive to the leading edge of said triggering signal (TRIG), for generating a first signal to enable said holding means (68) and for generating a second signal; and control logic circuit means (58) for generating said select control signal and said start signal in response to the second signal. A circuit according to Claim 14 characterised in that said trigger circuit means (52) is programmable to generate a third signal in response to the trailing edge of the triggering signal, and wherein said control logic circuit means (58) generates the stop signal in response to the third signal. A circuit according to any one of claims 14 or 15, characterised in that the triggering signal (TRIG) has one or another polarity, and said trigger circuit means is programmable to respond to either polarity of the triggering signal.

Inventors: MADEWELL, JIMMY, THREEWITT, BRUCE
Applicants: ADVANCED MICRO DEVICES, INC.
Application year: 1985
Main classification: G06F1
IPC codes: G06F11, G06F1, G06F9, H03K3