A BREAKDOWN PROTECTED TRANSISTOR DEVICE

Abstract: A protection circuit is provided for a bipolar planar transistor device (2). The protection circuit comprises a variable resistor device (6) formed of a junction type field effect transistor (7). The resistor device (6) is connected in series with the base of the planar transistor (2). The drain electrode (11) of the J-FET (7) is connected to the base of the planar transistor (2) while the collector of the planar transistor is connected to the gate of the J-FET. Due to this interconnected scheme, the base input resistance of the planar transistor (2) is increased to reduce its base current when a high voltage is applied accidentally to the collector. The base current is not eliminated, however, and the device (2) is protected but can still operate.

Description: BACKGROUND OF THE INVENTION The present invention relates to a large power semiconductor device having a self-protection feature. In particular, the invention is directed to a large power switching transistor device provided with a junction type field effect transistor (J-FET) acting as a protection circuit. Recently, great progress has been achieved in the fields of variable motor control and automatic control of various machines. Also, the industry has witnessed the advent of power transistors with greater breakdown voltages. As a result, the demand for large power switching transistors such as a Darlington transistor is sharply increasing. Under the circumstances, it is a serious concern in this field to develop large power switching transistors having a high breakdown voltage while permitting the use of a relativley high voltage (e.g., 480 volts AC), and operating over a wide area of safety operation (ASO). ASO is the range of Vce voltages which can be applied to the transistor without a breakdown occurring. If an accident occurs during the operation of a large power switching transistor (e.g., load short-circuiting, power surges, power source fluctuation etc.), a high voltage is applied between the collector and the emitter of the transistor. A large current will suddenly flow through the transistor and the transistor will be instantly destroyed. As a result, it is customary in the prior art to provide large power switching transistors with a protection circuit for protecting the transistor from destruction in the event of an accident. Such prior art circuits substantially increase the ASO during that time. It should be noted that the ASO will decrease in proportion to the continuous time the transistor is operating. Thus, it is necessary to provide some method in the prior art to prevent or limit breakdown as the transistor continues to operate. Figure 1 shows a conventional protection system for a power transistor Q1. A protective switch Q2, operable by the collector voltage of Q1, is connected between the base and emitter of Q1. When an excess voltage is applied between the collector and emitter of Q1, protective switch Q2 is turned on to short-circuit the base and emitter of transistor Q1. As a result, an excess collector current is prevented from flowing, thereby preventing the destruction of transistor Q1. Figure 2 is a graph showing the static characteristics of transistor Q1 and its protective switch Q2. The collector-emitter voltage V CE of Q1 is plotted on the abscissa, while the collector current I C is plotted on the ordinate. A₁ to A₃ represent the change of I C relative to V CE for each base current I B . Straight line b-b' represents the load characteristics; point b denotes the conductive state of the transistor and the point b ' denotes its nonconductive state. The curves represented by the dashed lines show the characteristics of a transistor Q1 which has not been provided with a protective switch such as switch Q2. The conventional protecton system described above utilizes protective switch Q2 to force transistor Q1 into the cut off region (i.e., values of V CE greater than or equal to V CO -Figure 2). This system, however, is defective since at V CE voltage values above V CO , transistor Q1 does not operate. As seen from Figure 2, curves A₁ - A₃ have collector current (I C ) values equal to zero above V CE voltage values greater than V CO . Therefore, it is difficult, if not impossible, to operate transistor Q1 at point b or other non-zero collector current values because switch Q2 is constantly on and collector current I C is thereby prevented from flowing. In order to permit Q1 to pass some collector current while switch Q2 is operating, it is necessary to set the bias point b'' within the narrow range R. In particular, b'' must be set between the operating points R₁ and R₂. R₁ represents the value of V CE which provides some collector current for all curves A₁ - A₃. R₂ represents the lowest value of V CE where breakdown occurs. In order to set the bias point b '' in this fashion, the power source voltage for driving the transistor must be determined by the static characteristics of the transistor device including the protective switch Q2. As a result, a substantial and practical restriction is imposed on the setting of the power source voltage. In addition, since the operating characteristics vary among the individual protective circuits, the setting for the source voltage must be changed for each transistor. Thus it is very difficult to design the power source circuit. Additional difficulty is presented since the bias voltage must be sufficiently stabilized in order to enable the protective circuit to operate normally despite the existence of source voltage fluctuations. It is extremely difficult , however, to stabilize the bias voltage due to the fluctuations. U.S. patent no. 4 441 116 by National Semiconductor Corporation discloses a bipolar transistor protected by a J-FET which overcomes some of the problems discussed above. However, the protected transistor described is not able to fullfil the parameters of enabling the transistor to use relatively high voltages, have a high breakdown voltage and enabling it to operate over a wide ASO. An object of the present invention is to provide a novel transistor device capable of protecting itself from breakdown in the event of accidents, such as load short-circuiting . More specifically, the present invention is intended to provide a large power switching transistor device with appropriate breakdown protection, whereby the transistor is not driving into the cut off region despite the occurrences of surge voltage (e.g., load short-circuiting). Thus, the device is protected from destruction, and the power source voltage needed for driving the transistor is not restricted by the protective circuit. The present invention utilizes a variable resistor element having the same construction as a junction type field effect transistor (J-FET) with two gate regions. This resistor element is connected in series with the base (i.e., input stage) of a planar bipolar transistor. The drain electrode of the J-FET is electrically connected to the base region of the bipolar transistor while the collector of the bipolar transistor is also the first gate region of the J-FET. The second gate region of the J-FET is connected to the collector via a diode. Due to this interconnected scheme, base input resistance of the transistor is increased to reduce its base current when a high voltage is applied to its collector during short-circuiting of the load. The base current, however, is not reduced to zero; thus, the transistor is not turned off, although it is protected from the high voltage. In short, the present invention provides a large power switching semiconductor device with breakdown protection capability in the event of load short-circuiting. Particularly, the breakdown protected transistor in accordance with the instant invention is not influenced by power source voltage fluctuations whereby it can be operated at any power source voltage provided the voltage is within the safe operation range. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a conventional circuit including a transistor provided with a protective switch; Figure 2 shows the static characteristics of the transistor circuit with a conventional protective switch of Figure 1; Figure 3 is a cross sectional view showing a semiconductor device according to one embodiment of the present invention; Figure 4 shows the static characteristics of the semiconductor device of the present invention; and Figure 5 is a schematic diagram of a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 3 is a cross sectional view showing a transistor device according to one embodiment of the present invention. The transistor device comprises an n-type semiconductor substrate 1 having a low impurity concentration. Substrate 1 acts as the collector region of a planar bipolar transistor 2 and as a first gate region of a junction type field effect transistor 7 formed in the substrate. Reference numerals 3 and 4 shown in Figure 3 denote the base and emitter regions of bipolar transistor 2, respectively; their conductivity type and impurity concentration are also shown. An oxide film 5 overlaps base and emitter regions 3 and 4. A variable resistor element 6, functioning as a protective circuit, is monolithically formed with transistor 2 in the substrate. Resistor element 6 comprises a junction type field effect transistor (J-FET) portion 7 and a diode portion 8. Portion 7 is electrically connected to base region 3 while portion 8 is connected in a forward direction to collector region 1. The J-FET portion 7 comprises: a p-type channel region 9 having a low impurity concentration; a p-type source region 10 having a high impurity concentration and formed within channel region 9, a p-type drain region 11, spaced from region 10, having a high impurity concentration and also formed within channel region 9; and an n-type second gate region 12 having a high impurity concentration and also formed within channel region 9 in a manner to cross both source region 10 and drain region 11. Second gate region 12 is used for controlling the thickness of the diffusion layer (i.e., the bottom portion 9a of the channel region immediately under this second gate) and for decreasing the impurity concentration of the diffusion layer. The impurity concentration is higher in the upper portion of the diffusion layer than in its lower portion. A source electrode 13 is formed on the surface of source region 10. A second gate electrode 14 is formed on second gate region 12, and a drain electrode 15 is formed on drain region 11. It should be noted that drain electrode 15 is connected to a base electrode 16 of the bipolar transistor 2. Diode portion 8 comprises an anode region 17 positioned to provide a pn junction together with the collector region 1 of transistor 2. Collector region 1 also acts as a cathode region of diode portion 8. Diode portion 8 also comprises an anode electrode 18, which is connected to second gate electrode 14 of J-FET portion 7 by use of connector 19. As shown in Figure 3, a base current supply terminal B is connected to source electrode 13 of J-FET portion 7. An emitter electrode 20 and a collector electrode (not shown) of the bipolar transistor 2 are respectively connected to a ground terminal E and a load as would normally be done with a single transistor. In the semiconductor device of the present invention, the voltage between the emitter and collector of the bipolar transistor 2 induces the depletion layer not only in the collector region but also in the bottom portion 9a of channel region 9. The base current and base input resistance of bipolar transistor 2 are controlled by the thickness of the formed depletion layer. It follows that, if a high voltage is applied between the emitter and collector, the thickness of the channel in which base current can now is decreased by the formed depletion layer resulting in an increased resistance between the source and drain regions. As a result, the base input resistance of bipolar transistor 2 is increased, producing a reduction in base current. In order not to impair the saturation characteristics of the transistor, it is necessary to properly design the length-to-width ratio of bottom portion 9a. It should be noted that a change in base input resistance relative to a change in emitter-collector voltage depends on: the thickness of the diffusion layer, the depth of second gate region 12 and on the impurity concentration of the diffusion layer. In the embodiment described above, the change in base input resistance relative to emitter-collector voltage is very large. Assuming, for example, a p-type channel region 9 having a depth of 10 µm and a surface impurity concentration of 5 x 10¹⁶/cm³ and an n-type gate region 12 having a depth of 5 µm and a high impurity concentration are formed in an n-type substrate of a low impurity concentration (i.e., 5 x 10¹³/cm³). In this case, the base input resistance can be changed 100 times or more when a voltage of 800 V is applied between the collector and the emitter. In view of possible breakdown voltage of the device, it is not desirable to tie the potential of the second gate region 12 with the potential of the source electrode or drain electrode in an attempt to fix the potential of the second gate region 12. In such a case, the collector-base breakdown would occur when the depletion layer in the channel region has expanded to reach the second gate region. Therefore, in accordance with one embodiment of the present invention, gate region 12 is connected to the anode region of the diode portion 8 to fix the potential. If, however, the breakdown voltage of junction 12 and 11 are sufficiently large, there is no need to utilize diode portion 8. Figure 4 shows the I C -V CE characteristics of both a semiconductor device designed in accordance with the present invention and a conventional single transistor. The semiconductor device of the present invention has 0.1 ohms of initial base input resistance. Also, the amount of change in resistance during application of the collector voltage is 100 times the original value. Curves C₃, C₄ and C₅ represent the I C -V CE characteristics of a device constructed in accordance with the present invention. Dashed lines C₁, C₂ and C₆ represent the I C -V CE characteristics of a conventional single transistor without an appropriate protection circuit. Curve C₁ shows a flow of collector current of approximately 280 A at a base current I B of 2 A if a voltage of 600 V is applied between the collector and the emitter due to short-circuiting during operation of the device. As a result, a conventional single transistor not provided with a variable resistor element will be destroyed in several micro-seconds after short-circuiting occurs. In the semiconductor device of the present invention, however, the collector current I C is held at a low level (e.g., 20 A) at a base current I B of 2 A, even with the application of a high voltage, such as 800 V, due to an accident occurring during the operation of the device. This protection control can be seen from curve C₃. It is clear that the semiconductor device of the instant invention avoids breakdown and maintains its operation since the base current is not interrupted. As can be seen from C₃, collector current continues to flow but at a lower level. It should also be noted that, in the semiconductor device of the present invention, the base current I B is decreased in accordance with an increase in the emitter-collector voltage. Although the characteristics of the device are changed with a change in base current I B , collector current continues to flow. Figure 5 shows a semiconductor device according to another embodiment of the present invention. In this embodiment, the technical concept of the present invention is applied to a three stage Darlington transistor. As seen from the drawing, the semiconductor device comprises a bipolar transistor portion 2A formed of a three stage Darlington transistor and a variable resistor element 6 connected in series with the base of a first transistor driving stage in transistor portion 2A. Variable resistor element 6 is similar to the one shown in Figure 3. The semiconductor device also comprises speed-up diodes (SUDs) as well as a base current supply terminal B and a collector current supply terminal C similar to those shown in Figure 3. If a high voltage is applied to the collector of the transistor output stage of transistor portion 2A, the resistance of the channel portion within the resistor element 6 is increased, thereby increasing the base input resistance of transistor portion 2, as previously described with the embodiment of Figure 3. As a result, the base current I B is decreased. It follows that the collector current I C is also decreased for preventing the destruction of portion 2A. It should also be noted that breakdown of transistor portion 2A is prevented even if load short-circuiting occurs as discussed in the embodiment of Figure 3. The large power switching semiconductor device of the present invention will avoid breakdown even if a load short-circuiting occurs and, thus, it is protected from destruction. It follows that the present invention provides a semiconductor device with a substantially enlarged safety operation region in the event of short-circuiting. In addition, the power source voltage is not restricted by the protection circuit, thereby making it unnecessary to take additional precautions to stabilize the power source voltage. In the embodiments described above, the variable resistor element 6 is formed monolithically with transistor 2. The variable resistor element 6 and the transistor 2, however, may be formed in separate chips to thereby provide a hybrid structure.

Claims: A transistor device formed on a substrate of a first conductivity type comprising a bipolar transistor (2) having a collector region of said first conductivity type; and a junction type field effect transistor (J-FET) (7), such that the base (3) of said bipolar transistor (2) is coupled to the drain (11) of said J-FET (7) and that the collector of said bipolar transistor (2) is coupled to a first gate region of said J-FET (7), said J-FET includes a second gate region (12) formed between the source (10) and drain (11) regions of the J-FET characterised in that said second gate region (12) is coupled to said collector (1) by a region of a second conductivity type and is thereby coupled to said collector by a diode (8) for increasing the base input resistance, thereby enabling the base current of said bipolar tansistor (2) to be reduced, but not eliminated, for protecting the transistor from being damaged due to a high voltage being applied to the collector of said transistor, yet maintaining the operation of said transistor (2). A transistor device as claimed in claim 1, in which said second gate region (12) is coupled to the anode (17) of said diode (8). A transistor device according to claim 1 or 2, in which said substrate (1) functions as said first gate region and said collector.

Inventors: IMAMURA, KAORU C/O PATENT DIVISION, MURAMOTO, KENICHI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: H01L29
IPC codes: H01L29, H01L21, H01L27