PROGRAMMABLE READ-ONLY MEMORY CELL AND METHOD OF FABRICATION

Abstract: A programmable read-only memory cell includes a semiconductor substrate (20) having an n-type epitaxial layer (22) embodying a collector region for an NPN transistor which also includes a base region (28), a p-type base contact region (21) and an n-type emitter region (32). Located on the emitter region (32) is an anti-fuse structure incorporating a region of undoped polycrystalline silicon (37) and an n-type doped polysilicon region (34). Metal contacts (50, 51) are provided for the anti-fuse structure and the base contact region (21). Programming is effected by applying a relatively low current through the undoped polycrystalline silicon region (37) which switches from a high to a low resistance condition. The cell enables production of a high density PROM and is fabricated on a chip together with CMOS devices by steps compatible with CMOS processing technology.

Description: PROGRAMMABLE READ-ONLY MEMORY CELL AND METHOD OF FABRICATION Technical Field This invention relates to electrically programmable read-only memory cells. The invention also relates to a process for fabricating electrically programmable read-only memory cells. Background Art A programmable read-only memory (PROM) is known from U.S. Patent Specification No. 4,403,399, which discloses a vertical diode/bipolar transistor structure. This device is programmed by creating an extremely high power density region in a thin epitaxi¬ al layer to induce migration of aluminum particles, therefore shorting the blocking diode junction. The bipolar devices in the array provide some current gain but their effectiveness is degraded by the high pro¬ gramming currents required to short the blocking diode junction since the bipolar transistor gain is low at such high current. Greater current could be obtained from the bipolar transistor by increasing the emitter area; however, because the size of the blocking diode is determined by the emitter size a larger diode requires a proportionately larger programming current. For this configuration, most of the programming cur¬ rent must be supplied as base current to the bipolar transistors from the peripheral circuitry. Therefore, this device is best built in a bipolar process with bipolar peripheral circuitry and two levels of low resistivity interconnect. A PROM is also known from an article by Tanamoto et al. , "A Novel MOS PROM Using Highly Resis¬ tive Polysilicon Resistor", IEEE Transactions on Electron Devices, Vol ED-27, No. 3, Pages 517-520, March 1980. This PROM utilizes a vertical "anti-fuse" structure and contains only MOS circuitry. By an "anti-fuse" is meant a structure which becomes more conductive as a result of a programming operation, in distinction to a "fuse" which becomes less conductive. The anti-fuse consists of high resistivity polysilicon which undergoes a dramatic decrease in resistivity upon application of sufficient voltage and current. The current required to lower the resistivity of the polysilicon is much lower than required to short the blocking diode in the device described above. The current is lower because a different physical mecha¬ nism is employed, i.e. a memory switching phenomenon. This known memory has the advantages of low power consumption, lower cost and reduces process complexi- ty» Since a vertical anti-fuse structure is utilized, the lateral area consumed by each bit is reduced when compared to a lateral fuse. However, an MOS transis¬ tor is required at each bit in the array. The MOS transistor used with each cell is an inherently later- al device adjacent to the anti-fuse structure. This known cell therefore has the disadvantage of lowering the density of the PROM, even though the anti-fuse is vertical. Disclosure of the Invention it is an object of the present invention to provide a read-only memory cell having a relatively low power consumption for programming., wherein the aforementioned disadvantage is alleviated. Therefore, according to the present invention, there is provided an electrically programmable read-only memory cell, characterized by a semiconductor substrate having a first conductivity type, a base region and a base contact region having a second conductivity type provided in said substrate, an emitter region having said first conductivity type provided in said base region, a dielectric layer provided over said base region and said base contact region and having openings formed therethrough, an anti-fuse structure including a region of undoped polysilicon in contact with said emitter region and a conductive layer of said first conductivity type, said anti-fuse structure having a defined periphery extend¬ ing over a portion of said dielectric layer, and conductive connections provided for said conductive layer and said base contact region. Further advantages of a memory cell according to the invention are high reliability and low manufac¬ turing cost. High reliability is aided since a passi¬ vation layer covering the device can be provided without apertures to permit the expulsion of blown fuse material. According to another aspect of the invention, there is provided a process of fabricating an electri¬ cally programmable read-only memory cell, character¬ ized by the steps of: providing a semiconductor sub- strate of first conductivity type; forming in said semiconductor wafer a base region of second conductiv¬ ity type and an associated adjacent base contact region of a second conductivity type; forming an emitter region of first conductivity type in said base region; providing a region of undoped polysilicon on said emitter region; forming a conductive layer having said first conductivity type on said region of undoped polysilicon; and providing an oh ic connection to said conductive layer, thereby forming a programmable anti- fuse structure connected to the emitter region of said bipolar transistor. In a preferred embodiment of the invention, a PROM cell is formed on a common chip with CMOS devic¬ es, the process according to the invention thus being seen to possess the advantage of co patability with CMOS processing technology. Thus, the preferred embodiment enables the provision of a PROM with a high density, merged, vertical fuse/bipolar transistor which can be fabricated by utilizing CMOS process technology to achieve a low cost PROM with low power consumption and high reliability. Brief Description of the Drawings Two embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figs. 1-8 are cross-sectional representations of an integrated circuit element showing the steps utilized in fabricating a single memory cell in an array of similar memory cells in accordance with a first embodiment of the invention; and Fig. 9 is a cross-sectional representation illustrative of a second embodiment of the invention. Best Mode for Carrying Out the Invention It should be understood that in the preferred embodiment a PROM is fabricated in a common structure with polysilicon gate CMOS devices (not shown) . Thus, a silicon wafer is processed to provide CMOS devices and vertical polysilicon anti-fuse structures which are merged with self-aligned emitters of respective bipolar transistors. The silicon wafers of one con¬ ductivity type, e.g. n-type, are provided with wells of the opposite conductivity type, e.g. p-wells, and vertical NPN devices fabricated in n-type " substrate regions. The PROM includes an array of cells, each having an emitter follower and a pad of semiconductor material which serves as an anti-fuse and constitutes the programmable element. For purposes of clarity, only a single cell is shown in the figures. Referring now to Fig. 1, there is shown a wafer, designated generally by the numeral 20, which includes a p+ base contact region 21 in an n- epitaxi- al layer 22, which has been grown on n+ bulk material 23 of the wafer. A field oxide layer 24 covering wafer 20 is disposed on top of the n- epitaxial layer 22 and in juxtaposition to the base contact region 21. A doped and patterned polysilicon interconnect elec- trode 27 is shown to be formed on top " of the field oxide layer 24. Although not shown in Fig. 1, the structure further includes self-aligned n+ source/drain regions for polysilicon gate NMOS devices in the CMOS struc- ture, formed by arsenic (n+) source/drain implant, anneal and drive-in steps, the areas of the PMOS devices and the PROM memory cells being masked during the arsenic implant, in accordance with known CMOS processing techniques. A blanket base ion implant step is then " performed to provide a p- active base region 28. The wafer is then annealed (to remove implant damage) at a . temperature of about 950 degrees C for about one hour. This diffuses base region 28 to a depth of about 0.5 microns. The surface of the wafer 20 is then masked to expose only the p+ base contact area, region 21, and the p+ source/drain regions of the polysilicon gate PMOS devices (not shown) included in the CMOS structure. These regions are then doped with boron in accordance with standard procedures and annealed, to produce the structure shown in Fig. 1. As is seen in Fig. 2, a layer of oxide 29 is deposited over the entire surface of the wafer. The oxide layer is then photolithographically masked so as to expose only the area 31 of the p- active base region 28 where the emitter is to be formed. The oxide 29 is then etched in accordance with convention¬ al practice down to the surface of active base region 28 to define the emitter contact area 31 on the active base region. Unlike other bipolar processes, areas of contact to other structures, such as the polysilicon 27 and base contact region 21, are not open at this point in the process. The emitter contact area 31 on the active base region 28 is then implanted with arsenic, using a dose of about 5 X 101*5 ions/cm2 at about 80 KeV. Upon annealing the wafer with approxi- ately 920 degrees C for approximately 30 minutes, a diffused emitter 32 which is approximately 0.25 mi¬ crons deep is formed in the active base region 28. Referring now to Fig. 3 , the fuse material is applied by depositing a layer of undoped polysilicon 33 to a thickness of approximately 0.5 microns over the- entire surface of the wafer 20. The surface of the undoped polysilicon layer 33 is then implant-doped with arsenic, using a dose of about 10 15 ions/cm 2 at about 40 eV to form an n+ conductive layer 34 approxi- mately 0.25 microns thick. An area 36 over the emit¬ ter contact area 31 is then photolithographically masked, and the exposed portion of the polysilicon layer is' etched away to leave a pad 37 of polysilicon, as is seen in Fig. 4. As is seen in Fig. 5, approximately 0.5 microns of silicon dioxide 38 may then be deposited uniformly over the entire wafer 20 in order to protect the edges of pad 37. The layer of silicon dioxide 38 is then etched away utilizing an anisotropic dry plasma etch applied normally with respect to the wafer 20, which leaves a deposit of oxide 39 in abutment with the peripheral edge 41 of the pad 37 (see Fig. 6).. This phenomenon results because the oxide layer 38 in the region adjacent to the edge of pad 37 is twice as thick as the oxide elsewhere. Since the oxide is not laterally etched, the deposit 39 remains after the etch. This sidewall oxide is not essential to the invention but may be a desirable process step for improved device integrity and yield. The wafer 10 is then annealed at a low temperature for a short period of time in an oxidizing ambient in order to grow approximately 100 Angstroms of oxide on the doped poly 34 to form a contact barri¬ er oxide layer 42 (see Fig. 6) . This short low tem¬ perature anneal forms the oxide layer 42 without causing excessive diffusion of arsenic from layer 34 into the adjacent layer 37. An appropriate anneal may be for two hours at 750 degrees C, with the first several minutes being performed in an oxidizing atmo¬ sphere. Referring now to Fig. 7, subsequent to the annealing step, standard CMOS processing is used to penetrate the oxide layer 29 and open contact areas 43 and 44 to the base contact region 21 and polysilicon interconnect 27, respectively. Contacts are also opened to CMOS device p+ and n+ diffused regions not shown in this figure. Referring to Fig. 8, electrical connections 50, 51 and 52 are made with the fuse pad 37, base contact region 21 and polysilicon interconnect 27, respectively, by depositing a layer of metal over the wafer 20 and etching unwanted metal away from areas 53 and 54 to separate the desired connections using standard photolithographic techniques. The thin oxide barrier layer 42 between the contact 50 and the poly¬ silicon fuse pad 37 stabilizes the low temperature annealed fuse to minimize any metal dissolution reac¬ tion during alloying of the contacts 51 and 52. Referring now to Fig. 9, in accordance with another embodiment of the invention, after the step of Fig. 7, oxide layer 42 is removed and a layer 59 of tungsten is deposited selectively on the fuse pad 37 (with or without the sidewall oxide 39) and on the contact surfaces 43 and 44 of the base 21 and inter¬ connect 27, respectively. The 250 to 1000 Angstroms thick tungsten layer 59 provides a contact barrier layer for subsequent metallization using 50, 51 and 52. After the wafer 20 is completed, a passivation layer is deposited. However, openings in the passivation layer over vertical anti-fuse areas are not required, (as in devices with lateral poly- silicon fuses) , since during programming of this PROM no material is expelled from the fuse pads 37. The aforedescribed process provides a merged, vertical fuse/bipolar transistor in conjunction with CMOS devices. The undoped polysilicon layer 37 func- tions as an "anti-fuse" which is stacked on the emit¬ ter 32 of a common collector NPN bipolar transistor to form a unique, high density, electrically programmable single transistor memory cell. The vertical, stacked configuration of the memory cell is provided while still obtaining the cost effectiveness and power advantages of CMOS peripheral circuitry. With reference to the embodiment in Fig. 8 of the drawings, the anti-fuse is programmed by forming a conductive path between metal interconnect 50 and diffuse emitter 32 through the application of appro¬ priate voltages to the NPN bipolar transistor. For example, the nominal resistance of several megohms between diffused emitter 32 and interconnect 50 can be reduced to the range of several thousand ohms by applying a current of one to .three milliamps for a period of one to two microseconds. These programming conditions are imposed on the device in Fig. 8 by connecting a nominal 13 volt bias to collector region 22, grounding interconnect metal 50 and applying .a .. nominal 13 volts to diffused base 21 by way of metal 51. To constrain the magnitude of the current through the NPN transistor, the base current is limited to approximately 100 microamps. Though the exact mechanism by which the conductive path is formed between diffused emitter 32 and metal 50 is not fully understood, it is known that the polysilicon layer 37 undergoes two changes. First, the grain structure of the polysilicon. in the region above diffused emitter 32 is reformed during programming to one of larger individual grains. Secondly, n-type dopant diffuses from emitter region 32 and doped polysilicon 34 to form a conductive path through formerly undoped polysilicon 37. The silicon dioxide of interfacial barrier oxide layer 42 has minimal effect on the programming of the anti-fuse because of its low dielectric integrity and the asper- ities on the upper surface of polycrystalline silicon 34. Note that in the alternate embodiment, depicted in Fig. 9, that the interfacial barrier oxide layer 42 is completely omitted.

Claims: - CLAIMS : 1. An electrically programmable read-only memory cell, characterized by a semiconductor sub¬ strate (22, 23) having a first conductivity type, a base region (28) and a base contact region having a second conductivity type provided in said substrate (22, 23), an emitter region (32) having said first conductivity type provided in said base region (28) , a dielectric layer (29) provided over said base region (28) and said base contact region (21) and having openings formed therethrough, an anti-fuse structure including a region of undoped polysilicon (37) in contact with said emitter region (32) and a conductive layer (34) of said first conductivity type, said anti- fuse structure having a defined periphery extending over a portion of said dielectric layer (29) , and conductive connections (50, 51) provided for said conductive layer (34) and said base contact region (21). 2. A memory cell according to claim 1, characterized by a protective oxide region (39) dis¬ posed around and in contact with the periphery of said anti-fuse structure (34, 37). 3. A memory cell according to claim 2, characterized in that an interfacial barrier oxide layer (42) is provided on said conductive layer (34) . 4. A memory cell according to claim 2, characterized in that a layer of tungsten (59) is provided on said conductive layer (34) . 5. A memory cell according to claim 1, characterized in that said anti-fuse structure has a thickness of approximately 0.5 microns. 6. A process of fabricating an electrically programmable read-only memory cell, characterized by the steps of: providing a semiconductor wafer (20); forming in a base region (28) of said " semiconductor wafer (20) an exposed emitter region (32) of a first conductivity type and an associated adjacent base contact region (21) of a second conductivity type for a bipolar transistor; providing a region of undoped polysilicon (37) on said emitter region (32) ; forming a conductive layer (34) having said first conductivity type on said region of undoped polysilicon (37) ; and providing an ohmic connection (50) to said conductive layer (34) , thereby forming a programmable anti-fuse structure (37, 34) connected to the emitter region (32) of said bipolar transistor. 7. A process according to claim 6, characterized in that semiconductor wafer (20) in¬ cludes an epitaxial layer of said first conductivity type embodying a collector region (22) for said bipo- lar transistor, and by the steps of forming in said epitaxial layer a base region (28) of said second conductivity type and forming said emitter region (32) in said base region (28) whereby a portion of said base region forms a base for said bipolar transistor. 8. A process according to claim 7, characterized in that said emitter region (32) is formed in said wafer (20) containing said base region (28) and said base contact region (21) by forming a layer of oxide (29) over said wafer (20) , masking the oxide layer (29) except in an area over an emitter region (31), etching the oxide layer (29) to expose an emitter area in said base region (28) , doping said emitter area with impurities of said first conductivi- ty type, and annealing said wafer (20) to form said emitter region (32) . - 9. A process according to claim 8, characterized in that said anti-fuse structure (37, 34) is formed by depositing a layer of undoped poly¬ silicon (33) over said emitter region " (32) and said oxide layer (29) , doping the exposed surface of the polysilicon layer (33) to form said conductive layer (34) in said polysilicon layer (33) , masking the polysilicon layer (33) in an area (36) overlying and adjacent to the emitter region (32) and etching away the unmasked areas of said polysilicon layer (33) to leave said anti-fuse structure (37, 34) overlying said emitter region (32) and having a periphery overlying said oxide layer (29) . 10. A process according to claim 9, characterized by the step of forming a layer of sili¬ con dioxide (38) over said wafer (20) including said anti-fuse structure (37, 34) and etching away the layer of silicon dioxide (38) to leave a protective deposit of silicon dioxide (39) in abutment with the periphery of said antifuse structure (37, 34) . 11. A process according to claim 10, characterized by the step of providing, in said layer of silicon dioxide (38) a contact area (43) for said base contact region (21) , and providing metal contacts (50, 51) overlying said anti-fuse structure (37, 34) and said base contact region (21) .

Inventors: ELLSWORTH DANIEL LLOYD, SULLIVAN PAUL ANDREW, ELLSWORTH, DANIEL, LLOYD, SULLIVAN, PAUL, ANDREW
Applicants: NCR CO, NCR CORPORATION
Application year: 1985
Main classification: H01L29
IPC codes: H01L23, H01L27