METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING AN OXYGEN-CONTAINING POLYCRISTALLINE SILICON LAYER

Abstract: In a method of making a semiconductor device (11) with a resistor (13) of high resistance, a first polycrystalline silicon layer (18) is formed to connect with an electrically connecting portion (17) in a semiconductor substrate (14), and a second polycrystalline silicon layer (19) containing oxygen and forming said resistor (13) is formed on the first polycrystal­ line silicon layer (18). Then, oxide formed between the two polycrystalline silicon layers (18,19) is removed by annealing.

Description: This invention relates to methods of manufacturing semiconductor devices having an oxygen-containing polycrystalline silicon layer. Figure 3 of the accompanying drawings shows a circuit diagram of a resistor load-type static random access memory (SRAM) in the form of a semiconductor device having a semiconductor substrate with a resistor electrically connected to the substrate, and including field effect transistors (FETs)12 and resistors 13. Figure 1 of the accompanying drawings shows a sectional view of a first previously-proposed example of the SRAM 11. In this example, an SiO₂ layer 15 is formed on an Si substrate 14. A diffusion region 17 is formed in the substrate 14 by diffusion through an opening 16 formed in the SiO₂ layer 15. The diffusion region 17 acts as the drain for the FET 12. A polycrystalline Si layer 18 is formed to cover the diffusion region 17 and the SiO₂ layer 15. The polycrystalline Si layer 18 acts as the resistor 13. The stand-by current of the SRAM 11 is determined by the resistance of the resistor 13. In the above example, the polycrystalline Si layer 18 serving as the resistor 13 has a relatively low resistivity of 5 x 10⁵ ohm.cm. Therefore, the stand-by current of the SRAM 11 is relatively high, and power consumption is high. These problems become particularly noticeable when a number of SRAMs 11 are integrated. Figure 2 of the accompanying drawings shows a second previously-proposed example of the SRAM 11, forming an improvement over the first example. The SRAM 11 of this example is substantially the same as that of the first example except that a polycrystalline Si layer 19 containing oxygen is used in place of the pure polycrystalline Si layer 18. As disclosed in issued Japanese Patent No. 55/13426, polycrystalline Si containing oxygen has a very high resistivity: about 2 x 10⁶ ohm.cm at an oxygen content of 2%, and about 10¹⁰ ohm.cm at an oxygen content of 20%. A semiconductor device having a layer of polycrystalline Si containing oxygen formed on a semiconductor substrate is also described in issued Japanese Patent No. 53/2552. The polycrystalline Si layer 19 containing oxygen is formed by a low-pressure chemical vapour deposition (CVD) method using, for example, SiH₄ (flow rate: 50 cc/min), N₂O (flow rate: 2 cc/min), and N₂ or He as needed. In this case, in order to stabilize the N₂O flow rate, only N₂O is supplied for 1 to 2 minutes before the SiH₄ is supplied. Therefore, the Si surface of the substrate 14 is oxidized, and a thin SiO₂ layer 20 is formed between the diffusion region 17 and the polycrystalline Si layer 19 containing oxygen. When P or As is doped in a connecting portion between the diffusion region 17 and the polycrystalline Si layer 19 in order to reduce the connection resistance of this connecting portion, the SiO₂ layer 20 becomes PSG or AsSG. Even if annealing is performed after the polycrystalline Si layer 19 has been formed, the SiO₂ layer 20 remains unchanged. Therefore, it is very difficult ohmically to connect the diffusion region 17 and the polycrystalline Si layer 19. As can thus be seen, it is difficult to obtain a sufficiently high resistance with the pure polycrystalline Si layer 18, while it is also difficult ohmically to connect the polycrystalline Si layer 19 containing oxygen to the diffusion region 17. US patent specifications US-A-4 001 762 and US-A-4 406 051 disclose further examples of semiconductor devices in which resistive elements formed of polycrystalline silicon containing oxygen are provided. According to the present invention there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a first polycrystalline silicon layer over at least an impurity diffusion region formed in a semiconductor substrate; and forming a second polycrystalline silicon layer, containing oxygen, on said first polycrystalline silicon layer; characterised in that: said second polycrystalline silicon layer contains 2 to 10 atomic % of oxygen; and said semiconductor substrate on which said first and second polycrystalline silicon layers are formed is annealed in a nitrogen atmosphere at 900 to 1000°C for 20 to 60 minutes. In methods embodying the present invention, an oxide formed between the first and second polycrystalline silicon layers upon formation of the second polycrystalline silicon layer containing oxygen is dispersed over the first and second polycrystalline silicon layers, thereby ohmically connecting the electrically connecting portion of the semiconductor substrate and the second polycrystalline silicon layer. In addition, a high resistance can be obtained in the second polycrystalline silicon layer. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figures 1 and 2 are sectional views of respective previously-proposed examples of SRAMs; Figure 3 is a circuit diagram showing an SRAM to which the present invention can be applied; Figure 4 is a sectional view showing steps in a first method embodying the present invention; and Figure 5 is a sectional view showing a step in a second method embodying the present invention and corresponding to the step shown in Figure 4E. In the first method embodying the invention, as shown in Figure 4A, an SiO₂ layer 15 is formed on an Si substrate 14. A diffusion region 17 is formed in the substrate 14 by diffusion through an opening 16 formed in the SiO₂ layer 15. Subsequently, as shown in Figure 4B, a polycrystalline Si layer 18 having a thickness of 5 to 20 nm is formed by a low-pressure CVD method on the diffusion region 17 and the SiO₂ layer 15. Since a gas containing oxygen is not used in this step, an SiO₂ layer is not formed between the diffusion region 17 and the polycrystalline Si layer 18. As shown in Figure 4C, a polycrystalline Si layer 19 containing 2 to 10 atomic % of oxygen and having a thickness of 150 to 400 nm is then formed by a low-pressure CVD method on the polycrystalline Si layer 18. In this process, as in the case of the example of Figure 2, the polycrystalline Si layer 18 is oxidized, and an SiO₂ layer 20 having a thickness of about 1 to 3 nm is formed between the first and second Si layers 18 and 19. As shown in Figure 4D, in order to reduce the connecting resistance between the diffusion region 17 and the polycrystalline Si layer 18, P or As ions 21 are ion-implanted in the connecting portion at a dose of 1 x 10¹⁶cm⁻² and an acceleration energy of 70 keV. The Si substrate 14 on which the polycrystalline Si layers 18 and 19 are formed is annealed in an N₂ atmosphere at 900 to 1,000°C for 20 to 60 minutes. Then, as shown in Figure 4E, the Si crystal grains of the polycrystalline Si layers 18 and 19, which had sizes of 2 to 5 nm, grow into Si crystal grains 22 having sizes of about 20 nm. The SiO₂ layer 20, which was sandwiched between the polycrystalline Si layers 18 and 19, is formed into SiO₂ masses 23 that are dispersed between the Si crystal grains 22. As a result, as shown in Figure 4E, the SiO₂ layer 20 disappears. The polycrystalline Si layers 18 and 19 are ohmically connected and thus the polycrystalline Si layer 19 and the diffusion region 17 are also ohmically connected. When the SRAM 11 is manufactured by this method, a resistor 13 having a resistance several times to several hundred times that of the example of Figure 1, using only the polycrystalline Si layer 18, can be formed. The stand-by current can be reduced to from 1/n to 1/100n (where n is a positive integer smaller than 10). Furthermore, the SiO₂ layer does not remain as in the case of the example of Figure 2. Therefore, the resistor 13 and the drain of the FET 12 can be ohmically connected. Growth of crystal grains as described above is also described in M. Hamasaki et al, "Crystal graphic study of Semi-insulating polycrystallize silicon (SIPOS) doped with oxygen atoms", J.A.P. 49(7), July 1978, pp 3987 to 3992, and T. Adachi et al, "AES and PES studies of Semi-insulating polycrystallize silicon (SIPOS) films", J.E. CS Vol. 127, No. 7, July 1980, pp 1617 to 1621. Figure 5 shows the second method embodying the invention and corresponds to Figure 4E of the first method. The second method has substantially the same steps as those of the first method except that the polycrystalline Si layer 18 is formed not on the entire surfaces of the diffusion region 17 and the SiO₂ layer 15, but only on the diffusion region 17 and the portion of the SiO₂ layer 15 near the diffusion region 17. In the SRAM 11, the polycrystalline Si layer 19 is used as a resistor in a direction along the surface of the Si substrate 14. However, when the polycrystalline Si layer 18 is formed on the entire surface of the Si substrate 14 as shown in Figure 4E, a current also flows in the polycrystalline Si layer 18. Since the polycrystalline Si layer 18 has a lower resistivity than that of the polycrystalline Si layer 19, the polycrystalline Si layer 18 must be made extremely thin as compared with the polycrystalline Si layer 19 in order to obtain a high overall resistance. However, it is not easy to form a very thin polycrystalline Si layer 18, and product reliability also suffers when such a thin layer is used. As in this method, however, if the polycrystalline Si layer 18 is formed only near the diffusion region 17 to be in ohmic contact with the polycrystalline Si layer 19, a resistor portion 24 in the polycrystalline Si layer 19 serving as a resistor 13 of the SRAM 11 has a high resistance. Therefore, since the polycrystalline Si layer 18 can be formed to have a thickness of 100 to 200 nm larger than in the first method, the polycrystalline Si layer 18 can be formed easily and product reliability is improved. In the first and second methods, the present invention is applied to the manufacture of SRAMs. However, the invention can also be applied to the manufacture of devices other than SRAMs.

Claims: A method of manufacturing a semiconductor device (11), comprising the steps of: forming a first polycrystalline silicon layer (18) over at least an impurity diffusion region (17) formed in a semiconductor substrate (14); and forming a second polycrystalline silicon layer (19), containing oxygen, on said first polycrystalline silicon layer (18); characterised in that: said second polycrystalline silicon layer (19) contains 2 to 10 atomic % of oxygen; and said semiconductor substrate (14) on which said first and second polycrystalline silicon layers (18,19) are formed is annealed in a nitrogen atmosphere at 900 to 1000°C for 20 to 60 minutes. A method according to claim 1 wherein said first and second polycrystalline silicon layers (18,19) are formed overlying the same region of said semiconductor substrate (14). A method according to claim 1 wherein said first polycrystalline silicon layer (18) is formed only near said impurity diffusion region (17). A method according to claim 1, claim 2 or claim 3 wherein said first polycrystalline silicon layer (18) has a thickness of 100 to 200 nm. A method according to claim 1, claim 2 or claim 3 wherein said first polycrystalline silicon layer (18) has a thickness of 5 to 20 nm, and said second polycrystalline silicon layer (19) has a thickness of 150 to 400 nm. A method according to any one of the preceding claims wherein P or As ions are implanted to reduce the resistance between said first polycrystalline silicon layer (18) and said impurity diffusion region (17). A method according to any one of the preceding claims wherein said first and second polycrystalline silicon layers (18,19) serve as a resistor (13) of a SRAM (11). A method according to claim 6 wherein said impurity diffusion region (17) is a drain region of an FET (12) of said SRAM (11).

Inventors: SUZUKI, HIDEO C/O PATENTS DIVISION, YAMOTO, HISAYOSHI C/O PATENTS DIVISION
Applicants: SONY CORPORATION
Application year: 1985
Main classification: H01L21
IPC codes: H01L27, H01L21