APPARATUS FOR SCROLLING DISPLAY IMAGES

Abstract: Apparatus for scrolling the display of images obtained from a plurality of data units, each having pattern signals repre­ senting a plurality of horizontal lines and a corresponding col­ our signal, comprises a video display (15) having a plurality of horizontal display lines, a first memory (14P) for storing the pattern signals formed with first addresses corresponding to the plurality of horizontal display lines and a first buffer area for temporarily storing received pattern signals, and a second memory (14C) for storing the colour signal formed with second addresses corresponding to the numbers of the data units and a second buffer area for temporarily storing a received colour signal, the pattern signals and a corresponding colour signal being stored in the first and second buffer areas, respectively. A read out system (16 - Figure 9) operates so that the first memory (14P), including the first buffer area, is read out by ac­ cessing the first addresses in a predetermined order and so that the second memory (14C), including the second buffer area, is read out by accessing the second addresses in a predetermined order. Also provided is a circuit for transferring the pattern sig­ nal of a horizontal line stored in the first buffer area to a corre­ sponding address of the first memory (14P) and for transferring a corresponding colour signal stored in the second buffer area to a corresponding address of the second memory (14C), and a circuit for supplying the pattern signals and the correspond­ ing colour signal to the video display (15).

Description: This invention relates to apparatus for scrolling display images. Systems have been proposed utilising standard telephone network lines to transmit various kinds of image information and to display such image information on a picture screen of a television receiver. One such proposed system is the so-called CAPTAIN ( c haracter a nd p attern t elephone a ccess i nformation n etwork) videotex or viewdata system as used in Japan and another such system is the PRESTEL videotex or viewdata system as used in the United Kingdom. In the CAPTAIN system the format of the picture display screen comprises 204 dots in the column direction and 248 dots in the row direction. In describing such screen display, the following definitions are generally employed: (1) "dot": the minimum unit for forming the picture screen; (2) "line": a series of 248 dots in the lateral or horizontal direction of the picture display screen that is used as the minimum unit indicating the display position in the longitudinal or vertical direction; (3) "sub-row": a number of display areas each of which is formed by dividing the display picture screen at its upper end by an area including 248 dots in the row direction and 12 dots in the column direction and which is used as a unit indicative of the display position in the column direction; (4) "sub-column": a number of display areas each of which is formed by dividing the display picture screen at its upper left-hand end by an area including 8 dots in the row direction and 204 dots in the column direction and which is used as a unit indicating the display position in the row direction; (5) "sub-block": a display area where the sub-column and the sub-row overlap that is used to specify the colour; and (6) "picture screen header": the uppermost sub-row on which is displayed a title or the like concerning the information currently being displayed, that is, the monitor display. A typical picture display screen is formed of 17 sub-rows x 204 lines and one sub-row is formed of 12 lines. However, in the following description, when the lines are counted from top to bottom, they are numbered from the 1st line to the 204th line, respectively, and when the lines are counted at every sub-row, they are numbered from the 1st to the 12th line of each sub-row, respectively. Further, the sub-rows are numbered as the 0th sub-row to the 16th sub-row, respectively. Generally, the format of data signals which are transmitted from a data base centre of a CAPTAIN system to a terminal apparatus of a user is chosen such that one section of the format is called a "packet". Each of these packets includes at its beginning a packet code indicating the kind of the packet it belongs to. Generally, there is a picture screen control packet, a colour information packet, and a small character sequential display packet. Further, the picture screen control packet includes, following the packet code, a code indicative of the display mode and a code for designating the colour of the picture screen header and the like. The colour information packet includes a code indicating to which sub-row the packet belongs, or the display position per sub-row unit in the column direction, and a colour code for specifying the colour of each sub-block in the sub-row designated by this code, and so on. Additionally, the small character sequential display pattern packet includes a code indicating to which line the packet belongs, or indicating the display position of the line unit in the longitudinal direction and pattern data indicative of dots on the line designated by this code. These packets are divided by flags, each of which has a particular bit arrangement, and then transmitted from the data base centre of the CAPTAIN system to the terminal apparatus of the user. The above-described picture screen control packet can designate a fixed display mode and a scroll display mode and, in the scroll display mode, a difference between the display position of the displayed picture information and the display position of newly received picture information is obtained and the picture information being displayed is shifted upwardly by the amount of this difference. Thus, the picture information is displayed such that the new picture information is inserted into the lowermost portion of the display picture screen. The picture screen header is not displayed in the scroll display mode. One kind of terminal apparatus for the CAPTAIN system is controlled by a microcomputer having a central processing unit (CPU) for parallel processing, a read only memory (ROM) in which its processing program is stored, a random access memory (RAM) for work area and buffer area, a video RAM having a capacity of one picture screen amount or more, a colour picture tube, a read address control circuit, and a deflecting circuit. The output from the deflecting circuit is supplied to the colour picture tube in which the deflection is carried out. A synchronising signal from the deflecting circuit is supplied to a read address control circuit which then produces a read address signal corresponding to the deflection position of the picture tube. This signal is supplied also to the video RAM. Accordingly, address data corresponding to the deflection position of the colour picture tube can be read out from the video RAM and this data is supplied to the colour picture tube which displays the data which is written in the video RAM. Additionally, circuitry is required for connection to the telephone lines used to transmit the data. Consequently, the data signal from the data base centre of the CAPTAIN system fed through the telephone network lines is demodulated by a modulator/demodulator, converted from a series signal to a parallel signal by a serial-to-parallel converting circuit and then fed to the CPU. Conversely, a data request signal from the CPU is converted from parallel to serial form by a parallel-to-serial converting circuit, modulated by the modulator/demodulator and then fed through the telephone network line to the data base centre of the CAPTAIN system. When the above-mentioned scrolling display is carried out, the data access for the video RAM is generally carried out such that the video RAM is formed into one section in which the pattern data is accessed and one section in which the colour code is accessed. Reading out of the video RAM sections is carried out at every field in synchronism with the scanning of the colour picture tube. The read address of the first section of the video RAM is varied at every horizontal period while, since the colour is determined on a sub-block unit basis and one sub-block is formed of 12 lines, the read address of the second section of the video RAM is varied at every 12 horizontal lines. Since the data transmission from the data base centre of the CAPTAIN system and the scanning of the colour picture tube are not synchronised with each other, the writing and the reading of data into and out of the video RAM sections are not always carried out alternately; and, since the data transmission rate is lower than the display speed, the data is read out several times for one writing. In short, upon scrolling display, the first to 12th addresses of the first video RAM section and the 0th address of the second video RAM section are used for the picture screen header and the data is written therein once. However, the last addresses or 216th and 17th addresses of the video RAM sections are connected to the 13th and first addresses thereof in an operation standpoint. Thus, the 13th to 216th addresses of the first section of the video RAM and the first to 17th addresses of the second section of the video RAM are formed as so-called ring shapes, respectively. Then, newly received data is written in the next addresses (the addresses followed by the 216th and 17th addresses are the 13th and 1st addresses) of the ring shapes. The scrolling display is generally carried out as mentioned above. In this method, however, when the data of the colour information packet or the small character sequential display pattern packet is not obtained due to noise and so on, mis-matching will occur between the pattern and the colour which will thereafter be scroll-displayed. More particularly, since the colour code and the pattern data of the 0th sub-row of the 1st page are the picture screen header and they are not scrolled, except the colour code and the pattern data as described above, the beginning of each page becomes the 1st sub-row. For example, considering the addresses of the video RAM sections in which the colour code of the 1st sub-row and the pattern data of the 1st line are written, they are written in the 17th and 205th addresses with respect to the 1st page, while they are written in the 16th and 193rd addresses with respect to the 2nd page, and they are written in the 15th and 181st addresses with respect to the 3rd page. In other words, if the page is changed, even with the same sub-row and the same line, the addresses in which the colour code and the pattern data thereof are written are decremented at every page by 12 addresses and 1 address, respectively. Accordingly, even if the colour information packet and the small character sequential display pattern packet contain the codes indicative of their display positions, the addresses in which the data is written are changed with the pages so that it is very difficult to write the colour code or the pattern data in the two sections of the video RAM by using the display position codes. To cope with this defect, when the colour code or the pattern data is obtained, the colour code or the pattern data is written in the address following the address in which the previous colour code or pattern data is written. Accordingly, if the colour code of the colour information packet at its n -th address is not obtained, for example due to noise, the colour code of the colour information packet at its (n + 1)th address is written in the address in which the colour code of the colour information packet at the n -th address should be written. Thus, thereafter, all colour codes are written in the video RAM with addresses decremented by every one address (the colour code of one sub-row amount is displaced upwardly in the picture screen). As a result, if such colour code and the pattern data are read out to thereby carry out a scrolling display, all the pictures under the sub-row of which the colour code cannot be obtained are scroll-displayed with the colour being displaced by one sub-row amount relative to the pattern data, and this is continued until the scrolling display is ended. On the other hand, when the pattern data of the small character sequential display pattern packet is not obtained, due to a similar reason, the succeeding pattern data is incremented by one address and then written in the video RAM thereafter. Consequently, all picture images below the line of which the pattern data is not obtained are scroll-displayed such that the patterns and the colours thereof are mis-matched by one line each. This is continued until the scrolling display is ended. Thus, as described above, if the colour code of the colour information packet and/or the pattern data of the small character sequential display pattern packet are not obtained, in the following scrolling display the pattern and its colour are all displaced with respect to each other. European Patent Application Publication No EP-A-0 104 431 discloses apparatus for scrolling a display image, the apparatus comprising: first memory means storing data representing the entire area of a large image; display means for producing a visual display of part of the large image; second memory means for storing a part of the large image to be displayed; and memory control means operative to control the first and second memory means to provide a scrolling display image. According to the invention there is provided apparatus for scrolling a display image derived from a plurality of data units, each having pattern signals formed of a plurality of horizontal lines and a corresponding colour signal, the apparatus comprising: display means for producing a visual display of an input signal as a plurality of horizontal lines; first memory means connected for receiving and storing the pattern signals and having a plurality of first addresses corresponding respectively to the plurality of horizontal display lines and having a first buffer area for temporarily storing the received pattern signals; second memory means connected for receiving and storing the colour signal and having a plurality of second addresses corresponding respectively to the plurality of data units and having a second buffer area for temporarily storing the received colour signals; means operative to store the received pattern signals and corresponding colour signals in the first and second buffer areas, respectively; and memory control means operative to control the first and second memory means such that the first memory means including the first buffer area is read out to the display means by accessing the first addresses in a first predetermined order and the second memory means including the second buffer area is read out to the display means by accessing the second addresses in a second predetermined order, and such that a pattern signal of a horizontal line stored temporarily in the first buffer area is transferred to a corresponding address of the first memory means and a corresponding colour signal stored temporarily in the second buffer area is transferred to a corresponding address of the second memory means, whereby the pattern signals and the corresponding colour signals are fed to the display means to provide a scrolling display image. Apparatus embodying the invention and described hereinbelow can prevent a displayed pattern and its associated colour from being displaced relative to each other. The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which like references designate like elements and parts throughout, and in which: Figures 1A and 1B are diagrammatic representations of data formats for a picture screen of a CAPTAIN ( c haracter a nd p attern t elephone a ccess i nformation n etwork) system; Figures 2A to 2C are diagrammatic representations of formats for data signals used in the CAPTAIN system; Figure 3 is a diagrammatic representation of a combination of data signals present upon scrolling display; Figure 4 is a block diagram of a special terminal apparatus used in the CAPTAIN system; Figures 5A to 5L are pictorial representations of data arrangements useful in explaining the accessing operation of a video RAM used in the terminal apparatus of Figure 4; Figures 6A to 6D are pictorial representations of data arrangements useful in explaining the accessing operation of the video RAM of Figure 4; Figures 7A to 7Q are pictorial representations of data arrangements useful in explaining apparatus embodying the present invention; Figures 8A to 8Q are pictorial representations of data arrangements relative to the video RAM of Figure 4 useful in explaining apparatus embodying the present invention; and Figure 9 is a block diagram of a scrolling image display apparatus embodying the present invention. Figures 1 to 3 illustrate data formats for the CAPTAIN system. More specifically, Figures 1A and 1B are diagrams showing the format of the picture display screen. The picture screen is formed of 204 dots in the column direction by 248 dots in the row direction, and the terms used in describing such picture screen are as defined hereinabove. One display picture screen is formed of 17 sub-rows x 204 lines and one sub-row is formed of 12 lines. In the following description, when the lines are counted from top to bottom, they are numbered as the 1st line to the 204th line, respectively, and when the lines are counted at every sub-row, they are denoted the 1st to 12th line of each sub-row, respectively. Further, the sub-rows are numbered as the 0th sub-row to the 16th sub-row, respectively. Figures 2A to 2C are diagrams showing the formats of data signals that are transmitted from a data base centre of a CAPTAIN system to the terminal apparatus of each user, shown in more detail in Figure 4. One section of the format is called a "packet". Figure 2A illustrates a picture screen control packet (hereinafter simply referred to as a "G packet"); Figure 28 illustrates a colour information packet (hereinafter simply referred to as a "C packet"); and Figure 2C illustrates a small character sequential display pattern packet (hereinafter simply referred to as an "S packet"). Each of these packets includes at its beginning a packet code or portion indicating what kind of packet it is. The packet code is followed by two other codes or portions. The three codes or portions of each packet and the bit lengths thereof are shown in Figures 2A to 2C. Following the packet code, the G packet includes a code indicative of the display mode and a code for designating the colour of the picture screen header or the like. The C packet includes a code indicating to which sub-row the packet belongs, or indicating the display position per sub-row unit in the column direction, and a colour code for specifying the colour of each sub-block in the sub-row designated by this code. The S packet includes a code indicating to which line the packet belongs, or indicating the display position of the line unit in the longitudinal direction, and pattern data indicative of dots on the line designated by this code. The packets are divided by flags, each of which has a particular bit arrangement, and are then transmitted from the data base centre of the CAPTAIN system to the terminal apparatus of the user. With regard to the display modes designated by the above-described G packet, there can be a fixed display mode and a scroll display mode. In the scroll display mode, a difference between the display position of the displayed picture information and the display position of newly received picture information is obtained, and the picture information being displayed is shifted upwardly by the amount of this difference. Thus, the picture information is displayed in such a way that the new picture information is inserted into the lowermost portion of the picture display screen. However, the picture screen header is not displayed in the scroll display mode. Accordingly, in the scroll display mode, the packets are transmitted in the combinations as shown in Figure 3, that is, the G packet is transmitted first and then the C packet (0) for designating the colour of the 0th sub-row and so on is transmitted. Thereafter, 12 S packets (0 - 1) to (0 - 12) including pattern data of 12 lines at the 0th sub-row are transmitted sequentially. The picture screen header is displayed in the 0th sub-row by the C and S packets (0), (0 - 1) to (0 - 12), respectively. Subsequently, the C packet for designating the colour of the first sub-row is transmitted and then 12 S packets (1 - 1) to (1 - 12) including the pattern data of the lines of the first sub-row are transmitted sequentially. Similarly, the C packet and the S packet are transmitted sequentially thereafter. Thus, the picture information is continuously being shifted one-by-one upwardly on the picture screen. When the S packet (16 - 12) of the last line of the 16th sub-row (204 lines in total) is transmitted and then displayed on the display picture screen, the display of the first page is completed and the next succeeding page is scroll-displayed by the respective C and S packets following the first page. Figure 4 illustrates an example of a special terminal apparatus 10 for use in the CAPTAIN system. A telephone subscriber's telephone network line 1 and a standard telephone 2 are connected to the terminal apparatus 10. The terminal apparatus 10 is controlled by a microcomputer, including an 8-bit central processing unit (CPU) 11 for parallel processing, a read only memory (ROM) 12 in which a processing program is stored, a random access memory (RAM) 13 for work area and buffer area, and a video RAM 14 having a data capacity of at least one picture screen amount. A colour picture tube or cathode ray tube (CRT) 15 is provided together with a read address control circuit 16 and a deflection circuit 17. An output signal from the deflection circuit 17 is fed to the colour picture tube 15, in which the deflection is carried out, and a synchronising signal from the deflection circuit 17 is fed to the read address control circuit 16, which then produces a read address signal corresponding to the deflection position on the picture tube 15, and this read address signal is fed to the video RAM 14. Accordingly, address data corresponding to the deflection position on the colour picture tube 15 is read out from the video RAM 14 and this data is supplied to the colour picture tube 15, which therefore displays thereon the data which is written in the video RAM 14. The terminal apparatus 10 also comprises a hybrid circuit or line coupling unit (LCU) 21, a modulator and demodulator (MODEM) 22, a serial-to-parallel converting circuit 23, a parallel-to-serial converting circuit 24, input/output (I/O) ports or interface circuits 25 and 26, and a key pad 27 for use by a user to carry out various operations. The LCU 21 is controlled by the output of the CPU 11 through the interface circuit 25 and, upon use of the CAPTAIN system, the telephone network line 1 is coupled through the LCU 21 to the MODEM 22. Consequently, a data signal supplied from the data base centre of the CAPTAIN system through the telephone network line 1 is demodulated by the MODEM 22, converted from a serial signal to a parallel signal by the serial-to-parallel converter 23, and then fed to the CPU 11. Conversely, a data signal, which is a request signal, from the CPU 11 is converted from a parallel signal to a serial signal by the parallel-to-serial convertor 24, modulated by the MODEM 22 and then fed through the telephone network line 1 to the data base centre of the CAPTAIN system. Only that portion of the CAPTAIN system that relates to this invention is summarised above and it is to be understood that other elements and data are involved. For example, there is a packet which includes other data. Nevertheless, such packet is not directly related to this invention and can be represented by the above-described packets, so that its detailed description can be omitted for the sake of brevity and clarity. When a scrolling display is carried out, data access for the video RAM 14 is generally carried out in a manner represented in Figures 5A to 5L and 6A to 6D. Figures 5A to 5L schematically illustrates internal addresses of the video RAM 14, the reference numeral 14P designating a video RAM section (hereinafter referred to as a video RAM) in which pattern data is accessed and the reference numeral 14C designating a video RAM section (hereinafter referred to as a video RAM) in which the colour code is accessed. In the video RAM 14P, numerals (1 to 216) represent line addresses, in which the pattern data of one line can be accessed from each address and, further, in the video RAM 14C, numerals (0 - 17) represent sub-row addresses of the RAM 14C, in which the colour code of one sub-row can be accessed from each address. The addresses 1 to 12 of the video RAM 14P and the 0th address of the video RAM 14C correspond to the picture screen header. Figure 6 shows exclusively the addresses 1 to 12 and the 0th address of the video RAMs 14P and 14C which correspond to the piocture screen header. In Figures 5A to 5L and 6A to 6D, the cross-hatched addresses indicate those at which the newest data of each page is written. Reading out of the video RAMs 14P and 14C is carried out at every field in synchronism with the scanning of the colour picture tube 15. In this case, in Figures 5A to 5L and 6A to 6D, arrows 1 ○ and 2 ○ indicate a range of addresses being accessed and the order thereof in the reading at every field, respectively. The read address of the RAM 14P is varied at every horizontal period, while, because the colour is determined on a sub-block unit basis and one sub-block is formed of 12 lines, the read address of the video RAM 14C is varied at every 12 horizontal lines. For example, when the 1st to 12th addresses of the video RAM 14P are read out sequentially, the 0th address of the video RAM 14C is read out 12 times simultaneously. Because the data transmission from the data base centre of the CAPTAIN system and the scanning of the colour picture tube 15 are not synchronised with each other, the writing in and the reading out of data relative to the video RAMs 14P and 14C are not always carried out strictly alternately; and, because the data transmission rate is lower than the display rate, the data is read out several times for one writing in period. Accordingly, when a scrolling display is carried out, and if the data is transmitted as shown in Figure 3, the following operations will be carried out. (i) Whe the C packet (0) of the 0th sub-row is transmitted, the colour code is written in the 0th address of the video RAM 14C, as shown by the cross-hatched portion in Figure 6A, but, as shown in Figure 5A, the reading of the video RAM 14P is started from the first address and carried out continuously up to the 204th address, while, at the same time, the reading of the video RAM 14C starting from the 0th address up to the 16th address is continuously carried out 12 times. (ii) When the S packet (0 - 1) of the first line of the 0th sub-row is transmitted, the pattern data thereof is written in the first address of the video RAM 14P, as shown by the cross-hatched portion of Figure 6B, and the reading of the video RAMs 14P and 14C is the same as that of operation (i) above. (iii) When the S packet (0 - 2) of the second line of the 0th sub-row is transmitted, the pattern data thereof is written in the second address of the video RAM 14P, as shown by the cross-hatched portion of Figure 6C, and the reading of the video RAMs 14P and 14C is again the same as that of operation (i) above. (iv) A similar operation is repeated and, when the packet (0 - 12) of the 12th line of the 0th sub-row is transmitted, the pattern data thereof is written in the 12th address of the video RAM 14P, as shown by the cross-hatched portion in Figure 6D, and the reading of the video RAMs 14P and 14C is also the same as that of operation (i) above. Consequently, by reading in according to the operations (i) to (iv) above, the picture screen header is displayed in colour at the position of the 0th sub-row on the picture screen of the colour picture tube 15. (v) When the C packet (1) of the first sub-row is transmitted, the colour code thereof is written in the 17th address of the video RAM 14C, as shown by the cross-hatched portion of Figure 5B, and the reading is the same as that of operation (i) above. (vi) When the S packet (1 - 1) of the first line of the first sub-row is transmitted, the pattern data thereof is written in the 205th address of the video RAM 14P, as shown by the cross-hatched portion of Figure 5B, and, when the writing is ended, as shown in Figure 5B, the reading of the video RAM 14P is sequential, starting from the 1st address to the 12th address and then skipping to the 14th address. Thereafter, the reading of the video RAM 14P is sequentially carried out from the 14th address to the 205th address. At the same time, although the reading of the RAM 14C is started from the 0th address, the succeeding first address is read out 11 times (normally 12 times) and the 2nd to 12th addresses are read out 12 times each. Finally, the 17th address is read out once. Accordingly, as a result of this reading, the picture screen header is displayed in colour at the position of the 0th sub-row on the screen of the colour picture tube 15 and the first line of the first sub-row is displayed in colour at the position of the lowermost line thereon. That is, scrolling display is started. (vii) When the S packet (1 - 2) of the second line of the first sub-row is transmitted, the pattern data thereof is written in the 206th address of the video RAM 14P as shown by the cross-hatched portion of Figure 5C, and, after this writing, as shown in Figure 5C, the reading of the video RAM 14P is carried out with respect to the area 1 ○, then skips to the 15th address and is carried out sequentially from the 15th address to the 206th address. At the same time, the reading of the video RAM 14C is moved from the area 1 ○ to the first address, the first address is read out 10 times, and the addresses from the second address to the 16th address are read out 12 times each. Thereafter, the 17th address is read out twice. Accordingly, as a result of this reading, the picture screen header is displayed in colour at the position of the 0th sub-row, and the first and second lines of the first sub-row are displayed in colour at the positions of the next following two lines. That is, a scrolling display of one line is carried out for operation (vi). (viii) Subsequently, a similar operation is carried out and, when the S packet (1 - 12) of the 12th line of the first sub-row is transmitted, the pattern data thereof is written in the 216th address of the video RAM 14P, as shown by the cross-hatched portion of Figure 5D. After this writing (Figure 5D) the reading of the video RAM 14P is carried out on the area 1 ○, then skips to the 25th address and the addresses from the 25th address to the 216th address are read out sequentially. At the same time, although the first address of the video RAM 14C should be read out after the area 1 ○, that reading is not carried out, or the reading of the 1st address is skipped, and the reading is then moved to the 2nd address. Then, the 2nd to the 17th addresses are read out sequentially 12 times each. Thus, under this condition, the picture screen header is displayed in colour at the position of the 0th sub-row and the 1st sub-row is displayed in colour at the position of the lowermost sub-row (the 16th sub-row). That is, a scrolling display of one sub-row amount is carried out. (ix) When the C packet (2) of the second sub-row is transmitted, the colour code thereof is written in the 1st address of the video RAM 14C, as shown by the cross-hatched portion of Figure 5E, and the reading is the same as that of operation (viii) above. (x) When the S packet (2 - 1) of the first line of the second sub-row is transmitted, the pattern data thereof is written in the 13th address of the video RAM 14P, as shown by the cross-hatched portion of Figure 5E, and after this writing (Figure 5E) the area 1 ○ of the video RAM 14P is read out and the reading then skips to the 26th address. Thereafter, the 26th to the 216th addresses are read out sequentially. The 13th address is read out next and, at the same time, the 2nd address of the video RAM 14C is read out 11 times after the area 1 ○, the 3rd to the 17th addresses are read out sequentially 12 times each and, finally, the 1st address is read out once. Accordingly, at this time, the picture screen header is displayed in colour on the picture screen at the position of the 0th sub-row, and the full lines of the 1st sub-row and the first line of the 2nd sub-row are displayed respectively in colour at the positions of the 12th line of the 15th and 16th sub-rows. That is, the scrolling display of one line is carried out further. (xi) Similar operations are repeated, as shown in Figures 5F to 5H. Figure 5F shows a state in which the pattern data of the 12th line of the 2nd sub-row is written, Figure 5G shows a state in which the pattern data of the 1st line of the 16th sub-row is written, and Figure 5H shows a state in which the pattern data of the 12th line of the 16th sub-row, or the last pattern data of the first page is written, respectively. In the state shown in Figure 5H, the data of the 1st line of the 1st sub-row is scrolled to the position of the 1st line of the 1st sub-row, and this means that all the data of just one page has been scroll-displayed. (xii) When the C packet (1) of the 1st sub-row of the second page is transmitted, the colour code thereof is written in the 16th address of the video RAM 14C, as shown by the cross-hatched portion of Figure 5I, and the reading is the same as that of operation (xi) above. (xiii) When the S packet (1 - 1) of the 1st line of the 1st sub-row of the second page is transmitted, the pattern data thereof is written in the 193rd address of the video RAM 14P, as shown by the cross-hatched portion of Figure 5I, and after this writing has ended (Figure 5I) the area 1 ○ of the video RAM 14P is read out, and then the reading skips to the 206th address. The 206th to the 216th addresses are then read out sequentially and this reading then skips to the 13th address. Thereafter, the 13th to the 193rd addresses are read out sequentially. At the same time, after the area 1 ○ of the video RAM 14C is read out, the 17th address of the video RAM 14C is read out 11 times and the 1st to the 15th addresses are read out sequentially 12 times each. Finally, the 16th address is read out once. Therefore, upon this reading, the first page is scrolled further by the amount of one line so that the 1st line of the 1st sub-row thereof disappears and the 1st line of the 1st sub-row of the second page is newly displayed at the lowermost position, that is, at the bottom line. In other words, the second page is scrolled after the first page. (xiv) When the C packet and the S packet of the second page 2 are transmitted subsequently, the scrolling display is carried out similarly to the first page, or to the operations shown in Figures 5B to 5H. When the S packet (16 - 22) of the 12th line of the 16th sub-line is transmitted, the state as shown in Figure 5J is presented. (xv) When the C packet of the first sub-row of the third page and the S packet (1 - 1) of the 1st line are transmitted sequentially, the state as shown in Figure 5K is established and similar operations will be carried out subsequently. In short, as shown in Figure 5L, upon performing a scrolling display, the 1st to 12th addresses of the video RAM 14P and the 0th address of the video RAM 14C are used for the picture screen header and the data is written therein once. However, the last addresses, or the 216th and 17th addresses, of the video RAMs 14P and 14C are connected to the 13th and 1st addresses thereof from an operation standpoint, as represented by broken line arrows of Figure 5L, respectively. Thus, the 13th to 216th addresses of the video RAM 14P and the 1st to 17th addresses of the video RAM 14C are formed, respectively, in so-called ring shapes. Then, the newly received data is written in the next addresses (the address followed by the 216th and 17th addresses are the 13th and 1st addresses) of the ring shapes. Therefore, in order for the addresses in which the new data are written to become the last addresses upon reading, the area 2 ○ is read out over 192 lines (the number of lines less the area 1 ○ ). As pointed out above, in this method, however, when the data of the colour information packet or the small character sequential display pattern packet is not obtained due to noise or other signal disturbances, a mis-matching wil occur between the pattern and the colour which is to be scroll-displayed. Because the colour code and the pattern data of the 0th sub-row of the 1st page are the picture screen header and are not scrolled, except the colour code and the pattern data as described above, the beginning of each page becomes the 1st sub-row. For example, considering the addresses of the video RAM 14C and 14P in which the colour code of the 1st sub-row and the pattern data of the 1st line are written, they are written in the 17th and 205th addresses with respect to the 1st page, as shown in Figure 5B, while they are written in the 16th and 193rd addresses with respect to the 2nd page, as shown in Figure 5I, and they are written in the 15th and 181st addresses with respect to the 3rd page, as shown in Figure 5K. In other words, if the page is changed, even with the same sub-row and the same line, the addresses in which the colour code and the pattern data thereof are written are decremented at every page by 12 addresses and 1 address, respectively. Thus, even if the C packet and the S packet contain the codes indicative of their display positions, the addresses at which the data is written are changed with the pages so that it is very difficult to write the colour code or the pattern data in the video RAMs 14C and 14P by using the display position codes. That is why, when the colour code or the pattern data is obtained, this colour code or the pattern data is written in the address following the address in which the previous colour code or pattern data is written. Accordingly, if the colour code of the colour information packet at its n -th address is not obtained due to noise, for example, the colour code of the C packet at its (n + 1)th address is written in the address in which the colour code of the colour information packet at the n -th address should be written. Thereafter, all colour codes are written in the video RAM with addresses decremented by one every address, so that the colour code is displaced upwardly by one sub-row amount on the picture screen. As a result, if the colour code and the pattern data are read out to carry out a scrolling display, all the pictures under the sub-row of which the colour code cannot be obtained are scroll-displayed with the colour being displaced by the amount of one sub-row relative to the pattern data, and this continues until the scrolling display is ended. On the other hand, when the pattern data of the small character sequential display pattern packet is not obtained, for similar reasons, the succeeding pattern data is incremented by one address and then written in the video RAM. Consequently, all picture images below the line of which the pattern data is not obtained are scroll-displayed such that the patterns and the colours thereof are each mismatched by one line, and this continues until the scrolling display is ended. If the colour code of the colour information packet and/or the pattern data of the small character sequential display pattern packet are not obtained, in the following scrolling display the pattern and its colour are all displaced with respect to each other. A preferred embodiment of the present invention provides a method and apparatus whereby data is accessed as shown, for example, in Figure 7, wherein like elements corresponding to those of Figure 5 are designated by the same references and will not be described in detail. The preferred embodiment of the present invention operates as will now be described with reference to Figure 7. (I) When the C packet (0) and the S packets (0 - 1) to (0 - 12) of the 0th sub-row are transmitted, in similar manner to operation (i) above, the writing and the reading of the colour code and pattern data are carried out as shown in Figures 6A to 6D and in Figure 7A. Note that Figure 7A is the same as Figure 5A. Accordingly, the picture screen header is displayed in colour at the position of the 0th sub-row on the screen of the colour picture tube 15. (II) When the C packet (1) of the 1st sub-row is transmitted, the colour code thereof is written in the 17th address of the video RAM 14C, as shown by the cross-hatched portion of Figure 7B, and the reading is the same as operation (I) above. (III) When the S packet (1 - 1) of the 1st line of the 1st sub-row is transmitted, the pattern data thereof is written in the 205th address of the video RAM 14P, as shown by the cross-hatched portion of Figure 7B, and after this writing (Figure 7B) the area 1 ○ of the video RAM 14P is read out and the reading then skips to the 14th address. Then, the 14th to 205th addresses are read out sequentially. At the same time, after the area 1 ○, the 1st address of the video RAM 14C is read out 112 times. Then, the 2nd to 16th addresses are read out 12 times each, and the 17th address is then finally read out once. Accordingly, as a result of this reading, the picture screen header is displaced in colour on the screen of the colour picture tube 15 at the position of the 0th sub-row and the 1st line of the 1st sub-row is displaced at the bottom line position. In other words, a scrolling display is started. When the reading assumes the state described above, the pattern data at the 205th addresses of the video RAM 14P is transferred to the 13th address, as shown by the cross-hatched portions in Figures 7B. (IV) When the S packet (1 - 2) of the 2nd line of the 1st sub-row is transmitted, the pattern data thereof is written at the 206th address of the video RAM 14P, as shown by the cross-hatched portion in Figure 7C, and after this writing (Figure 7C) the area 1 ○ of the video RAM 14P is read out and then the reading skips to the 15th address and the 15th to 206th addresses are read out sequentially. At the same time, after the area 1 ○, the 1st address of the video RAM 14C is read out 10 times and the 2nd to 16th addresses are read out 12 times each. Thereafter, the 17th address is read out twice. Accordingly, as a result of this reading operation the picture screen header is displayed on the screen in colour at the position of the 0th sub-row, and the 1st line and 2nd line of the 1st sub-row are displayed in colour at a position two lines from the bottom. That is, a scrolling display of one line amount is carried out for operation (III) above. When the reading assumes the state described above, the pattern data of the 206th address of the video RAM 14P is transferred to the 14th address, as shown by the cross-hatched portions in Figure 7C. (V) When similar operations are repeated and then the S packet (1 - 12) of the 12th line of the 1st sub-row is transmitted, the pattern data thereof is written at the 206th address of the video RAM 14P, as shown by the cross-hatched portion in Figure 7D, and after this writing (Figure 7D) the area 1 ○ of the video RAM 14P is read out and then the reading skips to the 25th address. Thereafter, the 25th to 216th addresses are read out sequentially. Although the 1st address of the video RAM 14C should be read out after its area 1 ○, the 1st address is read out zero times and, therefore, the 1st address following the area 1 ○ is skipped and the 2nd address thereof is then read out. Thereafter, the 2nd to 17th addresses thereof are read out sequentially 12 times each. Accordingly, under this state, the picture screen header is displayed in colour at the position of the 0th sub-row and the first sub-row is displayed in colour at the position of the last sub-row. That is, a scrolling display of one sub-row is carried out. When the reading assumes the state described above, the pattern data at the 216th address of the video RAM 14P is transferred to the 24th address thereof, as shown by the cross-hatched portions in Figure 7D. Further, as shown by the cross-hatched portions in Figure 7E, the colour code of the 17th address of the video RAM 14C is transferred to its 1st address. In this case, although the data of the 205th to 216th addresses of the video RAM 14P and the data of the 17th addresses of the video RAM 14C are transferred, these data still remain at the original addresses, but they are not shown by the cross-hatched portions in Figure 7E. After the transfer of the colour code at the 17th address of the video RAM 14C is ended, as shown in Figure 7E, the area 1 ○ of the RAM 14P is read out and the reading then skips to the 25th address and the 25th address thereof is read out. Subsequently, the 25th to 204th addresses are read out in turn. Thereafter, the 13th to 24th addresses are read out sequentially and, at the same time, after the area 1 ○ of the RAM 14C has been read out, the reading skips to the 2nd address and the 2nd to 16th addresses are read out 12 times each. Subsequently, the 1st address is read out 12 times. In this case, because the data of the 13th to 24th addresses of the video RAM 14P and the data of the 1st address of the video RAM 14C are those which are respectively transferred from the 205th to 216th addresses and from the 17th address, even if the read address is varied as shown in Figure 7E, the displayed state is the same as shown in Figure 7D. (VI) When the C packet (2) of the 2nd sub-row is transmitted, the colour code thereof is written at the 17th address of the video RAM 14C, as shown by the cross-hatched portion in Figure 7F, and the reading is the same as that of operation (V) above (Figure 7E). (VII) When the S packet (2 - 1) of the 1st line of the 2nd sub-row is transmitted, the pattern data thereof is written at the 205th address of the video RAM 14P, as shown by the cross-hatched portion in Figure 7F, and after this writing (Figure 7F) the area 1 ○ of the RAM 14P is read out and the reading skips to the 26th address. Then, the 26th to 204th addresses are read out sequentially. Further, after the 13th to 24th addresses are read out sequentially, the 205th address is then read out. At the same time, the area 1 ○ of the video RAM 14C is first read out and the reading skips to the 2nd address, which is then read out 11 times. In turn, the 3rd to 16th addresses are read out sequentially 12 times each. Thereafter, the 1st address is read out 12 times and, finally, the 17th address is read out once. Accordingly, as a result of this reading the picture screen header is displayed in colour at the position of the 0th sub-row on the picture screen of the colour picture tube 15, and the full lines of the 1st sub-row and the 1st line of the 2nd sub-row are displayed in colour at the positions of the 12th line of the 15th sub-row and the 16th sub-row. That is, a further scrolling display of one line is carried out. When the reading assumes the state described above, the pattern data at the 205th address of the video RAM 14P is transferred to its 25th address, as shown by the cross-hatched portions in Figure 7F. (VIII) When the S packet (2 - 2) of the 2nd line of the 2nd sub-row is transmitted, the pattern data thereof is written in the 206th address of the video RAM 14P, as shown by the cross-hatched portion in Figure 7G, and after this writing (Figure 7G) the area 1 ○ of the video RAM 14P is read out and then the reading jumps to the 27th address. Thereafter, the 27th to 204th addresses are read out sequentially. Further, after the 13th to 24th addresses are read out sequentially, the 205th and 206th addresses are read out, respectively. At the same time, after the area 1 ○ of the video RAM 14C is read out, the 2nd address is read out ten times and the 3rd to 16th addresses are read out sequentially twelve times each. Thereafter, the 1st address is read out twelve times and the 17th address is read out twice. Accordingly, the display is scrolled by extra one line. When such reading state appears, the pattern data at the 206th address of the video RAM 14P is transferred to its 26th address, as shown by the cross-hatched portions in Figure 7G. (IX) Similar operations are carried out successively and, when the pattern data of the S packet (2 - 12) at the 12th line of the 2nd sub-row is transmitted, the reading of the data from the video RAMs 14P and 14C is as shown in Figure 7H. Under this state, the scrolling display is carried out to the positions of the 15th and 16th sub-rows on the picture screen of the colour picture tube 15. When such state is brought about, as shown in Figure 7I, the colour code at the 17th address of the video RAM 14C is transferred to its 2nd address. After the transfer of the colour code, the video RAMs 14P and 14C are read out, as shown in Figure 7I. (X) When the C packet (3) and the S packets (3 - 1) to (3 - 12) of the 3rd sub-row are transmitted, the data of the video RAMs 14P and 14C and the reading of the data therefrom similarly assume the states shown in Figures 7J to 7L. That is, the colour code and the pattern data of the 3rd sub-row are accessed based on the 17th address of the video RAM 14C and the 205th to 216th addresses of the video RAM 14P, and the pattern data is transferred to the 37th to 48th addresses of the video RAM 14P corresponding to the 3rd sub-row. Then, when the pattern data of the S packet (3 - 12) at the 12th line of the 3rd sub-row is written in the 216th address of the video RAM 14P, the state shown in Figure 7L appears. As shown in Figure 7M, the colour code of the video RAM 14C is transferred to the 3rd address and thereafter the reading is carried out as shown in Figure 7M. (XI) Similar operations are carried out thereafter and, when the C packet (16) and the S packets (16 - 1) to (16 - 12) of the 16th sub-row are transmitted, the data and the reading of the data therefrom become as shown in Figures 7N to 7P, respectively. Under the state as shown in Figure 7P, the 1st line of the 1st sub-row is scrolled to the position of the 1st line of the 1st sub-row on the picture screen of the colour picture tube 15 or, in order words, the images of exactly one page amount are scroll-displayed. When the state as shown in Figure 7P is brought about, the colour code at the 17th address of the video RAM 14C is transferred to its 16th address, as shown in Figure 7Q, and thereafter the reading is carried out as shown in Figure 7Q. Since the state of Figure 7Q is exactly the same as that of Figure 7A, when the C packet (1) of the 1st sub-row of the 2nd page is transmitted, the data and the state thereof become as shown in Figure 7A, while when the colour code and the pattern data of the 2nd page are transmitted, the operations shown in Figures 7A to 7Q are once again carried out. Colour codes and pattern data of the 3rd page and the following pages are processed similarly, each page beginning with the state shown in Figure 1A and ending with the state shown in Figure 7Q, and the same operations as shown in Figure 7 are carried out for each page. According to the preferred embodiment of this invention, the sub-row to which the transferred colour code belongs, and the line to which the transferred pattern data belongs, are each made to correspond to the addresses of the video RAMs 14C and 14P one-by-one and, only when the pattern data of one sub-row is not complete, the colour code and the pattern data belonging to the sub-row are written in and read out from the buffer areas (its 205th to 216th addresses and 17th address), while, when the pattern data belonging to the sub-row is all complete, the colour code and the pattern data are read out from the addresses corresponding to the sub-row and the lines. Thus, even if the colour code of a certain sub-row cannot be obtained due to noise, for example, the colour code is not written at the corresponding address but the succeeding colour code can correctly be written at the corresponding address on the basis of the position indicating code (Figure 2) which is indicative of the position of that colour code. Thus, although the colour of the sub-row of which the colour code is not obtained due to the noise is disturbed, no mismatching will occur between the displayed pattern and colour in the succeeding sub-row. Furthermore, even if the pattern data of a certain line is not obtained, the succeeding pattern data can be written in the corresponding address so that no mismatching will occur between the displayed pattern and colour. Figure 8 is a diagram substantially the same as Figure 7, except that it is partially revised. In Figure 8, of the addresses in the video RAMs 14P and 14C, the addresses from which no reading is carried out are not shown, and the areas 1 ○ and 2 ○ are read out successively so that they are shown in continuous form. Figures 8A to 8Q correspond to Figures 7A to 7Q, respectively. According to Figures 8A to 8Q, the reading of the video RAM 14P begins with the 1st address at every vertical scanning line and continues to the 12th address. The address which will be read out next is the address marked by a o, and the address increments by one address each time the pattern data is obtained. The reading from the address marked by o is continued and, when the reading arrives at the 204th address, the 13th address is read out (except in Figurs 8B to 8E). Then, the reading is continued from the 13th address to the 24th address and, next, the reading begins with the 205th address. At the same time, the RAM 14C is also read out similarly. In this case, after the 0th address is read out, an address marked by X will be read out and such address is incremented by one address each time the colour code is obtained, and the number of readings of the address marked by X is decremented by one address each time the pattern data is obtained. The preferred image display apparatus embodying this invention will now be described with reference to Figure 9, which shows a form of the read address control circuit 16 used in the embodiment of the invention, and in which circuits 61 to 65 are principally for the read address of the video RAM 14P, while circuits 71 to 77 are principally for the read address of the RAM 14C. The circuit 61 is an 8-bit presettable up-counter that is supplied with a horizontal synchronising pulse Ph as a count input and which then forms a line address signal LA (which signal becomes the above-described 1st to 216th addresses) upon reading of the video RAM 14P. The counter 61 is formed such that when the level at an input terminal L thereof changes from "0" to "1", the data input at a terminal DI thereof can be loaded (preset) as its initial count value. The circuit 62 is an 8-bit 3-state latch circuit and is supplied with the address (which is the start address of the area 2 ○ ) of the video RAM 14P through the CPU 11 (Figure 4) and is latched therein. The latch circuit 62 assumes a high output impedance (open) when the level of a terminal OC thereof is "1", while when it is "0" the latch circuit 62 supplies its latched content to the counter 61 as the preset input thereof. The circuits 63 and 64 are 3-state output buffers, each of which assumes a high output impedance (open) when the level at a terminal OC thereof is "1". When the level at the terminal OC is "0", the output buffer 63 supplies the value "13" to the counter 61 as its preset input, and the output buffer 64 supplies the value "205" to the counter 61 as its preset input. Accordingly, after any one of the three output values, namely, "the value of mark o", "13", and "205" of the latch circuit 62 and the output buffers 63 and 64 is loaded into the counter 61, and the address signal LA is incremented by "1" from its loaded value at every horizontal synchronising signal Ph . The circuit 65 is a decoder that is supplied with the address signal LA from the up-counter 61 so that when LA = "204", an output Q₆₅ thereof becomes "0". The circuit 76 is a 4-bit presettable 12-scale down-counter, and the circuit 77 is a 4-bit latch circuit. The counter 76 counts the number reading out of each address of the video RAM 14C and the latch circuit 77 is supplied with the number reading out of the addresses marked by X of the video RAM 14C from the CPU 11 and then latched therein. The latched output from the latch circuit 77 is supplied to the counter 76 as a preset input thereof and the horizontal synchronising pulse Ph is supplied to the counter 76 as its count input. Accordingly, the counter 76 produces a borrow output Q₇₆ and the borrow output Q₇₆ is obtained as shown in the right-hand side of Figures 8A to 8Q. In other words, in the address marked by X, after the number of readings designated by the latch circuit 77 (the number of the horizontal synchronising pulses Ph ), the borrow output Q₇₆ = "1" is established, and thereafter, at every 12 horizontal synchronising pulses Ph , Q₇₆ = "1" is established. The circuits 71 to 75 correspond respectively to the circuits 61 to 65 and, more particularly, the circuit 71 is a 5-bit presettable up-counter and is used to produce a sub-row address signal CA (which becomes the 0-th to 17th addresses set forth above) upon reading of the video RAM 14C. To this end, the horizontal synchronising pulse Ph is supplied to the counter 71 as a count input thereof and the borrow output Q₇₆ is supplied as a count enable signal thereof. Consequently, the address specified by the address signal CA is varied at every signal Q₇₆, as shown in Figure 8. The circuit 72 is a 5-bit 3-state latch circuit and is supplied with the start address (the address marked by X) of the area 2 ○ of the video RAM 14C from the CPU 11 to be latched therein, and the latch circuit 72 supplies the latched content to the counter 71 as a preset input thereof when the level at a terminal OC is "1". The circuits 73 and 74 are 3-state output buffers, each of which assumes a high output impedance when the signal level at a terminal OC thereof is "1". On the other hand, when it is "0", the output buffer 73 supplies the value "1" to the counter 71 as its preset input, while the buffer 74 supplies the value "17" to the counter 71 as its preset input. Accordingly, any one of the output values, namely, "the value of the mark X", "1", and "17" of the latch circuit 72 and the output buffers 73 and 74 is loaded into the counter 71. After the value is loaded therein, the address signal CA is incremented by "1" from the loaded value at each borrow signal Q₇₆. The circuit 75 is a decoder that is supplied with the address signal CA from the up-counter 71 so that, when the address signal CA = "16", the level of an output Q₇₆ thereof becomes "0". A flip-flop circuit 81 is used to produce a flag. The flip-flop circuit 81 is controlled by the CPU 11, and an output Q₈₁ thereof becomes "1" when the 205th to 216th buffer areas and the 17th addresses of the video RAMs 14P and 14C are used in writing and reading. It becomes "0" when they are not used, that is, under the states shown in Figures 8E, 8I, 8M and 8Q, Q₈₁ = "0" is established, while under the other states, Q₈₁ = "1" is established. A signal DSP 1 is provided by counting, for example, the pulse Ph , and becomes "1" during a period from the time point prior to the 1st line by one horizontal period to the end of the 204th line, as shown in Figure 8R. The signal DSP 1 is supplied to a clear terminal CLR of the counter 61, so that the counter 61 is cleared during the period of DSP 1 = "0", so as to hold CL = "0", while its clear mode is released during the period of DSP 1 = "1". A signal DSP 2 becomes "1" during the period from the beginning of the 1st line to the end of the 204th line, as shown by Figure 85, and the signal DSP 2 is fed to clear terminals CLR of the counters 71 and 76, respectively. Further, a signal LD becomes "0" during the period of the scanning period of the 12th line in total, and a signal SCGT is a gate signal which becomes "1" during a scanning period at the positions of the 193rd to 204th lines (sub-row 16), as shown in Figure 8T. By employing the circuit arrangement of Figure 9, the following operations can be carried out: (A) As shown in Figure 8R, because during the period prior to the 1st line (this line number is the number on the picture screen of the colour picture tube 15 which is used in the following) by one horizontal period, DSP 1 = "0" is established, the counter 61 is cleared, and thus LA = "0" is established. Moreover, as shown in Figure 8C, since DSP 2 = "0" is established during this period, the counters 71 and 76 are also cleared so that CA = "0" and Q₇₆ = "0" are satisfied. (B) At a time point one horizontal period before the 1st line, the condition DSP 1 = "1" is established, so that the counter 61 is set in the count mode. (C) As the start point of the 1st line, because the synchronising pulse Ph is counted in the counter 61, LA = "1" is established, or the 1st address of the video RAM 14P is accessed by the address signal LA. As a result, the pattern data at the 1st line is read out from the 1st address of the video RAM 14P. At this time, since the condition DSP 2 = "1" is satisfied, the counters 71 and 76 are placed in the count mode. At this time, however, CA = "0" is satisfied, or the 0th address of the video RAM 14C is accessed by the address signal CA so that the colour code of the 0th sub-row is similarly read out from the 0th address of the video RAM 14C similar to the pattern data. Thus, the 1st line is displayed. (D) At the start of the 2nd line, the synchronising pulse Ph is counted by the counter 61 to establish LA = "2", so that the 2nd address of the video RAM 14P is accessed by the address signal LA, thereby to read out the pattern data at the 2nd line. At this time, although the synchronising signal Ph is counted by the counter 76, since Q₇₆ = "0" remains as it is CA = "0" is established. Thus, the colour code of the 0th sub-row is read out from the video RAM 14C. As a result, the 2nd line is displayed. (E) Similar operations are carried out to the 12th line, and the colour code and the pattern data of the 0th sub-row are read out and then displayed on the picture screen of the colour picture tube 15. (F) During the period in which the above operations (A) to (E) are being carried out, the CPU 11 loads the address marked by o into the latch circuit 62, the address marked by X into the latch circuit 72, and the reading number of the address marked by X into the latch circuit 77. (G) Although during the horizontal scanning period of the 12th line the condition LD = "0" is established, the signal LD rises up from "0" to "1" by the synchronising pulse Ph at the beginning of the 13th line. Then, the signal LD is supplied to the latch circuit 62 as its load pulse. Accordingly, the address marked by o which is latched in the latch circuit 62 is loaded into the counter 61 when starting the horizontal scanning of the 13th line. The signal LD is supplied to the latch circuit 72 and also through an OR-circuit 83 to the load terminal L of the counter 71 as its load pulse. Consequently, the address marked by X and latched in the latch circuit 72 is loaded into the counter 71. Further, the signal LD is supplied to a load terminal L of the counter 76 as its load pulse and, therefore, the reading number of the address marked by X (and latched in the latch circuit 77) is loaded into the counter 76. In other words, when starting the horizontal scanning of the 13th line, the address marked by o is loaded into the counter 61, the address marked by X is loaded into the counter 71, and the reading number of the address marked by X is loaded into the counter 76. (H) During the horizontal scanning of the 13th line, because of operation (G) above, the pattern data and the colour code are read out from the addresses marked by an X and they are displayed as the 13th line. (I) Thereafter, the counted value LA of the counter 61 is incremented at every synchronising pulse Ph and the read address LA of the video RAM 14P is incremented address-by-address from the address marked by at every line, as shown in Figure 8. On the other hand, in the counter 76, when the synchronising pulse Ph is counted by the reading number of the address marked by X, Q₇₆ = "1" is satisfied and, thereafter, Q₇₆ = "1" is established at every 12 horizontal synchronising pulses Ph . Since the horizontal synchronising pulse Ph is counted by the counter 71 only when Q₇₆ = "1" is satisfied, its counted value CA, or the read address CA of the RAM 14C, is incremented one address by one address from the address marked by X at every 12 lines, as shown in Figure 8, if the horizontal scanning is carried out in the reading number of the address marked by X. As described above, the pattern data and the colour code are read out up to LA = "204" and are displayed. (J) When the condition LA = "204" is satisfied, Q₆₅ = "0" is satisfied. In the following description, however, it is assumed that the colour code and the pattern data of the sub-row following the 2nd sub-row are transferred, as shown in Figures 8F to 8Q, for simplicity. Then, when the condition Q₆₅ = "0" is established, since SCGT = "0" is established, an output Q₈₄ of an AND-circuit 84 is "0". Accordingly, the signal Q₆₅ is supplied through an AND-circuit 85 to the terminal OC of the output buffer 63 and through an OR-circuit 82 to the load terminal L of the counter 61. When the scanning period of LA = "204" is ended and the succeeding synchronising signal Ph is obtained, the signal Q₆₅ rises from "0" to "1". As a result, at that time, the data "13" of the output buffer 63 is loaded into the counter 61. At the same time, similar operations are carried out in the output buffer 73 and counter 71. More specifically, when CA = "16", Q₇₃ = "0" is established. However, at the next Q₇₆ = "1", when the synchronising pulse Ph is supplied thereto, the output of an AND-circuit 86 is changed from "0" to "1". Since the output of the AND-circuit 86 is supplied to the terminal OC of the output buffer 73 and also through an OR-circuit 83 to the load terminal L of the counter 71, at this time the data "1" of the output buffer 73 is loaded into the counter 71. In other words, after LA = "204" and CA = "16", LA "13" and CA = "1" are established, respectively. (K) From the succeeding horizontal scanning period, the reading begins with the state of LA = "13" and CA = "1". Thereafter, the address signal LA is incremented one address by one address at every line and the address signal CA is incremented one address by one address at every 12 lines. Further, in response to the address, the horizontal scanning position is shifted downwardly one line by one line. (L) Under the states shown in Figures 8F to 8H, Figures 8J to 8L, and Figures 8N to 8P, because the buffer area (205th to 216th and 17th addresses) of the video RAMs 14P and 14C are used, Q₈₁ = "1" is satisfied, when the horizontal scanning position arrives at the position of the 16th sub-row (since at this time, SCGT = "1" is established) Q₈₄ = "1" is satisfied. Then, because the signal Q₈₄ and the signal Q₇₆ are both supplied to a NAND-circuit 87, when Q₇₆ = "1" is established during the period in which the horizontal scanning position is at the 16th sub-row, the output Q₈₇ of the NAND-circuit 87 becomes "0". The signal Q₈₇ is supplied to the terminal OC of the output buffer 64 and also through the OR-circuit 82 to the load terminal L of the counter 61, so that the data "205" of the output buffer 64 is loaded into the counter 61. Thus, under the states shown in Figures 8F to 8H, Figures 8J to 8L, and Figures 8N to 8P, when the horizontal scanning position or the address signal LA proceeds to the position of the 16th sub-row, on the following line with the pulse Q₇₆ = "1", the address LA becomes "205". Further, since the signal Q₈₇ is supplied to the terminal OC of the output buffer 74 and also through the OR-circuit 83 to the load terminal L of the counter 71, the data "205" is loaded into the counter 61 and, at the same time, the data "17" of the output buffer 74 is loaded into the counter 71. In consequence, the address signal LA becomes "205" and the address signal CA becomes "17" at the same time. (M) Thereafter, the address signal LA is incremented from "205" by each address at every line, while the address signal CA remains "17". (N) After the vertical display period is ended, DSP 1 = "0", DSP 2 = "0" and SCGT = "0" are established, respectively, thus forming a picture image of one field amount. (L') Under the states as shown in Figures 8I, 8M, and 8Q, and because the buffer areas (205th to 216th and 17th addresses) of the video RAMs 14P and 14C are not used, Q₈₁ = "0" is established. Accordingly, even when the horizontal scanning position reaches the position of the 16th sub-row and SCGT = "1" is established, Q₈₄ = "0" is left as it is, thus also leaving Q₈₇ = "1" as it is. Consequently, under the states as shown in Figures 8I, 8M, and 8Q, even when the horizontal scanning position reaches the position of the 16th sub-row, the addresses LA and CA are not changed over to the 205th and 17th addresses but become continuous. As described above, in the case of Figures 8F to 8Q, the colour code and the pattern data of the video RAMs 14P and 14C are read out and then displayed respectively. (J) Under the states as shown in Figures 8A to 8E, or the state that the colour code and the pattern data of the 1st sub-row are transmitted, if LA = "204" is established, Q₆₅ = "0" is satisfied. However, at this time, since Q₈₁ = "1" and SCGT = "1" are established, Q₈₄ = "1" is satisfied, so that when the succeeding signal Q₇₆ is changed from "0" to "1" and then to "0", the signal Q₈₇ is changed from "0" to "1". Thus, by the change of the signal Q₈₇, the data "205" of the output buffer 64 is loaded into the counter 61, and the data "17" of the output buffer 74 is loaded into the counter 71. In other words, the addresses LA and CA respectively become "204" and "16" after "205" and "17". (K) Thereafter, the state becomes similar to that of operation (M) above, and the address LA is incremented by one address each from "205" at every line, while the address CA remains as "17". (l) After the vertical display period is ended, DSP 1 = "0", DSP 2 = "0" and SCGT = "0" are established (same as operation (N) above). Accordingly, the picture image of one field amount is formed. As described above, according to the address control circuit 16 as shown in Figure 9, the read addresses LA and CA of the video RAMs 14P and 14C are controlled and the pattern data and the colour code are respectively read out. As set forth above, according to the preferred embodiment of this invention, the sub-row to which the transmitted colour code belongs and the line to which the pattern data belongs are made to correspond to the addresses of the video RAMs 14C and 14P one by one and only when the pattern data of one sub-row is not complete, the colour code and the pattern data belonging to the sub-row are written in the buffer areas (205th to 216th and 17th addresses) and then read out therefrom, while when the pattern data belonging to the sub-row is all complete, the colour code and the pattern are read out from the addresses corresponding to the sub-row and the line. As a result, even if the colour code of a certain sub-row is not obtained due to noise, for example, such colour code is not merely written in the corresponding address but the succeeding colour code can correctly be written in the corresponding address on the basis of the display position code (Figure 2) indicative of the position of the colour code. Therefore, although the colour of the sub-row of which the colour code cannot be obtained due to the noise is disturbed, it is possible to prevent mismatching from being produced between the displayed pattern and colour in the succeeding sub-row. Even if the pattern data of a certain line cannot be obtained, the succeeding pattern data can be written correctly in the corresponding address so that no mismatching will occur between the displayed pattern and colour. Since the buffer areas (205th to 215th and 17th addresses) of the video RAMs 14P and 14C can be changed to desired addresses only by changing the data "205" and "17" of the output buffers 64 and 74, it is possible to simplify the construction of the output buffers 64 and 74. Apparatus embodying this invention can be applied also to a television receiver of a television character multiplexing broadcast. Furthermore, the pattern data written in the buffer areas constituted by the 205th to 216th addresses of the video RAM 14P may not always be transferred to the inherent address at every one address but can be transferred to the inherent address with all its addresses together.

Claims: Apparatus for scrolling a display image derived from a plurality of data units, each having pattern signals formed of a plurality of horizontal lines and a corresponding colour signal, the apparatus comprising: display means (15) for producing a visual display of an input signal as a plurality of horizontal lines; first memory means (14P) connected for receiving and storing the pattern signals and having a plurality of first addresses corresponding respectively to the plurality of horizontal display lines and having a first buffer area for temporarily storing the received pattern signals; second memory means (14C) connected for receiving and storing the colour signal and having a plurality of second addresses corresponding respectively to the plurality of data units and having a second buffer area for temporarily storing the received colour signals; means (11) operative to store the received pattern signals and corresponding colour signals in the first and second buffer areas, respectively; and memory control means (11, 16) operative to control the first and second memory means (14P, 14C) such that the first memory means (14P) including the first buffer area is read out to the display means (15) by accessing the first addresses in a first predetermined order and the second memory means (14C) including the second buffer area is read out to the display means (15) by accessing the second addresses in a second predetermined order, and such that a pattern signal of a horizontal line stored temporarily in the first buffer area is transferred to a corresponding address of the first memory means (14P) and a corresponding colour signal stored temporarily in the second buffer area is transferred to a corresponding address of the second memory means (14C), whereby the pattern signals and the corresponding colour signals are fed to the display means (15) to provide a scrolling display image. Apparatus according to claim 1, wherein the memory control means (11, 16) comprises means for incrementing the number of an initial accessing address of the first memory means (14P) every horizontal period and means for incrementing the number of an initial accessing address of the second memory means (14C) every plurality of horizontal periods, whereby the first and second buffer memory areas are read out, respectively, after the first and second memory means (14P, 14C). Apparatus according to claim 2, in which the first and second memory means (14P, 14C) include header portions respectively corresponding to upper horizontal display lines of the display means (15), and the memory control means (11, 16) is operative to read out the header portions prior to the initial accessing address. Apparatus according to claim 3, wherein the memory control means (11, 16) comprises counter means for producing address accessing signals that determine the accessing addresses of the first and second memory means (14P, 14C) according to the predetermined orders. Apparatus according to claim 4, wherein the memory control means (11, 16) comprises preset means for presetting the counter means according to the predetermined orders.

Inventors: HANAMOTO, YOSHIHIRO C/O NIPPON TELEGRAPH, ISHIGAKI, YOSHIO C/O PATENT DIVISION, MAEDA, SATORU C/O PATENT DIVISION, NOGUCHI, YASUSHI C/O PATENT DIVISION, SAHARA, HIROSHI C/O PATENT DIVISION, SHIBUI, ICHIRO C/O NIPPON TELEGRAPH
Applicants: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, SONY CORPORATION
Application year: 1985
Main classification: G09G1
IPC codes: G09G5, H04N7