Memory access control system

Abstract: A memory access control system including at least one main memory (10′) having a plurality of memory banks (12a₀, 12b₀, ..... 12a n , 12b n ) divided into two groups (12a₀, 12a₁,. ... 12a n ), (12b₀, 12b₁, ... 12b n ) thus enabling parallel processing for data; a command address bus line, a write data bus line (17), and a read data bus line (18); and a device for simultaneously activating one request for access to the memory bank belonging to one group and another request for access to the memory bank belonging to the other group.

Description: The present invention relates to a memory access control system. More particularly, it relates to an access control system for a main memory having a plurality of memory banks. The present invention is advantageously used in a main memory of a computer system. Recently, a method has been disclosed for dividing a main memory of a computer system into a plurality of memory banks, thus enabling parallel processing of data and raising the practical throughput for data in the main memory. In this method, at least two data bus lines are provided for inputting write data and for outputting read data. Each of the data bus lines is used separately for input and output operations to facilitate control of the bus line and to raise the throughput for the data. In this case, however, there is a fifty percent limitation value on the utilization efficiency of the bus line, because either the input or the output bus line is selected alternatively for every request for access to the memory. The problems concerning the utilization efficiency of the bus lines will be explained in detail hereinafter. EP-A-0 109 298 discloses a computer memory having features corresponding to those of the preamble of accompanying claim 1. The memory comprises memory modules divided into "even" and "odd" sections containing even and odd address locations and having their own data latches, respectively. When a read access is to be performed, a control signal is generated which reads data from the memory into both data latches at once. A subsequent signal selects either the "even" or "odd" data latch to output the data of that latch onto a data bus. The other data latch is then selected so as to place its data onto the data bus in quick succession. Write accesses to the memory are dealt with in a corresponding manner. US-A-4 099 231 discloses a memory control system with a similar structure and operation. Up to four data words can be addressed simultaneously, but again data transfers are on a serial basis (one word at a time). US-A-3 792 439 discloses a message exchange system for transferring binary data signals in a program-controlled telecommunications exchange. A core memory is divided into a number of storage units each connected to individual processing units, such that processing can proceed simultaneously in several storage units at once. EP-A-0 029 517 discloses a data processing apparatus having a cache memory and in accordance with the preamble of accompanying claim 1. According to the present invention, there is provided a memory access control system comprising:- memory means having a plurality of even and odd-numbered memory banks divided into two groups; bus means for transferring data and including a command/address bus line, a write data bus line, and a read data bus line all coupled to said memory means, the write and read data bus lines each having a bus width of one word and being operable simultaneously; activating means, coupled to said bus means, for activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group in dependence on the single access request allowing two sequential data transfers, one from each group, to be performed over said bus means for the single access request so that in each cycle two words can be simultaneously transferred, one word over said read data bus lines and the other word over said write data bus lines, said activating means comprising:- command and address register means, connected to said command/address bus line, for sending two-word commands to said memory means, and for designating an address for a selected memory bank of each of said two groups; a decoder, connected to said command and address register means and said memory means, for activating each respective designated memory bank; a write data register, connected to said write data bus line, for transferring write data; and a read data register, connected to said read data bus line, for transferring read data; characterised in that said memory means comprises at least one main memory having: a plurality of bank registers, corresponding to said plurality of memory banks, each of said bank registers having an address register, a write data register, and a read data register; and a plurality of counter circuits corresponding to said plurality of memory banks, each counter circuit being constituted by flip-flop gates, AND gates, OR gates, and exclusive-OR gates, and being provided in an input portion of the respective memory bank; wherein each counter circuit is responsive to a signal from said decoder to start a count from zero, and while the count is non-zero to issue a clock hold signal for holding the contents of the respective address register and write data register to inhibit a next access request to the respective bank; and wherein the counter circuit of each odd-numbered memory bank is responsive to said two-word command to issue a delayed clock signal which is delayed by one cycle from said clock hold signal so as to delay write and read timing to the respective memory bank by one cycle; whereby said even numbered memory bank stores data at the same timing of said access, and said odd-numbered memory bank stores data after a delay of one cycle compared with the storing by said even-numbered memory bank. An embodiment of the present invention can provide a memory access control system to be used in a main memory of a computer system. An embodiment of the present invention can provide a memory access control system that can raise the utilization efficiency of and enable an improvement in the throughput of data bus lines between the main memory and a memory control unit, and between the memory control unit and a central processing unit or a channel processing unit. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1 is schematic block diagram of a relatively large scale computer system; Fig. 2 is a conventional schematic structure of the main memory shown in Fig. 1; Fig. 3 is a schematic structure of a main memory according to an embodiment of the present invention; Figs. 4A to 4D are detailed block diagrams of the main memory shown in Fig. 3; Figs. 5A and 5B are timing charts for commands, addresses, write data, and read data in the main memory shown in Fig. 4; Figs. 6A and 6B are detailed block diagrams of a memory control unit according to an embodiment of the present invention; and, Figs. 7 and 8 show control circuits provided for each of the memory banks shown in Fig. 4. Before describing the preferred embodiments, an explanation will be given of a conventional memory access control system. Figure 1 is a schematic block diagram of a relatively large scale computer system using at least one main memory (main storage unit) having a plurality of memory banks. In Fig. 1, reference numerals 1-1 to 1-n designate a plurality of central processing units (CPU), 2-1 to 2-n a plurality of channel processing units (CHP), 3 a maintenance unit (MU), 4 a memory control unit (MCU), and 5 a main storage unit (MSU). Each CHP 2 and CPU 1 is connected to the MSU 5 through the MCU 4. The MU 3 is connected directly to the MCU 4. In this system, the MCU 4 forms a queue by receiving requests for access to the MSU 5 transmitted from a CHP 2 or CPU 1, transfers the access requests to the MSU 5 in order based on the queue, and then transfers the read data from the MSU 5 to the CHP 2 or CPU 1 which requested access to the data. Figure 2 is a conventional schematic structure of main storage unit (MSU) 5. The MSU 5 is constituted by an array section 10 having a plurality of memory banks 12-1 to 12-n and a control section 11 having an address register 13 and a command register 14. Each of the memory banks 12-1 to 12-n can independently write and read the data. A memory address is assigned to each of the memory banks 12-1 to 12-n by an interleaving method. That is, where there are eight bytes per one word, a byte address is assigned to each memory bank 12, i.e., memory bank 12-1 is "0", memory bank 12-2 is "8", memory bank 12-3 is "16", ... and memory bank 12-n is "8 x (n-1)", as shown in Fig. 2. The operation of this system will be explained hereinafter. The MCU 4 sets the memory address to be accessed to the address register 13 of the MSU 5, and sets the read or write command to the command register 14 of the MSU 5 based on the access request from, for example, the CPU 1. When in the writing mode, the MCU 4 simultaneously sets the data to be written to the write data register 15. The MSU 5 selects one of the memory banks 12 by a decoded output based on a part of contents of the register 13 in a decoder 19, and transfers the write data of the write data register 15 to a bank address register and a bank data register included in the memory bank 12. Accordingly, only one memory bank selected by the decoded output based on the content of the decoder 19 is operated by one access request. In a read operation, the data to be read from the selected memory bank 12 is set to a read data register 16, and transferred from the read data register 16 to the MCU 4. In this case, the operation for setting the memory address from the address register 13 to the bank address register in the memory bank 12 occupies at least one cycle, and, in general, the access operation in the memory bank 12 itself occupies several cycles. Accordingly, although the memory bank 12 under operation is occupied by the access operation during this time, another memory bank 12 can set the next memory address in order. In such a memory having a plurality of memory banks, the read or write data of one word per one cycle can be input to or output from the MSU 5 at a very high utilization efficiency. In the conventional structure shown in Fig. 2, however, the above-explained data throughput is limited because either the bus line 17 or the bus line 18 is used alternately for each access request. Consequently, the utilization efficiency for each bus line cannot exceed a maximum value of fifty percent. A more effective utilization, i.e., an improvement of the practical throughput, has not yet been sufficiently achieved in a known memory access control system. A memory access control system according to an embodiment of the present invention will now be described. Figure 3 shows a schematic structure of a main storage unit (MSU) 5' according to an embodiment of the present invention. In Fig. 3, the same reference numerals signify the same components as in Fig. 2. The main storage unit (MSU) 5' comprises an array section 10' divided into two groups of memory banks, i.e., even number memory banks (even banks) belonging to one group 12a0 to 12an, and odd number memory banks (odd banks) belonging to the other group 12b0 to 12bn, in accordance with whether the word address number is odd or even. Each memory address is assigned to each of the memory banks by an interleaving method as in the case of conventional memory banks. In embodiments of the present invention, a two word access command is used to obtain access to the memory banks. The two word command comprises, for example, sixteen bytes (2 x eight bytes per one word) and can designate two memory banks by the access of two words constituted by a sequential address. The basic operation of the MSU 5' is explained below. A memory address and command sent from the memory control unit (MCU) are received by the address register 13 and the command register 14. When the command received by the register 14 is not a two word command, i.e., is the eight bytes of one word command, only one memory bank is activated. In this case, the MSU 5' operates under the same procedure as for the conventional system. When the command received by the register 14 is a two word command, a decoder 30 selects one by one memory banks each having the sequential address alternately from the even bank group and the odd bank group. Accordingly, two memory banks from adjoining even and odd banks are selected by the decoder 30. In this case, an even bank having the even address is designated first by a head memory address of a so-called two words boundary (16 bytes boundary). Figures 4A to 4D are detailed block diagrams of the main storage unit shown in Fig. 3. In Figs. 4A to 4D, even banks numbered 0, 2, 4, 6 ---, N-1 correspond to the even banks 12a0, 12a1, 12a2 ---12an shown in Fig. 3. Similarly, odd banks 1, 3, 5 --- N correspond to the odd banks 12b0, 12b1, 12b2 ---12bn shown in Fig. 3. Each memory bank, whether even or odd, comprises a bank register constituted by an address register A, a write data register WD, and a read data register RD. Reference numerals 20 and 23 designate selectors (SEL). The selector 23 is used only for partial store data, and functions to merge partial store data with write data. The selector 20 has two functions, to merge the partial store data with the write data and to take an output timing of read data in correspondence with the output of a control pipeline 21a. Reference number 21 is a pipeline register consisting of a control pipeline (CTRL) 21a and a write data pipeline (WD) 21b. The CTRL pipeline 21a controls the output timing of the read data by shifting the access request, and the WD pipeline 21b controls the partial store data as explained below. Reference 22 designates means for generating an error correcting code (ECC). Reference numeral 30 is a decoder generating a "BANK GO" command to activate the selected memory bank based on the two word command sent from the command (CMD) register 14. Figures 5A and 5B are timing charts of the operation in the command register 14, the address register 13, each of the memory banks, and the CTRL/WD pipelines 21a and 21b. A portion above the chain dotted line in the Figures is the memory control unit side. Operation of the MSU 5' shown in Fig. 4 will be explained in detail with reference to the timing chart shown in Fig. 5. T₀ , T₁ , T₂ --- T₁₉ are access request timings for the operation of each register and memory bank. The period between each of the timings is equivalent to one access request cycle. At the timing T₂ , the address register (MSU ADDR) 13 receives the memory address sent from the command/address register (MS CMD/ADDR) in the memory control unit (MCU) at the timing T₁. The command register (MSU CMD) 14 also receives, for example, a two word command sent from the MS CMD/ADDR in the MCU at the timing T₁ , and the write data register (MSU WDR) 15 also receives the write data sent from the write data register (MS WDR) in the MCU at the timing T₁. Where a two word command, i.e., 16 bytes command, is sent, the MSU CMD 14 sends the 16 bytes command to the decoder (DEC) 30. The decoder 30 generates the "BANK GO" command to the corresponding two memory banks selected, for example, EVEN BANK 0 and ODD BANK 1, and activates these banks. In the write mode, at the timing T₃ , the bank address register A₀ in the EVEN BANK 0 and the bank address register A₁ in the ODD BANK 1 simultaneously receive the memory address, and the bank write data register WD₀ in the EVEN BANK 0 also receives the write data. However, the bank write data register WD₁ in the ODD BANK 1 receives the write data after a delay of one cycle, i.e., at the timing T₄. When the command received by the MSU CMD 14 is not the two word command, only one memory bank is directly activated, but not through the decoder 30, rather by the MSU ADDR 13 and the MSU WDR 15. In the read mode, at the timing T₄ , the address register A₂ in the EVEN BANK 2 and the address register A₃ in the ODD BANK 3 simultaneously receive the read address, and the read data register RD₂ in the EVEN BANK 2 reads out the stored data after eight cycles, i.e., at the timing T₁₂ , and this read out data is output from the read data register (MSU RDR) 16 through the ECC register 22. However, the read data register RD₃ in the ODD BANK 3 reads out the stored data after a delay of one cycle, i.e., at the timing T₁₃. This read out control is performed by the control pipeline (CTRL) 21a. As shown in the upper portion of Figs. 5A and 5B, the command register (MS CMD) in the MCU can alternately command "write" and "read" instructions which consist of the two word command (FST 16 bytes and FCH 16 bytes; where FST is full store data and FCH is fetch data). As mentioned above, the address register (MS ADDR) in the MCU sends addresses to the address register (MSU ADDR) 13, and the MSU ADDR 13 designates two memory banks in the EVEN and ODD BANK's for both the "write" (store) and "read" (fetch) modes. Accordingly, at each timing, the MSU ADDR 13 can always activate two memory banks at every one cycle. These operations are performed similarly for other memory banks in the EVEN and ODD banks. As can be clearly understood, when write or read access requests consisting of the two word command are alternately and sequentially generated from the MS CMD/ADDR in the MCU, the MSU ADDR 13 designates two memory banks in the EVEN and ODD BANK's based on a portion of the lower bank address, and the MSU WDR 15 sends the write data to the designated memory bank at the predetermined timing. Accordingly, as shown in the Figure, after the timing T₁₃ , the MSU WDR 15 and the MSU RDR 16 simultaneously hold data, i.e., the MSU WDR 15 holds the write data and the MSU RDR 16 holds the read data. Consequently, the utilization efficiency, i.e., practical throughput, of the data bus lines 17 and 18 can be raised to a value of up to a hundred percent as the maximum efficiency value. The CTRL pipeline 21a functions as a shift register. This pipeline 21a can shift the access request input from the MSU CMD 14 and the MSU ADDR 13 by each pitch of P₁ , P₂ ---. For example, shifting of the access request cycle 1 of the "MS GO" command in the MCU is started at the timing T₂ , at which the EVEN BANK 0 and the ODD BANK 1 are designated. Similarly, shifting of the access request cycle 2 is started at the timing T₃ , at which the EVEN BANK 2 and the ODD BANK 3 are designated. When the shifted pitch of the cycle 2 reaches the timing P₉ , the read data of the RD₂ of the EVEN BANK 2 is output to the MSU RDR 16 by taking into account the correspondence between the read data and the shifted data in the selector (SEL) 20. At the next timing P₁₀ , the read data of the RD₃ of the ODD BANK 3 is output to the MSU RDR 16. In this case, the CTRL pipe line 21a controls the output of the RD₃ so that it is delayed by only one access cycle, to enable the RD₃ to output the read data after a delay of one cycle of the output of the RD₂. At the timings P₉ and P₁₀ of the cycle 4, the read data of the RD₆ and the RD₇ are output by the same method as in the cycle 2. The WD pipeline 21b shown in Fig. 4C is used for changing the 8 bytes write data to, for example, 2 bytes write data, as partial store data. This pipeline 21b is activated by a "load access" sent from the MSU WDR 15. Two bus lines PL₁ and PL₂ are used for this operation. That is, the partial store data, for example, 2 bytes write data, is sent to the SEL 20 and merged with the 8 bytes read data. The merged 8 bytes write data is sent to the SEL 23 through the ECC 22. The ECC 22 provides a new error correcting code to the new 8 bytes write data. The output data of the SEL 23 is then written in the designated memory bank as the 8 bytes write data as explained above. Figures 6A and 6B are detailed block diagrams of a memory control unit (MCU) 4' according to an embodiment of the present invention. In Fig. 6B, another main storage unit (MSU) 5'' is connected to the MCU 4' through the bus line, and the central processing units (CPU 0, CPU 1) and the channel processing unit CHP are also connected to the MCU 4' through the bus line. For the purpose of raising the practical throughput, the MCU 4' comprises, for example, two input ports P0 and P1 for the address command sent from the address register MSAR in the CPU 0, two input ports P0 and P1 for the CPU 1, and four channel ports P0 , P1 , P2 , and P3 for the CHP. The MCU 4' also comprises write data ports corresponding to each CPU 0 port, CPU 1 port, and CHP port. For example, the CPU 0 port WD is constituted by the ports P0U and P0L corresponding to the port P0 , and the ports P1U and P1L corresponding to the port P1. The port P0U is used for upper 8 bytes and the port P0L for lower 8 bytes. Accordingly, each port P0 , P1 , P 2 , and P 3 comprises a 16 bytes capacity, so that the CHP port WD comprises a 64 bytes (16 bytes x 4) capacity. Each port comprises a capacity of at least two words of data (for example, 8 bytes x 2), in this embodiment As can be clearly understood, in this embodiment a plurality of ports are provided in the MCU 4' corresponding to each CPU and CHP in order to raise the practical throughput of the MCU. These ports are provided because, since the practical throughput between the MSU and MCU is raised by using the above-explained division and control of the memory banks, it is necessary to raise the practical throughput between the MCU and CPU or CHP. In Figs. 6A and 6B, a priority circuit 41 decides the priority of the address sent from each CPU 0, CPU 1 and CHP port, and sends the address selected by the priority decision to a write data selection register 42. The register 42 recognizes the corresponding port of the priority address selected by the priority circuit 41 and sends the corresponding write data to the MSU 5' or MSU 5'' through a write data register MS WDR. In this case, the register 42 functions to select the two word command, i.e., 16 bytes per two cycles (the upper 8 bytes are always selected first, and then the lower 8 bytes are selected), or the one word command, i.e., 8 bytes per one cycle (in this case, only the upper 8 bytes are used). A BANK BUSY register 43 is used for storing a flag of the bank accessed by the priority circuit 41, in order to control a next access designating the same memory bank as that the just previously accessed. This flag operation is used because, since the just previously accessed memory bank is "busy", when the same memory bank is designated again, the next access must be delayed for the predetermined term to avoid access collision. A pipeline 44 selects the fetch data read out from the MSU 5' and the MSU 5'' by watching the read out timings of the MSU 5' and the MSU 5''. The pipeline 44 also reports data transmission, completion of store and the like to the CPU and CHP. The selection between the MSU 5' and the MSU 5'' is performed by the head address stored in each MSU and in the pipeline 44, in accordance with the correspondence between both head addresses. In the CPU, a store buffer SB comprises an address register ADDR, and write data registers WDU and WDL. The store buffer SB is used with a cache register (not shown). Each of the registers WDU and WDL comprise 8 bytes of upper data and 8 bytes of lower data, i.e., total ot 16 bytes of data per one address. For a store (write) access of 16 bytes, the store buffer SB outputs a 16 bytes data access, i.e., two word access per two access cycles. 16 bytes data access is, in general, used whenever there is a data store access of more than 8 bytes, for example, a "move" command, or "store-multi" command. For a store access of an 8 bytes data, only the upper 8 bytes are used for data access per one cycle. Accordingly, discrimination between the 16 byte data access and the 8 byte data access, i.e., between two word access and one word access, is based on the kind of command received (for example, "move", "store-multi", etc.) and the data length of the write data. Figures 7 and 8 show control circuits of the memory bank. The control circuit shown in Fig. 7 is provided at the input portion of each EVEN BANK, and the control circuit shown in Fig. 8 is provided at the input portion of each ODD BANK. In Fig. 7, the lower portion of the circuit is a three-bit counter as one embodiment. The flip-flop FF1 is used for the most significant bit, and the flip-flop FF3 is used for the least significant bit. When the "BANK GO" signal generated from the decoder 30 is input to an OR gate OR1, the circuit starts the count from "0". An output OR gate OR2 always reaches a high level and outputs a clock hold signal CLK HOLD when the count is between "1" to "7". The signal CLK HOLD holds the contents of the registers when it is tuned ON. The input of the clock signal is inhibited while the CLK HOLD is turned ON. When the CLK HOLD is being output, even if the BANK GO is stopped, (the BANK GO is output for only one cycle), the count is continued. Further when the count returns to "0" from "7", generation of the CLR HOLD is stopped and the count also is stopped. Accordingly, since the content of each of the registers ADDR and WDR is held by the CLK HOLD, the next access request cannot be received while the CLK HOLD is turned ON. For an EVEN BANK, an operation code OPC WR provided to the head of the memory address indicates whether there is a one word command (8 bytes command) or two word command (16 bytes command). Accordingly, when the BANK GO and OPC WR are input to the flip-flop FF0 through an AND gate, a write enable signal RAM WE having a high level signal is output directly from the flip-flop FF0 to the memory bank (RAM). In Fig. 8, the lower portion of the circuit is a three-bit counter, as in the circuit shown in Fig. 7. Accordingly, a flip-flop FF1 is used for the most significant bit, and a flip-flop FF3 is used for the least significant bit. When the operation code does not indicate a 16 bytes access, a write clock hold signal WR CLK HOLD is used equivalently as an address clock hold signal AD CLK HOLD and a write data clock signal WD CLK HOLD. In this case, the operation of this circuit is the same as that of the circuit shown in Fig. 7. When the operation code indicates a 16 bytes access, the WD CLK HOLD signal is delayed by one cycle from that of the WR CLK HOLD and receives the data at the second cycle. When the AD CLK HOLD signal is longer by one cycle than that of the WR CLK HOLD, the AD CLK HOLD holds the address for an extra one cycle. When operation code 16B indicates a 16 bytes access, if the 16 bytes access is input to the flip-flop FF, the output timing of the write enable WE is delayed by only one cycle by using both AND gates and flip-flop circuit. When the count becomes "7", the 16 bytes access is delayed by only one cycle by using the flip-flop FF0. Accordingly, the AD CLK HOLD is delayed by one cycle by output of the OR gate.

Claims: A memory access control system comprising:- memory means (5') having a plurality of even and odd-numbered memory banks divided into two groups (12a₀, 12a₁, ...; 12b₀, 12b₁, ...); bus means for transferring data and including a command/address bus line, a write data bus line (17), and a read data bus line (18) all coupled to said memory means (5'), the write and read data bus lines each having a bus width of one word and being operable simultaneously; activating means, coupled to said bus means, for activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group in dependence on the single access request allowing two sequential data transfers, one from each group, to be performed over said bus means for the single access request so that in each cycle two words can be simultaneously transferred, one word over said read data bus lines and the other word over said write data bus lines, said activating means comprising:- command and address register means (13, 14), connected to said command/address bus line, for sending two-word commands to said memory means (5'), and for designating an address for a selected memory bank of each of said two groups; a decoder (30), connected to said command and address register means (13, 14) and said memory means (5'), for activating each respective designated memory bank; a write data register (15), connected to said write data bus line (17), for transferring write data; and a read data register (16), connected to said read data bus line (18), for transferring read data; characterised in that said memory means (5') comprises at least one main memory having: a plurality of bank registers (BANK REG), corresponding to said plurality of memory banks, each of said bank registers having an address register (A), a write data register (WD), and a read data register (RD); and a plurality of counter circuits corresponding to said plurality of memory banks, each counter circuit being constituted by flip-flop gates, AND gates, OR gates, and exclusive-OR gates, and being provided in an input portion of the respective memory bank; wherein each counter circuit is responsive to a signal (BANK GO) from said decoder (30) to start a count from zero, and while the count is non-zero to issue a clock hold signal (CLK HOLD, WR CLK HOLD) for holding the contents of the respective address register (A0, A2, ...; A1, A3,...) and write data register (WD0, WD2,...;WD1, WD3,..) to inhibit a next access request to the respective bank; and wherein the counter circuit of each odd-numbered memory bank (12b₀, 12b₁,...) is responsive to said two-word command to issue a delayed clock signal (WD CLK HOLD) which is delayed by one cycle from said clock hold signal (WR CLK HOLD) so as to delay write and read timing to the respective memory bank by one cycle; whereby said even numbered memory bank stores data at the same timing of said access, and said odd-numbered memory bank stores data after a delay of one cycle compared with the storing by said even-numbered memory bank. A memory access control system as claimed in claim 1, wherein said activating means further comprises a control pipeline register (21a) for controlling an output timing of read data, a write data pipeline register (21b) for controlling a write timing of partial store data, and two selectors (20, 23) for merging said partial store data with said write data. A memory access control system as claimed in claim 1 or 2, wherein in a read operation, a said even number memory bank and an adjoining odd number memory bank are simultaneously accessed by said address register means (13) based on said two word command, and said even number memory bank reads out data at a timing of specific cycles after said access, but said odd number memory bank reads out data after a delay of one cycle compared with said even number memory bank under the control of said control pipeline register. A memory access control system as claimed in any preceding claim, wherein said two word command comprises a sixteen bytes command constituted by two eight bytes commands. A memory access control system as claimed in any preceding claim, further comprising a memory control unit (4') for controlling said command and address register means (13, 14), said write data register (15) and said read data register (16) in said main memory. A memory access control system as claimed in claim 5, wherein said memory control unit (4') comprises a plurality of input port means for central processing units and channel processing units. A memory access control system as claimed in claim 6, wherein each of said plurality of input port means comprises at least two input ports (P0, P1, ...; P0U, P0L, P1U, P1L), said two input ports being an upper eight bytes port and a lower eight bytes port.

Inventors: CHIBA TAKASHI, CHIBA, TAKASHI DAI 2 SAGINUMA GURIN HIRU 206
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1985
Main classification: G06F12
IPC codes: G06F13, G06F12