ARRANGEMENT FOR CHECKING THE PARITY BIT-CONTAINING BIT GROUPS

Abstract: In a system in which the parity of many bit groups must be checked it is proposed to check these bit groups simultaneously and jointly. The parity bits generated by the parity generators are interchanged crosswise, are combined with the parity bits con­ tained in the bitgroups and applied to a common output. Conse­ quently, only this specific output must be checked. The checking circuit itself is checked by inverting one of the parity generators periodically.

Description: flarrangement for checking the parity of parity bit-con taining bit groups. The invention relates to an arrangement for checking the parity of parity bit-containing bit groups. Such an arrangement is generally known. If in a system such as, for example, a telephone exchange, the parity of a bit group has to be determined in a large number of places, or the parity of many bit groups have to be checked in one place, this requires a large investment in equipment, such as parity generators and convertors. In addition, the result of the comparison between the transmitted parity of the bit group and the parity generated by the parity generator has to be checked, which requires additional hardware. So as to ensure the reliability of the system all the additional equipment must moreover also be supervised. The invention has for its object to provide an arrangement for checking the parity of a parity bit-containing bit groups, with the aid of which the parity can be checked using only few means and with which also the reliability of these means can be supervised. According to the invention, an arrangement for checking the parity of parity bit-containing bit groups is characterized in that a number of n bit groups are checked in parallel, that the arrangement comprises n parity generators (PG1, PG2, PG3) each coupled to one bit group for generating the parity of the relevant bit group, that the arrangement further comprises n comparison circuits each having first and second inputs and an output, that an output of a parity generator is always connected to a first input of a comparison circuit, that the parity bit of each of the bit groups is applied to the second input of the comparison circuit but in such manner that at a specific comparison circuit the generated parity bit applied to the first input is derived from a different bit group than the parity bit applied to the second input, that the outputs of the comparison circuits are connected to a logic network for generating, at an output of the logic network,a logic signal which supplies a first value if all the generated parity bits are in agreement with the parity bit contained in the bit groups and a second value if one of the generated parity bits is not in agreement with the parity bit of the associated bit group. An advantageous embodiment of an arrangement for checking the parity of parity bit-containing bit groups is characterized in that one of the parity generators has a control input for inverting the parity bit generated at the output of that parity generator, as a result of which the signal generated at the output of the logic network is inverted if the logic network has operated in the prescribed way. An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawing, the sole Figure of which shows in block schematic form an arrangement for checking the parity of parity bit containing bit groups. References R1, R2 and R3 denote a number of binary registers for storing a bit group consisting of a data portion D1 D2 and D3, respectively and a parity portion P1, P2 and cc.PP3, respectively. The invention is however not limited to embodiments comprising three registers. The invention can also be used without any drawbacks for any other number of registers. Parity generators PGt, PG2 and PG3 for generating the parity of the bit group data portion present in the data portion of the register are connected to an output of each data portion D1, D2 and D3 of the registers R1, R2 and R3, respectively. An output of each of the parity generators PG1, PG2 and PG3 and an output of each of the parity portions P1, P2 and P of the registers R1, R2 and R3 are together 3 3 connected to a logic circuit LC of which the exclusive OR-circuits EX-OR1, EX-OR2, EX-OR form part. This is 3 effected in such a way that the inputs of these circuits are connected in a cyclic sequence to outputs of different parity portions and parity generators. This means that the output of the parity portion P1 of register R1 is connected to a first input of the exclusive OR-circuit EX-OR1, whilst the output of parity generator PG2 is connected to a second input of the exclusive OR-circuit EX-OR1. Similarly, the output of the parity portion of register R2 is connected to the first and the output of parity generator PG3 to the second input of EX-OR2 and the output of the parity portion of register R3 is connected to the first and the output of parity generator PG1 to the second output of EX-OR Outputs of the exclusive OR-circuits EX-OR1 3. and EX-OR2 are connected to first and second inputs, respectively of a further exclusive OR-circuit EX-OR4, whilst an output of the exclusive OR-circuit EX-OR5 and an output of EX-OR4 are connected to a fifth exclusive OR-circuit EX-OR5. An output of EX-OR5 is connected to an output which also constitutes the output of the logic circuit LC. The checking circuit operates as follows. If the parities generated by the parity generators PG1, PG2 and PG3 correspond to the parity which was transmitted and stored in the parity portions P1, P2 and P3 of the registers, then at odput OUT a logic value of a first type will be supplied. In the example shown in the drawing PG1 = P1 = tlt, PG2 = P2 = "Oe and PG3 = P3 = "1" a signal having the logic value non will occur at output OUT. In all other cases in which the generated parity (PGi) corresponds to the parity contained in the parity portion P1 a logic value on will always appear at the output OUT. Consequently, this circuit has the advantage that for every three bit groups (n-bit groups in general) only one output need to be checked. If an error occurs, so that one of the parity generators generates a parity which differs from the parity bit stored in the register, then the output OUT will assume the second logic value ("1"), which is indicative of the occurrence of the error. Now it may happen that a malfunction occurs in the logic circuit LC causing a logic signal of the first type to be always supplied from the output, so that prevailing errors cannot be indicated anymore. To check this, one of the parity generators PG1, PG2 or PG3 (in the drawing PG1) is given a test input TST. Applying a suitable signal to the test input TST causes the output of the relevant parity generator (PG1 in the drawing) to be inverted. When the logic circuit supplies from the output OUT a logic signal of the first (second) value this must result in this value being inverted to the second (first) value. If no inversion occurs this indicates that the logic circuit LC is operating incorrectly. Inverting one of the parity generators at regular time intervals prevents a circuit (i.e. the logic circuit Lg) which becomes defective remaining unnoticed.

Claims: 1. An arrangement for checking the parity of parity bit-containing bit groups, characterized in that a number of bit groups is checked in parallel, that the arrangement comprises n parity generators (PG1, PG2, ... PGn) each coupled to a respective bit group for generating the parity of the relevant bit group, that the arrangement further comprises n comparison circuits each having first and second inputs and an output, that an output of each parity generator is always connected to a first input of a respective comparison circuit, that the parity bit of each of the bit groups is applied to the second input of a respective comparison circuit in such manner that at a specific comparison circuit the generated parity bit applied to the first input is derived from a different bit group from the parity bit applied to the second input, that the outputs of the comparison circuits are connected to a logic network for generating, at an output of a logic network, a logic signal which has a first value if all the generated parity bits are in agreement with the parity bit contained in the bit groups and has a second value if one of the generated parity bits is not in agreement with the parity bit of the associated bit group. 2. An arrangement for checking the parity of parity bit-containing bit groups as claimed in Claim 1, characterized in that one of the parity generators has a control input for inverting the parity bits generated at the output of that parity generator, in response to which the signal generated at the output of the logic network is inverted if the logic network has operated in the prescribed manner.

Inventors: MATENA, JAN, VERHEUL, HANS HENDRIK
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1985
Main classification: G06F11
IPC codes: H03M13, G06F11