PHASE DETECTOR

Abstract: A phase detector for detecting in real time the difference in phase between frequency pulse signals and data pulse signals, including a control signal generator for generating control signals corresponding to the occurrence of the frequency pulse signals and the occurrence or non-­ occurrence of the data pulse signals, and a circuit, operative during the occurrence or non-occurrence of the data pulse signals, for producing a phase error signal indicating differ­ ences between the real time occurrence of the frequency pulse signals and the data pulse signals. Another circuit of the phase detector, if needed, responds to the control signals to correct the integral of the phase error signal.

Description: The present invention relates generally to apparatus for comparing two signals and, more particularly, to a phase detector for detecting the difference in phase between frequency pulse signals and data pulse signals. In the processing of information generally, it often is necessary to compare two different signals to accomplish a variety of purposes. The comparison may result in the generation of an error signal representing a difference between the two signals. Circuitry may then respond to the error signal to minimize this difference between the two signals or perform some other function based on this difference, as is needed. For example, a phase detector is conventionally used to detect the difference in phase between two signals. The phase detector may be used in a phase-locked loop that, among other components, has a voltage controlled oscillator (VCO) whose output is a frequency pulse signal. The phase detector receives a stream of data pulse signals, together with the frequency pulse signal which is fed back from the VCO. Any difference in phase between the data pulse signals and the frequency pulse signal results in the generation of a phase error signal that is filtered and then used to control the VCO so that the frequency pulse signal and the data pulse signals become in phase. Certain types of data pulse streams, such as those known as MFM disk data, can cause difficulty when inputted to a phase-locked loop via the phase detector. This is because the data pulse stream will have "holes" in it, meaning that there are no data pulse signals in the pulse stream for a given period, such as a "bit time" if the data pulse signals are binary digital signals. As is known, these "missing" data pulse signals can cause the phase detector to malfunction. A prior approach to solving the problem of the missing data pulse signals is to arm the phase detector only if a data pulse signal occurs and to disarm the phase detector if a data pulse signal does not occur during the bit time. This technique uses a time delay device which receives in real time the stream of data pulse signals and outputs to the phase detector delayed data pulse signals which are to be compared to the frequency pulse signal of the VCO. The phase detector also receives in real time the stream of data pulse signals for arming purposes. Thus, in operation, the data pulse stream is fed to the input of the time delay device as well as to the phase detector. If a data pulse signal occurs, the phase detector is armed and then, a short time later, receives the same, but delayed, data pulse signal which had been delayed by the time delay device. This delayed data pulse signal is then compared with the frequency pulse signal to produce the phase error signal. However, if no data pulse signal occurs during the bit time, the phase detector is not armed, so that it does not operate for phase detection purposes. One problem with the prior solution is the requirement of a time delay device. In addition to requiring a time delay device which may be expensive, the delay must be precise, so as to have the phase detector properly compare its two input signals. The realization of such a precision time delay is not always easily accomplished. Also, the delay should be equal to one-half the cycle of the nominal frequency of the VCO. Therefore, if the nominal frequency of the VCO is to be changed, which may require using a different VCO in the phase-locked loop, then a new time delay device may be needed in view of the requirement that the delay be equal to one-half the cycle of the nominal frequency. Still furthermore, the arming and disarming of the phase detector has the disadvantage of causing the phase detector to change state between an operative or armed condition and a non-operative or disarmed condition. United States Patent Specification No 3,991,378, discloses a phase lock circuitry including means for providing a frequency variable feedback signal and a phase dectector receiving the input signal and the feedback signal. The phase detector provides pulses whose width and average value are dependent on the phase relationship between the input and feedback signals. Summary of the Invention The present invention provides apparatus for comparing the phase of pulses in a first pulse signal which may have pulses missing, with the phase of respective pulses of a second pulse signal having a positive half cycle and a negative half cycle in each pulse interval and which is regular and continuous, comprising control means for generating a set of control signals indicative of the occurrence and non-occurrence of pulses in each of said first and second pulse signals, and difference means responsive to said set of control signals to produce an output signal representative of the difference in phase between pulses of the first pulse signal and respective pulses of the second signal, the difference means being operative continuously and arranged to produce no change in the output signal in the event of the non-occurrence of a pulse in the first pulse signal; characterised in that the difference means includes charge storage means and charging means to vary the charge level therein in response to said set of signals to produce said output signal, the arrangement being such that in the event a pulse of the first signal does not occur during the respective pulse interval, said charge storage means is discharged during the positive half cycle and charged during the negative half cycle, so that the said charge storage means has the same charge at the beginning and end of said pulse interval. Brief Description of the Drawings Fig. 1 is a block diagram of a phase-locked loop showing one application of the present invention; Fig. 2 is a schematic illustration of partial circuitry of a phase detector of the present invention; Figs. 3A-3D are waveforms used to explain the present invention; Fig. 4 is a truth table used to explain one mode of operation of the present invention; and Fig. 5 illustrates schematically other circuitry of the present invention for implementing, as one example, the truth table of Fig. 4. Best Mode of Carrying Out The Invention Fig. 1 shows a circuit 10 of the present invention for comparing in real time input signals received on a line 12 and a line 14, respectively. In response to these input signals, the circuitry 10 produces an error signal on an output line 16 indicating a difference between the two input signals. As one example, the circuitry 10 is a phase comparator or detector 18 which may be part of an overall phase-locked loop 20 that also has a filter 22 and a voltage controlled oscillator (VCO) 24. In the general operation of the phase-locked loop 20, the VCO 24 will output on a line 25 frequency pulse signals that are fed back over line 12 as one of the input signals to the phase comparator 18. The other input signals on line 14 may be a stream of externally supplied data pulse signals which are to be compared to the frequency pulse signals on line 12. In response to any phase difference between the frequency pulse signals on line 12 and the data pulse signals on line 14, the phase comparator 18 will output a phase error signal on line 16. The filter 22 then filters the phase error signal which then controls the VCO 24 to adjust the frequency of the frequency pulse signals on line 25 in a direction to be in phase with the data pulse signals on line 14 and, thereby, minimize the phase error signal on line 16. The phase-locked loop 20 operates in such a manner that the frequency pulse signals on line 12 always occur, i.e., are always present, as an input to the phase detector 18. However, the externally provided data pulse signals on line 14 may or may not occur during a cycle of the frequency pulse signals on line 12 for any number of well-known reasons. Nevertheless, the phase detector 18 is always operative to provide an accurate phase error signal on line 16, irrespective of the occurrence or non-occurrence of the data pulse signals on line 14. As will be further described, the phase detector 18 assumes that a data pulse signal will occur during a given cycle of the frequency pulse signals, and corrects for that assumption should the data pulse signal not occur. The phase detector 18 has means 26 for generating control signals on lines 28 indicating the occurrence of the frequency pulse signals on lines 12 and the occurrence or non-occurrence of the data pulse signals on line 14. The phase detector 18 also has a means 30, responsive to the control signals on lines 28, for producing an output signal on a line 32 which indicates the phase difference between the real time occurrence of the frequency pulse signals on line 12 and the data pulse signals on line 14. As will be further described, the phase error signal produced by the means 30 on line 32 will be at a correct level at the end of each respective cycle of the frequency pulse signals on line 12. However, in certain applications of the phase detector 18, such as for a phase-locked loop 20, not only should the level of the phase error signal be correct at the end of each cycle, but the integral of the phase error signal throughout the duration of each cycle should be correct for satisfactory operation of the overall phase-locked loop 20. The means 30 may not provide for the proper integral of the phase error signal throughout each cycle. Accordingly, if it is needed or otherwise advantageous for the operation of a given phase-locked loop 20, the means 26 also can be adapted to produce control signals on lines 34 which indicate the occurrence of the frequency pulse signals on line 12 and the occurrence or non-occurrence of the data pulse signals on line 14. The phase detector 18 then will also have means 36 for providing for the correct integral of the phase error signal throughout the duration of each cycle by outputting a signal on a line 38 which, when summed with the signal on line 32 by a summer 40, results not only in the correct phase error signal on line 16 at the end of each cycle, but the correct integral of the phase error signal on line 16 during each cycle. Fig. 2 illustrates schematically the means 30 which responds to the control signals on lines 28 to produce the output signal on line 32 leading to the summer 40. Fig. 3A shows the frequency pulse signals on line 12, Fig. 3B shows the occurrence and non-occurrence of the data pulse signals on line 14, and Fig. 3C shows the output signal on line 32. Fig. 4 is a truth table of the logic or control signals on the lines 28 for the specific waveform periods A-H that are shown. The means 30 has a charge storage device 42, such as a capacitor 44, for storing a charge representing the difference in phase between the frequency pulse signals on line 12 and the data pulse signals on line 14. A current source CS₁, supplying a current of magnitude I, is coupled to the capacitor 44 through a switch SW₁ and a line 46. When switch SW₁ is closed, the capacitor 44 is discharged via line 46, switch SW₁, current source CS₁ and a line 48 to ground. When switch SW₁ is open, the capacitor 44 is not discharged. Another current source CS₂, coupled to V CC over a line 50, supplies a current of magnitude I to the capacitor 44 via a switch SW₂ and the line 46. Thus, when the switch SW₂ is closed, the current source CS₂ supplies current of magnitude I to charge the capacitor 44. When switch SW₂ is open, the capacitor 44 is not charged by the current source CS₂. Another current source CS₃, coupled to line 50, supplies current of a magnitude I to the capacitor 44 via a switch SW₃, a diode 52 and line 46. When switch SW₃ is closed, the capacitor 44 is charged by current source CS₃ through switch SW₃, diode 52 and line 46. When switch SW₃ is open, the capacitor 44 is not charged by the current source CS₃. The respective switches SW₁, SW₂, and SW₃ are controlled by respective logic control signals on respective lines 28-1, 28-2 and 28-3 of the lines shown generally at 28. Fig. 4 shows the logic state of these control signals on respective lines 28-1 to 28-3 for respective waveform periods A-H. A logic 1 indicates that the corresponding switch is closed and a logic 0 indicates that the switch is open. As shown in Fig. 3A, the frequency pulse signal on line 12 has given cycles CYC, with three exemplary cycles CYC₁-CYC₃ being shown. Each cycle CYC₁-CYC₃ has a positive half cycle and a negative half cycle. As indicated in Fig. 3B, three conditions will be described in which (1) a data pulse signal DPS₁ on line 14 occurs during the positive half cycle of a given cycle CYC, such as cycle CYC₁, (2) no data pulse signal on line 14 occurs during a full cycle, such as CYC₂, and (3) a data pulse signal DPS₂ on line 14 occurs during the negative half cycle of a given cycle CYC, such as cycle CYC₃. As will be further described, the phase detector 18 operates continuously by assuming that a data pulse signal will arrive on line 14 during a given cycle CYC of the frequency pulse signal on line 12. If the data pulse signal on line 14 does in fact arrive, then the assumption is correct. If the assumption is incorrect, in that such a data pulse signal does not arrive on line 14 during a given cycle CYC, then the phase detector 18 undertakes corrective action during the course of the given cycle CYC. The operation of the means 30 will be described in relation to the waveform periods A-H shown in Figs. 3A-3D. Also, it will be assumed that at the leading edge of the positive half cycle of CYC₁, the capacitor 44 is charged to a level L₁, as shown in Fig. 3C. As shown in Fig. 4, when such a leading edge occurs on line 12, switch SW₁ is closed, and switch SW₂ and switch SW₃ are opened, with these switches SW₁-SW₃ remaining in these states during the waveform period A. Accordingly, capacitor 44 begins to be discharged from the level L₁. Then, when the data pulse signal DPS₁ on line 14 occurs, which begins the waveform period B, switch SW₁ is opened and switches SW₂-SW₃ remain open, as indicated in Fig. 4. As a result, at this time the capacitor 44 has been discharged to a level L₂, as shown in Fig. 3C, and remains at this level L₂ through the waveform period C until the end of the cycle CYC₁. Thus, the level L₂ represents the difference in phase between the leading edge of the frequency pulse signal of cycle CYC₁ and the leading edge of the data pulse signal DPS₁ occurring within the positive half cycle of this cycle CYC₁. During the waveform period C, switch SW₁ and switch SW₃ are closed. Thus, current source CS₁ of magnitude I discharges the capacitor 44 while current source CS₃ of magnitude I charges the capacitor 44, so that the charge on capacitor 44 remains fixed, as shown. The reason for this dual discharging and charging of capacitor 44 will be discussed more fully below in relation to means 36. Next, assume that cycle CYC₂ is occurring. At the leading edge of the positive half cycle of cycle CYC₂, which begins the waveform period D, switch SW₁ is closed, while switch SW₂ and switch SW₃ are opened. Accordingly, capacitor 44 is discharged through switch SW₁, beginning at level L₂ and until the end of the positive half cycle of cycle CYC₂ at which time the charge is at a level L₃. Then, since no data pulse signal has occurred during the positive half cycle of cycle CYC₂, at the commencement of the negative half cycle, which begins the waveform period E, the truth table of Fig. 4 shows that switch SW₁ is opened, switch SW₂ remains open and switch SW₃ is now closed. Accordingly, capacitor 44 is now charged by current source CS₃ through switch SW₃ from level L₃ back to level L₂. Thus, at the end of the cycle CYC₂, in which no data pulse signal has occurred, the charge on capacitor 44 is the same at the beginning and end of the cycle CYC₂. Next, for cycle CYC₃, at the leading edge of the positive half cycle which starts waveform period F, and with capacitor 44 charged to level L₂, switch SW₁ becomes closed, switch SW₂ remains open and switch SW₃ becomes open, as indicated in Fig. 4. Accordingly, capacitor 44 now is discharged through switch SW₁ until the end of the positive half cycle to the level L₃. Then, at the commencement of the negative half cycle of the cycle CYC₃, beginning at waveform period G, switch SW₁ becomes open, switch SW₂ remains open, and switch SW₃ becomes closed. Accordingly, capacitor 44 is charged by current source CS₃ through switch SW₃ and diode 52 until the data pulse signal DPS₂ occurs during the negative half signal, at which time the charge is at a level L₄. Then, upon the occurrence of the leading edge of the data pulse signal DPS₂ during the negative half cycle, which commences waveform period H, and as indicated in Fig. 4, switch SW₁ remains open, but switch SW₂ now is closed with switch SW₃ remaining closed. Accordingly, capacitor 44 is now charged at a faster rate (2I) during waveform period H than during waveform period G, since current source CS₂ and current source CS₃ both supply current to capacitor 44. This charging at the rate of 2I occurs in anticipation of and until the leading edge of the next succeeding cycle CYC₄ occurs (only partially shown in Fig. 3A) at which time capacitor is charged to a level L₅, which is higher than level L₄ at the commencement of cycle CYC₃. This level L₅ indicates the difference in phase between the leading edge of the data pulse signal DPS₂ and the leading edge of the next succeeding cycle CYC₄. As described above, the charge stored on the capacitor 44 at the end of each cycle CYC₁-CYC₃ provides the correct information on line 32 identifying the difference in phase between the data pulse signals on line 14 and the frequency pulse signals on line 12. However, while not specifically illustrated, it can be seen that the integral of the signal shown in Fig. 3C throughout the duration of each cycle CYC₁-CYC₃ may not be correct for the satisfactory operation of the phase-locked loop 20. Accordingly, the phase detector 18 also includes, as shown in Fig. 2, the means 36 for providing for a correct integral of the phase error signal by outputting a signal on line 38 which, when summed by summer 40, produces the desired correction. The means 36 includes a charge storage device 52, such as a capacitor 54 which may be charged, discharged or have its charge fixed during the course of a given cycle CYC₁-CYC₃. A current source CS₄, coupled to V cc via a line 55, supplies a current of magnitude I through a switch SW₄ and a line 56 to charge the capacitor 54. A current source CS₅ of a magnitude I is coupled to the capacitor 54 through a switch SW₅ and line 56 to discharge the capacitor 54 to ground via a line 58. Another current source CS₆ is coupled to capacitor 54 through a switch SW₆ to discharge the capacitor 54 to ground via the line 58. Whereas the value of the current sources CS₄-CS₅ have the same magnitude I, the current source CS₆, for reasons to be described below, has a magnitude of I₁ which is greater than I, where I₁ may be, for example, 1.2I. For reasons also to be described below, means 36 has a clamping transistor 60 having a collector coupled to line 55 and an emitter coupled to line 56, with its base being coupled over a line 62 to a node 64 between switch SW₃ and diode 52. Switch SW₄, switch SW₅ and switch SW₆ are opened and closed in response to the logic control signals on respective lines 34-1 to 34-3, as shown in Fig. 2 and in accordance with the truth table of Fig. 4. Fig. 3D shows in solid lines the same waveform of Fig. 3C produced by the means 30 on line 32. Also shown in Fig. 3D by the chain-dotted line, is the waveform produced by the means 36 on line 38. In operation, upon the occurrence of the positive half cycle of cycle CYC₁ at the beginning of waveform period A, and assuming the charge on capacitor 54 is at level L₁ equal to the charge on capacitor 44, switch SW₄ is closed and switch SW₅ and switch SW₆ are open, as shown in Fig. 4. Accordingly, current source CS₄ begins to charge capacitor 54 through switch SW₄ and line 56 equally and opposite to the discharging of capacitor 44. Then, when the data pulse signal DPS₁ arrives during the positive half cycle of cycle CYC₁, shown at the beginning of the waveform period B, the switch SW₄ is now opened, with switch SW₅ and switch SW₆ remaining open. Accordingly, the charge on capacitor 54 is now at a level L₆ and becomes fixed or remains at level L₆ for the duration of the positive half cycle of cycle CYC₁. Then, at the commencement of the negative half cycle of cycle CYC₁, which starts waveform period C, switch SW₄ remains open, but switch SW₅ and switch SW₆ now are closed. Therefore, capacitor 54 now discharges quickly from level L₆ to the level L₂ at or before the end of the negative half cycle of cycle CYC₁. In order to be sure that capacitor 54 is discharged to the same level L₂ of capacitor 44 at or before the end of the negative half cycle CYC₁, both switch SW₅ and switch SW₆ are closed, so that a discharge or pull-down current of I+1.2I=2.2I via current source CS₅ and current source CS₆, respectively, is used. Actually, the maximum pull-down current need be only 2I, but the magnitude 2.2I is utilized to ensure that level L₂ will be reached within the appropriate time. Furthermore, the clamping transistor 60 is used to ensure that capacitor 54 is not discharged below the level L₂. During the waveform period C, switch SW₃ is closed, as previously described, so that transistor 60 is base biased via line 62 at a voltage which is slightly higher than the voltage of capacitor 44 due to a one voltage drop across diode 52. Then, until the charge on capacitor 54 falls to about level L₂, the voltage of capacitor 54 maintains transistor 60 off. Then, when capacitor 54 is discharged to about level L₂, the transistor 60 is turned on, so that current source CS₅ and current source CS₆ now draw current from V cc through transistor 60, rather than from capacitor 54. Then, for a cycle such as cycle CYC₂ in which a data pulse signal on line 14 does not occur, at the leading edge of the positive half cycle of cycle CYC₂, which commences the waveform period D, switch SW₄ is closed, with switch SW₅ and switch SW₆ being opened. Therefore, capacitor 54 is charged by current source CS₄ through closed switch SW₄ to a level L₇. This charging of capacitor 54 is equal and opposite to the discharging of capacitor 44 to level L₃. Next, during the negative half cycle of the cycle CYC₂, which commences the waveform period E, switch SW₄ is opened, switch SW₅ is closed and switch SW₆ remains open, so that capacitor 54 is discharged through switch SW₅ to the level L₂ which is the charge on capacitor 44 at this time. Thus, for a cycle such as cycle CYC₂ during which no data pulse signal occurs on line 14, capacitor 54 is charged and discharged equally and opposite to the discharging and charging, respectively, of capacitor 44. For cycle CYC₃ with the data pulse signal DPS₂ occurring during the negative half cycle, at the leading edge of the positive half cycle, which commences the waveform period F, switch SW₄ is closed, switch SW₅ is opened and switch SW₆ remains opened. Accordingly, current source CS₄ charges capacitor 54 through switch SW₄, equally and opposite to the discharging of capacitor 44, to the level L₇ at the end of the positive half cycle. Next, commencing at the negative half cycle, which begins the waveform period G, switch SW₄ is opened, switch SW₅ is closed and switch SW₆ remains open. Therefore, capacitor 54 is discharged via switch SW₅ to the level L₅, at which time the data pulse signal DPS₂ on line 14 occurs. At the time of the leading edge of the data pulse signal DPS₂, which commences the waveform period H, switch SW₄-switch SW₆ are opened, so that the charge level L₅ remains fixed during the waveform period H and equal to the charge on capacitor 44 at the end of cycle CYC₃. Fig. 3D also shows in dotted lines the averaged signal AVE on line 16 at any instant of time throughout the duration of each cycle CYC₁-CYC₃. This averaged signal AVE results from using the means 36 in addition to the means 30. As may be appreciated, the integral of the averaged signal AVE is such that the overall phase-locked loop 20 will operate more satisfactorily than if means 36 were not used. Fig. 5 shows schematically the means 26 for generating the control signals on lines 28-1 to 28-3 and lines 34-1 to lines 34-3 in response to the frequency pulse signals on line 12 and the data pulse signals on line 14. The means 26 includes a D-type flip-flop 64 which detects if data pulse signals on line 14 are occurring during any positive half cycle of the frequency pulse signals on line 12. Another flip-flop 66 detects if the data pulse signals on line 14 are occurring during any negative half cycle of the frequency pulse signals on line 12. Accordingly, flip-flop 64 has a data input D coupled to line 12 and a clock input coupled to the line 14. Flip flop 64 also has a clear input coupled to line 12 for clearing the flip-flop 64 on negative going or trailing edges of the frequency pulse signals on line 12. An AND gate 68 has one input coupled to line 12 and another input coupled to the output Q of flip-flop 64 over a line 70. The output of gate 68 is produced on the line 34-1 which is coupled to the switch SW₄. An OR gate 72 has one input coupled to the output of gate 68 on line 34-1 and another input coupled to the output Q of a flip-flop 74 on the line 34-3 leading to switch SW₆. The output of OR gate 72 is coupled to line 28-1 leading to switch SW₁. Flip flop 74 has a D input receiving a logic 1 over a line 76 and a clock input coupled to the line 70. An inverter 78 has its input coupled to line 12 and its output coupled to line 28-3 leading to switch SW₃ as well as to the D input of flip-flop 66 and to a clear input of flip-flop 74. The clock input of flip-flop 66 is coupled to the line 14, while the output Q of flip-flop 66 is coupled to the line 28-2 leading to switch SW₂ and the output Q is coupled to a line 80. An AND gate 82 has one input coupled to the line 28-3 and the other input coupled to line 80. The output of AND gate 82 is coupled to the line 34-2 leading to switch SW₅. As previously mentioned, the control signal generating means 26 will produce logic control signals indicating at all times the occurrence of the frequency pulse signals on line 12 and the occurrence or non-occurrence of the data pulse signals on line 14. However, one sequence of operation of means 26 will now be described, assuming that the signals appear on line 12 and line 14 as shown in Fig. 3A-Fig. 3B, for each waveform period A-H. Thus, assume that flip-flop 64 is cleared and that flip-flop 66 is cleared. Then, at the leading edge of the positive half cycle of cycle CYC₁, line 12 is at logic 1 and flip-flop 64 has a logic 1 on line 70. Accordingly, AND gate 68 outputs on line 34-1 a logic 1 to close switch SW₄. In addition, with line 34-1 being a logic 1, the OR gate 72 outputs a logic 1 on line 28-1 to close switch SW₁. Furthermore, inverter 78 inverts the logic 1 on line 12 to produce a logic 0 on line 28-3, thereby clearing flip-flop 74 to produce a logic 0 on line 34-3 and open switch SW₆. With flip-flop 66 being cleared at this time, the output Q on line 28-2 is at logic 0 to open switch SW₂. Also, since inverter 78 inverts the logic 1 on line 12 to produce the logic 0 on line 28-3, the switch SW₃ is opened. With line 28-3 being at logic 0 at this time, gate 82 is disabled to produce a logic 0 on line 34-2 to open switch SW₅. Thus, these are the logic states of switches SW₁-SW₆ as indicated for waveform period A in Fig. 4. Then, at the beginning of the waveform period B, at the leading edge of the data pulse signal DPS₁, flip-flop 64 is clocked, as is flip-flop 66. Accordingly, the output Q on line 70 goes to logic 0, so that AND gate 68 is disabled to produce a logic 0 on line 34-1 and open switch SW₄. Also, flip-flip 74 remains in the same cleared state to continue producing a logic 0 on line 34-3. The two inputs to OR gate 72 are at logic 0, so that line 28-1 is now at logic 0. Flip-flop 66, while clocked, does not change state, so that line 28-2 and line 34-2 remain at logic 0, as does line 28-3. Thus, switches SW₁-SW₆ are in the open state shown in Fig. 4 for waveform B. Next, at the beginning of waveform period C at the trailing edge of the positive half cycle of cycle CYC₁, flip-flop 64 is cleared via line 12. Accordingly, AND gate 68 outputs a logic 0 on line 34-1 in response to the logic 0 on line 12 and line 70 goes to logic 1 to clock flip-flop 74. Therefore, the output Q on line 34-3 is at logic 1, as is the output of OR gate 72 on line 28-1. Thus, switch SW₁ and switch SW₆ are closed, while switch SW₄ is open. Since line 12 is at logic 0, line 28-3 is now at logic 1 during this waveform period C. Also, flip-flop 66 is still cleared to produce a logic 0 on line 28-2 and a logic 1 on line 80. Accordingly, AND gate 82 outputs a logic 1 from line 80 and a logic 1 from line 28-3 to produce a logic 1 on line 34-2. Therefore, switch SW₂ is open and switch SW₃ and switch SW₅ are closed, as indicated in Fig. 4. Next, for waveform period D, at the leading edge of the positive half cycle of cycle CYC₂, line 12 goes to logic 1 with line 70 remaining at logic 1. Accordingly, AND gate 68 outputs a logic 1 on line 34-1. Also, OR gate 72 couples the logic 1 on line 34-1 to line 28-1. At this time, flip-flop 74 is cleared by the logic 0 on line 28-3, so that line 34-3 is at logic 0. Therefore, switch SW₁ and switch SW₄ are closed, while switch SW₆ is open. At the leading edge of the positive half cycle of cycle CYC₂, flip-flop 66 is cleared via the logic 0 on line 28-3 at the output of inverter 78. Accordingly, line 34-2 leading to switch SW₅ is at logic 0 since AND gate 82 is disabled by the logic 0 on line 28-3. Also, with flip-flop 66 being cleared, the output Q on line 28-2 is at logic 0. Thus, switches SW₂, SW₃ and SW₅ are opened. At the commencement of the waveform period E, flip-flop 64 becomes cleared and gate 68 becomes disabled. Accordingly, line 34-1 is at logic 0. Flip-flop 74 remains cleared to output a logic 0, so that line 28-1 is at logic 0 as is line 34-3. Thus, switches SW₁, SW₄ and SW₆ are opened. Also, the output of inverter 78 at this time on line 28-3 is at logic 1. And with flip-flop 66 still being cleared, line 80 is at logic 1, resulting in line 34-2 being at logic 1 via AND gate 82, and line 28-2 is at logic 0. Thus, switch SW₂ is opened, while switches SW₃ and SW₅ are closed. At the commencement of the waveform period F, line 12 goes to logic 1 and flip-flop 64 remains cleared, with line 70 at logic 1. Thus, gate 68 outputs a logic 1 on line 34-1, gate 72 outputs a logic 1 on line 28-1 and flip-flop 74, which is cleared via the logic 0 on line 28-3, provides a logic 0 on line 34-3. Therefore, switches SW₁ and SW₄ are closed, while switch SW₆ is opened. Also, with line 28-3 going to logic 0, flip-flop 66 becomes cleared. Therefore, line 28-2 goes to logic 0 as does line 34-2. Thus, switches SW₂, SW₃ and SW₅ are opened. Next, at the start of waveform period G, line 12 goes to logic 0 and flip-flop 64 is cleared. Thus, line 34-1 goes to logic 0, and with flip-flop 74 remaining cleared, line 34-3 is at logic 0, as is line 28-1. Therefore, switches SW₁, SW₄ and SW₆ are open. Flip-flop 66 is still cleared at this time, with line 28-3 being at logic 1. Therefore, line 28-2 is at logic 0 and line 34-2 is at logic 1. Consequently, switches SW₃ and SW₅ are closed, while switch SW₂ is opened. Finally, at the commencement of waveform period H, flip-flop 64 and flip-flop 66 are clocked by the data pulse signal DPS₂ on line 14 with line 12 being at logic 0. Accordingly, line 34-1, line 34-3 and line 28-1 are at logic 0, whereby switches SW₁, SW₄ and SW₆ are opened. Line 28-3 is at logic 1 via inverter 78. Therefore, upon the clocking of flip-flop 66, line 28-2 goes to logic 1 and line 34-2 goes to logic 0 since gate 82 becomes disabled via the logic 0 on line 80. Thus, switches SW₂ and SW₃ are closed, while switch SW₅ is opened.

Claims: Apparatus for comparing the phase of pulses in a first pulse signal (14) which may have pulses missing, with the phase of respective pulses of a second pulse signal (12) having a positive half cycle and a negative half cycle in each pulse interval and which is regular and continuous, comprising control means (26) for generating a set of control signals (28- 1,2,3 ) indicative of the occurrence and non-occurrence of pulses in each of said first and second pulse signals, and difference means (30) responsive to said set of control signals to produce an output signal (16) representative of the difference in phase between pulses of the first pulse signal and respective pulses of the second signal, the difference means being operative continuously and arranged to produce no change in the output signal in the event of the non-occurrence of a pulse in the first pulse signal; characterised in that the difference means includes charge storage means (44) and charging means (SW 1,2,3, CS 1,2,3) to vary the charge level therein in response to said set of signals to produce said output signal, the arrangement being such that in the event a pulse of the first signal does not occur during the respective pulse interval, said charge storage means is discharged during the positive half cycle and charged during the negative half cycle, so that the said charge storage means has the same charge at the beginning and end of said pulse interval. Apparatus, according to claim 1 characterised in that said difference means (30, 36) assumes that a pulse of the first signal (14) will occur during the respective pulse interval of the second pulse signal and corrects for the assumption in the event the pulse of the first signal does or does not occur during that interval. Apparatus, according to claim 2 characterised in that in the event that a pulse of the first signal does not occur during the respective pulse interval, the correction occurs beginning at the negative half cycle. Apparatus, according to any one of claims 1 to 3 characterised in that said difference means charges and discharges said charge storage means as follows: a) if a pulse of said first pulse signal occurs during the positive half cycle of the respective pulse interval, said charge storage means is discharged from the beginning of the positive half cycle until the occurrence of that pulse and then retains the remaining charge until the end of the respective pulse interval, in which a difference in charge between the beginning and end of the pulse interval represents a difference in phase between that pulse and the respective pulse of the second pulse signal; b) if a pulse of said first pulse signal does not occur during the entire respective pulse interval of said second pulse signal, said charge storage device is discharged from the beginning of the positive half cycle until the beginning of the negative half cycle of that pulse interval, and then said charge storage device is charged from the beginning of the negative half cycle until the end of the negative half cycle of that pulse interval, so that there is no difference in the charge on said charge storage device between the beginning and end of that pulse interval; and c) if a pulse of said first pulse signal occurs during the negative half cycle of the respective pulse interval, said charge storage device is discharge from the beginning of the positive half cycle until the beginning of the negative half cycle of that respective pulse interval, then said charge storage device is charged at a first rate until the occurrence of that pulse of the first pulse signal and then is charged at a second rate until the end of the negative half cycle of that pulse interval, in which a difference in charge between the beginning and end of that pulse interval represents a difference in phase between that pulse of the first pulse signal and the next succeeding pulse of the second pulse signal. Apparatus, according to any preceding claim, characterised in that said output signal has a correct value at the end of each pulse interval of the second pulse signal and the integral of the output signal over a pulse interval of the second pulse signal may be incorrect for a given application of the apparatus. Apparatus, according any preceding claim characterised in that said charge storage means comprises a capacitor (44). Apparatus, according to any preceding claim, characterised in that said charging means comprises: (a) a plurality of current sources (CS1, CS2, CS3) for supplying to and withdrawing current from said charge storage means; and (b) a plurality of switch means (SW1, SW2, SW3), responsive to said control signals, for coupling and decoupling said plurality of current sources (CS1, CS2, CS3) to and from said charge storage means. Apparatus, according to any preceding claim, characterised by correction means (36) for providing for a correction of the integral of the output signal over each pulse interval of the second signal. Apparatus, according to claim 8, characterised in that; said control means is arranged to generate a second set of control signals (34-1,2,3), and further characterised by second charge storage means (52) and second means (SW 4,5,6, CS 4,5,6 ) to vary the charge level therein in response to said second set of signals to produce a correction signal for said output signal. Apparatus, as claimed in claim 9, characterised in that summing means is provided to add the correction signal to the output signal. Apparatus, according to any one of claims 8 to 10, characterised in that said second charging means operates as follows; (a) if a pulse of said first pulse signal occurs during the positive half cycle of the respective pulse interval, said second charge storage means is charged from the beginning of the positive half cycle of that pulse interval until the occurrence of that pulse, then the increased charge is retained until the end of the positive half cycle of that pulse interval and then the second charge storage means is discharged from the beginning of the negative half cycle of that pulse interval until no later than the end of the negative half cycle of that pulse interval; (b) if a pulse of said first pulse signal does not occur during the respective pulse interval, said second charge storage means is charged from the beginning of the positive half cycle of that pulse interval until the beginning of the negative half cycle of that pulse interval, and then said second charge storage means is discharged from the beginning of the negative half cycle of that pulse interval until the end of the negative half cycle of that pulse interval and (c) if a pulse of said first pulse signal occurs during the negative half cycle of the respective pulse interval, said second charge storage device is charged from the beginning of the positive half cycle of that pulse interval, until the end of the positive half cycle of that pulse interval, then discharged from the beginning of the negative half cycle of that pulse interval until the occurrence of a further pulse of the first pulse signal and then the remaining charge is retained from the occurrence of that further pulse signal until the end of the negative half cycle of that pulse interval. An apparatus according to claim 11 characterised in that the charge in said second charge storage means is equal to the charge in said first storage means at the beginning of and the end of each pulse interval of the second pulse signal.

Inventors: ADAMS, NEIL RONALD
Applicants: ADVANCED MICRO DEVICES, INC.
Application year: 1985
Main classification: G01R25
IPC codes: H03L7, H03K5, G01R25