Semiconductor integrated circuit with redundant circuit replacement

Abstract: A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit (24) for detecting coincidence between data read from the memory unit (21) and a received input address (Ao, An). Data produced from the comparison by the comparison unit is delivered through an external connection terminal (7).

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit having memory cells. The integrated circuit according to the present invention is used for a memory device having a redundant circuit portion for replacing failed circuits. 2. Description of the Related Art In general, an integrated circuit device for a semiconductor memory is provided with "redundant-bit" type memory cells in addition to the usually used memory cells. These are used to replace failed memory cells or even to replace an entire bit line containing failed memory cells, in the latter case by a redundant bit line containing redundant memory cells. This increases the yield of the products in the manufacture of integrated circuits. In such an integrated circuit, read-only memories (ROM's) are provided for storing the addresses of the failed memory cells. When an input address signal coincides with the address of a failed memory cell stored in the ROM's, the circuit is switched to access a redundant memory cell instead of the failed memory cell. Accordingly, quick and correct detection of the written state of the ROM's is important. However, 2 n+1 cycles are usually required for detecting the written state of the ROM's. Hence, a very long time is required for testing an integrated circuit. Also, when several fuses are used for each bit in the ROM's, it is impossible to determine the blow-out state of each of the fuses, although the output state of the ROM's can be determined. This is undesirable and causes problems in an integrated circuit device for a semiconductor memory. An example of a semiconductor memory with a redundant element identification circuit is disclosed in WO-A-82 02793. According to this prior art, a redundant decoder is provided via a signal line. The redundant decoder is programmed with the addresses of the defective memory cells so as to select a predetermined redundant memory cell when a received address corresponds to a defective memory cell. A test circuit is provided to indicate, by means of an output signal, when the decoder has selected a redundant memory cell. The output signal is applied to an indicator circuit which is enabled in a test mode by an abnormal condition detector. The output of that detector is then applied to an external pin. Another prior art semiconductor memory having a built-in test circuit is disclosed in EP-A-0086310. The test circuit is based on a series connected transistor and diode between a voltage source and an input connection. A capacitor is connected between the gate of the transistor and the input part. The test circuit discriminates the signal level of an internal node to be inspected as a function of the flow or non flow of a current from the input connection when it is supplied with a particular signal having a voltage level higher than the power source level. SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved integrated circuit having memory cells, enabling quick and correct detection of the written state of the memory circuit in which the address information of the failed circuit portions is stored, and easy, reliable inspection of the integrated circuit having regular memory cells and redundant circuits without providing an additional external connection terminal of the integrated circuit. It is thus another object of the present invention to reduce the time required for the testing of an integrated circuit having regular memory cells and redundant circuits. It is still another object of the present invention to enable detection of the blow-out state of each of the plurality of fuses used in the memory cells in the integrated circuit. According to the present invention, these objects are met by the semiconductor integrated circuit of claim 1. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, Fig. 1 is block diagram of a prior art integrated circuit; Figs. 2 and 3 show examples of the structure of the coincidence detection circuit used in the circuit shown in Fig. 1; Fig. 4 is a block diagram of an integrated circuit according to an embodiment of the present invention; and Figs. 5 to 9 show examples of the structure of a coincidence detection circuit used in the circuit shown in Fig. 4. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a preferred embodiment, an example of the prior art integrated circuit will be described with reference to Figs. 1, 2, and 3. The device of Fig. 1 includes coincidence detection circuits 2, 2, ..., corresponding to the number of bits of the input address signals A 0 , A 1 , ... A n , and a depletion type transistor 32 as a load transistor. Non-inverted and inverted address signals A 0 , A 0 , A 1 , A 1 , ... A n and A n are supplied to the coincidence detection circuits 2, 2 ... Each of the coincidence detection circuits carries out a comparison between the input address signal and the stored address signal in a ROM in the coincidence detection circuit. When coincidence is attained, the impedance between the voltage source V cc and a control line 31 (N 1 ) becomes HIGH. Conversely, when coincidence is not attained, the impedance between the voltage source V cc and the control line 31 (N 1 ) becomes LOW. Hence, when all of the coincidence detection circuits indicate coincidence, the potential of the control line 31 (N 1 ) becomes HIGH, while when one or more of the coincidence detection circuits do not indicate coincidence, the potential of the control line 31 (N 1 ) becomes LOW. The ROM's in the coincidence detection circuits store the address of failed memory cell. When the input address signal coincides with the address of the failed memory cell stored in the ROM's, the potential of the control line 31 (N 1 ) becomes HIGH. On the basis of this fact, when the potential of the control line 31 (N 1 ) is HIGH, a redundant memory cell is accessed instead of the failed memory cell. Such a circuit operation enables automatic switching from the failed memory cell to a redundant memory cell. An example of the structure of each of the coincidence detection circuits 2, 2, ... is shown in Fig. 2. In the circuit of Fig. 2, a fuse 211 and a transistor 213 constitute a fuse blow-out type ROM. One bit of the address information of a failed memory cell is stored in this ROM. Transistors 231 and 232 constitute an inverter circuit. Transistors 241 to 244 constitute a comparison circuit in the form of an exclusive OR gate circuit. The series-connected transistors 241 and 242 and the series-connected transistors 243 and 244 are connected between the control line 31 (N 1 ) and the voltage source line V ss . The gate of the transistor 241 is connected to the output node N 2 of the inverter circuit (231, 232). The gate of the transistor 243 is connected to the output node N 3 of the fuse blow-out type ROM (211, 213). The non-inverted address signal A is supplied to the gate of the transistor 242, while the inverted address signal A the supplied to the gate of the transistor 244. In the circuit of Fig. 2, if the fuse 211 is blown, the potential of the output node N 3 of the ROM is LOW, and that of the output node N 2 of the inverter circuit is HIGH. Hence, the transistor 243 becomes OFF and the transistor 241 becomes ON. Under such a state, when the address signal A is LOW ("0"), the transistor 243 is in the OFF state and the transistor 242 becomes OFF. Hence, the potential of the control line 31 (N 1 ) becomes HIGH. When the address signal A is HIGH ("1"), the transistor 242 becomes ON and, hence, the potential of the control line31 (N 1 ) becomes LOW. In the circuit of Fig. 2, if the fuse is not blown, the potential of the node N 3 is HIGH, and the potential of the node N 2 is LOW. Hence , the transistor 243 becomes ON and the transistor 241 becomes OFF. Under such a state, when the address signal A is LOW while the inverted address signal A is HIGH, the potential of the control line 31 (N 1 ) becomes LOW by the operation of the transistors 243 and 244. When the address signal A is HIGH while the inverted address signal A is LOW, the potential of the control line 31 (N 1 ) becomes HIGH. Thus, in the circuit of Fig. 2, the fuse blow-put type ROM (211, 213) stores the address data "0" by the blown state of the fuse 211 and stores the address data "1" by the non-blown state of the fuse 211. Using such stored data, when an input address signal A coincides with the stored data, the potential of the control line 31 (N 1 ) becomes HIGH. Figure 3 shows another example of the structure of the coincidence detection circuits 2, 2, ... shown in Fig. 1. The ROM portion of the coincidence detection circuit of Fig. 3 includes a series-connected fuse 211 and a depletion type transistor 213, a series-connected fuse 212 and a depletion type transistor 214, and a NAND gate circuit consisting of a series-connected depletion type transistor 221, enhancement type transistor 222, and enhancement type transistor 223. When one or more of the fuses 211 and 212 is blown, one of the transistors 222 and 223 is in the OFF state. Hence, the potential of the node N 3 is HIGH. When neither the fuse 211 nor the fuse 212 is blown, both the transistors 222 and 223 are ON and, hence, the potential of the node N 3 is LOW. Thus, the reliability of the stored data in the ROM portion of the circuit of Fig. 3 is higher than that of the circuit of Fig. 2. In order to test the data written-in state of the ROM portions of the coincidence detection circuits shown in Fig. 2 and Fig. 3 corresponding to the bits of the address signal, the input address signals A 0 , A 1 , ... A n are chanced successively from "0, 0, ... 0" to "1, 1, ... 1", and the values of the address signals which make the potential of the control line 31 (N 1 ) HIGH is inspected. The values of the address signals A 0 , A 1 ... A n which make the potential of the control line 13 (N 1 ) HIGH indicate the address of the failed portion. A semiconductor integrated circuit according to an embodiment of the present invention is illustrated in Fig. 4. The circuit of Fig. 4 includes coincidence detection circuits 2, 2, ..., a load transistor 32, an output circuit consisting of transistors 61 and 62, and an external connection terminal 7. The transistor 32 is connected between a voltage source V cc and the control line 31 (N 1 ) and is operated as a pull-up circuit or a load circuit. The transistors 61 and 62 are connected in series between the voltage source V ss and an external connection terminal 7. The gate of the transistor 61 is connected with the control line 41 (N 21 ) while the gate of the transistor 62 is connected with the junction of the transistors 61 and 62. The external connection terminal 7 may be used also for a terminal for another signal. Non-inverted and inverted signals A 0 , A 0 , A 1 , A 1 , ... A n , A n are supplied to the coincidence detection circuits 2, 2, ... in the circuit of Fig. 4. The input address signals are compared with the address signals stored in the ROM's in the coincidence detection circuits. When the compared signals coincide, the impedance between the output terminal of the coincidence detection circuit connected with the control line 31 (N 1 ) and the voltage source V ss becomes HIGH. When the compared signals do not coincide, the above-mentioned impedance becomes LOW. Thus, when all of the outputs of the coincidence detection circuits 2, 2, ... indicate coincidence, the potential of the control line 31 (N 1 ) becomes HIGH. When one or more of the outputs of the coincidence detection circuits 2, 2, ... indicates non-coincidence, the potential of the control line 31 (N 1 ) becomes LOW. That is, when the address of the failed memory cell stored in the ROM's in the coincidence detection circuits coincides with the input signal address, the potential of the control line becomes HIGH. Based on this operation, a redundant memory cell is accessed instead of a failed memory cell only when the potential of the control line 31 (N 1 ) is HIGH. Such an arrangement allows endless automatic switching from the failed memory cell to the redundant memory cell. Various tests of the integrated circuit can be carried out conveniently by using the information concerning failed bits stored in the ROM's in the coincidence detection circuits. The detection of the information stored in the ROM's is carried out by inputting a sequence of varying addresses A 0 , A 1 ... A n and detecting sequentially the potentials of the external connection terminal accordingly. When the input signal address coincides with the address stored in the ROM's, the potential of the control line 31 (N 1 ) becomes approximately V cc , as described above. The above description assumes storage of only a single failure address. When plural failure addresses exist, a plurality of the circuits shown in Fig. 4 are used. The semiconductor integrated circuit further provides a status detection function indicating the written state of one of a plurality of memory cells in the memory from a terminal connected commonly to the plural memory cells, by supplying a specific address signal corresponding to that one memory cell. Each of the coincidence detection circuits 2, 2,... has two output terminals, one connected with a control line 31 (N 1 ), the other connected with a detection line 41 (N 21 ). When the detection line 41 (N 21 ) is active, its potential becomes approximately V cc , as described above. Under this condition, the potential of the external connection terminal 7 is reduced gradually from V ss . When the potential reaches the value "V ss - V th ", where V th is the threshold voltage of each of the transistors 61 and 62, the current starts to flow through the voltage source V ss , the transistor 61, the transistor 62, and the external connection terminal 7. When the input signal address does not coincide with the address stored in the ROM's, the potential of the control line 41 (N 21 ) becomes LOW, that is, approximately V ss . Under this condition, the potential of the external connection terminal 7 is reduced gradually from V ss . When the potential reaches the value "V ss - 2V th ", the current starts to flow. Thus, from the potential of the external connection terminal 7, when the current starts to flow through the external connection terminal, it is possible to detect the coincidence between the input signal address and the address stored in the ROM's and to confirm the address of the failed portion of the circuit. The indication of a resistor 8 and a voltage source V x , for example -3V, in broken lines is for explaining how current flows through the external connection terminal 7 after application of a voltage V x through the resistor 8 to the external connection terminal 7. The coincidence detection circuit shown in Fig. 2 is used for each of the coincidence detection circuits 2, 2,... in the circuit shown in Fig. 4. Each of the coincidence detection circuits 2,2, ... includes a memory portion 21, a comparison portion 24, and a status detection portion 25. The structure of the coincidence detection circuit 2 is illustrated in Fig. 5. The status detection portion 25 includes transistors 2501 and 2502, which are connected in series between a detection line 41 (N 21 ) and a voltage source V ss . The gate of the transistor 2501 is connected to a node N 3 in the ROM 21. The gate of the transistor 2502 receives the input signal A. In the circuit of Fig. 5, the impedance between the control line 31 (N 1 ) and the voltage source V ss is HIGH when the potentials of the nodes N 3 and N 2 conform to the input signals A and A , while the impedance is LOW when the potentials of the nodes N 3 and N 2 do not conform to the input signals A and A . In the circuit of Fig. 5, the potential of the input signal A is made HIGH in order to detect the storage state of the ROM 21, that is, the state of the fuse 211. When the potential of the input signal A is HIGH, the transistor 2502 becomes ON, and the information of the state of the fuse 211 is output to the detection line 41 (N 21 ). That is, when the fuse 211 is blown, the potential of the node N 3 is LOW, and the transistor 2501 becomes OFF. Accordingly, the impedance between the detection line 41 (N 21 ) and the voltage source V ss is HIGH. Hence, the potential of the detection line 41 (N 21 ) becomes HIGH due to the operation of the depletion type transistor 42 (Fig. 4) connected between the detection line 41 (N 21 ) and the voltage source V cc , so that the blown state of the fuse 211 is detected. In this case, it should be noted that it is required that the potential of just one bit of the address signal be made HIGH and the potentials of all of the other bits of the address signal be made LOW. When the fuse 211 is not blown, the potential of the node N 3 becomes HIGH, and the transistor 2501 becomes ON. Accordingly, the potential of the detection line 41 (N 21 ) becomes LOW. Another example of the structure of the coincidence detection circuit is shown in Fig. 6. The circuit of Fig. 6 is similar to the circuit of Fig. 3, except that the status detection circuit 25 consisting of transistors 2503 to 2507 is added. A non-inverted selection signal A n+1 and an inverted selection signal A n+1 are applied to the gates of the transistors 2505 and 2507. A non-inverted address signal A is applied to the gate of the transistor 2503. In order to detect the state of the fuse 211, the address signal A and the non-inverted signal A n+1 are made HIGH. Hence, the transistors 2503 and 2505 becomes ON. Under this condition, when the transistor 2504 is turned on or off corresponding to the potential of the node N 4 , the potential of the detection line 41 (N 21 ) becomes LOW or HIGH accordingly. Hence, when the fuse 211 is blown, the potential of the node N 4 is LOW, the transistor 2504 is OFF, and, accordingly, the potential of the detection line 41 (N 21 ) becomes LOW. When the fuse 211 is not blown, the potential of the node N 4 is HIGH, the transistor 2504 is ON, and, accordingly, the potential of the detection line 41 (N 21 ) becomes HIGH. Thus, by making both the address signal A and the selection signal A n+1 HIGH, it is possible to detect the state of the fuse 211. Similarly, by making the address signal A HIGH and the selection signal A n+1 LOW, that is, the selection signal A n+1 HIGH, the information of the state of the fuse 212 is output to the detection line 41 (N 21 ). Thus, in the circuit of Fig. 6, the state of each of the fuses 211 and 212 can be detected separately. The circuit of Fig. 6 is particularly useful for the case where the memory cell matrix is divided by rows or by columns to be divided into a plurality of blocks in which the switching to the redundant circuit is carried out simultaneously in parallel with regard to the plurality of blocks. Another example of the structure of the coincidence detection circuit is shown in Fig. 7. The circuit of Fig. 7 includes a status detection circuit 25, consisting of the transistors 2508 to 2511, and detection lines 41 (N 21 ) and 51 (N 31 ). Series-connected transistors 2508 and 2509 are connected between the detection line 41 (N 21 ) and the voltage source V ss , while series-connected transistors 2510 and 2511 are connected between the detection line 51 (N 31 ) and the voltage source V ss . The gates of the transistors 2508 and 2510 are connected to the nodes N 4 and N 5 . The gates of the transistors 2509 and 2511 receive the address signal A. In the circuit of Fig. 7, the transistors 2509 and 2511 are caused to be ON by making the address signal A high. Under this condition, when the fuse 211 is blown, the potential of the node N 4 is LOW, the transistor 2508 is OFF, and, accordingly, the potential of the detection line 41 (N 21 ) becomes HIGH. When the fuse 211 is not blown, the potential of the node N 4 is HIGH, the transistor 2508 is ON, and, accordingly, the potential of the detection line 41 (N 21 ) becomes LOW. Similarly, when the fuse 212 is blown, the transistor 2510 is OFF, and, accordingly, the potential of the detection line 51 (N 31 ) becomes HIGH. When the fuse 212 is not blown, the transistor 2510 is ON, and, accordingly, the potential of the detection line 51 (N 31 ) becomes LOW. Thus, in the circuit of Fig. 7, by making the address signal A HIGH, information on the states of the fuses 211 and 212 is output to the detection lines 41 (N 21 ) and 51 (N 31 ). In the above described embodiments, the address signal is increased successively by one bit for detecting the state of the ROM corresponding to each of the bits of the address signal. However, in the circuit of Fig. 5, when an inverted address signal A , instead of a non-inverted address signal A, is supplied to the gate of the transistor 2502, it is possible to detect the state of the fuse 211 by making the address signal A LOW. By making the address signal applied to the transistor 2502 to be, bit by bit, a non-inverted address signal or an inverted address signal, it is possible to select any pattern of address signals for detecting the written state of the ROM. An example of the above-described selection of an arbitrary pattern of the address signal is shown in the following tables (A) and (B). Table (A) indicates the address signal supplied to the gate of the transistor 2502. Table (B) indicates the address pattern for detecting the state of the ROM. Address signal A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 Address signal supplied to gate of 2502 A 0 A 1 A 2 A 3 A 4 A 5 A 6 MA 7 Address signal A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 No bits are selected 0 0 1 1 1 0 0 0 A 0 is selected 1 0 1 1 1 0 0 0 A 1 is selected 0 1 1 1 1 0 0 0 · · · A 7 is selected 0 0 1 1 1 0 0 1 Another example of the structure of the coincidence detection circuit is shown in Fig. 8. The circuit of Fig. 8 includes a status detection circuit 25 consisting of transistors 2512, 2521, 2522, ... 252k. The gate of the transistor 2512 receives the potential of the node N 3 which represent the state of the fuse 211. The gates of the transistors 2521, 2522, ... 252k receive either one of the non-inverted signals A (A 0 , A 1 , ... A n ) or one of the inverted signals A ( A 0 , A 1 , ... A n ) of the corresponding bit of the input address. The series-connected transistors 2521, 2522, ... 252k become ON when the sequence of the signals supplied to the gates of the transistors 2521, 2522, ... 252k corresponds to a specific address. When the series connected transistors 2521, 2522, ... 252k are ON, the information of the state of the fuse 211, which is represented by the ON or OFF state of the transistor 2512, is output to the detection line 41 (N 21 ). In the circuit of Fig. 8, 2 k+1 status detection circuits can be realized so that the detection of the states of 2 k+1 fuses can be carried out. A further example of the structure of the coincidence detection circuit is shown in Fig. 9. The circuit of Fig. 9 includes a status detection circuit 25 consisting of transistors 2531, 2532, 2541a, 2541b, 2542, 2543, ... 254k. The operation of the circuit of Fig. 9 will be apparent from the operations of the circuit of Fig. 6 and the circuit of Fig. 8.

Claims: A semiconductor integrated circuit having first memory means comprising first memory cells and a redundant circuit portion for replacing failed first memory cells, comprising : (a) coincidence detection circuit means (2) receiving input addresses and including (a1) second memory means (21) comprising a plurality of second memory cells for storing address information of a failed circuit portion of first memory cells for replacing the failed circuit portion by a redundant circuit portion; (a2) comparison means (24) for detecting coincidences between data stored in said second memory means and a received input address and indicating a detected coincidence on a first line connected to said comparison means; (a3) status detection means (25) for delivering a signal on a second line connected to said status detection means for indicating the written state of one of the plurality of second memory cells (21) in said second memory means by supplying a specific address signal corresponding to said one second memory cell; (b) delivery means (8, 31, 32, 61, 62) connected between the comparison means (24) and an external connection terminal for delivering the signal obtained from said first line by said comparison means through said external connection terminal (7) whereby the result of the comparison is indicated by the current passing through said external terminal when a predetermined voltage outside the usual operating range is present thereat. A circuit according to claim 1, wherein the delivery means comprise two transistors (61, 62) connected in series between said external terminal (7) and a voltage source (Vss), the gate of the transistor (61) which is connected to said voltage source being connected to an output line (31) of the comparison means (24), while the gate of the other transistor (62) is connected to the junction of the two transistors (61, 62). A circuit according to claim 1, wherein said comparison means (24) detects coincidence with regard to all the bits of address data (A 0 , A 0 , A 1 , A 1 , ..., A n , A n ). A circuit according to claim 1, wherein each of said memory cells comprises a fuse (211) and a transistor (213). A circuit according to claim 1, wherein said status detection means comprises transistors (61, 62) connected in series between a detection line (31) and a voltage source. A circuit according to claim 1, wherein said status detection means comprises a series connection of a transistor (2503) and parallel connected series connections of transistors, connected between a detection line (41) and a voltage source (Vss). A circuit according to claim 1, wherein said status detection means comprises transistors (2508, 2509) connected in series between a first detection line (41) and a voltage source (Vss) and transistors connected in series between a second detection line (51) and a voltage source (Vss). A circuit according to claim 1, wherein said status detection means comprises a series connection of series connected transistors and parallel connected series connections of transistors, connected between a detection line and a voltage source.

Inventors: FUJII YASUHIRO, HORII TAKASHI, NAKANO MASAO, NAKANO TOMIO, OGAWA JUNJI, SATO KIMIAKI, TAKEMAE YOSHIHIRO, TATEMATSU TAKEO, TSUGE NORIHISA, FUJII, YASUHIRO, HORII, TAKASHI, NAKANO, MASAO, NAKANO, TOMIO, OGAWA, JUNJI, SATO, KIMIAKI, TAKEMAE, YOSHIHIRO, TATEMATSU, TAKEO, TSUGE, NORIHISA, TATEMATSU, TAKEO ESUPERANSA DAI-3
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1985
Main classification: G06F11
IPC codes: G11C29