TWO STAGE DECODER CIRCUIT

Abstract: A two-state decoder circuit including a first-stage decoder circuit (7-1 to 8-2, 9, 10, 11), for decoding upper bits (A₀ to A₃) of an input signal, and a second-stage decoder circuit (4, 5, 6), which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits (A₄ to A₇) of the input signal. The first-stage decoder circuit is formed by a threshold-operation type logic circuit (11) which carries out selection or non-selection by comparing the input signal (9a, 10a) with a predetermined threshold level (VR), and the second-stage decoder circuit is formed by a diode-matrix circuit (D₅ to D₈).

Description: The present invention relates to a two-stage decoder circuit as described in the preamble of claim 1 and as known from EP-A-0 024 894, Fig.5. A multistage decoder circuit is often used as the decoder circuit in a semiconductor integrated circuit (IC) of a semiconductor memory device. Such a multistage decoder circuit can be operated by a small electric power and requires only a few circuit elements. Multistage decoder circuits, however, suffer from double selection and other problems due to the rise of the non-selected output when the address is changed. Therefore, measures must be taken to eliminate these problems. An embodiment of the present invention can provide a two-stage decoder circuit which is substantially free from the problems of double selection, etc. An embodiment of the present invention can provide a two-stage decoder circuit which offers improved reliability of the IC device. An embodiment of the present invention can provide a two-stage decoder circuit which substantially does not suffer from a rise in the decoder output when the address is changed, in which malfunctions caused by address exchange are eliminated or mitigated. An embodiment of the present invention provides a two-stage decoder circuit including a first-stage decoder circuit, for decoding upper bits of an input signal, and a second-stage decoder circuit, which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits of the input signal; the first-stage decoder circuit being formed by a threshold-operation type logic circuit which carries out selection or non-selection by comparing the input signal with a predetermined threshold level; the second-stage decoder being formed by a so-called diode-matrix circuit. Reference is made, by way of example to the accompanying drawings, in which :- Fig. 1 is a block diagram of a conventional two-stage decoder circuit; Fig. 2 is a waveform diagram showing a rise of the output signal in the two-stage decoder circuit shown in Fig. 1; Fig. 3 is a block diagram of one embodiment of a two-stage decoder circuit according to the present invention; Fig. 4 is a block diagram of the entire system of the two-stage decoder circuit shown in Fig. 3; Fig. 5 is detailed circuit diagram of an address buffer used in the two-stage decoder circuit shown in Fig. 3; Fig. 6 is a waveform diagram of the output signal in the two-stage decoder circuit shown in Fig. 3; Fig. 7 is a block diagram of a memory device using the two-stage decoder circuit shown in Fig. 3; and Fig. 8 is a block diagram of one example of the memory cell used in the memory device shown in Fig. 7. Figure 1 shows an example of a two-stage decoder circuit used in a conventional IC device. In the two-stage decoder circuit shown in Fig. 1, a first-stage decoder circuit is formed by an address buffer 1 for receiving a one-bit address signal A₀ , etc, address wires 2 formed by a plurality of signal wires, and AND gate. 3. A second-stage decoder circuit includes an address buffer 4, address wires 5 formed by a plurality of signal wires, and AND gate 6. The address buffer 1 is formed by a differential amplifier including transistors Q₁ , Q₂ , the emitters of which are connected with each other; a constant current circuit I₁ connected between the common emitters of these transistors Q₁ , Q₂ and a source V DD ; resistors R₂ , R₃ , one terminals of each being connected to the collectors of the transistors Q₁ , Q₂; and a resistor R₁ connected between the connected other ends of the resistors R₂ , R₃ and a source V CC . The address wires 2 include, for example,. four pairs of signal wires with an address buffer connected to each pair. In Fig. 1, however, only one address buffer is shown. The AND gate 3 includes diodes D₁ , D₂ , D₃ , D₄ , a resistor R₄ , and a transistor Q₃ , which are connected between a commonly connected anode of these diodes and the source V CC . The address buffer 4 in the second-stage address buffer has the same circuit construction as the address buffer 1 and has transistors Q₄ , Q₅ , a constant current circuit I₂ , and resistors R₅ , R₆ , R₇. The address wires 5 also include four pairs of signal wires, with an address buffer 4, etc, connected to each pair of signal wires. In Fig. 1, however, only one address buffer is shown. The AND gate 6 includes diodes D₅ , D₆ , D₇ , D₈; a resistor R₈ connected between commonly connected anodes of these diodes and the emitter of the transistor Q₃; a transistor Q₆ having its collector connected to the emitter of the transistor Q₃ and its base connected to commonly connected anodes of diodes D₅ , D₆ , D₇ , D₈; and a constant current circuit I₃ connected between the transistor Q₆ and the source V DD . In the circuit shown in Fig. 1, the input of the address buffer 1 of the first-stage decoder circuit, that is, the base of the transistor Q₁ , is supplied with one bit of the address signal. The base of another transistor Q₂ is supplied with a reference voltage V R . An inverted address signal A ₀ and non-inverted signal A₀ are output at the collectors of each transistor Q₁ and Q₂ and are supplied to one pair of the signal wires of the address wires 2. The other pairs of signal wires of the address wires 2 receive an inverted and non-inverted signal of other bits of address signals from similar address buffers (not shown). Cathodes of the diodes D₁ , D₂ , D₃ , D₄ are respectively connected to one of the signal wires in a corresponding pair of signal wires. The address buffer 4, etc., in the second-stage decoder circuit are supplied with one bit of the address signal and supply an inverted and a non-inverted address signal to pairs of the signal wires 2 of the address wires 5. Further, the output of the first-stage decoder circuit, that is, the emitter of the transistor Q₃ , is connected with a plurality of second-stage decoder circuits. In the circuit shown in Fig. 1, when the cathodes of the diodes D₁ , D₂ , D₃ , D₄ forming the AND gate 3 of the first-stage decoder circuit are all high level, the output of the AND gate 3 becomes high level, so that the emitter of the transistor Q₃ becomes high level. Therefore, at this time, when the cathodes of the diodes D₅, D₆ , D₇ , D₈ of the AND gate 6 of the second stage decoder are all high level, the output of the AND gate 6 becomes high level, and the emitter of the transistor Q₆ , that is, the output signal OUT, becomes high level, so that the word lines, etc, are selected. Conversely, when the output of the first-stage decoder circuit is low level, even if the cathodes of the diodes D₅ , D₆ , D₇ , D₈ of the AND gate 6 of the second-stage decoder circuit are all high level, the output OUT becomes low level, that is, the non-selected stage. Further, even if the output of the first-stage decoder circuit is high level, when the output of the AND gate of the second-stage decoder circuit is low level, the output OUT becomes low level, and also in this case, becomes the non-selected state. Therefore, one merit of this find of two-stage decoder is that the power consumption is very small. This because, if the first-stage decoder output is low, none of the second-stage decoders connected to the nonselected first-stage decoders consume power. Only the nonselected second-stage decoders connected to the selected first-stage decoder consume power. Consequently, at any time, only a single group of second-stage decoders connected to the selected first-stage decoder consumes power. Now, in the conventional two-stage decoder circuit mentioned above, the first-stage decoder circuit and the second-stage decoder circuit are all a matrix type. Therefore, there is the drawback that the output rises when the address is changed. That is, as shown by the dotted lines in Fig. 2, for example, in the transient state such as when the address signal Am falls and the address signal An rises, both address signals become the intermediate level. At such a time, when the address is changed, the output of the AND gate, which is in the non-selected state before and after the change of the address, rises as shown by the solid line in Fig. 2. In the circuit shown in Fig. 1, as the first-stage decoder circuit and the second-stage decoder circuit have AND gates using diodes, that is, are formed as the matrix type, the rise in the first-stage decoder circuit and the second-stage decoder circuit are superposed, so that a rise is caused at the output OUT. This is because the output level of the diode matrix type AND gate is set at V F (forward voltage of the diode) from the lowest input level at the cathode of the diode. Therefore, in the conventional circuit shown in Fig. 1, double selection, etc., is caused when the address is changed. Figure 3 shows the construction of a two-stage decoder circuit used in an IC device according to one embodiment of the present invention. In the two-stage decoder circuit shown in Fig. 3, a first-stage decoder circuit includes threshold-operation type logic circuits 11, which are different from the diode-matrix type logic circuit, in addition to the address buffers 7-1, 7-2, and 8-1, 8-2: and address wires 9 and 10 having a plurality of, for example four, signal wires. The address buffers 7-1, 7-2, 8-1, 8-2 in the first-stage decoder circuit receive as input one bit of address signals A₀ , A₁ , A₂ , A₃. Each address buffer forms the inverted signal and the non-inverted signal of these address signals and supplies them to the signal wires of the address wires 9. The logic circuit 11 includes transistors Q₇ , Q₈ , Q₉ each having commonly connected emitters, an emitter-follower transistor Q₁₀ having a base which is connected to the commonly connected collectors of the transistors Q₇ , Q₈ , a load resistor R₉ , and a constant current source I₄. The bases of the transistors Q₇ , Q₈ are respectively connected to one signal line of the address wires 9 and 10. Therefore, for example, 16 logic circuits the same as the logic circuit 11 are provided, as shown in Fig. 4. In the circuit shown in Fig. 3, the construction of the second-stage decoder circuit is the same as the circuit shown in Fig. 1, the same constituent parts shown by the same reference symbols. Sixteen such AND gate 6, etc., of the second-stage decoder circuit are connected to the output of the first-stage decoder circuit, for example. Figure 4 shows the overall system of the two-stage decoder circuit, wherein the same symbols as in Fig. 3 show the same elements. Further, in Fig. 4, 11-0, 11-1, ... , 11-15 designate logic circuits corresponding to 11 in Fig. 3; 6-0, ... , 6-15 designate AND gates corresponding to 6 in Fig. 3; and 4-1, ... , 4-4 designate address buffers corresponding to 4 shown in Fig. 3. Figure 5 shows a detailed construction of one of the address buffers 7-1, 7-2, 8-1, 8-2 in the circuit shown in Fig. 3. The address buffer shown in Fig. 5 includes a differential amplifier circuit formed by transistors Q₁₁ , Q₁₂ having commonly connected emitters, resistors R₁₀ , R₁₁ , R₁₂ , and a constant current circuit I₅ and includes multi-emitter transistors Q₁₃ and Q₁₄ which form an emitter-follower circuit connected to the collectors of the transistors Q₁₁ and Q₁₂ of the differential amplifier circuit. In the address buffer shown in Fig. 5, one bit address signal Ai is supplied to the base of the transistor Q₁₁ in the differential amplifier circuit. An inverted and a non-inverted address signal are obtained at the collectors of the transistors Q₁₁ and Q₁₂. These inverted and non-inverted address signals are supplied, via the emitter-follower circuit formed by the transistors Q₁₃ and Q₁₄ , to each signal wire forming the address wires mentioned above. One emitter of each multi-emitter transistor Q₁₃ and Q₁₄ in one address buffer is connected to one signal wire, respectively. Therefore, each signal wire in the first-stage decoder circuit in the circuit shown in Fig. 3 is connected with the same number of emitters as address buffers, so that a so-called wired logic type (OR logic type) circuit is formed. The operation of the two-stage decoder circuit having the above construction will be explained below. In Fig. 3, when one or more of the signals supplied to a signal wire from the address buffers 7-1, 7-2 is high level, the potential of the signal wire of, for example, the address wires 9, becomes high level. Only when both (all) the signals supplied from the address buffers 7-1, 7-2 to a signal wire are low level does it become low level. Therefore, the potential of the signal wire 9a connected to the base of the transistor Q₇ of the logic circuit 11 becomes low level only when the address signal A₀ is high level (for example, "1") and the address signal A₁ is low level (for example, "0"). Further, the potential of the signal wire 10a connected to the base of the transistor Q₈ of each signal wire of the address wires 10 becomes low level only when both the address signal A₂ is low level and the address signal A₃ is low level. The logic circuit 11 operates as a NAND gate. Only when the potentials of the signal wires 9a and 10a are both low level are the transistors Q₇ and Q₈ cut off and a high level signal output from the emitter of the transistor Q₁₀. When the input address signals A₀ , A₁ , A₂ , A₃ are in the other state mentioned above, one or more of the signal wires 9a and 10a becomes high level and one or more of the transistors Q₇ and Q₈ becomes on, so that the emitter of the transistor Q₁₀ becomes low level. In the above-mentioned operation, if, when the output of the first-stage decoder circuit becomes high level, all inputs of the AND gates of the second-stage decoder circuit become high level, the output OUT becomes high level as mentioned previously and the word line, etc., connected to the output are selected. Now, in the first-stage decoder circuit, for example, only one of four signal wires constituting the address wires 9 is low level; the other three are high level. Even when the address is changed, the potential of only two signal wires at maximum changes; the potential of the other signal wires are maintained at the high level state. Further, as the logic circuit 11 is a threshold-value-operated type NAND circuit, in which the base potential of the transistors Q₇ and Q₈ is operated by the base potential of the transistor Q₉ , that is, the reference potential V R as the threshold value, even when the potential of the signal wire 9a changes from low level to high level and the potential of the signal wire 10a changes from high level to low level, the rise of the output signal can be prevented by setting the reference potential V R at a suitable value as shown in Fig. 6. That is, the collector level of the transistor Q₇ , Q₈ does not follow the input levels 9a, 10a like the diode-matrix type in Fig. 1. The collector level changes only when all of the input levels become equal or higher than the reference potential V R . Such a condition may exist for a short time at a decoder which changes from the non-selected to selected state. Further, in a majority of the plurality of the first stage decoder circuits forming the two-stage decoder circuits, as the potential of the signal wires connected to the input of the logic circuit is held at high level as mentioned above, a majority of the outputs of the first-stage decoder circuits is maintained at low level. Therefore, no rise of the output occurs in such decoder circuits. In summary, at the present invention, since the first-stage decoder is a threshold operation type logic circuit, the problem of the rise of the output is almost completely resolved. Also, since the second-stage decoders are still diode-matrix types connected to the first-stage decoder, the small power consumption explained before is still maintained. Figure 7 shows an outline of a semiconductor memory device using above-mentioned two-stage decoder circuit. The memory device in Fig. 7 includes a memory cell array 13, X-decoder 14, Y-decoder 15, a read/write control circuit 16, a write amplifier 17, a sense amplifier 18, etc. The X-decoder 14 is formed by the two-stage decoder circuit mentioned above. The first-stage decoder circuit FD of the two-stage decoder circuit receives as input the address signals A₀ , ..., A3 , such as four bits, the second-stage decoder circuit SD receives as input other four bit address signals A₄ , ... , A₇. The X-decoder 14 is used to select one wire from the 256 wires connected to the memory array 13. The Y-decoder receives as input, for example, the 8 bits of address signals A₈ , A₉ , ..., A₁₅. By this Y-decoder, one wire is selected from the 256 wires connected to the memory array 13. Then, the data is written to the memory cell connected to the word line and the bit line selected as mentioned above. That is, when the write enable signal WE is, for example, high level in the state that the memory chip is selected by a chip select signal CS, the write amplifier 17 is enabled, so that the input data D IN is written in the memory cell selected by the write amplifier 17 and the read/ write control circuit 16. Further, when the write enable signal WE is low level, the sense amplifier 18 is enabled, so that the data is read from the selected cell by the sense amplifier 18 and the read/write amplifier 16 and is output as the readout data D out . Further, in the memory device shown in Fig. 7, the memory cell shown in Fig. 8 is used. The memory cell shown in Fig. 8 is a so-called diode-load type and is formed by one pair of multi-emitter transistors and one pair of load circuits including a parallel circuit of a diode and a resistor. As mentioned above, according to an embodiment of the present invention, a decoder circuit using a wired logic circuit is used as the two-stage decoder circuit for a semiconductor memory device. Therefore, the rise of the decoder output when the address is changed is reduced and malfunctions due to double selection, etc., can be prevented. Therefore, it becomes possible to improve the reliability of the IC device.

Claims: A two-stage decoder circuit comprising: a first-stage decoder circuit (17-11), for decoding upper bits (A₀,...,A₃) of an input signal, and a second-stage decoder circuit (4-6), which is activated by receiving a selected output signal of said first-stage decoder circuit and which decodes lowers bits (A₄,...) of said input signal; said second-stage decoder being formed by a diode-matrix circuit (D₅,..,D₈); characterized in that said first-stage decoder circuit is formed by threshold-operation type logic circuit(Q₈,Q₉) which carries out selection or non-selection by comparing said input signal with a predetermined threshold level (VR). A two-stage decoder circuit according to claim 1 wherein said threshold-operation type logic circuit comprises a plurality of emitter-coupled transistors (Q₇,Q₈,Q₉), one of said emitter-coupled transistors having a base which receives said predetermined threshold level and the other of said emitter-coupled transistors having a base which receives said input signal. A two-stage decoder circuit according to claim 1, wherein said diode matrix circuit comprises, a plurality of AND gates, each formed by a plurality of diodes (D₅,...,D₈) one of the cathodes thereof receiving said input signal and anodes thereof being commonly connected to a base of a transistor (Q₆), the collector of said transistor being connected to one of said outputs of said first-stage decoder circuits and one output OUT of said two-stage decoder circuit being obtained from the emitter of said transistor.

Inventors: OKAJIMA, YOSHINORI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G11C11
IPC codes: G11C11, H03M7, H01L21, G11C8