MOS-CASCODED BIPOLAR CURRENT SOURCES IN NON-EPITAXIAL STRUCTURE

Abstract: A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages (20, 22) each includ­ ing a 256-R resistor string DAC. The analog output voltage of the first stage (20) is coupled to the second stage (22) by two buffer amplifiers (A1, A2) each formed by a non-epi­ taxial process using a P-type substrate. The amplifiers in­ clude NMOS and PMOS-cascoded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnection within the source.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to current sources formed on an integrated-circuit (IC) chip. More particularly, this invention relates to MOS-cascoded bipolar current sources such as may be used as part of a high-performance amplifier circuit. The invention is described herein for use in amplifiers employed in a cascaded two-stage D/A converter. 2. Description of the Prior Art US-A-3,997,892 (Susset) shows a two-stage cascaded D/A converter wherein the first stage includes a resistor-string DAC to produce a first segment voltage corresponding to a set of higher-order input bits. That voltage is directed through buffer amplifiers to the second stage converter which interpolates the selected first-stage segment voltage in accordance with the lower-order bits. From US-A-4,237,472 a monolithic integrated circuit is known which can be formed by a non-epitaxial process in a n-well provided in a p-substrate. This known circuit comprises a pup-transistor connected in series with a PMOS transistor. Both transistors are interconnected without the need of bridging metallisation by sharing a common p-region, which constitutes the emitter of the bipolar transistor and the drain of the PMOS transistor. This circuit is designed as a EA ROM. For such a converter as disclosed in US-A-3 997 892 to perform successfully at high resolutions, such as 16-bits, the inter-stage buffer amplifiers must meet extremely stringent specifications. It has been found that such specifications cannot be achieved using known techniques. SUMMARY OF THE INVENTION An IC amplifier design is provided utilizing uniquely-configured MOS-bipolar current sources which significantly enhance the performance of the amplifier. These current source structures are formed using an N-well non-epitaxial IC process, and advantageously make possible inter-connections within the current source without the need for bridging metallization. These current sources comprise the features such as disclosed in claims 1 and 6. Although the current sources are disclosed in an amplifier implementation, such current sources can find application in other types of integrated circuits. Still other objects, aspects and advantages of the invention will in part be pointed out in, and in part apparent from, the following description of a preferred embodiment considered together with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 is a simplified diagrammatic showing of a two-stage cascaded D/A converter; FIGURE 2 is a circuit diagram of an amplifier used in the converter of Figure 1; and FIGURES 3A, 3B and 3C show details of N-type and P-type MOS-cascoded bipolar current sources formed with a non-epitaxial process, and adapted for use in the amplifier of Figure 2. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Referring first to Figure 1, which is a simplified diagram of a 16-bit D/A converter, it will be seen that the device includes two cascaded stages generally indicated at 20 and 22. Each stage comprises a 256-R resistor string 24, 26. Logic circuitry 28, 30 of known type of design is used to develop the switch control signals for the respective stages. Buffer amplifier A₁, A₂ are employed to direct the first-stage segment output voltage to the second stage where it is applied to the ends of the resistor string 26. The first stage resistor string 24 receives a voltage shown as +V REF AND -V REF . That voltage is divided by the resistor string into 256 nominally equal voltage segments. Any two adjacent voltage taps are selected in accordance with the upper byte (8 bits) of the 16-bit input word. Amplifier A₁ transfers the voltage of one selected tap (e.g. tap 251) to the top of the second stage. Amplifier A₂ transfers the voltage from an immediately adjacent tap (e.g. tap 252) to the bottom of the second stage. The output amplifier A₃ produces a signal linearly interpolating the voltage drop between taps 251 and 252, weighted by the lower byte of the 16-bit input word. Details of the switch selector system and the associated resistor string for this converter are described in the application of the same Applicants, filed with the EPO the same day under the title: "TWO-STAGE HIGH-RESOLUTION DIGITAL-TO-ANALOG-CONVERTER". Figure 2 shows a simplified circuit diagram of an amplifier suitable for use as amplifiers A₁, A₂ and A₃. These amplifiers were specified to settle to 16 bits in 3µs and simultaneously be high precision dc op-amps. The amplifier includes a single differential gain stage Q₁₁₃, Q₁₁₄, which uses an immitance inverter Q₁₀₈₋₁₁₂ as a load, followed by an MOS/bipolar unity gain impedance buffer. This dominant pole compensated amplifier achieves an A VOL of 10⁶ through the use of bootstrapping. This minimizes the signal dependent V CB modulation in Q₁₁₃ , ₁₁₄ and raises the differential load impedance of the gain stage by a factor equal to the loop gain of the amplifier formed by Q₁₀₈₋₁₁₂ , and, finally, linearizes the MOS/bipolar unity gain buffer by making V DS track between M₁₁₇ and M₁₁₉. To preserve open loop gain, all current sources (shown as an arrow-in-a-circle) are MOS-cascoded bipolar structures. Details of one such current source are shown at M₁₁₃ and Q₁₃₃. The resulting impedance enhancement afforded by the reverse voltage transfer ratio of the FET permits an Early voltage of 10⁶ volts to be achieved at the drain of M₁₁₃. Similarly, Q₁₀₄ and M₁₀₅ provide the same advantage for sources originating from the positive supply, side-stepping the inherently low impedance of the split vertical/lateral PNP'S which are unavoidable device problems in a non-epitaxial process. I b compensation is provided by a PMOS current reflector, operating in subthreshold, shown in part by M₁₀₁₋₁₀₃ and Q₁₀₀. The Darlington NPN/vertical output stage has an I b booster for the output VPNP, Q₁₂₂. M₁₀₉ , ₁₁₀ in conjunction with Q₁₂₅ , ₁₂₆ boosts the base drive into the output when V out lags the voltage at the emitter of Q₁₁₇ under negative slew. The amplifier occupies 0,969 mm² (1500 mil²) and settles to 10ppm in 3µs. The configuration of such P-type and N-type MOS-cascoded bipolar current sources are shown in Figures 3A and 3B, representing the cross-section and plan views respectively of the devices. Figure 3C shows the electrical circuit representation of each device, approximately aligned with the corresponding elements of Figures 3A and 3B. Referring now to the left-hand portion of Figures 3A and 3B, the non-epitaxial P-type substrate is doped to form the usual N-well 100. At the left end of the N-well is a first P-type diffusion 102 of generally rectilinear outline which serves as the drain of a PMOS device. The source of this device is formed by a second P-type diffusion 104 having its principal portion arranged as a square-shaped ring. The PMOS gate 106 is positioned between the source and drain. Within the square ring of diffusion 104 is another P-type diffusion 108 which serves as the emitter of a lateral PNP transistor. The N-type material of the N-well serves as the base of this transistor, and connection is made to the base by an N+ diffusion 109 of generally U-shape and extending partially around the square-ring P-type diffusion 104. The collector of the LPNP is diffusion 104, shared as above by the PMOS source. Thus it will be seen that this diffusion serves as both the collector of the LPNP and the source of the PMOS device. Since both of these functions are performed by the same diffusion, the PMOS source and the PNP collector are effectively connected together electrically, without any need for bridging metallization. That is, no additional layer of metal has to be added to the substrate to make this connection, which is illustrated in the circuit diagram of Figure 3C at 110. No electrode is provided for the P-type diffusion 104, since no external connection is needed to be made to the source/collector of the MOS-bipolar current source. Electrodes are provided for the PMOS drain and for the base and emitter of the LPNP transistor. A distinct characteristic of the PMOS-bipolar current source is that the entire circuit is integrated into a single N-well, which affords important benefits in carrying out the process. Turning now to the right-hand portion of Figures 3A and 3B, there is shown another N-well diffusion 112 within which is a P-type diffusion 114 containing another N-type diffusion 116. These three elements function respectively as the collector, base and emitter of an NPN transistor. Base and emitter electrodes 118, 120 are formed above the substrate to make the necessary connections. The N-well 112 is effectively extended laterally by means of an N+ diffusion 122 which overlaps the initial N-type diffusion. The N+ diffusion reaches to a region alongside a gate electrode 124, and a further N+ diffusion 126 is made on the other side of the gate. This latter diffusion serves as the drain of an NMOS device. The source of this device is formed by the N-type material with the N-well 112. Thus, it will be seen that the N-well 112 (which in this embodiment includes extension 122) serves as both the source of an NMOS device and the collector of an NPN transistor. Accordingly, these two elements are effectively electrically connected, as indicated at 128 in Figure 3C, without the need for a metallization layer. The inclusion of diffusion 122, a low resistivity source-drain diffusion comparable to that routinely used in N-MOS and CMOS fabrication, is to enhance the performance of the composite structure through the reduction of the ohmic resistance diagrammatically represented as path 128 in Figure 3C. The operation of this invention is otherwise unaffected by the omission of 122.

Claims: In a monolithic integrated circuit formed by a non-epitaxial process and having a P-type substrate with an N-well (100) therein; a P-type MOS-cascoded bipolar current source connected in said circuit and comprising: first (102) and second (104) separate P-type diffusions in said N-well (100) to serve as the drain and source of a PMOS device; a gate (106) positioned between said first and second P-type diffusions (102,104); a third P-type diffusion (108) in said N-well (100) separate from said first and second diffusions (102,104) and serving as the emitter of a lateral NPN transistor having said second P-type diffusion as its collector and said N-well (100) as its base; and electrodes making connection with said first (102) and third (108) P-type diffusions and N-well (100); whereby said PMOS source and said bipolar collector are electrically connected without requiring a diffusion-to-metal-to-diffusion interconnection. An integrated circuit as claimed in Claim 1, including an N-type diffusion (109) in said N-well (100) to make connection between an electrode and said N-well (100), said N-well providing the back-gate connection for said PMOS device. An integrated circuit as claimed in claim 1 or 2, wherein said second P-type diffusion (104) surrounds said third P-type diffusion (108). An integrated circuit as claimed in Claim 2 or 3, wherein said N-type diffusion (109) extends partially around said second P-type diffusion (104). An integrated circuit as claimed in any of Claims 2 to 4, wherein said second P-type diffusion (104) is a ring at least approximately square in shape; said N-type diffusion (109) being at least approximately U-shaped, with the two arms of the "U" extending along two respective parallel sides of the square P-type diffusion (104). In a monolithic integrated circuit formed by a non-epitaxial process and having a P-type substrate with an N-well (112) herein; an N-type MOS-cascoded bipolar current source connected in said circuit and comprising: a P-type diffusion (114) in said N-well (112) to serve as the base of an NPN transistor; an N-type diffusion (116) in said P-type diffusion (114) to serve as the emitter of said NPN transistor; electrodes (118,120) contacting said P-type (114) and N-type (116) diffusions to make connection to said base and said emitter; said N-well (112) serving as the collector for said NPN transistor; an N-type diffusion (126) in said P-type substrate, externally of said N-well (112), to serve as the drain of an NMOS device; an electrode contacting said external N-type diffusion (126); a gate (124) for said NMOS device adjacent said external N-type diffusion (126); said N-well (112) comprising N-type material (122) extending to a region which is adjacent said gate (124) but on the side thereof which is opposite said external N-type diffusion (126), said N-type material (122) serving as the source of said NMOS device and as the collector of said NPN transistor; whereby said NPN collector and said NMOS source are effectively connected electrically without requiring a diffusion-to-metal-to-diffusion interconnection. An integrated circuit as claimed in Claim 6, wherein said N-well 112 includes an initial N-type diffusion, said N-type material 122 comprising an N+ diffusion partially overlapping said initial N-type diffusion and extending to the side edge of said gate 124. Digital-to-Analog converter with an integrated circuit according to any of Claims 1 to 7.

Inventors: HOLLOWAY, PETER R.
Applicants: ANALOG DEVICES, INC.
Application year: 1985
Main classification: H01L27
IPC codes: H01L21, H01L27, H03M1