Method and apparatus for positioning transducers by digital conversion of analog signals

Abstract: A method of and apparatus for obtaining digital expres­ sion of analog signals, in particular signals produced by "reading" (i.e., tranducing) head-positioning information re­ corded on storage media, for example magnetic recording media. Head-positioning signals (36, 38) constitute signals bursts which are processed to obtain pulses whose width is dictated by the amplitude of the detected bursts, and the pulse width in each instance is expressed digitally by using the magnitude of the pulse to drive a counter-timer (61). The resulting count integrally embodies a digitized representa­ tion of the initial analog signal burst, which is directly avail­ able for further processing by digital means and for storage in digital memory apparatus.

Description: This invention relates broadly to methods and apparatus for obtaining digital expression of various analog form signals, in particular, signals which are "read" (i.e. transduced) from head-positioning information recorded on storage media, particularly magnetic storage media. More particularly, the method and apparatus of the invention pertain to digital quantification of tracking or positioning signals (embedded servo signals) located along recorded tracks and used in servo systems to maintain transducer alignment with a particular such track. In a particular such environment, the invention has desirable application to magnetic tape memory systems having pre-recorded servo positioning bursts along the different tracks, but in its more general aspects the invention is applicable to other forms of media and to a variety of identification and positioning signal formats. Reference should also be made to our co-pending application published as EP-A-0.490.876 (divided out of this application) which relates to an analogous apparatus for and method of decoding track identification information. Analog-to-digital code conversion has in the past been accomplished in a number of different ways, commencing long ago by use of various discrete-component hardware implementations and proceeding through periodic generations generally trending toward the development and production of integrated circuit devices intended for universal or widely-applicable use as "building block" converters, which have come to be used on a more or less generalized basis, in a multitude of applications, wherever the need presented itself. The use of such "off the shelf", multipurpose A/D converters has led to almost immediate acceptance and widespread use which to a considerable extent has replaced particularly-designed hardware converter implementations; however, it is quite likely that in a number of such instances individually-designed converter systems would yield both improved results and economic advantage as well, and the present invention is addressed to situations of this type. In a particular illustrative embodiment, the present invention is directed to "embedded servo" systems such as (by way of particular example) that disclosed in the applicant's US-A-4,472,750 and copending European application 85301749. In the systems particularly addressed in this patent and application, a format for embedded servo information is disclosed which includes positioning information blocks containing both track-identification information and servo-positioning tracking "bursts". In a preferred form of the invention, paired servo-tracking signals are recorded, for example by first and second ("A" and "B") bursts which are positioned on opposite sides of the track centerline and which appear in predetermined time sequence with respect to one another. Such tracking bursts are detected and decoded in an amplitude-representative manner, i.e. with opposite but equal amplitudes in the event the head is precisely centred on the track centerline, and with progressively different relative amplitudes resulting from tracking displacement of the head to one side or the other of the centerline, differencing of the "A" and "B" signal values producing an error signal which can be used in closed-loop servo-controlled tracking procedures. In an environment such as the one just described, digital processing is an integral part of the overall operation of the system, whose purpose is for the storage and retrieval of user data, typically recorded with very high-density bit streams in a modified FM recording format. It is thus desirable and perhaps essential to use such digital processing techniques (e.g., by microprocessor control) in decoding and utilising the positioning information, but it does not necessarily follow that the most effective and advantageous systems to be employed for this purpose should utilise "off the shelf" integrated circuit A/D converters, either for the quantification of the A and B servo-positioning bursts, or for the decoding of the track-identification information. A novel A-to-D conversion procedure is disclosed by which anticipated signal bursts are processed to obtain pulses whose particular width is dictated by the amplitude of the detected or received bursts, and whose particular width is quantified directly by using the magnitude of the pulse to drive a counter-timer. The resulting count thus integrally embodies a digitised representation of the initial analog signal burst, and provides a digital signal which is directly available for further digital processing as for example by storage in memory and comparison or computation through use of digital components or devices. Considered from a somewhat more particular perspective, the method and apparatus of the invention in a preferred embodiment comprises discrete hardware componentry utilised in conjunction with what may be typical or known types of read channel electronics in a digital storage device, for example magnetic disc or tape, which in effect separately channels the detected positioning signals after differentiation thereof, to subject such signals to times and comparative sample-and-hold techniques using as a reference a known function generated during an identical period, the reference and the held, sampled signal being applied to a bi-stable device (e.g., comparator) whose shifting states trigger a counter-timer and thus produce the aforementioned digital count. US-A-3 720 927 discloses a method and apparatus for reading and writing digital information. It discloses a pulse-coding arrangement, whereby two opposite-polarity pulse portions are combined so as to produce an algebraic sum from the two oppositely-sensed pulse portions. Specifically, during a first such portion a counter-timer is incremented a number of steps corresponding to the first pulse portion, and then it is immediately decremented by a number of steps corresponding to the other part of the pulse involved. The digitally-encoded result hence characterises the overall difference between the pulse portions. EP-A-069548 represents the closest prior art. The present invention differs from the disclosure of this document in that the former includes a ramp counter A/D converter which was not previously thought suitable for use in a sequentially-operating high speed tape drive. A ramp counter convecter is disclosed in: "The Radio and Electronic Engineer", vol. 53, No. 10, pp. 361-368, Oct. 1983, F.A. Bellis: "Introduction to digital audio recording". Specifically, the A/D converter used in the present invention is arranged capacitatively to hold a value representative of a sampled value, and to digitise the magnitude of the held value by timing an interval during which an output from a reference source changes at a known rate from a reference value to a further value which is representative of the held value. According to a first aspect of the present invention there is provided a method, in a tape drive, of processing analogue track-following information recorded on storage media and positioning a transducer-head in accordance therewith, the method comprising the following steps: (a) reading some first recorded information and producing a corresponding first sample signal therefrom; (b) holding on capacitative holding means a first value representative of the first sample signal; (c) digitising the magnitude of the first held value by timing an interval during which an output from a reference source changes at a known rate from a reference value to a first further value which is representative of the first held value; (d) outputting the timed interval, being a digital representation of the magnitude of the first held value, in the form of a first digital count value; and dumping the charge on the capacitative holding means; (e) reading some second recorded information and producing a corresponding second sample signal therefrom; (f) holding on the capacitative holding means a second value representative of the second sample signal; (g) digitising the magnitude of the second held value by timing an interval during which the output from the reference source changes at a known rate from the reference value to a second further value which is representative of the second held value; (h) outputting the timed interval, being a digital representation of the magnitude of the second held value, in the form of a second digital count value; (i) calculating a correction value based upon the first and second digital count values; and (j) positioning the transducer head by moving the head in dependence upon the correction value. According to a second aspect of the present invention there is provided a tape drive including means for processing analogue track-following information recorded on storage media and for positioning a transducer-head in accordance therewith, the tape drive comprising: (a) reading means for reading some first recorded information and producing a corresponding first sample signal therefrom; (b) capacitative holding means for holding a first value representative of the first sample signal; (c) digitising means for digitising the magnitude of the first held value by timing an interval during which an output from a reference source changes at a known rate from a reference value to a first further value which is representative of the first held value; (d) digital timing means for outputting the timed interval, being a digital representation of the magnitude of the first held value, in the form of a first digital count value; (e) means for dumping the charge on the capacitative holding means; (f) the reading means further being arranged to read some second recorded information and to produce a corresponding second sample signal therefrom; (g) the capacitative holding means further being arranged to hold a second value representative of the second sample signal; (h) the digitising means further being arranged to digitise the magnitude of the second held value by timing an interval during which the output from the reference source changes at a known rate from the reference value to a second further value which is representative of the second held value; (i) the digital timing means further being arranged to output the timed interval, being a digital representation of the magnitude of the second held value, in the form of a second digital count value; (j) calculating means arranged to calculate a correction value based upon the first and second digital count values; (k) positioning means for moving the transducer head in dependence upon the correction value. Means may be provided for cumulatively summing and storing the output from a substantially constant supply and using the cumulative store as said reference source. As indicated above, the conversion apparatus and method of the invention are most advantageously applicable to embedded servo-tracking systems, and in particular to certain such systems utilised in connection with magnetic tape as a recording media. In such an environment, the preferred embodiment allows for the use of the same basic digital conversation circuitry and components for use in both decoding track addresses and for comparing the A and B servo-positioning signals and generating an error signal therefrom. In particular, the preferred system produces digital representations of the track addresses and of A and B positioning signal magnitudes, and thus directly provides digital signals from which a normalized error signal may be produced by digital computation techniques. The method and apparatus of the preferred embodiment thus provide desirable and effective digital conversion techniques and circuitry by use of discrete hardware components providing multiple-purpose results on a more advantageous cost-effective basis than would be true, for example, by use of typical integrated circuit components. Additional objectives and advantages of the invention will be made more apparent upon consideration of the ensuing specification and by reference to the attached drawings, depicting a particular preferred embodiment of the invention. The invention may be carried into practice in various ways and one specific embodiment will now be described by way of example, with reference to the accompanying diagrams, in which: Figure 1 is reproduced from the aforementioned United States Patent 4,472,750, and illustrates a preferred and illustrative format for positioning information, in conjuction with which the method and apparatus of the invention are particularly advantageous and in connection with which the same will be explained; Figure 2 is also reproduced from the aforementioned United States Patent, and constitutes an illustrative timing and decoding illustration of an exemplary track-identification format; Figure 3 is a system block diagram showing the general attributes of a preferred read/write system for use in storage apparatus in accordance herewith; and Figure 4 is a schematic circuit diagram illustrating one particular preferred embodiment of the invention. As indicated above, Figures 1 and 2 are reproduced from United States Patent 4,472,750, and serve to depict an illustrative, but preferred, embedded servo format and track-identification coding scheme in connection with which the preferred embodiment will be explained. In Figure 1, an illustrative segment 10 of recording media is shown, which may be considered to be a segment of recording tape although in a broader aspect being representative of other forms of recording media, e.g., magnetic disc. The segment of media 10 so illustrated is shown to have user-data recording fields 18 and 18′ and a number of parallel data tracks or paths, designated I-IV inclusive, it being understood that any given number of such parallel paths or tracks will typically be present on media as customarily used. As illustrated, between the user-data fields 18 and 18′ is a block 20 of positioning information, which includes both track-identification headers 32, 32 a (track I), 34, 34 a (track II), 32′, 32′ a (track III), etc. In addition to the track-identification headers just noted, each of the blocks of positioning information 20 in each of the recording tracks also includes a pair of laterally-offset servo-positioning bursts 36 and 38, which are disposed sequentially with respect to one another along the length of the recording track and positioned on opposite sides of the track centerline. The bursts 36 and 38 may be designated "A" and "B" respectively. The aforementioned United States Patent 4,472,750 sets forth the purposes underlying the format just described, together with the advantages obtained thereby. For added clarity, and considering the showing set forth in Figure 1, it may be noted that this Figure is intended to principally illustrate the use of recording tape as a media, with the tracks being recorded in serpentine, alternating fashion, i.e., track I being forwardly-encoded, track II being reversely-encoded, track III being forwardly-encoded, etc. Within each such track, the first-encountered header (e.g. header 32 in track I and header 34a in track II) is forwardly-encoded, whereas the last-encountered headers (e.g., header 32 a in track I, header 34 in track II, etc.) are reversely-encoded, so as to present the same recording pattern and timing during read operations, bearing in mind that in the event a positioning error occurs it will be important to rapidly identify the particular track encountered. In the above-described positioning information format, it will be noted that the track-identification headers 32, 34 a etc. are each centered upon their respective recording tracks, whereas the servo-positioning bursts 36, 38, etc. are laterally offset, extending in opposite directions from the track centerline in each case. Accordingly, it will be understood that if a transducer head having a height of approximately one-half track is utilized, the amplitude of the signals reproduced from the track-identification headers will be approximately the same even if the transducer pole pieces (that is, the gap) are misplaced as much as one-half track away from the centerline of a track being followed. Essentially the opposite is true with respect to the amplitude of signals reproduced from the "A" and "B" servo-positioning bursts 36 and 38 (or 36′, 38′, etc.) since if the transducer head is precisely aligned with the track centerline, each such servo-positioning burst will be reproduced with equal amplitude although being disposed sequentially in time. The further the recording head errs away from the track centerline, however, the higher the amplitude will be for the signals reproduced from the particular servo-positioning burst over which the head is more fully aligned. It will be noted that in the illustrated embodiment of Figure 1, each of the data fields 18, 18′ in the adjacent tracks terminates at the same point along the tape, on a track-to-track basis, although such lateral registration is not in a strict sense an absolute requirement of the general system illustrated. The depicted arrangement does, however, serve to illustrate that in a forward progression through each of the serpentine recording tracks, the positioning information format provides a consistent pattern which is the same from one track to another on the basis of content and timing. Consequently, each such block of positioning information may be utilized as a synchronization pattern, and of course identical timing may be used for detection and decoding of the information contained therein. For example, referring to track I as illustrative, it will be noted that an erased gap designated "x" appears between the end of the user-data field 18 and the first (forwardly-encoded) header block 32. A different and longer erased gap (x+y) exists between the end of the oppositely-encoded header 32 a and the next ensuing user-data block 18′. The same pattern is true in track II if the same is considered in a right to left direction, and the pattern of track I is repeated in track III, etc. In actuality, the length of track "y" is the same as the length of one of the track-identification headers 32, 34, etc., and this distance or duration, is approximately twice that of the servo-positioning bursts 36, 38 (represented in Figure 1 by the designation "z"). Representing such durations are, for the length "y" of the track-identification headers, a duration of approximately 2 milliseconds, and the duration "z" of the positioning burst of the order of 1 millisecond. An exemplary track-identification header 32 occurring over a duration y is illustrated in Figure 2 a , and the envelope thereof is illustrated correspondingly in Figure 2 b . It may be seen in this Figure that the overall duration of the track-identification header is divided up into a number of bit cells, six of the same being shown for purposes of illustration in Figure 2 b wherein they are designated as bit cells A-F inclusive. During each such bit cell, a burst of uniform-frequency signal is recorded (for example, square waves at a frequency such as 125 kilohertz). The duration of each of these bursts of uniform frequency (and uniform amplitude) determines whether the logic value of that bit cell is a binary zero or a binary one. More particularly, in accordance herewith, each of the headers 32, 34, etc. occurs at a known timing point within the positioning block, and each such header is in effect subdivided into a known number of bit cells, each of which thus occurs at a known point in time and which may be decoded on the basis of that predetermined timing pattern. More particularly, if each bit cell is considered to be divided into three "sub-cells", the presence of the recorded signal for a duration of (for example) the first one-third of the bit cell may be taken to indicate the presence of a logic zero, whereas the continuing presence of the signal for the first two-thirds of the bit cell may be considered to be a logic one. In such an arrangement, there will typically be no signal present during the last one-third of each bit cell, and indeed the presence of signal during that interval may if desired by deemed an error check. Thus, the signal pattern depicted in Figure 2 may be seen to represent a properly-encoded signal whose overall logic value would be 001010. Each such bit value may be utilized as part of a track address, or a certain number less than the whole may suffice for that purpose, with remaining bit cell values being taken as an indicator of other desired information, e.g., the relative position of that block along the length of the recording track. While the detection, decoding, and error-signal generation techniques employed with positioning patterns of the nature of that illustrated at 20 in Figure 1 may be accomplished in a variety of different ways, certain particular such ways constitute the main focus of the present invention. More particularly, as illustrated in the system block diagram of Figure 3, (directed toward preferred methodology for writing such servo patterns), a preferred overall system for reproducing and processing the positioning information includes a closed-loop head-positioner system comprising a stepper motor 40 whose rotational output drives a positioning cam 42 which is in turn coupled by a pivotal positioning arm 44 to a transducer or head 46, shown as being vertically moveable upon a positioning and guiding head slide 48. The transduced "read" output from the head 46 is coupled along a path 50 to a read amplifier and filter 52, and the output of the latter is coupled sequentially to a rectifier 54, a peak detector 56, a sample-and-hold circuit 58, and an analog-to-digital converter 60, whose output ultimately is fed to a microprocessor 62 which controls the stepper motor driver 64, thus controlling the operation of stepper motor 40. The illustrated system also includes, for the sake of completeness, a servo signal "write" generator 66 whose output is coupled through a write amplifier 68 back to the transducer head 46, for recording or "writing" operations. The recording media or tape 10 is shown as being provided in cartridge form, enclosed within a cartridge housing 11, in which it is driven by a motor-driven capstan 70 which may be directly coupled to a capstan drive motor 72, a motor driver being shown as 74. Inasmuch as accurate tape speed control and regulation is of the essence in such operations, both for "reading" and "writing" on the tape, a tachometer 75 should be utilized, driven by the capstan drive motor 72, the tachometer output being coupled back to the microprocessor 62 along a path 76. Referring now to the schematic diagram shown in Figure 4, and considering the same generally in light of the overall system shown more generally in Figure 3, the read amplifier and filter 52 may generally be considered to be that portion of the circuit shown at the top of Figure 4. More particularly, this circuitry preferably includes an input switch section 80 comprising the two interconnected FET's 82 and 84, each of which controls (opens or closes) one of the two complementary input lines 86 and 88, both FET's in turn being simultaneously controlled by a write-enable or write-gate signal to a path 90 during times when information (user data) is being written on the media. The input switch 80 thus provides a read-disable feature during writing operations. Assuming a read mode, the inputs from the transducer head on paths 86 and 88 are coupled through the FET's 82 and 84 and are applied to an amplifier 92, which may be a TL 592 differential video amplifier which in effect provides a preamplifying function. Following the amplifier 92, the read signals are applied to a filter network 94, which is a 2-pole low-pass, 1-pole high-pass filter. Following the filter 94, the signals are applied to a differentiator network 96 and, after differentiation, are applied to a conventional data-read circuit 98, which may be an IC3470 read chip frequently used in such data-read applications. The processed data signals from read chip 98 are outputted on a path 100, which may be coupled back to the host data system for any of the customary functions (e.g., display, printing, etc.). Apart from user-data reading functions, outputted on the path 100 as noted above, the read system of Figure 4 also reproduces signals from the positioning information blocks 20 described above in connection with Figure 1 and 2. These read signals are of a very different nature from the user data signals, as already noted, and after passing through the input switch 80, preamp 92, filter 94, and differentiator 96, these signals are coupled along a path 102 for decoding and digital conversion, which involves the rectifier stage 54, peak detector stage 56, sample-and-hold stage 58, and ultimately the A-to-D section 60, the components of which are illustrated in the lower portion of Figure 4. With continued reference to Figure 4, it will be noted that the path 102 initially encounters a voltage level-setting and rectifying network 103 which is coupled to the "A+" voltage supply through an appropriate resistor 104 and which has a pair of series-connected diodes 106 used to bias the input of an operational amplifier 108. The resulting signals are then coupled to the half-wave recitifier and peak detector network 56, which preferably includes back-to-back diodes 110 and 111 which reject any signal component below a set level and pass only the selected (i.e., "sampled") positive peaks (half-wave rectification) of the differentiated positioning signal to a storage capacitor 112. The latter provides the "hold" function, under control of a "threshold" signal applied via an input line 135 to an AND gate 115 and an inverter 117, via a resistor 113, by means of which the storage capacitor 112 may be cleared or discharged (i.e., "dumped") at selected times. The sampled, peak-detected, differentiated signal is then coupled along a path 114 and applied to the negative input of a comparator 116. Also, this signal is outputted along a parallel path 114(a) for test or other purposes, as noted hereinafter. The comparator 116 has its positive input coupled to a constant-current charging network 120, which includes a transistor 122 whose base is coupled to the "B+" supply through a pair of series-connected diodes 121 and a voltage-developing resistor 123. The common node 124 of the comparator 116 and the constant-current source 120 is coupled to one side of a storage capacitor 126, which is selected to produce a reverse sawtooth wave shape in response to applied cycles of the constant-current charging circuit. The node or point 124 is also coupled to the input line 135 and the control gate 115, along a path 135, through a resistor 223 and an inverter 127. The nodal point 124 is, additionally, coupled from a point 125 (between the capacitor 126 and the inverter 127), through an inverter 128 back along a line 130(a) to a "clear" or "dump" input line 130, which in general parallels the threshold input line 136 noted above. Both input lines 130 and 135 are coupled to outputs of the microprocessor 62 (Figure 3) to receive control signals therefrom. The path 130 is also coupled, along a second branch 130(b), to one input of an "Exclusive OR" gate 132, whose other input is coupled back to the output of the comparitor 116, while also being connected to the "A+" supply source. Generally speaking, the overall functioning of the circuitry just described above is to provide a very accurately-timed switched output from the Exclusive OR gate 132 on a line 133, which is coupled to a digital counter-timer 61 (for example, an IC8253) which may be considered as part of the "analog-to-digital converter" block 60 shown in Figure 3. As explained more fully below, the result is a digital count value providing to the microprocessor. When utilized to process the track-address headers 32, these count values signify the presence of at least minimum-amplitude signal bursts within the various bit cells and also time the duration thereof, so as to indicate whether the same constitute logic zeros or logic ones. When dealing with the read output produced from reproduction of the A and B servo bursts 36 and 38, respectively, the count values directly indicate the amplitude of the tracking signals read, on the basis of which an error signal may readily be computed by the microprocessor for use in making tracking corrections. More particularly, the overall operation briefly described above is achieved by applying the rectified and peak-detected ("sampled") positioning information "read" signal to the capacitor 112, which stores ("holds") the resultant value while that value is applied to one input of the comparator 116. The other input of this comparator is coupled to the charging capacitor 126, which produces a linear ramp function as a result of being charged by constant-current source 120. If the positive input of the comparator is higher than the negative input, the output to gate 132 remains high, but whenever the opposite input condition prevails, the output goes low. Which of these two input conditions prevails is thus primarily a function of the amplitude of the signal stored on capacitor 112, which reflects the amplitude of the read signal from the transducer. Accordingly, considering the A and B servo-positioning bursts (36 and 38 in Figure 1), with appropriate internally-clocked sampling control signals from the microprocessor applied on inputs 130 and 135, each such A or B servo burst is sampled by clearing or dumping the storage capacitors 112 and 126 and then allowing the same to charge in response to their respective applied signals. As described above, the charge applied to capacitor 126 generates a linear ramp function whose magnitude is compared by comparator 116 to the magnitude of the "A" or "B" servo-positioning signal then being held on capacitor 112. Whenever the latter value is exceeded by the linearly-rising charge on capacitor 126, comparator 116 will toggle, or change state. The "dump" signal from the microprocessor on input 130 which initially clears the storage capacitor 126 via the line 130(a) is also applied by the line 130(b) as an input to the Exclusive OR gate 132; consequently, this input will normally remain high, as is also true of the output of comparator 116 prior to the time it toggles in the aforementioned manner. Thus, toggling of the comparator 116 causes a change of state by Exclusive OR gate 132, and this produces a switched output state on the path 133, which is used as one of the controls for the aforementioned counter-timer 61. When the sampling-storage capacitor 112 is discharged (through the resistor 113) by a control signal (logic low) applied to the input 135, the resulting logic low signal is also coupled along the path 136 to the node 124 and to the positive input of the comparator 116, thereby toggling the latter and changing the state of the Exclusive OR gate 132, which resets the counter-timer 61. As soon as charge from the next sampled servo signal has been accumulated on the storage capacitor 112, the counter-timer begins running again, and whenever the steadily-rising ramp applied to capacitor 126 causes toggling of the comparator 116, the change-state output of the comparator, under logical control of gate 132, will again stop the counter from running. The operation just described produces a digital count value in counter 61 which is directly proportional to the amplitude of the sampled servo signal held on the capacitor 112. This count thus provides a pulse signal whose width accurately measures the "A" servo amplitude, and a similarly-produced such signal immediately follows which measures the amplitude of the corresponding "B" servo signal. These two digital count values, coupled to the microprocessor 62 from the counter-timer 61, can readily be differenced to produce an error signal, and in fact the two such digital values can readily be utilized by the microprocessor to produce a normalized error signal, through application of the classical normalization relationship constituting the difference-sum quotient of the A and B values. The same basic type of operation provides a convenient and accurate way to decode the track address information encoded in positioning blocks 32, 34, etc.... This is accomplished by the processor 62 setting the input control line 135 low and in turn causing the output of the inverter 117 to also go low. This results in the capacitor 112 being discharged through the resistor 113. When track address signals (as shown in Figure 2 b ) are present. a semi-sawtooth signal is present on capacitor 112, with some nominal DC value. In the absence of signal (such as during the last third of each bit cell, after a burst defining a logic one or zero) the signal stored on capacitor 112 will decay to a nominal zero (volt) level. In addition to the operation just stated, the branch 136 of the control line 135 also causes the inverter 127 to go low, resulting in the constant-current source 120 providing current through the resistor 223 and establishing a preselected level at the node 124. This level at the node 124 is compared by the comparator 116 with the semi-sawtooth signal on the capacitor 112. In the presence of a track address signal within the bit cell, the minimum value on the capacitor 112 is greater than the value at node 124. When the track address signal stops, at some fixed time later, the value on the capacitor 112 will drop below the level at nodal point 124. This in turn causes comparator 116 to change state, indicating the absence of signal. The time counted from the first detected presence of the track address signal until the detected absence is used to accurately determine the logic value of the bit cell signal, i.e., a binary "one" or "zero". Thus, by successively accumulating on the capacitor 112 the charge attributable to the signal which is present in each of the bit cells shown in Figure 2, and by timing the duration of each such signal the encoded signals within each of the different bit cells may first be qualified with respect to satisfying a required minimum threshold value and then decoded as to logic zero or one value according to the length of time which the counter-timer 61 shows each threshold-qualified signal to have been present during the bit cell. During this operation, "dumping" of the storage capacitors for reset purposes is under microprocessor control on a time-gating ("windowing") basis corresponding to the known positioning signal location and the known bit cell timing and duration. By sequentially storing each resulting count for a bit cell grouping, the corresponding digital address or value is assembled for the track then being followed and read. From the foregoing description and discussion, it may be seen that the present embodiment provides a unique method and apparatus for A-D conversion, particularly (but not exclusively) useful in data-storage devices such as disc and tape drives, having different controllable modes of operation by which recording track address bursts are directly decodable and may first be tested or qualified against a predetermined minimum allowable recording amplitude, and also by which servo-positioning (tracking) bursts recorded along the data tracks on the media may be directly decoded, compared and used to produce a position-corrective error signal. In the second such mode, the method and apparatus produces precisely-timed pulses whose width is directly proportional to the amplitude of the recorded signals read from the media, the count values so produced thus digitizing the same. In the first such mode, where amplitude values (beyond merely meeting minimum threshold levels) may not be representative of information, the duration of the signals may be outputted in similar direct signal form but with the resulting digital count value representative of the duration of the transduced signal. At the same time, valuable economies are realized since although implemented from discrete circuit components rather than being of integrated-circuit form, the preferred apparatus may be constructed at approximately one-third the cost of typical integrated circuit (chip)-form A-D converters adapted for similar operational results.

Claims: A method, in a tape drive, of processing analogue track-following information recorded on storage media (10) and positioning a transducer-head (46) in accordance therewith, the method comprising the following steps: (a) reading some first recorded information and producing a corresponding first sample signal therefrom; (b) holding on capacitative holding means (112) a first value representative of the first sample signal; (c) digitising the magnitude of the first held value by timing an interval during which an output from a reference source changes at a known rate from a reference value to a first further value which is representative of the first held value; (d) outputting the timed interval, being a digital representation of the magnitude of the first held value, in the form of a first digital count value; and dumping the charge on the capacitative holding means (112); (e) reading some second recorded information and producing a corresponding second sample signal therefrom; (f) holding on the capacitative holding means (112) a second value representative of the second sample signal; (g) digitising the magnitude of the second held value by timing an interval during which the output from the reference source changes at a known rate from the reference value to a second further value which is representative of the second held value; (h) outputting the timed interval, being a digital representation of the magnitude of the second held value, in the form of a second digital count value; (i) calculating a correction value based upon the first and second digital count values; and (j) positioning the transducer head (46) by moving the head in dependence upon the correction value. A method as claimed in Claim 1 in which the first and second sample signals are peak-detected signals. A method as claimed in Claim 2 including differentiating the signals prior to the peak-detecting. A method as claimed in any of the preceding claims including establishing a required minimum amplitude threshold for the first and second recorded information by comparing an amplitude representation of the first and second sampled signals with a predetermined minimum allowable amplitude, and thereby selectively enabling an input. A method as claimed in any of the preceding claims in which the output from the reference source increases or decreases at a substantially linear rate from the reference to the first and second further value. A tape drive including means for processing analogue track-following information recorded on storage media (10) and for positioning a transducer-head (46) in accordance therewith, the tape drive comprising: (a) reading means for reading some first recorded information and producing a corresponding first sample signal therefrom; (b) capacitative holding means (112) for holding a first value representative of the first sample signal; (c) digitising means for digitising the magnitude of the first held value by timing an interval during which an output from a reference source changes at a known rate from a reference value to a first further value which is representative of the first held value; (d) digital timing means (6) for outputting the timed interval, being a digital representation of the magnitude of the first held value, in the form of a first digital count value; (e) means for dumping the charge on the capacitative holding means (112); (f) the reading means further being arranged to read some second recorded information and to produce a corresponding second sample signal therefrom; (g) the capacitative holding means further being arranged to hold a second value representative of the second sample signal; (h) the digitising means further being arranged to digitise the magnitude of the second held value by timing an interval during which the output from the reference source changes at a known rate from the reference value to a second further value which is representative of the second held value; (i) the digital timing means further being arranged to output the timed interval, being a digital representation of the magnitude of the second held value, in the form of a second digital count value; (j) calculating means arranged to calculate a correction value based upon the first and second digital count values; (k) positioning means for moving the transducer head (46) in dependence upon the correction value. A tape drive as claimed in Claim 6 including peak-detecting means for peak-detecting the signals. A tape drive as claimed in Claim 6 or Claim 7 including differentiating means for differentiating the signal prior to peak-detection. A tape drive as claimed in any one of Claims 6 to 8 in which the reference source is a linearly-ramped voltage source (120; 126). A tape drive as claimed in any one of Claims 6 to 9 including a bistable switching means (116) arranged to receive as one input the first and second hold value and as another input the output from the reference source, and arranged to change its output state in response to a predetermined relationship between the said inputs, the output from the switching means (116) acting to control the digital timing means (6). A tape drive as claimed in any one of Claims 6 to 10 in which the reading means, capacitative holding means and digitising means are further arranged to effect track-identification by decoding track-identification information recorded on the storage media (10), the positioning means being arranged further to move the transducer head (46) in dependence upon an output of the digital timing means which is representative of the decoded track-identification information.

Inventors: LUM FRANCIS, SOKOLIK EDMUND LOUIS, LUM, FRANCIS, SOKOLIK, EDMUND LOUIS
Applicants: CONNER PERIPHERALS INC, CONNER PERIPHERALS, INC.
Application year: 1985
Main classification: G11B5
IPC codes: G11B21, G11B5, G11B27