A DYNAMIC READ-WRITE RANDOM ACCESS MEMORY

Abstract: A dynamic read-write random access memory is de­ scribed having memory cells (211-214) each including switching means (Tt) and a capacitor (C) connected between one side of the switching means and a voltage supply line. A bit line (B, B) is connected to the other side of each switch means (Tt), and a word line (W₁ - W₄) is connected to a control terminal of each switching means (Tt). When a first voltage level is applied to one of the word lines one memory cell is selected and when a second voltage level is applied that memory cell is not selected. A voltage supply circuit (241) applies to the bit line (B, B ), when the memory cell is not selected, a voltage level between the second voltage level applied to the word line (W₁ - W₄) and a third voltage level at the junction of the switching means (Tt) and the capacitor (C), to prevent flow of leakage current through the switch means (Tt) to the bit line.

Description: This invention relates to a dynamic read-write random access memory, and more particularly to a dynamic read-write random access memory fabricated of MOS transistors. Various electrical circuits such as processors and memories have been integrated on semiconductor chips following recent prominent developments in semiconductor techniques. A dynamic read-write random access memory, hereinafter abbreviated as a "DRAM", is a semiconductor memory of the type allowing not only reading but also writing of data. DRAM is adapted to large capacity memories, where data stored in the form of stored electric charge, because memory cells formed of a small number of transistors are employed. Figure 1 is an example of a circuit diagram of a memory cell that includes a transistor and a capacitor. This memory cell is used in a DRAM because of the small number of transistors required. In fact, this memory cell only includes a capacitor (C) for storing data and a MOS transistor (T t ) for transferring data. Data is stored in the capacitor (C) connected between a voltage supply terminal (101) that supplies one voltage level (e.g., 5v) and a drain terminal (102) of the transistor (T t ). A writing operation of the memory cell is as follows: (i) a source terminal (103) of the transistor (T t ) is supplied with one voltage level, for example, a high voltage level (i.e. "1", e.g., 5v) corresponding to the data to be written; (ii) a gate terminal (104) of the transistor (T t ) is supplied with a high voltage level (e.g. 5v) to the selected memory cell such that the voltage level of the drain terminal (102) becomes a "1" voltage level, corresponding to the voltage level on the source terminal (103); and (iii) the voltage level of the gate terminal (104) changes from the high voltage level to a low voltage level, such that the transistor (T t ) becomes nonconductive. On the other hand, a reading operation from the memory cell is made by detecting (i.e. sensing) a change of the voltage level of the source terminal (103) of the transistor (T t ) at a time when the gate terminal (104) of the transistor (T t ) is supplied the high voltage level to select the memory cell. Although the above operation is explained by using one memory cell, an actual DRAM has many memory cells. Many source terminals of the memory cells are connected to a bit line, and as a result, a large stray capacitor occurs between the bit line and the semiconductor substrate. The capacitance of the stray capacitor is usually much larger than the capacitor (C). So, the change of the voltage level of the source terminal (103) of the transistor (T t ) is very small when the memory cell is selected. For that reason, the prior art DRAM usually has a sense amplfiier and a precharge circuit. Figure 2 shows a DRAM using the memory cell as shown in Figure 1. Source terminals of the memory cells (111, 113, .....) are connected to a bit line (B). On the other hand, source terminals of the memory cells (112, 114, .....) are connected to a bit line ( B ). Gate terminals of the memory cells (111, 112, 113, 114, .....) are respectively connected to word lines (W₁, W₂, W₃, W₄, ....). The bit line (B) is connected to a dummy cell (121), and the other bit line ( B ) is connected to another dummy cell (122). The gate terminal of the transistor (T t ) of the dummy cell (121) is connected to a dummy word line (DW₁). On the other hand, the gate terminal of the transistor (T t ) of the dummy cell (122) is connected to a dummy word line (DW₂). The two bit lines (B, B ) are connected to a sense amplifier (131) and a precharge circuit (132). There will now be described by reference to Figure 2 and Figure 3 operation of the DRAM shown in Figure 2. A. Reading operation under the condition that the memory cell (111) stores "1". (i) At time t₀. Voltage levels of all of the word lines (W₁, W₂, W₃, W₄, ....) and all of the dummy word lines (DW₁, DW₂) are V SS (e.g., Ov). All of the transistors of the memory cells (111, 112, 113, 114, .....) and the dummy cells (121, 122) are nonconductive and none of cells (111, 112, 113, 114, ......, 121, 122) are selected. The voltage level of a sense latch signal (SL) is high and is supplied to a gate terminal of a transistor (T SL ). Sense amplifier (131) is thus operative. The voltage level (V B ) of the bit line (B) is V SS because the sense amplifier (131) is flip-flop type differential amplifier. The voltage level (V B ) of the other bit line ( B ) is nearly V CC because electric charge precharged prior to a reading cycle is stored in the stray capacitor existing between the bit line ( B ) and the semiconductor substrate on which the DRAM is integrated. (ii) At time t₁. At time t₁, the voltage level of the precharge signal (PG) becomes high. Then, transistors (T PG1 , T PG2 , T PG3 ) of the precharge circuit (132) become conductive. As a result, the bit lines (B, B ) are precharged to "1". On the other hand, the voltage level of the sense latch signal (SL) is low and the transistor (T SL ) becomes nonconductive. As a result, the two bit lines (B, B ) are electrically separated from the V SS terminal. As shown in Fig. 3, the voltage level (V B ) of the bit line ( B ) drops a little. This change is due to phenomenon that current runs from the bit line ( B ) to the bit line (B) when the transistor (T PG2 ) becomes conductive. When another precharge circuit is used, the voltage level (V B ) may be shown by the broken line in Fig. 3. (iii) At time t₂. Then the voltage level of the precharge signal (PG) becomes low. (iv) At time t3. The voltage level of the word line (W₁) connected to the memory cell (111) changes from "0" to "1". The voltage level of the dummy word line (DW₂) connected to the dummy cell (122) is also changes from "0" to "1". The signal "V W " shown in the Fig. 3 illustrates the voltage level of the cord line (W₁) and that of the dummy word line (DW₂). (v) At time t₄. The word line (W₁) is sufficiently charged to "1". This means that the memory cell (111) is selected. The dummy word line (DW₂) is also sufficiently charged to "1" and the dummy cell (122) is selected too. (Prior to time t₄, the transistor (T d ) becomes conductive and a voltage level of the node between the transistor (T t ) and the capacitor (C') is brought to around V SS .) If leakage current does not flow through the transistor (T t ) of memory cell (111), the voltage level of the drain terminal, which is connected to the capacitor (C), of the memory cell (111) is "V CC -Vth", where Vth is the threshold voltage of the transistor (T t ). On the other hand the voltage level of the source terminal, which is connected to the bit line (B), of the memory cell (111) is kept at V CC . Therefore, the transistor (T t ) remains nonconductive. That is to say, the voltage level (V B ) does not change even though the memory cell (111) is selected. The voltage level of the drain terminal, which is connected to the capacitor (C), of the dummy cell (122) is nearly V SS . On the other hand, the voltage level of the source terminal, which is connected to the bit line ( B ), of the dummy cell (122) is nearly V CC because the bit line ( B ) remains V CC . This means that a potential difference between the drain and gate terminals of the transistor (T t ) of the dummy cell (122) is higher than a threshold voltage of the transistor (T t ) of the dummy cell (122). Therefore, this transistor (T t ) becomes conductive. As a result, precharged electric carrier on the bit line ( B ) is distributed not only by the capacitor (C') of the dummy cell (122) but also by the stray capacitor of the bit line ( B ) . This phenomenon is illustrated by using the following equations under the conditions that "Cp" is the stray capacitor of bit line ( B ) and "V X " is the voltage level of the bit line ( B ) after the distribution. C p (V CC - V SS ) = (C p + C')V X Therefore, The capacitance of the stray capacitor (C p ) is usually ten to hundreds of times larger than that of the capacitor (C') because many memory cells are connected to the bit line ( B ). On the other hand, the capacitance (C') of the dummy cell (122) is usually one half that of the memory cell (111), i.e., C' = C / 2 . Accordingly, Now, is represented by ΔV. Then, It is understood from the above equations that the voltage level of the bit line ( B ) drops by from V CC . (See the solid line at time t₅ in Fig. 3) (vi) At time t₅. The voltage level of the sense latch signal (SL) becomes high. Then the transistor (T SL ) becomes conductive and the sense amplifier (131) starts its operation. The sense amplifier (131) is a differential amplifier including a pair of cross-coupled MOS transistors (T₁, T₂) having a common source and having their gates connected to each other's drain. The transistor (T₂) becomes conductive and the transistor (T₁) does not because the voltage level at the gate terminal of the transistor (T₂) is higher than that of the transistor (T₁). The differential is Then, the voltage level of the bit line ( B ) is brought to V SS prior to time t₆ as shown in Fig. 3. As a result, the potential difference between the two bit lines (B, B ) becomes V CC - V SS . (vii) At time t₆. The voltage levels of the word line (W₁) and the dummy word line (DW₂) becomes V SS . B. Reading Operation under the condition that the memory cell (111) stores "0". Operation at time t₀ through t₃ under the condition that the memory cell (111) stores "0" is almost the same as that under the condition that the memory cell (111) stores "1", and the explanation thereof is therefore omitted. (v) At time t₄. The word line (W₁) is sufficiently charged to V CC and the memory cell (111) is selected. The dummy word line (DW₂) is also sufficiently charged to V CC . And the dummy cell (122) is selected. The voltage level of the drain terminal, which is connected to the capacitor (C) of the memory cell (111) is nearly V SS because the memory cell (111) stores a "0". On the other hand, the voltage level of the source terminal connected to the bit line (B) of the memory cell (111) is V CC because the voltage level of the bit line (B) remains "1". Then, the potential difference between the drain and gate terminals of the transistor (T t ) of the memory cell (111) becomes higher than the threshold voltage of this transistor (T t ), and the transistor (T t ) becomes conductive. Therefore, precharged electric carrier of the bit line (B) is distributed not only by the capacitor (C) of the memory cell (111) but also by the stray capacitor of the bit line (B). This phenomenon is illustrated by using the following equations under the conditions that "C p " is the stray capacitor of the bit line (B), where the values of stray capacitors of the bit line (B) and ( B ) are generally the same), and "V X " is the voltage level of the bit line (B) after the distribution. C p (V CC - V SS ) = (C p + C)V X It is apparent from the above equations that the voltage level of the bit line (B) drops by ΔV from V CC . (See the dotted line at time t₄ in Fig. 3.) Operation of the dummy cell (122) under the condition that the memory cell stores "0" is almost the same as that under the condition that the memory cell stores "1". That is to say, the voltage level of the bit line (B) is dropped by from V CC . (See the dotted line at time t₅ in Fig. 3.) (vi) At time t₅. The voltage level of the sense latch signal (SL) becomes high, and the transistor (T SL ) becomes conductive. Then the sense amplifier (131) starts its operation. The transistor (T₁) becomes conductive and the transistor (T₂) does not because the voltage level of the gate terminal of the transistor (T₁) is higher than that of the transistor (T₂) by the differential amount of Then, the voltage level of the bit line (B) is brought to V SS prior to time as shown in Fig. 3. As a result, the potential difference between the two bit lines (B, B ) becomes (vii) At time t₆. The voltage levels of the word line (W1) and the dummy word line (DW₂) become "0". The capacity of a semiconductor memory like the above DRAM has increased as miniaturisation techniques have advanced. For example, a 1M-bit DRAM is made of small MOS (insulated gate type) transistors whose gates are 1 µm to 1.5 µm long. Moreover, a 4M-bit DRAM which will be developed in the future may be formed of MOS transistors whose gate lengths are reduced to about 0.8 µm, and a 16M-bit DRAM which will be developed in the future may be made of MOS transistors whose gate lengths are reduced to about 0.5 µm. Each memory cell of such a large-capacity DRAM includes two elements, i.e., a capacitor for storing data and a MOS transistor for transfering data as shown in Fig. 4(a). The shorter the gate length and effective channel length of the transfer MOS transistor, the more difficult it is to control the threshold voltage of the MOS transistor due to the short-channel effect and the more ambiguous a boundary line between a gate oxide (141) and a field oxide (142) (see Figure 4(b)) becomes. Consequently, the subthreshold current current of the MOS transistor flows which is too much to be negligible. That is, characteristics of data being stored deterioriate. Fig. 5 shows the characteristics of V g vs. √ I D of a MOS transistor. V g is the gate voltage (V g ) and I d is the drain current (I d ) under the conditions that the transistor gate length is 1.0 µm, the channel length is 0.8 µm, the gate oxide thickness is 15 mm (150 Å), and the substrate density is 5 X 10¹⁵ [cm⁻³]. As shown in Fig. 5, a subthreshold current flows even though V g is 0V. This means that any data stored in a nonselected memory cell disappear due to the subthreshold current. One approach to solve this problem is to refresh the data before the data thoroughly disappears. Indeed, where there is no problem with the subthreshold current, data stored in memory cells is usually refreshed because leakage current runs through the capacitor or through the pn junction. However, where the subthreshold current is a problem and ten to hundreds times as large as the leakage current, data stored in the memory cells need to be refreshed ten to hundreds times as frequently as when overcoming the problem due to the ordinary leakage current. Actually however, it is impossible to refresh so often. Another approach to solve the problem due to the subthreshold current involves ion implantation, where ions of an acceptor impurity are implanted into the channel region of the N-channel transfer transistor and also into the region below this channel region in a high concentration to suppress the subthreshold current or the short-channel effect. If this measure is taken, the effective threshold voltage changes due to the reverse bias effect of the N-channel transistor, the channel mobility of the transistor is deteriorated, or the source-drain junction capacitance of the transistor for transfering data increases (see Fig. 4(a)). Consequently, the capacitance of the stray capacitor will increase. From US-A-4,204,277 it is known for a dynamic read-write random access memory to use MOSFETs. The respective data lines are connected to memory cells, each formed of one transistor and one capacitor with pre-charged transistors and enhancement-type MOS transistors for prevention of an erroneous behaviour of the random access memory. Each data line has a potential deviation prevention device connected to it for preventing the potential of the data line from being deviated from the reference potentials in order to minimise loss of stored content of any of the cells which are not being accessed. Accordingly, this invention seeks to provide a DRAM (dynamic read-write random access memory) comprising a memory cell including switching means and capacitive means connected between one side of the switching means and a voltage supply line; a bit line connected to the other side of the switching means; a word line connected to the control terminal of the switching means; and means for applying to the bit line when the memory is not selected, a voltage level between a first voltage level and a second voltage level; characterised in that the means includes first and second MOS transistors between a voltage supply; a first inverter circuit having an input connected to a junction between the first and second MOS transistors and an output connected to an input of a second inverter circuit which has an output connected to a gate of the second MOS transistor; and a gate of the first transistor connected to one side of the voltage supply and the voltage level applied to the bit line, when the memory is not selected is taken from the junction between the first and second MOS transistors to reduce the flow of leakage current through the switching means to the bit line when the memory cell is not selected. Preferred embodiments of the invention will now be described with reference to the accompanying drawings, wherein: Figure 1 is a circuit diagram of a conventional memory cell having a transistor and a capacitor; Figure 2 is a circuit diagram of a conventional DRAM using a memory cell as shown in Figure 1; Figure 3 is a timing diagram illustrating waveforms representing the operation of the respective parts of the DRAM of Figure 2; Figure 4(a) is a cross-sectional view of the memory cell, as shown in Figure 1, cut along the gate length direction; Figure 4(b) is a cross-sectional view of the memory cell, as shown in Figure 1, cut along the gate width direction; Figure 5 is a graph illustrating the V g vs. I d characteristic of the transistor as shown in Figure 1; Figure 6 is a circuit diagram of a DRAM according to an embodiment of the present invention; Fig. 7, 8 and 9 are circuit diagrams of voltage supply circuits which can be used in the DRAM as shown in the Fig. 6; Fig. 10 is a timing diagram illustrating waveforms representing the operation of the respective parts of the DRAM of Fig. 6; and Fig. 11 is a circuit diagram of a part of a DRAM according to another embodiment of the invention. Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to Fig. 6 thereof, each of memory cells (211, 212, 213, 214, .....) includes a MOS transistor (T t ) and a capacitor (C) connected in series to the transistor (T t ). Gate terminals of memory cells (211, 212, 213, 214, .....) are connected to respective word lines (W₁, W₂, W₃ , W₄, .....). These word lines (W₁, W₂, W₃, W₄, .....) are connnected to an address decoder (not shown). Source terminals of memory cells (211, 212, 213, 214, .....) are respectively connected to one or the other of two bit lines (B, B ). It is preferable that the memory cells (211, 212, 213, 214, .....) are alternately connected to the bit line (B) and the bit line ( B ), for the purpose of balancing stray capacitance associated with the two bit lines. The bit line (B) is connected to a dummy cell (221), and the bit line ( B ) is connected to another dummy cell (222). Each of the two dummy cells includes a voltage supply terminal supplied with one voltage potential V CC , e.g., 5V, a capacitor (C') for storing data and having a first charge terminal connected to the voltage supply terminal and a second charge terminal, a MOS transistor (T t ) for transfering data and having a drain terminal connected to the second charge terminal, a source terminal connected to a respective bit line (B, B ) and a gate terminal, and a MOS transistor (T d ) having a drain terminal connected to a node between the capacitor (C') and the transistor (T t ) and a source terminal connected to a voltage supply terminal supplied with another voltage potential V SS , e.g., OV. The gate terminal of the dummy cell (221) is connected to a dummy word line (DW₁), and the gate terminal of the dummy cell (222) is connected to a dummy word line (DW₂). The dummy cell (221) connected to the bit line (B) is selected when one of the memory cells (212, 214, .....) connected to the bit line ( B ) is selected. Similarly, the dummy cell (222) connected to the bit line ( B ) is selected when one of memory cells (211, 213, .....) connected to the bit line (B) is selected. The two bit lines (B, B ) are connected to a sense amplifier (231) and a precharge circuit (232). The sense amplifier (231) includes a pair of cross-coupled n channel type transistors (T1, T2) having a common source connection and having their gates connected to each other's drain. The drain terminal of the transistor (T₁) is connected to the bit line (B), and the drain terminal of the transistor (T₂) is connected to the bit line ( B ). The common source connection is connected to an output terminal of a voltage supply circuit (241) through a switching transistor (T SL ). The voltage supply circuit (241) is supplied with a voltage potential having a V CC voltage level and with a voltage potential having a V SS voltage level. The circuit (241) supplies a voltage potential having a mid-voltage level (V₁) between V SS and V CC . (V SS < V₁ < V CC ) The mid-voltage level (V₁) is between the voltage levels of the gate and drain terminals of nonselected memory cell. Figs. 7, 8 and 9 show circuits which may be used as the voltage supply circuit of the DRAM shown in Fig. 6. In the voltage supply circuit (241) of Fig. 7, a p-channel MOS transistor (T p ) is connected in series to a diode element (D). The series circuit of transistor (T p ) and diode element (D) is coupled between a V CC power source line (21) and a V SS power source line (22) with the gate of the transistor (T p ) connected to the V SS power source line (22). At the connecting point between the drain of the transistor (T p ) and the anode of the diode element (D), there is obtained the voltage V₁ which is different from the V SS power source potential by the forward voltage drop dV of the diode element (D). This voltage V₁ is output via an output voltage line (23). The voltage supply circuit (241) shown in Fig. 8 is different from the circuit of Fig. 7 only in that two serially connected diode elements (D₁, D₂) are used in place of the diode element (D). In this circuit (241), the value of dV is twice the forward voltage of one diode element. In the voltage supply circuit (241) of Fig. 9, a series circuit composed of a P-channel transistor (T P ) and an N-channel transistor (T N ) is connected between the V CC power source line (21) and the V SS power source line (22). A 2-stage inverter unit made of two CMOS inverters (I₁, I₂) is connected between the node of these transistors (T P , T N ) and the gate of the N-channel transistor (T N ). The gate of the P-channel transistor (T P ) is connected to the V SS power source line (22). The output voltage V₁ obtained at the node of the transistors (T P , T N ) is supplied through an output voltage line (23). When the voltage at this node is lower than the threshold voltage of the first-stage CMOS inverter (I₁), the output of this CMOS inverter (I₁) is equal to the V CC potential and that of the second stage CMOS inverter (I₂) is equal to the V SS potential. As a result, the N-channel transistor (T N ) is turned off. On the other hand, when the voltage at said node is higher than the threshold voltage of the CMOS inverter (I₁), the output of this CMOS inverter (I₁) is equal to the V SS potential and the second-stage CMOS inverter (I₂) is equal to the V CC potential. In this case, the N-channel (T N ) is turned on, whereby the output voltage V₁ becomes equal to the threshold voltage of the CMOS inverter (I₁). The inverters (I₁, I₂) are each formed of a P-channel transistor (T P .) and an N-channel transistor (T N' ). In the examples of the voltage supply circuit (241) shown in Figures 7 and 8, the mid-voltage level (V₁) is decided by the forward voltage drop (usually 0.6 ∼ 0.9) of one or more diodes. On the other hand, in the voltage supply circuit (241) shown in Fig. 9 the mid-voltage level (V₁) is decided by the threshold voltage of the inverter (I₁). A desired value of a mid-voltage level (V₁) is easily obtained when the voltage supply circuit (241) as shown in Fig. 9 is used because the level (V₁) is decided by the threshold voltage. The precharge circuit (232) is composed of a MOS transistor (T PG1 ) connected between the V CC voltage terminal and the bit line (B), a MOS transistor (T PG2 ) connected between the bit line (B) and the bit line ( B ) and a MOS transistor (T PG3 ) connected between the V CC voltage terminal and the bit line ( B ). Gate terminals of the transistors (T PG1 , T PG2 , T PG3 ) are commonly connected to a common gate terminal which is supplied with a precharge signal (PG). There will now be described by reference to Fig. 6 and Fig. 10 the operation of the DRAM as shown in Fig. 6. A. Reading Operation under the condition that the memory cell (211) stores a "1". (i) At time t₀. Voltage levels of all of the word lines (W₁, W₂, W₃, W₄, .....) and all of the dummy word lines (DW₁, DW₂) are V SS , e.g., OV. All of the transistors of the memory cells (211, 212, 213, 214, .....) and the dummy cells (221, 222) are nonconductive and none of the cells (211, 212, 213, 214,....., 221, 222) is selected. The voltage level of the precharge signal (PG) is low and the precharge circuit (232) does not yet operate. The voltage level of the sense latch signal (SL) is high and the sense amplifier (231) is operating. The sense latch signal (SL) is supplied to the gate terminal of the transistor (T SL ). The voltage level (V B ) of the bit line (B) is V₁ because the sense amplifier (231) is a flip-flop type differential amplifier. The voltage level (V B ) of the other bit line ( B ) is nearly V CC because electric charge precharged prior to a reading cycle is stored in the stray capacitor existing between the bit line ( B ) and the semiconductor substrate on which the DRAM is integrated. (II) At time t₁. At time t₁, the voltage level of the precharge signal (PG) becomes high. Then, transistors (T PG1 , T PG2 , T PG3 ) of the precharge circuit (232) become conductive. As a result, the bit lines (B, B ) are precharged to "1". On the other hand, the voltage level of the sense latch signal (SL) is low and the transistor (T SL ) becomes non-conductive. As a result, the two bit lines (B, B ) are electrically separated from the output terminal of the voltage supply circuit (241). As shown in Fig. 10, the voltage level (V B ) of the bit line ( B ) drops a little. This change is due to phenomenon that current runs from the bit line ( B ) to the bit line (B) when the transistor (T PG2 ) becomes conductive. When another precharge circuit is used, the voltage level (V B ) may be shown by the broken line in Fig. 10. (iii) At time t₂. Then the voltage level of the precharge signal becomes low. (iv) At time t₃. The voltage level of the word line (W₁) connected to the memory cell (211) changes from "0" to "1". The voltage level of the dummy word line (DW₂) connected to the dummy cell (222) also changes from "0" to "1". The voltage level "V W " shown in Fig. 10 illustrates the voltage level of the word line (W₁) and that of the dummy word line (DW₂). (v) At time t₄. The word line (W₁) is sufficiently charged to "1". This means that the memory cell (211) is selected. The dummy word line (DW₂) is also sufficiently charged to "1", and the dummy cell (222) is selected too. (Prior to time t₄, the voltage level of the node between the transistor (T t ) and the capacitor (C') is brought to around V SS .) If leakage current does not flow through the transistor (T t ), the voltage level of the drain terminal, which is connected to the capacitor (C) of the memory cell (211) is "V CC -Vth", where Vth is the threshold voltage of the transistor (T t ). On the other hand, the voltage level of the source terminal which is connected to the bit line (B) of the memory cell (211) is kept at V CC . Therefore, the transistor (T t ) of cell (211) remains nonconductive. That is to say, the voltage level (V B ) does not change even though the memory cell (211) is selected. The voltage level of the drain terminal, which is connected to the capacitor (C), of the dummy cell (222) is nearly V SS . On the other hand, the voltage level of the source terminal, which is connected to the bit line ( B ), of the dummy cell (222) is nearly V CC because the bit line ( B ) remains V CC . This means that the potential difference between the drain terminal of the transistor (T t ) and the gate terminal of the transistor (T t ) is higher than the threshold voltage of the transistor (T t ) of the dummy cell (222). Therefore transistor (T t ) of cell (222) becomes conductive. As a result, precharged electric carrier on the bit line ( B ) is distributed not only by a capacitor (C') of the dummy cell (222) but also by the stray capacitance of the bit line ( B ). This phenomenon is shown by using the following equations under the conditions that "C p " is the stray capacitance of bit line ( B ) and "V X " is the voltage level of the bit line ( B ) after the distribution. C P (V CC - V₁) = (C P + C')V X Therefore, The capacitance of the stray capacitor (C P ) is usually ten to hundreds of times larger than that of the capacitor (C') because many memory cells are connected to the bit line ( B ). On the other hand, the capacitance (C') of the dummy cell (222) is usually one half that of the memory cell (211) i.e., C' = C / 2. Accordingly, When is represented by ΔV, then, It is understood from the above equations that the voltage level of the bit line ( B ) drops by (See the solid line at time t₅ in Fig. 10.) (vi) At time t₅. The voltage level of the sense latch signal (SL) becomes high. Then the transistor (T SL ) become conductive and the sense amplifier (231) starts its operation. The sense amplifier (231) is a differential amplifier formed by a pair of cross-coupled MOS transistor (T₁, T₂) having a common source and having their gates connected to each other's drain. The transistor (T₂) becomes conductive and the transistor (T₁) does not because the voltage level of the gate terminal of the transistor (T₂) is higher than that of the transistor (T₁). Then the voltage level of the bit line ( B ) is brought to V₁ prior to time t₆ as shown in Fig. 10. As a result, the potential difference between the two bit lines (B, B ) becomes (V CC - V₁). (vii) At time t₆. The voltage levels of the word line (W₁) and the dummy word line (DW₂) becomes V SS . B. Reading Operation under the condition that the memory cell (211) stores a "0". Operation at time t₀ through t₃ under the condition that the memory cell (211) stores "0" is almost the same as that under the condition that the memory cell (211) stores "1", and the explanation thereof is therefore omitted. (v) At time t₄. The word line (W₁) is sufficiently charged to V CC and the memory cell (211) is selected. The dummy word line (DW₂) is sufficiently charged to V CC ' too, and the dummy cell (222) is selected. The voltage level of the drain terminal, which is connected to the capacitor (C) of the memory cell (211) is nearly V₁ because the memory cell (211) stores a "0". On the other hand, the voltage level of the source terminal connected to the bit line (B) of the memory cell (211) is V CC because the voltage level of the bit line ( B ) remains a "1". Then, the potential difference between the drain and gate terminals of the transistor (T t ) of the memory cell (211) becomes higher than the threshold voltage of the transistor (T t ) of the memory cell (211), and this transistor (T t ) becomes conductive. Therefore, pre-charged electric charge of the bit line (B) is distributed not only by the capacitor (C) of the memory cell (211) but also by the stray capacitance of the bit line (B). This phenomenon is shown by using the following equations under the conditions that "C P " is the stray capacitance of the bit line ( B ), it being understood that the values of stray capacitance of the bit line (B) and ( B ) are generally same, and that "V X " is the voltage level of the bit line (B) after the distribution. C P (V CC - V₁) = (C P + C)V X It is apparent from the above equations that the voltage level of the bit line (B) drops by ΔV from V CC , as is shown by the dotted line at time t₅ in Fig. 10. Operation of the dummy cell (222) under the condition that the memory cell stores a "0" is almost the same as that under the condition that the memory cell stores a "1". That is to say, the voltage level of the bit line ( B ) is dropped by from V CC , as is shown by the dotted line at time t₅ in Fig. 10. (vi) At time t₅. The voltage level of the sense latch signal (SL) becomes high, and the transistor (T SL ) becomes conductive. Then the sense amplifier (231) starts its operation. The transistor (T₁) becomes conductive and the transistor (T₂) does not because the voltage level of the gate terminal of the transistor (T₁) is higher than that of the transistor (T₂) by a differential amount equal to Then, the voltage level of the bit line (B) is brought to V₁ prior to time t₆ as shown in Fig. 10. As a result, the potential difference between the two bit lines (B, B ) becomes (vii) At time t₆. The voltage levels of the word line (W₁) and the dummy word line (DW₂) become a "0". A key feature of this embodiment of the present invention is that the lower voltage level applied to the bit line (i.e. V₁) is a level between V CC and V SS , whereas the lower voltage level applied to the bit line in the conventional DRAM is V SS . In this embodiment, V₁ is 0.6 V. Therefore, the actual gate voltage (V G ) of the memory cell (211), i.e., the voltage level of the gate terminal relative to that of the source terminal, is "V SS - V₁" equals - 0.6, i.e, V G = -0.6 V. As shown in Fig. 5, no subthreshold current flows at V G = -0.6 V. Therefore data-dissipation from the memory cell due to the subthreshold current does not take place according to this embodiment of the invention. Further, more frequent refreshing to prevent data from dissipating due to the subthreshold current is not required. That is to say, an ordinary refresh-cycle can be used in the embodiment. Further, an ion implantation as explained using Fig. 4(a) and Fig. 4(b), under the channel region of the transistor for transfering data is not required. Thus, the impurity concentration in the area under the channel region can be kept low when ions are not implanted there. Therefore the stray capacitance can be made small in this embodiment. In this embodiment, the sense amplifier (231) and the dummy cells (221, 222) are used. However, the invention can be used in a memory which does not use the sense amplifier (231) and the dummy cells (221, 222). Also, one reference voltage potential source of the sense amplifier (231), being connected to the bit line ( B ), might be used instead of the dummy cell (222). The voltage level of such a reference voltage potential is, for example, about Fig. 11 shows a circuit diagram of a part of a DRAM according to another embodiment of the invention. In this embodiment, the DRAM has a plurality of pairs of bit lines (B, B ), and a plurality of sense amplifiers as shown in Fig. 6. Each of the amplifiers is connected to a corresponding pair of bit lines (B, B ). The sense amplifiers each have commonly connected source terminals, which are connected to an output terminal of the voltage supply circuit (241) through a switching transistor (T SL ). The other parts of this embodiment are the same as those of the first embodiment. In this embodiment, only one voltage supply circuit (241) is required. That is to say, smaller numbers of transistors are required in this embodiment. In the each of the embodiments, the transistors (T t ) for transfering data and transistors (T₁, T₂) of the sense amplifier are N-channel type MOS transistors. These transistors may be replaced by P-channel type MOS transistors. In this case, the same advantages as achieved by the above embodiments are obtained only by reversing the reference potentials of the elements.

Claims: A dynamic read-write random access memory comprising: a memory cell (211 - 214) including switching means (Tt) and capacitive means (C) connected between one side of the switching means and a voltage supply line; a bit line (B, B ) connected to the other side of the switching means; a word line (W₁ - W₄) connected to the control terminal of the switching means (Tt); and means (241) for applying to the bit line (B, B ), when the memory is not selected, a voltage level between a first voltage level and a second voltage level; characterised in that the means (241) includes first and second MOS transistors (T p, T n ) between a voltage supply; a first inverter circuit (I₁) having an input connected to a junction between the first and second MOS transistors (T p , T n ) and an output connected to an input of a second inverter circuit (I₂) which has an output connected to a gate of the second MOS transistor (T n ); and a gate of the first MOS transistor (T p ) connected to one side of the voltage supply and the voltage level applied to the bit line, when the memory is not selected, is taken from the junction between the first and second MOS transistors (T p , T n ) to reduce the flow of leakage current through the switching means (Tt) to the bit line when the memory cell is not selected. A dynamic read-write random access memory as claimed in claim 1, characterised in the provision of means for detecting a change of voltage level of the bit line when the memory cell is selected. A dynamic read-write random access memory as claimed in claim 1 or 2, characterised in that there is a second memory cell (211, 214) including second switching means (Tt) having a control terminal through which operation of the switching means is controllable, and a second capacitive means (C) connected between one side of the switch means (Tt) and a supply voltage, a second bit line (B, B ) connected to the other side of the second switching means (Tt), and a second word line (W₁ - W₄) connected to the control terminal of the second switching means (Tt), whereby, when one voltage level is applied to the second word line (W₁ - W₄), the second memory cell is selected and, when another voltage level is applied, the second memory cell is not selected; and a differential amplifier including a pair of cross-coupled MOS transistors (T₁, T₂) having drains, respectively, connected to the first bit line and the second bit line, a common source connection, and respective gates connected to the drain of the other MOS transistor of the pair; and wherein the voltage applying means applies the voltage level to one A dynamic read-write random access memory as claimed in claim 3, characterised in that there is a switching transistor (TSL) connected between the common source connection of the MOS transistors (T₁, T₂) of the differential amplifier and an output terminal of the voltage level applying means, the switching transistor (TSL) being rendered conductive when the first memory cell (211, 214) is selected; a first dummy cell connected to the first bit line; a second dummy cell connected to the second bit line; and pre-charge means for pre-charging the first and second bit lines.

Inventors: UCHIDA, YUKIMASA C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: G11C11
IPC codes: G11C11