METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING AN IMPLANTATION STEP

Abstract: A method of manufacturing a semiconductor device involves the step of carrying out the implantation of an impurity in the main plane of a GaAs substrate (31) for the simultaneous formation of a plurality of regions (35, 36). When the angles formed with the perpendicular implanta­ tion of silicon ions in the GaAs main plane and the main orientations of GaAs substrate are expressed by the Euler angles (λ, µ, ϑ), then the crystal orientation is so prescribed as to satisfy the following conditions: 11° < λ < 33° 7° < µ < 24° ϑ ≒ 0°, thereby suppressing the occurrence of channeling in the implantation of ions in the substrate main plane and conse­ quently ensuring substantially uniform impurity concentra­ tion in the plural regions.

Description: This invention relates to a method of manufacturing a semiconductor device involving the step of impurity ion implantation. When a semiconductor device is manufactured, the well-known process is one which involves the step of implanting impurity ions in a substrate to fabricate a layer of a prescribed conductivity type. In the case of, for example, a GaAs integrated circuit, an active layer is produced in a semiconductor substrate by ion implantation to provide source and drain regions of high impurity concentration. Due to the high integration and increased speed of operation of semiconductor devices, greater demand is made for the precise control of ion implantation. When a layer of a prescribed conductivity type is formed by ion implantation, it sometimes happens that a channelling phenomenon appears, in which an impurity ion is implanted to a greater depth in a particular direction of implantation depending on the structure of a single crystal substrate. It is of course known, in other contexts, to cut a substrate at an angle to the (100) plane, as disclosed in FR-A-2084089. With a semiconductor single crystal substrate whose surface is parallel to the (100) plane, however, it is known that when the implantation of an impurity is carried out perpendicular to the substrate, axial channelling takes place because crystal lattices are widely separated from each other. The phenomenon of channelling becomes more noticeable as the constituent atoms of the substrate, and ions to be implanted have a larger atomic number, and the acceleration voltage for ion implantation decreases. When, therefore, an activated layer is made thinner for higher integration, the channelling more readily takes place. The conventional practice to avoid such a drawback, as disclosed for example in Solid State Technology 28 No. 2, p. 163 [1985], is to incline the major substrate surface by some degrees to the ion implantation direction in order to avoid axial channelling, and further, to rotate the substrate about the surface normal axis several or scores of degrees, thereby avoiding plane channelling. The conventional method of manufacturing semiconductor devices mentioned before is also accompanied with the following drawbacks. Since ion beams enter obliquely into the substrate surface, the mask material gives rise to shades, causing the patterns to be asymmetric and resulting in variation in the properties of the element devices thus produced. Moreover, difficulties arise in estimating the area ion implantated from the mask size. The smaller the pattern becomes for high integration, the more the drawbacks increase. Since the respective positions on the substrate have different separations from the ion source, said positions are electrically charged to different degrees by an ion beam-accelerating electric field, thus causing ions to be implanted with different densities. Consequently variations appear in the properties of the element devices formed on the substrate. Moreover, some ion-implanting devices do not allow the substrate rotation angle to be freely defined. When, therefore, such an ion-implanting device is used, it is impossible to produce highly reliable semiconductor devices. Therefore, the rotation angle of the substrate plane has to be determined for each substrate, requiring a great deal of work. The above-mentioned difficulties particularly arise in a semiconductor device having an extremely fine circuit arrangement, for example, a high speed digital IC or a high frequency analog IC fabricated by forming an MESFET on a GaAs single crystal substrate. It is accordingly the object of this invention to provide a method of manufacturing a semiconductor device which suppresses the occurrence of channelling when a plurality of regions are simultaneously formed in a monocrystalline, semiconductor substrate; by implantation of an impurity; and which substantially equalizes the impurity concentrations of the respective regions, thus significantly facilitating the mask of ion implantation. We acknowledge that JP-A-60733 (1985) discloses a substrate-cutting and implantation process in which a GaAs substrate is cut at an angle to the (100) plane such that, in terms of the Euler angles defined between the principal crystal axes and the normal to the cut major surface to the implanted, the angle λ = 45° ± 3° and the angle µ = 7° ± 3°. However, this results in a significant reduction in machinability of the substrate. The semiconductor device-manufacturing method of this invention is defined in Claim 1. If λ falls outside of the above-mentioned range, plane channelling appears, and if λ exceeds 33°, as in JP-A-60733 (above), the subject semiconductor monocrystalline substrate will be undesirably reduced in machinability. If µ is displaced from the above-mentioned range, then axial channelling will appear. Also if µ rises above 24°, the monocrystalline semiconductor substrate will undesirably decrease in machinability. The present invention offers the advantages that even when an impurity is perpendicularly implanted in a monocrystalline semiconductor substrate, no channelling occurs, dispensing with the troublesome task of defining the rotation angle of the substrate; when an ion implanter lacking a rotation angle-defining mechanism is applied, it is nonetheless possible to carry out ion implantation under a well-controlled condition; when an impurity is implanted perpendicularly to the main substrate plane, the implanted impurity does not present asymmetry and variations in the distribution within said substrate plane; an equal potential is preserved throughout the substrate plane; an impurity can be implanted under a well controlled condition; it is possible to provide a semiconductor device whose excellent elements indicate no variations in the properties on the substrate plane; and consequently a highly integrated semiconductor device can be provided. This invention can be more fully understood from the following detailed description of embodiments thereof, by way of example only, when taken in conjunction with the accompanying drawings, in which: Fig. 1 illustrates an ingot by way of indicating the relationship between the crystal orientation in which the substrate used in the embodiment of this invention is cut out and the direction in which an impurity is implanted in the substate; Fig. 2 is a chart setting forth the Euler angles; Figs. 3A to 3G show the sequential steps of manufacturing GaAs-MESFET embodying this invention; and Fig. 4 indicates a comparison between the threshold voltage variations observed in a semiconductor device manufactured by the method utilized in this invention and those appearing in a semiconductor device obtained by the conventional manufacturing method. Description may now be made which reference to the accompanying drawings of the method of manufacturing a semiconductor device GaAs MESFET utilized in this invention. Fig. 1 sets forth the relationship between the crystal orientation in which a gallium arsenide (GaAs) substrate is cut out in accordance with the method of this invention and the direction in which an impurity is implanted. Referring to Fig. 1, reference numeral 11 shows a GaAs ingot, and reference numeral 12 indicates an orientation flat formed on a (011) face. When an impurity is implanted in a GaAs substrate 13 cut out of said ingot 11 by the conventional method, as previously mentioned, ion implantation direction 14 is inclined to a (100) face at prescribed angle β (= 7°) in order to suppress the occurrence of axial channelling, and further the plane of said GaAs substrate 13 is rotated at angle α (= 20°) in order to avoid plane channelling. Unlike the above-mentioned conventional method, the embodiment of this invention applies the method of cutting out semiconductor monocrystalline substrate 15 from GaAs ingot 11 in such a manner that the substrate's major surface is inclined to the indicated (100) face at a prescribed angle as later described. Namely, the major surface of said GaAs substrate is so defined as to suppress the occurrence of axial and plane channellings in ion implantation direction 14. Concrete description may now be made by the Euler angles of the range within which angle inclination to the (100) face of the GaAs substrate is defined by the embodiment of this invention. The Euler angles (λ,µ,ϑ,) are generally indicated as shown in Fig. 2. Namely, angles (0°,0°,0°) represented by the equation λ=µ=ϑ=0° are plotted on axes X, Y, Z. It was assumed that under the above-mentioned conditions, the ion implantation direction was represented by axis Z, and the angles defined by the ion implantation direction with the main crystal axis were denoted by λ, µ, ϑ. Further, it was assumed that the size of an atom at a crystal lattice point was represented by 1/10 of the lattice spacing. First, the plane involving said λ, µ and ϑ is rotated counterclockwise about the Z axis by an angle of λ. At this time, line X is shifted to X₁, and line Y is moved to Y₁. Thereafter, said plane is rotated counterclockwise about line X₁ by an angle of µ. As a result, line Y₁ is shifted to Y₂, and line Z is moved to Z₂. Further, said plane is rotated counterclockwise about line Z₂ by an angle of ϑ. At this time, line X₁ is shifted to X₃, and line Y₂ is moved to Y₃. Computation was made as to the pattern which would be presented by a crystal lattice. Measurement was made of the angles which would not cause the lattice points to overlap each other three-dimensionally. As a result, the following conditions were ascertained. 11° < λ < 33° 7° < µ < 24° ϑ ≒ 0° In actuality, a GaAs substrate was prepared whose major surface represented the aforesaid crystal orientation. A silicon (Si⁺) impurity ion was implanted under the conditions: Acceleration voltage 150 keV Impurity doping dosage 3 x 10¹²/cm² Thus, numerous diode alleys were formed and determination was made of the manner in which the peak carrier concentration was distributed. As a result, it was found that said concentration fell within the range of 3 %. When Euler angle λ ranged between 21° and 26°, and Euler angle µ ranged from 10° to 11°, said peak carrier concentration was less than 1 %. Electronic line analysis clarified that the above-mentioned ranges represented the ion implantation direction in which the occurrence of defect of ion implantation was minimized. When a GaAs substrate whose Euler angles were defined to fall within the aforementioned range was cut out of an ingot, it was found that axial and plane channelling were effectively prevented when an impurity was implanted perpendicularly to the main plane of said GaAs substrate. The present invention offers further advantages that since an impurity can be implanted perpendicularly to the major substrate surface, the impurity implanting process is simplified and can be carried out under tightly controlled conditions; though the cleavage plane constituted by (110) face of the GaAs monocrystalline is susceptible to impacts and fractures readily, yet the major surface of said GaAs crystal is shifted from said (100) face at a prescribed angle in order to suppress the occurrence of channelling, said cleavage plane is not rendered perpendicular to the substrate major surface, thereby improving the impact strength of the subject GaAs-MESFET. Description may now be made with reference to Figs. 3A to 3G of the method of manufacturing the GaAs-MESFET utilized in this invention. Thoughout the figures, reference numeral 31 represents a monocrystalline semiconductor substrate prepared from gallium arsenide (GaAs). The substrate is cut out of an ingot in such a manner that the major surface of said substrate represents a crystal orientation in which Euler angles λ, µ and ϑ respectively denote 21°, 11° and 0°, and thereafter said major surface is polished. An ion implantation mask is provided on said major surface of the GaAs substrate 31 by means of a first photoresist layer 32a. Next, a silicon (Si⁺) impurity is implanted perpendicularly into the major surface of the substrate under the conditions: Acceleration Voltage 150 keV Doping Dosage 3 x 10¹²/cm² As a result, an n type conductivity layer 33 is deposited on the major surface of the substrate. Thereafter, the first resist layer 32a is removed from the major surface of the substrate. Heat treatment is continued at 850°C for 15 minutes to activate said n-type conductivity layer 33. Thereafter tungsten nitride layer 34 is deposited with a thickness of 100 nm (1000Å) over the phase surface of substrate 31 as indicated in Fig. 3B. A second photoresist layer 32b is formed on said tungsten nitride layer 34. A gate electrode-forming mask is provided by etching said second photoresist layer 32b except for that portion thereof which lies on the central portion of said n-type layer 33. Later as shown in Fig. 3C, gate electrode 34 is mounted on the n-type conductivity layer by reactive ion etching (RIE) by means of the aforementioned mask. Then said second photoresist layer 32b is removed from gate electrode 34. Then third photoresist layer 32c is formed all over the fabricated mass. That portion of said photoresist layer 32c which is mounted on said n-type layer is eliminated to provide a mask open to the MESFET forming region. Thereafter as shown in Fig. 3D, silicon is ion implanted by means of said mask perpendicular to the major surface of the substrate under the conditions: Acceleration voltage 180 keV Doping Dosage 2 x 10¹³/cm² to provide source and drain regions 35, 36 both of n⁺-type. Later said third photoresist layer 32c is eliminated, and silicon oxide (SiO₂) layer 37 is deposited with a thickness of about 500 nm (5000Å) by chemical vapor deposition (CVD) all over the fabricated mass (Fig. 3E). The whole mass is heat treated at 800°C for 15 minutes to activate the silicon constituting the source and drain regions. Later SiO₂ layer 37 is removed from the substrate. A fourth resist layer 32d is formed on that part of the substrate which is now rendered vacant by the removal of said SiO₂ layer 37. Those portions of said fourth resist layer 32d which were deposited on said source and drain regions are eliminated to form a mask open to the region for drawing out the source and drain electrodes. Later, as shown in Fig. 3F, a gold germanium alloy (AuGe) layer 150 nm (1500Å) thick is formed, and then gold (Au) is thermally deposited on said AuGe layer. Thus an AuGe/Au layer is formed all over the fabricated layer. Later, fourth photoresist layer 32d, together with that portion of said AuGe/Au layer which is deposited thereon, is removed (lift off step). Last, heat treatment is applied at 400°C for 2 minutes to provide source and drain ohmic electrodes, thereby finishing the GaAs-MESFET method used in this invention. The foregoing description was made of the process seemingly for manufacturing a single FET unit. In fact, however, a large number of FETs are formed on the substrate at the same time, as can be easily inferred. Measurement was made of threshold voltages Vth of the numerous GaAs-MESFETs of this invention simultaneously fabricated on the same substrate, the results being set forth in the coordinate system of Fig. 4. The ordinate represents the threshold voltages Vth and the abscissa denotes the diameter of the wafer. The circular plotted points (·) show the measured threshold voltages of the MESFET representing the invention, and the cross-shaped plotted points (x) represent the threshold voltages of an FET unit fabricated by including the wafer by 7 degrees in the ion implantation direction and further rotating the wafer lane by 210 degrees (corresponding to the conventional process). The pattern of the coordinate system of Fig. 4 clearly indicates that the threshold voltage of all the MESFETs manufactured by the method of this invention substantially stands at -4.0 volts, whereas noticeable variations appear in the threshold voltage of the MESFETs provided by the conventional process. The above-mentioned noticeable merit of the present invention arises from the fact that the source and drain regions of the elements fabricated by the method of this invention have a substantially uniform impurity concentration, no matter where said regions are formed in the substrate wafer. In the foregoing embodiment, the MESFET was prepared for a monocrystalline GaAs substrate having the structure of sphalerite. However, the present invention is not limited to this instance. Namely, the same effect can be ensured by fabricating any monocrystalline substrate having a diamond structure such as that prepared from Si, Ge or InP. Further, not only silicon, but also any other impurities known to this particular field, for example, S, Se, Mg, are adapted for ion implantation.

Claims: A method of manufacturing a semiconductor device comprising preparing a monocrystalline semiconductor substrate having a diamond or sphalerite structure and implanting an impurity in a major surface thereof (31) for the simultaneous formation of a plurality of regions (35, 36), the implantation being in a direction perpendicular to the major surface, characterized in that the substrate is prepared such that, when the angles formed between two Cartesian coordinate systems, the Z-direction of one of said coordinate systems coinciding with the said perpendicular direction and the Z-direction of the other of said coordinate systems coinciding with the <100> crystal direction of said substrate are expressed by the Euler angles (λ, µ, ϑ), then: 11° < λ < 33° 7° < µ < 24° and ϑ ≒ 0°, thereby suppressing the occurrence of axial and planat channelling in the implantation process. A method according to claim 1, characterized in that the angles which the Euler angles satisfy the following: 21° < λ < 26° 10° < µ < 11° and ϑ ≒ 0°. A method according to claim 1 or 2, characterized in that said single crystal substrate is prepared from semiconductor gallium arsenide. A method according to claim 3, characterized in that said impurity is silicon.

Inventors: FUKUDA, KATSUYOSHI PATENT DIV. K.K. TOSHIBA, MIKAMI, HITOSHI PATENT DIV. K.K. TOSHIBA, YASUAMI, SHIGERU PATENT DIV. K.K. TOSHIBA
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: H01L21
IPC codes: H01L21, H01L29