SEMICONDUCTOR MEMORY DEVICE HAVING READ-MODIFY-WRITE CONFIGURATION

Abstract: A semiconductor memory device having a read-modify-­ write (RMW) configuration suitable for modifying a large number of data with high speed and a simple circuit. The RMW configuration includes a data input and output circuit (11, 14, 16) for simultaneously storing or reading a plurality of data into or from the memory cells (MC), a data output circuit (10, 12, 13) for serially reading a plurality of data from the memory cells, and a data modification circuit (15) for successively receiving the plurality of data from the data output circuit, modifying the received data in a predeter­ mined logical operation and transmitting the modified data to the data input and output circuit.

Description: The present invention relates to a semiconductor memory device, more particularly, to a semiconductor memory device for performing high speed read-modify-write (hereinafter referred to as RMW) operations on a large amount of data. Demand has arisen for effectively writing image data in or reading image data from an image processing memory or the like and for effectively performing a high-speed RMW operation, i.e., the storage contents are read out from the memory, the read out data is modified, and the modified data is restored in the memory. A typical RMW application is exemplified by color inversion for inverting a color currently displayed on a display unit in a given relationship, and by pattern emphasis for emphasizing a specific pattern. A conventional RMW scheme is applied in such a manner that data is read out by using an RMW function of a dynamic-random access memory (D-RAM) device, the read out data is modified by an external circuit, and the modified data is restored in the corresponding memory cell. However, the conventional RMW scheme requires a relatively long processing time defined by the operating cycle of the D-RAM device, resulting in inconvenience. WO-A-82/2615 discloses a semiconductor memory device in accordance with the precharacterising portions of the accompanying claims 1, 2 and 4. EP-A-0 056 240 discloses a memory device for performing digital delay processing, which allows serial access mode operation wherein the memory contents of part or a whole row of cells are read out sequentially. A shift register is arranged parallel to a column decoder for performing such a serial readout, and the column decoder is operable to select the point along the shift register where readout is to begin. Neither of the above documents discloses a semiconductor device for performing high-speed RMW operations. According to one aspect of the present invention, there is provided a semiconductor memory device comprising:- a random access memory cell array including a plurality of memory cells; and register means comprising at least one register circuit array and a data input and output circuit for parallel data transfer between the register circuit array and said memory cells, and further comprising a serial data input and a serial data output; characterised in that:- said register means comprise a first register circuit array for reading data from said memory cells, and a second register circuit array for writing data to said memory cells; data modification means are provided for modifying, in a predetermined logical operation, data from the serial data output of said register means; the serial data output of the register means being connected to an input of the data modification means via transfer means, and an output of the data modification means being connected to the serial data input of the register means; whereby, in use, data transfer from and to said register means can be carried out simultaneously to effect a high-speed read-modify-write operation. According to a second aspect of the invention, there is provided a semiconductor memory device comprising:- a random access memory cell array including a plurality of memory cells; and register means comprising a register circuit array and a data input and output circuit for parallel data transfer between the register circuit array and said memory cells, and further comprising a serial data input and a serial data output; characterised in that:- data modification means are provided for modifying, in a predetermined logical operation, data from the serial data output of said register means, the serial data output of the register means being connected to an input of the data modification means via transfer means and an output of the data modification means being connected to the serial data input of the register means; and in that said transfer means comprise an output gate array, a pointer register circuit array and a data bus, the output gate array comprising gates connected between respective register circuits of the register means and said data bus and controlled by said pointer register circuit array; whereby, in use, data transfer from and to said register means can be carried out simultaneously to effect a high-speed read-modify-write operation. According to a development of the second aspect of the invention, there is provided a semiconductor memory device, wherein the data modification means comprises a plurality of modification circuits provided in parallel, and wherein the register means is in the form of a plurality of shift registers provided one or more for each respective modification circuit, each modification circuit having individual data transfer means connecting it to its respective shift register, whereby high-speed read-write-modify operations may be carried out in parallel by each modification circuit. According to a third aspect of the invention there is provided a semiconductor memory device comprising:- a random access memory cell array including a plurality of memory cells; and register means comprising a register circuit array and a data input and output circuit for parallel data transfer between the register circuit array and said memory cells; characterised in that:- data modification means are provided for modifying, in a predetermined logical operation, data from said register circuit array; said register circuit array is an array of latches each operable to supply data to a first data bus and to receive data from a second data bus, said first and second data buses being connected to an input and an output of said data modification means, respectively, via data transfer means; said data transfer means comprising a first array of gates, having gates in a one-to-one correspondence with said latches, for transferring data from the latches to said first data bus under control of a control register array, and a second array of gates having gates in a one-to-one correspondence with said latches, for transferring data from said second data bus to said latches under control of said control register array; whereby, in use, data transfers from and to said array of latches can be carried out simultaneously to effect a high-speed read-modify-write operation. An embodiment of the present invention can provide a semiconductor memory device for performing a high-speed RMW operation of a large amount of data for selected memory cells. The device may include a circuit for designating a predetermined range of data output from the data output circuit and data restore in the data input and output circuit, to perform a predetermined range of data modification. Reference is made, by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention; Fig. 2 is a circuit diagram of shift registers in the device shown in Figure 1; Fig. 3 is a timing chart for explaining the operation of the shift registers shown in Fig. 2; Fig. 4 is a circuit diagram of a modifying circuit in the device shown in Fig. 1; Fig. 5a to 5c are circuit diagrams showing modifications of the circuit of Fig. 4, respectively; Fig. 6 is a block diagram of a semiconductor memory device according to another embodiment of the present invention; Fig. 7 is a circuit diagram showing connections between the shift register and a data bus in the device shown in Fig. 6; Fig. 8 is a timing chart for explaining the operation of the circuit arrangement shown in Fig. 7; Fig. 9 is a circuit diagram of pointer shift registers in the device of Fig. 6; Fig. 10 is a timing chart for explaining the operation of the registers shown in Fig. 9; Fig. 11 is a circuit diagram showing a mnodification of the device shown in Fig. 6; Figs. 12 and 14 are block diagrams of semiconductor memory devices according to still other embodiments of the present invention; and Fig. 13 is a block diagram of a semiconductor memory device not according to the present invention. Figure 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention. The semiconductor memory device in Fig. 1 has a plurality of dynamic RAM (D-RAM) cells (MC) 1 arranged in a matrix form, a row decoder 5 for selecting word lines WL₀ to WL₂₅₅ of the memory cells in response to row address signals RA₀ to RA₇ , a sense amplifier array 2 of sense amplifiers SA₀ to SA₂₅₅ connected to bit lines BL₀ to BL₂₅₅ and BL₀ to BL₂₅₅ , a gate array 3 including 256 gates, a column decoder 4 for selecting one of the gates constituting the gate array 3 in accordance with column address signals CA₀ to CA₇ , a data bus DB connected to one gate of the gate array 3 which is selected by the column decoder 4, and an I/O amplifier 25 connected to the data bus DB. This arrangement is the same as a conventional D-RAM configuration. The same operation as in a conventional D-RAM device can be also applied to the semiconductor memory device of the first embodiment. It should be noted that the D-RAM device of the first embodiment has a memory capacity of 64 kbits (= 256 bits x 256 bits). The semiconductor memory device in Fig. 1 further has a data read shift register array 12 including 256 series-connected shift registers SRA₀ to SRA₂₅₅ connected to the bit lines BL₀ to BL₂₅₅ through a first transfer gate array 10 including 256 transfer gates, and a data write shift register array 14 having 256 series-connected shift registers SRB₀ to SRB₂₅₅ and connected to the bit lines BL₀ to BL₂₅₅ through a second transfer gate array 11 including 256 transfer gates. An output amplifier 13 is connected to the read shift register array 12. An output signal S OUT from the output amplifier 13 is supplied together with a modifying input signal S IN from a central processor unit (CPU), not shown, to a modifying circuit 15. An output signal from the modifying circuit 15 is supplied to the write shift register array 14. A typical example of the read and write shift registers SRA₀ to SRA₂₅₅ and SRB₀ to SRB₂₅₅ of Fig. 1 is a two-phase ratio type shift register as shown in Fig. 2. A timing chart of the two-phase ratio type shift register is illustrated in Fig. 3. In the shift register SR₂ , a value at a node N₁₄ of the preceding step of the shift register SR₁ is transferred as master data, and a transistor Q₂₂ is turned ON in response to a clock pulse P₁ to receive the master data in a node N₂₁. When a voltage level at the node N₂₁ is set at logic "1", the level at a node N₂₂ is inverted. In order to perform a slave transfer, a transistor Q₂₆ is turned ON in response to a clock pulse P₂ to set the level at a node N₂₃ to be equal to that at the node N₂₂. The signal level at a node N₂₄ is inverted in accordance with the signal level at the node N₂₃. Therefore, the data can be shifted bit by bit in each shift register. The operation of the semiconductor memory device in Fig. 1 will be described hereinafter. The D-RAM side is asynchronized with the shift register side and may be operated independently thereof. The D-RAM can be accessed in a conventional manner. At the same time, when the D-RAM is held in a nonaccess mode, an RMW operation can be performed in the following manner. In the RMW mode, a transfer instruction TR and a read instruction R/W = 0 are supplied to a transfer clock driver 16, and the driver 16 generates a clock signal T CLKA . The transfer gate array 10 is turned ON in response to the clock signal T CLKA , so that data, on the bit lines BL₀ to BL₂₅₅ connected to the accessed word line WL i , is simultaneously supplied to the read shift register array 12. The data in the shift register array 12 is then consecutively read as an output signal S OUT by the output amplifier 13, supplying the read signal S OUT to the modifying circuit 15. As shown in Fig. 4, the modifying circuit 15 for example includes an amplifier 151 for amplifying the input signal S IN , an OR gate 152 for producing a logical OR of the signals S IN and S OUT , and an amplifier 153 for amplifying an output from the OR gate 152. The original signal as the signal S OUT is logically ORed with the input signal S IN in the circuit of Fig. 4. However, the data modification is not limited to a logic sum (OR), but can be extended to a logic product (Fig. 5a), a logical exclusive OR (Fig. 5b) or a simple inversion (Fig. 5c) and so on. The modified signal is stored in the write shift register array 14. When the modified signals are loaded in to all the shift registers, the transfer instruction TR and the write instruction R/W = 1 are supplied to the transfer clock driver 16. The gate array 11 is turned ON in response to the clock signal T CLKB from the driver 16. The contents in the shift register array 14 are stored in the memory cells connected to the above-mentioned word line WL i . In this case, when the data in the memory cells is to be used for only display, an output amplifier (not shown) connected to the end stage SRB₂₅₅ of the shift register array 14 may serially output the data to be displayed on the display unit while the gate array 11 is kept OFF. As described above, a simultaneous high-speed RMW operation can be performed for memory cells connected to a given word line. In the above embodiment, two shift register arrays are used for the RMW operation. The semiconductor memory devices mentioned above perform an RMW operation for all shift registers (all bit lines). In general, however, an RMW operation is desired to be performed for desired bit lines. An embodiment suitable for this application will be described hereinafter. Figure 6 shows an arrangement of a semiconductor memory device according to a second embodiment of the present invention. Reference numeral 100 denotes a circuit corresponding to the D-RAM device (Fig. 1) including the memory cell array 1, the sense amplifier array 2, the gate array 3, the column decoder 4, the row decoder 5, and the I/O amplifier 25 so as to schematically show the connections between the respective components with the bit lines in units of columns. A shift register array 21a is connected to the bit lines BL₀ to BL₂₅₅ through a transfer gate array 20a including 256 transfer gates. The output terminals of the shift register array 21a are connected to the corresponding input terminals of an output gate array 22a including 256 gates, i.e., transistors. The drains of the transistors of the output gate array 22a are connected to a data bus DB. The data bus DB is connected to a modifying circuit 25a. A pointer shift register (PSR) array 23a is arranged to control the respective gates of the output gate array 22a. A column decoder 24a is arranged to set a value in the pointer shift register array 23a. Each shift register in the shift register array 21a may be the same as that shown in Fig. 3. One arrangement representing the connections between the shift registers SR₁ and SR₂ , the output gate 22a, and the PSR₁ and PSR₂ is shown in Fig. 7. The timing chart of the arrangement of Fig. 7 is shown in Fig. 8. The data is shifted bit by bit in response to the clock signals P1 and P2 in the same manner as in the first embodiment. According to the second embodiment, in addition, the contents in the shift registers appear on the data bus DB consisting of data buses SDB and SDB in response to a pointer instruction signal PO i from the pointer shift register array 23a. Figure 9 is a circuit diagram of part of an example pointer shift register array 23a. The n-th pointer shift register PSR n consists of a depletion-type transistor Q₅₆ and enhancement-type transistors Q₅₇ and Q₆₀ to Q₆₅. Other pointer shift registers are applied (constructed) in the same way. Figure 10 illustrates waveforms of a clock signal T CLK1 for driving the pointer shift register array 23a. The clock pulse signal T CLK1 shown in Fig. 10 for driving the pointer shift registers includes a first pulse PE and a second pulse NPE, which are phase-shifted by 180° from each other. The operation of the pointer shift registers will now be described. First, when the pulse PE is high level, it is assumed that an output SL n-1 at the (n-1)-th pointer shift register PSR n-1 is high level or logical "1", and all other outputs SL₀ to SL n-2 and SL n to SL₂₅₅ are low level or logical "0". Due to the application of a high level voltage of the output SL n-1 , the transistor Q₆₄ in the n-th pointer shift register PSR n is turned ON, with a resultant charging-up of a node SP n to a high level. By applying a high level signal at the node SP n to a gate of a transistor Q₇₅ in the pointer shift register PSR n-1 , the transistor Q₇₅ is turned ON, resulting in a low level at the node SP n-1 . The states at the node SP n and SP n-1 are maintained as is when the pulse PE becomes low. When the pulse NPE becomes high, the transistors Q₆₂ and Q₇₂ are turned ON, applying a high level signal at the node SP n to a gate of the transistor Q₆₀ and a low level signal at the node SP n-1 to a gate of the transistor Q₇₀. The signals applied to the respective gates of the transistors Q₆₀ and Q₇₀ are maintained if the pulse NPE becomes low. Again, by applying a pulse PE having a high level to the pointer shift registers PSR n and PSR n-1 , the signal levels at nodes SL n and SL n-1 are respectively rendered high and low. As a result, unique "1" bit data (a single "1" bit) is transferred from the pointer shift register PSR n-1 to the adjacent pointer shift register PSR n . The transistors Q 73A and Q 73B prevent the application of a high voltage to a gate of the transistor Q₇₀ , to securely maintain the node SL n-1 at the-low level. As the gate of the transistor Q₆₀ is supplied with a sufficiently high voltage, the gate voltage of the transistor Q 63B is rapidly rendered to the low level together with the change of the node SL n to a high level. The transistors Q₅₆ , Q₅₇ , and Q₆₁ in the pointer shift register PSR n and the transistors Q₆₆ , Q₆₇ , and Q₇₁ are used for preventing malfunctions which may arise due to the floating signal level, i.e., low level, because many nodes SL are low level. The depletion transistors Q₅₆ and Q₆₆ may be replaced by resistors. By applying one clock signal T CLK1 consisting of the pair of pulses PE and NPE to the pointer shift register array 23a, 1 bit data held in one pointer shift register is transferred to the next pointer shift register and that one pointer shift register is reset. This is successively effected in response to application of the clock signal T CLK1 . The pointer shift registers PSR₀ to PSR₂₅₅ feature a unique "1" bit shift therein. In this embodiment, an arbitrary amount (number of bits) of serial data appearing on the bit lines between the first bit line BL₀ and n-th bit line BL n-1 can be successively output via the shift registers SR₀ to SR n-1 and via the gate 22a, one of which (at a time) is selected in response to the unique "1" bit shift in the pointer shift register array 23a. Via the selected gate 22a, output data successively appear on the data bus DB, which may be output to the exterior of the device via an output amplifier (not shown) so that serial data for a display unit can be obtained. Alternatively, n-th pointer register PSR n-1 may be set at logic "1" and held thereat while a desired number of shifts of the shift register array 21a is carried out. This operation also brings about serial data output of the desired number of bits via the data bus DB, but in a reverse direction in the data shift. A modification circuit 25a may be the same as one of the types of modifying circuit described above. The RMW operation of the semiconductor memory device according to the second embodiment in Fig. 6 will be described hereinafter. When a transfer instruction TR is set at logic "1", the gate array 20a is turned ON in response to a clock signal T CLK from the transfer clock driver 26a, so that the data are simultaneously transferred from 256 memory cells defined by the predetermined word line and the bit lines BL₀ to BL₂₅₅ to the register array 21a. In one preferred mode of RMW operation, an output from an arbitrary one of the pointer shift registers PSR₀ to PSR₂₅₅ is set at logic "1", and the output gate connected to the "1" holding shift register of the register array 21a is turned ON, while data in the shift registers SR₀ to SR n-1 is shifted by one bit in response to the clock pulse (not shown). At the same time, the output from the shift register SR n-1 appears on the data buses SDB and SDB . The data on the data buses SDB and SDB as reference data is modified by the modifying circuit 25a together with the input signal S IN . In the next cycle, the modified value is stored in the shift register SR₀ , and at the same time the data in the shift registers SR₀ to SR n-2 is shifted to the shift registers SR₁ to SR n-1 , so that the content of the shift register SR n-2 appears on the data buses SDB and SDB . The same modification operation as described above is performed for n bits. In another mode of RMW operation, one of the pointer shift registers PSR₀ to PSR₂₅₅ is set at logic "1" and both the shift register arrays 21a and 23a are shifted synchronously. By this operation, n shift registers SR₀ to SR n-1 are made to store the same data which is a result of the modification of the initially accessed data by the one pointer register by the input signal S IN , with the number n corresponding to the number of shifts. The modified contents need not be restored in the memory cells to update the contents thereof but can be supplied from the shift register array 21a to another device. As may be apparent from the above description, a high-speed RMW operation can be performed for a predetermined range of 1st to nth bit lines BL₀ to BL n-1 , and the row decoder can be controlled to perform the RMW operation within a predetermined range of word lines. In the above embodiment, data on the first to n-th bit lines are modified. However, any modification range of n₁-th to n₂-th bit lines can be selected. Still another embodiment of the present invention is shown in Fig. 11. In the circuit of Fig. 11, the shift register array 21a in Fig. 6 is replaced with an set-reset (R-S) flip-flop array. More specifically, instead of the shift register, a latch circuit 27b consisting of a flip-flop 273, an OR gate 271, and an inverter 272 is used together with gates 22b and 28b associated with the latch circuit 27b. In operation, the contents of memory cells on a bit line BL i are read out and stored in the flip-flop 273 through a gate 20a and the OR gate 271. An output Q of the flip-flop 273 is extracted by a pointer instruction PO i from the pointer shift register PSR i onto the data bus DB through the gate 22a. The data on the data bus DB is modified by the modifying circuit 25a. The modified content (data) is stored in a flip-flop 273 through the gate 22b and the OR gate 271. The output Q of the modified and stored content is stored in the memory cell connected to the bit line BL i through the gate 28b in response to the clock signal T CLKB . In order to increase the RMW operation speed, an n-parallel RMW arrangement is shown in Fig. 12. The connection between the circuit of Fig. 12 and the memory cell array 100 is the same as described above. However, in order to perform the n-parallel RMW operation, n data buses DB-1 to DB-n and n modifying circuits 25-1 to 25-n are arranged. Furthermore, n pointer register arrays 23-1 to 23-n can be operated in parallel with n register arrays 21-1 to 21-n. The pointer register arrays 23-1 to 23-n and the register arrays 21-1 to 21-n may be shift registers or flip-flops. The modifying circuits 25-1 to 25-n may each be the same as the modifying circuit 15 of Fig. 1. The modifying circuit may include a circuit as shown in Figs. 4 and 5a to 5c or others. The circuits shown in Figs. 4 and 5a to 5c can be selectively used to perform various RMW operations. Devices for performing RMW operations for memory cells (m x n) of a specific area are shown in Figs. 13 and 14, respectively. The circuit in Fig. 13 has a gate array 31 consisting of gates Q₀ to Q₅₁₁ each having one end connected to a corresponding one of bit lines BL O to BL₅₁₁ , a latch array 32 consisting of data latches DL₀ to DL₅₁₁ each having one end connected to the other end of the corresponding gates Q₀ to Q₅₁₁ , a gate array 33 consisting of gates Q A0 to Q A511 each connected to the other end of the corresponding data latches DL₀ to DL₅₁₁ , and a shift register array 34 consisting of shift registers SR₀ to SR₅₁₁ for controlling the gates of the gate array 33. The gate array 33 is connected to the data bus DB to which the modifying circuit 25a is connected. In this device the memory cell array has a 512 x 512 matrix, and other arrangements of the circuit are the same as those of the previous circuit. The operation of the circuit shown in Fig. 13 will be described. When the memory cell (DRAM) side is not accessed, a specific word line WL j is selected by the row decoder 5. When a clock signal  S is enabled, all the gates Q₀ to Q₅₁₁ of the gate array 34 are turned ON, so that the contents of the memory cells connected to the word line WL j are transferred to the data latches DL₀ to DL₅₁₁ through the bit lines BL₀ to BL₅₁₁ and the gates Q₀ to Q₅₁₁. The clock signal  S is disabled after the above-mentioned data transfer period. Thereafter, the memory cells can be accessed. Among the contents latched by the data latches DL₀ to DL₅₁₁ , the contents of specific registers for the shift register array 34, e.g., SR i to SR i+n are subjected to the RMW operation. The shift registers SR₀ to SR i-1 are kept OFF in response to signals CL₀ to CL i-1 from the column decoder 24a, and the outputs from the shift registers SR₀ to SR i-1 are kept OFF. Therefore, the gates Q A0 to Q A(i-1) are kept off, and the contents of the data latches DL₀ to DL i-1 are left unchanged. The shift registers SR i to SR i+n are sequentially turned ON in response to the signals CL i to CL i+n from the column decoder 24a. The gates Q Ai to Q A(i+n) are sequentially turned ON in response to the ON outputs CL i to CL i+n . In this case, the input data D in is supplied to the data bus DB, and the contents modified by the modifying circuit 25a are sequentially latched by the data latches DL i to DL i+n . The data latches DL i+n+1 to DL₅₁₁ and DL₀ to DL i-1 store the contents of the memory cells without modification. The modified contents within the range of bit lines BL i to BL i+n for the word line WL j are held in the data latches DL i to DL i+n , while other latches store the contents of the memory cells without modification. In this state, the clock signal  S is enabled for a predetermined period of time while the memory cells are not accessed. The gate array 31 is turned ON, and the contents of the data latch array 32 are stored in the memory cells connected to the word line WL j . The modified contents can be stored in the memory cells within the range of bit lines BL i to BE i+n . Other memory cells hold the previous data. The same operations are performed for the word lines WL j+l to WE j+m , and thus high-speed RMW operation can be performed for the specific memory cell area (m x n). Figure 14 shows an embodiment wherein the gate array 33 in Fig. 13 includes a gate array 35 consisting of gates Q B0 to Q B511 connected to an input data bus DB(I) and a gate array 33 consisting of gates Q A0 to Q A511 connected to an output data bus DB(O). The contents of the memory cells temporarily transferred to data latches DL₀ to DL₅₁₁ are modified by the modifying circuit 25a together with the input data D in within the specific range of i to i+n, and the modified contents are latched by the data latches DL₀ to DL₅₁₁. The modified contents can be stored in the memory cells during the nonaccess mode of the memory cell array in the same manner as described above. In this circuit, high-speed RMW operation can be performed for the memory contents for the specific memory cell area (m x n), and the contents of other memory cell areas can be left unchanged.

Claims: A semiconductor memory device comprising:- a random access memory cell array (1) including a plurality of memory cells; and register means comprising at least one register circuit array (12, 14) and a data input and output circuit (10, 11) for parallel data transfer between the register circuit array and said memory cells, and further comprising a serial data input and a serial data output; characterised in that:- said register means comprise a first register circuit array (12) for reading data from said memory cells, and a second register circuit array (14) for writing data to said memory cells; data modification means (15) are provided for modifying, in a predetermined logical operation, data from the serial data output of said register means; the serial data output of the register means being connected to an input of the data modification means (15) via transfer means (13), and an output of the data modification means (15) being connected to the serial data input of the register means; whereby, in use, data transfer from and to said register means can be carried out simultaneously to effect a high-speed read-modify-write operation. A semiconductor memory device comprising:- a random access memory cell array (100) including a plurality of memory cells; and register means comprising a register circuit array (21a; 21-1, ...21-n) and a data input and output circuit (20a; 20-1, ...20-n) for parallel data transfer between the register circuit array and said memory cells, and further comprising a serial data input and a serial data output; characterised in that:- data modification means (25a; 25-1, ...25-n) are provided for modifying, in a predetermined logical operation, data from the serial data output of said register means (21a; 21-1, ...21-n), the serial data output of the register means being connected to an input of the data modification means (25a; 25-1, ...25-n) via transfer means (22a, 23a, DB; 22-1, ...22-n, 23-1, ...23-n, DB-1 , ...DB-n), and an output of the data modification means being connected to the serial data input of the register means (21a; 21-1, ...21-n); and in that said transfer means comprise an output gate array (22a; 22-1, ...22-n), a pointer register circuit array (23a; 23-1, ...23-n) and a data bus (DB; DB-1, ...DB-n), the output gate array comprising gates connected between respective register circuits of the register means (21a; 21-1, ...21-n) and said data bus and controlled by said pointer register circuit array (23a; 23-1, ...23-n); whereby, in use, data transfer from and to said register means (21a; 21-1, ...21-n) can be carried out simultaneously to effect a high-speed read-modify-write operation. A semiconductor memory device according to claim 2, wherein the data modification means comprises a plurality of modification circuits (25-1, ...25-n) provided in parallel, and wherein the register means is in the form of a plurality of shift registers (21-1, ...21-n) provided one or more for each respective modification circuit, each modification circuit having individual data transfer means (22-1, ...22-n, 23-1, ...23-n, DB-1, ...DB-n) connecting it to its respective shift register, whereby high-speed read-write-modify operations may be carried out in parallel by each modification circuit. A semiconductor memory device comprising:- a random access memory cell array including a plurality of memory cells; and register means comprising a register circuit array (32) and a data input and output circuit (31) for parallel data transfer between the register circuit array and said memory cells; characterised in that:- data modification means (25a) are provided for modifying, in a predetermined logical operation, data from said register circuit array (32); said register circuit array (32) is an array of latches each operable to supply data to a first data bus (DB (o) ) and to receive data from a second data bus (DB (1) ), said first and second data buses being connected to an input and an output of said data modification means (25a), respectively, via data transfer means; said data transfer means comprising a first array of gates (33), having gates in a one-to-one correspondence with said latches (32), for transferring data from the latches (32) to said first data bus (DB (o) ) under control of a control register array (34), and a second array of gates (35) having gates in a one-to-one correspondence with said latches (32), for transferring data from said second data bus (DB (1) ) to said latches under control of said control register array (34); whereby, in use, data transfers from and to said array of latches (32) can be carried out simultaneously to effect a high-speed read-modify-write operation. A semiconductor memory device according to any preceding claim, wherein said data input and output circuit (10, 11; 20a; 20-1, ...20-n; 31) comprises at least one set of gates, the gates being connected between respective memory cell selection lines (BL) of the memory cell array (1, 100) and said register circuit array and controlled in common by a gate drive circuit (16; 26a; 26). A semiconductor memory device according to any preceding claim, wherein the data modification means (15; 25a; 25-1 to 25-n; 25a) includes a logical operation circuit for performing a logical operation upon one bit data. A semiconductor memory device according to any preceding claim, wherein the registers of the register means are in the form of one or more shift registers (12, 14; 21a; 21-1, ...21-n). A semiconductor memory device according to any of claims 1 to 6, wherein the registers of the register means are constituted by flip-flops (32). A semiconductor memory device according to claim 1, wherein:- said data input and output circuit comprises a set of first gates (10) controlled in common by a gate drive circuit (16); a first register circuit array (12) is constituted by a plurality of registers connected in series; a terminal of each of said first gates (10) being operatively connected to a corresponding memory cell selection line (BL) and another terminal thereof being connected to a corresponding one of said first registers (12); in a data transfer mode, each of said first registers (12) being operable independently of each other, said gate drive circuit simultaneously driving said plurality of first gates (10) to simultaneously store a plurality of data of said memory cells into said first registers (12); in a data output mode, said first registers (12) being operable serially to successively output stored data therein to said transfer means (13). A semiconductor memory device according to claims 2, 3 or 4, wherein the data transfer means (22a, 23a, DB; 22-1, ...22-n, 23-1, ...23-n, DB1, ...DB-n; 33, 35, 34, DB (o) , DB (1) ) is provided with selecting means (23a; 23-1, ...23-n; 34) operable to select a subset of the registers of the register means, to perform the read-modify-write operation on the data of a predetermined range of memory cells. A semiconductor memory device according to claim 2 or 3, wherein said pointer register circuit array (23a; 23-1, ...23-n) is provided by a shift register which is controlled by a decoder (24a, 24) so as to successively activate the gates of the output gate array (22a; 22-1, ...22-n) in response to a command decoded at said decoder.

Inventors: OGAWA, JUNJI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G11C7
IPC codes: G11C11, G11C7