LOGIC CIRCUIT WITH FREQUENCY DIVIDER APPLICATION

Abstract: A logic circuit for use in a variable frequency divider (8) includes a driver (T1, T2), a latch (T3, T4), and an enabling switch (T5, T6) each comprising a pair of emitter coupled transistors. The driver (T1, T2) is coupled to the latch (T3, T4), and the emitters of the transistors of the enabling switch (T5, T6) are coupled to a current source (T9). A collector of each of the transistors of the enabling switch (T5, T6) is coupled to a respective pair of emitters of the latch or the driver. The collector of one of the transistors (T6) of the enabling switch (T5, T6) is coupled to the emitters of either the driver (T1, T2) or the latch (T1, T4) via a control switch (6), or the control switch (6) is coupled between the driver (T1, T2) and the current source (T9). The control switch (6) enables the elimination of external gating arrangements in variable frequency dividers. A variable frequency divider (8) may be constructed from one or more of the logic circuits in combination with one or more flip-flops. The division ratio of the variable frequency divider can be varied in dependence upon a signal (X1) applied to the control switch (6).

Description: Logic circuit with frequency divider application. This invention relates to logic circuits, and in particular, logic circuits for use in variable frequency dividers. A known type of logic circuit for use in a variable frequency divider takes the form of a clocked flip-flop as illustrated in Figure 1 of the accompanying drawings. Such a flip-flop comprises a driver, a latch, and an enabling switch each of which comprises a pair of emitter coupled transistors. A collector of each transistor of the driver is coupled to a collector of a respective transistor of the latch. Further, the emitters of the driver and the latch are each coupled to a respective collector of a respective transistor of the enabling switch, and the emitters of the enabling switch are coupled to a current source. A variable frequency divider may include two serially connected pairs of such flip-flops, each pair being arranged to operate as a D-type bistable incorporating the well known master/slave principle of operation. An example of such a variable frequency divider is illustrated in Figure 3 of the accompanying drawings. In this divider, an output of one of the D-type bistables is connected to an input of the other D-type bistable via an external gating arrangement. The division ratio of the frequency divider may be changed by applying a signal to the external gating arrangement. Variable frequency dividers which employ such external gating arrangements are disadvantageous in that the operating speed of the divider is slow. Further, such dividers consume relatively more power when operating at a given speed, that is, when being clocked at a given frequency. It is an aim of the present invention to provide a logic circuit which, when used in a variable frequency divider, enables elimination or at least reduction of external gating arrangements associated therewith thereby alleviating the above-mentioned disadvantages. According to the present invention there is provided a logic circuit including a driver, a latch, and an enabling switch each comprising a pair of emitter coupled transistors, wherein the driver is coupled to the latch, and wherein the emitters of the transistors of the enabling switch are coupled to a current source, a collector of each of the transistors of the enabling switch is coupled to a respective pair of emitters of the latch or driver, characterized in that the collector of one of the transistors of the enabling switch is coupled to the emitters of either the driver or the latch via a control switch. There may be provided a second driver, comprising a pair of emitter coupled transistors, coupled in parallel with the first driver. In this case, the emitters of the transistors of the first driver and the second driver are respectively coupled to the collector of said one of the transistors of the enabling switch via the control switch. In one embodiment of the present invention the control switch may comprise a pair of emitter coupled transistors. For example, the collector of one of the transistors of the control switch may be coupled to the emitters of either the driver or the latch, the collector of the other transistor of the control switch may be coupled to the collector of one of the transistors of the driver and one of the transistors of the latch, and the emitters of the transistors of the control switch may be coupled to the collector of one of the transistors of the enabling switch. In the case where the second driver is provided, the collector of one of the transistors of the control switch is coupled to the emitters of the first driver and the collector of the other transistor of the control switch is coupled to the emitters of the second driver. According to the present invention there is also provided a logic circuit including a driver, a latch, and an enabling switch each comprising a pair of emitter coupled transistors, wherein the driver is coupled to the latch, and wherein the collector of one of the transistors of the enabling switch is coupled to the emitters of the latch, the collector of the other transistor of the enabling switch is coupled to the emitters of the driver, and the emitters of the transistors of the enabling switch are coupled to a current source, characterized in that a control switch comprising a transistor is coupled between the driver and the current source, wherein the collector of the transistor is coupled to the collector of one of the transistors of the driver and the emitter of the transistor is coupled to the current source. The control switch may comprise a second transistor coupled to said transistor of the control switch thereby to form a pair of emitter coupled transistors. The second transistor may be coupled between the emitters of the enabling switch and the current source, the collector of the second transistor being coupled to the emitters of the enabling switch and the emitter of the second transistor being coupled to the current source. The control switch may include a second pair of emitter coupled transistors, in which the collector of one of the transistors of the second pair is coupled to the collector of one of the transistors of the first pair of emitter coupled transistors, and the collector of the other one of the transistors of the second pair is coupled to the emitters of each transistor of the first pair. The control switch may alternatively comprise a third transistor, the emitter of which is coupled to the emitters of the emitters of the pair of emitter coupled transistors of the control switch, and the collector of the third transistor is coupled to the collector of one of the transistors of the pair of emitter coupled transistors. A variable frequency divider may be constructed by including at least one logic circuit embodying the present invention. The division ratio of the variable frequency divider may be variable in dependence upon a signal applied to the control switch of the or one of the logic circuits. A pair of logic circuits which embody the present invention may be coupled together to form a gating stage of a variable frequency divider. In this case, the division ratio of the variable frequency divider may be varied in dependence upon a signal applied to the control switch of one of the pair of logic circuits. The variable frequency divider may be constructed by coupling the gating stage to a pair of clocked flip-flops arranged to operate as a D-type bistable incorporating the master/slave principle of operation. The use of such logic circuits in variable frequency dividers is advantageous in that external gating arrangements may be eliminated or at least reduced. This in turn enables the frequency divider to operate at a greater speed (i.e. greater clocking frequencies can be employed) whilst consuming less power. Hence, such logic circuits ar^≥ particularly advantageous when used in power conscious devices such as hand held receivers which use synthesis tuning and which must be continuously powered. The present invention will now be further described by way of example, with reference to the accompanying drawings, in which like reference numerals designate like elements, and in which: Figure 1 shows a circuit diagram of a flip-flop which forms part of a D-type bistable; Figure 2 shows a truth table of the flip-flop of Figure 1; Figure 3 is a block diagram of a variable frequency divider incorporating an external gating arrangement; Figure 4 shows a truth table of the divider of Figure 3; Figures 5a to 5c each show an alternative arrangement of control circuit for a logic circuit according to the present invention; Figure 6a shows a circuit diagram of a logic circuit according to one embodimejat of the present invention; Figure 6b shows a circuit diagram of a logic circuit according to another embodiment of the present invention; Figure 6c shows a circuit diagram of a logic circuit according to a further embodiment of the present invention; Figure 6d shows a circuit diagram of a logic circuit according to a further embodiment of the present invention; Figure 7a shows a truth table of the logic circuit of Figure 6a; Figure 7b shows a truth table of the logic circuit of Figure 6b; Figure 7d shows a truth table of the logic circuit of Figure 6d; Figure 8a is a block diagram of a variable frequency divider incorporating a pair of logic circuits according to the present invention; Figure 8b shows a truth table of the divider of Figure 8a when incorporating a pair of the logic circuits of Figure 6a; Figure 8c shows a truth table of the divider of Figure 8a when incorporating a pair of the logic circuits of Figure 6d; Figure 9a is a block diagram of a variable frequency divider when incorporating two of the logic circuits of Figure 6b; Figure 9b shows a truth table of the divider of Figure 9a when incorporating two of the logic circuits of Figure 6b; Figure 10a is a block diagram of a variable frequency divider when incorporating a logic circuit of Figure 6c; and Figure 10b is a truth table of the variable divider of Figure 10a. Figure 1 shows a circuit diagram of a known type of clocked flip-flop which comprises an emitter coupled pair of driver transistors T-_ and 2- each base of which is connected to respective driver input terminals D-_ and D ] _, an emitter coupled pair of latch transistors T3 and T respectively connected to latch output terminals Q-_ and Q]_. an enabling switch comprising a pair of emitter coupled transistors T5 and Tg respectively connected to clock inputs CK and CK, a pair of buffer transistors T7 and Tβ and a current source transistor T9. When a clock signal is applied to the clock inputs CK and CK, the transistor T5 is switched off for one half of the clock cycle during which time the transistor Tg is switched on, and the complement occurs during the second half of the clock cycle. Consequently, the driver pair T^ and T2 are enabled in antiphase with the latch pair T3 and T4 once per clock cycle. During one half of the clock cycle, the driver pair τ_ and T 2 are enabled (i.e. Tg is switched on due to a logical '1' being applied to the clock input CK), and the latch pair T3 and 4 are disabled. During this half cycle the latch outputs Q ] _ and " θ_ respectively take the values applied to the driver input terminals D j _ and D-_ (refer to the truth table shown in Figure 2). During the second half of the clock cycle, the transistor T 5 is switched on, the latch pair 3 and are enabled, and the latch outputs Q ] _ and Ql are therefore latched in their previous state. Figure 3 shows a variable frequency divider 1 which comprises two pairs of clocked flip-flops 2 which are serially connected as shown. Each pair 2 operates as a D-type bistable according to the well known master/slave principle, in which, the value (either '1' or '0') which sits on the driver input terminal D j _, on a defined edge of the clock signal applied to the clock input terminals CK and CK, gets transferred to the latch output terminal Q 2 nd then held or latched. For simplicity, the driver input terminals D-_/ D 2 and the latch output terminals Q-_/ Q 2 have been omitted from Figure 3. The latch output Q 2 of one of the flip-flop pairs 2 is connected to the driver input D^ of the other flip-flop pair 2 via an external gating arrangement which comprises an AND gate 3 and a NOR gate 4. One terminal of the AND gate 3 is connected to a control signal input terminal X-_ to which a control signal is applied for varying the division ratio of the frequency divider 1. In Figure 4, a truth table of the frequency divider 1 of Figure 3 is shown. From the truth table, it can be seen that when a logical '0' is applied to the control signal input terminal X-_, the divider 1 has a division ratio of 2, and when a logical 'I 1 is applied to the terminal X-_, the division ratio is 3, since the gating arrangement introduces an extra delay in the divide by 2 mode. Referring now to Figures 5a to 5c, there are shown alternative forms of control circuit 6 which may be incorporated into logic circuits embodying the present invention. The control circuit 6 of Figure 5a comprises a pair of emitter coupled transistors T-_g an< ^ τ ll* Tne base electrodes of the transistors τ ll are connected to control inputs X ] _ and " X * τ_ respectively. The control circuit 6 of Figure 5b comprises a pair of emitter coupled transistors T ] _ and T^3 and a second pair of emitter coupled transistors -_4 and Tτ_5« The base electrodes of the first pair of transistors j _ and ^3 are connected to the control inputs X-_ and Y_ respectively, and the base electrodes of the second pair of transistors T-_4 and T^5 are connected to control inputs Y and T. The collector of the transistor T-_ 2 is connected to the emitter electrodes of the second pair of transistors Tχ4 and -_ $ and the collector of the transistor ] _3 is connected to the collector of the transistor τ 15 * A third type of control switch 6 is shown in Figure 5c. This control switch 6 comprises a pair of emitter coupled transistors T ] _g and -_7, the base electrodes of which are connected to control inputs Y and ~Y " respectively. A third transistor T-_s is provided, the collector being connectec? to the collector of the transistor ^ -j r the emitter being connected to the emitter electrodes of the transistors T-_g and -_7, and the base electrode being connected to the control input Υ_ - Any one of the above described control switches 6 may be incorporated into a logic circuit according to the present invention. Examples of such logic circuits will be described below. Referring to Figure 6a, there is shown a logic circuit according to a preferred embodiment of the present invention which comprises the driver pair of transistors T-_ and T , the latch pair of transistors T_ and T4, the enabling switch transistors T5 and Tg, the buffer transistors T7 and Tg, and the current source Tg as illustrated in the flip-flop of Figure 1. This logic circuit also comprises a control switch 6 which, in this example, comprises the pair of emitter coupled transistors TJ ^ O and j _-_, which are coupled between the driver pair T j _ and T 2 and the transistor Tg of the enabling switch. As .can be seen from Figure 6a, the collector of the transistor J_ Q is connected to the collector of the transistor T]_ of the driver pair, the collector of the transistor T-_-_ is connected to the emitters of the transistors τ_ and T 2 and the emitters of the control switch transistors T_Q and Tτ_-_ are connected to the collector of the enabling switch transistor Tg. The base electrodes of the control switch 6 transistors J_Q and ]_ι are connected to control inputs Xj and X^ respectively. The control switch transistors T ] _ Q and Tτ_-_ may alternatively be coupled between the latch pair 3 and T and the transistor T5 of the enabling switch (not shown). In this case, the collector of the transistor Tg is connected to the emitters of the driver pair T-_ and T 2 , the collector of the control switch Tτ_j_ is connected to the emitters of the latch pair T3 and T4, and the emitters of the control switch T-_Q and Tτ_-_ are connected to the enabling switch transistor T5. The logic circuit of Figure 6a has a truth table as shown in Figure 7a. Here, it can be seen that when the logic circuit is in a driving state (that is, when there is a logical 'l 1 on the clock input C " κ) , and there is a logical •I 1 on the control input X-_, then the latch output Q3 is a logical *0' regardless of the logical value at the driver inputs D 3 and " E3 since the transistor Tτ_n is switched on (the symbol * in the truth table denotes that the value may be logical '1' or 'O'). An alternative form of logic circuit embodying the present invention is shown in Figure 6b. This is shown to comprise the control switch 6 of Figure 5a although the control switch of Figure 5b or 5c could alternatively be included. In this logic circuit, the collector of one of the transistors of the control switch 6 is connected to the collector of either the transistor Tι_ of the driver and the transistor T3 of the latch or the collector of the transistor T of the driver and the transistor T4 of the latch via a further driver which comprises a pair of emitter coupled transistors T-_g and T 2 n« The base electrodes of the transistors Tτ_9 and T 2 Q are connected to driver inputs D4 and D^ respectively. In this embodiment, the control switch 6 is operative for selecting whether the driver inputs D3, " S3 or D4, " D4 are used as inputs into this logic circuit (see the truth table of Figure 7b). In an alternative embodiment of the present invention, the control switch 6 of Figure 5b may be incorporated between the transistor Tg of the enabling switch and the driver transistors T ] _ and T 2 . Such an arrangement is shown in Figure 6c where it can be seen that the collector of the transistor T± of the second pair is connected to the collector of the transistor T ] _, the collector of the transistor T^5 is connected to the emitters of the transistors T j _ and T , and the emitters of the transistors T-_ 2 and -_3 of the first pair are connected to the transistor Tg of the enabling switch. In Figure 6d, a further logic circuit embodying the present invention is shown. In this case, the control switch 6, which comprises a pair of emitter coupled transistors T T _Q and T~_± , is coupled between the enabling switch 5 and Tg and the current source Tg. The collector of the transistor T-_-_ is connected to the emitters of the enabling switch T5 and Tg, the emitters of the control switch 6 are connected to the collector of the current source transistor T9, the collector of the transistor TJ_ Q is connected to the collector of the drive transistor T~_ , and the base electrodes of the transistors T^Q, T H °f th e coupling switch 6 are respectively connected to the control input terminals X^ and " x^. Figure 7d shows the truth table of the logic circuit of Figure 6d. In the embodiment shown in Figure 7d, the control switch transistor T-_-_ may be omitted and in its place, the emitters of the enabling switch Tg and T 5 may be directly connected to the current source transistor Tg- The control switch 6 of Figure 6d may be substituted for either of the control switches 6 of Figures 5b and 5c (not shown) . The logic circuits embodying the present invention may be coupled with each other and/or coupled with one or more flip-flops 2 (such as the one described with reference to Figures 1 and 2) to form a gating stage of a variable frequency divider. Figure 8a shows a variable frequency divider 8 in which the pair of flip-flops 2 is connected to a gating stage 10. The gating stage 10 comprises a pair of the logic circuits described with reference to Figure 6a. For simplicity, some of the complementary inputs and outputs have been omitted from Figure 8a. Further, although the two logic circuits of the gating stage 10 have driver inputs labelled D3, D4, control inputs labelled X-_/ X 2 , and latch outputs labelled Q3 and Q4, the circuits themselves are as illustrated in Figure 6a and have the truth table shown in Figure 7a. The gating stage 10 is connected to the pair of flip-flops 2 as shown in Figure 8a. The control input X-_, can receive a control signal which determines the division ratio of the divider 8. Referring to Figure 8b, a truth table for the divider 8 is shown. Here it can be seen that when the control input Xτ_ is a logical • 1', then the divider 8 has a division ratio of 2. When the control input l is a logical 'O 1 , particularly when the logical state of f j - , Q-_, Q 2 - Q3 and Q4 are 0,0,0, 1, and 0 respectively, the divider 8 has a division ratio of 3 for a complete output cycle. Figure 8c shows the truth table for the variable frequency divider 8 when the two logic circuits of the gating stage 10 are each constructed in accordance with the embodiment of the present invention as illustrated in Figure 6d. From Figure 8c, it can be seen that when a logical '1' is supplied to the terminal X-_, the divider 8 has a division ratio of 2. When a logical 'O 1 is supplied to the terminal Xτ_, particularly when the logical states of fjN' Q χ ι C.2' Q 3 an<3 Q 4 are respectively 0,0,0,1,0 and 1,0,1,1,0, then the division ratio of the divider 8 is 3. Figure 9a shows a variable frequency divider 12 which comprises a pair of gating stages 14 coupled together. Each gating stage 14 comprises a logic circuit such as the one shown in Figure 6b coupled to the logic circuit of Figure 1 (for clarity, the divider 12 is shown as a single ended arrangement, but the divder can be implemented in differential form). The divider 12 is operative to frequency divide by 2 or 3 depending on the value of a signal (that is, logic 1 or logic 0) applied to the control input X ] _ of one of the gating stages 14. Figure 9b is a truth table of the divider 12 when the gating stages 14 comprise the logic circuit as shown in Figure 6b. The divider 12 is operative to frequency divide by 2 when X-_ = 1 and by 3 when X^ = 0. Figure 10 a shows an alternative variable frequency divider which includes a logic circuit according to the present invention. In this case the logic circuit of Figure 6c is connected to the logic circuit of Figure 1, as shown in Figure 10a, to form a gating ?tage 16. The gating stage 16 is coupled to the flip-flop pair 2 to form the variable frequency divider. From the truth table shown in Figure 10b, it can be seen that the variable frequency divider of Figure 10a has a division ratio of 4 when the control signal input at X-_ = 0 and a division ratio of 3 when X-_ ~ 1. The logic levels of the Q outputs of the logic circuits of the variable frequency divider are denoted by A, B, C, and D in the truth table. The frequency divided output signal is provided by one of the logic circuits of the flip-flop pair 2 and is supplied to an output terminal 17. The variable frequency dividers described above are illustrated in the drawings as single ended devices but this is primarily for the sake of clarity since they can be implemented in differential form. The embodiments described above have the advantage that they enable the elimination of external gating arrangements in variable frequency dividers. The particular embodiments described above are intended to be examples and it is envisaged that variations could be made without departing from the scope of the present invention. For example, any one of the control switches 6 of Figures 5a to 5c could be employed in the logic circuits shown in Figures 6a, 6b, 6c and 6d. Furthermore, different combinations of logic circuits embodying the present invention may be combined with flip-flops to form variable frequency dividers having division ratios other than 2/3 or 3/4. In particular, the second pair of emitter coupled transistors T-_4 and ] _5 of the control switch 6 shown in Figure 5b make it possible to increase the possible number of variations of division ratio when a logic circuit incorporating such a control switch 6 is incorporated into a variable frequency divider. The variable frequency dividers can be arranged to frequency divide by 2 N""1 /2 N+ - 1 - + 1 where N is the number of serially connected master/slave logic circuits (e.g. gating stages 2, 6, 10, 14 and 16).

Claims: CLAIMS ; 1. A logftc circuit including a driver (T^, T 2 ), a latch (T3, T4), and an enabling switch (T5, Tg) each comprising a pair of emitter coupled transistors, wherein the driver (T^, T 2 ) is coupled to the latch (T3/ T4), and wherein the emitters of the transistors of the enabling switch (T5, Tg) are coupled to a current source (T9), a collector of each of the transistors of the enabling switch (T5, T ) is coupled to a respective pair of emitters of the latch or driver, characterized in that the collector of one of the transistors (Tg) of the enabling switch (T5, Tg) is coupled to the emitters of either the driver (T j _, T 2 ) or the latch (T , T4) via a control switch (6). 2. A logic circuit according to claim 1 wherein the control switch (6) comprises a pair of emitter coupled transistors. 3. A logic circuit according to claim 2, wherein a second driver (T-_9, T 2 o), comprising a pair of emitter coupled transistors, is coupled in parallel with the first driver (T lf T 2 ). 4. A logic circuit according to claim 3, wherein the emitters of the transistors of the first driver (T j _, T ) and the second driver ( j_9, T 2 Q) are respectively coupled to the collector of said one of the transistors of the enabling switch (T 5 , Tg) via the control switch (6). 5. A logic circuit according to claim 2, wherein the collector of one of the transistors (Tg) of the control switch (6) is coupled to the emitters of either the driver (T j _, T 2 ) or the latch (T 3 , T 4 ) , the collector of the other transistor (T 5 ) of the control switch (6) is coupled to the collector of one of the transistors (T^) of the driver and one of the transistors (T3) of the latch, and the emitters of the transistors of the control switch (6) is coupled to the collector of one of the transistors (Tg) of the enabling switch. 6. A logic circuit according to claim 4, wherein the collector of one of the transistors (T-_j) of the control switch (6) is coupled to the emitters of the first driver (Tτ_, T 2 ) and the collector of the other transistor (T-_Q) of the control switch (6) is coupled to the emitters of the second driver (T-_9, T g). 7. A logic circuit including a driver (T-_, T 2 ), a latch (T3, T 4 ), and an enabling switch (T5, Tg) each fcomprising a pair of emitter coupled transistors, wherein the driver is coupled to the latch, and wherein the collector of one of the transistors (T5) of the enabling switch (T5/ Tg) is coupled to the emitters of the latch, the collector of the other transistor (Tg) of the enabling switch is coupled to the emitters of the driver ( j T 2 ), and the emitters of the transistors of the enabling switch ( 5, Tg) are coupled to a current source (Tg), characterised in that a control switch (6) comprising a transistor s coupled between the driver (Tτ_, T 2 ) and the current source (Tg), wherein the collector of the transistor (T-_Q) is coupled to the collector of one of the transistors (T]_) of the driver and the emitter of the transistor (T^ Q ) is coupled to the current source (Tg) . 8. A logic circuit according to claim 7, wherein the control switch (6) comprises a second transistor (T; ) coupled to said transistor (TJ_ ) of the control switch (6) thereby to form a pair of emitter coupled transistors. 9. A logic circuit according to claim 8, wherein the second transistor (T ] _j_) is coupled between the emitters of the enabling switch (T 5 , Tg) and the current source (Tg), the collector of the second transistor (T-_-_) being coupled to the emitters of the enabling switch and the emitter of the second transistor being coupled to the current source (Tg). 10. A logic circuit according to any one of claims 2 to 6, claim 8, or claim 9, wherein the control switch (6) comprises a second pair of emitter coupled transistors (T j _ 2 , T ] _3), in which the collector of one of the transistors (T13) of the second pair is coupled to the collector of one of the transistors (T15) of the first pair of emitter coupled transistors, and the collector of the other one of the transistors (Tj_ 2 ) of the second pair is coupled to the emitters of each transistor of the first pair (T^, T-^5) . 11. A logic circuit according to any one of claims 2 to 6, claim 8 or claim 9, wherein the control switch (6) comprises a third transistor (T-_g), the emitter of which is coupled to the emitters of the pair of emitter coupled transistors (Tτ_g τi7^ °^ tne control switch, and the collector of the third transistor (T-_s) is coupled to the collector of one of the transistors (T-_7) of the pair of emitter coupled transistors. 12. A variable frequency divider (8) comprising at least one logic circuit according to any one of claims 1 to 9, wherein the division ratio of the variable frequency divider (8) can be varied in dependence upon a signal (X^) applied to the control switch (6) of the or one of the logic circuits. 13. A variable frequency divider comprising at least one logic circuit according to claim 10, wherein a variable frequency divider (8) comprising at least one logic circuit according to any one of claims 1 to 9, wherein the division ratio of the variable frequency divider (8) can be varied in dependence upon a signal (Xτ_) applied to the control switch (6) of the or one of the logic circuits. 14. A variable frequency divider comprising at least one logic circuit according to claim 11, wherein a variable frequency divider (8) comprising at least one logic circuit according to any one of claims 1 to 9, wherein the division ratio of the variable frequency divider (8) can be varied in dependence upon a signal (X ] _) applied to the control switch (6) of the or one of the logic circuits.

Inventors: AINSLEY PHILIP IAN JEREMY, COWLEY NICHOLAS PAUL, AINSLEY, PHILIP, IAN, JEREMY, COWLEY, NICHOLAS, PAUL
Applicants: PLESSEY OVERSEAS, PLESSEY OVERSEAS LIMITED
Application year: 1985
Main classification: H03K3
IPC codes: H03K3, H03K23