METHOD OF PRODUCING A CONTACT ON A SEMICONDUCTOR DEVICE

Abstract: In order to prevent diffusion of silicon into aluminium metallisation (7) from an underlaying silicon region (2) a titanium nitride diffusion barrier layer (6) is provided, in a self-aligned manner, at a window (3) in an oxide layer (1) over the silicon. The process involves depositing titanium (4) over the oxide (1) and in the window (3), annealing to cause titanium disilicide (5) to be formed in the window, removing unreacted titanium (4) and annealing in nitrogen to convert the titanium disilicide (5) to titanium nitride (6). Metallisation (7) of pure aluminium is subsequently applied and patterned as appropriate.

Description: SEMICONDUCTOR PROCESSING This invention relates to semiconductor processing and in particular to forming electrical contacts to silicon based semiconductor devices. The conventional method of forming contacts to semiconductor devices involves opening a window in a dielectric layer disposed on a processed silicon substrate and then depositing a metal such as aluminium over the dielectric layer, and into the window, and subsequently defining tracks in the metal for device wiring. Contacts between the metal in the window and the underlying silicon are formed by annealing at 400-4500C, typically for fifteen minutes, to produce an ohmic contact. During this anneal, silicon from the substrate can migrate into the overlying metal at the contact and the aluminium migrates to fill the voids left in the substrate. This eventually causes severe junction leakage. Silicon is added to the aluminium to saturate the metal at the anneal temperature thus reducing the interdiffusion. Levels of 1 to 2% silicon in aluminium are commonly used for this purpose. This does, however, result in etching difficulities and hillock growth on the metal which can cause catastrophic failure in multi-layer metallisation schemes. To avoid junction leakage without saturating the aluminium with silicon would require a diffusion barrier between the substrate and the metal layer. A known diffusion barrier layer is titanium nitride. A method of forming self-aligned titanium nitride contact between aluminium metallisation and an interconnect of metallic silicide, in particular titanium disilicide, is described in our co-pending G.B. Application No. 84 23265 (Serial No )(P.D. Scovell P.J. Rosser - G.J. Tomkins 8-5-4). This method involves disposing a dielectric layer, for example a thick silicon dioxide layer, over the entire wafer on which the titanium silicide interconnects are disposed, etching holes in the oxide to expose the silicide, annealing the wafer in nitrogen during which anneal nitrogen reacts with the exposed silicide to form titanium nitride regions thereat, depositing aluminium over the wafer and patterning it as required. Normally, titanium nitride contacts to silicon are formed by providing an oxide layer over a processed silicon wafer, etching windows in the oxide layer at regions where contacts are to be formed, sputtering titanium nitride over the oxide layer, defining contact areas photolithographically and etching the titanium nitride to leave pads over the windows. The nitride is, however, difficult to etch and any misalignment can cause a reliability hazard due to electromigration. According to the present invention there is provided a method of manufacturing a semiconductor device including the steps of providing an electrically insulating layer over a silicon layer or a silicon substrate and exposing a region of the silicon via a hole in the insulating layer, characterised by the subsequent steps of depositing titanium over the insulating layer and the exposed silicon region, causing titanium disilicide to be formed locally at the exposed region of silicon, removing unreacted titanium from the insulating layer, converting at least part of the titanium disilicide to titanium nitride and providing a metallisation layer over the insulating layer and the titanium nitride, the metallisation layer being in electrical contact with the silicon via the titanium nitride. Embodiments of the present invention will now be described with reference to the accompanying drawings which illustrate in cross-section successive stages (Figs. 1 to 6) in the manufacture of an aluminium interconnect to silicon with a diffusion barrier interposed therebetween. A method of automatically aligning a nitride pad to any silicon (polysilicon or single crystal) and according to the present invention will now be described. A dielectric layer, for example a silicon dioxide layer 1, is provided on a silicon substrate or wafer 2 (or a silicide layer) and windows 3 etched in the oxide layer 1 to expose a contact region as in conventional processing (Fig. 1). A thin layer of titanium 4, approximately (100nm) is deposited over the entire wafer (Fig. 2). By performing a sinter anneal, such as 8500C for twenty seconds or 6500C for 30 minutes, on the wafer, titanium silicide 5 is formed at the contacts exposed by the windows 3 where the titanium is directly in contact with silicon (Fig. 3). Elsewhere titanium silicide is not formed. Any thin oxide layer inadvertently left in the contact will be reduced. The remaining unreacted titanium is washed off in a selective etch, such as ammonium hydroxide and hydrogen peroxide, together with any nitrides of titanium formed during sintering (Fig. 4). The wafer is then heated (annealed) in nitrogen to convert all or part of the titanium silicide 5 to titanium nitride 6 (Fig. 5), thus leaving a titanium nitride barrier self-aligned to the contact region. This annealing may be achieved by heating the wafer at 11000C for a few seconds. Metallisation 7 (Fig. 6) is subsequently provided and etched in a conventional manner, the metallisation 7 being in electrical contact with the silicon 2 via the nitride 6. Aluminium metallisation can be of pure aluminium or its alloy with silicon that has conventionally had to be employed. The titanium nitride barrier layer prevents junction spiking and obviates the need to add 1 to 2% silicon to aluminium interconnects.

Claims: CLAIMS: 1. A method of manufacturing a semiconductor device including the steps of providing an electrically insulating layer over a silicon layer or a silicon substrate and exposing a region. of the silicon via a hole in the insulating layer, characterised by the subsequent steps of depositing titanium (4) over the insulating layer (1) and the exposed silicon region (2), causing titanium disilicide (5) to be formed locally at the exposed region of silicon, removing unreacted titanium (4) from the insulating layer (1), converting at least part of the titanium disilicide (5) to titanium nitride (6) and providing a metallisation layer (7) over the insulating layer (1) and the titanium nitride (6), the metallisation layer (7) being in electrical contact with the silicon (2) via the titanium nitride (6). 2. A method as claimed in claim 1, characterised in that the silicon (2) is polycrystalline or single crystal in form. 3. A method as claimed in claim 1 or claim 2, characterised in that the insulating layer (1) is of silicon dioxide. 4. A method as claimed in any one of the preceding claims, characterised in that the titanium disilicide (5) is formed by a rapid anneal process comprising heating at 8500C for twenty seconds. 5. A method as claimed in any one of the preceding claims, characterised in that the unreacted titanium (4) is removed by a selective etch. 6. A method as claimed in any one of the preceding claims, characterised in that the titanium disilicide (5) is converted to titanium nitride (6) by annealing in nitrogen. 7. A method as claimed in any one of the preceding claims characterised in that the metallisation (7) is of pure aluminium.

Inventors: ROSSER, PAUL JOHN, SCOVELL, PETER DENIS
Applicants: STC PLC
Application year: 1985
Main classification: H01L21
IPC codes: H01L21