DISPLAY APPARATUS

Abstract: A refresh buffer (2) of a display system stores data to be displayed and phantom attribute bytes which are copies of field attribute bytes. A plurality of phantom attributes bytes each of which controls display condition of corresponding row data are collectively stored in one area (26) of the refresh buffer as a table which is separated from a data area (22) of the refresh buffer. If a display screen is partitioned into left and right viewport, two phantom attribute byte tables are established. Searching, deleting and inserting of data can be performed continuously. So, data handling efficiency is very high.

Description: This invention relates to a display apparatus having a refresh memory to store attribute copy signals which are copies of field attribute signals defining the display condition of data to be displayed together with the data to be displayed. The field attribute byte defines not only the display condition (e.g., flashing, reverse video and highlight) of characters in the row in which the field attribute byte is included, but also the display condition of the next row, until the next field attribute byte appears. In the past, as is disclosed in EP-A-0 009 593, the field attribute byte last used in the preceding line is copied in the location immediately before the next row data using software in order to simplify the hardware. The field attribute byte thus copied is referred to as the attribute copy byte. From IBM Technical Disclosure Bulletin, Volume 26, No. 10B, March 1984, page 5596, a display apparatus utilizing a line attribute table for defining the condition of data to be displayed uniformly in a specific line is known. GB-A-2 084 836 discloses a video processor and controller having a look-up table for data row start addresses. The look-up table and data are in the same device or group of devices, addressed continuously to form one memory device. According to the above-mentioned prior art, however, since the attribute copy byte CA is stored between a certain row data and the following row data in the refresh memory 200 as shown in Figure 5, the data group is separated by the attribute copy byte CA, and the searching, deleting and inserting of data cannot be performed continuously by hardware, resulting in the decrease of data processing efficiency. The invention as set out in the appended claims solves such problems, and it is the object of the invention to provide a display apparatus having a refresh memory of high data processing efficiency even if the attribute copy signal is stored in said memory. In order to achieve the above object, the display apparatus of this invention comprises an attribute copy table which stores a plurality of attribute copy signals collectively in a plurality of sequentially accessible locations in the refresh memory, and a means to address said table for reading the attribute copy signal corresponding to data to be displayed out of said table before reading the data to be displayed out of said refresh memory. According to this invention, since the attribute copy signal defining the display condition of data to be displayed are read before the data to be displayed are read even if the attribute copy signals are stored apart from the data to be displayed, the data can be displayed in accordance with the attribute copy signals in an advantageous manner. With reference to the attached drawing, showing an example of the invention, the latter is explained in more details. In the drawing Fig. 1 is a block diagram showing an embodiment of a display apparatus according to this invention; Fig. 2 is an explanatory diagram showing the configuration of the refresh memory shown in Fig. 1; Fig. 3 is a flow chart showing the operation of preparing the attribute copy table; Fig. 4 is an explanatory diagram showing an example of the display state of the CRT screen;, and Fig. 5 is an explanatory diagram showing the configuration of a conventional refresh memory. Fig. 1 shows an embodiment of a display device according to this invention. In Fig. 1, the refresh memory 2 is a random access memory comprising a data storage area 22 which stores character bytes to be displayed and field attribute bytes, a start address table 24 which stores start addresses of each row of this data storage area 22 (here, a row does not mean the actual row of the memory but the storage area corresponding to the row of the screen) in desired sequence, and an attribute copy table 26 which stores attribute copy signals defining the display condition of characters in each row of the data storage area 22 in desired sequence (the same sequence as that of the start address). Fig. 2 shows the configuration of the refresh memory 2 in detail. The data storage area 22 has the capacity of two CRT screens. In this embodiment, the CRT screen displays 24 rows each of which consists of 80 characters. Data in row 0 of the data storage area 22 are D₀,₀, D₀,₁, ... D₀,₇₉; data in row 1 are D₁,₀, D₁,₁, ... D₁,₇₉; ... and data in row 47 are D₄₇,₀, D₄₇ ,₁, ... D₄₇,₇₉. The start address table 24 stores start addresses of 48 rows in the data storage area 22 in the desired sequence. For convenience of the description, the start address table 24 is assumed to store start addresses of rows in the same sequence as the rows of the data storage area 22. That is, the stored information A0 of the first address in the start address table 24 is the start address of the row that stores data from D₀,₀ to D₀,₇₉; the stored information A1 of the next address is the start address of the row that stores data from D₁,₀ to D₁,₇₉; and the stored information A47 of the last address is the start address of the row that stores data from D₄₇,₀ to D₄₇,₇₉. Since the details of the start address table 24 are described in EP-A-0 031 011 refer thereto. The attribute copy table 26 has 48 sequentially addressable memory locations corresponding to 48 row in the data storage area 22. The attribute copy byte CA0 stored in the first memory location of the attribute copy table 26 defines the display condition of data D₀,₀ to D₀,₇₉ in the row 0 of the data storage area 22 (if the field attribute byte is contained within the line, the display condition of data (characters) thereafter is defined by this field attribute byte); ... the attribute copy byte CA47 stored in the last memory location defines the display condition of data D₄₇,₀ to D₄₇,₇₉ in the row 47 of the data storage area 22 (same as above if the field attribute byte is contained within the row). Referring next to Fig. 3, how the attribute copy table 26 is made will be described. First, the microprocessor 4 establishes the area which is occupied by the attribute copy table in the refresh memory 2 (in this embodiment, from address 0 to address 47). This area contains a plurality of sequentially addressable memory locations. Next, the microprocessor 4 issues a read instruction to the refresh memory 2, and as is shown in Step 50 of Fig. 3, the microprocessor 4 loads the first address of the start address table 26 into the address register 6 and instructs the selection circuit 8 to transmit the content of the address register 6 to the refresh memory 2, thereby the start address A0 of the row 0 of the data storage area 22 is read out of the first address of the start address table 24, and is set in the address counter 12. On the other hand, the microprocessor 4 instructs the selection circuit 8 to transmit the content of the address counter 12 to the refresh memory 2, thereby the data D₀,₀ in the first memory location of the row 0 in the data storage area 22 is transmitted to the microprocessor 4. Then, the data in the row 0 are sequentially transmitted to the microprocessor 4 in every increment of the address counter 12 (Step 52). The microprocessor 4 judges whether or not the field attribute byte FA is present in the data in the row 0 (Step 54), and if it is present, the microprocessor 4 writes this field attribute byte FA as the attribute copy byte CA of the following row (Step 56). If the field attribute byte FA is absent, the microprocessor 4 writes the attribute copy byte CA0 of this row as the copy attribute byte CA1 of the following line (Step 58). This write operation is achieved by loading the address register 6 with address 1, which is the memory location of the attribute copy byte CA1, from the microprocessor 4, instructing the selection circuit 8 to pass the content of the address register 6 to the refresh memory 2, issuing a write instruction to the refresh memory 2 and transmitting the field attribute byte FA detected or the attribute copy byte CA0 in the row 0 to the refresh memory 2 through the bus. Usually a byte indicating no attribute is written as the attribute copy byte CA0 in the row 0. Next, the address register 6 is loaded with the following address in the start address table 26 (Step 60), and whether or not the data in the row 1, D₁,₀ to D₁,₄₇, contain the field attribute byte FA is checked. If the field attribute byte FA is detected, it is written as the attribute copy byte CA2 of the row 2; if it is not detected, the attribute copy byte CA1 of line 1 is written as the attribute copy byte CA2. By repeating such operations to the data in the last row, D₄₇,₀ to D₄₇,₇₉ (Step 46), the attribute copy table 26 is completed. The address counter 12 increases the count in accordance with the output pulse of a character width counter 16 which counts reference pulses generated by a clock 14 and outputs pulses in every character scanning of the CRT 36. In this embodiment, a character box consists of 9 x 12 dots. So the value of the counter 16 changes from 0 to 8 cyclically. The column counter 18 counts the output pulses of the character width counter 16 and outputs a pulse in every scanning line. The value of the counter 18 changes from 0 to 79 cyclically. The output pulse of the column counter 18 is a horizontal synchronizing signal which is connected to one terminal of an AND gate 11, and the output of the pointer 10 is supplied to another terminal of the AND gate 11. The pointer 10 is supplied with the address of the start address table 24 from the microprocessor 4 on displaying. The output terminal of the AND gate 11 is connected to the selection circuit 8. The content of the pointer 10 is passed to the refresh memory 2 as an address signal only when the AND gate 11 receives a horizontal synchronizing signal and the selection circuit 8 receives the selection instruction of the AND gate 11 from the microprocessor 4. The scanning line counter 40 counts the output pulses of the column counter 18 and generates a pulse in every line display of the CRT 36. The value of the counter 40 changes from 0 to 11 cyclically. The row counter 42 counts the output pulses of the scanning line counter 40 and generates a pulse in every picture display of the CRT 36. The value of the counter 40 changes from 0 to 23 cyclically. The counts of the row counter 42 are used to generate the address of the attribute copy table 26 on displaying. The first reason for this is that the counts of the row counter 42 can correspond to 24 sequential memory locations read out of the attribute copy table 26 during the display of one screen. The second reason is that since the change in the counts of the row counter 42 occurs immediately after the beam of the CRT 36 reaches the right edge of the picture and there is considerable time before the beam returns to the left end of the picture, the attribute copy byte can easily be read before the display data are read out of the data storage area 22 if the counts of the row counter 42 are used to generate the address of the attribute copy table 26. The content of the row counter 42 is supplied to the selection circuit 8 through the address converting circuit 44. The address converting circuit 44 corrects the counts output from the row counter 42 in accordance with instruction from the microprocessor 4, and transmits the result of correction to the selection circuit 8 as the address of the attribute copy table 26. When the memory locations of the attribute copy bytes to be read are from address 0 to address 23, for example, the address converting circuit 44 transmits the counts output from the row counter 42 to the selection circuit 8 without any correction. When the memory locations of the copy attribute bytes to be read are from address 24 to address 47, for example, the microprocessor 4 instructs the address converting circuit 44 to add 24 to the counts of the row counter 42, and the address converter circuit 44 transmits values 24 to 47, obtained by adding 24 to the counts 0 to 23 of the row counter 42, to the selection circuit 8. The character register 46 stores bytes showing characters to be displayed output from the refresh memory 2. The attribute register 48 stores the attribute copy byte read out of the attribute copy table 26 or the field attribute byte read out of the data storage area 22. The character generator 30 generates the dot patterns of characters corresponding to character bytes stored in the character register 46, and these patterns are converted to serial data by the parallel-serial converter 32 and transmitted to the video controller 34. The video controller 34 corrects patterns from the converter 32 in accordance with the content of the attribute register 48 and transmits them to the CRT 36. Next, the display operation of the embodiment shown in Fig. 1 will be described. It is assumed that data from the row 1 to the row 24 stored in the data storage area 22 are displayed on the CAT 36. First, the microprocessor 4 instructs the address converter circuit 44 when row 23 is displayed during previous display to add "1" to the counts output from the row counter 42 thereafter. When the previous display ends and the count of the row counter 42 becomes 0, the address converting circuit 44 adds 1 to the counts of the row counter 44, and transmits "1" to the selection circuit 8. In this time, the selection circuit 8 receives the instruction from the microprocessor 4 to transmit the output of the address converting circuit 44 to the refresh memory 2, and transmits "1" to the refresh memory 2 as an address signal, thereby the attribute copy byte CA1 is read out of address 1 of the attribute copy table 26, and is loaded in the attribute register 48. Next, the microprocessor 4 instructs the pointer 10 to load the address showing the second memory location of the start address table 24 and also instructs the selection circuit 8 to pass the output of the AND gate 11. In this time, since a horizontal synchronizing signal is generated by the column counter 18, the content of the pointer 10 is transmitted to the refresh memory 2, thereby the start address A1 of the row 1 of the data storage area 22 is read out of the second memory location of the start address table 24, and is loaded in the address counter 12. In this time, the selection circuit 8 receives instruction from the microprocessor 4 to transmit the output of the address counter 12 to the refresh memory 2, thus, data D₁,₀ is read out of the first memory location in row 1 of the data storage area 22 in the refresh memory 2. If this data is a character data, it is loaded in the character register 46, converted into a dot pattern by the character generator 30, converted into a serial data by the parallel-serial converter 32, converted into a signal suitable to the display condition defined by the attribute copy byte CA1 stored in the register 48 by the video controller 34, and transmitted to the CRT 46. If the data D₁,₀ is a field attribute byte FA, it is loaded in the attribute register 48, and controls the display condition of the following characters instead of the attribute copy byte CA1. The address counter 12 increments in accordance with pulses output from the character width counter 16, and data D₁,₁ to D₁,₇₉ in the row 1 are sequentially read. If these data are characters, they are displayed on the condition defined by the byte previously loaded in the attribute register 48; if these data are field attribute bytes, they are loaded in the attribute register 48 and control the display condition of the following character data. When the content of the row counter 42 changes to "1", the address converting circuit 44 outputs "2"; the selection circuit 8 transmits "2", the output of the address converting circuit 44, to the refresh memory 2 in accordance with the instruction of the microprocessor 4; the content of address 2, CA2, of the attribute copy table 26 is read and loaded in the attribute register 48. Then, the microprocessor 4 transmits the address showing the third memory location of the start address table 24 to the pointer 10 and instructs the selection circuit 8 to transmit this address to the refresh memory 2, and the start address A2 in the row 2 of the data storage area 22 is read out of the third memory location of the start address table 24. Then, in the similar way described above, data D₂,₀ to D₂,₇₉ in the row 2 are read. Thereafter, data in each row are sequentially read, and display is performed on the condition according to the attribute copy byte corresponding to each row or the field attribute byte. Fig. 4 shows the state in which data in row 1 to row 24 are displayed on the CRT 36. When a screen is vertically divided, it is preferable to provide each divided screen with an attribute copy table. In this case also, the address of the attribute copy table can be derived from the value of the row counter, but the table should be addressed when the signal showing the boundary of divided screen is being generated. This is for reading the attribute copy byte before reading data to be displayed. As seen from the above description, since the display apparatus of this invention stores copy attribute signals collectively in a table, the attribute copy signals do not split the data group. Therefore, the searching, deleting and inserting of data in the refresh memory can be performed continuously with the hardware, resulting in high data processing efficiency. In other words, according to this invention, a wider storage area can be controlled by a microprocessor which is the same as a conventional one.

Claims: A digital display apparatus comprising: a display device (36) for displaying characters; a refresh memory (2) including a first portion (22) for storing character data representing characters to be displayed and field attribute data representing attributes of fields of characters to be displayed; and a separate second portion (26), referred to as an attribute copy table, for storing selected field attribute data; means for loading into the first portion (22) of said refresh memory said character data in positions corresponding to the desired positions of the character on the display device (36), and said field attribute data in positions corresponding to the initial positions of fields of characters on the display device (36); means (4) for selecting the field attribute data valid at the end of a displayable line from the field attribute data of said first portion; said selection being based on a character field carry over from one displayable line of characters to another; means (4, 6, 8) for copying said selected field attribute data into said attribute copy table (26) in said refresh memory, each entry in the attribute copy table corresponding to the initial position of a line of characters for display within a field and being a copy of the field attribute data valid at the end of an immediately preceding line of characters for display within the field; and display control means (10, 11, 30, 34, 42, 44, 46, 48) for reading the character data, the field attribute data, and the copy field attribute data from the refresh memory (2) to generate lines of characters with corresponding attributes on the display device (36). Digital display apparatus according to claim 1, in which said display control means includes: a character register (46) for registering character data from the refresh memory (2); an attribute register (48) for registering said field attribute data from the refresh memory (2); character generator means (30) coupled to receive data from the character register (46) to generate signals for the video display device (36); and video control means (34) coupled to receive said signals and to receive data from the attribute register (46) to modify said signals in accordance with the field attribute data; said attribute data in the attribute register (48) remaining constant for each attribute field. Digital display apparatus according to claim 1 or 2, in which said refresh memory includes a start address table (24), and including: means for loading start addresses, each comprising the address of data representing an initial character for display on a corresponding line of characters on the display device; and addressing means (6, 8, 10, 11, 12) for selecting, for each line of characters for display on the display device (36) a corresponding start address from the start address table (24), and for addressing the refresh memory (2) with sequential addresses from the selected start address to retrieve character data and field attribute data for the line of characters. Digital display apparatus according to claim 3, in which said means for selecting said field attribute data for said attribute copy table (26) comprises an address register (6) for addressing said attribute copy table. Digital display apparatus according to anyone of claims 1 to 4 further including: counter means (12) responsive to an address read from the start address table (24) for addressing sequential locations in the first portion (22) of the refresh memory (2) containing character data and field attribute data; and corresponding processor means (4) for checking data addressed from said sequential locations in the refresh store (2) to select field attribute data stored therein and for inserting the selected field attribute data into said attribute copy table. Digital display apparatus according to anyone of claims 1 to 5, in which said display control means comprises: a row counter (42) coupled to clocking means, for generating successive counts for rows of characters to be displayed on the display devices; means (44) responsive to the counts of the row counter (42) to address the successive locations in the attribute copy table (26) for successive rows of characters to be displayed; pointer means (10) for storing an address of said start address table; and logic means (11) coupled to the pointer means and arranged to receive horizontal synchronizing signals for the display device (36) to direct the address stored in the pointer means to the refresh store (2) to access the address from the start address table (24) in response to a horizontal synchronizing signal; whereby for each row of characters displayed, the count in the row counter (42) defines the address of initial attribute data and the pointer means (10) defines the address of initial character data in the row. Digital display apparatus according to anyone of claims 1 to 6, including selection circuit means (8) coupled to receive the outputs of said address register, said logic means, said row counter and said counter means, said selection circuit means being coupled to receive control signals from said processor means to select the outputs of said address register, said logic means, said row counter and said counter means individually. Digital display apparatus according to anyone of claims 1 to 7, wherein for each view port provided for display on said display device (36) a separate attribute copy table (26) is established. Method for generating an attribute copy table in a digital display system according to anyone of claims 1 to 8 comprising the steps of: reading the data (D 0,0 - D 0,79 ) of the row (0) to be displayed from the first portion (22) of said refresh memory (2) into the display control means (4); checking if field attribute data (FA) is present in the data in the row (0) by display control means (4); a) if field attribute data (FA) is absent, the display control means (4) writes the copy display attribute data of this row (0) as the copy display attribute data of the following row (1); b) if the field attribute data (FA) is present, the display control means (4) writes the field attribute data of this row (0) as the copy display attribute data of the following row (1); continue the above described steps until the last row (n) is reached.

Inventors: NAKAGAWA, BANRI, NOJIMA, KATSUYUKI
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1985
Main classification: G09G1
IPC codes: G09G5