INDUCTANCE SYSTEMS

Abstract: Effective and efficient measurement of a dynamic physical parameter such as relative motion, force, or pressure is provided by an inexpensive system which includes a relatively movable reluctance device (9) surrounding the coil (5) according to changes in a dynamic parameter (F); a signal generator including a variable resistor (75, 89) and an inverter (73, 81, 83), comparator or operational amplifier (101); a processor (Fig. 14) for processing signals for the signal generator according to a count of the cycles in the output signal of the signal generator and a predetermined pulse train value; and a digital to analog converter (Fig. 18) for integrating digital signals to yield analog signals of a non-unitary slope whose length is reflective of the duration of the digital signals.

Description: Inductance Systems Background The present invention concerns apparatus and methods employing inductance devices having a variable reluctance in their magnetic fields for converting a parameter, such as relative motion, force, or pressure, into an electrical signal for measurement. The inven¬ tion further involves the generation of signals of varying frequency according to some parameter, and to the processing of such signals for some useful purpose. Transducers employing variable reluctances and inductances for detecting motion are known. These are referred to by such terms as proximity sensors and magneto sensors, and examples of these devices include the linear variable differential transformer ("LVDT") eddy current killed oscillator ("ECKO") and eddy cur¬ rent oscillator level detector ("ECOLD")- One such transducer uses a magnetic diaphragm positioned between two coils having magnetic cores. A change in diaphragm position in response to a force applied to it changes the gaps between the cores and the diaphragm resulting in changes in the inductances of the coils. The ratio of the changes in the inductances of the colls is mea¬ sured through an alternating current bridge. In order to obtain a direct current indication of the diaphragm motion, the alternating current bridge signal must be demodulated. These known transducers are generally expensive, are usually physically large and the cir¬ cuitry is susceptible to mechanical shock because of its bulk. U.S. Patent No. , 06,999 discloses an in¬ ductive sensor having an outer coil, a ferromagnetic core and a conductive sleeve movable between the coil and core, wherein displacement of the sleeve is re- • fleeted in changes in inductance of the device. U.S. Patent No. 4,310,807 discloses a reluctance proximity sensor having a reactive sensing unit in an L/C tuning circuit of an oscillator, which is connected ahead of an operational amplifier. A shortcoming of the latter 5 sensor is the requirement of a separate squaring cir¬ cuit for generating a square wave frequency response. Variable frequency oscillators are known which can be used with variable capacitive transducers to generate output signals whose frequencies are a func- 10 tion of the parameter being sensed by the transducer. For example, see U.S. Patent No. 4,310,806 dated January 12, 1982. These known devices are characterized by any of various shortcomings. They tend to be expensive, 15 bulky, delicate, complex in structure and in the way • they must be connected to other circuit components, operational only at high power levels and at high volt- -~ ~ ages, and* to be excitable only by AC voltage inputs. 2o Summary of the Invention It is a general object of the pre-sent inven¬ tion to measure a dynamic, physical parameter in an efficient and effective manner. Another object is to provide an inexpensive 25 yet effective system for measuring a dynamic, physical parameter. It is a more particular Object of th ' e inven¬ tion to provide a transducer for assuming electrical characteristics reflective of the value of a dynamic, 30 physical parameter, which can be constructed as a rugged, accurate, inexpensive and small device. A related object is to provide such a transducer which is stable under various temperature conditions, easy to use with other circuit components, and which is gener- ■ - > ally free of the shortcomings of known transducers. Still another object of the present invention is the provision of an oscillator for generating sig¬ nals whose frequencies vary according to characteris¬ tics of a transducer in the oscillator network, wherein the oscillator is effective and efficient and relative¬ ly free of the shortcomings of the prior art as dis¬ cussed previously. A further object of the invention is the pro¬ vision of an effective and efficient processor for processing signals from the signal -generators which generate variable frequency signals, such as those described above, to produce intelligible or otherwise usable output signals. Such a processor can be con¬ structed to be compact and rugged, and capable of avoiding shortcomings of the prior art as -discussed above. Another object is to provide an efficient digital to analog converter. The invention in preferred forms provides a small, rugged, inexpensive variable ' reluctance trans¬ ducer used in conjunction with an electronic circuit that operates solely with -direct current excitation. According to an aspect of the invention, an inductor having a variable reluctance that affects its magnetic field may form part of a self-excited oscillator gen¬ erating an analog or digital alternating current signal having an inductance-dependent frequency. The result¬ ing inductance is varied by changing the reluctance in the magnetic field created by the inductor. Changes in inductance and, therefore, the magnitude of the move¬ ment of the transducer components because of the applied force or pressure are conveniently determined by measuring the change in the frequency of the oscil¬ lator signal. In the preferred transducer, a reluctance means for varying the reluctance of the magnetic field of the inductor may be a shield receiving the inductor or a solid body proximate to, and movable relative to, the inductor. The reluctance means is made of a mate¬ rial that modifies the magnetic field by providing a reluctance different from that of air. Either the reluctance means or the Inductor may be mounted on a movable base such as a diaphragm that can be displaced in response to a force applied to it. A change in the nature of the magnetic path of the inductor leads to a change in inductance and indicates the relative motion of the reluctance means with respect to the inductor. Thus, eddy currents can be responsible for changes in effective inductance by providing a variable obstacle ' to the field. An oscillator according to the inven¬ tion produces a signal with an inductance-sensitive frequency, according to changes in a transducer in¬ cluded in the oscillator network, and when a transducer as described above is so employed, relative motion of the transducer elements results in changes in frequen¬ cy. Both the direction and magnitude of frequency changes may be conveniently measured in novel digital processor circuitry readily adapted to integrated cir- cuitry. That novel circuitry measures the time re¬ quired by an oscillator having an inductance-sensitive frequency to generate a fixed number of cycles in com¬ parison to time required to generate that number of cycles when no stimulus is applied to the transducer. A digital to analog converter according to an embodi¬ ment of the invention receives digital signals like the foregoing, and integrates them to produce output sig¬ nals having non-unitary slopes and lengths which vary according to the duration of the digital signals. Brief Description of The Drawings Figure 1 is a side view of an embodiment of a reluctance transducer according to the Invention. Figure 2 is a graph of the electrical response of an embodiment of the invention built according to Figure 1. Figure 3 is a graph of the electrical response of an embodiment of the invention built according to Figure 1. Figure 4 is a graph of the electrical response ' of another embodiment of the invention built according to Figure 1. Figure 5 is a perspective view of an embodi- ment of a reluctance transducer according to the inven¬ tion. Figure 6 is a perspective view of still an¬ other embodiment of a reluctance transducer according to the invention. Figure 7 is a side view of a fourth embodiment of a reluctance transducer according to the invention. Figures 8-13 are schematic diagrams of embodi¬ ments of signal generators according to the invention. Figure 14 is a schematic diagram of signal processing circuitry according to the invention for processing a signal generated In a variable inductance signal generator. Figure 15 is a timing diagram illustrating the operation of the circuitry shown in Figure 14. Figure 16 is a schematic diagram of other signal processing circuitry according to the invention for processing a signal generated in a variable induc¬ tance signal generator. Figure 17 is a timing diagram illustrating the operation of the circuitry shown in Figure 16. Figure 18 is a schematic diagram of circuitry for making an analog to digital converter In accordance with the invention. Detailed Description of Preferred Embodiments In Figure 1 an embodiment of a transducer according to the invention is shown in side view. Transducer 1 includes a core ~ , about which a coil ~ is wound. Preferably core 3 and coil ~ are rigidly mounted with respect to a flexible diaphragm 7 on which a hollow cylinder 9 is securely mounted. Core 3 is preferably made of a ferromagnetic material -to increase the inductance of coil ~ . Hollow cylinder 9 can be a non-ferrous metallic or ferromagnetic material whose relative position will variably alter the magnetic field around the coil, allowing for either an eddy current or altered magnetization effect. As shown in Figure 1, core 3 and coil ~ protrude partially into hollow cylinder ~ . In response to forces applied to the diaphragm (in the horizontal direction according to the drawing of Figure 1) , diaphragm ~ flexes with the result that the coil is inserted further into or with¬ drawn from cylinder 9- When current flows through coil 5, a corresponding magnetic field is created around the coil. Part of that field is intercepted by cylinder 9 and is modified by the cylinder. As diaphragm 7 flexes, more or less of the magnetic field of coil 5 is intercepted, resulting in a change with respect to time of the current flowing through coil ~ . This time rate of change of current and its corresponding field and inductive characteristics therein, serves to modify the inherent inductance of coil ~ . The inductance change is measured by sensing the change in the current flow¬ ing through coil ~ . That is, cylinder 9 provides a variable reluctance means for changing the reluctance to the magnetic field in the region about coil ~ . As in all the embodiments of the transducers illustrated in the figures, the shape of coil 5 In Figure 1 is merely schematic. The coil need not be helical and could even be planar. Various coil config¬ urations and the choice of core and shield materials affect the basic inductance achievable and the magni¬ tude of the changes in inductance, i.e. the dynamic range and sensitivity of the transducer resulting from the relative motion of the elements of the transducer. However, so long as the movement of the diaphragm is linear with respect to the applied force and the reluc¬ tance means principally intercepts relatively straight magnetic lines, the response of- the transducer is lin¬ ear. A number of examples of the embodiment of Figure 1 have been constructed and their.electrlcal characteristics measured. Core 3 w s formed from a ferromagnetic material and coil ~ wound around it. In these examples, cylinder.9 has a close fit over coil ~ but is relatively free from physical contact in order to reduce the friction between them to a minimum. A plastic sleeve was placed over the coil to protect it against damage and to reduce that friction. In gener¬ al, a closer fit between the cylinder and coil yields a greater dynamic range but a greater risk of friction; a looser fit yields a smaller dynamic range and a lower risk of friction. It was desired to construct a small, low cost, lightweight transducer so cylinder was constructed of aluminum in the measured examples. In order to obtain linear operation in any embodiment, it is preferable to have the edge of cylinder 9 intercept only the magnetic lines created by coil 5 that are nearly parallel to the longitudinal axis of core 3« In - • terms of the dimensions of the measured examples, the edge of cylinder 9 should extend over and cover a por¬ tion of the coll beyond the end of core 3 during opera¬ tion to assure operation in the linear range. In the measured examples, diaphragm 7 was initially a convo¬ luted rubber diaphragm having a central planar surface with concentric corrugations between it and the outer support structure. However, this type of diaphragm was found subject to drift, i.e. gradual position changes or "creep" under the influence of a steady state pres¬ sure or force. The drift effect is greatly reduced If a soft spiral spring is used in conjunction with the diaphragm. The spring provides increased resistance to its movement; however, this technique could increase cost and assembly time. A different diaphragm was constructed with a circular piece of flat or "sheet" rubber stretched over an open ended cylinder. This arrangement provided the necessary stability without the use of the enhancement spring mentioned above. In Figure 2, the measured change in frequency of an oscillator of the type shown in Figure ~ de¬ scribed below and Including a reluctance transducer as shown in Figure 1 is plotted as a function of the de¬ flection or relative movement of the cylinder and coil of the transducer. The cylinder had an inside diameter of 4.2 mm and an outside diameter of.6.25 mm, meaning its wall thickness was approximately 1 mm. A large linear range of frequency change as a function of de¬ flection was measured; e.g. the linear frequency re- sponse over a deflection range of about 3 mm was over 300 kHz. In Figure 3 > the measured change in frequency as a function of deflection is plotted for five more examples of oscillators of the type shown in Figure 9 and including reluctance transducers built according to" ■ - the embodiment of Figure 1. The curves show decreasing sensitivity as the cylinder's inner diameter becomes greater and the wall's thickness becomes thinner. This is the expected result because the thinner wall thickness means a smaller cross section and volume of reluctance varying metal is present to intercept the magnetic field of the coil. Likewise, the same wall thickness effects are shown in the graph illustrated in Figure 4, which plots the measured output response for four other oscillators similar to the foregoing but where the wall is quite thin, being constructed of layers of foil. Making the cylinder of a ferromagnetic material would increase the sensitivity and dynamic range of these transducers substantially, but at a significant increase in the cost of the unit. Another embodiment 11 of a reluctance trans¬ ducer is shown in Figure 5. There a coil 13 is wound around a tubular structure * 15 which has an air inner core 17. The reluctance shield includes a tubular portion 19 which is concentric to a rod 21. While these elements are shown separated in Figure 5 for clarity, in use core 15 is received by tubular shield 19 and rod 21 is received by air core 17. Both tube 19 and rod 21 ' are mounted on a flexible diaphragm 23 to which the forces to be measured are applied. In com¬ parison to the embodiment of Figure 1, this embodiment yields a lower inductance because of air core 17, but a greater dynamic range because a large portion of the total magnetic field produced by coil 13 is influenced by the incremental movement of the shield and tube over and into the coil. A very useful alternative to the simultaneous movement of tube 19 and rod 21 over and into the coil, is to securely mount tube 19 around the outer portion of coil 13. As a stationary shield, tube 19 will protect the coil against outside disturbances such as magnetic or electro-magnetic fields or the otion " of other metallic parts in the vicinity of the measurement. In this case, only the inner tube 21 will move into or out of the core section of the coil, i.e. a reversal of the means shown in Figure 1. Shield 19 can be a ferromagnetic material for best results in this approach. Still another embodiment 31 of a reluctance transducer is shown in Figure 6. As in the other em¬ bodiments, a coil 33 is wound about a core 35. How¬ ever, in place of a shield, a magnet 37 having a con- cave face 39 opposite coil 33 is mounted on a flexible diaphragm 41. In this embodiment, a large dynamic range is achieved because of the large magnetic field produced by magnet 37. It is not necessary that face 39 be concave, but that shape extends the linear re- sponse range of this embodiment because the concave face 39 is conformal to the magnetic lines of force leaving the top of core 35. An embodiment 51 of a transducer shown in Figure 7 permits measurement of a force regardless of its direction. The force is applied to a deflectable beam 53 on one end of which a magnet 55 is mounted. As in Figure 6, magnet 55 is disposed opposite a coil 57 wound around a core 59. Any o f-axis motion between coil 57 and magnet 55 results in a disturbance of the coil's magnetic field which may be measured as a change in the time dependent current flowing through the coil, i.e., a change in inductance. By strategically select¬ ing the cross sectional shape of beam 53 as suggested by the cross cut sections 54, 61 and 63, the amount of deflection in response to a given force in any direc¬ tion can be controlled. For example, for one unit of force in the x-direction, the beam could be made to move four units of distance, while the same one unit of force in the y-direction could be made to move the beam only one unit of distance. Any number of force- distance combinations could be implemented for any number of beams alone or In combination (parallel, for example), could be made. 5 Networks have been devised for generating variable frequency signals according to changes in inductance, and these can be used for measuring the changes in inductance in a reluctance transducer. Figure 8 schematically depicts a simple circuit in 10 which changes in inductance are converted Into changes in frequency that may be sensed to determine the force or pressure applied to, i.e. the relative movement of, the transducer elements. In Figure 8, a coil 71* which may be the coil of a reluctance transducer, is con- 15 nected between the input and output terminals of an inverter 73« Inverter 73 may be an integrated circuit Schmitt trigger such as a CD 40106. The input terminal of inverter 73 is connected to ground through a vari¬ able resistor 75« When the signal at the input termi- 20 nal of inverter 73 is in its low state, the signal at the output terminal is in its high state, causing an increasing current to flow through inductor 71 and the magnetic field about the inductor to grow. The rate of growth of the field is determined by the time constant ~ ~ of the inductance divided by resistance of the Induc¬ tive network 71 and 75- As the coil approaches saturation, I.e. a constant value of current, the volt¬ age drop across inductor 71 declines, causing a voltage rise at the input terminal of inverter 73. Once the 0 switching threshold voltage of inverter 73 is exceeded at its input terminal, the voltage at the inverter's output terminal switches to its low state causing a reverse flow of current through inductor 71 as the magnetic field of inductor 71 collapses at a rate 5 limited by the time constant of the inductive network. When the current falls low enough, the voltage at the input terminal of inverter 73 drops below the in¬ verter's switching threshold causing the voltage at the output terminal of inverter 73 to switch back to its 5 high state. This process is repetitive and generates a pulse train as shown in Figure 8. The frequency or pulse repetition rate and pulse width of the pulse train are determined in large measure by the character¬ istics of inductor 71« A higher inductance decreases 10 frequency and current consumption. While lower fre¬ quencies are less susceptible to interference, higher frequencies provide better resolution of the measure¬ ment. Resistance 75 allows adjustment o the base, i.e. quiescent, frequency of the oscillator by changing 15 the resistance component of the time constant. Changes in the Inductance of inductor 71 resulting from dis¬ turbance of its normal magnetic field, as by the shield of a reluctance transducer, disturb the oscillation process just described, resulting in an alteration of 20 the frequency, i.e. the repetition rate, of the pulse train signal generated. - In Figure 9 a modification of the embodiment of Figure 8 is schematically shown. The signal gen¬ erated by the embodiment of Figure 9 still has a fre- - - quency related to the magnitude of the inductance, but includes circuitry for improving its stability.- The output terminal of an inverter 81 is connected to the Input terminal of an Inverter 83 and to one terminal of an inductor 85- The other terminal of Inductor 85 is 0 connected through a resistance 87 to the input terminal of inverter 81 and through a variable resistance 89 to the output terminal of inverter 83- Inductor 85 may be the coil of a reluctance transducer. In this embodi¬ ment, resistance 87 provides a measure of stability against temperature and power supply voltage varia¬ tions. As in the embodiment of Figure 8, variable resistor 89 adjusts the frequency of the output signal by adjusting the inductive time constant of the net¬ work. Common, low power consumption, CMOS integrated circuit Schmitt trigger inverters such as the CD 40106 may be used In the sensing means embodiments shown in Figures 8 and 9. A different embodiment of a signal generator is shown in Figure 10, where a circuit element 101 may be either a comparator to produce a pulse train signal as shown or an operational amplifier to produce an analog, sinusoidal signal which is also shown. The positive sense input terminal 103 of circuit 101 Is used to establish a switching threshold. A voltage source 105, connected through the wiping contact of a potentiometer 107 to input terminal 103, is used to establish that threshold. * As before, an Inductor 109, which may be a coil in a reluctance transducer, is connected from the output terminal of circuit 101 to its negative sense input terminal 111. As in Figures 8 and 9 > variable resistance 113 connected between ground and terminal 111 permits adjustment of the time related Input voltage characteristics to circuit 101. When circuit 101 is a comparator, It acts like the inverter described above, switching the signal at its output terminal between high and low output states in response to voltage changes applied at negative sense input terminal 111 that cross the threshold es¬ tablished at positive sense input terminal 103. The resulting output signal Is a pulse train, i.e., a digi¬ tal signal. When circuit 101 is an operational ampli¬ fier, it responds to incremental changes in the input signal. As a result, the output signal Is sinusoidal. In the former case, resistance 113 varies the base frequency and In the latter, it has its greatest effect in varying the initial condition amplitude of the sinu¬ soidal signal. Another significant difference results depend- Ing upon whether circuit 101 is a comparator or opera¬ tional amplifier. For a comparator, the frequency of the pulse train generated varies when the inductance of inductor 109 changes. For an operational amplifier, the greatest variation is seen .in the amplitude of the output signal that varies in respons.e to the changes in inductance. While these changes may be detected by different circuitry, each of these sensing means em¬ bodiments generates a signal having a characteristic that varies in response to variations in the inductive time constant of feedback elements 109 and 113 * In many applications it is desirable to reduce power consumption to a minimum, for example where a battery Is used. Power consumption-ma be reduced by operating transducer circuitry only part of the time, substantially reducing average power requirements. In order not to lose "detail" in measurements, a time- control means must turn the transducer circuitry on and off at rate that is faster than the most significant variation in the variable being measured. Figure 11 illustrates circuitry analogous to that of Figure 8, except NAND gate 121 is substituted for inverter 73 as both a control means and frequency generating means. One Input terminal of NAND gate 121 receives a control signal as schematically illustrated in Figure 11. The other input terminal and the output terminal of NAND are connected with the circuit ele¬ ments as described in Figure 8 to form a variable- frequency oscillator. Only when the control signal is in its high state can the depicted circuitry operate to produce an oscillation signal at its output terminal. Thus a power savings is achieved by repeatedly pulsing gate 121 to operate the oscillator only Intermittent¬ ly. The output frequency of this network is far more sensitive to supply voltage variations than that of Figure 12 described below; therefore, it can be used as a "battery condition indicator" by making periodic checks on the oscillator frequency and comparing it against the initial condition value. Gate 121 may be a type CD 4093 quad Schmitt Trigger CMOS NAND gate. In Figure 12, a circuit analogous to that of Figure 9 is shown. Inverter 81 Is replaced by a NAND gate 131, and an electronic switch 141 is connected in series with inductor 85 which together act as the control means described for Figure 11. The output level of gate 131 is always high in the OFF mode of operation; thus, the OFF state of the inverter is always low which serves to avoid any uncertainty in the logic levels to be expected during lntermittant opera¬ tion. Switch 141 may be a type CD 4066 and Its opening and closing in response to the application of the con¬ trol signal assures the absence of oscillation during the OFF cycle. Circuitry analogous to that of Figure 10 Is illustrated in Figure 13- In the circuit of Figure 13, an electronic switch 151, which may be a type CD 4066, is again connected in series with inductor 109 of Figure 10 as a control means. A control signal opening and closing the switch is applied to switch 151. An open switch 151 prevents oscillation; a closed switch 151 permits oscillation. By thus removing the inductor from, and returning it to the network, the circuitry is essentially turned on and off to limit power consump¬ tion. Figure 14 shows a schematic embodiment of circuitry for detectin .variations in the frequency, -16- i.e. repetition rate, of a pulse train. The operation of the circuitry of Figure 14 is best understood in reference to the timing diagram of Figure 15- A frequency generator supplies the signal in which frequency variation is to be detected. For simplicity and not as a limitation, the circuitry of Figure 9 is repeated as an embodiment of a frequency generator with inverters 201 and 203 connected in series, an inductor 205 connected between the common connection of the Inverters and through a resistor 207 to the input terminal of inverter 201. A variable resistance 209 is connected between the output terminal of inverter 203 and through inductor 205 to the input terminal of inverter 203. The output terminal of in- verter 203 Is designated as point A and the signal present at that point is designated as signal A for convenience of reference. It is understood that the variable frequency " oscillator shown in Figure 14 as generating signal A can be replaced by any of the oscillator embodiments shown in Figures 8, 10, 11, 12 or 13 or any another variable frequency oscillator embodiment. A timing oscillator is constructed similarly, including inverters 211 and 213 connected in series. The fixed terminals of a potentiometer 215 are respec¬ tively connected between the common connection of in¬ verters 211 and 213 and (a) in series through a re¬ sistor 217 to the input of inverter 211 and (b) through a capacitor 219 to the output terminal of inverter 213- The wiping contact of potentiometer 215 Is connected to the terminal of capacitor 219 that is not connected to the output terminal of inverter 213- For purposes of explaining operation of the embodiment, the signal observed at the output terminal of inverter 213 Is designated as signal B. A pulse train generator Identical to the timing oscillator just described is provided, but its components can be of different values to produce dif¬ ferent pulse widths and repetition rates. That gen- erator includes inverters 221 and 223, a potentiometer 225, a feedback resistor 227 and a capacitor 229. The output signal at the output of inverter 223 is desig¬ nated as signal C to aid description of the operation of the circuit. The output of the frequency generator, signal A, is transmitted through a line connected to a count¬ ing means. In the embodiment shown, the counting means comprises two four bit counters, 231 and 233, connected in series to form an eight bit counter. The counters could each be one half of a CD 4520 binary type cir-» cuit. Each four bit counter has a count input terminal C, an enable input terminal E,' a reset terminal R and four output bit lines. Signal A is transmitted to terminal C of counter 231- The highest count bit line of counter 231 is connected to the E terminal of counter 233- The R terminals of each counter go to a reset line, RSI. The C terminal of counter 233 is grounded and its highest count bit line serves as an output terminal Q^. The output signal B of the timing oscillator including inverters 211 and 213 is connected to enable terminal E of counter 231- When that enable terminal receives a high signal, counter 231 begins counting the pulses in signal A. When that count reaches the sixteenth pulse, meaning 16 pulses have been received, a high to low transition occurs at the highest bit line and so is transmitted to the enable terminal of counter 233 which, serving as a negative edge trigger, will count one unit. The process is repeated until a count of 128 pulses Is reached where- upon the signal at terminal Q N goes high. The Q N terminal of counter 233 is connected to an 8 bit counter driver, including two 4 bit counters 235 and 237 connected to each other as counters 231 and 233 are. The enable terminal of counter 235 is connected to the Q„ terminal of counter 233 and the C terminal of counter 235 receives the signal designated as C and generated by the pulse train generator in¬ cluding inverters 221 and 223. Counters 235 and 237 could each be half of a CD 4518 BCD (Binary coded decimal) type circuit. A reset.line RS2 is connected to the reset terminals of counters 235 and 237- The output bit lines of each of counters 235 and 237 are connected, respectively, to display drivers 239 and 241 which convert the BCD Information into the form neces- sary to drive a two digit visual display 243- Drivers 239 and 241 each have a store terminal S, both of which are connected to a store line ST, and seven output terminals connected to display 243- Drivers 239 and 241 may each be a CD 4056 type circuit. Figure 14 also includes in phantom lines a D- flip flop 245 having its C terminal connected to termi¬ nal Q N of counter 233 (which in this option is not connected to counter 235). A type CD 4013 flip flop is suitable for this application. The Q NN output terminal of flip flop 245 is connected to the enable terminal of counter 235- Reset terminal R of flip .flop 245 is connected to reset line RSI. As more fully explained below, the purpose of flip flop 245 is to hold or freeze a high signal generated at the Q w terminal of counter 233, since that signal could assume Its low state in the embodiment after 256 pulses of Signal A; this would disable the 235, 237 counters causing an incorrect reading to occur. The operation of the circuit of Figure 14 is more clearly understood by reference to the timing diagram of Figure 15 where the top three time scales show the A and B signals and that at terminal Q.- when no stimulus Is applied, i.e. when the frequency of the frequency generator is in its initial condition state. If a reluctance transducer Is present in the frequency ■ generator A, that state would be a quiescent one when no force or pressure is being applied to the transducer elements. The middle three time scales show the A and C signals and signal at terminal Q N when a positive sense stimulus Is applied. The lower three time scales show the timing of the reset and store signals, RSI, RS2 and ST, respectively. At the start of an interval, the timing means switches signal B to its high condition activating- the cycle counter 231, 232 to count the transitions in the pulses generated by the frequency generating means 201, 203. The timing means is designed to switch signal B to its low state, ending the interval, on the positive transition of the 128th pulse, i.e. precisely when the Q signal goes high, if the frequency generating signal, signal A, is of the constant, quiescent frequency. These conditions are shown in the top three time scales of Figure 15- The end of timing Cycle B generates reset pulse RSI to clear the counters to zero in preparation of the next measurement Interval. Pulses ST and RS2 follow. If a positive sense stimulus Is applied causing the frequency of the signal A to Increase, the Q w output goes high before the B signal goes low to disable the cycle counter and end the Interval. This condition is illustrated in the middle three time scales of Figure 15. In this situation, when the 128th pulse is reached and Q N goes high, the display driver counter 235, 237 is activated and begins counting the pulses in signal C. This counting con¬ tinues until the end of the interval when the B signal goes low. The number of pulses of signal C counted is proportional to the increase in the frequency of signal A and, therefore, in the case of a linearly operating reluctance transducer, proportional to the force or pressure applied. As before, the end of timing signal B generates reset pulse RSI which clears the reluctance counters and with Q M low disables the display counters 235 and 237- The store pulse ST then latches the pulse count of signal C into the display drivers 239, 241 and the Information is displayed on digital display 243 as a measure of the magnitude of the stimulus,, e.g. the force or pressure applied. Following the ST pulse and the reset signal RS2 the next interval of measurement can begin immediately if desired. The circuitry of Figure 14 visually displays the change in frequency above the base frequency. Each successive display interval shows a value proportionate to the difference in frequency above the base value, but there Is no ability to show changes in frequency having a negative sense, i.e. changes reducing the frequency below the base or quiescent value. The cir¬ cuitry of Figure 16 provides this feature where needed. In Figure 16 another embodiment of a detecting means for detecting changes in the frequency of a digi- tal signal is provided. This embodiment is similar to that shown in Figure l4,.but has the ability to measure both positive and negative sense stimuli. Because this circuitry is similar to that of Figure 14, the same elements in both are given the same reference numerals as are the same signals. The operation of the circuit¬ ry of Figure 16 is better understood by reference to the timing diagrams of Figure 17- In Figure 16, a frequency generator, just like that in Figure 14 generates a pulse train, signal A. The generator receives a stimulus that changes the frequency of the pulses and that stimulus may be the changing inductance of a reluctance transducer respond¬ ing to an applied force. Signal A is applied to an 8 bit counter, comprising two 4 bit counters connected in series just as in Figure 14. The output signal of the 8 bit counter at terminal Q„ of counter 233 is con¬ nected to the input terminal of D-flip flop 245, the element that was noted as optional in Figure 14. In Figure 16 the output signal at the primary terminal, Q NN of flip flop 245 is connected to the first of two input terminals of an AND gate 247. The output at the complementary terminal §,,„ is connected to the first of two input terminals of an AND gate 2 9. Otherwise, flip flop 245 is connected in Figure 16 as it was in Figure 14. A timing oscillator, just as in Figure 14; generates signal B, a very long pulse in comparison to the pulse widths of signal A. Signal B is applied not only to the enable input terminal of counter 231 but also to the second of the two input terminals of AND gate 247 and to an inverter 251. The signal at the output of AND gate 247, signal D, is connected to the C terminal of a second D-flip flop 253- Flip flop 253 also receives reset signal RSI at its reset terminal. The output signal from the primary terminal Q of flip flop 253 is connected to a setting circuit 255 for establishing the sign of visual display 243 according to the direction of the change of the frequency of signal A. The output terminal of inverter 251 at which the complement of signal B, B, appears is connected to the second input terminal of AND gate 249. The output signal of AND gate 249, signal E, is likewise connected to an input terminal of a t ird D-flip flop 257, having the same reset connection to RSI. The output signal at the primary output terminal Q_ of flip flop 257 is connected to a second setting circuit 259 for establishing the sign of digital visual display 243 according to the direction of change of the frequency of signal A. Signals D and E, respectively, are connected to the two input terminals of an OR gate 261. The output terminal of OR gate 261 is connected to the enable terminal E of the driver counter means, including counters 235 and 237 as in Figure 14. The AND and OR gates, together with flip flop 245, comprise a decision means receiving the first enabling signal appearing at terminal Q M of counter 233 when, as before, 128 pulses have been counted. A first timing signal, the low-high transition of signal B, is generated to begin an interval and a second timing signal, the high-low transition of signal B is generated during the interval, to determine whether the frequency of signal A is increasing or decreasing. The decision means also receives these timing signals and determines whether the oscillator frequency is increasing or decreasing. The result of that determination is the generation of at least one direction signal, such as signals D and E, and the signals supplied to the setting circuits 255 and 259. Operation of the circuitry of Figure 16 is further understood by reference to the timing diagrams of Figure 17. The top five time scales in Figure 17 illustrate operation of the circuitry when the frequen¬ cy source is quiescent, i.e. when it is operating at its base frequency. This situation may include a re¬ luctance transducer with no force applied to it. Sig- nal A is constant in frequency over the entire inter¬ val. Signal B starts the interval with its low to high transition and later during the interval, preferably at its midpoint, generates as a second timing signal by undergoing a high low transition. At the beginning of the interval, signal B goes high, but the signals at termlnals Q N and Q N „ are low because the RSI and RS2 signals had already reset the network in preparation for the new intervals. As a result, signals D and E, and those at Q + and Q_ terminals of flip flops 253 and 257, are low. When 128 pulses have been counted, the signals at Q„ and Q NN go high, but in . this quiescent state, signal B drops to its low state at the same time. As a result, signal D remains low because of the transition in signal B and signal E remains low since the signal at terminal § WM drops to its low state in - the B signal transition. The driver counter 235, 237 is not enabled, no direction signal is generated and the ST pulse causes display 243 to register the zero signal at the output of counters 235, 237. The sixth through ninth timing scales of Figure 17 illustrate the operation of the circuit when a positive stimulus, a stimulus causing an increase in frequency, is applied to the -source of signal A. The increased frequency of signal A means that 128 pulses will be counted during the high level of signal B, and the signals at terminals Q*. and Q Nf . will go high during the early part of an interval, i.e. before the high-low transition of signal B. In response, signal D goes high, until the high-low transition In signal B, and display counter 235, 237 is enabled through OR gate 26l. When signal D goes high, a direction signal . appears at the Q terminal of flip flop 253 so that setting circuit 255 establishes the sign on display 243 as positive. The display counters 235, 237 then count the pulses in signal C until the high-low -transition in signal B, which switches signal D to its low state. At that point, the output of flip flop 245 has already latched with Q NN terminal signal high and QNN termi ¬ nal signal low, so that signal E remains in its low state. The output signal of OR gate 26l goes low, disabling display counter 235, 237. The display counter generates a frequency change signal that.is transmitted to display 243 by the ST pulse and which displays a value proportional to the number of pulses of signal C that were counted, a number that is propor¬ tional to the increase in frequency of signal A over the base frequency. When the stimulus is in the opposite sense causing the frequency of signal A to decrease, the situation shown in the last four time scales of Figure 17 results. In this case, from the time the interval begins when the first timing signal is given, i.e., when signal B goes from low to high, until the second timing signal is generated, i.e., at the high-low transition of signal B, fewer than 128 pulses are counted by cycle counter 231, 233-- Therefore, the signals at terminals Q M and Q NN remain low during the first portion of the interval. With the high-low transition of signal B, the B signal at the output of inverter 251 goes high and since the signal at § NN has remained high, signal -E goes high enabling driver counter 235-, 237 through OR gate 261. That is, the driver counter begins counting the pulses of signal C when signal - ! B switches from high to low. Of course, when 128 pulses have been counted, the signals at ter¬ minals Q N and Q MN still go high, meaning the signal at Q NN goes low, switching signal E to its low state. Signal D never goes high in this situation. Display counter 235, 237 is then stopped and the frequency change signal indicating the number of pulses counted is transmitted by pulse ST and appears on display 243 indicating the amount of the decrease in frequency, or, force or pressure according to the scaling. When sig¬ nal E goes high, a direction signal is produced as a high level signal at the Q terminal of flip flop 257, . . activating setting circuit 259 to set the sign of dis¬ play 243- s negative. No matter what scenario takes place during the • interval, i.e. between the low-high transitions in signal B, at the end of each interval, reset signals RSI and RS2 are generated in a conventional way to reset the cycle counter and display counter. Signal ST is also generated to save the value in the counter and display It on display 243. Another interval may begin immediately thereafter or there may be a "dead" time between intervals. Obviously, the measurement interval in any of the circuits should be much shorter than the minimum duration of variations in the frequency being detected. This same performance criteria applies whether measurements are made constantly or the circuitry is intermittently operated as described above to reduce power consumption. It is also important to realize that the digital displays 243 of Figures 14 and 16 may be replaced with other types of displays and, as dis¬ cussed in Figure 18 below, their drive signals can be used for other functions, digital, or analog. The cir- ' cultry of Figures 14 and 16 is particularly useful because it may be conveniently constructed, except for visual displays, on a single totally digital integrated circuit chip. As suggested above, the drive signals (D and E) that are developed from the interrogation of the applied force or pressure can be used for other useful functions. For example, a plus and minus digital to analog converter can be made by integrating the length of either or both of the D and E intervals to produce an analog signal level indicative of the parameter being measured. This type of circuitry will be useful ln many applications such as the control of trajecto¬ ries, speed, force, pressure or pressure regulation, level (mechanical or fluid), etc. Figure 18 shows one possible embodiment of this technique. The circuit shown in Figure 18 includes an OR gate 270 having an output connected to switches 272 and 274. Drive sig¬ nals D and E are applied to switches 272 and 274, re¬ spectively, as well as to the respective inputs of OR gate 270. Switch 272 is connected to a resistor 276, and a grounded resistor 27-8 is connected to the line interconnecting switch 272 and resistor 276. A signal is applied to resistor 276. The output of resistor 276 is connected to each of a switch 280, a capacitor 282 and to the negative input of an amplifier 284. Switch 274 is connected to , a resistor 286, and a grounded resistor 288 is connected to the line inter¬ connecting switch 274 and 286. A signal v /\r) p- \ is applied .to resistor 286. The output of resistor 286 is connected to the positive input of amplifie-r 284, to a capacitor 289 and to a switch 290. The latter switch is connected across capacitor 289, and the capacitor is connected to ground. A RESET signal can be applied to each of switches 280 and 290. The output signal of amplifier 284 is designated V , and the output line of amplifier 284 is connected to switch 280, to capacitor 282, and optionally to a switch 292 whose output is designated V O5. In the operation of the foregoing circuit, amplifier 284 of the network will respond to the E interval ^ through OR gate 270 and by closing switch 272 when E is high. In this case, a fixed volt¬ age appears at the input of resistor 276 connected to the inverting port of amplifier 284 resulting in the output of amplifier 284 having a negative moving ramp with a fixed slope, the length of which is dictated by the length of E. Resistor 278 references the invertin Input to ground when switch 272 is open . In a similar manner , amplifier 284 responds to the D interval through OR gate 270 and by closing switch 274 to place * a fixed voltage on the Input of resistor 286 which is connected to the non-inverting port of amplifier 284; the output of amplifier 284 generates a positive moving ramp with a fixed slope, the length of which is dic¬ tated by the length of the D Interval. As before, resistor 288 references the non-inverting input to ground when switch 274 is open. In this way, a series of short ramps, all of equal positive or negative non- unitary slopes (i.e. having values other whole numbers) and each having a length (and therefore a final ampli¬ tude) which is directly related to the length of time the signal appears. If neither E or D appears during a measurement interval, the output of amplifier 284 re¬ mains unchanged which is indicative of the fact that the measured parameter is the same as the reference and no correction is needed. In this case, OR gate 270 remains inactive until the next occurrence of either the D or E interval. In essence, the system integrates intermittent and variable intervals of time over the continuous progression of time, a unique and different concept in the art of control system theory. It should be noted that the Integration time constants for the positive or negative corrections do not have to be equal; this would be especially useful if the correc¬ tion in one direction requires a greater weight than that of the opposite direction. Further, the slope, or correction could also be adaptive by allowing the adapting input signal to automatically change the inte¬ gration time constant in response to certain pre¬ selected and properly weighted system parameters. This is suggested by the V AD p signals to the now variable input resistors 276 and 286. Finally, capacitors 282 and 289 are the reac¬ tive portion of the integration time constant, and since they represent the storage elements in the con¬ trol network, switches 280 and 290 along with the reset pulse shown are used to either Initialize the system or to clear it as requirements dictate. As an alternative to the output signal dis¬ cussed above, sample and hold function 292 (shown in phantom) could be added to the output. In this case, each and every measurement interval for the generation of the D or E signals would result in a brand new out¬ put signal V whose absolute value is a direct repre¬ sentation of the measured parameter rather than a cor¬ rection of the old Vo as previously described. The new value would then be stored in capacitor 294 by virtue of the momentary closure of switch 292 when the sample pulse occurs. The invention has been described with refer¬ ence to certain preferred embodiments. Various substi- tutions and modifications without departing from the spirit of the invention will occur to those of skill in the art. Accordingly, the scope of the Invention is limited solely by the following claims. We claim: 1. A reluctance transducer comprising an inner induc- •tive coil for generating a magnetic field in response to the flow of a direct electrical current, reluctance means proximate and surrounding said coil for modifying the reluctance presented to said magnetic field in response to changes in the relative positions of said coil and said reluctance means, and flexible coupling means affixed to one of said coil and said reluctance means for moving said coil relative to said reluctance !._eans In response to applied force.

Claims: 2. The invention of claim 1 wherein said reluctance means comprises a tubular receiving means mounted on said coupling means for receiving said coil within it. 3. The invention of claim 2 wherein said coil is wound on a form including an air core and said reluctance means Includes a rod mounted within said cylinder and received by said air core. 4. The invention of claim 1 wherein said reluctance means comprises a magnet. 5. The Invention of claim 4 wherein said magnet has a concave face opposite said coil. 6. The invention of claim 1 wherein said coupling means comprises a deflectable beam and said reluctance means comprises a magnet mounted on said beam opposite said coil. 7. A signal generator for producing an electrical signal having a variable frequency, said generator comprisin : inverting means for receiving an input signal having one of two possible states and for generating a variable frequency, output signal, said output signal having a state opposite the state of the Input signal when the value of the input signal exceeds a threshold value; and variable inductance means creating a magnetic field when energized and being electrically connected to said inverting means, said variable inductance means producing an inductance to establish a time constant according to the reluctance of the magnetic field about said variable Inductance means, said time constant controlling the frequency of the output signal of said inverting means. 8. The Invention according to claim 6 wherein said variable inductance means comprises a transducer whose 5 inductance is variable according to the value of a parameter. ~ . The Invention of claim 6 wherein the output signal of said inverting means comprises a pulse train, said inverter means has an input and an output terminal for 0 producing the output signal at said output terminal, and said variable Inductance means is connected between said input and output terminals as a feedback means for generating said pulse train. 10. The invention of claim 6 further including control 5 means for controlling the operation of said frequency generating means as a function of time. 11. The invention of claim 9 wherein the output signal of said inverting means comprises a pulse train, said control means comprise NAND gate means having first and 0 second input terminals and an output terminal for pro¬ ducing an output signal at said output terminal in¬ verted in sense from that of the signals at the input terminals only when the signals at the input terminals have the same sense, and said variable inductance means 5 is connected between said output terminal and said first input terminal as a feedback means for generating said pulse train when a control signal is present at said second input terminal. 12. The invention according to claim 6 wherein said ^ inverting means comprises a Schmitt inverter and said variable frequency output signal comprises a pulse train whose frequency is controlled by said time con¬ stant. 13. The invention according to claim 6 wherein said inverting means comprises a pair of Schmitt inverters, and said inductance means comprises an Inductor and resistance means connected across the respective Schmitt inverters. 14. The invention according to claim 6 wherein said 5 inverting means comprises analog comparator means for receiving an input signal and a threshold establishing signal, the output signal comprising a digital signal having the state opposite the state of the input signal - when the amplitude of the input signal exceeds said 10 threshold. 15- The Invention according to claim 6 wherein said Inverting means comprises operational amplifier means for receiving an input signal and a threshold estab- - lishing signal, the output signal comprising an analog signal varying according to changes in the amplitude of the input signal and having the state opposite the state of the input signal when the amplitude ' of the input signal exceeds said threshold. 16. The invention of claim 14 and further including 20 control means for controlling the operation of said amplifier means as a function of time, said control means comprising electronic switch means connected in series with said variable inductance means for re¬ ceiving a control signal to enable generation of said 25 analog signal. 17. The invention of claim 14 and further including control means for controlling the operation of said amplifier means as a function of time, wherein said operational amplifier means includes Inverting and non- *30 inverting input terminals, and said -control means com¬ prises control oscillator means connected to said non- inverting terminal for generating a control signal. 18. The invention of claim 13 wherein the output sig¬ nal of said comparator means comprises a pulse train, 35 said comparator means has a reference input terminal and a comparing input terminal for producing an output signal indicative of which input terminal has applied to it the larger magnitude signal, and said variable inductance means is connected between said comparing input terminal and said output terminal as a feedback means for generating said pulse train. 19. The Invention of claim 17 and further including control means for controlling the operation of said comparator means as a function of time, said control means comprising electronic switch means connected in series with said variable inductance means for re¬ ceiving a control signal to enable generation of said pulse train. 20. The invention of claim 17 and further including control means for controlling the operation of said comparator means as a function of time, said control means comprising control oscillator means connected to said reference input terminal for generating a control signal. 21. An electronic processing system for measuring the frequency of electrical signals generated by a variable frequency signal generator, said system comprising: cycle counting means for counting cycles of the signal generated by said variable frequency generator and gener¬ ating an enabling signal in response to a predetermined number of cycles; timing means for generating a timing signal for activating said cycle counting means at the beginning of a._predetermined interval; pulse train generating means for generating a pulse train signal uniform in time during said interval; and driver counter means receiving said enabling signal and said pulse train signal for counting the number of pulses In said pulse train signal during said interval after said enabling signal is received and for generating a frequency change signal in response to the number of said pulses counted. 22. The Invention of claim 20 further including visual display means receiving s'aid frequency change signal for displaying a number proportionate to the number of pulses counted by said driver counter means. 23« T e invention of claim 20 wherein said frequency change signals are digital, said invention further including: transmitting means for receiving said frequency change signals and for transmitting the received frequency change signals; and integrating means connected to said transmitting means for integrating transmitted signals to produce output signals having non- unitary slopes and lengths varying according to the duration of the transmitted signals. 24. An electronic processing system for measuring the frequency of electrical signals generated by a variable frequency signal generator, said system comprising: cycle counting means for counting cycles of the signal generated by said variable frequency generator and gener¬ ating a first enabling signal in response to a predetermined number of cycles; timing means for generating a first timing signal means to activate said cycle counting means at the beginning of an Interval and for generating a second timing signal during said interval; pulse train generating means for generating a pulse train signal uniform In time during said interval; decision means receiving said first enabling signal and said first and second timing signals for determining the direc¬ tion of change of the frequency of said electrical signal and for generating a direction signal in response to the di¬ rection of change of said frequency and for generating a second enabling signal during the time between the generation of said first enabling and said second timing signals; and driver counter means receiving said second enabling signal and said pulse train signal for counting the number of pulses In said pulse train signal while said second enabling signal is being received and for generating a frequency change signal In response to the number of said pulses counted. 25« The invention of claim 22 further including visual display means receiving said frequency change signal and -said direction signal for displaying a number proportionate to the number of pulses counted by said driver counter means and the direction of change of said frequency. 26. The invention of claim 22 wherein said decision means comprises logic means for generating said second enabling signal after generation of said first enabling signal and until generation of said second timing sig¬ nal. 27. The Invention of claim 22 wherein said decision means comprises logic means for generating said second enabling signal after generation of said second timing signal and until generation of said first enabling signal. 28. The invention of claim 22 wherein said decision means includes a D flip flop circuit having C and D input terminals and hig and low output terminals, said output terminals providing complementary output sig¬ 10 nals, said flip flop circuit receiving at said C input terminal said first ena&llng signal, a first AND gate having two input terminals receiving at one of said input- terminals said second timing signal and receiving at said other input terminal the signal from said high 15 output terminal, a second AND gate having two input terminals receiving at one of said input terminals said second timing signal and at said other input terminal the signal from said low output terminal and an OR gate receiving, and generating said second enabling signal 20 in response to the outpuit signals of said first and second AND gates . 29. The invention of cl-aim 22 wherein said frequency change signals are digital, said invention further . including: ~ - transmitting means for receiving said frequency change signals and for transmitting t e received frequency change signals;; and integrating means connected to said 0 transmitting me ^ ans for Integrating trans¬ mitted signals to produce output signals having non-unitary slopes and lengths varying according to the duration of the transmitted signals. -36- 30. A digital-to-analog converting system for con¬ verting digital electrical signals having alternate first and second states having durations, Into analog signals, said system comprising: transmitting means for receiving the digital electrical signals and for transmitting received digital signals when said signals are in said first state; and integrating means connected to- said transmitting means for integrating trans¬ mitted signals to produce output signals having non-unitary slopes and lengths varying according to the duration of the transmitted signals. 31. The invention according to claim 30 for receiving first and second electrical signals, each signal having alternate first and second states, the first states being high states and the second states being low states, and the high states being received by said transmitting means at different times, wherein: said transmitting means comprises OR gate means for receiving said first and second signals and for transmitting the one of said signals which is in the high state. 32. The invention according to claim 30 wherein said transmitting means further comprises switching means interposed between said OR gate means and said inte¬ grating means, said switching means establishing an electrical connection between said OR gate means and said integrating means when one of said first and sec¬ ond signals is in the first state to enable transmis¬ sion of the respective first and second signals and said switching means preventing transmission of the respective first and second signals when the respective signals are in the second state. 33- The invention according to claim 31 wherein said OR gate means has an input for receiving the first and second signals and an output for transmitting said sig¬ nals, and said switching means comprises first and second switches connected to the output of said OR gate means, said first switch being operable by the first signals and said second switch being operable by the second signal; and wherein said Integrating means comprises an operational amplifier having an inverting input port connected to said first switch, a non-inverting input port connected to said second switch and an output port, and reactive means connected to said Inputs. 34. The invention according to claim 3 wherein said reactive means comprises a first capacitor connected between the inverting port and the output port of the operational amplifier, and a second capacitor connected between said non-inverting port and ground. 35« The invention according to claim 33 and further including variable resistance means connected to the respective input ports of said operational amplifier for receiving adaptive signals to vary said resistance means to change the integration time constant of said integrating means. 36. The invention according to claim 33 and further including sample and hold means connected to the output port of said operational amplifier for generating out¬ put signals whose absolute value Is directly propor¬ tional to the duration of the high states of said first and second signals, respectively. 37. The invention according to claim 3 wherein said sample and hold means comprises a switch and a capaci¬ tor connected to said switch, said switch being actu- able in response to the generation of a sample signal to transmit the output signal of said operational amplifier to said capacitor. 38. The invention according to claim 30 and further including resetting means connected to said integrating means for resetting said integrating means in response to the generation of a resetting signal. 39. The Invention according to claim 37 and further' including adaptive means connected to said integrating means for varying the integration time constant of said integrating ' means in response to the generation of adapting signals.

Inventors: D ANTONIO NICHOLAS F, D ANTONIO RONALD W, D'ANTONIO, NICHOLAS, F., D'ANTONIO, RONALD, W.
Applicants: ANTONIO NICHOLAS F D, ANTONIO RONALD W D, D'ANTONIO, NICHOLAS, F., D'ANTONIO, RONALD, W.
Application year: 1985
Main classification: G08C19
IPC codes: G01D5