CIRCUIT FOR LIMITING JITTER TRANSIENTS DURING SWITCHING

Abstract: A phase comparator is included with each incoming channel to compare the clock phase of the incoming signal and a local oscillator. The phase comparator of an on-line active unit generates a signal to control the oscillator to maintain its output in phase with the incoming signal. The generated control signal is also connected to capacitor storage in associated channel phase comparators to provide them with an initial starting control voltage when they are switched in to be the receiving channels. Thus eliminating the uncontrolled operation of the oscillator during switching interval.

Description: The present invention relates to a circuit for limiting jitter transients during switching between two digital signals. The circuit is of the type described in the preamble of claim 1. It is known that during switching between two digital signals of the same character, which are received with a different phase, the resultant jitter transient must be kept within the amplitude and frequency limits which are predetermined by the international recommendation (recommendation G. 703 of CCITT) to secure the desired quality of the resultant digital signal downstream of the switching operation. An already known solution to this problem is to utilize the alignment word of the received digital signal prior to switching for synchronizing the frequency of the clock signal of the digital signal downstream of the switch. This solution theoretically avoids the jitter transient of the digital signal during the switching transient, but involves the use of an alignment word detection circuit which is rather complex to provide. The USA patent 4.511.859 is relative to a circuit that solves the problem maintaining the output signal fixed in absolute frequency and phase even though signals used as alternative references threfore are not in phase synchronism; this is obtained by "forcing" the signal references in the circuit to generate an output signal frequency not correlated with the references but having a costant absolute frequency. The circuit of the above patent is not simple and is expensive to implement since a mixing of analog and digital devices are used; moreover it presents granurality changes due to DAC. It is the object of the present invention to obviate these and other disadvantages of the prior art hitless switching, and to provide a circuit which is simpler and less expensive with respect to prior art solutions. The circuit for limiting the jitter transient of a PCM signal during switching which attains the above and other objects is inventively defined by the characterizing clause of the appendend main claim. It will be appreciated that the circuit according to this invention provides (and thus differentiating conceptually and physically from US Patent 4.511.859) during switching a gradually passage from the phase of one reference signal to that of the other reference signal. These and other features of the present invention will become more apparent from the following description of a preferred embodiment thereof, given merely by way of example and in no limiting sense, referring to the accompanying drawing, whose single figure is a block diagram of the electric circuit according to the present invention. Referring to the figure, CK1 indicates the clock signal of a digital signal at input 1; CK2 indicates the clock signal of a digital signal at input 2; REF CK indicates the reference clock signal which is generated by a conventional voltage controlled quartz oscillator VCXO and is applied to the inputs of the two identical automatic phase control circuits PLL1 and PLL2, which alternativly control the phase of the voltage controlled quartz oscillator VCXO in a similar manner. I1 and I2 indicate switches which, according to a predetermined logic; determine the phase latching of the oscillator VCXO to the clock signal of the digital signal at input 1 labeled CK 1 through the phase control circuit PLL1 or the digital signal at input 2 labeled CK 2 through the phase control circuit PLL2. Δ indicates a conventional phase comparator circuit which compares the phase of the clock signal of the digital signal at input 1 (CK1) or 2 (CK2) with the phase of the reference clock signal REF CK. The signal Vx1 indicates the direct voltage, having a magnitude proportional to the phase difference between the two input signals CK1 and REF CK to the phase comparator Δ , at the input to the operational amplifier IC3. The signal V3 indicates the voltage at the output of the operational amplifier IC3, which is equal to the control voltage VC1 of the voltage controlled quartz oscillator VCXO when the switch I1 is closed and simultaneously the switch I2 is open. This same voltage V3 is also applied to a first input of the operational amplifier IC4 of the phase control circuit PLL1 and to a first input of the operational amplifier IC2 of the phase control circuit PLL2. The signal Vx2 indicates the direct voltage having a magnitude proportional to the phase difference between the two input signals CK2 and REF CK to the phase comparator Δ of phase control circuit PLL2, at the non-inverting input to the operational amplifier IC1. The signal V1 indicates the output voltage from the operational amplifier IC1 which is equal to the control voltage of the voltage controlled quartz oscillator VCXO when the switch I2 is closed and simultaneously the switch I1 is open. This same voltage V1 is also applied to a second non-inverting input of the operational amplifier IC2 of phase control circuit PLL2 and to a second inverting input of the operational amplifier IC4 of the phase control circuit of PLL1. The signal V2 indicates the output voltage from the operational amplifier IC2 of the phase control circuit PLL2; I3 indicates a switch which is closed when the switch I1 is closed and the switch I2 is open. The closure of switch I3 makes it possible to apply the signal voltage V2 to the memory circuit of the phase control circuit PLL2 consisting of the resistances R11, R12 and the capacitor C11, The resistor R13is a matching resistor between the output of the memory circuit and a second inverting input of the operational amplifier IC1 of the phase control circuit PLL2. The signal V4 indicates the output voltage from the operational amplifier IC4 of phase control circuit PLL1; I4 indicates a switch which is closed when the switch I2 is closed and the switch I1 is open, and under such conditions applies the signal voltage V4 to the memory circuit of the phase control circuit PLL1 consisting of the resistances R1, R2 and the capacitor C1; R3 designates a matching resistance between the output of the memory circuit and a second inverting input of the operational amplifier IC3 of the phase control circuit PLL1. The principle of operation of the circuit according to the present invention will be explained referring in particular to the figure. Assuming that the voltage controlled quartz oscillator VCXO is phase latched to the clock signal of the digital signal at the first input CK1, the switches I1 and I3 are closed and the switches I2 and I4 are open. The voltage V3 = VC1, besides controlling the phase of the voltage controlled quartz oscillator VCXO, is applied to the input of the operational amplifier IC2 of the phase control circuit PLL2 and provides at its output a voltage V2 which charges the memory circuit consisting of capacitor C11 and resistors R11 and R12 of the phase control circuit PLL2; this provides at the input of operational amplifier IC1 of the phase control circuit PLL2 a negative feedback voltage such as to maintain the output signal voltage V1 from the operational amplifier IC1 of the phase control circuit PLL2 at a value equal to VC1, independently of the value of the input signal voltage Vx2. When the switching between the digital input signals occurs, i.e. the voltage controlled quartz oscillator VCXO is phase latched to the clock signal of the digital signal at the second input CK2, the switches I1 and I3 are opened andthe switches I2 and I4 are closed. The control voltage for the voltage controlled quartz oscillator VCXO at the first moment is V1 = Vc1 and is maintained at the same value by the charge voltage of the capacitor C11. The signal voltage V1 will then tend to reach the new value VC2 equal to the new value of the control voltage of the oscillator VCXO at a rate equal to that of the discharge of the capacitor C11 on R12. The discharge time constant for this memory comprised of the capacitor C1 and resistor R2 is given by T≃CR2 and is dimensioned in such a manner that the jitter transient imparted to the signal is within the amplitude and frequency limits predetermined by the international recommendation (recommendation G.703 of CCITT). After the switching transients subside the phase control circuit PLL1 operates as described above for phase control circuit PLL2. The voltage V1 = VC2, besides controlling the phase of the voltage controlled quartz oscillator VCXO, is applied to the input of operational amplifiers IC4 of the phase control circuit PLL1 and determines at its output a signal voltage V4 which charges the memory circuit of the phase control circuit PLL1; this then establishes as the input of operational amplifier IC3 of PLL1 a degenerative voltage such as to maintain the signal voltage V3 at the output from operational amplifier IC3 of PLL1 at a value equal to VC2, independently of the value of the input voltage Vx1.

Claims: An arrangement for limiting jitter transients during the interval of switching between a first and a second channel (CK1, CK2) comprising: a voltage controlled frequency oscillator (VCXO) including an output (REF CK) and a control input (through I1 or I2); a first and a second phase detector (PLL1, PLL2) each having an input connected to an associated incoming channel (CK1, CK2) and another input connected to said oscillator output (REF CK), including operative means (Δ, IC3, IC1) operative to detect phase differences between said inputs and developing a control voltage (VC1, VC2) as a function of the phase differences; switching means (I1, I2) for selectively impressing said control voltage (VC1, VC2) from one of said first and second phase detectors (PLL1, PLL2) onto said oscillator control input (through I1 or I2) for accordingly changing the phase of said oscillator output signal (REF CK) to conform with said input phase differences, each said phase detector (PLL1, PLL2) further including storage means (R1, R2, C1; R11, R12, C12) for storing a voltage value, characterized in that: a) the voltage controlled frequency amplifier (VCXO) is a voltage controlled constant frequency amplifier; b) the storage means (R1, R2, C1; R11, R12, C12) are time degradable storage means and store the control voltage; c) second switching means (13, 14) are included in each of the phase detectors (PLL1, PLL2) and operated to selectively impress the control voltage from the phase detector (PLL1, PLL2) connected with the voltage controlled constant frequency amplifier (VCXO) through the first switching means (I1, I2)to the time degradable storage means (R1, R2, C1; R11, R12, C12) of the other unconnected phase detector, whereby a control voltage is available which will tend to reach the control voltage of the unconnected phase detector (PLL1, PLL2) upon switching of the latter to the connected state. An arrangement as claimed in claim 1 wherein the operative means (Δ ,IC, IC3) includes a phase comparator (Δ) and a first operational amplifier (IC1, IC2) said phase comparator (Δ) having an output, and a first and a second input connected respectively to said oscillator output and said associated incoming channel, said (CK1, CK2) first operational amplifier (IC1, IC2) having a first and a second input and an output, filter means (C2, R7) connecting said comparator output to said operational amplifier's first input, said operational amplifier output comprising said control voltage (VC1). An arrangement as claimed in claim 2 further including a feedback path from said the output of first operational amplifier (IC1, IC3) to said operational amplifier second input. An arrangement as claimed in claim 3 further including a resistor (R4, R14) in said feedback path. An arrangement as claimed in claim 2 including switch means (13, 14) in said first and second phase detectors (PLL1, PLL2) operated to maintain said operational amplifier output disconnected from said associated first or second phase detection storage means (R11, R12, C11, R1, R2, C1) respectively when in an active state. An arrangement as claimed in claim 2 wherein said other connect means includes a second operational amplifier (IC2) having an output connected to said storage means (R1, R2, C1; R11, R12, C11). An arrangement as claimed in claim 1 wherein said storage means comprises a capacitor (C11). An arrangement as claimed in claim 7 including resistive means (R13) connecting said storage means capacitor (C11) to said first operational amplifier second input.

Inventors: CELLERINO, GIULIANO
Applicants: SIEMENS TELECOMUNICAZIONI S.P.A.
Application year: 1985
Main classification: H04L1
IPC codes: H03L7, H04L1, H04L7, H03K5, H03M1