LIGHT-EMITTING DIODE ARRAY

Abstract: Light-emitting diodes (LEDs) with supporting circuits on a chip or wafer for a full width array in which the chip is first coated with silicon dioxide to form a thin film layer, a plurality of holes corresponding in number and configuration to the desired array are next opened in the layer, gallium phos­ phide LEDs, together with p-n junctions and contact layers, are then grown epitaxially in the holes, and finally attendant LED operating circuits are epitaxially formed on the chip together with operative connections to the individual LEDs by integrated circuit techniques.

Description: The invention relates to light-emitting diode (LED) arrays, and more particularly, to a method of fabricating an LED array which may be combined with other like LED arrays to form a full-width image write bar. The use of an array of LEDs to write images on a record member, such as the photoreceptor of a xerographic type imaging system, has taken on renewed interest with the current interest in electronic image printers and the increased LED efficiencies obtained with gallium arsenide (GaAs) as LED substrate. As will be understood, LED arrays typically comprise one or more linear rows of LEDs in close juxtaposition with one another on a single chip or substrate. In electronic printer applications, the individual LEDs of the array are actuated in accordance with an image signal input. The resulting image rays created by the LEDs, which are focused onto the photoreceptor, create or write a latent electrostatic image on the photoreceptor as the photoreceptor is moved in synchronism therewith. Following this, the latent electrostatic image is developed, transferred to a suitable copy substrate material such as a copy sheet, and thereafter fused or fixed to provide a permanent copy. However, the number of LEDs that can be packed onto a single chip or wafer is limited, and this, in turn, limits the image resolution that can be achieved with a single LED array. Joining several of the smaller LED arrays together to form a longer array, and particularly, to form a full-length array with increased resolution, along with the attendant simplification of the printer optical system that this allows, is desirable. A primary limitation on resolution and density of a full-page width LED array is the need to wire each individual LED to an off-chip driver circuit. Much higher resolution and lower cost can be achieved if the drive circuitry can be on the same chip as the LED. This would eliminate much of the hybrid wiring normally required. Moreover, if these self-driving chips could be accurately cut and butted to form a continuous single line LED array, this would eliminate expensive optical or electronic stitching methods. Infra-red (IR) LEDs can be made with an efficiency more than an order of magnitude, and in some cases two orders of magnitude, greater than present day visible light LEDs. Moreover, because of recent advances in materials preparation, such as metallo-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE), IR LEDs can now be made from commercially-available materials like gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) in heterostructures which show reliability and uniformity much superior to previous visible-light LEDs. However, because these high efficiency IR LED arrays are structured differently from previous LED arrays, IR LED arrays have their own constraints and advantages. Because of past photoreceptor spectral limitations and the consequent unavailability of IR photorceptors, LED arrays are currently made from zinc-diffused gallium arsenide phosphide (Ga(As,P)) grown epitaxially on gallium arsenide (GaAs) or gallium phosphide (GaP). As will be understood, Ga(As,P) is an indirect gap semiconductor and LEDs constructed of this material are of relatively low external efficiency, usually 0.02 to 0.05%. With nitrogen doping, efficiency may be raised to 0.2 to 0.5% but there are uniformity problems associated with this. These types of LED arrays are also Lambertian radiators. The light typically must be collected by gradient index fiber lenses (with a numerical aperture of 0.08 to 0.3). This results in low overall optical system efficiency, usually less than 5%. Moreover, for a typical 3300 spot or pixel system, the LEDs that comprise the array must be time multiplexed by a factor of 20 or so or else 3300 drive transistors must be used. These factors combine to produce a very low level of energy at the photoreceptor, with resultant limitation of the processing speed to the approximately 50 mm/second range. Moreover, since III-V class LED materials, such as GaP and GaAs, when used as substrates, are easily damaged by saw cutting, etc., LED chips or arrays cannot normally be effectively butted together but instead must be staggered in two rows and then optically interlaced with rather complex and relatively expensive optical means such as a pair of gradient index fiber lenses. In addition, present state-of-the-art greatly limits the use of on-chip circuitry on III-V materials. GB-A-1 467 096 discloses a method of making an array of semiconductor light-emissive elements using layers of GaAlAs of opposite conductivity on a GaAs substrate, with the n-type layer being doped by ion implantation. GB-A-2 099 221 discloses an array of LEDs on one chip, and RAM and driver circuits on a separate chip mounted on the same substrate as that which supports the LED chip. The present invention accordingly relates to a method for fabricating a high-speed, high-resolution LED array as claimed in the respective appended claims, and to the LED arrays produced. The present invention will now be described by way of example, with reference to the accompanying drawings, in which: Figure 1 is a top view of a surface-emitting type LED chip; Figure 2 is a side view in cross-section of the LED chip shown in Figure 1; Figure 3 is an enlarged side view in cross-section showing details of a GaP LED chip fabricated on an SiO₂ coated substrate; Figure 4 is a view illustrating a plurality of LED chips assembled together in staggered fashion to form a full-width write bar; Figure 5 is a view illustrating a plurality of LED chips butted together end-to-end to form a full-width write bar; Figure 6 is a side view in cross-section of a surface-emitting type IR LED according to the present invention; Figure 7 is a top view showing the IR LED of Figure 6 in a multiple LED array; Figure 8 is a side view in cross-section depicting an alternative surface-emitting type IR LED array construction according to the present invention; Figure 9 is a top view of the IR LED shown in Figure 8 in a multiple LED array; Figure 10 is an isometric view of an edge-emitting type IR LED according to the present invention; Figure 11 is a top view showing the IR LED of Figure 10 in a multiple LED array; Figure 12 is a side view in cross-section of the IR LED array shown with barriers to prevent optical cross-talk between adjoining LEDs; and Figure 13 is a side view in cross-section illustrating a cross-talk preventing barrier formed by proton bombardment. Referring to the drawings, there is shown the solid state full-width write bar, designated generally by the numeral 10. Write bar 10 has at least one linear array 12 of light-emitting diodes (LEDs) 14. In the exemplary arrangement described herein, write bar 10 is used to write, either directly or through suitable lens means, images on a moving record member such as a previously-charged photoreceptor (not shown) of a xerographic system,through selective actuation of the individual LEDs 14 in the array 12 in accordance with an image signal or pixel input. For this purpose, the array 12 of LEDs 14 has an overall length equal to or slightly greater than the effective width of the photoreceptor. Ordinarily, write bar 10 is disposed at right angles to the direction of photoreceptor movement and in predetermined spaced relation to the surface of the photoreceptor, as will be understood by those skilled in the art. As a result, write bar 10 writes, i.e. exposes, the photoreceptor a line at a time as the photoreceptor moves therepast to create a latent electrostatic image represented by the image signal input to write bar 10. Following writing of the image on the photoreceptor by write bar 10, the latent electrostatic image created on the photoreceptor by LED write bar 10 is developed and transferred to a suitable copy substrate material such as a copy sheet. The copy sheet bearing the transferred image is thereafter fused or fixed to render the copy permanent while the photoreceptor is cleaned in preparation for recharging. Write bar 10 is formed from a plurality of generally rectangular substrates or chips 16 separated as by sawing or other suitable means from one or more larger silicon wafers (not shown) for example. Chips 16 may be assembled in the staggered relationship as shown in Figure 4, or butted end-to-end as shown in Figure 5, to form a write bar of desired length. Where chips 16 are disposed in staggered fashion, as shown in Figure 4, the chips may, for example, be operatively joined or stitched together by suitable electrical circuitry effective to crossover from one chip to the next when writing an image line without loss or distortion of the image at the chip junctions. Alternatively, chips 16 may be optically joined or stitched together in effect to remove the stagger and align the images produced by each chip at the record member without loss or distortion of the image at the junctions between chips. Where a plurality of chips 16 is arranged in end-to-end relation, as shown in Figure 5, the chips, following alignment with one another, are joined together by suitable means to provide a write bar 10 of desired length. The top or upper surface 19 of chip 16 is coated with a thin film layer 20 of silicon dioxide (SiO₂) for example. An array of holes 24 is next opened in layer 20, holes 24 being of a predetermined size, spacing, and orientation to provide an array 12 of desired size and resolution. Holes 24 may be formed photolithographically by placing a photo-mask of appropriate configuration (not shown) over layer 20 and applying a suitable etch to remove the layer 20 at the point where holes 24 are desired. Following formation of holes 24, gallium phosphide (GaP) LED structures 26 are grown in each of the holes 24, preferably by chemical vapor deposition (CVD). Concurrently, p-n junctions 28 and electrical contact layers 29 are grown with each layer of the GaP LED structure 26. Other growing techniques may be employed instead, such as molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or metallo-organic chemical vapor deposition. Following the formation of the GaP LED structures 26, LED contacts 32 and other supporting circuitry, such as a suitable fanout or distributing circuit 33 and a signal processing circuitry 35, are fabricated on chip 16 using conventional silicon integrated circuit (IC) techniques. Fanout circuit 33 provides image signals to the chips of write bar 10, either in parallel to the chips or serially to all chips of bar 10 in a preset sequence, or in a suitable serial/parallel combination. Since the GaP LED structures 26 are relatively high temperature materials, the IC processing, which is normally at a lower temperature, has no adverse effect on the previously-formed LED structures. A Si₃N₄ temporary protective coating may be placed over the GaP structure to minimize adverse effects during IC processing. While write bar 10 is shown and described as having a silicon substrate with GaP LED structures, other substrate materials, such as gallium phosphide (GaP) or gallium arsenide (GaAs) which can operate in the visible or near infra-red, may instead be used as described below. Referring now to Figures 6 and 7 of the drawings, a high efficiency heterostructure array 12 of IR LEDs 14 is fabricated according to the present invention. Heterostructure LED array 12 has a GaAs-n wafer or substrate 112, with one side 113 metallized to form a common electrical contact surface 114 for the LEDs of the array. A first layer 120 composed of Ga 1-x Al x As-n is grown on the opposite side 115 of substrate 112 followed by a layer 122 of either GaAs-p or Ga 1-z Al z As-p and a layer 124 of Ga 1-y Al y As-p. The thickness of substrate 112 is approximately 0.254 to 0.381 mm while the combined thickness of layers 120, 122, 124 is approximately 5 to 10 µm. Suitable ranges for x, y and z and approximate layer thicknesses for this embodiment are given in Table 1. An electrical contact layer 128 of GaAs-p+ (heavily doped p-type), which forms an electrical contact area for a metallization layer 134, is next grown over the layer 124, followed by an insulating layer 130 such as SiO₂. Contact and insulating layers 128, 130 are selectively etched at predetermined points to form an LED light-emitting area or window 135 of predetermined dimension and configuration defining each LED 14, LEDs 14 being formed a preset spaced intervals along wafer 112 in the array configuration desired. In the example shown in Figures 6 and 7, LEDs 14 are formed in parallel rows 136, 138, with the LEDs of each row being offset or staggered with respect to the LEDs of the other row. Further selective etching is used to remove the portion of insulating layer 130 bordering the LED windows 135 and uncover a portion 128' of contact layer 128. The uncovered portions 128' of bonding layer 128 surrounding each LED 14 are metallized at 134 to form a metal contact pad for each LED. A metal lead 137 is bonded to each LED contact pad. While array 12 is shown and described as comprising two rows of LEDs 14, array 12 may comprise one or any number of parallel rows of LEDs 14. In the embodiment shown in Figures 8 and 9, where like numbers refer to like parts, the LEDs 14 of array 12 are there formed in a single row 136'. In this embodiment, contact layer 128 is dispensed with and the metallization layer 134 is placed directly on third layer 124, including the light-emitting windows 135 of LEDs 14. In this embodiment, metallization layer 134 is made extremely thin (or of a suitable transparent electrically conducting material) so that layer 134 is transparent to the light-emitting windows 135 of LEDs 14. Suitable ranges for x, y and z and approximate layer thicknesses for this embodiment are given in Table II. In the embodiment shown in Figures 6-9, array 12 comprises one or more linear arrays of surface-emitting LEDs. In the embodiment shown in Figures 10 and 11, where like numbers refer to like parts, array 12 comprises a linear array of edge-emitting LEDs. Referring thereto, a first layer 150 of Ga 1-x Al x As-n is grown on substrate 112 followed by an emitting layer 152 of GaAs-p or Ga 1-z Al z As-p. In this arrangement, LEDs 14 emit from layer 152 along edge 155 of substrate 112. Layer 156 of Ga 1-y Al y As-p is grown on layer 152 followed by contact layer 128 and insulating layer 130. Suitable ranges for x, y and z and approximate layer thicknesses for this embodiment are given in Table III. In all of the above structures, a layer of GaAs-n of 1 to 5 µm thick may be grown prior to the first Ga 1-x Al x As layer to act as a buffer layer and improve crystal quality. If this buffer layer is used, first layer 120 (Figures 6-9) or 150 (Figures 10, 11) can be as thin as approximately 0.5 to 1.0 µm. Insulating layer 130 is selectively etched to uncover a generally rectangular area 158 of contact layer 128 above each LED 14. A strip-like portion 159 of metallization layer 134 is removed along each side to provide electrical isolation between adjoining LEDs of the array. Metallization layer 134 covers the areas 158 of contact layer 128 to form contact pads 160 for the LEDs 14. Leads 137 are bonded to contact pads 160. Referring now to the embodiments shown in Figures 12 and 13, where like numbers refer to like parts, to avoid crosstalk between adjoining LEDs 14 of array 12 because of internal material transparency, which permits an "on" LED to cross-couple light into an adjacent "off" LED, a light barrier 170 is provided between adjoining LEDs 14. In the arrangment shown in Figure 12, barrier 170 is produced by etching, either chemically or through an ion etch, a channel 172 through metal contact layer 134, contact layer 128, Ga 1-y Al y As-p layer 124, GaAs-p layer 122 and either into or through the Ga 1-x As x As-n layer 120. The interior walls of channel 172 are coated with a suitable light reflective or absorbing layer 174. Where a reflective light barrier is desired, layer 174 may comprise any suitable light-reflecting material such as a reflective metal with a suitable insulator layer thereunder to prevent short-circuiting of the LED. Where a light absorbing layer is desired, layer 174 may comprise any suitable non-conducting light-absorbing material such as dyed polyimide or developed, dyed photoresist. In the embodiment shown in Figure 13, light barrier 170 is formed by controlled proton bombardment using a mask to expose the region between adjoining LEDs 14, the latter producing a barrier region 175 of high optical absorption and high electrical resistivity. Additionally, the embodiments shown in Figures 12 and 13 will reduce lateral current spreading under the electrical contact 128' and in layers 128, 124, and 122 and improve the efficiency of the LEDs. While light barrier 170 is illustrated as comprising a channel-like recess having a generally rectangular shape when viewed in the cross section, other configurations, such as a V-shape, may be used. Similiar heterostructure LED arrays may also be formed using indium gallium arsenide phosphide (InGaAsP) material. These LEDs also can operate with high efficiency and can be made for the wavelength range of approximately 1.1 to 1.7 µm. As has been described in US-A-4,424,524 LED arrays of the type described herein can also be used as photodiode arrays for image recording. Since GaAs/GaAlAs and InGaAsP are direct band gap materials, they should provide high optical absorption and efficient photodiode array systems. Approximate compositions and thicknesses of various layers shown in Figures 6 and 7: Layer Approx. Composition (atomic fraction) Approx. Thickness (µm) 20 x=0.2 to 0.5 2 to 10 22 z=0.0 (GaAs) 0.3 to 1.0 24 y=0.2 to 0.5 1 to 2 28 0.0 0.2 to 1.0 20 x=z+(0.2 to 0.5) 2 to 10 22 z=0.0 to 0.30 0.3 to 1.0 24 y=z+(0.2 to 0.5) 1 to 2 28 0.0 0.2 to 1.0 Approximate compositions and thicknesses of various layers shown in Figures 8 and 9: Layer Approx. Composition (atomic fraction) Approx. Thickness (µm) 20 x=0.3 to 0.6 2 to 10 22 z=0.0 (GaAs) 0.3 to 1.0 24 y=0.1 to 0.35 1 to 2 20 x=z+(0.3 to 0.6) 2 to 10 22 z=0.0 to 0.2 0.3 to 1.0 24 y=z+(0.1 to 0.15) 1 to 2 Approximate compositions and thicknesses of various layers shown in Figures 10 and 11: Layer Approx. Composition (atomic fraction) Approx. Thickness (µm) 50 x=z+(0.3 to 0.5) 2 to 10 52 z=0.0 to 0.30 0.3 to 1 56 y=z+(0.3 to 0.5) 0.5 to 1.0 28 0.0 0.2 to 0.5

Claims: A method of forming a light-emitting diode (LED) array for assembly with at least one other like LED array to form a solid-state full-width array (10) of LEDs, including the steps of: a) metallizing a first major surface of a GaAs-n substrate (112) to provide a common electrical contact (114) for the LEDs; b) growing a first layer (120), of GaAlAs-n, on the second major surface of the substrate; c) growing a second layer (122), of GaAs-p or GaAlAs-p on the first layer; d) growing a third layer (124), of GaAlAs-p, on the second layer to form a double hetero-structure together with the first and second layer e) depositing a layer (130) of insulation material on the third layer; f) etching away the insulation layer at selected areas to expose chosen areas of the third layer to form windows (135) defining each of the LEDs, and g) metallizing the areas of the third layer exposed by the windows to provide individual electrical contacts (134) for each of the LEDs. The method according to claim 1, including the steps of: a) growing an electrical contact layer (128) of GaAs-p⁺ on the third layer (124) before the insulation layer (130) is deposited on the electrical contact layer; b) etching away both the insulation and contact layers to expose the chosen areas of the third layer to form the windows (135); c) etching a portion of the insulation layer in the area bordering each of the windows to expose a portion (128') of the contact layer, and d) metallizing the exposed portions of the contact layer to provide individual electrical contacts (134) for each of the LEDs. The method according to claim 1, including the step of metallizing both the third layer areas comprising the windows, and the windows themselves, with a transparent electrically-conducting covering to provide electrical contacts for each of the LEDs. The method according to any preceding claim, including the step of forming a light barrier (172) between adjacent LEDs to prevent optical crosstalk therebetween, by etching a recess (172) through the insulation, contact, third, and second layers and into or through the first layer. An array of infra-red light-emitting diodes (LEDs) for assembly with a least one other like LED array to form a solid-state full-width array of LEDs for printing images, including: a) a GaAs-n substrate (112), the first major surface of the substrate being metallized to provide a common electrical contact (114) for the LEDs; b) a first layer (120), of GaAlAs-n, on the second major surface (115) of the substrate; c) a second layer (122), of GaAs-p or GaAlAs-p, on the first layer; d) a third layer (124), of GaAlAs-p, on the second layer forming a double hetero-structure together with the first and second layer; e) a layer (130) of insulation material on the third layer, the insulation layer being provided with windows (135) exposing chosen areas of the third layer defining each of the LEDs, and f) a metal contact layer on the surfaces of the third layer exposed by the windows, to provide individual electrical contacts for the LEDs. The array according to claim 5, including a) a fourth layer (128) of GaAs-p +, between the third layer and the insulation layer; b) the windows extending through both the insulation and the fourth layers; c) the insulation layer bordering each of the windows being absent to expose areas (128') of the fourth layer, and d) a metal contact layer (134) on the exposed areas of the fourth layer to provide individual electrical contacts for each of the LEDs. The array according to claim 8 or 9, including a recess (172) between adjoining LEDs forming a light barrier to prevent optical crosstalk between the adjoining LEDs.

Inventors: ARAGHI, MEHDI NAJM, DANIELE, JOSEPH JOHN
Applicants: XEROX CORPORATION
Application year: 1985
Main classification: H01L33
IPC codes: H01L27, H01L33