PROGRAMMABLE READ ONLY MEMORY DEVICE AND MEMORY SYSTEM EMPLOYING THE SAME

Abstract: A memory system having an erasable programmable read only memory (EPROM) (52) for storing principal data. A read only memory (ROM) (71) for storing key data, and a processing unit (2) for writing or reading the principal data into or from the EPROM (52) applying the key data. The EPROM (52) has an address converter (504) having a volatile memory (5042,5045) for storing tentatively the key data. External address data for writing the principal data into the EPROM (52) are converted to internal address data by the address converter (504) using the key data stored in the volatile memory (5042,5045), so that the principal data stored in the EPROM (52) are read out by converting the external address data into the internal address data using the key data stored in the volatile memory (5042,5045). The key data stored in the ROM (71) are read out and applied to the volatile memory (5042, 5045) during the power of the memory system is ON, the control of the key data ist processed by processing unit (2).

Description: BACKGROUND OF THE INVENTION The present invention relates to memory system having a semiconductor memory device, more particularly to a memory system which protects principal data stored in the semiconductor memory device from being copied. In a television game system for example, the system has usually a microcomputer having an erasable programmable read only memory device (EPROM) which is a kind of a programmable read only memory device (PROM) being electrically programmable. The game can be performed by the microcomputer controlled by the program data stored in the EPROM. Since the program involves the software of the television game, it is very important to protect the program data from being copied. Generally, creating a program is a hard task and requires a lot of man-hour, so the leakage of the program data causes a great economical damage to a system maker and a program owner. Not only in the television game system, but also in other systems, a program is so important that the system maker and program owner must take precautions against wicked persons who try to imitate a similar system and sell by copying the program data. Therefore, it has been required to realize a memory means from which the stored data cannot be copied. Trials for protecting the stored data from the memory device have been made, but only made on the simple substance of a memory device. For example, there is a semiconductor memory device improved so that the data stored in the memory device cannot be read from the simple substance of a memory device. However, since the measure is taken only in the memory device, it can be easyly presumed by the persons skilled in the art. Then, there are many illegal copies in the market. The guard of stored data from a memory device becomes a big problem in the field of the semiconductor memory device. A programmable read only memory device according to the precharacterising part of claim 1 is disclosed in EP-A-0 114 552. The contents of the latter document is considered, pursuant to Article 54 ( 3 ) and ( 4 ) EPC, as comprised in the state of the art. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory system having a semiconductor memory device so that the data stored in the memory device cannot be copied from the simple substance of the memory device. Further object of the present invention is to provide the memory system with additional power consumption being less than one percent of the power consumed in the prior art semiconductor memory device. More further object of the present invention is to provide the semiconductor memory device in the memory system, without enlarging its size from that of the prior art semiconductor memory device. Still further object of the present invention is to provide the memory system in low cost. The present invention can be performed by: improving not only the memory device but also the periphery of the memory device, extending to a memory system; and storing the key data at an optional place in the memory system, doing not in the memory device. The above improvement being applied, the key data cannot be found out from the memory device, and are also impossible to be found in the memory system because the memory system consists of many components; it will take a long time if they are possible. An EPROM can be applied as a semiconductor memory device and the EPROM is modified so as to have additionally an address converting means through which external address data are converted into internal address data; the external address data are what applied to the memory device from the exterior of it, and the internal address data are for accessing to a memory part of the EPROM being called memory cells. The address converter has a volatile memory in which key data provided in the memory system except the memory device are tentatively stored, and the stored key data are used for the convertion. Storing or erasing the key data into or from the volatile memory is made by turning the system power on or off respectively, so that the key data can be protected from being found out. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a computing system which applies the prior art EPROM; Fig. 2 is a block diagram of the prior art EPROM in the computing system of Fig. 1; Fig. 3 is a block diagram of a computing system which includes an invented memory system having a first embodiment of an invented EPROM; Fig. 4 is a block diagram of the first embodiment of the invented EPROM; Fig. 5 is a block diagram of an address converter in the first embodiment of the invented EPROM; Fig. 6 is a block diagram of a computing system which includes an invented memory system having a second embodiment of the invented EPROM; Fig. 7 is a block diagram of a second embodiment of the invented EPROM; Fig. 8 is a block diagram of an address converter in the second embodiment of the invented EPROM; Fig. 9 is a diagram illustrating the function of the second embodiment of the invented EPROM; and Fig. 10 is a diagram illustrating the relation among the writing, the stored, and the read principal data each having their own address data respectively. DETAILED DESCRIPTION OF THE INVENTION Before disclosing the present invention, the function of a prior art EPROM in a computing system will be discussed showing Figs. 1 and 2 for the sake of understanding the present invention. In Fig. 1, the power of the computing system is turned on by operating a control panel (CONT PANEL) 1. The power-on control signal is fed to a central processing unit (CPU) 2 and controls a power supply (POW SUP) 3. The POW SUP 3 supplies power to every unit of the system through LINEs 103 marked by asterisks *. The CPU 2 is a conventional type and is processed by the processing data stored in a read only memory (ROM) 41. The processing data are accessed from the CPU 2 through a LINE 104 and the data are fed to the CPU 2 through a LINE 105. An EPROM 51 is for storing constantly the data such as program data or operating system data, the data will be called the "principal data" hereinafter for distinguishing from other data such as key data and address data. The EPROM 51 has plurality of memory cells for storing the principal data, having individual address on each cell. The principal data are accessed by external address data fed from the CPU 2 through a LINE 107 for reading the principal data from the EPROM 51 through a LINE 108. The address data consists of a plurality of bit signals which are simultaneously fed to the EPROM, being called the "address signals" hereinafter. The principal data read from the EPROM 51 are processed in the CPU 2 and fed to respective units through an output terminal (OUT-TERM) 6. The access for reading the principal data from the EPROM 51 is made in the EPROM 51 by an access control signal fed from the CPU 2 through a LINE 106. In Fig. 2, the external LINEs having the same reference numerals to those in Fig. 1 designate the same parts, but the LINE 108 has only an arrow for reading the principal data because the figure shows only a case of reading the principal data; a symbol RD on the LINE 108 means the data read from the EPROM 51. A cell array (CELL ARRAY) 501 consists of plurality of memory cells arranged in a matrix. The matrix consists of rows and columns, so an address signal circuit 502 is provided for accessing the principal data stored in the CELL ARRAY 501. The address signal circuit 502 is a conventional type consisting of an address buffer (ADDRESS BUFF) 5021, a row decoder (ROW DEC) 5022, and a column decoder (COLUMN DEC) 5023. Reference numerals AD0, AD1, ---, and AD(n-1) show the external address signals. The external address signals are fed to the ADDRESS BUFF 5021 consisting of buffer devices such as inverters. The output of the ADDRESS BUFF 5021 is fed to the ROW DEC 5022 and the COLUMN DEC 5023 respectively, each decoder consists of decoding devices such as logical AND circuits and produces decoded address signals. The decoded address signals directly access to the CELL ARRAY 501, and the stored principal data are read out and fed to a sense amplifier (SENSE AMP) 503. A sense amplifier is a buffer amplifier for writing or reading the principal data into or from the memory cells, but the SENSE AMP 503 in Fig. 2 is for only reading the principal data. Detailed description of the present invention will be disclosed showing two embodiments with respect to two kinds of key data; the figures from 3 to 5 are for the first embodiment and the rest are for the second embodiment. Fig. 3 is a computing system which includes an invented memory system having an invented EPROM 52 using a first kind of key data. In the figure, the same reference numerals or symbols to those in Fig. 1 designate the same parts or units. The computing system is similar to that of Fig. 1 except the processing data being modified for processing the key data and a memory device being added for storing the key data. The ROM 71 is to store key data and is hidden in the computing system or the memory system except the EPROM 52 for protecting the key data from being found. The processing data for processing the key data are stored in the ROM 42. The key data in the ROM 71 are accessed from the CPU 2 through a LINE 110 and are fed to the CPU 2 through the LINE 111 and are further fed to the EPROM 52 through the LINE 107. So the LINE 107 is used for feeding the external address data and the key data to the EPROM 52. However, the key data are fed to the EPROM 52 in a short period of time when the power of the memory system is ON; the period and timing are given by changing the voltage level of a gate signal  in high or low, the gate signal is fed to the EPROM 52 from the CPU 2 through a LINE 112, and the sequence of applying the key data is advanced in the CPU 2 following the processing data stored in the ROM 42. The EPROM 52 is provided by adding an address converter 504 to the prior art EPROM 51 in Fig. 4. The address converter 504 consists of a group of transfer gates (TRANSFER GATE A) 5041, of flip flop circuits (FF) 5042, and of logical exclusive OR gates (EOR GATE) 5043. When the key signals or the external address signals are fed to address input terminals T0, T1, ---, and T(n-1), the signals are fed to the TRANSFER GATE A 5041 and the EOR GATE 5043. The gate signal  is fed to the TRANSFER GATE A 5041 through the LINE 112 (one line of the LINE 107 can be used instead of the LINE 112 for saving the number of the external connecting wires of the EPROM 52). In the prior art, the external address signals were directly fed to the address signal circuit 502 as shown in Fig. 2, however in the present invention, the external address signals are once converted into internal address signals by the address converter 504, and the internal address signals are fed to the address signal circuit 502; the order of the address signals is changed by the key data. The EPROM 52 has two functional modes; a reading mode and a writing mode. The principal data can be written into the EPROM 52 in the writing mode and read from the EPROM 52 in the reading mode. The writing mode is enforced at a factory side; the principal data can be written or revised at a factory side by using an exclusive equipment such as an EPROM writer. The reading mode is enforced at a user side. Fig. 4 shows the EPROM 52 being in the reading mode. The block diagram of the address converter 504 is shown in Fig. 5. In the figure, the same reference numerals or symbols to those in Fig. 4 designate the same parts or units. The address converter 504 has n external address input terminals T0, T1, ---, and T(n-1) and one gate signal terminal T01, and n outputs which go to internal address input terminals TT0, TT1, ---, and TT(n-1) of the ADDRESS BUFF 5021; that is, the external address signals consisting of bit signals AD0, AD1, ---, and AD(n-1) are converted into the internal address signals and fed to the internal address input terminals. The gate signal terminal T01 and the LINE 112 mentioned above are not always necessary, one terminal of the external address input terminals and one line of the LINE 107 can be used for them to save the connecting wires from the EPROM 52. The EOR GATE 5043 consists of n exclusive OR gates G0, G1, ---, and G(n-1) each having two input terminals and one output terminal. One input terminal of respective EOR gate is connected to respective external address input terminal, the other input terminal is connected to the output of respective FF circuit which will be stated later, and the output terminal of respective EOR gate is connected to respective internal address input terminal of ADDRESS BUFF 5021. Since each EOR gate is the exclusive OR gate, the relation between the input and the output of the EOR GATE becomes as follows: if one input is a bit signal 0, the output bit signal becomes equal to the other input bit signal; and if one input is a bit signal 1, the output becomes a reversed bit signal to the other input bit signal. The FF 5042 consists of n flip flop (FF) circuits FF0, FF1, ---, and FF(n-1). Respective FF circuit is a reset set flip flop circuit and functions as follows: when the power of the FF circuit is turned on and no input signal comes in, which is equal to that an input of a level 0 comes in, the input level of the FF circuit is in low (a level 0), so the FF circuit is in a "result" state, producing output of a level 0; when an input of a level 1 is fed to the FF circuit, the FF circuit becomes a "set" state, producing output of a level 1, and the "set" state is held on until the FF circuit receives the level 0 or the power of the FF circuit is turned off. The TRANSFER GATE A 5041 consists of n transfer gates S0, S1, ---, and S(n-1) each being a MOS transistor which functions as a switch. Each transfer gate is placed between respective external address input terminal T0, T1, ---, or T(n-1) and respective FF circuit and is controlled by the gate signal from the gate signal terminal T01. When the voltage level of the gate signal  becomes high (H), each transfer gate is ON so that respective external address input terminal is connected to respective FF circuit, and when the level is changed to low (L), the transfer gate is OFF so that the connection is disconnected. The gate signal is fed to every transfer gate, so all transfer gates S0, S1, ---, and S(n-1) are simultaneously operated by the gate signal. In Fig. 5, the number of the devices in each group is equal to the number (n in the figure) of the external address signals. The number of the devices is not always necessary to be equal to the number of the address signals, however greater the number of the devices is better to protect the stored principal data from being copied. In the writing or reading mode, the function of the EPROM 52 is advanced in following three steps: first, the key data are fed to the EPROM 52 and stored in the FF 5042 when the power of the EPROM 52 is turned on to prepare for receiving the external address signals; second, the external address signals are fed to the EPROM 52 so that the principal data are written into or read from the EPROM 52; and third, the key data stored in the FF 5042 are disappeared when the power of the EPROM 52 is turned off. When the EPROM 52 is in the memory system, the three steps are performed in the reading mode, and the first and second steps are automatically performed by CPU 2 following the processing data stored in the ROM 42 when the power of the memory system is turned on, the third step is performed by only turning the power of the memory system is turned off. In the memory system, in the first step, the key data are fed to the external address input terminals and at the same time the gate signal  becomes H by turning the system power on. So, respective transfer gate is ON and respective key datum of a level 1 or 0 is fed to respective FF circuit, so that respective FF circuit is set so as to produce the output of a level 1 or 0 corresponding to respective input key datum. Then the gate signal  is returned to L. However, the state of respective FF circuit is held on until the power is turned off. Meanwhile, respective EOR gate also receives the key datum and the output of respective FF circuit, which causes the EOR gate to produce some output. However, in the first step, the CPU 2 processes so that the data come from the EPROM 52 are not treated as the principal data, so there is no necessary to consider the key data signals fed into the EOR gate in the first step. In the second step, the external address signals are fed into the external address input terminals after the gate signal  is returned to L. So all transfer gates are OFF, so that respective EOR gate receives respective external address signal at the one input terminal and the output of respective FF circuit, which has been kept in a level of 0 or 1, at the other input terminal, producing the output of the internal address signal. Table 1 shows an example for this. Address Symbol External Address Signals Key Data Internal Address Signals AD0 - 1 0 1 - 0 - 1 0 1 - AD1 - 1 0 0 - 1 - 0 1 1 - AD2 - 0 1 1 - 1 - 1 0 0 - AD3 - 0 1 1 - 0 - 0 1 1 - AD4 - 1 1 1 - 1 - 0 0 0 - AD5 - 0 0 1 - 0 - 0 0 1 - AD6 - 1 0 1 - 0 - 1 0 1 - AD7 - 0 0 0 - 1 - 1 1 1 - In TABLE 1, assume that the matrix of the CELL ARRAY 501 consists of 16 rows and 16 columns and the address symbols AD0, 1, 2, and 3 are for the rows, and AD4, 5, 6, and 7 are for the columns. Three groups of the external address signals are shown as an example in the table, obtaining three group of the internal address signals. Comparing between respective groups of the external and internal address signals, it will be clear that the internal address signals are converted so as to be completely different from the external address signals. The key data can be taken as much as 8th power of 2 varieties; 256 varieties. Fig. 10 shows the relation among writing, stored, and read principal data. The writing principal data are what intended to be written into the EPROM 52 with the external address data, the stored principal data are what stored in the EPROM 52 by the internal address data, and the read principal data are what read from the EPROM 52 using the same address data to that for the writing principal data. Figs. 10(1), (21)-(22), and (31)-(32) show the writing, the stored, and the read principal data respectively. Figs. 10 (21) and (23) are both stored principal data, and Figs. 10(31) and (32) are both read principal data but different kinds. In the figures, reference symbols A1, A2, A3, ---mean the address data, D1, D2, D3, --- mean the principal data, and respective A and D which are arranged each other in a lateral direction indicate the principal data D and its address data A. There are two bunches of solid arrows between Figs. 10(1) and (21) and between (21) and (3), the former means that the external address data are converted into the internal address data by the key data when the principal data are written into the CELL ARRAY 501, and the latter means that the principal data stored in the CELL ARRAY 501 are read out using the same key data. The former is performed at the factory side, and the latter is made at the user side. Therefore, if the CELL ARRAY 501 is taken out from the memory system and the stored data is tried to be read out, the data are read out with the address data being equal to the internal address data. The same result occurs when the stored principal data are read out in the memory system without using the key data. These are shown in Figs. 10(22) and (23), and a bunch of the dotted arrows which run in parallel means that the stored principal data are read out without the key data. In the third step, the system power is turned off, then the key data stored in the FF circuit 5042 are disappeared because of the character of the volatile memories. The three steps also can be applied in the writing mode when the the principal data is written into the EPROM 52 by using the EPROM writer at the factory side. In the above description, respective key signal is fed to the EPROM 52 in parallel each other. However, the key data can be fed to the EPROM 52 in a series of key signals. The second embodiment shown in the figures from 6 to 9 is for this. This key data will be called "series key data". In the figures, the same reference numerals or symbols to those in the figures from 1 to 5 designate the same parts or units. Fig. 6 shows a block diagram of the computing system having an invented memory device which uses the series key data. In the figure, a ROM 72 stores the series key data, a LINE 113 is for feeding the series key data, a LINE 114 is for feeding a clock signal which is needed to process the series key data. Fig. 7 shows a block diagram of an invented EPROM which uses the series key data. As shown in the figure, the EPROM has the same construction to the EPROM of the first embodiment except a means of converting the key data from series to parallel. The convertion is performed by a shift register (SHIFT REG) 5045 and a transfer gate B (TRANSFER GATE B) 5044 in the address converter 504. The SHIFT REG 5045 consists of plurality of shift register elements whose number is less than the number of the external address signals fed to the EPROM simultaneously; this number also can be said that greater the number is better to protect the EPROM from being copied. The EOR GATE 5043 is equal to that of the first embodiment; one input terminal receives respective external address signal and the other input terminal receives respective output from the SHIFT REG 5045. The series key signal and the clock signal are fed to the TRANSFER GATE B 5044 in which they are gated by the gate signal  so that they are fed to the SHIFT REG 5045 respectively passing through the TRANSFER GATE B 5044 when the gate signal  is H. Fig. 8 shows a block diagram of an address converter 504 of the second embodiment. The function of the address converter is explained with Fig. 9 which illustrates the relation among the gate signal, the series address signals, the clock signals, and the output of the SHIFT REG 5045 being shown by bit signals. The block diagram of the SHIFT REG 5045 is also shown in Fig. 9. TRANSFER GATE B 5044 consists of two transfer gates G01 and G02, the series key signals are fed to G01 and the clock signals are fed to G02 and both signals are gated by the gate signal  as shown in Fig. 9(a), (b), and (c). The gate signal , the key signals, and the clock signals are provided in CPU 2, and the width, number, and timing of each pulse of respective signal depend on the characters of the external address data and the key data. Fig. 9 shows an example when the number of the external address signals is eight and the SHIFT REG 5045 consists of eight elements M0, M1, ---, and M7 as shown in Fig. 9(c). The clock signals are fed to each element of the SHIFT REG 5045, the key signals are fed to the SHIFT REG 5045 from M0 to M7, and the both signals have the relation as shown in Fig. 9(b) and (c) (the abscissa in Fig. 9(a), (b), or (c) is expressed in time "t"). In Fig. 9(a) and (b), each element of the shift resister produces the output of a level 1 when the leading edge of the clock pulse coincides with the high level of the key signal, and the element produces the output of a level 0 when the leading edge coincides with the low level of the key signal. The output level produced from each element is shifted to next element at the trailing edge of each clock pulse. So, the element M0 produces a level 1 at time t₁ and the level 1 is shifted to next element M1 at time T₂ and so on. As a result, when all pulses have been fed to the shift register (at time t₁₆ in the figure), respective element produces the output level as shown in Fig. 9(d), and this state is held on until the power of the shift register is turned off. Thus, the series key data as shown in Fig. 9(b) are converted to the parallel key data as shown in Fig. 9(d), the converted parallel key signals are fed to the EOR GATE 5043 respectively. The sequence of feeding the gate signal, the key data, and the clock signal to the EPROM, and the three steps for writing or reading the principal data into or from the EPROM are equal to those in the first embodiment. In the first and second embodiments, the address converter 504 is located between the input terminals for the external address signals and the ADDRESS BUFF 5021 in the address signal circuit 502 as shown in Fig. 4, 5, 7, or 8. However the address converter 504 can be placed between the ADDRESS BUFF 5021 and the decoders (ROW DEC 5022 and COLUMN DEC 5023) in the address signal circuit 502. Applying the memory system having the EPROM to a system like a computing system as mentioned in the first and second embodiments, the principal data cannot be copied from the EPROM itself because the key data are not stored in the EPROM, and the key data cannot be found because they are stored at the periphery of the EPROM (there are many electrical components), and the key data are used only in the closed memory system; nobody knows what is and where is the key data except the system maker. The components used in the address converter 504 are made of the metal oxide semiconductor (MOS), so additional power consumption is as little as less than one percent of the power consumption of the usual EPROM. The die size of the EPROM is the same to that of the usual EPROM because additional components are few and additional connecting wires are also few. Therefore, the cost increase according to the present invention is negligible. The EPROM can be used conventionally without the key data, because every FF circuit or element of the shift resister produces the output of a level 0 if the gate signal  is not supplied, so the principal data can be accessed by only the external address data without the key data. In the embodiments mentioned above, the EPROM is used for the semiconductor memory device, however, a programmable read only memory device (PROM), whose stored data cannot be erased when the data has been written in it, can be also applied as the semiconductor memory device in the memory system.

Claims: A programmable read only memory device for storing principle data, receiving external address data and key data, comprising a plurality of address input terminals (T0, T1...T(n-1)) for receiving said external address data; a plurality of non-volatile memory cells (501) for storing said principal data; volatile memory means (5042,5045) for storing key data; address converting means (504) for converting said external address data into internal address data according to said key data stored in said volatile memory means (5042, 5045); and means (502) for accessing said non-volatile memory cells designated by said internal address data, characterized in that said key data is directly transmitted from said address input terminals to said volatile memory means (5042, 5045) in response to a control signal (). A programmable read only memory device according to claim 1 characterized in transfer gate means (5041, 5043) controlled by said control signal (), said transfer gate means (5041,5044) transferring said key data applied to said address input terminals to said volatile memory means. A programmable read only memory device according to claim 1 or 2, characterized in that said address converting means (1504) comprises a plurality of logical gate circuits (5043). A programmable read only memory device according to claim 3 characterized in that said logical gate circuits (5043) comprises a plurality of exclusive OR gates (G0,G1 ....G(n-1). A programmable read only memory device according to anyone of claims 1 - 4 characterized in that said volatile memory means (5042) comprises a plurality of flip flop circuits (FFO, FF1....FF(n-1). A programmable read only memory device according to anyone of claims 1 to 4 characterized in that said volatile memory means (5045) comprises a shift register. (MO,M1...M(n-1). Use of a programmable read only memory device according to anyone of claims 1 to 4 characterized in non-volatile memory means (71)for storing said key data; means (2) for processing the sequence of writing said principal data in said memory system using said key data and reading said stored principal data from said memory system using said key data.

Inventors: YOSHIDA, MASANOBU
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F12
IPC codes: G06F1, G11C17, G06F12, G09C1, G06F21, G06F13