METHOD AND APPARATUS FOR DATA MERGING/SORTING

Abstract: In order to perform merging/sorting which can flexibly cope with the variation of a data length, data is divided every predetermined number of bits (m bits), a plurality of proces­ sors each of which process the m-bit data are connected, and the alteration of the data length can be coped with by chang­ ing the number of the connected processors. On this occa­ sion, in order to permit reduction in the quantity of informa­ tion items which are exchanged among the respective proces­ sors, the merging/sorting is so carried out that the processor processing certain m bits receives input information from only the processor processing immediately upper m bits and delivers output information to only the processor processing immediately lower m bits. Besides, in order to perform searching, each of key words to be searched is subjected to m-bit slicing and a search key and data in areas storing the m-bit sliced key words are com­ pared so as to find areas storing key words which agree with the search key.

Description: Field of the Invention: The present invention relates to special-purpose hardware and a method which execute data merging/sorting in a database or in file processing, and more particularly to a method and an apparatus for merging/sorting data which is flexible with regard to a change in data length. Description of the Prior Art: As database-oriented hardware for merging/sorting data, there is known a heap sort type engine proposed by the inventors (Tanaka, Y. et al: Pipeline Searching and Sorting Modules as Components of a Data Flow Database Computer, IFIP Congress '80, pp. 427-432, Oct. 1980). This engine can completely overlap the transmission and sorting calculation of data, and can therefore perform a very efficient computation. This engine, however, has been problematic in the following points: (1) Due to complicated circuitry, the number of elements is too large and poses a problem in LSI implementations. (2) There is no expansibility for an alteration in the data length. Another sorting engine is known which is a merge sort type engine (Todd, S.: Algorithm and Hardware for a Merge Sort Using Multiple Processors, IBM J.Res.Develop., Vol. 22, No. 5, May 1978). Since the merge sort is simpler in the calculative system than the heap sort, it can simplify hardware, but it has not solved the above problem (2). Summary of the Invention: In view of the above circumstances, the present invention consists in building an engine for sorting which is flexible to a change in the data length, and it has for its object to provide a method and an apparatus for merging and sorting which meet the requirement of simplifying circuitry to the utmost in order to permit LSI implementation. In accordance with the present invention, this object is solved, with regard to the method, by the features described in claim 1; and with regard to the apparatus, by the features described in claim 8. Preferred embodiments of the method given in claim 1 are included in subclaims 2 to 7, and a preferred embodiment of the apparatus given in claim 8 is included in claim 9. Therefore, as a means for realizing expansibility for a change in data length, it is considered to divide the data every certain fixed number of bits (every m-th bit) and then to process the divided data. Concretely, this becomes an arrangement in which a plurality of processors each processing the m-bit data are connected. A change in the data length can be coped with by altering the connected number of processors. In this case, it is required to exchange information among the processors, and the quantity of the exchange information needs to be rendered small. The present invention is so constructed that the processor processing certain m bits receives input information from only the processor processing immediately upper m bits and delivers output information to only the processor processing immediately lower m bits. According to the present invention, a merging sorter can be built, in general, by serially connecting mergers. Brief Description of the Drawings: Fig. 1 is a general arrangement diagram of a merging/sorting apparatus according to the present invention; Fig. 2 is a diagram showing the stored form and output form of input data in the present invention; Fig. 3 is an explanatory diagram showing the input timings of data in the present invention; Fig. 4 is a block diagram showing the arrangement of a modified bit sliced engine in the present invention; Fig. 5 is a block diagram showing the arrangement of a bit sliced merger; and Fig. 6 is a diagram showing a method of building one device for merging long data or a plurality of devices for merging short data. Detailed Description of the Preferred Embodiment: Now, the present invention will be described in conjunction with one embodiment. In general, the merging/sorting is to obtain (N + M) sorted data from N data and M data already sorted respectively. Concretely, first of all, the two head data of the respective sets are compared to preferably output the smaller data in case of sorting the data in the ascending order or the larger data in case of sorting the data in the descending order. Subsequently, the compared data in the unselected set and the next data in the selected set are subjected to a similar calculation. In this way, the sorting of the (M + N) data ends. Fig. 1 is a block arrangement diagram of a merging/sorting apparatus according to the present invention. The merging sorter is constructed of bit sliced mergers each of which calculates and compares m bits, and input buffers. Here, the bit sliced merger which calculates the m bits of the uppermost digit (= O) is assumed to be a modified bit sliced merger 10 (hereinbelow, abbreviated to 'MBSM 10'), and the bit sliced mergers which calculate the ensuing m bits respectively are assumed to be bit sliced mergers 11 (hereinbelow, abbreviated to 'BSMs 11'). In addition, the k-th BSM 11 as reckoned from the uppermost digit is called BSM 11-k (the MBSM 10 shall correspond to k = 0). Here, it is assumed that the numbers of data in the respective sets be equal and be N. It is also assumed that the sorting in the ascending order be performed here. R n is to denote the n-th data of one set (n: L → N), and L n the n-th data of the other set. R n,k and L n,k are respectively to denote the data of the k-th m bits as reckoned from the upper digits of the data R n and L n (k = 0 shall indicate the data of the m bits of the uppermost digit). Accordingly, R n,0 and L n,0 indicate data to be input to the MBSM 10, and R n,k and L n,k data to be input to the BSM 11-k. The input buffers 12 are buffers which store these input data. In this regard, the input buffer 12-0 is the buffer for storing the data L n,0 and R n,0 (n: 0 → N), and the input buffer 12-k is the buffer for storing the data R n,k and L n,k . Practicable storage charts are shown in Fig. 1. The MBSM 10 delivers two control information to the BSM 11-1, and the BSM 11-k obtains two input information from the BSM 11-k - 1 and delivers two output information to the BSM 11-k + 1. The MBSM 10 and the BSM 11 differ as to the presence and absence of input information. Fig. 2 illustrates in detail a method of inputing data to-be-sorted to the BSM 11-k. A method of inputing data to-be-sorted to the MBSM 10 and a method of outputing a calculated result therefrom are similar to the illustrated method. The BSM 11-k has two pointers rp20 and ℓp21. The pointer rp20 is an input pointer for the data R n,k , while the pointer ℓp²¹ is an input pointer for the data L n,k . Accordingly, the BSM 11-k receives as its input data the data in the input buffer 12-k pointed by the pointers rp20 and ℓp21, that is, the rp-th data of the data R n,k and the ℓp-th data of the data L n,k respectively. Concretely, the data R rp,k and L ℓp,k become the input data. On this occasion, as illustrated in Fig. 3, it is assumed that data a 1,0 and b 1,0 be input from the buffer 12-0 to the MBSM 10 at a time 0. Then, it is at a time k that data a l,k and b l,k are input from the buffer 12-k to the BSM 11-k. That is, the calculation of the BSM 11-k proceeds with a delay of one time with respect to that of the BSM 11-k - 1. Likewise, the output of data delays by one time in succession. The reason is that, when data a n,k and b n,k are to be calculated in the BSM 11-k, the calculated result of data a n,k-1 and b n,k-1 needs to be known. The BSM 11-k obtains information concerning this, from the BSM 11-k - 1. Next, Fig. 4 shows the detailed arrangement of the MBSM 10, and Fig. 5 the detailed arrangement of the BSM 11-k. Since the MBSM 10 processes the m bits of the uppermost digit, it may merely deliver the smaller one of data b ℓp,0 and a rp,0 to a data output line OUTPUT 44. On the other hand, in the case of the BSM 11-k, a number to be selected changes depending upon the calculated result of the upper digit. For example, in a case where data b ℓp,1 and a rp,1 are compared by the BSM 11-1, the data a rp,1 must be output irrespective of the magnitudes of the data b ℓp,1 and a rp,1 if b ℓp,0 > a rp,0 holds. The reason is that, when the data b ℓp,1 is output in this case, it is delivered in spite of the data b ℓp,0 not having been output at the upper digit yet. Since the data b ℓp,0 and b ℓp,1 are obtained by slicing a number b ℓp , outputing them separately makes it impossible to obtain a correct result. In this case, a value to be output can be determined according to the magnitudes of the data b ℓp,1 and a rp,1 for the first time when b ℓp,0 = a rp,0 has held. In the present invention, these judgements are made on the basis of the difference of the pointer from that of the calculator of the upper digit. That is, when the difference of the pointer from that of the upper digit has become null, it is found that the particular pointer must not be advanced. (The fact that the pointer of the lower digit goes ahead of the pointer of the upper digit, signifies that a number not delivered at the upper digit has been output at the lower digit.) In a case where the calculator of the upper digit has advanced the pointers rp20 and ℓp²¹ as the result of the calculation of data b ℓp,k and a rp,k , it brings corresponding control information output lines CTLR 42 and CTLL 43 to "1", and in any other case, it brings them to "0", so as to inform the lower-digit calculator of the situation. (This is common to all of the MBSM 10 and the BSHs 11.) The lower-digit calculator receives the "1" or "0" at blocks RI 50 and LI 51. (The MBSM 10 need not be provided with these portions because it has no upper-digit calculator.) Regarding the difference of the pointer from that of the upper-digit calculator, when the pointer of the particular calculator itself is advanced by adding the content of the block RI 50 and LI 50, this value may be subtracted. Blocks DR 52 and DL 53 denote the differences of the pointers with respect to the upper-digit calculator (DR 52 concerns the pointer rp20, and DL 53 the pointer ℓp²¹). However, in executing the calculations with the data a rp,k and b ℓp,k , the control information items from the upper digit have already entered the blocks RI 50 and LI 51. Therefore, the calculations need to be carried out according to the values obtained by adding the contents of the blocks RI 50 and LI 50 to the differences DR 52 and DL 53 respectively. Block D'R 54 and D'L 55 denote the results of the additions, and a counter I 56 and a counter II 57 are provided in order to execute the additions. When the contents of the blocks RI 50 and LI 51 are "1", the respective counters increase the contents of the blocks DR 52 and DL 53 by one and deliver the results to the blocks D'R 54 and D'L 55, whereas when the contents of the blocks RI 50 and LI 51 are "0", the respective counters supply the blocks D'R 54 and D'L 55 with the contents of the blocks DR 52 and DL 53 as they are. The blocks DR 52, DL 53, D'R 54 and D'L 55 and the adders I 56 and II 57 do not exist in the MBSM 10 because they are portions required for grasping the differences of the pointers with respect to the upper digit. Meanwhile, with this idea, when a rp,k = b ℓp,k holds in case of intending to select and output the smaller one of the data a rp,k and b ℓp,k , both the pointers rp20 and ℓp21 need to be put forward. By way of example, it is assumed that a 1,0 = b 1,0 have held. On this occasion, since the BSM 11-1 needs must select the smaller one of data a 1,1 and b 1,1 , it must get the MBSM 10 to advance both the pointers so that the values of the blocks D'R 54 and D'L 55 of the BSM 11-1 may be "1" when this BSM 11-1 executes the calculation of the data a 1,1 and b 1,1 . (When the MBSM 10 advances only one of the pointers rp and ℓp, either of the differences (D'R 54, D'L 55) of the pointers thereof relative to those of the BSM 11-1 becomes null, and hence, a hindrance will arise if the smaller one of the data a 1,1 and b 1,1 is the data as to which the difference of the pointers is null.) Even when both the pointers rp20 and ℓp21 are moved, one data is output. It is therefore necessary to store that one pointer has been excessively advanced. A block C 40 stores the number of times by which the pointers have been moved in excess. Besides, in order to store what value has been accumulated, the output result is stored in a block V 41. The accumulated result is discharged in the following three cases: (1) The case where neither of the pointers can be advanced any longer. (2) The case where only either of the pointers can be advanced and where a value indicated by the pointer to be advanced differs from the content of the block V 41. (3) The case where both the pointers can be advanced and where the smaller one of values indicated by the respective pointers differs from the content of the block V 41. Thus far, the portions other than the processor I 45 of the MBSN 10 and the processor II 58 of the BSM 11-k have been described. Now, the functions of the two processors will be stated. As already stated, the difference between the MBSM 10 and the BSM 11-k is whether or not the limitation of the calculated result of the upper-digit calculator is imposed. In a case where neither of the contents of the blocks D'R 54 and D'L 55 is zero, the BSM 11-k has the differences of the pointers of its own from the pointers of the upper-digit calculator, and hence, it may advance both the pointers rp20 and ℓp21, so that it is not subject to the limitation of the result of the upper-digit calculator. Accordingly, the processed content of the processor I 45 becomes equal to that of the processor II 58 for D'R 54 0 and D'L 55 0. Therefore, the functions of the processor II 58 in respective cases will be explained here. Case 1: D'R 54 = D'L 55 = C 40 = 0. Case 1 is not existent. This signifies that neither of the pointers ℓp20 and rp21 can be advanced and that there is no data accumulated up to now. In this situation, there is quite no data to be output. Since, however, the BSM 11-k delays by one time interval as compared with the BSM 11-k - 1, at least one data to be output exists actually. Case 2: D'R 54 = D'L 55 = 0 and C 40 > 0. Since, in this case, the pointers rp20 and ℓp21 cannot be advanced, data accumulated up to now is output. Accordingly, the following operations are executed: CTLR 42 ← 0, CTLL 43 ← 0, OUTPUT 44 ← V 41, C 40 ← C 40 - 1, DL 53 ← D'L 55, DR 52 ← D'R 54 Case 3: D'L 55 = 0 and D'R 54 > 0 In this case, the pointer ℓp21 cannot be moved. This case is further divided into two cases: Case 3. 1: C 40 = 0 or a rp,k = V 41 In this case, the data a rp,k may be output, and the pointer rp20 may be advanced. The content of the block c 40 need not be altered. Accordingly, operations indicated below are executed: CTLR 42 ← 1, CTLL 43 ← 0, OUTPUT 44 ← a rp,k , V 41 ← a rp,k , rp20 = rp20 + 1, DL 53 = D'L 55, DR 52 = D'R 54 - 1 Case 3. 2: C 40 0 and a rp,k V 41 In this case, there is data accumulated in the past, and moreover, the data a rp,k differs from the content of the block V 41, so that the accumulated data needs to be first output. CTLR 42 ← 0, CTLL 43 ← 0, OUTPUT 44 ← V 41, C 40 ← C 40 - 1, DR 52 ← D'R 54, DL 53 ← D'L 55 Case 4: D'L 55 > 0 and D'R 54 = 0 This case is reverse to Case 3 in the relationship of D'L 55 and D'R 54, and becomes a form symmetric to that of Case 3. Case 4. 1: C 40 = 0 or b ℓp,k - V 41. Operated results are as follows: CTLR 42 ← 0, CTLL 43 ← 1, OUTPUT 44 ← b ℓp,k , V 41 ← b ℓp,k , ℓp21 ← ℓp21 + 1, DL 53 ← D'L 55 - 1, DR 52 ← D'R 54 Case 4. 2: C 40 0 and b ℓp,k V 41. Operated results are indicated below. CTLR 42 ← 0, CTLL 43 ← 0, OUTPUT 44 ← V 41, C 40 ← C 40 - 1, DL 53 ← D'L 55, DR 52 ← D'R 53 Case 5: D'L 55 > 0 and D'R 54 > 0 Since, in this case, there is room for advancing both the pointers ℓp21 and rp20, the data a rp,k and b ℓp,k can be compared. In this regard, MiN (a rp,k , b ℓp,k ) shall indicate the smaller one of the values of the data a rp,k and b ℓp,k . Case 5. 1: MiN (a rp,k , b ℓp,k ) V 41 and C 40 0 In this case, there is data accumulated, and the value of the block V 41 is smaller than both the data a rp,k and b ℓp,k , so that the accumulated data needs to be first output. The following operated results are obtained: CTLR 42 ← 0, CTLL 43 ← 0, OUTPUT 44 ← V 41, C 40 ← C 40 - 1, DL 53 ← D'L 55, DR 52 ← D'R 54 Case 5. 2: C 40 = 0 or MiN (a rp,k , b p,k ) = V 41 In this case, operated results are determined by the values of the data a rp,k and b ℓp,k . Case 5. 2. 1: a rp,k > b ℓp,k In this case, the data b ℓp,k is output. Operated results become as follows: CTLR 42 ← 0, CTLL 43 ← 1, OUTPUT 44 ← b ℓp,k , V 41 ← b ℓp,k , ℓp21 ← ℓp21 + 1, DL 53 ← D'L 55 - 1, DR 52 ← D'R 54 Case 5. 2. 2: a rp,k < b ℓp,k In this case, the data a rp,k is output. Operated results become as follows: CTLR 42 ← 1, CTLL 43 ← 0, OUTPUT 44 ← a rp,k , V 41 ← a rp,k , rp20 ← rp20 + 1, DL 53 ← D'L 55, DR 52 ← D'R 54 - 1 Case 5. 2. 3: a rp,k = b ℓp,k In this case, either value may be output. Both the pointers ℓp21 and rp20 are put forward, and the content of the block C 40 is increased by one: CTLR 42 ← 1, CTLL 43 ← 1, OUTPUT 44 ← a rp,k , V 41 ← a rp,k , C 40 ← C 40 + 1, ℓp21 ← ℓp21 + 1, rp20 ← rp20 + 1, DL 53 ← D'L 55 - 1, D'R 52 ← D'R 54 - 1 The functions of the processor I of the MBSM 10 become equal to those in Case 5. Therefore, when the blocks RI 50 and LI 51 of the BSM 11 are normally set at "1", the BSM 11 performs functions equivalent to those of the MSBM 10. Accordingly, by furnishing each BSM 11 with a control circuit 61 and turning a control signal 62 ON and OFF as illustrated in Fig. 6, the blocks RI 50 and LI 51 can be respectively supplied with outputs RO 42 and LO 43 from the upper digit as they are (in the case of the control signal 62 = OFF) or can be always supplied with "1" (in the case of the control signal 62 = ON). The BSM 11-k whose control signal 62-k has been turned ON functions equivalently to the MBSM 10 which processes the m bits of the uppermost digit. Accordingly, a processor for sorting one long data can be built by turning OFF all the control signals 62-k, and a plurality of processors for sorting short data respectively can be built by turning ON the control signals 62-k in proper places. According to the present invention, a sorter conforming to the variation of a data length can be flexibly built. Here, the sorter signifies an apparatus in which devices as shown in Fig. 1 are serially connected in a plurality of stages. Information which is output from each bit sliced merger is composed of 2 bits, and the number of stages of the mergers which are required for sorting N data is log₂ N. Therefore, the number of pins, which are required in a case where a circuit with the bit sliced mergers connected in N stages is put into the form of a chip, becomes 4 log₂ N with input/output control information taken into account. This value is 48 when N = 4096 is assumed. In case of slicing in single bit unit, one pin for each of input data and output data and further pins for V cc (power source), ground (earth), etc. are required, and the total number of the required pins suffices with 50 odd. Besides, the number of required transistors is predicted to be on the order of 100 thousands in a static RAM and on the order of 50 thousands in a dynamic RAM, and the LSI implementation thereof will be satisfactorily possible with the present-day LSI technology.

Claims: A method of merging/sorting data to obtain a set of (N+M) sorted data from a first set of N data and a second set of M data already sorted, characterized by: each data being divided in digits of m bits and using a system having bit sliced mergers, each of which calculates and compares m bits, and each having two input buffers, each buffer being adapted to store the corresponding digits of the data in a set, each buffer having an input pointer to point to the digit in calculation, said mergers starting from the one dealing with the most significant digit carrying forward control information to the merger dealing with the next lower digit, said control information determining whether or not the two pointers have to be advanced, said two pointers being provided in correspondence with the respective sets and indicating those addresses of said buffer which store data to be applied in said respective sets at present among the two sets of bit sliced data, whereby the timing of the data to be applied to a merger is delayed by one unit with respect to the timing of the data to be applied to the merger for an immediate upper merger, said method comprising the following steps: (a) comparing during a first time period (TIME 0) in the first merger (10) dealing with the most significant digit first data (b1,0; a1,0) and outputting the relevant data (either b1,0 or a1,0) depending on the sorting order, and outputting control information to the second merger indicative whether the pointers have been advanced as a result of the calculation on the data; (b) comparing during a second time period (TIME 1) in the first merger (10) the data in the unselected set and the next data in the selected set, and comparing the digits (b1,1; a1,1) in the second merger (11-1), and outputting in the second merger irrespective of the result of this comparison the data belonging to the same set as the data being output in the first merger if it is not true that the comparison in the first merger during the first time period indicated equal digits, and if there are equal digits the relevant data in the second merger must be selected (either b1,1 or a1,1), and both pointers in the second merger (11-1) must be advanced, control information indicative of the advancing being outputted to the third merger; (c) before performing calculations in the second merger, the control information of the first merger is added to the difference information of the second merger, whereby the particular pointer cannot be moved if the result of the addition is null; (d) repeating steps (b) and (c) in following time periods for the following mergers. A method of merging/sorting as defined in claim 1, wherein among said bit sliced mergers any merger (11) other than the merger (10) dealing with the most significant digit controls its operation on the basis of differences between said two pointers amd the pointers corresponding to the merger dealing with the next upper digit. A method of merging/sorting as defined in claim 2, wherein said merger (11) other than said merger (10) for dealing with the most significant digit is subjected to an operation control quite equal to that of said merger (10) for dealing with the most significant digit when neither of the differences of said two pointers is zero. A method of merging/sorting as defined in claim 2, wherein the operation control of said merger (11) other than said merger (10) dealing with the most significant digit is so performed that, when either or both of the differences of said two pointers is/are zero, the pointer affording the zero difference is not advanced. A method of merging/sorting as defined in claim 1, wherein, when either of said two pointers and two data stored in the addresses of said buffer is to be selected, both said pointers are advanced subject to said two data being equal; and when the pointer has been advanced excessively, a counter indicative of the number of times of such excessive advances is incremented by one, and a content of the corresponding data is stored as stored data in said merger. A method of merging/sorting as defined in claim 5, wherein the stored data items in a number accumulated in said counter are outputted without advancing either of said two pointers, when any one of the following three conditions has held: Condition 1: Both the differences of the two sets of pointers become zero. Condition 2: Either of the differences of the two sets of pointers is zero, and the data stored in the address of said buffer indicated by the pointer not affording the zero difference is different from said stored data. Condition 3: Neither of the differences of said two sets of pointers is zero, and a smaller one of the two data stored in the addresses of said buffer indicated by the respective pointers is different from said stored data. A method of merging/sorting as defined in claim 1, wherein control circuitry is connected to the bit sliced mergers (10, 11) for flexibly coupling said mergers, so that one processor for merging/sorting long data or a plurality of processors for merging/sorting short data can be built respectively. An apparatus for merging/sorting data to obtain a set of (N+M) sorted data from a first set of N data and a second set of M data already sorted, characterized by: means for dividing each data in digits of m bits, a plurality of bit sliced mergers (10, 11), each of which calculates and compares m bits, wherein each of said mergers has two input buffers (12), each buffer being adapted to store the corresponding digits of the data in a set, and each buffer having an input pointer to point to the digit in calculation, said mergers start operation from the one (10) dealing with the most significant digit and carrying forward control information to the merger (11-1) dealing with the next lower digit, said control information determines whether or not the two pointers have to be advanced, said two pointers being provided in correspondence with the respective sets and indicating those addresses of said buffer which store data to be applied in said respective sets at present among the two sets of bit sliced data, and whereby the timing of the data to be applied to a merger is delayed by one unit with respect to the timing of the data to be applied to the merger for an immediate upper merger, said apparatus comprising further: (a) means for comparing during a first time period (TIME 0) in the first merger (10) dealing with the most significant digit first data (b1,0; a1,0) and for outputting the relevant data (either b1,0 or a1,0) depending on the sorting order, and for outputting control information to the second merger indicative whether the pointers have been advanced as a result of the calculation on the data; (b) means for comparing during a second time period (TIME 1) in the first merger (10) the data in the unselected set and the next data in the selected set, for comparing the digits (b1,1; a1,1) in the second merger (11-1), and for outputting in the second merger irrespective of the result of this comparison the data belonging to the same set as the data being output in the first merger if it is not true that the comparison in the first merger during the first time period indicated equal digits, and if there are equal digits, for selecting the relevant data in the second merger (either b1,1 or a1,1), and for advancing both pointers in the second merger (11-1), and for outputting control information indicative of the advancing being to the third merger; (c) means (56, 57) for adding the control information of the first merger to the difference information of the second merger before performing calculations in the second merger, so that the particular pointer cannot be moved if the result of the addition is null; (d) means for repeating steps (b) and (c) in following time periods for the following mergers. An apparatus for merging/sorting as defined in claim 8, wherein control circuits (61) are connected with the bit sliced mergers (10, 11) as coupling means for flexibly coupling said mergers, so that one processor for merging/sorting long data or a plurality of processors for merging/sorting short data can be built respectively.

Inventors: TANAKA, YUZURU, TSUCHIDA, MASASHI, YAMAMOTO, AKIRA
Applicants: HITACHI, LTD., TANAKA, YUZURU
Application year: 1985
Main classification: G06F15
IPC codes: G06F7, G06F17, G06F15