MOS TRANSISTORS HAVING SCHOTTKY LAYER ELECTRODE REGIONS AND METHOD OF THEIR PRODUCTION

Abstract: A MOSFET structure in a silicon body (10) has a Schottky layer source electrode (16), such as platinum silicide, which extends into and fills a cavity underneath a sidewall oxide layer (14) located on a sidewall of the gate electrode. The cavity is formed by isotropically etching an exposed region of the silicon body surface at the source and drain regions to be formed, in order to undercut the sidewall oxide layer, whereby an edge of the subsequently formed Schottky source electrode in the cavity is substantially aligned with an overlying edge of the gate electrode.

Description: MOS TRANSISTORS HAVING SCHOTTKY LAYER ELECTRODE REGIONS Field - of the-Invention This invention relates to semiconductor devices and particularly to MOS (metal oxide semiconductor) field effect transistors including Schottky layer electrode regions. Background of the-Invention It is known that layers composed of certain metals and metal-like materials ("Schottky layers") have the property of forming Schottky barriers at their interfaces with a semiconductor body, and that these Schottky layers can be used as source and/or drain electrodes in p-channel MOS transistors, such transistors having certain desired characteristics, e.g., low leakage currents. A problem with such Schottky layer transitors, however, is that of providing close alignment of the source and/or drain regions with edges of the gate electrode. This problem is solved by this invention. Summary-of the-Invention This invention in one embodiment involves a MOSFET device structure located at a major surface of a silicon semiconductor body, having a Schottky source and/or drain electrode layer, and a gate electrode overcoated with an insulating material layer. The source and/or drain electrode layers each extends into a cavity in the body which extends under the insulated gate electrode structure thereby providing alignment of the source and/or drain regions with edges of the gate electrode. Whether the Schottky electrodes make a Schottky barrier or ohmic contact depends upon the conductivity of the contacted semiconductor material, as described hereinafter. Brief Description of-the-Drawing FIGS. 1-10 illustrate in cross section various successive stages in the manufacture of an illustrative portion of a p-channel MOSFET structure in accordance with a specific embodiment of the invention; FIG. 11 illustrates in cross section a stage in the manufacture of an illustrative portion of a p-channel MOSFET structure in accordance with another specific embodiment of the invention; and FIG. 12 illustrates in cross section an n-channel MOSFET structure in accordance with yet another specific embodiment of the invention. FIGS. 5-8 show, on an enlarged scale, a left-hand portion of the structure shown in FIGS. 1-4 and 9-10. Detailed-Description The workpiece shown in FIG. 1 fabricated by known processes is and comprises a silicon substrate 9 having an n type epitaxial surface layer 10 thereon, a thick oxide layer 11 known as a "field" oxide, a thin oxide layer 12 eventually to form the gate dielectric layer, and a gate electrode layer 13 of polysilicon. Next (FIG. 2), the exposed top and side surfaces of the polysilicon layer 13 are subjected to a conventional oxidation step to provide the layer with a thin silicon dioxide covering layer 14. Typically, this thin oxide layer 14 has a thickness of about 300 Angstroms. As a result of the oxidation of the polysilicon, the thickness of the original thin oxide layer 12 (FIG. 1) is increased somewhat, as indicated by the designation of oxide layer 121 (FIG. 2), except in regions thereof (still denoted by reference numeral 12 in FIG. 2) underlying the polysilicon layer 13. Then the exposed portions of the thin oxide layer 121 and the top portion (but not the sidewall portions) of the thin oxide layer 14 are completely removed (FIG. 3) by an anisotropic etching step, such as by the known chemically reactive back-sputtering (reactive ion etching) with fluoride ions (F+) in a plasma produced by CHF3 (Freon 23). By "anisotropic" etching is meant that the removal of material during etching is preferential in that only those surfaces which are parallel to the top surface of the layer 10 are attacked and removed by the etching process. Next, as indicated in FIG. 4, the then exposed top surface of the n-type surface layer 10 is subjected to an isotropic etching step to remove typically a thickness of about 95 Angstroms of silicon and thus to undercut the remaining sidewall oxide layer 14 and to form cavities located between the bottom of this sidewall oxide and the top surface of the n-type surface layer 10. By "isotropic" etching is meant that the etch removal rate is substantially the same in all directions, although there can also be some crystallographic preferences, for example, as indicated by the slanting wall portions 101.1 and 102.1 of the exposed top surface portions 101 and 102 of the ntype silicon layer 10. This isotropic etching can be either a wet etching, typically with a liquid mixture of hydrofluoric acid and nitric acid, or a dry etching, typically with argon or other suitable etchant gas, at a sufficiently high pressure of about one mm Hg to result in substantially isotropic etching, for a time interval sufficient for undercutting the sidewall oxide 14 by the distance of 95 Angstroms with an accuracy to within 10 Angstroms. Then, as indicated in FIG. 5, positively charged argon ions are directed upon a platinum cathode target 31, whereby the top surface of the structure being manufactured is subjected to an anisotropic deposition of platinum layers 32, 33, and 34. More specifically, the structure being manufactured is placed in proximity to a platinum target from which platinum atoms are removed by sputtering due to the positively charged argon ions. These ions arrive at the platinum target 31 with considerable momentum, acquired by the ions under the influence of an ion accelerating dc electric field produced by a dc voltage E1 of negative polarity applied to the target 31 and an ion accelerating ac field produced by an RF voltage E2 applied through a capacitor C2 to the surface layer 10. Typically, E1 is about 1,000 volts; and E2 is about 500 volts peak-to-peak (twice the ac amplitude) at a frequency of about 13 MHz. Consequently, relatively very little (if any) argon strikes (with any considerable momentum) the structure as compared with the target 31. In this way, the platinum is not removed from the layers 32, 33, and 34. The temperature of the structure is, or is maintained, advantageously at about 200 degrees C or less during this anisotropic platinum deposition of the layers 32, 33, and 34, in order to ensure that the deposited platinum does not become platinum silicide. Next, the sputtering process is repeated, but under conditions resulting in the platinum layers 32, 33 and 34 being removed and redistributed as deposits 35 and 36 (FIG. 6) within the cavities underlying the oxide layers 11 and 14. This is accomplished by increasing the ac voltage E2 to a higher voltage, e.g., 1000 volts, whereby the argon ions strike the top surfaces of the workpiece to remove the platinum layers 32, 33 and 34. The platinum from those layers, as well as some from the target 31, is scattered in all directions including directions into the cavities. Once deposited in the cavities, however, the overlying edges of the oxide layers 11 and 14 protect the deposits 35 and 36 from the bombarding argon ions whereby these deposits are both formed and maintained in the sputtering process. Typically, the structure is maintained at about 200 degrees C or less, again to ensure that platinum silicide (which is more resistant to sputter-removal than is platinum) does not form. While the presence of the layers 32, 33 and 34 (FIG. 5) is generally preferred to ensure complete filling of the cavities, these layers need not be prior formed, and all the platinum for the cavities can be obtained in a single sputtering process directly from the target 31. Then, as indicated in FIG. 7, the ac voltage E2 is reduced, typically back to about 500 volts peak-to-peak, whereby platinum layers 41, 42, and 43 are anisotropically deposited upon the top surfaces of the structure being manufactured. Again, the temperature of the structure is below about 200 degrees C, so that platinum silicide does not form. Next, to sinter the platinum and thereby form platinum silicide, the structure is heat-treated in a suitable atmosphere, such as argon gas mixed with about 15 percent oxygen, at a temperature of typically about 625 degrees C. The platinum in the layers 42 and 43 thereby become platinum silicide layers 15 and 16 (FIG. 8), because they overlie silicon. However, the extreme lefthand portion of the layer 42, which does not overlie silicon, remains essentially platinum. Then the platinum, but not the platinum silicide, is removed, as by a wet etching with aqua regia typically at about 80 degrees C, whereby the platinum silicide layers 15 and 16 remain. During the silicide forming process, the layer 43 (16) expands into the surrounding silicon. By proper selection of dimensions and processing parameters, such expansion results in the right-hand edge of the layer 16 (the source region) being in close alignment with the lefthand edge of the gate electrode 13. The same result, if desired, is obtainable with the drain region 17 (FIG. 9) of the device. Obtaining such alignments is a principal advantage of the invention. After the formation of the platinum silicide layers 15, 16, and hence 17, the top surface of the structure being fabricated is coated at selected areas with a known insulating layer 22 (FIG. 9) having an opening therethrough to expose the underlying platinum silicide layer 15. Known means are then used to provide contacts 18, 19, and 20 to the gate electrode and source and drain regions, respectively, as shown in FIG. 10. As an alternative to the above steps, and as indicated in FIG. 11, positively charged argon ions are directed upon a platinum cathode target 31, whereby, in one step, platinum is simultaneously deposited on the workpiece and converted to platinum silicide where it contacts silicon. In this process, the workpiece is maintained at a temperture of around 6250C to form the silicide. As another alternative to the platinum deposition, a low pressure chemical vapor deposition of the platinum can be used, followed by sintering the deposited platinum to form platinum silicide in the regions underlain by silicon and by removal of the platinum underlain by silicon dioxide (but not of the platinum silicide) by means of a wet etching with aqua regia, for example. FIG. 12 illustrates in cross section an n-channel MOSFET device structure 100 in accordance with another embodiment of the invention. Here platinum silicide source and drain electrodes 86 and 87 make essentially ohmic (rather than Schottky barrier) contact with underlying n+ doped silicon regions 81 and 82 in a p-type surface layer 80. Instead of aligning the edges of the gate electrode with corresponding edges of the platinum silicide electrodes, as in the previously described structures, each edge of the gate electrode 18 in the structure 100 is aligned with the corresponding underlying proximate edge (pn junction) of the n+ doped silicon region 81 or 82. The structure 100 can be fabricated as described above but with the following modifications: (1) forming the n+ regions 81 and 82 in the p-type layer 80, (2) making the depth of the cavity (formed by isotropic etching) somewhat less (for alignment purposes), and (3) depositing correspondingly less platinum. More specifically, the n+ regions 81 and 82 can be formed during the sputtering of the platinum by adding the donor impurity dopant arsenic or antimony (or both) to the target 31 (FIG. 7 or FIG. 11) whereby these n+ regions 81 and 82 are simultaneously formed ("cosputtered") during the bombardment of the platinum. These n+ regions are thus formed by rejection from the platinum of the impurity dopant into the silicon ("segregation coefficient"). Because all subsequent processing temperatures are well below the temperature at which significant diffusion of impurities in silicon can occur, the thickness of the n+ regions 81 and 82 can be as little as about 100 Angstroms (or less). Alternatively, the n+ regions 81 and 82 can be formed at an earlier stage of the fabrication--for example, by means of conventional techniques as ion implantation and diffusion of donor impurities using the gate electrode layer 13 together with sidewall oxide layer (FIG. 4) as a protective mask which is impervious to these impurities. In any event, at their extremities the n+ regions 81 and 82 form pn junctions 91 and 92 in the p-type layer 80. Advantageously, the pn junction 91 has its right-hand extremity substantially aligned with the left-hand edge of the gate electrode layer 13. This alignment can be obtained, for example, by making the initial depth of the cavity (FIG. 4) equal to about 63 Angstroms and the thickness of the n+ region 81 equal to about 100 Angstroms, whereby after a (net) deposition of about 100 Angstroms of platinum the thickness of the platinum silicide layer 81 is about 200 Angstroms. As known in the art (for example, see M. P. Lepselter and J. M. Andrews, "Ohmic Contacts to Silicon," printed in Ohmic Contacts to Semiconductors, edited by B. Schwartz, published by The Electrochemical Society, 1969, pp. 159-186, Table 1 at p. 173), platinum silicide forms a Schottky barrier with n-type silicon having a barrier height of 0.85 volts as compared with a barrier height of only 0.25 volts with p-type silicon. Because of this relatively high barrier height with n-type silicon, which would seriously impair the transconductance of the MOSFET structure, the n+ regions 81 and 82 were formed in the n-channel structure 100. In this way, the effective barrier is reduced to acceptable levels by virtue of quantum mechanical tunneling of charge carriers through the barrier, whereby the MOSFET transconductance is not seriously impaired by the Schottky barrier. It should be understood that both p-channel and n-channel MOSFET structures 20 and 100 can thus be formed upon the same silicon bulk 9, thereby to provide complementary MOS (CMOS) technology, in which the n-type surface layer 10 is the "n-tub" and the p-type surface layer 80 is the "p-tub" in CMOS terminology. Instead of platinum, titanium or zirconium can be used to form the metal silicide source and drain electrodes. Moreover, since titanium silicide and zirconium silicide both have approximately the same barrier height or 0.55 volts with respect to both p-type and ntype silicon, a symmetrical structure can be used for these silicides. That is, p-channel and n-channel transistors with zirconium or titanium silicide electrodes are advantageously supplied with highly doped p+ and n+ impurity regions, respectively, intervening between the silicide electrodes and the n-type and p-type surface layers 10 and 80, respectively. Typically, the thicknesses of these p+ and n+ regions are both about 100 Angstroms (or less). The doping concentration, in terms of impurity atoms (or ions) per square centimeter (i.e., the "surface concentration") in these p+ and n+ impurity regions can and should be made sufficiently low to avoid reintroduction of the latchup problem, typically of the order of 1013 or less per square centimeter for a tub of the doping level of the order of 1013 or more per square centimeter, but at the same time the volume concentration is sufficiently high, typically of the order 5 x 1019 per cubic centimeter, to lower the effective barrier (by virtue of tunneling) so that the transconductance of the resulting MOS transistor structure is not seriously impaired. On the other hand, somewhat higher surface concentrations of impurities in, and hence greater thicknesses of, the n+ and p+ impurity regions for lowering the effective barrier can be tolerated without running too much risk of latchup during operation with ordinary power supply current limitations. Further modifications are possible. For example, for forming the metal silicide electrodes, other transition metals can be used--such as cobalt, hafnium, or tantalum-which form metal silicides suitable for Schottky barriers with silicon. Instead of forming the platinum or other metal silicide by sputtering, the metal can be first evaporated all over the top surface of the structure being fabricated and then converted (on the silicon regions) into the metal silicide by means of a temperature pulse ("spike") treatment, typically of about 400 to 650 degrees C for about 2 to 6 minutes; the metal remaining as such on the oxide can thereafter be removed by etching with hot aqua regia.

Claims: Claims 1. An MOS transistor structure having a Schottky layer source electrode (16) formed on a semiconductor body 10; a gate electrode layer (13) separated from the body by a gate insulating layer (12); and a sidewall insulating layer (14) coating a sidewall of the gate electrode, CHARACTERIZED IN THAT the source electrode (16) of the transistor extends into and fills a cavity in said body which undercuts the sidewall insulating layer and terminates in preselected relationship with an edge of said gate electrode layer. 2. The transistor of claim 1 in which the semiconductor body is silicon, the gate insulating layer is silicon dioxide, the gate electrode layer is polycrystalline silicon,- and the source electrode layer is a metal silicide. 3. The transistor of claim 2 in which the sidewall insulating layer is silicon dioxide. 4. The circuit of claim 1 in which the source electrode extends underneath the sidewall insulating layer to a position in substantial alignment with an overlying edge of the gate electrode layer. 5. A method for making a MOSFET transistor in a semiconductor body comprising the steps of: forming a polysilicon gate electrode having a pair of opposing sidewalls each coated with an oxide layer, the gate electrode being separated from a major surface of a monocrystalline silicon semiconductor body by a silicon dioxide layer: CHARACTERIZED BY etching the silicon body at then exposed portions of its major surface contiguous with the then exposed edges of the sidewall oxide layer to form a cavity in the silicon body undercutting one of the sidewall oxide layers; and bombarding the major surface with metal and forming metal silicide layers on the then exposed silicon portions of the major surface of the silicon body to fill the cavity with a metal silicide layer. 6. The method of claim 5 in which, during the bombarding, essentially no metal or metal silicide accumulates on the oxide while the metal silicide is formed and accumulates on the exposed portions of the silicon body. 7. The method of claim 6 in which a top major surface of the polysilicon gate electrode is exposed during the metal bombardment, whereby metal silicide is also formed and accumulates on the major surface of the gate electrode during the metal bombardment. 8. The method of claim 7 in which the metal is platinum.

Inventors: LEPSELTER MARTIN PAUL, LEPSELTER, MARTIN, PAUL
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1985
Main classification: H01L29
IPC codes: H01L21, H01L29