SEMICONDUCTOR CIRCUIT

Abstract: A semiconductor circuit for generating a pulse with a constant pulse width regardless of the pulse widths of the input signals, including a pulse-width fixing circuit (WC) for latching the output signal of a gate circuit when an input signal received by the gate circuit changes and for resetting the latching a predetermined time after the latching.

Description: The present invention relates to a semiconductor circuit, more particularly, to a circuit applied in, for example, a static semiconductor memory for generating a clock signal when an input signal, such as the address signal, changes. A static memory generally does not need a clock signal, in contrast to a dynamic memory which always needs a clock signal. Some special static memories, however, use clock signals to represent address changes, write instructions, or power downs, to decrease the access time, and so forth. In static memories using the clock signals, when a memory cell of the static memory is accessed, a bit-line pair is temporarily short-circuited to be the same potential by applying a clock signal and then is changed to a high (H) level or a low (L) level in accordance with the data stored in the memory cell. This decreases the access time in comparison with the case without using a clock signal, wherein the change is effected from the H or L state depending on the previously read stored data to the H or L state depending on the stored data which is to be currently read. This short-circuiting is also effected in a sense amplifier, wherein the response speed for currently read data is increased by resetting the output signals by the clock signal before starting the operation of the sense amplifier. A clock signal representing a change of an input signal, such as an address signal, is conventionally generated by taking a logical OR of pulses generated by changes of respective input signals. For example, the address signals as the input signals are 10 bits in a 1K-memory, 11 bit in a 2K-memory, and so forth. From each bit of the address signals, a complementary pair of bit A i and its inverted bit A i (i=0, 1, 2, ...) is obtained, which are input to a decoder to act as a signal for selecting a word line or a bit line. A pulse generating circuit for each of the above-mentioned pulses is provided in an address inverter. The pulse generated from the pulse generating circuit is supplied to the OR gate for obtaining the above-mentioned logical OR. However, the clock signal thus generated has a problem in that, when the rising time and the falling time of the input signals are indefinite, the clock width of the clock signal changes depending on the input signals. When the input signals are input address signals, this problem is caused because (1) since the address inverters and, accordingly, the above-mentioned pulse generating circuits are present over a certain area of a memory chip, the wiring lengths between each pulse generating circuit and the OR gate are different from each other, so that the timings of the output pulses reaching the OR gate are slightly different; (2) since the pulses output from the respective pulse generating circuits do not always have the same pulse widths, the pulse widths of the clock signals and the falling timings of the clock pulses are changed depending on which address signal is changed; (3) there is a case when a plurality of address signals (bits) are changed almost simultaneously but at slightly different timings, and, in this case, since the clock width is a logical sum of the plurality of pulses, the pulse width has a tendency to expand because the pulse widths generated by the respective changes of the address signals are not always the same. It is not preferable, in order to ensure the short- circuiting of the pair of bit lines and so forth, that the clock pulse width be changed depending on which of the input signals or which of the input address signals changes. Therefore, for the above-mentioned reset of the bit line pair or of the sense amplifier, the clock signal is required to have at least a predetermined pulse width and constant falling and rising timings in response to each change of the input signals. It is accordingly desirable to provide a semiconductor circuit which can provide a pulse with at least a constant pulse width in response to each change of input signals. US-A-3 601 636 discloses a single-shot device having two NAND gates interconnected to provide an output pulse of fixed duration in response to an input signal, obtained using an RC delay circuit interposed between the two NAND gates. For short input pulses, the output pulse is the same length regardless of the input signal, but for longer input pulses the output pulse has at least the duration of the input pulse. EP-A-0 105 757 by the present applicant discloses an asynchronous memory device having an address change detector which generates a clock signal of selected pulse width in response to a change in an address signal. The address change detector includes a set of pulse generators each responsive to a respective address bit, and an OR gate receiving the pulses from the pulse generators, the output of the OR gate constituting the clock signal. J. Markus, "Modern Electronic Circuits Reference Manual", McGraw-Hill, 1980, discloses on page 680 a so-called PWM MONO circuit which provides pulse-width modulation with high-duty cycles and complementary output. The output pulse is generated from a NOR gate and lasts at least as long as a "STROBE" input signal applied to the NOR gate. According to the present invention, there is provided a clock signal generating circuit of a semiconductor memory device, comprising:- a plurality of pulse generating circuits each having an input for receiving an address input signal and having an output for providing a pulse in response to a change of said address input signal; and a gate circuit having a plurality of inputs connected to the outputs of said pulse generating circuits and having an output for providing an output signal in response thereto; and characterised in that:- said gate circuit comprises a set of inverter gates each formed by a respective input transistor and pull-up transistor whose gate terminals are both connected to an output of a respective one of said pulse generating circuits, all the pull-up transistors being connected in common to said output of said gate circuit, and all the input transistors being connected in series; and in that a pulse-width control circuit is provided, operatively connected to the output of said gate circuit, for latching the output signal of the gate circuit and for later resetting said latching so as to extend the pulse width of the output signal to at least predetermined width; said pulse-width control circuit comprising: a delay circuit for delaying the output signal of the gate circuit; and a latch and reset circuit having a first transistor and a second transistor connected in series between a first power supply line and the output of said gate circuit, said first transistor being controlled in response to the output of said gate circuit, and said second transistor being controlled in response to the output of said delay circuit, and a third transistor and a fourth transistor connected in parallel between said gate circuit and a second power supply line, said third transistor being controlled in response to the output of said gate circuit, and said fourth transistor being controlled in response to the output of said delay circuit. Thereby, the present invention can guarantee a predetermined minimum duration of an output clock signal, whilst allowing the output clock signal to be elongated in response to appropriate input signals. Reference will now be made, by way of example, to the accompanying drawings, wherein:- Fig. 1 is a schematic block diagram of a semiconductor memory chip for explaining the background of the present invention; Fig. 2 is a circuit diagram of a semiconductor circuit according to an embodiment of the present invention; Fig. 3 is a circuit diagram of a clock signal generating circuit included in the circuit shown in Fig. 2; Figs. 4A to 4F are waveform diagrams for explaining the operation of the circuit shown in Fig. 3; Fig. 5 is a circuit diagram illustrating an example of a pulse generating circuit included in the circuit shown in Fig. 2; and Fig. 6 is a circuit diagram illustrating another example of a pulse generating circuit included in the circuit shown in Fig. 2. Figure 1 is a schematic plan view of a semiconductor memory chip. In Fig. 1, the semiconductor memory chip CP has a memory cell array MCA, a plurality of address inverters AI₀ , AI₁ , ..., and AI n , and a clock signal generating circuit CG. Each of the address inverters AI₀ , AI₁ , ..., and AI n consists of an address buffer circuit ADB i and a pulse generating circuit PG i , where i=0, 1, ..., or n. The address buffer circuit ADB i receives an address signal A i to provide a waveform shaped address signal. The pulse generating circuit PG i generates a pulse in response to a change in the address signal A i . The outputs of the pulse generating circuits PG₀ , PG₁ , ..., and PG n are connected through conducting lines ℓ₀ , ℓ₁ , ..., and ℓ n to the inputs of the clock signal generating circuit CG. Since the lengths of the conducting lines ℓ₀ , ℓ₁ , ..., and ℓ n are different from each other, the times necessary to transfer the signals from the pulse generating circuits PG₀ , PG₁ , ..., and PG n to the clock signal generating circuit CG are slightly different from each other. This causes the problem of different timings of the generation of the clock signals output from the clock signal generating circuit, as mentioned before. Figure 2 is a circuit diagram of a semiconductor circuit according to an embodiment of the present invention. In Fig. 2, A₀ , A₁ , A₂ , ... are bits of an address for accessing a static memory, and PG₀ , PG₁ , PG₂ , ... are pulse generating circuits provided in address inverters AI₀ , AI₁ , ... (Fig. 1) for receiving respective bits A₀ , A₁ , ... of the address. Each pulse generating circuit PG i (i=0, 1, 2, ...) outputs a pulse having a relatively indefinite width of the low level (hereinafter referred to as L) when the corresponding bit changes from the high level (H) to L or from L to H. PG n is a pulse generating circuit which outputs a pulse when a chip select signal CS turns from the H level to the L level. The outputs of the pulse generating circuits PG₀ , PG₁ , PG₂ , ..., and PG n are connected to the gate electrodes of pairs of transistors Q₁₁ and Q₂₁ , Q₁₂ and Q₂₂ , Q₁₃ and Q₂₃ , ..., and Q 1n and Q 2n , respectively. The pairs of transistors Q₁₁ and Q₂₁ , Q₁₂ and Q₂₂ , Q₁₃ and Q₂₃ , ..., and Q 1n and Q 2n each forms a complementary metal oxide semiconductor (CMOS) inverter gate. These CMOS inverter gates constitute a clock signal generating circuit CG of a NAND gate functioning as an OR gate with respect to the L level of at least one of the input signals. That is, when at least one of the pulse generating circuits PG₀ , PG₁ , ..., and PG n generates the pulse of the L level, the clock signal generating circuit CG outputs the H level at its output T₁. Since the clock signal generating circuit CG is a NAND gate, when all of the inputs are at the H level, the level of an output end T₁ becomes L. If at least one input is L, the level of the output end T₁ becomes H. Note that the transistors Q₁₁ , Q₁₂ , ..., and Q 1n , sources of which connected to a power supply V CC are illustrated by small circles in the figure, are P-channel metal oxide semiconductor (MOS) transistors; and the transistors Q₂₁ , Q₂₂ , ..., and Q 2n without the small circles are N-channel MOS transistors. The N-channel MOS transistors Q₂₁ , Q₂₂ , ..., and Q 2n are connected in series. There are the same number of pairs of the P-channel and N-channel MOS transistors Q₁₁ and Q₂₁ , Q₁₂ and Q₂₂ , ..., and Q 1n and Q 2n as pulse generating circuits PG₀ , PG₁ , ..., and PG n . To the output end T₁ , two CMOS inverter gates consisting of P-channel MOS transistors Q₃ and Q₅ and N-channel MOS transistors Q₄ and Q₆ are connected. By this, a node T₂ of the CMOS inverter consisting of the transistors Q₅ and Q₆ becomes an output end of the clock signal generating circuit CG. In conventional circuits, only the pulse generating circuits PG₀ , PG₁ , ..., and PG n and the clock signal generating circuit CG are provided, whereby a clock signal is generated from the output end T₂ whenever any address bit A₀ , A₁ , ... changes or the chip select signal CS falls. However, as mentioned before, there was a problem in that the pulse width and particularly the end time (here, the rising time) of the clock signal generated by the conventional clock signal generating circuit are not always constant. The generating timings (here, the falling timings) of the clock signals of the pulse generating circuits PG₁ , PG₂ , ... are relatively constant. The fluctuations occur in the end timings (here, the rising timings). Because of these fluctuations, the pulse width of the output clock signal was not always constant. In the present invention, the clock signal generating circuit CG is provided with a circuit WC for making the output pulse width constant. The circuit WC consists of a latch and reset circuit, constructed by P-channel MOS transistors Q₇ and Q₈ connected in series between the power supply V CC and the output end T₁ of the NAND gate and N-channel MOS transistors Q₉ and Q₁₀ connected in parallel between the source of the transistor Q 2n and the ground power supply V SS , and a control circuit CNT, constructed by P-channel MOS transistors Q₃₁ and Q₃₃ , N-channel MOS transistors Q₃₂ and Q₃₄ , a resistor R, and a MOS capacitor C forming an RC delay circuit, as shown in Fig. 2. Figure 3 is a circuit diagram of the clock signal generating circuit CG and the circuit WC included in the circuit shown in Fig. 2. Referring to Fig. 3, in the latch and reset circuit formed by the P-channel MOS transistors Q₇ and Q₈ and the N-channel MOS transistors Q₉ and Q₁₀ , the gate of the transistor Q₇ is connected to the output end of the inverter formed by the transistors Q₃ and Q₄; the gate of the transistor Q₈ is connected to the output end of the control circuit CNT; the gate of the transistor Q₉ is connected to the output end of the CMOS inverter formed by the transistors Q₃ and Q₄; and the gate of the transistor Q₁₀ is connected to the output end of the control circuit CNT. In the control circuit CNT, the transistors Q₃₃ and Q₃₄ form one CMOS inverter, and the transistors Q₃₁ and Q₃₂ form another. The gates of the transistors Q₃₃ and Q₃₄ function as an input end of the control circuit CNT and are connected to the output end T₁ of the NAND gate. The output of the CMOS inverter formed by the transistors Q₃₃ and Q₃₄ is connected to the gates of the transistors Q₃₁ and Q₃₂. The source of the transistor Q₃₄ is connected through the resistor R to the ground power supply V SS . Between the output of the CMOS inverter formed by the transistor Q₃₃ and Q₃₄ and the ground power supply V SS , the CMOS capacitor C is connected. The output of the CMOS inverter formed by the transistors Q₃₁ and Q₃₂ functions as the output of the control circuit CNT. Figures 4A through 4F show the potential changes in respective portions in the circuit shown in Fig. 3. In Figs. 4A-4F, ₀ and ₁ represent pulses generated by the pulse generating circuits PG₀ and PG₁; and 1 ○ , 2 ○ , 3 ○ , and 4 ○ represent potential changes of the nodes 1 ○ , 2 ○ , 3 ○ , and 4 ○ in the circuit shown in Fig. 3. The operation of the circuit shown in Fig. 3 is described with reference to Figs. 4A to 4F. In a state when no change occurs in any address bit or the chip select bit CS , the output signals ₀ , ₁ , ... of the all pulse generating circuits PG₀ , PG₁ , ... and PG n are at the H level so that, as illustrated in Fig. 3 and in Fig. 4C, the node T₁ is L; the output 2 ○ of the inverter formed by the transistors Q₃ and Q₄ is H, as shown in Fig. 4D; and, accordingly, the transistor Q₇ is OFF; the transistor Q₉ is ON; the output 3 ○ of the CMOS inverter formed by the transistors Q₃₃ and Q₃₄ is H, as shown in Fig. 4E; the capacitor C is charged to V CC ; the output 4 ○ of the inverter formed by the transistors Q₃₁ and Q₃₂ is L, as shown in Fig. 4F; and, accordingly, the transistor Q₈ is ON and the transistor Q₁₀ is OFF. In the transistors Q₇ and Q₈ , since the transistor Q₇ is OFF, the node T₁ is not pulled up to V CC . Also, in the transistors Q₉ and Q₁₀ , since the transistor Q₉ is ON, the transistors Q₂₁ , Q₂₂ , ... and Q 2n connected in series in the NAND gate are connected through the transistor Q₉ to a ground power supply V SS . In this state, when either of the address bits, for example, A₁ , is changed so that a pulse ₁ falls from H to L at a time t₁ as illustrated in Fig. 4B, the NAND gate generates H so that node T₁ becomes H as shown in Fig. 4C, and the output 2 ○ of the inverter formed by the transistors Q₃ and Q₄ becomes L. Therefore, the P-channel transistor Q₇ turns ON so that the node T₁ is pulled up to V CC by the transistors Q₇ and Q₈; and the transistor Q₉ turns OFF so that the source of the transistor Q 2n is inhibited from being pulled down to V SS . Thus, the node 2 ○ of the clock signal generating circuit CG is latched to L; and, accordingly, the output end T₂ is latched to H. In this state also, the output 3 ○ of the inverter formed by the transistors Q₃₃ and Q₃₄ gradually decreases to L; and the output 4 ○ of the inverter formed by the transistors Q₃₁ and Q₃₂ becomes H at a time t₂ when the level at the node 3 ○ becomes lower than the threshold voltage of the P-channel transistor Q₃₁. Since the RC delay circuit formed by the resistor R and the capacitor C is inserted, the change of the level at the nodes 4 ○ includes the time delay td. When the output 4 of the inverter formed by the transistors Q₃₁ and Q₃₂ becomes H after this delay, the P-channel transistor Q₈ turns OFF at a time t₃ so that the above-mentioned pulling up of the node T₁ is stopped, i.e. the latch is released; and the N-channel transistor Q₁₀ turns ON in response to the H level at the node 4 so that the transistors Q₂₁, Q₂₂, ... and Q 2n connected in series are connected through the transistor Q₁₀ to V SS . Accordingly, as long as the pulses from the pulse generating circuits are not present, i.e. under the condition that all of the output signals ₀, ₁, ... output from the pulse generating circuits PG₀, PG₁, ..., and PG n are at the H level, the node T₁ is pulled down to V SS (L level) and, therefore, the node 2 is raised to the H level at the time t₃ as shown in Fig. 4D. Thus, the output clock width of the clock signal generating circuit CG becomes a constant value determined by the RC time constant. Even when there are differences in the reset timings of the pulse ₁, as illustrated by arrows in Fig. 4B, the output clock pulse at the node 2 has a constant pulse width T. There is a possibility of generation of two or more pulses output at slightly different timings from the pulse generating circuits PG₀, PG₁, ... and PG n . As an example, Figs. 4A and 4B show the two pulses ₀ and ₁ generated at different timings t₁ and t₄ from the pulse generating circuits PG₀ and PG₁. In this case, the pulse width of the pulse at the node 2 is elongated to greater than the predetermined minimum value T, and terminates at a time t₅. The time t₅, hence the duration of the output clock pulse in this case, is determined by the reset timing of ₀. Fig. 4D shows the elongated output clock pulse by a dashed line. Fig. 5 shows an example of one of the pulse generating circuits PG₀, PG₁, ..., except for the circuit PG n . In Fig. 5, AP is an input pad to which one of the address bits A₀ , A₁ , A₂ , ... is applied; Q₄₁ , Q₄₃ , Q₄₅ , Q₄₇ , Q₄₉ , Q₅₁ , Q₅₃ , Q₅₅ , Q₅₇ , and Q₅₉ are P-channel MOS transistors; and Q₄₂ , Q₄₄ , Q₄₆ , Q₄₈ , Q₅₀ , Q₅₂ , Q₅₄ , Q₅₆ , Q₅₈ , and Q₆₀ are N-channel MOS transistors. Pairs of transistors Q₄₁ and Q₄₂ , Q₄₃ and Q₄₄ , Q₅₃ and Q₅₄ , and Q₅₅ and Q₅₆ , constitute CMOS inverters, respectively. Groups of transistors Q₄₅ , Q₄₆ , Q₄₇ and Q₄₈ , Q₄₉ , Q₅₀ , Q₅₁ and Q₅₂ , and Q₅₇ , Q₅₈ , Q₅₉ and Q₆₀ constitute CMOS NAND gates, respectively. The mutual conductances gm of the transistors Q₄₆ , Q₄₈ , Q₅₈ and Q₆₀ are made to be relatively small. On the contrary, the mutual conductances gm of the transistors Q₅₀ and Q₅₂ are made to be relatively large. Since the mutual conductances gm of the transistors Q₅₀ and Q₅₂ are relatively large, the output pulse  at the node T₃ falls rapidly in response to a change of an address bit applied to the input pad AP. Also, since the mutual conductances gm of the transistors Q₄₆ , Q₄₈ , Q₅₈ and Q₆₀ are relatively small, the output pulse  at the node N₃ rises a predetermined time later from the change of the address bit applied to the input pad AP. In more detail, for example, when the potential at the input pad AP is at H, then the node N₁ is L; the node N₂ is H; the transistor Q₄₆ is ON; the node N₄ is H; the node N₅ is L; the node N₆ is H; the transistor Q₄₈ is ON; and, accordingly, the node N₃ is L and the output end T₃ is H. In this state, the node N₄ is H; the node N₅ is L; and the node N₆ is H; and the transistor Q₅₂ is ON. From this state, when the address bit applied to the input pad AP turns to L, then the node N₁ becomes H; the node N₂ becomes L; the node N₃ becomes H; and the transistor Q₅₀ turns ON. Because of its large gm, the output end T₃ rapidly turns to the L level. Also, the node N₄ turns to L, and the node N₅ turns to H. The transistors Q₅₈ and Q₆₀ turn ON in response to the H levels at the nodes N₅ and N₃ , respectively. However, since the mutual conductances of the transistors Q₅₈ and Q₆₀ are relatively small, the node N₆ gradually turns to the L level. Therefore, in response to the rapid operation of the transistor Q₅₀ , the output end T₃ rapidly turns to the L level in response to a fall of the applied address bit. When the transistors Q₅₈ and Q₆₀ turn ON, the node N₆ gradually turns to the L level so that the transistor Q₅₂ becomes OFF. Thus, a predetermined time later from the fall of the address bit, the output end T₃ rises again to the H level. The pulse width of the pulse obtained at the output end T₃ of the pulse generating circuit PG is determined by the values of the mutual conductances gm of the transistors Q₅₀ , Q₅₂ , Q₅₈ , and Q₆₀. Similarly, when the potential at the input pad AP changes from L to H, a pulse having a pulse width corresponding to the difference in the mutual conductances gm of the transistors Q₅₀ , Q₅₂ and Q₄₆ , Q₄₈ is output at the output end T₃. Since the mutual conductances gm of the transistors can not be determined accurately in the manufacturing process, the pulse width of the pulse at the output end T₃ is relatively indefinite because the rising time is indefinite. Therefore, as illustrated in Fig. 4B by the arrows, the end of the pulse ₁ is indefinite. This is the reason why the pulse generating circuit CG including the circuit WC as shown in Fig. 2 is necessary. By the circuit shown in Fig. 2, a constant pulse width can be obtained regardless of the pulse widths applied from the pulse generating circuits PG₀ , PG₁ , ..., and PG n . Figure 6 is a circuit diagram showing an example of the pulse generating circuit PG n shown in Fig. 2. In Fig. 6, the circuit PG n includes pairs of P-channel and N-channel transistors Q₆₁ and Q₆₂ , Q₆₃ and Q₆₄ , Q₆₅ and Q₆₆ , and Q₇₁ and Q₇₂ which respectively constitute CMOS inverters. Q₆₉ is a P-channel transistor, and Q₇₀ and Q₇₃ are N-channel transistors. Q₆₇ , Q₆₈ , Q₆₉ and Q₇₀ constitute a CMOS NAND gate. This circuit PG n also generates a pulse at an output end T₄ in response to a change from H to L of the chip select signal CS . The pulse generating circuits PG₀ , PG₁ , ..., and PG n are not restricted to those for receiving the address bits A₀ , A₁ , A₂ , ... or the chip select signal CS . For example, a static random-access memory (RAM) is known in which a predetermined time after an address change, the selected word line is turned to the nonselected state (L level) so as to save power. In this case, when a write instruction is applied, the above-mentioned selected word line must be set to the H level during a necessary time. To do this, the pulse generating circuit must generate a pulse in response to a write enable signal WE . The clock signal generating circuit CG is not restricted to the circuit shown in Fig. 2. Various variations are possible within the scope of the present invention. For example, the number of the CMOS inverters in the clock signal generating circuit may be arbitrarily selected in accordance with the desired output. If a pulse of H level is necessary, an additional inverter may be added. Is a clock signal must be generated in response to a change from L to H of an input signal, this is also possible to those skilled in the art based on the circuit shown in Fig. 2. Further, in place of connecting the node T₁ to the gates of the transistors Q₃₃ and Q₃₄ , the output of the inverter formed by the transistors Q₃ and Q₄ may be connected through an additional CMOS inverter to the gates of the transistors Q₃₃ and Q₃₄ , or the output end T₂ may be connected to the gates of the transistors Q₃₃ and Q₃₄. Still further, in place of the output end T₂ , the output of the CMOS inverter formed by the transistors Q₃ and Q₄ may be used as the output end of the clock signal generating circuit CG.

Claims: A clock signal generating circuit of a semiconductor memory device, comprising:- a plurality of pulse generating circuits (PG₀, PG₁, ...) each having an input for receiving an address input signal and having an output for providing a pulse in response to a change of said address input signal; and a gate circuit (CG) having a plurality of inputs connected to the outputs of said pulse generating circuits (PG₀, PG₁, ...) and having an output for providing an output signal in response thereto; characterised in that:- said gate circuit (CG) comprises a set of inverter gates (Q₁₁, Q₂₁; Q₁₂, Q₂₂;...Q 1N , Q 2N ) each formed by a respective input transistor (Q₂₁, Q₂₂,...Q 2N ) and pull-up transistor (Q₁₁, Q₁₂,...Q 1N ) whose gate terminals are both connected to an output of a respective one of said pulse generating circuits (PG₀, PG₁,...), all the pull-up transistors being connected in common to said output of said gate circuit, and all the input transistors being connected in series; and in that a pulse-width control circuit (WC) is provided, operatively connected to the output of said gate circuit (CG), for latching the output signal of the gate circuit and for later resetting said latching so as to extend the pulse width of the output signal to at least a predetermined width; said pulse-width control circuit (WC) comprising: a delay circuit for delaying the output signal of the gate circuit (CG); and a latch and reset circuit (Q₇ ...Q₁₀) having a first transistor (Q₇) and a second transistor (Q₈) connected in series between a first power supply line (V cc ) and the output of said gate circuit, said first transistor being controlled in response to the output of said gate circuit (CG), and said second transistor (Q₈) being controlled in response to the output of said delay circuit, and a third transistor (Q₉) and a fourth transistor (Q₁₀) connected in parallel between said gate circuit and a second power supply line, said third transistor being controlled in response to the output of said gate circuit, and said fourth transistor being controlled in response to the output of said delay circuit. A circuit as set forth in claim 1, wherein said pulse-width control circuit (WC) further comprises:- a control circuit (CNT) having an input end responsive to said output of said gate circuit (CG) and having an output end connected to said latch and reset circuit (Q₉, Q₁₀), said control circuit (CNT) including said delay circuit for transferring a signal change at said input end to said output end with a predetermined time delay. A circuit as set forth in claim 2, further comprising an inverter (Q₃, Q₄) having an input end, connected to said output of said gate circuit (CG), and an output end, connected to a gate electrode of said first transistor (Q₇), and wherein said second transistor (Q₈) has a gate electrode connected to said output end of said control circuit (CNT), said first and second transistors being connected in series between a power supply and said output of said gate circuit (CG). A circuit as set forth in claim 3, wherein said third transistor (Q₉) has a gate electrode connected to said output end of said inverter (Q₃, Q₄) and said fourth transistor (Q₁₀) has a gate electrode connected to said output end of said control circuit (CNT), said third and fourth transistors being connected between said gate circuit (CG) and a ground power supply. A circuit as set forth in claim 4, wherein said control circuit (CNT) comprises:- a first inverter (Q₃₃, Q₃₄) having an input end connected to said output of said gate circuit (CG); a second inverter (Q₃₁, Q₃₂) having an input end connected to the output end of said first inverter (Q₃₃, Q₃₄) and having an output end connected to the gate electrodes of said second transistor (Q₈) and said fourth transistor (Q₁₀); a resistor (R) connected between said first inverter (Q₃₃, Q₃₄) and the ground power supply; and a capacitor (C) connected between the output end of said first inverter (Q₃₃, Q₃₄) and the ground power supply; said resistor (R) and said capacitor (C) forming said delay circuit. A circuit as set forth in any one of claims 1 to 5, further comprising an additional pulse-generating circuit (PG N ) arranged to receive a chip select signal ( CS ) for selecting said memory device. A circuit as set forth in any one of claims 1 to 5, further comprising an additional pulse-generating circuit (PG N ) arranged to receive a write enable signal for enabling a write operation of said memory device. A circuit as set forth in any preceding claim, wherein said clock signal is used for short-circuiting pairs of bit lines in said memory device.

Inventors: SUZUKI, ATSUSHI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H03K3
IPC codes: H03K3, G11C11