SYSTEM FOR CORRECTING ERROR IN DIGITAL DATA

Abstract: A system for correcting error in digital data, wherein the reproduced data signals are supplied to error correcting circuits (34), (43) to correct error in the reproduced data signals relying upon the interpolation or substitution of data in the proximity of erroneous data. When an error is con­ tained in the proximity data, the data in the proximity thereof is corrected and is fed back to the correcting circuits (34), (43) to correct it. The erroneous data are sequentially cor­ rected relying upon small correct data.

Description: The present invention relates to an error concealing system for digital data for use with, for example, a digital VTR. BACKGROUND ART EP 0 044 963-A1 discloses a method for error concealing erroneous digital data in which the correct data which precedes and the correct data which follows the chain of erroneous PCM-signals are used as a basis for calculating a first error-concealed data. The result of this calculation i.e. first error-concealed data then is used as a basis for the next interpolation process which provides the error-concealed value of the next disturbed data. Interpolation is carried out by an interpolation circuit which comprises a summing amplifier having three input terminals of different sensivity by which the input value is weighted. The output of the A/D-converter is fed to the input terminals via switches which are controlled by an error concealing control circuit. The second output terminal of the switches is connected to sample-and-hold circuits via another switch which is controlled by a control signal. The setting of the resistor circuitry depends on the number of subsequent erroneous data. If the number of erroneous data exceeds the number of four, the last correct data is fed to the output until there is only a difference of four sampling intervals to the next correct data. While the device of D1 is useful for linear arrays of data, it is not adapted to deal with two dimensional data arrays like video pictures because erroneous pixels in video pictures cannot only be error-concealed by the preceding a the subsequent pixel within the same line but also by surrounding pixels situated in the preceding and the next line of the same field or even the corresponding pixel in the preceding or the next field or frame. An example of a prior art digital VTR will hereinafter be described with reference to Figs. 1 to 3. In the first place, an arrangement relationship of rotary magnetic heads of the prior art digital VTR will be described with reference to Fig. 1. Reference letter DR designates a tape guide drum which is constituted by a rotary drum as an upper drum and a fixed drum as a lower drum. This tape guide drum DR may be formed of a fixed drum as an upper and lower drum and a rotary drum as a middle drum. Reference letters H A to H D designate recording rotary magnetic drums and H A ' to H D ' designate reproducing rotary magnetic heads. Each of these rotary magnetic heads is mounted on the rotary drum of the tape guide drum DR with an arrangement relationship that will be described below. The recording rotary magnetic heads H A , H B and H C , H D are two pairs of recording rotary magnetic heads disposed with an angular spacing of 180°, while the reproducing rotary magnetic heads H A ', H B ' and H C ', H D ' are two pairs of reproducing rotary magnetic heads disposed with an angular spacing of 180°. The lines connecting these two pairs of reproducing rotary magnetic heads and two pairs of recording rotary magnetic heads are perpendicular to each other. The recording rotary magnetic heads H A and H B are adapted to record a digitized video signal so as to form magnetic tracks each having a different azimuth on a magnetic tape TP, while upon reproducing the reproducing rotary magnetic heads H A ' and H B ' are adapted to reproduce the recorded signals on the respective tracks. Similarly, the recording rotary magnetic heads H C and H D are adapted to record a digitized video signal so as to form magnetic tracks each having a different azimuth on the magnetic tape TP, while upon reproducing, the reproducing rotary magnetic heads H C ' and H D ' are adapted to reproduce the signals recorded on these tracks. References TG₁ and TG₂ designate tape guide poles for determining a wrapping angle ϑ with which the magnetic tape TP is wound around the tape guide drum DR. The tape wrapping angle ϑ is selected to be, for example, 240°. Then, a recording system of the prior art digital VTR will be described with reference to Fig. 2. Reference numeral 1 designates an A/D converter to which component color video signals, i.e., a luminance signal Y, a blue color difference signal B-Y and a red color difference signal R-Y are supplied and thereby A/D-converted to be digital component video signals. These digitized component video signals are supplied to a multiplexer 2, in which they are multiplexed and 2-channel encoded and thereby produced as 2-channel multiplexed digital video signals. These signals are supplied to a shuffle circuit 3 provided with a memory and thereby shuffled. In this shuffle circuit 3, the 2-channel digital video signals are written in the memory by respective write clock pulses and then read out therefrom by respective read clock signals at a predetermined processing speed, whereby to shuffle the 2-channel digital video signals, thus preventing a burst error from occurring in a reproduced data due to the dropout of the tape and so on. The 2-channel digital video signals derived from the shuffle circuit 3 are supplied to an error correcting and encoding circuit 4 in which they are encoded and then fed to a time base expanding circuit (FIFO memory) 5 and thereby time-base-expanded. In the time base expanding circuit 5, the 2-channel digital video signals from the error correcting and encoding circuit 4 are written in a memory by a write clock signal corresponding to the processing speed and then read out therefrom by a read clock signal corresponding to the recording rate. The 2-channel digital video signals derived from the time base expanding circuit 5 are alternately supplied to recording amplifiers 6A, 6B and 6C, 6D at every 1/5 field (or at every 1/6 field). The respective outputs from the recording amplifiers 6A, 6B and 6C, 6D are respectively supplied to the recording rotary magnetic heads H A , H B and H C , H D and thereby recorded on the magnetic tape TP so as to form slant tracks. A reproducing system of the prior art digital VTR will be described with reference to Fig. 3. The digital video signals reproduced from the magnetic tape TP by the reproducing rotary magnetic heads H A ' to H D ' are respectively supplied through playback amplifiers 7A, 7B, 7C and 7D to playback processors 8A, 8B, 8C and 8D each having a PLL and a bit synchronizing circuit. In these playback processors 8A to 8D, the reproduced digital video signals from the respective amplifiers 7A to 7D are supplied to the PLLs and thereby the clock signals are detected. By these clock signals, the respective digital video signals supplied to the bit synchronizing circuits are synchronized. Further, the playback processors 8A to 8D include extracting circuits for extracting block synchronizing signals from the synchronized digital video signals on the basis of the output signals from the bit synchronizing circuits and the PLLs. The outputs from the playback processors 8A to 8D are supplied to a time base corrector 9 in which they are time-base-compressed. In this time base corrector 9, the outputs from the playback processors 8A to 8D are written in a memory by a write clock signal corresponding to a recording rate and then read out therefrom by a read clock signal corresponding to the processing speed to thereby time-base-compress the same. The time-base-compressed 2-channel digital video signals derived from the time base corrector 9 are supplied through a synchronizing detector circuit 10 to an address reproducing circuit 11. The 2-channel digital video signals derived from the address reproducing circuit 11 are supplied to an error correcting decoder 12 in which they are error-corrected and then supplied to and written in a frame memory 13. The 2-channel digital video signals read out from the memory 13 are supplied to a de-shuffle circuit 14. In the de-shuffle circuit 14, the 2-channel digital video signals from the memory 13 are written by a write clock signal based on the write processing speed and de-shuffled and read out therefrom by a read clock signal corresponding to a read processing speed, so that even if the burst error occurs in the reproduced signal due to the dropout or the like, there is a small possibility that errors will occur together on the picture. The 2-channel digital video signals from the de-shuffle circuit 14 are supplied to a de-multiplexer 15 in which they are decoded to 3-channel digital component video signals. Thereafter, they are fed to an error concealing circuit 16 and thereby error-concealed. The 3-channel digital component video signals from the error concealing cirucit 16 are supplied to a D/A converter 17 in which they are D/A-converted and thereby developed as analog component video signals, that is, the luminance signal Y, the blue color difference signal B-Y and the red color difference signal R-Y. The method for error-concealing the digital video data in the prior art digital VTR will be described with reference to Figs. 4 to 9. Fig. 4 illustrates a desired picture element e on a desired scanning line L n on the video screen of a television receiver and 8 adjacent picture elements a to d and f to i on the same scanning line L n adjacent the desired picture element and on the upper and lower scanning lines L n-1 and L n+1 . In this case, between two picture elements adjacent on the upper and lower scanning lines of the video screen, for example, picture elements a and d there is a time difference of one horizontal period (1H). When the data corresponding to the picture element e must be error-concealed, the data is interpolated by one of the data of picture elements adjacent to the picture element e in the left and right hand sides (d, f), in the upper and lower sides (b, h), in the oblique directions (a, i; c, g), in the cross-form (b, d, f, h) and x-form (a, c, g, i) or is substituted with the data corresponding to any one of the ambient picture elements. A prior art error concealing apparatus will be described with reference to Fig. 5. In Fig. 5, reference numeral 20 designates an overall arrangement of a delay memory. Since 9 picture elements of square lattice extending to, for example, three scanning lines shown in Fig. 4 are to be processed, the full delay time of the delay memory 20 is set as 2H + 2T S where T S is the delay time for one picture element (sample unit) and H is the horizontal period. Reference numerals 21 to 28 designate individual delay elements, respectively and reference numeral 29 designates an error concealing circuit. A digital video data signal applied to an input terminal IN was already error-corrected. If the error of this digital video signal is beyond the error correction ability, such digital video data signal accompanying with an error flag is supplied to the first unit delay memory 21 and also branched to and supplied to the error concealing circuit 29. The output from the first unit delay memory 21 is supplied to the second unit delay memory 22 and also branched to and supplied to the error concealing circuit 29. Reference numeral 23 designates a main delay memory and the delay time thereof is selected to be equal to a time difference (1H - 2T S ) between the picture element f on the right-hand side of one scanning line L n and the picture element g at the left-hand side of the succeeding scanning line of the square lattice shown in Fig. 4. The output from the second unit delay memory 22 is supplied to the main delay memory 23 and also branched to and fed to the error concealing circuit 29. The delay memories 24 to 26 have the delay times same as those of the above mentioned delay memories 21 to 23. The output from the first main memory 23 is sequentially supplied through the third and fourth unit delay memories 24 and 25 to the second main memory 26 and the outputs from the respective delay memories 24 to 26 are also branched to and then fed to the error concealing circuit 29. Reference numerals 21 and 28 designate fifth and sixth unit delay memories. The output from the second main delay memory 26 is sequentially supplied to both the unit delay memories 27 and 28 and the outputs from both the unit delay memories 27 and 28 are supplied to the error concealing circuit 29. The error concealing circuit 29 uses the respective digital video data derived from the delay memory 20 to carry out concealing processings, such as, determining the optimum interpolation direction and so on. The digital video data error-concealed therein is led out at an output terminal OUT. When the input digital video data does not require the error-concealment, the input digital video data is merely passed through the error concealing circuit 29 and then developed at the output terminal OUT as it is. At the center of the delay memory 20, or the connection point between the third and fourth unit delay memories 24 and 25 or at time point t₀ in which a data e ○ corresponding to the central picture element e of the square lattice shown in Fig. 4 exists, data at the input and output terminals of the delay memory 20 and at the respective branching Points thereof become i ○ to a ○ corresponding to the respective picture elements i to a in the direction from the input terminal to the output terminal. Fig. 6 illustrates patterns of the recording tracks formed on the magnetic tape TP by the afore mentioned digital VTR, in which A, B, C and D respectively designate slant tracks recorded by the recording rotary magnetic heads H A , H B , H C and H D which are sequentially suffixed as 0, 1, 2, .... Reference A', B', C' and D' respectively designate tracing tracks in a case where the magnetic tape TP is transported at the constant and same speed as that of the recording mode and the respective tracks are traced by the corresponding reproducing rotary magnetic heads H A ', H B ', H C ' and H D ' to thereby reproduce the recorded signals. These references A', B', C' and D' are suffixed as 0, 1, 2, .... In this case, since these tracing tracks are substantially completely coincident with the recording tracks, the amplitudes of the envelopes of the respective reproduced high frequency signals are made substantially constant on the whole of each tracing track by the respective reproducing rotary magnetic heads H A ' to H D '. Since as earlier noted the dig tal VTR carries out the shuffling operation upon recording, it is rare that errors will occur together on the video screen upon playback mode with constant tape speed. Accordingly, even if the error occurs in the data corresponding to the picture element e in Fig. 4, the data corresponding to the nearby picture elements a to d and f to i can be used for the error concealing processing in their original conditions. However, when the magnetic tape TP similarly to Fig. 6 is transported at high speed, for example, at a tape transport speed three times the transport speed of the recording mode, the patterns of the tracks A₁', B₁', C₁', D₁', A₂', B₂', ... traced by the reproducing rotary magnetic heads H A ' to H D ' become as shown in Fig. 7. Since the respective magnetic heads alternately intersect the recording tracks having different recording azimuths a large number of times, the envelope at every track of each reproduced high frequency signal by the reproducing rotary magnetic heads H A ' to H D ' becomes a waveform in which a lozenge is repeatedly formed as shown in Fig. 8. Since such reproduced high frequency signal can be used only in its portion (the hatched area in Fig. 8) where the amplitude thereof is higher than a predetermined value, the desired reproduced data can not be obtained. Accordingly, an error occurs in a data near a data to be concealed a reproduced data can not be obtained and so on, so that the error concealment using the nearby data can not be made. In this case, the quality of the reproduced picture is deteriorated. Although as shown in Fig. 9 it may be considered that the sampling range of the concealing data is enlarged, this urges the circuit scale to be increased considerably and is neither economical nor the realities. Fig. 9 illustrates a desired picture element e on a desired scanning line L n and 24 adjacent picture elements a to d , f to i and j to y on the same scanning line L n and upper and lower two of scanning lines L n-2, L n-1 ; L n+1 , L n+2 of the video screen of the television receiver. In this case, however, let it be assumed that data corresponding to the picture elements a to i be erroneous and that data corresponding to the remaining picture elements be correct. By the interpolation or delay by using the data of the picture elements selected from the 24 picture elements, the data corresponding to the picture element e is error-concealed. In view of such aspects, an object of this invention is to provide an error concealing system for digital data by which in a reproducing system having a relatively high error rate, the concealing processing can be carried out by using an error concealing data of small scale and which is particularly useful in a digital video device. DISCLOSURE OF INVENTION In order to achieve the above mentioned object, the present invention is to provide an apparatus for concealing errors comprising the features of claim 1. Specific embodiments are described in the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1, 2 and 3 are respectively a locational representation of a tape guide drum and rotary magnetic heads, a block diagram of a recording system and a block diagram of a reproducing system of an example of a digital VTR to which the present invention is applied with good effect, Figs. 4, 9, 11 and 13 are diagrams useful for explaining the present invention, Fig. 5 is a block diagram showing a prior art error concealing circuit, Figs. 6 and 7 are respectively pattern diagrams showing track patterns of a magnetic tape, Fig. 8 is a waveform diagram showing an envelope of a reproduced high frequency signal, Fig. 10 is a block diagram showing an example of an error concealing apparatus to which the present invention is applied and Fig. 12 is a block diagram showing another example of the error concealing apparatus to which the present invention is applied. BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of an error concealing system for digital data according to the present invention will hereinafter be described with reference to Figs. 10 and 11. Fig. 10 shows an arrangement of an example of an error concealing apparatus to which the present invention is applied. In Fig. 10, like parts corresponding to those of Fig. 5 are marked with the same references and the overlapped explanation therefor will be omitted. In Fig. 10, reference numeral 30 designates an overall arrangement of a delay memory. The total delay time of this delay memory 30 is determined as 2H + 2T S same as that of the delay memory 20 shown in Fig. 5. Reference numerals 31 and 32 respectively designate a compensation delay memory and a main delay memory. The compensation delay memory 31 is supplied with the output from the fourth unit delay memory 25 and the output from the main delay memory 32 is supplied to the fifth unit delay memory 27. A multiplexer 33 is interposed between the compensation delay memory 31 and the main delay memory 32. Reference numeral 34 designates an error concealing circuit and, the output and a control signal s ○ from the error concealing circuit 34 are supplied to the multiplexer 33. Since the error concealing circuit 34 has a delay time T p between its input and output, the delay time of the compensation delay memory 31 is selected to be T P - T S and in correspondence therewith, the delay time of the main memory 32 is determined to be 1H - T S - T P . The operation of the error concealing apparatus of Fig. 10 is as follows. In a rectangular lattice shown in Fig. 11A, let it be assumed that data corresponding to the picture elements a to c on the scanning line L n-1 be correct and that other data corresponding to the picture elements d to ℓ on the other scanning lines L n to L n+2 be all erroneous. In this case, although in the prior art error concealing apparatus shown in Fig. 5 the data corresponding to the picture elements d to f on the scanning line L n can be concealed by using the correct data corresponding to the picture elements a to c on the scanning line L n-1 , the data corresponding to the picture element h on the scanning line L n+1 can not be concealed because all the data surrounding such data are all erroneous. However, in the error concealing apparatus shown in Fig. 10, since the main delay memory 32 is provided at its input side with the multiplexer 33, the erroneous data (e ○ in the illustrated state) is error-concealed by the error concealing circuit 34 and, the error-concealed data and an error flag whose presentation is switched from "erroneous" to "correct" in response to such data concealment are supplied to the multiplexer 33. At that time, the multiplexer 33 is switched by the control signal s ○ derived from the concealing circuit 34 such that it transmits the concealed data. As described above, the concealed data on the scanning line L n is fed back to the main delay memory 32 and both the unit delay memories 27 and 28. Then, the respective data in the delay memory 30 are moved from the illustrated state after one horizontal period to the state where the erroneous data h ○ can be concealed since there are error-concealed data d ○ ', e ○ ', f ○ ' on the scanning line L n and erroneous data g ○ to ℓ ○ on the scanning lines L n+1 and L n+2 as shown in Fig. 11B. As described above, in this error concealing apparatus, since the concealed data is fed back to the delay memory, the erroneous data can sequentially be concealed by using the correct data of small scale. Thus, even when the error rate is relatively high such as when the digital VTR is in the playback mode at a high speed, it is possible to carry out the error concealment with ease. While in the above the playback mode at high tape speed is described, this is also true for the playback mode at low tape speed. Another example of the error concealing apparatus to which the present invention is applied will be described with reference to Figs. 12 and 13. Fig. 12 shows an arrangement of another example of the error concealing apparatus. In Fig. 12, like parts corresponding to those of Figs. 5 and 10 are marked with the same references and overlapped explanation will be omitted. In Fig. 12, reference numerals 20A and 20B respectively designate rear field and front field line delay memories. Both the line delay memories 20A and 20B are exactly the same in arrangement as the delay memory 20 shown in Fig. 5. Reference numerals 41 and 42 designate field delay memories for the rear and main fields, respectively. The field delay memories 41 and 42 are both supplied with the outputs from the rear field and main field line delay memories 20A and 20B. The delay times of both the field delay memories 41 and 42 are selected to be both (1V - 2H + 2T S ). The outputs therefrom are supplied to the main field and front field line delay memories 30 and 20B. Reference numeral 43 designates an error concealing circuit. To the error concealing circuit 43, there are supplied the branched outputs from the front field, rear field and main field line delay memories 20A, 20B and 30, that is, data a+₁ to i+₁ from the rear field, data a₋₁ to i₋₁ from the main field and data a₋₁ to i₋₁ from the front field. Further, from the error concealing circuit 43, the output and the control signal s ○ thereof are supplied to the multiplexer 33 provided in the main field line delay memory 30, similarly to the embodiment of Fig. 10. Fig. 13 shows a relationship amongst the data of the respective fields. From this, it will be apparent that the apparatus of Fig. 12 is used in such a case that the present invention is applied to three dimensions containing the time base. Accordingly, from the explanation given on the embodiment of Fig. 10, it can easily be understood that the data, which is concealed by using the correct data of the preceding field, is fed back to the delay memory and the erroneous data at the succeeding field can be sequentially concealed. While in the apparatus of Fig. 12 the data of a certain field and the fields before and after such field, i.e., totally 3 fields are used for error concealment, instead of 3-field data, 3-frame data can be used. According to the present invention as described above in detail, since the concealed data is fed back to the delay memory and is used as the correct data for the error concealment, the erroneous data can sequentially be concealed by the correct data of small scale. Consequently, when the present invention is applied to the digital VTR, even upon playback mode at variable tape speeds, it is possible to improve the quality of the picture by using the circuit arrangement of a small scale.

Claims: An apparatus for concealing errors in a digital video signal, said apparatus comprising a delay memory circuit (30) including pairs of delay elements (21, 22; 24, 25; 27, 28) connected in series and main delay memories (23, 32) interposed between said pairs of delay elements, the input and the output of each delay element being branched to an error concealing circuit (29) providing error-concealed data at its output, wherein said delay memory circuit (30) includes a compensation delay memory (31) followed by multiplexer (33), and the output of the error concealing circuit is connected to one of the input terminals of said multiplexer for feeding back error-concealed data that was previously error-concealed to conceal errors in data subsequent to said previously error-concealed data. The apparatus of claim 1, characterized in that the compensation delay memory (31) is connected to the output of the second pair (24, 25) of delay elements and the output of said multiplexer (33) is connected to the input of the second main delay memory (32). The apparatus of claim 2, characterized in that the delay times of said delay elements (21, 22; 24, 25; 27, 28), said main delay memories (23, 32) and said compensation delay memory (31) are selected such that the delay time of the delay elements is substantially equal to the delay time T S for one picture element, the delay time of the first main delay memory (23) is substantially equal to (1H-2T S ), wherein H is the horizontal period, the delay time of the compensation delay memory substantially equals (T P -T S ), wherein T P is the delay time of the error concealing circuit (34), and the delay time of the second main delay memory (32) is substantially equal to (1H-T S -T P ). An apparatus for concealing errors in a digital video signal, said apparatus comprising a first delay memory circuit (20A) including a first (21, 22), a second (24, 25) and a third (27, 28) pair of delay elements, and a first main delay memory (23) interposed between said first pair (21, 22) and said second pair (24, 25) of delay elements and a second main delay memory (26) interposed between said second pair of delay elements (24, 25) and said third pair of delay elements (27, 28), a compensation delay memory circuit (30) including a first (21, 22), a second (24, 25) and a third (27, 28) pair of delay elements, a main delay memory (23) being interposed between said first and said second pair of delay elements, a compensation delay memory (31), a multiplexer (33) and a second main delay memory (32) connected in series and interposed between said second and said third pair of delay elements, and a second delay memory circuit (20B) identical with said first delay memory circuit (20A) and connected after the compensation delay memory circuit (30), wherein the input and the output of each of said delay elements is branched to an error concealing circuit (43), the output of the error concealing circuit (43) is connected to one of the input terminals of said multiplexer (33) for feeding back error-concealed data that was previously error-concealed to conceal errors in data subsequent to said previously error-concealed data, and wherein a first field delay memory (41) is interposed between the output of the first delay memory circuit (20A) and the input of the compensation delay memory circuit (30), and a second field delay memory (42) is interposed between the output of said compensation delay memory circuit (30) and the input of the second delay memory circuit (20B). The apparatus of claim 4, characterized in that the delay times of the field delay memories (41 and 42) are selected to be both (1V-2H+2T S ), wherein V is the field period.

Inventors: SUMA, TETSURO SONY CORPORATION
Applicants: SONY CORPORATION
Application year: 1985
Main classification: G11B20
IPC codes: H04N5, H04N9, H04B14, G11B20