INTELLIGENT PROCESSOR/MEMORY ELEMENTS AND SYSTEMS

Abstract: The invention relates to an elementary component of an Intelligent Computing System. Its all basic functions - the basic operation, the system logic and the storage of information - are carried out by the elementary component which is universal in the sense of system independence and has Q stable states. In the basic operaton the Q states represent the Q-nary alphabet of the operational code. In the evaluation of Q-nary logical propositions, where K≧Q, these Q states represent Q truth values as pure complementary values, while coherent superpositions of them represent the rest (K-Q) truth values. The results of basic and logical operations are stored distributively in a system of elemen­ tary components that occupy one of Q states, where in coherent superposition cases one of them is chosen probabilistically. A Q-­ nary logical relaxation can be attained by restricting to Q out of K balanced truth values. An elementary component of the invention is used in advantage to a finite network of identical elementary components for storage and/or processing of information in numerical (K=Q) and/or symbolic (K>Q) forms. A Möbius topolo­ gical type network of a system of the invention appears to be an optimal interconnection network which performs a minimal amount of processing at each step of the execution, sequentially or in parallel, carries out minimal-switch routing and provides a degree of reliability that increases with an increasing number of elementary components. Moreover, storage and processing of information by such a system can be selfprotected to a high degree against natural or artificial disturbances. Together with the controlable memory structure it provides a comprehensive specification of an Intelligent Computing System, which complies with certain criteria of intelligence.

Description: The invention relates to an elementary component of a system for storage and/or processing of information in numerical and/or symbolic forms comprising n positions and a plurality of inputs for common control of and energy supply to said positions, wherein each position comprises a channel input for a Knary code flow where K > 2, a Binary memory element, where tt2 and KLQ, a channel output for a K-nary code flow, a first K-nary logic switch means having its input connected to said channel input and its output to an input of said Q-nary memory element, and a second K-nary logic switch means having an input connected to an output of said Q-nary memory element and an output connected to said channel output. A similar elementary component is known in the art as a storage means for operations in a processor to store a byte of binary information. An operation on a thus stored byte is executed by superposing a subsequent byte for example, whereby the present states of the binary memory elements are updated in accordance with the rules of an addition modulo 2. It is an object of the present invention to provide an elementary component that is universal in the sense of system independence. It is a further object of the present invention to extend the functional capacity of the elementary component. It is also an object of the invention to provide in addition to its storage function an elementary component with a processing function which are unified in terms of space and code whereby the present states of the Binary memory elements are updated in accordance with the rules of an unitary operator of multiplicative type. It is another object of the invention to provide a system for storage and/or processing of information in numerical and/or symbolic forms comprising laterconnected and cooperating elementary components of the invention to unify both a storage function and a processing function of a system. It is a further object of the invention to provide a self-controlled system of storage and/or processing of information in numerical and/or symbolic forms by avoiding memory and/or time conflicts. It is also an object of the invention to provide a system having a specially distributed I/O function in T channels, where T > 1. It is still another object of the invention to enable the system to perform sequential or parallel processing of information in accordance with the type of program to be executed. It is a further object of the invention to provide a system for an optimal realization of an interconnection network which performs a minimal amount of processing at each step of execution and carries out minimal-switch routing. It is still another object of the invention to provide a system which can detect its own state, i.e., can be triggered to process the existing state of the memory withput any input simply by uniform impulse, meaning that the system has an intelligence in a sense of the autodetection criterion. It is still another object of the invention to provide a system for realization of an interconnection network with a Sobius type of topology, meaning that the system has an intelligence in a sense of realizing the Principle of Nature Parallellism. According to the invention the elementary component as defined above is characterized in that by ability to conserve a unit of information in the short-term (S-) mode and/or in the long-term (G) mode, where the said S-mode conserving a unit of information in the form of a n-codeword ak and the said Lrsode conserving the same unit of information in the form of the complementary n-code word k, where ak and ak belong to the same [ m1, m2 ..., mit ..., m#1)-out-of-n ] code and mi being the number of the position occupied by the i-th character of a Binary alphabeth, where misn/Q, wherein the said second K-nary logic-switch means comprises W feedback inputs, where W = K-Q, for connection to the outputs of the binary memory elements at the corresponding positions in W subsequent elementary components, wherein a unified processor-memory functioning is defined by successive processes of absorption and emission, the said first K-nary logic switch means evaluating a K-nary code information unit from the said input channel and causing a K-nary logical proposition comprising the evaluated K-nary code information unit and the state of the assiciated Q-nary memory element at corresponding position to select a unique state of the associated binary memory element at corresponding position according to a logical table 'absorption', the said second K-nary logic switch means assigning a unique K-nary code information unit for the said output channel according to the logical table 'emission' with respect to the state and to the memory mode of the associated Binary memory element at corresponding position and W states of feedback output from Binary memory elements at corresponding positions in W subsequent elementary components, wherein if at some position channel input is lacking this can be considered as a special input value, wherein the said feedback inputs insure preservation of a said [ (ml, m2, ..., mi, ..., m0-1)-out-of-n ] code for n-codewords presented in parallel, wherein the elementary component can be controlled by changing two from three processing modes by a first common control signal, namely from a 'passive' processing mode to a 'stand-by' processing mode and from a 'standby' processing mode to a 'passive' processing mode, wherein said modes being a 'passive' processing mode preserving the actual state of each element, and a 'stand-by' processing mode enabling to perform the processing function by a transition from the 'stand-by' processing mode to the 'active' processing mode as a result of absorption, and by a transition from the 'active' processing mode to the 'stand-by' processing mode to perform the processing and the storage functions if in L-mode and the storage function only if in S-mode as a result of emission, said 'passive' processing mode enabling free passage of Knary information units from the said input channel and of W feedback outputs from binary memory elements at corresponding position in W subsequent elementary components from the said output channel along the first K-nary logic switch means, the Q-nary memory element and the second K-nary logic switch means, as an operational selection option or as a reliablity precaution measure, wherein the same first common control signal controls by means of a variable R the conversion of the said memory modes from S- to L-, frequency selective, the second common control signal controls by means of a variable F(q) conversions of the said memory modes from S- to L, and from L- to S-, selectively in accordance with address and/or current processing mode, wherein as a consequence of the said processor-memory unification the K-nary logic over a binary alphabet or (K over Q)-logic being defined by: 1. K truth values and 2. the storage of the result of the evaluation of a K-nary logical proposition in a Q-nary form according to a probabilistic rule, wherein a Q-nary logical relaxation can be attained by restricting to Q out of K balanced truth values. An elementary component of the invention is used in advantage to a finite network of identical elementary components for storage and/or processing of information in numerical (K=Q) and/or symbolic (K > Q) forms. According to the invention a network of elementary components represented by an (NxH)-matrix Aij (N < M), where aij an elementary component, is characterized by the following rule of transition of information EMI4.1 where the operations j and 4 being defined as an operation addition modulo N or M, respectively, for i = 0, N-l and j I 0, Marl. A network implementing transition according to such rule provides an optimal trajectory in the sense that neither queuing nor conflicts occur along such a trajectory, which goes through all elementary components, sequentially or in parallel, without reiteration and the process returns to the starting position. A network as defined above represents a particular architecture of the system, i.e., a Möbius type of topology, which provides the possibility of realization the Principle of Natural Parallelism. In particular the 'passive' processing mode of elementary components is used for continuation of the storage and/or of the processing functions of the system once an elementary component is down as a result of failure. That is a system consisting of elementary components of the invention features a degree of reliability increasing with an increasing number of components. In a system of the invention T optimal parallel trajectories can be realized, where T is the greatest common factor of a given pair N, M. If M is increased while N is held fixed, the values of T vary periodically, with a period equal to N, between 1 and N through all common factors. Thus it is possible for any N to define some Mo such that: a. if M = Mg, , then T = N, i.e., parallel trajectories; b. if M = Mo + 1, then T = 1, i.e., a sequential trajectory. Thus a system of the invention appears to be an optimal realization of an interconnection network which performs a minimal amount of processing at each step of the execution, sequentially or in parallel, and carries out minimalswitch routing with the options of identifying Input/Output with any elementary component (if T = 1) or with any column (if T > 1) of matrix Aij. The system of the invention is in compliance with the non-linear criterion of an intelligent computing system, the autodetection criterion, which is formulated as the ability of a system to detect or measure the interaction of a system with itself, thus decoupling itself from the environment. In the following the basis of the subject matter of the invention will be described as the '3 over 2' model [A. Stern and V. Stern, 1984]. In this description an elementary component is referred to as a pnM-cell and a system consisting of PnM-cells as a PnM-medium. In addition, a description is given of an embodiment of a pnM-cell and of a embodiment of a pnM-medium as PnMnetwork. The description refers to a drawing: Figure 1 represents the system of 2 interconnected PnM-cells; Figure 2 is a diagram showing life history of a PflN-cell with respect to memory and processing modes; Figure 3 represents an oriented Dedekind structure; Figure 4 is a representation of a pnM-network; Figure 5 shows in graphic form levels of memorization, which represent the controlled memory structure of the PnM-medium; Figure 6 shows in schematic form an embodiment of a PnM-cell of the invention; Figure 7 shows in schematic form an embodiment of a PnM-network of the invention; Figure 8 depicts an illustrative logic circuit for implementing the embodiment of Figure 6. Figure 9 shows a block diagram of PnM-cell interconnections as illustration of the embodiment of figure 1. Figure 10 depicts a logic circuit implementation of the memory mode conversion control. THE 3 OVER 2 MODEL The basic principles of Intelligent Computing Systems are formulated as: 1. Distributivity and Sobius topological closure; 2. Inseparability of the memory cell from the processing operator; 3. Complementarity of memory modes. The point of view taken is that, starting only from the principle of the inseparability of the memory cell from the processing operator, which is taken to be a necessary condition for the system to be intelligent, in some sense, we can define the basic functions of a computing system - the basic operation, the system logic and the storage of information. All three are carried out by the universal elementary component which has two stable states. In the basic operation the two states represent the binary alphabet of the operational code. In the evaluation of ternary logical propositions, as functions with variables the values of which form a continuum on the boolean interval [ 0, 1 ] , these two states represent "false" and "true", as pure complementary values, while a coherent superposition of them represents "undetermined". The results of basic and logical operations are stored distributively in a system of elementary components that occupy one of two states, where in the "undetermined" case one of them is chosen probabilistically. A Sobius topological type network appears to be an optimal realization of an interconnection network which performs a minimal amount of processing at each step of the execution, sequentially or in parallel, carries out minimal-switch routing and provides a degree of reliability that increases with an increasing number of elementary components. Together with the controllable memory structure it ensures the satisfaction of sufficient conditions for the system to be intelligent, as: 1. Autodetection criterion and 2. The Natural Parallelism. We believe that the chief value of the resulting specification of the system as a Basic Machine would be not only substantial advance in computational power and technical characteristics, but the formation of the basis for the generation of an Intelligent Computing System. 1. Introduction The overall speed of processing and the storage capacity of information has increased by several orders of magnitude over the past decades, primarily because of revolutionary developments in hardware technology. The resulting high level of performance has extended the solvability of computational problems, but as far as software is concerned progress has been much less striking. It has become apparent that any further substantial increase in computational power can be achieved only by fundamental developments in system architecture and system logic. The present state of the art has stimulated attention towards the use of parallelism in the interconnection of processing and memory units into a system in which the soft/hardware distinction becomes vague [E. Dijkstra, 1968]. As a result, a number of different architectures for parallel computing systems have emerged with different advantages and limitations. All of them are based on some concept of how computation is to proceed and how components are to interact. Our main concept is the Principle of Natural Parallelism, which is formulated as follows: Any real process can be described as a system of cooperating and communicating processes which occur simultaneously in some space. This space need not necessarily be continuous and infinite; it can be discrete and finite, but some notion of a direct neighbourhood of each element is indispensable. The real and not so trivial problem consists of how to formulate this concept constructively, as a computing system of universal form, so that any phenomenon which is of interest can be inserted into it as an information-processing model. This way of formulating the problem has many attractive possibilities, but also indicates some new obstacles. It implies the need to develop a system of concepts in which any natural interaction can be described as information processing in a distributed computing medium and vice-versa, i.e., an interacting element of a space is regarded as a universal microcell-multipolar which performs information processing [A. Ershov, 1969]. Evidently, if a sufficient supply of computational power is available - so that each element of the space corresponds to a separate element of the computing medium - then control and realization of a computational process are simplified to the tuning and triggering of the corresponding medium. Since the medium reproduces a described phenomenon "one to one" there is no need at all for any processing organization. If the process under consideration consists of even only one element more than the available number of elements of the medium, then complicated problems arise, related to the taking into account of boundary effects and the dynamic retuning of the medium. The constructive resolution of these problems would lead to a successful embodiment of the very promising properties of Natural Parallelism. 2. The Model Description Following the formalism of Programming Theory we introduce the concept of the program as a set of information-operational objects. Let us state a universal algorithm. The process which is realized by applying it to a program is termed the execution of the program. Execution of the program can be seen as a process which flows through time and can be represented as a finite sequence of information-processing steps, taking place instantaneously at successive, discrete intervals of time. There always exists a conclusive event, the occurrence of which signifies that execution of the program is finished and makes it possible to declare some object to be the result of the execution. With any particular program, therefore, we can associate a function which is computed or realized by the program. The arguments of this function are the input data of the program, and the value of the function for given arguments is the result of the program with the corresponding input data. Conceptually, execution of the program consists of two main parts: informational and operational; i.e., it can be broken down into processing units which act on units of information. Suppose that there exists a structure which defines a system of control and information relations between these two classes of objects: the processing units, operators, which are applied selectively to the units of information, memory cells. If such a structure can guarantee execution of a certain class of programs, then we term it a computing system or medium. 2.1. The Processor-Memory cell. Let us introduce a computing medium as a homogeneous, in some sense, discrete and finite space A, to each element of which there corresponds an elementary cell ajj (i = O, N-l; j = O, N-i), connected into an interconnection network. We assign to the elementary cell the following dual function: I Informational - the conservation of some unit of information; II Operational - the performance of some unit of action in the processing of the conserved unit of information. This dual functioning expresses a basic principle of such a computing medium the principle of the inseparability of an elementary memory cell from an elementary processing operator. Supposing that such an elementary cell is universal in the sense of system independence, we call it the ProcessornMemory (pnM-)cell and refer to such a computing medium as a PflM-medium, where sign n is used to underline the unification of the abovementioned dual functioning. The information property of the PnM-cell aij consists in the ability to conserve a unit of information ij on the address ajj in the form of an n-word ak ' (awl, a2, ..., an) in some block code over the alphabet F = (0, 1), which represents the unit of information introduced above. Consider in the set of codewords G = {ak} the complementary element ak to each element ak. We can define two memory modes of the PnM-cell as follows: 1. Short-term (S-)mode - the unit of information ij is conserved in the form of the n-codeword ak; 2. Long-term (L-)mode - the unit of information aij is conserved in the form of the n-codeword ak. Those two modes are convertible as follows: - a. from S- to L-mode by internal or external means; - b. from L, to S-mode by external means only. Let us define on the set G the binary operations (V and A) which represent the unit of processing introduced above, such that any program of a set P can be represented as a finite associative sequence of such operations. We shall refer to those operations as the basic operation. Then a PnM-cell can be considered to be an n-polar with the following operational properties: 1. Reception of the n-codeword Y from communication channel; 2. Execution of the basic operation V over the conserved n-codeword X and the received n-codeword Y; 3. Depending on the memory mode: - a. if in the S-mode, then the storage in itself of the result of the basic operation V in the form of the n-codeword ZS; - b. if in the L-mode, then the execution of the basic operation A over the obtained n-codeword ZS and the conserved n-codeword X, and the maintenance of the conserved n-codeword X; 4. Transmission into the communication channel of the n-codeword ZS or ZL, where ZS and ZL are results of the basic operations with respect to the S- or the L-memory mode, respectively, and X, Y, ZS and ZL E G. It seems logical to assume that the PflN-cell with these operational properties processes and conserves the information in a single code. Such a universal operational code should, if possible, possess the following properties: be convenient for performing the basic operations and be optimal for conservation of information. If we suppose that the communication channel is an error-protected one, then an attractive candidate for the universal operational code is an arithmetic code with constant weight m, i.e., a (m-out-of-n)code. The power of the set G in this case would be: EMI10.1 The density of conservation of information for a given n is maximum if the code weight m is equal to half of the length of an n-codeword, since EMI10.2 where n is even. (2.2) Let the basic operations (V and A) be positional operations such as XVY - ZSs with ZS f (fl(xl, y1), f2(x2,y2), .., fn(xn,yn)) (2.3) z5AX P ZL, with ZL = (#Ú(x1, y1), #ê(x2, Y2), ..., #n(xn, Yn)) where: fi, fi - switching functions on the i-th position. The switching functions fi and fi may be defined in terms of carrier-switches and by assigning to them the ability to perform the following functions: - to carry the n-codeword Y P (y1, Y2, ..., y11) in the form of an information n-package through the communication channel; - to realize the positional switching functions fi(xi, Yi) and (i - l, ..., n), where X = (xl, x2, ..., xn) is the n-codeword conserved in pnM-cell. In this case the operational properties of the PnM-cell can be considered as successive processes of absorption and emission of an information package which consists of n carrier-switches. Let us introduce 3 types of carrierswitches: A, B and C, together with rules for their absorption and emission, as follows: - absorption (emission) of carrier-switch type A leaves the position unmodified; - absorption (emission) of carrier-switch type B modifies the position to "O" (to "1"); - absorption (emission) of carrier-switch type C modifies the position to "1" (to "0"). Then rules for emission only, subject to the condition that the memory be preserved, can be formulated as follows: - a position associated with the value 0 can emit carrier-switches type A or C only; - a position associated with the value 1 can emit carrier-switches type A or B only. We now consider a system of two PnM-cells A0 and A1, connected by a communication channel, in which are stored the n-codewords ao and al, respectively. Evidently, from the rules of emission formulated above, the n-package ssO, which corresponds to the n-codeword A0 and is emitted by the PflM-cell A0, can have maximum No = 2n different combinations of carrier-switches. The Pfl#cell A1 can absorb only those n-packages which switch the n-codeword a1 stored in it into a resulting n-codeword ssl = a1 * ss0 in the same code, where * means the basic operations in general, i.e., there are only N# < No possibilities. 0 In this case absorption of the n-package ss0 by the PflM-cell A1 can be guaranteed only by imposing, via feedback, some regulating condition, on the emission of the n-package ssO by the PnM-cell Ag. Such an operational condition can be described functionally as a relation between the composition of the information n-package ssk and the information stored in the PnM-cells Ak and Ak+l at the moment of completion of the absorption of the information n-package ssk-l (Figure 1). We can formulate this as a law of preservation of the code, as follows Ck =D&gamma;(&alpha;k+1, k) where: Ck (k1j,k2j, ..., k##) - the composition of the k-th information n package, kij(j = 1,3) - the carrier-switch of the j-th type in the i-th position, D&gamma;(&alpha;k+l, k) - the operational difference between the n-codewords ak and ak+l in canonical representations [W. Peterson and E. Weldon, 1972]: EMI12.1 where dyj E (0, -1, 1) - the balanced ternary digit and the index y (y=1,4) expresses the dependence on the memory mode combinations for a pair of PnM- cells A0 and A1 such as (S,S), (S,L), (L,S) and (L,L). If the values of dyj are assigned as some kind of information charges to the carrier-switches A, B and C, respectively, such a relationship becomes evident. The introduction of such operational properties leads us to the concept of the processing mode of the pnM-cell. Let each PnM-cell be in one of three processing modes: "passive", "stand-by", "active". We denote the processing modes of a pnM-cell by a superscript l l = 0, 1, 2) and define them by the rules of transition from one mode to another as follows: ai; + a#+1, for l = 0, 1 ij ij t t-1 aij aij , for l s 1, 2 These definitions of the processing modes and the rules of transition allow us to formulate the operational properties of a PnMrcell with respect to the execution of a program: - if aij0 + aij1, then the P@M-cell is inserted into the program; - if aij1 + aij0, then the P@M-cell is removed from the program; - if aij ai; then the PnM-cell processes information in accordance with the basic operation V; - if aij2 + aij1, then the P@M-cell: a. if in the S-mode, stores the result of the basic operation V or b. if in the L-mode, processes information in accordance with the basic operation A and maintains the conserved information. The cyclical transition aij1 + aij2 + aij1 which corresponds to the processing- memorizing act, we term the triggering of a PnM-cell. Since only a "stand-by" PnM-cell can become "active", then in the P@M-medium two types of processing of information can be distinguished: - if a passive PnM-cell receives the n-codeword Bk, then it sends out the same n-codeword Bk+l = - if a stand-by PflM-cell receives the n-codeword ssks then it sends out the n-codeword ssk+l = &alpha;k+1 * ssks where ok+l is the conserved n codeword. In this respect, failure of a PnM-cell can be regarded as its being put irreversibly into the "passive" processing mode as a reliability precaution measure. Moreover, a degree of reliability increases with an increasing number of PflM-cells in the system. The conversion of the memory modes by internal means can be defined via processing modes as follows: - if a PflM-cell has been in "stand-by" and "active" processing modes for longer than some characteristic time AT, then it converts from the S mode to the L-mode, which is maintained until an external control signal is applied at time 1. The life history of a pnM-cell can be represented as a time diagram of memoryprocessing modes (Figure 2). The probability that a PnM-cell will convert from the S-mode to the L-mode in a time interval At can be expressed as follows: P(aij : S#L) = P(aij : S-L i ai1j2)P(aij2) = 3 [ p.At + o(#t) ] .R = [ ii.R + f(q) ] At where: = 1 - the conversion coefficient, #T R (O < R < 1) - the relative time in "stand-by" and "active" processing modes and f(q) - a term of second order in At, or higher. R and f(q) can be regarded as control variables, each with its own influence on the probability introduced above. 2.2. The System Logic. Since the PflM-cell is destined to be part of a computing medium, the system logic must be defined. The fact that we have introduced three types of carrier-switches as a consequence of the processor-memory unification, leads us to formulate the logic for the pnM-medium as a ternary logic over the binary alphabet or a (3 over 2)-logic with the following types of truth values: "undetermined", "false" and "true" assigned to carrier-switches A, B and C, respectively. In this respect each position of a pnM-cell can be seen as an oriented Dedekind structure on which this logic is built (Figure 3). The orthogonal-complementary relationships between elements of this structure comply with the dual functioning requirement of the universal elementary cell introduced above. Let us assign a non-integer value between 0 and 1 to "undetermined", as a coherent superposition of the boolean values 0 ("false) and 1 ("true") IG. Birkoff and J. von Neumann, 1936]. This provides a basis for formulating all necessary logical functions for the pnM-medium with variables the values of which form a continuum on the boolean interval [ 0,1 ] [ L.A. Zadeh, 1965]. The result of the evaluation of a ternary logical proposition is stored in binary form according to the following probabilistic rule: P(x) 1 1 1 (sgn(l - x))(2 - L) 2 (sgn(2- x))(## where L the value of the logical variable and x E F. By restricting a system to carrier-switches type B and C only or to 2 out of 3 balanced truth values, the binary logical relaxation can be attained with the feedback device become irrelevant. 2.3. The Interconnection Network Consider the execution of a program by a PnM-medium. In the initial state of the memory all PflM-cells are passive. In accordance with some particular program a subset Pi of the set P of pnM-cells is selected and inserted into the program by transition to the "stand-by" processing mode. The execution of the program is represented as a sequence consisting of triggering of the "stand-by" PflM-cells and passage through the "passive" PflM-cells of the set P. With such a sequence can be put in correspondence some information-logical trajectory in a space A. The existence of the "passive" pnM-cells leads to the appearance of certain degrees of freedom, i.e., for a given program Pi and for the same initial state of the memory, it is possible to realize some set of variants of the execution of the program by the PflM-medium or some set of trajectories in the space A. Evidently, the result of execution does not depend on which variant is realized, and the choice of an optimal trajectory, in some sense, can be defined by a topological structure of the space A only. Since any program P. E P consists of a finite associative sequence of basic operations, then an optimal trajectory would be one which goes through all the cells of the PnM-medium sequentially or in parallel without reiteration. Consider an (NxM)-matrix aij (N < M) which corresponds to a space A. Let us define on the sets of indices i, j (i P O, N-l; j 3 0, M-l) an operation addition modulo N or M, respectively, as P X# Y= Z x+Y where Z is a remainder of the quotient P, 0 < Z < P-l and P is equal to N or M. Let us define the concept of the direct neigbourhood of aij E A as follows: The direct neighbourhood of the element aij consists of the elements EMI15.1 Let us permit in the space A only those trajectories which consist of transitions following the rule: EMI15.2 so forbidding transitions in the two orthogonal directions such as: EMI15.3 The introduction of such a rule, governing the transition from one PnM-cell to another, as a step in the execution of a program fixes some interconnection network in the PnM-medium as a topological structure, in some sense, of the space A. Such a PnM-network can realize the optimal trajectory described above and may be considered as a special type of architecture. Grouptheoretical considerations imply that, depending on the values of N and M, a pnM-network can realize T optimal parallel trajectories, where T is the highest common factor of each given pair N, M. If M is increased while N is held fixed, the value of T varies periodically, with a period equal to N, between 1 and N through all common factors. Therefore it is possible for any N to define some MO so that: - a. if M = Mg, then T = N, i.e., parallel trajectories, - b. if M = Mo + 1, then T = 1, i.e., a sequential trajectory. This opens up the possibility of dynamic switching between sequential and parallel processing as an algorithmic flexibility option. The condition that a PnM-medium has a homogeneous network structure can be satisfied if in addition to the PnM-cells aij introduced above we admit the existence of two types of degenerate cells bi; and Ck;- Such b- and c-cells have the same fundamental nature as a-cells, but cannot conserve or process information. They are used (Figure 4): - a. cells bij - to prevent the routing of information in the two orthogonal directions; - b. cells ckj - to realize the dynamic switching between sequential and parallel processing (solid arrows represent sequential routing; dashed arrows represent parallel routing). By identifying the elements aij, bjj and Ck; of the first row (i,k=O) with those of the last row (i,k=N-i), and the elements aij, bjj of the first column (j=O) with those of the last column (j=N-i), we obtain a pnM-network with a Sobius type of topology [A. Stern, 1982 ] . The 2-dimensional cyclic shift interconnection pattern indicates that after N.M/K transitions from one PflN-cell to another the process returns to the starting position. It makes a pnM-netwOrk topologically and functionally equivalent to an iterated form of a Shuffle-Exchange interconnection network, with the possibility of identifying Input/Output with any element (if T=1), or any column (if T > 1), of the matrix ajj. This particular type of topology provides the possibility of constructing complicated 3-dimensional computing mediums consisting of multi-layered, equivalent, non-oriented topological structures with different functional assignments, which penetrate, are tangent to and bound one another. For processing purposes the PflM-network appears to be very powerful since it can be seen as an optimal realization of an interconnection network which performs a minimal amount of processing at each step of the execution of a program and carries out minimal-switch routing with no queuing or conflicts. 2.4. The Memory Structure The result of the execution of a program Pi e P is represented simultaneously by: 1. Short-(S-)form, i.e., K information n-packages and 2. Long-(L-)form, i.e., the final state of the memory. In the first case the result is output for immediate utilization; in the second it is conserved distributively over all PnM-cells of a set Pi. The number of PflN-cells that have converted from S-mode to L-mode during the execution of a program Pi, which corresponds to the degree of memorization, depends on the power of the set of PnM-cells inserted into the program, or in other words on the execution time relative to the characteristic time of conversion AT. If the execution time or the power of the set Pi is small, then the degree of memorization is also small, and the final state of the memory will be destroyed by the execution of a subsequent program. One way to memorize the result of the execution of a program of this sort is to repeat the execution until a sufficient degree of memorization has been attained. However, it would clearly be preferable to be able to control the desired level of memorization in the L-form relative to the execution time of the particular problem. In general, the process of L-form memorization can be described as a probabilistic death process as follows: H = HOe [ R+f(q) ] t where: H - the number of PnM-cells in the S-mode and Ho - the total number of pnM-cells in the computing medium. If we were to apply sinusoidal excitation in phase with the processing, the value of R would be 0.5 independent of the frequency. Let us call this a "working" memorization mode, which extends the average S-mode life-time as a simple realization of memory control. Together with the natural mode this mode clearly separates two possible regions of forced memorizing (Figure 5). The S-forced memorization could be achieved by varying the control variable R in a more complicated way than sinusoidally. The Forced memorization could be achieved by making the control variable f(q) dominate the process through some mechanism for internal triggering of the PnM-cell by an external signal, applied in accordance with the corresponding address or processing mode. Conversion from Lr to S-mode, which is equivalent to erasing the result of execution of some program, can be realized by the same external signal. By local application of Forced memorization or non-application of S-forced memorization, for example by frequency filtering, local memorization of the results of the execution of a certain class of programs could be achieved. 3. Intelligent Computing Systems The criteria for any system to be intelligent, in some sense, are usually stated in a framework either of projective or of attributive properties, or both. These approaches are basically linear and deal with the interaction of a system with the environment only. We have taken for the main criterion of intelligence the ability of a system to detect its own state - the autodetection criterion [A. Stern and V. Stern, 1973 ] . Such a clearly nonlinear approach directs attention to the unique property of intelligence, which is the detection or measuring of the interaction of a system with itself, thus decoupling itself from the environment. The pnM-network can be triggered to process the existing state of the memory without any input simply by a uniform impulse. This can be considered as the execution of a special type of program, the result of which is characteristic of the state of the system, so satisfying the autodetection criterion. This directly links the problem of intelligence with the fundamental physical problem of measurement. The advantages of parallelism in the interconnection of processing and memory units have become apparent. The principle of Natural Parallelism is very promising as a foundation for intelligent computing. Therefore the ability of the system to store and to process information in accordance with this principle can be considered as another criterion of intelligence. The functional properties of the PflM-cell and a Pafbius type of topology of the pnM-system provide the possibility of realizing the Principle of Natural Parallellism. Assuming that it satisfies the above criteria, the Intelligent Computing System is necessarily hardware oriented with numerical computation and symbolic manipulation being considered as complementary modes of Left-Right intelligent processing [ R.W. Sperry, 19611. The technological realization of the embodiment of the PflM-system can, as a consequence of its natural organisation, really promise miniaturization down to atomic-molecular level [A. Stern, 1982; R.G. Brewer and E.L. Hahn, 19841. Moreover, storage and processing of information by such a system will be selfprotected to a high degree against natural or artificial disturbances. The possibility of developing a molecular device computing system is proved to be feasable [ F.L. Carter, 1984 ] . The proposed PflM-system naturally fits for such realization and promises not only a substantial advance in computational power and technical characteristics, but the formation of new technology for the generation of Artificial Intelligence Systems. Figure 6 shows in schematic form the Processor-fl-Memory(PflN-) cell. The PnMcell 1 is connected to a transmission medium 2 equally comprising n separate parallel and bidirectional channels from "1" to "n", each carrying input information in ternary code G3:(A,B,C) and output information in binary code G2:(0,1). Transmission medium 2 is provided for interconnection of the PnMcell 1 with a preceding PnM-cell (not shown). The PrIM-cell 1 is connected to a transmission medium 3 equally comprising n separate parallel and bidirectional channels from "1" to "n", each carrying output information in ternary code G3 and input information in binary code G2. Transmission medium 3 is provided for interconnection of PrIM-cell 1 with a succeeding PnM-cell (not shown). In the PnM-cell 1 each of identical positions 4 is associated with a bidirectional channel in respective transmission mediums 2 and 3. Each position 4 comprises: a receiver RT for ternary input, a ternary logic switch means SA with ternary output, a binary memory device 5 with binary outputs, a ternary logic switch means SE with binary inputs and ternary output, and a transmitter TT for ternary output. Receiver RT and transmitter TT are interface means between position 4 and associated channels in the transmission mediums 2 and 3 respectively. Logic switch means SA evaluates ternary input information units A, B or C for performing a basic operation V which is carried out in the associated memory device 5 according to the logical table ('absorption') with respect to the state of the memory device 5. The state of memory device 5 is fed back (6) through the binary output to the corresponding position in the PnM-cell from which the ternary input information unit is received through the associated channel in the transmission medium 2. Logic switch means SE assigns a unique ternary output information unit A, B or C to the result of a basic operation V or A according to the logical table ('emission') with respect to the state and to the memory mode of the associated memory device 5, and to the state of binary feedback input 7 from the memory device at the corresponding position in the PrIM-cell to which the ternary output information unit will be transmitted through the associated channel in the transmission medium 3. The PnM-cell 1 comprises an accumulating time means (not shown), generating an internal control signal, common for all memory elements, such that when the total time in the 'stand-by' and 'active' processing modes is equal to a predetermined time AT, conversion from the S- to the Memory mode takes place in accordance with the probabilistic rule. External input signals 8, 9, 10 and 11 comprise: - Common control input signal 8 controls the transition of processing modes (from 'passive' to 'stand-by' and from 'stand-by' to 'passive') directly and the conversion of memory modes (from S- to L-mode) indirectly by means of control variable R, frequency selective; - Common control input signal 9 controls the conversion of memory modes (from S- to i-mode and from L, to S-mode) by means of control variable f(q) in accordance with address and/or current processing mode; - Common control input signal 10 for write/read information in/from memory devices 5; - Common input signal 11 for supplying the energy required for operation of the PnM¯cell. Figure 7 shows in schematic form an embodiment of a PnM-network of the invention. An interconnection network 70 comprises an array of pnM-cells A interleaved with an array of insulating degenerate PrIM-cells b. One column of cells A is replaced by a column 71 of degenerate cells C, which are control means for realization of the dynamic switching between sequential and parallel processing. Adjacent to the column 71 of cells C the column 72 of cells b can be moved between positions bl and b2, position bl in fact short circuiting each of the cells C with a cell A in the next column 73, resulting in a PnM- network having N-4 rows and M=12 columns and thus being operative in 4 parallel processing trajectories. Position b2 leaves the pnM-network in a condition with N=4 rows and M!13 columns and thus being operative in one sequential processing trajectory. An illustrative logic circuit implementation of the embodiment of Figure 6 is shown in Figure 8. For convenience, we assume that the ternary signals A, B, C are transmitted from one cell to another in the form of a signal change on one of three lines A, B, C, respectively. Such signal change could be a level transition, e.g. from high-to-low or from low-to-high, or a phase transition. We also assume that binary feedback signals on line 6 and 7 are encoded in a conventional high-low (or one-zero) binary code. The ternary input signed A or B or C is resolved through receiver (RT) into two binary logic signals X and Y in accordance with table 1. TRUTH TABLE INPUT RECEIVER ABC XY 10010 010 0 0 00101 Table 1 The binary signals X, Y then pass into Input Multiplexer (IM). The IM is a dual two to one multiplexer. Depending on the processing mode of the preceding PrIM-cell k-l, passive or stand-by (X,Y) inputs are chosen from the receiver or from bypass multiplexer of preceding PnM-cell (figure 9). Outputs (X,Y) of IN are then passed to the Bypass Multiplexer (BM), which is a dual one to two multiplexer. Depending on the processing mode of the PnM-cell k, passive of stand-by, the signals X,Y are either passed on to the Logic Memory (LM) or forwarded on to the IM of the succeeding PnM-cell k+1. Logic gates 100, 101, 102, 103, 104, 105, 106 and 107 perform the basic logic switch SA function. The Dtype flip-flop 110 performs the binary memory function. Elements 120, 121, 122, 123 and 124 perform the basic logic switch function of SE. The transfer function of the LM, which consists of the SA, binary memory device and SE logic, is described in table 2. INPUT S/L MINIT MFINAL FEEDBACK OUTPUT B C 1000 0 0 0 C 10001 1 0 A 0100 0 0 0 C 01001000 0010 0 1 O A 0 0 1 0 1 1 0 A 1000 0 0 1 A 1 0 0 0 1 1 1 B 0100 0 0 1 A 0100101A 0010 0 1 1 B 00101 1 1 B 1001000C 1001 1 1 O A 01010000 0 1 0 1 1 1 0 B 001 1 0 0 0 C 001 1 1 1 0 A 1 0 0 1 0 0 1 A 100 1 1 1 1 B 0101001A 0101 1 1 1 B 001 1 0 0 1 C 001 1 1 1 1 B Table 2. The Feedback Bypass Multiplexer (FBM) is a dual one to two multiplexer and will either choose the information from the succeeding PnM-cell k+l for itself if the PnM-cell k is in the stand-by processing mode and at the same time feeding its memory information to the preceding PflM-cell k-l. If the PrIM-cell k is in the passive processing mode, then the feedback signal from the succeeding pnM-cell k+l directly passed to the preceding PnM-cell k-l. The output from the SE logic block to transmitter (TT) has the following transfer function described in table 3. TRUTH TABLE OUTPUT TRANSMITTER Xl Yl Zl ABC 1 0 0 100 0 1 0 0 1 0 O 0 1 0 0 1 Table 3 Logic elements 130, 131, 132 and 133 perform the function of complementing the stored data in the binary memory device whenever a conversion from S-memory mode to Memory mode or from Memory mode to S-memory mode occurs. Logic element 132 has the following truth table: CLOCK CLEAR q (CALK) X O 0 0 X-DON'T CARE o -TRANSITION Table 4. Logic elements 200, 201 and 202, shown in figure lO, perform the function of memory mode conversion, where the global operator control signal has the meaning of control variable f(q), and the clock control signal is locally generated by accumulating time means and globally has the meaning of control variable R.

Claims: CLAIMS 1. The method for an elementary component of a system for storage and/or processing of information in numerical and/or symbolic forms comprising n positions and a plurality of inputs for common control of and energy supply to said positions, wherein each position comprises a channel input for a K-nary code flow, where K > 2,a Binary memory element, where Q > 2 and K > Q, a channel output for a K-nary code flow, a first K-nary logic switch means having its input connected to said channel input and its output to an input of said Q-nary memory element, and a second K-nary logic switch means having an input connected to an output of said binary memory element, and an output connected to said channel output, characterized in that: : (A) the ability to conserve a unit of information in the short-term (S-)mode and/or in the long-term (L-)mode, where the said S-mode conserving a unit of information in the form of a n-code word ak and the said i-mode conserving the same unit of information in the form of the complementary n-code word ak' where ak and ak belong to the same [ (ml, m2, ..., mi, ..., m0-i)-out-of-n ] - code and mi being the number of the position occupied by the i-th character of a Q-nary alphabet, where mi = n/Q, (B) the said second K-nary logic switch means comprises W feedback inputs, where W = K-Q, for connection to the outputs of Q-nary memory elements at the corresponding position in W subsequent elementary components, (C) a unified processor-memory functioning is defined by successive processes of absorption and emission, (D) the said first K-nary logic switch means evaluating a K-nary code information unit from said input channel and causing a K-nary logical proposition comprising the evaluated K-nary# code information unit and the state of the associated Q-nary memory element at the corresponding position to select a unique state of the associated Binary memory element at the corresponding position according to a logical table 'absorption', (E) the said second K-nary logic switch means assigning a unique K-nary code information unit for the said output channel according to the logical table 'emission' with respect to the state and to the mode of the associated Q-nary memory element at the corresponding position and to W states of feedback output from Binary memory elements at corresponding positions in W subsequent elementary components, (F) the said feedback input insures preservation of a said [ (m1, m2, ..., mi, ..., m0-1)-out-of-n ] -code for n-codewords presented in parallel, (G) the elementary component can be controlled by changing two out of three processing modes by a first common control signal, namely from a 'passive' processing mode to a 'stand-by' processing mode and from a 'stand-by' processing mode to a 'passive' processing mode, wherein said modes being a 'passive' processing mode preserving the actual state of each element, and a 'stand-by' processing mode enabling to perform the processing function by a transition from the 'stand-by' processing mode to the 'active' processing mode, as result of absorption and by a transition from the 'active' processing mode to the 'stand-by' processing mode to perform the processing and the storage functions if in Mode, and the storage function only if in S-mode, as result of emission, said 'passive' processing mode enabling free passage of Knary information units from the said input channel and of W feedback outputs from Q-nary memory elements at corresponding position in W subsequent elementary components from the said output channel along the first K-nary logic switch means, the Binary memory element and the second K-nary logic switch means, as an operational selection option and as a reliability precaution measure, (H) the K-nary logic over a binary alphabet or (K over Q)-logic being defined by: - a. K truth values and - b. the storage of the result of the evaluation of a K-nary logical proposition in a Binary form, according to a probabilistic rule, (I) a Binary logical relaxation can be attained by restricting to Q out of K balanced truth values. 2. The method for an elementary component according to claim 1, wherein K = 3, Q = 2 and W P 1. 3. The method for an elementary component according to claim 1, wherein K = 2, Q = 2 and W = 0. 4. The method for an elementary component according to claims 1, 2 or 3, wherein an internal clock means comprises an accumulator timing means generating an internal common control signal at a point of time indicating total time in 'stand-by' and 'active' processing modes equalling a predetermined time interval AT, said internal common signal commanding conversion from S- to L- memory mode, wherein the said first common control signal controls indirectly by means of variable R the conversion of the said memory modes from S- to L, frequency selective, the second common control signal controls by means of a variable f(q) conversions of the said memory modes from S- to i- and from L- to S-, selectively in accordance with address and/or current processing mode. 5. The method for an elementary component according to claims 1, 2, 3 or 4 wherein (A) the first ternary logic switch means, the binary memory element and the second ternary logic switch means are technologically realized as an atomic switch, (B) a nucleus of an atom with equal numbers of protons and neutrons, as required by the universal (n/2-out-of-n) code, is considered as a binary memory element, (C) the different energy levels of a nucleon represent positions of conserved n-code binary word and the said position is associated with the value 0 in a case of neutron and with the value 1 in a case of proton, (D) the successive processes of absorption and emission are associated with the strong interactions, mediated by mesons triplet TE , TE , TE and are responsible for causing ternary logical propositions, (E) the S- and the Memory modes are associated with the different energy levels of a nucleus, wherein S- to L-conversion is associated with spontaneous or forced de-excitation to a lowest energy level of a nucleus and L- to Sconversion is associated with forced excitation to a higher energy level of a nucleus only, (F) the said conversions of the said memory modes are associated with the weak interactions as the successive mutually opposite processes of ss-decay and E- capture involving all nucleons of certain type in a nucleus simultaneously, (G) the 'passive' processing mode is associated with the ground state of a nucleus, the 'stand-by' processing mode and the 'active' processing mode are associated with the first and the second excited states respectively, wherein the splitting of above-mentioned levels of excitation into S- and L- sublevels represents the energy structure of the memory modes of an atomic switch. 6. The method for an elementary component according to claim 1, 2, 3, 4 or 5 in which said elementary components are interconnected in a finite network for storage and/or processing of information in numerical (K = Q) and/or symbolic (K > Q) forms, wherein said network is described by an (NXM)-matrix A (N < M), where aij being a said elementary component, wherein said interconnections of said network are organized in accordance with operations ; and 4 being defined as an operation addition modulo N or M, respectively, for i = O, N-l; ;and j O, M-1, such that said network can realize T parallel computing processes, where T > 1,with possibility of identifying I/O with any elementary component (if T21) or with any column of elementary components (if T > 1), where the T is the highest common factor of each given pair N and M. 7. The method for an elementary component according to claim 6, wherein the elementary components of the first row of said (NXM)-matrix are identified with the elementary components of the last row and the elementary components of the first columns are identified with those of the last column, such that said network has a Mbbius type of topology. 8. The method for an elementary component according to claim 6 or 7 wherein degenerate elementary components of type b are arranged to prevent routing of information in two orthogonal directions through homogeneous network. 9. The method for an elementary component according to claim 8 wherein degenerate elementary components of type b are realized as the hydrogen atom which is moleculary bound with an elementary component. 10. The method for an elementary component according to claim 8 or 9 wherein degenerate elementary components of type c are inserted for control purposes and are arranged to provide dynamic switching between parallel and sequential processing. References Birkhoff, G., and J. von Neumann, "The Logic of Quantum Mechanics", Annals of Mathematics, Vol. 37, pp. 823-843j 1936. Brewer, R.G. and E.L. Hahn, "Atomic Memory", Scientific American, Vol. 251, No.6, pp. 42-49, 1984. Carter, F.L., "The Molecular Device Computer: Point of Departure for Large Scale Cellular Automats", Physica lOD, pp. 175-194, 1984. Dijkstra, E.W., "Cooperating sequential processes", in: F. Genuys (ed.), Programming Languages, Acad. Press, New York, NY, pp. 43-112, 1968. Ershov, A.P., "Parallel programming", Proc. IInd Allunion Conf. Homogeneous Computing Systems and Mediums, University of Moskow, 1969. Peterson, W.W., and E.J. Weldon, "Error-correcting Codes", 2nd ed., MIT Press, - Cambridge, pp. 449-463, 1972. Sperry, R.W., "Ordered Functioning in Disordered Structures", Proc. Symposium on Self-Organization, University of Illinois, 1961. Stern, A., and V. Stern, "Denken als quantenmechanischer Vorgang", J. Ideen des exakten Wissens, DVA, Stuttgart, No.9, pp. 544-551, 1973. Stern, A., "Mdbius structure of intellect", Report No. 26.10.82.365, University of Amsterdam, 1982. Stern, A., "Foundation of the Intelligence Code", Report No. 29.11.82.375, University of Amsterdam, 1982. Stern, A. and V. Stern, "An Intelligent Computing System", Report 8406/I (Econometric Institute, Erasmus University Rotterdam), 1984. Zadeh, L.A., "Fuzzy sets", Information and Control, Vol. 8, N3, pp. 338-353, 1965.

Inventors: STERN, AUGUST, STERN, VICTOR
Applicants: STERN, AUGUST, STERN, VICTOR
Application year: 1985
Main classification: G06F15
IPC codes: G06F15