DIFFERENTIAL CODING CIRCUIT

Abstract: A differential coding circuit including a subtractor (7,8), a quantizer (3) for quantizing a differential signal (D) from the subtractor (1), and a predicted signal generating circuit (4,5,6) for generating a predicted signal on the basis of a quantized differential signal from the quantizer (3). The subtractor (7,8) subtracts the quantized differential signal of the quantizer (3) and the predicted signal from the sampled input signal (A). The critical path of the circuit is shortened, therefore the operation speed of the differential coding circuit increases.

Description: The present invention relates to a differential coding circuit for coding a PCM signal comprising: subtracting means for effecting subtraction on an input PCM signal to be quantized to produce a differential signal; quantizing means for quantizing the differential signal produced by said subtracting means and for outputting a quantized differential signal; prediction means for generating a predicted signal in dependence upon the quantized differential signal and a first prediction coefficient; first supply means for supplying to said subtracting means only a first value corresponding to the quantized differential signal multiplied by a second prediction coefficient; and second supply means for supplying to said subtracting means only a second value corresponding to the predicted signal multiplied by a third prediction coefficient. Such a circuit is disclosed in US-A-4 541 102. The differential coding circuit according to the present invention can be used, for example, as a device which effects bandwidth compression coding of a picture signal. A differential coding circuit of the prior art, as described later in more detail, includes, for example, a subtracter for calculating a differential signal between a sampled input signal and a predicted signal, a quantizer for quantizing the differential signal, an adder for adding a quantized differential signal from the quantizer and a predicted signal before one sampling period, and a multiplier for multiplying an output signal of the adder by a prediction coefficient so as to generate the predicted signal. When used as a picture bandwidth compression coding device, however, the speed of operation is not as high as desired. It is an object of the present invention to provide an improved differential coding circuit which has an increased speed of operation for carrying out, for example, bandwidth compression using a DPCM coder. According to the invention, the coding circuit initially defined is characterized in that: said subtracting means includes: a three-input two-output digital-digital converter, having a first input connected to receive the input PCM signal, a second input connected to receive and invert the first value from said first supply means and a third input connected to receive and invert the second value from said second supply means, and two outputs for outputting add value and carry value signals for each digit; and an adder circuit operatively connected to said digital-digital converter to receive the output signals therefrom and comprising a plurality of adders for adding the add value for each digit to a respective lower order carry value to obtain one output. Embodiments of a differential coding circuit in accordance with the present invention will now be described with reference to the accompanying drawings, in which; Fig. 1 is a block diagram of a communication system in which a differential coding circuit is used. Fig. 2 is a block diagram of a differential coding circuit of the prior art; Fig. 3 is a block diagram of a differential coding circuit according to one embodiment of the present invention; Fig. 4 is a more detailed block diagram of a D-D converter, an adder, and a flip-flop in Fig. 3; Fig. 5 through Fig. 16 are block diagrams of differential coding circuits according to other embodiments of the present invention; Fig. 17 is a block diagram of the difference coding circuit of the prior art used in a picture bandwidth compression coding device; Fig. 18 shows the relationship of predicted signals in a picture frame; and Fig. 19 and Fig. 20 are block diagrams of differential coding circuits of the present invention used in picture bandwidth compression coding devices. DESCRIPTION OF THE PREFERRED EMBODIMENTS For a better understanding of the preferred embodiments, the differential coding circuit of the present invention will first be explained in comparison with the differential coding circuit of the prior art. Figure 1 shows one example of a communication system used in a DPCM system. Figure 2 is a block diagram of a differential coding circuit of the prior art used in the system of Fig. 1. In Fig 1, 101 is an analog-to-digital (A/D) converter which samples an analog input signal in a constant period and converts it to a digital sampled signal, 102 a differential coding circuit to which the sampled input signals are input from the A/D converter 101 and which outputs a quantized differential signal obtained by quantizing a differential signal between the sampled input signal and a predicted signal generated in the differential coding circuit 102, 103 a transmitting circuit for coding the quantized differential signal (or DPCM signal) into an form for transmission and sending that signal to the transmission line, 104 a transmission line, 105 a receiving circuit, 106 a differential decoding circuit, and 107 a digital-to-analog (D/A) converter. In Fig. 2, 1 is a subtracter, 2 a flip-flop as a delay element, 3 a quantizer, 4 an adder, 5 a multiplier for multiplying an input signal by a prediction coefficient p (for example, 1 / 2), and 6 a flip-flop as a delay element. The mode of operation of this differential coding circuit will be explained below. A sampled input signal from the A/D converter 101 is input into the subtracter 1, which calculates a differential signal between the sampled input signal and a predicted signal from the multiplier 5. This differential signal is input into the quantizer 3 via the flip-flop 2, which delays the differential signal by one sampling period. The quantizer 3 quantizes the differential signal and outputs the quantized differential signal (or DPCM signal) to the transmitting circuit 103. This quantized differential signal is also input into the adder 4. The adder 4 adds this quantized differential signal and the predicted signal before one sampling period stored in the flip-flop 6. The multiplier 5 multiplies the above summed value by the prediction coefficient p to generate the current predicted signal and sends this current predicted signal into the subtracter 1. The subtracter 1 subtracts the predicted signal from the sampled input signal, as described above. Thus, the differential coding circuit of Fig. 2 outputs a quantized differential signal to the transmitting circuit 103. Figure 3 shows an embodiment of a differential coding circuit according to the present invention. Elements the same in function as in previous drawings bear the same reference numerals (same below). The circuit of Fig. 3 is disposed at the position of the differential circuit 102 in Fig. 1. In Fig. 3, the signal lines are represented by a single line. In practice, of course, there are a plurality of signal lines in a parallel array. The number of lines is indicated by the numerals on top of slash marks on the signal lines. The sampled input signal from the A/D converter 102 is input to the carry input terminal of a digital-to-digital converter 7 having three input terminals and two output terminals (D/D converter). The D/D converter 7 outputs a carry signal and a summed signal to the adder 8. The D/D converter 7 and the adder 8 function equivalently to the subtracter 1 in Fig. 2, therefore, the adder 8 outputs a differential signal. This differential signal is input to the quantizer 3 via the flip-flop 2, which works as a delay element, and is then quantized by the quantizer 3. The quantized differential signal from the quantizer 3 is sent to the adder 4 and the multiplier 9. The quantized differential signal input into the multiplier 9 is multiplied by the prediction coefficient p (p = 1 / 2 , in this example) at the multiplier 9, then inverted and input into the addition input terminal of the D/D converter 7. On the other hand, the quantized differential signal input into the adder 4 is added to the content of the flip-flop 6 at the adder 4. The summed signal is multiplied by the prediction coefficient p at the multiplier 5, then is input into the flip-flop 6. The output signal of the flip-flop 6, i.e., the predicted signal before one sampling period, is multiplied by the prediction coefficient p at the multiplier 10, then inverted and input into the other addition input terminal of the D/D converter 7. The D/D converter 7 calculates the differential value between the sampled input signal and the output signals from the multipliers 9 and 10 for each line and converts these three input signals into two output signals. These two output signals are added by the adder 8. The output signal of the adder 8 is input into the quantizer 3 via the flip-flop 2. Figure 4 is a more detailed block diagram of the D/D converter 7, the adder 8, and flip-flop 2 of Fig. 3. In Fig. 4, the D/D converter 7 includes eight full-adders 7₁ to 7₈ , the adder 8, nine full-adders 8₁ to 8₉ , the flip-flop 2, and nine one-bit type flip-flops 2₁ to 2₉. A7 to A0 represent eight bits of a sampled input signal. B6 to B0 and C6 to C0 represent seven bits of signals obtained by multiplying eight bits of the output signal of the quantizer 3 by the prediction coefficient p (i.e., 1 / 2) at the multipliers 9 and 10, respectively. The bits A0 to A7 of the sampled input signal are input into the carry input terminal of the full-adders 7₁ to 7₈ , respectively. The bits B0 to B6 and bits C0 to C6 are inverted and input into two addition input terminals of the full-adders 7₁ to 7₇ , respectively. In the case of the full-adder 7₈ of the most significant bit (MSB), the bits B6 and C6 are input to the addition terminals. The summed output terminals of the full-adders 7₁ to 7₈ are connected to the addition input terminals of the full-adders 8₁ to 8₈ of the adder 8, respectively. The summed output terminal of the full-adder 7₈ is also connected to the addition input terminal of the full-adder 8₉. The carry output terminals of the full-adders 7₁ to 7₈ are connected to the other addition input terminals of the full-adders 8₂ to 8₉ , respectively. The other addition input terminal of the full-adder 8₁ of the least significant bit (LSB) is grounded. Alternatively, a correction signal of the operation precision may be input into that. The carry output terminals of the full-adder 8₁ to 8₈ are connected to the carry input terminals of the next significant full-adders 8₂ to 8₉ , respectively, except that the high level voltage is applied to the carry input terminal of the full-adder 8₁. The summed output terminals of the full-adders 8₁ to 8₉ are connected to the quantizer 3 via the flip-flops 2₁ to 2₉ , respectively. The differential coding circuits of Fig. 2 and Fig. 3 operate equivalently in function. That is, in Fig. 2, if A represents the sampled input signal, D the differential signal input into the flip-flop 2, Q the quantized differential signal output from the quantizer 3, R the output signal of the flip-flop 6 to the adder 4, and p the prediction coefficient, the predicted signal to the subtracter 1 is expressed by p x (Q + R) . Therefore, the differential signal D is expressed as; D = A - p x (Q + R) On the other hand, in Fig. 3, the differential signal D is expressed as; D = A - p x Q - p x R As obvious from these two expressions, the circuits of Fig. 2 and Fig. 3 are equivalent in function. The operation speed of the differential coding circuits of Fig. 2 and Fig. 3 is dependent upon the critical path of the signal, i.e., the path with the longest signal transmission time. The critical path of Fig. 2 is, based on the flip-flop 2, the path from the flip-flop 2 through the quantizer 3, adder 4, multiplier 5, and subtracter 1 and back to the flip-flop 2. In the case of Fig. 3, three signal paths should be investigated; a first path from the flip-flop 2 via the quantizer 3, the multiplier 9, the D/D converter 7, and the adder 8 and back to the flip-flop 2; a second path from the flip-flop 2 via the quantizer 3, the adder 4, and the multiplier 5 to the flip-flop 6; and a third path from the flip-flop 6 through the multiplier 10, the D/D converter 7, and the adder 8 to the flip-flop 2. Regarding the operation speeds of each element of the circuit, the subtracter 1 and the adders 4 and 8 take more operation time than the D/D converter 7, since they consist of serial arithmetic circuits which involve a carry from the LSB to MSB in sequence. Accordingly, of the three paths of Fig. 3, the first path is the critical path requiring the longest signal transmission time. Comparing the critical path of the circuit of Fig. 3 with that of Fig. 2, the adder 8 and the adder 4 have almost the same operation speed, and the D/D converter 7 is faster than the subtracter 1. As a result, the Fig. 3 circuit is faster than the Fig. 2 circuit by the difference in speed of the converter over the subtracter. Figures 5 through 9 show other embodiments of the differential coding circuit according to the present invention. These embodiments are modified in regard to the constitution of the adder 4, the multiplier 5, the flip-flop 6, and the multiplier 10 of Fig. 3. However, these circuits are equivalent to the circuit of Fig. 3 in function. In Fig. 5, the output signal of the multiplier 5 is inverted and input into the input terminal of the D/D converter 7 via the multiplier 10 and the flip-flop 16. In Fig. 6, the output signal of the adder 4 is inverted and input to the input terminal of the D/D converter 7 via a multiplier 11 which multiplies it's input signal by a square of the prediction coefficient p and the flip-flop 16. In Fig. 7, the positions of the multiplier 5 and the flip-flop 6 are reversed, in comparison with Fig. 3, and the output signal of the adder 4 is input to the flip-flop 6 via the multiplier 11 described above. Further, the output signal of the flip-flop 6 is inverted and input to the input terminal of the D/D converter 7. In Fig. 8, the positions of the multiplier 5 and the flip-flop 6 are also reversed in comparison with Fig. 3, and the output signal of the multiplier 5 is inverted and input to the input terminal of the D/D converter 7 via the multiplier 10. In Fig. 9, the positions of the multiplier 5 and the flip-flop 6 are also reversed in comparison with Fig. 3, and the output signal of the flip-flop 6 is inverted and input to the input terminal of the D/D converter 7 via the multiplier 11 described above. Furthermore, as other embodiments of the present invention, it is possible to reverse the positions of the flip-flop 2 and the quantizer 3 of Figs. 3 and 5 through 9, respectively. Figure 10 shows another embodiment of the differential coding circuit according to the present invention. This circuit has an operation speed even faster than that of the Fig. 3 circuit. The improvements over the Fig. 3 circuit are as follows. First, instead of the quantizer 3, a quantizer 31 outputting two output signals is used. That is, this quantizer 31 outputs, on one hand, the quantized differential signal Q and, on the other hand, an output signal p x Q corresponding to the value obtained by multiplying the prediction coefficient p by the quantized differential signal Q in response to the differential signal D input from the flip-flop 2. Further, the multiplier 9 of Fig. 3 is eliminated, and the output terminal of the quantizer 31 and the input terminal of the D/D converter 7 are directly connected. The quantizer 31 may be constituted by a read-only memory (ROM), random-access memory (RAM), programmable logic array (PLA), etc. The output bits are divided into two output portions; one for the signal Q, the other for the signal p x Q. Different data, i.e., Q and p x Q, are stored in the storing regions of the two output portions with respect to one input signal, i.e., one input address. Second, in order to shorten the operation time in the case of the signal path from the flip-flop 2 via the adder 4 to the flip-flop 6, the positions of the multiplier 5 and the flip-flop 6 of Fig. 3 are reversed. Further, the output signal of the flip-flop 6 is inverted and input, on one hand, to the adder 4 via a multiplier 5, which multiplies it with the prediction coefficient p, and, on the other hand, to the D/D converter 7 via a multiplier 11, which multiplies it with a square of the prediction coefficient p. As clear from the drawings, the circuit of Fig. 10 is equivalent to the circuit of Fig. 3 in function in spite of the modification described above. Regarding the operation speed of the Fig. 10 circuit, the circuit has the following signal paths: a first path from the flip-flop 2 via the quantizer 31, the D/D converter 7, and the adder 8 back to the flip-flop 2; a second path from the flip-flop 2 via the quantizer 31 and the adder 4 to the flip-flop 6; and a third path from the flip-flop 6 via the multiplier 11, the D/D converter 7, and the adder 8 to the flip-flop 2. When the multiplier 11 is faster than the quantizer 31, the critical path of the Fig. 10 circuit is the first path. Comparing this critical path of Fig. 10 with that of Fig. 3, the operation speed of the former is faster than that of the latter by a delay time of the multiplier 9. Figure 11 shows a further embodiment of the differential coding circuit according to the present invention. Again, the operation speed is faster than that of the Fig. 3 circuit. The improvements over the Fig. 3 circuit are as follows. First, the quantizer 31, the same as that of Fig. 10, is directly connected just after the adder 8. The quantized differential signal Q from the quantizer 31 is input into the transmitting circuit 103 and the adder 4 via a flip-flop 14. The signal p x Q, obtained by multiplying the quantized differential signal Q by the prediction coefficient p, is inverted and input into the D/D converter 7 via a flip-flop 15. The quantizer 31 is in practice constituted by a ROM, RAM, PLA, etc., as described above. In Fig. 11, however, the quantizer 31 is represented by an equivalent functional block diagram comprising a quantizing portion 311 and a multiplying portion 312. Further, in order to shorten the transmission time of the path from the flip-flop 6 to the flip-flop 2 of Fig. 3, the multiplier 10 is eliminated. Instead, the output signal or the adder 4 is inverted and input into the D/D converter 7 via the multiplier 11, which multiplies it with a square of the prediction coefficient p, and a flip-flop 16. The Fig. 11 circuit is equivalent with the Fig. 3 circuit in function. Regarding the operation speed of the Fig. 11 circuit, the circuit has the following signal paths: a first path from the flip-flop 15 via the D/D converter 7, the adder 8, and the quantizer 31 back to the flip-flop 15; a second path from the flip-flop 14 via the adder 4 to the multiplier 5 and the flip-flop 6 or to the multiplier 11 to the flip-flop 16; and a third path from the flip-flop 16 via the D/D converter 7, the adder 8, and the quantizer 31 to the flip-flop 14 or 15. In this case, the critical path is the first path or the third path. Therefore, compared with the Fig. 3 circuit, the Fig. 11 circuit is faster by the delay time at the multiplier 9 or 10. It is possible to modify the Fig. 11 circuit. For example, the quantizer 31 and the flip-flops 14 and 15 may be constituted by a single registered ROM having both functions. Figure 12 shows a further embodiment or the differential coding circuit according to the present invention. Again, the operation speed is faster than that of the Fig. 3 circuit. The improvements over the Fig. 3 circuit are as follows. In the Fig. 12 circuit, the quantizer 3 is replaced by the quantizer 32, which functions to output the value obtained by quantizing the multiplied differential signal by the prediction coefficient p. Therefore, the multipliers 9 and 10 of the Fig. 3 circuit, which serve to multiply the prediction coefficient p, are eliminated. Further, a multiplier 13 for multiplying by the reciprocal 1 / P of the prediction coefficient is provided in front of the D/D converter 7, so that the prediction coefficient p multiplied at the quantizer 32 is cancelled at the output terminal of the quantizer 32. The Fig. 12 circuit has an equivalent function with the Fig. 3 circuit. The quantizer 32 may be embodied by a RAM, ROM, PLA, etc. In Fig. 12, the quantizer 32 is represented by an equivalent functional block diagram containing a multiplying portion 321 and a quantizing portion 322. Regarding the operation speed of the Fig. 12 circuit, the circuit has the following two paths: a first path from the flip-flop 2 via the quantizer 32, the D/D converter 7, and the adder 8 back to the flip-flop 2 and a second path from the flip-flop 2 to the flip-flop 6 via the quantizer 32, the adder 4, and the multiplier 5. When the multiplier 5 is faster than the quantizer 32, the critical path is the first path. Comparing this critical path with that of Fig. 3, the operation speed for the prediction of the Fig. 12 circuit is faster than that of the Fig. 3 circuit by the delay time of the multiplier 9. Further, the Fig. 12 circuit may be modified. For example, the positions of the flip-flop 2 and the quantizer 32 may be reversed. Also, the positions of the multiplier 5 and the flip-flop 6 may be reversed. In the former case, if the delay time of the multiplier 5 is ZERO (i.e., bit shift) or the position of the multiplier 5 and the flip-flop 6 are reversed, the critical path is the path from the flip-flop 2 via the D/D converter 7, the adder 8, and the quantizer 32 back to the flip-flop 2. Similarly, in the latter case, if the delay time of the multiplier 5 is smaller than that of the D/D converter 7, the critical path is the path from the flip-flop 2 via the quantizer 32, the D/D converter 7, and the adder 8 back to the flip-flop 2. In each case, the operation speed for the prediction of the circuit is faster than that of the Fig. 3 circuit by the delay time of the multiplier 9. Figure 13 shows a further embodiment of the present invention, which improves the differential coding circuit of Fig. 12. That is, in the Fig. 12 circuit, if the prediction coefficient p of the multiplier 5 is small, the number of output bits of the multiplier 13 increases. Accordingly, the delay time of the adder 8 increases, therefore the delay time of the critical path increases. As a result, the operation speed of the Fig. 12 circuit becomes low. The circuit of Fig. 13 is provided to solve this problem. In Fig. 13, the coefficient of the multiplier 13 is selected as 1/2 n p, where n is an integer more than one, and p is the prediction coefficient of the multiplier 5. In accordance with this change, the coefficient of the multiplying portion 321 of the quantizer 32 is selected to 2 n p, a multiplier 131 is inserted between the quantizer 32 and the D/D converter 7, and a multiplier 132 is inserted between the multiplier 5 and the D/D converter 7. The coefficients of the multipliers 131 and 132 are selected as 1/2 n . In this circuit, due to the low coefficient of the multiplier 13, the number or output bits of the multiplier 13 does not increase, therefore the delay time of the adder 8 does not increase. Further, when the coefficients of the multipliers 131 and 132 are 1/2 n , they may be constituted by a "bit shift", which has no delay time. As a result, the delay time or the critical path of Fig. 13 is almost the same as that of Fig. 12 even though the prediction coefficient p of the multiplier 5 is small. Figure 14 shows another embodiment of the differential coding circuit according to the present invention. The operation speed is faster than that of the Fig. 2 circuit. In Fig. 14, 17 and 18 are subtracters, and 9 and 10 are multipliers for multiplying the prediction coefricient p (in this example, p = 1 / 2). The improvements over the Fig. 2 circuit are as follows. An output signal of the flip-flop 6 corresponding to the predicted signal before one sampling period is multiplied by the prediction coefficient p at the multiplier 10, then input to the subtracter 17. The subtracter 17 calculates the differential value between the sampled input signal and the output signal from the multiplier 10. The quantized differential signal output from the quantizer 3 is multiplied by the prediction coefficient p at the multiplier 9, then input to the subtracter 18. The subtracter 18 calculates the differential value between the output signals of the multiplier 9 and the subtracter 17, then outputs it to the quantizer 3 via the flip-flop 2. That is, in Fig. 2, the output signals of the quantizer 3 and the flip-flop 6 are added at the adder 4, multiplied with the prediction coefficient p at the multiplier 5 to make the predicted signal, then subtracted from the sampled input signal at the subtracter 1. On the other hand, in Fig. 14, the output signal of the quantizer 3 and that of the flip-flop 6 are multiplied by the prediction coefficient p separately at the multipliers 9 and 10, respectively, then subtracted from the sampled input signal A separately at the subtracters 17 and 18. As a result, the Fig. 1A circuit functions equivalently to the Fig. 2 circuit. The critical path determining the operation speed is the path from the flip-flop 2 via the quantizer 3, the multiplier 9, and the subtracter 18 back to the flip-flop 2. Compared with the Fig. 2 circuit, the Fig. 14 circuit is faster by the delay time of the adder 4. In this circuit of Fig. 14, the constitution of the adder 4, the multiplier 5, the flip-flop 6, and the multiplier 10 can be modified in the same manner as described in Figs. 5 through 9. Also, the positions of the flip-flop 2 and the quantizer 3 can be reversed in the above described modifications. Figure 15 shows another embodiment of the differential coding circuit according to the present invention. The operation speed is increased in comparison with the Fig. 14 circuit. In Fig. 15, the sampled input signal is input to the subtracter 17. The output terminal of the subtracter 17 is connected to one of the input terminals of the quantizer 33, while the output terminal of the quantizer 33 is connected to the other input terminal via the flip-flop 19. The output terminal of the flip-flop 19 is also connected to one or the input terminals of a code converting circuit 20. The code converting circuit 20 has two output terminals, one of which is connected to the subtracted input terminal of the subtracter 17 via a flip-flop 21, the other of which is connected to the other input terminal of the circuit 20 via a flip-flop 22. The flip-flops 21 and 22 delay the input signal by one sampling period. The quantizer 33 and the code converting circuit 20 are constituted by a ROM, RAM, PLA, etc. and are illustrated by an equivalent function block diagram in Fig. 15. That is, the function of the quantizer 33 is represented equivalently by a reverse converting portion 331 which reverse converts the output signal from the flip-flop 19 to restore the number of bits, a multiplying portion 332, which multiplies the output signal of the reverse converting portion 331 by the prediction coefficient p (for example, 1 / 2), a subtracting portion 333, which subtracts the output signal of the multiplying portion 332 from the output signal of the subtracter 17, a quantizing portion 334, which quantizes the differential output signal of the subtracting portion 333, and a converting portion 335, which code-converts the quantized differential signal of the quantizing portion 334 to reduce the number of bits. The function of the code-converting circuit 20 is represented equivalently by a reverse converting portion 201, which reverse converts the output signal of the flip-flop 19, an adding portion 202, which adds the output signal of the reverse converting portion 201 and the output signal of the flip-flop 22, a multiplying portion 203, which multiplies the output signal of the adding portion 202 by a square value p² of the prediction coefficient, and a multiplying portion 204, which multiplies the output signal of the adding portion 202 by the prediction coefficient p. The Fig. 15 circuit functions equivalently to the Fig. 14 circuit. In this case, the critical path of Fig. 15 is a path from the flip-flop 21 via the subtracter 17 and the quantizer 33 to the flip-flop 19. Comparing Fig. 15 with the Fig. 14, since the operation speeds of the quantizers 3 and 33 and the subtracters 17 and 18 are almost equal, the Fig. 15 circuit operates faster by the delay time of the multiplier 9. Figure 16 shows a modification of the Fig. 15 circuit. The Fig. 16 circuit has a code-converting circuit different from that of the Fig. 15 circuit. That is, in Fig. 16, the code-converting circuit 200 is represented by the equivalent function block diagram including the inverting portion 201, a multiplying portion 205, which multiplies the output signal of the flip-flop 22 by the reciprocal p⁻¹ of the prediction coefficient, the adding portion 202, and the multiplying portion 203. This Fig. 16 circuit increases the operation speed by the same amount as the Fig. 15 circuit. Further, for example, in Fig. 15, the quantizer 33, the flip-flops 19, 21, and 22, and the code-converting circuit 200 are separately constituted. However, the quantizer 33 and the flip-flop 19 or the code-converting circuit 200 and the flip-flops 21 and 22 can be formed by a single registered ROM. The same may be said in the case of Fig. 16. An explanation will now be made of an example of the use of the differential coding circuit of the present invention. The example refers to use in a picture bandwidth compression coding device which can effect prediction within a field, between fields, and between frames. For ease of understanding, an explanation of a use of a differential coding circuit of the prior art in a picture bandwidth compression coding device will first be given with reference to Fig. 17. Figure 17 shows a plane (two-dimension) predictive coding circuit of the prior art. In Fig. 17, reference numerals 1 through 6 indicate the same elements as in Fig. 2. Reference numerals 41 and 42 are delay circuits which store respectively the predicted value P(1H - 1), and the predicted value P(1H - 2) of one horizontal scanning line before of the same frame, as shown in Fig. 18, where P(0) represents a current predicted value. Reference numerals 43 and 44 are multipliers which multiply the output signals of the delay circuits 41 and 42 by the prediction coefficient 1 / 4 , respectively, and 45 an adder which adds the output signals of the multipliers 5, 13, and 14 and outputs a summed value to the subtracter 1 and the flip-flop 6. The mode of operation of the Fig. 17 circuit will be now explained. A predicted signal P(1) of one sampling period before output from the adder 4, the predicted signal P(1H - 1) of one horizontal scanning line before of the current input signal delayed at the delay circuit 41, and the predicted signal P(1H - 2) of one sampling period before of the predicted signal P(1H - 1) delayed at the delay circuit 42 are multiplied by the prediction coefficients 1 / 2 , 1 / 4 , and 1 / 4 at the multipliers 5, 43, and 44 respectively, for weighting thereof. These signals are then added by the adder 45 so as to obtain the predicted signal P(0). The subtracter 1 subtracts this predicted signal P(0) from a sampled input signal of the pixel and outputs a differential signal to the quantizer 3 via the flip-flop 2, which delays the differential signal by one sampling period. The quantizer 3 quantizes the differential signal and outputs the quantized differential signal (or DPCM signal). The critical path of the Fig. 17 circuit is a path from the flip-flop 2 via the quantizer 3, the adder 4, the multiplier 5, the adder 45, and the subtracter 1 back to the flip-flop 2. In order to increase the operation speed of the Fig. 17 circuit in the prior art, it has been necessary to constitute the circuit by a special device, for example, an emitter coupled logic (ECL) device. However, when the characteristics of the quantizer and/or multiplier are complicated, such a circuit cannot be realized even if an ECL device is used. Figure. 19 shows a high-speed plane predictive coding circuit (or DPCM circuit) according to the present invention. In Fig. 19, reference numerals 2 to 10 indicate the same elements as in Fig. 3. Reference numerals 46 and 47 are delay circuits with delay times one sampling period smaller than those of the delay circuits 41 and 42 of Fig. 17, respectively. Reference numerals 48 and 50 are adders, 49, 52 and 53 flip-flops, used as the delay circuit for one sampling period delay, and 51 the subtracter. The mode of the operation of the Fig. 19 circuit will be described hereinafter. The delay circuits 46 and 47 store the predicted signal P(1H - 2) and the predicted signal p(1H - 3) which is one sampling period faster than the delay circuits 41 and 42, respectively. These output signals of the delay circuits 46 and 47 are multiplied by the prediction coefficient 1 / 4 at the multiplier 43 and 44, respectively, and then added to each other at the adder 48. The subtracter 51 obtains the differential value between the summed value of the adder 48 and the sampled input signal. This differential value is input to the D/D converter 7 via the flip-flop 52, having the delay time of one sampling period. At the same time, the summed value of the adder 48 is input to the adder 50 via the flip-flops 49, and 53, also having the delay time of one sampling period, so as to be added to the output signal of the flip-flop 6. Then, the summed signal of the adder 50 is input to the adder 4. By this, the Fig. 19 circuit is made equivalent to the Fig. 17 circuit. In Fig. 19, there are the following signal paths which must be investigated to determine the operation speed of the circuit: a first path from the flip-flop 2 via the quantizer 3, the multiplier 9, the D/D converter 7, and the adder 8 back to the flip-flop 2 and a second path from the flip-flop 6 via the adder 50, the multiplier 10, the D/D converter 7 and the adder 8 to the flip-flop 2. When the delay time of the adder 50 is less than that of the quantizer 3, the critical path is the first path, as in the Fig. 3 circuit, and the operation speed is not reduced due to the second path. Consequently, the operation speed of the Fig. 19 circuit is faster than that of the Fig. 17 circuit without using a special device such as an ECL device. Figure 20 is a general block diagram of a differential coding circuit used in a picture bandwidth compression coding device according to the present invention. In Fig. 20, the output values of the delay circuits 61₁ to 61 n , corresponding to a pixel value of the same line, a pixel value of the same field, a pixel value of a different field, a pixel value of a same frame, a pixel value of a different frame, etc. are multiplied by the weighted prediction coefficient α₁ to α n at the multipliers 62₁ to 62 n respectively. These values are then added at the adder 48. The summed value of the adder 48 is input into the subtracter 51. The output value of the adder 4, almost equal to the input value of two sampling periods before, is multiplied by the prediction coefficient α₀ at a multiplier 63. Also, multipliers 64 and 65 multiply the input signal by the prediction coefficient α₀. Although the circuits of Figs. 19 and 20 utilize the circuit of Fig. 3, however, the circuit of Fig. 14 may also be utilized in the same way. All embodiments described above relate to linear prediction and were explained on the supposition that the prediction coefficient p was linear. Therefore, in these embodiments, the predictor was constituted only by means of a multiplier, for example, the multipliers 5, 9, 10, or 11. However, the predictor is not limited to a multiplier when linear prediction is effected, for example, it may be realized by means of a "bit shift". Further, the present invention can be applied to nonlinear prediction if the following condition regarding the signals Q and R of, for example, Fig. 3 is satisfied: p(R + Q) ≃ pR + pQ In such a case, the multiplier for prediction described above can be replaced by predicting means constituted by a combination of the gates, ROM, RAM, PLA, etc. Further, when the present invention is applied to the differential coding circuit effecting adaptive quantizing (or ADPCM), the quantizer and/or predictor may have a control input which changes the characteristics of the quantizer and/or predictor.

Claims: A differential coding circuit for coding a PCM signal comprising: subtracting means (7,8;17,18;17.333) for effecting subtraction on an input PCM signal to be quantized to produce a differential signal; quantizing means (3;31;32) for quantizing the differential signal produced by said subtracting means and for outputting a quantized differential signal; prediction means (4,5,6;20;200) for generating a predicted signal in dependence upon the quantized differential signal and a first prediction coefficient; first supply means (9,312,131) for supplying to said subtracting means a first value corresponding to the quantized differential signal multiplied by a second prediction coefficient; and second supply means for supplying to said subtracting means a second value corresponding to the predicted signal multiplied by a third prediction coefficient; characterized in that: said subtracting means includes: a three-input two-output digital-digital converter (7), having a first input connected to receive the input PCM signal, a second input connected to receive and invert the first value from said first supply means and a third input connected to receive and invert the second value from said second supply means, and two outputs for outputting add value and carry value signals for each digit; and an adder circuit (8) operatively connected to said digital-digital converter to receive the output signals therefrom and comprising a plurality of adders for adding the add value for each digit to a respective lower order carry value to obtain one output. A differential coding circuit according to claim 1, wherein: said first prediction coefficient is equal to said second prediction coefficient and said third prediction coefficient. A differential coding circuit as recited in claim 1 or 2, wherein said subtracting means further comprises: a delay element (2), operatively connected to said adder circuit (8) and said quantizing means (3), for outputting the differential signal to said quantizing means (3), wherein said quantizing means (3) comprises a quantizer, operatively connected to said delay element (2), said prediction means (4,5,6) and said first supply means (9), for generating the quantized differential signal. A differential coding circuit as recited in claim 1 or 2, wherein said quantizing means comprises: a quantizer (3), operatively connected to said adder (8), for generating the quantized differential signal; and a delay element, operatively connected to said quantizing means (3), said first supply means (9) and said prediction means (4,5,6) for delaying and outputting the quantized differential signal. A differential coding circuit as recited in claim 1 or 2, wherein said subtracting means comprises: a delay element (2), operatively connected to said adder and said quantizing means, for outputting the differential signal to said quantizing means (3); and wherein said quantizing means comprises a quantizer (3), operatively connected to the said delay element (2), said prediction means (4,5,6) and said first supply means (9), for generating the quantized differential signal and the first value, said quantizer outputting the quantized differential signal to said prediction means and the first value to said first supply means. A differential coding circuit as recited in claim 5, wherein said quantizer comprises one of a read only memory, a random access memory, a programmable logic array and programmable array logic. A differential coding circuit as recited in claims 1 or 2 further comprising: a quantizer (3), operatively connected to the said adder circuit (8), for generating the quantized differential signal and the first value; and delay means, operatively connected to said quantizing means, said first supply means and said prediction means, for delaying and outputting the quantized differential signal to said prediction means and the first value to said first supply means. A differential coding circuit as recited in claim 7, wherein said quantizer comprises at least one of a read only memory, a random access memory, a programmable logic array and programmable array logic. A differential coding circuit as recited in any of claims 1 to 8, wherein said prediction means comprises a prediction signal generating loop including - an adder (4), operatively connected to said quantizing means (3), for adding a prior predicted signal to the quantized differential signal to produce a sum, a first predictor (5), operatively connected to said adder (4), for multiplying the sum output from said adder (4) by the first prediction coefficient to produce the predicted signal, and a delay element (6), operatively connected to said first predictor (5), said adder (4) and said second supply means (10), for delaying the predicted signal output by said first predictor (5) and supplying the prior predicted signal to said adder (4) and said second supply means (10), and wherein said second supply means comprises a second predictor (10), operatively connected to said delay element and said subtracting means (7,8), for multiplying the output from said delay element by the second prediction coefficient to produce the second value supplied to said subtracting means (7,8). A differential coding circuit as recited in any of claims 1 to 8, wherein said prediction means comprises a prediction signal generating loop including - an adder (4), operatively connected to said quantizing means (3), for adding a prior predicted signal to the quantized differential signal to produce a sum, a first predictor (5), operatively connected to said adder and said second supply means, for multiplying the sum output from said adder by the prediction coefficient to produce the predicted signal, and a delay element (6), operatively connected to said first predictor and said adder, for delaying the predicted signal output by said first predictor (5) and supplying the prior predicted signal to said adder (4), and wherein said second supply means comprises: a second predictor (10), operatively connected to said first predictor (5), for multiplying the predicted signal from said first predictor by the first prediction coefficient to produce the second value; and a second delay element (16), operatively connected to said second predictor (10) and said subtracting means (7,8), for delaying the second value supplied to said subtracting means. A differential coding circuit as recited in any of claims 1 to 8, wherein said prediction means comprises a prediction signal generating loop including - an adder (4), operatively connected to said quantizing means (3) and said second supply means (10), for adding a prior predicted signal to the quantized differential signal to produce a sum, a first predictor (5), operatively connected to said adder(4), for multiplying the sum output from said adder by the first prediction coefficient to produce the predicted signal, and a first delay element (6), operatively connected to said first predictor (5) and said adder (4), for delaying the predicted signal output by said first predictor and supplying the prior predicted signal to said adder (4), and wherein said second supply means comprises: a second predictor (11), operatively connected to said adder (4), for multiplying the sum output from said adder (4) by the first prediction coefficient squared to produce the second value;and a second delay element (16), operatively connected to said second predictor (10) and said subtracting means (7,8), for delaying the second value output from said second predictor (11). (Fig. 6). A differential coding circuit as recited in any of claims 1 to 8, wherein said prediction means comprises a prediction signal generating loop including - an adder (4), operatively connected to receive the quantized differential signal from said quantizing means (3), for adding the predicted signal to the quantized differential signal to produce a sum, a first predictor (11), operatively connected to said adder (4), for multiplying the sum output from said adder by the first prediction coefficient squared to produce the second value, a delay element (6), operatively connected to said first predictor (11) and said second supply means for delaying the second value output from said first predictor (11) and providing an output to said second supply means, said second supply means supplying the output of said delay element (6) to said subtracting means as the second value, and a second predictor (5), operatively connected to said delay element (6) and said adder (4), for multiplying the output of said delay element by the reciprocal of the first prediction coefficient to produce the predicted signal. (Fig. 7). A differential coding circuit as recited in any of claims 1 to 8, wherein said prediction means comprises a prediction signal generating loop including - an adder (4), operatively connected to receive the quantized differential signal from said quantizing means (3), for adding the predicted signal and the quantized differential signal to produce a sum, a delay element (6), operatively connected to said adder, for delaying the sum output from said adder to produce an output, a first predictor (5), operatively connected to said delay element (6), said adder (4) and said second supply means, for multiplying the output from said first delay element (6) by the first prediction coefficient to produce the predicted signal, and wherein said second supply means comprises a second predictor (10), operatively connected to said first predictor (5) and said subtracting means (7,8), for multiplying the predicted signal output from said first predictor by the first prediction coefficient to produce the second value supplied to said subtracting means. (Fig. 8). A differential coding circuit as recited in any of claims 1 to 8, wherein said prediction means comprises a prediction signal generating loop including - an adder (4), operatively connected to receive the quantized differential signal from said quantizing means (3), for adding the predicted signal and the quantized differential signal to produce a sum, a delay element (6), operatively connected to said adder (4), for delaying the sum output from said adder to produce an output, a first predictor (5), operatively connected to said delay element (6), said adder (4) and said second supply means, for multiplying the output from said first delay element by the first prediction coefficient to produce the predicted signal, and wherein said second supply means comprises a second predictor (11), operatively connected to said delay element (6), for multiplying the output from said delay element (6) by the square of the first prediction coefficient to produce the second value supplied to said subtracting means. (Fig. 9). A differential coding circuit as recited in any preceding claim, wherein said quantizing means comprises: a quantizer, operatively connected to said subtracting means, said quantizer including at least one of a read only memory, a random access memory, a programmable logic array and programmable array logic; and a delay element, operatively connected to said quantizer and said prediction means. A differential coding circuit as recited in any of claims 1 to 14, wherein said quantizing means comprises a registered read only memory operatively connected to said subtraction means and said prediction means. A differential coding circuit according to any preceding claim further comprising: product means (13) for multiplying the input signal to be quantized by a reciprocal of the first prediction coefficient times 2 n where n is zero or an integer greater than one, before supply to said subtraction means (7); wherein: said quantizing means (32) is arranged to produce a differential signal corresponding to the subtracted value output by said subtracting means multiplied by the first prediction coefficient times 2 n and to quantize the differential signal to produce a quantized differential signal; said first supply means (131) is arranged to supply a value corresponding to the quantized differential signal multiplied by 1/2 n ; and said second supply means (132) is arranged to supply a value corresponding to the predicted signal multiplied by 1/2 n . (Fig. 13). A differential coding circuit as recited in claim 17, further comprising a delay element (2), operatively connected to said adder circuit (8) and said quantizing means (32), for delaying and outputting the sum to said quantizing means (32), wherein said quantizing means comprises a quantizer (322), operatively connected to said delay element (2), said prediction means (4,5,6) and said first supply means (131), for generating the quantized differential signal in dependence upon the subtracted value from said subtracting means (7) multiplied by the first prediction coefficient times 2 n , wherein said first supply means comprises a first multiplier (131), operatively connected to said quantizer (32), for multiplying the quantized differential signal from said quantizer by 1/2 n to produce the first value supplied to said digital-digital converter (7), and wherein said second supply means (132) comprises a second multiplier, operatively connected to said prediction means (4,5,6), for multiplying the predicted signal by 1/2 n to produce the second value supplied to said digital-digital converter (7). A differential coding circuit as recited in claim 17, wherein said quantizing means (32) comprises: a quantizer (322), operatively connected to said adder circuit (8), for generating the quantized differential signal in dependence upon the subtracted value from said subtracting means multiplied by the first prediction coefficient times 2 n ; and a delay element, operatively connected to said quantizing means (32), said prediction means and said first supply means, for delaying and outputting the quantized differential signal to the prediction means and said first supply means, wherein said first supply means comprises a first multiplier (131), operatively connected to said quantizer (32), for multiplying the quantized differential signal from said quantizer by 1/2 n to produce the first value supplied to said digital-digital converter, and wherein said second supply means comprises a second multiplier (132), operatively connected to said prediction means (4,5,6), for multiplying the predicted signal by 1/2 n to produce the second value supplied to said digital-digital converter. A differential coding circuit, according to claim 1, wherein said first prediction means includes a first predictor for generating a first predicted signal in dependence upon the quantized differential signal and the first prediction coefficient; and a second predictor for generating a second predicted signal in dependence upon the quantized differential signal; and said second supply means is arranged to supply to said subtracting means (7) a value corresponding to a sum of the first and second predicted signals multiplied by the first prediction coefficient. A differential coding circuit according to claim 1, wherein: said prediction circuit (20) includes one of a read only memory, a random access memory, a programmable logic array and programmable array logic, for producing a first output signal and a second output signal; a first delay element (22) is operatively connected to receive the second output signal from said prediction circuit (20), for supplying a delayed second signal to said prediction circuit (20), said prediction circuit producing the second output signal in dependence upon both the quantized differential signal and the delayed second signal; a second delay element (21) is provided operatively connected to said prediction circuit (20) and said subtracting means (17), for receiving the first output signal from said prediction circuit (20) and supplying a delayed first output signal as the value to be subtracted by said subtracting means; and said first supply means is arranged to supply a previous value of the quantized differential signal to said quantizing means (334), said quantizing means producing the quantized differential signal in dependence upon the differential signal and the previous value of the quantized differential signal. (Fig. 15).

Inventors: FUKUI, HIROKAZU, GAMBE, HIROHISA, IKEZAWA, TOSHI, MAKI, SHINICHI MOEGINO HAITSU 105, MATSUDA, KIICHI SHIBUE-SO 7, OKAZAKI, TAKESHI, TSUDA, TOSHITAKA 3-304, MINAMINOMACHI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H03M3
IPC codes: H03M3, G06T9, H04N11