IMPROVED WAFER SHAPE AND METHOD OF MAKING SAME

Abstract: A semiconductor blank wafer to be used in a final simultaneous polishing step of both wafer surfaces for getting a wafer of superior flatness and surface finish, the wafer having a diametral cross-sectional shape like that of a "dogbone" wherein the wafer is thinner in its medial region than it is in the peripheral region and has rounded edges, this shape resulting from a chemical thinning operation.

Description: This invention relates generally to semiconductor device fabrication, and more particularly to an improved semi-conductor blank wafer to be used in a final polishing step, and the method of making this improved wafer. In the manufacture of very large scale integrated circuit devices a monocrystalline boule is grown with the desired orientation of the crystal axes. This boule is then ground to a cylindrical shape with added flats, or other fiduciary marks. The boule is then sliced into individual wafers. Depending on the surface finish left by the slicing saw, the wafers may, if necessary be ground or lapped to remove the saw marks and to improve the parallelism of the wafer surfaces. The next step is to chemically thin the wafers to further refine the surface finish and to remove any stresses induced by the slicing and/or grinding or lapping operation. Finally, the wafers are polished to the desired thickness to provide highly polished parallel planar surfaces to the wafer. The wafers are then processed to produce integrated circuit chips. As the size of the wafers increases and derivatively the number of chips per wafer, the planarity (or lack thereof) becomes extremely critical. Also, as the number of devices per chip increases, the size of a device and the interconnecting metallizations becomes smaller, even microscopic. As critical as the lack of crystallographic flaws in the wafer is the necessity to have a "perfect" planar surface throughout the wafer. This is necessary because the subsequent device process steps employ photo-lithographic steps. Any non-planarity of the wafer surface will give rise to distortions which will affect the tolerances of the semiconductor devices and in the limit will render them inoperative. Intuitively one would believe that to obtain a "perfect" wafer, i.e. one with two perfectly parallel flat mirrored surfaces, one should attempt at each step, beginning with the slicing of wafers from the boule to maintain the surfaces as parallel planar as possible at each successive step, so that the next following step need only provide minor corrections to the non-parallelism, non-planarity, surface roughness and surface stresses until the required precision is attained. But as a matter of fact, most of the polishing machines, especially two-surface polishing machines as shown in US Patent 3 691 694 and as used in the final wafer-polishing step immediately before processing the integrated circuit chips show a greater ablation in the outer region of the wafer than in the inner section. It is therefore difficult to obtain a "perfect" planar surface throughout the whole wafer, which is particularly crucial for the production of VLSI-Chips. It is also to be noted that it is standard practice in the preparation of wafers for semiconductor device fabrication to chamfer, round or otherwise break the square corners at the edges of the wafer. It is an object of the invention as claimed to provide a semiconductor blank wafer to be used in a final simultaneous polishing step of both wafer surfaces for getting a wafer of superior flatness and parallelism and a method of making same. This is achieved by giving the wafer a "dogbone" cross-section for compensating the inhomogeneous ablation of the polishing machine in one of the steps before the final polishing step, preferably during the chemical etching step. The result is a wafer with superior flatness, which is especially necessary in the steps where the photolithographic masks are applied to the wafer at the production of VLSI-Chips. The invention as claimed will now be described in detail and with respect to the accompanying drawings. Fig. 1 is an exaggerated diametrical cross-section of a wafer illustrating the "dogbone" shape, and Fig. 2 is a schematic representation of the mounting cage for the nested wafers. The improved wafer shape is shown in Fig. 1. This is a diametrical cross-section of a generally disc-shaped semiconductor wafer, with the section being taken along a diameter which does not intersect a fiducial mark. As can readily be seen from the drawing the wafer 10 has a generally "dogbone" shape wherein the thickness in the medial region 12 is less than it is in the peripheral region 14. The corners of the wafer are non-rectilinear having a radius R. It is appreciated that the drawing is not to scale, because the difference in thickness and the corner radii are very small as compared with the gross dimensions of the wafer. To appreciate the magnitude of the difference in thicknesses and of the radius the following is a table of value of a preferred embodiment of each of several different sizes of wafers: The foregoing tabular values are the preferred dimensions within a range of dimensions which will produce a superior wafer after polishing. The surface flatness and finish resulting from the polishing operation will be hereinafter described. It should be noted that the shape shown exaggerated in Fig. 1, and typically dimensioned in the table is the inherent result of the chemical thinning operation. Thus, because of the dynamic flow of the etchant solution with respect to the wafers, the concentration and temperature of the etchant, and the duration of the chemical thinning operation, the resultant smooth transitional curve from minimal thickness at the wafer center to a maximum thickness at the wafer edges will be automatically achieved. The important parameter is the difference in the medial and peripheral thickness. It has been determined through experimentation that the difference (ΔT) between the maximum and minimum can be expressed by the formula If the diameter D is expressed in millimeters and ΔT is expressed in the same dimensions then "a" should be chosen from the range of 5 x 10⁻⁶ to 1 x 10⁻⁴. A value of "a" less than the foregoing range will not produce a wafer of acceptable flatness, and a value of "a" greater than the higher range value will require a longer polishing time to achieve an equivalent surface flatness. For each of several wafer sizes the preferred value of "a" is as follows: It has been repeatedly demonstrated, and documented in the prior art, that square corners on a wafer are undesirable. Square corners tend to fracture unpredictably and the fractures may encroach on the area intended for device fabrication. Therefore, the square corners were intentionally rounded either mechanically or by selective chemical etching. A derivative benefit of the chemical thinning operation to be described is that the square corners are rounded, but not to such an extent that the rounded arc extends into the area intended for device fabrication after the wafer is polished. Referring now to Fig. 2 which illustrates schematically a chemical thinning apparatus. The wafers 10 are nested by edge supports in a fixture 20, which is rotated at selectable speeds about an axis A-A. The fixture 20 with the mounted wafers is totally immersed in an etchant solution contained in an enclosed trough (not shown). Since the wafer profile is a function of the etch rate of the selected semiconductor material, the dynamic flow of the etchant solution over the wafer surface, and the time the wafers are exposed to the etchant, it is desirable to standardize the variable for any given wafer material and size so the process can be replicated with a high degree of precision. The etch rate is a function of the material to be etched, the composition of the etchant and temperature. Therefore, the simplest way to define this variable is to define the range of etch rates which will produce the "dogbone" shape when a nest of wafers is revolved in the solution at a selected speed and time. This then provides a choice of etchants and temperatures. It has been found that an etch rate from 0.10 to 0.53 microns per second, as measured by a sample immersed in a stagnant bath of etchant, is the preferred range. Thus, one can vary the temperature of a given etchant to increase the etch rate or maintain the temperature constant and vary the composition of the etchant to achieve the desired etch rate within the range. It has also been found to be desirable to constantly replenish the etchant in the thinning apparatus and to maintain its temperature within a small range. For doped silicon wafers suitable for semiconductor fabrication, the preferred etch rate is 0.34 microns per second with the bath at a temperature of 55°C. The etchants that have been employed successfully are as follows, with formula 1 being preferred: As has been stated the resulting wafer shape is also a function of the dynamic flow of the etchant over the wafer surface. Intuitively one can appreciate that the flow of the etchant with respect to the wafer surface is a hydrodynamic phenomenon which is propably susceptible to analysis by application of the principles of fluid dynamics. However, rather than attempt this complex analysis and solution, it is preferable to recognize a few fundamental principles and develop a range of process parameters by experimentation that produce the desired results and replicate these parameters for each successive batch of wafers. The first parameter for consideration is the spacing between adjacent wafers. In the limit of zero spacing the etchant will be inhibited from penetrating to the medial region of the wafers. This is obviously an inoperative choice if the wafers are to be chemically thinned more in the medial region than at the peripheral region. The opposite limit of "infinite" spacing between wafers is equally impractical because it would limit the number of wafers that could be batch processed. Therefore, for maximum production efficiency it is desirable to select an inter wafer spacing as small as possible which will produce the requisite "dogbone" shape. It has been found, again by experimentation, that the preferred spacing (S) between wafers lies within the range of values defined by the formula It will be noted that the wafer thickness does not appear in the foregoing relationship, because "S" is the distance between adjacent surfaces, not the center-to-center distance. The perturbation of the etchant is primarily affected by the spacing between the surfaces and very little if any by the wafer thickness, at least for the range of semiconductor wafers useful for fabricating semiconductor devices. The final variable is the speed of rotation of the encaged stack of wafers. The rotational speed cannot be expressed as a function of wafer diameter, inter-wafer spacing, etch rate and/or etch time. However, it has been found through experimentation that the speed range and optimum speed are as follows: It has been demonstrated, again through experimentation, that the optimum process parameters for a variety of different wafer sizes are as follows: The finished dimensions of the foregoing wafers after simultaneous double surface polishing in a machine such as that described in US Patent 3 691 694 are as follows (with reference to Fig. 1) where ΔP is the deviation from parallelism of the two surfaces, measured with a non-contacting capacitive thickness gange with an accuracy of ± 0.25 µm (± 0.01 mil). Illustrative of the success of this process for producing flat wafers, the following table represents interferometer-measured values of flatness and surface finish for wafers polished from a "dogbone" wafer blank. As illustrative of typical wafer processing from slicing through final polishing, the following dimensions are typical for two widely used thicknesses of 80 mm (3 inch nominal) wafers and 125 mm (5 inch nominal) wafers. Thicknesses are measured at end of process step While the process parameters for a preferred process have been set forth, it is apparent that combinations of other parameters may also produce a "dogbone" wafer shape. However, the preferred values have been demonstrated to produce consistent results in a production evironment where production time, and derivatively cost is a prime consideration in the selection of parameters.

Claims: 1. A semiconductor blank wafer, to be used in a final simultaneous polishing step of both wafer surfaces, characterized by a diametral cross-sectional shape wherein a) the thickness of the wafer varies smoothly from a thin portion in the medial region of the wafer to a thicker portion at the peripheral region of the wafer, and; b) the edges of the wafer are rounded whereby the cross-section can be visualized as having a "dogbone" like shape (Fig. 1). 2. The wafer as claimed in claim 1 wherein the difference in thickness (ΔT) between the thinner medial region and the thicker peripheral region satisfies the following relationship: 3. The wafer as claimed in claim 1 or 2 wherein the edges of the wafer are rounded with a radius of curvature (R) satisfying the following relationship: 4. The wafer of claim 3 wherein the radius of curvature (R) is about 50 µm. 5. The wafer as claimed in one of the preceding claims wherein the shape is produced by a chemical thinning operation. 6. The wafer as claimed in claim 5, wherein the chemical thinning comprises the steps of: a) Including the wafer coaxially among a nest of spaced apart wafers wherein the spacing (S) between the wafers has a dimension equal to b) Immersing the thus-nested wafers in an etching solution having an etch rate for the semiconductor material in the range from 0.10 to 0.53 microns per second. c) and rotating the thus-immersed wafers at a speed of from 50 RPM to 110 RPM for a time between 2 and 5 minutes. 7. A method of making a wafer having a "dogbone" like shape as recited in one of the preceding claims characterized in that the wafer is produced by a chemical thinning operation. 8. The method as claimed in claim 7, wherein the spacing (S) between the wafers has a dimension equal to 9. The method of one of the claims 7 or 8, wherein the preferred spacing between wafers having a nominal diameter of 3 inches is 3 mm. 10. The method of one of the claims 7 or 8, wherein the preferred spacing between wafers having a nominal diameter of 5 inches is 7 mm.

Inventors: HAUSE, JAMES ROBERT, MENDEL, ERIC
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1985
Main classification: H01L21
IPC codes: H01L29, H01L21