MICROPROCESSOR SYSTEM

Abstract: A microprocessor system comprises a microprocessor having multiplexed address/data bus communicating with a plurality of memory and input/output devices. A demultiplexing register allows to demultiplex the microprocessor address/data bus, while a decoder allows to select, according to the most significant address bits, one of the system devices, during a microprocessor external operation. The system output devices comprise a plurality of TTL outputs whose inputs are connected to the output of a demultiplexing register where, during a microprocessor external operation, an information is latched representative of the less significant address portion. A datum information transfer to an output gate TTL is obtained by having an external operation executed by the microprocessor such that the most significant address bits select such gate and the less significant address portion represents the datum to be transferred.

Description: The present invention relates to a microprocessor system and, more particularly, to a microprocessor system having address/data bus multiplexed and provided with a plurality of output gates TTL. Several microprocessors present a multiplexed address/data bus to reduce the total number of external connection pins. A corresponding system is known from an article in ELECTRONIC DESIGN, vol. 26, no. 11, p. 116: "8-bit single-board microcomputer ASC/80". During an external operation performed by such microprocessors (for instance a memory access or an input/output operation) both addresses and data are present, during different instants of the machine cycle, on the channel or multiplexed bus. The selection between the two kinds of information is performed with the use of suitable control signals supplied by the microprocessors themselves. The only restraint for the use of a microprocessor with multiplexed bus is the demultiplexing process of such bus in order to enable its interfacing with standard memory circuits. Demultiplexing is generally obtained by means of a register latching the information representative of an address in correspondence of a suitable microprocessor control signal. Since the latching instant and for the whole remaining machine cycle the address/data bus changes to a data bus only. The microprocessors, embodied with MOS (Metal-Oxide-Semiconductor) technology, provide a limited capacity of static load (fan out) to their own bus lines. The output logic gate coupled to each of said lines can, in fact, output a little current amount. If the line is overcharged it can be damaged by overheat and it may work incorrectly. The most of the microprocessor manufacturers point out the maximum static load of the bus lines. Typical static load features consists of a single TTL load. Generally such load features are sufficient for microprocessor systems embodied on a single plate where the microprocessor is directly interconnected through the data bus and the address bus to memories and peripherals of its own MOS family. However, in systems where the microprocessor has to drive several TTL inputs the fan-out of the microprocessor bus lines must be increased by suitable insertion of additional drivers between bus lines and TTL loads. With reference to the mentioned case and when the used microprocessor is provided with a multiplexed address/data bus, the present invention avoids the insertion of any drivers on the data bus. In fact, according to the present invention, the inputs of the output gates TTL are not directly connected to the lines of the multiplexed address/data bus but to the outputs of the demultiplexing register which, therefore, acts also as driver for the system TTL output gates. As the information present on the outputs of the demultiplexing register formally stands for addresses, the microprocessor task is to treat such information as data to be transferred to a preestablished output gate TTL. This is obtained by mapping the output gates TTL as memory and accessing one of such gates with a fictitious memory access operation. The invention is set out in claims 1 and 2. These and other features will appear clearly from the following description of a preferred embodiment of the present invention and from the enclosed drawing where: Figure 1 shows a microprocessor system with multiplexed address/data bus object of the present invention. The microprocessor system of fig. 1, which may be embodied on a single board, can for instance stand for the control circuitry of a dot matrix printer. It is constituted by: a microprocessor 1, for instance microprocessor 8085 manufactured by INTEL circuital block 2 comprising a read/write working memory RAM 2A and a plurality of programmable input/output gates 2B, ..., 2N. Block 2 can be implemented with one or more integrated circuits manufactured by INTEL with code 8155 of the same logic family of microprocessor 8085. For sake of simplicity, during the present description assumption will be made that circuital block 2 is constituted by a single circuit 8155; a read only control memory 3 devoted to contain the control programs which can be executed by microprocessor 1; control memory 3 can for instance be implemented with one or more integrated circuits manufactured by INTEL with code 8316 or 2716 of the same logic family of microprocessor 8085. For sake of description simplicity assumption is however made that the control memory is constituted by only one of such circuits; a data communication interface 4 designated to serially receive and transfer data on terminals RD or TD respectively. Interface 4 can for instance be implemented with integrated circuit manufactured by INTEL with code 8251 of the same logic family of microprocessor 8085; a plurality of TTL output gates 5A, ..., 5M for instance implemented with integrated circuits manufactured by TEXAS with code 74LS377; a demultiplexing register 6 for instance implemented with integrated circuit manufactured by TEXAS with code 74LS373; a decoder 7 designated to select the suitable system unit to/from which microprocessor 1 wants to transfer/receive information. Decoder 7 can for instance be implemented with one or more integrated circuits manufactured by INTEL with code 8205. Microprocessor 1 has 8 output lines A8÷A15 where the 8 most significant bits of the address are provided during an access operation to one of the units constituting the system. The 8 less significant bits of the address are provided on the bidirectional lines AD 0÷7 at the beginning of the access operation. Control signal ALE in output from microprocessor 1 states, at logical level 1, that the information present on lines AD 0÷7 is representative of the address bits A0÷7. In a subsequent phase of the access operation to one of the system units, when signal ALE is at logical level 0, an information is present representative of the datum received or transferred by the micrprocessor. Signals ( ) in output from microprocessor 1 indicates, when at logical level 0, that the datum is to be received (transferred) by the microprocessor. A suitable number of address lines A8÷15 are connected to the intputs of decoder 7 (for instance lines A11÷15 if assumption is made to map the memory space available according to 2K locations blocks). Decoder 7 provides in output a plurality of signals S A , S B , ... S R , intended to select the system unit to (from) which the microprocessor wants to transfer (receive) an information. The address/data lines AD 0÷7 are connected to the inputs of register 6 which receives on its control input a signal ALE. When ALE rises to logical level 1, register 6 latches the information present at its inputs making therefore available on its outputs the information representative of address bits A0÷A7. Register 6 outputs are connected to the inputs of output gates 5A, ... 5M, and to the inputs ADDL of the less significant address bits of control memory 3. Besides, inputs ADDH receiving the most significant bits of memory 3 are connected to a suitable number of address lines A8÷A15. Microprocessor pins AD0÷7 are further connected to the multiplexed pins ADD/DATA of circuital block 2 and to pins DATA of both control memory 3 and of communication interface 4. As such units belong to the same logic family of microprocessor 1 they can be controlled by microprocessor 1 without driving problems. Signal ALE besides to the enabling input of register 6, is also applied to a suitable control input of circuital block 2 and provides the latching of information present on pins ADD/DATA in a demultiplexing register internal to circuit 2, when this circuit is selected. Circuit 2 further receives a suitable information, for instance address bit A8, on a control input IO/ M . Such information states, if at logical level 0 (1) that the unit involved in the data transfer with microprocessor 1 is memory RAM 2A (one of the gates 2B, ..., 2N) Signals , , in output from microprocessor 2, are applied to two control inputs of circuital block 2 and communication interface 4. Signal is further applied to a control input of control memory 3 and signal to the timing inputs of output gates 5A, ..., 5M. It can be now shown how microprocessor 1 loads a datum into one of the output gates 5A, ... 5M. This is possible by having a memory write operation executed by microprocessor 1 into a location whose address portion A8÷A15 selects the desired output gate and whose address portion A0÷A7 is representative of the datum to be transferred to such gates. With reference to microprocessor 8085, to obtain such result in an immediate way, the microprocessor has to perform for instance a microinstruction "STA addr" (storing of the accumulator content into the memory location "addr") where the value of the two bytes constituting the address information "addr" is given according to the above mentioned criterion. It is also possible the transfer of the content of any of the microprocessor registers to a pre-established output gate. However, in this case, before the processor execute the fictitious memory access operation, it must transfer to its internal address register both the information selecting the output gate and the content of its internal register containing the datum to be transferred. For instance, with reference to microprocessor 8085 again, a simple routine to transfer the content of accumulator A to an output gate having address XX, may be: MVI H,XX; transfer of address XX to a register H internal to microprocessor 8085 MOV L,A; transfer of accumulator A content to a register L internal to the microprocessor MOV M,A; transfer of the accumulator content to the memory location whose address is contained into register H (most significant address byte A8-A15) and L (less significant address byte A - A7). It is clear that with this simple routine the information contained into accumulator A, which must be transferred to an output gate, is firstly transferred to internal register L generally devoted to store an address portion and, with the final microinstruction MOV M, A such information is loaded into register 6 and then transferred to the output gate which is selected according to the content of register H. The information appearing on pins AD0-7 in a second phase of instruction MOV M,A is not important for the transfer and it is actually ignored by the selected output gate and by the other system components.

Claims: Microprocessor system comprising: microprocessor (1) having a first group of address lines internally connected to the output of a first address register H, a second group of multiplexed address/data lines internally and selectively connected to the output of a second address register L or of an accumulator and a plurality of control lines, a demultiplexing register (6) having inputs connected to said second group of multiplexed lines and outputs, a control memory (3) having address inputs connected to the outputs of said demultiplexing register and to one line at least of said first group, having information outputs connected to said second group of lines, and a selection input, a plurality of TTL output gates (5A..5M), each provided with data inputs, a decoder (7) having inputs connected to a subset of lines of said first group and a plurality of outputs, each of them respectively connected to the selection input of said control memory said system characterized in that each of said TTL output gates comprises one enabling input connected to said microprocessor, a plurality of said decoder outputs is connected to corresponding output gates TTL, and further characterized by direct connection between the outputs of said demultiplexing register and the data inputs of said TTL output gates, and in that said address register L, intended to contain an address portion, is loaded with data information to be transferred to one of said output gates during the time slot used to transfer address information. In a microprocessor system comprising: a microprocessor (1) having a first group of address lines internally connected to the output of a first address register H, a second group of multiplexed address/data lines internally and selectively connected to the output of a second address register L or of an accumulator and a plurality of control lines, a demultiplexing register (6) having inputs connected to said second group of multiplexed lines and outputs, a control memory (3) having address inputs connected to the outputs of said demultiplexing register and to one line at least of said first group, having information outputs connected to said second group of lines, and a selection input, a plurality of TTL output gates (5A..5M), each provided with data inputs, a decoder (7) having inputs connected to a subset of lines of said first group and a plurality of outputs, each of them respectively connected to the selection input of said control memory said system characterized in that each of said TTL output gates comprises one enabling input connected to said microprocessor, a plurality of said decoder outputs is connected to corresponding output gates TTL, and further characterized by a direct connection between the output of said demultiplexing register and the data inputs of said TTL output gates, the information transfer method from said microprocessor to one of said output gates TTL comprising the following steps: loading said address register H with an information selecting an output gate, loading, during the same machine cycle, said address register L with the information to be transferred, executing a fictitious memory transfer operation to the address specified by the content of said address register H and L.

Inventors: COSTANTINI, GIORGIO
Applicants: BULL HN INFORMATION SYSTEMS ITALIA S.P.A.
Application year: 1985
Main classification: G06F13
IPC codes: G06F13