METHOD FOR DRIVING A GAS DISCHARGE PANEL

Abstract: An AC driving surface discharge display panel has a ma­ trix arrangement of a plurality of display dots each of which comprises a pair of display cell and selection cell. Firstly, all display cells on a selected line are simultaneously fired, by ap­ plying a firing voltage between pairing parallel display elec­ trodes defining said display cell line. Next, a discharge informa­ tion stored unwanted display cell among said fired display cell line is selectively erased by discharging an adjacent pairing se­ lection cell. An address sequence of the present invention comprising the line firing step and selective erasing step is performed with wide operation margin.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an improved method for driving an AC driven gas discharge display panel and in more detail, to a new method for stably driving a surface discharge type or monolithic type gas discharge panel with a wider operation margin. Description of the Prior Art As a kind of a gas discharge panel known by the name of an AC plasma display panel, there is a surface discharge type display panel utilizing lateral discharges between adjacent electrodes. Basically, as is disclosed in the U.S. Patent US-A-3,646,384, for example, granted to F.M. Lay, a gas discharge panel of this type has the structure that the electrodes defining discharge cells are disposed with coverage by dielectric layers only on the one substrate among a pair of substrates arranged opposingly through the space filled with discharge gas. Therefore, this structure provides advantages that requirement on accuracy of gap of the space filled with discharge gas is remarkably alleviated and moreover multi-color display can be realized easily by coating internal surface of the other substrate for covering to the substrate being provided with said electrode with the ultraviolet ray excitation type phosphor. However, with the structure of the conventional panel, satisfactory life time and operating margin can not be attained, because of the damage of the dielectric layer due to the concentration of the discharge current at the portion corresponding to the edges of the electrodes. Thus, the inventors of the present invention have proposed a three-electrode type AC surface discharge panel providing separated cells for display and cells for selection. An example of structure and operation of this gas discharge panel is described in detail in EP-A-0 135 382 , which was published on March 27 th , 1985, and therefore falls under Article 54(3), EPC. The three-electrode type surface discharge panel separating the display cell - select cell is very effective for realizing long operating life of the panel. Moreover, an internal decoding function is easily provided by multiple connection of display electrode pairs and thereby the drive circuit is very simplified. However, in said separated display cell - select cell type panel, a picture element is formed by a pair of display cell and select cell. Therefore, it is difficult to acquire the practical operation margin in the write address method disclosed in our prior patent application and it has been probable that erroneous operation is generated by dispersion of power supply and aging of panel characteristics. Further, in said write address method, the simultaneous addressing at line by line can not be attained in the case of the display electrodes being multiply connected. US-A-4 011 558 discloses a DC type two-electrode gas discharge panel having a structure with the display cells defined at the intersecting points of two crossing electrodes. It discloses further a driving method for this type of a DC two-electrode gas discharge panel. SUMMARY OF THE INVENTION With the aforementioned background, it is an object of the present invention to provide an improved display addressing method having a wide range of operation margin for an AC surface discharge display panel. It is another object of the present invention to provide a new driving method which is stably addressing with a low volatage to the three-electrode type surface discharge display panel with a pair of separated display cell and select cell corresponding to the picture elements. It is a further object of the present invention to provide a driving method which makes address on the basis of line-at-a-time address sequence to the three electrode type surface discharge matrix panel having the multiple-connected display electrode pairs. It is still a further object of the present invention to provide an improved method for driving the three-electrode type surface discharge panel with simplified and economical circuit structure. These objects are solved by the features of claim 1. The present invention is also characterized in that a sustain voltage waveform to be applied to said display cells is applied as an asymmetrical composite waveform of a sustain voltage having a high amplitude to be applied to the one display electrode forming said selection cells and a sustain voltage having a low amplitude to be applied to the other display electrode. The present invention is further characterized in that the operations for generating discharge to all display cells of said dot line to be selected are sequentially applied to the respective dot lines, and this fired display cells line scanning is carried out at least one dot line preceding the dot line where selecting operation is applied to the selection cells of said unwanted dots. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial perspective view indicating the structure of surface discharge type display panel to which a method for driving a panel of the present invention is applied. Fig. 2 is a plan view of electrode arrangement. Fig. 3 is a sectional view along the line III-III' of Fig. 2. Fig. 4 shows an electrode configuration schematically indicating the discharge cell arrangement for explaining a driving method of the present invention. Fig. 5 is an example of a drive voltage waveform to be used in the present invention. Fig. 6 shows an electrode arrangement of the multi-connected panel. Fig. 7 shows voltage waveforms for driving the panel shown in Fig. 6. Fig. 8(a) and (b) are examples showing the states of each line in one block for explaining the line address sequence of the present invention. Fig. 9 shows voltage wave-forms for driving the electrodes in accordance with the states of Fig. 8. Fig. 10 shows experimental data of operation margin obtained by the present invention. Fig. 11(a) to (h) show the selecting conditions of discharge cells corresponding to the sequences of address operation according to a modified embodiment. Fig. 12 show the voltage waveforms for realizing the address sequences of Fig. 11. Fig. 13 shows a typical driving circuitry for realizing the driving method of the present invention. Fig. 14 shows the operation margin obtained by addressing method of Fig. 11. DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the structure of three-electrode type AC surface discharge display panel to which the driving method of the present invention is applied is explained. With reference to Figs. 1, 2 and 3, a plurality of pairs of display electrodes 11 each consisting of two electrodes, are arranged in the vertical direction on a lower glass substrate 10 which functions as the electrode support substrate and the selection electrode 13 extending in the horizontal direction and the separator electrode 14 to be used under the floating condition are provided on such substrate through a dielectric layer 12 consisting of low melting point glass. On the selection electrode and separator electrode, a surface layer 15 consisting of magnesium oxide (MgO) is formed in the thickness of several thousands or Angstrom (1 Angstrom = 10⁻¹⁰ m). Moreover, the gas space 17 surrounded by the upper glass substrate 16 for the cover is provided at the upper part of such surface layer. It is also permitted that a phosphor material which emits light when excited by the ultraviolet ray is provided at the internal surface of the cover glass 16. The display electrode pair typically indicated by the symbol 11 is composed of the adjacent two display electrode pairs of X₁, Y₁ and X₂, Y₂ as is more obviously shown in Fig. 2 and each display electrode pair is provided with discharge areas x and y which are projected towards each other so that they are adjacently located. Moreover, the selection electrodes W₁, W₂ typically indicated by the symbol 13 are also provided crossing the area adjacent to the discharge areas x and y and the separator electrode 14 under the floating condition is provided along said selection electrode in the side separated from said discharge areas. Thus, the selection cells T are respectively formed corresponding to the intersecting points of the selection electrodes W₁, W₂ and the one display electrodes Y₁, Y₂and the display cells K are formed between the discharge areas x, y of each display electrode pair, in the vicinity of said selection cells T. Namely, the picture element PIXEL of one dot is formed by a pair of adjacently located display cell K and selection cell T defined by the three kinds of electrodes X, Y and W. In such a panel structure having three kinds of electrodes, discharge of selection cell T largely affects the adjacent display cell K due to the coupling of space charges or the spread of wall charges. Namely, discharge at the selection cell T triggers discharge at the display cell K as is described in the prior application No. EP-A-0 135 382. On the other hand, discharge at the selection cell T causes a ceasing of discharge at adjoining display cell K, namely erasure of information being stored in the display cell in the form of wall charge. The basic concept of the present invention lies in the erasing address sequence which erases discharge of unwanted display cells for the display in the once fired display cells line by utilizing vicinity erasing function by discharge of selection cells. In this case, firing of display cells line is carried out by applying a firing voltage to the display electrode pair. Next, operations are explained in detail by referring to Fig. 4 and Fig. 5. Fig. 4 shows an electrode arrangement as an example of basic configuration of a surface discharge display panel having four (2 x 2) display cells (PIXELS). X₀ is the one display electrode group connected in common, Y₁ and Y₂ are the other display electrodes forming a pair with electrodes X₀ respectively. The selection electrodes W₁ and W₂ are arranged in such a direction as to cross the display electrode through the insulating layer. Thereby, the selection cells T₁∼T₄ are formed at the intersecting points of the display electrodes Y₁, Y₂ and said selection electrodes W₁, W₂ and moreover the display cells K₁∼K₄ for displaying information are formed on the display electrode pair located in the vicinity. Fig. 5 shows voltage waveforms to be applied to the respective electrodes X₀, Y₁, Y₂, W₁, W₂ in Fig. 4, composite voltage waveforms applied to the pairing display electrodes Y₁ ∼X₀, Y₂ ∼X₀, and equivalent voltages namely wall voltages of positive and negative wall charges which are alternately accummulated on the wall surface of dielectric material due to the discharge of display cells K₁∼K₄ with the corresponding symbols. In these waveforms, the passage of time is plotted from the left to the right. The following explanation is based on the condition of obtaining the display pattern where the cells K₂ and K₃ among the display cells K₁ ∼K₄ are fired and K₁ and K₄ are not fired. The voltages shown in Fig. 5 are applied respectively to the electrodes X₀, Y₁, Y₂, W₁, W₂. Namely, at the timing A₁, the one line firing pulse W₁ is applied to the one display electrode Y₁ and a composite voltage |V₁ + V w | between the pairing display electrodes X₀ and Y₁ exceeds the firing voltage of display cell. As a result, the display cells K₁, K₂ of the first line start discharge. With such discharge, the wall charges represented by wall voltages indicated as K₁, K₂ shown in Fig. 5 are accummulated on the wall surface of dielectric material corresponding to the display cells K₁, K₂ of the first line. Next, at the timing E₁, the selection pulse P₁ in the same width as the sustain voltage is applied to the selection electrode W₁ nearest to the unwanted display cell K₁ for the display pattern on the first line. An amplitude of V a of this selection pulse P₁ is set to the level which causes discharge of the selection cell T₁ by a composite voltage |V a + V₂| with the sustain voltage -V₂ to be applied to the display electrode Y₁. In this case, the wall charges accummulated by discharge of adjacent discharge cell K₁ are spreading on the wall surface of dielectric material of selection cell T₁ and such wall charges promotes generation of discharge of selection cell T₁. Therefore, discharge at selection cell occurs at a lower selection voltage than that in the case where the display cell K₁ is in the not firing condition. When a composite pulse p₁ + q₁ for selection is applied to the selection cell T₁, discharge occurs at the rising edge of said pulse. The space charges during such discharge neutralizes the wall charges accummulated on the wall surface of dielectric material of the adjacent display cell. Thereafter, the wall charges generated by preceding selection discharge are accummulated on the wall surface of dielectric material of selection cell T₁, but when a composite pulse applied across electrodes W₁ and Y₁ falls, self-discharge occurs due to the avalanche phenomenon of the wall charge itself. This self-discharge further reduces accummulated wall charges of adjacent display cell and simultaneously wall charges of the selection cell disappear by themselves. Attenuation profile of wall voltage during such process is indicated in a circle R of Fig. 5. Particularly, immediately after the selection pulse P₁, a voltage applied to the display cell K₁ is zero. In this timing, self-discharge generated by the falling edge of a pulse to be applied to the selection cell effectively approximates the wall charge to zero. During this period, application of sustain voltage for the display electrode X₀ is paused during the period d₁ in order to attenuate wall charges. Thereby, discharge of display cell K₁ can be suspended accurately. Meanwhile, the wall charges generated by the preceding discharge is still held at the display cell K₂ on the same display electrode pair since discharge for selection is not generated on the selection cell T₂ forming a pair with the cell K₂. Accordingly, when the sustain voltage is applied again across the display electrodes of the first line forming a pair, discharge for display is regenerated continuously at the not erased display cell K₂. The addressing of the first line completes with the line firing step, selection erasing step and sustain voltage re-supply step as explained above. Thereafter, for the addressing of the second line, a firing pulse W₂ is applied across the display electrode pair X₀ and Y₂ at the timing A₂ in Fig. 5 and thereby all cells K₃, K₄ on the display electrode pair X₀-Y₂. In order to leave the discharge of display cell K₃ at the timing E₂, the selection pulse p₂ is applied only to the selection electrode W₂ adjacent to the unwanted display cell K₄ to be erased to generate discharge at the selection cell T₄, and thereby wall charges of display cell K₄ are reduced and the display cell K₄ is erased during the period d₂ where the sustain voltage is zero. As a result, discharge is continued only at the display cell K₃ on the display electrode pair X₀-Y₁. The wall voltage is lowered by interfering discharge of display cells with discharge of adjacent selection cells and thereby display discharge of unwanted picture elements can be suspended accurately. Next, as the second embodiment of the present invetion, a method for driving a surface discharge display panel having internal decoding function through the multiple connection of display electrode pairs is explained. Fig. 6 shows a schematic diagram of a panel which has a simplified electrode arrangement and has eight PIXELS (2 x 4), wherein a number of external connecting terminals can be reduced for a number of electrodes. With reference to Fig. 6, all display electrode pairs are divided into plural groups (two groups, in Fig. 6), the electrodes X₁, X₂ are formed by connecting in common the one display electrodes forming a pair for each group, the electrodes Y₁, Y₂ are formed by connecting in common the electrodes of the same sequence of each group of the other display electrodes, and the display cells K₁₁, K₁₂, ....K₄₂ are formed with such display electrode pairs for the sustain discharge. Meanwhile, the selection cells T₁₁, T₁₂, ...., T₄₂ formed at the intersecting points of the one display electrodes Y₁, Y₂ and selection electrodes W₁, W₂, W₃ are provided adjacent to the display cells K₁₁, K₁₂, ...., K₄₂ and the discharge of it affects the wall charges and pace charges of display cells. Fig. 7 shows examples of driving waveforms for the line sequential address of said multiple connected panel. The basic purpose of this second embodiment is that realizing the application of a low voltage IC driving element for driving the selection electrodes W₁, W₂. The waforms shown in Fig. 7 are used, under the supposition that the panel having the configuration shown in Fig. 6 is in the operation including fired cells and non-fired cells, for newly firing the display cell K₂₂ of the second line formed between the display electrode pair X₁ and Y₂ and additionally not firing the cell K₂₁. Namely, the waveforms X₁, X₂, Y₁, Y₂ are voltage waveforms to be applied to the display electrodes X₁, X₂, Y₁, Y₂. The waveforms X₁-Y₁, X₁-Y₂, X₂-Y₁, X₂-Y₂ are composite voltage waveforms applied across the display electrodes and the waveforms K₂₁ and K₂₂ indicate wall voltages accumulated as a result of discharge of cells K₂₁ and K₂₂. Moreover, the waveforms W₁, W₂ indicate selection pulses to be applied to the selection electrodes W₁ and W₂. When the pairing firing pulses W₃ and W₄ are simultaneously applied to the pairing display electrode X₁ and Y₂ at the timing A₃, all cells on the display electrode pair X₁-Y₂ fire with the pulse having the peak to peak value of |W₃ + W₄| exceeding the discharge voltage. After two cycles for stabilization, the selection pulse p₃ is applied to the selection electrode W₁ to which the display cell K₂₁ not selected, namely to be erased belongs but any voltage is not applied to the selection electrode W₂ to which the selected display cell K₂₂ belongs. Thereby, the cell K₂₁ loses wall charges and is erased as shown in a circle R of wall charge diagram K₂₁ and the cell K₂₂ does not lose the wall charges and restarts the discharge depending on the sustain voltage applied again. Particularly, during the period d₃ of the voltage waveform X₁-Y₂ applied to the cell to be erased, a cell voltage is zero and at this time discharge by the falling edge of the composite selection voltage p₃ + q₃ triggers self-erasure of wall charge, resulting in erasure with less residual wall charges. In succession, operations of cells other than those described above are also investigated. Other cells on the display electrode Y₂ to which large asymmetrical selection pulses W₄ and q₃ are applied may receive the largest influence. Since the selection cell T₄₁, for example generates erasing discharge for selection by receiving the pulses p₃ and q₃, display cell K₄₁ is also erased as in the case of cell K₂₁, if any means is not given. But since a supplemental selection pulse r₃ is applied, immediately after the selection pulses p₃ and q₃, to the sustain electrode X₂ at the cell K₄₁, a rising amplitude f which is enough for redischarge can be obtained immediately after the selection pulse between the display electrode pair X₂ and Y₂. Thereby, discharge at cell K₄₁ can be continued and new wall charge can also be obtained. Display discharge of cells K₁₂, K₃₂, K₄₂ related to the selection electrode W₂ among other cells is not disturbed because the selection pulse p₃ is not applied. The discharge condition of the remaining cells K₁₁, K₃₁ related to the selection electrode W₁ to which the selection pulse is applied is not changed because the pulse which triggers discharge at the one display electrode Y₁ is not applied even at the timings of A₃ and E₃.. The asymmetrical pulse used in this method realizes reduction of address voltage because of the reason explained below. The display cell K₂₁ fired at the timing A₃ in figure 7 is erased because an erasing discharge is generated at selection cell T₂₁ by a composite voltage of wall voltage formed previously at cell K₂₁ and applied voltage pulses q₃ + p₃. The one voltage q₃ among the voltages causing erasing discharge has a large peak value and therefore the value of pulse P₃ which is applied from selection electrodes side can be set so much lower. In this embodiment, voltages are set as follow; V₂ = -160, V₁ = -100, V W = +80. At this time, normal address operation has been attained with the range of V p = +20 ∼ 50. Accordingly, the selection electrode can be driven with a voltage of 30V and a low voltage IC which can be manufactured easily is put into the practical use. A third embodiment which has improved said erasing adress method is explained hereunder. This third embodiment is characterized in that one line firing sequence is precedingly provided for the erasing address sequence. Fig. 8(a) and (b) are examples showing the states of each line in one block having 64 PIXELS (8 x 8) for explaining the line address sequence of the present invention. Fig. 8(a) shows the display condition before one selecting operation cycle of Fig. 8(b). In Fig. 8, circles in the vicinity of electrode intersecting points indicate the firing display cells and the not fired display cells are not encircled. In Fig. 8, the eight(8) display electrodes X i (i = 1, 2, ..., 8) are connected in common as one group and parallel Y i are arranged on the same plane, forming pairs with X i and Y i and the display cell is formed in the vicinity of the selection electrodes W j (j = 1, 2, ..., 8) which cross over them, separated through an insulator as has already been explained in connection with Fig. 1. If the address scanning is carried out sequentially from the lower electrode number i for simplification, a waveform shown in Fig. 9 must be applied as an example. In Fig. 9, the upper most waveform represented by the symbol t i indicates the timing of erasing half-selection pulse to be applied to the selection electrode W j (when firing and erasing is realized by applying the pulse to the pairing matrix electrode, respectively the one pulse is called a half-selection pulse), and the erasing half-selection pulse is applied to the selection electrode adjacent to the display cells which does not require the display on the basis of line sequential and thereby erasing address operations for each line is achieved. On the other hand, a common waveform X s in Fig. 9 is applied to the selected group of X side display electrode X₁ to X₈ and the waveform Y i is applied to the electrode Y i respectively. Further, the bottom waveform X n in Fig. 9 is applied to the group of non-selected X side display electrodes which is not shown. In contrast waveform X s with X n , it is remarked that the selective sustain pulses Ps for selectively reversing the polarity of wall voltage being applied to selected X electrode group at the timing prior to the application of the erase selection pulse. Here, the pulses V x3 , V y3 among the all cells firing pulses V xi and V yi simultaneously fire all cells on the third line corresponding to the display electrode pair X₃ - Y₃. In the same way, pulses V xi and V yi fire all cells on i-th display electrode pair by respective composite voltages. After the period T f3 where wall voltage grows sufficiently, the erasing half-selection pulse V e3 is applied to the display electrode Y₃ corresponding to the erasing selection timing t₃, while the other erasing half-selection pulse is applied to the selection electrode W i having the display cells to be erased at the timing t₃, and as explained above, unwanted display cells on the third line electrode pair X₃, Y₃ can be erased. During such firing and erasing of the third line, both firing pulses V x4 and V y4 are applied to the display electrode of 4th line and thereby all cells of 4th line are fired before completion of address to the 3rd line. The wall charges remaining at the display cells to be erased by the erasing operation of 3rd line are absorbed by preceding discharge of plural cycles of display cells of 4th line in the all cells firing condition and cells are erased more accurately. Fig. 10 shows experimental data of operation margin. The horizontal axis indicates an erasing voltage to be applied to the selection electrode and the vertical axis indicates a sustain voltage applied to the display electrode, showing the operable range. In Fig. 10, the region enclosed by the curve I indicates the operation range in case the pre-fire scanning system explained as the third embodiment is employed. The region enclosed by the curve II indicates the operable range in the erasing address system described in the first embodiment. These data show the operation examples of surface discharge panel of 0.6 mm dot pitch having the PIXELS of 240 lines x 80 dots. The display electrode pairs of 240 lines comprise 15 groups of X electrodes and 16 groups of Y electrodes each of which is multiply connected. Between the display electrodes and selection electrodes, a dielectric material layer in the thickness of 12 µm is provided and the surface of the selection electrode is coated with a thin film of magnesium oxide in the thickness of 0.4 µm. The gas space is filled with a gas mixture of Ne and 0.2% Xe in the pressure of 500 Torr (1 Torr = 1,333 x 10² Pa). As is obvious from Fig. 10, a wider operation margin can be obtained by the addressing method of the pre-fire scanning system. There are modifications of the addressing method mentioned above and one of them is explained hereunder by referring to Figs. 11 - 14. Fig. 11 (a), (b), ... (h) show the selecting conditions of discharge cells corresponding to the procedures of address operation of a display panel of 9 x 5 dots with matrix connection where nine display electrode pairs are divided into three groups in unit of three electrodes. Fig. 12 shows the waveforms to be applied to the electrode of such panel. The heading symbols A i (i is an integer, 1, 2, 3 ...., n), X i and Y i are electrode names and voltage waveforms respectively applied to the selection electrode, the one display electrode X and the other display electrode Y. For the selection electrode A i , a positive selection pulse with amplitude V a is used, for the display electrodes X i and Y i , an ordinary sustain pulse is used at the display cell selection timing and the sustain pulse extracting waveform at the non-selection timing. In Fig. 11, the electrodes among A i , X i and Y i enclosed by double circle (O ○) are executing the write operation, the electrodes enclosed by circle ( ○) are receiving the selective sustain pulse, and the electrodes not enclosed are receiving a sustain voltage with extraction of waveform. First, as shown in Fig. 11 (a), a write pulse V W is applied from the Y electrode side, for example, as shown in the timing T₁ of Fig. 12, across the first common display electrode X₁ and all Y electrodes forming the pair with said electrode. Thereby, all display cells of a group where the display electrode X₁ forms the one electrode are fired by a composite voltage with the voltage -V s applied from the X electrode side. Next, as shown in Fig. 11(b), the selection pulse V a is applied to the selection electrode A₁ including the three selection cells 21, 22, 23 formed between the one display electrode X₁ and the selection electrode A₁ at the timing T₂ of Fig. 12 in order to discharge three selection cells mentioned above. It will be supposed that the discharge at display cell 31 formed by the pairing display electrodes X₁, Y₁ and associated with the selection electrode A₁ is left for display. After the selection pulse V a is applied to the selection electrode A₁, the sustain pulse Ps is selectively applied to the display electrode Y₁ during the period of timing T₃ in order to continue the discharge. However supply of the sustain pulse to the non-selected electrodes Y₂, Y₃ is suspended, therefore the wall charges and space sharges at display cells 32, 33 to be erased are reduced by recombination of them utilizing the self-discharge which is generated at the falling edge of said selection pulse V a . As a result, the display cells 32, 33 can be erased. At the timing T4, the sustain pulses are applied between all X electrodes and Y electrodes and thereby all firing cells are maintained as shown in Fig. 11(c). Then, if it is supposed that only the lowest cell 36 of the display electrode X₁ among the three selection cells 24, 25, 26 under the nearest point of the selection electrode A₂ of the second line is maintained in the firing condition, after three selection cells 24, 25, 26 are all fired by applying the selection pulse V a to the electrode A₂ at the timing T₅, the selective sustain voltage pulse Ps is applied only to the display electrode Y₃ for continuing the discharge at cell 36. On the other hand, the wall charges of display cells 34, 35 are erased due to the discharge in the selection cells 24, 25 by the application of the selection pulse V a as shown in Fig. 11(d). Thereby, at the timing T₆, where the next sustain pulse is applied, the display cell groups associated with the selection electrodes of the 1st and 2nd lines and under the display electrode X₁ are selectively displayed as shown in Fig. 11(e). Explanation of operations of selection electrodes A₃, A₄, A₅ is omitted here in order to avoid repeated explanation. Then, operations of cells belonging to the display electrode X₂ are explained hereunder, although these are the same qualitatively. As shown in Fig. 11 (f), all cells 37, 38, 39 under the display electrode X ₂ are fired by applying the write pulse, at the timing T₇ of Fig. 12, across all electrodes of the display electrode X₂ and display electrode Y. At this time, since the no sustain pulse 40 is applied to the display electrodes X₁, X₃ during the selecting operation of the display electrode X₂, the firing cells formed by the display electrodes X₁, X₃ are all holding the wall charges. Then, at the timing T₈, the selection pulse V a is applied again to the selection electrode A₁ in order to fire all selection cells 27, 28, 29 formed by the electrodes A₁ and X₂. If the display cell 38 nearest to the selection electrode A₁ between the display electrodes X₂ and Y₂ is considered as the display cell to be erased, supply of pulses to the display electrode Y₂ is suspended temporarily at the timing T₉ and thereby elimination of discharge of the selected cell 28 triggers consumption of wall charges and space charges of the display cell 38 nearest to said selection cell 28 as shown in Fig. 11(g). Sustain pulses which are responding between the display electrode X₂ and display electrodes Y₁ and Y₃ are applied to the display cells 37, 39 which are required to continue the discharge in order to hold the display discharge occurring at the first time. Thereby, at the timing T₁₀, only upper and lower two display cells 37, 39 remain on the display electrode X₂ associated line A₁, resulting in the display as shown in Fig. 11(h). Such operation is sequentially performed to the entire part in order to display the necessary information. Fig. 13 shows a typical high voltage driver to be provided at the periphery of display panel realizing the present invention. In this figure, D x and D y are drivers for driving the display electrodes X i and Y i respectively which outputs pulse voltages from earth voltage to sustain voltage -V s by the switching to the display electrodes X i and Y i as shown by the waveforms X i and Y i of Fig. 12. D a is a selection driver which outputs the waveform of selection pulse A i shown in Fig. 12. The write pulse V W of sustain waveform Y i shown in Fig. 12 is realized by supplying the write voltage V W through the switching element 30 comprised in the driver D y . A circuit configuration of Fig. 13 is suited to that for outputting the drive waveforms shown in Figs. 5, 9 and 12. Fig. 14 shows the operation margin actually obtained in accordance with above this addressing method as shown in Fig.11. The horizontal axis means the amplitude of selection pulse V a for erasing and the vertical axis means a peak value of pulse of the sustain voltage V s . M₁ is an example of operation margin in accordance with the write address method of the prior art. M₂ is an operation margin obtained by the method of the above described modified embodiment. This margin is remarkably extending in the low voltage side of selection pulse and thereby stability can be judged. As is understood from above explanation, the address method of the present invention is based on that after all display cells of a group on the display electrode are fired, the selection cells adjacent to the display cells not displayed on the display electrode are fired, and thereby the wall charges of display cells adjoining with the adjacent are erased in such selection cells having a relation as using in common the one display electrodes are erased. With employment of this method, it can be observed that the self-discharge occurs only with wall charges on the falling edge of pulses applied to the selected cells, consuming the wall charges and thereby the wall charge disappears gradually, and accordingly, such wall charges can be erased in a wider range of sustain voltage. Moreover, in this method, since display cells to be selected are left by erasing unnecessary cells after all cells on the display electrode pair of the selected line are fired, a problem of difficulty in firing of discharge cells is solved and reliability of operation and increase in margin can be attained also in these points. As the wall charges generated on the display cells by the line firing sequence give assistance to the discharge of selection cells, voltage of selection pulse for generating a selective discharge can be lowered. In addition, a low voltage operation IC element which are easily available that can be used by employing an asymmetrical sustain voltage system described for the embodiments. Even in the abovementioned electrode arrangement to which the decoding function is provided, the line sequential addressing can be realized and the driving circuit can be simplified without lowering the driving speed. Therefore,the present invention is very effective for realizing the three-electrode type surface discharge display panel.

Claims: A method for driving a gas discharge panel having plural display electrode pairs (11) which are adjacently arranged in parallel in units of two electrodes (Y₁, X₁; Y₂, X₂₁,...) and plural selection electrodes (13) isolated therefrom and arranged in a direction crossing these display electrode pairs, and a plurality of display dots arranged in a matrix each of which comprises a selection cell (T) and a display cell (K), the selection cell being defined at respective intersecting points between the one display electrodes (Y₁, Y₂, ... )of said display electrode pairs and the selection electrodes (13; W₁, W₂, W₃ ... ), and the display cells (K) being defined between the pair of display electrodes adjacent to said selection cells (T), characterized in that a firing voltage exceeding the discharge start voltage is applied across a pair of display electrodes (X₁, Y₁, ...) of one line to be selected, thereafter a voltage is selectively applied to the selection electrodes (W₁, W₂, W₃, ...) which form selection cells of dots which are not to be displayed on the pertinent dot lines whereby the wall charges of the display cell (K) forming a pair with the pertinent selection cell (T) are erased, and then only the remaining display cells are caused to discharge by applying an AC sustain voltage across said display electrode pair (Y₁, X₁; Y₂, X₂; ...). A method for driving a gas discharge panel according to claim 1, wherein a sustain voltage waveform to be applied to said display cells is applied as an asymmetrical composite waveform of a sustain voltage having a high amplitude to be applied to the one display electrode forming said selection cells and a sustain voltage having a low amplitude to be applied to the other display electrode. A method for driving a gas discharge panel according to claim 1 or 2, wherein the operations for generating discharge to all display cells (K) of said dot lines to be selected are sequentially applied to the dot lines for pre-fire line scanning, and this pre-fire line scanning is carried out at least one dot line preceding the dot line where selecting operation is applied to the selection cells (T) of said unwanted dots. A method for driving a gas discharge panel comprising a plurality of display electrode pairs adjacently arranged in parallel in units of two electrodes (Y₁, X₁), a plurality of selection electrodes (W₁, W₂) insulated therefrom and arranged in a direction crossing these display electrodes and a plurality of display dots arranged in a matrix each of which comprises a selection cell (T) and a display cell (K), the selection cell being defined at respective intersecting points between the one display electrodes (Y₁, Y₂, ... ) of said display electrode pairs and the selection electrodes (13; W₁, W₂, W₃ ... ), and the display cells (K) defined between the pair id display electrodes adjacent to said selection cells (T), and providing such an electrode structure that a first display electrode of each pair is connected with plural adjacent first electrodes as a group, and the second display electrode of each pair is connected in common with the same order second electrode in each said group, said method being characterized by firing a display cell line by applying a firing voltage across a selected pair of display electrodes; erasing a discharge information stored in an unwanted display cell (K) among said fired display cell line by applying a selection voltage across a selected selection electrode and said second display electrode and redischarging remaining display cells by applying an AC sustaining voltage to said display electrode pair. A method for driving a gas discharge panel wherein a plurality of display electrode pairs (X, Y) are adjacently arranged in parallel in units of two electrodes (X₁Y₁, X₁Y₂, X₁Y₃; X₂Y₁, X₂Y₂, X₂Y₃; ...), a plurality of selection electrodes (A₁, A₂, A₃, A₄, A₅, ... ) insulated therefrom and arranged in a direction crossing these display electrodes, and a plurality of display dots arranged in a matrix each of which comprises a selection cell and a display cell, the selection cells (21, 22, 23; 24, 25, 26, ...) being defined at respective intersecting points between the one display electrodes of said display electrode pairs and the selection electrodes (A₁, A₂, A₃ ... ), and the display cells (31, 32, 33; 34, 35, 36; ...) being defined between the pair of display electrodes (X,Y) adjacent to said selection cells, the display electrode pairs being grouped such that the first display electrodes of display electrode pairs (X, Y) of each group are connected in common while the other display electrodes (Y₁, Y₂, Y₃, ...) of each pair of said group can be operated individually, characterized by the following steps: firing all display cells belonging to one group of electrodes (X₁, Y₁, Y₂, Y₃; ...) all at once, sequentially selecting one by one the select electrodes (A₁, A₂, A₃, ...) to generate a discharge on all selection cells belonging to the selected select electrodes (A₁, A₂, A₃, ...) including the display cells which are not to display and erasing said display cells adjacent to said sequentially selected selection cells not to display and by subsequently suspending supply of the sustaining voltage pulse (P S ) to the display electrodes (Y₁, Y₂ , Y₃, ...) having the display cells which are nor required to display, and redischarging un-erased display cells by supplying the sustain voltage pulsed (P S ) across all display electrodes (X, Y). Method according to any of the preceding claims, charaterized in that the display electrodes (Y₁, X₁) are arranged on the support substrate (10) of the gas discharge panel. Method according to any of the preceding claims, charaterized in that the selection electrodes (W₁, W₂) are arranged on an insulation (12) covering the display electrodes (Y₁, X₁). Method according to any of the preceding claims, charaterized in that the selection electrodes (W₁, W₂) are covered by a surface layer (15).

Inventors: NIINUMA, ATUO, SHINODA, TSUTAE
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G09G3
IPC codes: G09G3