PLL-CIRCUIT

Abstract: Phase locked loop (PLL) circuits are widely used for data carrier extraction in many applications. Conventional PLL's have the disadvantage that the VCO oscillating frequency will be driven to its minimal or maximal frequency when the input data signal is absent and therefore the locking to a new data signal takes a relatively long time. This is unacceptable in applications where the input data signal often is interrupted and a fast locking is required (e.g. PLL circuits in disk con­ trollers). The invention presents a new PLL circuit and a new phase detector for preventing the long lock acquisition times by controlling the VCO by a predetermined reference fre­ quency when the data input signal is absent.

Description: The invention relates to a phase locked loop (PLL) circuit comprising a voltage controlled oscillator (VCO) with an oscillator output which is coupled to a first input of a frequency detector and to a first input of a phase detector, the outputs of the frequency and phase detectors being coupled to first and second inputs respectively of a loop filter (R₁, R₂, C F ), whose output is coupled to a control input of the VCO; the phase detector (10) being provided with a data input for receiving a data signal (DATIN) and comprising a digital comparison circuit generating an output signal as a result of a sequence of comparisons of a cycle of the data signal with a cycle of a signal from the VCO, whereby the comparison circuit is triggered each time by the start of a data signal (DATIN) and the generated output signal is either in a first state (PU) from said start of a data signal to the next transition of the oscillator output signal (VCOIN) if the oscillator output signal is at a first state at said start or in a second state (PD) during the next full time interval in which the oscillator output signal is in the first state, if the oscillator output signal is in a second state at said start. Such phase locked loop circuits may be part of a disk phase locked loop circuit like the Signetics SCB 68549 integrated circuit. Further PLL circuits are known from IEEE Transactions on Communications Vol. Com 27, No. 9, September 1979, pages 1288-1295 "Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery", David G. Messerschmitt. As summarized in said publication the initial acquisition of a phase locked loop when used for timing or carrier extraction is a significant practical problem, since the narrow bandwidth generally required for jitter requirements severely restricts the pulling range. In the cited prior art several methods have been used to effect the acquisition. This article further shows an arrangement of a frequency detector for the coarse regulation of a voltage controlled oscillator (VCO) and a phase detector for its fine adjustment. Both the phase and the frequency detector are receiving the VCO frequency signal and the data input signal. In a PLL circuit used for carrier extraction the data input signal is often interrupted (e.g. due to a rather long series of "zeroes" or movements of a read head in a disk storage medium). As a result of the discontinuous data input signal (missing data signals) the PLL circuit will detune the VCO. So the PLL circuit will not quickly lock to a new data signal, although it has approximately the same frequency as the interrupted data signal. In the described PLL circuits the acquisition time is relatively long because the phase and frequency detectors regulate the VCO to its maximal or minimal oscillating frequency when the data signal is interrupted. As a result the first received new data signals will be stumbled. A phase locked loop circuit in which a digital phase comparison circuit is used is known from DE-A 31 15 057. The digital comparison circuit only reacts to transitions of the data or the VCO-frequency signal in one direction and is insensitive to the actual duty cycle or frequency of the incoming signals. In the known circuit no separate frequency detector is foreseen. For a proper operation of the known PLL it is necessary that both the VCO-frequency signal and the data signal are present. In the before described use the data signal may be absent during a prolonged period, a situation that can not be handled satisfactorily by the known circuit. It is an object of the invention to provide a PLL circuit that will keep the oscillating frequency of the VCO near the frequency of the next incoming data signal during absence of the data signals and will generate output signals that result in a relatively ripple-free control signal for the VCO. The PLL-circuit according to the invention is set out in Claim 1. When data signals are absent, the phase detector will not be triggered and thus does not generate an output signal which influences the oscillating frequency of the VCO. After each comparison the phase detector generates a single polarity output signal. In general, several succeeding comparisons will result in succeeding output signals with the same polarity and can easily be filtered by simple filter means to form a relatively ripple-free control signal for the VCO. A PLL as defined hereinbefore and comprising a phase detector according to the invention will be tuned to the reference frequency applied to the reference frequency input of the frequency detector. The reference frequency given be chosen as close to the clock frequency of the data signal as possible. Such provisions accelerate the locking of the PLL to the next incoming data signal after an interruption. By itself, US patent 4020422 describes a phase comparator indicating a phase difference range of n x 360 o , between two input signals, comprising edge triggered shift registers, for dividing the input signals by n, means for modulating the width of the resulting output pulses in proportion to the phase difference of the input signals, and integrating means to combine the modulated pulses into a time-averaged signal which is indicative of the phase difference. Further attractive aspects of the invention are recited in dependent claims. The invention will be described with reference to the following Figures, in which Figure 1 shows a PLL circuit in which the phase and frequency detectors according to the invention may be used Figure 2 shows a phase detection according to the invention Figure 3 shows an embodiment of a frequency detector Figure 4 shows a further embodiment of a frequency detector Figure 5 shows a state-event diagram of the frequency detector in Figure 4. In Figure 1 a PLL circuit is shown which maintains the voltage controlled oscillator (VCO) of the phase locked loop operating near a frequency to which it will be locked even when the locking signal is absent. In this PLL curcuits it is possible to control the lock and capture range of a phase locked loop. The circuit consists of an interconnection of three principle logic circuits; a phase detector (10), a frequency detector (14) and a VCO (12). Two resistors R1, R2 and a capacitor CF constitute a loop filter. The phase detector is a design that is insensitive to missing pulses, therefore the circuit is effective in recovering the clock from data that uses Miller, Manchester or other encoding schemes. The operation of the circuit is similar to a standard PLL circuit except that a second control source providing a reference frequency F ref is to be used. By changing the ratio of the resistors R1 and R2 in the loop filter, the effect of the frequency detector on lock in and lock range can be varied. At any time during which no pulses are being received by the phase detector, the loop will be locked to the reference frequency which is received at the F ref input of the frequency detector and may be generated by e.g. a cristal oscillator. This can be thought of as a means for keeping the loop locked to some nominal frequency while awaiting the arrival of the data signal. In order for this circuit to operate in the desired manner, it is important that the output signals of the frequency detector be a function of the frequency difference between its two inputs (the VCO output and F ref ) and not the phase difference between the two. A phase detector 10 (⊘ DET) also receives the VCO output signal. The output signals of the frequency detector 14 and the phase detector 10 are sent to the voltage controlled oscillator 12 to maintain its oscillating frequency near or at the frequency to which it will be locked. The circuit of the present invention, when used in a phase locked loop for controlling up to 4 memory discs, either floppy discs or hard discs, is to produce an oscillator frequency to match the frequency of the data signal, received on the input DATIN, locked condition, any slight change of the input frequency, called jitter, will appear as a change in phase between the data signal and the voltage controlled oscillator frequency. This phase shift then acts as a signal to adjust the frequency of the phase locked loop voltage controlled oscillator 12 to match the input frequency. Referring now to Figure 2, it should be noted that the phase detector circuit 10 shown assumes that when voltage on the input from the voltage controlled oscillator 12 is increased, the output frequency increases. It is of course possible to design the PLL circuit so that voltage controlled oscillator circuits with the reverse characteristics may be used. The starting state is for the output of all three flip flops (21, 22, 23) to be in their reset, or zero state. The description that follows will show that this state can reached regardless of any arbitrary starting state. If a rising edge occurs on data input DATIN, while the VCO signal on a first input VCOIN is low, flip flop 21 is set. While set, the output of flip flop 21 activates inverter 26. As a result the pump-up signal (PU) is active. When the VCO signal on the input VCOIN goes high, the output of inverter 24 goes low resetting flip flop 21, the output of which switching off inverter 26, thus disabling the pump-up signal (PU). The output of inverter 24 also prevents flip flop 21 from being set by positive transitions on the data input DATIN when the VCO signal is high. If a rising edge occurs on data input DATIN while the VCO signal on input "VCOIN is high, the flip flop 22 is set. On the next falling VCO edge, the output of inverter 24 goes from low to high and flip flop 23 is set, thus causing its inverting output to go low and clear flip flop 22. While flip flop 23 is set, its output activates inverter 28 and thus the pump-down signal (PD) is active. When the VCO signal returns to its high state, the output of gate 25 goes low and flip flop 23 is cleared, deactivating the inverter 28 and the pump-down signal. This logic causes the pump-up signal (PU) to be active from a rising edge of the data signals on input DATIN that occurs while VCO signal is low until the VCO signal rises. The pump-down (PD) is active for the full low half VCO period that follows a rising edge of the data signal which occurred during a VCO high time. Each output signal, which in a typical application is sent through a low pass filter before being used to control the frequency of a voltage controlled oscillator 12 , has two states. Since one state is common to both pump-up (Pin) and pump-down (PD), there is a total of three output states. If pump-up (PU) is active, the signal can be thought of as being connected to the positive supply. If pump-down (PD) is active, the signal can be thought of as being connected to ground. When inactive, the pump-up output and pump-down output can be thought of as being an open circuit. Thus it is that the three states, pump-up active, pump-down active and inactive are identical to those of tristate drivers. The detector thus disclosed has a linear relationship between phase error and pump-up pulse width, but a fixed pump-down pulse width for all phase errors for which the signal is generated. The effect of this operation cam be thought of as follows. A normal linear relationship between phase error for both pump-up and pump-down results in a phase error probability distribution that is Gaussian, centered at zero error. In the circuit illustrated in Figure 2, the resulting distribution is similar except that for a VCO with a positive characteristic the distribution is centered about a point at which the input is leading the VCO by some phase difference. The exact location is determined by the ratio of two resistors R1 and R2 connected from pump-up output and pump-down output to the loops's integrating capacitor CF. Figure 3 shows a first embodiment of a frequency detector 14A. A series of flip flops (Q7, Q8, Q9, Q10), a series of NOR-gates 32 leading to a pair of tristate drivers 34. The two inputs are labeled F ref1 for the reference frequency input and VCO, for the input, which has been connected to the output of the voltage controlled oscillator ( 12 ) in the loop (see Figure 1). The output of the frequency detector circuit 14 is labelled FO1. The reference frequency and the VCO frequency signals are assumed to be digital signals with a fixed, at least on a short term basis, frequency. The signals however need not be square waves since only one edge, in the case of the embodiment of Figure 3 the rising edge, has an effect on the circuit 14A . The output signal of the circuit 14A , which is sent through a low pass filter before being used to control the frequency of the voltage controlled oscillator 12 , has three states. The first state is pump-up, in which case the signal may be thought of as being connected to the positive supply. The second state is pump-down, in which case the signal may be thought of as being connected to ground. The third state is inactive in which case the output FO1 can be thought of as being an open circuit. The operation of the circuit is as follows. The starting state is for all four flip flops is to be in their reset or zero state. The description that follows will show that this state will be reached regardless of any arbitrary starting state. A transition on either the F ref1 or the VCO₁ input will cause the flip flop pair Q7, Q8 or Q9, Q10 to assume the state 1, 0. The next positive edge causes the state of the affected pair to advance to 1,1. When both Q8 and Q10 are in the 1 state a direct clear will be effected returning the flip flops to their original states. A list of all possible stable states for Q7, Q8, Q9, Q10 and the associated pump-up/pump-down action follows. All states are of the form X1X1 are not included since they are unstable and are cleared to 0000. States of the form O1XX and XXO1 are not included since they cannot be reached from the starting state 0000. However, if these states should occur after e.g. powering-up the circuit, the flip flops will be in their reset state after a few cycles of the VCO or reference frequency. Q7 Q8 Q9 Q10 Pup Pdown 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 0 0 0 1 0 1 1 1 0 Analysis of the results of this circuit will show that when the reference frequency is greater than the VCO frequency over the course of one cycle of the reference frequency and one cycle of the VCO frequency, there will be a net pump-up signal, that is the pump-up width will be greater than the pump-down width. When the reference frequency is less than the VCO frequency there will be net pump-down. These net signals are independent of the phase difference between the reference frequency and the VCO frequency signals. Figure 4 shows a further embodiment of a frequency detector 14B . The detector comprises three D-type flip flops (Q4, Q5, Q6), an AND-gate (42), a NOR-gate (44) and a tristate driver (46). This frequency detector is provided with the inputs F ref2 and VCO₂ and an output FO₂. The functioning of this detector is illustrated by the state event diagram of Figure 5. In a starting condition, all three flip flops (Q4, Q5, Q6) are in a zero state, meaning that their non-inverting outputs are at logical "zero" value, and consequently their inverting outputs are at "one". The AND- (42) and NOR- (44) gates render the tristate driver (46) inactive, which means that it can be thought of as having a extremely high output impedance (HiZ) or even as an open circuit. A rising edge in the reference frequency on input F ref2 sets flip flop Q4 to its "one" state, which activates the tristate driver (46) and generates a pump-up signal at the output FO₂. After receiving the next rising edge on input F ref2 flip flop Q5 also is set to "one", disabling the tristate driver (46). The frequency detector 14B awaits a rising edge in the VCO signal on input VCO₂, on which the flip flop Q6 is set to "one". The high output signal of flip flop Q6 resets both flip flops Q4 and Q5 and generates the pump-down signal at the output FO₂ through the tristate driver (46), which has been enabled via NOR-gate 44. On the next rising edge on the input VCO₂, the flip flop Q6 takes the "zero" state over from flip flop Q5 and renders the tristate driver (46) inactive. At this instant the first state has been reached again and a new cycle of states may be started. It will be noted that the output FO₂ generates a "pump-up" signal during a full period of the reference frequency and afterwards generates a "pump-down" signal during the following full period of the VCO output signal. By applying these signals to the loop filter, a control voltage for the VCO 12 is generated. (See Figure 1).

Claims: A phase locked loop (PLL) circuit comprising a voltage controlled oscillator (VCO) (12) with an oscillator output which is coupled to a first input of a frequency detector (14) and to a first input of a phase detector (10), the outputs of the frequency and phase detectors being coupled to first and second inputs respectively of a loop filter (R₁, R₂, C F ), whose output is coupled to a control input of the VCO (12); the phase detector (10) being provided with a data input for receiving a data signal (DATIN) and comprising a digital comparison circuit generating an output signal as a result of a sequence of comparisons of a cycle of the data signal with a cycle of a signal from the VCO, whereby the comparison circuit is triggered each time by the start of a data signal (DATIN) and the generated output signal is either in a first state (PU) from said start of a data signal to the next transition of the oscillator output signal (VCOIN) if the oscillator output signal is at a first state at said start or in a second state (PD) during the next full time interval in which the oscillator output signal is in the first state, if the oscillator output signal is in a second state at said start; the frequency detector (14) being provided with a reference input for receiving a reference frequency (F REF ) where the output (FO₁, FO₂) of the frequency detector derives from a first voltage level which is either active or inactive and a second voltage level which is either active or inactive, the frequency detector (14) further comprising reset means (Q₆, Q₈, Q₁₀) for terminating a cycle of comparison and starting a new cycle selection means (Q₇-Q₁₀, 32, 34; Q₄-Q₆, 42, 44) for activating the first voltage level during a first portion of a cycle of comparison; and for activating the second voltage level during a second portion of a cycle of comparison, the second portion being non-coincident with the first portion; whereby the difference in length of the first and second portions is zero when the signals at the first input and the reference input of the frequency detector have the same frequency, and the sign of said difference corresponds to the sign of the difference of the frequencies between the signals at the first and reference inputs. A PLL circuit according to Claim 1, characterized in that the frequency detector (14A) comprises a first (Q₇), second (Q₈), third (Q₉) and fourth (Q₁₀) D-type flip flop (FF), the D-input of the first (Q₇) and the third (Q₉) flip flop receiving a constant binary value (+); the clock inputs (CLK) of the first (Q₇) and second (Q₈) flip flop being connected to the reference input (F REF ), the clock inputs (CLK) of the third (Q₉) and the fourth (Q₁₀) flip flop being connected to the first input of the frequency detector (VCO); the non-inverting outputs of the first (Q₇) and third (Q₉) flip flop being connected to the D-inputs of respectively the second (Q₈) and the fourth (Q₁₀) flip flop whose non-inverting outputs are connected to the inputs of a NAND-gate constituting the reset means, whose output is connected to the reset input (RST) of the flip flops (Q₇-Q₁₀) of the frequency detector; the frequency detector (14A) further comprising a first and a second two input NOR-gate and a first and a second three input NOR-gate (32), the outputs of the three input NOR-gates being connected to a control input of a first respectively second tristate driver (34), the outputs of which being interconnected for forming the output of the frequency detector (FO₁); the inverting outputs of the first (Q₇) and third (Q₉) flip flop being connected to an input of the first respectively second two input NOR-gate (32); the non-inverting outputs of the second (Q₈) and fourth (Q₁₀) flip flop being connected to the second input of the first respectively second two input NOR-gate (32) as well as to an input of the second respectively first three input NOR-gate (32), which latter NOR-gates have their third input connected to the output of the second respectively first NOR-gate for generating complementary binary signals on the outputs of the first and second tristate drivers (34). A PLL according to Claim 1 characterized in that the frequency detector (14B) comprises a fifth (Q₄), a sixth (Q₅) and a seventh (Q₆) D-type flip flop (FF), whereby the first input (VCO₂) of the frequency detector is connected to the clock input (CLK) of the seventh flip flop (Q₆); the clock inputs (CLK) of the fifth (Q₄) and sixth (Q₅) flip flop being connected to a reference input (F REF2 ); reset inputs RST of said latter flip flops being connected to the non-inverting output of the seventh flip flop (Q₆), to an input of a third tristate driver (46) and to a first input of a first NOR-gate (44), whose output is connected to a control input of the third tristate driver (46); the non-inverting outputs of the fifth (Q₄) and sixth (Q₅) flip flops being connected to respectively the D-inputs of the sixth (Q₅) and seventh (Q₆) flip flops; the D-input of the fifth (Q₄) flip flop receiving a constant binary value; the non-inverting output of the fifth (Q₄) flip flop further being connected to a first input of a first AND-gate (42), whose second input is connected to the inverting output of the sixth flip flop (Q₅) and whose output is connected to a second input of the first NOR-gate (44). A PLL according to Claim 1, 2 or 3 where the output of the phase detector has a first voltage level which is either active or inactive and a second voltage level which is either active or inactive, and where the First voltage level is activated if the oscillator output signal (VCOIN) is in a first state at the start of the data signal (DATIN) and is inactivated at the next transition of the data signal characterized in that the phase detector comprises a period selection means (21, 22, 23) for activating the second voltage level (DD) during a half period of the oscillator output signal (VCOIN) which is the first half period signal after a start of a cycle where the start of the cycle is activated if the oscillator output signal (VCOIN) is in a second state at the start of the data signal (DATIN). A PLL as claimed in Claim 4, characterized in that the comparison circuit comprises an eighth (21), a ninth (22) and a tenth (23) D-type flip flop; the eighth (21) and the ninth (22) D-type flip flop having their clock input coupled to the data input (DATIN), the tenth D-type flip flop (23) having its clock input coupled to the reset input of the eighth D-flip flop (21) and to the first input (VCOIN). A PLL as claimed in Claim 4 or 5, characterized in that at least one output (PU, PD) of the phase detector (10) is in a high impedance state when both voltage levels are inactive. A PLL as claimed in Claim 4, 5 or 6, characterized in that the phase detector comprises an eighth (21), a ninth (22) and a tenth (23) D-type flip flop (FF), each with a data input (D), a non-inverting output and and inverting output, a clock input and a reset input; the clock inputs of the eighth (21) and ninth (22) flip flop being coupled to the data input (DATIN) of the phase-detector, the clock input of the tenth flip flop (23) being coupled to the reset input of the eighth flip flop (21); the first input (VCOIN) of the phase detector (10) being connected to the D-input of the ninth flip flop (22) and through a first inverter (24) to the reset input of the eighth flip flop (21), said first input (VCOIN) further being connected to a first input of a first NAND-gate (25), whose second input is connected to the inverting output of the ninth flip flop (22) and whose output is connected to the reset input of the tenth flip flop (23), the inverting output of the tenth flip flop (23) being coupled to the reset input of the ninth flip flop (22) and to a control input of a first tristate driver (28); the non-inverting output of the ninth flip flop (22) being connected to the D-input of the tenth flip flop (23); the inverting output of the eighth flip flop (21) being coupled to a control input of a second tristate driver (26) and the D-input of the eighth flip flop (21) receiving a constant binary value (+5V); the outputs of said first and second tristate drivers (26, 28) generating complementary binary signals (PU, PD) upon activation of the control inputs, being interconnected to form the output of the phase detector.

Inventors: YARBOROUGH, JOHN MILTON
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1985
Main classification: H03D13
IPC codes: H03D13, H03L7