METHODS OF AND APPARATUS FOR REPRODUCING RECORDED VIDEO SIGNALS

Abstract: Reproduction of a recorded video signal in a digital process involves switching between a plurality of field memories (13,14,15) to store image data of one video field picked up by a rotary head (2) and to retrieve image data for reproduction, each time the scanning of one record area is completed. The method also includes detection of reversal of a tape drive direction and for disabling the switching between the field memories (13,14,15) for a given period so as to hold the video image reproduced on a video monitor unchanged.

Description: This invention relates to methods of and apparatus for reproducing recorded video signals. More particularly, the invention relates to recorded video signal reproduction applicable to digital video tape recorders (DVTRs). Some recent DVTRs have systems for recording and distributing samples from each field of image data among a plurality of separate track blocks on a single track, such as by shuffling or interleaving for added data fidelity. The organization of data recorded on the digital video tape is shown diagrammatically in Figure 2 of the accompanying drawings. Figure 2A shows one synchronization block containing image data (DATA) for one-fourth of a horizontal line (H/4). In addition to the DATA block, the synchronization block (SYCB) includes synchronization code (SYNC CODE), address code and cyclic redundancy check code (CRC CODE) blocks. A number of synchronization blocks (SYCB) are strung together to form a track block (TRK) covering 1/N field, as shown in Figure 2B. N, for example ten, track blocks (TRK) form one field block (FIB), as shown in Figure 2C. This one field block (FIB) contains image data covering one field. In the reproduction process, the image data recorded in each ten track blocks are reproduced by means of a reproducing head and recorded in a field memory. The image data for one field are then retrieved from the field memory at a predetermined speed for reproduction on a video monitor. Two field blocks (FIB) form one frame block (FLB). The frame block (FLB) thus contains image data for successive odd and even-numbered fields including image data for one screen page on the video monitor. The image data organized as above are recorded on a video tape 1 in the form shown in Figure 3 of the accompanying drawings. Four recording/reproducing heads 2A, 2A' and 2B, 2B' are used to record the image data on the video tape 1. During recording, the video tape 1 is driven at a predetermined constant speed. The recording/reproducing heads 2A and 2A' and 2B and 2B' are mounted on a rotary drum 3 for rotation therewith in synchronism with the video tape drive. Each pair of recording/reproducing heads 2A, 2A' and 2B, 2B' serves to record data for two neighbouring track blocks simultaneously. First (odd number) record fields RE, consisting of ten track blocks each and second (even number) record fields RE₂ also consisting of ten track blocks are recorded alternately. The image data recorded on the video tape 1 can be reproduced in various ways. For example, the recorded image data may be reproduced in a normal REPLAY mode in which the video tape 1 is driven at the predetermined normal speed, a HIGH-SPEED SEARCH mode in which the video tape 1 is driven at a much higher speed, for example at a speed eight times faster than the normal speed, a SLOW mode in which the video tape 1 is driven a slower speed, for example 1/3 of the normal speed, and a STILL mode in which the tape drive is temporarily stopped. In the normal REPLAY mode, the recording/reproducing heads 2A, 2A' and 2B, 2B' can scan every track block in order to pick up all of the image data with relatively high fidelity. On the other hand, when the video tape recorder is operated in SLOW mode, the heads 2A, 2A' and 2B, 2B' scan across the video tape 1 as shown in broken line in Figure 3. As shown in Figure 3, the scanning angle of the heads is steeper than the angle of the track blocks, so that the heads tend to scan more than one track block in each scan cycle. Therefore, the reproduced input video signal Vin contains image data for more than one track block. This will not cause serious problems as long as the heads scan track blocks within the same field (also called the "record area"). However, when the heads cross track blocks from different, adjoining record areas, image data from both record areas will be included in the input video signal Vin. For example, when heads scan the first track block A of the first record area RE₁, they tend to also scan the last, that is the tenth track block J of the preceding second record block RE₂. In this case, the input video data contains image data from both the first and second record areas RE₁ and RE₂. This means that the input video signal Vin includes both odd-numbered field image data and even-numbered field image data. This requires special signal processing to separate the odd-numbered field image data from the even-numbered field image data. In particular, when the tape drive is switched between forward drive and reverse drive, proper time sequence control is needed for image data picked up before and after reversing the tape drive direction, so that the video image displayed on the video monitor will not be disrupted or distorted. In order to ensure good video fidelity when reversing the tape drive direction, it is necessary temporarily to hold the system in the STILL mode for a given period during which a single constant image will appear on the video monitor. Our UK patent specification GB-A-2 098 021 (published 10.11.1982) discloses digital television apparatus comprising first, second and third field stores each capable of storing digital signals relating to one field of a television signal, a digital video tape recorder to supply a digital television signal at a variable rate to the field stores, a write control device to supply the digital television signal to one or to two of the field stores for writing therein, depending on the rate of supply of the digital television signal, and a read control device to read the stored digital television signal from one or from two of the field stores depending on the rate of supply of the television signal, the write and read control devices rotating the writing and reading around the field stores cyclically. According to the present invention there is provided a method of reproducing a video signal recorded on a video tape in the form of a plurality of tracks, the method comprising the steps of: providing a memory means including at least three memories, each capable of holding all of the image data for one field picked up from the recording tracks of the video tape by a reproduction head; characterized by: selecting one of said memories in said memory means for storage of the image data from the field currently being picked up by said head, a storage control means selecting said memories in a given order and detecting inclusion of image data from more than one field in an input video signal from said head and selecting more than one memory for storage of image data for each field separately; selecting one of said memories currently holding one field of image data in a predetermined sequence for retrieval of the stored image data as an output video signal; monitoring the selection condition of said memory means; detecting reversal of the tape drive direction; and disabling, in response to reversal of the tape drive direction, selection of a different said memory for retrieval and supply of the stored data for a period of time related to said monitored selection condition of said memory means. According to the present invention there is also provided apparatus for reproducing a video signal recorded on a recording medium in the form of a plurality of tracks, comprising: a memory means including at least three memories, each capable of holding all of the image data for one field picked up from the recording tracks of the recording medium by a reproduction head; characterized by: storage control means for selecting one of said memories in said memory means for storage of the image data from the field currently being picked up by said head, said storage control means selecting the memories in a given order and detecting inclusion of image data from more than one field in an input video signal from said head and selecting more than one memory for storage of image data for each field separately; retrieval control means for selecting one of said memories currently holding one field of image data in a predetermined sequence for retrieval of the stored image data as an output video signal; a memory condition detecting means for monitoring the selection condition of said memory; a drive direction detecting means for detecting reversal of the tape drive direction; and a memory switching disabling means, responsive to reversal of the tape drive direction, for disabling selection of a different memory for retrieval and supply of the stored data for a period of time related to the memory selection conditions detected by said memory condition detecting means. Thus, a method according to the invention for reproducing a recorded video signal involves switching between a plurality of field memories to store image data for one video field picked up by a rotary head, and to retrieve image data for reproduction each time the scanning for one record area is completed. The method also includes a process for detecting reversal of the tape drive direction, and for disabling the switching between the field memories for a given period so as to hold the video image reproduced on a video monitor unchanged. One field of image data stored in one field memory is subsequently accessed for retrieval after completion of the scanning of the corresponding record area. The method also includes the steps of detecting image data on the video tape from a field other than the field from which image data are being stored and accessing another field memory not currently in use for storage or retrieval for storage of the image data of said other field. The given period for which access for retrieval is disabled is variable depending upon the scanning condition of the rotary head. For instance, when the rotary head is scanning a single field or record area, the given period may be shorter than when the rotary head is scanning more than one record area. The switching between the field memories or disablement thereof is triggered by a pulse signal produced each time the scanning of one record area is completed. An apparatus according to the invention for reproducing a video signal may include at least three memories, each capable of storing all of the image data for one field. One of the memories is selected for storage of image data currently being picked up from one record area of the recording medium. The memory selection is performed anew each time the scanning of one field is completed, whereupon a different memory is selected for storage of the image data from the next field. At the same time, another memory is selected for retrieval of stored image data for video reproduction. The memory selected for retrieval is the memory which was selected for storage of image data in the immediately preceding memory selection cycle. Reversal of the tape drive disables retrieval memory selection for a given period, which period may depend upon the scanning conditions of the recording medium. The invention will now be described by way of example with reference to the accompanying drawings in which like parts are referred to by like references, and in which: Figure 1 is a schematic block diagram of an embodiment of recorded video signal reproducing apparatus according to the present invention; Figures 2A to 2D are diagrams illustrating the organization of data recorded on a video tape serving as a recording medium; Figure 3 is a diagram showing the relationship between recording head scan and rotary head speed; Figure 4 is a plan view of a rotary video head; Figure 5 is a block diagram of a scanning mode detecting circuit of the reproducing apparatus of Figure 1; Figure 6 is a timing chart of signals produced by the circuit elements of the scanning mode detecting circuit of Figure 5 while the system operates in the SLOW mode; Figure 7 is a block diagram of an address control circuit of the reproducing apparatus of Figure 1; and Figures 8 and 9 are diagrams illustrating the operation of the address control circuit of Figure 7. Referring now to Figure 1, the video signal reproducing system includes a demultiplexing circuit 11 converting a serial input signal V in derived by reproducing video signal data recorded on a magnetic video tape 1 into parallel data signals. The converted parallel data are conducted from the demultiplexing circuit 11 to a latching circuit 12. The system has first, second and third field memories 13, 14 and 15, which serve as image data memories and together form a single video signal memory 16. The first, second and third field memories 13, 14 and 15 are connected to receive the latched parallel data from the latching circuit 12 as image data. The field memories 13, 14 and 15 of the video signal memory 16 are also connected to receive a control input from a write address counter 17 which generates a write address signal S₁ identifying the next address in the video signal memory 16 to be used for storage. The field memories 13, 14 and 15 are controlled by the write address signal S₁ to store the image data from the latching circuit 12 in a memory area starting at the address identified by the write address signal. The write address counter 17 is connected to receive an input from a memory switching control circuit 18 which includes an address control circuit 19. The address control circuit 19 supplies an address load signal S₂ to the write address counter 17. The address load signal S₂ specifies a loading address. The write counter 17 periodically increments the loading address in order to derive the write address signal for supply in response to a reproduction locking signal S₃ from the demultiplexing circuit 11. The first, second and third field memories 13, 14 and 15 are also connected to receive a control input from a read address counter 21, specifically to receive a read address signal S₄ which identifies the next address in the memory 16 to be accessed for data retrieval. The field memories 13, 14 and 15 respond to the read address signal S₄ from the read address counter 21 by retrieving the image data recorded in the memory area starting at the address specified by the read address signal S₄. The read address counter 21 is, in turn, connected to receive an input from the address control circuit 19 in the memory switching control circuit 18 to receive an address load signal S₅. The read counter 21 increments or decrements a loading address specified by the address load signal S₅. The counter value of the read address counter 21 specifies which of the first, second and third field memories 13, 14 and 15 is to be accessed. The image data retrieved from the appropriate field memories 13,14 or 15 of the video signal memory 16 in response to the read address signal S₅ from the read address counter 21 are fed to a multiplexing circuit 23 via a latching circuit 22. The multiplexing circuit 23 converts the parallel data latched by the latching circuit 22 into a serial reproduced video output signal V out . The memory switching control circuit 18 generally selects one of the first, second and third field memories 13, 14 and 15 in accordance with a memory-management mode selected on the basis of the data recorded on the magnetic video tape 1 which depends upon the reproduction mode and drive direction selected manually via a control panel (not shown). A scanning mode detecting circuit 24 connected for output to the address control circuit 19 supplies a signal identifying the current reproduction mode. As shown in Figure 3, the video magnetic tape 1 to which the preferred embodiment of the video signal reproducing system of the invention is applied has a plurality of helical tracks A to J. As will be appreciated from Figure 3, each group of helical tracks A to J covers one field of image data. The track A is adjacent to the track J of the preceding group of tracks. The track A will be referred to hereafter as the "leading boundary track" and the track J will be referred to as the "trailing boundary track". Furthermore, each group of tracks consisting of the tracks A to J will be referred to hereafter as a "record area". The record areas covering odd-numbered fields will be referred to as "odd number record areas" and those covering even-numbered fields will be referred to as "even number record areas". Obviously, odd number record areas and even number record areas alternate along the tape with each leading boundary track A adjoining the trailing boundary track J of the preceding record area. As shown in Figure 5, the scanning mode detecting circuit 24 includes a boundary track detecting circuit 31. The boundary track detecting circuit 31 detects when the rotary head is scanning one of the boundary tracks A or J. The boundary track detecting circuit 31 includes a first detector circuit 32 having D flip-flop circuits D₁₁ and D₁₂. The first detector circuit 32 is responsive to a first detecting pulse OS produced when the head moves across the leading boundary track A of the odd number record area RE₁. The boundary track detecting circuit 31 also includes a second detector circuit 33 having D flip-flop circuits D₂₁ and D₂₂. The second detector circuit 33 is responsive to a second detecting pulse OE produced when the head moves across the trailing boundary track J of the odd number record area RE₁. The boundary track detecting circuit 31 further includes a third detector circuit 34 having D flip-flop circuits D₃₁ and D₃₂. The third detector circuit 34 is responsive to a third detecting pulse ES produced when the head moves across the leading boundary track A of the even number record area RE₂. The boundary track detecting circuit 31 further includes a fourth detector circuit 35 having D flip-flop circuits D₄₁ and D₄₂. The fourth detector circuit 35 is responsive to a fourth detecting pulse EE produced when the head moves across the trailing boundary track J of the even number record area RE₂. The detecting pulses OS and OE are produced by a detector circuit (not shown) when it detects an address code of Figure 2A recorded in the leading track A of an odd number record area RE₁. Therefore, the detecting pulses OS and OE are produced every time the head moves across the leading track A of an odd number record area RE₁. As will be appreciated from a comparison of Figures 3 and 6, in the SLOW mode, the phase of the detecting pulses OS and OE shifts through every cycle of the head rotation relative to the head position, as represented by a head position signal PG which will be referred to hereafter as the "PG signal", as the heads cross the boundary tracks at different points along the tracks A or J in successive head rotations. After a given number of cycles of rotary head rotation, the head will stop crossing the boundary track altogether until after another, larger number of head rotations. The detecting pulses OS and OE will of course be absent during this period. Figure 6 shows an example in which the head moves across the leading boundary track A three times in each such cycle of "beating of the head position PS and detecting OS-EE signals". As the head rotates in the forward direction, the detecting pulses OS and EE will be present while the head first crosses the leading boundary track A of the odd number record area RE₁. In other words, the detecting pulses OS and EE will occur in the same head scan when the head moves across both the trailing boundary track J of the even number record area RE₂ and the leading boundary track A of the subsequent odd number record area RE₁. Similarly, the detecting pulses ES and OE will nearly coincide when the head first crosses the leading boundary track A of the even number record area RE₂. In summary, the first to fourth detecting pulses OS, OE, ES and EE occur when the scanning trace of the head crosses the corresponding leading and trailing boundary tracks A and J of the odd number and even number record areas RE₁ and RE₂. It then becomes easy to recognize, for example, that the reproducing head is scanning the odd number record area RE₁ over the period from the first occurrence of the first detecting pulse OS to the last (third) occurrence of the second detecting pulse OE. Similarly, between the first occurrence of the third detecting pulse ES and the third occurrence of the fourth detecting pulse EE, the reproducing head is scanning the video data stored in the even number record area RE₂. It should also be noted that when the reproducing head moves across a leading or trailing boundary track, it may also be crossing the neighbouring trailing or leading track of the adjoining record area. Accordingly, the input video signal Vin sometimes contains image data for both odd number and even number fields. Image data for each field must be recorded in separate field memories 13 to 15 of the video signal memory 16 to allow separate signal processing of each field of image data. When the reproducing head is driven forwards, the detecting pulses occur in order of the first detecting pulse OS, the second detecting pulse OE, the first detecting pulse ES and the fourth detecting pulse EE. Alternatively, when the reproducing head is driven in the reverse direction, the order of occurrence of the detecting pulses is reversed, since the reproducing head moves from the trailing boundary track J towards the leading boundary track A in each record area. Therefore, during reverse driving of the reproducing head, the detecting pulses occur in the following order; the fourth detecting pulse EE, the third detecting pulse ES, the second detecting pulse OE and the first detecting pulse OS. Although the order of occurrence of the detecting pulses differs from that in forward drive, reproducing operations themselves remain substantially the same as in the forward drive mode. Returning to Figure 5, the D flip-flop circuits D₁₁ and D₁₂ each have a preset terminal PR receiving the first detecting pulse OS. The flip-flop circuits D₁₁ and D₁₂ are set in response to the first detecting pulse OS. Also, the PG signal is applied to the flip-flop circuits D₁₁ and D₁₂ as a trigger signal. The flip-flop circuit D₁₁ is triggered by the PG signal and reset by a logical-0 input at its D-terminal. The D-terminal of the flip-flop circuit D₁₂ is connected to the Q-terminal (set output terminal) of the flip-flop circuit D₁₁. Therefore, the flip-flop circuit D₁₂ is reset when the flip-flop circuit D₁₁ is reset. Therefore, the output at the Q-terminal of the flip-flop circuit D₁₂ drops to logical-0 in response to the first pulse of the first detecting signal OS. (The detecting pulses OS-EE are all inverse-logic pulses.) After the last pulse of the first detecting signal OS, the output at the Q -terminal returns to logical 1 in response to two successive second PG signal pulses: the output at the Q-terminal of the flip-flop circuit D₁₂ will be hereafter referred to as the "first detector output OSG". Similarly, the second, third and fourth detector circuits 33, 34 and 35 supply the second, third and fourth detector outputs OEG, ESG and EEG through respective Q -terminals of the flip-flop circuits D₂₂, D₃₂ and D₄₂, in response to the PG signal. Each of the second, third and fourth detector outputs OEG, ESG and EEG varies in substantially the same manner as set out with respect to the first detector output OSG. Specifically, each of the second, third and fourth detector outputs OEG, ESG and EEG drops to the logical-0 level in response to the first pulse of corresponding detecting signal OE, ES and EE and returns to the logical-1 level in response to two successive PG signal pulses. The Q -terminals of the second-stage flip-flop circuits D₁₂, D₂₂, D₃₂ and D₄₂ of the first to fourth detector circuits 32, 33, 34 and 35 are connected to supply an output to a switching circuit 41. The switching circuit 41 is, in turn, connected to an odd number field scan detecting circuit 42 and an even number field scan detecting circuit 43. The odd number field scan detecting circuit 42 and the even number field scan detecting circuit 43 comprise D-flip-flop circuits. The switching circuit 41 is also connected to receive a forward/reverse switching signal FR from a manually operable forward/reverse switch which controls the switch position of the switching circuit 41. The switching circuit 41 supplies set signals ST₁ and ST₂ in response to the first and third detector outputs OSG and ESG, and supplies reset signals RT₁ and RT₂ in response to the first and third detector outputs OSG and ESG, and supplies reset signals RT₁ and RT₂ in response to the second and fourth detector outputs OEG and EEG, when the switching signal FR is at a level indicative of forward drive. The set signals ST₁ and ST₂ are supplied from the switching circuit 41 to present terminals RP of the flip-flop circuits 42 and 43 serving respectively as the odd number field scan detector circuit 42 and the even number field scan detector circuit 43. In addition, the switching circuit 41 supplies the reset signals RT₁ and RT₂ to trigger inputs of the flip-flop circuits 42 and 43. In the circuit arrangement set forth above, the flip-flop circuit of the odd number field scan detector circuit 42 is set in response to trailing edges of HIGH-level first detector output pulses OSG and is reset by the constant logical-0 input at its D-terminal in response to the leading edge of the HIGH-level second detector output OEG. Therefore, as shown in Figure 6 (D₁), the flip-flop 42 supplies through its Q -terminal an odd number field scan indicative signal I₁ which is held at logical-0 value for the period T₁ during which the head scans through the odd number record area RE₁. Similarly, the flip-flop circuit of the even number field scan detector circuit 43 is set in response to the trailing edge of HIGH-level third detector output pulses ESG and is reset in response to the leading edge of HIGH level fourth detector output EEG. Therefore, as shown in Figure 6 (D₂), the output I₂ at the Q -terminal of the flip-flop 43 is held at logical-0 value for the period T₂ during which the head scans through the even number record area RE₂. Alternatively, when reverse drive is selected, the switching circuit 41 supplies the set signal ST₁ and ST₂ In response to the second and fourth detector outputs OEG and EEG, and the reset signal RT₁ and RT₂ in response to the first and third detector outputs OSG and ESG. The flip-flop circuit 42 is set in response to the trailing edge of the HIGH-level second detector output OEG and reset in response to the leading edge of the first detector output OSG. Therefore, as above, the output I₁ at the Q -terminal of the flip-flop circuit 42 is held at logical-0 value for the period T₁ during which the head scans in the reverse direction through the odd number record area RE₁, as shown in Figure 6 (D₁). Likewise, the flip-flop circuit 43 is set in response to the trailing edge of the fourth detector output EEG and reset in response to the leading edge of the third detector output ESG. Thus, the output I₂ at the Q -terminal of the flip-flop circuit 43 is held at logical-0 value for the period T₂ during which the head scans in the reverse direction through the even number record area RE₂. It should be appreciated that, in Figure 6, the time axis progresses from right to left and the detector outputs OSG, OEG, ESG and EEG drop at points coincident with the first pulse of the corresponding detecting pulse OS, OE, ES and EE and remain at logical-0 until the second PG pulse following the last pulse of the corresponding detecting pulse. The flip-flop circuits 42 and 43 have inverting output terminals ( Q -terminals) through which the logical inverts of the odd number field scan indicative signal I ₁ and the even number field scan indicative signal I ₂ respectively are supplied, as shown in Figure 6 (E₁) and (E₂). These inverted signals I ₁ and I ₂ are processed by differentiation circuits 44 and 45. The differentiation circuits 44 and 45 respond to the leading edge of the respectively corresponding inverted signal I ₁ and I ₂ to supply switching pulses CH₁ and CH₂, during forward drive operation. Alternatively, in reverse drive operation, the differentiation circuit 44 and 45 supplies the switching signals CH₁ and CH₂ in response to the trailing edge of the corresponding inverted signals I ₁ and I ₂ Therefore, as can be easily appreciated, the differentiation circuit 44 and 45 supplies the switching pulses CH₁ and CH₂ every time the scan switches between an odd number field and an even number field according to change of the logical level of the input from the flip-flop circuits 42 and 43 as set forth above. As shown in Figure 7, the switching pulses CH₁ and CH₂ are supplied to a NAND gate 51 which is, in turn, connected to supply outputs to a memory selection switching circuit 52 and a memory switching disabling circuit 53. In this arrangement, the gate signal of the NAND gate 51 serves as a trigger signal for the memory selection switching circuit 52 and the memory switching disabling circuit 53. As shown in Figure 7, the Q -terminals of the flip-flops 42 and 43 are connected to an exclusive-OR gate 55 which serves as a disabling condition detector. The memory selection switching circuit 52 selects into which of the field memories 13, 14 and 15 the odd number and even number field image data from the reproducing head are to be stored. The memory selection switching circuit 52 similarly serves to specify from which of the field memories 13, 14 and 15 recorded image data are to be retrieved. The memory selection switching circuit 52 is also connected to the manually operable forward/reverse switch to receive the forward/reverse switching signal FR as an up/down control signal. The circuit 52 includes an up/down counter 52a to increment and decrement the memory selection code. These changes in the up/down counter 52a are controlled in accordance with the forward/reverse switching signal FR. That is, the up/down counter 52a increments the memory selection code during the forward drive operation and decrements it during reverse drive operation. The resultant counter value of the up/down counter 52a is fed to a load address converter circuit 54. As shown in Figure 7, the counter value is supplied in the form of three binary signals QC, QB and QA, making up a 3-bit code. Therefore, the load address converter circuit 54 receives QC, QB and QA as counter value indicative data. The load address converter circuit 54 derives a writing address load signal S₂ on the basis of the 3-bit counter output QC, QB and QA. The write address load signal S₂ is supplied to the write address counter 17 as mentioned previously. The load address converter circuit 54 also derives a read address load signal S₅ on the basis of QC, QB and QA to identify which of the field memories 13, 14 and 15 to access. The read address load signal S₅ is fed to the read address counter 21. The load address converter circuit 54 also receives an odd/even field indicative signal OES recorded on the video tape and picked up by the reproducing head 2. The load address converter circuit 54 further includes ROM 54a storing a look-up table scheduling access to of the field memories 13, 14 and 15. The look-up table stored in ROM 54a is as follows: OES QC QB QA S2 S5 Odd Even O 0 1 0 #1 #3 O/E 0 1 0 #1 #2 #3 E 0 1 1 #2 #1 O/E 0 1 1 #3 #2 #1 O 1 0 0 #3 #2 O/E 1 0 0 #3 #1 #2 E 1 0 1 #1 #3 O/E 1 0 1 #2 #1 #3 O 1 1 0 #2 #1 O/E 1 1 0 #2 #3 #1 E 1 1 1 #3 #2 O/E 1 1 1 #1 #3 #2 Values for the signals S2 and S5 are found in the table in the ROM 54a in terms of the code signal values QA, QB and QC and the odd/even field indicative signal OES. For example, when the number represented by the code signal QC, QB and QA is "010", and the odd/even field indicative signal OES indicates scanning of the odd number field only, the load address converter circuit 54 generates a write address load signal identifying the first field memory 13 and a read address load signal S₅ identifying the third field memory 15, as shown in Figure 8. In response to the write address load signal S₂ and the read address load signal S₅ thus derived, the image data are stored in the first field memory 13 and recorded image data in the third field memory 15 are read out. On the other hand, when the code signal is "010" and the odd/even field indicative signal OES indicates scan of both odd and even-numbered fields, the write address load signal S₂ specifies both of the first and second field memories 13 and 14. At the same time, the read address load signal S₅ specifies the third field memory 15. In this case, the image data for the odd number field are stored in the first field memory 13 and the even number field image data are stored in the second field memory 14. As above, the image data recorded in the field memory 15 are read out, at the same time. Therefore, the image data recorded in the third field memory 15 are at this time, reproduced on a video monitor. After storing the image data in one of the field memories 13, 14 and 15, the switching pulse CH₁ and CH₂ is produced. The memory selection switching circuit 52 is responsive to the switching pulses CH₁ and CH₂, to increment or decrement the code signal QA, QB and QC in a predetermined order according to the forward/reverse drive identified by the forward/reverse indicative signal FR. Therefore, in the above example, the memory selection switching circuit 52 supplies the code signals QC, QB and QA reading "011" in response to the switching pulses CH₁ and CH₂. In this case, the even field image data would be stored in the second field memory 14 and the odd number field image data would be stored in the field memory 15. In addition, the first field memory 13 would be accessed for the previously stored image data. As will be appreciated herefrom, the memory selection switching circuit 52 increments or decrements the up/down counter value in response to each switching pulse CH₁ and CH₂ to update the read/write states of the first, second and third field memory 13, 14 and 15. The field memories 13, 14 and 15 are selectively designated for storage of image data according to the order determined by the look-up table in ROM 54a of the load address converting circuit 54. On the other hand, the field memory to which writing in the image data is finished, is subsequently accessed for the previously stored image data. Therefore, in the foregoing example, since the field memory 13 will have completed its writing operation at the next change of the switching pulses CH₁ and CH₂, the image data recorded in the first field memory 13 will be read out next, after the code signal value changes from "010" to "011". Here, in the embodiment, the code signal value may shift, during forward drive operation, in the table sequence "010", "011" ..."111", "010". On the other hand, during reverse mode operation, the code signal value may shift through the reverse order: "010", "111", "110" ..."010". The order of selection of the field memories 13, 14 and 15 for image data storage and image data retrieval is reversed when the head drive direction is reversed. In the foregoing example, when the code signal value switches from "011" to "100", the second field memory 14, in which the even number field data are all stored before the next switching pulse CH₁ or CH₂, is next accessed for retrieval of the stored image data. The memory selection switching circuit 52 and the load address converter circuit 54 together form the address control circuit 19 in conjunction with the memory switching disabling circuit 53. The memory switching disabling circuit 53 disables the switching operation of the memory selection switching circuit 52. The memory switching disabling circuit 53 comprises a counter 53a clocked by the output of the NAND circuit 51. The memory switching disabling circuit 53 also has a load data input terminal LA which is directly connected for input from the exclusive-OR gate 55, and another load data input terminal LB which is connected for input from the exclusive-OR gate 55 through an inverter 56. The exclusive-OR gate 55 receives the odd-numbered field indicative Q-terminal output I₁ and the even number field indicative Q-terminal output I₂ as condition inputs. On the basis of the condition inputs, the exclusive-OR date 55 supplies a condition signal I H to the load data input terminal LA and inverted load condition signal I H to the load input terminal LB through the inverter 56. On the basis of the inputs from the Q-terminals of the flip-flop circuits 42 and 43, the disabling circuit derives disabling conditions according to the following table. I₁ I₂ LB LA Disabling release condition 1(odd) 0(even) 0 1 twice 0(even) 1(odd) 0 1 twice 1(odd) 1(odd) 1 0 once 0(even) 0(even) 1 0 once As will be appreciated herefrom, when the reproducing head scans both an odd number record area and an even number record area, the combination of outputs I₁ and I₂ from the Q -terminals of the flip-flops becomes "1:0" or "0:1". Therefore, the combination of input levels at the load data input terminals LA and LB will be "1:0" in both cases. On the other hand, when the reproducing head scans only one of the odd number record area and the even number record area, the combination of outputs I₁ and I₂ will be "1:1" or "0:0". Therefore, the combination of load data inputs LA and LB will be "0:1". The memory switching disabling circuit 53 also has a load input LOAD which is connected to receive an input from a switching timing detector circuit 57 as a detector signal CT. The switching timing detector circuit 57 generally comprises a pair of D-flip-flops D₅₁ and D₅₂. The D-flip-flop D₅₁ receives the switching signal FR at its D-terminal. The Q-terminal of the flip-flop D₅₁ is connected to the D-terminal of the second-stage flip-flop D₅₂. Also, the Q-terminal of the first-stage flip-flop D₅₁ is connected to one input of an exclusive-OR gate EX. To the other input of the exclusive-OR gate EX, the Q -terminal of the second-stage flip-flop D₅₂ is connected. The exclusive-OR gate EX derives the logical sum of the outputs from the flip-flops D₅₁ and D₅₂. The logical sum derived by the exclusive-OR gate EX serves as the detector signal CT of the switching timing detector circuit 57. The detector signal CT drops to logical 0 from logical 1 when the switching signal FR switches state. The trailing edge of the logical-1 detector signal CT triggers the memory switching disabling circuit 53 to sample the values at its load data inputs LA and LB. Therefore, when the driving direction is reversed from forward to reverse or from reverse to forward, the load data "1:0" or "0:1" are read from the load data inputs LA and LB. The memory switching disabling circuit 53 is then responsive to the output of the NAND gate 51 produced in response to the switching pulses CH₁ and CH₂. Assuming that the inputs through the load data inputs LA and LB are "1:0", the memory switching disabling circuit 53 supplies a carrier signal CA after two successive inputs from the NAND gate 51. On the other hand, assuming the load data inputs LA and LB are "0:1", then the memory switching disabling circuit 53 supplies the carrier signal CA after the next input from the NAND gate 51. The carrier signal CA is supplied to the memory selection switching circuit 52 via an inverter 58 and serves as an enabling signal for the memory selection switching circuit 52. When enabled by the carrier signal CA, the memory selection switching circuit 52 can increment or decrement the memory selection code. The memory switching disabling circuit 53 is held in this condition until the next detector signal CT is received from the switching timing detector circuit 57. As will be appreciated herefrom, when the head drive is reversed while the reproducing head is scanning both an odd number record area and an even number record area, the memory selection switching circuit 52 is disabled until two switching pulses CH₁ and CH₂ are received. On the other hand, when the head drive is reversed while the reproducing head is scanning only one of the odd number and even number record areas, the memory selection switching circuit 52 is disabled until the next single switching pulse CH₁ or CH₂. As shown in Figure 8, when the video tape 1 is driven in the forward direction, image data of the odd number fields and even number fields O₁₁, E₁₁, O₁₂, E₁₂, O₁₃, E₁₃ are supplied as reproduction input data Vin. During this forward reproduction operation, when the reproducing head scanning the odd number record area O₁₁ approaches the trailing boundary track J, the reproducing head starts to scan the even number record area E₁₁ as well. Of course, when the reproducing head scans across both of an odd number record area O₁₁ and an even number record area E₁₁, the reproducing input signal Vin contains image data from both the odd number field O₁₁ and the even number field E₁₁. The memory selection switching circuit 52 of the address control circuit 19 supplies the memory selection code QC, QB and QA as described previously. This memory selection code is labelled "SELECTION CODE" in Figure 8. As shown in Figure 8, when the video tape 1 is driven in the forward direction, the memory selection code follows the sequence "100", "101", "110", "111", "010", "011". The memory selection switching circuit 52 supplies the memory selection code to the load address converter circuit 54 to designate one or two of the field memories 13, 14 and 15 for storage of the image data contained in the reproduction input signal Vin and the remaining field memory 13, 14 or 15 for access to and reproduction of the previously stored image data. In the example shown in Figure 8, when the reproducing head starts scanning the odd number record area O₁₁, the memory selection code is "011", and therefore, the image data from the record area O₁₁ is stored in the third field memory 15. At the same time, the image data in the record area E₁₀ are stored in the second field memory 14, as shown in the TABLE I. After completing the scan of the record area E₁₀, the memory selection code changes to "100". Therefore, the third field memory 15 is continuously designated for storage of the image data from the record area O₁₁. At this time, the second field memory 14 is designated for access to the stored image data. Upon reaching the trailing boundary track J, the reproduction input data Vin start to include image data from both the odd number record area O₁₁ and the even number record area E₁₁. As a result, the first field memory 13 is designated for storage of the image data from the record area E₁₁. When the second detector output OEG is output during scanning of the trailing boundary track J of the odd number record area O₁₁, the switching pulse CH₁ or CH₂ is supplied from one of the differentiation circuits 44 and 45. The memory selection switching circuit 52 then increments the switching pulse so that the memory selection code becomes "101". As a result, the first field memory 13 is still used to store the image data from the even number record area E₁₁. On the other hand, the third field memory 15 is designed for retrieval of stored image data from the record area O₁₁. The image data read from the third field memory 15 are supplied as the reproduction output Vout. In summary, in response to each switching pulse CH₁ or CH₂, the memory selection code is incremented by one while the video tape 1 is driven forward. Incrementing the memory selection code reallocates the field memories for storage and retrieval of image data. Of course, the image data to be read out of field memory are the same image data stored in the last storage operation. When the tape drive is reversed from forward to reverse while only the even number record area E₁₃ is being scanned, in which case the memory selection code is "011", the switching timing detector circuit 57 is triggered by the forward/reverse switching signal FR to supply the detector signal CT to the memory switching disabling circuit 53. At this time, the inputs I₁ and I₂ to the exclusive-OR gate 55 are "0:0". Therefore, the load data inputs LA and LB are "1:0". As a result, the memory switching disabling circuit 53 supplies a disabling signal to the memory selection switching circuit 52 through the inverter 58. At this time, since a single record area is being scanned, the memory selection switching circuit 52 is disabled until the next switching pulse CH₁ or CH₂. Therefore, in this state, the second field memory 14 is still designated for storage of image data contained in the reproduction input signal Vin. At the same time, the first field memory 13 is designated for retrieval of image data. As the reproducing head approaches in reverse the leading boundary track A of the record area E₁₃, the switching pulse CH₁ or CH₂ is supplied to the memory section switching circuit 52 and the NAND circuit 51 supplies a pulse to the memory switching disabling circuit 53. Since the load data input LA and LB read "1:0", the memory switching disabling circuit 53 responds to the NAND circuit output by supplying the carrier signal CA to the memory selection switching circuit 52. As a result, the memory selection switching circuit 52 is enabled to decrement the switching pulses CH₁ and CH₂. During this initial stage after reversal of the tape drive direction from forward to reverse, the reproducing head, as it approaches the leading boundary track A of the record area E₁₃, starts scanning across the tracks in the record area O₁₃. Even after receipt of the enabling carrier signal CA, the memory selection code in the memory selection switching circuit 52 remains "011". Therefore, the third memory 15 is newly designated for storage of the image data from the record area O₁₃. Also, the first field memory 13 continues to be accessed for retrieval of image data. When the scanning of the record area O₁₃ is finished, the switching pulse CH₁ or CH₂ is again supplied to the memory selection switching circuit 52. The memory selection switching circuit 52 decrements the switching pulse CH₁ or CH₂. Figure 9 illustrates the situation in which the tape drive is reversed from forward to reverse while the reproducing head is scanning both an odd number record area O₁₃ and an even number record area E₁₂. The switching timing detecting circuit 57 produces the detector signal CT in response to the forward/reverse switching signal FR. The memory switching disabling circuit 53 is responsive to the detector signal CT to read the load data input LA and LB. In this case, the load data inputs LA, LB are of the combination "0:1", the memory switching disabling circuit 53 supplies a disabling signal to the memory selection switching circuit 52 to disable counting operation of the latter for two occurrences of the switching pulses CH₁ or CH₂. Therefore, after being disabled, the memory selection switching circuit 52 will not respond to the next two switching pulses CH₁ or CH₂. Since the memory selection code at the moment of reversal of the tape drive was "010", this code value is maintained until the third successive switching pulse CH₁ or CH₂. For instance, as seen from Figure 9, since the third field memory 15 was being accessed for retrieval of image data when the forward/reverse switching signal FR arose, it continues to be accessed until the third switching pulse CH₁ or CH₂ is received. During this period, the second field memory 14 is used for storage of image data from the record area E₁₃ and the first field memory 13 is used for storage of image data from the record area O₁₃. After completion of the scan of the record area E₁₃, the first switching pulse CH₁ or CH₂ is supplied to the memory selection switching circuit 52 and also to the memory switching disabling circuit 53 through the NAND gate 51. However, since the memory selection remains disabled, the memory selection code remains "010". Therefore, the image data in the record area O₁₃ continue to be stored in the first field memory 13 and image data stored in the third field area 15 continue to be retrieved for video reproduction. As will be appreciated from Figure 9, the image data to be read out during this period are the image data from the record area E₁₂ stored before reversal of the tape drive direction. As the video tape 1 continues in reverse, the reproducing head reaches the boundary between the record areas O₁₃ and E₁₂ and starts to pick up image data from both record areas. As shown in Figure 9, the image data from the record area E₁₂ are stored in the second field memory 14, at this time. When the scanning of the record area O₁₃ is finished, the second switching pulse CH₁ or CH₂ is supplied. As a result, the memory switching disabling circuit 53 is triggered to supply the carrier signal CA. The memory selection switching circuit 52 is responsive to the carrier signal CA received via the inverter 58 to return to its enabled state. At this time, however, since the second switching pulse CH₁ or CH₂ does not change the memory selection code, the image data from the record area E₁₂ continue to be stored in the second field memory 14. Also, the image data from the record area E₁₂ stored in the third field memory 15 continue to be retrieved. After completion of the scan of the record area E₁₂, the third switching pulse CH₁ or CH₂ is produced. The memory selection switching circuit 52 decrements the memory selection code to "111" in response to the third switching pulse CH₁ or CH₂. As a result, the first field memory 13 is designated for storage of image data from the record area O₁₂. At the same time, the second field area, now holding image data from the record area E₁₂, is designated for retrieval. Therefore, the video image reproduced on the video monitor remains unchanged. After this, video image data are scanned, stored, retrieved and reproduced in the same manner as explained with respect to forward tape drive. The only difference is the order of update of the memory selection code, which is the reverse of that in forward tape drive. Various modifications are of course possible; for example, although three field memories have been used in the described embodiment, more field memories can be used.

Claims: A method of reproducing a video signal recorded on a video tape (1) in the form of a plurality of tracks, the method comprising the steps of: providing a memory means (16) including at least three memories (13, 14, 15), each capable of holding all of the image data for one field picked up from the recording tracks of the video tape (1) by a reproduction head (2); characterized by: selecting one of said memories (13, 14, 15) in said memory means (16) for storage of the image data from the field currently being picked up by said head (2), a storage control means (18, 17) selecting said memories (13, 14, 15) in a given order and detecting inclusion of image data from more than one field in an input video signal from said head (2) and selecting more than one memory (13, 14, 15) for storage of image data for each field separately; selecting one of said memories (13, 14, 15) currently holding one field of image data in a predetermined sequence for retrieval of the stored image data as an output video signal; monitoring the selection condition of said memory means (16); detecting reversal of the tape drive direction; and disabling, in response to reversal of the tape drive direction, selection of a different said memory (13, 14, 15) for retrieval and supply of the stored data for a period of time related to said monitored selection condition of said memory means (16). A method according to claim 1 wherein said period of time is variable depending upon the scanning condition of a rotary head (2) forming said reproduction head (2), in such a manner that, when said rotary head (2) is scanning a single field, said period of time may be shorter than when said rotary head (2) is scanning more than one field. A method according to claim 1 or claim 2 wherein said selection of a said field memory (12,13,14) or disablement thereof is triggered by a pulse signal produced each time the scanning of one record area is completed. Apparatus for reproducing a video signal recorded on a recording medium (1) in the form of a plurality of tracks, comprising: a memory means (16) including at least three memories (13,14,15), each capable of holding all of the image data for one field picked up from the recording tracks of the recording medium (1) by a reproduction head (2); characterized by: storage control means (18,17) for selecting one of said memories in said memory means for storage of the image data from the field currently being picked up by said head (2), said storage control means (18,17) selecting the memories (13,14,15) in a given order and detecting inclusion of image data from more than one field in an input video signal from said head (2) and selecting more than one memory (13,14,15) for storage of image data for each field separately; retrieval control means (18,21) for selecting one of said memories (13,14,15) currently holding one field of image data in a predetermined sequence for retrieval of the stored image data as an output video signal; a memory condition detecting means (52,54) for monitoring the selection condition of said memory (16); a drive direction detecting means (53) for detecting reversal of the tape drive direction; and a memory switching disabling means (53), responsive to reversal of the tape drive direction, for disabling selection of a different memory (13,14,15) for retrieval and supply of the stored data for a period of time related to the memory selection condition detected by said memory condition detecting means (52,54). Apparatus according to claim 4 wherein said memory condition detecting means (52,54) includes a signal generator (52a) which produces a memory switching demand each time the scanning of one field of image data is completed. Apparatus according to claim 4 wherein said storage control means (18,17) include a counter means (17) for counting said memory switching demand for deriving a binary code, and a look-up table (54a) to be looked up in terms of said binary code for deriving a memory selection control signal which identifies said memories (13,14,15) for writing said image data. Apparatus according to claim 4 wherein said retrieval control means (18,21) is also responsive to said memory selection control signal for selecting one of memories (13,14,15) for retrieval and supply of the stored image data. Apparatus according to claim 4 wherein said memory condition detecting means (52,54) is arranged to detect the selection condition of said memory (16) between a first condition in which a single memory (13,14,15) is selected for storing one field of image data, and a second condition in which two memories (13,14,15) are selected for storing two fields of image data. Apparatus according to claim 8 wherein said memory switching disabling means (53) derives said disabling period of time in such a manner that, when said memory condition detecting means (52,54) detects said first condition, a first shorter period is derived, and when said memory condition detecting means (52,54) detects said second condition, a second longer period is derived. Apparatus according to claim 9 wherein said first period corresponds to a period of time in which one memory switching demand is supplied, and said second period corresponds to a period of time in which two of said memory switching demands are supplied. Apparatus according to claim 5 wherein said memory condition detecting means (52,54) is arranged to detect the selection condition of said memory (16) between a first condition in which a single memory (13,14,15) is selected for storing one field of image data, and a second condition in which two memories (13,14,15) are selected for storing two fields of image data. Apparatus according to claim 11 wherein said memory switching disabling means (53) derives said disabling period of time in such a manner that, when said memory condition detecting means (52,54) detects said first condition, a first shorter period is derived, and when said memory condition detecting means (52,54) detects said second condition, a second longer period is derived. Apparatus according to claim 12 wherein said first period corresponds to a period of time in which one memory switching demand is supplied, and said second period corresponds to a period of time in which two of said memory switching demands are supplied. Apparatus according to claim 13 wherein said counter means (17) is arranged to count up said memory switching demands to increment said binary code by one at every occurrence of a said memory switching demand while said drive direction detecting means (53) detects driving of the video tape (1) in a first direction, and to count down said memory switching demand to decrement said binary code by one at every occurrence of said memory switching demand while said drive direction detecting means (53) detects driving of said video tape (1) in a second direction opposite to said first direction. Apparatus according to claim 14 wherein said signal generator (52a) includes a detector for detecting the rotary head position scanning at least one of a leading and a trailing boundary of a record area constituted by a plurality of tracks for generating said memory switching demand.

Inventors: KOMINAMI, HISANORI C/O PATENT DIVISION
Applicants: SONY CORPORATION
Application year: 1985
Main classification: H04N5
IPC codes: H04N5, G11B20