MULTI-STATE SIGNAL MONITOR CIRCUIT

Abstract: A multi-state signal monitor circuit for a data transmis­ sion system which transmits a plurality of bits of data after conversion into a multi-state signal and obtains original data of plural bits through analog-to-digital conversion of the received multi-state signal. Data is discriminated more precisely than the number of bits of data of a plurality of bits on the occasion of analog-to-digital conversion in the receiving side (10B) and the focusing degree of the received signal to the quantization level is detected by utilizing said extra bits. Thereby the error rate is monitored quickly and accurately with simplified circuits. The monitor circuit comprises an A-D converter (120) and a pseudo error rate measuring circuit (122).

Description: The present invention relates to multi-state-signal monitor circuit provided at the receiving side of a system for transmitting the data of plural bits by means of a multi-state signal. Various systems have been proposed for transmitting data having plural bits after converting it into a multi-state signal. For example, in a digital radio transmission system utilizing quadrative amplitude modulation (QAM), the I-channel data and Q-channel data are respectively converted to multi-state signals. Two carriers having a phase difference of 90 degrees are respectively amplitude modulated and combined for transmission. The receiving signal is quadrature-detected by the carrier regenerated from said receiving signal and the I-channel and Q-channel multi-state signals thus obtained are converted to digital from analog form in order to obtain the original data. In such a transmission system, if the radio link fails due to fading, etc., the error rate of received data becomes high and therefore if the error rate measured exceeds a specified value, the transmission line is switched to a spare transmission line or an equalizer is reset in order to prevent divergence of the equalizer. As a method for measuring the error rate of received data, particular pattern is transmitted from the transmitting side and the accuracy of said pattern received is checked in the receiving side. However, this method has the following disadvantages: a) Transmission capacity is reduced owing to transmission of said particular pattern. b) A complicated circuit is required for detecting said particular pattern. c) The error rate is usually small and therefore a longer time is taken for a cycle of measurement or a large time constant of integration is required for accurate measurement and thereby detection is much delayed. As another method for measuring error rate of received data, a plurality of comparators for discriminating the quantization level and other levels and logic circuits for logically calculating outputs of such comparators are provided, a number of times of displacement from the quantization level at the time of discrimination of a received multi-state signal is measured as a speudo error rate and it is used as that corresponding to error rate. However, this method contains the following problem: d) Many comparators are required and the logic circuits for calculating outputs from them are complicated as the number of bits of data to be transmitted increases and quantization levels increase. As a further method for obtaining error rate of received data, analog to digital conversion is carried out at normal discrimination timing and at a timing a little shifted from the normal discrimination timing. The number of decisions for the value different from that of the normal discrimination timing is measured as a pseudo error rate and it is used as the value corresponding to the error rate. However, this method has the following disadvantages: e) Another analog to digital converter is required for detection of the pseudo error rate, increasing the scale of the circuit. f) Since the rate of deterioration of focusing degree to the quantization level due to the shift from the correct discrimination timing is different depending on the causes of line failure (for example, multi-path-fading by reflected wave, attenuation of signal by rain fall and device failure) accurate correspondence to error rate cannot be obtained. US-A- 4 305 150 discloses an on-line channel monitor for measuring the quality of a communication channel of a transmission system wherein data is transmitted from the sending side after it is converted to a PSK signal and said data is regenerated through discrimination of said PSK signal in the receiving side. In the receiving side there is provided an analog-to-digital converter for discriminating the multi-state signal into a number of upper bits, which correspond to said data, and a plurality of lower bits, which serve for identifying the specified ranges separated from the quantization levels of said multi-state signal. Moreover it is provided a pseudo error rate measuring circuit for measuring the frequency of entering said specific ranges. It is an object of the present invention to provide quick and an accurate error rate measurement in a QAM transmission system with multi-level amplitude modulation without reducing transmission capacity. Briefly, an analog-to-digital converter for discriminating the received multi-state signal more precisely by a plurality of bits greater than the number of bits corresponding to the transmitted data and a pseudo error rate measuring circuit for reasuring the frequency of said plurality of bits to show the specified range separated from the quantization levels of said multi-state signal is provided in a transmission system being a QAM-system with multi-level amplitude modulation. Fig. 1A and Fig. 1B show block diagrams of transmitting side and receiving side of a 16-value QAM-radio transmission system to which the present invention is applied; Figs. 2A to Fig. 2C show waveforms of a 4-value signal in which the high frequency component is not limited, a 4-value signal in which the high frequency component is limited, and a clock signal; Fig. 3A and Fig. 3B show profiles for explaining embodiments of the present invention; and Figs.4A to Fig. 4G are block diagrams of embodiments of the present invention. In transmitting side apparatus 10A of a 16-value QAM radio transmission system shown in Fig. 1A, digital-to-analog converters 101, 102 respectively convert the 2-bit data DI, DQ of two systems of Inphase -channel (I-ch) and Quadrature-channel(Q-ch) into the 4-value signals shown in Fig. 2A. In Fig. 2A, V₀toV₃ show the quantization levels. The low-pass-filters 103 and 104 limit the high frequency component of said 4-value signals and shape the waveform as shown in Fig. 2B. Meanwhile, a 90 o hybrid 105 branches the carrier output from an oscillator 106 into a couple of carriers having the phase difference of 90 o and then outputs them to the mixers 107, 108, which respectively amplitude modulate said two carriers with a couple of said 4-value signals where the higher frequency components are limited. Said two modulated signals are combined in a hybrid 109 and then tramsitted from an antenna 111 via a transmitter 110. In the receiving side apparatus 103 shown in Fig. 15, an incoming signal is received by a receiver 113 from an antenna 112. Said received signal is branched to the I-ch and Q-ch by a hybrid 114. Meanwhile, a 90 o hybrid 115 branches two carriers having phase difference of 90 o regenerated by the carrier regeneration circuit 116 and then outputs these signals to the mixers 117, 118 respectively, which respectively obtain the original 4-value signals by demodulating said I-ch and Q-ch received signal using said couple of regenerated carriers. Said demodulated couple of 4-value signals become similar to the modulated signal in the transmitting side shown in Fig. 2B when the line is normal. Even if the line fails, the signal is equalized by an equalizer 119 so long as such failure is minor and the signal is similar to that shown in Fig. 2B. As such carrier generation circuit and equalizer, those disclosed in the EP-A-0 129 514 are possible. The demodulated 4-valve signals of I-ch and Q-ch are respectively discriminated by the analog-to-digital converters 120 and 121. Thus , the I-ch is discriminated into the 4 bits (b₀ b₃), while Q-ch is discriminated into the 2 bits (b₀,b₁) respectively at the time instants where the clock shown in Fig. 2C rises. The respective upper two bits (b₀,b₁) are output as the discrimination data (D1,DQ) and the lower two bits (b₂, b₃) of I-ch are output to a pseudo error rate measuring circuit 122. The pseudo error rate measuring circuit 122 decides a pseudo error when the lower bits shows the range separated from the quantization levels (V₀∼V₃) and measures a frequency of such pseudo error as the pseudo error rate (err). As shown in Fig. 3A, the range quantized or discrimited into the quantization levels (V₀∼V₃) is classified into four ranges by said lower bits (b₂,b₃). Of these ranges, the ranges indicated by the lower two bits (b₂,b₃) of "00" and "11" are separated from the quantization levels as shown by γ in the Figure. The frequency of entering such range is considered as the pseudo error rate. As shown in Fig. 4A, the pseudo error rate measuring circuit 122 is basically composed of a pseudo error detection circuit 123 which receives the lower 2 bits (b₂,b₃) of analog-to-digital converter 120 and detects pseudo errors and a measuring circuit 124 which receives the detected output sent from said pseudo error detection circuit 123 and measures the number of such detections. The pseudo error detection circuit 123 is composed of an AND circuit 125 which ANDs said 2 bits (b₂,b₃), inverters 126 and 127 which respectively invert said 2 bits, an AND circuit 128 which ANDs the outputs of said inverters 126 and 127 and an OR circuit 129 which ORs the outputs of said AND circuits 125 and 128, and outputs "1" when said lower 2 bits are "00" or "11". The measuring circuit 124 is composed of a counter 130 which counts "1" output of the pseudo error detection circuit 123 and a timer which causes said counter 130 to output a value of said counter 130 for every constant period and also resets it, and outputs a value counting "1" within the constant period as the pseudo error rate. If the degree of convergence deteriorates due to line failure, the lower 2 bits of the analog-to-digital converter 120 more often become "00" or "11" and it is enough that the specified processing is carried out when said count value exceeds the predetermined value. As shown in Fig. 4B, the pseudo error detection circuit 123 may be formed only by a single exclusive OR circuit 132. However, since it outputs "0" when said lower 2 bits (b₂,b₃) are "00" or "11", the counter 130 of measuring circuit 124 is required to count a number of times of the input to become "0" As shown in Fig. 4C, the measuring circuit 124 may be formed by an integration circuit consisting of a resistor R and capacitor C and pseudo error rate may be output as an analog value. Where pseudo error detection is input at a high level, the difference between the integration output and a low level is determined as a pseudo error rate, where it is input at a low level, the difference between the integration output and a high level is determined as the pseudo error rate. As shown in Fig. 3B, in case decision is made more minutely by 3 bits than the number of bits of data and said 3 bits (b₂, b₃, b₄) are used for pseudo error detection, it is possible to set the range as narrow as indicated by γ₁ or as wide as indicated by γ₂ as the range of pseudo error. As shown in Fig. 4D, the pseudo error detection circuit which detects the range of γ₁ can be composed of an AND circuit 133 which ANDs said 3 bits (b₂∼b₄), a NOR circuit 134 which NORs said 3 bits and an OR circuit 135 which ORs outputs of the AND circuit 133 and NOR circuit 134. This circuit outputs "1" when said 3 bits are "000" or "111". As shown in Fig. 4E, the pseudo error detection circuit which detects the range of γ₂ may be formed by an inverter 136 which inverts the most significant bit (b₂) of said 3 bits, an AND circuit 137 which ANDs the output of inverter 136 and two other bits (b₃, b₄), a NOR circuit which NORs the output of inverter 136 and two other bits and a NOR circuit 139 which NORs the output of AND circuit 137 and the output of NOR circuit 138. This detection circuit outputs "1" when said 3 bits are not "011" and "100". When it is required to precisely set the range of pesudo error, further precise discrimination is necessary In Fig. 1B, only the I-ch signal is monitored but in case the Q-ch signal must be monitored,it can be achieved simply by providing the analog-to-digital converter and pseudo error rate measuring circuit which are the same as those for the I-ch also in the Q-ch. Where it is required to simultaneously monitor the I-ch and Q-ch, as shown in Fig. 4F, the pseudo error detection circuit 123 can be formed by the AND circuits 140 and 141 which ANDs 2 bits (b₂,b₃) for detecting pseudo errors of I-ch and Q-ch, the NOR circuits 142 and 143 which NOR respective 2 bits and an OR circuit 144 which ORs the outputs of said AND circuits 140 and 141 and the outputs of said NOR circuits 142 and 143. Similar logical operations may be realized by the circuit shown in Fig. 4G. The pseudo error detection circuit 123 shown in Fig. 4G is formed by the exclusive OR circuits 145 and 146 which each form the exclusive OR result of 2 bits of the I-ch and Q-ch and a NAND circuit 147 which NANDs the outputs of said exclusive OR circuit 145 and 146. This circuit outputs"1" when 2 bits of I-ch are "00" or "11" or when 2 bits of Q-ch are "00" or "11". This output is supplied to the measuring circuit 124. In these embodiments, the present invention is applied to the 16-value QAM radio transmission system but it can also be adapted to any system where data is transmitted from the transmitting side after it is converted to a multi-value or state signal and said data is obtained in the receiving side by means of analog-to-digital conversion. As explained above, the present invention descriminates the data more precisely than the number of bits of data by a plurality of bits in the receiving side and thereby detects a pseudo error only from said plurality of bits and thereby a pseudo error can be detected simply by using a simplified aditional circuit and the circuit is not complicated even when a number of bits of data increases. Moreover, an accurate error rate can be realized because data is monitored only at the decision timing of data. Where the range of pseudo error is set adequately, the frequency of generating pseudo errors can be set to the adequate degree and the pseudo error rate can be detected quickly. Moreover, the transmission capacity is not reduced because it is not required to transmit a particular pattern for the error rate detection.

Claims: A multi-state signal monitor circuit for a transmission system wherein data is transmitted from the sending side after it is converted to a multi-state signal and said data is regenerated through discrimination of said multi-state signal in the receiving side, having, in the receiving side thereof, an analog-to-digital converter (120) for discriminating said multi-state signal into a number of upper bits, which correspond to said data, and a plurality of lower bits, which serve for identifying specified ranges separated from the quantization levels of said multi-state signal, and a pseudo error rate measuring circuit (122) for measuring the frequency of entering said specified ranges as a pseudo error rate, characterized by said transmission system being a QAM-system with a multi-level amplitude level modulation. A multi-state signal monitor circuit according to claim 1, wherein said pseudo error rate measuring circuit (122) comprises a pseudo error detection circuit (123) for detecting whenever said plurality of lower bits indicate said specified range, and a measuring circuit (124) for measuring frequency of detection in said pseudo error detection circuit (123). A multi-state signal monitor circuit according to claim 2, wherein said pseudo error detection circuit (123) comprises: a first AND circuit (125) for obtaining the AND result of said plurality of bits; a plurality of inverters (126, 127) which invert said plurality of bits, a second AND circuit (128) for obtaining the AND result of the outputs of said plurality of inverters (126, 127), and an OR circuit (129) for obtaining the OR result of the outputs of said first and second AND circuits (125, 128). A multi-state signal monitor circuit according to claim 2, wherein said pseudo error detection circuit (123) comprises: an AND circuit (133) for obtaining the AND result of said plurality of bits, a NOR circuit (134) for obtaining the NOR result of said plurality of bits, and an OR circuit (124) for obtaining the OR result of the output of said AND circuit (133) and the output of said NOR circuit (134). A multi-state signal monitor circuit according to claim 2, wherein said pseudo error detection circuit comprises: an inverter (136) for inverting the most significant bit among said plurality of bits, an AND circuit (137) for obtaining the AND result of the bits except for the most significant bit among said plurality of bits and the output of said inverer (136); a NOR circuit (138) for obtaining the NOR result of the bits except for the most significant bit among said plurality of bits and the output of said inverter (136), and a second NOR circuit (139) for obtaining the NOR result of the output of said AND circuit (137) and the output of said first NOR circuit (138). A multi-state signal monitor circuit according to claim 2, wherein said plurality bits are 2 bits and said pseudo error detection circuit comprises an exclusive OR circuit (132) for obtaining the exclusive OR result of said 2 bits. A multi-state signal monitor circuit according to claim 2, wherein said pseudo error detection circuit (123) comprises, first and second AND circuits (140, 141) for obtaining the AND result of respective pluralities of bits of the I and Q channels, first and second NOR circuits (142, 143) for obtaining a NOR result of respective plurality of bits of said two channels, and an OR circuit (144) for obtaining an OR result of the outputs of said first and second AND circuits (140, 141) and the outputs of said first and second NOR circuits (142, 143). A multi-state signal monitor circuit according to claim 2, wherein said plurality of bits includes 2 bits, and said pseudo error detection circuit (123) comprises, the first and second exclusive OR circuits (145, 146) for obtaining an exclusive OR result of said 2 bits of the I and Q channels, and a NAND circuit (147) for obtaining a NAND result of the outputs of said exclusive OR circuit. A multi-state signal monitor circuit according to any one of claims 2 to 8, wherein said measuring circuit (124) comprises, a counter (130) for counting "1" or "0" of said detection circuit (123) and a timer (131) for causing said counter (130) to output a counted value for every constant period and also for resetting said counter (130). A multi-state signal monitor circuit according to any one of claims 2 to 8, wherein said measuring circuit (124) comprises an integration circuit (R, C) for integrating the output of said detection circuit (124).

Inventors: NOZUE, YOSHIHIRO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H03M13
IPC codes: H04L1, H04L25, H04L27, H03M13