SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device comprises a bias circuit having MOS transistors connected in series and comprising first depletion type MOS transistor (Q52), a second MOS transistor (Q53), and third MOS transistor (Q54), connected in series in the order between said power source voltage and said reference voltage. The gate of the third transistor (Q54) is connected to receive a chip enable signal (A). Said further transistor (Q51) is connected between said power source terminal and a common interconnection node of the gates of the first and second transistors and the junction (S2) between the first and second transistors. The gate of the further transistor (Q51) is connected to receive said chip enable signal (A). Said junction (S2) between the first and second transistors is connected to the gate of said first bypass MOS transistor.

Description: The present invention relates to a semiconductor memory device comprising: a bit line; a memory cell connected to said bit line; clamp circuit means connected between a power source terminal and said bit line, for clamping the voltage of said bit line to a predetermined value, said clamp circuit means comprising a load MOS transistor whose output current path is connected between said power source terminal and said bit line; bypass circuit means connected between said bit line and a reference voltage terminal, and operable to cause an electrical bypass current to flow therethrough from said bit line to said reference voltage terminal, said bypass circuit means comprising a first bypass MOS transistor whose output current path is connected between said bit line and said reference voltage terminal; and bias circuit means. Such a device is known from GB-A-2 092 403. The present invention relates more particularly to improvements on a read-out circuit in a nonvolatile memory device. In a semiconductor memory device, bit lines contained in its read out circuit are accompanied inevitably by stray capacitance. The stray capacitance impedes the memory operation. A measure, which has been taken for this problem, employs a clamp circuit connected to each bit line. The clamp circuit clamps a bit signal to restrict the stray capacitance distributed in association with the bit line. For a short memory cycle, this measure effectively restricts the stray capacitance problem. For a long memory cycle, however, it ineffectively restricts the stray capacitance. When the memory operation cycle is long, weak inversion currents are produced in the transistors in the clamp circuit. The weak inversion currents increase a maximum amplitude of the bit signal. The increased maximum amplitude of the bit signal elongates a discharge time of the bit line, and therefore elongates an access time of the memory device. A semiconductor memory device of prior art will be described referring to Fig. 1. The semiconductor memory device shown in Fig. 1 is an EPROM. Each memory cell of the memory device is a MOS (metal oxide semiconductor) transistor of the double silicon structure with a floating gate. In Fig. 1, reference numeral 12 designates a word line, and reference numeral 13 designates a bit line. A bit select transistor 14 is inserted in the bit line 13. A relatively large capacitance is distributed over the bit line. The capacitance delays a signal propagating on the bit line 13. To minimize the signal delay, a clamp circuit 19 consisting of transistors 15 and 16 is provided and clamps the amplitude of the signal on the bit line 13 to a small limited value. The amplitude limited signal is applied to a resistive load 17. The signal appearing across the load 17 is amplified by a post stage amplifier (not shown). A delay time of the signal on the bit line 13 is expressed by C BIT × ΔV/I CELL where C BIT is the capacitance of the bit line 13, ΔV an amplitude of a signal on the bit line 13, and I CELL a cell current flowing through the transistor 11. The expression shows that a delay time of the signal on the bit line 13 is proportional to the signal amplitude on the bit line 13. The amplitude of the bit line signal is set at approximately 0.2 V. The clamp circuit 19 clamps a maximum signal voltage of the bit line signal to 1 V = V B - V TN , specifying that the output voltage V B of a bias circuit 18 is 2 V, the power source potential V DD is 5 V, and the threshold voltage V TN of each transistor 15 and 16 is 1 V. However, only when the memory device operates in an ordinary short operating cycle, the maximum potential on the bit line 13 can be limited to 1 V. In a long operating cycle, weak inversion currents flow through the transistors 15 and 16 of the clamp circuit, so that the maximum potential on the bit line exceeds 1 V. As a result, the signal amplitude ΔV is increased up to about 0.5 V, for example. Accordingly, a discharge time of the bit line is longer than that in the case of 0.2 V for the maximum potential. Therefore, an access time to the memory is also long. An object of the present invention is to provide a semiconductor memory device which can operate with a short access time even for a long memory operation, with the circuit arrangement free from the weak inversion current. The invention is characterized in that said bias circuit means is arranged to bias said first bypass MOS enhancement transistor, and comprises MOS transistors connected in series between said power source terminal and said reference voltage terminal, said MOS transistors comprising a first depletion type MOS transistor of the first conductivity type, a second enhancement MOS transistor and a third enhancement type MOS transistor of the first conductivity types, connected in series in that order between said power source voltage and said reference voltage, the gate of the third enhancement transistor being connected to receive a chip enable signal, said bias circuit means further comprising a further MOS enhancement transistor of a second conductivity type opposite to the first conductivity type being connected between said power source terminal and a common interconnection node of the gate of the first and second transistors and the junction between the current paths of the first and second transistors, the gate of the further transistor being connected to receive said chip enable signal, and said junction between the first and second transistors being connected to the gate of said first bypass MOS transistor. Further embodiments are characterized in the sub-claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows the signal read out circuit of a conventional EPROM (erasable and programmable read only memory); Fig. 2 shows the signal read-out circuit of an example of a semiconductor memory device; Fig. 3 shows the signal read-out circuit of a semiconductor memory according to an embodiment of the present invention; Fig. 4 shows a current characteristic of a weak inversion current bypassing circuit in the semiconductor memory device shown in Fig. 3; Fig. 5 shows a cross-sectional view of an N channel depletion transistor assembled into the weak inversion current bypass circuit in the semiconductor memory device of Fig. 4; Fig. 6 is a circuit diagram of another weak inversion current bypass circuit, equivalent to that used in the semiconductor memory device of Fig. 3; and Fig. 7 shows a relationship between a memory operation cycle and an access time of the semiconductor memory device shown in Fig. 2 and that of prior art shown in Fig. 1. To solve the above-mentioned problem, it only needs removal of the weak inversion current. To this end, it is necessary to couple a circuit for discharging the weak inversion current with the clamp circuit. A first example implementing such an idea is illustrated in Fig. 2. In Fig. 2, the transistor 11 serves as an EPROM cell. The transistor 11 is an N channel MOS transistor of the double layer polysilicon structure having a floating gate. A transistor 14 serves as a bit line select transistor 14, and is inserted in series in the bit line 13. A word line 12 is connected to the gate of the transistor 11. The drain of the cell transistor 11 is connected to the bit line 13. The source of the transistor 11 is coupled with a low potential power source V SS . A clamp circuit 21 is connected to the bit line 13. A resistive load 22 is also connected to the bit line, and sets a bit line potential. A weak inversion current bypassing circuit 23 is coupled with the clamp circuit 21. A bias circuit 24 is coupled with the clamp circuit 21 and the bypassing circuit 23, to bias the transistors of these circuits 21 and 23. Data stored in the cell transistor 11 is transferred to an amplifier (not shown) through the bit line 13. The weak inversion current bypassing circuit 23 is made up of an N channel MOS transistor Q3. The clamp circuit 21 is made up of N channel MOS transistors Q1 and Q2. The gates of the transistors Q1 to Q3 are connected to the bias circuit 24. The bias circuit 24 applies a bias voltage 2V TH to the gates of the transistor Q1 to Q3. V TH represents a threshold voltage of each of the transistor Q1 to Q3. The current paths of the transistors Q1 and Q3 are connected in series between high and low power sources V DD and V SS . The current paths of the bit line select transistor 14 and the transistor Q2 are inserted in the bit line 13 in a series fashion. The transistor Q2 in the clamp circuit 21 serves as a transfer gate. The transistor Q1 clamps the bit line voltage at a predetermined voltage. The resistive load 22 is made up of a single P channel transistor 22. One end of the current path of the transistor Q4 is connected to the high potential power source V DD , while the other end thereof to the bit line 13. A bit line voltage appearing across the load circuit 22 is sensed and amplified by an amplifier (not shown) provided at the succeeding stage. The bias circuit 24 is composed of a P channel transistor Q5, and N channel transistors Q6 to Q8. The current paths of the transistors Q5 and Q6 are connected between the power sources V DD and V SS . Similarly, the current paths Q5, Q7 and Q8 are connected in series between the power sources V DD and V SS . The source of the transistor Q5 and the drains of the transistors Q6 and Q7 are interconnected. This interconnection point provides the 2V TH bias voltage. The drain and gates of each of the transistor Q7 and Q8 are interconnected. The gate of the transistor Q6 is connected to the source of the transistor Q7 and the drain of the transistor Q8. As already stated, when the memory operation cycle is long, weak inversion currents are generated by the transistors Q1 and Q2 in the clamp circuit 21. The inversion currents raise the maximum voltage on the bit line 13, to create a long access time problem. The transistor Q3 provides a path for bypassing such inversion current. Accordingly, the width and length of the channel of the transistor Q3 must be so selected as to allow the inversion current to flow into the power source V SS . If the transistor Q3 is appropriately biased, it can bypass the inversion currents without any special design of its channel geometry. Fig. 3 shows an embodiment of the present invention. In this embodiment, a weak inversion current bypassing circuit 23 comprises a depletion type MOS transistor with a constant current feature. As shown, a memory cell 11 is an N channel MOS tansistor of the double layer polysilicon structure having a floating gate. A word line 12 is connected to the floating gate and the control gate of the cell transistor 11. The drain of the transistor 11 is connected to a bit line 13. The source of the transistor 11 is coupled with the power source V SS . The N channel MOS transistor 14 inserted in the bit line 13 serves as a transfer gate. N channel transistors 15 and 16 make up a clamp circuit 19. A bias circuit 18 biases the transistors 15 and 16 of the clamp circuit 19. A resistive load circuit 17 is also connected to the bit line 13. The transistor 16 serving as a transfer gate is located closer to the data output terminal D OUT than the transistor 14 also serving as a transfer gate. The bias voltage output from the bias circuit 18 is generally set at 2V when the threshold voltage of each of the transistor 15 and 16 is 1 V. Accordingly, a maximum potential (V B - V TH ) on the bit line 13 is clamped at 1 V. The resistive load is located closer to the output terminal D OUT than the transfer gate 16. The discharge circuit 23 is comprised of a P channel enchancement type transistor Q51, an N channel depletion type transistor Q52, and N channel enhancement type transistors Q53 to Q56. The transistors Q55 and Q56 are connected in series between a node S1 of the bit line 13 and the power source V SS . The node S1 is a node between the transistors 14 and 15. The transistor Q51 is placed between the power source V DD and the gate of the transistor Q55. The current paths of the transistors Q52 to Q54 are connected in series and between the power sources V DD and V SS . The gates of the transistors Q52, Q53 and Q55 are interconnected and to the source of the transistor Q52 and the drain of the transistor Q53. S2 designates a node between the current paths of the transistors Q52 and Q53, S3 a node between the current paths of the transistors Q55 and Q56, S4 a node between the transistors Q53 and Q54. A potential Vs2 at the node S2, the high power source potential V DD , and the threshold voltage V THD of the transistor Q52 are related by the following relation Hence, V DD + V THD > Vs2 If the above relation is satisfied, the transistor Q52 feeds a constant current. A variation of the drain current ID of the transistor Q52 with respect to the potential Vs2 at the source of the transistor Q52 is shown in Fig. 4. As seen from the graph of Fig. 4, the drain current ID is kept constant in the range where the above expression is satisfied. A chip select signal A is applied to the gates of the transistors Q51 and Q54. The chip select signal A is at V DD level in a chip select mode, while it is at V SS level in a chip nonselect mode. The gate of the transistor Q56 is coupled with the high power soruce V DD . A ratio of the channel width to length of the transistor Q53 is given by W1/L1 × N where N > 1, and W1 and L1 are of the channel width and length of the transistor Q55. A ratio of the channel width to length of the transistor Q54 is given W2/L2 × N where N > 1, and W2 and L2 are the channel width and length of the transistor Q56. Further, the channel width to length ratio of the transistor Q52 is much smaller than that of each transistor Q55 and Q56. In a chip select mode, the transistor Q51 is turned off and the transistor Q54 is turned on, and the following relation holds V DD + V THD > Vs2. Accordingly, a constant current flows through the transistor Q52. Since the gate of the transistor Q56 is connected to the V DD , if the ratio W2/L2 of the transistor Q56 is sufficiently large, its mutual conductance gm is large, and hence its resistive component is neglibile. In this case, accordingly, the potential Vs2 at the node S2 is determined by a current amplification factor β of the transistor Q54. The current I1 flowing through the transistor Q52 is I1 = β/2 × (Vs2 - V THN )2, where V THN is a threshold voltage of the transistor Q54. The mutual conductance of each of the transistor Q53 and Q54 is much larger than that of the transistor Q52. Therefore, the potential Vs2 is slightly larger than the threshold voltage V THN of the transistor Q54. Then, the following relation holds Vs2 < V THN + 0.3 V The potential Vs2 at the node S2 is applied to the gate of the transistor Q55. The channel width to length ratio of the transistor Q53 is N times that of the transistor Q53. The channel width to length ratio of the transistor Q54 is N times that of the transistor Q56. The gates of the transistors Q53 and Q55 are applied with the equal potential. In a chip select mode, the gates of the transistors Q54 and Q56 are applied with the equal potential (V DD ). Further, the potential Vs3 at the node S3 is low. Vs3 < Vs2, and Vs3 < V THN + 0.3 V. Therefore, the transistor Q55 operates in a similar way to that of the transistor Q55. Hence, the bypass current I2 of the transistor Q55 is I2 = I1/N This expression teaches that the current I2 is constant irrespective of the bias voltage of the bias circuit 18 and the V DD level. If I2 = 1 µA , I1 = N µA. In this case, the transistor Q52 of the depletion type must be formed which is capable of feeding a current of N µA. As already described, the transistor Q52 must have a satisfactorily small ratio of channel width to length. That is, it only needs a geometry of a long channel length and a small channel width. However, if the channel width is small, the threshold voltage V THD of the transistor Q52 is high. To cope with this problem, in manufacturing the memory device, as shown in Fig. 5, the channel region of the transistor Q52 and its peripheral region 62 (regions not hatched) are formed off the ion implantation region so that these regions are not ion implanted. If so manufactured, the threshold voltage V THD is prevented from being varied. In Fig. 5, reference numeral 63 designates a gate insulation film formed on the substrate 61, and numeral 64 a gate electrode formed on the insulation film 63. The bypass circuit 23 in the Fig. 3 embodiment may be replaced equivalently by the circuit arrangement as shown in Fig. 6. The circuit 23 of Fig. 6 is made up of only an N channel depletion type transistor Q57 having a constant current feed nature. The transistor Q57 is inserted between the bit line 13 and the node S1. The gate of the transistor Q57 is connected to its source. The bypass current to be flowed is extremly small, e.g. 1 µA. In this bypass circuit, the channel length L of the transistor must be satisfactorily long. Fig. 7 shows a relationship of the memory operation cycle v.s. access time of the memory device shown in Fig. 2 and that of the prior art shown in Fig. 1. In the graph, a curve denoted as I indicates the relationship of the present invention, while a curve II indicates that of the prior art. As shown, the access time is small over the entire range of the operation cycle as measured. As seen from the foregoing description, provided is the bypassing circuit for bypassing the weak inversion current which is generated in the transistors of the clamp circuit when the memory operation cycle is long. Therefore, the access time elongating problem inevitable for the prior art is successfully solved, thus securing a high speed memory operation performance.

Claims: A semiconductor memory device comprising: a bit line (13); a memory cell (11) connected to said bit line; clamp circuit means (19) connected between a power source terminal (VDD) and said bit line, for clamping the voltage of said bit line to a predetermined value, said clamp circuit means comprising a load MOS transistor (15) whose output current path is connected between said power source terminal (VDD) and said bit line (13); bypass circuit means (23) connected between said bit line (13) and a reference voltage terminal (VSS), and operable to cause an electrical bypass current to flow therethrough from said bit line (13) to said reference voltage terminal (VSS), said bypass circuit means (23) comprising a first bypass MOS enhancement transistor (Q55) of the first conductivity type whose output current path is connected between said bit line (13) and said reference voltage terminal; and bias circuit means (Q51-Q54), characterized in that: said bias circuit means is arranged to bias said first bypass MOS enhancement transistor (Q55), and comprises MOS transistors connected in series between said power source terminal (VDD) and said reference voltage terminal (VSS), said MOS transistors comprising a first depletion type MOS transistor (Q52) of the first conductivity type, a second enhancement MOS transistor (Q53) and a third enhancement type MOS transistor (Q54) of the first conductivity types, connected in series in that order between said power source voltage (VDD) and said reference voltage (VSS), the gate of the third enhancement transistor (Q54) being connected to receive a chip enable signal (A), said bias circuit means further comprising a further MOS enhancement transistor (Q51) of a second conductivity type opposite to the first conductivity type being connected between said power source terminal (VDD) and a common interconnection node of the gate of the first and second transistors (Q52, Q53) and the junction (S2) between the current paths of the first and second transistors, the gate of the further transistor (Q51) being connected to receive said chip enable signal (A), and said junction (S2) between the first and second transistors (Q52, Q53) being connected to the gate of said first bypass MOS transistor (Q55). A semiconductor memory device according to claim 1, characterized in that said bias circuit means comprises first and second biasing circuits (18, Q51-Q54) for generating respective first and second bias voltages, the gate of said load MOS transistor (15) is connected to said first biasing circuit (18) and applied with said bias voltage of said first biasing circuit, and the gate of said bypass MOS transistor (Q55) is connected to said second biasing circuit (Q51-Q54) applied with said second bias voltage of said second biasing circuit. A semiconductor memory device according to claim 2, characterized in that said second biasing circuit (Q51-Q54) comprises a current mirror circuit, and said second bias voltage of said second biasing circuit corresponding to an electric current flowing through said current mirror circuit. A semiconductor memory device according to claim 1, characterized in that said biasing circuit means (Q51-Q54) further comprises a second bypass MOS transistor (Q16, Q56) connected in series with said first bypass MOS transistor, the gate of the second bypass MOS transistor being connected to a predetermined voltage, in use of the memory device.

Inventors: ATSUMI, SHIGERU, OHTSUKA, NOBUAKI, SAITO, SHINJI, TANAKA, SUMIO
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: G11C7
IPC codes: G11C7, G11C16, G11C11