ERROR RECOVERY SYSTEM IN A DATA PROCESSOR HAVING A CONTROL STORAGE

Abstract: An error recovery system in a data processor of the pipe­ line type, including control storage (11) for storing instruction data, having a code adapted to the detection and correction of errrors, for controlling the data processor. A parity check cir­ cuit (16) checks instructions read from the control storage (11) and stops at least a part of pipeline processing immediately upon the detection of an error. An error correction circuit (14) corrects the error in the read instruction data and rewrites the instruction data into the control storage (11) while the part of the pipeline processing is stopped.

Description: The present invention relates to an error recovery system and method in a data processor for pipeline processing, more particularly to a system and method for recovering an error of a control storage in a data processor which is controlled by microinstructions stored in the control storage and which carries out pipeline processing. In data processors which carry out pipeline processing of machine instructions, an error in the microinstructions read from the control storage which stores the microinstructions can obstruct the correct execution of the entire pipeline processing. Accordingly, in a previously proposed pipeline processing, an error correction code is provided in the microinstructions stored in the control storage, and detection and correction of errors in the read-out microinstructions are carried out. More specifically, microinstructions relating to the pipeline processing are stored in the control storage. When a microinstruction is read out, it is written in a data register. A decoder decodes the instruction in the data register to transmit it to each control point, which carries out the pipeline processing, and to the microinstruction register for the succeeding cycles. On the other hand, the contents of the instructions are read out into an error detection and correction circuit. Then, an error correction code is employed to check whether there is an error bit in the instruction. When no error is detected, a pipeline controller is made to carry out a predetermined operation. The pipeline controller generates a release signal in each cycle of the pipeline processing to execute each cycle of D(decode), A(address generation), T(translation), B(buffer access), E(execution), and W(write) normally. The decoding of read-out instructions is carried out in the D cycle, an address calculation of the operand is carried out in the A cycle, an address translation of the address is carried out in the T cycle, a buffer or register is accessed in the B cycle, processing is carried out to the data read-out from the buffer or register in the E cycle, and a write operation of processed results is carried out in the W cycle. When an error is detected in the instruction read out by the data register, the operation of the pipeline controller is halted and an interlock is carried out to the pipeline. In the course of interlocking, the error in the instruction is corrected in the register and rewrite of the correct instruction to the control storage is carried out. The error correction code can generally detect and correct a 1-bit error. For a 2-bit error, use is made of a single-error correction double-error-detection (SEC. DED) code, which can only detect 2-bit errors. It would take considerable time for this previously proposed error detection and correction circuit not only to correct errors, but even detect errors. On account of this, it has been necessary to provide an exclusive correction cycle to detect and correct errors every time an instruction is read out. The addition of such a correction cycle to the normal pipeline processing cycles, however, results in excessive augmentation of the entire pipeline processing time, so is not preferable in respect to performance. Further, when an error is detected in an instruction read out from the control storage, the processing of the machine instruction is stopped and then reexecuted in machine instruction units. In the case of a machine instruction which realizes its function through a plurality of flows; however, in some cases, the write operation to the register is performed in a flow prior to the faulty flow, and it is impossible to return to the original state before the instruction was run for reexecution (this is called "over retriable point"). In such a case, the error cannot be corrected. EP-A-0 141 743 constitutes prior art for the present application under Article 54(3) and (4) EPC. It discloses a pipeline error correction method which avoids the use of gates between a system memory and system processor so as to reduce delays due to error correction. A data word and its associated error correction code are separately accessible, and data words are stored in the system memory before the calculation of the error-correction code is complete. Parity bits are included in each data word and can be checked separately from the error-correction code. EP-A-0 105 710 by the present applicant discloses an error recovery method for a microprogram-controlled unit, having the features of the preamble of accompanying claim 1. At the same time as a microinstruction is transferred to a pipeline processing unit, it is checked by an error detection and correction circuit. However, no separate parity check is carried out. According to one aspect of the present invention, as claimed in claim 1 there is provided a method of error recovery for a data processor of the pipeline type in which a plurality of microinstructions are read from a control storage based upon a machine instruction and said read-out microinstructions are processed in an overlapped manner in a pipeline processing portion, said method comprising the steps of:- using an error detection and correction code for each microinstruction stored in said control storage; and checking said microinstructions read in sequence simultaneously with the processing of said microinstructions in said pipeline processing portion by means of an error detecting means, and characterized by the steps of:- stopping, within an operand address calculation cycle, the pipeline process corresponding to a microinstruction in which an error is detected and the operation of the microinstruction succeeding thereto, when an error is detected in said microinstruction by the detecting means; correcting said error in the microinstruction by an error correction means; and restarting, from said operand address calculation cycle, the pipeline process after the completion of the correction of said microinstruction on the basis of the corrected microinstruction; whereby an error recovery is carried out by stopping and subsequently restarting the pipeline process of a microinstruction without having to carry out again the execution of said machine instruction from the beginning. According to a second aspect of the present invention, as claimed in claim 6 there is provided a data processor of the pipeline type equipped with an error recovery system, in which a plurality of microinstructions are read from a control storage based upon a machine instruction and said read-out microinstructions are processed in an overlapped manner in a pipeline processing portion, said data processor comprising:- error detecting means for checking said microinstructions read in sequence simultaneously with the processing of said microinstructions in said pipeline processing portion, using an error detection and correction code for each microinstruction stored in said control storage; and characterized by:- stopping means for stopping, within an operand address calculation cycle, the pipeline process corresponding to a microinstruction in which an error is detected and the operation of the microinstruction succeeding thereto, when an error is detected in said microinstruction by the detecting means; error correction means for correcting said error in the microinstruction; and restarting means for restarting, from said operand address calculation cycle, the pipeline process after the completion of the correction of said microinstruction on the basis of the corrected microinstruction; whereby an error recovery is carried out by stopping and subsequently restarting the pipeline process of a microinstruction without having to carry out again the execution of said machine instruction from the beginning. The present invention can reduce or eliminate a drawback of the previously proposed error recovery system in a control storage. An embodiment of the present invention can provide a system and method for recovering an error of a control storage in a data processor of the pipeline type, wherein an error in an instruction read from the control storage can be detected at an early stage, the pipeline system can be interlocked at a stage before the instruction is carried out, and the error can be corrected during the interlocking. Reference is made, by way of example, to the accompanying drawings in which: Figure 1 illustrates in block diagram form a preferred embodiment of the present invention; Fig. 2 is a schematic block diagram explaining a detailed structure of the embodiment in Fig. 1; Fig. 3 is a time chart of the operation in a pipeline process in the case of no error; Fig. 4 is a schematic block diagram explaining an error correction code of the microinstruction form; and Fig. 5 is a time chart of the operation in a pipeline process in the case of an error. A detailed description will be given of an embodiment of the present invention with reference to the accompanying drawings. Figure 1 is a schematic block diagram of an error recovery system according to an embodiment of the present invention. In Fig. 1, 11 is a control storage for storing, for example, microinstructions for executing pipeline processing, 12 a data register in which can be written the microinstructions read from the control storage 11, 13 a decoder for decoding the microinstructions, 14 a circuit for detecting and correcting the errors in the instructions, 15 a pipeline controller for generating release signals of each cycle in pipeline processing and executing each cycle in sequence, and 16 a circuit for parity checking a microinstruction code. Figure 2 shows an example of the detailed structure of the portions in Fig. 1. Reference numerals 121 to 125 are data registers. Reference numerals 131 to 135 are decoders. One output of 131 is conveyed to the control storage address control to carry out address control. The other output of 131 is conveyed to a general-purpose register (GPR) and an effective address generator (EAG). On the other hand, by a machine instruction, the output of an instruction register is sent to the control storage address control. The output of the decoder 132 is sent to a translation look-aside buffer (TLB). The output of the decoder 133 is sent to a buffer storage (BS). The output of the decoder 134 is sent to an arithmetic logic unit (ALU). The output of the decoder 135 is sent to a general-purpose register (GPR) and a buffer storage. The content of the control storage 11 is sent to the parity check circuit 16 and a register 121. The output of the error detection and correction circuit controls the control storage 11 as a (by sending) corrected data and controls the pipeline controller 15. The input signal of the decoder 131 controls the control storage address control and the output signal is transmitted to the control storage 11. Describing, with reference to Fig. 1, the operation in the case of no error in the microinstruction read from the control storage 11, a microinstruction for pipeline processing read from the control storage 11 is written into the data register 12 and the parity check circuit 16, simultaneously. The decoder 13 decodes the microinstruction stored in the data register 12 to send it to each control point for the pipeline processing and to the microinstruction register for the next cycle. On the other hand, the contents of the microinstruction are read out into the error detection and correction circuit 14. As no error is detected by the parity check circuit 16 or the error detection and correction circuit 14, the pipeline controller 15 executes a predetermined operation. Specifically, the pipeline controller 15 generates a release signal for each cycle of the pipeline processing to execute in sequence normal-state pipeline processing, for instance, PLP-1 and PLP-2, as shown in Fig. 3. The operation of pipeline processing in Fig. 3 is in this case normal operation. Next, an explanation of the operation when an error exists in the microinstruction read from the control storage 11. An error correction code is used for the microinstruction. The error correction code, as shown in Fig. 4, is composed of check bits and data bits. The error correction code is constituted in a manner such that the error bit can be corrected by using exclusive OR logic in connection with a parity check. The error correction code ECC may be an SEC-DED code, which, as stated above, is able to detect and correct the error for a 1-bit error and to detect the error for a 2-bit error. In the present invention, the code is given a definite parity. The data bit of the 1-bit error detection and correction code is made a 1-bit detection bit and a parity appended throughout to obtain the SEC.DED code. The SEC.DED code is thus made to be itself, for instance, an even parity. When an error correction code ECC which is itself an even parity is employed, an error of odd bits can easily be detected by the parity check. The error correction code ECC according to the present invention is not limited to an even parity, but as a bit error is usually a 1-bit error, to use, as an ECC, an SEC.DED code which is able to detect and correct a 1-bit error and to detect a 2-bit error and which is itself an even parity, enables realization of an error correction code ECC with a desired definite parity without having to provide a special additional circuit. When the microinstruction is read from the control storage to the parity check circuit 16, the parity check circuit 16, which comprises exclusive OR circuits, detects whether or not there is a bit error in the microinstruction by means of a parity check. It can detect bit errors in the microinstruction before the termination of the A cycle due to the high speed of the parity check. Accordingly, the pipeline controller 15 can be stopped before the move from the A cycle to the next T cycle, for interlocking of the pipeline. Figure 5 is a timing chart of an example of operation in each pipeline, when an error is detected in the microinstruction by the parity check. In Fig. 5, pipeline processing is carried out in a normal condition until the pipeline processing stage PLP-1. At the pipeline processing stage PLP-2, an error is found in the microinstruction read from the control storage 11. Specifically the parity check circuit 16 detects the error in the microinstruction by the parity check in the A₂ cycle and it stops the pipeline controller 15 before it proceeds to move on to the next T₂ cycle, thus interlocking the pipeline (Refer to t a in Fig. 5). Once the pipeline is interlocked, the pipeline processing stage PLP-1, before the stage PLP-2, is kept unchanged and the flows of T₁ , B₁ , E₁ , and W₁ proceed. The flow of each pipeline starting from the stage PLP-2 is stopped, as shown in the figure, i.e. the wait state is entered with the A₂ cycle state of the stage PLP-2 and with the D₃ cycle state of the stage PLP-3. From the stage PLP-4 on, read-out of the microinstruction is not carried out. While the pipeline is in an interlock state, the error detection and correction circuit 14 corrects the bit error produced in the microinstruction in the data register 12 by means of the error correction code ECC and, as the case may be, rewrites the correct microinstruction into the control storage 11. When the correction of the bit error and the rewriting into the control storage 11 are over at a time t b , the interlock is released and the pipeline processing stages from stage PLP-2, inclusive, are restarted after the cycle before the interlocking. The foregoing embodiment was explained with reference to the use of a microinstruction as a command. The commands, however, are not limited to microinstructions. Also, the error correction code ECC is not restricted to an SEC.DED code. Since there are both a parity check circuit and an error detection and correction circuit in the present invention, it is also possible to detect any trouble in the circuits by an inconsistency of results of the checks, for instance, no error in the parity check, but a 1-bit error in the ECC check. Also, when there is a defect in the control storage, causing an error in the instruction, an error will be continually generated at each read instruction. In an embodiment of the present invention, when an error occurs in the rewritten instruction a predetermined number of times, the rewrite into the control storage can be stopped based on the reason that there is an error in the control storage itself and the processing carried on. The defect in the control storage can then be repaired separately to restore the control storage to its former state. According to the present invention, there is provided a system for recovering errors in a control storage in a data processor of the pipeline type controlled by instructions in a control storage. A parity check circuit employs a definite parity for the error correction code in the instruction. The parity of the instruction read from the control storage is checked and, as soon as an error is detected in the parity, the pipeline system is interlocked. An error detection and correction circuit corrects the error of the instruction read out in the course of interlocking, and as the case may be, rewrites the correct instruction into the control storage. By these circuits, the error detection in course of the instruction is executed before a T (transformation) cycle and the pipeline system is interlocked therewith, thus enabling correction of errors per flow unit of the instruction.

Claims: A method of error recovery for a data processor of the pipeline type in which a plurality of microinstructions are read from a control storage (11) based upon a machine instruction and said read-out microinstructions are processed in an overlapped manner in a pipeline processing portion, said method comprising the steps of:- using an error detection and correction code for each microinstruction stored in said control storage (11); and checking said microinstructions read in sequence simultaneously with the processing of said microinstructions in said pipeline processing portion by means of an error detecting means (14, 16), and characterized by the steps of:- stopping, within an operand address calculation cycle, the pipeline process corresponding to a microinstruction in which an error is detected and the operation of the microinstruction succeeding thereto, when an error is detected in said microinstruction by the detecting means; correcting said error in the microinstruction by an error correction means (14); and restarting, from said operand address calculation cycle, the pipeline process after the completion of the correction of said microinstruction on the basis of the corrected microinstruction; whereby an error recovery is carried out by stopping and subsequently restarting the pipeline process of a microinstruction without having to carry out again the execution of said machine instruction from the beginning. A method according to claim 1, wherein the pipeline which is processed simultaneously with said checking step, stopped in said stopping step, and restarted in said restarting step, calculates operand addresses. A method according to claim 1 or 2, wherein said checking step includes a parity check of the microinstruction for detecting a parity error. A method according to claim 3, further comprising a step of stopping stages prior to a stage in which a parity error is detected and restarting said prior stages when said parity error is corrected. A method according to any preceding claim, further comprising a step of replacing the microinstruction read from said control storage (11) by the corrected microinstruction. A data processor of the pipeline type equipped with an error recovery system, in which a plurality of microinstructions are read from a control storage (11) based upon a machine instruction and said read-out microinstructions are processed in an overlapped manner in a pipeline processing portion, said data processor comprising:- error detecting means (14, 16) for checking said microinstructions read in sequence simultaneously with the processing of said microinstructions in said pipeline processing portion, using an error detection and correction code for each microinstruction stored in said control storage (11); and characterized by:- stopping means for stopping, within an operand address calculation cycle, the pipeline process corresponding to a microinstruction in which an error is detected and the operation of the microinstruction succeeding thereto, when an error is detected in said microinstruction by the detecting means (14, 16); error correction means (14) for correcting said error in the microinstruction; and restarting means for restarting, from said operand address calculation cycle, the pipeline process after the completion of the correction of said microinstruction on the basis of the corrected microinstruction; whereby an error recovery is carried out by stopping and subsequently restarting the pipeline process of a microinstruction without having to carry out again the execution of said machine instruction from the beginning. A data processor according to claim 6, wherein said data processor comprises:- means for calculating operand addresses; means for controlling a reading of operand data; means for performing a calculation; and means for writing the results of calculation into a storage. A data processor according to claim 6 or 7, wherein the pipeline process which is processed simultaneously with said error detection by said error detection means, stopped by said stopping means, and restarted by said restarting means, consists of the calculation of operand addresses, said error correcting means (14) correcting errors in said microinstructions by using said error detection and correction code. A data processor according to claim 6, 7 or 8, wherein said error detection and correction code is a single error correction, double error detection code. A data processor according to any of claims 6 to 9, wherein said pipeline processing portion comprises a plurality of control registers, and said error detecting means (14, 16) comprises a parity check circuit (16), operatively connected to the control storage (11) and a first of the control registers, for checking parity of a microinstruction transferred from the control storage to the first of the control registers and stopping pipeline processing only in accordance with the contents of the first of the control registers when a parity error is detected; and wherein said error correction means (14) is also operatively connected to the control storage (11) and the first of the control registers and is operable to correct the microinstruction transferred from the control storage to the first of the control registers while processing is stopped. A data processor according to claim 10, wherein said data processor further comprises:- a pipeline controller (15), operatively connected between the parity check circuit (16) and the control registers, for releasing the microinstruction in the first control register to successive control registers and the corresponding pipeline processing stages in dependence on the parity check.

Inventors: KITAMURA, TOSHIAKI, OINAGA, YUJI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F11
IPC codes: G06F9, G06F12, G06F11