CLOCK BUFFER CIRCUIT WITH NON-SATURATED PULL-UP TRANSISTOR TO AVOID HOT ELECTRON EFFECTS

Abstract: A clock buffer circuit for multiple phase complementary clocking signals that receives a plurality of corresponding enabling signals (ENPH0-ENPH3) and generates a like plurality of clock signals (PH0-PH3) in response thereto. Each clocking signal (PH0) is generated by a buffer module (17A) including a resistor (61A), a pull-up transistor (60A) and a pull-down transistor (55A), which are connected in series between a positive power supply and ground, with the clocking signal being taken from the node between the pull-up and pull-down transistors. In each module, before the clocking signal shifts from a low state to a high, the pull-down transistor is on so that the clocking signal is at a low state. The pull-up transistor in each module is controlled by the corresponding enabling signal (EPH0D) and is enabled to begin conducting at the time that the clocking signal is to shift to a high state. The resistor keeps the pull-up transistor in its linear, non-saturated operating regions, which results in an increase in the intrinsic capacitance in the pull-up transistor from the saturated condition. After the pull-up transistor is turned on, allowing the intrinsic capacitance of the pull-up transistor to charge, the pull-down transistor is then turned off and the gate of the pull-up transistor is isolated. The voltage levels at the gate and source terminals of the pull-up transistor rise in a bootstrapping operation. When the clock signal is to shift to a low state, the complementary phase clocking signal (PH1) turns on the pull-down transistor.

Description: Background of the Invention 1. Field of the Invention The invention relates generally to the field of clock buffer circuits and more specifically to a clock buffer circuit with non-saturated pull-up transistor to avoid hot electron effects. 2. Description of the Prior Art In digital devices, particularly in microprocessors and other devices in which various operations must be synchronized, global clock or timing signals are used to synchronize the various circuits within the device. The conductors, or lines, carrying the clock signals are often quite lengthy, as they must extend throughout the devices to all of the various circuits which must be synchronized. Because the lengths of the lines which carry the timing signals and the number of circuit elements driven by the timing signals result in large capacitive loads for the circuits which generate the clocking signals, those circuits must be able to provide large amounts of current to ensure that the clock signals have fast rising and falling edge rates. The problem is particularly acute in integrated circuit chips, since it is desired to keep the active devices as small as possible, which limits the amount of current available from the devices. Typically, timing signals are initially generated by a flip-flop or a set of flip-flops connected to generate inter-related multiple-phase output signals. Since flip-flops of the switching speed required for the clock signals of current microprocessors typically cannot also provide the currents required for the fast rise and fall times, the output signals from the flip-flops are transmitted as enabling signals to a buffer circuit, which includes transistors large enough to produce clocking signals having the required currents. The output signals from the buffer circuit comprise the clock signals which are transmitted to the various synchronized circuits throughout the device. Since the clock buffer circuit must provide large amounts of current, the clock buffer can take up a significant portion of the area of chips designed using very large scale integration techniques. The problem of providing a clock buffer circuit on such chips is greatly magnified when, as is the case with many microprocessors, the clock circuit must provide clock signals of several different phases all of which are themselves synchronized. Not only must the flip-flops providing the enabling signals be synchronized, the buffer circuits must also be synchronized to ensure that the generated clocking signals have the required rise and fall characteristics with respect to each other. In prior clock circuits, the clock buffer circuits used bootstrapping techniques to boost the voltage level of the output signal of the buffer circuit to a desired nominal output voltage. In such bootstrapping techniques, pull-up and pull-down field effect transistors are connected in series between a positive power supply and ground. A bootstrap capacitor is connected to the gate terminal of the pull-up transistor and the output clock signal is taken from the node between the two transistors. The enabling signal is applied to the gate of the pull-up transistor. When the clocking signal is at ground level, the pull-down transistor is turned on and the pull-up transistor is turned off. The enabling signal from the flip-flop clock signal generator begins to rise, which turns the pull-up transistor on, when the clocking signal is to rise. Since both the pull-up and pull-down transistors at this point are conducting, a condition known as "overlap", the voltage level of the clocking signal increases slightly above ground. The capacitor connected to the gate of the pull-up transistor is charged during this period. The gate of the pull-up transistor is then isolated and the pull-down transistor is turned off, which causes the voltage level of the gate of the pull-up transistor to rise above the power supply voltage level and the voltage level of the node between the transistors, from which the clocking signal is taken, to increase to the power supply voltage level. The prior bootstrap techniques had a number of problems, however. The overlap current, that is, the current flowing through the pull-up and pull-down transistors when they were both conducting, was quite large. Furthermore, the required bootstrap capacitors occupied large amounts of chip area, which reduced the amount of chip area available for other circuits. Furthermore, since the pull-up transistor was driven into saturation, electrons in the transistor's channel were subject to a high electric field associated with the high drain to source voltage accompanying saturation, which could accelerate them into the substrate and or cause tunnelling into the gate oxide insulating the gate terminal from the substrate, so-called "hot electron" problems. The electrons driven into the substrate caused noise problems in signals throughout the rest of the chip, while electrons tunnelling into the gate oxide caused a degradation in the operation of the transistor by increasing the threshold voltage required to turn the transistor on. Since this degradation occurred over, and varied with, time, and also varied from transistor to transistor, the reliability of the chip would undergo a steady and unpredictable deterioration. An other prior art is constituted by the document IBM TECHNICAL DISCLOSURE BULLETIN, volume 18, No 3, August 1975, pages 710, 711, New York, US, of WM CHU et al, intitulated "Bootstrap push-pull driver". Summary of the Invention These and other problems are corrected by providing a new and improved clock buffer circuit for use on an integrated circuit chip which receives a plurality of enabling signals having predetermined phasing relationships from, for example, a flip-flop circuit and generated a like number of output clocking signals having the same phasing relationships to be transmitted to other circuits on the chip. More precisely, the invention concerns a new clock buffer circuit as claimed in claims 1 and 5. The invention, which is defined by the appended claims, opperates in accordance with the following operating Principles. Initially, the pull-down transistor (that is, the transistor connected to ground) is turned on, that is, conducting, and the pull-up transistor is turned off, or non-conducting. In that condition, the clock signal output is at a ground, or low, voltage level. When the clock signal is to switch from the ground level to a high level, that is, the power supply voltage level, the enabling signal turns the pull-up transistor on, causing it to begin conducting. The resistor and two transistors form a voltage divider when both transistors are conducting to raise the voltage level at the output node towards the voltage level of the positive power supply. In this condition, and depending on the parameters of the circuit, during this overlap period the voltage level of the output clocking signal may be on the order of several hundred millivolts. The second transistor is then turned off isolating the node between the transistors from ground, and the gate of the first transistor is isolated from the rest of the circuit, causing it to float. The charge stored in the intrinsic gate to source and gate to drain capacitances of the pull-up transistor causes the voltage level at its gate terminal to be bootstrapped to a voltage level above that of the positive power supply, causing the voltage at the source terminal of the pull-up transistor, that is, the node beteen the transistors, from which the clock signal output is taken, to increase to approximately the level of the positive power supply. The presence of the resistor in the bootstrap circuit provides several benefits. Since the pull-up transistor is not saturated, the sum of its intrinsic gate to drain and gate to source capacitances is greater than if the pull-up transistor were saturated. The resistor also reduces the source to drain voltage difference across the pull-up transistor, reducing the "hot electron" effect and accompanying noise and deterioration problems. Furthermore, the resistor limits the overlap current, that is, the current that passes through the pull-up and pull-down transistors when they are both on. Prior circuits do not have a current-limiting resistor, resulting in a wasting of power, generation of excess heat, and requiring interconnects having larger cross-sections to handle the currents. In addition, since, in the prior art, the drain terminal of the pull-up transistor was connected directly to the positive power supply, the drain was held at the voltage level of the positive power supply. The addition of the resistor allows the voltage level of the drain of the pull-up transistor to vary, which enables the gate to source and gate to drain capacitances to both effectively couple charge into the gate of the pull-up transistor, resulting in sufficient bootstrap action without the need for a discrete bootstrap capacitor. In one specific embodiment, the clock buffer circuit provides four clock signals in two pairs of complementary signals, with the signal pairs being displaced by one-fourth period. In that embodiment, each clock signal is generated by a separate module of the buffer circuit, with the modules generating each pair of signals being cross-connected to control and synchronize the rising and falling of the respective signals. Each module sends two signals to the other module in the pair, one signal controlling the rising and the other to controlling the falling of the other signal in the pair. The pairs of modules are also cross-connected to control which of the signals received from the other module in each pair controls the receiving module. Brief Description of the Drawings The invention is pointed out with particularity in the appended claims. The above and other advantages of the invention may be better understood from the following detailed description when taken in conjunction with the accompanying drawings in which: Fig. 1 is a general block diagram of a clock signal generating circuit including the instant invention; Fig. 2 contains a timing diagram illustrating the relationship among the clock signals generated by the circuit depicted in Fig. 1; Figs. 3A and 3B together form is schematic circuit diagram depicting two modules of the clock buffer circuit depicted in Fig. 1 which generate complementary clock signals ; Fig. 3C is a diagram useful in understanding the circuit depicted in Fig. 3A. Detailed Description of an Illustrative Embodiment With reference to Fig. 1, a clock circuit 10 receives a BASE CLK base clocking signal from, for example, a crystal oscillator, over a line 11. The BASE CLK signal is directly received in a counter circuit 12, which generates four enabling signals identified as EN PH0 through EN PH3 (which are generally referred to as EN PHn, where "n" is an integer between 0 and 3) and transmits them over lines 13 through 16 to a clock buffer circuit 17. The clock buffer circuit comprises four modules 17A through 17D, each of which receives an EN PHn signal from the counter circuit and, in response thereto and to control signals from the other modules, generates a clock signal PH0 through PH3. The buffer circuit modules then transmit the generated clock signals on lines 20 through 23 to the clocked circuit components on the remainder of the device (not shown). Fig. 2 illustrates the general timing relationships among the various clocking signals PHn ("n" being an integer from 0 to 3) of one embodiment of the invention. The EN PHn enabling signals have the same timing relationships as the corresponding PHn clocking signals, although it will be recognized by those skilled in the art that the PHn clocking signals will be delayed from the respective EN PHn signals due to gate and other delays in the buffer circuit modules. As shown in Fig. 2, the PH0 and PH1 signals are complementary signals, that is, they are 180° out of phase. The PH2 and PH3 signals are also complementary signals. The transitions in the PH2 and PH3 signals occur midway between the transitions in the PH0 and PH1 signals, and the pairs of signals are thus a quarter period out of phase. As has been noted, the EN PH0 through EN PH3 enabling signals generated by counter circuit 12 have the same general relationship as the PH0 through PH3 clocking signals depicted in Fig. 2. The clock buffer circuit 17 is provided to ensure that sufficient current is provided to the clocked circuit components on the rest of the device so that the PH0 through PH3 clock signals have fast rise and fall times. It will be appreciated that, since the lines carrying clocking signals on, for example, an integrated circuit chip are often relatively quite long, since they travel to and control large numbers of circuits, a large amount of current must be provided rapidly to ensure acceptably fast rise and fall times. Typically, the flip-flops which generally comprise a counter circuit such as counter circuit 12 are not able to provide the required current, and so the clock buffer circuit is connected to the counter circuit to buffer the enabling signals from the counter circuit to provide clock signals having the required currents. Figs. 3A and 3B depict a detailed circuit diagram of two modules of the buffer circuit 17, specifically modules 17A and 17B, which, respectively, receive the EN PH0 and EN PH1 enabling signals and generate the PH0 and PH1 clock signals (Fig. 2). The circuits comprising the other modules 17C and 17D are similar to the circuits depicted in Figs. 3A and 3B. In a physical implementation of the circuit, the actual sizes of the transistors which are used in the circuit will depend on the amount of current required to be supplied by the particular module. With reference to Fig. 3A, module 17A includes a buffer section 30A which receives the EN PH0 enabling signal on line 13 from counter circuit 12 (Fig. 1) and which generates two enabling signals EPH0 and EPH0D, the EPH0D signal being delayed from the EPH0 signal. The amount of the delay which is desired between the EPH0 and EPH0D enabling signals depends on factors which will be explained below. The EPH0D enabling signal is transmitted to a generating section 29A, which also receives the EPH1 enabling signal and the PH1 clock signal from module 17B (Fig. 3B) and the PH2 and PH3 clock signals from modules 17C and 17D. In response to these signals, module 17A generates the PH0 clock signal. The buffer section 30A is conventional, essentially including a plurality of inverter circuits 31, 40 and 41 connected to form two non-inverting buffers. The EPH0 enabling signal is taken from node 45 and the delayed enabling signal EPH0D is taken from node 46, which forms the output of the second buffer in the series. Since the buffer section is conventional, it will not be described further herein. With reference to Fig. 3B, module 17B also includes a buffer section 30B, which is similar to buffer section 30A and so will not be described in detail. The buffer section 30B receives the EN PH1 enabling signal on line 14 from counter circuit 12 (Fig. 1) and also generates two enabling signals EPH1 and EPH1D, the EPH1D signal being delayed from the EPH1 signal in like manner to the delay between the EPH0 and EPH0D signals. The EPH1D enabling signal is transmitted to a generating section 29B, which also receives the EPH0 enabling signal and the PH0 clock signal from module 17A (Fig. 3A) and the PH2 and PH3 clock signals from modules 17C and 17D. In response to these signals, module 17B generates the PH1 clock signal. In brief, the EPH0D delayed enabling signal is transmitted to generator section 29A of module 17A and is used with the EPH1 enabling signal and the PH1 clock signal from module 17B to control the generation of the PH0 clock signal. Similarly, the EPH1D enabling signal is transmitted to generator section 29B (Fig. 3B) and is used with the EPH0 enabling signal and the PH0 clock signal from module 17A to control the generation of the PH1 clock signal by generator section 29B. Both modules receive the PH2 and PH3 clock signals from modules 17C and 17D. In generator section 29A, the PH2 and PH3 clock signals selectively control the use by generator section 29A of the EPH1 or PH1 signals from module 17B in the generation of the PH0 clock signal, so that the timing of the falling edge of the PH1 signal is used by generator section 29A to control the timing of the rising edge of the PH0 signal an the timing of the rising edge of the EPH1 signal is used to control the timing of the falling edge of the PH0 clock signal. Similarly, the PH2 and PH3 clock signals selectively control the use by generator section 29B of the EPH0 or PH0 signals from module 17A in the generation of the PH1 clock signal, so that the timing of the falling edge of the PH0 signal is used by generator section 29B to control the timing of the rising edge of the PH1 clock signal and the timing of the rising edge of the EPH0 signal is used to control the timing of the falling edge of the PH1 clock signal. The operation of generator sections 29A and 29B will be described with particular attention to time A in Fig. 2, that is, when the PH1 clock signal is falling and the PH0 clock signal is rising (time A). Since the operation of the generator sections is identical, the operation at time B, when the PH0 clock signal is falling and the PH1 clock signal is falling will be only briefly noted. The operations at other signal transitions will be apparent to those skilled in the art. With reference to Fig. 3A, immediately prior to time A, a pull-up transistor 60A connected through a resistor 61A to the positive power supply is off (non-conducting) and its associated pull-down transistor 55A, which is connected to ground, is on (conducting). As a result, the node between the transistors 55A and 60A, from which the PH0 clock signal is taken, is at the ground voltage level. Since, at this time, the EPH1 signal has just gone low, transistor 56A is also off. Transistor 50A, controlled by the high PH3 clock signal (Fig. 2), is on and transistor 51A, controlled by the low PH2 clock signal, is off, causing node 52A to be high and transistor 53A to be on. With transistor 56A off and transistor 53A on, the node 54A is controlled by the high PH1 clock signal, causing transistor 55A to be on. Transistor 57A, a depletion mode transistor, is also on. Since transistor 55A is on, as noted above, the PH0 clock signal is at the ground voltage level. Transistor 60A is maintained in an off condition by a low EPH0D signal from buffer 30A through the on transistor 57A. With reference to Fig. 3B, and also immediately prior to time A, a pull-up transistor 60B connected through a resistor 61B to the positive power supply is turned on, and its associated pull-down transistor 55B which is connected to ground, is turned off. As a result of this, and a bootstrapping action described below in connection with transistor 60A, which is identical to the bootstrapping action of transistor 60B, the node between the transistors 55B and 60B, from which the PH1 clock signal is taken, is at the voltage level of the positive power supply. Since the EPH0 signal is low, transistor 56B is also off. Transistor 57B, also a depletion mode transistor, is off since the voltage level of the gate terminal, which was last controlled by the low PH0 signal, is below the voltage level of the source terminal, which is at the high voltage level of the gate terminal of the bootstrapped pull-up transistor 60B, by an amount greater than the threshold. Transistor 50B, controlled by the low PH2 clock signal, is off and transistor 51B, controlled by the high PH3 clock signal, is on. At this time, the node 52B is low, turning off transistor 53B and preventing the low PH0 clock signal from controlling node 54B. The fall of the EN PH1 enabling signal causes the EPH1 and EPH1D signals to fall. When the EPH1 signal is low, transistor 56A is off, and node 54A is controlled by the PH1 clock signal through transistor 53A. The subsequent rise of the EN PH0 enabling signal enables the buffer 30A to cause the EPH0 enabling signal to go high, to a voltage level of the positive power supply. When the EPH0 enabling signal goes high, it turns on transistor 56B, which, in turn, turns on transistors 55B and 57B. Turning on transistors 55B and 57B, in turn, causes the PH1 clock signal to begin falling, and the falling EPH1D signal, which is applied to transistor 60B through transistor 57B, also causes transistor 60B to rapidly turn off, which contributes to a fast fall time for the PH1 clock signal. With reference to Fig. 3A, when the EPH0D enabling signal then goes high, transistor 60A is turned on through transistor 57A. At this point, the PH1 clock signal has not completely fallen, and so both the pull-up transistor 60A and the pull-down transistor 55A are on and conducting at the same time. Resistor 61A limits the overlap current which flows through transistors 60A and 55A at this time when both are conducting, thereby reducing the power drawn from the positive power supply. With reference to Fig. 3C, which depicts the voltage as a function of time of the PH0 and PH1 clock signals around time A, the signal voltage resulting from the overlap current is reflected in a small increase in the voltage level of the PH0 clock signal. Since transistor 60A is turned on, it is also storing charge in its intrinsic gate to drain and gate to source capacitances. The resistance of resistor 61A is selected to maintain transistor 60A in a linear, unsaturated mode of operation to maximize the intrinsic gate to source and gate to drain capacitances of the transistor and eliminate the need for extrinsic bootstrap capacitors. With reference again to Fig. 3A, since transistor 53A is on and the PH1 signal is falling, node 54A goes low and turns off both transistor 55A and transistor 57A, the latter causing the gate of transistor 60A to float. While transistor 55A was on, the source terminal of transistor 60A, from which the PH0 clock signal is taken, was held to approximately ground level, but with transistor 55A off, the voltage level of the source terminal, and thus of the PH0 clock signal, is no longer held at ground level, but instead starts to rise. Furthermore, since, when the pull-down transistor is off, the overlap current portion of current through the resistor is eliminated, the voltage drop across the resistor is decreased, thus causing the voltage level of the drain terminal to rise. Since the voltage levels of both the source and drain terminals of the pull-up transistor 60A are rising, and its gate terminal is isolated by transitor 57A being off, the charge stored in the gate to source and gate to drain capacitances of pull-up transistor 60A causes the voltage level of the gate terminal of the pull-up transistor to rise above the voltage level of the positive power supply in a bootstrapping operation. It will be appreciated by those skilled in the art that, by an appropriate selection of the characteristics of transistor 60A, the voltage level of the gate terminal of the pull-up transistor may be made so as to cause the voltage level at the source terminal, which corresponds to the node between the transistor 60A and transistor 55A from which the PH0 clock signal is taken, to increase to about the voltage level of the positive power supply. At this point, the PH0 signal is high and the PH1 signal is low. At time B (Fig. 2), the same operations occur, except that the PH1 clock signal rises and the PH0 clock signal falls. At this time, the PH2 clock signal is high and the PH3 clock signal is low, turning off transistor 53A and turning on transistor 53B. Transistor 56A (Fig. 3A) is turned on by the high EPH1 enabling signal from buffer 30B (Fig. 3B). Since transistor 53A is off, node 54A is controlled by transistor 56A. Transistor 56A, in turn, turns on transistors 55A and 57A, thereby causing the PH0 signal to fall, and transistor 60A is turned off by the low EPH0D signal. The operation of the generator section 29B in Fig. 3B at time B is the same as described above for generator section 29A at time A. As has been noted, the EPHnD signals are delayed from the respective EPHn signals. The delay time is selected to permit the complementary clock signals to have the desired synchronization of rising and falling which, in turn, is also a factor in controlling the overlap time when both transistors 55A or 55B and 60A or 60B, respectively, in the respective generator sections are on. For example, at time A, as described above, the EPH0 signal controls when the PH1 clock signal begins to fall. The EPH0 signal turns on transistor 56B (Fig. 3B), which, in turn, turns on transistor 55B, causing the PH1 signal to begin to fall. The EPH0D signal then controls when the PH0 clock signal begins to rise, as it turns on transistor 60A. It will be appreciated that the operation of clock signal generators 29A and 29B has been described when they are in a steady state mode of operation, several clock cycles after the buffer circuit is initially turned on. When the circuit is initially turned on, several cycles are required to enable the modules 17A through 17D to allow the clock signals to have uniform amplitudes. The resistances of resistors 61A and 61B are selected to keep the pull-up transistors 60A and 60B in their linear, non-saturated, operating ranges. When the transistors are kept non-saturated, the sum of the intrinsic gate to drain and gate to source capacitances is larger than if the transistors were allowed to be saturated, thereby eliminating the need for explicit bootstrap capacitors connected to the gate terminal of the pull-up transistor. The resistors also limit the current through the pull-up and pull-down transistors during the overlap period, thereby allowing a reduction in the amount of power drawn by these transistors during this period. The resistors 61A and 61B also reduce "hot electron effect" problems by reducing the source to drain potentials across the pull-up transistors , which reduces the likelihood of electrons accelerating into the substrate or tunnelling into the gate oxide. The reduction of the source to drain potential across the pull-up transistors helps to reduce potential noise problems from excess substrate currents, and also reduces possible deterioration in operation of the transistors from electrons becoming lodged in the gate oxide. As has also been noted, the resistors 61A and 61B also serve to limit the overlap current when both the respective pull-up and pull-down transistors are on, which reduces the power consumed by the circuit and also reduces the size the the components required to accommodate the current. In addition, reducing the overlap current helps to reduce the amount of waste heat generated by the circuit, which helps to enhance circuit life and reliability. The resistors also enable the intrinsic and gate to drain capacitance of the respective pull-up transistors to increase the bootstrapping effect while eliminating the need for extrinsic bootstrap capacitors. It will be appreciated that the invention provides a new and improved clock buffer circuit for generating clock signals, in response to enabling signals, having desired phasing relationships. The foregoing description has been limited to a specific embodiment of this invention. It will be apparent, however, that the invention can be practiced in integrated circuit chips having diverse basic construction, or in chips that use different internal circuitry.

Claims: A clock buffer circuit for generating a clock signal (PH0) in response to a timing signal (ENPH0) and a first enabling signal (EPH1), said clock buffer circuit comprising: a. first input means (56A) for receiving said first enabling signal (EPH1); b. means (30A) responsive to said timing signal (ENPH0) for generating a second enabling signal (EPH0D), both enabling signals being initially in a high condition prior to the time the clock signal (PH0) is to be asserted and said first enabling signal (EPH1) being in a low condition at the time said clock signal is asserted; and c. signal generating means comprising resistor means (61A), first pull-up transistor means (60A) and first pull-down transistor means (55A) serially connected between high and low power supplies, said first pull-up transistor means (60A) being connected to receive said second enabling signal (EPH0D) through a switch means (57A), said switch means being conditioned in response to the assertion of said first enabling signal (EPH1), to couple said second enabling signal (EPH0D) to said first pull-up transistor means (60A), and said first pull-down transistor means (55A) being connected to receive said first enabling signal (EPH1), said resistor means (61A) being selected to maintain both said first pull-up and first pull-down transistor means in a non-saturated condition when conducting, the node between said first pull-up transistor means and said first pull-down transistor means comprising an output terminal (20) for transmitting said clock signal (PH0), such that both said first pull-up and first pull-down transistor means are energized by said enabling signals to conduct prior to the time the clock signal (PH0) is to be high and at the time said clock signal becomes high, said first pull-down transistor (55A) being de-energized and said switch means (57A) being conditioned in response to a change of state of said first enabling signal (EPH1) to isolate said first pull-up transistor means (60A) from said low power supply and said second enabling signal (EPH0D) whereby the voltage level at said output terminal (20) is increased due to the charge stored in the intrinsic capacitance in the first pull-up transistor means (60A). A clock buffer circuit as defined in claim 1 further including means (53A) for receiving a third enabling signal (PH1) which is high in advance of the assertion of the first enabling signal (EPH1), said means (53A) for receiving the third enabling signal conditioning said switch means (57A) to couple said second enabling signal (EPH0D) to said first pull-up transistor means (60A) in order to de-energize said first pull-up transistor means when said second enabling signal thereafter goes low. A clock buffer circuit as defined in claim 2 further including a second input means for receiving fourth (PH3) and fifth (PH2) enabling signals wherein the fourth enabling signal (PH3) is high when the clock signal (PH0) is to shift from a low state to a high state and the fifth enabling signal (PH2) is high when said clock signal is to shift from a high state to a low state, said second input means including a first enabling signal switch means (53A) connected to means (50A,51A) for receiving said fourth and fifth enabling signals, said first enabling signal switch means (53A) conditioned to couple said third enabling signal (PH1) to said first pull-down transistor means (55A) when said fourth enabling signal (PH3) is high and to not couple said third enabling signal (PH1) to said first pull-down transistor means (55A) when said fifth enabling signal (PH2) is high. A clock buffer circuit as defined in claim 3 in which said second input means includes transistor means (53A), and said circuit further comprises input signal means connected to said second input means, output signal means connected to control said first pull-down transistor means (55A) and said switch means (57A), and control means comprising second pull-up transistor means (50A) and second pull-down transistor means (51A) connected in series between high and low power supplies, the node (52A) between said second pull-up and second pull-down transistor means being connected to control said transistor means (53A), said second pull-up transistor means (50A) being connected to receive said fourth enabling signal (PH3) and said second pull-down transistor means (51A) being connected to receive said fifth enabling signal (PH2). A clock buffer circuit for generating a number of pairs of clock signals (PH0 - PH3) in response to a like number of pairs of corresponding timing signals (ENPH0-ENPH3), each pair of said clock signals being pairwise complementary signals and each pair of timing signals being pairwise complementary signals, the signals being timed so that transitions between non-complementary pairs of signals do not overlap, said clock buffer circuit comprising a plurality of modules (17A-17D) each generating one of said clock signals, each module comprising: a. means (30A-30D) for receiving a timing signal and generating in response thereto an enabling signal (EPH0-EPH3) and a delayed enabling signal (EPH0D-EPH3D), said enabling signal having high and low transitions in advance of corresponding transitions of said delayed enabling signal; b. means (53A) connected to the module (17B) generating the complementary clock signal (PH1) for receiving the complementary clock signal; c. signal generating means comprising resistor means (61A,61B,..), first pull-up transistor means (60A,60B,..) and first pull-down transistor means (55A,55B,..) serially connected between high and low power supplies, said first pull-up transistor means being connected to receive said delayed enabling signal through a switch means (57A,57B,..), said switch means being conditioned in response to the assertion of said complementary clock signal (PH1) to couple said delayed enabling signal to said first pull-up transistor means, and said first pull-down transistor means being connected to receive said complementary clock signal (PH1), said resistor means being selected to maintain both said first pull-up and said first pull-down transistor means in a non-saturated condition when conducting, the node between said first pull-up transistor means and said first pull-down transistor means comprising an output terminal (20) for transmitting said clock signal (PH0), such that both said first pull-up and first pull-down transistor means are energized by said delayed enabling signal (EPH0D) and said complementary cock signal (PH1) to conduct prior to the time the clock signal (PH0) is to be high, and at the time said clock becomes high said first pull-down transistor means (55A) being de-energized and said switch means (57A) being conditioned in response to the shift from a high condition to a low condition of said complementary clock signal (PH1) to isolate said pull-up transistor (60A) from said low power supply and said delayed enabling signal whereby the voltage level at said output terminal is increased due to the charge stored in the intrinsic capacitance in the first pull-up transistor means (60A). A clock buffer circuit as defined in claim 5 wherein each module further includes means (56A,56B,..) for receiving the enabling signal from the module (17B) generating the complementary clock signal as a complementary enabling signal (EPH1), said complementary enabling signal receiving means (56A) conditioning said switch means (57A,57B,..) to couple said delayed enabling signal (EPH0D) to said first pull-up transistor means (60) in order to de-energize said first pull-up transistor means when said delayed enabling signal (EPH0D) is thereafter shifted to a low condition. A clock buffer circuit as defined in claim 6 wherein each module further includes input means for receiving a further pair of complementary clock signals as second (PH2) and third (PH3) enabling signals such that the third enabling signal (PH3) is high when the clock signal (PH0) is to shift from a low state to a high state and the second enabling signal (PH2) is high when said clock signal is to shift from a high state to a low state, said input means including enabling signal switch means (53A) connected to means (50A,51A) for receiving said second and third enabling signals, said enabling signal switch means (53A) conditioned to couple said complementary clock signal (PH1) to said first pull-down transistor means (55A) when said third enabling signal (PH3) is high and to not couple said complementary clock signal to said first pull-down transistor means when said second enabling signal (PH2) is high. A clock buffer circuit as defined in claim 7 in which said input means comprises transistor means (53A,53B,..), and said circuit further comprises input signal means connected to said input means, output signal means connected to control said first pull-down transistor means (55A,55B,..) and said switch means (57A,57B,..), and control means comprising second pull-up transistor means (50A,50B,..) and second pull-down transistor means (51A,51B,..) connected in series between high and low power supplies, the node between said second pull-up and second pull-down transistor means being connected to control said transistor means (53A), said second pull-up transistor means being connected to receive said third enabling signal (PH3) and said second pull-down transistor means being connected to receive said second enabling signal (PH2).

Inventors: BECK, JOHN C., DOBBERPUHL, DANIEL W.
Applicants: DIGITAL EQUIPMENT CORPORATION
Application year: 1985
Main classification: H03K19
IPC codes: G06F1, H03K19, H03K5