TAG CONTROL CIRCUIT FOR BUFFER STORAGE

Abstract: A tag control circuit (300′) in a memory access control apparatus in a digital computer system including a central processor (1) having a buffer storage (100), including a tag information store and update circuit (23, 30), and a circuit (24, 26, 27) for finding the necessity of operation for invalidation of the tag information and/or transmission of invalidation information to the central processor. The tag control circuit (300′) includes a first circuit (40, 42, 43) storing a plurality of access requests of the necessity operation found at the necessity of operation-finding circuit, a second circuit (51, 52, 53) storing a plurality of invalidation execute information found at the necessity of operation-finding circuit, and a circuit (19′) receiving a new access request and the access request stored in the first storing circuit and outputting one access request. The tag control circuit (300′) may further include a third circuit (45) storing only store access requests before sup­ plying them to the necessity of operation-finding circuit, an output of which is connected to the access request receiving and outputting circuit. The access request receiving and outputting circuit may output one access request defined by the following priority order: a new read access request, an access request stored in the first storing circuit, and a store access request stored in the third storing circuit.

Description: The present invention relates to a digital computer system, more particularly to a tag control circuit in a memory access control apparatus in a digital computer system. In a digital computer system including a central processor(s), a main storage, and a memory access control apparatus provided between the central processor(s) and the main storage, the central processor is provided with a buffer storage having a considerably faster access time compared to the main storage, however, a considerably smaller memory capacity. The central processor can directly access data stored in the buffer storage, which may be identical to that in the main storage,without an access request to the main storage through the memory access control apparatus. This improves the data access time in the central processor. The data in the buffer storage, which may be frequently used in the central processor, is previously transferred from a certain area in the main storage to an area in the buffer storage in response to an access request from the central processor. The data in the buffer storage may be updated in the area and may also be returned to the area in the main storage upon transfer of new data to the same area. In order to manage use in the buffer storage, first and second tag control circuits are provided. The first tag control circuit is provided in the central processor and is called "TAG1". The second tag control circuit is provided in the memory access control apparatus and is called "TAG2". The present invention essentially relates to the second tag control circuit TAG2. A previously proposed digital computer system, which will be explained later in detail with reference to the drawings, suffers from unnecessary communication between the central processor and the memory access control apparatus for managing the buffer memory storage, with a resultant reduction of the performance of the central processor. A previously proposed digital computer system also suffers from poor reliability of judgement of invalidation in the second tag control circuit TAG2 for a faulty data block of the buffer storage, which will be explained in more detail with reference to a specific example. An embodiment of the present invention can provide a tag control circuit in a memory access control apparatus for managing a buffer storage which can reduce unnecessary communication between the central processor and the memory access control apparatus for management of the buffer storage. An embodiment of the present invention can provide a tag control circuit in a memory access control apparatus which can improve the availability of data blocks of the buffer storage. According to the present invention, there is provided a tag control circuit in a memory access control apparatus in a digital computer system including a central processor and a main storage, said central processor including a buffer storage temporarily storing data for use therein and another tag control circuit for managing a status of said buffer storage, and said memory access control apparatus, for processing an access request to said main storage, being provided between said central processor and said main storage, comprising: means for storing and updating tag information indicating the status of said buffer storage; means for finding a necessity of an operation for invalidation of said tag information and/or transmission of invalidation information to said central processor; first means for storing at least one access request of the operation found at said necessity of operation finding means; and means for receiving a new read access request and the access request stored in said first storing means and outputting one access request from received access requests to said necessity of operation finding means in accordance with a predetermined priority order; characterised in that: said first storing means store a plurality of access requests of the operation found at said necessity of operation finding means; second means are provided for storing a plurality of invalidation execute information found at said necessity of operation finding means corresponding to said access requests stored in said first storing means; and third means are provided for storing only store access requests to said main storage before supplying them to said necessity of operation finding means, an output of which is connected to said access request receiving and outputting means; whereby said tag information storing and updating means effect an invalidation operation and/or transmission operation of the invalidation information on said central processor in response to information stored in said necessity of operation finding means and said second and third storing means. The tag information storing and updating means (circuit) effects an invalidation operation and/or transmission operation of the invalidation information to the central processor in response to information stored in the necessity operation finding circuit and the second storing circuit. Preferably, the tag information storing and updating circuit may include a plurality of registers, the number of which is equal to that of data blocks in the buffer storage. The necessity of operation finding circuit also includes a plurality of circuits for finding the necessity of operations, the number of which is equal to that of the registers of the tag information storing and updating circuit. The second storing circuit includes a plurality of registers, the number of which is equal to that of the registers in the tag information storing and updating circuit. The first storing circuit may include a plurality of steps of registers connected in series and in parallel with each other. The second storing circuit may also include a plurality of steps of registers connected in series and in parallel with each other, the number of steps of which is the same as that of the first storing circuit. The first and second storing circuits may be operated at synchronous timings. Preferably, the number of steps of registers of the first storing circuit is defined by the number of read access requests output consecutively in a predetermined period. The access request receiving and outputting circuit may preferably output one access request defined by the following priority order: a new read access request, an access request stored in the first storing circuit, and a store access request stored in the third storing circuit. Preferably, the tag control circuit may further include a circuit for adding redundancy to error discrimination. The redundancy adding circuit may include a counter for counting errors of the buffer storage. The redundancy adding circuit outputs an invalidation signal when the counted value exceeds a predetermined value during a predetermined period. Reference is made, by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram of a digital computer system including a memory access control apparatus having a tag control circuit in accordance with the present invention; Fig. 2 is a circuit diagram of a tag control circuit in a previously proposed memory access control apparatus; Fig. 3 is a circuit diagram of a replace control circuit in a previously proposed tag control circuit; Fig. 4 is a circuit diagram of a tag control circuit in a memory access control apparatus of an embodiment in accordance with the present invention; Fig. 5 is a circuit diagram of a replace control circuit in the tag control circuit in Fig. 4; Figs. 6a to 6g are timing charts illustrating the operation mode of the tag control circuit 300' in Fig. 4; Figs. 7a to 7f are timing charts illustrating another operation mode of the tag control circuit 300' in Fig. 4; Figs. 8a to 8g are timing charts illustrating still another operation mode of the tag control circuit 300' in Fig. 4; and Fig. 9 is a circuit diagram of an embodiment of the replace control circuit in Fig. 4. Before describing a preferred embodiment of the present invention, an explanation will be given of the basic construction and operation of a digital computer system which can include circuits in accordance with the present invention. Figure 1 is a block diagram of the digital computer system. In Fig. 1, the computer system includes two sets of parallel operating central processors (CPU) 1 and 6, a main storage 2, a main storage access control apparatus 3, a system monitoring unit 5, and a channel processing unit 4. The main storage 2 includes a plurality of memory cells of, for example, a semiconductor static random-access-memory (RAM) type. The channel processing unit 4 controls input and/or output devices. The system monitoring unit 5 monitors statuses in the computer system and can serve to correct a fault in the computer system. The central processors 1 and 6, the system monitoring unit 5, and the channel processing unit 4 transmit commands for memory access to the main storage access control apparatus 3 to access data in the main storage 2. In the following description, memory access for only the central processor 1 will be explained. The central processor 6, which may be operated in parallel with the central processor 1 by a pipeline operation system, has a similar construction to that of the central processor 1. Thus, the basic operation of the central processor 6 is similar to that of the central processor 1. The central processor 1 has a buffer storage 100 and a first tag control circuit (TAG1) 110. The buffer storage 100 consists of a plurality of memory cells, which may have faster access times than the main storage 2 and may be directly accessed from the central processor 1. The buffer storage 100, however, has a smaller memory capacity than the main storage 2, with a resultant requirement of frequent transfer of data between the buffer storage 100 and the main storage 2. When the data to be used in the central processor 1 is stored in an area in the buffer storage 100, the central processor 1 uses the data in the buffer storage 100 without transmitting an access request to the main storage 3 through the memory access control apparatus 3. On the other hand, when the data to be used in the central processor 1 is not stored in any area in the buffer storage 100, the central processor 1 must transmit an access request for transfer of data to the main storage 2 through the memory access control apparatus 3. The data read from the main storage 2 is once transferred to an area in the buffer storage 100, which is defined by tag information for indicating the status of the buffer storage 100 stored in the first tag control circuit (TAG1) 110. After completion of the data transfer, the central processor 1 is able to use the data just transferred into the buffer storage 100. The data can be directly updated by the central processor 1. Furthermore, when a new data transfer request to the same area occurs, the updated data must be removed from the area in the buffer storage 100 and restored to the main storage 2 to maintain the updated result for future use. After that, the new data transfer request may be realized. The status of use of data stored in the buffer storage 100 is kept in the first tag control circuit 110 as tag information. The buffer storage 100 consists of a plurality of data blocks composed of each data blocks, for example, 64 bytes and defining a minimum capacity for one transfer. The tag information indicates the current status of use of each data block in the buffer storage 100, thus is updated in response to a change of use. The data stored in the buffer storage 100 must be the same as that in the main storage 2, because the data stored in the main storage 2 is used in common by the whole digital computer system. When the data stored in the main storage 2 is updated due to a store request from the central processor 6 or other units 4 and 5, data stored in the buffer storage 100 corresponding to the above updated data cannot be used in the central processor 1 as it is and can be deemed invalid for use in the central processor 1. Accordingly, the central processor 1 and the tag control circuit 110 must once effect an invalidation operation which resets a validity bit (the valid bit) of the corresponding tag information. The updated data in the main storage 2 may be again transferred to the buffer storage 100 if required in the central processor 1. The above invalidation operation may also be effected when the data stored in the buffer storage 100 must be once restored to the main storage 2 due to, for example, the generation of a new store request to the same area storing the data therein. Furthermore, the invalidation operation may be effected when a fault or defect arises in the data block in the buffer storage 100. Even in an invalidation operation due to the other units 4 to 6, the central processor 1 must always watch (inspect) all memory requests occuring in the memory access control apparatus. This results in disturbances of operation in the central processor, with a resultant low efficiency of operation of the central processor 1. In order to overcome the above defect in buffer invalidation operation in the central processor, a second tag control circuit TAG2 300 is provided in the memory access control apparatus 3 for the central processor 1 and a second tag control circuit TAG2 350 for the central processor unit 6. The tag control circuits 300 and 350 correspond to the tag control circuits 110 and 610, respectively. When the memory access control apparatus 3 receives an access request for storing data from the other units 4 to 6 to the main storage 2, the memory access control apparatus 3 compares the tag information in the tag control circuit 300 with the received access request, and, when the address of the main storage 2 in the received access request matches the address stored in the tag control circuit 300, transmits a buffer invalidation signal including the address of the main storage 2 to the central processor 1. At the same time, the memory access control apparatus 3 effects a buffer invalidation operation on the corresponding tag information in the tag control circuit 300, that is, resets a valid indication signal in the tag information. Upon receipt of the buffer invalidation signal from the memory access control apparatus 3, the central processor 1 may also effect a buffer invalidation operation on the tag information in the tag control circuit 110. As can be seen from the above, by providing the tag control circuit 300 and performing the buffer invalidation operation, the central processor 1 need not inspect all memory access requests existing in the memory access control apparatus 3. This contributes to improving the ability of the central processor 1 having the buffer storage 100. However, a computer system as mentioned above still requires redundant communications between the central processor and the memory access control apparatus for managing use of the buffer storage. This will be explained immediately below with reference to the drawings. Figure 2 is a circuit diagram of the tag control circuits 300 and 350 in the memory access control apparatus 3. A detailed circuit diagram of the tag control circuit 350 is omitted, because the circuit is basically identical to the tag control circuit 300. In Fig. 2, reference numeral 10 designates a pipeline register receiving access request information, 19 a priority selection circuit, 20 a register receiving the selected access request, and 23 a tag information store unit consisting of 16 way register groups 23-0 to 23-15. The tag information store way register groups 23-0 to 23-15 are provided correspondingly to the data blocks in the buffer storage 100. Each of the tag information store way register groups 23-0 to 23-15 consists of a plurality of registers each of which consists of 24 bits, eight upper bits of which indicate the validity or invalidity of the corresponding data block in the buffer storage 100 and 16 lower bits of which indicate the memory address for the data stored in the corresponding data block in the buffer storage 100. Each of the tag information store way register groups 23-0 to 23-15 may be operated independently. The access request information also consists of 24 bits, eight upper bits of which designate one data block in the buffer storage 100, i.e., the corresponding register in the tag information store way register group of the tag information store way register groups 23-0 to 23-15, and 16 lower bits of which indicate the memory address. In Fig. 2, reference numeral 24 represents a comparator unit consisting of 16 way comparators 24-0 to 24-15, 26 a register unit consisting of 16 way registers 26-0 to 26-15, and 27 a register unit consisting of 16 way registers 27-0 to 27-15. The comparator unit 24 determines the necessity of operations for updating the valid or invalid bit and/or updating the new memory address and also finds parity errors in the access request information. The register unit 26 stores a way signal indicating execution of the above invalidation or the like operation determined at the comparator unit 24. The register unit 27 stores the memory address output from the tag information store unit 23 which concerns the above invalidation operation and outputs the stored memory address to the central processor 1 as a part of the buffer invalidation signal. In addition, in Fig. 2, reference numeral 28 designates an OR circuit, 30 a replace control circuit, explained in detail later, 40 and 41 registers, 47 a selector, 48 a register, 49 a buffer for temporarily storing buffer invalidation signals, and 50 a selection signal generation circuit. The operation of the circuit 300 will now be explained. When the memory access control apparatus 3 receives an access request from one of the central processors 1 and 6, the channel processing unit 4, and the system monitoring unit 5, the memory access control apparatus 3 first inspects the received access request to determine whether it is reasonable (possible or acceptable) and transmits an access command for the received access request to the main storage 2 to activate an access operation in the main storage 2. The register 10 is connected to another register (not shown), which may be jointly operated in the pipeline processing system, through a control line 101. The access request information set in the register 10 can be used for control of the pipeline system through the control line 101. Further explanation will be omitted, because this does not directly pertain to the present invention. The access request information stored in the register 10 is transferred to the register 20 through the priority selection circuit 19. The priority selection circuit 19 receives two signals from the register 10 and the register 40 and outputs the signal from the register 10 prior to the signal from the register 40 when both signals concurrently exist at inputs thereof. The memory address included in the access request information stored in the register 20 is supplied to one input terminal in each of the comparators 24-0 to 24-15 through a line 107. Each memory address stored in one register in each group of the register groups 23-0 to 23-15, which is designated by the eight upper bits mentioned above through a line 106, is also supplied to another input terminal at each of the comparators 24-0 to 24-15. Each of the comparators 24-0 to 24-15 checks the parity of the input signals, compares the two input addresses, and outputs a signal indicating the validity of the parity, coincidence of the input address, and the buffer data block validity/invalidity to each of the registers 26-0 to 26-15 through a line 108. Each signal stored in each of the registers 26-0 to 26-15 is supplied to the replace control circuit 30. Figure 3 is a circuit diagram of the replace control circuit 30 and other related circuits 27 and 48. The replace control circuit 30 consists of a NAND gate circuit 31 consisting of 16 NAND gates 31-0 to 31-15, each having inverted input terminals, an AND gate circuit 32 consisting of 16 AND gates 32-0 to 32-15, a register 33, a decoder 34, an AND gate circuit 35 consisting of 16 AND gates 35-0 to 35-15, each having inverted and non-inverted output terminals, a NAND gate circuit 36 consisting of 16 NAND gates 36-0 to 36-15, a NAND gate circuit 37 consisting of 16 NAND gates 37-0 to 37-15, an AND gate circuit 38 consisting of 16 AND gates 38-0 to 38-15, and a timing control circuit 38a. The replace control circuit 30 receives the signals from the registers 26-0 to 26-15 at the AND gate circuit 35 and effects the following operation in response to the relationship of the signals from the registers 26-0 to 26-15 and a grade of an access request which is currently processed in the memory access control apparatus 3, the grade being either an read access or a store access to the main storage 2, except when parity errors or other errors are found therein: Case A: When there exists coincidence of the addresses and the access request is a read access: Processing for buffer invalidation to the register groups 23-0 to 23-15 is not required, thus the replace control circuit 30 immediately terminates their operation. Case B: There exists coincidence of the addresses and the access request is a store access: An invalidation operation for the corresponding registers of the register groups 23-0 to 23-15 is required. In addition, the tag control circuit 300 must inform the central processor 1 of the necessity of invalidation operation of the first tag control circuit 110 in the central processor 1. The above operations are effected as follows: For the buffer invalidation operation in the tag control circuit 300, the replace control circuit 30 discriminates the way (faulty data block in the buffer storage) to be made invalid with reference to the contents of the registers 26-0 to 26-15 and the store access request at the gate circuits 38 and 32. That is, the AND gate 38 receives a store request valid signal ST-VAL and address match signals TAG2-MCH0 to TAG2-MCH15 stored in the registers 26-0 to 26-15 and outputs one high level signal to the AND gate 32. The replace control circuit 30 sets a way-invalidation signal from the AND gate 32 to the register 48. The access request in the register 20 is once loaded to the register 40 through a line 104. After a few clock cycles elapse, the access request once loaded in the register 40 is again loaded in the register 20 through a line 103 and the selection circuit 19, in accordance with control of the timing control circuit 38a. Then, the valid (validity) the corresponding register in the group of the register groups 23-0 to 23-15 designated by the content stored in the register 48 is reset from one ("1") to zero, which indicates an invalid status. The memory address stored in the corresponding register in the group of the register groups 23-0 to 23-15 is transferred to the corresponding register of the registers 27-0 to 27-15. The memory address stored in the corresponding register of the registers 27-0 to 27-15 which forms a part of the buffer-invalidation signal is transmitted to the central processor 1 through the OR circuit 28, the selector 47, and the buffer circuit 49. Case C: When coincidence of the addresses is not detected and the access request is the read access: An operation for updating the content in the tag information store registers in the register groups 23-0 to 23-15 is required. The operation is as follows: the replace control circuit 30 receives an updating way signal CPUO-BS-WAY from the central processor 1 at the register 33. The updating way signal is decoded at the decoder 34 and output to the register 48 through the gate circuits 31 and 32. A new main storage memory address stored in the register 20 is stored in the register in the corresponding register group of the register groups 23-0 to 23-15 designated by the content of the register 48. In addition, the operation for informing the main storage memory address to the corresponding central processor is required in the tag control circuit 300 so as to effect the invalidation operation for TAG1 in the central processor. The above operation in the tag control circuit 300 is similar to that described in the above-mentioned case B. Case D: When there is no coincidence between the address from the central processors 1 and 6 or the other elements 4 and 5 and the addresses stored in the registers in the register groups 23-0 to 23-15, and the access request is a store access: No operation for invalidation is required. In the above cases B and C, when a parity error is detected in the comparators 24-0 to 24-15 or when way-error signals TAG2-WAY-ERR0 to TAG2-WAY-ERR15 are received at the circuit 31, the operation for invalidation and/or updating the registers in the register groups 23-0 to 23-15 cannot be effected, thus the received access request information is retransferred to the corresponding central processor through the registers 40 and 41 and the selector 47 as a buffer-invalidation signal having an erroneous indication. During the operations of cases B and C, the tag control circuit 300 inhibits reception of new access request information. Accordingly, when the operation for invalidation and/or updating the tag information storing register groups 23-00 to 23-15 is effected in the tag control circuit 300, the central processor 1, which may request a buffer memory invalidation and/or update operation for the tag control circuit 300, must wait until the above operation in the tag control circuit 300 is completed. This clearly reduces the performance of the central processor. This is a disadvantage of a previously proposed digital computer system, in other words, there is disadvantageous communication between the memory access control apparatus 3 including the tag control circuit(s) and the central processor(s). In addition, in the previously proposed tag control circuit, all error information detected in the comparators 24-0 to 24-15 is transmitted through the register 41, the selector 47, and the buffer circuit 49, as mentioned above. An error may be generated due to noise on the lines between the central processors 1 and 6 or the other units 4 and 5 and the memory access control apparatus 3 or in the tag control circuit 300. Errors may be caused by incidential and instantaneous noise, which can be automatically eliminated immediately. Accordingly, the transmission of all error information to the central processor is not always necessary. These extra operations for the above errors in the central processor result in low efficiency of operation. In the previously proposed digital computer system, the above disadvantage cannot be eliminated. Furthermore, in the tag control circuit 300, when only one way error signal TAG2-WAY-ERR-0 to TAG2-WAY-ERR-15 from the central processor, or when only one parity error is detected in the comparator unit 24, is received at the gate circuit 31, the way in question is changed to be invalid even if the way error signal is not correct, for example, when the way error signal is superposed by instantaneous noises. This means that the tag control circuit 300 acts too sensitively with regard to errors. As a result, the data block in the buffer storage 100 corresponding to the way detected as erroneous may be too easily (unnecessarily) made available. This low reliability of error judgement may result in low availability of the buffer storage 100. Preferred embodiments of the present invention which can overcome the above disadvantages in a previously proposed digital computer system will now be explained. Figure 4 is a circuit diagram of an embodiment of a tag control circuit 300' in a memory access control apparatus 3 in accordance with the present invention. The circuit 300' corresponds to the tag control circuit 300 shown in Fig. 2. In Fig. 4, reference numerals the same as those in Fig. 2 indicate the same circuit elements. The tag control circuit 300' in Fig. 4 further includes a queuing register 45, registers 42 and 43, a selector 44, register units 51 to 53, and a selector 54 in addition to the tag control circuit 300 in Fig. 2. Accordingly, the selection signal generation circuit 50' is changed to output additional selection signals to the selector 44 and 54. The priority selection circuit 19' is also changed to output a highest priority access request in three access requests input therein. The queuing register 45 simply stores store access requests for later input to the register 20 through the priority selection circuit 19'. The queuing register 45 can hold 10 store access requests in this embodiment. Each of the register units 51 to 53 consists of 16 parallel-connected registers 51-0 to 51-15, 52-0 to 52-15, and 53-0 to 53-15, as shown in Fig. 5. The selector 54 includes a plurality of AND gates 54-1 to 54-6 as also shown in Fig. 5. In this embodiment, it is assumed that up to three read access requests can be consecutively output from the central processor during a predetermined period. As mentioned above, when the necessity of invalidation and/or update operation is detected, the access request is once loaded to the register 40. In order to handle three consecutive read access requests without delay in the central processor, a replace register unit consisting of three series-connected replace registers 40, 42, and 43 is preferably provided for queuing the access requests. In general, the access requests to be replaced can be shifted from the series-connected registers 40 to 43. However, the contents of the registers 40, 42, and 43 are not always shifted in the registers 42 and 43. For this the registers 40, 42, and 43 are also connected in parallel, and the selector 44, which outputs one of three input signals in response to a selection signal from the selection signal generation circuit 50', is provided. The above-mentioned concept may be applied to the three series-connected register units 51 to 53 and the selector 54. The register units 51 to 53 may be synchronously operated with the operation of the replace registers 40, 42, and 43. The operation of the tag control circuit 300' shown in Figs. 4 and 5 will be explained. Figures 6a to 6g are timing charts of the tag control circuit 300'. When an access request indicating a store request ST₀ is supplied to the register 10 at a time of a clock 1 (see Figs. 6a and 6b), the store request ST₀ is stored once in the queueing register 45 at a next clock time 2τ (Fig. 6d). The queuing register 45 simply stores store access requests, functioning in a first-in-first-out (FIFO) manner. The queuing register 45 can hold up to 16 store access requests, which is larger than the steps of the replace register unit of the registers 40, 42, and 43. When the register 10 receives another access request indicating a read request (or fetch request) RD₀ at a time of a clock 2τ (see Figs. 6a and 6c), the received read access request RD₀ is supplied to an input of the priority selection circuit 19' at a time of a clock 3τ. Simultaneously, the store access request ST₀ output from the register 45 is supplied to another input of the priority selection circuit 19' through a line 121. When three input signals are applied to the priority selection circuit 19', the priority selection circuit 19' outputs one input signal decided by a priority order. The highest priority is given to the signal on the line 104 output from the register 10. The second priority is given to the signal on the line 122 output from the selector 44. The lowest priority is given to the signal on the line 121 output from the register 45. Accordingly, in this case, the read access request RD₀ is selected at the priority selection circuit 19' and supplied to the resister 20 at a time of clock 3τ. The store access request ST₀ remains in the register 45, because it is not selected. The read access request RD₀ having a starting main storage memory address reading data to the data block in the buffer storage 100 is supplied to the comparators 24-0 to 24-15. When an address is found which is the same as the main storage memory address in the read access request RD₀ , in the corresponding tag information storing register in the register groups 23-0 to 23-15, no updating operation is required, as mentioned above for case A. Thus, the operation for the above read access request is immediately terminated. On the other hand, no address is found identical to the above main storage memory address, an output of the comparator of the comparators 24-0 to 24-15 designated by the read access request RD₀ is loaded into the corresponding register of the registers 26-0 to 26-16 which indicates the necessity of an update operation to the corresponding register of the tag information storing register groups 23-0 to 23-15. The above output is supplied to the replace control circuit 30. Upon receipt of the outputs of the registers 26-0 to 26-15, the replace control circuit 30 finds the way for which an invalidation operation is required at the circuits 35, 36, and 32. The found invalid way signal is stored in the corresponding register of the invalid way designation storing registers 51-0 to 51-15. The read access request RD₀ in the register 20 is once transferred to the first stage of the register 40 in the replace register unit. At a time of clock 3τ, a new store access request ST₁ is received at the register 10 (Fig. 6b). The received store access request ST₁ is also added to the register 45 at a time of the next clock 4τ. At the time of clock 4τ, only the store access request ST₀ stored in the register 45 is again supplied to the priority selection circuit 19' and is loaded in the register 20. When no address is found in the tag information storing register in the register groups 23-0 to 23-15, which is identical to the main storage memory address in the store access request, no invalidation operation is required, as mentioned-above in case D, thus the operation is immediately terminated. On the other hand, when an address is found identical to the main storage memory address, the store access request ST₀ may be also once stored in the replace register 40, at a time of clock 5τ. At the time of clock 5τ, before loading the store access request ST₀ into the register 40, the read access request REP-RD₀ once loaded in the register 40 is again loaded in the register 20 through the selector 44 and the priority selection circuit 19'. Along with the above operation, the tag registers designating the contents stored in the registers 51-0 to 51-15 are also transferred to the register 48 through the selector 54 due to the control of the selection signal generation circuit 50'. The update operation to the register of the tag information storing register groups 23-0 to 23-15 designated by the content of the register 48, that is, the designated register of the tag information storing register groups 23-0 to 23-15, is loaded with a new read memory address in the registers 20. Prior to the above new read memory address store (update) operation to the corresponding register of the tag information storing register groups 23-0 to 23-15, an old memory address is transferred to the corresponding register of the registers 27-0 to 27-15. The operation for transmission of the buffer invalidation to the central processor 1, which includes the old memory address in the corresponding register of the registers 27-0 to 27-15, is effected. In the central processor 1, the tag information storing register in the tag control circuit 110, which corresponds to the register of the tag information register groups 23-0 to 23-15 in the tag control circuit 300', may be updated to coincide with the register of the tag information storing register groups 23-0 to 23-15. At a time of clock 6τ, the store access request REP-ST₀ stored in the register 40 is again supplied to the priority selection circuit 19'. At the same time, the store access request ST₁ stored in the queuing register 45 is also supplied to the priority selection circuit 19'. In accordance with the above-mentioned priority order, the priority selection circuit 19' chooses the store access request REP-ST₀ prior to the access request ST₁. As a result, the invalidation operation of the corresponding register of the tag information storing register groups 23-0 to 23-15 is effected, that is, the valid bit in the corresponding register of the tag information storing register groups 23-0 to 23-15 is reset. At the same time, the memory address stored in the corresponding register of the tag information storing register groups 23-0 to 23-15 is supplied to the corresponding register of the registers 27-0 to 27-15. The buffer invalidation signal is output to the central processor 1, with a resultant update in the tag information storing register in the tag control circuit 110. At a time of clock 7τ, the store access request ST₁ is selected at the priority selection circuit 19', thus the invalidation operation for the store access request ST₁ may be effected. During the above operation, the central processor 1 can output the store access request ST₀ , the read access request RD₀ , and the store access request ST₁ without any wait. Figures 7a to 7f are timing charts illustrating another operation mode in the tag control circuit 300', wherein three consecutive read access requests RD₀ to RD₁ , all of which require the invalidation and/or update operation, are received. At a time of clock 1τ, the register 10 receives a first read access RD₀. At a next clock 2τ, the read access RD₀ is loaded in the register 20 and is once transferred to the register 40. At a time of clock 2τ, the register 10 receives a second read access request RD₁. At a next time 3τ, the read access request RD₁ and the read access request RD₀ stored in the register 40 are input to the priority selection circuit 19'. In accordance with the priority order mentioned above, the read access request RD₁ is chosen and supplied to the register 20. However, the read access request RD₁ must be also stored in the replace register unit. Then, first, the first read access request RD₀ stored in the register 40 is again stored in the register 42. After that, the second read access request RD₁ in the register 20 is stored in the register 40. At a time of clock 3τ, the register 10 receives a third read access request RD₂. At a next clock 4τ, the read access request RD₂ and the read access request RD₀ loaded in the register 42 are supplied to the priority selection circuit 19'. As mentioned above, the third access request RD₂ is loaded. The third access request RD₂ must be also stored in the replace register unit. Then, the read access request RD₀ in the register 42 is further transferred to the register 43, and the read access request RD₁ stored in the register 40 is also transferred to the register 42. After that, the read access request RD₂ is stored in the register 40. The read access requests RD₀ to RD₁ stored in the registers 43 and 42 are consecutively loaded to the register 20 from clock 5τ to clock 7τ, and the invalidation and update operation thereof is effected. During the above operation, the central processor 1 can output the read access requests RD₀ to RD₂ consecutively, without any wait. In addition, the central processor 1 can receive only the three buffer invalidation signals at the time from clock 5τ to 7τ, which indicate truly necessary invalidation operations. Figures 8a to 8g are timing charts illustrating still another operation mode in the tag control circuit 300'. The register 10 receives a store access request ST₀ at a clock time 1τ and read access requests RD₀ and RD₁ at clock times 2τ and 4τ. In this case, it is also assumed that the above access requests require invalidation operations. The operation during the clock time 1τ to 4τ is similar to that of the operation mentioned with reference to Figs. 6a to 6g. At a time of clock 5τ, the read access request RD₁ is stored in the register 40. However, the store access request ST₀ is not stored in the replace register unit, thus the store access request ST₀ is erased. As a result, the invalidation operation to the tag information storing register groups 23-0 to 23-15 for the store access request ST₀ is omitted, and the transmission of the buffer invalidation signal to the central processor 1 is not effected. In the embodiment, the central processor 1 may again output the invalidation request, if required later. This, on one hand, may cause a lower efficiency of the central processor 1, but on other hand, contributes to simplification of the tag control circuit 300'. The above defect can be easily eliminated by increasing the replace registers or by restoring the store request to the queuing register 45. Figure 9 is a circuit diagram of an embodiment of the replace control circuit 30'. The replace control 30' in Fig. 7 further includes a redundancy judgement circuit 39 consisting of 16 parallel-connected AND gates 391-0 to 391-15, each having inverted and non-inverted output terminals, a counter 392, 16 parallel-connected AND gates 393-0 to 393-15, and 16 parallel-connected latch circuits 394-0 to 394-15, in addition to the replace control circuit 30 shown in Fig. 5. The redundancy judgement circuit 39 receives way error signals TAG2-WAY-ERR-0 to 15, each of which is low-level when the data block in the buffer storage may be faulty. The counter 392 counts the low-level way error signals with the clock signals and outputs a high level carry-over signal CR to one input terminal of the AND gates 393-0 to 393-15 when the counted value exceeds a predetermined value, for example, 16, during a predetermined period. As a result, at least one of the AND gates 393-0 to 393-15 which receives the high-level output signal from one inverted output terminal of the AND gates 391-0 to 391-15 outputs a high-level signal to the corresponding circuit of the latch circuits 394-0 to 394-15, thus holding the high-level signal in the circuit of the latch circuits 394-0 to 394-15. The high-level signal stored in the corresponding latch circuit designates the data block in the buffer storage 100 to be made invalid for use and is supplied to the gates circuits 31, 36, and 37 for invalidation of the faulty data block. The data block invalidation (way separation) is intended to invalidate the corresponding tag information storing register. When a true way error signal, for example, TAG-WAY-ERR-0, is supplied to the redundancy judgement circuit 39, a data block invalidation (way separation) signal for a way 0 is output from the latch circuit 394-0 after a predetermined period, 16 clocks in this embodiment, elapses. On the other hand, even if some way error signals, the number of which is smaller than the counted number for outputting the carry-over signal CR in the counter, are supplied to the redundancy judgement circuit 39 during the predetermined period, the counter 392 is reset after the predetermined period elapses. Thus, no way separation signals are output from the latch circuits 394-0 to 394-15, because the above instantaneous way error signals may be considered illegal signals which may be generated by noise disturbance or the like. The way separation function is provided for every data block to ensure use of normal data blocks in the buffer storage 100. Note that, by providing the redundancy judgement circuit 39 in the replace control circuit 30', an illegal invalidation operation would never be caused by one or a few incidental errors. In this embodiment, the invalidation operation for the faulty data block is effected after 16 error signals are received. This means that the redundancy judgement circuit 39 will tolerate error signals due to noise disturbances or the like. Also, this contributes to improved availability of the use of the data blocks. During the counting operation, the way separation information is not transmitted to the central processor 1. Naturally, the final way separation information, which may mean a true data block fault, is transmitted to the central processor 1. In this regard, redundant communications between the central processor 1 and the tag control circuit 300' are reduced, with a resultant improvement in the operation efficiency of the central processor 1. In the circuit 39 shown in Fig. 9, the counter 392 is commonly used for counting the way error signal TAG2-WAY-ERR-0 to -15. This, on one hand, contributes circuit simplification, but, on other hand, may result in some uncertainty of discrimination of the faulty data block. The latter problem may be solved by providing counters on each line between the AND gates 391-0 to -15 and the AND gates 393-0 to -15.

Claims: A tag control circuit (300') in a memory access control apparatus (3) in a digital computer system including a central processor (1) and a main storage (2), said central processor including a buffer storage (100) temporarily storing data for use therein and another tag control circuit (110) for managing a status of said buffer storage, and said memory access control apparatus (3), for processing an access request to said main storage (2), being provided between said central processor (1) and said main storage (2), comprising: means (23,30) for storing and updating tag information indicating the status of said buffer storage (100); means (24,26,27) for finding a necessity of an operation for invalidation of said tag information and/or transmission of invalidation information to said central processor(1); first means (40,42,43,) for storing at least one access request of the operation found at said necessity of operation finding means (24,26,27); and means (19') for receiving a new read access request and the access request stored in said first storing means and outputting one access request from received access requests to said necessity of operation finding means (24,26,27) in accordance with a predetermined priority order; characterised in that: said first storing means (40,42,43) store a plurality of access requests of the operation found at said necessity of operation finding means (24,26,27); second means (51,52,53) are provided for storing a plurality of invalidation execute information found at said necessity of operation finding means corresponding to said access requests stored in said first storing means (40,42,43); and third means (45) are provided for storing only store access requests to said main storage (2) before supplying them to said necessity of operation finding means (24,26,27), an output of which is connected to said access request receiving and outputting means (19'); whereby said tag information storing and updating means (23,30) effect an invalidation operation and/or transmission operation of the invalidation information on said central processor (1) in response to information stored in said necessity of operation finding means and said second and third storing means. A tag control circuit according to claim 1, wherein said tag information storing and updating means (23,30) includes a plurality of register groups, the number of which is equal to that of data blocks in said buffer storage, said necessity of operation finding means (24,26,27) includes a plurality of circuits for determining the necessity of operation, the number of which is equal to that of said register groups in said tag information storing and updating circuit, and said second storing means (51,52,53) includes a plurality of registers, the number of which is equal to that of said register groups in said tag information storing and updating means (23,30). A tag control circuit according to claim 1, wherein said first storing means (40,42,43) includes a plurality of steps of registers connected in series and in parallel with each other, and said second storing means (51,52,53) includes a plurality of steps of registers connected in series and in parallel with each other, a number of steps of which is the same as that of said first storing means, said first and second storing means being operated at synchronous timings. A tag control circuit according to claim 3, wherein the number of said steps of registers of said first storing means (40,42,43) is defined by the number of read access requests output consecutively in a predetermined period. A tag control circuit according to claim 4, wherein said tag information storing and updating means (23,30) includes a plurality of register groups, the number of which is equal to that of data blocks in said buffer storage, said necessity of operation finding means (24,26,27) includes a plurality of circuits for determining the necessity of operation, the number of which is equal to that of said register groups in said tag information storing and updating means, and said second storing means (51,52,53) includes a plurality of registers, the number of which is equal to that of said register groups in said tag information storing and updating means. A tag control circuit according to claim 5, wherein said access request receiving and outputting means (19') outputs one access request defined by the following priority order: a new read access request, an access request stored in said first storing means, and a store access request stored in said third storing means. A tag control circuit according to any preceding claim, further including means (39) for adding redundancy to error discrimination. A tag control circuit according to claim 7, wherein said redundancy adding means (39) includes a counter (392) for counting an error or fault of said buffer storage, and wherein said redundancy adding means outputs an invalidation signal when the counted value exceeds a predetermined value during a predetermined period. A tag control circuit according to claim 7 or 8, wherein said redundancy adding means (39) discriminates an error in each data block of said buffer storage with redundancy.

Inventors: CHIBA, TAKASHI 206, DAINISAGINUMAGURINHIRA, ISHIDA, MIYUKI 7, DAIICHIKURUMA-SO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F12
IPC codes: G06F12