LEVEL DETECTOR

Abstract: For detecting whether an input signal is above or below a reference level in such a way that brief signal interruptions and negative spurious pulses are not interpreted as de­ creases below the reference level, the detector comprises an input comparator (1), a first delay circuit (5), a second delay circuit (10) and an output circuit. The first delay circuit (5) comprises a first integrator comprising a first transistor (T₂) and a first capacitor (8), a first current source (7) and a second comparator (T₃). The second delay circuit (10) comprises a second integrator comprising a second transis­ tor (T₄) and a second capacitor (13), a second current source (12) and a third comparator (T₅). The first delay circuit (5) and the second delay circuit (10) have equal delay times. In order to ensure that during detection of a decrease below the reference level a positive spurious pulse is not interpreted as an increase above the reference level a third Transistor (T₆) connects a third current source (30) in parallel with the first current source (7) of the first delay circuit when the input signal lies below the reference level, so that the delay time of the first delay circuit (5) becomes smaller than that of the second delay circuit (10).

Description: The invention relates to a level detector having an input for receiving an input signal and an output for supplying an output signal, comprising: a first comparator, having an input and an output, for comparing the level of the input signal of the level detector with a reference level, which input of the first comparator is coupled to the input of the level detector; a first delay circuit for generating the output signal of the level detector if the level of the input signal of the first level detector decreases below the reference level for the duration of interval, which first delay circuit comprises a first capacitor arranged between an input and an output of a first integrator, which input of the first integrator coupled to the output of the first comparator and which output of the first integrator is coupled to a first current source and to a first input of a second comparator, said second comparator having an output and a second input for receiving a first reference potential; a second delay circuit for terminating the output signal of the level detector if the level of the input signal of the level detector exceeds the reference level for the duration of a second time interval, which second delay circuit comprises a second capacitor arranged between an input and an output of a second integrator, which input of the second integrator is coupled to the output of the second comparator and which output of the second integrator is coupled to a second current source and to a first input of a third comparator, said third comparator having a second input for receiving second reference potential and an output which is coupled to the output of the level detector. Such a level detector may be employed in, for example, a Compact Disc Digital Audio player. At the time of filing of the present Application such a player is commercially available under the type designation Philips CD 303. In such a player the digital audio information in the form of a spiral tracks of pits and non-pits is read by means of a laser beam and converted into a signal current. This signal current constitutes a sequence of sinusoidal pulses of variable width. The signal is amplified and applied to inter alia a plurality of level detectors, in which the signal level of the rectified signal is compared with a plurality of reference levels in order to supply control signals for the various control devices employed in a compact-disc player if these reference levels are not reached. The player comprises, for example, a tracking system in order to keep the laser beam on the track. The maximum signal level is obtained if the laser beam follows the centre of the track. If the beam is offset from this centre the signal level decreases. If a level corresponding to approximately 60% of the nominal level is not reached, a level detector generates a control signal by means of which the laser beam is returned to the centre of the track. In addition, the player comprises level detectors which, if a level corresponding to approximately 5O% and 20% of the nominal level is not reached then a control signal is generated respectively disabling a phase-locked loop in the speed-control system, which system becomes unreliable for low signal levels, and for detecting the absence of the signal as a result of flaws in and on the disc, so called drop-outs. For these control systems it is important that the level detectors accurately detect whether the levels are reached and in such a way that brief interruptions in the signal level between two consecutive pulses and spurious pulses cannot actuate these control systems. In the known compact-disc player the level detectors are constructed as a discrete circuits with non-integrable capacitors. However, it may be desirable to integrate these detectors on the same substrate as the other control circuits. A level detector which, in principle, is suitable for this purpose is known from United States Patent Specification 4,338,530, which describes a level detector of the type defined in the opening paragraph. In this detector the input signal is applied to a comparator which compares the input signal level with a reference level. The output signal of this comparator is applied to a first delay circuit which ensures that if the input signal briefly decreases below the reference level of the comparator such a decrease is not produce an output signal on the output of the level detector. The level detector only produces an output signal on its output when the input signal has remained below the reference level of the comparator for a specific time interval. A second delay circuit ensures that when the input signal again exceeds the reference level of the comparator the output signal of the level detector is sustained until the input signal has remained above the refence level for a specific second time interval. A drawback of this detector is that if the first time interval and the second time interval are equal to each other, which is desirable for the above-mentioned uses, a positive spurious pulse during a detected decrease below the reference level will be interpreted as an increase above the reference level. This leads to an undesired actuation of further circuits. Therefore, it is the object of the invention to improve the known level detector in such a way that the above problem is eliminated. According to the invention a level detector of the type defined in the opening paragraph is therefore characterized in that the first time interval and the second time interval are substantially equal to each other, and in that a switchable third current source is arranged in parallel with the first current source, and in that the level detector is provided with switching means for switching on the third current source if the output of the third comparator is currentless. At the instant at which a decrease below the reference level is detected the third current source causes the first time interval of the first delay circuit to become smaller than the second time interval of the second delay circuit. This ensures that during a detected decrease below the reference level a positive spurious pulse is not detected as an increase above the reference level. An embodiment of the invention is characterized in that the second comparator comprises a first transistor of a first conductivity type, having an emitter, a base and a collector, the emitter constituting the first input of the second comparator, the base constituting the second input of the second comparator and the collector constituting the output of the second comparator, and the third comparator comprises a second transistor of the first conductivity type, having an emitter, a base and a first and second collector, the emitter of the second transistor constituting the first input of the third comparator, the base of the second transistor constituting the second input of the third comparator and the first collector of the second transistor constituting the output of the third comparator, and in the switching means comprises a third transistor of a second conductivity type opposite to the first conductivity type, having a base, an emitter and a collector, the base of the third transistor being connected to the second collector of the second transistor and the collector of the third transistor being connected to the third current source and the collector of said third transistor being connected via a diode, to the first input of the second comparator. A further embodiment of the invention is characterized in that the first integrator comprises a fourth transistor of the second conductivity type, having a base, an emitter and a collector, the base of the fourth transistor being connected to the output of the first comparator the emitter of the fourth transistor being connected to a point carrying a third reference potential, and the collector of the fourth transistor being connected to the first current source, and in that the second integrator comprises a fifth transistor of the second conductivity type, having a base, an emitter and a collector, the base of the fifth transistor being connected to the output of the second comparator, the emitter of the fifth transistor being connected to the point carrying the third reference potential, and the collector of the fifth transistor being connected to the second current source, and in that the first current source, the second current source and the third current source each supply a current which is proportional to the current-gain factor of a transistor of the second conductivity type. Embodiments of the invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a known level detector, Figures 2a to 2d show some characteristics to explain the operation of the arrangement shown in Figure 1, Figure 3 shows a level detector in accordance with the invention, and Figures 4a to 4d show some characteristics to explain the operation of the arrangement shown in Figure 3. Figure 1 shows a known level detector. The level detector comprises an first comparator 1 having an input 2 to which the input signal, in the present case an input current I i , is applied. The output of a current source 4 carrying a reference current I ref is applied to the input 2. Further, the input 2 is connected to the emitter of a PNP transistor T₁ whose base is at a constant voltage V R and whose collector is connected to the output 3 of the comparator 1. This output 3 is connected to the input 6 of a first delay circuit 5. This circuit comprises an integrator comprising an NPN transistor T₂ whose base is connected to the input 6 and whose emitter is connected to the negative power-supply terminal, in the present case earth. Between the collector and the base of a transistor T₂ a capacitor 8 is arranged, which may for example be constituted by the collector-base capacitance of the transistor itself. The collector of the transistor T₂ is connected to the positive power-supply terminal by a current source 7. This current source 7 carries a current β I₁, i.e. a current which depends on the current gain factor β of a transistor. Such a current source can be realised, for example, by applying a constant current I₁ to the base of a transistor and using the collector current as the output current. The collector of the transistor T₂ is further connected to the emitter of a PNP transistor T₃ whose base is at a constant voltage V R and whose collector is connected to the output 9 of the first delay circuit 5. The transistor T₃ forms the comparator of the first delay circuit 5. A second delay circuit 10 comprising transistors T₄ and T₅, a capacitor 13 and a current source 12 is constructed in the same way as the first delay circuit 5. The input 11 of this second delay circuit is connected to the output 9 of the first delay circuit. The output 14 is connected to the base of an NPN transistor T₆ whose collector is connected to the positive power-supply terminal by a current source 20. The collector of the transistor T₆ is connected to the output 21 of the level detector. The transistor 6 with the current source 20 amplifies and inverts the output current of the second delay circuit 10. The operation of the arrangement will now be described in more detail with reference to figures 2a to 2d. Figure 2a shows the waveform of the input signal applied to the input 2 of the level detector. In the present example the input signal is the amplified and rectified signal current obtained by reading a compact disc. The input current I i comprises a sequence of sinewave pulses of variable width. This input current I i is compared with a reference current I ref to generate a control signal being if the maximum signal current I i is a smaller than the reference current I ref , in such a way that if the reference level I ref is not reached for a short time between two consecutive sinewave pulses this should not be detected. It is assumed that at the instant t = 0 the current I i is larger than the reference current I ref . The voltage on the emitter of the transistor T₁ is consequently higher than the voltage V R on its base, so that this transistor conducts and the difference between the input current I i and the reference current I ref is applied to the input 6 of the first delay circuit 5. The transistor T₂ is then turned on and is almost fully bottomed. As a result of this, the capacitor 8 is then discharged almost completely and the voltage V A on the collector of the transistor T₂, whose waveform is shown in Figure 2b, is substantially zero volts. Consequently, the transistor T₃ is cut off, so that the entire current β I₁, from the current source 7 flows through the transistor T₂. Then no current is applied to the input 11 of the second delay circuit 10, so that the transistor T₄ does not conduct. The capacitor 13 is then charged, in which case the voltage V B on the collector of the transistor T₄, whose waveform is shown in Figure 2c, is equal to V B = V R + V BET₅ , where V BET₅ is the base-emitter voltage of the transistor T₅. The current β I₂ from the current source 12 is then applied to the base of the transistor T₆ via the transistor T₅, so that this transistor T₆ conducts and receives the current from the current source 20. The output 21 is then currentless, as is illustrated in Figure 2d. If at the instant t = t₁ the current I i is smaller than the current I ref , the transistor T₁ and consequently the transistor T₂ are cut off. The capacitor 8 is then charged by the current β I₁ from the current source 7, so that the voltage V A increases. At the instant t = t₂ the current I i becomes larger than the current I ref . The transistor T₂ is turned on again via the transistor T₁. The capacitor C₈ is then almost wholly discharged immediately, so that the voltage V A becomes again substantially zero volts. The capacitor 8 has a comparatively low capacitance C. However, as a result of the Miller effect this capacitor, as seen from the collector of the transistor T₂, has a capacitance which is ( β +1) times as high. As a result of this, the voltage V A on the collector of the transistor T₂ increases only slowly in the interval t₁ = t₂ and does not reach the level at which the transistor T₃ is turned on. In this way it is achieved that if the current I₁ briefly decreases below the reference level I ref this has no effect on the output 21. In a similar way the interruptions between the instants t₃ - t₄; t₅ - t₆ and t₇ - t₈ have no effect on the output 21. At the instant t = t₉ current I i again becomes smaller than the current I ref and now remains below this level for a considerable time due to the absence of a signal, for example as a result of a dropout. The transistor T₂ is then turned off. The capacitor C₈ is now charged to such an extent that after a time τ₁ at the instant t = t₁₀ the voltage on the collector of the transistor T₂ becomes equal to V A = V R + V BET₃ , where V BET₃ is the base-emitter voltage of the transistor T₃. The current βI₁ from the current source 7 then flows to the base of the transistor T₄ via the transistor T₃, so that this transistor T₄ is turned on. The capacitor 13 is now almost wholly discharged immediatley so that the voltage V B becomes zero volts. As a result of this, the transistor T₅ is turned off, so that the transistor T₆ also becomes currentless. The current from the current source 20 now flows to the output 21 of the level detector. If the current I i becomes smaller than the current I ref , this is only detected at the output of the level detector if the current I₁ has remained smaller than the current I ref for at least a time interval τ₁. The delay time τ₁ is given by: where ( β + 1) C is the total Miller-multiplied capacitance, V R is the voltage across the capacitor 8 in the charged condition, and β I₁ is the current of the current source 7. The β -dependence of the current from the current source 7 ensures that the delay time τ₁ is independent of β and variations thereof. The delay time τ₁ can be adjusted by means of the current βI₁, the voltage V R on the base of the transistor T₂ and the capacitance C of the capacitor C₈. The delay time τ₁ should be adjusted in such a way that this time is longer than the maximum period of the input signal or, in the case of a rectified signal such as the signal shown in Figure 2a, the maximum half-cycle of the signal. For the signal shown in Figure 2a this maximum half-cycle is approximately 1 / us. The delay time τ₁ may then be selected to be for example τ₁ ≈10 / us. Such a time can be obtained, for example, by means of a collector-base capacitance of the transistor T₂ of C ≈1pF, a current I₁ ≈ 0.3 / uA and a voltage V R ≈ 3V. At the instant t = t₁₁ the current I i again becomes larger than the current I ref . Via the T₁ the transistor T₂ is turned on, so that the capacitor C₈ is discharged and the voltage V A becomes zero volts again. The transistor T₃ and the transistor T₄ are consequently cut off. As a result of this, the capacitor 13 is charged. If the reference level I ref is not reached briefly as between the instants t₁₂ and t₁₃, this has no influence on the charging of the capacitor 13. After a time τ₂ at the instant t + t₁₄ the voltage on the collector of the transistor T₄ becomes V B = V R + V BET₅ . The current βI₂ from the current source 12 then turns on the transistor T₆ via the transistor T₅, so that the output 21 becomes currentless again. The current I i should therefore be above the reference level I ref for a period τ₂ before this is detected on then output of the level detector. Brief interruptions of the signal during the time τ₂ are not regarded as excursions below the level. the delay time τ₂ may be selected to be equal or unequal to the delay time τ₁ the time τ₂ being adjustable in the same way as the time τ₁. As a result of the appearance of a negative spurious pulse or spike at the instant t = t₁₅ during a signal pulse the current I i becomes smaller than the current I ref very briefly. This spurious pulse is suppressed in the same way as brief signal interruptions between two consecutive signal pulses. A drawback of the arrangement shown in fig. 1 is that if a positive spurious pulse occurs between the instants t₁₀ and t₁₁, this is detected as an increase above the reference level and results in a corresponding signal on the output 21. When the spurious pulse exceeds the reference level the capacitor 8 is discharged rapidly and at the same time charging of the capacitor 13 is started. If briefly after this the level decreases below the reference level charging of the capacitor 8 begins. As the charging of the capacitor 13 has started earlier, the voltage V B on the collector of the transistor T₄ reaches the level at which the transistor T₅ is turned on before the voltage V A on the collector of the transistor T₂ has reached the level at which the transistor T₃ is turned on and discharges said capacitor 13. The spurious pulse is transferred to the output 21 of the detector because the transistor T₅ is turned on. A level detector in accordance with the invention is shown in Fig. 3 in which identical parts bear the same reference numerals as in Figure 1. In this embodiment the transistor T₅ in the delay circuit 10 is provided with a second collector. This second collector is connected to the base of a NPH transistor T⁷, whose emitter is connected to the negative power-supply terminal and whose collector is connected to the positive power-supply terminal by the current source 30 carrying a current βI₃ and to the collector of the transistor T₂ by a diode D₁. The transistor T⁷ operates as a switch by means of which the current source 30 can be connected in parallel with the current source 7. In the present embodiment the currents βI₁ and βI₂ from the current sources 7 and 12 are substantially equal to one another, so that in the case of equal capacitors 8 and 13 and equal voltages on the bases of the transistors T₃ and T₅ equal delays τ₁ and τ₂ are obtained, which is desirable for some purposes. In the present example the current βI₃ from the current source 30 is selected to be equal to βI₁, but this need not be necessarily so. The operation of the arrangement will be explained with reference to Figures 4a to 4d, where Figure 4a again represents the input signal I i ' Figures 4b and 4c represent the voltage V A and the voltage V B on the collectors of the respective transistors T₂ and T₄ , and Figure 4d represents the output current I₀. It is assumed that at the instant t = 0 the input current I i is larger than the reference current I ref . In this situation the voltage V B on the collector of the transistor T₄ is high and the transistor T₅ conducts, so that the transistor T₇ is driven into conduction. This transistor T₇ consequently receives the full current βI₃ from the current source 30. The diode D₁ prevents a part of the current βI₁ from flowing from the current source to the transistor T₇. Moreover, the diode D₁ is cut off. If the input current decreases below the reference level I ref between two consecutive sinewave pulses, such as between the instants t = t₁ and t = t₂ and if negative spurious pulses appear during a sinewave pulse, this does not effect the output of the level detector, in the same way as in the circuit arrangement shown in figure 1. At the instant t = t₃ the current I i again becomes smaller than the current I ref . After a time τ₁ at the instant = t₄ the voltage V A reaches the level at which the transistor T₃ is turned on. As a result of this, the voltage V B decreases and a current flows to the output 21. Since the transistor T₅ is cut off the transistor T₇ is also cut off, so that the current source 30 is connected in parallel with the current source 7. If at the instant t = t₅ as a result of a positive spurious pulse the current I i becomes larger than the current I ref the capacitor 8 is discharged rapidly and charging of the capacitor 13 begins. Very briefly after this at the instant t = t₆ the current I i again becomes smaller than the current I ref , so that the charging of the capacitor 8 begins. Since the current source 30 is connected in parallel with the current source 7, the capacitor 8 is charged more rapidly than the capacitor 13, i.e. 2x as fast in the present embodiment. The voltage V A on the collector of the transistor T₂ then reaches the level at which the transistor T₃ is turned on in a time τ i which is smaller than the time τ₂ in which the voltage V B on the collector of the transistor T₄ has reached the level at which the transistor T₅ is turned on. Since the transistor T₃ is turned on the capacitor 13 is discharged rapidly. As a result of this, the transistor T₅ remains in the non-conductive state, so that the positive spurious pulse is not transferred to the output. It is to be noted that in the arrangement of Figure 1 positive spurious pulses are also suppressed if the delay time τ₂ is selected to be longer than the delay time τ₁, which is easy to demonstrate. The invention is not limited to the present embodiments. For example, the comparator 1 may be constructed in different ways. Instead of a current the input signal may be a voltage which is compared with a reference voltage by means of a voltage comparator having a current output. In principle, the output transistor T₆ with the current source 20 may be dispensed with. However, alternatively these elements may be replaced by another output circuit. The integrators and comparators of the delay circuits may also be constructed in a manner other than shown. In the arangement shown in Figure 2 the current source 30 may also be arranged in parallel with the current source 7 in any other way. Finally, it is to be noted that the transistors may, of course, be replaced by transistors of opposite conductivity types.

Claims: A level detector having an input (2) for receiving an input signal (I i ) and an output (21) for supplying an output signal (I o ), comprising: a first comparator (1), having an input and an output, for comparing the level of the input signal of the level dectector with a reference level (I ref ), which input of the first comparator is coupled to the input of level detector; a first delay circuit (5) generating for the output signal of the level detector if the level of the input signal (I i ) of the level detector decreases below the reference level (I ref ) a first time for the duration of a first time interval (T₁), which first delay circuit comprises a first capacitor (8) arranged between an input and an output of a first integrator (T₂), which input (6) of the first integrator is coupled to the output (3) of the first comparator (1) and which output of the first integrator is coupled to a first current source (7) and to a first input of a second comparator (T₃), said second comparator having an output and a second input for receiving a first reference potential (V R ), a second delay circuit (10) for terminating the output signal of the level detector if level the level of the input signal (I i ) of the level detector exceeds the reference level (I Ref ) for the duration of a second time interval (τT₂) which second delay circuit comprises a second capacitor (13) arranged between an input and an output of a second integrator (T₄), which input (11) of the second integrator is coupled to the output (9) of the second comparator (T₃) and which output of the second integrator is coupled to a second current source (12) and to a first input of a third comparator (T₅), said third comparator having a second input for receiving a second reference Potential (V R )and an output which is coupled to the output of the level detector, characterized in that the first time interval and the second time interval are substantially equal to each other, and in that a switchable third current source (30) is arranged in parallel with the first current source (7), and in that the level detector is provided with switching means (T₇) for switching on the third current source if the output of the third comparator (T₃) is currentless. A level detector as claimed in Claim 1, characterized in that the second comparator (T₃) comprises a first transistor of a first conductivity type having an emitter, a base and a collector, the emitter constituting the first input of the second comparator, the base constituting the second input of the second comparator the collector constituting the output of the second comparator and the third comparator (T r ) comprises a second transistor of the first conductivity type, having an emitter, a base and a first and second collector, the emitter of the second transistor constituting the first input of the third comparator, the base of the second transistor constituting the second input of the third comparator and the first collector of the second transistor constituting the output of the third comparator, and in that the switching means (T₇) comprises a third transistor of a second conductivity type opposite to the first conductivity type, having a base, an emitter and a collector, the base of the third transistor being connected to the second collector of the second transistor and the collector of the third transistor being connected to the third current source and, the collector of said third transistor being connected via a diode to the first input of the second comparator. A level detector as claimed in Claim 1 or 2, characterized in that the first integrator (T₂) comprises a fourth transistor of the second conductivity type, having a base, an emitter and a collector, the base of the fourth transistor being connected to the output of the first comparator, the emitter of the fourth transistor being connected to a point carrying a third reference potential, and the collector of the fourth transistor being connected to the first current source, and in that the second integrator (T₄) comprises a fifth transistor of the second conductivity type, having a base, an emitter and a collector, the base of the fifth transistor being connected to the output of the second comparator, the emitter of the fifth transistor being connected to the point carrying the third reference potential, and the collector of the fifth transistor being connected to the second current source, and in that the first current source, the second current source and the third current source each supply a current which is proportional to the current-gain factor of a transistor of the second conductivity type.

Inventors: BIERHOFF, MARTINUS PETRUS MARIA, SCHOOFS, FRANCISCUS ADRIANUS CORNELIS MARIA, SLOMP, ALBERT HENDRIKUS, VAN MIL, JOB FRANCISCUS PETRUS
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1985
Main classification: H03K5
IPC codes: G11B20, G01R19, H03K5