TELEPHONE SWITCHING SYSTEM SWITCH PROCESSOR INTERFACE

Abstract: The interface (DT18) circuit eliminates the separation between hard-wired telephone switching system computer facilities and the customer owned switchably connectable computer facilities (T18). A general purpose communication interface (DT18) is provided which connects the customer provided computer facilities (T18) to both the switching network (101) and the hard-wired computer facilities of the telephone switching system via the standard telephone switching system port circuit (118). This general purpose communication interface (DT18) enables the customer provided computer facilities (T18) to communicate directly with the telephone switching system processor (100), thereby providing the customer with direct access to the call system processing data and subroutines of the telephone switching system.

Description: TELEPHONE SWITCHING SYSTEM SWITCH PROCESSOR INTERFACE This invention relates to a system processor interface arrangement in a switching system which serves a plurality of terminal equipment, each of which is connected by an associated port circuit to a switching network of the switching system, which switching network establishes network connections among the terminal equipment by interconnecting the associated port circuits, comprising, a system processor for controlling the operation of the switching system, a control signalling circuit connected to and interconnecting the system processor and the port circuits for exchanging control signals therebetween. Background of the Invention Stored program controlled telephone switching systems are used to interconnect telephone station sets as well as digital terminals, personal computers and large main-frame computers. The telephone switching system establishes communication connections between these computer facilities in a manner analogous to voice communications connections between subscribers who are using analog telephone station sets. The computer facilities are connected to communication pairs of the telephone switching system by modems. A standard telephone station set is also connected to the communication pair and is used to originate a call to a destination computer facility. As a result of the call origination, a communication connection is established through the switching network from the originating telephone station set to the destination computer facility. The user then switches the modem on line and the modem converts the digital signals output by the computer facility to analog signals which are transmitted by the switching network to a modem associated with the destination computer facility. The destination modem converts the received analog signals to digital signals for use of the destination computer facility. Thus, the telephone switching system simply provides a communication path between two designated end points which, in this case, are connected to computer facilities. The stored program controlled telephone switching system uses computers to govern its operation. A system processor or a number- of system processors operating in synchronization are hard-wired into the telephone switching system to control call establishment and switching network operation. Telephone switching systems also make frequent use of hard-wired micro-processors to perform low level time consuming tasks such as line scanning, protocol conversion, etc. thereby freeing the system processor to implement the high level call processing routines. There is a clear separation between these two computer environments. In one situation, computers are hard-wired into the telephone switching system to realize fixed telephone switching system control functions while in the other situation the telephone switching system interconnects customer owned computer facilities in a fashion analogous to the interconnection of analog station sets. The problem that the telephone subscriber with a computer terminal had was the restrictive use of the switching system because the only operations that were available from the switching system were the operations that were preprogrammed by the manufacturer of the switching system. The problems are solved in accordance with this invention by a system processor interface arrangement in which the system processor interface arrangement connected to one of the port circuits for providing direct signalling access to the system processor via the control signalling circuit of the one port circuit. Summary of the Invention The interface circuit of this invention eliminates this separation between hard-wired telephone switching system computer facilities and the customer owned switchably connectable computer facilities. A general purpose communication interface is provided which connects the customer provided computer facilities to both the switching network and the hard-wired computer facilities of the telephone switching system via the standard telephone switching system port circuit. This general purpose communication interface enables the customer provided computer facilities to communicate directly with the telephone switching system processor, thereby providing the customer with direct access to the call processing data and subroutines of the telephone switching system. The telephone switching system is equipped with port circuits which provide an interface for the terminal equipment via the communication pair. These port circuits transmit and receive a baseband signal on the communication pair that multiplexes voice, data and control signals. The telephone switching system routes the voice and data components of this signal through the switching network to other port circuits and thence to the associated terminal equipment. The control component of this signal is routed through a control signalling channel to the system processor of the telephone switching system. These port circuits presently provide only a limited control signalling channel communication capability. The terminal equipment transmit and receive only call setup information such as on/off hook, dialing, ringing, button and lamp status. The present invention includes a general purpose communication interface which uses this existing control signalling channel capability of the telephone switching system to establish a communication path between a computer connected to the communication pair and the system processor as well as the existing voice and data communication -paths to the switching network of the telephone switching system. The computer can be connected to any communication pair in the telephone switching system via this general purpose communication interface. The computer can communicate directly with the system processor of the telephone switching system to thereby provide an interface for: direct customer programming of the telephone switching system, creation of new features and services, or providing additional call processing capability for the telephone switching system. An example of this capability is that call processing subroutines and their associated data bases (such as attendant console/directory assistance) can reside on the computer. The telephone switching system then operates in synchronization with the computer to process calls by way of appropriate signals communicated between the system processor and the computer over the control signalling channel. In the case of attendant console operation, the telephone switching system routes attendant- directed calls to a station set associated with the computer and concurrently transmits call control information to the computer over the control signalling channel. The "operator" at the computer receives the call on the associated telephone station set as the computer concurrently executes the appropriate attendant call processing routine. This enables an individual at the computer to provide, for example, a combined attendant console/directory assistance function. The operator enters the name of the called party into the computer and the computer uses the directory assistance data base to identify the station number of the called party. The computer then automatically generates a call transfer request message. The call transfer message is transmitted via the control signalling channel to the system processor which activates the switching network ^ to transfer the call. The computer thereby relieves the telephone switching system processor of the burden of providing this real-time intensive task and also integrates what is now two discrete functions: directory assistance and operator services. This general purpose communication interface arrangement provides additional flexibility to the customer since the computer can be connected to any communication pair in the telephone switching system. Thus, in the above example, any employee at any location at any time can provide the attendant console/directory assistance function without requiring dedicated wiring as is required for existing attendant console arrangements in telephone switching systems. Brief Description of the Drawings FIG. 1 illustrates in block diagram form, the overall system structure of the subject telephone switching system; FIG. 2 depicts the details of the general purpose communication interface; FIG. 3 depicts the details of the firmware which controls the operation of the generate purpose communication interface; FIGS. 4-6 depict the details of the telephone switching system port circuit; FIG. 7 illustrates the method of arranging FIGS. 4-6; FIG. 8 depicts the details of the DCP signalling protocol; FIG. 9 depicts the details of the HDLC message frame; Detailed Description of the Drawing The telephone switching system of this invention is illustrated in FIG. 1. This system includes a plurality of terminal equipment T11-T58 each of which is associated with a respective one of port circuits 111-158. This terminal equipment includes telephone station sets as well as digital terminal devices and computer facilities. A switching network 101, which comprises a time slot interchange circuit connected to a number of port data/control interface circuits 171-175. Each port data/control interface circuit (e.g. 171) shown in FIG. 1 serves eight port circuits (111-118) and functions to interface these port circuits with switching network 101 as well as system processor 100. Switching network 101 operates under control of system processor 100 and establishes communication connections among the terminal equipment by interconnecting the associated port circuits 111-158. Terminal Equipment The standard digital terminal T11 generates an RS232 signal output which has a very limited transmission range. A digital terminal interface module (e.g.-DTl1) is used to convert the RS232 signals output by digital terminal T11 to alternate bipolar modulated code signals which can be transmitted a significant distance over a communication pair TR11 to the port circuits 111 of the telephone switching system. The digital terminal interface module DT11 is either an integral part of the digital terminal or connected between the existing digital terminal T11 and the associated communication pair TR11. In addition to this signal conversion, digital terminal interface module DT11 uses a particular message frame format (DCP) to effect data transmission between port circuits such as 111 and their associated digital terminals such as T11. This DCP format consists of a framing bit and three fields: an S field that conveys control signalling data, and two I fields that convey information data (FIG. 8). This is a well-known data transmission format as described in the article by N. Accarino et al entitled, "Frame-Mode Customer Access to Local Integrated Voice and Data Digital Network" published in the Conference Report of the IEEE 1979 International Conference on Communications. In this DCP data transmission format, one of the I fields can be used for the transmission of PCM- encoded voice information while the other one (or both I fields) can be used for the transmission of either bulk or interactive data. Message Format The terminal equipment served by the telephone switching system may be various types of equipment and the terminal equipment illustrated in FIG. 1 has concurrent voice and data transmission capability. In this system, all the terminal equipment which receive voice transmissions from the user convert the received analog voice signals into a set of digital data segments, each comprising an eight bit PCM-encoded voice sample. The terminal equipment which generates digital transmissions (such as keyboards) receive and originate digital data messages which are generally of length greater than eight bits. A typical format (HDLC) of these data messages is illustrated in FIG. 9, wherein each data message includes flag characters at the beginning and end of the data message; data, control and address fields; and a cyclic redundancy check field for error checking purposes. Signalling Channels This telephone switching system is equipped with two signalling channels which reflect the basic DCP message frame format used by the port circuits. In particular, a control signalling channel (S channel) conveys control messages (S field bits) between system processor 100 and terminal equipment T11-T58. The S channel extends from each terminal (such as T11 ) through associated digital terminal interface module (DTIM) DT11, communication leads TR11 , port circuit 111, leads P11 and thence through port data/control interface circuit 171 to system processor 100 via I/O BUS. The switching system is also equipped with an information channel (I channel) which conveys information data (I field segments) such as the eight-bit PCM-encoded voice signals or bulk data (in eight- bit bytes) between switching network 101 and terminal equipment T11-T58. The I channel extends from each terminal (such as T11 ) through associated digital terminal interface module (DTIM) DT11, communication leads TR11 , port circuit 111, leads P11 and thence through port data/control interface circuit 171 to switching network 101 via leads PA1. Thus, the digital terminal and its associated digital terminal interface module multiplex the actual data transmissions (voice and data) with the control signals. This multiplexed signal is then transmitted over the communication pair to the associated port circuit where it is demultiplexed. The actual data transmission is switched in traditional fashion by the switching network to the designated destination and the control signals are forwarded to the system processor. Again, these control signals are the standard on-hook/off-hook status, button operation, lamp lighting, and ringing signals common to all telephone switching systems. To effectively illustrate the structure and operation of the subject general purpose communication interface, the details of the existing port circuit and especially the S channel must first be explored. I Channel Realization System processor 100, in the course of connecting a calling digital terminal (T11) to a called digital terminal (T58), assigns a time slot in switching network 101 for the interconnection of digital terminals T11 and T58. Switching network 101 controls the data (I channel) transmissions between terminal equipment T11-T58. In particular, 'switching network 101 transmits each eight bit data segment received from digital terminal T58 to port circuit 111 via port data/control interface circuit 175. Port circuit 111 transmits each data segment so received to digital terminal T11 via. digital terminal interface module (DTIM) DT11 and also receives a reply data segment from diqital terminal T11 via DTIM DT11 for transmission to digital terminal T58. Port circuit 111 "transmits the reply data segment received from DTIM DT11 to switching network 101 via port data/control interface circuit 171. Switching network 101 stores the received data segment, and interchanges the data segments received from digital terminal T11 and digital terminal T58 during the time slot assigned for this call. This action interconnects these digital terminals. S Channel Realization The control or S channel transmissions are controlled by system processor 100. System processor 100 periodically scans each port, trunk and service circuit connected to switching network 101 to find if there is a control message for system processor 100. During each such scan cycle, system processor 100 transmits timing, address and control information to port data/control interface circuits 171-175 via I/O BUS. Each port data/control interface circuit (ex. 171) has a multiplexer which interprets the signals received on I/O BUS during each scan cycle and determines whether the address signals transmitted thereon identify one of the port circuits (e.g. 111) served by that port data/control interface circuit (171). If such a match occurs during a scan cycle, port data/control interface circuit 171 enables the identified port circuit 111 to read the control message transmitted to port data/control interface circuit 171 by system processor 100. Port circuit 111 reads the control message written into port/data control interface circuit 171 by system processor 100 and places the control message into a control message register (not shown) in port circuit 111. Port circuit 111 transmits this control message one bit at a time from the control message register to digital terminal interface module DT11. Digital terminal interface module DT11 assembles these serial bits into commands for digital terminal T11. Digital terminal T11 responds to these commands by performing the indicated operation, such as lighting a lamp, producing an audible ring signal, etc. If digital terminal T11 has no reply or other control message to send back to system processor 100, digital terminal interface module DT11 transmits idle bits back to port circuit 111. If digital terminal T11 has a control message to send to system processor 100, it is written into the control message register of port circuit 111 one bit at a time. Port circuit 111 sets a data-ready bit in its status register (not shown) to indicate to system processor 100 that a control message 5 has arrived from digital terminal T11. System processor 100 periodically scans the port circuit status registers via I/O BUS and port data/control circuit 171 for a set data-ready bit. When one is found, system processor 100 reads the control message stored in the 10 control message register of port circuit 111 and resets the data-ready bit in the status register. Control Signalling Channel The general purpose communication interface of this invention makes use of the control signalling channel 15 (S channel) to provide a direct communication link between a computer connected to a communication pair and the system processor of the telephone switching system. The computer used for this purpose can, for example, be a personal computer having a floppy disc memory. For the interaction 20 of the personal computer with the system processor to be understood, the port circuit must be examined in detail. To accomplish this, a description is provided of the general purpose port circuit. This description provides an understanding of the typical digital terminal connection to 25. the telephone switching system, upon which foundation the general purpose communication interface description can be constructed. Port Circuit, FIGS. 4-6 FIGS. 4, 5 and 6, when arranged shown in FIG. 7 30 disclose details of the port circuit with emphasis upon the port circuitry associated with the reception and generation of S bit signalling messages in the DCP frame format shown in FIG. 8. The communication pair TR18 comprises a 35 160 kilobit per second data link to the associated terminal equipment, computer T18. The 160 kilobit rate results from the fact that message segments of 20 bits (as shown in FIG. 8) are transmitted between computer T18 and port circuit 118 at an 8 Khz rate. Alternate bipolar modulation is used to transmit the data signals. Receiver The operation of the receiving portion of port circuit 118 is first described. Message segments from computer T18 are received in the DCP frame format and applied over communication pair TR18 to line receiver 401. Line receiver 401 derives its synchronization from the framing bits of each received message segment and passes the remaining fields (the S field and the two I fields) in serial form to frame demultiplexer 404 over lead 402. The synchronization circuitry of line receiver 401 generates a receive clock signal and applies it over lead 403 to the control portion of demultiplexer 404 as well as to receive formatter 407 and clock detector 408. Line receiver 401 separates the received signal from the noisy environment of the communication pair TR18 and transforms it into a logic level signal that is applied to the input of demultiplexer 404. Demultiplexer 404 demultiplexes the S field and the two I fields. The information in the two I fields comprises the data transmission from computer T18. This data transmission is extended over leads RI- | and RI 2 to multiplexer 405 which multiplexes the signals together and places them on time multiplexed bus PCM. Each I field occupies a different time slot on time multiplexed bus PCM and thus the information in each I field is transmitted out sequentially during each occurrence of its associated time slot. This information is applied to the time slot interchange facilities of the system which performs a conventional time slot interchange function and interconnects each I field with the port to which the call is directed. This invention is not concerned with the processing or switching of the I field information and therefore it is not described herein in further detail. The interface from the switch multiplexer 405 to the bus PCM contains both data and clock signals to control the switch multiplexer 405 and the switch demultiplexer 448. The S field information comprises one bit of the message segment of FIG. 8 and is applied over lead 460 to the receive formatter 407. Lead 460 comprises an eight kilobit per second serial channel carrying the S field information. Receive formatter 407 performs the customary flag detection operation on this signal. That is, it looks for a pattern of a 0, followed by six 1's and a 0, as shown on FIG. 9, and synchronizes to that pattern as long as the flags appear on . lead 460. As soon as receive formatter 407 detects a nonflag sequence, as is the case when a signalling message character is received, it begins to perform a serial to parallel conversion on each nonflag byte. During the time when nonflag characters are being received, receive formatter 407 performs a conventional zero delete function whenever it detects a sequence of five 1's followed by a 0. It does this in accordance with the HDLC protocol in order to prevent a message character from being construed as the reception of a flag character. Receive formatter 407, while it is performing this serial to parallel conversion on nonflag characters, also detects the reception of a flag character at the end of each message. It then generates a signal that is applied to lead 412 to specify the end of message for the received character. This path is also termed RCVEOM (Receive End Of Message). Receive formatter 407 applies each character after it is formed into a parallel format to leads 411 and from there to the " receive FIFO 414. Receive formatter 407 also generates a signal that is applied to lead 413 to control the strobing of information into FIFO 414. The signal on lead 413 appears concurrently with the signals on leads 411 and 412 so that they then can be strobed into FIFO 414. Receiver FIFO 414 Receiver FIFO 414 is organized as a 48 word, nine bit per word FIFO. The nine bits in each word are the eight bits representing the received character on leads 411 and a one bit "end of message" signal on lead 412 indicating whether or not each receive character does or does not represent the last character of a message. The characters that are applied to the input of receive FIFO 414 pass through in the conventional manner to the output of receive FIFO 414. These eight bits are applied over leads 416 to tri-state gates 417. The end of message signal associated with each character is applied over lead 419 to counter 421. The end of message signal is present only when the character is indeed the last character of a message and, at that time, the end of message signal increments counter 421 by a count of one. Tri-state gates 417 are enabled by a read register signal on lead 420. This signal is generated by system processor 100 and. applied to port circuit 111 over I/O BUS via port data/control interface circuit 171 and leads DATA when system processor 100 wishes to read the contents of FIFO 414. System processor 100 effects this operation by applying a unique address signal over the above described path to address decoder 433 to cause it to generate an output on lead 420 extending to FIFO 414 and gates 417. Each port circuit, including port circuit 111 shown on FIGS. 4, 5 and 6, is assigned a plurality of I/O BUS addresses. The various addresses represent the various functions of which the port circuit is capable. A particular function is initiated by the application of the associated I/O BUS address to decoder 433. Accordingly, in order to read out a character from FIFO 414, system processor 100 applies the port address associated with lead 420 to address decoder 433 via the DATA lead. Address decoder 433 responds to this address, drives lead 420 to cause the character at the output of FIFO 414 to be extended over leads 416 and through gates 417 to leads DATA. This character is then passed through port data/control interface circuit 171 and over I/O BUS to system processor 100 which stores it and every other received character until a complete message is formed. The read register lead 420 also extends to the OUTSTB terminal of FIFO 414. FIFO 414 responds to the trailing edge of this signal and advances the next character stored within FIFO 414 to the output of FIFO 414 so that it can be read on the next read register operation. Thus, the read register signal on lead 420 performs two functions. The first is to enable gates 417 to pass the character currently on FIFO 414 output over leads 416, through gates 417 to DATA lead. The trailing edge of the read register signal on lead 420 advances the next ' character within FIFO 414 to the output of FIFO 414. The ninth bit in FIFO 414 is the END OF MESSAGE bit on lead 419. This signal performs two functions. The first function is to provide a READ END OF MESSAGE signal to the input of the Status gate 426. Status gate 426 can be read by system processor 100 when it performs a READ STATUS REGISTER function on port circuit 111. Status gate 426 has a unique address and when system processor 100 applies this address to I/O BUS, the address is decoded by decoder 433 which applies an enable signal over lead 429 to activate status gate 426. Status gate 426 applies the signal present on lead 419, to DATA lead for transmission to system processor 100. The enabling of lead 429 enables all of the status register gates 424 through 428. The second function .of the READ END OF MESSAGE signal bit on lead 419 is to decrement R MSG counter 421. Counter 421 at any time has a count in it that indicates the number of messages currently stored within FIFO 414. Counter 421 is incremented by a RECEIVE END OF MESSAGE signal on lead 412 and is decremented when a READ END OF MESSAGE signal is read out of FIFO 414 on lead 419. Thus, the current count of counter 421 represents the number of complete messages currently stored within FIFO 414. The output of counter 421 on lead DR is the signal which permits a DATA READY indication to be read by system processor 100 as it scans status gates 424-428. The DR signal is extended through gate 458 when lead 422 carries an enable signal and from there the signal extends over lead 406 to the input of the scan register gate 423 and to gate 425. System processor 100 can read either scan register gate 423 or FIFO 414 by applying the appropriate addresses to I/O BUS. The address for either of these is decoded by decoder 433. The appropriate output of decoder 433 is enabled to activate the appropriate tri- state gate, such as 423 or 417, to allow data to be applied to DATA lead. Transmit System processor 100 can generate and write messages into port circuit 118 of FIGS. 4, 5 and 6 for transmission to computer T18. It does this by utilizing the write portion of port circuit 118. The first step system processor 100 performs on a port write operation is to determine whether transmit FIFO 440 is full and is able to accept the message. If FIFO 440 is not full, system processor 100 writes the first byte of the message into port circuit 118. System processor 100 performs this function by first applying the appropriate address signal to I/O BUS. The signal that is applied is that which is associated with the write portion of port circuit 118. Decoder 433 decodes this address and generates the WREG signal on lead 435. This signal enables tri-state gate 434 which allows the message information now on I/O BUS to be extended through gate 434 and over lead 457 to the input of FIFO 440. This signal on lead 435 is also applied to the INSTB input of FIFO 440 to strobe the message information currently on lead 457 into FIFO 440. Also strobed into FIFO 440 at this time is the ninth bit, a WRITE END OF MESSAGE bit, which is applied to FIFO 440 over lead 436. This signal indicates that the character associated with this bit is the last character of a transmitted message. System processor 100 sequentially writes each character of a message into FIFO 440. Just before the last character of the message is to be input into FIFO 440, system processor 100 writes into control register 431 via gate 432 which drives lead 459 to generate a WRITE END OF MESSAGE signal on lead 436. This signal is strobed into FIFO 440 at the same time the last byte of the message is strobed via the WREG signal on lead 435. The signal on lead 436 is automatically reset after the last byte is written into FIFO 440 by the trailing edge of the WREG signal on lead 435. Transmit FIFO 440 is organized as a 48 word by nine bits per word FIFO. Eight of the nine bits represent the character information; the ninth bit of each word represents the absence or presence of a WRITE END * OF MESSAGE signal. Transmit FIFO 440 has a WRITE BUFFER FULL output termed WBF. When all 48 words in FIFO 440 are filled, the WBF signal is extended over lead 430 to status register gate 427. This gate is periodically read by system processor 100 prior to writing FIFO 440. When FIFO 440 is full, the output of gate 427 advises system processor ' 100 that FIFO 440 can accept no more bytes for the time being. If FIFO 440 is detected to be full in the middle of writing a message, system processor 100 will queue the remainder of the message and throttle the load until a previously loaded message is transmitted and FIFO 440 becomes sufficiently empty to accept at least one more byte. The outputs of FIFO 440 are applied to leads 441 and 442. Lead 442 carries eight bits representing character information and lead 441" "carries an END OF MESSAGE bit. FIFO 440 receives a strobe signal from transmit formatter 445 over lead 443. The character information on lead 442 and the END OF MESSAGE signal on lead 441 are applied to the input of transmit formatter 445. Transmit Formatter 445 Transmit formatter 445 normally continuously generates and sends out flag characters on the channel to the associated customer station as long as there are no messages in FIFO 440. At such times, transmit formatter 445 sequentially generates a flag character of 0, six 1's and a 0. Whenever FIFO 440 is not empty, transmit formatter 445 begins the process of unloading the characters from FIFO 440 and transmitting them out over the S channel. It does this by performing a parallel to serial conversion on the received characters and the zero insertion function required for transparency. Thus, transmit formatter 445 first sends out flag characters when it determines from transmit FIFO 440 over lead 439 that FIFO 440 is not empty, then, at the end of transmission of the flag character, transmit formatter 445 generates a strobe signal that is applied over lead 443 to FIFO 440. This signal is used internally by transmit formatter 445 to load the character information on lead 442 and any END OF MESSAGE signal on lead 441 into transmit formatter 445. The trailing edge of this strobe signal is also used to advance FIFO 440 to bring the next character in FIFO 440 to the FIFO output. Transmit formatter 445 performs a parallel to serial conversion on the received information. It also performs a zero insertion function when it is sending non- flag characters out over lead 446. That is, if the transmitted bit stream of the message has five consecutive 1's, transmit formatter 445 inserts a 0 between the fifth-1 and the next bit transmitted. Thus, transmit formatter 445 transmits out each character it receives and it checks the END OF MESSAGE bit associated with each character. hen the last character in a message is received from FIFO 440, lead 441 is set to a 1. This tells transmit formatter 445 that this character is the end of a message and causes transmit formatter 445 to insert a flag after this character. Transmit formatter 445 does this and then checks for a transmit empty signal on lead 444. If the empty signal is present, transmit formatter 445 continues to generate and transmit flags. If the empty signal is not present, transmit formatter 445 then reads the next character out of FIFO 440. This new signal is a first character of a subsequent message. Transmit formatter 445 processes any such first characters of the subsequent message, and all other characters of that subsequent message, in a manner similar to that already described. System processor 100 can write an initialize bit into control register .431. This bit causes FIFOs 414 and 440 to be cleared as well as the MESSAGE counters 421 and 438. This effectively removes all information from port circuit 118. Lead 409 interconnects clock detector 408 with status register gate 424. Clock detector 408 normally receives clock pulses on lead 403 from line receiver 401. At such times, clock detector 408 applies a 0 over lead 409 to register gate 424. This permits system processor 100, when reading register gates 424-428, to determine that clock, pulses derived from the received data stream are being received over communication pair TR18 by line receiver 401 and applied over lead 403 to detector 408. This is the normal operable state of the system. If, for any reason, line receiver 401 fails to receive a data stream, detector 408 receives no clock pulses and sets lead 409 equal to a 1 to permit system processor 100 to read gate 424 and determine this condition. This condition could exist for example when the associated terminal equipment T11 is disconnected from communication pair TR11. _ _ - ' ' Lead 422 interconnects the lower input of AND gate 458 with control register 431. This path is normally held in an enabled state by control register. This enables gate 458 and permits the DR output of counter 421 to be extended over lead 406 to scan register gate 423. This DATA READY signal is used to advise system processor 100 that at least a single message is currently contained within receive FIFO 414. Address decoder 433 contains flip-flops so that when an address is applied to the I/O BUS together with appropriate control signal by system processor 100, these control signals latch the address into the decoder flip- flops. The output of these flip-flops extends to circuitry which decode the address and give output signals unique to each different address. One of these output signals extends to lead 459. This signal is active at the time that data appears on I/O BUS and is used to strobe the data into latches in control register 431. That data is retained because it is latched into control register 431. Control register 431 contains flip-flops which store the state of port circuit 111 as controlled by system processor 100, as subsequently described. Transmit message counter 438 functions similarly to receive message counter 421 to indicate whether FIFO 440 currently contains a complete message. Transmit message counter 438 is incremented over lead 436 when a message is entered into FIFO 440. Transmit message counter 438 is decremented over lead 441 when a message is read out of FIFO 440. The output of transmit formatter 445 extends over lead 456 to the frame multiplexer 449. Switch demultiplexer 448 receives PCM time slot signals on bus PCM, separates out the 11 and 12 field signals for use by port circuit 118 from their assigned time slots and applies them to leads 453 and 454. An output of transmit message counter 438 extends to transmit*formatter 445 on lead 439 which indicates when the contents of transmit message counter 438 is 0. This implies that no messages are contained in FIFO 440 and that transmit formatter 445 should generate flag characters. The 11 , 12 signals are received by frame multiplexer 449 together with the serialized S channel bits on lead 456. Once each frame, frame multiplexer 449 inserts the eight bit 11 field, the eight bit 12 field and the one bit S field into a framing signal and applies it over lead 452 to the line transmitter 450 which adds the F field bits. From there, resultant twenty bit frame of FIG. 8 is extended over communication pair TR18 to computer T18. Line transmitter 450 and frame multiplexer 449 operate under control of the output signals from clock generator 455. Switch demultiplexer.448 receives its control signals from bus PCM. General Purpose Communicatipn Interface - FIG. 2 The subject general purpose communication interface is connected to communication pair TR18 and functions to establish two communication paths between computer T18 and the telephone switching system. One of the communication paths is a voice communication channel which extends from a telephone handset 209 associated with computer T18 to the telephone switching network 101. The other communication path is a data communication channel which extends from computer T18 to system processor 100 via the S (control signalling) channel of the telephone switching system. These two communication paths are created by switching the two channels which are multiplexed on communication pair TR18 in the DCP format of FIG. 8: S (Control signalling) channel; I (information) channel which consists of two sub-channels - 11 for PCM encoded voice and 12 for data. The general purpose communication interface routes the 12 and S channel signals directly to computer T18 via a pair of RS232 connectors while the 11 channel signals are routed through CODEC 207 to a telephone handset 209 for voice communication. Thus, the general purpose communication interface is totally transparent to messages on the S channel. The general purpose communication interface simply provides computer T18 with direct access to system processor 100 via the S channel. General purpose communication interface (illustrated in FIG. 2) is a microprocessor controlled circuit which contains a number of interface and protocol conversion devices. Computer T18 generates ΞIA control, ASCII data and timing signals that are converted by protocol conversion circuit 202 from RS232 signal levels to 5 volt logic signal levels. Protocol conversion circuit 202 also converts the signals received from computer T18 to a format compatible with microprocessor 205. Protocol conversion circuits 202 and 204 are commercially available devices. These devices are designed to interface high speed communications lines, which carry signals having an IBM Bisync or HDLC protocol, to a microcomputer system such as microprocessor 205. The protocol conversion circuit (202 and 204) implements two independent serial receiver/transmitter channels to an attached device such as computer T18. The serial channels carry signals having a serial protocol (HDLC) and protocol conversion circuit 202 decodes the serial protocol and stores the message contained therein in a receive buffer (not shown). Microprocessor 205 periodically reads out the contents of the receive buffer and writes messages into a transmit buffer (not shown) in protocol conversion circuit 202 for conversion to HDLC protocol and transmission to computer T18 via the serial channels. These messages processed by microprocessor 205 are the one bit S channel and eight bit I channel messages discussed above. Similarly, protocol conversion circuit 204 interfaces with the communication pair TR18 via digital line interface circuit 203. Program instructions stored in memory 206 handle the HDLC protocol used on the S channel. In fact there are two control sub-channels on the S channel: one control sub-channel corresponding to each I channel. Microprocessor 205 maintains separate protocol state information for each of these S channels (S1, S2). Protocol conversion circuit 204 generates idle flags when no data is being received from computer T18. These idle flags are periodically read by digital line interface 203 and transmitted to switching network 101 via the I channel (port circuit 111, port data/control interface circuit 171). However, once computer T18 begins transmitting a data message, protocol conversion circuit 204 formats the received data message and stores it in eight bit increments in a data message memory (not shown) in protocol conversion circuit 204. Digital line interface 203 interconnects general purpose communication interface with port circuit 118 via communication leads TR18. Digital line interface 203 includes a control circuit (not shown) and a phase locked loop (not shown) which recover the clock signals from the message frames serially transmitted by port circuit 118 to general purpose communication interface via communication leads TR18. These recovered clock signals are used by digital line interface 203 to both receive message frames from port circuit 118 and generate message frames for serial transmission to port circuit 118. Digital line interface 203 reads out two eight bit bytes (11 and 12) at a time of the formatted data message from the data message memory of protocol conversion circuit 204. Similarly, digital line interface 203 reads one bit (S) at a time of the control message stored by microprocessor 205 in protocol conversion circuit 204. Digital line interface 203 combines the two eight bit data bytes (II and 12) with the one bit (S) control message to create the message frame of FIG. 8. The resultant message frame is transmitted in serial form by digital line interface 203 to port circuit 118 via communication leads TR18. Message frames transmitted to general purpose communication interface by port circuit 118 are received and decoded in reciprocal fashion by the general purpose communication interface. Digital line interface 203 receives message frames serially transmitted by port circuit 118 on communication leads TRV8. Digial line interface 203 stores the received 8 bit data bytes and control bit in protocol conversion circuit 204. Microprocessor 205 reads the received control message from protocol conversion circuit 204 in eight bit increments and interprets same. If the control message requires that computer T18 be signaled, microprocessor 205 loads the control message into protocol conversion circuit 202 so that the control message will be forwarded to computer T18. Protocol conversion circuit 202 reads the two eight bit data bytes from microprocessor 205 and transmits same to computer T18 via EIA interface 201. Protocol conversion circuit 202 calculates a CRC code on the received data message to insure accuracy of transmission. General Purpose Communication Interface Software - FIG. 3 The program instructions or software stored in memory 206 is illustrated in schematic form in FIG. 3. As shown in FIG. 3 (as boxes with round corners), there are 6 tasks performed by microprocessor 205: 1. the main routine (300), 2. the computer enqueue handler (301), 3. the computer dequeue handler (302), 4. the switch enqueue handler (303), 5. the switch dequeue handler (304), and 6. the timer (305). Also, as shown in the figure, there are the following data structures: 1. the S1 and S2 message queues (306, 307) for messages from system processor 100 to computer T18, 2. the TO-PC queue (308) for messages that are routed to computer T18, 3. the S1 and.S2 message queues (309, 310) for messages received from computer T18, 4. the TO-SWITCH message queue (311) for messages routed to system processor 100, 5. the protocol state information (312, 313) for the HDLC-like protocol on each of the S1 and S2 channels, and 6. a collection of templates (314) of all possible messages that can be sent to system processor 100. Each of the queue handler tasks and the timer task are implemented as interrupt handlers. The timer's (305) job is to decrement a counter for each of the S channels so the main routine can determine if there is a protocol timeout. The main routine (300) is an infinite loop that continuously checks for work to do. There is work to do if any of the queues that the main routine reads is non¬ empty. These queues are the S1 and S2 queues (309, 310) from computer T18 and the S1 and S2 queues (306, 307) from system processor 100 which contain messages that originated at computer T18 or at system processor 100, respectively. The job of the switch enqueue and dequeue tasks (303, 304) is to send and receive S channel messages to and from system processor 100. On receiving S channel message bytes from protocol converter 202, the dequeue task (303) interacts to determine when the end of the message arrives. The dequeue task (303) then reads the message itself to determine if the message arrived over the S1 channel or the S2 channel. At this point, the dequeue task (303) prepends the S channel number and the message size to the message. Additionally, microprocessor 205 adjusts the queue writer pointer to allow the main routine (300) to detect that a message is in the queue (306, 307). The main routine (300) detects that one of the switch input queues (306, 307) is non-empty. Certain messages are received from the switch exclusively to satisfy the protocol. Appropriate action is taken by the main routine (300) to maintain the protocol if the message is of this type. Other messages are information messages that should be interpreted by computer T18. In this case the main routine (300) will move this message to the TO-PC queue (308) and perform whatever is necessary to satisfy the HDLC-like protocol used on the particular S channel. Usually this means that an acknowledge message is sent back out to system processor 100 by stuffing a message template with the proper sequence numbers and enqueueing this in the TO-SWITCH queue (311), and then resetting the timeout counter. The PC enqueue task (301) will now enqueue the message and deliver it to computer T18 via protocol converter 202. The PC dequeue task (302) reads messages from computer T18 via the serial port (protocol converter 202) and dequeues them in much the same way as described earlier for the switch dequeue task (304). Note that in this case there are two formats: 1. a "real" S Channel message (S channel Message Format) which should go to system processor 100, and 2. a command to be interpreted by the general purpose communication interface. An example of the general purpose communication interface control message is to tell the general purpose communication interface to transmit a TOUCH-TONE signal on the voice path. This is the mechanism by which dialing is done for voice calls. If the message is interpreted as a command for the general purpose communication interface it is executed by microprocessor 205, otherwise the message is injected into the TO-SWITCH queue (311). The switch enqueue task (303) will then send it to system processor 100 over the DCP link (communication pair TR18). The main routine (300) also periodically checks the values of the S1 and S2 channel timeout counters, S1 STATE and S2 STATE (312, 313) to determine if there is a protocol timeout. If there is, appropriate action is taken. General purpose communication interface thereby implements a direct communication channel between computer T18 and system processor 100. The signalling protocol disparity between computer T18 and system processor 100 is handled by the selection of protocol conversion devices 202, 204 while the transfer of messages between protocol conversion devices 202, 204 is orchestrated by microprocessor ' 205 operating under control of program instructions stored in memory 206. Microprocessor 205 creates the necessary message queues and coordinates the operation of protocol conversion devices 202, 204. This- arrangement accomplishes the elimination of the existing barrier between customer provided computer facilities and the system processor of the telephone sv/itching system. While a specific embodiment of the invention has been disclosed, variations in structural detail, within the scope of the appended claims, are possible and are contemplated. There is no intention of limitation to what is contained in the abstract or the exact disclosure as herein presented. The above-described arrangements are only illustrative of the application of the principles of the invention. Normally, other arrangements may be devised by those skilled in the art without departing from the spirit and the scope of the invention.

Claims: Claims 1. A system processor interface arrangement in a switching system which serves a plurality of terminal equipment, each of which is connected by an associated port circuit to a switching network of the switching system, which switching network establishes network connections among the terminal equipment by interconnecting the associated port circuits, comprising: a system processor (100) for controlling the operation of the switching system; a control signalling circuit (171) connected to and interconnecting the system processor (100) and the port circuits (111, 118) for exchanging control signals therebetween; CHARACTERIZED IN THAT the system processor interface arrangement (DT18) connected to one of the port circuits (118) for providing direct signalling access to the system processor (100) via the control signalling circuit (171) of the one port circuit (118) . 2. A system processing interface arrangement in a switching system which serves a plurality of terminal equipment, each of which is connected by an associated port circuit to a switching network of the switching system, which switching network establishes network connections among the terminal equipment by interconnecting the associated port circuits, comprising: a system processor (100) for controlling the operation of the switching system; a control signalling circuit (171) connected to and interconnecting the system processor (100) and the port circuits (111, 118) for exchanging control signals therebetween; the system processor interface arrangement (DT18) connected to one of the port circuits (118) for providing direct access to both the system processor (100) via the control signalling circuit (171) of the one port circuit and the switching network (101) via the one port circuit (118). 3. The system processor interface arrangement of claims 1 or 2 CHARACTERIZED IN THAT the system processor interface arrangement (DT18) is connected to a computer facility and comprises: means responsive to signals output by the computer facility for generating messages containing the signals; a data line interface (203) connected to both the generating means and the control signalling circuit (171) for transmitting the messages to the system processor (100) via the control signalling means circuit (171). 4. The system processor interface arrangement of claim 3 CHARACTERIZED IN THAT the data line interface (203) includes: a switch protocol conversion circuit for translating the signalling protocol of the messages to the protocol required by the control signalling means (171). 5. The system processor interface arrangement of claim 3 CHARACTERIZED IN THAT the generating means includes: a memory (206) for storing a set of predefined messages for transmission to the system processor (100); a processor (205) responsive to the signals for selecting one of the predefined messages to reflect the information content of the signals.

Inventors: CHAN NORMAN CHIN-HUNG, PEDERSON LEIF KENNETH, CHAN, NORMAN, CHIN-HUNG, PEDERSON, LEIF, KENNETH
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1985
Main classification: H04Q11
IPC codes: H04M3, H04Q3, H04Q11