METHOD FOR PRODUCING A DMOS SEMICONDUCTOR DEVICE

Abstract: An improved method for the fabrication of a DMOS tran­ sistor. The method comprises forming the source region of the transistor by introducing doping from a doped, thin po­ lycrystalline layer. A thin insulating layer is used to protect the body channel contact region, from the source doping, and the thin polycrystalline layer is completely consumed and converted into an insulator by oxidation subsequent to the source doping step.

Description: This invention relates generally to an improved method for fabricating double-diffused MOS (DMOS) transistors and, more particularly, to an improved method of fabricating DMOS power transistors that can be used either in a discrete or an integrated structure or format. In the past, DMOS transistors have been utilized either as discrete power transistors or as components in monolithic integrated circuits. DMOS transistors are inherently conservative of semiconductor substrate area because of the manner in which they are fabricated in a self-aligned fabrication sequence. A channel body region was usually first formed by dopant introduction of one type dopant (P or N impurities) through an aperture in a mask of gate-forming material to provide a channel region which was self-aligned with the gate. Then a source region Was usually formed by dopant introduction of a type opposite to that of the channel body region through the existing aperture so that the source was self aligned to both the gate electrode and the channel body region. This permitted a very compact structure that utilized very little semiconductor substrate area. However, in most applications of the DMOS device, particularly for power devices, it is necessary to form a very low resistance electrical short between the channel body region and the source region to prevent undesired parasitic transistor action that might occur without shorting the channel body region to the source region. Because the channel body region is lightly doped, and because a low resistance electrical contact to a semiconductor region typically requires a heavily-doped surface region, it is necessary to provide an auxiliary heavily doped contact region for the channel body region to insure a good electrical contact to both the source and body regions. Such a heavily doped body region usually could not be self-aligned and hence there was an increase in the overall size of the DMOS device. Typically, the heavily doped body contact region was usually formed before the other two regions. Then a rather thick masking oxide patterned layer was used to protect the heavily doped body contact region against the source region dopant introduction step. The necessity to etch away or remove this masking oxide patterned layer together with any oxide over the source regions without disturbing the insulator over and/or under the gate electrode increased costs, tolerances, and process complexity and, as a result, decreased the yields of electrically good devices. While various processes have been utilized in an attempt to ameliorate the foregoing problem, a need existed to provide an improved DMOS fabrication method and process sequence Which allows an effective source to channel body electrical short without decreasing yield and which permits or is susceptible to device dimensional reduction. A further DMOS integrated circuit and its manufacturing process is disclosed by EP-A-022 388. The known integrated circuit includes a plurality of highly integrated DMOS transistor fingers with high channel density, with each transistor having a P-type channel region and a respective N-type source. However, the known DMOS manufacturing process, according to EP-A-022 388, fails to provide for a sufficiently low resistance path between the transistor source and channel regions. The article "Source and Drain Junctions by Oxidizing Arsenic Doped Polysilicon" by Kingsborn et. al, published in INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 1983, PAPER 29.6, p.674-676, discloses a process for producing IGFETS with a very shallow junction, a gate offset oxide and reduced gate S/D overlap, with the process including the steps of providing an arsenic doped polysilicon layer and oxidizing the polysilicon layer during the formation of source regions. However, said article also fails to provide for a low resistance path between the IGFETS source and channel regions. In view of the foregoing the task of this invention is to provide an improved process for the fabrication of a DMOS transistor. Within said task it is an object of this invention to provide an improved fabrication method for a DMOS transistor which results in a smaller device and a higher yield of good devices. It is another object of this invention to provide an improved DMOS fabrication method or process sequence which facilitates the provision of an electrical short between the body channel region and the source regions of the DMOS transistor. It is yet another object of this invention to provide an improved method for fabricating power DMOS transistors. It is still a further object of this invention to provide an improved process for fabricating DMOS transistors in integrated circuits. Foregoing task, as well as these and other objects which will become apparent hereinafter, are achieved by a process for manufacturing DMOS transistors as defined in the accompanying claims. In accordance with a preferred embodiment of this invention, a method for the fabrication of a DMOS transistor is disclosed wherein the DMOS transistor comprises a body channel region and at least one source region located in a substrate. The method comprises doping and forming the source regions of the DMOS transistor from a doped polycrystalline layer deposited on the substrate. The source regions of the DMOS transistor are formed by, for example, an arsenic doped polycrystalline silicon layer which is then thermally oxidized to leave a thin oxide over the source regions of the DMOS transistor device. By using the polycrystalline layer as a doping source, only a very thin oxide is required to mask protect the body channel contact region from the effects of the source region doping and drive in diffusion step. The thin oxide remaining over both the source regions and the body channel contact region is removed in a metal deposition operation to electrically short together the source regions and the body channel contact region without impairing the integrity of the insulator over or under the gate electrode and without the need or use of large tolerances for the formation of the various regions. In accordance with another embodiment of this invention, a method is disclosed for the fabrication of a DMOS transistor in a semiconductor substrate. The DMOS transistor comprises a body channel region, a body channel contact region, at least one source region, a gate electrode, and a gate insulator. The fabrication method comprises the steps of forming the body channel contact region, forming the body channel region, protecting at least a portion of the body channel region with an insulator, depositing a thin layer of doped polycrystalline silicon to contact at least a portion of the body channel contact region that is unprotected by the insulator, and forming the source region by doping from the doped polycrystalline silicon. The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawing. Figures 1a, b, c, d, e and f depict cross-sectional views of the DMOS device of this invention at six different stages of the fabrication process in order to illustrate the improved method of this invention. Referring now to Figure 1a, a cross-sectional view of a semiconductor substrate suitable for the fabrication of an improved DMOS transistor device according to the improved method of the present invention is shown. An epitaxial layer 3 of N-type material deposited on a heavily-doped N⁺ substrate 2 is illustrative of a starting point of the improved process. Alternatively, the N-region 3 could be an isolated (PN junction isolated or dielectric isolated) tub region in an integrated circuit substrate according to well-known conventional isolation type processes. At least one (and preferably two or more) P+ regions 4 are formed in the surface of the N-type region 3 by, for example, conventional photolithographic masking, etching and diffusion techniques using a P type dopant source such as Boron. If desired, ion implantation techniques can be used to form the P+ regions 4 and the number of the P+ regions 4 would depend on whether a discrete DMOS device was being formed or Whether one or more DMOS devices were being used in an integrated circuit configuration. The one or more so formed surface regions 4 of heavily-doped P+ type semiconductor material Will eventually form the high conductivity or low resistivity contact regions for the body channel of the completed DMOS device. Then a layer 12 of oxide (silicondioxide) is preferably thermally grown or deposited over the surface of the substrate including the one or more P+ regions 4. This oxide will preferably and subsequently serve as the gate insulator of the completed DMOS device. Then a layer of, for example, 500 nanometers (5,000 Angstrom) of polycrystalline silicon is deposited on the insulating layer 12 and patterned, preferably by conventional photolithographic masking and etching techniques, leaving one or more conductive gate electrode regions 20 with each gate electrode region 20 serving as the gate electrode for a completed DMOS device. The polycrystalline silicon is preferably doped with, for example, phosphorous after the polycrystalline silicon deposition step in order to render it electrically conductive and thereby provide the one or more gate electrodes 20. The insulating layer 12 typically has a thickness in the range of 50 to 150 nanometers (500 Angstrom to 1500 Angstrom) and preferably has a thickness of about 85 nanometers (850 Angstroms). Referring next to Figure 1b, an additional P type doping is introduced through the apertures formed by the doped polysilicon regions 20. A suitable P type dopant, such as Boron, is most conveniently and accurately introduced by ion implantation through the thin insulating layer 12. The doping thus introduced along with the doping in the heavy P⁺ type regions 4 previously introduced are then driven into the substrate at high temperature in order to form P type body channel regions 6 and the much higher P⁺ doped channel body contact regions 4A, respectively. Because of lateral diffusion during the drive in diffusion operation, it should be noted that the more lightly doped P regions 6 extend outwardly (under the oxide portion that is under the doped polysilicon gate electrode 20) beyond the more heavily doped P⁺ regions thereby providing optimum channel regions for the N channel DMOS device that is formed by the process of this invention. Proceeding now to Figure 1c, portions of the gate insulating oxide layer 12 have been removed by conventional photolithographic masking and etching techniques to expose portions of the P type regions 4A and 6. The portions of the insulating layer 12 remaining over the P⁺ body channel contact regions 4A serve to mask or protect these regions from the subsequent doping step depicted in the following Figures 1d and 1e. Referring now to Figure 1d, a thin layer of polycrystalline silicon 30 has been deposited over all portions of the surface of the semiconductor substrate. The thickness of this thin polycrystalline silicon film is preferably about 30 nanometers (or 300 Angstrom), and it is doped with an N type impurity such as, preferably, arsenic during the polycrystalline silicon deposition step. Arsenic is a preferred N type dopant because it will produce shallower N⁺ source regions 8 because of its slower diffusion rate than, for example, phosphorous and will also permit the use of a thin masking oxide for the formation of the arsenic doped N⁺ source regions 8. The N type dopant serves to provide the N⁺ source regions 8 as shown in Figure 1e after exposure to high temperature during a diffusion drive-in cycle. During the course of this diffusion drive-in heat treatment, the arsenic in the arsenic doped, thin polycrystalline silicon film or layer 30 is transferred or conveyed into the N⁺ source region 8. An oxidizing operation is carried out or introduced during this drive-in diffusion step to convert the polysilicon layer 30 to an insulator layer 14 of oxide (silicon dioxide) covering all the conductive or semiconductor regions of the device including the gate electrodes or regions 20. Thus, not only have the heavily-doped N⁺ source regions 8 been formed, but these N⁺ regions 8 and the P⁺ body channel contact regions 4A are both overlain with nearly the same thickness of the thin thermal oxide insulator layer 14 over the N⁺ regions 8 and the P⁺ regions 4A which facilitates the subsequent contact opening for metal contact deposition and formation. Referring now to Figure 1f, a layer 18 of deposited (and patterned by photolithographic masking and etching techniques) oxide (preferably, a phosphorous doped vapox) is used to augment the thin thermally grown oxide layer 14 in order to more completely insulate and protect the gate electrode regions 20. This layer 18 of deposited oxide is preferably lightly-doped with phosphorus in order to enhance its insulating and passivating functions. Apertures have been formed, etched or cut through both of the oxide layers 14 and 18 to expose portions of the N⁺ source regions 8 and the P⁺ body channel contact regions 4A at the surface of the semiconductor substrate. Then, a layer 40 of a suitable, electrically conductive material such as aluminum or an aluminum alloy is deposited over the entire structure and patterned (not shown) to delineate individual DMOS devices for an integrated circuit application. This conductive layer serves to make electrical contact to the N⁺ source regions 8 of the DMOS device as well as to provide a desirably low resistance, electrical shorting contact between the heavily doped N⁺ source regions 8 and the heavily doped P⁺ body channel contact region 4A. The N-region 3 together with the underlying N+ region 2 provide the drain regions for the DMOS device and an electrical contact to the N-region 3 (not shown) is either provided by providing an ohmic contact to a surface portion of this N-region 3 or, if the DMOS device is used as a discrete DMOS power device, by providing an ohmic electrical contact to the backside of the N⁺ region 2. The conductivity types shown in the preferred embodiment may be reversed thus providing a P channel DMOS device. The starting point is a substrate or substrate portion of a first conductivity type, followed by the introduction of body channel and body channel contact regions of a second conductivity type opposite to the first conductivity type, and culminated by the introduction of source regions of the first conductivity type from a doped polycrystalline silicon source (doped with impurities of said first conductivity type) which is subsequently oxidized. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included just for the sole purpose of increasing intelligibility of the claims and accordingly, such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: A method of manufacturing a DMOS transistor comprising a lightly doped channel region (6) and a heavily doped channel contact region (4A) of a first conductivity type and at least one source region (8) located in a semiconductor substrate (2) of a second conductivity type, said method comprising the steps of: forming said channel contact region (4A) and channel region (6) extending beyond said channel contact region (4A) in a major surface of said semiconductor substrate (2); protecting at least a portion of said channel contact region (4A) and a portion of said channel region (6) by depositing a protective insulating layer (12) on the surface of said substrate (2) to define a surface region of said channel contact region (4A) and the channel of said DMOS transistor respectively; depositing a thin layer (30) of doped polycrystalline silicon to contact at least a further portion of said channel contact region (4A) adjacent to said channel region (6) that is unprotected by said protective insulating layer (12), said thin layer (30) of polycrystalline silicon being doped with impurities of said second conductivity type; forming said source region (8) by doping from said polycrystalline layer (30) at said further portion of said channel contact region (4A) that is unprotected, and simultaneously completely oxidizing said polycrystalline layer (30); removing portions of said oxidized layer to expose portions of said source region (8) and said channel contact region (4A); and depositing an electrically conductive material (40) on said exposed portions of said source region (8) and said channel contact region (4A), to form a very low resistance electrical connection between said channel contact region (4A) and said source region (8). A method according to claim 1, characterized in that said thin layer (30) of doped polycrystalline silicon is deposited so as to contact at least a further portion of said channel region (6) that is unprotected by said protective insulating layer (12), and in that said source region (8) is formed at said further portion of said channel region (6). A method according to one or more of the preceding claims, characterized in that said protective insulating layer (12) comprises a gate insulator. A method according to one or more of the preceding claims, characterized in that said step of providing said protective insulating layer (12) comprises the step of forming a silicon dioxide layer followed by the step of forming openings in said silicon dioxide layer. A method according to one or more of the preceding claims, characterized in that said thin layer (30) of polycrystalline silicon is doped with arsenic, said source region (8) being of N type conductivity, and said DMOS transistor being an N channel DMOS transistor. A method according to one or more of the preceding claims, characterized in that said step of forming said channel region (6) comprises ion implantation through a gate insulating region (20). A method according to claim 6, characterized in that said step of protecting a portion of said channel region (6) comprises leaving a portion of said gate insulating region (20) over said channel contact region (4A).

Inventors: CONTIERO, CLAUDIO
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1985
Main classification: H01L21
IPC codes: H01L21, H01L29