DATA PROCESSING APPARATUS WITH FIXED ADDRESS SPACE AND VARIABLE MEMORY

Abstract: A CPU initialises pluggable adapters with built-in iden­ tity and conditional ROS and compiles an HFLIH table of identity against status register address and an SFLIH table of identity against on-board system function. It stores the tables with a control module in enabled memory on the keyboard adapter. Conditional ROS is enabled on any adap­ ter receiving a broadcast of its own identity. Adapter inter­ rupts are ORed. HFLIH is stepped through by the control module to access adapter status sequentially, servicing each adapter in turn from its ROS, using its broadcast iden­ tity. System functions are accessed via SFLIH.

Description: This invention relates to data processing apparatus with fixed address space and variable memory and is directed primarily to improving the accommodating of variable amounts of memory resident on pluggable devices potentially exceeding the available memory address space of the system. During the power on sequence of various personal computers and intelligent work stations, a range of code residing in Read Only Storage (ROS) is automatically executed. This code initialises the system such that the hardware is tested, put into a known state, and system parameters are defined. As part of this sequence, a number of hardware adapters must be initialised. Typically, each adapter has its own ROS associated with it and the base ROS (on the system board) implements a well defined algorithm to identify these adapter ROS modules and execute them. Each adapter then requires a certain range of address space with the systems memory map. As more and more adapters are integrated into the system, more and more system memory address space is consumed. Since memory address space is a finite resource, the administration of address space becomes a difficult problem. Additionally, many adapters' ROS modules must provide code to service hardware interrupts associated with the device. This does two things: 1. Places a greater demand on limited address space. 2. Requires a solution to the address space problem to allow continued support of an interrupt handler scheme. Techniques are known in the prior art for maximising use of system address space by eliminating gaps between volumes requisitioned by devices. In a system described in U. S. Patent 4,025,903, memory is provided as pluggable modules with self-adjusting addressing by communication amongst themselves. The size of the address space required by each individual module is permanently stored in the module and is used to calculate, internally of each module, the memory addresses of the module (i.e., the device) based on an address communicated by the next lower module. While such systems eliminate waste in address space assignment, the address space required is still the aggregate of the individual device requirements and may exceed the address space available. In the prior art, limitation of address space has been relieved by memory address expansion schemes. For example, in some systems, data is placed in one address volume and commands in another. In other systems, high order bits of each address are used to point to registers in a matrix which supply a larger number of bits which replace those high order bits so as to create an address space of increased size. Such prior art schemes, while useful in individual employments, carry with them system architecture requirements which cannot be satisfied by simple modification of systems designed for a single, fixed size address scheme. IBM Technical Disclosure Bulletin, Vol 21, p 34 (1978) describes a memory expansion system wherein added storage units are identified by a device identification number. It is also known to provide add-on feature units having a numerical rank in which they are serviced. For example, features added to a system may share a common attention line, and when a general poll is passed to the features, the identity of the lowest numbered feature requiring service is returned in terms of its number. From one aspect the present invention provides a data processing system comprising a central processor, addressing means defining a finite memory address space, and a plurality of modules connectable into one common segment of said address space for access by said central processor, each of said modules having address decoding means responsive to addresses in said common segment of said address space, at least one of said addresses being decodable by said decoding means of more than one of said modules, each of said modules having an identification indicium which is different from that of any of the other of said plurality of modules said decoding means of which is responsive to a same address, each of said modules having an identifier register writable by said processor for receiving identifier data broadcast to all of said plurality of modules by said central processor, and each of said modules having comparison means sensitive to the contents of its said identifier register and operative upon and during a predetermined relationship of the contents of said register to the indicium of the module to enable that module to respond to a predetermined set of addresses comprising said one common segment so long as that module is enabled and to the exclusion of all other modules of said plurality of modules having a different identification indicium. A conventional data processing system of the kind which corresponds to the kind of data processing system provided by the present invention can be said to include a central processor connected to a large but fixed number of ports to any or all of which may be attached devices, whether directly or by way of adapter, such devices including memory and/or function and in-built identity. The central processor defines a fixed size address space onto which is mapped, in an individual window, the memory or function of each valid attached device. The current status of each attached device is maintained in a register or latch, on or off the device, the status location being accessed by an address which does not occupy a position in the fixed size address space defined by the processor. For those operations which may be invoked in relation to a set of such devices; access is made sequentially to each appropriate window. In the arrangement of the present invention, on initialisation of the system, each port is tested in turn, and, if a device is attached thereto, that device is tested and initialised. If this process is successful, the identity of that device is added to one or other of a pair of tables or logs, build up this way during initialisation, for that set of devices.s One log associates the device identity with the status address for that device and the other log associates the device identity with the function provided by that device. In operation, when an operation is invoked in relation to that set of devices, by use of one or other of the logs built up during initialisation, the interested and only the interested devices of the set, by definition, installed and valid, appear to the central processor as a single device occupying a single window in the fixed size address space. The central processor accesses a default location in the address space for the set and is directed to the logs. If a function is required, it will be passed to a given area of an identified device using the function/identity log. If a service operation is required, the other log is used to examine the status of each device in turn, the processor passing to the next device if the perceived status is not appropriate to the operation. Otherwise, the stored identity is used to access the memory on the device even though the processor uses the window of the fixed size address space assigned to the function above referred to. The identity is, in either case, broadcast to all devices, only that device that has that identity built into it, being enabled. Thus, with the arrangement of the present invention, only one window in the fixed address space is required to service all the attached devices belonging to the set, together with a single default address, rather than requiring a default address and a window per device. This can be regarded as a memory expansion mechanism, a memory mapping mechanism or a memory paging mechanism but is, in reality, the reverse of a virtual device mechanism. The present invention will be described further by way of example with reference to embodiments thereof as illustrated in the accompanying drawings in which: Fig. 1 is a diagram of one form of apparatus of the invention; Fig. 2 shows an individual pluggable device of the apparatus of Fig. 1; Fig. 3 is a diagram illustrating the organisation of the memory address space of the system of Fig. 1, as employed in servicing a software interrupt, together with a table (1.1.2.3) of software intervention vectors utilised by the system; Fig. 4 is a diagram illustrating the handling of a hardware interrupt in accordance with the invention, together with a system configuration table utilised in the control of the system; and Fig. 5 is a diagram illustrating the accessing of the tables shown in Figs. 3 and 4 when the tables are themselves resident on a pluggable adapter unit. In accordance with the one embodiment of the present invention, a distributed ROS scheme requires each adapter card in the computer system to support its own ROS module. These adapters or modules all share the same address space, e.g., 4K bytes at CB000x. In order to guarantee that addressing capability within any one of these modules is active at one time, each adapter is characterised by three things: 1. Supports a select register resident in or architectually associated with the adapter at a common I/O address. 2. Is assigned a unique identification number. 3. Supports logic such that when the select register is written with a data value, the logic enables addressing capability within the adapter's ROS module only if the data value matches the adapters assigned unique identifier (I.D.). If the data value does not match the assigned I.D., the addressing capability of that adapter is disabled. The system software supports the above hardware selection mechanism by providing a Distributed ROS nucleus. This nucleus is invoked by the base system ROS through that ROS's well defined algorithm. This occurs at system initialisation. At system initialisation the Distributed ROS nucleus pages in all ROS modules, validates them, and allows their adapter initialisation code and adapter diagnostic code to execute. If the adapter requires interrupt handler services during normal system operation, and it provides interrupt handling code within its ROS module, the nucleus code will add this adapter's information to an adapter configuration table which is used to support interrupt handler services during normal operation. This scheme is possible because each Distributed ROS module is required to support a well-defined protocol, e.g., in the leading bytes of the module. This protocol identifies the module as valid; identifies whether or not an interrupt service routine is present and whether interrupt services are required during normal operation; and provides other miscellaneous information. During normal processing, interrupts occur at which time an adapter may require interrupt servicing. In accordance with other aspects of the invention, on hardware interrupts, a Distributed ROS nucleus module receives control. This module polls status registers on board the adapter units and accessible via system register addresses found in an adapter configuration table which was constructed from the protocol information found in each Distributed ROS module. Upon detecting an interrupting device, this nucleus module pages in the current ROS module (by use of the unique identification number found in the adapter configuration table) and jumps to a fixed point within that adapter's ROS module where an interrupt service routine exists. This allows effective sharing of interrupt levels and continues to support interrupt service requirements placed on a ROS scheme. Thus this Distributed ROS scheme solves the address problem by sharing the same address space among several adapters. It manages this address space through a hardware paging technique under software control. It continues to support interrupt servicing requirements thereby meeting all requirements placed on the scheme. A plurality of code modules are individually connectable into a processor system at the same address space of the system, by operation of address decoding means in each module responsive to addresses in said segment but normally disabled, said decoding means of each module being uniquely enableable by a signal broadcast to all of said modules but identifying only one. The system includes a table identifying the modules attached to the system and a pointer to the operative status of each, and means responsive to the table contents to formulate enabling signals to be broadcast, one at a time, to the modules. Such an arrangement provides in an architecture as aforesaid, for modules of code corresponding to optional features to share memory space in a manner suited to the basic organisation of the system. Alternatively, it could be said to provide an improved method and means to support the dynamic integration of hardware adapters into a computer system (including the testing, initialisation and servicing of such adapters) through a software controlled hardware paging technique. For the purposes of detailing one embodiment of the present invention, modification of a known processor having a fixed address space and a separate register address space has been assumed. Fig. 1 illustrates only those features of that processor, an IBM (IBM is a registered trademark) Personal Computer/XT which is germane to the present invention. This processor has a central processing unit (CPU) 10 communicating with three separate bus structures, a data bus 12, an address bus 14, and a control bus 16. These three structures interconnect the CPU 10 with, inter alia, main memory 18 and eight sockets 20, sometimes called "slots" but referred to herein as "ports". Various modules are provided in the form of printed circuit cards which can be plugged into the sockets, at the will of the user, to form a variable part of the processor. Clearly, being physically pluggable is not sufficient. Modules which can form part of a processor must be logically compatible and form a group of modules from which a current selection can be made. Fig. 2 represents, schematically, features of a pluggable module in accordance with the invention. The module comprises a card element 22 having a plug portion 24 including contact areas 26, 28, 30 which make contact with corresponding conductors in any one of the sockets 20 when the card 22 is plugged into it. The module carries read only storage (ROS) 32, and function circuits 34 which are accessible via a decode mechanism 36 which, however, is normally disabled and remains so until enabled by a signal on line 38 raised by an ID compare circuit 40. The ID compare circuit 40 is activated by and during the presence of an ID value in register 42 if that value matches the ID permanently "burnt in" the card. The ID number is one which has been broadcast to all cards in sockets 20 and is recorded in a register 42 which constitutes part of the I/O register set of the system and has an address which is the same for all of the cards 22. The register 42 is written with data received on the data bus 44 of the card as a step in the module addressing in accordance with the invention. As set forth in the summary of invention, during system initialisation, the presence of cards in sockets is detected and tables are created of the identification numbers (IDs) of the cards which populate the sockets, the individual address of the status register of each card, and the function, if any, carried on the card. This information is organised into two tables, the software first level interrupt handler table (SFLIH), and the hardware first level interrupt handler table (HFLIH), each accessible through a control component or nucleus having an address indicated at 50 in the overall address space 52 of the system. In the software interrupt handling procedure illustrated by Fig. 3, a function vector in address area 54 is utilised to examine the SFLIH table via an address in segment 50, whereby the system can determine the ID which is unique to the function desired. This ID is then broadcast to all cards plugged into the sockets 20 and is received in a register in each of them but compares to the ID in only one of them. In that one card, the resulting successful comparison enables the address decoding mechanism of the card. Thereafter, the card can be communicated with by addresses of a fixed window space 56 in the address space 52 scheme of the system. All cards installed in the sockets 20 share this same address space window, but the address decoder of only one of them is enabled and therefore operations can proceed with that one as if it were installed at window 58 of the address space. In the case of the handling of hardware interrupt vectors, more steps are needed since the activity was not system initiated and therefore the system must first determine which card or module requires service. When a module acts, via the interrupt handler of the system (not shown) to request service, an interrupt vector points to a routine in the control component as indicated at 70, whereupon the HFLIH table is consulted to test the status of each card having an ID posted in the HFLIH table. The HFLIH contains the status register address of each device which provides memory. The control component causes the status registers so identified to be accessed, one at a time. Whenever a status is encountered which indicates that service is required, the control component broadcasts the ID associated, in the HFLIH, with the register address currently being used. The result is that the memory on the device providing that status is enabled, causing a service cycle to be initiated in the usual fashion but utilising the common address window 56 as the address space for that card. If, on the other hand, the status register of the addressed card does not indicate need for service, the next card in the HFLIH table is interrogated in the same manner. It is convenient, and a feature of the invention, to locate the HFLIH and SFLIH tables in RAM on a pluggable card 22T. Fig. 5 is a schematic representation of such an arrangement. In that figure, a hardware or software vector initiated action, indicated at 80, is in fact transferred via the control module or component 50 to the card 22T, as indicated at 82, which card is accessed and is preferably the keyboard attachment card as this is presumed attached in all workable configurations.

Claims: A data processing system comprising a central processor, addressing means defining a finite memory address space, and a plurality of modules connectable into one common segment of said address space for access by said central processor, each of said modules having address decoding means responsive to addresses in said common segment of said address space, at least one of said addresses being decodable by said decoding means of more than one of said modules, each of said modules having an identification indicium which is different from that of any of the other of said plurality of modules said decoding means of which is responsive to a same address, each of said modules having an identifier register writable by said processor for receiving identifier data broadcast to all of said plurality of modules by said central processor, and each of said modules having comparison means sensitive to the contents of its said identifier register and operative upon and during a predetermined relationship of the contents of said register to the indicium of the module to enable that module to respond to a predetermined set of addresses comprising said one common segment so long as that module is enabled and to the exclusion of all other modules of said plurality of modules having a different identification indicium. Data processing system as claimed in claim 1 comprising means for storing a first table associating the identification indicium of each attached memory including module with the register address of the status register of that device, the central processor being arranged to respond to a request for service by accessing the first table and broadcasting the identification indicium of the device requesting service followed by one or more memory addresses. Data processing system as claimed in claim 1 or claim 2 wherein at least one of the attached memory including modules has stored therein, routines defining system functions, the system including means for storing a second table associating the identification indicium of each system function providing device with the system function provided, the central processor obtaining any one of the system functions included in the second table by accessing the second table by system function and broadcasting the associated device identity followed by one or more memory addresses. Data processing system as claimed in claim 2 or claim 3 including an initialisation facility for, on power up and system reset, initialising and determining the nature and location of the currently attached modules, the initialisation facility including means for generating the first table and/or the second table. Data processing system as claimed in claim 4 wherein the initialising facility is arranged to retain the generated table or tables in writeable memory on one of the attached modules. Data processing system as claimed in claim 4 or claim 5 wherein the establishing of the tables and/or the selective enabling of module memory are themselves system functions resident on one attached module. Data processing system as claimed in claim 6 wherein the device on which the system functions of establishing the tables and/or the selective enabling of module memory are resident is the keyboard.

Inventors: HARTER, RONALD SCOTT, LUCASH, JEFFREY STUART, MAJOR, ROBERT JAMES
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1985
Main classification: G06F12
IPC codes: G06F13, G06F12