High to low transition speed up circuit for TTL-type gates

Abstract: The specification discloses an input transistor (14) which is variable between high and low impedance states in response to input voltage transitions at terminal 10. An output transistor (16) is coupled to the input transistor (14) and is responsive to an input transition at terminal 10 for changing impedance states. Circuitry including a speed up transistor (44) is coupled between the input transistor (14) and output transistor (16) for applying added current to the output transistor (16) to speed the change of impedance state. The circuitry applies added current to output transistor (16) until the output voltage at terminal (18) falls below twice the base-emitter voltage of the output transistor (16).

Description: TECHNICAL FIELD OF THE INVENTION This invention relates to a transition speed up circuit. This circuit can be used for increasing the speed of output transition of TTL-type gates. BACKGROUND OF THE INVENTION Many circuits are commonly used for electronic devices wherein it is important that a rapid transition be made from one voltage level to another. Such a typical output circuit for a TTL gate might normally have a low voltage level input and a high voltage output. If a high voltage input occurs, it is important that the output circuit provides a very fast transition to a low output. It is also important that such output circuits be able to drive high capacitive loads and that a high impedance tri-state output also be provided. Previously developed output circuits for TTL gates have been developed with "speed up" elements which apply extra speed up current to an output transistor during output transition. An example of such a circuit is shown in "IBM Technical Disclosure Bulletin, vol. 8, No. 2, July 1965, pages 317, 318 - L.W. Atwood, "Logic circuit". However, such prior speed up circuits do not apply speed up current for a sufficiently long time or a sufficiently high magnitude, and also such previously developed speed up circuits often cannot be used as a high impedance tri-state circuit. From JP-A-59-122125 a TTL-logical output circuit is known, having a phase splitter configuration and a speed up circuit for the pull down transistor, the speed up circuit comprising a second phase splitter transistor that is in a configuration similar to Figure 1 of the present application. This known circuit has the same disadvantage as the prior art circuit according to Figure 1, namely because the speed up current is not applied long enough to the output transistor. SUMMARY OF THE INVENTION In accordance with the present invention, the transition speed up circuit having the features of claim 1 has been developed which substantially eliminates or minimizes the problems associated with previously developed output speed up circuits. The present speed up circuit includes an input transistor which is variable between high and low impedance states in response to input voltage transitions. An output transistor is coupled to the input transistor and is responsive to an input voltage transition applied to the input transistor for changing impedance states. Circuitry is coupled between the input and output transistors for applying added current to the output transistor to speed up the change of impedance state. The circuitry applies added current until the output voltage across the output transistor falls below twice the base-emitter voltage of the output transistor. The circuit may also be connected to provide a high impedance tri-state output. Preferred embodiments of the speed up circuit according to the invention are defined in the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS For a more detailed explanation of the present invention and for other objects and advantages thereof, reference is now made to the following drawings, taken in conjunction with the accompanying description: FIGURE 1 illustrates the circuitry of a prior art speed up circuit for use with a TTL gate; FIGURE 2 is a schematic circuit of the preferred embodiment of the present improved speed up circuit; and FIGURE 3 is a modification of the speed up circuitry shown in FIGURE 2. DETAILED DESCRIPTION OF THE INVENTION FIGURE 1 is a schematic diagram of a prior art speed up circuit. A high or low input voltage at input terminal 10 is applied through a diode 12 to the base of a Schottky clamped input transistor 14. As is known, a Schottky clamped transistor comprises a Schottky diode connected across the base and collector of the transistor. The emitter of input transistor 14 is applied to the base of a Schottky clamped output transistor 16. The collector of transistor 16 is connected to an output terminal 18 to provide a desired output voltage to TTL circuitry. A speed up Schottky diode 20 is connected across the collectors of input transistor 14 and output transistor 16. Diode 20 provides additional or speed up current to the base of the output transistor 16 through transistor 14 during turn on, to cause transistor 16 to become conductive more rapidly in response to voltage transitions received at input voltage terminal 10. An active turn off Schottky clamped transistor 22 may be connected through resistors 24 and 26 to the base of transistor 16. Also, as part of a typical circuit, a Darlington pair transistor configuration is provided which includes a transistor 28 connected at its emitter to the output terminal 18 and a Schottky clamped transistor 30 connected across the base and collector of transistor 28. Resistors 32, 34, 36 and 38 provide necessary biasing and current control to the transistors of the circuit. In operation of the prior act circuit of FIGURE 1, assume that the input voltage applied to terminal 10 is low and the output voltage at terminal 18 is high. Transistors 14, 16 and 22 are nonconductive. When the input voltage applied to terminal 10 transitions to a high state, the transistor 14, which also acts as a phase splitter, becomes conductive and applies current from its emitter to the base of the output transistor 16. In addition, speed up base current is applied to transistor 16 through transistor 14 from diode 20 which also begins conduction. In response to the base current, the output transistor 16 begins to conduct, and the output voltage at terminal 18 begins to drop until finally diode 20 stops conduction. This reduces the additional speed up current applied to the base of transistor 16. At this point, the only source of turn on current being applied to output transistor 16 is through the resistors 32 and 34 and transistor 14. It may be shown that diode 20 terminates conduction when the output voltage at terminal 18 equals the base emitter voltage of output transistor 16 plus the on voltage of input transistor 14 plus the diode voltage of diode 20. Since the on voltage of input transistor 14 approximately equals a transistor base-emitter voltage minus a Schottky diode voltage drop, then the output voltage for turning diode 20 off may be shown to be approximately twice the base-emitter voltage of the output transistor 16, since the voltage drop of diode 20 is equal to a Schottky diode voltage drop. In other words, diode 20 becomes nonconductive and stops applying speed up current when the output voltage at terminal 18 reaches approximately twice the base-emitter voltage of output transistor 16. This threshold value of prior speed up circuits has been found to be excessively high for optimum performance, as speed up current is not applied long enough to the output transistor 16, thus lengthening the turn on time of the circuit. Moreover, the additional speed up current applied to transistor 16 is limited by the h FE of transistor 14. Since transistor 14 normally supplies turn on current to output transistor 16 through resistor 34, this tends to reduce the additional turn on current available for transistor 16. Moreover, the circuit shown in FIGURE 1 provides difficulties when it is desired to utilize a high impedance three-state output. FIGURE 2 illustrates an improved circuit in accordance with the present invention wherein like numerals are used for like and identical components shown in FIGURE 1. Thus, FIGURE 2 includes the voltage input terminal 10, input diode 12 and input transistor 14. The emitter of transistor 14 is connected to the base of the Schottky clamped output transistor 16, the collector of which is applied to output terminal 18 to provide a voltage output. Transistor 22 is connected at its emitter and collector through resistors 24 and 26 to the base of transistor 16. A Darlington pair formed from transistors 28 and 30 is connected to the collector of transistor 16. Biasing resistors 32, 34, 36 and 38 are connected similarly as in FIGURE 1. In FIGURE 2, however, the previously described diode 20 is replaced by an improved speed up circuit. The circuit comprises a diode 40 connected at its cathode to the input terminal 10 and at its anode to a Schottky diode 42. The cathode of diode 42 is tied to the output terminal 18 and to the collector of output transistor 16. A speed up transistor 44 is connected at its base to the junction of interconnected diodes 40 and 42. The emitter of speed up transistor 44 is connected to the base of output transistor 16 and the collector thereof is tied to bias voltage. A resistor 46 is connected between the base of speed up transistor 44 and the bias voltage. In operation of the improved speed up circuit of FIGURE 2, assume that the voltage applied to the input terminal 10 is low and the voltage at output terminal 18 is high. The cathode of Schottky diode 42 is a logic "one" since it is tied to the output voltage. The cathode of diode 40 is a logic "zero" since the voltage input is low. The speed up transistor 44 is thus normally nonconductive. However, when a high voltage input is applied to the input terminal 10, the cathode of diode 40 goes to a logic "one". Diodes 40 and 42 operate to provide an AND function, so that the speed up transistor 44 is turned on only when logic "ones" are simultaneously applied to the cathodes of diodes 40 and 42. When this condition occurs, current flows from resistor 46 to the base of speed up transistor 44. Transistor 44 is connected as an emitter follower to the Schottky clamped output transistor 16 and thus applies emitter current to the base of the output transistor 16. This provides a DC speed up source for speeding up the conduction of transistor 16. Of course, upon the application of the high voltage to the input terminal 10, the input transistor 14 also begins to conduct and begins applying base current to output transistor 16 as in the previous circuit. The present circuit provides additional speed up current to output transistor 16 because of the gain provided by transistor 44. Moreover, the speed up current is applied from transistor 44 for a longer period of time then provided by the diode 20 (FIGURE 1). When the output voltage at the collector of transistor 16 falls to approximately twice the base-emitter voltage of transistor 16 minus a Schottky diode drop, only then will transistor 44 begin to turn off. This threshold level is thus substantially lower than twice a transistor base-emitter voltage. When the voltage at the collector of transistor 16 further falls, transistor 44 will become non conductive. It may thus be seen that the time of application of speed up current to output transistor 16 with the circuit of FIGURE 2 is substantially longer than the prior circuitry, due to the lower threshold turn off voltage level. In addition to these improved turn on characteristics, the circuit shown in FIGURE 2 may also be used to provide a tri-state output. To provide this output, a diode 48 is connected at its anode to the base of transistor 14. A diode 50 is connected at its anode to the collector of transistor 14. A diode 52 is connected at its anode to the base of the speed up transistor 44. The cathodes of diodes 48, 50 and 52 are tied together to a V₃ terminal 54 to provide a high impedance tri-state output. In operation, diode 48 holds transistor 14 off, diode 50 holds off transistors 28 and 30, and diode 52 holds off transistor 44. In these states, the output transistor 16 does not have a source of base current, so the voltage output at terminal 18 is at a high impedance state and the input to the speed up circuit is a reversed biased diode so that the output can be moved up and down as desired. The present invention may thus be seen to increase the amount of base current drive to the output transistor 16 during the turn on of the transistor 16. The current from the speed up transistor 44 during turn on of transistor 16 not only decreases the turn on time of the circuit, but allows the circuit to drive large capacitance loads with reduced effect on the turn on time. The additional turn on current is only applied during a high condition at both the input and output of the circuit, due to the AND function provided by the diodes 40 and 42. FIGURE 3 illustrates a variation of the circuitry shown in FIGURE 2 with like numerals being utilized for like and corresponding parts of the previous Figures. As may be seen, this circuit differs from that shown in FIGURE 2 by utilizing a Schottky clamped speed up transistor 44 and by tying the collector of the transistor 44 directly to the voltage output terminal 18. In addition, the tri-state circuitry comprising diodes 48-52 and terminal 54 has been eliminated from this Figure for clarity of illustration, although it should be understood that the tri-state circuitry could also be used in the circuitry of FIGURE 3. In operation of the circuitry of FIGURE 3, the additional speed up current applied from speed up transistor 44 during switching of the circuit is supplied by the load on the output terminal 18 in order to assist in discharging the load. Further, the collector of speed up transistor 44 turns itself off through the base collector of the Schottky clamp incorporated therewith. This allows the diode 42 of FIGURE 2 to be eliminated. With these modifications, the circuitry of FIGURE 3 operates in a similar manner as the circuitry of FIGURE 2 in order to provide improved speed up turn on of output transistor 16 to provide a fast transition for the output voltage at terminal 18. It will thus be seen that the present invention provides a speed up current for an extended period of time in order to provide a fast transition of an output transistor in a TTL output circuit. The present invention lowers the threshold voltage at which turn off of the speed up device occurs. The utilization of active gain devices such as transistors in place of the previously used diodes provides enhanced magnitude of speed up current, thereby further decreasing the turn off time of the circuit. The present device thus maintains speed up current to the output transistor below a threshold level of twice the base-emitter voltage of the output transistor. Although Schottky diodes have been disclosed for use with elements such as diode 42, it will be understood that a conventional collector-base diode could be alternatively utilized. In such a case, the threshold voltage for turn off of speed up current could be lowered to approximately one base-emitter transistor voltage, as the threshold voltage equals two base-emitter voltages minus a diode voltage, and since a collector-base diode voltage equals approximately one base-emitter voltage. Of course, Schottky diodes have smaller dimensions and less required storage charge.

Claims: A transition speed up circuit for speeding up the change of state of an output terminal (18) of a pull down transistor (16), said pull down transistor (16) being turned on in response to a transition of an input (10) received at an input transistor (14), which input transistor (14) is coupled to supply turn on current to the base of said pull down transistor (16), the circuit including a controllable speed up means (44) to add current to the pull down transistor turn on current during the change of state and means (40, 42) to control the speed up means (44), said means (40, 42) being connected to the control terminal of said speed means (44) and being connected between the input (10) and the output (18), respectively, and being arranged to switch on the speed up means in response to an input transition during the turn on period of the pull down transistor (16) and to switch off said speed up means in dependence upon a predetermined voltage at the output terminal (18) by applying a conduction preventing potential derived from the output terminal to the control terminal after said turn on period. A circuit as claimed in claim 1 wherein said speed up means comprises a transistor (44) arranged to amplify controlling current. A circuit as claimed in claim 2, wherein said means includes a pair of unidirectional conductive elements (40, 42) connected in series and connected between said input (10) and said output (18), said speed up transistor (44) connected between the junction of said unidirectional conductive elements (40, 42) to be controlled thereby and said pull down transistor (16), conduction of said speed up transistor (44) causing said added current to be applied to the base of said pull down transistor (16). A circuit as claimed in claim 3, wherein one of said pair of unidirectional conductive elements (42) is a Schottky diode. A circuit as claimed in claim 4, wherein the speed up transistor (44) is a Schottky clamped transistor and said one unidirectional conductive element (42) comprises said transistor Schottky clamp diode. A circuit as claimed in claim 3 or claim 4, wherein said input transistor (14) has a base for receiving either a low input voltage or a high input voltage, said pull down transistor (16) has a base connected to the emitter of said input transistor (14) the collector of said output transistor (16) providing an output voltage. a diode (40) is connected at its cathode to said input (10), said speed up transistor (44) has a base connected to the anode of said diode (40), the emitter of said speed up transistor (44) being connected to said base of said output transistor (16); and said speed up transistor (44) becoming conductive upon a high input voltage being applied to said input (10). A circuit as claimed in claim 4 or claim 6, wherein the collector of said speed up transistor (44) is connected to said collector of said pull down transistor (16). A circuit as claimed in claim 6, further including a second diode (42) connected at its anode to the base of said speed up transistor (44) and connected at its cathode to said collector of said pull down transistor (16), whereby said diode (40) and said second diode (42) provide an AND function by allowing current to said base of said speed up transistor (44) when both said input voltage and said output voltage have a high voltage level. A circuit as described in claim 8, further including a third diode (48) connected at its anode to said base of said input transitor (14); a fourth diode (52) connected at its anode to the base of said speed up transistor (44); a fifth diode (50) connected at its anode to the collector of said input transistor (14); and the cathodes of said third, fourth and fifth diodes connected together to form a high impedance tri-state control input (54). A logic circuit including a transition speed up circuit as claimed in any preceding claim.

Inventors: MARTIN ROBERT C, OVENS KEVIN M, SALZMAN JAMES F, STRONG BOBBY D, MARTIN, ROBERT C., OVENS, KEVIN M., SALZMAN, JAMES F., STRONG, BOBBY D.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1985
Main classification: H03K19
IPC codes: H03K19