One-chip microcomputer

Abstract: In a one-chip microcomputer, an EPROM is formed together with an ROM and RAM on one semiconductor substrate. Data such as fixed data necessary in the micro­ computer can be changed by the use of the EPROM. In case data are to be written in the EPROM, an EPROM writer is used. This EPROM writer outputs write data to the EPROM and checks (or verifies) the data written in the EPROM immediately thereafter. If any error is detected, the subse­ quent data write is interrupted. In order to inhibit the unnecessary operation interruption in case the address designated by the EPROM writer comes out of the range of the EPROM, the checking (or verifying) data signal to be fed from the one-chip microcomputer to the EPROM writer is forcibly set at a blank level.

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device and, according to the first part of claim 1 and to a technique effective for use in a one-chip microcomputer in which an ROM (i.e., Read Only Memory) to be stored with a data processing program is constructed of an EPROM (i.e., Electrically Programmable Read Only Memory). In a one-chip microcomputer, a predetermined data processing is executed in accordance with a program which is written in the built-in ROM. Prior to the present invention, we have conceived the use of an EPROM as the built-in ROM. This use of the EPROM makes it possible to promptly provide a one-chip microcomputer which has the data processing function desired by the user and to improve the mass productivity. If a mask type ROM is used as the aforementioned ROM, more specifically, it takes time to fabricate a variety of masks during program development. In case the EPROM is used as above, it would be convenient to conduct the writing operation by the use of an existing EPROM writer. As compared with the address space in the microcomputer, however, the ratio to be occupied by the EPROM is far smaller, e.g. at most 4K (4K x 8 bits) of an address space of 8K. As a result, errors for as many as half of the addresses are caused if the writing operation is conducted by the use of the existing EPROM writer (e.g., 8K x 8 bits = 64 Kbits) having the same address space as that of the microcomputer. In case the existing EPROM writer is used, more specifically, it is desirable that the construction of the usable EPROM writer be not restricted. In accordance with the existing EPROM writer, the address data are renewed sequentially from the start address, and the data to be written are sequentially outputted. The EPROM writer reads out the data written into the EPROM and checks them each time the writing operation into one address is executed. If, in this case, the start address of the EPROM is conveniently coincident with that of the EPROM, the data are written into the EPROM in a normal manner. However, the address space to be given to the built-in EPROM has not always a range convenient for the EPROM writer. In case the address data outside of the address range of the EPROM are outputted from the EPROM writer at the start of the data writing operation, no data are written into the EPROM. In this case, it is substantially impossible to check (verify) the write data after the data writing operation is conducted, because the address data designate memories other than the EPROM. As a result, errors, which should not exist, are detected by executing the verifying operation. Thus, in the operation to write into the addresses in which the EPROM is present, the check (or verification) can be made, but all data become erroneous for the remaining write check so that no continuous write is conducted. Incidentally, a high-grade EPROM writer capable of arbitrarily designating the addressing range is present but has a high price and raises a problem in distribution. Incidentally, the EPROM is disclosed in Japanese Patent Laid-Open No. 54 - 152933, for example. Address discriminators used for protecting specific memory areas, I/O ports or storage facilities from access by unauthorised programs are disclosed in EP-A-0 109 504 and US-A-4 298 934 for example. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device according to the preamble of claim 1 which may be programmed by a conventional EPROM - programmer. It is a further object to provide an operating method for the above device. These objects are solved by the device of claim 1 and the method set forth in claim 11. These and other objects and novel features of the present invention will become apparent from the description to be made herein with reference to the accompanying drawings. Representatives of the present invention to be disclosed herein will be briefly described in the following. It is made possible to write a programmable ROM by means of a simple writer by adding a function to discriminate an address space, which is assigned to the programmable ROM to be stored with a data processing program, and a function to send out a signal identical to a blank to the output for the assigned address other than the address space assigned. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing one embodiment of the one-chip microcomputer to which the present invention is applied; Fig. 2 is a diagram showing an address space for explaining the summary of the writing operation of the same; Fig. 3 is a specific circuit diagram showing a control circuit WCON of Fig. 1; Fig. 4 is a specific circuit diagram showing an EPROM of Fig. 1; and Fig. 5 is a specific circuit diagram showing input and output ports of Fig. 1. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a block diagram showing the embodiment of the one-chip microcomputer to which the present invention is applied. A rectangular encircled by double-dotted lines in Fig. 1 indicates an integrated circuit LSI. The respective circuit blocks formed in the rectangular construct the one-chip microcomputer as a whole and are formed in one semiconductor substrate made of silicon by the known semiconductor integrated circuit device fabricating technique. Indicated by a symbol CPU is a micro processor which has its major component blocks exemplified as representatives. Specifically: symbol A indicates an accumulator; symbol X an index register; symbol CC a condition code register; symbol SP a stack pointer; symbols PCH and PCL program counters; symbol CPU-CONT a CPU controller; and symbol ALU an arithmetic logic operation unit. The construction of such microprocessor CPU is well known in the art by "Fundamentals of Microcomputer" published by on April 10, 1983 by KK OHM and written by Koji YADA, for example, and its detail description is omitted. Indicated at symbols I/O₁ and I/O₂ are input/output ports each having a data transmission direction register therein. The input/output port I/O₁ can be controlled by a control circuit WCON, and its specific example will be described later with reference to Fig. 3. On the other hand, symbol I indicates an input only port. Indicated at symbol OSC is an oscillator for generating a highly accurate reference frequency signal by making use of a quartz crystal unit Xtal attached externally, although not especially limited thereto. Clock pulses necessary for the microprocessor CPU are generated by that reference frequency signal. This reference frequency signal is used as a reference time pulse of a timer, too. This timer is composed of a counter COUT, a prescaler PR and a controller CONT. Indicated at symbol RAM is a random access memory which is used mainly as a memory circuit for temporary data. Indicated at symbol EPROM is an electrically programmable read only memory which is to be written with a program for a variety of data processings. The respective circuit blocks described above are connected around the micro processor CPU with one another through a bus BUS. This bus contains a data bus and an address bus. In the bus BUS, incidentally, the address bus ADD is linked to the external terminal and can be linked directly to the EPROM. In the microcomputer of the present embodiment, the aforementioned EPROM is used, and there is provided the control circuit WCON for controlling the write of the EPROM and so on. The control circuit WCON receives a chip enable signal through an external terminal CE to enable the data to be written in the EPROM if the chip enable signal is in an EPROM direct access mode (or at a low level). If in the EPROM direct access mode, the control circuit WCON outputs a control signal ce for an interruption into the CPU control circuit CPU-CONT. This CPU control circuit CPU-CONT is interrupted by the control signal ce to control the CPU input/output port I/O₂, the input only port I and so on and to open the internal bus BUS. The control circuit WCON discriminates the voltage level fed from an external terminal V pp to control the write/read operation modes and to feed its writing high voltage to the aforementioned EPROM. For example, if either a relative low voltage (e.g. 5 V) equal to an internal supply voltage Vcc or the ground potential (i.e., 0 V) of the circuit is supplied from the external terminal Vpp, the control circuit WCON generates a high-level discrimination signal. This high-level signal is used to establish the read operation mode, for example, when the EPROM is selected by the CPU. As a result, the verifying operation is made possible. If the writing high voltage (e.g., about 12 V) of the EPROM is fed from the external terminal Vpp, on the other hand, the control circuit WCON generates a low-level discrimination signal. For example, the data input buffer of the EPROM is rendered into its operative state in response to a low-level pulse generated by feeding the aforementioned high voltage Vpp for a predetermined period, and a write signal of a logic "0" generated by making use of the high voltage Vpp is prepared in accordance with the data fed from the data bus so that the logic "0" is written in a memory cell (e.g., a FAMOS transistor) selected. At this time, incidentally, the addressing of the EPROM is conducted in response to the address signal fed from the external terminal. Moreover, the aforementioned address signal is fed to the address discrimination circuit contained in the aforementioned control circuit WCON. This address discrimination circuit inhibits the write operation and feeds out the read signal at that time as a blank (i.e, a logic "1"), although not limitative thereto, if it detects the set address other than those in the address space to which the EPROM is assigned. Incidentally, the aforementioned write inhibiting function need not be provided. This is because the non-existing address designation of the EPROM is conducted so that EPROM is not selected not to effect the writing operation. The writing operation of the EPROM of the present embodiment will be schematically described with reference to the address space diagram of Fig. 2. Let the case be considered, in which, of address spaces A0 to A3 set by the address bus ADD: the address of the input/output port is assigned to A0 to A1; the area of the EPROM is assigned to A1 to A2; and an RAM area is assigned to the remaining A2 to A3. In the writing operation of the EPROM by the writer, then, the continuous writing operations of the area A0 to A3 are conducted, and the blank (i.e., the logic "1") is written for the set addresses (i.e., the hatched areas) of those other than the aforementioned EPROM areas (A0 to A1 and A2 to A3) when in the verifying operation (e.g., the read check after the write). For these writing operations, the control circuit WCON makes its output blank (i.e., the logic "1") for the set addresses other than those of the aforementioned EPROM areas (A0 to A1 and A2 to A3) so that the continuous writing operation can be conducted without any write error. Fig. 3 shows a specific circuit of the control circuit WCON of Fig. 1. The control circuit WCON is constructed of a voltage level detector VDT, an address discriminator ADC, and first and second control signal generators CSG₁ and CSG₂. The voltage level detector VDT is composed of an input circuit HSC for voltage level detection and an inverter IV₂ as a buffer. The input circuit HSC is made of a hysterisis circuit so that it may be insensitive to the undesired noises applied to the external terminal Vpp, although not limitative thereto. The hysterisis circuit is not shown in detail because it is known per se, and both its two threshold voltages are made to take intermediate values between the supply voltage Vcc of the circuit and the high voltage such as 12 V fed to the terminal Vpp. With the construction described above, the voltage level detector VDL outputs a high-level discrimination signal  vd substantially equal to the supply voltage Vcc, when the supply voltage Vcc of the circuit or the ground voltage is fed to the external terminal Vpp, and a low-level discrimination signal  vd substantially equal to 0 V when the high voltage as high as about 12 V is fed to the external terminal Vpp. The address discriminator ADC is constructed to discriminate the address space of the EPROM with reference to the upper three bits of the (not-shown) address bus in the internal bus BUS, although not especially limitative thereto. More specifically, the output of a NAND circuit ND₄ is set at a low level only when the most significand bit am and the next significant am-1 of the address signal are at the logics "0" and "1", whereas the output of a NAND circuit ND₅ is set at a low level only when the bits am and am-1 are at "1" and "0". Likewise, the output of a NAND circuit ND₆ is set at the low level only when the bits am, am-1 and am-2 take the values "1", "1" and "0", respectively. In accordance with the outputs of those NAND circuits ND₄ to ND₆, the output of a NAND circuit ND₇, i.e., the output  ad of the address discriminator ADC is set at the high level, if the bits am, am-1 and am-2 are within the range "010" to "110", and otherwise at the low level. The output  ad is fed to the second control signal generator CSG₂ and to the first control signal generator CSG₁ as a kind of chip enable signal. In response to the output  vd of the voltage level detector VDT, the chip enable signal fed through the external terminal CE and the output  ad of the address discriminator ADC, the first control signal generator CSG₁ outputs control signals  r ,  w and we necessary for the EPROM, and a control signal ce indicating the direct access mode of the EPROM. The control signal ce is made substantially identical to the chip enable signal (which will be referred to as a CE signal) of the external terminal CE , although not limitative thereto, such that it is set at the high level if the CE signal is at the high level, i.e., not the chip enable level, whereas it is set at the low level if the CE signal is at the low level, i.e., at the chip enable level. The first control signal generator CSG₁ contains a not-shown OR circuit for generating the internal chip enable signal by OR composing the CE signal and an inverted level signal of the discrimination signal  ad outputted from the address discriminator ADC. Although not especially limitative, the combination of the high level of the discrimination signal  vd and the chip enable level of the internal chip enable signal is deemed as the reading operation mode, whereas the combination of the low level of the discrimination signal  vd and the chip enable level of the internal chip enable signal is deemed as the program mode or the write mode. The non-chip enable level of the internal chip enable signal is deemed as a standby mode. The control signal  r is used for controlling the operations of output buffer circuits OB₁ to OB n of the EPROM, as will be described later with reference to Fig. 4, so that it is set at the high level in the reading operation mode and at the low level in the remaining modes. The control signal  w is used for controlling the operations of input buffers DW₁ to DW n of the EPROM so that it is set at the high level in the program mode and at the low level in the remaining modes. The control signal we is changed in synchronism with the control signal  w so that it is set at the low level in the program mode and at the high level in the remaining modes. The second control signal generator CSG₂ is composed, as shown in Fig. 3, of a NAND circuit ND₈ and inverter circuits IV₃ to IV₅ so that it outputs a control signal  c in response to the outputs  ad and ce of the address discriminator ADC and the output  r of the first control signal generator CSG₁. The control signal  c is set at the high level when the discrimination signal  ad and the control signal ce are at the low level and when the control signal  r is at the low level, i.e., when the reading operation mode is designated by the CE signal and the detection signal  rd and when the address other than those in the address space of the EPROM is designated by the address discriminator ADC. The EPROM is composed, as shown in Fig. 4, of: an address decoder DEC made receptive of the address signal through the bus line BUS; an memory array MM having its word lines W₀ to W k selected by the address decoder DEC; a column switch C-SW connected between the memory array MM and common data lines CD₁ to CD n and adapted to be switched by the address decoder DEC; sense amplifiers SA₁ to SA n linked to the common data lines CD₁ to CD n , respectively; the output buffer circuits OB₁ to OB n connected between the respective sense amplifiers SA₁ to SA n and the bus line BUS; the input buffer circuits DW₁ to DW n connected between the bus line BUS and the common data lines CD₁ to CD n ; and a high-voltage supply circuit connected between the each word line of the memory array MM and the external terminal Vpp. The address decoder DEC is made receptive of not only the address signal but also the control signal we and the write voltage Vpp to output the selection signal substantially at the selection level of the supply voltage Vcc of the circuit and the selection signal substantially at the non-selection level of the ground potential of the circuit to the column switch C-SW and the word lines W₀ to W k of the memory array MM if the control signal we is at the high level. If the control signal we is generally at the low level of 0 V and if the voltage Vpp is generally at the write level of 12 V, the selection level of the selection signal to be fed to the column switch C-SW is set generally at the write level. At this time, moreover, the word level to be selected from the word lines W₀ to W k is set generally at the write level by the high-voltage supply circuit HVS. The output buffer circuits OB₁ to OB n have their operations controlled by the control signal  r such that they output such data signals to the bus line BUS if the control signal  r is at the high level as correspond to the data signals as outputted from the sense amplifiers SA₁ to SA n . The output buffer circuits OB₁ to OB n are brought into their high-output impedance states if the control signal  r is at the low level. The input buffer circuits DW₁ to DW n receive the voltage V pp , and have their operations controlled by the control signal  w . If the control signal  w is at the high level, the respective input buffer circuits DW₁ to DW n outputs such a signal at the level of 0 V or the V pp level to the respective common data lines CD₁ to CD n as corresponds to the data signal fed through the bus line BUS. If the control signal  w is at the low level, the respective input buffer circuits DW₁ to DW n are brought into the high-output impedance states. As a result, when in the reading operations the read data signals of the memory array MM fed to the respective common data lines CD₁ to CD n through the column switch C-SW are fed to the bus line BUS through the sense amplifiers SA₁ to SA n and the output buffers OB₁ to OB n , respectively. When in the writing operations on the other hand, the high-voltage level write data signals outputted from the input buffer circuits DW₁ to DW n are fed to the memory array MM through the common data lines CD₁ to CD n and the column snitch C-SW. In accordance with the present embodiment, the input/output circuit I/O₁ has its construction modified slightly as the input/output circuit of the EPROM direct access mode for the ordinary input/output circuit. A specific example of the construction of the input/output circuit I/O₁ is shown in Fig. 5. The input/output circuit I/O₁ contains: circuits composing the ordinary input/output circuit such as an output buffer OB and an input buffer IB linked to an input/output terminal I/O and data transmission direction registers RGr and RGi having their respective contents determined by the control signals fed through the bus line BUS; NAND circuits ND₁ to ND₃, a gate circuit GC; an inverter circuit IV₁; and an OR circuit OR. In accordance with this construction, the output of the NAND circuit ND₃, i.e., the control input of the output buffer circuit OB is made identical to the output O₁ of the register RGr, if the control signal ce is at the high level, and to the control signal  r if the control signal ce is at the low level. The gate circuit GC is made substantially identical to the circuit composed of the NAND circuits ND₁ to ND₃. The output of the gate circuit GC, i.e., the control input of the input buffer circuit IB is made identical to the output O₂ of the register RGi, if the control signal ce is at the high level, and to the control signal  w if the control signal ce is at the low level. The output of the OR circuit is set at the high level irrespective of the signal fed from the bus line BUS if the signal  c is at the high level. As a result, the output buffer and input buffer OB and IB have their respective operations controlled by the registers RGr and RGi if the control signal ce is at the high level, in other words, if the EPROM direct access mode is not designated. The output buffer OB and the input buffer IB have their respective operations controlled by the control signals  r and  w irrespective of the outputs O₁ and O₂ of the registers RGr and RGi if the control signal ce is at the low level, in other words, if the EPROM direct access mode is designated. In the EPROM direct access mode (namely, ce : at the low level), if the control signal  w is set at the high level, the input buffer IB is accordingly brought into its operative state. In accordance with this, the write data signal fed from the EPROM writer to the input/output terminal I/O is fed to the EPROM of Fig. 4 through the input buffer IB and the bus line BUS. If the control signal  r is at the high level in the EPROM direct access mode, the output buffer OB is accordingly brought into its operative state. In accordance with this, the outputs of the output buffers OB₁ to OB n of Fig. 4 are outputted to the input/output terminal I/O through the OR circuit OR and the output buffer OB. If, at this time, the address space indicated by the address signal fed from the bus line BUS to the EPROM is out of that of the EPROM, the signal  c outputted from the circuit CSG₂ of Fig. 3 is set at the high level. In accordance with this, the signal at the high level is outputted from the output buffer OB of Fig. 5 irrespective of the signal level of the bus line BUS. In the program of the EPROM by the EPROM writer, incidentally, either a socket especially for setting the semiconductor device of the present embodiment or a conversion socket for changing the pin arrangement is prepared and is linked to the socket which is mounted in the EPROM writer. For verification of the EPROM, either the data corresponding to the address other than those of the address space of the EPROM or expectable values are all set at the (high level) "1". As a result, the signals outputted from the input/output circuit I/O₁ of Fig. 1 or 5 become coincident with the expectable values set in advance in the EPROM writer, when an address outside of the address space of the EPROM is designated. According to the present invention, the following effects can be attained. (1) By detecting the address designation in which the programmable ROM is not present and by blanking the read signal at that time, there can be attained an effect that the writer can continue its writing operation without any consideration into the ROM areas. (2) Thanks to the effect (1), there can be attained another effect that the writing operation can be performed by the simplified writer which has the minimum writing function including the verifying operation. (3) Thanks to the effects (1) and (2), there can be attained still another effect that a copying operation or the like can be easily conducted to write a plurality of semiconductor integrated circuit devices containing the programmable ROMs. Although the present invention made by us has been described specifically in connection with the embodiment thereof, it should not be limited thereto but can naturally be modified in various manners within the scope of the gist thereof. For example, the programmable ROM should not be limited to the aforementioned EPROM but may be replaced by a variety of programmable ROMs such as an electrically writable PROM, e.g., an electrically erasable PROM EEPROM or an electrically unerasable PROM. In this modification, the control circuit WCON shown in Fig. 1 is made to conduct the write control according to the built-in programmable ROM. The signal level forcibly set when the address other those of the address space of the programmable ROM may be either at the high level or at the low level. Although the foregoing description has been directed mainly to the case in which the present invention is applied to the one-chip microcomputer providing the background thereof and having the built-in EPROM, the present invention should not be limited thereto but may be widely applied to a variety of semiconductor integrated circuit devices containing the programmable ROM and having a larger address space than that of the former.

Claims: A semiconductor integrated circuit device (LSI) including an electrically programmable read only memory (EPROM) into which data is written and subsequently checked by external writer means and including a control circuit (WCON) controlling the read/write operation of said electrically programmable read only memory, said device comprising: a first external terminal to which an address signal is applied from said external writer means during said data write or data check operation, wherein the address space is divided into a first address space (A1 to A2) assigned to the electrically programmable read only memory (EPROM) and a second address space (A0 to A1 and A2 to A3) not assigned thereto, a second external terminal through which data is written to the electrically programmable read only memory (EPROM) from the external writer means or read from the electrically programmable read only memory (EPROM) to the external writer means during said data write or data check operation, and a third external terminal (Vpp, CE) to which an operation select signal controlling said data write and said data check operation is supplied, characterized in that said control circuit (WCON) further comprises an address discriminator (ADC, WCON) discriminating whether or not the address signal received from said first external terminal designates an address in said first address space (A1 to A2) and outputting a discrimination result signal (Θad), and a control signal generator (CSG1, CSG2, WCON) receiving said discrimination result signal (Θad) and said operation select signal (Vpp, CE), detecting whether the operation selected by said external writer means is the data write or data check operation, and outputting a first control signal (Θc) to set the data to be outputted on said second external terminal to a predetermined level in case the data check operation is selected and the address signal designates an address in said second address space (A0 to A1, A0 to A3). The device of claim 1, characterized in that the level of data inputted by the external writer means to the second external terminal in the data write operation in case that the data is to be written into said second address space (A0 to A1, A2 to A3) corresponds to said predetermined level. The device of claim 1 or 2, characterized by an input-output circuit (I/O) having its input and output terminals coupled to said second external terminal, wherein the data is written to the electrically programmable read only memory (EPROM) from the external writer means via said second external terminal and said input-output circuit (I/O) and wherein the data is read out from the electrically programmable read only memory (EPROM) to the external writer means via said input-output circuit (I/O) and said second external terminal. The device of claim 3, characterized in that said first control signal (Θc) is supplied to said input-output circuit (I/O). The device of claim 3 or 4, characterized by a bus line (BUS) coupled to said first external terminal and to said second external terminal via said input-output circuit (I/O), wherein the address input terminal of said electrically programmable read only memory (EPROM) is coupled to said first external terminal via said bus line (BUS) and the data input-output terminal of the electrically programmable read only memory (EPROM) is coupled to said second external terminal via said bus line (BUS) and said input-output circuit (I/O), and wherein said address discriminator (ADC) is coupled to said first external terminal via said bus line (BUS). The device of any of claims 1 to 5, characterized in that said control signal generator (CSG) includes means (CSG1) for outputting, in response to said discrimination result signal (Θad) and said operation select signal (Vpp, CE), a second control signal (Θr, Θw, we) controlling the write or read operations of said electrically programmable read only memory (EPROM). The device of claim 6, characterized in that said second control signal (Θr, Θw, we) is supplied to said electrically programmable read only memory. The device of any of claims 1 to 7, characterized by a microprocessor (CPU) coupled to the electrically programmable read only memory (EPROM), wherein the data written into the electrically programmable read only memory (EPROM) constitutes a program and the microprocessor (CPU) executes a predetermined data processing in accordance with the program. The device of claim 8, characterizerd by a random access memory (RAM) coupled to the microprocessor (CPU) for providing a work area of the microprocessor, wherein the second address space (A0 to A1, A2 to A3) comprises a space (A2 to A3) assigned to the random access memory (RAM). The device of claim 8 or 9, characterized by register means (M1) coupled to the microprocessor (CPU) for storing data therein, wherein the second address space (A0 to A1 and A2 to A3) further comprises a space (A0 to A1) assigned to the register means (M1). A method of programming and subsequently checking an electrically programmable read only memory(EPROM) included in a semiconductor integrated circuit device(LSI) by external writer means, an address space of the semiconductor integrated circuit device (LSI) being divided into a first address space(A1 to A2) assigned to the electrically programmable read only memory(EPROM) and a second address space(A0 to A1 and A2 to A3) not assigned thereto, comprising the following steps: supplying an address signal and a data signal from the writer means to the semiconductor integrated circuit device(LSI), discriminating whether an address designated by the address signal is in the first address space(A1 to A2) or in the second address space, writing the data indicated by the data signal into the electrically programmable read only memory(EPROM) at the address designated by the address signal and subsequently reading it by the external writer means to verify the programmed data, if the address is in the first address space(A1 to A2), and providing a predetermined data signal from the semiconductor integrated circuit device(LSI) to the external writer means in a reading step by the external writer means, if the address designated by the address signal is in the second address space(A0 to A1, A2 to A3).

Inventors: KOBAYASHI ISAMU, SAKAKIBARA YASUHIRO, SUZUKI YOSHINORI, KOBAYASHI, ISAMU, SAKAKIBARA, YASUHIRO, SUZUKI, YOSHINORI
Applicants: HITACHI LTD, HITACHI MICROCOMPUTER SYST, HITACHI MICROCOMPUTER SYSTEM LTD., HITACHI, LTD.
Application year: 1985
Main classification: G06F12
IPC codes: G06F15, G11C16, G11C17, G06F12