TIMER CIRCUIT

Abstract: A timer circuit which is used for write and erase time control of a semiconductor memory, and configured so as to transfer a charge of a charge storage capacitor (1) to a charge pump capacitor (2) through a first transfer gate (4) thereafter to repeatedly effect a discharge operation by using a second transfer gate (3) thereby to gradually reduce a charge of the charge storage capacitor (1), thus performing a timer oper­ ation, characterized in that there is provided a circuit (7, 9, 10, 11, 12) for making an adjustment such that a voltage applied to the charge pump capacitor (2) is smaller than a voltage applied to the charge storage capacitor (1).

Description: The present invention relates to a timer circuit used for controlling a write and erase time of E²PROM (Electrical Erasable Programmable Read Only Memory), etc. From "Introduction to MOS LSI Design" by J. Mavor et al, Addison Wesley, 1983, a timer circuit is known which comprises a charge storage capacitor having a first and a second terminal, the second terminal being for connection to a reference potential; a charge pump capacitor having a first and a second terminal; a first transfer gate connected between said first terminals of both capacitors to periodically transfer a part of a charge stored in said charge storage capacitor to said charge pump capacitor; a second transfer gate connected across said charge pump capacitor to periodically discharge a charge stored in said charge pump capacitor while said first terminals of both capacitors are isolated from one another by said first transfer gate; and means for transferring a charge to said charge storage capacitor. Thus, there has been proposed a timer circuit used for a write and erase time control of a semiconductor memory, wherein its timer operation is performed by transferring a charge stored in a charge storage capacitor to a charge pump capacitor through a first transfer gate thereafter to repeatedly effect a discharge operation by using a second transfer gate, thus gradually lessening the charge in the charge storage capacitor. However the drawback with the above-mentioned conventional timer circuit is that a large capacity ratio of the timer is required for ensuring prolonged operation time, resulting in enlargement of the LSI. An object of the present invention is to provide a timer circuit having a capacity ratio of two capacitors set as small as possible and a sufficiently long timer interval. According to the invention, the timer circuit initially defined is characterized by an adjustment circuit arranged to apply to said second terminal of said charge pump capacitor a voltage whose value decreases in response to a decrease of the charge stored in said charge storage capacitor so that in use of the adjustment circuit the voltage applied to said charge pump capacitor is always smaller than the voltage across said charge storage capacitor. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:- Fig. 1 is a circuit diagram illustrating a prior art timer circuit to which the switched capacitor technique is applied; Fig. 2 is a circuit diagram illustrating an embodiment of a timer circuit according to the present invention; Fig. 3 is a circuit diagram illustrating another embodiment of a timer circuit according to the present invention; and Fig. 4 is a circuit diagram illustrating a further embodiment of a timer circuit according to the present invention. Referring to Fig. 1, there is shown a prior art timer circuit to which the switched capacitor technique is applied. The timer circuit shown in this figure comprises a charge storage capacitor 1 having a capacity C₀, a charge pump capacitor 2 having a capacity C₁, and two transfer gates 3 and 4 which are opened and closed in accordance with fundamental clocks ₁ and ₂, respectively. The operation of the circuit is as follows. First, a charge is supplied to a node 5 by a reset operation thereby to charge the capacitor 1. It is assumed that a potential at the node 5 in this case is V₀. The fundamental clock ₁ has the same frequency as that of the fundamental clock ₂ and an inverted phase with respect to a phase of the fundamental clock ₂. The transfer gates 3 and 4 are operative in a manner that when one is opened, the other is closed. When the transfer gate 4 is opened, a part of the charge which has been stored in the capacitor 1 is transferred to the capacitor 2. Assuming now that a potential at the node 5 in this case is V₁, the following equation (1) holds and the following equation (2) can be derived from the equation (1): Subsequently, when the transfer gate 4 is closed, the transfer gate 3 is opened to discharge the charge which has been stored in the capacitor 2. The above-mentioned operation will be repeatedly carried out in correspondence with a time period of the fundamental clocks ₁ and ₂, thus to gradually discharge the charge which has been stored in the capacitor 1. Assuming now that the time period of the fundamental clocks ₁ and ₂, is T, a potential V(t) at the node 5 in the case where reset operation is effected at a time of t=0 is expressed by the following equation (3): A time required until the potential V(t) is less than a predetermined value is utilized for a timer operation. In the above-mentioned conventional timer circuit, the potential V(t) at the node 5 decreases as an exponential function of time as understood from the equation (3). For this reason, it is required to set the capacity ratio C₀/C₁ to an extremely large value in order to constitute a timer having an operation time sufficiently longer than the time period T of the fundamental clock. This result in the large occupation area of capacitors within a wafer for LSI circuit. Preferred Embodiments of the Invention Referring to Fig. 2, there is shown an embodiment of a timer circuit according to the present invention. Circuits components identical to those shown in Fig. 1 are represented by the same reference numerals, respectively, and their explanation will be omitted. A P-type MOS transistor 6 is a transistor serving as a reset switch coupled between a power supply terminal Vcc and the node 5. A ground terminal of the charge pump capacitor 2 is grounded through an N-type MOS transistor 7 having a small conductance gm. The ground terminal of the capacitor 2 is connected to the output of the transfer gate 3. A circuit for adjusting a potential at a node 8 is connected between the nodes 5 and 8 and comprises an inverter 9, a P-type MOS transistor 10 and an N-type MOS transistor 11. A transistor which provides a small back-bias effect is used for the transistor 11. When a signal is applied to the gate of the transistor 6 to reset the circuit, a charge is stored in the capacitor 1. It is assumed that a potential at the node 5 in this case is V₀. When the transfer gate 4 is opened, a part of the charge which has been stored in the capacitor 1 is transferred to the capacitor 2. At this time, because the conductance gm of the transistor 7 is small, a potential level at the node 8 is fairly greately biased with respect to the ground level and a voltage applied to the capacitor 2 becomes considerably smaller than a voltage applied to the capacitor 1. Assuming that a potential at the node 5 in this case is V₁, the value of V₁ is approximately expressed by the following equation (4): where gm₁, gm₂ and K denote conductance of the transistor 7, conductance of the transistor 11 and coefficient of back-bias effect of the transistor 11, respectively. If the conductance gm₁ is set to a value smaller than the conductance gm₂, the coefficient K of back-bias effect is nearly equal to 0.2 because the transistor 11 has a small back bias-effect, thus making it possible to provide a small difference between the potentials V₀ and V₁. Subsequently, when the transfer gate 4 is closed, the transfer gate 3 is opened, thus to discharge the charge which has been stored in the capacitor 2. By repeatedly carrying out the above operation based on the time period of the fundamental clocks ₁ and ₂, the charge which has been stored in the capacitor 1 is gradually discharged. An adjustment is made such that the potential at the node 8 is automatically lowered according as the potential at the node 5 lowers. Thus, this ensures that the voltage applied to the capacitor 2 is always smaller than the voltage applied to the capacitor 1. The potential at the node 5 substantially linearly decreases in accordance with the equation (4). When an attention is drawn to the potential at a node 12, it is nearly equal to Vcc as long as the transistor 10 is turned on and becomes zero volts when the transistor 10 turns off. Because the on-off operation of the transistor 10 is controlled through the inverter 9 on the basis of a potential at the node 5, a timer function can be eventually obtained by detecting the potential at the node 12. In this instance, such a detection can be easily effected because the potential at the node 12 takes the value of 5V or 0V. The advantages experimentally confirmed in a quantitative manner in connection with the above-mentioned embodiment will be described. The following settings are now assumed: At a time of t = 0, reset operation is effected and a voltage V₀ at this time is equal to 5 volts; the value of the conductance gm₂ of the transistor 11 is larger than that of the conductance gm₁ of the transistor 7 and the factor A expressed by the equation (5) is equal to 0.1; and the coefficient K of back-bias effect is equal to 0.2 because a transistor having small back-bias effect is used for the transistor 11. By performing the substitution of the above values into the equation (4) in order to calculate the potential V(t) at the node 5, the equation (6) is derived from the equation (4) as follows. As understood from this equation (6), the potential V(t) linearly decreases with respect to time and the capacity ratio (C₁/C₀) is multiplied by the factor of 0.5. Accordingly, when the same capacity ratio C₁/C₀ as that of the prior art timer circuit is employed, a timer circuit having a time interval about ten times longer than that of the prior art timer circuit can be obtained. Referring to Fig. 3, there is shown another embodiment of a timer circuit according to the present invention. The timer circuit in this embodiment comprises a pair of timer circuit each of which corresponds to the circuit employed in the first-mentioned embodiment of the invention. Accordingly, in regard to one circuit, a prime is attached to each of circuit components corresponding to those shown in Fig. 2 while in regard to the other circuit, double primes are attahced to each circuit component corresponding thereto, and their explanation will be omitted. A reset circuit 13 is used for resetting the entire circuit. Because a pair of timer circuits are coupled in a manner that outputs from one and the other timer circuits are supplied to the other and one timer circuits as reset inputs, respectively. Accordingly, after the entire circuit is reset, outputs 1 and 2 are phase-inverted to each other, thus producing a rectangular wave signal having a time period set in the timer circuit. It is possible to extremely prolong (e.g., one thousand times) this time period as compared to the time period T of the clocks ₁ and ₂. Referring to Fig. 4, there is shown a further embodiment of a timer circuit according to the present invention. The timer circuit in this embodiment has a feature that the inverter 9 and the P-type MOS transistor 10 in Fig. 2 are eliminated so that the circuit is simpler than that of Fig. 2 in structure, thereby resulting in being less responsive. As stated above, with the timer circuit according to the present invention, an adjustment is made so that a voltage applied to a charge pump capacitor is always smaller than a voltage applied to a charge storage capacitor. Even in the case where a timer circuit having a time interval sufficiently longer than the time period T of the fundamental clock is required, the occupation area of the both capacitors can be reduced.

Claims: A timer circuit comprising: a charge storage capacitor (1) having a first and a second terminal, the second terminal being for connection to a reference potential; a charge pump capacitor (2) having a first and a second terminal; a first transfer gate (4) connected between said first terminals of both capacitors to periodically transfer a part of a charge stored in said charge storage capacitor (1) to said charge pump capacitor (2); a second transfer gate (3) connected across said charge pump capacitor (2) to periodically discharge a charge stored in said pump capacitor (2) while said first terminals of both capacitors are isolated from one another by said first transfer gate (4); and means for transferring a charge to said charge storage capacitor (1), characterized by: an adjustment circuit (7,9,10,11,12) arranged to apply to said second terminal (8) of said charge pump capacitor (2) a voltage whose value decreases in response to a decrease of the charge stored in said charge storage capacitor (1) so that in use of the adjustment circuit the voltage applied to said charge pump capacitor (2) is always smaller than the voltage across said charge storage capacitor (1). A timer circuit as set forth in claim 1, wherein said adjustment circuit comprises a transistor (7) connected between the second terminal (8) of said charge pump capacitor (2) and a grounded point, said transistor (7) being operable to allow a potential at said second terminal (8) to be higher than ground potential. A timer circuit according to claim 2 wherein said adjustment circuit comprises a circuit (9,10,11,12) connected between said second terminal (8) and said first terminal of said charge storage capacitor (2) and operable to adjust the potential at said second terminal (8) in accordance with the potential at said first terminal. A timer circuit as set forth in claim 2 or 3 wherein said adjustment circuit comprises a second transistor (11) whose gate is connected to the first terminal (5) of said charge storage capacitor (1), and one of the source and drain of which is connected to the second terminal (8) of said charge pump capacitor (2) while the other is connected to a power source (Vcc). A timer circuit as set forth in claim 4 wherein said adjustment circuit comprises a pair of P-type and N-type transistors (10,11) connected in series with each other, wherein gates of said P-type transistor and said N-type transistor are connected to the first terminal (5) of said charge storage capacitor (1) through an inverter (9) and directly respectively, and one output terminal of the circuit comprising said pair of transistors (10,11) connected in series is connected to the second terminal (8) of said charge pump capacitor (2) while the other output terminal is connected to a power source (Vcc).

Inventors: TSUJIMOTO, JUN-ICHI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: G11C7
IPC codes: G11C7, H03K17