SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A TEST CIRCUIT

Abstract: A semiconductor integrated circuit device having a test circuit including a plurality of gate cells (2) arranged in a matrix; wiring for connecting the gate cells so as to constitute a logic circuit; a plurality of row selection wires (3) provided along the gate cells in a row direction, each of the gate cells (2) being operatively connected to a row selection wire (3) a plurality of a column read-out wires (4) provided along the gate cells in a column direction, outputs of each of the gate cells (2) being operatively connected to column read-out wires (4), a row selection ring counter (6), operative­ ly connected to the row selection wires (3), for selecting any of the row selection wires (3) and for the selecting of any of the gate cells (2) connected to the selected row selection wire (3); and a data selector (8) and ring counter (7) for reading out of the gate cells (2) arranged in the logic circuits through the column read-out wires (4).

Description: SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A TEST CIRCUIT BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a test circuit, particularly, to a gate array type large-scale integrated circuit (gate array LSI) having an improved test circuit. The gate array LSI according to the present invention can be easily tested for the operation of the logic circuit constituted by the gate cells. 2. Description of the Related Art AN LSI logic device with a test circuit was proposed in Japanese Unexamined Patent Publication (Kokai) No. 48-32490. This prior art discloses row wirings and column wirings for detecting whether each unconnected gate operates properly. After finding faulty gate cells and proper gate cells, only the proper gate cells are connected to form the overall logic circuit. At the same time, the row or column wirings are fixed to the power supply voltage so as not to affect the real logic function. Therefore, this prior art test circuit cannot be used for testing the final logic function of the final device. Recent research in the field of LSI testing has concentrated on the design of more effective test patterns using computer-aided-design (CAD) fault simulation and the design of more effective, simpler test circuits for incorporation in LSI's to allow testing by the scan pass method. Testing by test patterns using CAD fault simulation, however, is disadvantageous in view of the long time required for the fault simulation program, which time is increasing along with the increasingly greater scale of LSI's. Testing by incorporation of test circuits and the scan pass method is therefore more preferable. One of the better known of the scan pass methods now in use is the level sensitive scan design (LSSD) method of IBM Corporation. Specifically, the logic circuit in the LSI is divided into combinational circuit portions and flip-flop circuit portions. The flip-flop circuits can be connected in series through switching circuits provided in those flip-flop circuits. Connected, the flip-flop circuits constitute a shift register. The test of the circuit is performed by switching between a "shift mode" and "normal mode". In the shift mode, a scan signal is input to the shift register. In other words, data is applied to the shift register to set up the flip-flop circuits as a predetermined "1" or "on. The flip-flop circuits are then disconnected by the switching circuits and returned to the logic circuit. A predetermined logic operation is performed, then the flip-flop circuits is reconnected to form the shift register, after which the data of the shift register is read out and checked. The above method has some problems, however. For example, it requires that the LSI be designed to allow formation of a shift register by the flip-flop circuits. Excessive signal lines must be provided to allow different types of LSI's to be checked. Also, it is only possible to test the flip-flop circuits, i.e., it is not possible to check the basic gate cells constituting the logic gates and the flip-flop gates in the logic circuit. Finally, this method requires a change in the design of the test circuit and its wiring for each different type of LSI. SUMMARY OF THE INVENTION The primary object of the present invention is to provide a semiconductor integrated circuit device having an improved test circuit. Another object of the present invention is to provide a gate array type LSI having an improved test circuit enabling easy testing of the operation of the logic circuit. In accordance with the present invention, since the gate array has plural gate cells in the matrix, the row selection wires and the column read-out wires are prepared along the gate cells' array as the master pattern. After designing the connecting wires between the gate cells according to a customer's logic data, a final logic device is produced. In order to test the final device, the test circuit is used for checking the condition of every gate cell during the logic operation. There is provided a semiconductor integrated circuit device having a test circuit, including: a plurality of gate cells arranged in a matrix; wiring for connecting the gate cells so as to constitute a logic circuit; a plurality of row selection wires provided along the gate cells in a row direction, each of the gate cells being operatively connected to a row selection wire; a plurality of column read-out wires provided along the gate cells in a column direction, outputs of each of the gate cells being operatively connected to column readout wires; row selection means, operatively connected to said row selection wires, for selecting any of the row selection wires and for selecting any of the gate cells connected to the selected row selection wire; and output means for reading out the gate cells arranged in the logic circuit through a column read-out wire. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings; Fig. 1 is a schematic view of a semiconductor integrated circuit device according to an embodiment of the present invention; Fig. 2A shows in detail the circuit of switches and an output stage of a row selection ring counter shown in Fig. 1; Fig. 2B is a schematic structural view of a switch shown in Fig. 2A; Fig. 3 shows in detail switching circuits of a data selector shown in Fig. 1; Fig. 4 shows in detail the circuit of switches and a row selection ring counter according to another embodiment; Figs. 5A and 5B show in detail the circuits of the row and column selection ring counters shown in Fig. 1; Fig. 5C is a schematic view explaining the operation of the ring counters shown in Figs. 5A and 5B; ; Fig. 6 is a schematic view of a semiconductor integrated circuit device according to another embodiment of the present invention; and Fig. 7 shows in detail the circuit of a gate cell shown in Fig. 1. DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to the present invention will be explained in detail hereinafter. Figure 1 is a schematic view of a semiconductor integrated circuit device according to an embodiment of the present invention. In Fig. 1, reference numeral 1 represents a gate array type LSI. LSI 1 includes a plurality of basic gate cells 2 arranged in a matrix and a test circuit. The test circuit is constituted by a plurality of row selection wires 3, a plurality of column read-out wires 4, a plurality of switches 5, a row selection ring counter 6, a column selection ring counter 7, and a data selector 8. Each of the gate cells is constituted by, for example, a transistor-transistor logic (TTL) NAND circuit, as shown in Fig. 7. They are connected by wirings DW to constitute a logic circuit based on customer requirements, for example, as shown in Fig. 1. The data is input to the "INPUT" terminal, and a logic output is obtained from the "OUTPUT" terminal. Each row selection wire 3 is provided along the gate cells in the row direction, and each column read-out wire 4 is provided along the gate cells in the column direction. A switch 5 is provided at each intersection of the wires 3 and 4, so that the output of the corresponding gate cell 2 is connected to a column read-out wire 4 through the switch 5. The detailed structure of the switch 5 is shown in Fig. 2A. The row selection ring counter 6 is provided in order to sequentially select the row selection wires 3. A row selection clock is input to the input terminal 9. Similarly, the column selection ring counter 7 is provided in order to sequentially select column read-out wires 4. The column selection clock is input to the input terminal 10. These ring counters 6 and 7 are mainly constituted by a plurality of flip-flop circuits, as shown in detail in Figs. 5A and 5B. The column selection ring counter 7 and the data selector 8 constitute an output means. The data selector 8 is a kind of multiplexer and is constituted by a plurality of switch circuits SW, as shown in detail in Fig. 3. A column read-out wire 4 is selected by the column selection ring counter 7 and the selected switch circuit SW in the data selector 8 is turned on. Accordingly, the data of the selected gate cell 2 is output to the monitor output terminal 11 through the switch 5 at the intersection and the switch circuit SW in the data selector 8. As obvious from the drawing, only three external input and output pins are added to the LSI 1 for testing the logic circuit. That is, the input terminal pin 9 is provided to the ring counter 6 for inputting the row selection clock, the input terminal pin 10 to the ring counter 7 for inputting the column selection clock, and the monitor output terminal pin 11 to the data selector 8 for outputting the readout data. In the gate array design process, a master bulk is produced in advance so as to shorten the real production tie from receiving the customer's logic data to pro c'#cing the final device and to reduce the real pro action cost. Further, some part of the mask pattern of the wiring is also fixed in advance. Only the remaining tart of the wiring mask pattern is altered based on the custorner s design data (logic data). Now, turning back to Fig. 1, the designed portion is just the wiring patterns DW which connect the basic ate cells 2 so as to constitute the logic circuit. This designed portion is the above remaining part of the wring mask pattern. The other portion including the test circuits is prepared before designing the designed wirings DW. In the present invention, these prepared test circuits are constructed so as to be used after producing the actual device in which the designed wirings DW of the customer's logic data are formed on the prepared bulk. In the ordinary operation period of the logic circuit, all outputs of the row selection ring counter 6 are low level (non-selection level). Therefore, all switches 5 are turned OFF so as not to influence the operation of the logic circuit. That is, in the present invention, the row and column selection means, which corresponds to the row and column selection ring counter, has functions of the test mode and non-test mode, which modes are selectively switched. The operation of the test circuit will be explained below. With every input of a row selection clock to the row selection ring counter 6, the output "1" in the ring counter 6 is shifted as shown in Fig. 5C. A row selection wire 3 is selected corresponding to the output of the ring counter 6 which has become a high level "1". Accordingly, row selection wires 3 are sequentially selected by the output "1" of the ring counter 6. When a row selection wire 3 is selected, all switches 5 connected to the row selection wire 3 are turned ON. When a switch 5 is turned ON, the output data of the gate cell 2 appears on the column read-out wire 4. The column selection ring counter 7 selects one of the column read-out wires 4. The corresponding switch circuit SW in the data selector 8 is turned ON when an output of the ring counter 7 becomes a high level "1". The output data of the gate cell 2 is output to the monitor output terminal 11 through the selected column read-out wire 4. Accordingly, when a row selection wire 3 is fixed to the high level "1", all gate cells along the selected row selection wire 3 can be sequentially checked in the monitor output terminal 11 through the column read-out wire 4. Conversely, when a switch circuit SW in the data selector 8 is fixed ON, all gate cells along the selected column read-out wire 4 can be sequentially checked by sequentially selecting the row selection wires 3. Furthermore, by fixing both the ring counters 6 and 7, just the output of the specific gate cell 2 can be read out clock by clock of the original whole logic circuit operation. This means that a specific gate cell can be monitored in real time during the logic circuit operation. Figure 2A shows in detail the circuit of switches 5 and an output stage of the row selection ring counter 6. A switch 5 is constituted by two elements, for example, an n-p-n transistor T and a resistor R. The resistor R is connected between a row selection wire 3 and the base of the transistor T. The emitter E of the transistor T is connected to the output of the gate cell 2 and the collector C is connected to a column read-out wire 4. In this case, as shown in Fig. 2B, the resistor R is formed by extending the base diffusion area B of the transistor T. Thus, the switch 5 is actually constituted by one element. In the figure, E represents an emitter area, B a base area, and C a collector area. The output stage of the row selection ring counter 6 includes transistors (T1 , T2 Ta and Tb) resistors fE# to R4), and a diode D1. In this case, the tran itors Ta and Tb are Schottky barrier transistors. An output stage is provided for every row selection wire 3. hen the transistor T1 is turned ON, the output point P becomes a high level "1" and the row selection wire 3 becomes selected. When the transistor T2 is turned ON, the output point P becomes a low level "0" and the row selection wire 3 becomes non-selected. When the row selection wire 3 becomes non-selected, i.e., low level, the transistor T is turned OFF in spite of the output level of the gate cell 2. On the other hand, when the row selection wire 3 becomes selected, i.e., high level, the base of the transistor T in the switch 5 becomes high and the transistor T is turned ON or OFF according to the output level of the gate cell 2. Accordingly, the output data of the gate cell 2 appears on the column read-out wire 4 through the transistor T. Figure 3 shows in detail the switching circuits SW of the data selector 8. A switching circuit SW is provided at the end of each column read-out wire 4. Each switching circuit SW is constituted by two transistors T3 , T4 and two resistors. All collectors of the transistors T3 are connected to the input terminal IN of an output buffer 13 through a common data wire 12. The transistor T4 is connected between the base of the transistor T3 and the output terminal 14 of the ring counter 7. The transistors T3 , T4 of switching circuit SW constitute a NAND gate circuit with the transistor T of the switch 5. When the output terminal 14 is low (non-selected state), the transistor T4 is turned ON and the transistor T3 is turned OFF. When the output terminal 14 is high (selected state), the transistor T4 is turned OFF and the transistor T3 is turned ON or OFF depending on the "1" or NOt of the output data of the gate cell 2 transmitted through the transistor T of the switch 5. That is, when the output of the gate cell 2 is high, the transistor T3 is turned ON. Conversely, when the output of the gate cell 2 is low, the transistor T3 is turned OFF. Accordingly, when the transistor T3 is turned ON, a low level signal appears on the data wire 12. When the transistor T3 is turned OFF, a high level signal appears on the data wire 12. The output buffer 13 outputs a low or high level signal from the monitor output 11 corresponding to the high or low level of the data wire 12. Consequently, the operation of the logic circuit 1 shown in Fig. 1 can be checked by the output of the monitor terminal 11. That is, the output of the gate cell 2 at each intersection is sequentially checked to see if it is the expected value (designed value). If it is, the logic circuit of the previous stage of the checked gate cell is correctly operating. Accordingly, the entire logic circuit 1 can be tested by checking sequentially each output of the gate cell 2 at the monitor terminal 11. Also, if both the selection ring counters 6 and 7 are fixed, a specific gate cell output can be monitored during the logic circuit operation so that the logic level of the predetermined point of the entire logic circuit can be monitored in real time. Figure 4 shows detailed circuits of the switch and the row selection ring counter 6 according to another embodiment. In this embodiment, the switch 5 is constituted by one element, i.e., a metal-oxide semiconductor (MOS) type transistor Q. Each output stage of the row selection ring counter 6 is constituted by a complementary MOS (CMOS) type inverter having MOS transistors Q1 and Q2 instead of the two transistors T1 , T2 and the diode D1 and the resistor R1 shown in Fig. 2A. The circuit structure of this embodiment is simpler than the first embodiment. Figures 5A and 5B show in detail the circuits of the row and column selection ring counters 6 and 7. In Fig. SA, reference numerals 21 to 24 represent D type lip-flop circuits, 25 an AND gate, and 26 an OR gate. The D type flip-flop circuits 21 to 24 are connected in Eer es through the Q outputs. As can be understood, the Q outputs correspond to the outputs of the output stages of the ring counter 6 or 7 shown in Figs. 2A and 4. The selection of the row or the selection of the column is performed according to the high or low level of the Q outputs. The data of the Ç output of the final-stage flipflop circuit 24 is fed back to the D input of the first-stage flip-flop circuit through the OR gate 26. Inverted data of the Q outputs (Q) are also input to the D input of the flip-flop circuit 21 through the AND gate 25 and the OR gate 26. These flip-flop circuits 21 to 24 are driven by a common clock signal (reset signal mentioned above) input to each of the CK terminals in the flip-flop circuits. As shown in Fig. 5C, it is necessary to obtain an all "O" Q output state at the beginning. To obtain an all tlQfl state, a reset signal is commonly input to the clear terminals CR in the flip-flop circuits. When all Q outputs are "0", all Q outputs become "1". Accordingly, the AND gate 25 outputs "1", the OR gate outputs t and this output "1" is fed back to the D input of the flip-flop circuit 21. In this state, when the next clock signal is input, since the Q output of the firststage flip-flop circuit 21 becomes "1" and the Q output becomes "0", the output of the AND gate 25 becomes "0". At this point, since all Q outputs of the flip-flop circuits 22 to 24 maintain the "0" state, the output state of the ring counter becomes "1,0,0,0", as shown in Fig. 5C. The Q output "1" is shifted toward the right with each sequential clock signal. As obvious from Fig. 5C, the ring counter becomes "0" whenever the reset signal is input and restarts from the output "1,0,0,0" by the next clock signal. The output of the ring counter circulates between "1,0,0,0" and "0,0,0,1" until the next reset signal is input. The condition in which all Q outputs become the "0" state means a non-test mode, which does not affect the normal logic function of the gate array logic circuit. The condition in which any one of the Q outputs is the "1" state means a test mode which selects one of the row selection wire or column read-out wire. Figure 5B shows another embodiment of the ring counter. In this embodiment, the flip-flop circuit 27 is provided at the input portion to generate "1" instead of the AND gate 25. At the beginning, all Q outputs of the flip-flop circuits 21 to 24 are set to "0" by the reset signal. At the same time, the flip-flop circuit 27 is preset to "1". This preset signal "1" is applied to the D input of the flip-flop circuit 21 through the OR gate 26. When the next clock signal is input, the Q output of the fXip-flop 27 returns to "0" by the D input level, which is fixed to low level "L". The same operation as explained in Fig. 5A is performed until the next reset signal is input. Figure 6 is a schematic view of a semiconductor integrated circuit device according to another embodiment of the present invention. In this embodiment, all gate cells 2 are divided into, for example, four blocks 1 to 4. In this case, a row selection ring counter (ROW CTR I) 6a is provided for the upper half portion and the row selection ring counter (ROW CTR II) 6b for the lower half portion. A column selection ring counter and data selector are provided for each of blocks 1 to 4. That is, a column selection ring counter (COLUMN CTR 1) 7a and data selector (SEL 1) Ba are provided for the block 1, a column selection ring counter (COLUMN CTR 2) 7b and data selector (SEL 2) 8b for block 2, a column selection ring counter (COLUMN CTR 3) 7c and data selector (SEL 3) 8c for block 3, and a column selection ring counter (COLUMN CTR 4) 7d and data selector (SEL 4) 8d for block 4. In this case, the necessary time for scanning all gate cells is shortened to a quarter compared with the first embodiment shown in Fig. 1, because the number of clocks for the row and column selection is reduced to half. However, three external output pins are added for each monitor output. The added monitor output pins are shown by reference numerals 31 to 33. Moreover, although the column selection ring counter 7 and the data selector 8 are used as the output means for selecting column read-out wires 4 in these embodiments, the output means can be replaced with a shift register which has the same number of bits as the number of column read-out wires. That is, a parallelin/serial-out type shift register may be used for such a register instead of the column selection ring counter and the data selector. In this case, the sequential monitor output can be obtained from the shift register. Figure 7 shows in detail the circus of the gate cell 2. This circuit is a typical three-input TTL-NAND gate circuit. In Fig. 7, TR1 is a multiemitter transistor. A low or high input signal is input to each of the emitters. TR2 is a phase splitter transistor, and TR4 and TR5 are output transistors. A Darlington connection is formed by the transistors TR3 and TR4. In accordance with the structure of the present invention, first, it is possible to check the basic gate cells, not just the flip-flop circuits. Second, it is possible to reduce the number of external pins required for the testing because ring counters are used as row and column selection means, unlike in the conventional scan pass method, wherein an address decoder is used. Third, it is not necessary to serially scan all the flip-flop gates which construct the shift registor for the test operation as in the conventional LSSD method because the rows and columns are selected by ring counters so as to access the specific gate cell directly. Finally, the test circuit does not substantially affect the logic circuit, because the test circuit is turned OFF when no gate cells are selected for checking. Moreover, it is very easy to design the logic circuit because only a switch needs to be added to each gate cell.

Claims: CLAIMS 1. A semiconductor integrated circuit device having a test circuit comprising: a plurality of gate cells arranged in a matrix; wiring means for connecting the gate cells so as to constitute a logic circuit; a plurality of row selection wires provided along said gate cells in a row direction, each of said gate cells being operatively connected to said row selection wire; a plurality of column read-out wires provided along said gate cells in a column direction, outputs of each of said gate cells being operatively connected to column read-out wires; row selection means, operatively connected to said row selection wires, for selecting any of said row selection wires and for selecting any of said gate cells connected to said selected row selection wire, and output means for reading out said gate cells arranged in said logic circuit through a column read-out wire. 2. A semiconductor integrated circuit device as claimed in claim 1, further comprising switching means, each means connected between a row selection wire and gate cell, said means being turned ON/OFF by said row selection means. 3. A semiconductor integrated circuit device as claimed in claim 1, wherein said row selection means comprises a ring counter constituted by a plurality of flip-flop circuits. 4. A semiconductor integrated circuit device as claimed in claim 1, wherein said output means comprises a column selection means and a data selector. 5. A semiconductor integrated circuit device as claimed in claim 1, wherein said output means comprises a shift register. 6. A semiconductor integrated circuit device as claimed 2, wherein said switching means is further connected between each said row selection wire and column read-out wire. 7. A semiconductor integrated circuit device as claimed in claim 4, wherein said column selection means comprises a ring counter constituted by a plurality of flip-flop circuits. 8. A semiconductor integrated circuit device as claimed in claim 2, wherein said switching means comprises an n-p-n type transistor and a resistor. 9. A semiconductor integrated circuit device as claimed in claim 8, wherein said resistor is formed by extending a base diffusion area of said n-p-n type transistor. 10. A semiconductor integrated circuit device as claimed in claim 2, wherein said switching means comprises an MOS type transistor. 11. A semiconductor integrated circuit device as claimed in claim 1, wherein said logic circuit is divided into at least four blocks, each block provided with said row selection means and said output means.

Inventors: OHBA, OSAM, YOSHIDA, MAKOTO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G01R31
IPC codes: H01L21, G01R31, H01L27, G01L27