Image sensor device

Abstract: An image sensor device provided with a linear array of photoelectric converting elements each having a capacitor on a control electrode area of a semiconductor transistor is disclosed. The image sensor device is provided with means for sequentially selecting the photoelectric converting elements, and the potential of the control electrode area of the selected photoelectric converting element is controlled through said capacitor, thereby accumulating the carriers generated by photoexcitation in said control electrode area and reading a voltage generated according to the amount of carrier accumulation or dissipating thus accumulated carriers.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an image sensor device in which arranged two-dimensionally are photoelectric converting elements (hereinafter called photosensor cells) each having a capacitor on the control electrode area of a semiconductor transistor. Description of the Prior Art Recent developments on image sensor device have been principally conducted on CCD type and MOS type. The CCD image sensor device is based on a principle that potential wells are formed under MOS capacitor electrodes for accumulating electric charges generated by the entering light, and, in signal reading, said potential wells are moved in succession by pulses supplied to the electrodes thereby transferring the accumulated charges to an output amplifier. On the other hand, the MOS image sensor device is based on a principle that electric charges generated by the entering light are accumulated in photodiodes constituting a light-receiving area and each comprising a p-n junction, and, in signal reading, MOS switching transistors respectively connected to said photodiodes are turned on in succession to transfer the accumulated charges to an output amplifier. However such conventional image sensor devices have been associated with following drawbacks which will be a major obstacle in achieving a higher sensitivity and a higher resolving power in the future. More specifically, the CCD image sensor devices have drawbacks that (1) the MOS output amplifier formed on a same chip tends to generate, from the interface between silicon and a silicon oxide layer, 1/f noises which are easily noticeable on the image. (2) the maximum charge that can be accumulated in a potential well is reduced and the dynamic range becomes smaller if the number of cells are increased with a higher density in order to achieve a higher resolving power, and (3) the sequential charge transfer is interrupted if only one cell is defective. On the other hand, the MOS image sensor devices have drawbacks that (1) a large drop in the signal voltage occurs at the signal reading since a wiring capacitance is connected to each photodiode, (2) a large wiring capacitance tends to generate random noises, and (3) noises of a fixed pattern are present because of fluctuation in the parasitic capacitances of the MOS switching transistors. Thus, for example in a two-dimensional solid-state image sensor device, image taking under a low illumination becomes difficult, and a size reduction of the cells for achieving a higher density deteriorates the S/N ratio since the wiring capacitance is not significantly reduced while the accumulated charge becomes smaller. In this manner the CCD and MOS image sensor devices are associated with fundamental problems in achieving a higher resolving power. On the other hand, there has been proposed a new semiconductor image sensor device (European Patent Application published as 0132076 published after the present priority date) in which electric charges generated by the entering light are accumulated in control electrodes, for example bases of bipolar transistors or gates of static induction transistors (SIT) or MOS transistors, and the accumulated charges are amplified at signal reading by the amplifying function of the cells. This structure can provide a high output, a wide dynamic range, a low noise level and a non-destructive signal reading, thus leading to a possibility for a higher resolving power. EP0311346 shows a similar device. However there is a certain limit in the resolving power since this structure, if employed in a two-dimensional image sensor device, is fundamentally based on x-y addressing, and each cell is basically composed of a conventional MOS cell combined with an amplifying element such as a bipolar transistor or a SIT transistor. Also in case a large number of cells are arranged for achieving a high resolving power, a high-speed function is difficult to achieve because shift registers for reading the output signals become complicated. Besides, the S/N ratio becomes lower though the output impedance becomes higher. Also a one-dimensional image sensor device is associated with certain drawbacks which will be explained in the following in relation to the accompanying drawings. Fig. 1 is a circuit diagram of a conventional one-dimensional image sensor device containing an array of plural photosensor cells, in which electric charges are accumulated in capacitors electrically connected to control electrode areas. Referring to Fig. 1, said photosensor cells 101 are linearly arranged, and output terminals thereof are connected, through MOS transistors 5 l - 5 n , to a common output line 20. Said common output line 20 is connected to an output terminal 22 through an output amplifier 21, and is also grounded through a line-refreshing MOS transistor 24. The gates of the MOS transistors 5 l - 5 n are respectively connected to terminals 7 l - 7 n of a logic circuit 19. In such conventional image sensor device, the optical information signals of the photosensor cells 101 are serially released through the common output line 20 and the output amplifier 21 by serial activation of the MOS transistors 5 l - 5 n . The time required for signal reading from a photosensor cell 101 is proportional to the floating capacitance of the common output line 20. Consequently, the total time required for signal reading rapidly increases with an increase in the number n of the photosensor cells 101. In this manner, in the conventional structure, the high-speed signal reading operation becomes difficult to achieve, when the number n of the photosensor cells is increased in order to achieve a high resolving power. Furthermore, in the above-explained photosensor cell 101 in which the electric charge generated by photoexcitation is accumulated in the control electrode, the accumulated charge has to be dissipated for refreshing, after the signal reading is completed. Such refreshing operation has been conducted at the same time for all the photosensor cells 101, so that, particularly in a two-dimensional image sensor device, the time from said refreshing operation to the start of signal reading is different for all photosensor cells 101, and for this reason it has been difficult to achieve a high-speed operation and a uniform photoelectric converting property. DE-A-3345238 discloses a solid state image pick up device constructed by arranging a plurality of isolated gate static induction transistor (SIT) elements arranged in a matrix, with gate electrodes connected to gate signal lines through respective capacitors and drain electrodes connected to respective signal read-out lines. Respective signal read-out lines are connected through read-out line control switches and sampling gate switches to corresponding register units of a CCD shift register. SIT's of the same row are connected to the same gate signal line and SIT's of the same column are connected to the same signal read-out line. Light output signals are simultaneously read out from the SIT elements of the same gate signal line and the signals are simultaneously stored in the shift register and are converted into time series signals during the period until the next light output signals are simultaneously read out from SIT elements of the next gate line. For reset, signal pulses are supplied to a gate line so as to forward bias the junction between the gate and the source of the SIT elements. It is proposed that the CCD shift register may be replaced by a construction in which respective signal read-out lines are provided with capacitors for holding read-out signals, and these capacitors are successively scanned by transistors driven by a digital shift register. SUMMARY OF THE INVENTION According to the present invention there is provided a photosensor device as set out in claim 1. The remaining claims set out optional features. An embodiment of the present invention provides an image sensor device which can easily provide a high output level, a high sensitivity, a low noise level and a high resolving power. An embodiment of the present invention provides an image sensor device capable of high-speed signal reading even when the number of the photosensor cells is increased. An embodiment of the present invention provides an image sensor device which is provided with a stable photoelectric converting property and provides a high output level, a resolving power and a high-speed signal reading operation. An embodiment of the present invention provides a solid-state image sensor device which makes it possible to attain a high cell density and to obtain a wide dynamic range combined with significantly reduced blooming and smear. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a conventional image sensor device; Fig. 2A is a cross-sectional view of a photosensor cell of a sensor constituting an embodiment of the present invention, while Fig. 2B is an equivalent circuit diagram of said photosensor cell; Fig. 3 is a circuit diagram of a line sensor illustrated to assist explanation; Fig. 4 is a timing chart showing the function of the line sensor of Fig. 3; Fig. 5A is a cross-sectional view of an alternative photosensor cell, while Fig. 5B is an equivalent circuit diagram of said photosensor cell; Fig. 6 is a circuit diagram of a line sensor using the cell of Fig. 5, illustrated to assist explanation; Fig. 7 is a timing chart showing the function of the line sensor of Fig. 6; Fig. 8 is a chart showing the function sequence of an embodiment of the image sensor device of the present invention; Fig. 9 is a circuit diagram of the embodiment of the image sensor device of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be clarified in detail by the embodiment thereof shown in Fig. 9. Fig. 2A is a cross-sectional view of a photosensor cell in an embodiment of an image sensor device , and Fig. 2B is an equivalent circuit diagram of said photosensor cell. Referring to Fig. 2A, on a silicon substrate 1 which is rendered n or n+ type by doping with an impurity such as phosphorus (P), antimony (Sb) or arsenic (As), there are formed an array of photosensor cells each of which is electrically insulated from the neighboring ones by means of separating areas 2 composed of SiO 2 , Si 3 N 4 or polysilicon. On the photosensor cells there is formed a passivation layer 13 composed for example of a PSG layer. The structure of each photosensor cell is as follows. On an n - -type area 3 of a low impurity concentration formed for example by epitaxy, a p-type area 4 is formed by doping with a p-type impurity, and, in a part of said p-type area 4 there is formed an n + -type area 5 by impurity diffusion or by ion implantation. Said p-type area 4 and n + -type area 5 respectively constitute the base and emitter of a bipolar transistor. Above said n - -type area 3 there is formed an oxide layer 6, on which formed is a capacitor electrode 7 of a determined area. Said capacitor electrode 7 faces said p-type area 4 across an oxide layer 8, whereby the potential of the floating p-type area 4 can be controlled by pulse voltages applied to the capacitor electrode 7. There are further provided an emitter electrode 8 connected to the n + -type area 5; an unrepresented wiring for releasing the signals to the exterior from said emitter electrode 8; an unrepresented wiring connected to the capacitor electrode 7; an n + -type area 11 of a high impurity concentration formed on the rear face of the substrate 1; and an electrode 12 for supplying a potential to the collector of the bipolar transistor. In the following there will be explained the basic function. Light 13 irradiates the p-type area 4 constituting the base of the bipolar transistor, whereby a charge, composed of holes in this case, corresponding to the quantity of incident light, is accumulated in the p-type area 4 (accumulating operation). The accumulated holes shift the base potential to positive. Then a positive signal reading voltage Vr is applied to the capacitor electrode 7 to bias the p-type area 4 positively, whereby the p-type area 4 in which the holes are accumulated is biased in forward direction with respect to the n + -type area 5. Thus a current by electrons flows from the n + -type area 5 to the n - -type area 3, so that the n + -type area 5 and the emitter electrode 8 in the floating state shows an increase in the potential. Thus an electric signal corresponding to the amount of incident light can be obtained by reading said change in the potential of the emitter electrode 8 (signal reading operation). The charge accumulated in the p-type area 4 can be eliminated by grounding the emitter electrode 8 and applying a positive pulse of a positive voltage Vf to the capacitor electrode 7, whereby the p-type area 4 is biased in the forward direction with respect to the n + -type area 5 and the accumulated charge is dissipated (refreshing operation). Thereafter the above-mentioned steps of accumulation, readout and refreshing are repeated. In short, the above-explained photosensor cell is based on a principle that the electric charge generated by the incident light is accumulated in the p-type area 4 constituting the base, and the current from the emitter 8 to the collector 12 is controlled by thus accumulated charge. Consequently the charge is read after an amplification by the amplifying function of each cell. This process provides a high output level, a high sensitivity and a low noise level and is promising for a higher resolving power in the future. Fig. 3 is a circuit diagram of a line image sensor not embodying the present invention and illustrated to assist explanation. In Fig. 3, photosensor cells SC1 - SCn of the structure shown in Fig. 1A have mutually connected collector electrodes 12. Capacitor electrodes 7 are connected, respectively through switching transistors Tr1 - Trn, to output terminals Sr1 - Srn for signal readout of a shift register 101, and further connected, respectively through switching transistors Tf1 - Tfn, to output terminals Sf1 - Sfn for refreshing of said shift register 101. The gates of the switching transistors Tr1 - Trn are commonly connected to a terminal 102, while those of the switching transistors Tf1 - Tfn are commonly connected to a terminal 103. Said terminals 102 and 103 respectively receive two-phase clocks 1 and 2 to turn on and off said switching transistors in synchronization with said clock signals. The shift register 101 is connected with terminals 102, 103 and 104 to receive the above-mentioned clock signals 1 and 2 and to receive a start pulse PS from the terminal 104. In synchronization with the two-phase clock pulses 1 and 2, the output terminals Sr1 - Srn of the shift register 101 in succession release signal reading pulses of a voltage Vr while the output terminals Sf1 - Sfn release refreshing pulses of a voltage Vf as will be explained later. The emitter electrodes 8 of the photosensor cells SC1 - SCn are commonly connected to a signal readout line 105, which is connected to an input terminal of an output amplifier 106 and is grounded through a switching transistor 107. Said switching transistor 107 is provided to dissipate the charge on the signal readout line, and receives, through the gate thereof, a clock signal r determining the timing of charge dissipation. In the following there will be given an explanation on the function of the above-explained line sensor arrangement , while making reference to a timing chart shown in Fig. 4. It is assumed that charges corresponding to the incident light are already stored in the base areas 4 of the photosensor cells SC1 - SCn through the accumulating step explained above. At first a start pulse PS is supplied to the shift register 101, and a clock signal 1 is supplied to said shift register 101 and to the gate of the switching transistor Tr1. The clock 1 turns on the switching transistor Tr1, and, in synchronization with said clock 1 a signal readout pulse of a voltage Vr is released from the terminal Sr1 of the shift register 101. Said signal readout pulse is transmitted through the switching transistor Tr1 in the on-state and is supplied to the capacitor electrode 7 of the photosensor cell SC1. In response there is conducted a signal readout operation as explained before whereby the emitter 8 of the photosensor cell SC1 releases a signal representing optical information, which is supplied through the line 105 to the output terminal after amplification in the output amplifier 106. Upon completion of signal readout from the photosensor cell SC1, the switching transistor 107 is turned on by the clock r to ground the signal readout line 105, thus dissipating the charge accumulated in the wiring capacitance. Simultaneously, in response to the clock 2, the terminal Sf1 of the shift register 101 releases a refreshing pulse of a voltage Vf, which is transmitted through the switching transistor Tfl turned on by said clock 2 and supplied to the capacitor electrode 7. In this manner the charges accumulated in the photosensor cell SC1 and in the signal readout line 105 are eliminated. Subsequently, in response to a clock 1, the terminal Sr2 supplies a pulse of the voltage Vr to the capacitor electrode of the photosensor cell SC2, thus effecting the signal readout thereform. Upon completion of said signal readout, the photosensor cell SC2 is refreshed by a clock 2, while the signal readout line 105 is refreshed by a clock r. In this manner the optical information of all the photosensor cells SC1 - SCn can be serially read by effecting the signal readout and refreshing for each photosensor cell in synchronization with the clocks 1 and 2. Since each photosensor cell is refreshed at the completion of the signal readout operation, the photosensor cells can collectively enter the accumulating operation when the signal readout and refreshing for the last cell SCn are completed. Thereafter the above-explained steps are repeated. Fig. 5A is a cross-sectional view of an alternative photo-sensor cell , and Fig. 5B is an equivalent circuit diagram of said photosensor cell. In this arrangement, at the elimination of the accumulated holes, the p-type area 4 is set at a determined potential by a MOS transistor to achieve complete refreshing. As shown in Fig. 5A, the refreshing MOS transistor is composed of main electrode areas consisting of a p-type area 4 and a p-type area 41 formed on an n - -type epitaxial layer 3, and the capacitor electrode 7 positioned across an oxide layer 6 serves as the gate. Thus, in the present arrangement, the MOS transistor is turned off when a positive voltage is supplied to the capacitor electrode 7 but is turned on to connect the electrode 42 with the p-type area 4 when a negative voltage exceeding a determined threshold value is supplied. Fig. 6 is a circuit diagram of an image sensor device using the cell of Fig. 5. In Fig. 6, photosensor cells SC1 - SCn are respectively provided with refreshing MOS transistors T1 - Tn. The capacitor electrodes 7 of the photosensor cells are connected, respectively through switching transistors Trf1 - Trfn, to output terminals S1 - Sn of a shift register 201, and the gates of said transistors Trf1 - Trfn are commonly connected to a terminal 202 for effecting on-off operations by clocks  rf . In synchronization with said clocks  rf , the shift register 201 releases a signal readout pulse of a positive voltage Vr and a succeeding refreshing pulse of a negative voltage -Vf, in succession, from the terminals S1 - Sn. Electrodes 42 of the photosensor cells SC1 - SCn are commonly connected to a terminal 203, receiving a determined refreshing voltage Vrf. Other components same as those in Fig. 3 are represented by same numbers and will not be explained further. In the following there will be given an explanation on the function of the above-explained arrangement, while making reference to a timing chart shown in Fig. 7. When the switching transistor Trfl is turned on by a clock rf, the terminal S1 of the shift register 201 releases a signal readout pulse of a positive voltage Vr, which is supplied, through said switching transistor Trf1, to the capacitor electrode 7 of the photosensor cell SC1. Because of said positive voltage Vr the MOS transistor Tl remains turned off, and the photosensor cell SC1 effects a signal readout operation explained above. Subsequently the terminal S1 supplies a refreshing pulse of a negative voltage -Vf to the capacitor electrode 7 of said photosensor cell SC1 to turn on the MOS transistor T1, whereby the base area 4 releases the charge accumulated therein through the electrode 42 and is set at a determined potential Vrf. Simultaneously with said refreshing operation, the switching transistor 107 is turned on to refresh the signal readout line 105. The above-explained operations are effected in succession in the photosensor cells SC1 - SCn and the optical information is serially released from the output terminal. This arrangement allows to arbitrarily select the potential of the base area 4 and to achieve complete refreshing by suitably selecting the refreshing voltage Vrf. Though the MOS transistors Tl - Tn are formed in the photosensor cells, they may also be formed on the separating areas 2. It is also possible to form said separating area 2 with a semiconductor of the same conductive type as the base area 4 to achieve insulation by a p-n junction and to form a refreshing MOS transistor by maintaining said separating area at a potential Vrf. In the following there will be explained an embodiment of the present invention, employing the photosensor cells of a structure shown in Fig. 2A. Fig. 9 is a circuit diagram of the embodiment of the present invention, in which shown are phototransistors 901 11 - 901 mn and capacitors 902 11 - 902 mn for transmitting control signals to said phototransistors, both two-dimensionally arranged in n columns and m rows; and sample-hold circuits 906 1 -906 n composed of MOS transistors 903 1 - 903 n for controlling the output signals from the emitters of the phototransistors 901 11 - 901 mn , capacitors 904 1 -904 n connecting main electrodes of said MOS transistors 903 1 - 903 n with a power input terminal 915, MOS transistors 909 1 - 909 n of which gates are connected to the main electrodes of said MOS transistors 903 1 - 903 n , MOS transistors 905 1 - 905 n of which main electrodes are respectively connected to the MOS transistors 909 1 - 909 n and to the power input terminal 925 and of which gates are respectively connected to the terminals 907 1 - 907 n of a logic circuit 919, and resistors 908 1 - 908 n connected at ends thereof to the other main electrodes of the MOS transistors 909 1 - 909 n and to a common output line 920 and connected at the other ends to the power input terminal 915. There are further provided a control signal input terminal 917 for supplying control signals to the photosensor cells; a control signal input terminal 916 for supplying control signals to the MOS transistors 903 1 - 903 n ; a positive voltage input terminal 918; an output terminal 922; a control input terminal 926 for supplying control signals to the MOS transistors 910 1 - 910 n ; and a power input terminal 927. In the following there will be explained the function of the embodiment shown in Fig. 9. As already explained before, the phototransistors 901 11 - 901 mn achieve photoelectric conversion by a basic function consisting of an accumulation step, a signal readout step and a refreshing step. In Fig. 9 it is assumed that all the MOS transistors are of n-channel type, that the positive voltage input terminal 918 and the power input terminal 925 receive positive voltages, and that the input terminals 915 and 927 are grounded. In the accumulation step, an H-level signal is supplied to the control input terminal 926 to turn on the MOS transistors 910 1 - 910 n , thereby grounding all the emitters of the phototransistors 901 11 - 901 mn . Also a positive voltage is supplied to the input terminal 918 to positively bias all the collectors of said phototransistors, and a pulse of a positive voltage V RF is supplied from arbitrary one of the control signal input terminals 917 1 - 917 m during a refresh operation to bias the bases of the phototransistors 901 11 - 901 mn at a determined negative potential for the accumulation step. In this state the photosensor cells are irradiated with light to accumulate holes in the base areas. The pulse for negatively biasing the bases of the phototransistors 901 11 - 901 mn may be given to one row or plural rows at a time. In the signal readout, an H-level signal is supplied to the control signal input terminal 916 to turn on the MOS transistors 903 1 - 903 n and an L-level signal is supplied to the control signal input terminal 926 to turn off the MOS transistors 910 1 -910 n , whereby all the emitters of the phototransistors 901 11 - 901 mn are left floating, and a positive bias voltage is supplied through the positive voltage input terminal 918 to positively bias all the collectors of the phototransistors 901 11 - 901 mn . In this state pulses of a positive voltage V RE are supplied in an arbitrary or sequential order to the control signal input terminals 917 1 - 917 m . When the pulse of voltage V RE is supplied to an input terminal 917 i , the outputs of the phototransistors 901 i1 - 901 in are held in the capacitors 904 1 - 904 n of the sample-hold circuits 906 1 - 906 n and the accumulated voltages in said capacitors 904 1 - 904 n are applied to the gates of the MOS transistors 909 1 - 909 n . The signal readout from the sample-hold circuits 906 1 - 906 n to the output terminal 922 is effected by supplying an L-level signal through the control input terminal 916 to turn off the MOS transistors 903 1 - 903 n and releasing H-level signals in succession from the output terminals 907 1 - 907 n of the logic circuit 919, thereby turning on the MOS transistors 905 1 - 905 n in succession. Thus, in response to an H-level signal from the output terminal 907 1 of the logic circuit 919, the MOS transistor 905 1 is turned on to apply the positive voltage at the terminal 925 to the MOS transistor 909 1 . Consequently a current corresponding to the voltage applied to the gate is generated between the main electrodes of the MOS transistor 909 1 , thus generating a voltage, across the resistor 908 1 , corresponding to the accumulated voltage in the capacitor 904 1 , and said voltage is released from the output terminal 922 as an optical information signal. Thereafter the voltages accumulated in the capacitors 904 2 - 904 n are released in succession through the output terminal 922. After the signal readout of an i-th row, the phototransistors 901 i1 - 901 in and the capacitors 904 1 - 904 n are refreshed by entering an H-level signal to the control input terminal 916 to turn on the MOS transistors 903 1 - 903 n and entering an H-level signal through the control input terminal 926 to turn on the MOS transistors 910 1 - 910 n , whereby the capacitors 904 1 - 904 n are discharged through the MOS transistors 903 1 - 903 n and 910 1 - 910 n . Similarly the phototransistors 901 i1 - 901 in are refreshed by applying the positive voltage V RF to the input terminal 917 i . Upon completion of the refreshing operation explained above, the phototransistors 901 i1 - 901 in initiate the accumulating operation. Simultaneously the signal readout and refreshing are effected in the above-explained manner for the phototransistors 901 j1 - 901 jn of a j-th row. Since the optical information signals of each row are collectively held in the capacitors 904 1 -904 n and then are serially released, it is possible to simultaneously effect the signal readout and refreshing of a row and the accumulation for other plural rows. The signal readout and refreshing need not necessarily be effected for each row in turn but may be effected for plural rows at a time. The above-explained circuit of Fig. 9, constituting the embodiment of the present invention, is characterized by the fact that the refreshing and accumulation for different rows and the signal readout from the sample-hold circuits can be simultaneously conducted. Consequently the photoelectric conversion can be achieved in a sequence in which the time from the refreshing to the signal readout is maintained constant in any row. Fig. 8 is a chart showing the operating sequence, for further clarifying the function of said embodiment. In Fig. 8, R indicates the signal readout operation from the phototransistors to the sample-hold circuits 906 1 - 906 n ; RSH indicates a period of signal readout from the sample-hold circuits 906 1 - 906 n to the output terminal 922 and refreshing of the photo-transistors; ST indicates the accumulating period; and W indicates that the signal readout is conducted on certain phototransistors outside the row of said symbol W. More specifically, in the period W, the base of the phototransistor is maintained negative to effect the accumulating operation, but the emitter is shifted to a positive potential because the signal readout is conducted from the emitter of phototransistors of another row to the sample-hold circuits. However the potentials of the emitter and base are still maintained in an inverse bias state, as in the accumulation. In Fig. 8 it is particularly noteworthy that the distance between two neighboring R's is constant in any row, and this fact is particularly meaningful when the number m of rows is increased, or when the number of photosensor cells is increased. There is required a long time for the signal readout from the 1st row to the last m-th row if the number M of row is large. Thus, if the accumulation and readout are effected after simultaneous refreshing for all rows, the last row will have a longer accumulation time and will therefore show a different photoelectric converting characteristic in comparison with the first row. Such drawback does not appear in the circuit of Fig. 9 and sequence of Fig. 8 as the period from refreshing to signal readout is constant in any row. Though the MOS transistors in the embodiment shown in Fig. 9 are composed of N-channel MOS transistors, it is also possible to employ P-channel MOS transistors or complementary circuits in which N- and P-channel MOS transistors are combined. Also the cathode-follower amplifiers employed in the sample-hold circuits may be replaced by other amplifiers such as differential amplifiers. The image sensor device of the present embodiment is capable of a high-speed signal readout operation even for an increased number of photosensor cells, thus providing a high-speed operation combined with a high resolving power, since the signals from plural photosensor cells are temporarily retained in holding means and then released sequentially. Also in the two-dimensional array, the photosensor cells can have a uniform accumulation time, thus ensuring a stable photoelectric converting characteristic, because each photosensor cell can be refreshed immediately after the signal readout operation. Also a high-speed operation is rendered possible because of the absence of idle time after the completion of signal readout as in the conventional structure.

Claims: A photosensor device comprising: a plurality of phototransistors (901) arranged in rows and columns, each phototransistor (901) having a control region (4), first and second main regions (1, 5) and an electrode (7) capacitively coupled to the control region (4), and being arranged to accumulate charge carriers in the control region (4) in response to photo-excitation; a plurality of column output lines, each connected to the first main region (5) of a plurality of phototransistors (901) in a respective column; a capacitor (904) in a respective sample-hold circuit (906) for each column output line, for storing signals read from the phototransistors; a first switch means (903) in the respective sample-hold circuit (906), connected in each column output line between the said capacitor (904) and the said first main regions, for reading out from the first main regions (5) of the phototransistors (901) connected to the respective column output line signals corresponding to the accumulated charge carriers in the control regions (4), and storing the read-out signals on the respective said capacitor; output means (905, 909, 919, 920) for subsequently supplying output signals serially to an output in accordance with respective signals stored on the capacitors; and a plurality of row control lines for carrying read control signals to select a row of phototransistors (901) from the first main regions (5) of which signals are to be read out by the first switch means (903) and for carrying reset control signals to select a row of phototransistors (901) to be refreshed during a refresh operation, characterised in that the phototransistors (901) are bipolar transistors and the first main regions (5) are emitters, the second main regions (1) are collectors, and the control regions (4) are bases, in that the photosensor device comprises a respective second switch means (910) for each column output line, connected on the side of the first switch means (903) remote from the respective capacitor (904), for applying a reference potential to the emitters (5) of the phototransistors connected to the respective column output line, and in that the photosensor device comprises reset means for operating the first and second switch means to apply the reference potential, during a refresh operation for a row of phototransistors (901) selected by the reset control signals, to both the emitters (5) of the phototransistors of the selected row and the capacitors (904) on which the signals from the emitters were stored. A photosensor device according to claim 1 comprising biassing means arranged to bias the collectors reversely relative to the bases during the accumulation of charge carriers, during the reading out of signals from the emitters, and during the refresh operation. A photosensor device according to claim 1 or claim 2 in which the reset means is arranged to apply the reset control signals via the row control lines to the said electrodes of the phototransistors of the selected row, relative to the reference potential applied to the emitters, so as to forward bias the junction between the bases and the emitters during the refresh operation.

Inventors: OZAKI MASAHARU, SHINOHARA MAHITO, SUGAWA SHIGETOSHI, SUZUKI TOSHIJI, SUZUKI TSUNEO, TANAKA NOBUYOSHI, OZAKI, MASAHARU, SHINOHARA, MAHITO, SUGAWA, SHIGETOSHI, SUZUKI, TSUNEO, SUZUKI. TOSHIJI, TANAKA, NOBUYOSHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1985
Main classification: H01L27
IPC codes: H04N3, H01L27