OPTICAL RECEIVER

Abstract: Optical receiver with a bias circuit (T8, R2/3, R44/45) adapted to reversely bias a photodiode (PIN). This bias circuit for increasing optical power levels shifts the operating point of the photodiode (PIN) towards and into the nonlinear operating region of the photodiode which then becomes forwardly biased and for optical power levels above a predetermined value operates as a constant current source supplying a constant current (Ic) to said photodiode (PIN).

Description: OPTICAL RECEIVER The present invention relates to an optical receiver with a bias circuit adapted to reversely bias a photodiode . Such an optical receiver is already known in the art, e.g. from the article "Optical Fiber Technology Detectors and Receivers" by G. Ante 11 et al, Electrical Communication, Volume 56, No 4, 1981, pp 349-357. The main characteristics of an optical receiver a its sensitivity and its dynamic range and both of these characteristics are not optimum in two known types of optical receivers, i.e. in high impedance receivers and in tranεimpe- dance receivers. Indeed, the former exhibit a relatively high sensitivity together with a relatively small dynamic range, whilst the latter on the contrary have a relatively small sensitivity but a higher dynamic rang . The dynamic range is limited because at higher optical power values saturation of the receiver, e.g. of the bias circuit, occurs by the DC component of the higher photocurren . Moreover, when the anode of the photodiode is coupled to the gate electrode of a field effect transistor (FET) forming part of an amplifier, it has been found that the operation of the receiver may be dependent on the FET used, i.e. on the gate-to-source voltage required to make it conductive and therefore also on the diode voltage . An object of the present invention is to provide an optical receiver, such as described above, but which does not present the above drawbacks. According to the invention this object is achieved due to the fact that said bias circuit for increasing optical power levels shifts the operating point of the photodiode towards and into the non-linear operating region of the photodiode which then becomes forwardly biased and for optical power levels above a predetermined value operates as a constant current source supplying a constant current to said photo¬ diode. When the photodiode becomes forwardly biased, a forward current starts flowing through it due to which the total DC current flowing in the bias circuit is automatically reduced and this circuit and/or other circuitry of the receiver are thus prevented from being saturated. On the other hand, due to the presence of the constant current source, the opera¬ ting point of the photodiode shifts towards and into its non¬ linear region independently of the diode voltage. Another characteristic of the present optical receiver is that said bias circuit includes a transistor the emitter-to-collector pathof which is coupled in series with a first resistance and said photodiode between the poles of a DC voltage supply source, the base of said transistor being connected to the tapping point of a voltage divider comprising second and third resistances also connected in series between said poles. Still another characteristic of the present optical receiver is that one pole of said DC voltage supply source is connected via said first resistance to the emitter of said transistor which is a PNP transistor whose collector is connected to the cathode of said photodiode. The bias circuit does not require the use of a high first resistance because the value of the constant current not only depends on the voltage drop in this first resistance but also on the voltage drop in the second resistance. The disadvantage of the use of a high resistance is that it occupies a relatively large space and has not always a high reliability The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of embodiments taken in conjunction with the accompanying drawings wherein : Fig. 1 represents an optical receiver according to the invention and including a first embodiment of a photo¬ diode bias circuit; Fig. 2 is an equivalent circuit of the photodiode PIN of Fig. 1 when forwardly biased; Fig. 3 represents a second embodiment of a photodiode bias circuit for use in an optical receiver accor¬ ding to Fig. 1; Fig. 4 shows the current versus bias voltage characteristic of this photodiode for various values of the optical power level. The optical receiver shown in Fig. 1 is able to receive high frequency, e.g. 140 Mbit/sec, optical data signals and operates with voltages V+ = 12 Volts, V- =■ -12 Volt ground, and -20 Volts (not shown) used as supply voltage for the operational amplifiers included in the amplifier. The re¬ ceiver is of the high impedance type and includes a photo- detector constituted by a P.I.N. (positive-intrinsic-negative) photodiode PIN, a n-channel field effect transistor FET constituting the input stage of an amplifier circuit Al, amplifier A2, a 200 Hz oscillator OS, a detector DET and an equalizer EQ. The anode of the photodiode PIN is connected in junction point Pi to the gate ectrode of the FET whose source electrode is coupled to this gate electrode via a regulating negative feedback loop including the amplifier circuit A2 and a bias resistance Rl having a high value, e.g. 1 Megohm, in series. The cathode of the photodiode PIN is connected via resistor R2 to the tapping point of a voltage divider comprising resistors R3 and R43 which are connected in series between V+ and ground. The output of the oscillator OS whose input terminal is grounded, is coupled to the junction point P2 of R2 and PIN via a capacitor CIO. The drain electrode of the FET is connected via the remaining part of amplifier circuit Al to a signal input of the equalizer EQ whose output OUT constitutes the receiver output. An output of the amplifier circuit A2 is coupled to a control input of this equalizer EQ via the detector DET. The amplifier circuit Al of which the FET forms partincludes a NPN transistor Tl which forms a cascode circuit with the FET. The supply voltage V+ is connected to the collec tor of Tl via resistor R4 and to the joined drain of the FET and the emitter of Tl via variable resistor R5 and resistor R6 in series, the junction point of R5 and R6 being grounded throu the supply source decoupling capacitor Cl. The base of Tl is connected via resistor R7 to the tapping point of a voltage divider comprising resistors R8 and R9 which are connected in series between V+ and ground. This tapping point is also connected to ground via decoupling capacitor C2 which maintains this point at ground for data signals. The supply voltage V+ is also connected to the collector of an emitter follower transistor T2 whose base is connected to the collec¬ tor of transistor Tl through resistor RIO and whose emitter is grounded via resistor RE. The amplifier circuit A2 includes an operational amplifier 0A1 whose output is connected to its inverting input \___ resistor R12 and capacitor C3 in parallel, and this invert¬ ing input is also connected to the source electrode of the FET via resistor R13, the latter source electrode being connected to ground via resistor R14 and decoupling capacitor C4 in parallel. This capacitor C4 maintains the source of FET at ground for data signals. The output of 0A1 is also connected via resistor R15 to the junction point P3 of bias resistor Rl a one plate of a capacitor C5 whose other plate is grounded. R15 and C5 together constitute a filter preventing 0A1 from providing negative feedback to the data signals. The non- inverting input of OAl is connected to a tapping point of a potentiometer resistance R16 connected between V+ and ground and providing a reference voltage VREF. The 200 Hz oscillator OS includes an operationa amplifier 0A2 whose non-inverting input is grounded and whose output is connected to its inverting input via the cascade connection of three cascaded cells each comprising a series resistor R17, R18 and R19 and a grounded shunt capacitor C6, C7 and C8 respectively. The components of each cell are so chosen that this cell produces a phase rotation of 60° for a frequency of 200 Hz signal only. Thus the three cells in series together produce a 180° phase rotation for this frequency. Because also 0A2 realizes a 180° phase rotation a frequency of 200 Hz is submitted to a 360° or 0° phase rotation. On the contrary, other frequencies are submitted t a phase rotation different from 0° . The amplitude of the 200 Hz signal at the output of 0A2 is for instance about 25 Volts peak-to-peak and that of the 200 Hz signal at the ou put of the first cell R17, C6 is e.g. about 12 Volts. The latter output is connected to ground via an attenuator compri resistor R20 and diode Dl in series and providing for instanc a 1 V (RMS) output signal at the junction point of R20 and D This diode Dl is fed from V+ through resistor R21 and is connected in parallel with capacitor C9 used to remove harmon from the attenuator output signal. The attenuator output is connected to the above mentioned junction point P2 via a 200 Hz coupling capacitor CIO i rming a short-circuit for a 200 Hz signal and this junction point is also connected to ground via capacitor Cll which maintains point P2 at ground for the high frequency data signals. The detector DET comprises the cascade connectio of an amplifier and a peak detector proper. The amplifier includes an operational amplifier 0A3 to the inverting input of which the output of OAl is connected through a 200 Hz coupling capacitor C12 and resistor R22 in series. The non- inverting input of 0A3 is connected to V- and its output is connected to its inverting input via resistor R23 and capaci¬ tor C13 in parallel. The output of OA3 is connected to the non-inverting input of operational amplifier 0A4 via a filter network comprising capacitor C14, shunt capacitor C15 and shunt resistor R24. R24 and C15 are both connected to V-. By a suitable choice of the components C12 to C14 and R22 to R24 a filtering action is performed on the 200 Hz signal supplied from the output of OAl via capacitor C12. The operational amplifier 0A4 forms part of the peak detector proper and its inverting input is connected to V- via a capacitor charge/discharge circuit comprising resistor R25 and capacitor C16 in parallel and its output is connected to the inverting input via diode D2. The equalizer EQ includes a differentiator comprising series capacitor C17 and shunt resistance R26 the one ends of which are connected to the output terminal OUT. The output of the amplifier circuit Al is connected to the other end of C17 via capacitor C18 and the other end of R26 is grounded. The equalizer includes compensation means associated to the differentiator C17, R26 to modify the operation thereof in function of the dynamic resistance and the diffusion capacitance of the PIN photodiode . These means include NPN transistors T3 to T7. The supply voltages V+ and V- are interconnected via resistor R27, the collector-to- emitter path of transistor T5, resistor R28, the collector-to- emitter path of transistor T7 and resistor R29 in series. The base of T5 is connected to the junction point of resistor R30 of e.g. 39 kilo-ohms and diode D3 which are connected in series between V+ and ground so that a predetermined DC bias current flows through this diode . Transistor T7 and resistor R29 form part of a voltage-to-current converter which further includes operational amplifier 0A5 whose non-inverting input is connected to the inverting input of 0A4 through resistor R31 and to ground via coupling capacitor C19. The emitter of T7 is connected to the inverting input of 0A5 via resistor R32 and to V- via resistor R29, whilst the output of OA5 is connected to the base of T7 through resistor R33. The collector of the transistors T3 and T4 which are connected as emitter follower are directly connected to V+, whilst the collector of T6 is connected to V+ via resistor R34 of e.g. 1 kilo-ohm. The emitters of T3, T4 and T6 are connected to V- through resistors R35, R36 and R37 respectively The base of T3 is connected to the junction point of resistors R38 and R39 which are connected in series with data signal coupling capacitor C18 between the emitter of T2 and ground. Likewise, the base of T4 is connected to the junction point of resistors R40 and R41 which are connected in series with coupling capacitor C20 between the emitter of T3 and ground. The emitter of T4 is connected to that of T5 via data signal coupling capacitor C21 and the collector of T5 is connected to the junction point of C17 and R26 via coupling capacitor C24. The emitter of T6 is connected to ground through data signal coupling capacitor C22, whilst its collector is connecte to the junction point of resistor R34 and data signal coupling capacitor C23 which are connected in parallel with resistor R30. The base of T6 is connected to the junction point of C17, C18 and R38 through resistor R42. The coupling capacitors C18 to C24 constitute short-circuits for the data signals. The above described optical receiver operates as follows when high frequency, e.g. 140 Mbit/sec, optical data signals are supplie to the PIN photodiode . The source current of the FET is maintained at a constant value, e.g. 10 mA, by means of the regulating loop comprising the gate-to-source path of this FET, resistor R14 shunted by capacitor C4, amplifier A2 and resistor Rl. Thus, also the gate-to-source DC voltage of the FET is maintained at a constant value . When the above optical data signals are supplied to the PIN diode they are integrated in the input capacitance (not shown) at the gate of the PET. They are then amplified in amplifier Al of which the FET forms part and supplied via capacitor C18 to the equalizer EQ at the output OUT of which equalised data signals appear. The optical data signals generate in the PIN diode a photocurrent which has a DC component I and an AC component i . When calling I the DC current flowing in the internal circuit of the PIN diode and VI the voltage at the junction point of the voltage divider R3, R43, the DC voltages VP2 and VP3 at the junction points P2 and P3 are given by : VP2 = VI - I.R2 (1) VP3 = VP1 - I.R1 (2) so that the reverse DC bias voltage applied across the PIN diode is VPIN = VI - VP1 - I.R2 (3) both VI and VP1 being substantially constant. As long as the PIN diode is reversely biased, the current I is equal to the DC component I of the photocurrent and therefore increases wife increasing optical power supplied to the diodes, so that in this case both VP3 and VPIN decrease. However, as soon as the current I reaches a value such that the PIN diode becomes forwardly biased by the voltage drop over R2, a forward current I_ + i starts flowing through this diode so that the current I is then equal to I less P the DC component I of this forward current and is thus limited In fact I then remains substantially constant. As a consequence also the voltage VP2, VP3 and VPIN remain substantially constant so that there is no danger neither for saturating the FET or/and subsequent circuitry nor for blocking the amplifier A2. This is not so if resistor R2 were not present. Indeed, in this case the current I would not be limited so that for a certain value of this current the voltage VP3 would become substantially equal to the supply voltage of OAl and from that moment on the gate voltage VP1 of the FET would increase and finally the latter would saturate . As described above, the output of the oscillator OS is connected via coupling capacitor CIO and PIN diode in series to a parallel circuit one branch of which comprises the resistors Rl and R15 in series and the other branch of which is constituted by the gate-to-source path of FET and amplifier OAl in series. The following relation may therefore be written when the gain of OAl is much larger than Rl + R15 r VOA1 = VOS . R1 + R15 (4) r wherein V0A1 is the output voltage of OAl; VOS is the 200 Hz output voltage of OS; r is the dynamic resistance of the PIN diode . As long as the PIN diode is reversely biased, i.e. for lower optical power values, e.g. below -20 dBm, the dynamic resistance r of this diode is much larger than Rl + R15. As a consequence the output voltage V0A1 is then negligible so that the detector DET is then not operative and therefore does not affect the operation of the equalizer EQ. In this case only the differentiator circuit C17, R26 thereof is effective. On the contrary, when the PIN diode becomes forwardly biased the output voltage V0A1 of OAl becomes sufficiently large because r becomes considerably smaller so that the detector DET is then operated. As a consequence thereof the equalizer is adjusted, as will be described later. The equivalent circuit of the input circuit including the PIN diode and the associated FET includes a current source supplying a current i (not shown) to a parallel circuit mainly including the resistance Rl and the input capacitance C. (not shown) at the gate of the FET. To check the influence of the forwardly biased PIN diode reference is made to Fig. 2 which shows the equivalent circuit of this forwardly biased diode. The latter circuit comprises an impedance Zl which shunts the last mentioned input capacitance constituted by a parallel circuit with a diode D having a relatively small dynamic resistance r and a so called diffusion capacitance C which is proportional to the inverse of this dynamic resistance r of the diode D as w ll as to the current flowing through this diode . When calling i the AC component and I the DC compo- nent flowing in the parallel circuit D, C_ the following approximate relations may be written : C D = a (I D + ^ » IT (5) wherein i D is the portion of i flowing through D, the current flowing through C being equal to i_; a and b are constants; , • T k(v+V_) ,,« X Ω + X D = 6 D (6) V_ = I .e V D (7) i-> o wherein Io is the reverse diode saturation current; k is a constant; V is the DC voltage across C , D. and i = C • * • (8) τ C C D * dt C8) By taking the relations (5) to (8) into account the value of the current I. + i is given by : «!- ___ • -r -< v .. . dv , , _. •χ D + X = ∑ D ' 6 (1 + ^ (9) It should be noted that v not only is the AC data voBage across the PIN diode but also the AC voltage at the gate PI of the FET because due to the presence of capacitor Cll point P2 is at ground potential for these data signals. From the above and relation (9) it follows that the forwardly biased PIN diode constitutes an impedance Zl which shunts the above mentioned input capacitance C. at the gate of the FET and through which flows the current I + i. When calling Z.. the parallel impedance of this shunt impedance Zl and the input capacitance Ci.n, then v = Zt, . ip wherein i is the total AC current as already mentioned. In order P that the voltage at the output OUT of the receiver should be independent from the impedance Z , across the capacitor C17 should be branched an impedance Z2 through which flows a current proportional to the current I_ + i flowing through Zl. As described in detail hereinafter with this purpose a current i3+l3 is derived from the junction point of C17 and R26 through transistor T5. As mentioned above the AC voltage v is applied to the gate of the FET. Supposing that the gain of the amplifier Al is equal to A, then the output voltage signal of Al at the emitter of emitter follower transistor T2 is equal to -Av. This voltage signal is applied via capacitor C18 to a buffer comprising emitter follower transistor T3 and associated resistors. The voltage signal -Av at the emitter of T3 is applied via capacitor C20 to the volt_g_ divider comprising resistors R40 and R41 which have a value equal to (A-l)R and R respectively . Consequently the voltage signal at the base of emitter follower transistor T4 is equal to -v. This transistor T4 also acts as a buffer and provides the same voltage -v at its emitter. Via capacitor C21 this voltage is applied to the emitter of transistor T5. From Fig. 1 it also follows that the above output voltage -Av of amplifier Al is also applied to the base of transistor T6 and from there, via the base-to-emitter junction of this transistor to the upper plate of capacitor C22 whose lower plate is grounded. As a consequence an AC current -il flows through this capacitor C22, the current il being substantially equal to il = C22 .-—J (10) With the above given values of the resistors R30 and R34, the collector impedance of transistor T6 is mainly constituted by diode D3 so that an AC current substantially equal to il flows through this diode . This AC current is superimposed on the DC bias current II which continuously flows from V+ to ground via resistor R30 and diode D3 in series. The current il + II produces across diode D3 a voltage u + U given by the following relation : il + II = I . e k(u + U) (11) o wherein I is the diode reverse saturation current; o u is the AC voltage across D3; U is the DC voltage across D3. Because II = Io . ekU (12) it follows from the relations (11) and (12) that To be noted that the diode D3 is used in order that notwithstanding the non-linear behaviour of the base-emitter junction diode of T5 the current il should flow therein . Indeed, this current produces across the diode D3 a non¬ linear voltage u which gives rise to the same current il in the base-to— emitter junction of T5 . As already described above , the 200 Hz output voltage VOAl of operational amplifier OAl is given by re lation (4) and this voltage is not negligible when the dynamic resistance r of the PIN diode is re lative ly small, as is supposed . This output voltage VOAl is applie d to the detector DET and more particularly to the circuit including operational amplifier 0A3 which acts as a filter for the 200 Hz frequency. The thus filtered 200 Hz signal is applied to the peak detector proper including operational amplifier 0A4. There in the filtering 200 Hz signal is converted into a DC voltage V with an amplitude equal to the peaks of the input signal . In the voltage-to-current switch including operational amplifier 0A5 and transistor T7 the voltags V is converted into a DC current P V 12 = ^ (14) Because V corresponds to the mean value of the P 200 Hz input signal VOAl and also of the 200 Hz signal VOS as follows from relation (4) , the current 12 is proportional to mean value of the inverse of the dynamic diode resistance r. 5 Instead of using a peak detector also a mean value detector could be used since the purpose is to obtain a DC voltage signal which is proportional to the 200 Hz signal amplitude. Independently from the value of U, the current 12 10 produces across the base-emitter junction of transistor T5 a DC voltage V2 given by 12 = l o . e V2 (15) Therefore the total voltage applied across the junction is equal to u + v + V2. Indeed, as described 15 above the voltages u and -v are applied to the base and emitter of T5 respectively. As a result of this above voltage u + v + V2 a current i3 + 13 is generated in the base-emitter junction diode of transistor T5 and also in the collector thereof. This, current is given by the relation 2r0 ι ■3 n .+__ 1r3 l = I T . ek(u+V+V2) (,1,6_,) o From the relations (13) and (16) it follows ι •3-3 _+_ 1τ3-3 = 1-p.0-, —l —+ I e k . ekV2 (17) and from the relations (10), (15) and (17) it follows 2 - > 5c ι 3 _+_ 1-r3. = τ12i . e kv . (•1-. +, ~Aγ.Cz~22 —dv «), (,1_8_.) As mentioned with respect to relation (14) the current 12 is proportional to the mean value of the inverse — of the dynamic diode resistance. From relation (5) it follows 1 that the mean value of — is equal to I_ . Consequently 0 12 is proportional to I D . For instance : 12 = m.I D (19) wherein m is a constant. From the relations (18) and (19) follows χ •3 ■_ +, « 1--3_ = m. - Ir D . e kv ( .1. + , — A J.CJ —22 - d~v . ) ( .2_0__.) A C22 When —=τ — = a the relations (9) -and (20) are equal when not taking the constant f into account. In this case the capacitor C17 is shunted by an impedance which is Zl equal to ~ wherein Zl is the impedance shunting the input capacitance C. at the gate of the FET, as already mentioned. The voltage with absolute value Av is applied to Z 1 the parallel connection of — m and C17 which forms an impedance Z't so that when Z't is much larger than the value of R26 the voltage VOUT developed across R26 is equal to Av R 6. ^T . Because v = Zt.ip and when choosing C17 = mC. , VOUT becomes proportional to i , as required. P Reference is now made to Fig. 3 which shows a second embodiment of a circuit for biasing the photodiode PIN. This circuit is similar to the one represented in Fig. 1, but now includes a constant current source comprising PNP transistor T8 and a low impedance voltage divider comprising transistors R2 and R44, R45 (instead of R43) which are connected in series between V+ and ground. The tapping point P4 of this voltage divider is connected to the cathode P2 of the diode PIN via resistor R2 and the emitter-to-collector pat of transistor T8 in series. The base of transistor T8 is connected to the junction point P5 of the resistors R44 and R4 Typical values of the resistors are : R2 : 910 kilo -ohms R3 : 10 kilo-ohms R44 : 1.5 kilo-ohms R45 : 3.6 kilo -ohms so that the voltages V . and V at the tapping points P4 and P5 are substantially constant. . --__ . -, ■ .. V P4.R44 /,,-. When calling d = R44+R45 - 21 - the voltage drop across resistor R44, the constant collector current I able to be supplied by the transistor T8 is given by the relation ic = ^b +rτ1 • Vd R " J2 VsE ' ( 22 ) wherein b is the current amplification factor. For lower optical power values the PIN diode is reversely biased and the current I flowing in the outside circuit of this diode is equal to the DC component I of the photocurrent, this current increasing with optical power. This remains so as long as I is smaller than the above mentioned constant current I and in this case transistor T8 c is in the saturated condition. The collector voltage applied to the cathode of the PIN diode is then equal to V c = V P5 + i V BEi " | V CEsatl (23) Because p5 , V and s are substantially constan also V is constant so that a constant reverse bias voltage V PIN = V c " V P1 (24 ) is then applied across the diode. For increasing optical power values remaining below that at point B for which 1 - x c the operating point of the diode shifts along the vertical line AB, represented in characteristic I versus V PIN in Fig ' 4 * When the current Ip reaches the value Ic then the operation point of the diode follows the horizontal line BC and the bias voltage decreases until it reaches a value for which a forward current starts flowing in this diode . The diode is then forwardly biased and operates in its non-linear region. As explained above -in relation to Figs. 1 and 2 this is required to extend the dynamic range of the optical receiver. While the principle of the invention have been described above in connection with . specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the inventio .

Claims: CLAIMS -16- 1) Optical receiver with a bias circuit adapted to reversely bias a photodiode, characterized in that said bias circuit for increasing optical power levels shifts the opera- ting point of the photodiode (PIN) towards and into the non¬ linear operating region of the photodiode which then becomes forwardly biased and for optical power levels above a predetermined value operates as a constant current source supplying a constant current (I ) to said photodiode (PIN) . 2) Optical receiver according to claim 1, characterized in that for optical power levels below said predetermined value said bias circuit supplies a substantial¬ ly constant voltage (V ) to said photodiode (PIN) . 3) Optical receiver according to claim 1 or 2, characterized in that said bias circuit includes a transistor (T8) the emitter-to-collector path of which is coupled in series with a first resistance (R2) and said photodiode (PIN) between the poles of a DC voltage supply source (VP4) , the base of said transistor (T8) being connected to the tapping point of a voltage divider comprising second (R44) and third (R45) resistances also connected in series between said poles. 4) Optical receiver according to claim 3, characteri.?_≤d in that one pole of said DC voltage supply source (V ) is connected via said first resistance (R2) to the emitter of said transistor (T8) which is a PNP transistor whose collector is connected to the cathode of said photo¬ diode (PIN) . 5) Optical receiver with a bias circuit adapted to reversely bias a photodiode, characterized in that said bias circuit for increasing optical power levels shifts the operating point of the photodiode towards and into the non-linear operation region of the photodiode which is then forwardly biased and that it includes means (OS, OAl, DET, EQ) coupled between said bias circuit and the output (OUT) of the receiver for compensating the effect of said forwardly biased diode (PIN) which is equivalent to a second impedance (zl) constituted by a parallel circuit comprising an equivalent diode (D) with a relatively small dynamic resis¬ tance (r) and a diffusion capacitance (C ) dependent on said dynamic resistance (r) and on the current (I + i ) through said equivalent diode (D) . 6) Optical receiver according to claim 5, characterized in that said compensating means provide a Zl third impedance (—) which is proportional to said second impedance (Zl) and coupled between said bias circuit (R2, PIN, Rl) and said receiver output (OUT) . 7) Optical receiver according to claim 6, charac¬ terized in that said bias circuit (R2, PIN, Rl) has a high impedance and is coupled to said receiver output (OUT) via the cascade connection of an amplifier circuit (FET, Al) and an equalizer (EQ) which includes a differentiator circuit comprising a fourth resistance (R26) and a capacitance (C17) Zl across which said third impedance (—) is branched in parallel 8) Optical receiver according to claim 5, characterized in that said compensating means include means (OS, OAl, DET) to measure said dynamic resistance (r) and to provide an output signal (VOAl) related to said dynamic resis¬ tance (r) . 9) Optical receiver according to claim 8, characterized in that said measuring means (OS, OAl, DET) include an oscillator (OS) coupled to the cathode of said diode (PIN) whose anode is coupled to an input of a second amplifier circuit (FET, OAl) shunted by a fourth impedance (Rl) , said output signal (VOAl) being provided at the output of said second amplifier circuit (FET, OAl) and being propor¬ tional to the inverse of said dynamic resistance (r) . 10) Optical receiver according to claim 9, characterized in that said amplifier circuit (FET, Al) include a field effect transistor (FET) and that said second amplifier circuit (FET, OAl), said field effect resistor (FET) and said fourth impedance (Rl) also form part of a regulating loop to maintain the source current of said field effect transistor (FET) substantially constant. 11) Optical receiver according to claim 9, characterized in that said compensating means further include means (DET, 0A5, T7) for converting said output signal (VOAl) into a first DC current (12) proportional to the mean value of the inverse of said dynamic resistance (r) and to a second DC current (I ) flowing through said equivalent diode (D) . 12) Optical receiver according to claim 11, characterizedin that said conversion means (DET, 0A5, T7) include the cascade connection of a peak detector (DET) operating on said output signal (VOAl) and of a voltage-to- current converter (0A5, T7) providing said DC current (12) . 13) Optical receiver according to claim 7, characterized in that said compensating means are adapted to derive from the junction point of said capacitance (Cl7) and said fourth resistance (R26) a third current (i3 + 13) proportional to a fourth current (I + i) flowing through said second impedance (Zl) . 14) Optical receiver according to claim 11, characterized in that said compensating means provide a third Zl impedance (—) which is proportional to said second impedance (Zl) and coupled between said bias circuit (R2, PIN, Rl) and said receiver output (OUT), that said bis circuit (R2, PIN, Rl) has a high impedance and is coupled to said receiver output (OUT) via the cascade connection of an amplifier circuit (FET, Al) and an equalizer (EQ) which includes a differentiator circuit comprising a fourth resistance (R26) and a capacitance (C17) across which said third impedance (— Zl) is branched in parallel,, and that said compensating means are adapted to derive from th e junction point of said capacitance (C17) and said fourth resistance (R26) a third current (i3 + 13) proportional to a fourth current (I + i) flowing through said second impedance (Zl) and include a first transistor (T5) whose first emitter is coupled to the output of said voltage-to-current converter (0A5, T7) , first means to apply across the base-emitter junction diode of said second transistor a first AC voltage (-v) proportional to that applied across said second impedance (Zl) and third means to apply to said second transistor (T5) a second AC voltage (u) giving rise in said junction diode to a current proportional to a fifth (i CD ) current flowing in said diffusion capacitance (C ) . 15) Optical receiver according to claim 14, characterized in that said first means include a voltage divider (R40, R41) to derive said first AC voltage (-v) from the output signal (-Av) of said amplifier circuit (FET, Al) . 16) Optical receiver according to claim 14, characterized in that said second means include a third transistor (T6) to the base of which the output signal of said amplifier circuit (FET, Al) is applied and whose emitter circuit includes a capacitance (C22), the collector circuit of said third transistor (T6) including a second diode (D3) whose anode is connected to the base of said second transistor (T5) . 17) Optical receiver with a bias circuit including a reversely biased photodetector, characterized in that said bias circuit includes means for limiting the bias current through said detector (PIN), upon a predetermined optical power level being reached, so as to forwardly bias said detector. 18) Optical receiver, characterized in that it includes a measuring circuit for the dynamic resistance of a diode, which includes an oscillator (OS) coupled to the cathode of said diode (PIN) and a parallel circuit coupled to the anode of said diode (PIN) and comprising an amplifier (OAl) and a resistance (Rl + R15) . 19) Optical receiver according to claim 18, characterized in that said amplifier (OAl) is an operational amplifie .

Inventors: WITTERS HUGO FRANS JOSEF, WITTERS, HUGO, FRANS, JOSEF
Applicants: BELL TELEPHONE MFG, INT STANDARD ELECTRIC CORP, BELL TELEPHONE MANUFACTURING COMPANY, N.V., INTERNATIONAL STANDARD ELECTRIC CORPORATION
Application year: 1985
Main classification: H04B9
IPC codes: H03F3, H04B10