FORMING TRENCHES IN INTEGRATED CIRCUIT STRUCTURES

Abstract: An improved process is disclosed for making an inte­ grated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning silicon dioxide and silicon nitride layer on a layer of silicon. The improvement comprises isotropically etching the silicon layer to provide an enlarged shallow etch area undercutting the patterned silicon dioxide and silicon nitride layers. Subsequent deeper anisotropic etching to form the trench will result in a trench having an enlarged upper width which, in turn, prevents the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps. Possible creation of openings to such voids in the polysilicon during subse­ quent planarization is thereby eliminated thus avoiding undesirable oxidation of such voids and undesirable stress formation therefrom.

Description: In the formation of an integrated circuit structure, it is sometimes desirable to electrically separate or insulate one or more devices from adjacent portions of the structure by etching a slot or trench in one or more layers of the structure, usually in a silicon layer. After formation of the trench, a layer of silicon oxide is deposited or grown on the exposed surface to provide the desired electrical insulation or dielectric. However, for purposes of subsequent planarization, the groove or trench must be refilled. Conventionally, this is accomplished by depositing a layer of polysilicon followed by etching back or polishing of the surface to achieve the desired planarization. In the normal practice of forming such a trench, conventional anisotropic etching is carried out through a mask or pattern of silicon dioxide (silox) which is placed over the silicon layer to be etched, resulting in the formation of a narrow trench having the same width as the mask. This trench will sometimes be formed somewhat bowed, i.e., it will tend to neck in at the upper corners. This, in turn, may result in the formation of a void during subsequent deposition of the polysilicon filler as shown in Figure 1 representing the prior art. Etching and/or polishing during subsequent planarization processing steps may open this void since it normally forms just beneath the corners, i.e., just beneath the necked down portion. Thereafter, oxidation of the planarized surface will result in undesirable oxidation of the now exposed polysilicon surfaces in the void. This oxidation, in turn, creates undesirable internal stresses due to the expanded volume of the silicon dioxide as it forms upon opposing walls of the void. United States Patent Specification No 4,472,240 discloses that the formation of voids during the filling of trenches can be avoided by providing "Y" shaped trenches. These trenches can be formed by isotropic and subsequent anisotropic etching. Modification of the trench profile to prevent the formation of such voids has been unsuccessful. Since, apparently, the process cannot be carried out in a manner which will prevent such formation of voids it. wouild be highly desirable to prevent any voids in polysilicon which do occur within the trench, as it is planarized, from being subsequently opened and exposed to undesirable oxidation. It is therefore an object of this invention to provide an improved process for the formation of trenches in integrated circuit structures whereby voids formed during subsequent refilling will not be opened during planarization and subjected to undesirable oxidation. Advantageously an improved process for forming trenches in integrated circuit structures is provided whereby the trench profile results in the formation of voids, during subsequent refilling steps, which are sufficiently removed from the surface to prevent the formation of openings thereto during subsequent etching or polishing of the surface whereby oxidation of the voids cannot occur. Accordingly, the present invention provides a method of forming a trench in a surface or a silicon substrate of an integrated circuit structure comprising the successive steps of: a) forming a patterned silicon oxide layer on said surface to provide a silicon oxide mask for etching the trench, b) isotropically etching a shallow hollow in the substrate through said mask, the hollow being wider than the desired width of the bottom part of the finished trench to undercut the edges of the opening in the mask, c) anisotropically etching the substrate through said mask to complete the formation of the bottom part of the trench to the desired depth of the trench, d) oxidising the walls of the so formed trench to form an oxide layer thereon, e) refilling the trench by depositing material therein, f) planarizing said surface to remove any of said material deposited on the surface adjacent the trench, and g) forming an oxide layer over said material in the trench, the anisotropic etching step being to a sufficient depth that the planarizing step does not open to the surface any void formed in the material deposited in the refilling step. The formation of undesirable stress in the integrated circuit structure is thereby avoided. In the accompanying drawings, by way of example only: Figure 1 is a cross-sectional view of an integrated circuit structure processed by prior art procedures illustrating a void formed during polysilicon deposition. Figure 2 is a cross-sectional view of the prior art structure of Figure 1 after planarization of the surface illustrating an opening to the void which has occurred and subsequent oxidation of the polysilicon walls of the void. Figure 3 is a cross-sectional view of an integrated circuit structure processed in accordance with the invention showing shallow isotropic etching. Figure 4 is a cross-sectional view of the structure of figure 3 showing subsequent anisotropic etching to form the trench and subsequent oxidation to form electrical isolation. Figure 5 is a cross-sectional view of the structure of figure 4 after oxidation of the trench walls and deposition of polysilicon in the trench. Figure 6 is a cross-sectional view of the structure of figure 5 after planarization. Figure 7 is a cross-sectional view of the structure of figure 6 after oxidation to form a slot walled device. Figure 8 is a cross-sectional view of an alternate structure to that illustrated in figure 7 showing a field oxide wall device constructed in accordance with the invention. Figure 1 illustrates the prior art construction wherein a void 14 is formed in the polysilicon layer 10 used to fill trench 2 due to the polysilicon adjacent the corners 12 causing a necking effect. While the void, as shown in Figure 1, is completely closed; in Figure 2, subsequent planarization by etching and/or polishing of the surface to remove excess polysilicon can result in the formation of an opening 16 into the void. Subsequent conventional processing to place an oxide layer 18 over filled trench 2 can result in undesirable oxidation of the surfaces of the polysilicon within the void as shown at 19. This, in turn, will result in the formation of stresses due to the expanded volume of the oxides of silicon formed within the void. Referring now to Figure 3, in the practice of the invention, a silicon layer 20 having one or more active device regions is covered with a thin oxide layer 22 (conventionally silicon dioxide) and overlaid with a silicon nitride layer 26 and an oxide layer 24. Optionally, a second silicon nitride layer (not shown) can be applied which is separated by another oxide layer (not shown) from silicon nitride layer 26. This second nitride layer may be used, if desired, as an etchant block if oxide layer 24 etches away completely during subsequent oxide etching steps as will be described. The oxide and nitride layers are masked and plasma etched using CF₄ + O₂ or CHF₃ + C₂F₆ or any other suitable chemistry to form the desired opening 30 corresponding to the desired width of the groove or trench to be formed. These process steps, up to this point, represent conventional prior art processing. The exposed silicon layer 20 is now isotropically etched through mask opening 30 using SF₆ plasma etch or any other suitable isotropic wet silicon etch such as a wet etch using chromic-HF to form the etched portion 34 which undercuts layers 22, 24 and 26 at 32 to provide an opening 34 which is wider than opening 30. The depth of this etch should be adequate to prevent subsequent oxidation of the voids as will be explained below. Preferably, the depth should be about 0.5 to 1.0 microns. The undercutting at 32 should be sufficient to provide a width of about 2.0 microns when the width of mask opening 30 is about 1.0 to 1.5 microns. The trench proper is now formed to the desired depth by a conventional anisotropic reactive ion etch using chlorine chemistry to a depth of about 6 microns to form the opening of trench 40 as shown in Figure 4. Still referring to figure 4, boron is then implanted at 50 in silicon layer 20 below the bottom of trench 40 using a shallow implant B₁₁+ source to prevent surface inversion. A wet oxide etch, i.e. HF, is now performed to remove oxide layer 22 from under the nitride overhang at 32 as well as any oxide deposits on the trench walls. The walls of trench 40 (which includes the remaining portions of initial opening 34) are now etched to remove any surface damage on the newly formed walls using a wet silicon etch, such as iodine or CrO₃, to a depth of about 0.1 microns. The nitride overhang at 32 is now removed with hot phosphoric acid. If a second nitride layer is present, as previously discussed, this layer may also be removed during this step. Oxide layer 24 is then stripped away with an HF etchant leaving nitride layer 26 over oxide layer 22. The walls of trench 40 are now oxidized to form a thin oxide layer 60, i.e., silicon dioxide, of about 3000 Angstroms. Oxide layer 60 forms the electrical insulation or dielectric to separate the active devices in the integrated circuit structure. Polysilicon 70 is then deposited to fill trench 40 and deposit a layer on the surface of the structure over nitride layer 26 of about 2 microns thick as shown in figure 5. It will be noted that a void 74 has formed in polysilicon 70. However, because of the enlarged upper portion of trench 40 formed, in accordance with the invention, by the initial isotropic etching to form opening 34, void 74, formed by necking in of the polysilicon, either due to the trench shape or the deposition itself, only occurs at a lower point in trench 40. The surface is now planarized by polishing or by plasma or wet etching to remove polysilicon on the surface of the structure down to silicon nitride layer 26, as shown in Figure 6. The use of the nitride layer 26 at this point aids in controlling the polishing by giving more thickness control due to the harder silicon nitride material. An oxide layer 80 of about 1 micron thickness is grown over the polysilicon in trench 40. As shown in Figure 7, the nitride layer 26 defines the width of trench 40 whereby oxide layer 80 only covers the polysilicon deposited in trench 40. Figure 8 illustrates an alternate embodiment wherein nitride layer 26 is masked to provide an opening wider than the trench. Oxide layer 80', grown through this mask, provides an additional area of field oxide 72 over silicon 20 adjacent trench 40. However, the device shown in Figure 7 is preferred due to the more dense packing of devices in the integrated circuit structure which is permitted thereby. When the alternate embodiment of figure 8 is used, nitride layer 26 may be optionally stripped, after planarization, and a new layer of nitride deposited to give a consistent thickness and better quality to the resulting nitride layer. As seen in Figures 5-8, in accordance with the invention, void 74 in polysilicon material 70 is located a considerable distance below the oxide material 80 or 80' due to the initial isotropic etching to provide the wider opening adjacent the top surface of silicon 20. The resulting wide opening causes the formation of the void 74 deeper in trench 40. Subsequent planarization, as shown in Figure 6, does not, therefore, remove sufficient polysilicon above void 74 to provide an opening thereto which could otherwise result in oxidation of the walls of void 74 during the subsequent oxidation step to provide oxidation layer 80 or 80' over polysilicon 70. One specific example of a method in accordance with the invention for making a trench in an integrated circuit structure, wherein any voids formed during deposition of polysilicon to refill the trench are not opened during planarization whereby oxidation of the walls of the void is prevented, may be summarised as follows:- a) patterning layers of silicon oxide and silicon nitride previously deposited over a layer of silicon on an integrated circuit structure containing devices to be separated by said trench to form a mask; b) isotropically etching a shallow opening in said silicon layer sufficiently to undercut the edges of the openings in said overlying silicon oxide and nitride mask and to provide an opening depth of 0.5 to 1.0 microns; c) anisotropically etching said silicon through said mask to the desired depth of the trench; d) implanting boron into the region of said silicon layer beneath said trench; e) etching to remove any deposits from the walls of said trench and to remove protruding portions of an oxide layer between said silicon and said silicon nitride layer which protrudes into said shallow opening after said shallow isotropic etching step; f) chemically etching the walls of said trench to remove any surface damage thereto; g) removing those portions of said silicon nitride layer which protrude into said shallow opening after said shallow isotropic etching step; h) removing said oxide mask; i) oxidizing the walls of said trench to provide electrical insulation between devices in said integrated circuit structure separated by said trench; j) refilling said trench by depositing silicon therein; k) planarizing said structure to remove polysilicon deposited on the surface of said structure adjacent said trench; l) removing those portions of said nitride layer remaining after polishing; m) placing a nitride layer over said polysilicon; n) patterning said nitride layer to permit placement of an oxide layer at least over said trench; and o) placing an oxide layer over said material in said trench. Thus, the invention provides an improved process to form a trench in an integrated circuit structure whereby the top portion of the trench is made wider than the required ultimate width to thereby inhibit the formation of voids close to the surface during subsequent polysilicon deposition due to necking at this portion of the trench depth. It should be noted here that while the process has described a number of steps representing one embodiment of conventional processing, there may be modifications in such steps representing variations in the process of forming the trench as is well known to those skilled in the art without departing from the spirit of the invention. That is, other process steps may be used in conjunction with the formation of an initial wide shallow opening by the isotropic etch of the invention without department from the scope of the invention which is to be limited only by the appended claims.

Claims: A method of forming a trench (40) in a surface on a silicon substrate (20) of an integrated circuit structure comprising the successive steps of: a) forming a patterned silicon oxide layer (24) on said surface to provide a silicon oxide mask for etching the trench, b) isotropically etching a shallow hollow (34) in the substrate through said mask, the hollow being wider than the desired width of the bottom part of the finished trench to undercut the edges of the opening in the mask, c) anisotropically etching the substrate through said mask to complete the formation of the bottom part of the trench to the desired depth of the trench, d) oxidising the walls of the so formed trench to form an oxide layer (60) thereon, e) refilling the trench by depositing material (70) therein, f) planarizing said surface to remove any of said material deposited on the surface adjacent the trench, and g) forming an oxide layer (80) over said material in the trench, the anisotropic etching step (c) being to a sufficient depth that the planarizing step (f) does not open to the surface any void (74) formed in the material deposited in the refilling step (e). The method of claim 1 including the further step of implanting boron (50) into the region of said silicon layer beneath said trench prior to oxidising the walls of the trench. The method of claim 1 or 2, characterised by the step of removing said oxide mask layer before said oxidising of said trench walls and any deposition of said material in said trench. The method of claim 3 characterised by the step of etching said trench to clean said walls and repair any damage after said anisotropic etching step and removal of said oxide mask. The method of any preceeding claim, characterised in that said surface is formed by a layer of silicon nitride (26) on the substrate. The method of claim 5, characterised in that a further silicon oxide layer (22) is interposed between said nitride layer and the substrate. The method of claim 5 or 6, characterised by the further step, after said anisotropic etching step, of removing those portions of said nitride layer and said further silicon oxide layer if presemt, which protrude into said shallow hollow after said isotropic etching step. The method of any preceding claim, characterised in that said material used to refill said trench is polysilicon. The method of any one of claims 5 to 8, characterised by the further step of patterning said nitride layer after said planarization step to permit the growing of an oxide region (80) between the edge of said trench and adjacent active device regions as well as over said trench. The method of any one of claims 5 to 8, characterised by the further steps of stripping said nitride layer and forming a further nitride layer on said surface, after said planarization step, and patterning said further nitride layer to permit placement of said oxide layer over at least said trench. The method of any preceding claim, characterised in that said isotropic etching step is carried out for a sufficient time to permit said shallow hollow to reach a depth of 0.5 to 1.0 x 10⁻³ centimetres. The method of any preceding claim, characterised in that said isotropic etching step comprises plasma etching said silicon with SF₆. The method of any one of claims 1 to 11, characterised in that etching step comprises etching with a chemical etch capable of attacking silicon. The method of any preceding claim, characterised in that said anisotropic etch step uses a reactive ion etch. The method of any preceding claim, characterised in that said anisotropic etch step is carried out for a time period sufficient to provide a trench depth of about 6 × 10⁻³ centimetres.

Inventors: PRICE, WILLIAM L., SCHLUPP, RONALD L., THOMAS, MAMMEN
Applicants: ADVANCED MICRO DEVICES, INC.
Application year: 1985
Main classification: H01L21
IPC codes: H01L21