COLOR SIGNAL PROCESSING CIRCUIT

Abstract: Multiplier and multiplicand output means (202, 200, 211 - 216, 124) is connected to multiplier means (300) having a multiplier and multiplicand input section. The multiplier and multiplicand output means produces second matrix coeffi­ cient signals (K10) in response to first matrix coefficient signals, automatic chroma control signal and adjustment signal. The second matrix coefficient signals (K10) are inputted to the multiplier (300) on a time-sharing basis and are multiplied with an input digital chroma signal (C11) in this multiplier. The second matrix coefficient signals (K10) include an automatic chroma control component, color saturation control component and hue control component.

Description: The present invention relates to a digital television device for converting an analog video signal to a digital video signal and processing the digital video signal and, more particularly, to a color signal processing circuit therefor. Along with the development of digital IC techniques, signal processing at the baseband which was conventionally subjected to analog processing, can be digitally performed in a television receiver. A digital signal processing circuit is capable of high-precision and nondistorted processing. Stable operation with regard to changes in temperatures, deterioration over time and noise can also be achieved. The digital signal processing circuit can be coupled to a memory or a computer for easily performing multiscreen television processing, scanning rate conversion, still image processing and other special effects. The digital signal processing circuit can also be coupled to various different media signals. In a digital television system, in the same manner as in the conventional analog television system, automatic chroma control (ACC), color saturation control, hue control, chrominance signal demodulation and matrix operation are required. Many multipliers are required for this signal processing. As is well known to those skilled in the art, multiplier circuits are large. For example, in a multiplier network for multiplying data of 8 × 8 bits, about 1,000 gates are required. The large size of the multiplier is a critical problem in preparing a digital video signal processing IC. Another problem is that a great number of circuits are required for the matrix operation. When the matrix operation is performed by a digital circuit, external R, G, B signals can be easily handled. One advantage, however, is that many additional components required for the analog matrix circuit can be omitted. There is a strong demand for a decrease in the number of components in the matrix circuit. A color signal processing circuit according to the precharacterizing portion of claim 1 is disclosed in the document DE-A-31 23 038. In this circuit, the digital chroma signal and the burst signal are multiplied by means of a multiplier with a coefficient. From the output signal of the multiplier, the average value of the burst amplitude is obtained and this average value is compared with a set value corresponding to a desired color contrast. The said coefficient is changed in accordance with the comparison result. In this way, the known circuit uses a single multiplier concurrently controlling hue and control contrast, respectively, and amplifying the burst amplitude and chroma signals, respectively, to a set value. The present invention has been made in consideration of the above situation, and its object is to provide a color signal processing circuit which reduces great number of high-speed multipliers in color signal processing (ACC, color saturation, hue control and matrix operation). This object is achieved with a color signal processing circuit as claimed. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a digital television receiver; Fig. 2 is a block diagram of a digital signal processing circuit according to an embodiment of the present invention; Fig. 3 is a timing chart for explaining the operation of the circuit shown in Fig. 2; Fig. 4 is a table for explaining the calculation of the circuit shown in Fig. 2; Fig. 5 is a block diagram of a digital signal processing circuit according to another embodiment of the present invention; Figs. 6A and 6B are respectively timing charts for explaining the calculations of the circuit shown in Fig. 5; Fig. 7 is a circuit diagram of a data selector and a timing pulse generator of Fig. 5; Fig. 8 is a timing chart for explaining the operation of the circuit shown in Fig. 5 and 7; and Fig. 9 is a diagram of a digital signal processing circuit according to still another embodiment of the present invention. Preferred embodiments of the present invention will be described with reference to the accompanying drawings. Fig. 1 is a block diagram showing the overall configuration of a video signal processing system. An analog video signal AV is sampled and digitized by an analog-digital (A/D) converter 102 to a digital video signal DV. Sampling is performed in response to a sampling pulse S generated from a voltage-controlled oscillator (to be referred to as a VCXO hereinafter) 103. The sampling pulse S has a frequency four times the color subcarrier frequency f SC and a phase synchronized with the axes of color demodulation. In the following description, I and Q are the color demodulation axes. In this case, the sampling phases are ±I and ±Q. Sampling phase control is performed by a phase-locked loop (PLL) circuit 104. During the color burst period of the digital video signal DV, the PLL circuit 104 calculates the sampling phase and generates a phase error signal S1 representing a difference between the sampling phase signal and the I, Q phases. The signal S1 controls the oscillation frequency of the VCXO 103 so that the phase of the sampling pulse S is synchronized with the I and Q phases. The sampling pulse S is supplied to the respective circuits as the reference clock for digital processing. The digital video signal DV is separated by a luminance/chrominance separator (to be referred to as a Y/C separator) 105 into a luminance signal Y1 and a chrominance signal C. The signal Y1 is subjected to contour correction, and contrast and brightness control in a luminance signal processing circuit 112. The circuit 112 generates a new luminance signal Y2. The chrominance signal C is subjected to automatic chroma control (ACC), color saturation control, hue control, color demodulation and matrix operation in a chrominance signal processing circuit 113. The circuit 113 generates three color-difference signals R-Y, G-Y and B-Y. The circuit 113 receives a timing signal S2 from the PLL circuit 104. The signals R-Y, G-Y and B-Y are respectively added to the signal Y2 by adders 121, 122 and 123. The adders 121, 122 and 123 generate color signals R, G and B, respectively. These signals are converted to analog signals which drive a color CRT through an output circuit. A controller 124 receives an image quality control signal 125 used by a user to control the image quality, and a signal 126 supplied from the digital processing section to the controller 124 so as to operate various types of automatic control. The controller 124 processes the input signals 125 and 126 in accordance with a predetermined program. Signal processing parameters 127 from the controller 124 are supplied to the respective circuits of the digital processing section. The general description of the digital processing section has been given as described above. The chrominance signal processing circuit 113 as the main feature of the present invention will be described hereinafter. Fig. 2 is a block diagram of the circuit 113. The signal C from the Y/C separator 105 is supplied to a signal conversion section, i.e., a phase processing circuit 201. The circuit 201 converts all data of -Q phase to those of +Q phase and all data of -I phase to those of +I phase. The circuit 201 also converts the signal C to a chrominance signal C10 having a data format of ...Q, I, Q, I, Q, I.... Preprocessed signal conversion is performed so as to make the subsequent data processing easier. The signal C10 together with an ACC signal A0 from an ACC circuit 301 is supplied to a multiplexer 202. The output of the multiplexer 202 is supplied to a multiplier 300. The ACC circuit 301 detects the amplitude of a color burst signal and controls the level of the ACC signal A0 in response to the detected amplitude, so that the amplitude of color burst signal approaches a predetermined value. The multiplexer 202 selects the signal A0 or C10. The output signal C11 from the multiplexer 202 is supplied to the multiplier 300. The output chrominance signal C11 has a format shown in Fig. 3. The signal C11 is the signal A0 during a period T0 and the signal C10 during periods T1 and T2. The signal C11 supplied to the multiplier 300 is multiplied with an output signal K10 (the matrix coefficient and the ACC signal) from the multiplexer 227 in a time-division manner. An output signal C12 from the multiplier 300 has been controlled on ACC, color saturation and hue. The signal C12 is supplied through a color killer circuit to the matrix operation section for generating the color-difference signals. The color killer circuit comprises, for example, an AND gate 302 and is controlled in response to a color killer signal from the ACC circuit 301. The color killer signal disables the AND gate 302 when the level of the color burst signal is lower than a predetermined value. The matrix operation section comprises a delay circuit 304, an adder 305 and registers 306 to 308. The registers (306 to 308) generate the R-Y, C-Y and B-Y signals, respectively. A multiplicator and multiplicand output section constituted by the multiplexer 202, multiplexers 221 to 227, registers 211 to 216 and the controller 124 will be described hereinafter. A matrix coefficient output section 200 supplies, for example, a multiplicator to the multiplier 300, and the multiplexer 202 supplies a multiplicand to the multiplier 300. The section 200 receives the signal C12, the signal A0 from the ACC circuit 301, and first matrix coefficients RQ1, GQ1, BQ1, RI1, GI1 and BI1 from the controller 124. The section 200 has the registers 211 to 216 which receive the output chrominance signal C12, the multiplexers 221 to 226 and a multiplexer 227. The registers 211 to 216 provide second matrix coefficients RQ2, GQ2, BQ2, RI2, GI2 and BI2 which are supplied to the multiplexers 221 to 226. The multiplexers 221 to 226 select one of the group of matrix coefficients RQ1 to BI1 and a group of matrix coefficients RQ2 to BI2. The output signal (i.e., the matrix coefficient) is supplied to the multiplexer 227. The multiplexer 227 selects the output pulses from the multiplexers 221 to 226 in a time-division manner and supplies the output signal K10 as a multiplicator to the multiplier 300. Fig. 3 shows the chrominance signals C10 and C11 for one horizontal period and the signal K10. The signal C11 serves as the multiplicand and the signal K10 serves as the multiplicator. During the nonsignal period T0, excluding the video period T2, and color burst signal period T1 in the one horizontal period as shown in Fig. 3, the multiplexer 202 generates the ACC signal A0, and the multiplexer 227 sequentially generates the first matrix coefficients RQ1 to BI1 as the signal K10. In this case, an output (product) of the multiplier 300 is sequentially stored in the registers 211 to 216. The respective outputs from the registers 211 to 216 are the second matrix coefficients RQ2 to BI2 which are the products of the first coefficients RQ1 to BI1 and the ACC signal A0. The second matrix coefficients RO2 to BI2 are obtained by the following equation. During the burst period T1 of the chrominance signal C10, the multiplexer 202 selects the signal C10 from the phase processing circuit 201, and the multiplexer 227 selects the signal A0 from the ACC circuit 301. The multiplier 300 multiplies the color burst signal with the signal A0. A product from the multiplier 300 is supplied to the ACC circuit 301. The circuit 301 thus obtains a new ACC signal A0. During the video period T2 of the signal C10, the multiplexer 202 selects the chrominance signal C10 from the circuit 201, and the multiplexers 227 and 221 to 226 sequentially select the matrix coefficients RQ2 to BI2 as the outputs received from the registers 211 to 216. Fig. 4 shows a relationship between the signals C11 and K10 supplied to the multiplier 300 during the period T2. The color-difference signals are given as follows: When the output signal C12 from a multiplier 303 is added to a signal delayed by one sampling period, the R-Y, G-Y and B-Y components appear for every other sampling period, as shown in Fig. 4. Thus, the R-Y, G-Y and B-Y components are extracted by registers 306, 307 and 308 to obtain the R-Y, G-Y and B-Y signals. In order to separate and demodulate the color-difference signal R-Y, the signal is latched in the latch circuit 306 in response to an R-Y pulse R. The color-difference signals G-Y and B-Y can be processed by latch circuits 307 and 308 respectively in response to G-Y and B-Y pulses G and B. The pulses R, G and B are generated by the timing pulse generator 311. The timing pulse generator 311 produces the pulses R, G and B by using a color demodulation pulse C from the phase locked loop circuit 104, the sampling pulse S from the VCXO 103 and a burst flag pulse BFP. The pulses R, G and B are produced by latch circuits included in the timing pulse generator 311 as shown in Fig. 7. In this case, the signals R-Y, G-Y and B-Y have a latch period of six sampling periods corresponding to a frequency of 2.4 MHz. This frequency can be used in practice even in consideration of the sampling theorem and the bandwidth of the chrominance signal. The first matrix coefficients RQ1 to BI1 supplied from the controller 124 will be described hereinafter. The first matrix coefficients RQ1 to BI1 are expressed by the following equation: wherein, A1 is the color saturation degree adjustment signal controlled by the user, ϑ is the hue adjustment signal controlled by user, RQ0, GQ0, BQ0, RI0, GI0, and BI0 are the reference matrix coefficients determined in accordance with the CRT characteristics. The matrix coefficients RQ1 to BI1 include saturation and hue control data given by microprocessor control of the controller 124. A timing signal tn, required for the above operation, is prepared by a timing pulse generator 311 using a burst flag pulse BFP, a color demodulation pulse C and the sampling pulse. According to the embodiment described above, nine multipliers used in the conventional color signal processing can be reduced to one multiplier by a combination of software processing and time-divisional matrix coefficient multiplications. The multiplication between the ACC signal A0 and the first matrix coefficient (the ACC signal A0 follows a variation of it for every one horizontal period), is performed by hardware using the nonsignal period T0, thereby greatly decreasing the software load. In addition, the software operations are also confined to those using the fixed values and the control signals from the users, thus further decreasing the software load. According to this embodiment, the software processing load can be decreased, and the amount of hardware is also decreased, thereby providing a color signal processing circuit suitably formed into an IC. The present invention is not limited to the above embodiment. In the above embodiment, the data of -Q and -I phases of the chrominance signal C are converted by the circuit 201 to positive polarity data. However, when a means is provided for changing the polarity of the signal K10 supplied to the multiplier 300 so as to synchronize with the -Q and -I phases, the circuit 201 can be omitted. The polarities of the chrominance signal C and the signal K10 supplied to the multiplier 300 need not be processed. In this case, the polarity of the output signal from the multiplier 300 is processed. The present invention may also be exemplified by the circuit shown in Fig. 5. Referring to Fig. 5, the chrominance signal C from a Y/C separator 105 is supplied to a multiplier 300 and is multiplied with an output signal K10 received from a data selector 310. The data selector 310 corresponds to the matrix coefficient output section 200 of Fig. 1. The data selector 310 receives the matrix coefficients RI, RQ, GI, GQ, BI and BQ generated from a controller 124 and data of an ACC signal generated from an ACC circuit 301. A select signal comprises a burst flag pulse BFP and a matrix coefficient select signal K4 for selecting one of the seven input signals. Fig. 6 is a timing chart for explaining the operation of the circuit shown in Fig. 5. The data selector 310 generates the signal A0 during the color burst period. The signal A0 is switched in response to the pulse BFP. Fig. 6A shows a relationship between the chrominance signal C, the pulse BFP and the signal A0. More specifically, the ACC operation is carried out during the color burst period. During this period, the ACC circuit 301 detects the amplitude of the color burst, and controls the amplitude to reach a predetermined value. Except during a period excluding the color burst period, the matrix coefficients RQ to BI are generated as the output signal K10 at a timing shown in Fig. 6B. More specifically, the coefficients ±RQ, ±GQ and ±BQ are generated when the phases of the signal C are set at the ±Q phases. However, the coefficients ±RI, ±GI and ±BI are generated when the phases of the signal C are set at the ±I phases. These sets of outputs are periodically selected and generated. As a result, the multiplier 300 sequentially generates components Q·RQ, I·RI, Q·GQ, I·GI, Q·BQ and I·BI as the output signal C12. Since the matrix operation can be expressed by the following equation; The color difference signals can be obtained by adding the signal C12 and its one sampling period delayed signal C13. The latch circuit 304 delays the signal C12 by one sampling period. A sum output C14 from the adder 305 derives R-Y, B-Y and G-Y components for every other sampling. In order to separate and demodulate the color-difference signal R-Y, the signal is latched by the latch circuit 306 in response to an R-Y pulse R. The color-difference signals G-Y and B-Y can be processed by latch circuits 307 and 308 in response to G-Y and B-Y pulses G and B, respectively. Each of the signals R-Y, G-Y and B-Y has a latching period of six sampling periods corresponding to a frequency of 2.4 MHz. This frequency can be used in practice even in consideration of the sampling theorem and the bandwidth of the chrominance signal. The controller 124 receives the signal A0 from the ACC circuit 301, and the color saturation signal A1 and the hue signal ϑ which are controlled by the user. An internal memory of the controller 124 stores reference matrix coefficients RI0, RQ0, GI0, GQ0, BI0 and BQ0 determined by the characteristics of the color CRT. The matrix coefficients RI, RQ, GI, GQ, BI and BQ are calculated by using the reference coefficients in the following manner: The chrominance signal C is multiplied with above the matrix coefficients RI, RQ, GI, GQ, BI and BQ so the ACC, color saturation and hue control operations are completed. Therefore, the demodulated signals R-Y, G-Y and B-Y will not require color processing (color saturation and hue processing). Now the timing pulse generator 311 and the data selector 310 as the main features of the present invention will be described in detail. The relationship between the signal C and the output signal K10 generated from the data selector 310 is shown in Fig. 6B. This relationship is actually maintained by the timing pulse generator 311. Fig. 7 is a detailed logic diagram of the generator 311 and the selector 310, and Fig. 8 is a timing chart for explaining the circuit arrangement of Fig. 7. Referring to Fig. 7, a selector 515 in the data selector 310 selects the signal A0 as the output signal K10 in response to the pulse BFP during the color burst period and a matrix signal MAX as the output signal K10 to the multiplier 300 during a period excluding the color burst period. As shown in Fig. 8, the matrix signal MAX has 12 matrix coefficients. A data selector 513 receives 12 positive and negative matrix coefficients and selects one of them one by one in response to a matrix coefficient select signal SEL. The signal SEL is derived from the color demodulation pulse C for -Q phase from the PLL circuit 104 and the sampling pulse S. The latch pulses R, G and B for demodulating the signals R-Y, G-Y and B-Y are obtained by delaying the pulse C by a predetermined period of time. The generator 311 comprises counters 501 and 504, an AND gate 503 and a latch circuit 507 so as to generate the signal SEL. The latch circuit 507 is connected in series with latch circuits 508 to 512 so as to generate the latch pulses B, G and R. The sampling pulse S of Fig. 8 is used as a clock for the latch circuits 507 to 512 and for the counter 504. The pulse C is used as a data input to the latch circuit 507 and serves as a clock to the counter 501. Fig. 8 shows waveforms or contents of the sampling pulse S, the chrominance signal C, the color demodulation pulse C, and an output DN from the counter 501. Fig. 8 also shows an output pulse T10 from the AND gate 503. The pulse T10 is supplied to a clear terminal of the counter 504. The counter 504 generates the signal SEL obtained by converting the pulse S by duodecimal notation. The pulses B, G and R are generated from the output terminals of the latch circuits 508, 510 and 512, respectively, as shown in Fig. 8. The circuit arrangement described above only comprises about 200 gates. The circuit can be easily manufactured at low cost. Unlike a conventional circuit having nine multipliers, the circuit arrangement of the present invention reduces the multiplexers to one by a combination of software processing and time-divisional matrix coefficient multiplications and the circuit can be advantageously used in an IC. In the above embodiment, in order to use only one multiplier, preprocessing (i.e., the calculations given by matrix (1)) of matrix coefficients to be multiplied with the chrominance signal C is performed entirely by software. However, preprocessing of the matrix coefficients is not limited to this technique. Various changes and applications may be made in cooperation between software and hardware in accordance with the software capacity. For example, the complicated operations in matrix (1) are caused by a coordinate rotation matrix for changing the hue: The hue control can be performed using a technique for changing the sampling phase upon analog-digital conversion, thereby decreasing the software load. In this case, the controller 124 performs the following operation: Excluding the signal A0 among the signals included in matrix (1), the signals are fixed values or semi-fixed values controlled by the subscriber. When the signal A0 is calculated by hardware, the processing speed of the software can be decreased. In this case, a circuit shown in Fig. 9 is used. The circuit of Fig. 9 is substantially the same as that of Fig. 5, except that a multiplier 701 is added to multiply the output K11 from the selector 310 with the signal A0. An output K10 from the multiplier 701 is supplied to the multiplier 300. In this case, the signal A0 is not supplied to the controller 124 but directly multiplied by hardware with the matrix signal K11. Therefore, the controller 124 performs the following operation: The output K10 is set at logic "1" during the color burst period. During this period, the signal C is multiplied with the signal A0, and automatic color signal gain control has top priority. According to the present invention, the number of multipliers used in the conventional circuit can be greatly decreased, and the system can comprise only ICs. In particular, unlike the conventional matrix circuit having six multipliers, only one multiplier is used to perform time-divisional multiplication. Only one multiplier is required for the entire color signal processing circuit in cooperation with the software. The matrix coefficients of the above-mentioned equations are disclosed by signs RI, GI, BI, RQ, GQ, and BQ. I and Q in these signs are used for indicating color demodulation axes. However, the color demodulation axes of this invention are not limited to general I and Q axes, thus they are disclosed by X and Y.

Claims: A color signal processing circuit comprising: multiplier means (300) for receiving a first signal (C11) and a second signal (K10) and producing a third signal (C12) which is multiplication of said first and second signals (C11, K10), said first signal (C11) including a digital chroma signal and ACC signal (A0); means (202) for transmitting said first signal (C11) to said multiplier means (300); and ACC means (301) for generating an ACC signal (A0) upon application of said third signal, characterized by said transmitting means (202) including first selector means which selects said ACC signal (A0) during a non-signal period of said first signal (C11) and selects said digital chroma signal (C10) during burst and video signal periods of said first signal (C11); matrix coefficient means (200, 211, - 216, 124) responsive to said third signal (C12) for generating a plurality of matrix coefficients, said matrix coefficient means including a second selector means (227) for selecting said matrix coefficients in time division manner and for producing said second signal (K10); and said ACC means (301) being connected between said multiplier means (300) and said matrix coefficient means (200, 211 - 216, 124). A color signal processing circuit according to claim 1, characterized in that said matrix coefficient means (200, 211 - 216) provides first matrix coefficients and second matrix coefficients; said second selector means (227) selects said first matrix coefficients as said second signal (K10) during nonsignal period (T0) of said digital chroma signal and selects said ACC signal (A0) as said second signal during burst signal period (T1) of said digital chroma signal and selects said second matrix coefficients during video period (T2) of said digital chroma signal; and wherein said second matrix coefficients are the multiplication of said ACC signal (A0) and said first matrix coefficients. A color signal processing circuit according to claim 2, characterized in that said matrix coefficient means further includes register means for storing said second matrix coefficients, and includes third selector means for selecting said first matrix coefficients and said second matrix coefficients stored in said register means. A color signal processing circuit according to claim 3, characterized in that said matrix coefficient means further comprises, adjusting means (124, A1, ϑ) for adjusting said first matrix coefficients by an arithmetic operation of thereby color saturation and hue are controlled, where, RX1, GX1, BX1, RY1, GY1 and BY1 are the first matrix coefficient signals, A1 is the adjust color saturation degree adjustment signal, RX0, GX0, BX0, RY0, GY0, and BY0 are the predetermined first matrix coefficient signals, ϑ is the hue adjustment signal, and where said second matrix coefficients RX2, GX2, BX2, RY2, GY2, and BY2 are obtained by an arithmetic operation of where, said A0 is the ACC signal. A color signal processing circuit according to claim 1, characterized by further comprising: delay means (304) connected to said multiplier means (300) for delaying said third signal by a given period and for producing a delayed signal; and means (305) for adding said third signal and delayed signal for producing a color difference signal. A color signal processing circuit according to claim 1, characterized in that said transmitting means (202) substantially transmits said digital chroma signal; and said second selector means (227) selects said ACC signal (A0) during burst signal period (T1) of said digital chroma signal, and selects said matrix coefficients during video period (T2) of said digital chroma signal. A color signal processing circuit according to claim 6, characterized in that said matrix coefficient means (200, 211 - 216, 124) comprises; adjusting means (124, A1, ϑ) for adjusting said matrix coefficients RX, GX, BX, RY, GY and BY by an arithmetic operation of thereby color saturation and hue are controlled, where, A1 is the color saturation degree adjustment signal, ϑ is the hue adjustment signal, A0 is the ACC signal, RX0, GX0, BX0, RY0, GY0, and BY0 are the predetermined first matrix coefficient signals. A color signal processing circuit comprising: multiplier means (300) for receiving a first signal (C11) and a second signal (K10) and producing a third signal (C12) which is a multiplication of said first and second signals (C11, K10), said first signal (C11) being a digital chroma signal; and ACC means (301) connected to said multiplier means (300) for generating an ACC signal upon application of said third signal (C12); characterized by data selector means (310) for selecting matrix coefficients (K11) in time division manner; a multiplier (701) for multiplying said matrix coefficients (K11) and said ACC signal, and for producing said second signal (K10); and adjusting means (124, A1, ϑ) for adjusting said matrix coefficients (K11) by an arithmetic operation wherein said multiplier (701) performs an operation of K11 x A0 in order to obtain said second signal, where, RX0, GX0, BX0, RY0, GY0, and BY0 are the predetermined first matrix coefficient signals, A1 is the color saturation degree adjustment signal, ϑ is the hue adjustment signal, and A0 is the ACC signal. A color signal processing circuit according to claim 8, characterized by further comprising; delay means (304) connected to said multiplier means (300), for delaying said third signal by a given period and for producing a delayed signal, and means (305) for adding said third signal and delayed signal, for producing a color difference signal. A color signal processing circuit comprising: multiplier means (300) for receiving a first signal (C) and a second signal (K10) and producing a third signal (C12) which is multiplication of said first and second signals (C, K10), said first signal (C) including a digital chroma signal and a burst signal; and ACC means (301) for generating an ACC signal (A0) upon application of said third signal (C12); characterized by matrix coefficient means (124, 310) for generating a plurality of matrix coefficients (K10), said matrix coefficient means including selector means (310) for selecting said ACC signal (A0) during a burst signal period (T1) of said first signal (C) and for selecting said matrix coefficients during a video period (T2) of said digital chroma signal, and adjusting means (124, A1, ϑ) for adjusting said matrix coefficients (K10 = RX, GX, BX, GY and BY) by an arithmetic operation of thereby color saturation and hue are controlled, where, A1 is a color saturation degree adjustment signal, ϑ is a hue adjustment signal, A0 is the ACC signal, and RX0, GX0, BX0, RY0, GY0 and BY0 are predeterminded first matrix coefficient signals.

Inventors: SUZUKI, SUSUMU C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: H04N9
IPC codes: H04N9