THE MULTI INPUT FAST ADDER

Abstract: A multi input arithmatic logic unit by combination of breaking down the inputs into several stages of bitwise processing followed by shifting of outputs according to the power of bits. This process may also be repeated or serially combined, combined with carry look ahead stages or used for producing modular units by introducing carry-in and carry outs. This may also be incorporated to process negative numbers, produce logical functions, multipliers, dividers, mathematical functions, control units, etc.

Description: THE MULTI INPUT FAST ADDER Int oduct ion This invention is related to the speed ing up of arithmetic logic units of computers and micro computers. It leads to manufacturing of integrated circuits for real time and fast digital processing . and control applications. Addition of more than two numbers cannot be done by a human being except using the cumulative law? where one adds two numbers at first, and add the third number to the result and so on. This technique has been adopted in computer technology and therefore has inherent limitations. Addition of several numbers must be done using the above technique. As one number consists of several dig i ts»ad i ton has to be started from lowest bit and a carry has to be passed to higher bits. Carry look-ahead technique is used to speed up this operation. It is described in detail in reference .1). However there is no existing method to carry out a faster addition with more than two numbers at a time.Although a boolean expression can be used for one bit addition. the problem of carry propagation results in a significant delay. To reduce the time of adding several var iables»more arithmetic logic units can be used in parallel » reducing the number of steps to a logarithmic figure. But t is i s an expensive solution. Multiplication which is done as a series of additions also suffers from this technolo i al I i i tat ion.If one coefficient is ■ fixed, this can be speeded up by using read only memor i es.wh i ch d pend on known coe f ic ients . in digital fi lters this technique is being applied to speed up operation. However this requires a customer designed filter for each ap lication, which is described in reference(≤) . In large computers fast multipliers are used with special design for a speci ic conf igurat i on.Boo lean expression for full processing are extremely expensive.Due to irregula ities of these express i ons.a microprocessor has not been bui lt with this faci lity? up to now. Invent i on Thi invention enables the faster arithmetic operations by incorporati g more than two ad itions at a time. Several inputs of several bits can be added in a single unit. Addition of the same level bits of several variables are done by programmable logic array units, which produce certain number of out put bits of different powers. Each of these out put bits are considered as input to the next stage. Shifting of higher power bits to appropriate position is required. After shifting these bits of same power are added again? using programmable logic array units. Stage to stage . number of outputs per stage decreases. At the last stage there are only two outputs corresponding to each bit position. w ich can be treated as the addi ion of two numbers consisting of several bits, which is the normal application in present day technology. Incorporating - carry look ahead technique at thi stage wi ll lead to faster speeds . However one can use these two inputs, with normal carry propagation procedures, depending on the requi ement. Several bits of . several inputs can be grouped into .blocks of bits of all the inputs* to produce modular units. Each block wi ll have certain number of intermediate carry bits in addition to the normal carry. Numbers are represented in 2's complement form, and can be positive or negative. To remove overflow, a sufficient number of additional sign bits are introduced . before processing. In hardware i lementation t is is quite simple as . only the sign bit is * fed in parallel to the required number of positions. This operation can be considered as a mere division* to guarantee that the result is within the limits of 2-'s complement representation (1 > result >= -1 ). The technique is valid for integer representation of numbers as well as for normalized representation of numbers. Given below is one embodiment of carrying out above invention, and is in the form of explanation only? and not limiting in scope. Figure 1) shows the general block diagram of this application Figure C2) shows the 5 inputs of each digit and i s three out puts from PLA corresponding to the equations given below. XO a A'B^C^D^E + A'-B^D E*+ A*B^C D'E*+ A'-B C^D * -E , -+ A B*C*D*E*+ A^C D E + A B C^D E + A*B C D*E + A^B C D E'+ A B C D E + A B' • C D' Έ + A B'-C D E^+ A B C'D'-E + A B CD E'-+ A B C D'-E'-t- A B C D E XI = A A'' '-BB'' '--CC D D E E + + A'-B CH ) E + A'-B C D'E + A'-B C D E'-+ A B' '- C 1 * -D E + A B' • C D' -E + A B'-C D E'-+ A B C'D'-E + A B C'-D E'-+ A B *_, D' • E' • + A B C < ■ - D ' ' • E' • + A B'-C D'-E + A B'C'D E'-+ A B'-C'D'-E + A' ■* B C D' ' • E + A'-B C'-D E'+ A'-B C'-D'-E + A'-B'-C D E'+ A'-B'-C D'-E + A'B'-C'D E X2 = ABCD + BCDE + CDEA + DEAB + EABC These three outputs are shifted according to their values and added using another PLA to obtain two out puts. Figure (3) shows the implementation of this PLA in detai l . (2 d stage of addition requires 3 carriers from previous stage modular unit, and simi larly first stage of addition generates these carriers for the next stage ) Equations governing the 2nd stage are Yi.o = X Ci .o ) X Ci-1.1) X 0-2*2) + X Ci .o) X'-Ci-l.t) X'-Ci-2.2) X'-Ci .o) X Ci-1.1) X'Ci-2.2) + X'-Ci .o) X" C i-1.1) X Ci-2.2) Yi.l = X Ci .o) X Ci-1.1) + X (i .o) X C i-2.2) + X i-1.1) XC i-2.2) The outputs obtained from the second addition are shifted again according to their positions which reduces the problem to a two input case. Thi d PLA (as shown in Figure (4) is used to produce Generators and Propagators required for carry look ahead process ing. Equations- governing this PLA are given * below. Si = YCi JO) + Y( i-1.1) + Ci Pi = YCi JO) + YCi-1.1) Gi = YCi .o) YCi-1.1) These generators CGi) * propagators CPi) and carry in CCi) are combined in the carry look ahead unit to produce carries C1.C2JC3.Cout* block generator CGb) and block propagator CPb).These block outputs can be used for further stages of carry look ahead processing. Figure C5) explains the PLA i plementation of this carry look ahead unit. Cl =Go + Po Co C2 =G1 + PI Go + PI Po Co C3 =G2 + P2 Gl + P2 PI Po Co Co t =G3 + P3 G2 + P3 P2 Gl + P3 P2 PI Go + P3 P £. PI Po Co Pb =P3 P2 PI Po Gb =G3 + P3 G2 + P3 P2 Gl P3 P2 PI Go + P3 P2 PI Po Co When negative number manipulation is required * same technique can be used .Principle of operation is similar with additional sign bits introduced to inputs . However the result has only one sign bit * and the speed of operation has increased by a order of magnitude. delays associated with few types of ALUs are shown below 4b i ts lSbi t. 64b i t: 256 i ts 1.T o nu bers o ly 9 13 17 with carry look ahead 2.Five numbersC4 additions) 20 'b 52 btf 3.Five numbersC3 stages) 27 33 51 Parallel addition used 4.Five numbers 13 17 21 Proposed method All delays are given in basic gate delays. Sti ll higher improvement can be obtained in adding more numbers at once. Carrying out of the invention As mentioned before this invention can be carried out in several ways* depending on the application. Five input four bit standard configuration can be produced as a MSL I/C. This wi ll have 20 inputs* 5 carry ins and 5 carry outs C including 3 first stage car r i es * 1 second stage carry and the normal carry) .block generator and block propagator out puts for further stages of car ry look ahead processing * and four out put bi s.After considering clocks and power connections it can be concluded that this configuration can fit into a 40 pin package.This wi ll have many ap lications in real time processing. In microprocessors this can be used as a bui lding block of the ALU .Configuration can be changed from 4 bits to any number requi red. umber of parallel inputs also can be changed to a conveni ent number. Main frames can use the same technique to produce fast multipliers and adders to speed up operation. Advantages Ci) The system suggested enables the design of a modular unit * possibly a chip * which can be used for fast addition and thereby improve the capabi lities of digital fi lters by allowing a smaller sampling time during two successive samplings of a real time processing system. This opens a new avenue for fi lters which require a higher frequency response . Certain present requirements * which cannot be carried out due to a technological limitation of processing speed become possible. Cii) The system suggested can be incorporated in fast multipliers in main frames as well as in microprocessors » as a functional unit . Flexibility of having different stages makes the component cheaper and allows for more design variations. Ci ii) The system suggested requires only * very elementary programmable logic array units and standard carry look ahead units * enabling the design to be more regular and therefore accurate and » very fast design at chip level. Civ ) The method suggested does not have any technological I imi tat ion and is avai lable for production in a <,>e r y short time. C v ) The method suggested can change the concept of normal computin * as new instructions of multi le addi ions can be incorporated at micro instruction level . Thi wi ll speed up the overall performance of computers. Cvi ) This has a special application in cascade digital fi lters * where all figures require addition of only five numbers . Present technology of fixed coefficients and associated ROMs can be changed to that of programmable digital filters. This wi ll reduce digital filter cost by an order of magnitude as customer bui lt ROMs can be com letely eliminated. Industrial applications (a) Production of a fast operation chip A Radar moving target indicator CMTI) is atypical example for this application. The MTI fi lter has to process its data within the pulse repetetion interval and provide the processed information for displaying purposes. The same i formation is required for antenna controlling in tracking radars. Therefore fi lter complexity is basically limited by the processing time. Any i provement in processing time enables the use of better fi lters and hence is quite useful as an aviation aid. Applications can be extended to controls and military uses. Cb ) At present digital fi lters in various applications requi e different ROMs depending on the fi lter coeff i c i ent .Th i chip wi ll reduce the cost of these fi lters as customerized production is completely eliminated. One fi lter may replace a group of fi lters depending on the applications reducing customer costs urthe . Typ i caI exa p le i ≤ a com uni cat i on channe I wh i ch uses several frequencies* depending on time of operation* sun spots and atmospheric conditions. As one programmable fi lter can accommodate all these fi ltering faci lities* a number of fi lters is no more required. Cc) Present compi ler structure has only the addition instruction for adding two numbers. Software has to reduce any arithmetic statement into a set of machine instructions of adding two numbers at a time. With t is type of processor this may become simpler.lt improves throughput and system software development faci lities s im ltaneous ly.Th is wi ll have special application in statistical and weather data processing computers* as very large number of repetetive additions are to be carried out. Cd) At present multiplication is done mainly by* using addition in stages. This technique reduces multiplication ti e by an order of magnitude. Fast division lgorithems which require fast multipliers are not used in microprocessor level at present. This technique solves this technology problem *and hence faster divisions become possible at this level. Ce)Extension of above techniques can be used for any mathematical function generation and multiple nput comparisons using logical functions. Both func ions have tremendous applications in electronic and control fields. COImplementation of the technique can be extended to software* where hard ware shifting of outputs can be simulated using software shifting. This will have a wide application in multi processor envi onment* when array processing and pipelining principles are used for faster operations. Given above is one variation* and the description is with an one embo ime in the way of an example only* and not limiting scope. ther- embodiments and variations* yet wi hin the concept is possible and is covered in t is application. Reference Cl): FUNDAMENTALS HAND BOOK OF ELECTRICAL AND COMPUTER ENGINEERING III - Sheldon S.L. Chang* Editor - in - Chief pages 47 - 49 Reference C2) : DIGITAL FILTERS ANALYSIS AND DESIGN - Andreas Antoni ou pages 426 - 431

Claims: CLAIMS 1. A multi input Arithmetic Logic Unit CALU) by combination of breaking down the inputs into several stages of bitwise processing Cone or more bit positions can consist of a single block in this breaking down procedure ) followed by shifting of outputs according to the power of bits. 2. An Arithmetic Logic unit where the process as claimed in claim one is applied repeatedly Cthat is process is repeated or the two or more stages of processes as in claim one are serially combined). 3. Process consisting of* Combination of one or more of above claimed processes with one or more of carry look ahead stages. 4. Process consisting of* breaking down of the bit chain of* one or more of the processes* as claimed in claims one to three above* to produce modular units * by introducing one or more of carry ins and carry outs. 5 Process which incorporates one or more of above c laims one to four to process negative numbers. 6. Process which incorporates one or more of above c lairns one to five to produce logical functions. 7. process which incorporates one or more of above c laims one to six to produce mul i liers. 3. process which incorporates one or more of above c lai s one to seven* to produce dividers, 9. process which incorporates one or more of above c la i m≤ one to eight* to produce any other mathematical fuu.nnct i on. 10. process which incorporates one or more of above c laims one to nine* to produce control units, 11. process which incorporates one or more of above c lai s one to ten* to produce digital fi lters. 12. Software techniques w ich use one or more of above c lai s one to eleven. 13. Techniques substantially simi lar to the usage given in above claims one to twelve* or as descri ed in the descri pt ion.

Inventors: KUMARASENA ARYA KEERTHI, KUMARASENA, ARYA, KEERTHI
Applicants: KUMARASENA ARYA KEERTHI, KUMARASENA, ARYA, KEERTHI
Application year: 1985
Main classification: G06F7
IPC codes: G06F7