A SOLID-STATE IMAGE SENSOR

Abstract: A solid-state image sensor having a plurality of unit cells, each of which comprises a photosensitive area (24, 25) and a CCD register (23) for the transfer of a signal charge generated in said photosensitive area (24, 25), both said photosensitive area (24, 25) and said CCD register (23) are disposed on a layer (22), having a different polarity from the charging polarity of said signal charge. which is disposed on a substrate (21) hav­ ing the same polarity as said signal charge.

Description: This invention relates to a solid-state image sensor particularly, but not necessarily exclusively, an interline CCD image sensor i.e., an interline charge coupled device image sensor. Although solid-state image sensors are advantageous over pick-up tubes in compactness, minimization of weight, durability, reliability, exhibiting no burn-in from intense overloads, etc., they give rise to blooming and smear which do not arise in pick-up tubes. Blooming occurs when excess signal charges in the photodiode overflow into the transfer channel, resulting in distinct white lines on the obtained image, while smear takes place when a signal charge generated deep inside the substrate diffuses into the transfer channel, resulting in indistinct white lines on the obtained image. Blooming can be eliminated by means of overflow drains composed of an n⁺-diffusion layer which absorbs excess charges, as disclosed by W.F. Kosonocky et al., "Control of Blooming in Charge-Coupled Imagers", RCA Review, vol. 35, pp 3-24, March 1974. However, the problem of smear has not yet been solved. The above-mentioned approach for the elimination of blooming sacrifices photosensitivity and dynamic range because the active area is reduced, and accordingly a method for the transfer of the excess charges into the substrate has been proposed by Y. Ishihara et al., "Interline CCD Image Sensor with an Antiblooming Structure", IEEE Transactions on Electron Devices, vol. ED-31, No. 1, January 1984. Figure 3 shows a unit cell of the interline CCD image sensor described in the above-mentioned article, wherein an n⁻-layer 3 constituting a buried channel of the vertical CCD register is formed on a thick p-type layer 13 , while an n-type layer 14 constituting a p-n junction photodiode as a photosensitive area is formed on a thin p-type layer 12 . Both the thick p-type layer 13 and the thin p-type layer 12 are positioned on an n-type substrate 1 . A transfer gate region 7 positioned between the n⁻-layer 3 and n-type layer 14 contains the part of the p-type layer which has not undergone depletion. This unit cell is electrically isolated from adjacent unit cells by channel stops 6 composed of p⁺-layers formed in the surroundings thereof. On the n⁻-layer 3 and the transfer gate region 7 , a polysilicon electrode 9 , which is an electrode for the vertical CCD register to be driven by pulses  v fed to the electrode 9 , is formed. On the polysilicon electrode 9 , an Al film 10 is further formed as a photo-shield. A reverse bias voltage is applied between the channel stops 6 and the n-type substrate 1 , resulting in a complete depletion of the thin p-type layer 12 . The pulses  v have three levels, V H (high), V M (middle) and V L (low). When the pulses  v are between the V M and V L levels, the n⁻-layer 3 constituting the vertical CCD register area is isolated from the n-type layer 14 constituting the photosensitive area by the transfer gate region 7 containing a part of the p-type layer. When the pulses  v are at the highest potential V H , a signal charge accumulated into the photosensitive area is transferred from the photosensitive area into the vertical CCD register area through the transfer gate region 7 , and the potential of the n-type layer 14 constituting the photosensitive area results in a level equal to the surface potential of the transfer gate region 7. This signal charge is further transferred to a horizontal CCD register (not shown) to be read out at a gated charge detector (not shown). As the photogenerated signal charge accumulates in the n-type layer 14, the potential of the n-type layer 14 decreases. However, the excess charges generated in the n-type layer 14 when it receives intense illumination are transferred from the n-type layer 14 into the n-type substrate 1 through the thin p-type layer 12 which has been depleted, resulting in a suppression of blooming. The prior art image sensor shown in Figure 3 can therefore suppress blooming, but it still has the following serious problems: The first problem is that the image sensor cannot be made compact because of the inevitable lateral expansion of the thick p-type layer 13. The size of the unit cell cannot be minimized beyond a certain extent in the lateral direction because the size of the thin p-layer 12 is essential to a certain extent. The second problem is that smear takes place unavoidably when a signal charge generated in the non-depleted thick p-type layer 13 diffuses into the vertical CCD register and mixes with the signal charge in it. An image sensor of the above-mentioned type which suppresses unwanted lateral diffusion of carriers by complete depletion of the p-type layer not only below the photodiode area but also below the vertical CCD register area is shown in the earlier-priority EP-A-0 174 133, which was published after the priority date of this application. This document does however not provide a photodiode area consisting of two different layers. According to one aspect of the present invention there is provided a solid-state image sensor having a plurality of unit cells, each of which comprises a photodiode area in which, in operation, signal charges accumulate, and a CCD register area for receiving and transferring the signal charges generated in the photodiode area, both the photodiode area and the CCD register area being formed in a first semiconductor layer having a first conductivity type such that its majority carriers are of the opposite polarity to the signal charges; the first layer being disposed on a semiconductor substrate having a second conductivity type opposite to the first, wherein the first layer is reverse-biased with respect to the substrate so that those parts of it which lie between the substrate and the photodiode area and between the substrate and the CCD register area are completely depleted; and the photodiode area consists of two different layers, a lower layer of the second conductivity type and an upper surface layer in contact with it, the upper layer having a higher impurity concentration than the lower. The upper layer of the photodiode area may be of either the first or the second conductivity type, and it may, in a preferred embodiment, be formed by a self-alignment technique using an electrode of the CCD register as a mask. Depletion is, according to the invention, attained not only in that region of said first layer which lies between the substrate and the photosensitive area but also in the region between the substrate and the CCD register, by the application of a reverse bias voltage between the substrate and the layer which is formed on the substrate. The CCD register, in a preferred embodiment, comprises a buried channel. In this case the lower region of the photosensitive area, facing the substrate, can be formed simultaneously with the buried channel of the CCD register according to another aspect of the present invention. Thus, an embodiment of the invention described herein makes possible the objects of (1) providing a solid-state image sensor which can attain a suppression of not only blooming but also smear; and (2) providing a solid-state image sensor having a compact structure. For a better understanding of the invention and to show how it may be put into effect reference will now be made by way of example to the accompanying drawings in which: Figure 1 is a sectional view showing a unit cell of an embodiment of a solid-state image sensor of this invention. Figure 2 is a sectional view showing a unit cell of a second embodiment of a solid-state image sensor of this invention. Figure 3 is a sectional view showing a conventional unit cell of an interline CCD image sensor. Figure 1 shows a unit cell of an interline CCD image sensor in accordance with this invention, which comprises an n-type substrate 21, a first, p-type, layer 22 formed on the n-type substrate 21, a vertical CCD register which comprises a buried channel constituted by an n⁻-layer 23 formed on the p-type layer 22, and a photosensitive area which contains a p-n junction photodiode including an n⁻-layer 24 and an n⁺-layer 25. The n⁻-layer 24 is positioned in the region below the surface of the photosensitive area, nearest the n-type substrate 21, while the n⁺-layer 25 is positioned on the upper surface of the photosensitive area. Since the n⁺-layer 25 can be formed by a self-alignment technique using a polysilicon electrode 29 for the CCD register as a mask, it does not complicate the production process of this image sensor. Moreover, since the n⁻-layer 24 can be formed at the same time as the n⁻-layer 23 constituting the buried channel of the CCD, it allows for further simplification of production processes for this image sensor. A transfer gate region 27 containing a part of the p-type layer is positioned between the n⁻-layer 23 and the n⁺-layer 25 . This unit cell is isolated from adjacent unit cells by channel stops 26 composed of p⁺-layers formed in the surroundings thereof. On the n⁻-layer 23 and the transfer gate region 27 , the polysilicon electrode 29 functioning as an electrode for the CCD register which is driven by pulses  v fed to the electrode 29 is disposed through an insulating film. On the polysilicon electrode 29 , an Al film 30 is disposed as a photo-shield. A reverse bias voltage is applied between the channel stop 26 and the n-type substrate 21 , resulting in complete depletion not only in the region of the p-type layer positioned between the substrate 21 and the CCD register, but also in the region of the p-type layer positioned between the substrate 21 and the photodiode area. The introduction of the pulses  v (having three potential levels, V H , V M , and V L ) into the polysilicon electrode of the image sensor of this invention having the above-mentioned structure, the reading out of a signal charge at a gate transfer detector, the control of the transfer of the signal charge into the CCD register, and the control of the accumulation of the signal charge in the photosensitive area are attained in the same manner as for a conventional image sensor. Since the region of the p-type layer positioned below the photodiode area has been depleted, excess charges generated in the photodiode area receiving intense illumination are transferred from the photodiode area into the n-type substrate 21 through the n⁻-layer 24 and the p-type layer 22 in the same manner as the conventional image sensor in Figure 3 . Due to the above-mentioned particular structure of the image sensor of this embodiment, the region of the p-type layer 22 positioned below the n⁻-layer 23 is also depleted and charges generated deep inside said region can be transferred from said region into the n-type substrate 21 without diffusion of the charges into the CCD register, so that smear can be completely suppressed. Moreover, the transverse expansion of the thick p-type layer required in a conventional image sensor is not required in above-mentioned image sensor of this invention, so that compactness of the image sensor can be achieved. Figure 2 shows another unit cell of an interline CCD image sensor according to this invention, which has the same structure as the unit cell of the image sensor shown in Figure 1 , except that a p⁺-layer 32 is employed instead of the n⁺-layer 25 which constitutes the region of the outer surface of the photosensitive area. This image sensor shown in Figure 2 operates in the same manner and attains the same effects as that shown in Figured 1 , except that when the pulses  v are at the highest potential level V H and the signal charge accumulated in the photosensitive area is read out at the horizontal CCD register, the n⁻-layer 24 must be completely depleted because the p⁺-layer 32 is formed with a high impurity concentration and positioned at the same potential as the p⁺-channel stop layer 26 . As mentioned above, each of the unit cells of the image sensor is designed in a manner to form both the buried channel CCD register of the n⁻-layer constituting the transfer area and the photodiode constituting the photosensitive area on the same p-type layer disposed on the n-type substrate, so that excess charges generated in the photodiode receiving intense illumination can be transferred from the photodiode into the n-type substrate through the depleted region of the p-type layer therebetween, resulting in a suppression of blooming. Moreover, since the region of the p-type layer positioned between the CCD register and the n-type substrate is also depleted, charges generated deep inside the depleted region of the p-type layer do not diffuse into the CCD register, resulting in a suppression of smear. Since the image sensor has only one p-type layer 22, on which both the CCD register and the photodiode are formed, and does not have a thick p-type layer 13, of considerable lateral extent, as in the conventional image sensor in Figure 3, it can be made compact, whereas the conventional image sensor cannot be made compact because of the transverse extent of the said thick p-type layer 13.

Claims: A solid-state image sensor having a plurality of unit cells, each of which comprises a photodiode area (24,25;24,32) in which, in operation, signal charges accumulate, and a CCD register area (23) for receiving and transferring the signal charges generated in the photodiode area, both the photodiode area and the CCD register area being formed in a first semiconductor layer (22) having a first conductivity type such that its majority carriers are of the opposite polarity to the signal charges; the first layer (22) being disposed on a semiconductor substrate (21) having a second conductivity type opposite to the first, wherein the first layer (22) is reverse-biased with respect to the substrate (21) so that those parts of it which lie between the substrate (21) and the photodiode area (24,25) and between the substrate (21) and the CCD register area (23) are completely depleted; and the photodiode area consists of two different layers, a lower layer (24) of the second conductivity type and an upper surface layer (25;32) in contact with it, the upper layer having a higher impurity concentration than the lower. A solid-state image sensor according to claim 1, wherein the upper layer (25) is of the second conductivity type (Fig. 1). A solid-state image sensor according to claim 1, wherein the upper layer (32) is of the first conductivity type (Fig. 2). A solid-state image sensor according to any preceding claim, wherein the upper layer (25;32) is self-aligned with an electrode (29) of the CCD register. A solid-state image sensor according to any preceding claim, wherein the CCD register comprises a buried channel. A method of making a solid-state image sensor according to claim 5, comprising the steps of: forming the said first layer (22) on the substrate (21), forming the CCD register area (23) and the lower photodiode layer (24) in the first layer (22), and forming the upper photodiode layer (25;32) in contact with the lower layer, wherein the formation of the lower layer (24) of the photodiode area is simultaneous with the formation of the buried channel (23) of the CCD register.

Inventors: MIYATAKE, SHIGEHIRO
Applicants: SHARP KABUSHIKI KAISHA
Application year: 1985
Main classification: H01L27
IPC codes: H04N5, H01L27, H01L31