SEMICONDUCTOR MEMORY INCORPORATING A TEST PATTERN GENERATOR

Abstract: In a semiconductor device comprising a memory cell array (1) and a test pattern generating circuit (8), the test pattern generating circuit generates a test pattern and transmits the test pattern to the memory cell array when receiving both a least significant bit signal (A₀) of address signal (A₀ ... A n ) supplied to the memory cell array, and a control signal (CNT1).

Description: The present invention relates to a semiconductor device incorporating a memory cell array, for example, a random-access memory (RAM). Generally, in a semiconductor device incorporating a memory cell array (for example, RAM) various kinds of logic circuits are provided in addition to the memory cell array for transmitting or receiving signals to or from the array. Such logic circuits include, for example, counter circuits and arithmetic logic units (ALU). Address signals for the memory cell array are supplied from the output side of the counter circuits, and data which has been calculated in the ALU's is supplied from the output side of ALU's to the array and written into the predetermined address. Also, predetermined data read from the memory cell array is supplied to the input side of the ALU's in order, for example, to carry out predetermined calculation in the ALU's again. In the prior art, if it was desired to test the function or the internal state of the memory cell array, the test was carried out through the above logic circuits. However, in this case, the test data to be written into the memory cell array was designated from the outside. Therefore, there was the problem that it was necessary to use a large amount of test data, resulting in poor efficiency for the testing. In view of the above, it has been desired to provide a test circuit within the above semiconductor device, enabling direct testing without the need for supplying test data from the outside. However, even if such a test were to be used, a problem would arise that the test pattern constituting the test data to be written into each memory cell becomes large, especially when the capacity of the memory cell array is large. As a result, the writing of the test data for the memory cell array would still be troublesome. JP-A-57-3299 discloses a memory integrated circuit having the features of the precharacterising part of accompanying claims 1 and 2. According to a first aspect of the present invention, there is provided a semiconductor device according to accompanying claim 1. A second aspect of the present invention provides a semiconductor device according to accompanying claim 2. The present invention is intended to solve the above-mentioned problems. An embodiment of the present invention may enable automatic generation of a pattern of test data just by supplying address signals for the memory cell array (for example, RAM), without the necessity of supplying test data from the outside. In this connection, in one type of test pattern, generally called a "checkerboard" pattern, the test data to be written into adjacent memory cells consists of alternate "1"'s and "0"'s. This test pattern, recently known is simple, but desirable in that it can detect exactly defective parts of the memory cell array. According to an embodiment of the present invention, it is possible to automatically generate such a checkerboard pattern just by supplying address signals for the memory cell array. An embodiment of the present invention may provide a semiconductor device incorporating a test pattern generating circuit able to test the internal state of the memory cell array before shipment of the semiconductor device. Thus, in embodiments of the present invention, if the address signals are row address signals for the memory cell array, for example, the least significant bit signal of the row address signals changes alternately between "0" and "1" every time each adjacent row address (namely, each of even row address and odd row address) is input in turn. As a result, it is possible to automatically generate the desired test pattern (the checkerboard pattern, for example), by processing logically the above least significant bit signal and the predetermined control signal. Reference is made, by way of example, to the accompanying drawings in which:- Figure 1 is a schematic block diagram illustrating the overall constitution of a semiconductor devices to which the present invention pertains; Fig. 2 is a circuit diagram illustrating the constitution of the test pattern generating circuit and the connections between the test pattern generating circuit and the memory cell array in a semiconductor device according to one embodiment of the present invention; Fig. 3 is a circuit diagram illustrating an example of a memory cell in the memory cell array, and a selector, a write amplifier, and a sense amplifier connected to the memory cell shown in Fig. 2; Fig. 4A and Fig. 4B are diagrams illustrating the test pattern generated by the test pattern generating circuit shown in Fig. 2; Fig. 5 is a circuit diagram illustrating the constitution of the test pattern generating circuit and the connections between the test pattern generating circuit and the memory cell array in a semiconductor device according to another embodiment of the present invention; and Fig. 6 is a diagram illustrating the test pattern generated by the test pattern generating circuit shown in Fig. 5. Figure 1 is a schematic block diagram illustrating the overall constitution of a semiconductor device incorporating a memory cell array. As shown in Fig. 1, there are provided a memory cell array 1 (for example, RAM) and a logic circuit area 10 on a chip 12, which logic circuits transmit or receive signals (for example, address signals A₀ to A n and data signals D₀ to D m ) to or from the memory cell array 1. There are provided a counter circuit 101 and an arithmetic logic unit (ALU) 102, for example, in the above logic circuit area 10. The address signals A₀ to A n for the memory cell array 1 are supplied from the output side of the counter circuit 101. Data D₀ to D m which has been calculated in the ALU 102 is supplied from the output side of ALU 102 to the memory cell array 1 and written into predetermined memory cells of the memory cell array 1. Predetermined data read from the memory cell array 1 is also supplied to the input side of the ALU 102 in order to carry out a predetermined calculation in the ALU 102 again, for example. Input and output circuits 11 are provided around the chip 12. Signals are transmitted between the above semiconductor device and the external circuit through the I/O circuits 11. Figure 2 illustrates the constitution of a test pattern generating circuit and connections between the test pattern generating circuit and the memory cell array in a semiconductor device according to one embodiment of the present invention. In Fig. 2, there is shown a memory cell array (RAM) 1. Only row address signals A₀ to A n are supplied as the address signals, i.e., no column address signals are used. The row address signals A₀ to A n are input to corresponding address buffers 2. The address buffers 2 output the internal row address signals A₀, A₀ (the inverted signal of the signal A₀) to A n , A n (the inverted signal of the signal A n ), respectively, and supply these internal row address signals to the corresponding row decoders 3. The row decoders 3 select the predetermined word line (for example, WL₀) and supply the selecting signal (for example, high level signal) to that selected word line WL₀ according to the level of the above internal row address signals. In this embodiment, both write word lines and read word lines are used as word lines. Thus, when the data is written into the memory cell array 1, the level of the write enable signal WE becomes low, and a switching circuit 4 supplies the selecting signal to the selected write word line (for example, WWL₀). When the data is read from the memory cell array 1, the level of the write enable signal WE becomes high, and the switching circuit 4 supplies the selecting signal to the selected read word line (for example, RWL₀). Also, selectors 5 and write amplifiers 6 are connected to the data input side of the memory cell array 1. Sense amplifiers 7 are connected to the data output side of the memory cell array 1. When a control signal CNT2 supplied from the outside to the selectors 5 becomes high level, for example, the test data T₀ to T m supplied from the test pattern generating circuit 8 is input through the selectors 5, the write amplifiers 6, and the write bit lines WBL₀ , WBL₀ , WBL₁ , WBL₁ , and the like, to the memory cells connected to the selected word line in the memory cell array 1. On the other hand, when the control signal CNT2 supplied to the selector 5 becomes low level, for example, the usual data D₀ to D m supplied from the logic circuit area 10 is input through the selectors 5, the write amplifiers 6, and the above write bit lines to the memory cells connected to the selected word line in the memory cell array 1. Also, the output data X₀ to X m which is read from the memory cells connected to the selected word line in the memory cell array 1 is output through the read bit lines RBL₀ , RBL₁ , and the like, and the sense amplifiers 7. Also, there is provided a test pattern generating circuit 8 which generates test data to be written into the memory cell array 1 to test the array 1. In the test pattern generating circuit 8, there are provided AND gates 83, 84, 85, 86, and the like. The least significant bit signal A₀ of the row address signals A₀ to A n and the inverted signal A₀ produced by inverting the signal A₀ through an inverter 81 are input to AND gates 83 and 84, respectively. Also, the above signals A₀ and A₀ are input to the following AND gates 85 and 86, respectively. Similarly, the above signals A₀ and A₀ are input to the further following AND gates in the same manner. A control signal CNT1 is input from the outside to the AND gates 83 and 85, through an inverter 82, and to the AND gates 84 and 86 directly. Similarly, the above control signal CNT1 is input to the further following AND gates in the same manner. The output signals of a pair of AND gates 83 and 84 are input to an OR gate 87, from where the test data T₀ is output. Also, the output signals of a pair of AND gates 85 and 86 are input to an OR gate 88, from where the test data T₁ is output. Similarly, the output signals of each pair of AND gates are input to the corresponding OR gate, from where the test data T₀ to T m is output. Thus, if all of the row address signals A₀ to A n are low level, and the word line WL₀ is selected by the row decoders 3, the least significant bit signal A₀ of the row address signals supplied to the test pattern generating circuit 8 is also low level. Thus, the low level signal A₀ is input to each of AND gates 83, 86 -----, and the inverted high level signal A₀ is input through the inverter 81 to each of AND gates 84, 85 -----. At this time, if the control signal CNT1 supplied to the test pattern generating circuit 8 is set to low level, the low level control signal is input directly to each of AND gates 84, 86 -----, and the inverted high level signal produced by inverting the control signal CNT1 through the inverter 82 is input to each of AND gates 83, 85 -----. As a result, both the output signals of AND gates 83 and 84 become low level, and, thus, the output signal of the OR gate 87 also becomes low level. Therefore, the test data T₀ is output as the low level signal (namely, "0"). On the other hand, as the output signal of the following AND gate 85 becomes high level, the output signal of the OR gate 88 also becomes high level (although the output level of the AND gate 86 is low). Thus, the test data T₁ is output as the high level signal (namely, "1"). Similarly, the test data T₀ to T m of the predetermined level is output from the test pattern generating circuit 8. As a result, when the control signal CNT2 supplied to the selectors 5 is set to high level and the write enable signal WE supplied to the switching circuit 4 is set to low level, each of the test data T₀ to T m which alternately changes between "0" and "1", as shown in the first row of the pattern shown in Fig. 4A, is written into each memory cell (for example, 1-00) connected to the selected write word line WWL₀ in the memory cell array 1. Next, if the word line WL₁ is selected by changing the levels of the row address signals A₀ to A n , then the above least significant bit signal A₀ supplied to the test pattern generating circuit 8 becomes high level. Therefore, at this time, each of the test data T₀ to T m which alternately changes between "1" and "0", as shown in the second row of the pattern shown in Fig. 4A, is written into each memory cell connected to the selected write word line WWL₁ in the memory cell array 1, through a similar operation as above-mentioned and so on. Thus, each of the test data which alternately changes between "0" and "1" as shown in Fig. 4A (namely, each of the test data constituting the above-mentioned checkerboard pattern) is written into each memory cell in the memory cell array 1. Although in the above-mentioned embodiment, the active level of the control signal CTN1 is set to the low level, if the active level of the control signal CNT1 is set to the high level, each of the test data constituting another checkerboard pattern as shown in Fig. 4B is written into each memory cell in the memory cell array 1. Figure 3 is a circuit diagram of an example of a memory cell (for example, 1-00) in the above memory cell array 1 and a selector 50, a write amplifier 60, and a sense amplifier 70 connected to the above memory cell. As shown in Fig. 3, there are provided an inverter 501, AND gates 502 and 503, and an OR gate 504 in a selector 50. When the above-mentioned control signal CNT2 becomes high level, the test data T₀ supplied from the test pattern generating circuit 8 is input to the write amplifier 60 through the gates 502 and 504. On the other hand, when the control signal CNT2 becomes low level, the usual data D₀ supplied from the logic circuit area is input to the write amplifier 60 through the gates 503 and 504. In the write amplifier 60, there are provided an amplifier 601 and an inverter 602. The write amplifier 60 is connected to the memory cell 1-00 through the write bit lines WBL₀ and WBL₀ . In the memory cell 1-00, there are provided a plurality of transistors Q₁ to Q₈ (among these, transistors Q₁ and Q₂ are P-channel type transistors, and transistors Q₃ to Q₈ are N-channel type transistors). The memory cell 1-00 is connected to the write bit lines WBL₀ and WBL₀ , the read bit line RBL₀ , the write word line WWL₀ , and the read word line RWL₀. A P-channel type transistor Q₉ is connected between the power source V DD and the read bit line RBL₀ , and a clock signal CLK is supplied to the gate of the transistor Q₉. When data is written into the memory cells connected to the write word line WWL₀ , the voltage level of the selected word line WWL₀ becomes high. At this time, if the data T₀ or D₀ of high level (namely, "1"), for example, is to be written into the memory cell 1-00 through the selector 50, the voltage level of the write bit line WBL₀ supplied through the amplifier 601 becomes high, and, contrary to this, the voltage level of the write bit line WBL₀ supplied through the amplifier 601 and the inverter 602 becomes low. Thus, in the memory cell 1-00, the transistor Q₅ turns on, and the voltage level of the connection point A between the transistors Q₂ and Q₄ becomes high. Thus the data "1" is written into the memory cell 1-00. Further, at this time, the transistor Q₆ also turns on, and the voltage level of the connection point B between the transistors Q₁ and Q₃ becomes low. Thus, the above-mentioned high level voltage at the connection point A is latched. In this connection, when the data is written into the memory cell, the clock signal CLK becomes low level, and, thus, the memory cell 1-00 is charged up through the P-channel type transistor Q₉ and the read bit line RBL₀ by the power source V DD . When the data is read from the memory cells connected to the read word line RWL₀ , the voltage level of the selected word line RWL₀ becomes high, and, thus, the transistor Q₇ turns on. At this time, the above clock signal CLK becomes high level, and the transistor Q₉ turns off. When the data "1" has been written into the memory cell 1-00 as above-mentioned, the transistor Q₈ turns off (because the gate level of the transistor Q₈ is low level) . Thus, the high level data X₀ produced by the above-mentioned charging up is output through the transistor Q₇ , the read bit line RBL₀ , and the sense amplifier 70 in which an amplifier 701 is provided. Contrary to this, if the data "0" is written into the memory cell 1-00, the transistor Q₈ turns on (because the gate level of the transistor Q₈ becomes high). Thus, the level of the read bit line RBL₀ becomes low (namely, the level of V ss ) by the discharging through the transistor Q₈ , and the low level data X₀ is output through the sense amplifier 70. Figure 5 illustrates the constitution of the test pattern generating circuit and the connections between the test pattern generating circuit and the memory cell array in a semiconductor device according to another embodiment of the present invention. In Fig. 5, there is shown the memory cell array (RAM) 1' to which in this case both row address signals and column address signals are supplied as address signals. As shown in Fig. 5, there are provided address buffers 2', row decoders 3', column decoders 4', selectors 5', write amplifiers 6', column selectors 7', and sense amplifiers 8'. In the embodiment shown in Fig. 5, the memory cell array 1' is physically constituted in the size of four row addresses and four column addresses, as shown in Fig. 6. The address signals A₀ to A₂ are input to the corresponding address buffers 2'. The address buffers 2' output the internal column address signals A₀ and A₀ and the internal row address signals A₁ , A₁ , A₂ , and A₂ and supply these internal address signals A₀ to A₀ and A₁ to A₂ to each of the column decoders 4' and the row decoders 3'. The row decoders 3' select the predetermined row address according to the level of the internal row address signals A₁ to A₂ . Also the column decoders 4' select the predetermined column address according to the level of the internal column address signals A₀ and A₀ . Also, the selectors 5' and the write amplifiers 6' are connected to the data input side of the column selectors 7'. The sense amplifiers 8' are connected to the data output side of the column selectors 7'. At the time that the data is to be written into the memory cell array by the control of the usual write enable signal, if a control signal CNT2 supplied from the outside to the selectors 5' becomes high level, for example, test data of two bits T₀ and T₁ supplied from the test pattern generating circuit 9 are input through the selectors 5', the write amplifiers 6', and the column selectors 7' to predetermined memory cells in the memory cell array 1'. Contrary to this, if the control signal CNT2 becomes low level, for example, the usual data of two bits D₀ and D₁ supplied from the logic circuit area 10 is input through the selectors 5', the write amplifiers 6', and the column selectors 7' to the predetermined memory cells in the memory cell array 1'. On the other hand, at the time that the data is to be read from the memory cell array 1', the data X₀ and X₁ is output from the predetermined memory cells through the column selectors 7' and the sense amplifiers 8'. In this connection, the column selectors 7' select two column addresses as the addresses to or from which the above data of two bits are input or output, according to the output level of the column decoders 4'. Also, there is provided a test pattern generating circuit 9 which generates the test data to be written into the memory cell array 1' in order to test the memory cell array 1'. In the test pattern generating circuit 9, there is provided an exclusive NOR gate 91 to which both of the least significant bit signal A₁ of the row address signals and the least significant bit signal A₀ of the column address signals are supplied. In this connection, there is only one bit signal A₀ for the column address signal in this embodiment, and therefore, the above signal A₀ is also the least significant bit signal of the column address signals. The output signal of the exclusive NOR gate 91 becomes high level when both levels of the above supplied signals coincide (namely, both high or both low), and becomes low level when the levels of the above supplied signals do not coincide. The output signal of the exclusive NOR gate 91 is input to each of the AND gates 94 and 96 directly and is input to each of the AND gates 95 and 97 through an inverter 92. Further, a control signal CNT1 is input from the outside to each of the AND gates 94 and 96 directly and is input to each of the AND gates 95 and 97 through an inverter 93. The output signals of a pair of AND gates 94 and 95 are input to an OR gate 98, from where the test data T₀ is output. Similarly, the output signals of a pair of AND gates 95 and 97 are input to an OR gate 99, from where the test data T₁ is output. Then, the test data T₀ and T₁ is input to the above-mentioned selectors 5'. When the test data is to be written into each memory cell in the memory cell array 1', if all of the address signals A₀ to A₂ are set to the low level, the output level of the exclusive NOR gate 91 becomes high. Thus, the above high level signal is supplied to AND gates 94 and 96 directly, and the low level signal produced by inverting that high level signal through the inverter 92 is supplied to the AND gates 95 and 97. Also, if the active level of the control signal CNT1 is high level, the high level control signal CNT1 is supplied to the AND gates 94 and 96 directly, and the low level signal produced by inverting that control signal CNT1 through the inverter 93 is supplied to the AND gates 95 and 97. As a result, each output level of the AND gates 94 and 96 becomes high, and, thus, each output level of OR gates 98 and 99 (namely, each level of the test data T₀ and T₁) becomes high. Thus, the high level test data "1" is written into the predetermined two memory cells arranged at the intersection of the row address selected when the row address signals A₁ and A₂ are both low level (namely, the top row address in the pattern shown in Fig. 6) and each of two column addresses selected when the column address signal A₀ is low level (namely, the first and third column addresses from the left side in the pattern shown in Fig. 6). Similarly, if the address signals A₀ and A₂ are set to the high level and the address signal A₁ is set to the low level, all output levels of AND gates 94 to 97 become low, and, as a result, each output level of the OR gates 98 and 99 (namely, each level of the test data T₀ and T₁) becomes low. Thus, the low level test data "0" is written into the predetermined two memory cells arranged at the intersection of the row address selected when the row address signals A₁ and A₂ are low level and high level respectively (namely, the third row address from the top side in the pattern shown in Fig. 6) and each of two column addresses selected when the column address signal A₀ is high level (namely, the second and fourth column addresses from the left side in the pattern shown in Fig. 6). Further, by repeating a similar operation, each test data constituting the checkerboard pattern as shown in Fig. 6 is written into each memory cell in the memory cell array 1'. In this connection, if the active level of the control signal CNT1 is set to the low level, it is obvious that each data written into each memory cell is inverted. As described above, according to the present invention, it is possible to automatically generate a pattern of the test data (for example, a checkerboard pattern) and to transmit the test pattern to the memory cell array just by supplying address signals for the memory cell array, without the necessity of supplying test data from the outside. Although in the above-described embodiments a checkerboard pattern of test data is generated, it will be understood that in other embodiments of the invention a different pattern of test data may be generated, by providing a suitable arrangement of a test pattern generating circuit.

Claims: A semiconductor device comprising:- a memory cell array (1); a test pattern generating circuit(8); and selector means (5) for receiving a control signal (CNT2) from the outside; said test pattern generating circuit (8) being operable to generate a test pattern using address signals including a least significant bit signal (A₀), and said selector means (5) being operable, in response to said control signal (CNT2), to transmit said test pattern to said memory cell array (1); characterised in that:- said test pattern generating circuit (8) includes first logic circuitry (83, 84, 87) and second logic circuitry (85, 86, 88) each arranged to receive said least significant bit signal (A₀), an inverted signal of said least significant bit signal, a further control signal (CNT1) received from the outside, and an inverted signal of said further control signal; the first logic circuitry (83, 84, 87) performing the logical function of ANDing the least significant bit signal (A0) with the inverted further control signal ( CNT1 ), of ANDing the inverted least significant bit signal ( A0 ) with the further control signal (CNT1), of ORing the result of both said ANDings and outputting the result of the ORing as test data (T0, T2, T4, ...), and the second logic circuitry (85, 86, 88) performing the logical function of ANDing the inverted least significant bit signal ( A0 ) with the inverted further control signal ( CNT1 ), of ANDing the least significant bit signal (A0) with the further control signal (CNT1), of ORing the result of both said ANDings and outputting the result of the ORing as test data (T1, T3, T5, ...); whereby the logic circuitries output a sequence of test data (T0, T1, T2, T3, ...) of alternate 0s and 1s or a sequence of alternate 1s and 0s, dependent on the further control signal (CNT1) (Fig.2) A semiconductor device comprising:- a memory cell array (1'); a test pattern generating circuit (9); and selector means (5') for receiving a control signal (CNT2) from the outside; said test pattern generating circuit (9) being operable to generate a test pattern using address signals including two least significant bit signals (A₀, A₁), and said selector means (5') being operable, in response to said control signal (CNT2), to transmit said test pattern to said memory cell array (1'); characterised in that:- said test pattern generating circuit (9) includes first logic circuitry (94, 95, 98) and second logic circuitry (96, 97, 99) each arranged to receive a signal derived from said two least significant bit signals (A₀, A₁) by exclusive NORing, a further control signal (CNT1) received from the outside, and an inverted signal ( CNT1 ) of said further control signal; the first logic circuitry (94, 95, 98) performing the logical function of ANDing the result of said exclusive NORing of said two least significant bit signals (A₀, A₁) with said further control signal (CNT1), of ANDing the result of the inversion of the result of said exclusive NORing of said least significant bit signals (A₀, A₁) with said inverted signal of said further control signal ( CNT1 ), of ORing the result of both said ANDings and outputting the result of the ORing as test data (T0); and the second logic circuitry (96, 97, 99) performing the logical function of ANDing the result of said exclusive NORing of said two least significant bit signals (A₀, A₁) with said further control signal (CNT1), of ANDing the result of the inversion of the result of said exclusive NORing of said least significant bit signals (A₀, A₁) with said inverted signal ( CNT1 ) of said further control signal, of ORing the result of both said ANDings and outputting the result of the ORing as test data (T1); whereby the logic circuitries output the same test data (T0, T1) both being 0 or 1 dependent on the further control signal (CNT1) (Fig. 5). A semiconductor device according to claim 1 or 2, wherein the test pattern is a checkerboard pattern.

Inventors: NAITOH, MITSUGU, SUEHIRO, YOSHIYUKI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G11C29
IPC codes: G06F15, G11C29, G11C11, G01R31, G06F11