TRI-WELL CMOS TECHNOLOGY

Abstract: A semiconductor structure having at least three types of wells (65, 68, 71) which may be of different doping levels and methods of manufacturing such a structure. In one method, regions which will become active devices are protected with a nitride layer (62) as the associated well-regions (65, 68, 71) are implanted. In another method, previously implanted wells are covered with thick oxide (66, 69) which in combination with the nitride layer (62) provides automatic alignment of adjacent wells. In yet another method, implanted wells are covered with oxide (66) while a last well is implanted with this last well being defined by both thick oxide (66) and photoresist (67a). All methods avoid a masking step and avoid the need for aligning the edge of a later photoresist mask with the edge of an earlier photoresist mask. The structures formed by these methods may have heavily-doped P wells, heavily-doped N wells, and lightly-doped P or N wells, or both, for forming higher breakdown voltage devices on the same chip with lower breakdown voltage devices.

Description: 1 TRI-WELL CMOS TECHNOLOGY 2 3 4 * This is a continuation-in-part of application Serial " No. 06/614,418, filed by the same inventors on May 25, 7 1984. δ 9 BACKGROUND OF THE INVENTION ™ This invention relates to a tri-well CMOS structure H and method of manufacture which provides at least three 12 kinds of active regions for device formation. The active 13 regions may include lightly doped regions of either N or P 1 type for the formation of devices having a high breakdown 15 voltage, moderately to heavily doped P wells for N channel 16 devices having a low breakdown voltage, and moderately to 17 heavily doped N well regions for P channel devices having 1° a low breakdown voltage. 19 A prior art P well CMOS structure is illustrated in 20 Fig. la. P well 1 is diffused into a silicon substrate 2 . 21 Silicon substrate 2 has been moderately doped with N type 22 dopants to a level within the range of approximately 9 ". 2 x 1015 to 4 x 1015 atoms/cm3. Source and dram regions 24 4 and 5 respectively of an N channel device 3 having a 25 gate 6 are then formed in P well 1, and source and drain 26 regions 8 and 9 of a P channel device 7 having a gate 10 27 are formed in N type substrate 2. 28 In practice, due to processing variations, there is 29 some deviation between the actual doping levels achieved 30 in the P well and the N substrate, and their desired doping 31 levels. For control purposes, in order to render these 32 deviations less significant, the doping of P well 1 is at 33 least an order of magnitude greater than the doping of N 34 substrate 2, thereby insuring that, regardless of process¬ 35 ing variations, P well 1 will have a sufficiently high 36 concentration of P type dopants. 37 38 Problems of scale emerged from the prior art structure ^ 9 as the device densi.ty i.e., the number of devi.ces per unit 3 area, was increased. For example, as the distance between the P+ source and drain regions 8 and 9 of device 7 is reduced, the doping of N substrate 2 must increase to obtain appropriate electrical parameters, such as device threshold voltage, in the shorter channel length P channel Q w transistor 7. However, increasing the doping of N sub- Q * strate 2 requi.res a correspondi.ng proporti.onal increase m. 0 the doping level of P well 1 for control purposes as explained above. 2 The increase in the doping level of P well 1 causes 3 increased junction capacitance between N+ source and drain 4 regions 4 and 5 and P well 1. In fact, for a single-sided 5 junction under zero bias, the junction capacitance varies 6 directly as the square root of the dopant concentration on 7 the lightly doped side of the junction, as shown in MOS 8 INTEGRATED CIRCUITS, pgs. 45 and 46, Engineering Staff of 9 American Micro-Systems, Robert E. Krieger Pub. Co., Malibu, 0 Fla. (1979), which is incorporated herein by reference. 1 in turn this increased capacitance has the undesirable 2 effect of reducing the switching speed of transistor 3. 3 In order to overcome these problems of scale, a 4 twin- ub CMOS technology was developed by Parrillo, et 5 al., in "TWIN-TUB CMOS-A TECHNOLOGY FOR VLSI CIRCUITS", 6 IEEE Tech. Dig., Int. Electron Device Meet., 1980, 7 p. 752-755 which is incorporated herein by reference. 8 Fig. lb illustrates the Parillo Twin-tub structure. 9 The Parillo structure includes lightly doped epitaxial 0 region 20 formed on an N+ substrate 21. The use of an N+ 1 substrate reduces the substrate resistance and prevents 2 "latch-up", a term which refers to the turning on of 3 "parasitic" bipolar transistors within the structure shown 4 in Fig. lb as will be explained later. 5 Both a P well 23 and an N well 24 are then formed in 6 the epitaxial layer 20 by ion implantation. This is 7 accomplished in a self-aligned manner by first defining an 8 oxide-nitride mask (not shown), implanting and selectively 9 . . ώ oxidmg N well 24, removing the remaining mask and lmplant- 3 ing P well 23 self-aligned to the oxide masked N well 24. 4 The P well 23 and N well 24 are doped independently 5 in order to optimize the performance characteristics of ° the active devices formed in P well 23 and N well 24, 7 respectively. For example, the active devices may include ° transistor 28 having gate 27, gate dielectric layer 33 and q , source and drain regions 25 and 26, respectively, formed 10 in P well 23 and transistor 32 having gate 31, gate di¬ ll electric layer 33, and source and drain regions 29 and 30 1 formed in N well 24. Thus it can be seen that increasing 13 the doping of N well 24 to accommodate a decrease in the 14 dimensional parameters of the P channel device 32 no 1 longer necessitates a corresponding increase in the dopant 16 concentration of P well 23. Of importance, parasitic 17 bipolar transistors exist within this twin well structure. 18 For example, an NPN parasitic transistor is formed by N+ 19 region 26, P well 23, and N+ substrate 21. However, the 0 N+ substrate has low resistivity and thus prevents "latch-up". Latch-up is a well-known problem, an analysis 2 of which is' presented in an article entitled "Elimination 3 of Latch-up in Bulk CMOS", IEDM Paper 10.2, December 8-10, 4 Washington, D.C., which is incorporated herein by reference, 5 Both N well 24 and P well 23 in the prior art twin-tub 6 structure described by Parillo are heavily doped. Parillo 7 uses a dopant concentration of about 10 atoms/cm at the 8 surface of each well. Because of the relatively high 9 doping in both wells, this structure is not well suited to 0 integration with devices such as transistors, diodes, or 1 resistors which are designed to operate at high voltages, 2 say greater than 20 volts. In particular the prior art 3 twin-tub structure is not suited for the integration of 4 erasable programmable read only memories (EPROMS) or with 5 electrically erasable programmable read only memories 6 (EEPROMS) which require junction breakdown voltages greater 7 than approximately 20 volts. 8 In addition to the need for providing both high and low voltage devices on the same chip, and thus providing a variety of doping levels for different wells, it is desir- able to develop methods for forming structures which are faster and less expensive, and allow for forming smaller devices while retaining high yield. Various prior art methods have been developed to accomplish the objective of providing on the same chip different doping levels and dopants for different wells. A method shown in Figures 2a and 2b forms multiple windows in a nitride/oxide layer, exposing the surface to permit the subsequent formation of diffusion isolation regions, base regions, and collector contact regions in the semiconductor body. The areas are masked, exposed, and doped in a predetermined sequence. The original areas of oxide/nitride, which were left between windows serve to define the edges of the wells, and on these areas of oxide/nitride the edges of successive photoresist masks are defined. Mask misalignment tolerances can be less stringent because the edges of the masks are formed over the previously formed areas of nitride/oxide and the nitride/oxide serves to define the edge of the well. U.S. patent No. 3,928,081 to Marley, Jr., et al., shows such ' a method for eliminating mask misalignment tolerances. As shown in Figs. 3a and 3b, U.S. Patent 4,450,021, issued to Batra, et al., one of the coinventors of this application, uses a mask 109 for defining regions 110 to be doped and uses the same mask for depositing a protective layer 111 over the doped regions. With this arrangement, the alignment of the edge of the protective layer 111 is assured, because the edge of the oxide defines the area to e doped. When the mask is removed, the second regions ιi2 which are now exposed are automatically aligned to be doped without interfering with the first regions which are covered by protective layer 111. By this method it is possible to achieve doping of two wells with one masking step, thus saving the time of applying and defining the mask and thus also achieving automatic self-alignment of the areas to be doped. The method shown in this prior art patent is described as being applicable to implanting source and drain regions in the chip. Thus, use of portions of the device as a mask for forming later portions is a well-known method of preven - ing misalignment. Cerofolini, et al., in U.S. Patent No. 4,277,291, discloses a di.fferent method, shown i.n Figs. 4a and 4b, which could be used for forming adjacent, self-aligned N and P wells in which a heavily N-doped oxide mask is in place during P-doping and diffusion. The N-doped oxide mask prevents doping of the masked portion during the p-doping step and then produces diffusion of the N-dopant from the doped oxide into the substrate at the same time the P-doped region is being diffused into the substrate, resulting in simultaneous formation of self-aligned N and P wells. SUMMARY The present invention provides a semiconductor struc¬ ture having at least three active regions for device formation formed in a lightly doped substrate, for example, a first moderately to heavily doped well of the same conductivity type as the substrate, a second moderately to heavily doped well having conductivity type opposite to that of the substrate, and a third lightly doped region of either type having a conductivity of the same order of magnitude as the substrate. In one embodiment of the structure the third region is a portion of the substrate itself. T e present invention also provides a method of forming a semiconductor structure which requires fewer masking steps than the number of wells to be formed in the substrate. Two embodiments of this method are described, both achieving a tri-well substrate using only two photo- masking steps. Both methods are appropriate for applica- tions in which the multiple devices on a chip will be separated by a thick field oxide. With the first method adjacent wells are not self-aligned. The first method involves placing an oxide/nitride layer over regions which will become active devices and doping through the nitride the substrate of the active device and the adjacent exposed field. The second method involves first defining an exposed region to be doped, then doping that region to form a well in which the field and active region of a device will be formed, then covering that region with a thick oxide layer. Using a second photoresist mask, another area of thin oxide/nitride is removed, with the newly formed thick oxide and/or the oxide/nitride serving to define edges of the second exposed area, and so on with subsequent regions. This order of formation causes subse- quent well regions to be automatically self-aligned with previous well regions and also results in a process for forming successive well regions requiring fewer masking steps than the number of wells, in contrast to previous methods. This improvement in turn results in allowing a. higher yield of smaller devices at a lower manufacturing cost. Neither method requires accurate alignment of a photoresist mask with a previous photoresist mask. Alter- native embodiments are also described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. la shows a prior art P well CMOS structure. Fig. lb shows a prior art twin-tub CMOS structure. Figs. 2a and 2b show a prior art method of forming windows for the subsequent formation of doped wells followed in series by separate masking of subsequent wells. Figs. 3a and 3b show a prior art method of using an oxide region to define the edge of a well to be doped followed by growing an oxide or nitride mask over the doped region before removing the photoresist mask. Figs. 4a and 4b show a prior art method of growing adjacent wells using a mask of heavily-doped oxide which implants dopants of one conductivity type while dopants of opposite conductivity type are implanted into an exposed adjacent area. Fig. 5 shows one embodiment of the tri-well CMOS structure constucted in accordance with this invention. Fig. 6 shows a second embodiment of the tri-well CMOS structure constructed in accordance with this invention. Figs. 7a through 7j show steps in forming three wells of different compositions using the method of this inven- tion in an embodiment where active devices will be formed after formation of the wells, and where adjacent wells are not self-aligned. Figs. 8a through 8h show steps in forming three wells of different composition using the method of this invention where adjacent wells are self-aligned. Figs. 8i and 8j show a device having two implanted, self-aligned wells and a third self-aligned high voltage region available for active device formation. Figs. 9 through 11 show steps of well known design used to form a device upon the substrate which was formed as shown in Figs. 7a through 7j or Figs 8a through 8h according to the method of this invention. DETAILED DESCRIPTION one embodiment of a structure constructed in accord- ance with this invention is depicted in cross sectional view in Fig. 5. The region 40 is a lightly doped P type semiconductor substrate, typically silicon. Alternatively, region 40 is epitaxial semiconductor material formed on an underlying substrate. For simplicity, this specification will refer to region 40 as a substrate. in this embodiment, substrate 40 is a P type silicon semiconductor having a resistivity in the range of approxi- mately 30 to 100 ohm-cm. For a P type silicon substrate, 2 a resistivity of approximately 30 to 100 ohm-cm corresponds J -\ to an impurity concentrati .on of approxi.mately 1 x 1014 to / , 14 3 ^ 2.5 x 10 P type atoms/c in the substrate. This is shown in Grove, Physics and Technology of Semiconductor 6 Devices, pgs. 111-113, John Wiley & Sons (1967) which is 7 incorporated herein by reference. In general, the resis¬ ts ° tivity of the substrate decreases as the impurity concen- 9 tration in the substrate increases. 0 Since resistivity, p, is the reciprocal of conduc- tivity, σ, (i.e., σ = 1/ρ), one may equivalently specify 2 the corresponding conductivity of the substrate. in turn the breakdown voltage for several important 4 classes of PN junctions is inversely proportional to the 5 substrate impurity concentration. For example, a so- called one-sided step junction, which is an abrupt junction 7 wherein the impurity concentration in each of the P and N 8 regions is uniform throughout that region and wherein the 9 concentration of the impurity on one side of the junction 0 is much larger than on the other side of the junction, has 1 the property that the junction breakdown voltage isf inverse- 2 iy proportional to the substrate dopant concentration for 3 a constant critical field as shown in Grove, supra, at pg. 24 194, which is incorporated herein by reference. Similary, very shallow diffused junctions behave very much like 26 one-sided step junctions. See Grove, supra, at pg. 159. 27 Thus low P type impurity concentrations in the sub- 8 strate 40 and region 43, typically of the order of 1 x 10 n i4 3 ώ? to 2.5 x 10 atoms/cm , permit the formation of active 30 devices in region 43 having high junction breakdown volt- 31 ages (greater than 20 volts). In another embodiment, 32 region 43 is simply a portion of the substrate 40. 33 N well 41 is an N type region formed in substrate 40, 34 typically by ion implantation, having moderate to heavy 35 dopant levels of an N type material, for example, within J O ϋ m the range of approximately 8 x 10 " 4 to 3 x 10X6 atoms/cm3. 3 Alternatively, well known diffusion processes can be used 38 to form N well 41. The N well 41 is suitable for the 1 formation of low voltage devices, for example P channel 2 transistors, resistors or diodes (not shown). 3 P well 42 is a region of moderate to heavily doped P 4 type semiconductive material formed (typically by ion 5 implantation or diffusion) in the substrate 40. The P type dopant concentration in P well 42 ranges from approxi- ■ 7 14 16 3 ' mately 8 x 10 to 3 x 10 atoms/cm . P well 42 is suitable for the formation of low voltage devices, for 9 example resistors, diodes, or N channel transistors. 10 p well 42 and N well 41 of Fig. 5 are doped indepen- 11 dently to achieve desired electrical characteristics, e.g. 12 threshold voltages, which depend on dopant levels, of the 13 p channel and N channel devices formed therein. Region 43 14 is a lightly-doped region of P type semiconductive material. 15 Typically the dopant level in region 43 is within the ιo c range of approxi ■mately 1 x 1014 to 4 x 1014 or more P type 17 atoms/cm and is thus suitable for the formation of devices 18 having high junction breakdown voltages (greater than 20 19 volts) in close proximity to the low voltage devices 20 formed in P well 42 and N well 41. 21 The above embodiment uses a P type substrate. An N 22 type substrate can also be used, where well region 43 is 23 of P type conductivity. However when an N type substrate 24 is used, it should be noted that generally lower impurity 25 concentrations produce the same resistivity, as shown in 26 Grove, supra, at page 113. For example, a substrate 27 resistivity of 10 to 50 ohm-cm corresponds to an N type 28 impurity concentration of approximately 4 x 10 to 29 i x ιo 14 atoms/cm 3 . 30 it is also important to note that the arrangement of 31 the regions 41, 42, and 43 shown in Fig. 5 is not critical. 2 For example in another embodiment, as shown in Fig. 6, 3 N well 51 and region 53 are separated by P well 52. In 4 this embodiment, region 53 has the same conductivity type 5 as the substrate 50 and a conductivity of the same order 6 of magnitude as substrate 50. 7 8 1 One process for forming a tri-well CMOS structure 2 according to the present invention is illustrated in 3 Figs. 7a through 7j. Another begins with Fig. 7a and 4 moves to Figs. 8a-8h. In either case, the process begins 5 with a lightly doped substrate 60 of either N type or P type. When substrate 60 is P type, a dopant concentration -j . 4 3 . ' of approximately 1x10 atoms/cm is typical. An N type substrate would have a lower dopant concentration. 9 Fig. 7a shows a lightly doped semiconductor structure 0 with a base oxide layer and a nitride layer formed thereon. 1 Base oxide layer 61 is formed on substrate 60 to a thick- 2 ness within the range of approximately 500 to 1000A, for 3 example by thermal oxidation at approximately 1000°C for 4 approximately 45 to 75 minutes in an atmosphere of 0_ + 3% 5 HCL. 6 Nitride layer 62 is formed on base oxide layer 61 7 using, for example, low pressure chemical vapor deposition 8o (LPCVD) to a thickness of approximately 1500A °. Oxide 61 9 separates nitride 62 from substrate 60 and thus allows 0 nitride 61 to be completely removed at a later stage. 1 2 First Embodiment 3 According to one method for forming the separately 4 implanted well regions of this invention, base oxide 61 5 and nitride layer 62 shown in Fig. 7a are then patterned 6 to define the active regions of the device shown in Fig. 7 7b. The active regions remain covered by oxide 61 and 8 nitride 62 while the adjacent field regions are exposed. 9 This patterning is accomplished by spinning photoresist 81 0 onto nitride 62 which is then soft baked. The field mask 1 is then aligned to the wafer flat and the portions of 2 photoresist exposed by the mask are subjected to actinic 3 radiation. Exposed portions of photoresist 81 are then 4 removed by development. Photoresist 81 is then hard baked 5 so that it is not affected by the etchants used to remove 6 the unmasked regions of nitride and oxide. Typically, 7 plasma etching is used to remove the unmasked regions of 8 nitride and buffered HF is used to remove the regions of oxide. The remaining portions of photoresist 81 are removed after the etching step in order to produce struc- ture 64 shown in Fig. 7c. As will be appreciated by those of ordinary skill in the art, if desired, the photoresist 81 and masking to define active areas (i.e., those areas located in substrate 60 beneath portions of oxide 61 and nitride 62 which remain in the structure of Fig. 7c) can be postponed until after formation of all desired well regions. A P well mask of photoresist 82 is formed on struc- ture 64 which exposes the P well (N channel) field and active regions 65. At this stage, the field regions are fully exposed and the active regions are partly protected by the nitride/oxide sandwich 61, 62 as shown in Fig. 7d. A field implant of P type dopants is then accom- pushed using boron at a dosage of approximately 3x10 ions/cm and an energy level of approximately 25 KeV. This step implants a shallow boron charge into the field regions which raises the field inversion potential, hence preventing parasitic field devices. Next, a P-well implant is performed using Boron at a T O O dosage of approximately 6x10 ions/cm at an energy level of approximately 120 KeV, which is sufficient that the P well is implanted through the nitride/oxide layer. AS shown in Fig. 7e, similarly, an N well mask of photoresist is used to expose N well (P channel) field and active regions 71. A field implant of N type dopants is then accomplished using phosphorus. The N well implant is performed using phosphorous at a dosage of approximately 1 o o 2x10 ions/cm at an energy of approximately 150 KeV. A high voltage region mask need not be formed when the lightly doped substrate itself serves as the high voltage region. However, if it is desired to adjust the dopant type or the dopant concentration in the high voltage region, a high voltage region mask (not shown) is formed using photoresist in order to expose field and active 1 regions 68 for high voltage devices. This step is follow- 2 ed by a high voltage region implant using a selected 3 impurity type. For example, for a P type high voltage /- region, a dopant concentration of approxi.mately 1x1014 to -> . 4x1014 P type atoms/cm3 is used. In one embodiment, the 6 field implant for the high voltage region is performed 7 together with either the N type or P type field implant 8 described above, as appropriate, depending on the dopant 9 type of the high voltage region. 0 Figure 7e illustrates the semiconductor structure 1 after the formation of the N well mask, N well implant, 2 and removal of the N well mask, formation of the P well 3 mask, P well implant, and removal of the P well mask, and 4 formation of the high voltage region mask, high voltage 5 region implant, and removal of the high voltage region 6 mask. 7 As shown in Fig. 7f, the dopants in the N well and P 8 well and high voltage region implants are then diffused 9 into substrate 60 by subjecting the wafer to an oxygen 0 atmosphere at about 1150°C for approximately 8 to 12 1 hours, which also forms a field oxide layer 101 with a 2 thickness of about 1000A. The field oxide 101 is then 3 further grown in a wet oxygen ambient at approximately 4 1000°C for approximately 2 to 4 hours to a final thickness 5 of about 6,000 to 10,000A. Field oxide 101 serves as 6 electrical isolation between adjacent active areas formed 7 within substrate 60. Fig. 7f shows the semiconductor 8 structure after field oxidation with N well 71, high 9 voltage region 68 and P well 65 formed in the substrate. 0 The dotted line around the high voltage region 68 in Fig. 1 7f indicates that this region may be the substrate itself 2 if no high voltage region implant is employed. 3 Nitride layer 62 is then removed, for example using a 4 phosphoric acid wet etch or a CF 4 plasma etch, in order to 5 form the semiconductor structure in Fig. 7g with nitride 6 layer 62 removed from the active areas. The base oxide 61 7 is then stripped from the active regions, for example by 8 etching with buffered HF, and a layer of gate oxide 102 is 2 formed over the entire semiconductor structure to a thick- J _ ness within the range of approximately 300-350A° as shown 4 in Fig. 7h, for example by thermal oxidation in dry oxygen 5 with approximately 3% HC1 at approximately 900°C for 6 approximately 90 minutes. If desired, after formation of 7 gate oxide layer 102, appropriate threshold adjustment implants are performed, as is well known in the art. q Polycrystalline silicon layer 103 (shown m Fig. 7ι) 0 o is then deposited to a thickness of approximately 3500A over the entire semiconductor structure, for example by * low pressure chemical vapor deposition. Polycrystalline silicon layer 103 serves as electrical interconnect, 4 device gate areas, and capacitor electrodes. Polycrys¬ 5 talline silicon layer 103 is doped with phosphorous to 6 decrease sheet resistance to approximately 20 to 30 ohms/ 7 square. 8 As shown in Fig. 7j , using photoresist and well-known 9 photolithigraphic and etching techniques (for example 0 etching with CF 4 plasma), gates 121, 122 and 123 for 1 active devices in the N well 71, high voltage region 68, 2 and P well 65 and doped polycrystalline silicon intercon . ■ nects (not shown) are then formed. 4 Second Embodiment 6 According to a second method for forming the separately implanted well regions of this invention in which adjacent well regions are automatically self-aligned, base oxide layer 61 and nitride layer 62 shown in Fig. 8a are then patterned to define one of the well regions of the device. Referring to Fig. 8a, this patterning is accomplished by spinning onto nitride layer 62 photoresist 63 which is then soft baked. The first well region mask is then aligned to the wafer and the portions of photoresist exposed by the mask are subjected to actinic radiation. Exposed portions 64 of the photoresist are then removed as shown in Fig. 8a. Photoresist 63 is then hard baked so that it is not affected by the etchants which will be used to remove the unmasked regions of nitride and oxide. Typically, plasma etching is then used to remove the unmasked regions of nitride, and buffered HF is used to remove the regions of oxide as shown in Fig. 8b. A P well implant 65 is performed using boron at a dosage of approximately 6x1012 ions/cm2 at an energy level of approximately 120 KeV. As shown in Fig. 8c, photoresist 63 is then removed. As shown in Figure 8d, following the doping of P well 65, a layer of oxide 66 is formed on the exposed region and the dopants in P-well 65 are simultaneously slightly diffused into substrate 60 by subjecting the wafer to an oxygen atmosphere within the range of approximately 900 to 1000°C for approximately 1-3 hours, which forms oxide layer 66 to a thickness of approximately 3,0O0A. As shown in Figure 8e, after formation of oxide 66, a second layer of photoresist 67a and 67b is applied and patterned to expose the area where the second well region will be formed. The exposed portions of nitride 62 and oxide 61 are removed (in a manner such as has been pre- viously described), exposing the area which will become a second well 68. The formation of this second well demonstrates a significant feature of this self-aligned method. On one side, oxide layer 66 rather than the second layer of photoresist 67b serves to define the edge of the second well. Therefore, the edge of the second well 68 is per- fectly aligned with the edge of the first well 65 without depending on perfect alignment of photoresist 67b. Thus, problems with prior art alignment of adjacent wells are overcome and yet the process remains simple and inexpensive. in this embodiment, the second well is doped for forming a high voltage device. A high voltage region need not be formed when the lightly-doped substrate itself has the desired characteristics to serve as the high voltage region. However, if it is desired to adjust the dopant 1 type or the dopant concentration in the high voltage 2 region, exposed high voltage region 68 may be implanted 3 using a selected impurity type as shown in Fig. 8e. For 4 example, for a P-type high voltage region, a final dopant c 14 14 3 D concentration of approximately 1x10 to 4x10 atoms/cm 6 is used. 7 As shown in Figure 8f, after implantation, as with the P well dopants, high voltage region dopants are slightly diffused and oxide 69 grown on the exposed area. The same conditions described above for growing oxide on the P well will result in fast growth of oxide on the exposed high voltage region and much slower thickening of the existing oxide above the P well. This is because oxide growth is highly nonlinear, depending on the proximity of silicon atoms and oxygen atoms to each other. As shown in Figure 8g, oxide and nitride are then removed from the area adjacent to high voltage well 68 where N well 71 is to be formed. An N-type dopant such as phosphorus is then used to provide a low energy implant at dosage of approximately 5 x 10 ions/cm at an energy level of approximately 25 KeV. The dopants in well regions 65, 68 and 71 are now diffused to their desired junction, depth of approximately 3 to 6 microns, for example by heat¬ ing the wafer in a dry oxygen atmostphere at approximately 1150°C for approximately 8 to 12 hours, thus forming oxide 72 to a thickness of approximately 1000A. Alternatively, if desired, portions of oxide 61 and nitride 62 need not be removed from the area adjacent to high voltage well 68 where N well 71 is to be formed. In this event, an N type dopant such as phosphorous is used to provide an implant through oxide 61 and nitride 62 covering to be formed N well 71. At this time, thick oxide layers 66 and 69 serve as a mask. After implantation, the device is heated in order to diffuse the dopants to form N well 71 as shown in Figure 8h. Since nitride layer 62 remains, thick oxide layer 72 shown in Figure 8h is not formed above N well region 71. Using appropriate and well known techniques, nitride layer 62 and oxide layers 61, 69 and 66 are then removed, and further processing as described below provides the structure shown in Figure 9. Note that three types of wells have thus been formed using only two photoresist masks 63 and 67a,b, and that it was not necessary to align the edge of one photoresist mask with the edge of a previous mask. Thus, a simpler manufacturing process with automatic self-alignment has been achieved. Optionally, oxide 72 may be grown to diffuse well 71 to the depth of wells 68 and 65. Oxide layers 66, 69 and 72 are then removed, leaving a tri-well substrate for device formation having good planarity and sharply defined well regions. Fig. 8h shows the semiconductor structure after oxidation, leaving N well 71, high voltage region 68 and P well 65 formed in the substrate. The dotted line around the high voltage region 68 in Fig. 8h indicates that this region may be the substrate itself if no high voltage region implant is employed. Oxide layers 66, 69 and 72 are then removed using, for example, buffered HF, and devices are formed in well regions 65, 68 and 71 in a well-known manner. An alternative embodiment shown in Figure 8j provides a structure having two implanted and diffused wells 65, 68, and which uses substrate 60 as the high voltage region without requiring an implant in the high voltage region. In this alternative embodiment, after forming oxide layer 66 as shown in Figure 8d, and applying photoresist 67a, 67b, as shown in Figure 8e, implantation is then performed through oxide/nitride layers 61 and 62 to form implanted well region 68 as shown in Figure 8i. Well 68 is automati- cally selfaligned with well 65. Subsequent heating to a temperature of approximately 1,150°C for approximately 8 to 12 hours diffuses implanted well 68. The layers of nitride 62, thick oxide 66 and thin oxide 61 are then removed to produce the substrate of Figure 8j having three regions for forming active devices: implanted well 65, implanted well 68, and substrate region 60 which is appro- 3 priate for high voltage devices. 4 As will also be appreciated by those who are skilled 5 in the art in light of the teachings of this invention, it 6 is also possible to implant well region 68 by first removing 7 nitride layer 62. In this event, during the diffusion of 8 implanted dopants in well region 68, an additional thick 9 oxide layer is formed over N well 68. This thick oxide is 0 then simultaneously removed with the removal of thick 1 oxide layer 66. 2 3 Device Formed Using This Invention 4 Regardless of which embodiment is used, oxides formed 5 over well regions and the substrate itself are removed, 6 as is any remaining nitride. A new base oxide layer (200 O O 7 to 500A thick) and a layer of nitride (1500A) is formed δ thereon. An active area mask, which defines the active 9 regions, is used followed by field implantation and the n0 formation of field oxide (typically 10,000A ° thick), as 1 is known in the art. The initial base oxide/nitride layer 2 is removed, and a gate dielectric is formed. 3 Figs. 9-11 show formation of a portion of a typical 4 circuit using the tri-well substrate just described after 5 formation by any of the method embodiments which have been 6 described in detail. Thick oxide 101 is formed at the 7 boundaries between one well and the next to prevent forma- 8 tion of parasitic current paths between one active device 9 and the next. A thinner portion of oxide 102 for insula- tion purpose is formed over the centers of each well 1 region. 2 A polycrystalline silicon layer is then deposited as 3 described earlier and gates 121, 122 and 123 for active devices in N well 71, high voltage region 68, and P well 65 and doped polycrystalline silicon interconnects (not 6 shown) are then formed. 7 8 Source and drain regions 145 (shown in Fig. 10) are formed in N well 71 by forming a P type source/drain mask 130 (shown in Fig. 9) of photoresist which exposes the regions where P type boron ions are to be implanted to form source/drain regions. The boron implant is performed using a dosage of 3x10 ions/cm at an energy level of approximately 50 KeV. If the high voltage region 68 is also N-type, boron mask 130 also exposes the high voltage region. similarly, N+ source and drain regions are formed in P well 65 by forming an N+ source/drain mask of photo- resist (not shown) which exposes the regions where N+ type ions are to be implanted. The N+ implant can be performed using a dosage of approximately 5x10 phosphorous ions/cm at an energy level of approximately 75 KeV. If the high voltage region 68 is also P type, the N+ source/drain implant for the high voltage region 68 is accomplished at the same time that the N+ source/drain regions are formed in P well 65. After the source and drain implants, the wafer is subjected to an 0 2 ambient at approximately 900°C to 2 1000°C to achieve appropriate junction depth of approxi- 3 mately 0.3 microns. During this process approximately 4 500A of oxide is grown on the source/drain regions. The 5 resulting semiconductor structure shown in Fig. 9, has P+ 6 well source and drain regions 145, N+ p well source and 7 drain regions 146 and source and drain regions 147 of a δ selected conductivity type in high voltage region 68. 9 Standard processing techniques are employed to com- 0 plete the formation of active devices on regions 65, 68, 1 and 71 to produce a device such as shown in Fig. 10, with 2 first metal contact layer AL-1, second metal layer AL-2, 3 first PVX layer PVX-1 and second PVX layer PVX-2. 4 The above embodiments are intended to be exemplary 5 and not limiting, and in view of the above disclosure, 6 many substitutions and modifications will be obvious to 7 one of average skill in the art without departing from the 8 spirit and scope of the invention. As but one example, as will be readily recognized by one of ordinary skill in the art in light of the teachings of this invention, the well regions can be formed first, and the field implants formed thereafter. As another example, it would of course be possible to form more than three regions, providing, for one example, two high voltage regions of opposite conduc- tivity type. As yet another example, the second well can be formed not adjacent to the first well, photoresist serving to mark both boundaries of the second well. After forming of thick oxide on this second well, thick oxide over the first and second wells then defines both boundaries of a third well.

Claims: CLAIMS We Claim: 1. A semiconductor structure comprising: a substrate of a first conductivity type; a first well, formed within said substrate, of said first conductivity type having greater conductivity than said substrate; a second well, formed within said substrate, of a second conductivity type opposite said first conductivity type having greater conductivity than said substrate; and a third region in said substrate of either said first conductivity type or said second conductivity type having a conductivity of the same order of magnitude as said substrate for the formation of devices having high junction breakdown voltages, and in which the edges of said first, second, and third wells are automatically self-aligned. 2. Structure in Claim 1 wherein said third region is of said first conductivity type. 3. Structure in Claim 1 wherein said third region is of said second conductivity type. 4. Structure in Claim 1 wherein said third region is a portion of said substrate. 5. Structure in Claim 1 wherein the resistivity of said substrate is in the range of approximately 30 to 100 ohm-cm. 6. Structure in Claim 1 further comprising a first transistor having a gate, and having a source and a drain formed in said first well; a second transistor having a gate, and having a source and a drain formed in said second well; and 1 a third transistor having a gate, and having a source and a drain formed in said third region. 3 4 7. Structure in Claim 1 wherein said substrate is c 1 4 14 -> silicon and contains approximately 1 x 10 to 2.5 x 10 atoms/cm of P type dopants, said first well contains a ' concentration of approxi.mately 8 x 1014 to 3 x 1016 8 atoms/cm of P type dopants, said second well contains a α y concentration of approximately 8 x 1014 to 3 x 1016 atoms/cm 0 of N type dopants and said third region contains approximate 1 x 1014 to 4 x 1014 atoms/cm3 of P type dopants. 2 3 8. Structure in Claim 7 wherein said high junction 4 breakdown voltages are greater than approximately 20 5 volts. 6 7 9. A method of forming wells in a semiconductor substrate comprising: 9 depositing a thin layer of oxide on said substrate, depositing a layer of silicon nitride on said thin 1 layer of oxide, 2 initiating a process to be repeated at least two 3 times of: 4 applying a layer of photoresist, removing portions of said photoresist, thereby expos- i g portions of said silicon nitride, removing exposed portions of said silicon nitride and thin oxide, thus creating exposed portions of said semiconduc tor substrate, implanting dopants of a selected conductivity type to a selected concentration into said exposed portions of said semiconductor substrate, thereby forming a well of said selected conductivity type having a breakdown voltage determined by said selected concentration, oxidizing said exposed portions of semiconductor substrate thus creating protective thick oxide over said exposed portions and diffusing said dopants into said semiconductor substrate, and after sufficient repetition of said process, when • 9^ the desired number of regions have been formed, removing said protective thick oxide. 4 ς " -* 10. A method for forming wells in a semiconductor 6 substrate as in Claim 9, where said process to be repeated at least two times is repeated three times. 8 9 11. A method for forming wells in a semiconductor 0 substrate as in Claim 9, wherein said first conductivity 1 type is N and said second conductivity type is P. 2 3 12. A method for forming wells in a semiconductor substrate as in Claim 9 wherein said first conductivity 5 type is P and said second conductivity type is N. 6 7 13. A method for forming wells in a semiconductor 8 substrate as in Claim 11 wherein said dopants of said 9 first conductivity type are phosphorous and said dopants 0 of said second conductivity type are boron. 1 2 14. A method for forming wells in a semiconductor, 3 substrate as in Claim 12 wherein said dopants of said 4 first conductivity type are boron and said dopants of said 5 second conductivity type are phosphorous. 6 7 15. A method for forming wells in a semiconductor 8 substrate as in Claim 9 where in subsequent repetitions of 9 said process, said step of removing portions of said 0 photoresist may also expose portions of said protective 1 thick oxide, thus providing automatic alignment of adjacent 2 wells. 3 4 16. A method of forming wells in a semiconductor 5 substrate comprising: depositing a thin layer of oxide on said substrate 7 8 depositing a layer of silicon nitride on said 9 thin layer of oxide, initiating a process to be repeated at least one time of: applying a layer of photoresist, c removing portions of said photoresist, 7 thereby exposing porti.ons of sai.d si.li.con ni.tri.de, δ removing exposed portions of said silicon nitride and thin oxide, thus creating exposed 10 portions of said semiconductor substrate, 1 ■U 1- L i.mplanting dopants of a selected conducti.vi.ty 1^9 type to a selected concentrati.on i.nto sai.d ■ j , XJ exposed portions of said semiconductor substrate, 14 thereby forming a well of said selected conductiv- 1 ity type having a breakdown voltage determined 1 by said selected concentration, 17 oxidizing said exposed portions of semicon- 1 8 ductor substrate, thus creating protective thick 19 oxide over said exposed portions and diffusing 20 said dopants into said semiconductor substrate, 21 and after sufficient repetition of said 22 process, when one well region remains to be 23 formed, 24 applying a layer of photoresist, 25 removing portions of said photoresist, 26 thereby creating exposed portions of said silicon 7 nitride, 2δ implanting through said exposed portions of 29 silicon nitride and said thin layer of oxide 30 dopants of a selected conductivity type to a 31 selected concentration into said semiconductor 2 substrate, thereby forming a well of said selected 3 conductivity type having a breakdown voltage 4 determined by said selected concentration, diffusing said dopants of a selected conduc- ° tivity type into said semiconductor substrate, 7 8 1 rem-oving said layer of si.licon ni.tri.de and ^ 9 said thin and thick layers of oxide. 3 4 17. A method for forming wells in a semiconductor substrate as in claim 16, where said process to be repeated ° at least one time is repeated one time. 7 18. A method for forming wells in a semiconductor substrate as in claim 16, where said process to be repeated at least one time is repeated two times. 1 2 19. A method for forming wells in a semiconductor 3 substrate as " in claim 16, where said first conductivity 4 type is N and said second conductivity type is P. 5 ° 20. A methof for forming wells in a semiconductor 7 substrate as in claim 16, wherein said first conductivity 8 type is P and second conductivity type is N. 9 0 21. A method for forming wells in a semiconductor 1 substrate as in claim 19, wherein said dopants of said 2 first conductivity type are phosphorous and said dopants 3 of said second conductivity type are boron. 4 5 22. A method for forming wells in a semiconductor 6 substrate as in claim 20, wherein said dopants of said . 7 first conductivity type are boron and said dopants of said 8 second conductivity type are phosphorous. 9 0 23. A method for forming wells in a semiconductor 1 substrate as in claim 16, where said steps of removing 2 portions of said photoresist thereby exposing portions of 3 said silicon nitride may also expose portions of said 4 protective thick oxide, thus providing automatic alignment 5 of adjacent wells. 6 7 8

Inventors: BATRA TARSAIM LAL, JOY RICHARD C, BATRA, TARSAIM, LAL, JOY, RICHARD, C.
Applicants: AMERICAN MICRO SYST, AMERICAN MICROSYSTEMS, INC.
Application year: 1985
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L29