PARALLEL SYNCHRONOUS OPERATION

Abstract: For achieving parallel synchronous operation between two microprocessors (1, 2) there is arranged a switch (4) controlled by a logical circuit (3), which senses the clock outputs of the microprocessors. If there is deviation from synchronism, the logical circuit (3) sends a signal to the switch (4), which then breaks off the incoming clock signal to the clock input of one microprocessor (2) such that parallel synchronism is stepwise achieved.

Description: PARALLEL SYNCHRONOUS OPERATION TECHNICAL HELD The invention relates to apparatus for providing parallel synchronous operation of at least two micro-processors, in a computer system. BACKGROUND ART Modern computers and computer systems often include micro-processors, with which sub-functions are performed. To obtain great reliability in their perfor- mance it is desirable simultaneously to perform the subfunctions in two microprocessors working in parallel. They must operate synchronous to enable comparison of their results. Their clock frequency is controlled by the computer system clock, which has its frequency divided in the clock counters of the microprocessors. There is often a fixed division by a factor of four. If further division is required this is suitably performed with the aid of a JK-flipflop connected to the respective clock input. A problem in synchronizing two or more microprocessors is that their internal functions are inaccessible from outside. It is therefore not possible to achieve parallel synchronism with the aid of a resetting pulse. DISCLOSURE OF INVENTION The present invention relates to apparatus, with the aid of which two or more mircroprocessors are brought into parallel synchronous operation. The invention is characterized in the accompanying claims. BRIEF DESCRIPTION OF DRAWINGS The invention in accordance with the claims is described hereinafter with the aid of the accompanying drawings, where Figure 1 illustrates one embodiment of the invention and Figure 2 another embodiment. Figure 3 is a time chart for the signals with respect to synchronization. BEST MODE FOR CARRYING OUT THE INVENTION Figure 1 is a logic diagram where the apparatus comprises a negative exclusive OR circuit 3 and an AND circuit 4 connected to two clock counters 1,2, each associated with a microprocessor 6,7. The computer system clock Cl is connected to the input of the clock counter 1. The output of the circuit 4 is connected to the input of the other clock counter 2, one input of the circuit 4 being connected to the system clock Cl. The frequency of this clock is divided by a factor of four in the clock counters 1,2. The outputs of the latter are each connected to an input of the circuit 3, the output of which is connected to the other input of the circuit 4. The output of the circuit 3 will be zero for a signal difference at the outputs of the clock counters 1,2. The system clock signal is then prevented by the circuit 4 from reaching the clock counter 2. If there is no difference in the signals on the outputs of the clock counters, the output of the circuit 3 is ONE, and the circuit 4 allows the system clock signals to reach the clock counter 2. From this it follows that for asynchronism between the clock counters, the counter 2 will be periodcally stopped until parallel synchronism occurs (described in detail in connection with Figure 3). Figure 2 illustrates another embodiment. An arithmetic circuit 5 comprising a JK-flipflop to each microprocessor is connected between the system clock and the microprocessors. The arithmetic circuit divides the system clock frequency by a factor of two, resulting in that the total division of the frequency will be by a factor of eight. The JK inputs to the flipflop having its output connected to the clock input of the other microprocessor 2 are commonly connected to the output of the logical circuit 3. The AND function of the circuit 4 in Figure 1 is thus replaced. The time chart in Figure 3 illustrates the phasing-in to parallel synchronism between the mircoprocessors, in the case where the frequency of the signal clock Cl is divided by a factor of eight, according to Figure 2. In the chart, A, , B, and C-. depict the frequecy division sequence in the microprocessor 1, while A« B« and C„ depict the frequency division sequence in the microprocessor 2. One of the two most unfavourable cases possible is illustrated in the diagram. For describing the phasing-in a positive period is denoted by a logical ONE and a negative by a logical ZERO. A shifts when Cl goes from O to 1, B shifts when A goes from 1 to O, and C shifts when B goes from 1 to O. The Cl pulses to A 2 are stopped at difference between C, and m. According to the chart, this occurs for the first time when C, goes from O to 1 after the Cl period 3. A 2 is in the state 1 until the Cl period when C, has gone from 1 to 0, i.e. after the period 8. Then A„ gets the Cl pulse and goes from 1 to 0. At the same time B« goes from 1 to 0 and C 2 from 0 to 1. Then there is once again a difference between C, and C 2 , thus A 2 being blocked again for the Cl pulses. This difference prevails until C-, once again goes from 0 to 1, which takes place after the period 11. There is subsequent equality between A, and A 2 , B-. and B 2 , C, and C 2 , i.e. a state of parallel synchronism. Independent what division factor is used for the Cl frequency the phasing-in always takes place at the latest within 1,5 times the cycle time of the clock counters. Figure 3 also explains the phasing-in of the apparatus according to Figure 1, with the difference that the division uses a factor of 4, and thus only the frequency division sequences A and B exist.

Claims: CLAIMS 1. Apparatus for providing parallel synchronous operation of a first and a second microprocessor (1,2) in a computer system, where the clock frequency of the microprocessors is obtained by internal division of a system clock frequen¬ cy, characterized in that the apparatus includes a switch (4) for breaking and making the system clock signal path to the clock input of the second microprocessor (2), and a logical circuit (3) for controlling the switch (4), the two inputs of the circuit (3) being connected to the clock outputs of the microprocessors (1,2) such that for signal difference between their inputs the logical circuit causes the switch (4) to break the system clock signal path, while for signal equality on the clock outputs it causes the switch to make said path, a stepwise phasing-in to parallel synchronism thus being attained. 2. Apparatus as claimed in claim 1, characterized in that the logical circuit (3) comprises a negative exclusive OR circuit and in that the switch (4) comprises an AND circuit. 3. Apparatus as claimed in claim 1, characterized in that the switch (4) is included in a dividing arithmetic circuit (5), comprising a first and a second JK- flipflop connected between the system clock and the clock input of a micropro¬ cessor assigned to each flipflop, the second JK flipflop having its output connected to the second microprocessor (2) and its J and K inputs connected to the output of the logical circuit (3), this JK flipflop performing the function of the switch (4).

Inventors: SUNDELL GOESTA INGVAR, SUNDELL, GOESTA, INGVAR
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON
Application year: 1985
Main classification: G06F1
IPC codes: G06F1, G06F11, G06F15