SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Abstract: A semiconductor device such as a MOS transistor includes floating and control gates (43, 44). Between the gates is provided a composite insulating layer (25a) includ­ ing a silicon nitride layer (39). The end portions of the composite insulating layer extend in the channel-length direction of the MOS transistor beyond the end portions of at least one of the floating and control gates.

Description: This invention relates to a semiconductor device comprising source and drain regions between which a channel region is formed, a gate insulating layer provided on said channel region, a floating gate provided on said gate insulating layer, a composite insulating layer provided on said floating gate and including a plurality of insulating layers which are disposed on one another and different from one another in their properties, said insulating layers having the same width in the length direction of said channel region, and a control gate provided on said composite insulating layer, the width of said floating gate in the length direction of said channel region being substantially equal to that of said control gate. The invention also relates to a method of manufacturing the device. A semiconductor device having a floating gate and control gate, for example, a MOS transistor can externally detect the level of a threshold voltage and thus be used as a memory element of a memory device. The structure of a conventional MOS transistor with the above-mentioned double gates will be explained below with reference to Figs. 1A and 1B. Fig. 1A is a cross sectional view as taken along a channel-length direction of a prior art semiconductor device and Fig. 1B is a cross sectional view as taken along a channel-width direction of Fig. 1A. In the arrangement shown in Figs. 1A and 1B, n-type source and drain regions 12 and 13 are formed in the surface portions of a p-type semiconductor substrate 11, and a channel region 14 is formed between the source region and the drain region. An insulating layer (a gate insulating layer) is formed on the channel region 14. A floating gate 16 of polysilicon is formed on the insulating layer 15. Then, an insulating layer 17 is formed on the floating gate 16 and a control gate 18 is formed on the insulating layer 17. A silicon dioxide (Si0₂) layer 19 covers the whole surface of the above-mentioned MOS transistor. As shown in Fig. 1B, the MOS transistor area is isolated by a field insulating layer 20 from the other MOS transistor area. In the above-mentioned MOS transistor the floating gate 16 is "electrically floated". A strong electric field is induced through the utilization of a coupling capacity present between the control gate 18 and the floating gate 16. As a result, a Fowler Noldheim type tunnel current flows through the layer 17 and charges are selectively injected into the floating gate 16, whereby data can be written into the MOS transistor. Upon applying a voltage between the source and the drain a channel current flows, producing hot electrons in the neighborhood of the drain 13. The hot electrons are injected into the floating gate 16, causing a rise in the threshold voltage of the MOS transistor whereby it is possible to write data in the MOS transistor, i.e., to permit a programming. Since the charges injected into the floating gate 16 continue to be held in the floating gate 16 unless a reprogramming is performed, the data once programmed is nonvolatilely held in the MOS transistor. The above-mentioned MOS transistor formed in a memory device is referred to, as required, as a memory cell. In the memory device a situation must be avoided that charges are injected into a cell with respect to which a read/write operation is carried out or that the charges so injected flow out. As understood from the above, there is a risk that, with such a cell in that state, erroneous data will be read out of the memory device. For an enhanced integration density and microminiaturization of the memory device, insulating layers are made thinner and thinner and the temperature in the manufacturing process is made lower and lower. Therefore, there is a tendency that erroneous charges are injected or discharged more often in the memory cell. The floating gate 16 is usually formed of polysilicon and isolated from the control gate 18 by a silicon dioxide (SiO₂) layer 17 which is thermally formed on the surface of the floating gate 16. Due to the adoption of a lower oxidation temperature and formation of thinner and thinner SiO₂ layers, an uneven surface is formed for the SiO₂ layer, causing charges to be liable to concentrate locally and thus a leakage current to be liable to be produced across the gates 16 and 18. An MOS transistor of this type is disclosed in JP-A-58-87877. The floating gate is separated from the control gate by a single layer of silicon nitride which covers the top and the side walls of the floating gate. The control gate is smaller than the floating gate. In order to eliminate the above-mentioned drawbacks, the inventor has developed memory cells as shown in Figs. 2A and 2B. The memory cell was disclosed in "1984 Symposium on VLSI Technology Digest of Technical Papers", September 10-12, 1984, San Diego, IEEE New York 1984, p. 40 to 42, entitled "Poly-Oxide/Nitride/Oxide Structures for Highly Reliable EPROM Cells". This outline will be explained below with reference to Figs. 2A (a cross sectional view as taken along a channel-length direction of a prior art semiconductor device) and 2B (a cross sectional view as taken in a channel-width direction of Fig. 2A). A composite insulating layer 24 is formed, as shown in Figs. 2A and 2B, between a floating gate 16 and a control gate 18. The composite insulating layer 24 includes SiO₂ layer 21 formed by the thermal oxidation of the floating gate 16 of polysilicon, a silicon nitride layer 22 formed on the layer 21 and an SiO₂ layer 23 formed by the thermal oxidation of the surface of the layer 22. It has been found that this memory cell can reduce such leakage current to a greater extent than that in the memory cell of Figs. 1A and 1B. However, it has been observed that, if the temperature of the manufacturing process is further reduced in the arrangement shown in Figs. 2A and 2B, a larger leakage current is produced at an X point in Fig. 2A. Here, the X point shows the end-portions of the composite layer 24 in the channel-length direction and the Y point shows the end portions of the composite layer 24 in the channel-width direction. The enhanced integration density and the larger size of the silicon wafer are essential requirements under which it is possible to implement an inexpensive integrated circuit of an enhanced function. In order to satisfy these essential requirements it is unavoidable to adopt a low-temperature manufacturing process in which case the above-mentioned leakage current should be made as low as possible. JP-A-56-26472 discloses a semiconductor memory having a double insulating layer between a control gate and a floating gate. However, one sub-layer extends only beyond the control gate, and the two gates are of differing lengths. JP-A-56 134 775 discloses a semiconductor memory element having an Mo floating gate and a control gate of identical lengths, the gates being separated by an MoO film formed by thermal oxidation of said floating gate and a layer of silicon nitride extending beyond the gates. An object of this invention is to provide a semiconductor device which can sufficiently suppress a leakage current as produced across a floating gate and a control gate. Another object of this invention is to provide a method for manufacturing a semiconductor device, which can sufficiently suppress a leakage current as produced across a floating gate and a control gate. According to one aspect of the invention, the semiconductor device initially defined is characterized in that the end portions of said composite insulating layer extend in the length direction of said channel region beyond the end portions of said floating and control gates. According to a further aspect of the invention, there is provided a method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, comprising the steps of: selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO₂ (silicon dioxide) layer covering said active region; forming a first polysilicon layer covering said first SiO₂ layer and said field insulating layer; patterning said first polysilicon layer so as to have a width appropriate for forming said floating gate, said width being measured in the channel-width direction; forming a multilayered insulating layer on said first polysilicon layer from which said composite insulating layer is formed; forming a second polysilicon layer on said multilayered insulating layer; forming a resist pattern on said second polysilicon layer said resist pattern having a length corresponding to the intended length of said composite insulating layer as measured in the channel length direction; using said resist pattern as a mask, and effecting etching of said second polysilicon layer said composite insulating layer and said first polysilicon layer so as to have an equal length; and doping an impurity of second conductivity type into said first and second regions for forming said source and drain regions , characterised by: shortening the lengths of said first polysilicon layer and of said second polysilicon layer after the etching step so as to form said control and floating gates. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1A is a cross sectional view in the channel-length direction of a prior art semiconductor device; Fig. 1B is a cross sectional view in the channel-width direction corresponding to Fig. 1A; Fig. 2A is a cross sectional view in the channel-length direction of another prior art semiconductor device; Fig. 2B is a cross sectional view in the channel-width direction corresponding to Fig 2A; Figs. 3A to 3E are cross sectional views, respectively, in the channel-width direction of a semiconductor device according to one embodiment of this invention, for explaining the manufacturing steps; Figs. 4A to 4E are cross sectional views, respectively, in the channel-length direction corresponding to Figs. 3A to 3E; Figs. 5A to 5C are cross sectional views in the channel-width direction, respectively, of a semi-conductor device according to another embodiment of this invention, for explaining the manufacturing steps; and Fig. 6 is a cross sectional view in the channel-length direction of still another embodiment of this invention. The steps of manufacturing the embodiment of this invention will be explained below with reference to Figs. 3A to 3E and 4A to 4E. The semiconductor device according to the embodiment of this invention is constructed of a memory cell, a plurality of such memory cells constituting an EPROM (erasable programmable read only memory). Figs. 3A to 3E correspond to Figs. 4A to 4E, respectively. In these Figures a p-type silicon semiconductor substrate 31 has a (100) crystalline surface and a resistivity of 20Ω.cm. A thermal oxidation SiO₂ (silicon dioxide) layer 32 is formed on the semiconductor substrate 31 and then a silicon nitride layer 33 is formed on the SiO₂ layer 32 by LPCVD (low pressure chemical vapor deposition) method. The silicon nitride layer 33 and the SiO₂ layer 32 are patterned by photolithgraphy to remain on an active region which includes source, drain and channel formation regions. An impurity for channel stop, such as boron, is ion implanted in the region excluding the active region by an ordinary MOS transistor manufacturing method. Then, a field SiO₂ layer 34 of about 1 µm in thickness is formed by a selective oxidation (see Figs. 3A, 4A). After the silicon nitride layer 33 and thermal oxidation SiO₂ layer 32 have been removed, an SiO₂ layer 35 of about 20nm (200 Å) in thickness is grown, as shown in Figs. 3B and 4B, on that surface of a semiconductor substrate 31 as defined within an active region. Then, boron is ion implanted, as an impurity, in the active region at 70 KeV with a concentration of 3 × 10¹² cm⁻² to permit the control of the threshold voltage on a MOS transistor (or cell). A first polysilicon layer 36 of about 400nm (4,000 Å) in thickness is deposited by the LPCVD (low pressure chemical vapor deposition) method on the surface of the resultant structure including the SiO₂ layer 35 and field SiO₂ layer 34. Then, phosphorus is doped at a density of 3 × 10²⁰ cm⁻³ into the polysilicon layer 36. It is preferable that as the doping method the ordinary phosphorus diffusion using POCℓ₃ gas be carried out for about 20 minutes at 950°C. However, it may be possible to implant phosphorus ions. Isolated polysilicon layers are formed by patterning the first polysilicon layer 36. That is, in order to separate the floating gates in the adjacent cells from each other at last, the first polysilicon layer 36 is subjected to a patterning step by photolithography to leave those portions of the first polysilicon layer 36 as indicated in Fig. 3B. The first polysilicon layer 36 as shown in Fig. 3B corresponds in width to the floating gate as viewed in the channel-width direction (see Figs. 3B and 4B). Then, a second SiO₂ layer 38 of about 30nm (300 Å) in thickness is formed on the polysilicon layer 36, as shown in Figs. 3C and 4C. A silicon nitride layer 39 of about 15nm (150 Å) in thickness is formed on the second SiO₂ layer by the LPCVD method and a third SiO₂ layer 40 of about 6nm (60 Å) in thickness is formed on the silicon nitride layer 39. The third SiO₂ layer 40 can be formed either by the CVD method or by oxidizing the silicon nitride layer 39 at 950°C. These layers 38, 39 and 40 constitute a multilayered insulating layer 25 and a composite insulating layer 25a as explained later with reference to Fig. 4D is formed from the multilayered insulating layer 25. A second polysilicon layer 41 is formed on the third SiO₂ layer 40 and phosphorus is doped as an impurity into the second polysilicon layer 41 at a density of 5 × 10²⁰ cm⁻³. A resist pattern 42 is formed on the second polysilicon layer 41. It is to be noted that the length of the resist pattern 42 (the length of the pattern 42 in the channel-length direction shown in Figs. 4C and 4D) corresponds to the length of the composite insulating layer 25a in Fig. 4D (the length of the layer 25a in the channel-length direction) (see Figs. 3C and 4C). Then, as shown in Figs. 3D and 4D an anisotropic etching step such as RIE (Reactive Ion Etching) is performed with the resist pattern 42 as a mask, followed by an isotropic etching step. First, the anisotropic etching of the second polysilicon layer 41 is selectively carried out. At this time a gas containing CCℓ₄ can be used as an etchant gas. With the resist pattern 42 as a mask the layers 40, 39 and 38 are sequentially etched in a selective fashion, using a CF4 gas as a chief etchant. Then, with the resist pattern as a mask, the first polysilicon layer 36 is etched selectively, using a gas containing CCℓ4 as an etchant. As a result, the first polysilicon layer 36 is such that only its portion as indicated in Fig. 4D is left as a floating gate 43. Similarly, the second polysilicon layer 41 is such that only its portion as indicated in Fig. 4D is left as a control gate 44. In this Figure, it is to be noted that the lengths of the floating gate 43 and control gate 44 as viewed in the channel-length direction are indicated by a dotted line In the above-mentioned isotropic etching step, with the resist pattern 42 as a mask, the ends of the floating gate 43 and control gate 44 in the channel-length direction are etched in a gas containing (CF₄ + O₂) gas as a main etchant to permit these ends to be recessed to an extent of about 50nm (500 Å) as shown in Fig. 4D. Stated in more detail, in the arrangement shown in Fig. 4D the composite insulating layer 25a is not etched in the isotropic etching step with only the floating and control gates etched. In consequence, as shown in Fig. 4D, the ends of the composite insulating layer 25a as viewed in the channel-length direction provide a projecting structure with respect to the recessed ends of the floating and control gates. Then, the resist pattern 42 is removed and arsenic ions are implanted into the substrate 31 at 40 KeV with a concentration of 2 × 10¹⁵ cm⁻², causing a diffusion to occur to permit n-type source and drain regions to be formed in the substrate. An SiO₂ layer 47 is deposited on the whole surface of the cell in an O₂ atmosphere at 950°C (Figs. 3E and 4E). Then, as in the manufacture of an ordinary MOS transistor an SiO₂ layer of 500nm (5,000 Å) in thickness is formed by the CVD method on the whole surface of the cell as shown in Fig. 4E (not shown), and PSG (Phospho-Silicate Glass) is deposited, with a thickness of 700nm (7,000 Å), on the whole surface of the cell as shown in Fig. 4E, followed by an annealing step for 30 minutes at 950°C. The formation of contact holes and, for example, aluminum interconnections are performed, thereby completing an EPROM. Instead of the above mentioned isotropic etching step, thermal oxidation step for the floating and control gates may be employed. In other words, the floating and control gates 43 and 44 can be shortened in their lengths in the channel-length, direction as shown in Fig. 4D, by being subjected to thermal oxidation. The semiconductor device according to the embodiment of this invention has the following advantages. Since the ends of the silicon nitride layer 39 in the composite insulating layer 25a, as viewed in the channel-length direction, provide the projecting structure in the channel-length direction with respect to the recessed ends of the floating gate 43, a path of leakage current leading from the floating gate 43 to the control gate 44 is longer than the leakage current path shown in Fig. 2A. The silicon nitride layer 39 is relatively high in dielectric constant in comparison with the SiO₂ layer and thus the intensity of the electric field in the silicon nitride layer is relatively small as compared with that in the SiO₂ layer. This means that owing to the presence of the silicon nitride layer the distance between the floating gate 43 and the control gate 44 becomes effectively longer. In the above-mentioned embodiment the suppression of the leakage current at the above-mentioned edge portions X, Y has been explained as being important in connection with Figs. 2A and 2B. In the above-mentioned embodiment, the ends of the silicon nitride layer 39 extends beyond the ends of the floating gate electrode in the channel-length direction, the concentration of the electric field at the above-mentioned ends or edge portions X becomes lower, thus enabling the generation of the leakage current to be suppressed down to a much lower extent. Upon comparison between Figs. 2A and 4E the leakage current can be suppressed due to the presence of the silicon nitride layers 22 (Fig. 2A) and 39 (Fig. 4E), provided that the above-mentioned edge portions are disregarded. In Fig. 2A, however, only the insulating layer 19 exists between the floating gate 16 and the control gate 18 at the edge portion X, failing to enhance an insulating effect between the gates. In consequence, the leakage current of the device as shown in Fig. 2A becomes remarkably greater than the leakage current of the device shown in Fig. 4E. Supposing the total edge lengths of the floating gates to be equal to each other, it has been possible to suppress the leakage current of Fig. 4E down to one tenth to one hundredth that of Fig. 2A. A semiconductor device according to another embodiment of this invention will be explained below with reference to Figs. 5A to 5C. In the embodiment of Figs. 3A to 3E and 4A to 4E the ends of the composite insulating layer 25a in the channel-length direction has been explained as extending beyond the ends of the floating gate 43 and control gate 44 in the channel-length direction. Furthermore, as shown in Fig. 3E, the silicon nitride layer 39 has been explained as being shared between the adjacent cells in the channel-width direction. In the other embodiments of this invention, as shown in Fig. 5C, a silicon nitride layer 39a of one cell is separated from that of another cell, and the ends of the silicon nitride layer 39a in the channel-width direction extend beyond the ends of the first polysilicon layer 36a in the channel-width direction, that is, beyond the ends of a floating gate in the channel-width direction. The method of manufacturing these embodiments will be explained below. The above-mentioned steps as shown in Fig. 3A can be applied to said other embodiments. That is, a thermal oxidation SiO₂ layer 32 is formed on a silicon semiconductor substrate 31 and a silicon nitride layer 33 is deposited by the LPCVD method on the layer 32. Then, an active region is patterned by photolithography. A channel stop impurity, such as boron, is ion implanted into the region other than the active region by using an ordinary MOS transistor fabrication method. Then, a field SiO₂ layer 34 of 1 µm in thickness is formed by the selective oxidation method. After the removal of the above-mentioned silicon nitride layer 33 and SiO₂ layer 32, an SiO₂ layer 35a of about 20nm (200 Å) in thickness is formed on the surface of the substrate 31. In order to control the threshold voltage of the cell, boron is ion implanted into the active region at 70 KeV with a concentration of 3 × 10¹² cm⁻². A first polysilicon layer 36a of about 400nm (4,000 Å) in thickness is formed by the LPCVD method on the whole surface of the resultant structure including the active region and phosphorus is doped in a first polysilicon layer 36a, with a concentration of 3 × 10²⁰ cm⁻³, and a second SiO₂ layer of about 20nm (200 Å) in thickness is formed on the surface of the first polysilicon layer 36a. At this time it is preferable that the oxidation temperature is selected to be below 950°C so as to prevent boron ions previously implanted into the channel region from thermally diffused, to make the impurity concentration at the surface portion of the channel region low, and to make the impurity concentration in an inner portion of the channel region high. The reason is that it is possible to prevent a short channel effect which is otherwise liable to occur when the cell is micro-miniaturized and further more it is possible to elevate the efficiency with which hot electrons are produced in the channel region. Then, a silicon nitride layer 39a of about 15nm (150 Å) in thickness is formed by the CVD method on the second SiO₂ layer 38a, and a third SiO₂ layer 40a of about 6nm (60 Å) in thickness is formed on the surface of the layer 39a. Then, in order to separate the first polysilicon layer 36a from an adjacent cell in the channel-width direction, predetermined portions of a laminated layer 27 including the third SiO₂ layer 40a, silicon nitride layer 39a, second SiO₂ layer 38a and first polysilicon layer 36a are selectively removed. In this case, the removed area includes that portion of the laminated layer 27 which is located on a peripheral circuit formation area, not shown, where cells are not formed. These steps are indicated in a sectional view in Fig. 5A. After the surface of the substrate 31 has been washed and cleaned, an SiO₂ layer (not shown) of about 30nm (300 Å) in thickness is deposited on the peripheral circuit formation area at a temperature of about 900°C. That SiO₂ layer, not shown, formed at this step is used as a gate insulating layer for transistors of which the peripheral circuit is comprised. This SiO₂ layer, not shown, is also formed on the exposed surface of the cell. Since the SiO₂ layer is formed by a low-temperature growth step, a higher growth speed is involved at the exposed surface portions of the first polysilicon layer 36a, i.e., at those surface portions exposed by the separation of the layer 36a. For this reason, an SiO₂ layer 48 of about 80nm (800 Å) in thickness is formed on the end surfaces of the layer 36a in the channel-width direction. When the growth rate of SiO₂ on the polisilicon surface is increased, the ends of the silicon nitride layer 39a overhang beyond the ends of the layer 36a. These steps are indicated in a cross sectional view in Fig. 5B. A second polysilicon layer 41a for a control gate formation is deposited on the entire surface of the resultant structure. Thereafter, a resist pattern 42 is formed on the silicon layer 41a as explained with respect to Fig. 4C. As explained with reference to Fig. 4D, the second polysilicon layer 41a, third SiO₂ layer 40a, silicon nitride layer 39a, second SiO₂ layer 38a and first polysilicon layer 36a are selectively etched by the anisotropic etching method in a sequential fashion. Only the second polysilicon layer 41a and first polysilicon layer 36a are etched by the isotropic etching method by an extent of about 50nm (500 Å). The relation of the composite insulating layer 25a to the floating gate 43 and control gate 44 is as shown in Fig. 4D. Then, the second polysilicon layer at the peripheral circuit formation area is selectively removed by the photolithography and an n-type impurity doping step is performed to form source and drain regions 45 and 46 in the substrate (see Fig. 4E). The following steps have already been explained with reference to Fig. 4E and, thus, further explanation is omitted. In the above-mentioned embodiment, it is possible to prevent the electric field from being concentrated toward the edges of the floating gate (Fig. 4E) both in the channel-length direction and in the channel-width direction, permitting a leakage current to be further suppressed. Since in the above-mentioned embodiment the thickness of the gate insulating layer for transistors in the peripheral circuit formation area and that of the gate insulating layer for cells can be independently set with a greater freedom of design. Furthermore, the adoption of the low-temperature process permits the microminiaturization of cells as well as an improvement in the write-characteristics of cells. This invention is not restricted to the above-mentioned embodiments. For example, the SiO₂ layer formed by the CVD method in which tetraethoxysilane (TEOS) is used for reactant can be used instead of the silicon nitride layer 39 or 39a. Fig. 6 shows a sectional view of such an embodiment as viewed in the channel-length direction. In Fig. 6 the composite insulating layer 25b includes a CVD SiO₂ layer 40b and an SiO₂ layer 38b formed by thermally oxidizing the surface of the floating gate 43 and a CVD SiO₂ layer 40b. The insulating layer 17 in Fig. 1A is the SiO₂ layer thermally grown on the polysilicon layer, resulting in a poor withstand-voltage characteristics. In consequence, the SiO₂ layer 40b is excellent in current-voltage characteristics over the SiO₂ layer 38b and, in addition, the ends of the layer 40b extend beyond the ends of the floating gate 43 in the channel-length direction, offering a greater advantage of suppressing the leakage current. The method for manufacturing a semiconductor device of this embodiment can readily be reduced to practice by modifying the portion or portions of the arrangement of Figs. 3A to 3E and 4A to 4E.

Claims: A semiconductor device comprising source and drain regions (45, 46) between which a channel region is formed, a gate insulating layer (35) provided on said channel region, a floating gate (43) provided on said gate insulating layer, a composite insulating layer (25a, 25b) provided on said floating gate and including a plurality of insulating layers (38,39,40;38b,40b) which are disposed on one another and different from one another in their properties, said insulating layers having the same width in the length direction of said channel region, and a control gate (44) provided on said composite insulating layer, the width of said floating gate (43) in the length direction of said channel region being substantially equal to that of said control gate (44) characterised in that the end portions of said composite insulating layer (25a, 25b) extend in the length direction of said channel region beyond the end portions of said floating and control gates (43, 44). A semiconductor device according to claim 1 characterised in that said composite insulating layer (25a) includes a silicon nitride layer (39). A semiconductor device according to claim 1 characterised in that said composite insulating layer (25b) includes a CVD SiO₂ layer (40b). A semiconductor device according to claim 1 or 2 characterised in that said composite insulating layer (25a) comprises a silicon nitride layer (39) and an SiO₂ layer (40) formed on said silicon nitride layer. A semiconductor device according to any one of claims 1,2 or 4 characterised in that said floating gate (43) is made of a polysilicon layer; and said composite insulating layer (25a) comprises a first SiO₂ layer (38) formed on said floating gate, a silicon nitride layer (39) formed on said first SiO₂ layer, and a second SiO₂ layer (40) formed on said silicon nitride layer. A semiconductor device according to any preceding claim characterised in that the end portions of said composite insulating layer also extend in the channel-width direction of said channel region beyond the end portions of said floating gate (43). A method of manufacturing a semiconductor device having floating and control gates (43, 44) which further includes source and drain regions (45, 46), a channel region, and a composite insulating layer (25a;25b) provided between said floating and control gates, comprising the steps of: selecting first and second regions on a semiconductor substrate (31) of a first conductivity type, said source and drain regions (45, 46) being formed in said first and second regions; forming a field insulating layer (34) surrounding an active region including said first and second regions; forming a first SiO₂ (silicon dioxide) layer (35) covering said active region; forming a first polysilicon layer (36;36a) covering said first SiO₂ layer ( 35) and said field insulating layer (34); patterning said first polysilicon layer so as to have a width appropriate for forming said floating gate (43), said width being measured in the channel-width direction; forming a multilayered insulating layer (25, 27) on said first polysilicon layer from which said composite insulating layer (25a;25b) is formed; forming a second polysilicon layer (41, 41a) on said multilayered insulating layer (25); forming a resist pattern (42) on said second polysilicon layer (41;41a), said resist pattern having a length corresponding to the intended length of said composite insulating layer (25a;25b), as measured in the channel length direction; using said resist pattern (42) as a mask, and effecting etching of said second polysilicon layer (41;41a), said composite insulating layer (25a;25b) and said first polysilicon layer (36;36a) so as to have an equal length; and doping an impurity of second conductivity type into said first and second regions for forming said source and drain regions (45, 46), characterised by: shortening the lengths of said first polysilicon layer (36;36a) and of said second polysilicon layer (41;41a) after the etching step so as to form said control and floating gates (43,44). A method of manufacturing a semiconductor device according to claim 7, characterised in that said multilayered insulating layer (25) comprises a second SiO₂ layer (38) provided on said first polysilicon layer (36), a silicon nitride layer (39) provided on said second SiO₂ layer, and a third SiO₂ layer (40) provided on said silicon nitride layer. A method of manufacturing a semiconductor device according to claim 7 or 8 characterised in that said etching step comprises an anisotropic etching step for sequentially etching, by using said resist pattern (42) as a mask, said second polysilicon layer (41;41a) said multilayered insulating layer (25), and said first polysilicon layer (36;36a). A method of manufacturing a semiconductor device according to any of claims 7 to 9 characterised in that said shortening step comprises an isotropic etching step for further etching, using said resist pattern (42) as a mask, only said second polysilicon layer (41;41a) and said first polysilicon layer (36;36a). A method of manufacturing a semiconductor device according to any of claims 7 to 9 characterised in that said shortening step comprises a thermal oxidation step for shortening said second polysilicon layer (41;41a) and said first polysilicon layer (36;36a) to the desired lengths of said control and floating gates (43;44). A method of manufacturing a semiconductor device according to claim 7 characterised in that said multilayered insulating layer is formed on said first polysilicon layer (36a) before said patterning step of said first polysilicon layer; said multilayered insulating layer includes a second SiO₂ layer (38a) covering said first polysilicon layer (36a), a silicon nitride layer (39a) covering said second SiO₂ layer, and a third SiO₂ layer (40a) covering said silicon nitride layer; said multilayered insulating layer and said first polysilicon layer are patterned so as to have a width slightly larger than the desired width of said floating gate (43), said width being measured in the channel-width direction; and the ends (50) of said patterned silicon nitride layer (39a) are dimensioned to extend in the channel-width direction beyond the ends of said patterned first polysilicon layer by a thermal oxidation treatment for shortening said first polysilicon layer to the desired width of said floating gate.

Inventors: SATO, MASAKI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: H01L29
IPC codes: H01L29, H01L21