LINE DEFLECTION CIRCUIT WITH RASTER DISTORTION CORRECTION

Abstract: A horizontal deflection circuit (20) with raster distortion correction includes a horizontal deflection winding (L H ) coupled to a first retrace capacitor (C₁, C₂, C₃), and an input inductance such as the primary winding (W₁) of a flyback transformer (T₁) coupled to a second retrace capacitor (C RT ). Horizontal switching elements (Q₁, D₁) are operated at a horizontal deflection rate for generating current in the inductance (W₁) and a horizontal scanning current in the deflection winding (L H ). During retrace, the horizontal deflec­ tion winding (L H ) and the first retrace capacitor (C₁, C₂, C₃) form a first resonant circuit (33) and the input inductance (w₁) and the second retrace capacitor (C RT ) form a second resonant circuit 32). One of the switching elements (D₁) decouples the resonant circuits (33, 32) from each other to minimize the interaction therebetween. A source (Q₂) of raster distortion correction current is coupled to the deflec­ tion winding (L H ) to provide the required scanning current modulation.

Description: This invention relates to line (usually horizontal) deflection circuits with raster distortion correction. An east-west pincushion raster distortion corrected horizontal deflection circuit is described in U.S. Patent US-A-4,429,257, by P.E. Haferl, entitled VARIABLE HORIZONTAL DEFLECTION CIRCUIT CAPABLE OF PROVIDING EAST-WEST PINCUSHION CORRECTION. In the disclosed circuitry, the flyback transformer winding and the horizontal deflection winding each form separate retrace resonant circuits isolated from one another. This arrangement avoids undesirable interaction between the retrace-loaded resonant circuit of the flyback transformer and the retrace resonant circuit of the deflection winding. A source of pincushion correction current is coupled to the deflection winding via a choke impedance. In the circuitry disclosed in the Haferl patent, only one of the flyback transformer and deflection retrace resonant circuits is grounded, while the other resonant circuit is left floating above ground during retrace. A retrace pulse voltage is used to provide synchronization information to the horizontal oscillator. If the deflection retrace resonant circuit is grounded, such retrace pulse synchronization information is readily available from the deflection retrace capacitance network. The flyback transformer retrace resonant circuit however, is left floating during retrace, potentially requiring additional circuitry to disconnect the flyback transformer from the B+ voltage supply during retrace. In an alternative arrangement, the flyback transformer retrace resonant circuit is grounded and the deflection retrace resonant circuit is left floating. In such an arrangement, retrace pulse synchronization information is more readily obtainable from a secondary winding of the flyback transformer than from the deflection retrace resonant circuit. However, since the two retrace resonant circuits are decoupled from one another, the synchronization information contained in the flyback transformer retrace pulse voltage may not correspond exactly to the desired synchronization information contained in the deflection retrace pulse voltage. In U.S. Patent Application Serial No. 651,301, filed September 17, 1984, by P.E. Haferl, entitled, EAST-WEST CORRECTION CIRCUIT , both a flyback transformer and a deflection retrace resonant circuit are provided, with the deflection retrace resonant circuit left floating during retrace. Synchronization information for the horizontal oscillator is provided from a secondary winding of the flyback transformer. The flyback transformer input winding and the deflection retrace resonant circuit are coupled together by a relatively small valued retrace capacitor during the retrace interval to enable relatively accurate deflection synchronization information to be obtained from a flyback transformer retrace pulse voltage. The value of this retrace capacitor is chosen so as to minimize transient distortion of the deflection retrace pulse voltage that may be caused by sudden high voltage loading changes. Another Form of deflection circuit, as disclosed in GB-A-2086683, also includes two resonant circuits which are coupled together at all times through a transformer between them. A deflection circuit in accordance with the present invention as set forth in the appended claims also includes two resonant circuits but they are decoupled from each other during retrace, thereby to minimize interaction between them, by the switching means which generate the line deflection current in the deflection winding. Advantageously neither of the two resonant circuits is placed in a floating condition during retrace. In the accompanying drawings: FIGURE 1 illustrates a raster distortion corrected horizontal deflection circuit, embodying the invention; and FIGURE 2 illustrates still another raster distortion corrected horizontal deflection circuit, embodying the invention. In raster distortion corrected horizontal deflection circuit 20 of FIGURE 1, source of B+ supply voltage and energy is coupled between a terminal 21 and a point of reference potential, ground terminal 22. Terminal 21 is coupled to an input inductance, the primary winding W₁ of a flyback transformer T₁. The lower end terminal of primary winding W₁ is coupled to the collector of a horizontal output transistor Q₁ of a horizontal switching means comprising horizontal output transistor Q₁, series connected damper diodes D₂ and D₃, and a disconnect diode D₁. Coupled between the cathode of damper diode D₂ and ground is the series arrangement of an S-shaping capacitor C s , a magnetically biased linearity correction coil 23 and a horizontal deflection winding L H . Also coupled between the cathode of damper diode D₂ and ground is the series connected retrace capacitance network of retrace capacitors C₁, C₂ and C₃. A horizontal oscillator and driver circuit 31 provides horizontal rate switching signals to the base of horizontal output transistor Q₁. Operation of horizontal output transistor Q₁ enables current to flow in a primary winding W₁ and horizontal scanning current i₃ to flow in horizontal deflection winding L H . During the early portion of the horizontal trace interval, damper diodes D₂ and D₃ conduct horizontal scanning current i₃ and conduct current in flyback transformer winding W₁ via diode D₁. During the latter portion of the horizontal trace interval, horizontal output transistor Q₁ conducts current from flyback transformer winding W₁ and horizontal scanning current via diode D₁. When horizontal output transistor Q₁ becomes non-conductive to initiate the horizontal retrace interval, two retrace resonant circuits are formed. A first retrace resonant circuit 33 is formed by horizontal deflection winding L H and retrace capacitance network C₁ - C₃. This retrace resonant circuit generates a retrace pulse voltage across deflection winding L H and a retrace pulse voltage V₁ at the anode of diode D₁, across retrace capacitance network C₁ - C₃. A second retrace resonant circuit 32 is formed by the input inductance of flyback transformer primary winding W₁ and a flyback transformer retrace capacitance C RT coupled between winding W₁ and ground. A retrace pulse voltage V₄ is developed by flyback transformer retrace resonant circuit 32 across retrace capacitance C RT' at the cathode of diode D₁. The amplitude of flyback transformer retrace pulse voltage V₄ is greater than the amplitude of deflection retrace pulse voltage V₁, thereby reverse biasing diode D₁. In this way, diode D₁ serves to disconnect or decouple the two retrace resonant circuits 32 and 33 from each other during the retrace interval so that no current flows from flyback transformer winding W₁ to deflection retrace resonant circuit 33. During the horizontal trace interval, energy from the B+ supply source is stored in the input inductance of flyback transformer primary winding W₁. This energy is transferred to the flyback transformer retrace resonant circuit 32. The energy replenishes losses sustained in driving the retrace driven load circuits coupled to various ones of the secondary windings of the flyback transformer, such as high voltage circuit 30 coupled to high voltage winding W₄. Beam current loading of flyback transformer retrace resonant circuit 32 by high voltage circuit 30 produces a harmonically distorted retrace pulse voltage V₄. Because deflection retrace resonant circuit 33 is decoupled from flyback transformer retrace resonant circuit 32 by means of disconnect diode D₁, variations in beam current loading or other loading of flyback transformer T₁, such as audio loading, produce no significant distortion of the deflection retrace pulse voltage V₁ and the retrace pulse voltage across horizontal deflection winding L H . A raster distortion correction circuit 34 provides a source of correction current i₂ to deflection winding L H via a diode D₆. In addition to providing raster distortion correction such as east-west pincushion correction, current i₂ provides the drive power to replenish horizontal deflection losses. In correction circuit 34, a vertical or field rate parabolic waveform correction signal 27, obtained from the vertical deflection circuit, not illustrated, is coupled to a conventional pulse width modulator east-west control circuit 29. A field rate sawtooth waveform signal 28 provides trapeze distortion correction to control circuit 29. The pulse width modulation is performed on a horizontal rate signal that is synchronized with horizontal deflection by a deflection retrace pulse voltage 26 coupled to the junction of deflection retrace capacitors C₂ and C₃. The pulse width modulated base drive voltage for a driver transistor Q₂, developed by east-west control circuit 29 is illustrated in FIGURE 1 by the voltage waveform V R1 . To obtain the current i₂, energy is stored in the inductance of an east-west pincushion transformer T₂ by the current i₁ flowing in a winding W a of the transformer during conduction of east-west pincushion driver transistor Q₂. The energy or supply voltage source for transformer T₂ is secondary winding W₃ of flyback transformer T₁. During the latter portion of each horizontal trace interval, transistor Q₂ is conductive, producing an upwardly ramping current i₁ in winding W a , as noted from waveforms V₁, i₁, and V R1 illustrated in FIGURE 1. At the beginning of each horizontal retrace interval, transistor Q₂ is made non-conductive by the base drive voltage V R1 . The reverse biasing of diode D₅ is aided by the negative retrace pulse voltage 25 developed at the anode of the diode by flyback transformer winding W₃. With current in winding W a of transformer T₂ abruptly cutoff at the beginning of retrace, the dotted end of winding W b becomes positive and current i₂ is generated in winding W b by means of energy transfer between windings W a and W b , as illustrated in FIGURE 1 by the current i₂ at time t₃. Current i₂ flows into first deflection retrace resonant circuit 33 at the junction of deflection retrace capacitors C₁ and C₂, to replenish deflection losses and to provide the needed east-west pincushion correction modulation of horizontal scanning current i₃. The amplitude of correction current i₂ at the beginning of horizontal retrace varies in an east-west manner to likewise vary the horizontal scanning current i₃ and the deflection retrace pulse voltage V₁. Time t₂ of the waveforms of FIGURE 1 indicates the instant within each horizontal trace interval that transistor Q₂ becomes conductive when the top and bottom raster lines are being scanned, and time t₁ indicates the time when the center raster lines are being scanned. Advancing the position of the entire interval t₁ - t₂ to a point early within the horizontal trace interval, increases the peak value of correction current i₂. The amplitude of scanning current i₃ is thereby increased, resulting in increased raster width. A decrease in scanning current amplitude occurs when the position of the interval t₁ - t₂ is retarded. The greater the amount of energy that is stored in pincushion transformer T₂ during each horizontal trace interval, the higher the resulting amplitudes of correction current i₂, deflection retrace pulse voltage V₅ developed at the junction of retrace capacitors C₁ and C₂, deflection retrace pulse voltage V₁, and scanning current i₃. It should be noted that correction current i₂ does not decrease to zero at time t₄, the end of the horizontal retrace interval. Thus after time t₄ and until driver transistor Q₂ becomes conductive, current i₂ circulates in winding W b via the ground connections provided by conduction of the appropriate one or both of damper diodes D₂ and D₃. Because correction current i₂ does not decrease to zero within the horizontal retrace interval, retrace time modulation of the deflection retrace pulse voltages is avoided. Such modulation could have been produced had diode D₆ become nonconductive during horizontal retrace. During the startup phase of circuit operation, B+ supply rail voltages for such circuits as horizontal oscillator and driver 31 and east-west control circuit 29 may be provided in a conventional manner, not illustrated in FIGURE 1. Upon startup of horizontal oscillator and driver 31, horizontal output transistor Q₁ begins its switching operation to generate flyback transformer retrace pulse voltages in the windings of flyback transformer T₁. Because diode D₁ blocks power transfer to deflection retrace resonant circuit 33 from flyback transformer retrace resonant circuit 32, the switching operation of horizontal output transistor Q₁ cannot, by itself, initiate the development of deflection retrace pulse voltages and horizontal scanning current. Without the generation of deflection retrace pulse voltages, such as voltage 26, typical east-west control circuits that do not incorporate free running oscillators are unable to generate the horizontal rate switching voltage V R1 required for driver transistor Q₂. Absent the switching of driver transistor Q₂, no energy can flow to deflection retrace resonant circuit 33 to initiate the buildup of deflection retrace pulse voltages and horizontal scanning current. A prior art solution in such a situation is to provide a source of startup current from a voltage supply such as a main rectified supply and inject the current into the current path of S-shaping capacitor C S . Such an arrangement is shown in U.S. Patent 4,362,974, by W.F.W. Dietz, entitled, COMMUTATED SWITCHED REGULATOR WITH LINE ISOLATION FOR TRANSISTOR DEFLECTION. In accordance with an inventive feature, horizontal deflection circuit 20 of FIGURE 1 avoids the need for a separate startup supply to transfer energy to deflection retrace resonant circuit 33. Even though flyback transformer T₁ does not transfer power to deflection winding L H during steady-state operation, it does advantageously transfer power during the startup interval. The retrace pulse voltage 24 developed by winding W₂ of flyback transformer T₁ is rectified by a diode D₄ and coupled to the junction of deflection retrace capacitors C₁ and C₂. Winding W₂ provides initial deflection power to generate the deflection retrace pulse voltage 26 for starting up east-west control circuit 29 and for providing initial synchronization information to horizontal oscillator and driver circuit 31. During steady-state operation the deflection retrace pulse voltage V₅ is of a greater amplitude than that of flyback transformer retrace voltage 24, thereby cutting off diode D₄ and disconnecting winding W₂ from deflection retrace resonant circuit 33. Several advantages are provided by the inventive raster distortion corrected horizontal deflection circuit 20 of FIGURE 1. For example, the amplitude of horizontal scanning current i₃ becomes generally independent of B+ voltage variations at terminal 21. The impedance of horizontal deflection winding L H need not be matched to the value of the B+ voltage chosen at terminal 21. Beam current loading of flyback transformer T₁ does not produce scanning current disturbances known as "Mäusezähne",or mouseteeth wiggles that may otherwise be observed when displaying a white crosshatch line pattern. Because the scanning current amplitude is relatively independent of the B+ voltage, a very large range of raster width adjustment is available. Various modifications to the circuit of FIGURE 1 are possible. For example, the junction of diodes D₆ and D₄, instead of being connected to the junction of diodes D₂ and D₃ may be connected to the junction of diodes D₁ and D₂. Capacitor C₂ and diode D₃ may be omitted, with the anode of diode D₂ being grounded and the bottom plate of capacitor C₁ being connected directly to the top plate of capacitor C₃. The junction of diodes D₄ and D₆ would then be connected to the junction of diodes D₁ and D₂. FIGURE 2 illustrates a raster distortion corrected horizontal deflection circuit 120 similar to the circuit of FIGURE 1. Circuit 120 may be advantageously used when the available B+ voltage is lower than the average trace voltage applied to horizontal deflection winding L H and when yoke transformation is not desired. Items in FIGURES 1 and 2 similarly identified function similarly or represent similar quantities. In FIGURE 2, horizontal output transistor Q₁ is directly connected to S-shaping capacitor C₅ and horizontal deflection winding L H . Flyback transformer winding W₁ is coupled to horizontal output transistor Q₁ via disconnect diode D'₁. Diode D'₁ of FIGURE 2 is poled in the sense opposite that of corresponding diode D₁ of FIGURE 1. To enable diode D'₁ to decouple flyback transformer retrace resonant circuit 32 from deflection retrace resonant circuit 33 during retrace, horizontal deflection circuit 120 is designed to produce a deflection retrace pulse voltage V₁ that is greater in amplitude than that of flyback transformer retrace pulse voltage V₄. This produces the required cutoff of diode D'₁ during retrace. With flyback transformer retrace capacitor C RT being connected to the anode of diode D'₁ and damper diodes D₂ and D₃ being connected at the cathode of diode D'₁ ' damper action is no longer available to flyback transformer retrace resonant circuit 32 by diodes D₂ and D₃. A separate damper diode D₇ is coupled across capacitor C RT and provides to the flyback transformer retrace resonant circuit the required damper action at the end of retrace. Diode D₇ thereby further isolates retrace resonant circuits 32 and 33 from one another near the end of their respective retrace intervals. Diode D'₁ of FIGURE 2 conducts lower amplitude flyback transformer current during horizontal trace than does the corresponding diode D₁ of FIGURE 1. Because diode D'₁ is poled to conduct current from flyback transformer winding W₁ to deflection retrace resonant circuit 33, the B+ supply source at terminal 21 provides startup current to charge retrace resonant circuit 33 via the diode during the startup interval. Flyback transformer winding W₂ and diode D₄ of FIGURE 1 therefore need not be used in the circuit of FIGURE 2. In steady-state operation, the startup current path to deflection retrace resonant circuit 33 from the B+ supply source is disabled by the disconnect action impressed on diode D'₁. By providing a horizontal switching arrangement that includes a blocking or disconnect element, such as diode D₁ or D'₁ ' both flyback transformer retrace capacitor C RT and deflection retrace capacitance network C₁-C₃ may be ground connected and their retrace pulse voltages ground referenced. Deflection synchronization retrace pulses that are ground referenced are readily available from the deflection circuitry without requiring the flyback transformer circuitry to AC float above ground during retrace. The resonant frequencies or retrace times of flyback transformer retrace circuit 32 and deflection retrace circuit 33 are selected to maintain separation between the two circuits and to ensure that diode D₁ of FIGURE 1 and diode D'₁ of FIGURE 2 do not conduct during retrace. In FIGURE 1, the retrace frequency of circuit 32 may be selected lower than that of circuit 33, resulting in the retrace time for retrace pulse voltage V₄ being longer than that of retrace pulse voltage V₁. In FIGURE 2, the retrace frequency of circuit 32 may be selected higher than that of circuit 33 resulting in the retrace time for retrace pulse voltage V₄ being shorter than that of retrace pulse voltage V₁. Because the flyback transformer and deflection retrace resonant circuits are isolated from each other by diode D₁ or D'₁, only the flyback transformer retrace resonant circuit provides energy to high voltage load 30. Therefore, the primary inductance of flyback transformer T₁ must be sufficiently low that enough energy is stored in the transformer at the end of trace to obtain a sufficiently low equivalent high voltage source impedance under peak loading conditions. An advantage of having both retrace resonant circuits 32 and 33 ground referenced is that the correction and energy supply current i₂ is injected directly into the deflection retrace circuit 33 and not via the flyback transformer circuit. No harmonics of the flyback transformer current oscillation is developed across winding W b of transformer T₂, thereby enhancing the isolation between the two retrace resonant circuits.

Claims: A line deflection circuit comprising: a source (B+) of direct current supply voltage; a flyback transformer (T₁) including a first winding (W₁) direct current coupled to said source and a second winding (W₄) coupled to a load circuit; a line deflection winding (L H ); a first retrace capacitance (C₁,C₂,C₃) coupled to said line deflection winding (L H ); a second retrace capacitance (C RT ) coupled to said first winding (W₁); switching means (Q₁,D₁) coupled to said line deflection winding (L H ) and to said first winding (W₁) and operable at a line deflection rate for generating a line scanning current in said deflection winding (L H ), and for applying said direct current supply voltage to said first winding (W₁) to store energy therein, operation of said switching means defining line trace and retrace intervals such that during said retrace intervals said line deflection winding (L H ) and said first retrace capacitance (C₁,C₂,C₃) form a first resonant circuit (33), to generate a first pulse voltage (V₅) and said first winding (W₁) and said second retrace capacitance (C RT ) form a second resonant circuit (32) to generate a second pulse voltage (25) that transfers energy stored in said first winding (W₁) to said load circuit, characterized in that said switching means (Q₁, D₁) decouples the two resonant circuits from each other to minimize the interaction therebetween during loading of said load circuit; and that a transformer (T₂) is coupled to said flyback transformer (T₁) and to said deflection winding (L H ) and has said first pulse voltage (V₅) developed at a first winding (dotted terminal of W b ) of said transformer (T₂) and said second pulse voltage (25) developed at a second winding (undotted terminal of W a ) of said transformer (T₂) for generating a current (i₂) to replenish losses sustained by said deflection winding (L H ). A line deflection circuit according to Claim 1 characterized in that both of the two resonant circuits (33,32) are connected to a point of common reference potential so that neither is placed in a floating condition during said retrace intervals. A line deflection circuit according to Claim 2 characterized by means (34) coupled to said transformer (T₂) for modulating said replenish current (i₂) in accordance with a raster distortion correction signal to concurrently modulate said line scanning current. A line deflection circuit according to Claim 1 characterized in that said switching means (Q₁,D₁) includes a line deflection output transistor (Q₁) the coupling of which to said line deflection winding (L H) or first winding (W1) is via a disconnect device (D₁) that decouples the two resonant circuits (33,32) during said retrace intervals. A line deflection circuit according to any of Claims 1 to 4 characterized in that said switching means includes a first damper device (D₂,D₃) coupled to said first retrace capacitance (C₁,C₂,C₃) and a second damper device (D₇) coupled to said second retrace capacitance (C RT ). A line deflection circuit according to any of Claims 1 to 5 characterized in that the amplitude of the first pulse voltage (V₅) is greater than the amplitude of the said second pulse voltage (25). A line deflection circuit according to Claim 2 characterized by a line deflection oscillator (31) coupled to said switching means (Q₁) and having a synchronizing input coupled to said first resonant circuit (33) for synchronizing operation of said switching means (Q₁) in accordance with the pulse voltage developed by said first resonant circuit (33). A line deflection circuit according to Claim 1 characterized in that said transformer (T₂) has a primary winding (W a ) that includes said second terminal (undotted terminal) coupled to said flyback transformer (T₁) and a secondary winding (W b ) that includes said first terminal (dotted terminal), and further including a controllable switch (Q₂) coupled to said primary winding (W a ) and being conductive during said trace intervals for developing said second pulse voltage (25) at said second terminal (undotted terminal of W a ) during said trace intervals, said replenish current flowing in said secondary winding (W b ) during said retrace intervals. A line deflection circuit according to Claim 3 characterized in that said modulating means comprises a switching element (Q₂) responsive to a line rate signal (from W₃) and to a field rate raster distortion correction signal (27). A line deflection circuit according to Claim 6 characterized by a further winding (W₂) of said flyback transformer (T₁) coupled to said first resonant circuit (33) via a rectifier (D₄) to provide start-up current thereto.

Inventors: HAFERL, PETER EDUARD
Applicants: RCA LICENSING CORPORATION
Application year: 1985
Main classification: H04N3
IPC codes: H04N3