ROUNDING UNIT FOR USE IN ARITHMETIC PROCESSING OF FLOATING POINT DATA

Abstract: A rounding unit for use in arithmetic processing of float­ ing point data is disclosed. The rounding unit comprises a mantissa part register (101, 104) for storing the mantissa part of the floating point data, an exponent part register (108, 109) for storing the expo­ nent part of the floating point data, a judging circuit (112) for judging whether the rounding operation is raising or truncat­ ing, a mantissa part incrementer (105) for incrementing the mantissa part of the floating point data and outputting a carry signal (106) when it is overflowed, an exponent part increment­ er (110) for incrementing the exponent part of the floating point data and a selection circuit (113) which, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, orders to the mantissa part register to store a constant data of which the most signifi­ cant bit is '1' and the other bits are '0', when the rounding operation is raising and the carry signal is present. For generating the constant data, a constant register (107) or an adjusting means (120) is employed. The rounding unit of the invention executes the rounding operation of floating point data by hardware and thus it oper­ ates at a very high speed.

Description: Background of the Invention The present invention relates to a rounding unit, and more particularly to a rounding unit for use in the arithmetic processing operation of floating point data. A floating point data is represented by an exponent part and a mantissa part. That is, a floating point data A is represented by M x 2 E where E represents the exponent part and M indicates the mantissa part. When floating point data are processed by an arithmetic unit, their exponent parts and mantissa parts are in general independently processed, respectively. In the arithmetic processing operation of floating point data, however, mantissa part data which have a data length exceeding the predetermined word length for the mantissa part are often treated. For example, in the case of the multiplication of floating point data, multiplication is conducted with the mantissa parts and possibly results in a data having a data length twice longer than the word length which is predetermined for the mantissa part. Thus, an operation for adjusting the data length of the resulted mantissa part data with the predetermined word length is required to complete the processing. Such an operation is called "rounding operation". The computer which processes floating point data is usually equipped with a means which can temporarily store the data underflowing the least significant bit of the mantissa part. In accordance with the ordered rounding mode, the underflowing data is rounded by, for example, raising or truncating the same, to complete the arithmetic processing operation. The rounding mode includes a rounding to a nearest value, a rounding in the negative direction, a rounding in the positive direction, and a rounding in the direction toward zero. But the rounding operation includes only two cases, that is to raise one unit to the place of the least significant bit of the mantissa part and to truncate the value underflowing the least significant bit of the mantissa part. Namely, the rounding operation can be summarized as modifying the result or the arithmetic operation by adding "1" to the least significant bit of the mantissa part or truncating the underflowing value, depending upon the mode of rounding operation and the result of the arithmetic processing. However, there is an exception which can not be summarized as above. Such an exception is illustrated in Fig. 1. In this exceptional case, a mantissa part data, in which all of the bits are "1", is obtained as a result of the arithmetic processing, as shown In Fig. 1 (A). If such a mantissa part data is incremented by "1" by the rounding operation, the incremented data overflows the most significant bit of the mantissa part so that all of the bits in the mantissa part become "0" as shown in Fig. 1 (B). Thus an adjustment must be made to the mantissa part and to the exponent part. That is, the mantissa part must be a constant value in which the most significant bit is "1" and the other bits are "0", while the exponent part is incremented by "1" as shown in Fig. 1 (C). Accordingly, the rounding operation must always be conducted to cover such an exception. In the prior art, the rounding operation is conducted following to an operation flow shown in Fig. 2. First, it should be judged whether the rounding operation is raising or truncating. If the operation is raising, the mantissa part M B is incremented by "1" and then it is also judged whether or not a carry occurs due to the increment of the mantissa part M B . These operations have been conducted by a program in the prior art. But, in the case of processing a number of floating point data, checking operation of a carry signal must be conducted each time the increment operation of the mantissa part is conducted, even if the exception described above rarely occurs. Then, the period of time for the rounding operation is prolonged because of the checking of the carry signal. Further, in case a carry occurs as a result of the increment of the mantissa part, both the mantissa part and the exponent part must be adjusted, which causes to further prolong the period of time for the rounding operation. A rounding unit according to the preamble part of claim 1 is disclosed in IEEE Journal of Solid-State Circuits, Vol. SC-17, number 5, October 1982, New York, pp. 898-907, WARE et al "64 Bit Monolithic Floating Point Processors". Also in this rounding unit the rounding operation for a floating point data has to be conducted so that, when a rounding - by raising is indicated, the mantissa part is firstly incremented, and if an overflow is generated as the result of the increment of the mantissa part the exponent part is incremented and the incremented mantissa part is shifted by one in direction of the least significant bit. These operations, namely the increment of the mantissa part, the increment of the exponent part and the shift of the incremented mantissa have to be performed sequentially so that it requires a substantial time and rounding cannot be processed with high speed. A similar processor is disclosed in "Electronics", 10 February 1982, pages 149-152, WARE et al: "C-MOS chip set streamlines floating-point processing". Wherein the increment of the fraction is performed independently of the increment of the exponent leading to the above mentioned problems relating to high-speed processing. From "Electronic Design", 17 May 1984, pages 144-151 by Windsor et al: "Arithmetic duo excels in computing floating point products." It is known to use a different rounding method relating to different data formats and to switch among the data formats to maximize the precision of intermediate calculations. It is therefore the object of the invention to provide a rounding unit for arithmetic of floating point data in which the rounding operation can be performed with high speed. This object is achieved by a rounding unit for arithmetic processing of floating point data comprising a mantissa part and an exponent part, said unit comprising: A first data bus for transmitting data, a mantissa part data bus for transmitting the mantissa part of the floating point data, an exponent part data bus for transmitting the exponent part of the floating point data, a mantissa part register connected to said first data bus and to said mantissa part data bus for storing the mantissa part of the floating point data, an exponent part register, separate from said mantissa part register and connected to said first data bus and to said exponent part data bus, for storing the exponent part of the floating point data, a mantissa part incrementer, connected to said mantissa part data bus, for receiving and incrementing the mantissa part of the floating point data to provide increment mantissa data and for outputting a carry signal when it is overflowed, an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating point data to provide increment exponent data, a judging circuit for judging whether a rounding operation is raising or truncating, means for controlling said mantissa part incrementer and said exponent part incrementer in such a manner that said exponent part incrementer increments the exponent part of the floating point data concurrently with incrementing of the mantissa part of the floating point data by said mantissa part incrementer, and means, responsive to the carry signal from said mantissa part incrementer and the judging signal from said judging circuit representing that the rounding operation is raising, for outputting constant data in which the most significant bit is "1" and the remaining bits are "0". In a further embodiment of the invention said constant data outputting means includes a constant data register for storing said constant data, said constant data stored in said constant data register being read out in response to said carry signal from said mantissa part incrementer and said judging signal from said judging circuit representing that the rounding operation is raising. In a still further embodiment of the invention said constant data outputting means includes an adjusting means receiving said carry signal and the incremented data from said mantissa part incrementer, for generating said constant data by adding "1" to the most significant bit of said incremented data when said carry signal is outputted. According to the invention increment of the mantissa part and increment of the exponent part is performed concurrently, wherein, in response to the carry signal and the judging signal that it is a rounding-by-raising operation, the constant data is generated in which the most significant bit is "1" and the remaining bits are "0". This concept of concurrently incrementing the exponent part and the mantissa part leads to a rounding unit which can perform high speed rounding. Other objects and aspects of the invention will become apparent from the following description and embodiment of the invention which will be made with reference to the accompanying drawings. Brief Description of the Drawings Fig. 1 illustrates an exceptional case of the rounding operation of floating point data where an adjustment must be made to the mantissa and exponent parts. Fig. 2 shows operation flow of the rounding operation of the prior art. Fig. 3 is a block diagram showing a rounding unit of an example according to the present invention. Fig. 4 is a timing chart showing an operation flow of the rounding unit shown in Fig. 3. Fig. 5 a block diagram showing a rounding unit of another example according to the present invention. Fig. 6 shows in detail the adjusting means of the rounding unit shown in Fig. 5. Detailed Description of the Preferred Embodiments of the Invention Now, before describing the examples of the present invention, the rounding operation of the mantissa part data is illustrated in Table 1. As illustrated in Table 1, when the rounding operation is to truncate the value underflowing the least significant bit of the non-rounded mantissa part data M B , both of the mantissa part data and the exponent part data are not changed. On the other hand, when the rounding operation is to raise a unit to the place of the least significant bit of the mantissa part, that is, to add "1" to the least significant bit of the mantissa part data, either of two different operations is to be conducted depending upon the result of the increment of the mantissa part data. That is, when a carry operation is to be conducted to the exponent part due to the increment of the mantissa part data, the mantissa data must be a constant data of "1 0 ... 0" and the exponent part data must be incremented by "1". When a carry does not occur, the mantissa part data is incremented by "1" and the exponent part data remains unchanged. With the above in the mind, a preferred example of the present invention will be described with reference to Fig. 3. In the first example which will be explained with reference to Fig. 3, the rounding unit is to execute rounding operation of a floating point data of 32 bit length which consists of a coding part of one bit length, a mantissa part of 24 bit length and an exponent part of 7 bit length. As shown in Fig. 3, a rounding unit according to the present invention includes a first mantissa part register 101 to which a data M B representing the mantissa part of a floating point data before the rounding operation is executed is transferred from an arithmetic unit (not shown in the drawing) through a data bus 102. On the other hand, the first mantissa part register 101 is coupled to a mantissa part data bus 103. Thus, the first mantissa part register 101 may store a data representing the mantissa part of 24 bit length of a floating point data before the rounding operation is executed and transfer the same to the mantissa part data bus 103. A second mantissa part register 104 is also coupled with the mantissa part data bus 103 from which a data of 24 bit length may be transferred and stored therein. The second mantissa part register 104 is for storing a data M A representing the mantissa part of a floating point data after the rounding operation is completed. Thus, second mantissa part register 104 is of 24 bit length and coupled to the data bus 102 so as to transfer the rounded mantissa part data M A to the arithmetic unit. The rounding unit shown in Fig. 3 further includes a mantissa part incrementer 105 coupled to the mantissa part data bus 103 from which a data of 24 bit length may be set therein. The mantissa part incrementer 105 increments the data by "1" and, when an overflow occurs in the increment operation, it generates a carry signal 106. The thus incremented data may be transferred to the mantissa part data bus 103. The rounding unit further includes a constant register 107 coupled to the mantissa part data bus 103. The constant register 103 stores a constant data of 24 bit length in which the most significant bit is "1" and the other bits are "0". For rounding operation of a data representing the exponent part of the result of the arithmetic processing of floating point data, the rounding unit further includes a first exponent part register 108, a second exponent part register 109 and an exponent part incrementer 110. As mentioned above, the data representing the exponent part of the floating point data has 7 bit length. Then, the first and second exponent part register 108 and 109 can store a data of 7 bit length. The first exponent part register 108 receives a data E B representing the exponent part of the result of the arithmetic processing of floating point data before the rounding operation is executed from the arithmetic unit (not shown in the drawings), and it is also coupled to an exponent part data bus 111 so as to output the data E B to the exponent part data bus 111. On the other hand, the second exponent part register 109 is for storing a data E A representing the exponent part of the floating point data after the rounding operation is completed. The second exponent part register 109 is coupled to the exponent part data bus 111 to receive therefrom the data. The exponent part incrementer 110 is coupled to the exponent part data bus 111 to receive an exponent part data therefrom and to output an incremented exponent part data thereto. The exponent part incrementer is an adder of 7 bit length to increment the inputted exponent part data by "1". That is, "1" is added to the least significant of the exponent part data. The rounding unit shown in fig. 3 further includes a judging circuit 112 and a selection circuit 113. The judging circuit 112 is coupled to the data bus 102 to receive an information for judging whether the rounding operation is raising or truncating. The judging circuit 112 is connected to the selection circuit 113 by a line 114 through which a judging signal is inputted to the selection circuit 112. The selection circuit 112 receives a carry signal 106 at a first input and a judging signal 114 at a second input. On the other hand, the selection circuit 113 is connected to the mantissa part incrementer 105 via a line 115 for outputting a signal R₁, to the constant register 107 and the exponent part incrementer 110 via a line 116 for outputting a signal R₂, to the first mantissa part register 101 via a line 117 for outputting a signal R₃ and to the first exponent part register 108 via a line 118 for outputting a signal R₄. The selection circuit 113 decides to output either of the signals R₁, R₂, R₃ and R₄. The signal R₁ is to order to the mantissa incrementer 105 to output the incremented mantissa part data to the mantissa part data bus 103. The signal R₂ is to order to the constant register 107 and the exponent part incrementer 110 respectively to output the constant data to the mantissa part data bus 103 and the incremented exponent part data to the exponent part data bus 111. The signal R₃ is to order to the first mantissa part register 101 to output the mantissa part data M B to the mantissa part data bus 103, and the signal R₄ is to order to the first exponent part register 108 to output the exponent part data E B to the exponent part data bus 111. The selection of the signals R₁, R₂, R₃ and R₄ made by the selection circuit 113 is illustrated in Table II. The operation of the rounding unit shown in Fig. 3 will be described with reference to Fig. 4 which shows a timing chart of the operation of the rounding unit. As shown in Fig. 4, T₁ and T₂ indicate two subsequent periodic cycles generated by a clock (not shown in the drawings) to synchronize the operation of the rounding unit. Each clock cycle is divided into two periods by pulses ₁ and ₂. Pulse ₁ is at the high level during the second half period of each clock cycle while pulse ₂ is at the high level during the first half period of each clock cycle. First, the mantissa part M B and the exponent part E B of the result at the arithmetic processing of floating point data are respectively inputted to the first mantissa part register 101 and the first exponent part register 108 during the period ₂ of the cycle T₁ through the data bus 102. During a subsequent period ₁ of the cycle T₁, the first mantissa part register 101 and the first exponent part register 108 transfer the mantissa part data M B and the exponent part data E B respectively to the mantissa part data bus 103 and the exponent part data bus 111. Then, the mantissa part incrementer 105 and the exponent part incrementer 110 receive and latch the mantissa part data M B and the exponent part data E B respectively through the mantissa part data bus 103 and the exponent part data bus 111. During the period ₂ of the next cycle T₂, increment of the mantissa and exponent parts M B and E B and the selection of the signals by the selection circuit 113 are executed. That is, the mantissa part incrementer 105 increments by "1" the mantissa part data M B on which the rounding operation has not been executed. The mantissa part incrementer 105 outputs a carry signal "1" when the increment of the mantissa part data M B overflows the most significant bit, and it outputs a signal "0" when the carry does not occur. The exponent part incrementer 110 increments by "1" the exponent part data E B on which the rounding operation has not been executed. During the period ₂ of the cycle T₂, the selection circuit receives a carry signal 106 from the mantissa part incrementer 105 and a judging signal 114 from the judging circuit 112. Based on these input signals, the selection circuit 113 selects either of the signals R₁, R₂, R₃ and R₄ according to the logic illustrated in Table II. When the judging signal indicates that the rounding operation is to truncate the value underflowing the least significant bit of the mantissa part, the selection circuit 113 selects the signals R₃ and R₄. During the period ₁ of the cycle T₂, the first mantissa part register 101 transfers the data M B to the second mantissa part register 104 through the mantissa part data bus 103 according to the signal R₃, and the first exponent part register 108 transfers the data E B to the second exponent part register 109 through the exponent part data bus 111. When the judging signal indicates that the rounding is to raise one unit to the place of the least significant bit of the mantissa part and the carry signal 106 is absent, the selection circuit selects the signals R₁ and R₄. During the period ₁ of the cycle T₂, the mantissa part incrementer 105 and the first exponent part register 108 are actuated by the signals R₁ and R₄ respectively to transfer the incremented data to the mantissa part data bus 103 and transfer the exponent part data E B to the exponent part data bus 111. Then the second mantissa part register 104 and the second exponent part register 109 read the data present respectively in the mantissa part data bus 103 and the exponent part data bus 111. When the judging signal 114 indicates that the rounding operation is to raise a unit to the place of the least significant bit of the mantissa part and the carry signal is "1", the selection circuit 113 selects the signal R₂ which orders to the constant register 107 and the exponent part incrementer 110 to output the data to the mantissa part data bus 103 and the exponent part data bus 111, respectively. During the period ₁ of the second cycle T₂, the constant register 107 and the exponent part incrementer are actuated by the signals R₁ and R₂ respectively to transfer the constant data to the mantissa part data bus 103 and transfer the incremented exponent part data to the exponent part data bus 111. Then the second mantissa part register 104 and the second exponent part register 109 read the data present respectively in the mantissa part data bus 103 and the exponent part data bus 111. That is, the rounded mantissa part data M A which is now held in the second mantissa part register 104 is a constant data in which the most significant bit is "1" and the other bits are "0". The rounded exponent part data E A which is held in the second exponent part register 109 is a data obtained by incrementing by "1" the exponent part data E B . As explained in detail in above, the rounding operation of floating point data can be executed within two clock cycles up to the storing of the rounded data in the registers 104 and 109. Thus, the rounding operation can be conducted at a very high speed. Then the second mantissa part register 104 and the second exponent part register 109 transfer respectively the data M A and E A to the arithmetic unit through the data bus 102. The second example of the rounding unit according to the present invention will be explained with reference to Figs. 5 and 6. The rounding unit of the present example is similar to that shown in Fig. 3 except that an adjusting means is employed in lieu of the constant register 107 shown in Fig. 3 and that the logic of the selection circuit 113 is different from that of the selection circuit 113 of the rounding unit shown in Fig. 3. In Fig. 5, same numerical references are used as in Fig. 3 to indicate the same or corresponding elements. As shown in Fig. 5, the rounding unit of the second example includes an adjusting means 120 having an input connected to the output of the mantissa part incrementer 105 and an output coupled to the mantissa part data bus 103. In this example, the output of the mantissa part incrementer 105 is not coupled with the mantissa part data bus 103. Similar to the rounding unit shown in Fig. 3, the selection circuit 113 receives at an input the carry signal 106 from the mantissa part incrementer 105 and at another input a judging signal 114 from the judging circuit 112. But, the output of the selection circuit 113 is connected to the adjusting means 120 for outputting a signal R₁, to the exponent part incrementer 110 for outputting a signal R₂, to the first mantissa part register 101 for outputting a signal R₃ and to the first exponent part register 108 for outputting a signal R₄. As shown in Fig. 6 which shows in detail the adjusting means 120, the adjusting means 120 is connected at an input thereof to the output of the mantissa part incrementer 105 and receives at another input thereof the carry signal 106 from the mantissa part incrementer 105. The adjusting means 120 modifies the incremented data by adding the carry signal 106 to the most significant bit of the incremented mantissa part data. That is, when the carry signal is "1" which means that a carry occurs due to the increment of the mantissa part data, the adjusting means 120 modifies the incremented data to "10 ... 0". Thus, the mantissa part data thus modified by the adjusting means 120 becomes a constant data in which the moot significant bit is "1" and the other bits are "0". On the other hand, when the carry signal is "0" which means that a carry does not occur, in fact, the adjusting means does not modify the incremented mantissa part data. Turning to Fig. 5, the selection circuit 113 receives the carry signal 106 and the judging signal 114 and selects the signals from R₁, R₂, R₃ and R₄ according to a logic illustrated in Table III. The operation of the rounding unit shown in Fig. 5 is similar to that of the rounding unit shown in Fig. 3 except when the judging signal 114 indicates that the rounding operation is raising. That is, when the judging signal indicates that the rounding is to raise one unit to the place of the least significant bit of the mantissa part and the carry signal 106 is absent, the selection circuit selects the signals R₁ and R₄. During the period ₁ of the cycle T₂, the adjusting means 120 and the first exponent part register 108 are actuated by the signals R₁ and R₄ respectively to transfer the adjusted data to the mantissa part data bus 103 and transfer the exponent part data E B to the exponent part data bus 111. As mentioned above, however, in this case, the adjusted mantissa part data remains unchanged. Thus, the mantissa part data M A stored and held in the second mantissa port register 104 is equal to the mantissa part data M B incremented by "1". When the judging signal 114 indicates that the rounding operation is to raise a unit to the place of the least significant bit of the mantissa part and the carry signal is "1", the selection circuit 113 selects the signals R₁ and R₂ which order to the adjusting means 120 and the exponent part incrementer 110 to output the data to the mantissa part data bus 103 and the exponent part data bus 110, respectively. During the period ₁ of the second cycle T₂, the adjusting means 120 and the exponent part incrementer 110 are actuated by the signals R₁ and R₂ respectively to transfer the adjusted incremented data to the mantissa part data bus 103 and transfer the incremented exponent part data to the exponent part data bus 111. Then the second mantissa part register 104 and the second exponent part register 109 read the data present respectively in the mantissa part data bus 103 and the exponent part data bus 111. That is, the rounded mantissa part data M A which is now held in the second mantissa part register 104 is the adjusted incremented data, which is equal to a constant data in which the most significant bit in "1" and the other bits are "0". The rounded exponent part data E A which is held in the second exponent part register 109 is a data obtained by incrementing by "1" the exponent part data E B . As explained in above, the rounding unit according to the present invention can process at a high speed floating point data of any form without checking the presence of a carry by a software. Further, the rounding unit of the present invention can be fabricated by hardware circuits which are simple in construction and thus it is very useful for rounding operation of floating point data of high speed. Although the examples are explained with the floating point data including a mantissa part of 24 bit length and an exponent part of 7 bit length, a rounding unit having a construction similar to the above examples can process floating point data of an enlarged format.

Claims: A rounding unit for arithmetic processing of floating point data comprising a mantissa part and an exponent part, said unit comprising: A first data bus (102) for transmitting data, a mantissa part data bus (103) for transmitting the mantissa part of the floating point data, an exponent part data bus (111) for transmitting the exponent part of the floating point data, a mantissa part register (101, 104) connected to said first data bus (102) and to said mantissa part data bus (103) for storing the mantissa part of the floating point data, an exponent part register (108, 109), separate from said mantissa part register (101, 104) and connected to said first data bus (102) and to said exponent part data bus (111), for storing the exponent part of the floating point data, a mantissa part incrementer (105), connected to said mantissa part data bus (103), for receiving and incrementing the mantissa part of the floating point data to provide increment mantissa data and for outputting a carry signal when it is overflowed, an exponent part incrementer (110), connected to said exponent part data bus (111), for receiving and incrementing the exponent part of the floating point data to provide increment exponent data, characterized in that the unit is further comprising: A judging circuit (112) for judging whether a rounding operation is raising or truncating, means (113) for controlling said mantissa part incrementer (105) and said exponent part incrementer (110) in such a manner that said exponent part incrementer (110) increments the exponent part of the floating point data concurrently with incrementing of the mantissa part of the floating point data by said mantissa part incrementer (105), and means (107, 120), responsive to the carry signal from said mantissa part incrementer (105) and the judging signal from said judging circuit (112) representing that the rounding operation is raising, for outputting constant data in which the most significant bit is "1" and the remaining bits are "0". A rounding unit as claimed in claim 1, wherein said constant data outputting means includes a constant data register (107) for storing said constant data, said constant data stored in said constant data register being read out in response to said carry signal from said mantissa part incrementer (105) and said judging signal from said judging circuit (112) representing that the rounding operation is raising. A rounding unit as claimed in claim 1, wherein said constant data outputting means includes an adjusting means (120) receiving said carry signal and the incremented data from said mantissa part incrementer (105), for generating said constant data by adding "1" to the most significant bit of said incremented data when said carry signal is outputted.

Inventors: IWASAKI, JUNICHI, TAKAHASHI, TOSHIYA
Applicants: NEC CORPORATION
Application year: 1985
Main classification: G06F7
IPC codes: G06F7