HIGH-SPEED SEMICONDUCTOR DEVICE

Abstract: A high-speed semiconductor device comprising an emit­ ter potential barrier layer (2) disposed between an emitter layer (1) and a base layer (3), a collector layer (5), and a collector potential barrier layer (4a) disposed between the base layer (3) and the collector layer (5). The collector potential barrier layer (4a) has a structure having a barrier height changing from a high level to a low level along the direction from the base layer (3) to the collector layer (5), whereby, even when no bias voltage is applied between the collector layer (5) and the emitter layer (1), a collector current can flow through the device.

Description: HIGH-SPEED SEMICONDUCTOR DEVICE The present invention relates to a high speed semiconductor device, for example that known as a hot electron transistor (HET). Examples of related references in the field are as follows: "Resonant Tunneling in Semiconductor Double Barriers", by L.L. Chang, L. Esaki, and R. Tsu, in Applied Physics Letters, Vol. 24, No. 12, 15 June, 1974; Japanese Unexamined Patent Publication (Kokai) No. 58-3277 published on January 10, 1983, Applicant: International Business Machines Corporation, Inventor: L. Esaki, claiming priority based on United States Application Serial Number 280,141 filed on February 5, 1982; "Characterization of Double Heterojunction GaAs/AlGaAs Hot Electron Transistors", N. Yokoyama, et al. PROCEEDINGS OF THE IEEE INTERNATIONAL ELECTRON DEVICES MEETING, Dec. 1984, pp 532 to 535; and United State Application Serial No. 754,416, filed July 12, 1985 or European Patent Application No. 85401440.4, filed July 15, 1985. In recent years, due in part to advances made in molecular beam epitaxy (MBE) technology, there have been proposed semiconductor devices using heterojunctions. Among the same, considerable expectations are placed on HET's as high speed semiconductor devices, since hot electrons are used in the HET's as carriers and thus the transit time of the hot electrons HET through the/base is drastically shortened (United States Application Serial No. 722,053, filed April 11, 1985, or European Patent Application No. 85400744.0, filed April 16, 1985). the HErS pro##osed prior to / present invention, however, contain the problems of high power consumption and low switching speed, because the lowest collector-emitter voltage for conducting current through the HET is relatively high. An embodiment of the present invention may improve the power consumption characteristic of an HET. An embodiment of the present invention may improve the switching speed characteristic of an HET. In accordance#with the present invention, there is provided a high-speed semiconductor device comprising an emitter layer, a base layer, an emitter potential barrier layer disposed between said base layer and said collector layer, a collector layer, and a collector potential barrier layer disposed between said base layer and said collector layer. The collector potential barrier layer has a structure having a barrier height changing from a high level to a low level along the direction from the base layer to tho collector layer,, when the device is in a thermal equilibrium state. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1A is an energy band diagram of a thermal equilibrium state of a prototype HET prior to the present invention; Fig. 1B is an energy band diagram of an operating state of a prototype HET prior to the present invention; Fig. 1C is an energy band diagram showing a state when the collector-emitter voltage VCE is zero in a prototype HET prior to the present invention; Fig. 2 is a graph > illustrating a relationship between the collector-emitter voltage VCE and the collector current IC in an HET prior to the present invention; Fig. 3 is a cross-sectional view of an HEX according to an embodiment of the present invention; ; Fig. 4A is an energy band diagram showing a thermal equilibrium state of an HET according to an embodiment of the present invention; Fig. 4B is an energy band diagram in an operating state of the HET of Fig. 4A; Fig. 5 is a graph diagram illustrating a relationship between the collector-emitter voltage VCE -and-the collector current IC in the HET of Fig. 4B; Fig. 6A is an energy band diagram showing a thermal equilibrium state of an HET according to another embodiment of the present invention; and Fig. 6B is an energy band diagram showing an operating state of the HET of Fig. 6A. Before describing embodiments of the present invention, a prototype HET prior to the present invention and the problems therein will first be described with reference to Figs. lA through lC and Fig. 2. Figures 1A through lC are energy band diagrams of a thermal equilibrium state, an operating state, and a state when VCE is zero, respectively, in a prototype HET prior to the present invention. The prototype HET has five layers, i.e., an n type GaAs emitter layer (E) 1, a non-doped AlGaAs emitter potential barrier layer (EPB) 2, an n type GaAs base layer (B) 3, a non-doped AlGaAs collector side potential barrier layer (CPB) 4, and an n type GaAs collector layer (C) 5. In the Figures lA through lC, the solid lines represent the lowest energy level EC of the conduction band in respective layers. In the thermal equilibrium state, since no voltage is applied between the emitter layer 1 and the base layer 3 or between the emitter layer 1 and the collector layer 5, the Fermi levels EFE , EFB , and EFC in the emitter layer 1, in the base layer 3, and in the collector layer 5 are the same as each other, as shown in Fig. lA. In such an HET, a positive bias voltage VCE is applied between the collector layer 5 and the emitter layer 1, and a positive bias voltage VBE is applied between the base layer 3 and the emitter layer 1 so that the base Fermi level EFB is lowered by, for example, 0.30 eV, from the emitter Fermi level, and the collector Fermi level EFC is lowered by, for example, 0.50 eV, from the emitter Fermi level. The energy band diagram in this state is shown in Fig. 1B. Due to the positive bias voltages, the gradient of the energy level in the emitter potential barrier layer 2 or in the collector potential barrier layer 4 becomes larger. As a result of the larger gradient in the emitter potential barrier layer 2, the emitter barrier becomes thinner. Thus, electrons injected from the emitter layer I can tunnel through the emitter potential barrier 2 to be injected in the base layer 3. There, the potential energy held by the electrons e is converted to kinetic energy so that the electrons become high-speed hot electrons. Since the level of collector potential barrier layer 4 is also lowered'and has a gradient due to the lowered energy levels of the base Fermi level EFB and the collector Fermi level EFC , the hot electrons can pass through the collector potential barrier layer 4 to be injected into the collector layer 5 without scattering. In prior HETs however, problems arise when the collector-emitter voltage VCE is close to zero, as shown in Fig. lC. That is, since the emitter Fermi level EFE and the collector Fermi level EFC are equal in tis case, and the collector potential barrier layer 4 has a height BH from the lowest level of the collector induction band ECC , the kinetic energy of the hot electrons in the base layer is lower than the barrier height BH from the collector conduction band ECC Therefore, the hot electrons cannot pass through the collector potential barrier 4. More specifically, if the collector potential barrier layer 4 is comprised of intrinsic-type Al 3Geo 7As, the barrier height BH there would be approximately 0.3 eV. Since the thickness of the emitter potential barrier layer 2 would be 250 to 500 (25 nm to 50 nm), and the thickness of the collector side potential barrier layer 4 would be 1500 to 2000 (150 nm to 200 nm), in the state where the collector emitter voltage VCE is close to zero, even if a base emitter voltage VBE were applied to give the level difference AE of 0.30 eV, the electrons would tunnel through the emitter potential barrier layer 2, but could not cross the collector potential barrier layer 4. Figure 2 is a graph showing the relationship between the collector emitter voltage VCE and the collector current IC in a prototype HET prior to the present invention. In the F#igure, the horizontal axis indicates the collector emitter voltage VCE and the vertical axis the collector current Ic. C1 through C4 are curves representing voltage-current characteristics. Lo represent a load line. As may be judged from the Figure, when the collector emitter voltage VCE.= 0, no collector current IC flows. It only begins to flow when a voltage enabling overcoming of the barrier height BH = 0.3 eV, i.e., a voltage of VCE = 0.3 V or more, is applied. Further, if the base emitter voltage VBE is raised, the collector emitter voltage VCE required for raising the collector current IC would shlf U )Further, if the base emitter voltage VBE is raised, the electrons at the emitter layer 1 would tunnel through at a location close to the bottom of the conduction band. Therefore, to pass a collector current IC under such a state, the collector emitter voltage VCE would have to be further increased. In general, in this type of semiconductor device, if the collector current IC can flow regardless of the ir#ressed collector emitter voltage VCE being low, the stching speed can naturally be improved and the power consumption reduced. In addition, when the prototype HET is used as a logic element in a logic circuit, the low output level L is too high as will be seen from the intersection of load line Lo with one of the curves C1 through C4. Therefore, when the prototype HET is used as a logic element in a logic circuit, a level shift circuit to lower the low output level is needed. The present invention enables a collector current to toflaweven when the collector emitter voltage VCE is almost zero. In the high speed semiconductor device of the present invention, the value x at a nondoped Al Gal As collector potential barrier layer existing between the base layer and collector layer is gradually reduced from said base layer side to said collector layer side to provide a so-called grading state. With the above-mentioned constitution, the barrier height BH at the collector potential barrier layer is gradually reduced from the base layer side to the collector layer side, so even when the collector emitter voltage VCE is close to almost zero, if the base emitter voltage VBE is applied, electrons tunneling from the emitter layer through the emitter side potential barrier layer for injection into the base layer will be able to cross the collector side potential barrier layer and reach the collector layer without hindrance. Embodiments of the present invention will be described in the following. Figure 3 is a cross-sectional view of an HET according to an embodiment of the present invention. In Fig. 3, reference numerals 1, 2, 3, and 5 represent an emitter layer, an emitter potential barrier layer, a base layer, and a collector layer, respectively According to this embodiment of the present invention, a new collector potential barrier layer 4a is further pro1dE# The collector layer 5 is formed on a semi-insulating GaAs substrate 6, the collector-potential barrier (CPB) layer 4a is formed on the collector layer 5, the base layer 3 is formed on the CPB 4a, and the emitterpotential barrier (EPB) layer 2 is formed on the base layer 3. The emitter layer 1 is formed on the emitterpotential barrier layer 2, and a collector electrode 7 made of gold.germanium/gold (Au¯Ge/Au) is formed on the collector layer 5 so as to be in ohmic contact with the collector layer 5. The notation Au.Ge/Au represents a state wherein an alloy Au-Ge is covered by a layer of Au. A base electrode 8 made of goldXgermanium/gold (Au. Ge/Au) is formed on the base layer 3 so as to be in ohmic contact with the base layer 3. The term Au¯Ge/Au represents a state wherein an alloy Au-Ge is covered by a layer of Au. An emitter electrode 9 made of gold. germanium/gold (Au. Ge/Au) is formed on the emitter layer 1 so as to be in ohmic contact with the emitter layer 1. Examples of the combination of the material in the embodiment shown in Fig. 3 are as follows. Example 1 Emitter layer 1: GaAs Emitter potential barrier layer 2: Al Ga As, y l-y where y is a constant, e.g., 0.3 Base layer 3: GaAs Collector potential barrier layer 4a: Alx Gal-xAs, where x is variable Collector layer: GaAs Example 2 Emitter layer 1: GaAs Emitter potential barrier layer 2: Al In As, y l-y where y is a constant, e.g., 0.47 Base layer 3: In Ga As, where z is a constant, z e.g., 0.53 Collector potential barrier layer 4a: Al In As, x where x is variable Collector layer-5: GaAs In this example, the value x should be smaller than the value y. Figure 4A is an energy band diagram in a thermal equilibrium state of the HET of the embodiment shown in Fig. 3. As will be seen from the comparison of Figs. 1A and 4A, the conduction band in the collector-potential barrier layer 4a in this embodiment has a structure having a barrier height changing from a high level to a low level along the direction from the base layer 3 to the collector layer 5. That is, the barrier height between the base layer 3 and the collector potential barrier layer 4a is BH1 , which is as high as, for example, 0.30 eV. The barrier height BH1 may or may not be the same as the barrier height of the emitter potential barrier layer 2. In Fig. 4A, the barrier height BE1 is shown as being lower than the barrier height of the emitter potential barrier layer 2. On the contrary, the barrier height between the collector potential barrier layer 4a and the collector layer 5 is BE2 , which is a value smaller than the potential barrier of the emitter potential barrier layer 2 and higher than the lowest energy level ECC of the conduction band in the collector layer 5. The potential barrier in the layer 4a is for example linearly decreased from BH1 to BR2. In the Figure, the value x at the intrinsic type Al Gal As collector potential barrier layer 4a is reduced from the base layer 3 side to the collector layer 5 side, whereby a grading state is achieved. By doing so, the potential barrier also falls, as illustrated. Figure 4B is an energy band diagram illustrating in an operating state of the HET according to an embodiment of the present invention. In Fig. 4B, a positive bias voltage VBE is applied betweu: the base layer 3 anc the emitter layer 1 so that the base Fermi level EFB is lowered by, for example, 0.30 eV, from the emitter Fermi level EFE The lowest energy level ECB of the base conduction band is also lowered by 0.3 eV from the energy level ECE In this embodiment, no voltage is applied between the collector layer 5 and the emitter layer 1. Therefore, the lowest energy level ECE of the conduction band of the emitter layer 1 is the same as the lowest energy level ECE of the conduction band of the collector layer 5. Accordingly, the collector potential barrier layer 4a is lowered to be lower than the lowest energy level ECC of the collector conduction band. Each of the electrons e tunneling from the emitter layer 1 through the emitter potential barrier layer 2 to the base layer 3 has a kinetic energy higher than the energy level ECE or ECC Since the collector potential barrier layer 4a does not act as a potential barrier for the electrons having the energy higher than ECC or ECE,the hot electrons in the base layer 3 will easily cross the collector potential barrier layer 4 and reach the collector layer 5. The collector potential barrier layer 4a in Fig. 4B does not act as a potential barrier but acts as a PN junction, such as that in a conventional bipolar transistor, for insulating the base layer 3 from the collector layer 5. The barrier height BH2 at the collector layer 5 side is determined to be as small as possible as long as electrons in the collector layer 5 do not enter the base layer 3 due to thermal diffusion. for example If /eye vauex at the intrinsic type AlxGal xAs collector potential barrier layer 4a is made 0.3 at the base layer 3 side and 0.1 to 0.2 at the collector layer 5 side, the barrier height BH1 of the base layer 3 side at the collector side potential barrier layer 4a may be 0.3 eV and the barrier height BH2 of the collector layer 5 side may be 0.1 to 0.2 eV. Figure 5 is a graph showing the relationship between the collector emitter voltage VCE and the collector current IC according to an embodiment of the present invention in the state as shown in Fig. 43. In the Figure, the horizontal axis indicates the collector emitter voltage VCE and the vertical axis the collector current Ic. As can be understood from the Figure, a collector current IC begins to flow even when the collector emitter voltage VCE is almost zero. Further, even if the base emitter voltage VBE is made high, there is almost no shifting of the lowest collector emitter voltage VCE for conducting a collector current Ic. Therefore, the switching speed can be improved and the power consumption reduced. Further, the low output L shown in Fig. 5 is sufficiently low in comparison with the ¯ low output shown in Fig. 2. Therefore, the HET according to the embodiment of the present invention is convenient for use in a logic circuit, since no level shift circuit is necessary. To change the structure of the intrinsic type Al Go as collector side potential barrier layer as x in the present invention, the content of Al in the crystalline layer may be gradually changed or the MBE method may be applied to form superimposed films of intrinsic type Al Ga, As with different x values. Further, When reducing the barrier height from the base layer side to the collector layer side as mentioned above, there might be thought to be sane cause for concern with the withstand (breakdown) voltage between the collector and base. The withstand voltage when the collector layer is made positive in potential, should be more than the power supply voltage at the circuit. When made negative in potential, however, it may be about the same as the withstand voltage between the base and emitter. Therefore, the problem of withstand voltage is not an immediate concern. Figure 6A and 6B show another embodiment of the (alternative) present invention. As shown in Fig. 6A, another/ew:tter potential barrier later 2a is employed in this embodi- ment. The emitter potential barrier layer 2a has at least one quantum well QW known as a superlattice. The quantum well QW is made of, for example, GaAs. Both emitter barrier layers 2a1 and 2a2 2 adjacent to the quantum well QW are made of Al Ga1##As, where x is a x value equal to 0.33. The value x in the layers 2a1 and 2a2 should be greater - than a value y in Al G As in y the collector potential barrier layer 4a. Resonant tunneling through sucn a quantum well QN itself is aknown phenomenon, described in, for example, "Resonant tunneling through quantum wells at frequencies up to 2.5 THz", by T.C.L.G. Solder, et al., Appl. Phys. Lett. 43 (6), 15 September 1983 pp 588-590. By employing a quantum-well structure, or superlattice, the so-called resonant tunneling is carried out near the Fermi level. Therefore, the tunneling effect through the emitter potential barrier layer 2a is carried out more effectively in comparison with the first embodiment shown in Fig. 4A. A resonant hot electron transistor (RHET1 has already been proposed. (see United States Application Serial No. 754,416, or European Patent Application No. 85401440.4). In the embodiment shown in Figs. 6A and 6B, the superlattice structure is applied to the emitter potential barrier layer 2a. The operation of a resonant hot electron transistor employing the graded collector potential barrier layer 4a is very similar to the operation as described with reference to Fig. 4B. Therefore, the description for operation with reference to Fig. 6B is omitted here. With the above-mentioned constitution, the barrier height at the collector potential barrier layer is gradually reduced from the base layer side to the collector layer side, so even when almost no the collector emitter voltage is applied, electrons tunneling fror the emitter layer through the emitter potential barrier for injection- into the base layer will be able to cross the collector side potential barrier layer and reach the collector layer without any hindrance. Therefore, even when the collector emitter voltage is almost zero, a collector current may flow immediately upon application of the base emitter voltage. As a result, the switching speed can be improved and the power consumption reduced.

Claims: CLAIMS 1. A high-speed semicomcuctor device comprisD.#g: an emitter layer, a base layer, an emitter potential barrier layer disposed between said emitter layer and said base layer, a collector layer, and a collector potential barrier layer disposed between said base layer and said collector layer, said collector potential barrier layer having a structure having a barrier height changing from a high level to a low level along the direction from said base layer to said collector layer when the device is in a thermal ilibrium state. 2. A high-speed semiconductor device as set forth in claim 1, wherein said collector potential barrier layer is formed by non-doped Awl go where the x a1#xAs, value x gradually decreases from said base layer side to said collector layer side. 3. A high-speed semiconductor device as set forth in claim 1, wherein said collector potential barrier layer is formed by non-doped AlxInl xAs, where x gradually decreases from said base layer side to said collector layer side. 4. A high-speed semiconductor device as set forth wherein in claim 1,2, or 3, / the barrier height of said collector potential barrier layer is lower than the kinetic energy of hot electronstunneled from said emitter layer through said emitter potential barrier layer to said base layer when a positive bias voltage is applied between said base layer and said emitter layer, even when said collector layer and said emitter layer have substantially the same energy levels. 5. A high-speed semiconductor device as set forth said in claim 1,2,3 or 4,whe rein/emitter potential barrier layer has at least one quantum well, whereby the passage of electrons from said emitter layer to said base layer may be effected by resonant tunneling.

Inventors: IMAMURA, KENICHI, OHSHIMA, TOSHIO, YOKOYAMA, NAOKI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H01L29
IPC codes: H01L29