MULTILAYER WIRING SUBSTRATE

Abstract: A multilayer wiring substrate comprising two groups of power supply wiring layers each containing a plurality of power supply wiring layers for supplying a plurality of different voltages, respectively, and a plurality of insulating layers. A plurality of first via-hole wirings connect each of the power supply wiring layers in a first of the groups to a corresponding one of the power supply wiring layers in a second of the groups. On a bottom surface of the second group of wiring layers there are a plurality of terminals which are connected to the wiring layers by a plurality of second via-hole wirings. A signal wiring layer section containing a plurality of thin film signal wiring layers, a plurality of insulating layers and a plurality of third via-hole wirings connecting the signal wiring layers to each other is provided on the first group of power supply wiring layers. Finally, each of a plurality of internal wirings has one end exposed at the top surface of the signal wiring layer section and another end connected to the power supply wiring layers in the first group.

Description: The present invention relates to a multilayer wiring substrate and, more particularly, to a multilayer wiring substrate having a plurality of power supply wiring layers. An example of conventional ceramic multilayer wiring substrates is disclosed in U.S. Pat. No. 4,245,273. The prior art substrate has a plurality of integrated circuit (IC) chips on the top surface thereof, a plurality of input/output (I/O) pins used as I/O terminals, a plurality of power pins used as power supply terminals on the bottom surface of said substrate, and a plurality of power supply wiring layers provided therein to supply predetermined different voltages to the IC chips and other electrical components provided on the substrate. However, as described later in detail by referring to the drawings, the laminated structure of the power supply wiring layers in the prior art substrate has a disadvantage in that it is not easy to obtain the predetermined voltage from a desired power supply wiring layer at a desired location on the substrate. Another disadvantage of the prior art substrate is that when the signal wiring layers and the insulating layers formed by a thick film technique using inorganic insulating paste are alternately formed on the substrate, the resistance values of via-hole wirings for power supply, which penetrate the insulating layers, are undesirably larger because of a large thickness of each of the insulating layers. EP-A-0.099.544 discloses a multi-level interconnection packaging structure for mounting large scale integrated circuit semiconductor device chips. The structure comprises a multi-layer ceramic body, a multi-level interconnection layer on top of the body, and a plurality of input/output pins on the bottom of the body. Within the body are multiple layers of conductive patterns connected by vias. The interconnection layer provides a smaller grid size of a denser interconnection on the top surface of the ceramic body. It includes first and second levels of conductive patterns spaced by a dielectric layer and via studs which connect the first and second level conductive patterns. Pads for mounting integrated circuit chips are included in the second level patterns. An object of the present invention is to provide a substrate free from the above-mentioned disadvantages of the prior art substrate. According to the present invention, there is provided a multilayer wiring substrate comprising a ceramic substrate (1) containing a plurality of power supply wiring layers (a-h), a signal wiring layer section (2) on top of the ceramic substrate (1) and a plurality of terminals (20) on the bottom of the ceramic substrate (1), wherein: the said plurality of power supply wiring layers (a-h) comprise a first group (11) of power supply wiring layers for supplying a plurality of different voltages, respectively, the wiring layers in the first group (11) being parallel arranged and vertically spaced, and a plurality of first insulating layers for insulating the wiring layers in the first group from each other; and a second group (12) of power supply wiring layers which are in one-to-one correspondence with the layers in the first group (11), the wiring layers in the second group (12) being parallel-arranged, vertically spaced and located vertically above the first group, and a plurality of second insulating layers for insulating the wiring layers in the second group from each other; a plurality of first via-hole wirings (23,25,27,29) connect each of the power supply wiring layers in the first group to a corresponding one of the power supply wiring layers in the second group; and a plurality of second via-hole wirings (22,24,26,28) connect said terminals (20) to said power supply wiring layers in said first group (11); said signal wiring layer section (2) comprises a plurality of thin film signal wiring layers (41,42,43), a plurality of third insulating layers (51,52,53) for insulating the signal wiring layers, and a plurality of third via-hole wirings (61,62,63)for connecting said signal wiring layers to each other, to form a plurality of internal wirings each having one end (44) exposed on a top surface of the signal wiring layer section and the other end (41) connected to one of said second power supply wiring layers (12). The invention will now be described, by way of example, with reference to the accompanying drawings, in which:- Fig. 1 is a cross-sectional view of a prior art substrate; and Fig. 2 is a cross-sectional view of an embodiment of the present invention. Referring to Fig. 1, a prior art ceramic multilayer wiring substrate 110 comprises a first power supply wiring layer 111 connected to via-hole wirings 131 and 134 whose one ends are exposed on the bottom surface of the substrate 110 and connected to via hole wirings 132 and 133 whose one ends are exposed on the top surface of the substrate 110; a second power supply wiring layer 112 connected to a via-hole wiring 141 where one end is exposed on the top surface of the substrate 110 and connected to a via-hole wiring 142 whose one end is exposed on the bottom surface of the substrate 110; and a third power supply wiring layer 113 connected to a via-hole wiring 151 whose one end is exposed on the bottom surface of the substrate 110 and connected to a through-hole wiring 152 penetrating through the substrate 110. The prior art substrate further includes a fourth power supply wiring layer 114 connected to a through-hole wiring 161 penetrating through the substrate 110, a plurality of insulating layers 120 for insulating the wiring layers 111 through 114 from one another, and a plurality of signal wiring layers 115. In the prior art substrate, when a power supply wiring layer (for example, the wiring layer 112) is connected to the wiring layer 115 through the via-hole wiring 141 at a location on the top surface of the substrate, another power supply wiring layer (for example, the wiring layer 111), arranged on a plane which is closer to the top surface of the substrate 110 than the wiring layer 112, cannot be connected to the through-hole wiring 151 located opposite to the via-hole wiring 141. As a result, it is not easy to obtain the predetermined voltage from a desired power supply wiring layer at a desired location on the top surface of the substrate 110. Referring to Fig. 2, an embodiment of the invention comprises a ceramic multilayer wiring section 1 and a thin film multilayer wiring section 2. The section 1 comprises pin-shaped terminals 20; through-hole wirings 21 connected to some of the terminals 20 to perform the transmission of signals given to or from the section 2; via-hole wirings 22 and 23 connected to first power supply wiring layers a and e supplying a first power supply source voltage, via-hole wirings 24 and 25 connected to second power supply wiring layers b and f for supplying a second power supply source voltage; via-hole wirings 26 and 27 connected to third power supply wiring layers c and g for supplying a third power supply source voltage, and via-hole wirings 28 and 29 connected to fourth power supply wiring layers d and h for supplying a fourth power supply source voltage. A via-hole wiring 30 connected to the wiring layer e , a via-hole wiring 31 connected to the wiring layer f , a via-hole wiring 32 connected to the wiring layer g and a via-hole wiring 33 connected to the wiring layer h are arranged in the vicinity of the top surface of the section 1. Each of the wiring layers in the wiring section 1 is made of tungsten or molybdenum. in the wiring section 1 is made of tungsten or molybdenum. The wiring layers a through d on the bottom side of the section 1 belong to a first group 11, while the wiring layers e through h on the top side of the section 1 belong to a second group 12. Such a structure allows arbitrary connection of any of the terminals 20 to any of the power supply wiring layers in the first group 11 as well as arbitrary connection of any of via-hole wirings arranged at arbitrary positions on the top surface of the section 1 to any of the power supply wiring layers in the second group 12. For example, in the part surrounded by a dashed line X in Fig. 2, the first group 11 alone cannot directly connect the wiring-layer b to a portion 41a of a signal wiring layer 41 due to the presence of a through-hole wiring 28 connected to the wiring layer d . However, the layer b can indirectly be connected to the portion 41a by connecting the wiring layer f in the group 12 to the portion 41a. The locations and the number of via-hole wirings connecting the wiring layers, which provide the same power supply source voltage, can be arbitrarily selected as follows: 100 lines between the wiring layers a and e ; 50 lines between b and f ; 50 lines between c and g ; and 20 lines between d and h . In other words, the number and the location of the via-hole wirings can be selected to satisfy the required current capacity of each power supply wiring. In the embodiment, the thin-film multilayer wiring section 2 formed on the section 1 comprises: thin film signal wiring layers 41, 42, 43 and 44 made of gold or copper; polyimide insulating layers 51, 52 and 53 made of a polyimide material for insulating the signal wiring layers from each other; and via-fills 61, 62 and 63 composed of a mixture of gold and polyimide. Since a polyimide insulating film has a superior insulation property as compared to the insulating film formed by printing and sintering inorganic paste, sufficient insulation can be achieved by the use of a thin polyimide insulating film. for example, a fifteen-micron thick polyimide insulating film can achieve the same insulation ability as an inorganic insulating film of a sixty-micron thickness. As a result, the resistance of the via-hole wiring penetrating such a thinner polyimide insulating film can be reduced.

Claims: A multilayer wiring substrate comprising a ceramic substrate (1) containing a plurality of power supply wiring layers (a-h), a signal wiring layer section (2) on top of the ceramic substrate (1), and a plurality of terminals (20) on the bottom of the ceramic substrate (1), wherein: the said plurality of power supply wiring layers (a-h) comprise a first group (11) of power supply wiring layers for supplying a plurality of different voltages, respectively, the wiring layers in the first group (11) being parallel arranged and vertically spaced, and a plurality of first insulating layers for insulating the wiring layers in the first group from each other; and a second group (12) of power supply wiring layers which are in one-to-one correspondence with the layers in the first group (11), the wiring layers in the second group (12) being parallel-arranged, vertically spaced and located vertically above the first group, and a plurality of second insulating layers for insulating the wiring layers in the second group from each other; a plurality of first via-hole wiring (23,25,27,29) connect each of the power supply wiring layers in the first group to a corresponding one of the power supply wiring layers in the second group; and a plurality of second via-hole wirings (22,24,26,28) connect said terminals (20) to said power supply wiring layers in said first group (11); said signal wiring layer section (2) comprises a plurality of thin film signal wiring layers (41,42,43), a plurality of third insulating layers (51,52,53) for insulating the signal wiring layers, and a plurality of third via-hole wirings (61,62,63) for connecting said signal wiring layers to each other, to form a plurality of internal wirings each having one end (44) exposed on a top surface of the signal wiring layer section and the other end (41) connected to one of said second power supply wiring layers (12). A multilayer wiring substrate as claimed in Claim 1, in which the number of said first via-hole wirings connecting one of said power supply wiring layers inthe first group to a corresponding one of said power supply wirig layers in the second group is determined depending on a direct current resistance value required for the corresponding power supply wiring layer. A multilayer wiring substrate as claimed in Claim 1 or 2, in which each of said third insulating layers is made of polyimide. The multilayer wiring substrate as claimed in Claim 3, in which each of said third via-hole wirings is made of a material including a mixture of gold and polyimide.

Inventors: INOUE, TATSUO
Applicants: NEC CORPORATION
Application year: 1985
Main classification: H01L23
IPC codes: H01L23, H05K3