SECURITY DEVICE FOR THE SECURE STORAGE OF SENSITIVE DATA

Abstract: A device (11) for protecting stored sensitive data includes ceramic housing (17) which is formed of six parts (P1-P6) connected together and which contains a resettable shift register memory (79) storing sensitive data. On each part (P1-P6) is provided a pair of conductive path portions (L1, L2) disposed in superposed relationship and having complementary zig-zag configurations. The conductive path portions on the parts (P1-P6) are interconnected to form first and second conductive paths (WM1, WM2). Interruption of either conductive path (WM1, WM2) by an attempt to break into the housing (17) causes a reset signal generator (107) to provide a reset signal to erase the contents of the memory (79). A temperature sensor circuit (109) responsive to the temperature in the housing (17) falling below a predetermined level also causes the reset signal generator (107) to provide a reset signal for the memory (79).

Description: SECURITY DEVICE FOR THE SECURE STORAGE OF SENSITIVE DATA Technical Field This invention relates to security devices for protecting stored sensitive data, of the kind including a closed housing containing memory means adapted to store sensitive data, wherein said housing embodies conductive path means the interruption of which, brought about by an attempt to penetrate said housing, causes the erasure of the contents of said memory means. Background Art International Patent Application No. WO 84/04614 discloses a data security device which includes a container formed of a brittle material such as prestressed glass and which includes a data processor, a volatile CMOS RAM memory device for storing encryption key data, and a battery ' forming the power supply for the memory device. The container consists of a housing and a lid. The battery is connected to the memory device by a power supply conductor formed in a winding path configuration on the interior surfaces of the housing and the lid, the parts of the power supply conductor on the housing and lid being connected by pairs of contacts at the joint faces between the housing and the lid. The conductor is formed by an evaporated metal thin film material. The power supply conductor pattern is bifilar and thej parts of the conductor are interleaved with additional conductors on the interior surfaces of the housing and lid which are earthed or connected to a voltage source. Thus, if the power supply conductor is interrupted or connected to either of the additional conductors the power supply to the volatile RAM would be so much altered that the data in the RAM would be destroyed. The known device has the disadvantage of a relatively low level of security since the width of the power supply conductor provided on the housing must be maintained sufficiently great to enable the provision of an adequate power supply to the memory device. Such relatively wide conductors are subject to the possibility of penetration. For example, it could be possible to produce a hole of sufficiently small diameter to maintain a conductive path in a relatively wide power supply conductor, yet enable unauthorized access to the memory device via the hole. Furthermore, the thin film technology utilized in the manufacture of the known device results in high device cost. German Offenlegungsschrift No. 3023427 discloses a data storage unit which includes a plurality of memory devices within a closed container formed by a housing and a lid. Located within the material forming the walls of the container are a plurality of differential pressure sensing devices connected to closed channels also located in the walls of the container, such that any attempt to break into the container which disrupts the pressure in the closed channels is detected by the pressure sensing devices and causes the operation of a relay to provide an erase signal to erase the contents of the memory devices. Also located within the material forming the walls of the container are a pair of thin conductors, which run in an arbitrary configuration through the housing and the lid, and are connected to a power source and the relay. Any external influence which breaks either of these thin conductors also causes th^ relay to provide an erase signal to erase the contents of the memory devices. However, this known device is of complex and expensive construction resulting from the provision of the closed channels and pressure sensing devices. Furthermore, the possibility exists of forming a small diameter hole. into the interior of the unit without interrupting either of the pair of thin conductors. Thus, the degree of security achievable with his known unit is also limited. Disclosure of the Invention It is an object of the present invention to provide a security device for protecting stored sensitive data having a high degree of security against unauthorized access. Therefore, according to the present invention, there is provided a security device for protecting stored sensitive data, of the kind specified, characterized in that said conductive path means includes first and second conductive paths, in that said housing contains tamper detection circuitry coupled to said first and second conductive paths, said tamper detection circuitry including reset signal generating means, and in that the interruption of either of said first and second conductive paths causes said reset signal generating means to produce a reset signal to erase the contents of said memory means. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is an illustration of the assembled device or module of the invention; Fig. 2 is an exploded perspective view of the various parts of the housing of the device of Fig. 1? Figs. 3A, 3A1, 3B, 3B1, 3B2, 3C, 3C1, 3C2 and 3D are exemplary illustrations of how three conductive layers separated by two insulating layers are selectively deposited on a ceramic substrate and connected together to form any one of the parts P1-P6 of Fig. 2; Fig. 4 is a partial sectional view of the housing 17 of Fig. 1; Figs. 5A and 5B together show the islands and conductive paths in conductive layer 3 for each of the parts shown in Fig. 2; Figs. 6A and 6B together show the conductive paths in conductive layer 2 for each of the parts shown in Fig. 2; Figs. 7A and 7B together show the conductive paths in conductive layer 1 for each of the parts shown in Fig. 2; Fig. 8 shows the connections of the conductive paths in Figs. 7A and 7B by way of pre¬ selected connections and islands in Figs. 5A and 5B to form a first conductive path designated as WM1, and further shows the connections of the conductive paths in Figs. 6A and 6B by way of preselected connections and islands in Figs. 5A and 5B to form a second con¬ ductive path designated as WM2; Fig. 9 is a schematic block diagram of the electronic circuitry contained within the device of Fig. 1; Fig. 10 is a functional block diagram illustrating how the key storage key (KSK) is generat¬ ed and how the KSK is utilized in loading KEYS and in encrypting and decrypting data; and Fig. 11 is a schematic block diagram of the tamper detection circuitry of Fig. 9. Best Mode for Carrying Out the Invention Referring now to the drawings. Fig. 1 illustrates an exemplary form of a security device 11 of the invention. A plurality of conductors 12 con¬ nected to a plurality of pins 13 are shown on both sides of a bottom part P6 of a housing 17 of the device 11 for connecting the device 11 to external electronic equipment (not shown). The housing 17 is preferably comprised of ceramic, since a ceramic housing cannot be penetrated by chemicals due to the fact ceramic will not dissolve. An exploded perspective view of the various parts of the housing 17 of the device 11 is illustrat¬ ed in Fig. 2. As shown, the housing 17 is comprised of a top part or cover PI, side parts P2 through P5 and a bottom part P6. Coupled to the bottom part P6 by way of surface mounting pins (not shown) is elec¬ tronic circuitry 19 which is encased within the hous¬ ing 17 for security and protection. Each of the parts P1-P6 is comprised of a ceramic substrate having three conductive layers separated by two nonconductive or insulating layers, with all layers being deposited on the ceramic sub¬ strate by a conventional screening technique using conventional thick film techniques. Figs. 3A, 3A1, 3B, 3B1, 3B2, 3C, 3C1, 3C2 and 3D illustrate how three conductive layers separated by two insulating layers are selectively deposited on a ceramic substrate and connected together to form any one of the parts P1-P6. Screens (Figs. 3A1, 3B1, 3B2, 3C1 and 3C2) with very small holes (where the diameter of a hole may be equal to approximately 300 micrometers) are used to deposit conductive or insulating paste on a ceramic substrate 20 (Fig. 3D). For every conductive layer and insulating layer a different screen is prepared. After each screening the layered ceramic part 20 is heated up to 800 degrees centigrade to harden the just deposited paste. Fig. 3A illustrates the first conductive layer LI to be deposited on the ceramic substrate 20. As shown in Fig. 3A, LI is comprised of one track 21. Fig. 3A1 illustrates the screen that is placed on the ceramic substrate 20 and used to deposit the layer LI on the ceramic substrate 20. The screen of Fig. 3A1 is the negative of the required layer LI. The shaded area 22 in Fig. 3A1 is blocked off with a polymer (not shown) so that a conductive paste (not shown) can only pass through an open area 21χ to form the track 21 of the layer LI on the ceramic substrate 20. Layer LI is then hardened at 800 degrees centigrade in an oven. The thickness of the track 21 of layer LI is about 10 micrometers. Points or areas 1.1, 1.2 and 1.3 on layer LI of Fig. 3A are then blocked off with a polymer at the respective hole positions 30, 29 and 28 of the screen shown in Fig. 3B1, because these areas have to be selectively connected later to subsequently laid conductive layers {L2 and L3). Insulating paste is now screened over the assembly of Fig. 3A to form an insulating layer one (Fig. 3B1) and the now insulated assembly of Fig. 3A is heated up again to 800 degrees centigrade to harden it. Fig. 3B illustrates the second conductive layer (L2) to be deposited on the hardened assembly of Fig. 3A by using the screen shown in Fig. 3B2. As shown in Fig. 3B layer L2 is comprised of two tracks 23 and 24. The screen of Fig. 3B2 is the negative of the pattern of Fig. 3B. The shaded area 25 of Fig. 3B2 is blocked off again with a polymer. After screening with conductive paste through open areas 23χ and 24ι of the screen of Fig. 3B2 and heating the hardened assembly of Fig. 3B, connections are made between points 1.1 of Fig. 3A and 2.1 of Fig. 3B by way of hole 30 in insulating layer one of Fig. 3B1 and between points 1.2 of Fig. 3A and 2.2 of Fig. 3B by way of the hole 29 in insulating layer one of Fiq. 3B1. Note that the track 23 of Fig. 3B crosses over the track 21 of Fig. 3A. Insulating layer two (Fig. 3C1) is needed to enable the deposition of the third conductive layer L3. The laying of these two layers is accomplished by using the screens of Figs. 3C1 and 3C2 in a manner similar to that previously described with respect to Figs. 3B1 and 3B2. More specifically, hole positions 31, 32 and 33 of the screen shown in Fig. 3C1 are blocked off with a polymer before insulating layer two is deposited. When the polymer is removed from the insulating layer two (as is similarly done with insulating layer one), holes 31, 32 and 33 are left in the insulating layer two, as indicated in Fig. 3C1. The conducting layer L3 is laid or deposited through the screen shown in Fig. 3C2. After the insulating layer two and layer L3 are laid or deposited, the pattern of L3 results, as shown in Fig. 3C. As shown in Fig. 3C, L3 is comprised of two tracks 26 and 27 which are respectively connected to square islands 3.6 and 3.7. Island 3.6 in layer L3 of Fig. 3C is connected via point 3.3 in layer L3 of Fig. 3C to point 1.3 of LI in Fig. 3A through the hole 31 in insulating layer two and the hole 28 in insulating layer one. On the other hand, island 3.7 in layer L3 of Fig. 3C is connected via point 3.5 in layer L3 of Fig. 3C to point 2.5 in layer L2 of Fig. 3B by way of hole 33 in insulating layer two (Fig. 3C1). In addition, island 3.7 in layer L3 of Fig. 3C is also connected via point 3.4 in layer L3 to point 2.4 in layer L2 of Fig. 3B by way of hole 32 insulating layer two (Fig. 3C1). Fig. 3D illustrates a sectional view of connections between layers or tracks L3 and LI and between layers or tracks L2 and LI. The ceramic substrate 20 is approximately 700 micrometers thick and each of the conductive and insulating layers is only about 10 micrometers thick. The width of each of the tracks LI, L2 and L3 is about 300 micrometers. The conductive layers or tracks LI, L2 and L3 are selectively connected together at preselected islands or connection points. For example the point 3.5 and island 3.6 of conductive layer L3 of Fig. 3C are respectively connected to point 1.3 in conductive layer LI of Fig. 3A by means of conductive epoxy through the hole 33 (Fig. 3C1) and the holes 31 and 28 (Figs. 3C1 and 3B1), respectively. The assembly of Fig. 3D (comprised of the layers of Figs. 3C, 3C1, 3B, 3B1 and 3A) is then put into an oven (not shown) and heated to about 800 degrees C for the proper duration of time in order to harden the conductive layer 3 and the conductive epoxy. Referring now back to Fig. 2, the parts P1-P6 are assembled together into the housing 17 of Fig. 1 in the following manner. Initially the top part PI is sequentially glued to side parts P2-P5. First, ex¬ posed islands on part P2 are respectively electrically connected to associated exposed islands on part PI with conductive epoxy. In a similar manner, exposed islands on part P3 are respectively electrically connected to associated exposed islands on part PI with conductive epoxy; exposed islands on part P4 are respectively electrically connected to associated exposed islands on part PI with conductive epoxy; and exposed islands on part P5 are respectively electri¬ cally connected to associated exposed islands on part PI with conductive epoxy. Conductive epoxy is next placed on the remaining exposed islands on the assem¬ bly of parts P1-P5. Then the assembly of parts P1-P5 is properly oriented with respect to part P6 and gently placed onto part P6 to electrically connect the remaining islands on part P6 with the remaining uncon¬ nected islands on the assembly of parts P1-P5. After the assembly of parts P1-P6 is electrically connected together at associated islands to form the housing 17 (FIG. 1), as described above, nonconductive epoxy is applied along the lines between adjacent pairs of the parts P1-P6 to seal any gaps between adjacent pairs of the parts P1-P6 and to provide additional strength for the housing 17. Fig. 4 is a partial sectional view of the completed housing 17 showing the connection of an island 37 on layer 3 of part 2 (L3P2) with an island 39 on layer 3 of part 1 (L3P1) by means of conductive epoxy 35, and the further gluing of the parts PI and P2 together with nonconductive epoxy 41. An additional layer of ceramic (not shown) is mounted onto the bottom part P6 to hold the electronic circuitry 19. The electronic circuitry 19 is then mounted onto this additional layer of ceramic by way of surface mounting pins (not shown). Any necessary contacts between the conductive layer 3 and the elec¬ tronic circuitry 19 are connected together with sur¬ face mounting pins (not shown). Then the assembled structure of parts P1-P5 is glued to bottom part P6, with the associated exposed islands between the assem¬ bly of parts P1-P5 and the bottom part P6 being con¬ nected together with conductive epoxy before the entire assembly of parts P1-P6 is sealed all over with nonconductive epoxy, as discussed before. As men¬ tioned before, the plurality of leads 12 and plurality of contacts 13 (shown in Fig. 1) are all on part P6. The formation of first and second continuous conductive paths WM1 (wire mesh 1) and WM2 (wire mesh 2) through the parts P1-P6 of the ceramic housing 17 (Fig. 1), as shown in Fig. 8 (as well as in Figs. 9 and 11), will be explained by now referring to Figs. 5A, 5B, 6A, 6B, 7A, 7B and 8. Figs. 5A and 5B together show the islands and conductive paths in conductive layer 3 (L3) for each of the parts P1-P6 shown in Fig. 2. The Figs. 6A and 6B together show the conductive paths in conductive layer 2 (L2) for each of the parts P1-P6 shown in Fig. 2. Similarly, Figs. 7 A and 7B together show the conductive paths in conductive layer 1 (LI) for each of the parts P1-P6 shown in Fig. 2. It will be appreciated that on each part P1-P6 the conductive path in each of the layers LI and L2 is disposed in a winding or zig-zag configuration over substantially the entire surface of the parts P1-P6. Finally, Fig. 8 shows the connections of the conductive paths in Figs. 7A and 7B by way of preselected connections and islands in Figs. 5A and 5B to form the first continuous conductive path WM1 and also shows the connections of the conductive paths in Figs. 6A and 6B by way of preselected connections and islands in Figs. 5A and 5B to form the second continuous conductive path WM2. As shown in Figs. 5A and 8, pins A and C are respectively the input and output pins of WM2. Simi¬ larly, pins B and D are respectively the input and output pins of WM1. These pins A, B, C and D are internally connected to leads (not shown) which are coupled through surface mounting pins (not shown) to the group of pins 13 (Fig. 1). The alphanumerically identified squares in Figs. 5 A and 5B (such as BD1 in Fig. 5A) represent islands to be connected, while the alphanumerically identified circles in Figs. 5A, 5B, 6A, 6B, 7A and 7B (such as AC1 in Fig. 5A) represent connection points. By using Fig. 8 as a guide it can be readily seen in Figs. 5A, 5B, 7A and 7B that the line BD (or continuous conductive path WM1) from pin B (Fig. 5A) to pin D (Fig. 5A) sequentially passes through a zig¬ zag conductive path through the conductive layers L1P2 (Fig. 7B), L1P3 (Fig. 7B) , L1P1 (Fig. 7B) , L1P5 (Fig. 7B), L1P4 (Fig. 7B) and L1P6 (Fig. 7A) via the islands and connection points BD1-BD30 and lines 43-47. Similarly, by using Fig. 8 as a guide, it can be readily seen in Figs. 5A, 5B, 6A and 6B that the line AC (or continuous conductive path WM2) from pin A (Fig. 5A) to pin C (Fig. 5A) sequentially passes through a zig-zag conductive path through the conduc¬ tive layers L2P6 (Fig. 6A) , L2P4 (Fig. 6B) , L2P5 (Fig. 6B), L2P1 (Fig. 6B), L2P3 (Fig. 6B) and L2P2 (Fig. 6B) via the islands and connection points AC1-AC39 and lines 51-64. Furthermore, the zig-zag paths of the wire meshes WMl and WM2 are disposed in complementary fashion on each of the parts PI to Pδ. For example, referring to Fig. 4, the conductive path portions of the layer L2P1 overlie the spaces between the conductive path portions of the layers L1P1, and the spaces between the conductive path portions of the layer L2P1 overlie the conductive path portions of the layer L1P1. Referring to Fig. 9, the electronic circuitry 19 of Fig. 2 will now be discussed in more detail. The electronic circuitry 19 includes data processing circuitry 67 and tamper detection circuitry 69. The data processing circuitry 67 can be utilized to perform any desired data processing opera¬ tion in such applications as, for example, electronic payment systems, electronic fund transfers, data encryption/decryption, PIN (personal identification number) verification, data transmission/reception, access control and home banking. The data processing circuitry 67 includes a processor 71 for selectively controlling the operation of the electronic circuitry 19 in response to input data and instructions, a timing and control circuit 73 for controlling the operation of the processor 71, a programmable read only memory (PROM) 75 for storing the software program to be executed by the processor 71, a random access memory (RAM) 77 for providing a temporary memory storage, a volatile or resettable 64 bit shift register memory 79 for permanently storing the most sensitive or secure data such as a key storage key (KSK) (to be explained), a random number generator 81 and an input/output (I/O) unit 83. A data, control and address bus 85, bidirectional I/O bus 87 and I/O lines 89 and 91 are coupled to the processor 71, timing and control cir- - 12 - cuit 73, PROM 75, RAM 77 and I/O unit 83 to enable the data processing circuitry 67 to perform its data processing operations. Data may be passed over bi¬ directional I/O bus 87 to or from the processor 71 and over I/O lines 89 and 91 to or from the I/O unit 83. The right-hand ends of the I/O bus 87 and I/O lines 89 and 91 (as shown in Fig. 9) may be selectively coupled to, for example, another data processor (not shown), a main computer (not shown) and a peripheral (such as a keyboard) (not shown) via the pins 13 (Fig. 1) in order to enable the data processing circuitry 67 to perform its preselected operations. Power to operate the electronic circuitry 19 is preferably supplied from external power sources (not shown), such as power supplies and batteries, connected to preselected ones of the pins 13 (Fig. 1). An initialization subroutine, contained in the software program stored in the PROM 75, is execut¬ ed in a special mode of operation controlled by an authorized person. Preferably, this initialization subroutine can only be executed once after the securi¬ ty device 11 (Fig. 1) has been completely assembled. For purposes of additional security it is preferable that the volatile memory 79 be, for exam¬ ple, a resettable memory such as a 64-bit shift regis¬ ter memory. During the execution of an INITIALIZE subroutine the processor 71 applies an INITIALIZE signal to the random number generator 81 to enable the generator 81 to generate a random number which is stored in the memory 79 as an exemplary sequence of 64 random bits. This sequence of 64 random bits is the KSK (key storage key), which is the most sensitive or secure data contained in the data processing circuitry 67. Referring to the functional block diagram of Fig. 10, it will now be explained how the sensitive KSK data is generated and then utilized by the data proc- essing circuitry 67 in the loading or storage of subsequently entered KEYS and in all subsequent en¬ cryption and decryption operations of output and input data, respectively. INITIALIZE KSK In response to the INITIALIZE signal from the processor 71, the random number generator 81 generates the random 64-bit KSK. This KSK is then permanently stored in the resettable shift register memory 79. The invention prevents this KSK from being externally accessed. LOAD KEYS After KSK has been generated, a person can store 64-bit KEYS in the RAM 77. Each KEY to be entered is an exemplary sequence of 64 bits of clear data (hereinafter designated as KEY CLEAR) that can be entered into the data processing circuitry 67 by way of, for example, a keyboard (not shown) connected to pins 13 (Fig. 1). For added security each KE x CLEAR is encrypted with KSK by exclusive-ORing them together in an exclusive-OR (EX-OR) gate 93 to develop a KEYx ENCR signal that is also 64 bits in length. This KEY ENCR signal is then stored in the RAM 77. ENCRYPT/DECRYPT DATA To encrypt outgoing clear data or decrypt incoming encrypted data, a desired KEYx ENCR signal is extracted from the RAM 77 while the KSK is extracted from the resettable shift register 79 by well-rknown read-out techniques. The EYx ENCR signal and the KSK are then exclusive-ORed together in an EX-OR gate 95 to recover the associated KEY CLEAR signal. In a data encryption operation, the KEY CLEAR signal is routed to a data encryption device 97 where it is used to encrypt clear data entered into the data processing circuitry 67 (Fig. 9) by way of one of the I/O buses 87, 89 and 91. Encrypted data from the device 97 is then outputted from the security device 11 (Fig. 1) by way of the pins 13 (Fig. 1). In a data decryption operation, encrypted data entered into the data processing circuitry 67 (Fig. 9) by way of the pins 13 (Fig. 1) is applied to a data decryption device 99. The KEYx CLEAR signal, which is routed from the EX-OR gate 95 to the data decryption device 99, is used by the data decryption device 99 to develop clear data which can then be utilized by the data processing circuit 67. The EX-OR gates 93 and 95, the data encryption device 97 and the data decryption device 99 can be implemented in hardware or the operations performed by those units can be performed as a func¬ tion of software subroutines of the program contained in the PROM 75. Referring back to Fig. 9, it should be noted that the above-described implementation for generating the KSK is for illustrative purposes only and does not form any part of the invention. Any other suitable implementation could therefore be used to generate the KSK. The important things to consider are that the resettable memory 79 stores the KSK, that the contents of the memory 79 cannot be altered, (if the security device 11 was programmed to run the initialization program only once) , that the KSK is never outputted to the outside world from the security device 11, and that for purposes of security external access to the KSK contents of the memory 79 by various means must be prevented. Tamper detection circuitry 69 is included in the electronic circuitry 19 to specifically actively destroy the KSK in the resettable memory 79 if there is any attempt to penetrate the ceramic housing 17 to * gain access to the KSK stored in the memory 79. It should be realized that if the KSK is destroyed, any data stored in RAM 77 becomes meaningless or useless. Two principal ways that someone could employ to at¬ tempt to gain access to the KSK stored in the reset¬ table memory 79, as well as the reaction of the tamper detection circuitry 69 to such attempts, are discussed below. ATTEMPT TO BREAK INTO HOUSING 17 An attempt to penetrate the ceramic housing 17 may be made by drilling into or cracking the hous¬ ing 17. To protect against this possibility, wire mesh 2 (WM2) of Fig. 8 is connected between a supply voltage V- and a sense circuit 101, while wire mesh 1 (WMl) of Fig. 8 is connected between a reference potential such as ground and a sense circuit 103. It will be recalled that WMl and WM2 are different con¬ ductive paths on different levels or layers of each of the parts P1-P6 of the housing 17, as shown in Figs. 1-8. An attempt to drill into or crack the housing 17 that damages either or both of WMl and WM2 will be readily sensed. If WM2 is broken or shorted to either WMl or ground by such an attempt, sense circuit 101 will generate a low voltage signal at point 105. Similarly, if WMl is broken or shorted to either WM2 or ~ 7Q by such an attempt, the sense circuit will generate a low voltage signal at point 105. In re¬ sponse to a low voltage signal at point 105, a low voltage detector 107 generates a RESET signal which resets the memory 79 to actively clear or destroy the KSK in the resettable memory 79. ATTEMPT TO FREEZE KSK CONTENT OF MEMORY 79 BEFORE BREAKING INTO HOUSING 17 It is known that it is possible to retain data in static CMOS cells of a memory in an unpowered state (no supply voltage or battery voltage present), if those cells are initially frozen below -90 degrees centigrade before power is removed from the memory. A low temperature sensor 109 is therefore needed in the tamper detection circuitry 69 to protect the security device 11 (Fig. 1) against the above- described tampering at extremely low temperatures. The sensor 109 is also connected to point 105. Sensor 109 is so implemented that when the temperature within the housing 17 (Fig. 1) falls to, for example, -25 degrees centigrade, the sensor 109 generates and applies a low voltage signal to point 105. This low voltage signal applied from sensor 109 to point 105 will also cause the low voltage detector 107 to gener¬ ate a RESET signal to reset the memory 79 to actively clear or destroy the KSK in the memory 79. Referring now to Fig. 11, the tamper detection circuitry 69 will be described in more detail. The tamper detection circuitry 69 is essentially comprised of four parts. A first part includes WM2 and sense circuit 101. A second part includes WMl and sense circuit 103. A third part includes the low temperature sensor 109. All of the first, second and third parts are connected to a common output at point 105 which, in turn, is connect¬ ed to the fourth part which includes the low voltage detector 107. Consequently, if any of the first, second or third parts detects any attempt to gain access to the KSK in memory 79 (Fig. 9) a low output is developed at point 105. As mentioned before, such a low output at point 105 will cause the low voltage detector 107 to actively reset the memory 79 to de¬ stroy the KSK stored therein. In the first part, pin C of WM2 is coupled to sense circuit 101. A high or positive supply voltage Vc is applied to pin A of WM2 and to each of cascaded inverters 111 and 113 in sense circuit 101. For purposes of this discussion assume that ~ 7r- = +4.5 volts. A one megohm (1M T-) resistor 115 is connected between pin C of WM2 and a low reference potential such as ground. Pin C is also connected to the input of inverter 111. The output of inverter 113 is ap¬ plied through a 120 kilohm resistor 117 to point 105. When WM2 is undamaged (not broken or shorted to either ground or WMl), the input to inverter 111 is high, the output of inverter 111 is low and the output of inverter 113 is high. In the second part, pin D of WMl is coupled to sense circuit 103 and pin B of WMl is connected to the low reference potential or ground. A one megohm resistor 119 is connected between pin D of WMl and Vr- . The supply voltage Vc is also applied to cascaded inverters 121, 123 and 125. Pin D is also connected to the input of inverter 121 which, in turn, has its output connected to the input of inverter 123. The output of inverter 123 is then connected to the input of inverter 125. The output of inverter 125 is ap¬ plied through a 120 kilohm resistor 127 to point 105. A 30 kilohm resistor 129 is connected between point 105 and ground to develop a common output for the sense circuits 101 and 103, as well as to the low temperature sensor 109 (to be explained). When WMl is undamaged (not broken or shorted to either V^ or WM2), the input to inverter 121 is high, the output of inverter 123 is low and the output of inverter 125 is high. Part 3 includes the low temperature sensor 109 (Fig. 9). The low temperature sensor 109 compris¬ es: a negative temperature coefficient (NTC) bridge circuit 131 which includes serially-connected resis- tors 133 and 134 respectively coupled between V- and ground, and serially-connected resistors 135 and 136 respectively coupled between ~ IQ and ground; an opera¬ tional amplifier 137 having its non-inverting input (+) connected to the junction of resistors 133 and 134 and its inverting input (-).connected to the junction of resistors 135 and 136; an inverter 139 for invert¬ ing the output of the operational amplifier 137; and a diode coupled between the output of inverter 139 and point 105. The resistors 133 and 136 may be 800 kilohm resistors, while the resistors 134 and 135 may be 68 kilohm resistors having negative temperature coeffi¬ cients (NTC) . With this implementation the bridge circuit 131 would be unbalanced until the temperature inside the housing 17 reaches approximately -25 de¬ grees C. It can be readily seen that when the bridge circuit 131 is unbalanced, the operational amplifier 137 develops a low output which is inverted by inver¬ ter 139 to backbias the diode 141. Therefore, when the temperature inside the housing 17 (Fig. 1) is above -25 degrees centigrade, the low temperature sensor 109 is effectively disconnected by the back- biased diode 141 from the point 105. Part 4 includes a low voltage detector 107 connected to point 105 for developing a RESET signal when the potential across resistor 129 is below a preselected threshold voltage of, for example, +1.15 volts when Vc = +4.5 volts), and a capacitor 145 connected between point 105 and ground for retaining the input potential (voltage developed across resistor 129) to the detector 107 for a sufficient time to enable the detector 107 to generate a RESET signal when the potential across resistor 129 falls below +1.15 volts. The low voltage detector 107 may be a voltage comparator which develops a low output when the voltage across resistor 129 falls below an internal reference potential of +1.15 volts. Various conditions will now be discussed. NO ATTEMPT MADE TO GAIN ACCESS TO KSK When no attempt has been made to freeze and/or penetrate the housing 17 to gain access to the KSK in the resettable memory 79 (Fig. 9) the tempera¬ ture in the housing 17 (Fig. 1) will be high enough not to trigger the low temperature sensor 109 and both WMl and WM2 will be undamaged. As a result, the outputs of inverters 113 and 125 will both be high. Therefore, the voltage developed across resistor 129 (approximately +1.5 volts) will be above the 1.15 volt threshold of the low voltage detector 107. Conse¬ quently, the low voltage detector 107 will not develop the RESET signal. ATTEMPTED PENETRATION OF HOUSING 17 BREAKS WM2 OR SHORTS WM2 EITHER TO GROUND OR WMl When WM2 is broken or shorted either to • ground or WMl, pin C goes to a low potential, causing the input to inverter 111 to go low. This low input is inverted to a high signal by inverter 111. The high signal (+4.5 volts) from inverter 111 is inverted by inverter 113 to a low signal (0 volts). Assume that WMl is not broken at this time and therefore that inverter 125 develops a high output (+4.5 volts). As a result, a voltage divider comprised of resistors 117, 127 and 129 will cause point 105 to fall to approximately +0.9 volts. Since +0.9 volts is below the +1.15 volt threshold of the low voltage detector 107, the low voltage detector 107 will develop the RESET signal to actively reset memory 79 (Fig. 9). ATTEMPTED PENETRATION OF HOUSING 17 BREAKS WMl OR SHORTS WMl EITHER TO V c OR WM2 When WMl is broken or shorted either to Vc or WM2, pin D goes high (+4.5V). This high signal is inverted by inverter 121. The low signal (0 volts) from inverter 121 is inverted by inverter 123. The high signal from inverter 123 is inverted by inverter 125. Assume that WM2 is not broken at this time and therefore that inverter 113 develops a high output (+4.5 volts). As a result, the voltage divider com¬ prised of resistors 117, 127 and 129 will cause point 105 to fall to approximately +0.9 volts. This will then cause the low voltage detector 107 to develop the RESET signal to reset memory 79 (Fig. 9). If both WMl and WM2 are broken, the inverters 113 and 125 will both go low, causing the charge across capacitor 145 to fall toward 0 volts. However, as soon as the voltage across capacitor 145 falls below +1.15 volts, the low voltage detector 107 will generate the RESET signal. V C FALLS BELOW +3.5 VOLTS If Vc falls below +3.5 volts, the voltage across capacitor 145 will fall below +1.15 volts. This again will cause the low voltage detector 107 to generate the RESET signal. TEMPERATURE IN HOUSING 17 FALLS BELOW -25 DEGREES CENTIGRADE When the temperature in the housing falls below -25 degrees centigrade, the bridge circuit 131 in the low temperature sensor 109 becomes either balanced or unbalanced in the opposite direction. In either event, the operational amplifier 137 develops a high output which is inverted by inverte.r 139. The low output (0 volts) from inverter 139 forward biases diode 141 causing point 105 to fall toward 0 volts. This will cause the charge across capacitor 145 to fall toward 0 volts. However, as soon as the voltage across capacitor 145 falls below +1.15 volts, the low voltage detector 107 generates the RESET signal to clear the memory 79. The invention thus provides a security device 11 for the secure storage of sensitive data. It provides protection for the device 11 against chemical attack, physical attack, and tampering at extremely low temperature. The ceramic housing cannot be pene¬ trated by chemicals, since ceramics will not dissolve. Physical attack by cutting or drilling will result in the ceramic housing 17 cracking or breaking, thus breaking or damaging at least one of the two conduc¬ tive paths WMl and WM2. This will cause the tamper detection circuitry 69 to actively reset the "reset¬ table memory 79 to destroy the sensitive data stored therein. Similarly, any attempt to tamper with the security device 11 at an extremely low temperature will also cause the tamper detection circuitry 69 to actively reset the memory 79.

Claims: CLAIMS 1. A security device for protecting stored sensitive data, including a closed housing (17) containing memory means (79) adapted to store sensitive data, wherein said housing (17) embodies conductive path means (WMl, WM2) the interruption of which, brought about by an attempt to penetrate said housing (17), causes the erasure of the contents of said memory means (79), characterized in that said conductive path means includes first (WMl) and second (WM2) .conductive paths, in that said housing (17) contains tamper detection circuitry (69) coupled to said first and second conductive paths (WMl, WM2), said tamper detection circuitry (69) including reset signal generating means (107), and in that the interruption of either of said first and second conductive paths (WMl, WM2) causes said reset signal generating means (107) to produce a reset signal to erase the contents of said memory means (79). 2. .A security device according to claim 1, characterized in that said first and second conductive paths (WMl, WM2) are disposed in respective first and second superposed layers (LI, L2). 3. A security device according to claim 2, characterized in that said housing includes a plurality of individual parts (P1-P6) connected together, each of said parts (P1-P6) including a substrate having a first conductive path portion (e.g. L1P1) provided thereon, an insulating layer overlying said first conductive path portion (e.g. L1P1) and a second conductive path portion (e.g. L2P1) overlying said insulating layer, and in that said first conductive path (WMl) includes a series connection of said first conductive path portions (e.g. L1P1) and said second conductive path (WM2) includes a series connection of said second conductive path portions (e.g. L2P1). 4. A security device according to claim 3, characterized in that said first and second conductive path portions (e.g. L1P1 and L2P1) are disposed in complementary winding paths on each of said individual parts (e.g. PI) . 5. A security device according to claim 4, characterized in that said first conductive path (WMl) is coupled to a first sensing circuit (103) responsive to interruption of said first conductive path (WMl) to develop a first sensing signal, in that said second conductive path (WM2) is coupled to a second sensing circuit (101) responsive to interruption of said second conductive path (WM2) to develop a second sensing signal, and in that said first and second sensing circuits (103, 101) are coupled to said reset signal generating means (107) which is adapted to generate said reset signal in response to the provision of said first or second sensing signals. 6. A security device according to claim 5, characterized in that said tamper detection circuitry (69) includes temperature sensing means (109) coupled to said reset signal generating means (107) and responsive to a decrease in temperature within said housing (17) below a predetermined level to provide a third sensing signal, said reset signal generating means (107) being further responsive to generate said reset signal in response to the provision of said third sensing signal. 7. A security device according to claim 6, characterized in that said temperature sensing means (109) includes a temperature sensitive bridge circuit (131) having a first operational state when the temperature within said housing (17) is at or above said predetermined level and a second operational state when the temperature within said housing (17) is below said predetermined level, and in that amplifier means (109) coupled to said temperature sensitive bridge circuit (131) and adapted to generate said third sensing signal in response to said second operational state. 8. A security device according to any one of the preceding claims, characterized in that said memory means includes a resettable shift register memory (79) .

Inventors: KLEIJNE THEODOOR ADRIAAN, KLEIJNE, THEODOOR, ADRIAAN
Applicants: NCR CO, NCR CORPORATION
Application year: 1985
Main classification: G06F1
IPC codes: G06F12, G06F21, G06K19