AUTOMATIC LEVEL CONTROL CIRCUIT FOR AN AD CONVERTER

Abstract: The invention relates to an automatic level control circuit comprising an analog-to-digital (AD) converter (4) for discri­ minating an input signal with respect to a plurality of reference levels to produce a decoded digital signal and an error digital signal, and a reference voltage generator (6) responsive to said decoded digital signal and said error digital signal for providing a reference voltage to said AD converter (4), said reference levels being controlled to optimum ones responsive to a variation in the level of said input signal. The circuit is practable and simple in construc­ tion.

Description: The present invention relates to an automatic level control circuit for an A/D converter and, more particularly, to an automatic level control circuit applicable to a demodulator of a multi-level quadrature amplitude modulation (QAM) system and others. The current trend in the art of microwave band digital communications is toward the use of a multi-level QAM system which enhances effective utilization of the limited frequency band. In such a communication system, an analog-to-digital (AD) converter at a receive terminal compares a demodulated baseband signal with a plurality of predetermined reference levels to thereby transform the baseband signal to two-level parallel digital signals. In this instance, the prerequisite is that the input level of the baseband signal to the AD converter is maintained constant relative to the reference levels despite possible changes in the receive level and those in the gain of a receive amplifier. The above prerequisite has heretofore been met by installing variable-gain amplifiers one before a QAM detector and the other after the QAM detector and controlling their gains by means of outputs of AD converters. The problem with the prior art implementation is that, as will also be discussed later in detail, the use of variable-gain amplifiers which are adapted for stabilization of signal level makes the circuit construction complicated and, thereby, brings about the need for extra steps and time for the adjustment of variable-gain amplifiers in the production line. In US-A-3,935,569 a digital coder is described subject to a compression law having multiple linear segments with slopes decreasing in geometrical progression having a ratio of 1/2, in which a chain of threshold detectors in a linear progression is used a first time to determine the number of the segment, then a second time to determine the position of the level on the segment. A voltage divider connected between a high point and a low point comprising a plurality of equal resistors provides a plurality of reference levels. Each threshold detector receives a corresponding reference level and an input signal and provides a corresponding output signal. It is therefore an object of the present invention to provide an automatic level control circuit which is practicable with a simple construction. This object is achieved by an automatic level control circuit comprising the features of claim 1. The present invention has the advantage that the reference levels assigned to the AD converter are controlled to optimum ones responsive to a fluctuation in the level of the input signal. The dependent claims are directed to preferred embodiments of the invention. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which: Fig. 1 is a block diagram showing a prior art 16-level QAM demodulator, which includes an automatic level control circuit. Fig. 2 is a discrimination domain map associated with a 4-level baseband signal; Fig. 3 is a block diagram of an automatic level control circuit for an AD converter embodying the present invention; Fig. 4 is a block diagram showing another embodiment of the present invention; and Figs. 5 and 6 are block diagrams representative of two different applications of the automatic level control circuit of the present invention to a 64-level QAM demodulator. Referring to Fig. 1 of the drawings, a prior art 16-level QAM (16 QAM) demodulator is shown. As shown, a received intermediate frequency (IF) signal is applied to a QAM detector 2 via a variable-gain amplifier 1a. The QAM detector 2 detects the IF signal by using reference signals which are shifted 90 degrees in phase relative to each other, thereby producing two parallel streams of demodulated signals. One of the demodulated signal streams is routed through an amplifier 3 to an AD converter 4a, and the other through a variable-gain amplifier 1b to an AD converter 4b. As shown in Fig. 2, each of the AD converters 4a and 4b is provided with four different error discrimination levels (dotted lines) and three different code discrimination levels (solid lines) in order to convert the input to three-bit outputs (X₁, X₂ and X₃). Among the outputs X₁ - X₃, the outputs X₁ and X₂ represent reproduced decoded outputs (DATA 11 and 12) associated with the detected baseband signal, while X₃ is an error output for determining a deviation of the input signal from a reference level. The first- and third-bit outputs X₁ and X₃ are applied to an Exclusive-OR (Ex-OR) gate 5a which provides a value X₄' as shown in Fig. 2 in response to the input signal level. Specifically, the value X₄' becomes a ZERO when the input signal level is higher than the reference level and a ONE when the former is lower than the latter. Similarly, the AD converter 4b provides the three-bit outputs Y₁, Y₂ and Y₃. The outputs Y₁ and Y₃ are applied to an Ex-OR gate 5b which provides a value Y₄' in response to the input signal level. By controlling the variable-gain amplifiers 1a and 1b by the outputs of the Ex-OR gates 5a and 5b via low-pass filters (LPF) 20a and 20b, respectively, it is possible to stabilize gain fluctuations common to the quadrature components, and gain fluctuations particular to the individual quadrature components which are attributable to variations in the circuit characteristics. The reference numeral 21 designates a carrier synchronizing circuit adapted to generate a reference signal for the QAM detector 2 responsive to the outputs X₁ and X₃ of the AD converter 4a and the outputs Y₁ and Y₃ of the AD converter 4b. The prior art system described above has the disadvantage that it cannot avoid a relatively complicated circuit arrangement due to the use of variable-gain amplifiers and, therefore, requires extra steps and time for adjusting the amplifiers in the production line. For details of such a prior art system, a reference may be made to European Patent Application Publication EP-A-0 120 416. Referring now to Fig. 3, an automatic level control circuit for an AD converter 4 embodying the present invention is shown. As shown, the circuit comprises an AD converter adapted to transform an input signal into 3-bit digital signals by multi-level discrimination, and a reference voltage generator 6 adapted to logically process the outputs of the AD converter 4. The outputs of the reference signal generator 6 are applied to the AD converter 4 to control reference levels which are assigned to the AD converter 4. In detail, the AD converter 4 includes seven comparators 13 to which the reference levels shown in Fig. 2 are assigned. An input signal 100 (baseband signal provided by QAM-detection of a 16-level QAM wave) is applied to an input terminal IN of the AD converter 4 and compared by the comparators 13 with the respective reference levels. The outputs of the comparators 13 are applied to a logic circuit 12 which then produces three-bit output signals X₁, X₂ and X₃. The reference levels, or voltages, associated with the respective comparators 13 are generated by dividing DC voltages applied to reference voltage terminals REF1 and REF2 of the AD converter 4 by means of a series connection of multiple voltage dividing resistors 14 and 14a. Among the outputs X₁ - X₃ of the AD converter 4, X₁ and X₃ are applied to an Ex-OR gate 5 which is included in the reference voltage generator 6. The output of the Ex-OR gate 5 is delivered to an inverter 7 whose output X₄' is coupled to an LPF 8. The LPF 8 separates a DC component from the input and applies it to a polarity converter 9 with the result that the DC component is transformed into two reference voltages 101 and 102 which are the same in level but opposite in polarity. The reference voltages 101 and 102 respectively are coupled to the reference voltage terminals REF1 and REF2 of the AD converter 4. In the construction described above, the output X₄' of the inverter 7 becomes a ONE when the level of the input signal 100 has fluctuated to a level higher than the reference level and becomes a ZERO when it has fluctuated to a level lower than the reference level. The positive and negative reference voltages applied to the AD converter 4 increase responsive to a turn of the signal X₄' to a ONE so as to increase the distance between each adjacent reference levels (although the center reference level is unchanged), while decreasing it responsive to a turn of the signal X₄' to a ZERO. This allows the distance between the input level and each reference level to be successfully controlled to an optimum one. Referring to Fig. 4, another embodiment of the present invention is shown. In this particular embodiment, the automatic level control circuit comprises the AD converter 4, a reference voltage generator 6a, a subtractor 11 for applying subtraction to the input signal 100, an LPF 10, and an amplifier 15. In Fig. 4, the reference voltage generator 6a uses an inverting amplifier 9a in place of the polarity converter 9 of Fig. 3 so that a negative reference voltage 103 is applied to the reference voltage terminal REF2 of the AD converter 4. The other reference voltage terminal REF1 of the AD converter 4 is connected to ground via a protective resistor. In such a circuit arrangement, a change in the output of the reference voltage generator 6a causes not only the distance between adjacent reference levels but also the center reference level to change. To compensate for such an occurrence, the error signal X₃ output from AD converter 4 is routed to the subtractor 11 via the LPF 10 and amplifier 15. The circuit in accordance with this particular embodiment is capable of adjusting the distance between adjacent reference levels to an optimum one responsive to any fluctuation in the input level and, besides, coping with drifts of a DC component which is superposed on the input as well as DC drifts particular to the circuit. It should be noted that the DC component compensation circuitry inclusive of the subtractor 11 as shown in Fig. 4 is applicable in the same manner to the arrangement shown in Fig. 3. It should also be noted that the same circuit arrangement is applicable to input signals other than four-level signals. In an actual 16 QAM demodulator, the circuit of Fig. 3 or 4 will be directly connected to each of the output components of the QAM detector 2 of Fig. 1 Referring to Fig. 5, a 64 QAM demodulator is shown which is made up of a QAM detector 40, 4-bit AD converters 41 and 42, reference signal generators 43 and 44, and a carrier synchronizing circuit 45. The QAM detector 40 and the carrier synchronizing circuit 45 respectively are constructed in the same manner as the circuits 2 and 21 of Fig. 1, while the reference signal generator 43 or 44 is constructed in the same manner as the circuit 6 of Fig. 3 or the circuit 6a of Fig. 4. The QAM detector 40 is adapted to detect a 64 QAM signal output from the carrier synchronizing circuit 45 and, thereby, produce quadrature signals P and Q. The AD converter 41 converts the output P of the QAM detector 40 to 4-bit digital signals X₁ - X₄ responsive to reference voltages which are applied thereto from the reference signal generator 43. Among the signals X₁ - X₄, X₁ - X₃ are delivered as reproduced data DATA11 - DATA13, while the signal X₄ is applied to the reference signal generator 43 together with the signal X₁ to be processed in the same manner as in Fig. 3. Likewise, the AD converter 42 converts the output Q of the QAM detector 40 to 4-bit digital signals Y₁ - Y₄ responsive to reference voltages which are applied thereto from the reference signal generator 44. The signals Y₁ - Y₃ are delivered as reproduced data DATA21-23, while the signal Y₄ is applied to the reference signal generator 44 together with the signal Y₁. Referring to Fig. 6, another application of the present invention to a 64 QAM demodulator is shown. In Fig. 6, blocks 40, 42, 44 and 45 are the same as those blocks of Fig. 5 which are designated by like reference numerals, and blocks 1a, 5a and 20a those of Fig. 1. In Fig. 6, fixed voltages are coupled to the terminals REF1 and REF2 of the AD converter 46, while outputs of the reference signal generator 44 are coupled to those of the AD converter 42 as has been the case with the arrangement of Fig. 5. The automatic gain controlled (AGC) circuit 1a which is connected to an input terminal of the QAM detector 40 functions to compensate for the level difference between the outputs P and Q of the detector 40 only. Advantageous features of such a circuit arrangement will be more clearly understood when compared with the previously stated publication. In summary, it will be seen that the present invention provides an automatic level control circuit which is capable of optimumly controlling the reference levels of AD converters against fluctuations of input level without resorting to variable-gain amplifiers, thereby achieving a simple construction and promoting the ease of adjustment.

Claims: An automatic level control circuit comprising an analog-to-digital (AD) converter (4) for discriminating an input signal (IN) with respect to a plurality of reference levels to produce a decoded digital signal (X1, X2) and an error digital signal (X3) representing the deviation of the input signal from a reference level, said reference levels being generated by dividing a reference voltage (REF1, REF2), and a reference voltage generator (6; 6a) for providing said reference voltages to said AD converter characterized in that said reference voltage is responsive to a control signal ( X 4) which is derived from correlation between the decoded signal and the error digital signal so that each of said plurality of reference levels coincides with a corresponding level of input signal. An automatic level control circuit as claimed in claim 1, wherein said reference voltage generator (6; 6a) provides two reference voltages to said AD converter (4) and said reference levels being generated by dividing a difference between said two reference voltages (REF1, REF2). An automatic level control circuit as claimed in Claim 1 or 2, wherein said reference voltage generator (6) comprises an Exclusive-OR gate (5) responsive to said decoded digital signal and error digital signal, a lowpass filter (8) for smoothing the output of said Exclusive-OR gate, and a polarity converter (9) responsive to the output of said lowpass filter for providing said reference voltage. An automatic level control circuit as claimed in Claim 1 or 2, wherein said reference voltage generator (6a) comprises an Exclusive-OR gate (5) responsive to said decoded digital signal and error digital signal, a lowpass filter (8) for smoothing the output of said Exclusive-OR gate, and an amplifier (9a) responsive to the output of said lowpass filter for providing said reference voltage. An automatic level control circuit as claimed in any of claims 1 to 4, comprising a detector (40) for detecting a quadrature amplitude-modulated carrier wave and providing said input signal. An automatic level control circuit as claimed in any of claims 1 to 5, comprising means (10, 11, 15) for changing the level of said input signal in response to said error digital signal.

Inventors: YOSHIDA, YASUHARU
Applicants: NEC CORPORATION
Application year: 1985
Main classification: H03M1
IPC codes: H03G3, H03M1, H04L27