SEMICONDUCTOR MEMORY

Abstract: In a semiconductor memory comprising a plurality of row lines (X₁ to X m ), memory cells (M) driven by selecting a row line, sense amplifiers (7) connected to the memory cells via column lines (Y₁ to Y n ), and a column line voltage setting circuit (10) for setting predetermined voltage (V y ) on the column lines, the predetermined voltage defined by a function of activation voltage peculiar to semiconductor switch elements constituting the column line voltage setting circuit is made nearly equal to the threshold voltage of said sense amplifier. Thus, a high-speed, low power consumption semiconductor memory can be realized.

Description: BACKGROUND OF THE INVENTION In a ROM (Read Only Memory), switching devices such as MOS transistors are provided at intersections of row lines and column lines to store "1" or "0". As the integration density of such a ROM becomes higher, the impedances within the circuit and the parasitic capacitances also increase. Accordingly, it is difficult to attain a higher speed together with a lower power consumption. A high-speed readout technique for such a ROM was disclosed in Japanese Examined Patent Publication No. 46797/83 published on October 18, 1983, for example. In accordance with this disclosed technique, a MOS transistor for precharging a column (X) line is provided between the column line and the power supply. Upon change in the address signal, a precharge signal having a constant duration is applied to the gate of such a MOS transistor to precharge the column line at a high speed. In driving a row line, it is pulled up only by a MOS transistor of depletion type which has a high impedance and which always stays in the conduction state. Accordingly, the operation of the MOS transistor comprising a memory cell for discharging the electronic charge is not hampered. The maximum voltage on the column line of the above described prior art is the potential on the column (Y) line when row (X) lines which do not form memory cells are continuously selected. This voltage is nearly equal to the power supply voltage. And the lowest voltage on such a column (Y) line is low enough to be detected by a sense circuit. Since both precharge and discharge are monitored in the form of time, the voltage magnitude must have a sufficient allowance and it usually exceeds half of the power supply voltage. The voltage amplitude of the Y line is nearly half of the power supply voltage. A bipolar ROM employing a column line precharge circuit is disclosed in EP-A-0 102 485 from which the first part of claim 1 starts out. However, the precharge voltage and the threshold voltage of the sense amplifier of the described memory are influenced independently by manufacturing tolerances. This memory is therefore difficult to manufacture. MOS-read only memories employing precharge circuits are further disclosed in US-4 404 660, US-4 208 730, and US-4 318 014, wherein the latter document describes a memory in which only the selected column line is precharged. MOS-memories however are slower than bipolar memories. SUMMARY OF THE INVENTION It is therefore the object of the invention to provide a read only memory of high operating speed and low power consumption which is particularly reliable and easy to manufacture. This object is met by the invention defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a circuit diagram of an embodiment of the present invention. Fig. 2 shows the configuration of a column line voltage setting circuit shown in Fig. 1. Fig. 3 shows a time chart of the circuit illustrated in Fig. 1. Figs.4 and 5 show other embodiments of the column line voltage setting circuit. Figs. 6, 7 and 8 show embodiments of a sense amplifier. Figs. 9, 10, 11 and 12 show memory configuration diagrams and time charts of other embodiments. Fig. 13 shows an embodiment of a part of a memory illustrated in Fig. 11. Figs. 14 and 15 show memory configuration diagrams and time charts of another embodiment, respectively. Figs. 16, 17 and 18 show comparative examples of a sense amplifier and a column line voltage setting circuit. Fig. 19 shows an example of a memory using the sense amplifiers and column line voltage setting circuits illustrated in Figs. 16, 17 and 18. Fig. 20 shows a circuit diagram for illustrating another embodiment of the present invention. Fig. 21 shows waveforms appearing at various points of Fig. 20. Figs. 22 to 24 show circuit diagrams for illustrating other embodiments. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described by referring to Figs. 1 to 5. Fig. 1 shows the circuit configuration of a semiconductor memory which is an embodiment of the present invention. An X decoder 1 includes AND gates G₁ for producing X-line selection signals on the basis of an address signal ADR and a clock signal . An X driver 2 includes m NPN bipolar transistors Q₁ for driving row lines X₁ to X m with low impedance. The base, collector and emitter of the NPN transistor Q₁ are connected to an output of an AND gate G₁, the power supply potential V cc , and one of row lines X₁ to X m , respectively. An m-row, n-line memory cell matrix 3 includes NMOS transistors M constituting memory cells, row lines X₁ to X m , column lines Y₁ to Y n , resistors R₁ having high resistance values for discharging the leak electronic charge stored on the column lines Y₁ to Y n . The gate, drain and source of each memory cell M are connected to one of the row lines X₁ to X m , one of the column lines Y₁ to Y n , and the ground potential, respectively. In an X-line discharge circuit 4, electronic charges stored across parasitic capacitance of the row lines X₁ to X m are rapidly discharged through m MOS transistors M₁. A precharge circuit 5 includes a column line voltage setting circuit 10 for setting the column line setting voltage V y which is the operation voltage of the column lines Y₁ to Y n . The precharge circuit 5 further includes n NPN bipolar transistors Q₂ coupled to the column lines Y₁ to Y n in the emitter follower form. According to the output signal of the column line voltage setting circuit 10, the NPN bipolar transistors Q₂ rapidly charge the parasitic capacitance of the column lines Y₁ to Y n up to the column line setting voltage V y . In a Y selector 6, a Y-line signal from a Y decoder 11 selects a plurality of lines out of a group of column lines Y₁ to Y n via switching MOS transistors M₂. A sense amplifier 7 includes an NPN bipolar transistor Q₃ having an emitter coupled to the ground, resistors R₂, diodes D₁ and D₂, and a sense amplifier B₁. One sense amplifier 7 is connected to a plurality of column lines via MOS transistors M₂. Fig. 2 shows an embodiment of the column line voltage setting circuit 10 illustrated in Fig. 1. In Fig. 2, a P-type MOS transistor M p1 and an N-type MOS transistor M n1 supply base currents of all of the NPN transistors Q₂ which in turn supply the charging currents to the column lines. In addition, the MOS transistors M p1 and M n1 constitute an inverter gate. The circuit 10 is controlled by a clock signal . When assumes its L level, a bias current id₁ flows through the PMOS transistor M p1 and diodes D₃ and D₄. Then the base of each NPN transistor Q₂ is biased to approximately 2V BE which is twice the base-emitter voltage. Since the parasitic capacitance C yp1 of the column lines Y₁ to Y n is charged by emitter currents i y0 to i yn-1 of NPN transistors Q₂, which constitute emitter followers, up to the voltage of 1 V BE which is lower than the base voltage of the NPN transistor Q₂ by 1V BE . The voltage of 1V BE becomes the operation voltage of the column lines Y₁ to Y n . That is to say, the precharge circuit 5 forms a voltage supply having a low output impedance, and the column line voltage setting circuit 10 sets the voltage of the voltage supply to V BE . The sense amplifier 7 of Fig. 1 is a common emitter amplifier. A bias current is supplied to the base of each NPN transistor Q₃ through a resistor R₂ and a diode D₁. The base-emitter voltage V BE of the bipolar transistor Q₃ can then be expressed as where k is Boltzmann constant, T absolute temperature, I E emitter current, I ES reverse saturation current, and kT/q = V T is approximately 26 mV at room temperature. Assuming that the current amplification factor is β, the collector current I c can be related to the base current I B as I E ≃ I C = β I B . (2) The mutual conductance gm between the base-emitter voltage V BE and the collector current I c can be represented as Equation (1) can be rewritten as From the foregoing description, the base-emitter voltage V BE of the bipolar transistor generally assumes a value of 0.6 to 0.8 V and exhibits good uniformity on an LSI (large scale integrated circuit). For example, a change in the base-emitter voltage V BE corresponding to a change of 1 mA in the collector current i c is 25 mV. That is to say, the base-emitter voltage V BE exhibits good constant voltage characteristics. In other words, assuming that the current amplification factor β is 100, the above described change in the collector current I c and that in the base-emitter voltage V BE corresponds to a change of 10 µA in the base current I B . Accordingly, the bias current i b applied to the base of the NPN transistor Q₃ in the sense amplifier 7 produces the base-emitter voltage V BE to let flow the collector current i c . If the above described bias current i b is so chosen as to turn on the NPN transistor Q₃, the output data D out turns to its "L" level. If an X selector and Y selector are then activated to turn on a memory cell transistor M coupled to the sense amplifier 7, a part of the above described base bias current i b is diverted to the MOS transistor M of the memory cell. If the base current of the NPN transistor Q₃ in the sense amplifier 7 is thus reduced by 10 µA, for example, the collector current changes by 1 mA as evident from the foregoing description. As a result, the output D out of the sense amplifier turns to its "H" level. At this time, the change in the base-emitter voltage V BE is 25 mV, and the threshold voltage V st of the sense amplifier 7 can be said to be 1 V BE . The operation of the memory circuit illustrated in Figs. 1 and 2 will now be described by referring to Fig. 3. When the address signal ADR is applied to the memory circuit in synchronism with the clock Φ, the column line voltage setting circuit 10 is driven. That is to say, the PMOS transistor M p1 illustrated in Fig. 2 turns on. And the base voltage which has been adjusted to 2 V BE is applied to the base of the NPN transistor Q₂ included in the precharge circuit 5. As a result, the parasitic capacitance C yp of the Y line is charged up to the column line setting voltage V y = V BE . The potential at the column line rises as shown in Fig. 3(e). At the same time, the Y decoder output is issued as illustrated in Fig. 3(f). The MOS transistors M₂ for Y selector are turned on at the rate of one per group to directly couple the column lines Y₁ to Y n to the sense amplifiers 7. As described above, both the column line setting voltage V y and the threshold voltage V st are 1 V BE . Due to the difference between these two circuits in bias current, for example, however, a slight difference may be incurred between these two voltage values. When the MOS transistor M₂ for Y selector turns on, the charge current or the discharge current flows between the parasitic capacitance C py and the resistor R₂ of the sense amplifier 7 or the base of the NPN transistor Q₃, the differential voltage being eliminated. By the signal which appears during the "L" period of the clock Φ, an X-line drive signal WL, which is an AND signal of the X decoder output and , is sent out as illustrated in Fig. 3(c). Thus, only one of the row lines X₁ to X m is driven to its "H" level. If at this time a memory transistor M is present between the driven row line and the selected column line, the electronic charge of the column line is discharged through the MOS transistor M to lower the potential BL of the column line as illustrated in Fig. 3(e). When this has been detected, i.e., when the potential of the column line has reached the Y line setting voltage V y minus 25 mV in the above described example, the sense amplifier 7 sends out an output signal D₀ of "H" level as illustrated in Fig. 3(g). The discharge circuit 4 is provided for, during the period of the clock Φ,discharging the electronic charge stored across the parasitic capacitance C px of the row line when the row line is driven. The MOS transistors M₁ connected to all of the row lines X₁ to X m are driven as illustrated in Fig. 3(d) to return the potential of the row lines X₁ to X m to the "L" level. It is evident from the above description that in this embodiment the parasitic capacitance C py of the column line Y₁ to Y n is stably and rapidly charged to a low voltage value of V c = 1 V BE (0.6 to 0.8 V) by the precharge circuit including the column line voltage setting circuit 10. Assuming that the total parasitic capacitance of the column line C pyt = 2 nF, charging voltage V c1 = 0.7 V, and the operation frequency is 10 MHz, the dissipated power in the present embodiment is 70 mW, which is sufficiently low as compared with the prior art. The column line setting voltage V y is set nearly equal to the threshold voltage V st of the sense amplifier 7. When the MOS transistor M for memory cell begins to discharge the electronic charge across the parasitic capacitance C py of the column line, therefore, a slight change in the potential of the column line can be rapidly detected to yield the output signal. Assuming that the parasitic capacitance C py = 4 pF, and the drain current of the MOS transistor M is 100 µA in the above described example, it takes only 1 nsec to produce on the column lines Y₁ to Y n a potential change of 25 mV required for the operation of the sense amplifier 7, resulting in very rapid readout. The precharge time can also be reduced. Assuming that the precharge current is 500 µA under the above described conditions, the precharging can be completed in approximately 5.6 nsec. Fig. 4 shows another embodiment of the column line voltage setting circuit illustrated in Fig. 1. Reference letters in Fig. 4 that are like reference letters in Fig. 2 refer to like components. In Fig. 4, Q₄ denotes an NPN bipolar transistor and D₅ denotes a diode. The potential at a point A coupled to the base of the NPN bipolalr transistor Q₂ is defined by the base-emitter voltage V BEq4 of the NPN transistor Q₄ through which a collector current i ybq flows and the forward voltage drop V Fd5 across the diode D₅ through which a current i ybb flows. And the potential at the point A is approximately 2V BE in the same way as Fig. 2. The base current i yb0 of the emitter follower transistor Q₂ included in the precharge circuit 5 is varied according to the magnitude of the load, the change rate of the potential of the column lines Y₁ to Y n , and the like. Accordingly, the current i Mp1 flowing through the PMOS transistor M p1 must have a sufficient allowance with respect to its maximum value. And the difference between i MP1 and i yb0 is bypassed as the current i d1 flowing through diodes D₃ and D₄ in case of Fig. 2 and as the collector current i ybq of the NPN transistor in case of Fig. 4. A change in the bypass current influences V BE defined by the equation (1) or the forward voltage drop V F , and the voltage drop caused by the parasitic resistance of diodes D₃ and D₄ or the NPN transistor Q₄. In the embodiment of Fig. 4, the bypass current i ybq flows through only the NPN transistor Q₄ and it is reduced to half that of Fig. 2. Accordingly, the change in the column line setting voltage V y is small as compared with Fig. 2. Fig. 5 shows still another embodiment of the column line voltage setting circuit 10. Reference letters in Fig. 5 that are like reference letters in Figs. 2 and 4 refer to like components. The circuit of Fig. 5 includes NPN transistors Q₅ and Q₆, diodes D₆ and D₇ and a resistor R₄. In this embodiment, the base current fed to all of the NPN transistors Q₂ in the precharge circuit 5 is supplied from the NPN transistor Q₅ constituting an emitter follower. Accordingly, the base current of the NPN transistor Q₅ supplied through the PMOS transistor M p1 becomes equal to i ybo /β, which has a very small value. While the current i MP1 flowing through the MOS transistor M p1 is directly supplied to the bases of all NPN transistor in the embodiments of Figs. 2 and 4, the base current i yb0 of the NPN transistor Q₂ is supplied from the NPN transistor Q₅ in the embodiment of Fig. 5. In the embodiments of Figs. 2 and 4, the PMOS transistor M P1 must have correspondingly low impedance. Assuming that this impedance is Z P1 , the current i MP1 flowing through the MOS transistor M P1 can be represented as Excepting i yb0 which becomes the base current of the NPN transistor Q₂, the current i MP1 is bypassed to the diodes D₃ and D₄ in Fig. 2 or to the NPN transistor Q₄ in Fig. 4. When charging of column lies Y₁ to Y n has been completed, the current i yb0 becomes zero and the entire current i MP1 is bypassed. Meanwhile, in the embodiment of Fig. 5, the base current i yb0 of the NPN transistor Q₂ is supplied from the NPN transistor Q₅. When charging of the parasitic capacitance of the column lines Y₁ to Y n has been completed, the emitter potential of the NPN transistor Q₅ rises up and the NPN transistor Q₅ turns off. The NPN transistor Q₅ thus performs impedance conversion and switching function. Accordingly, the diodes D₆ and D₇ and the NPN transistor Q₆ included in the bias circuit for defining the base potential of the NPN transistor Q₅ operate with a high impedance. Since the change in the operation current is small, the NPN transistor Q₅ and the column line setting voltage V y can be set very stably. The source of the NMOS transistor M n1 is connected to the base of the NPN transistor M n1 . When a control signal C y turns to its "H" level to turn on the NMOS transistor M n1 , therefore, the base of the NPN transistor Q₅ is short-circuited to the emitter thereof to turn off the NMOS transistor M n1 rapidly. In addition, the emitter potential of the NPN transistor Q₅ (i.e., the base potential of the NPN transistor Q₅) becomes equal to the base potential of the NPN transistor Q₅. If the value of the resistor R₄ is suitably chosen, the current flowing through the diodes D₆ and D₇ is decreased to lower the base potential of the NPN transitor Q₅ when the PMOS transistor M p1 turns off. Thus, it is possible to reduce the base voltage of the NPN transistor Q₅ as much as a voltage almost equal to a difference in the base potential of the NPN transistor Q₅ between when the base of the NPN tansistor Q₅ is short-circuited to the emitter thereof to make the voltage between them zero and when the base of the transistor Q₅ is lowered as mentioned above. When the column lines Y₁ to Y n are recharged, it is scarecely necessary to charge the parasitic capacitance located at the node A. Therefore, it becomes possible to activate the precharge circuit 5 at a high speed and significantly reduce the precharge time. If the source of the NMOS transistor M n1 in Fig. 5 is connected to a coupling point A' between the diodes D₆ and D₇, it becomes possible to further decrease the change in the potential at the point A when the NMOS transistor M n1 turns on. Further, even in Figs. 2 and 4, it is possible to prevent the potential at the node A from being lowered to the ground potential by connecting the source of the NMOS transistor M n1 to the anode of the diode D₄ or to the base of the NPN transistor Q₄. Fig. 6 shows another embodiment of the sense amplifier 7 illustrated in Fig. 1. Reference letters in Fig. 6 that are like reference letters in Fig. 1 refer to like components. In Fig. 6, a Schottky diode SBD, is a clamp diode for preventing the saturation of the NPN transistor Q₃ in the same way as the diodes D₁ and D₂ of the sense amplifier 7 illustrated in Fig. 1. While in the sense amplifier 7 of Fig. 1 a part of the current flowing through the resistor R₂ is always diverted to the collector side of the NPN transistor Q₃ through the diode D₂, in this embodiment the current flowing through the resistor R₂ is usually supplied to the base of the NPN transistor Q₃. Accordingly, the efficiency of utilization is improved, resulting in saved power consumption. Fig. 7 shows another embodiment of the sense amplifier 7 illustrated in Fig. 1. Reference letters in fig. 7 that are like reference letters in Fig. 1 refer to like components. In Fig. 7, the column line Y i is connected to a common anode coupling node B between diodes D₁ and D₂. As a result, the threshold voltage V st of the sense amplifier 7 becomes approximately 2V BE (1.2 to 1.6 V). Accordingly, the column line setting voltage V y of the column line voltage setting circuit 10 must also be approximately 2V BE in conformity with the threshold voltage V st . This can be easily attained by adding a diode in series with the diodes D₃ and D₄ of Fig. 2, the diode D₅ of Fig. 4, or the diode D₇ of Fig. 5, for example. When there is a difference between the column line setting voltage V y and the potential at a node B in this embodiment, the diodes D₁ and D₂ can prevent the NPN transistor Q₃ of the sense amplifier from being saturated by a current rushing from the parasitic capacitance C py of the column line into the base of the transistor Q₃. Fig. 8 shows still another embodiment of the sense amplifier 7 illustrated in Fig. 1. Reference letters in Fig. 8 that are like reference letters in Fig. 1 refer to like components. In the sense amplifier of Fig. 8A, an NPN transistor Q₇, NMOS transistors M n2 and M n3 , PMOS transistors M p2 , M p3 and M p4 , resisors R₅ and R₆, and diodes D₈, D₉ and D₁₀. Fig. 8B is a time chart for the operation of the circuit illustrated in Fig. 8A. The gate of the NMOS transistor M n2 and the gate of the PMOS transistor M p2 are controlled by a sense amplifier control signal SEN. During the period of clock Φ while the sense amplifier 7 is not working, the control signal SEN turns to the "H" level as illustrated in (d) of Fig. 8B. Thus, the NMOS transitor M n2 turns on and the PMOS transisstor M p2 turns off. When the PMOS transistor M p2 turns off, the load resistance of the NPN transsitor Q₃ becomes substantially infinitely great ∞. Thus the collector current is cut off, resulting in saved power dissipation. Since the NMOS transistor M n2 turns off, the saturation of the NPN transistor Q₃ is prevented. The PMOS transistor M p4 is provided for supplying the base current to the NPN transistor Q₃. The base current of the NPN transistor Q₃ must be so defined that the NPN transistor Q₃ may sufficiently turn on when the memory transistor M is absent on the column line Y i . And the base current of the NPN transistor Q₃ must not be so large as to saturate the NPN transistor Q₃ even in saturation. In addition, the base current of the NPN transistor Q₃ must be small enough to raise the collector voltage of the NPN transistor Q₃ to bring it into the OFF state or nearly into the OFF state when the memory transistor M is present on the column line Y i and it is selected to divert a part of the base current of the NPN transistor Q₃ thereto. That is to say, the base current of the NPN transistor Q₃ and its load resistance must be determined in close relation to the ON resistance of the memory transistor M. This object is attained by the circuit illustrated in Fig. 8A. At first, both the load circuit and base bias circuit of the PNP transistor Q₃ comprise the PMOS transistors M p2 and M p4 as constituent elements to make the circuits match each other. Thus, the circut of Fig. 8A is hardly affected by nonuniformity in the manufacturing process. In addition, the PMOS transistor M p4 of the base bias circuit is made to be a constant current source, the current value of which is defined by the channel conductance of the memory transistor M constituting a memory cell. A gate bias circuit 12 is provided for this purpose. In the circuit 12, the NMOS transistor M n3 is so formed as to have the same size as that of the memory transistor M constituting a memory cell. The NMOS transistor M n3 is driven with the gate voltage being nearly set to the row (X) line voltage of the memory matrix and with the drain voltage being nearly set to the column (Y) line voltage. The base bias current is defined as the product of a proportionality constant K and the drain current of the NMOS transistor M n3 driven as described above. The proportionality constant K is defined by a current mirror circuit comprising the PMOS transistors M p3 and M p4 . In the embodiment of Fig. 1, the gate of the memory tansistor M constituting a memory cell is driven by the emitter follower circuit and the row line voltage V x can be represented as V x = V cc - V BE . And the drain voltage V y is the column line setting voltage V y , and it follows that V y = V BE . In the circuit 12, the circuit comprising the resistor R₆, diodes D₉ and D₁₀, and the NPN ransistor Q₇ produes the row line voltage V x , and the circuit comprising the diode D₈ and the resistor R₅ produces the column line voltage V y . The PMOS transistors M p3 and M p4 are formed to have a ratio of approximately 2:1 in channel width, and the current transfer ratio k is chosen to be approximately 0.5. By this embodiment, the optimum design allowance with respect to the process nonuniformity can be chosen. Thus, it is possible to realize a semiconductor memory with a high yield rate and without sacrificing the speed and power dissipation. Fig. 9 shows another embodiment of a semiconductor memory according to the present invention. Reference letters in Fig. 9 that are like reference letters in Fig. 1 refer to like components. The embodiment of Fig. 9 includes AND gates G H0 to G Hm for decoding the upper address, AND gates G L0 to G Lm for decoding the lower adress, AND gates G₀₀ to G mm for selecting one row line on the basis of decoding result of the upper and lower address, row lines X₀₀ to X mm , latch circuits L₀ to L m , and AND gates G M0 to G Mm . In the embodiment of Fig. 1, all of the MOS transistors M₁ in the discharge circuit 4 are driven each readout cycle. When the number of row lines is large, the power dissipation cannot be neglected. In addition, the load of the gate G₂ becomes heavy and hence the operation speed is also lowered. This drawback is mitigated in the embodiment of Fig. 9, the time chart of which is illustrated in Fig. 10. The basic operation of the embodiment of Fig. 9 will now be described. From the decoding AND gates G L0 to G Lm for the lower address, a block signal XB i (Fig. 10(c)) for designating a block of row lines is produced. The block signal XB i is latched in a latch circuit L i to be converted to a block discharge signal BDL i (Fig. 10(e)). By a discharge MOS drive signal BD i (Fig. 10(h)) produced from the block discharge signal BDL i (Fig. 10(e)), a discharge MOS transistors M₁ belonging to the block having the driven row line are driven at the former half of the next readout cycle. Therefore, the number of the discharge MOS transistors M₁ which are driven becomes small, resulting in lower power dissipation and higher speed. Fig. 11 shows another embodiment of the present invention. Reference letters in Fig. 11 that are like reference letters in Figs. 1 and 9 refer to like components. The embodiment of Fig. 11 differs from that of Fig. 9 in that the clock signal is not applied to inputs of the AND gates G₀₀ to G mm located at the final stage of the decoder and that the output of the Y decoder 11 controls the column line voltage setting circut 10 in the precharge circuit 5 to precharge only a selected column line. Fig. 12 shows the operation time chart of the circuit illustrated in Fig. 11. Since the output of the X decoder is sent out without being subjected to AND operation with the clock Φ, the block signal XB i (Fig. 12(c)) and the X-line drive signal WL i (Fig. 12(g)) appear during the duration of the clock Φ. Accordingly, the row line is driven earlier and hence the output D out of the sense amplifier 7 is produced earlier, resulting in higher speed of operation. Further, precharging of the column lines Y₀ to Y n is carried out only for a column line selected by the Y decoder. Assuming that the Y decoder conducts decoding at a ratio of 1/8, for example, the power required for charging and discharging the parasitic capacitance of the column line is further reduced to 1/8. Approximately 70 mW in the embodiment of Fig. 1 is reduced to approximately 9 mW in that of Fig. 12. Fig. 13 shows embodiments of the Y decoder 11 and the column line voltage setting circuit 10 illustrated in the embodiment of Fig. 11. Reference letters in Fig. 13 that are like reference letters in Figs. 1 and 4 refer to like components. The column line voltage setting circuit 10 in Fig. 13 has nearly the same configuration as that of Fig. 4. The difference exists in that the source of the NMOS transistor M n1 is connected to the base of the NPN transistor Q₄, that an NMOS transistor M n4 having a gate controlled by the clock is connected in parallel with the NMOS transistor M n1 , and that the gate of the NMOS transistor M n1 and the gate of the PMOS transistor M p1 are controlled by the output of the Y decoder 11 and the source of the PMOS transistor M p1 is driven by a clock driver 13. A Y driver circuit 14 includes an NPN transistor Q₉, a PMOS transistor M p6 , NMOS transistors M n7 and M n8 . Fig. 14 shows still another embodiment of the present invention. Reference lettrers in Fig. 14 that are like reference letters in Fig. 1 refer to like components. The embodiment of Fig. 14 differs from that of Fig. 1 in that the clock signal is not applied to the input of a NAND gate G₁', that the base of the NPN transistor Q₁ is driven by the output of the X decoder through an inverter G₄ and the MOS transistor M₁ for X-line discharging is directly driven by the output of the X decoder, and that only a column line selected by the Y decoder is precharged in the same way as the embodiment of Fig. 11. The operation chart of this embodiment is illustrated in Fig. 15. As illustrated in Fig. 15(e) and (f), the row line voltage W Lx and W Li are so produced as to correspond in both rising and falling edges to a decoder output X x of the previous cycle (Fig. 15(d)) and a decoder output X i of the present cycle (Fig., 15(c)), respectively. And only the output voltage of the precharge circuit 5 as illustrated in Fig. 15(g) and (h) is controlled by the clock Φ. Since individual row lines are activated independently by the decoder output and precharging is also controlled by the Y decoder output, the operation with high speed and low power consumption can be realized. Fig. 16 shows comparative examples of the sense amplifier 7 and the column line voltage setting circuit 10. Reference letters in Fig. 16 that are like reference letters in Fig. 1 refer to like components. In the circuit of Fig. 16, diodes D₁₀ to D₁₆, an NPN transistor Q₁₀, and resistors R₁₀ and R₁₁ are included. An NPN transistor Q₁₀ included in the sense amplifier 7 is common base type, and diodes D₁₃ to D₁₆ constitute a bias circuit for defining the base potential. The bias voltage is represented as V cc -4V F ≃ V cc -4V BE . The column line setting voltage V y is further lower by the base-emitter voltage V BE of the NPN transistor Q₁₀. Assuming that V cc is 5V in an equation V y =V cc -5V BE , it follows that V y ≃ 1 to 2V. Until the column line parasitic capacitance C py in the present circuit is charged up to this column line setting voltage V y , the charging current is mainly supplied from the emitter of the NPN transistor Q₁₀. When charging has been completed, the emitter current becomes zero to turn Dout to the "H" level. When X i is then driven to turn the memory transistor M on, a current from the parasitic cpacitance C py and the emitter of the NPN transistor Q₁₀ flows into the MOS transistor M. As a result, a voltage drop across the resistor R₁₀ is incurred to turn Dout to the "L" level. That is to say, the column line setting voltage V y in the present embodiment as well is equal to the threshold voltage V st of the sense amplifier 7. Thus, the column line setting voltage V y becomes nearly equal to the threshold voltage V st of the sense amplifier 7. Further, if charging the column line parasitic capacitance C py has been completed, there is no DC current path until the memory transistor M turns on, DC current being completely zero. Therefore, it is possible to realize a semiconductor memory which dissipates less power as compared with the above described sense amplifiers. The diodes D₁₀ to D₁₂ are clamp diodes for preventing the NPN transistor Q₁₀ from being saturated when the parasitic capacitance C py is charged. Fig. 17 shows another comparative example. Reference letters in Fig. 17 that are like reference letters in Figs. 1 and 16 refer to like components. In Fig. 17, the base of the NPN transistor Q₁₀ is biased to 2V BE in nearly the same way as the embodiment of Fig. 4. Accodingly, the column line setting voltage V y is expressed as V y =V BE . This is nearly the same potential as the potential of Figs. 2, 4 and 5. Fig. 18 shows the configuration of the sense amplifier 7 and the column line voltage setting circuit 10 according to a further comparative example. The sense amplifier 7 has the same configuration as the example of Fig. 17. And the column line voltage setting circuit 10 has similar configuration to the embodiment of Fig. 5. In the example of Fig. 18, the base current of the NPN transistor Q₁₀ is supplied from the NPN transistor Q₁₃. Only the base current of the NPN transistor Q₁₃ and the collector current and base current of the NPN transistor Q₁₂ are supplied from a resistor R₁₃. Thus, it becomes possible to realize small output impedance in a circuit of relatively large impedance. Further, the current of the resistor R₁₃, which is the source of the current flowing through diodes D₁₈ and D₁₉ required for setting the bias voltage, is not largely affected by the load of the circuit 10. Thus, stable output voltage is obtained. In any of the examples of Figs. 16, 17 and 18, a plurality of sense amplifiers 7 can be connected to one column line voltage setting circuit 10. Fig. 19 shows an example of a semiconductor memory whereto the circuits of Figs. 16, 17 and 18 have been applied. Reference letters in Fig. 19 that are like reference letters in Fig. 14 refer to like components. In this example, any part of the circuit is not controlled by the clock Φ. Thus, a completely static ROM can be realized, resulting in further higher speed and lower power dissipation. This sense amplifier 7 forms a part of the column line voltage setting circuit 10. The charging current for the parasitic capacitance of the column line is restricted by the load resistor R₁₀. In addition, this current depends upon the channel conductance of the MOS transistor M of the memory cell. Accordingly, this current cannot be made large freely. When the charging time of the above described parasitic capacitance becomes long, therefore, the column line voltage setting circuit 10 of the invention as illustrated in Figs 2, 4 and 5 can be provided to enhance the precharge capability. However, this results in a dynamic circuit. Fig. 20 shows the circuit configuration of a semiconductor memory which is another embodiment of the present invention. Fig. 21 shows the operation time chart of the circuit illustrated in Fig. 20. The embodiment of Fig. 20 shows the case of a read only memory (hereafter abbreviated as ROM). Reference numeral 3 denotes a memory cell matrix in which MOS transistors constituting memory cells can be arranged in a matrix form. Row lines and column lines are represented by W L and DL ij (i=1 to n, j=1 to m), respectively. Reference numeral 2 denotes an X decoder. A precharge circuit 5 is provided for charging the parasitic capacitance of the column line DL ij . Q₂ denotes a bipolar transistor, the emitter (reference electrode) of which is connected to the column line Dij at a node 113 and the collector of which is connected to a first power source. Numeral 11 denotes a Y decoder. Numeral 6 denotes a Y selector circuit. MOS transistors M ij (i=1 to n, j=1 to m) are provided to select one out of each group of column lines DL 1j , DL 2j ... ... DL nj (j=1 to m) belonging to the same bit and connect it to a common node 112 of each group. A sense circuit 70 includes a second bipolar transistor Q₃, the emitter (reference electrode) of which is connected to a common node 112 of each bit of the above described column line DL ij and the collector of which is connected to a resistor R₁. A buffer amplifier A₁ converts the collector voltage of the second bipolar transistor Q₃ into the desired logical output voltage which has been shaped. The resistor R₁, bipolar transistor Q₃ and buffer amplifier A₁ constitute each of sense amplifiers 7₁ to 7 n for amplifying the voltage appearing at the common node 112 of the column line D ij . A column line voltage setting circuit 10 supplies the base (control electrode) voltage of the first bipolar transistor Q₂ which is a constituent of the precharge circuit 5. The column line voltage setting circuit 10 is composed of a resistor R₂, diodes D₁ and D₂, a P-channel MOS transisor M₁, and an N-channel MOS transistor M₂. A sense amplifier bias circuit 90 supplies the base (control electrode) voltage of a second bipolar transistor Q₃ which is a constituent of the sense amplifier. The sense amplifier bias circuit 90 is composed of a resistor R₃, diodes D₃ and D₄, a P-channel MOS transistor M₃ and a N-channel MOS transistor M₄. The operation of the circuit of Fig. 20 will now be described by referring to a time chart of Fig. 21. Fig. 21(b) shows the waveform of the output signal of the Y decoder 11. Among the MOS transistors M ij (i=1 to n, j=1 to m) constituting the Y selector circuit 6, M ij0 (i=1 to n) is driven. Among column lines DL ij , lines DL ij0 (i=1 to n) are selectively connected to the sense amplifiers 7 i (i=1 to n), respectively. Fig. 21(c) shows the waveform of a control signal C₁ of the column line voltage setting circuit 10. The control signal C₁ turns to the "L" level in the precharge section I. As a result, the PMOS transistor M₁ turns on and the NMOS transistor M₂ turns off. Accordingly, the output voltage V bp of the column line voltage setting circuit 10 is applied to the base of the bipolar transistor Q₂ in the precharge circuit 5. Since the drain of the PMOS transistor M₁ is clamped to the second power supply by diodes D₁ and D₂, the output voltage V bp can be represented as V bp =2V F , where V F is the forward voltage drop across the diode. The forward voltage drop V F across the diode is nearly equal to the base-emitter voltage V BE of the bipolar transistor. Accordingly, the output voltage of the column line voltage setting circuit 10 can be represented as V bp =2V F ≃ 2V BE . Hence, the precharge voltage V p of the column line (voltage at the node 113) can be represented as V p ≃ V BE . Fig. 21(e) shows the waveform of the column line voltage. As described above, the parasitic capacitance of the column line is charged by the emitter current of the bipolar transistor Q₂ to be set to V F =V BE . In a section II which is a discharge section, the control signal C₁ turns to the "H" level. Accordingly, the PMOS transistor M₁ of the column line voltage setting circuit 10 turns off and the NMOS transistor M₂ turns on. As a result, the diode D₁ is short-circuited by the NMOS transistor M₂. The output voltage of the circuit 10 thus becomes V bp =V F to turn off the first bipolar transistor Q₂ of the precharge circuit 5. The resistor R₂ functions to supply a bias current to the diode D₂ through the NMOS transistor M₂ and clamp the output voltage V bp of the column line voltage setting circuit 10 to V F during the discharge section II. As shown in Fig. 21(d), a control signal C₂ of the sense amplifier bias circuit 90 turns to the "L" level during the discharge section II. Since in this embodiment the sense amplifier bias circuit 90 is configured similarly to the above described column line voltage setting circuit 10, the operation of the circuit 90 is similar to that of the column line voltage setting circuit 10 during the precharge section I. Accordingly, the output voltage V ba of the sense amplifier bias circuit 90 is so biased as to satisfy the relation V ba =2V F ≃ 2V BE . The voltage V F of the emitter of the bipolar transistor Q₃ which forms the input terminal of the sense amplifier 7 i (i=1 to n) is so set as to satisfy the relation V F =V BE . Under such a state, the output signal X of the X decoder 2 as illustrated in Fig. 21(a) is sent to one of the row lines WL. If a MOS transistor M₀ is present at the imtersection of the row line W L and the column line DL ij0 , therefore, the electronic charge stored across the parasitic capacitance of the column line DL ij0 is discharged through the MOS transistor M₀, the potential V D of the column line being lowered. The precharge voltage V p of the column line DL ij0 set by the column line voltage setting circuit 10 during the precharge section I is nearly equal to the sense amplifier input voltage V F during the discharge section II. Accordingly, the descent of the column line voltage V D directly becomes the change in the sense amplifier input voltage. As illustrated in Fig. 21(f), therefore, the output voltage of the sense amplifier is settled with an extremely short delay. The broken line indicated in Fig. 21(d) corresponds to a state in which the control signal C₂ of the sense amplifier bias circuit 90 is fixed to the "L" level. As described above, the base-emitter voltage V BE of the first bipolar transistor Q₂ in the precharge circuit 5 is equal to the base-emitter voltage V BE of the second bipolar transisstor Q₃ in the sense circuit 70. If the control signal C₂ is the "L" level during the precharge section I, therefore, the collector current of the second bipolar transistor Q₃ in the sense circuit 70 is equal to the collector current of the first bipolar transistor Q₂ in the precharge circuit 5. In general, this current value is significantly larger than the readout current flowing through the above described MOS transistor M₀ of the memory cell. Accordingly, the second bipolar transistor Q₃ of the sense circuit 70 may be saturaterd due to the voltage drop across the resistor R₁ and may hinder the operation. To prevent this, the control signal C₂ is turned to the "H" level during the precharge section I. Since the output voltage V ba of the sense amplifier bias circuit 90 thus satusfies the relation V ba < V bp , the second bipolar transistor Q₃ is cut off. In this embodiment, however, a MOS transistor M ij (i=1 to n, j=1 to m) of the Y selector circuit 6 is connected between the column line DL ij , whereto the emitter of the first bipolar transistor Q₂ in the precharge circuit 5 is connected, and the common node 112, whereto the emitter of the second bipolar transistor Q₃ in the sense circuit 5 is connected. Therefore, it is possible to restrict the current flowing from the second bipolar transistor Q₃ in the sense circuit 70 to the column line D ij0 side. Accordingly, saturation of the second bipolar transistor Q₃ can be prevented by suitably setting the channel conductance of the MOS transistor M ij and the resistance value of the resistor R₂. In this case, it is possible to fix the control signal to the "L" level as represented by broken lines in Fig. 21(d). In this case, the MOS transistors M₃ and M₄ of the sense amplifier bias circuit 90 do not have the function of the control gate. By suitably choosing the resistance value of the resistor R₃, therefore, the MOS transistors M₃ and M₄ can be eliminated. Fig. 22 shows still another embodiment of the present invention. In this semiconductor memory, the memory matrix 1 and the decoder 2 are eliminated, and the relation m=4 holds true. Reference letters in Fig. 22 that are like reference letters in Fig. 20 refer to like components. The embodiment of Fig. 20 in that four column line voltage setting circuits 10 are provided corresponding to the number of output signals of the Y decoder 11. Control signals C₁₁ to C₁₄ of the column line voltage setting circuit are controlled by the output signals of the Y decoder 11. The output signal of each column line voltage setting circuit 10 applies the bias voltage to the base of the first bipolar transistor Q₂ for precharging the data line DL ij0 selected by the Y decoder 11. According to this embodiments, only one out of m (m=4 in Fig. 22) column lines belonging to one bit is selectively precharged. Accordingly, the power dissipation required for charging and discharging the parasitic capacitance in the memory matrix can be reduced to 1/m. In case of a large capacity memory, reduction in the output current of the column line voltage setting circuit 10 by 1/m means reduction in the charging electronic chage to the memory matrix per circuit by 1/m. Thus, the time required for precharge can be reduced and the maximum emitter current of the first bipolar transistor Q₂ in the precharge circuit 5 can be restricted to a practically reasonable value, resulting in improved reliability. Fig. 23 shows other embodiments of the column line voltage setting circuit 10 and the sense amplifier bias circuit 90 illustrated in Figs. 20 and 22. Reference letters in Fig. 23 that are like reference letters in Figs. 20 and 22 refer to like components. In Fig. 23, a reference voltage circuit 101 supplies common reference voltage V R to both the column line voltage setting circuit 10 and the sense amplifier bias circuit 90. The reference voltage circuit 101 includes a resistor R₁₀ and diodes D₁₀ to D₁₃. In the column line voltage setting circuit 10 and the sense amplifier bias circuit 90, resistors R₁₁ to R₁₄, a PMOS transistor M₁₀, NMOS transistors M₁₁ to M₁₄, bipolar transistors Q₁₀ to Q₁₃ and an inverter G₁₀ are included. The operation in the configuration of Fig. 23 will now be described. A bias current for diodes D₁₀ to D₁₃ connected in series is supplied from the resistor R₁₀ which is connected to the first power supply Vcc and which forms a bias circuit. The forward voltage drop 4V F =V R thus produced is used as the common reference voltage for the column line volttage setting circuit 10 and the sense amplifier bias circuit 90. In the sense amplifier bias circuit 90, the base of the bipolar transistor Q₁₂ is connected to the output of the reference voltage circuit 101, and the emitter of the bipolar transistor Q₁₂ is connected to the base of the bipolar transistor Q₁₃. The emitter of the bipolar transistor Q₁₃ is used as the output terminal of the sense amplifier bias circuit 90. Resistors R₁₃ and R₁₄ are bias resistors for keeping the base-emitter voltage V BE of each of bipolar transistors Q₁₂ and Q₁₃ higher than a fixed value when loads of the resistors R₁₃ and R₁₄ are light or absent. By cascade connection of the bipolar transistors Q₁₂ and Q₁₃ as decribed above, it becomes possible to obtain a sufficiently large current amplification factor and restrict a change in output voltage V ba with respect to a change in load (a change in emitter current of the bipolar transistor Q₁₃) to a sufficiently small value. Assuming that the forward voltage drop V F of the diodes D₁₀ to D₁₃ can be represented as V F ≃ V BE in the same way as Fig. 20, the output voltage V ba can be represented as V ba =4V BE -2V BE =2V BE , which is equal to the output voltage of Fig. 20. The column line voltage setting circuit 10 is obtained by adding a switching circuit for interrupting the output to the above described sense amplifier bias circuit 90. That is to say, a PMOS transistor M₁₀ and an NMOS transistor M₁₁ connected in parallel are inserted into the base circuit of the bipolar transistor Q₁₀ to switch the base current of the bipolar transistor Q₁₀. NMOS tansistors M₁₂ and M₁₃ are provided for extracting the base storage charge of the bipolar transistors Q₁₀ and Q₁₁ at high speed when the base current is cut off. Thereby, the emitter current of the bipolar transistor Q₁₁, which is the output current of the column line voltage setting circuit 10, is cut off at high speed. The remaining basic configuration of the circuit 10 is similar to the sense amplifier bias circuit 90. In the column line voltage setting circuit 10, the switching MOS transistors M₁₀ and M₁₁ are inserted in series between the base of the bipolar transistor Q₁₀ and the reference voltage circuit 101. Therefore, a high current amplification factor as described above is especially effective in reducing the voltage drop across the MOS transistors M₁₀ and M₁₁ and in stabilizing the output voltage. Since in this embodiment the reference voltage circuit 101 for determining the output voltage of the column line voltage setting circuit 10 and that of the sense amplifier bias circuit 90 is used in common for both circuits, it is possible to maintain excellent harmony between the output voltage V bp and V ba of these two circuits. Further, sufficiently large current amplification factors are assured in these two circuits. Even when a plurality of column line voltage setting circuits 10 are provided as in the embodiment of Fig. 22, therefore, it is possible to obtain stable, well-matched output voltage values by using the common reference voltage. It is a matter of course that a plurality of sense amplifier bias circuits 90 can also be connected to one reference voltage circuit 101, if necessary. In the above described respective embodiments of the present invention, the parasitic capacitance of the column line is precharged via the first bipolar transistor having the emitter coupled to the column line. Since the bipolar tarnsistor which is approximately ten times higher in drive capability (smaller in ON resistance) than the MOS transistor is used for precharging, it is possible to make the time required for precharging extremelty short. Since the emitter of the sense circuit for reading data from the memory is directly or indirectly connected to the column line and the base of the sense circuit is connected to the sense amplifier bias circuit, it is possible to make efficient use of large gm of a bipolar transistor for detecting the column line voltage. Further, since the output voltage of the column line voltage setting circuit 10 is set nearly equal to that of the sense amplifier bias circuit 90, the precharge voltage is nearly equal to the detection voltage (threshold voltage) of the sense amplifier. Thus, a slight change in the column line voltage can be detected during the readout, resulting in readout at extremely high speed. Although in the examples described before bipolar transistors are used as the first and second transistors, FET's can be used instead at a cost of slight degradation in performance. In this case, the gate, source and drain of the FET may be used as the gate which is a control electrode, emitter which is a reference electrode and the collector, respectively. Fig. 24 shows another embodiment of the present invention. Reference letters in Fig. 24 that are like reference letteres in Figs. 20, 21, 22 and 23 refer to like components. In Fig. 24, the base of the second bipolar transistor Q₃ in the sense circuit 70 is connected to the AC ground. The emitter of the second bipolar transistor Q₃ is connected to a MOS transistor M₂₀₄ for biasing and a series circuit of a MOS transistor M ij for column line selection and a MOS transistor M₀ constituting a memory cell. The collector of the second bipolar transistor Q₃ is connected to a MOS transistor M₂₀₀ constituting the load impedance. A gate bias circuit 60 produces gate voltage V bg of the load MOS transistor M₂₀₀. A bipolar transistor Q₂₀ has a base connected in common to the base of the second bipolar transistor Q₃ in the sense circuit 70. A MOS transistor M₂₀₂ has the same size and conductivity type as those of the MOS transistor M ij in the Y selector circuit 6. A MOS transistor M₂₀₃ has the same size and conductivity type as those of the MOS transistor M₀ in the memory matrix. A MOS transistor M₂₀₁ has a gate connected in common to the gate of the load MOS transistor M₂₀₀ in the sense circuit 70 and has the same conductivity type as that of the load MOS transistor. In the above described configuration, the same voltage V x ' as the gate voltage V x of the MOS transistor M₀ in the memory matrix 3 during the ON time is applied to the gate of the MOS transistor M₂₀₃. And the same voltage V y ' as the gate voltage V y of the MOS transistor M ij in the Y selector circuit 6 during the ON time is applied to the gate of the MOS transistor M₂₀₂. When the MOS transistor M₂₀₄ is in the OFF state, therefore, the base voltage and emitter circuit impedance of the bipolar transistor Q₃ are equal to those of the bipolar transistor Q₂₀. Hence, equal magnitude of collector currents flow through the bipolar transistors Q₃ and Q₂₀. The MOS transistor M₂₀₁ inserted in the collector circuit of the bipolar transistor Q₂₀ has the gate and drain connected together and constitutes a current mirror circuit in conjunction with the MOS transistor M₂₀₀. Owing to the above described configuration, the load impedance of the second bipolar transistor Q₃ always matches with the impedance of the emitter circuit of that transistor. Even if the MOS transistor M₀ in the memory matrix 3 and the MOS transistor M ij in the Y selector circuit 6 vary in threshold voltage, mobility or the like due to the variation in process conditions, or even if the power supply voltage varies, it is thus possible to maintain always optimum load impedance. Owing to the present invention, a semiconductor memory with high speed and low power dissipation can be realized.

Claims: A semiconductor memory comprising: a plurality of memory cells (M) connected to row lines (X1 - Xm); sense amplifiers (7) connected to said memory cells (M) by column lines (Y1 - Yn); and means (5) for setting a predetermined column line voltage (Vy) for said column lines (Y1 - Yn), including a first bipolar transistor (Q2) the collector of which being connnected to a first power source, the emitter being connected to an associated column line (Y1 - Yn) and the base being connected to a base bias circuit (10), characterized in that each sense amplifier (7) includes a second bipolar transistor (Q3) at its input side, that the base bias circuit (10) provides a voltage determined by the forward voltage drop across a number of pn-junctions, and that the threshold voltage of the sense amplifier (7) is determined by the forward voltage drop across one or more pn-junctions and is substantially equal to the predetermined column line voltage (Vy). A semiconductor memory according to Claim 1, wherein each memory cell (M) comprises an MOS transistor. A semiconductor memory according to Claim 1 or 2, wherein said second bipolar transistor (Q3) has its collector connected to a second power source through a load element (R₃), its base connected to said second power source through a series circuit of an impedance element (R₂) and a diode (D₁) and has its emitter connected to another power source, wherein a diode (D₂) is connected between a point where said impedance element (R₂) and said diode (D₁) are connected together and said collector, and wherein said base is used as an input terminal of said sense amplifier. A semiconductor memory according to Claim 3, wherein said impedance element comprises a second MOS transistor (M p4 ) of a first conduction type, and the gate of said second MOS transistor is connected to a gate bias circuit (12) which produces an output voltage for controlling the current of said second MOS transistor in correlation with the current of a first MOS transistor constituting a memory cell (M). (Fig. 8A). A semiconductor memory according to Claim 4, wherein said gate bias circuit (12) includes: a third MOS transistor (M n3 ) having the same size and conduction type as said first MOS transistors constituting said memory cells (M); a drain bias circuit (R₆, D₉, D₁₀, Q₇) for applying nearly the same voltage as said predetermined column line voltage (V y ) to the drain of said third MOS transistor (M n3 ); a bias circuit (D₈, R₅) for applying nearly the same voltage as the voltage (V x ) applied to said row lines to the gate of said third MOS transistor (M n3 ); and a fourth MOS transistor (M p3 ) of the first conduction type connected so as to let flow the drain current of said third MOS transistor (M n3 ) through it, the gate and drain of said fourth MOS transistor (M p3 ) being connected together, the drain of said fourth MOS transistor (M p3 ) being used as the output terminal of said gate bias circuit (12). (Fig. 8A). A semiconductor memory according to claim 1, wherein said first and second bipolar transistors (Q₂, Q₃) are of the same conduction type, the emitter of said second bipolar transistor (Q₃) being connected to the associated column line and its base being connected to a sense amplifier bias circuit (90) generating an output voltage substantially equal to that of said column line voltage setting means (5). A semiconductor memory according to Claim 6, wherein said sense amplifier (7) and said column line voltage setting means (5) are connected through impedance means (M ij ). A semiconductor memory according to Claim 7, wherein said impedance means (M ij ) comprise field effect transistors for selectively connecting one of said column lines to its associated sense amplifier (7). A semiconductor memory according to Claim 6, wherein said base bias circuit (10) and said sense amplifier bias circuit (90) have a common reference voltage line (V R ).

Inventors: IWAMURA, MASAHIRO, KURITA, KOZABURO, MAEJIMA, HIDEO, MASUDA,  IKURO, NAKANO, TETSUO, UENO, MASAHIRO, MASUDA, IKURO
Applicants: HITACHI, LTD.
Application year: 1985
Main classification: G11C7
IPC codes: G11C7, G11C5