ADVANCED VIDEO PROCESSOR WITH HARDWARE SCROLLING

Abstract: A video system with hardware scrolling includes the com­ bination (1) of a video processor including a color palette for processing of data, a memory (31) for storing of data to be pro­ cessed, a monitor (33) and (35) for displaying of the processed data, a processor (30) for controlling the transfer of data from the memory (30) to the monitor (33) and (35). The video pro­ cessor (1) includes a control logic (65) for controlling the trans­ fer of data and instructions between the processor (30) and the video processor (1); a memory control logic (67) for control­ ling, in response to the instructions from the processor (1), the transfer of data from the memory (31); registers and counters (63) for arranging data from the memory (31) in a predeter­ mined order, to provide scrolling data for changing a display on the monitor (33) and (35) pixel by pixel and to apply the scrolling data according to the prearranged order to the sprite processor (10); and video output logic (57) for converting the scrolling data to a video signal to which the monitor (33) and (35) will respond to provide a display of a plurality of rows and characters of pixels.

Description: This invention relates generally to video signal devices and, more particular, to a video display processor which can superimpose one or more mobile patterns at selected location on a larger, defined pattern image to obtain a display. The display may be scrolled in both the horizontal and vertical directions one pixel at a time. The basic principle for superimposing one or more mobile patterns at selected locations on a larger, fixed pattern image was described and claimed in U.S. Patent US-A-4,243,984, assigned to the assignee of the present invention. Other systems which disclose moveable patterns are provided in the following U.S. Patent Numbers US-A-4,112,422; US-A-4,129,858; US-A-4,034,990; US-A-4,107,664; US-A-4,016,362; US-A-4,116,444; US-A-3,771,155; US-A-4,296,476; US-A-4,232,374; US-A-4,177,462; and US-A-4,119,955. In GB-A-2,070,399 there is described an apparatus providing a raster scan video display having a host processor and an image memory with access by the host processor to the image memory being controlled by an image memory access controller. Signals representing an image generated by the host processor are conveyed via a signal bus to a rewrite controller which under the control of a panning controller selects some of the signals from the host processor for storage in the image memory through the image memory access controller. A c.r.t. tube display receives image data from the image memory through the image memory access controller at the request of the panning controller. Control signals applied to the panning controller enable the image area displayed on the c.r.t. to pan through the image data provided by the host processor. According to the present invention there is provided a video system comprising: a host processor for generating data representative of features to be displayed, a memory for storing said data, a video display processor for controlling data transfer between said host processor and said memory and for generating a displayable signal from said data, and a display for displaying said signal, said host processor having a control bus and a data bus connected to said display processor, and said memory having a data bus and an address bus connected to said display processor, characterized in that said display processor includes an address register for generating address outputs on said address bus in response to signals on said control bus to permit said storage of said data representative of features to be displayed, a plurality of registers loadable by said processor via said data bus of said host processor and arranged to define characteristics of said features, and means for accessing said stored data in dependence upon the content of said plurality of registers, whereby said features as displayed have said defined characteristics. Graphics patterns on a video monitor or TV set used as a video monitor may be scrolled pixel by pixel with a hardware scrolling feature of the advanced video processor. A vertical scroll register and a horizontal scroll register allow up to 256 moves in the horizontal direction, and 256 pixels in the vertical direction. The horizontal scroll register is part of the advanced video processor and is loaded by host CPU that controls the operation of the advanced video processor with 8 bits of information for the horizontal positioning of a pixel and another 8 bit register for the vertical position. Depending on the width and height of the screen, by changing of the 8 bit contents of either/or the horizontal scrolling or vertical scrolling register the display may be rolled in either direction or up and down pixel by pixel. A display is defined as, depending on the mode of operation, a plurality of pixels arranged in between 248 and 256 lines and 192 to 256 rows. Displays may be scrolled one pixel at a time in both the vertical and horizontal directions by changing the contents of either or both a horizontal scroll register and a vertical scroll register that are contained within the advanced video processor. When the contents of the horizontal scroll register or the vertical scroll register are changed, the data that is being displayed and obtained from a memory location within a video display RAM is changed according to the modification to the address of the video display RAM by the horizontal scrolling registers and the vertical scrolling registers. These and other objects and advantages of the present invention will be more apparent from a reading of the specification in conjunction with the figures in which: Figure 1 is a block diagram of a video display system according to the invention. Figure 2 is a block diagram of the advanced video processor of Figure 1; Figure 3 is a diagram illustrating theapproaching coincidence of two sprites; Figure 4 is a diagram indicating the use of sprites for a computer game; Figure 5 is a diagram illustrating the use of sprites to create a graphics display; Figure 6 is a diagram of a byte and bit assignments of the byte according to the invention; Figure 7 is a block diagram of an alternate embodiment of the invention; Figure 8 is a block diagram illustrating the use of a direct memory address capabilities of the advanced video processor according to the invention; Figure 9 is a bus assignment of the advanced video processor's data bus; Figure 10 through 14 are register assignment layouts; Figure 15 is a color assignment design; Figure 16 is a status bit assignment design; Figure 17 is a schematic diagram of the advanced video display processor In Figure 1, to which reference should now be made, there is shown a block diagram of a video display system 100 incorporating an advanced video processor 1 according to the invention. A host microcomputer 30 (CPU) interfaces with an Advanced Video Processor (AVDP) 1 via a bidirectional data bus 51, a control bus 49 and an interrrupt line 47. The AVDP 1 is used to interface microprocessor 30 to a color video monitor 33. The AVDP 1 uses a dynamic RAM 31 to store the information displayed on the video screen. The microprocessor 30 loads the AVDP's 1 configuration registers through the 8 bit CPU to AVDP data bus 51. The microprocessor 30 then loads the video RAM 31 with the information that is to be displayed on a video screen 32. The AVDP 1 refreshes the video screen 32 independently of CPU accesses. The video RAM 31 is accessed by the AVDP 1 through an 8 bit address bus and 8 bit data bus. The AVDP 1 also supplies the necessary RAS (Row Address Strobe) and CAS (Column Address Strobe) to interface the dynamic video RAM 31 to AVDP 1. Additionally, connected to the advanced video processor 1 is a random access memory, video RAM 31, which is connected to the advanced video processor 1 via bydirectional data bus 53, memory address bus 55 and a control line 45. The graphics are displayed on either one or two possible systems, a Red, Green, and Blue (RGB) monitor 33 which is connected to the advanced video processor 1 via an RGB bus 39 or a composite video monitor or TV set 35 which is connected to the advanced video processor 1 via a color difference bus 41 and a video encoder or RF monitor 37. Additionally, sound is provided to the composite video monitor or TV set 35 via a sound bus 43. The advanced video processor 1 includes 7 basic function blocks. These include the CPU control logic 65 which handles the interface between the host microcomputer 30 and the advanced video processor 1 and is the termination portion of the control lines 49, the input and output of data to data bus 51 and the providing of interrupts to the host microcomputer 30 via interrupt line 47. CPU control logic 65 enables the host microcomputer 30 to conduct five basic operations. These include the writing of data into the video RAM 31, the reading of data from the video RAM 31, the writing of data to the advanced video display processor (AVDP) 1's internal registers 63, the reading of data from some of the advance video processor 1's internal registers 63 and the writing to an internal sound generator 69 that is contained within the advance video processor display logic. The type and direction of data transfers are controlled by the control lines 49 and in particular CSW, CSR, and mode input lines. CSW is the CPU 30 to AVDP 1 write select line. When CSW is active low the eight bits on the CDO-CD7 of the data lines 51 are strobed into the video display processor. CSR is the CPU to AVDP read select line. When CSR is active low the AVDP outputs eight bits of data onto the CDO-CD7 lines for the CPU to read. When CSW and CSR are both active low the sound generator 69 is addressed. Mode determines the source or destination of a read or write transfer. Mode is generally connected to a CPU low order address line. Figure 9 provides an illustration of the data transfer between the host CPU 30 to the AVDP 1. A video RAM control logic 67 controls the interface between the advanced video processor 1 and the video RAM 31 and handles the transfer of data from the data bus 53 that is provided to the video RAM 31 at the memory address location that is provided on the memory address bus 55 in response to the control signals that are provided on the control lines 4. In the embodiment shown, the data bus 53 is an 8 bit bidirectional bus and the memory address bus 55 is an 8 bit multiplex address bus. The advance video processor illustrated in Figure 1 can directly address 16K bytes, two (TMS4416s or equivalent, 32 bytes, 4 TMS4416s or equivalent, or 65K bytes 8 (TMS41664S) (all TMS parts are manufactured by Texas Instruments or equivalent) while currently providing dynamic refresh to the video RAM 31. The internal registers 63 in the embodiment shown in Figures 1 and 2 contain two read only registers, a status register and a sprite collision register in Figure 16 and forty nine write only registers illustrated in Figures 11. The write only registers provide the following functions. Three of the write ony registers define the mode of operation of the advanced video display processor 1 and specify options such as the mode of operation and type of video signal output necessary to drive the RGB monitor 33 or the composite video mointor or TV set 35. Six of the write only registers that are contained within the internal register block 63 are designated advanced video display procesor 1 to display memory address mapping registers and specify locations in the video RAM 31. One write only register is a color code register and defines colors when the video display processor 10 is operating in the text mode. Two separate registers are scrolling registers; one is horizontal scrolling the other is for vertical scrolling. One programmable interrupt register enables the advance video processor 1 to be reconfigured during a horizontal retrace interval that occurs in all television monitor signals. Four block move address and decament counter registers allow a defined block of video memory to be moved to another video memory location. Thirty two palette pilot registers define up to 16 displayable colors (from a 52 color palette) per horizontal scan lines. The read only registers provide the following functions. A status register contains flags for interrupts, coincidence and eleventh sprite occurance on any one horizontal line. The AVDP has a single 8-bit status register 28 which can be read by the CPU 1. The format of the status register 28 is shown in Figure 12. The status register contains the interrupt pending flag (F), the sprite coincidence flag (C), the eleventh sprite flag (11S), and the eleventh sprite number if one exists. The status register 28 may be read at any time to test the F,C and 11S status bits. Reading the status will clear the interrupt flag F. However, asynchronous reads of the status will cause the frame flag (F) bit to be reset and therefore possibly missed. Therefore the status register should only be read when the AVDP 1 interrupt is pending. It requires only one data transfer to read the status register 28. Interrupt Pending Flag (F) The F status flag in the status register is set to 1 whenever there is an interrupt pending. This bit will be set one of three ways; when a block move has completed, when a programmable interrupt is selected, or when an end of frame has occurred (Vertical Retrace Period). The interrupt pending flag is reset to 0 when the status register is read or by the external reset. When the appropriate interrupt enable bit (IE bit 2 of write only register 1 or PIE bit 2 of write only register 10) is set to 1 (INT) will be active low whenever the F status flag is a logic 1. Note the status register needs to be read after each interrupt in order to clear the interrupt and receive the new interrupt on the next occurence. Coincidence Flag (C) The C status flag in the status register is set to a 1 if two or more sprites coincide. Coincidence occurs if any two sprites on the screen have one overlapping pixel. Transparent colored sprites, as well as those that are partially or completely off the screen, are also considered. The C flag is cleared to a 0 after the status register is read or the AVDP is externally reset. The status register 28 should be read immediately upon powerup to ensure that the coincidence flag is reset. The AVDP 1 checks each pixel position for coincidence during the generation of the pixel regardless of where it is located on the screen. This occurs every 1/60th of a second. Therefore when moving more than one pixel position during these intervals it is possible for the sprites to have multiple pixels overlapping or even to have passed completely over one another when the AVDP 1 checks for coincidence. Eleventh Sprite Flag (11S) and Number The 11S status flag in the status register is set to a 1 whenever there are 11 or more sprites on a horizontal line (lines 0 to 209 depending on the mode chosen) and the frame flag (F) is equal to 0. The 11S status flag is cleared to a 0 after the status register is read or the AVDP is externally reset. The number of the 11th sprite is placed into the lower 5 bits of the status register when the 11S flag is set and is valid whenever the 11S flag is 1. The setting of the 11th sprite flag will not cause an interrupt. A sprite collision detection register detection register defines which group or groups of sprites have collided. A sprite collision register 83 is an 8 bit register that can be used to determine which groups of sprites collided. The sprite color byte is composed of 4 color bits, an early clock bit and 3 remaining bits; these 3 remaining bits are used to divide the sprites into eight groups. Each bit in the sprite collision register 83 corresponds to one group. Therefore, whenever 2 sprites collide one or more of these bits are set. This register is cleared by a CPU read to this register. Figure 6 shows the layout of these groups in the sprite collision register 83. It requires 3 data transfers to read this register. A sprite processor 10 incorporates full sprite control on the advanced video display processor 1 which in the embodiment shown on a single chip. The sprite processor 10 includes the features which with as many as 10 sprites may occur (in the embodiment shown in Figure 1) on a single horizontal scan line. Previous video display processors were limited to only four sprites per line. The sprites may be multi-color or single color with each horizontal half scan line of the sprite having the option of being a different color from the sprite. Additionally, unique sprite coincident detection is provided in the embodiment of the disclosure. A coincidence occurs if any two sprites on the display have at least one overlapping pixel. Sprite mapping necessary to provide this feature is contained in the video RAM 31. Graphics and text processing is provided by a graphics and text processor 60 in which the host microprocessor 30 configures the advanced video display processor 1 to operate in one of the following display modes in the embodiment shown in Figure 1: A first graphic display mode in which resolution with two colors for each of an 8x8 pixel block in a 256 x 192 pixels display; Graphics 2 mode which provides two colors for each 8 x 1 pixel block in a 256 x 192 pixel display; Graphics 3 provides two colors for each 4 x 2 pixel blocks for a 256 x 192 pixel display; Graphics 4 provides high resolution with two colors for each 8 x 1 pixel block in a 512 x 192 total pixel resolution; A graphics 5 provides a full bit map of 256 x 210 pixel resolutions; A first text mode provides 40 columns by 24 rows of text; and A second text mode provides 80 columns x 24 rows of text. All text and graphics modes with the exception of the full bit map mode designated as graphics 5 are table driven. A sound generator 1 provides in the embodiment shown in Figure 1 on chip sound generation that is compatible with the devices such as an SN764889 device manufactured by Texas Instruments Incorporated. The circuit provides 3 programmable tone generators; one programmable noise generator; a 120 to 100,000 HTZ frequency response and 15 programmable attenuation steps from 2dB to 28dB in steps of 2dB. Figure 2, to which reference should now be made, is a block diagram of the advance video processor 1 of Figure 1. As was discussed earlier in conjunction with Figure 1, there are included in the internal registers 63 two read-only registers and forty nine write-only registers. Included in these are color palette registers 2 which are 16 registers of 9 bits each for 16 colors. The color palette registers 2 are addressed by a sprite control logic 59; a first color buffer 61; a second color buffer 62 and a third color buffer 64 which are a part of the graphics and text processor 60; a border color register 29; and a text color register 30 which provide program colors. It should be noted that in the advance video display processor 1 the embodiments of Figures 1 and 2 does not fetch color for each character in the text mode as it does in the graphics mode. A color palette read logic 65 addresses the color palette registers 2 to place the contents contained within the color palette registers on a D-to-A logic 67 which as was discussed in conjunction with the color palette and video output logic 57 of Figure 1, provides the Red, Green and Blue colors to either the RGB monitor 33 or the different signal to the video encoded RF modulator 37. Depending on the configuration of the advanced video processor 1, the output of the D-to-A logic 67 is placed on either the RGB bus 39 or the different color bus 41. A color palette write logic 3 controls the loading of the color codes into the color palette register 2 which includes registers R32 through R63 of Figure 11. The format for the palette is shown in Figures 13 and 14. The palette consists of sixteen 9 bit registers which allows the user to display 16 of 512 colors on the screen at one time. On an external reset the color palette is initiallized with the default values shown in Figure 15 for the color difference outputs. A horizontal counter, Programmable Logic Array (PLA) 5, counts positions on the horizontal scan lines and decodes instructions based upon the beam position of the scan and provides timing to the D-to A control logic control logic 67 which is used to identify the sprite position and color. The vertical counter PLA 6 counts rows positions on the scan lines, decodes instructions and provides timing to the sprite register 11 as does horizontal counter PLA as to position color data. Not shown in Figure 2 is the fact that the horizontal counter PLA 5, and vertical counter PLA 6 are connected to the following logic functions. A color priority logic 7 decides priority of color logics between border color logic 29 text color logic 30, color buffers logic 61, and 64 and sprite control logic 59. The priority is based first on border, then on sprite when in active area, or other sprites and there are three or more dependent colors and 7 modes of operations by which the color priority logic provides the appropriate color for the advanced video display processor 1. A interrupt logic 8 provides interrupt to the hose CPU 30 that is based upon a timing signal interrupt to load one of the registers. Refer to Figure 16 wherein: IE = INTERRUPT ENABLE BIT 2 OF REGISTER 28. F = INTERRUPT FRAME FLAG BIT 0 OF STATUS REGISTER; and PIE= PROGRAMMABLE INTERRUPT ENABLE BIT 2 OF REGISTER 10 A programmable interrupt logic 29 can provide an interrupt for any horizontal scan or line and in the embodiment shown in Figure 1 includes an eight bit register the contents of which is compared with the contents of the vertical counter PLA 6 and provides an interrupt request to the interrupt logic 8 when there is a comparison between the contents of the two registers indicating that that scan line requires an interrupt in the program sequences being executed by the host CPU 30. The sprite control logic 59 controls the sprites fetch and checks vertical position from the vertical counter PLA 6 and causes the sprite horizontal position pattern and color data to be fetched. A sprite control logic 59 processes and checks all of the sprites which in the embodiment of Figure 1 includes 32 sprites to see if their positions are valid. If a sprite is to be loaded on the next scan line, the sprite control logic 59 loads the sprite number or vertical position into a sprite stack 11. The sprite stack 11 places the address of the sprite on the RAM address bus 69 for retrieval from the video RAM 31. A CPU register 12 interfaces the host microcomputer 30 with the video RAM 31 via the data bus 51 and 51A which is contained within the video processor 1. A name register 13 contains the name of the background pattern (an 8 bit number) which is used to fetch the pattern and color bytes for the next character to be displayed. The scroll logic includes a vertical state register 22, vertical scroll register 23, character counter 24, horizontal scroll register 25, and horizontal state register 26. For graphics modes 1,2,3,4 and text modes 1 and 2, the screen is broken up into characters. The character counter 24 counts the characters as the TV scan horizontally and vertically. The horizontal state register 26 determines which pixel of the character is being displayed. The vertical state counter 22 determines which row of the character is being displayed. Graphics mode 5 is bit mapped and is not broken up into characters. The horizontal state 26, vertical state 22, and character counter 24 will count pixel by pixel as the TV scans horizontally and vertically in this mode. These counters are used to address the video RAM 31. The horizontal scroll register 25 contains an 8 bit number which determines the horizontal scroll location of the screen. At the beginning of each horizontal line the contents of the horizontal scroll register 25 is loaded into the horizontal state register 26 and character counter 24. By changing the starting position of the counters the screen can be scrolled up to 256 different horizontal positions. The vertical scroll register 23 contains an 8 bit number which determines the vertical scrolling of the screen. At the beginning of each screen scan, the vertical scroll register 23 is loaded into the vertical state register 22 and the character counter 24. By changing the starting position of the counters the screen can be scrolled up to 256 different vertical positions. The base registers 15, 16, 17, 18 defines the locations in video memory 31 where the sections of video information will be stored. The name base register defines the location of the name table in memory. The color base register 16 defines the location of the video color information. The pattern base register 17 defines the location of the pattern bits used to map each character. The sprite location register 18 defines the location of the sprite patterns, sprite colors, sprite horizontal position, and sprite vertical position. The command registers 19, 20, 21 control the mode of operation of the advanced video processor 1. The operation of each bit is explained in the Table 1 sections 3.2.1, 3.2.2, and 3.2.11. A status register 28 provides status via data bus 51A to the host microcomputer 30 that reflects the following interrupt information; a programmable interrupt via occured; more than 10 sprites are being used; two sprites collide; and five bits addition status bits for the 11th sprit on a line. The CPU control logic 65 provides interrupts to the host microcomputer 30 and receives the write commands, the read commands, and mode commands indicating operation; if writing or reading to the video internal registers 63 or video RAMs 31. The blank name registers 27 (2) 16 bit registers are used to move data from one section of memory to another section of memory. One register contains the number of bytes to be moved; the other register contains the read memory location. The write memory destination is located in the address register 14. The color buffers 60 contain 3 bytes of pattern plane color information. Buffer 64 contains the colors which are ready to be loaded onto the color Bus 86. This buffer contains 1 byte of information or (2) 4 bit colors. For graphics modes 1,2,3,4 the LSB nibble of the color byte is loaded onto the color bus if the pattern bit=1 and the MS nibble of the color byte is loaded onto the color bus if the pattern bit=0. For graphics (5), (the bits mapped mode) the LSB nibble is the first color pixel to be displayed and the MSB nibble is the second color pixel to be displayed. Buffers 61 and 62 are temporary storage buffers which will be loaded into buffer 64. The pattern buffer 84 contains the 1's and 0's which will determine which color in buffer 64 will be displayed. The pattern buffer 84 is loaded into the pattern shift register 86 and shifted out serially. The output of the shift register 86 loads the colors from buffer 64 onto the color bus 86 depending on the color priority logic. The sprite registers 100 contain the sprite horizontal pointer 82, the sprite pattern register 81, the sprite color register 80, and the sprite coincidence selection logic 70. This is repeated 10 times for 10 sprites per horizontal line. The sprite horizontal counter 82 is loaded with the horizontal sprite position and decrements to the value of zero. Then the sprite pattern register 81 begins shifting bits out serially. 1's load this sprite color onto the color bus 86 and 0's are not used. The sprite color register 80 contains 4 bits for the sprite color, 1 bit for early clock, and 3 bits to indicate the sprite group. The sprite coincidence detection logic 70 determines if two or more sprites are shifting 1's out of the sprite pattern register 80 at the same time. If this happens 2 or more sprites have collided on the screen. The sprite groups are decoded from the three bits stored in the 10 sprite color registers 80, and the bits corresponding to the sprite groups are set in the sprite coincidence register 83. If the sprites are in the border area and will not be displayed, the bits will not be set. The three bits in the sprite color register 80 can be decoded into 8 groups, each group corresponds to a bit in the sprite coincidence register 83. Figure 4, the coincidence detector of Figures 1 and 2 is useful in the application of the invention to video games; for example a space game in which a space ship 110 which is defined as sprite 1 belonging to group 1, and a plurality of rocket ships which are defined as sprites 2, 3 and 4, all assigned to group 2, a flying saucer 11 which is sprite 8 of group 4 and a plurality of meteors 115, 116 and 117 all are sprites belonging to group 3 are used to implement the game. If one of the rocket ships 112 a, b or c which are in group 2 collide with one another, a coincidence will be detected and bit 2 of the sprite coincidence register 53 will be set . If the spaceship 110 collides with one of the missiles 112, a coincidence will be detected, and bits 1 and 2 of the sprite coincidence register 83 will be set. The host CPU 30 can check to see if the spaceship 10 has collided with another object by reading the sprite coincidence register 83 and checking bit 1. Figure 5 demonstrates multicolor sprites. Sprites can have a different color on each horizontal line. Sprite (1) which contains the hat, eyes, nose, and mouth is only one sprite, even though there are four different colors. Sprite (2) is the face of the sprite and has to be drawn as a separate sprite since it is on the same horizontal lines as the eyes, nose, and mouth. When sprite 1 and sprite 2 are combined together the sprite 129 is created. Figure 7 combines the necessary processing on a single chip that allows both grahics and alphanumeric data (video-text) to be generated. In Figure 7, two way communication is provided in a video text example over standard lines 237 using a modem 235, a data access arrangement 234, and a UART 233. The host CPU 30 has additional interface to a ROM memory 231 and a RAM memory 232, as well as operator interface by a keyboard 236. The Advance Video Data Processor is connected to four RAM's that represent the video RAM 31, and includes an A RAM, B RAM, C RAM, and D RAM as illustrated in Figure 7. The use of the four RAMs which in the preferred embodiment are TMS44116s manufactured by Texas Instruments, provides the memory necessary for the video data storage. The video data is sequenced out by the advance video display processor 1 and then encoded by the video encoder 37 to dot data for each horizontal scan line. The information can then be viewed on the TV set 35. The video display processor 1 provides all the video information and synchronization required to refresh and display the images on the TV set 35. In Figure 8, to which reference should now be made there is shown the Direct Memory Access (DMA) via a DMA controller 103 and a DMA pin 101 which allows the host microcomputer 30 to directly access the video RAM 31. This pin goes to a logic '1' when there is no CPU access Figure 17 is a schematic diagram of the implementation of the Advance Video Processor 1 with field effect transistors technology.

Claims: A video system (100) comprising: a host processor (30) for generating data representative of features to be displayed, a memory (31) for storing said data, a video display processor (1) for controlling data transfer between said host processor and said memory and for generating a displayable signal from said data, and a display (33,35) for displaying said signal, said host processor having a control bus (49) and a data bus (51) connected to said display processor, and said memory having a data bus (53) and an address bus (55) connected to said display processor, characterized in that said display processor includes an address register (14) for generating address outputs on said address bus in response to signals on said control bus to permit said storage of said data representative of features to be displayed, a plurality of registers (15,16 17,18,23,25) loadable by said processor via said data bus of said host processor and arranged to define characteristics of said features, and means (10,57,60) for accessing said stored data in dependence upon the content of said plurality of registers, whereby said features as displayed have said defined characteristics. A video system as claimed in claim 1 characterized in that said features are graphics features. A video system as claimed in claim 1 or claim 2 and characterized in that a defined characteristic is feature colour. A video system as claimed in claim 1, claim 2 or claim 3 characterized in that a defined characteristic is feature position. A video system as claimed in any preceding claim characterized in that a graphic feature is made up of a plurality of pixels and at least one of said plurality of registers is arranged so that when it is loaded with data in a pre-arranged order, said feature is scrolled pixel by pixel. A video system as claimed in claim 1 characterized in that said features are sound features. A video system as claimed in any preceding claim characterized in that said address register (14) may be loaded with an address representative of a target address for a block move and in that the system further comprises means (27) for effecting said block move in dependence upon said address.

Inventors: LEACH, JERALD G.
Applicants: TEXAS INSTRUMENTS INCORPORATED
Application year: 1985
Main classification: G09G1
IPC codes: G06F3, G09G5, G09G1