ARRAY SELECTION CIRCUITRY FOR A RANDOM ACCESS MEMORY

Abstract: The disclosure is directed to an improved random ac­ cess memory (RAM). More particularly, to improved selec­ tion circuitry for use in an array employing CTS (Com­ plementary Transistor Switch) type memory cells. The word selection part of the circuitry uses a voltage mode selection scheme; the bit select part has a circuitry for discharging stored charges on the bit lines and a circuit for up level clamping the bit line for limiting the upper potential level.

Description: The invention is directed to an improved random access memory (RAM). More particularly the invention is directed to improved selection circuitry for an array using CTS (Complementary Transistor Switch) memory cells. The following patents and publications are directed to memory array circuitry and more particularly bit selection, word line selection and related circuitry employed therein. Patents USP 3,423,737 entitled "Nondestructive Read Transistor Memory Cell" granted January 21, 1969 to L. R. Harper. USP 3,525,084 entitled "Memory Sense System with Fast Recovery" granted August 18, 1970 to L. J. Dunlop et al. USP 3,582,911 entitled "Core Memory Selection Matrix" granted June 1, 1971 to J. P. Smith. USP 3,623,033 entitled "Cross-Coupled Bridge Core Memory Addressing System" granted November 23, 1971 to P. A. Harding. USP 3,636,377 entitled "Bipolar Semiconductor Random Access Memory" granted January 18, 1972 to P. C. Economopoulos et al. USP 3,736,574 entitled "Pseudo-Hierarchy Memory System" granted May 29, 1973 to E. D. Gersbach et al. USP 3,753,008 entitled "Memory Pre-Driver Circuit" granted August 14, 1973 to G. Guarnashelli. USP 3,771,147 entitled "IGFET Memory System" granted November 6, 1973 to H. J. Boll et al. USP 3,786,442 entitled "Rapid Recovery Circuit For Capacitively Loaded Bit Lines" granted January 15, 1974 to S. B. Alexander et al. USP 3,789,243 entitled "Monolithic Memory Sense Amplifier/Bit Driver Having Active Bit/Sense Pull-Up" granted January 29, 1974 to N. M. Donofrio et al. USP 3,843,954 entitled "High-Voltage Integrated Driver Circuit and Memory Embodying Same" granted October 22, 1974 to A. A. Hansen et al. USP 3,863,229 entitled "SCR (or SCS) Memory Array with Internal and External Load Resistors" granted January 28, 1975 to J. E. Gersbach. USP 3,919,566 entitled "Sense-Write Circuit for Bipolar Integrated Circuit Ram" granted November 11, 1975 to M. S. Millhollan et al. USP 3,942,160 entitled "Bit Sense Line Speed-Up Circuit for Mos Ram" granted March 2, 1976 to R. T. Yu. USP 4,007,451 entitled "Method and Circuit Arrangement for Operating A Highly Integrated Monolithic Information Store" granted February 8, 1977 to K. Heuber et al. USP 4,042,915 entitled "Mos Dynamic Random Access Memory Having An Improved Address Decoder Circuit" granted August 16, 1977 to J. A. Reed. USP 4,078,261 entitled "Sense/Write Circuits for Bipolar Random Access Memory" granted March 7, 1978 to M. S. Millhollan et al. USP 4,090,254 entitled "Charge Injector Transistor Memory" granted May 16, 1978 to I. T. Ho et al. USP 4,104,735 entitled "Arrangement for Addressing A Mos Store" granted August 1, 1978 to R. Hofmann. USP 4,174,541 entitled "Bipolar Monolithic Integrated Circuit Memory With Standby Power Enable" granted November 13, 1979 to C. R. Schmitz. USP 4,194,130 entitled "Digital Predecoding System" granted March 18, 1980 to J. D. Moench. USP 4,242,605 entitled "Transient Array Drive For Bipolar Rom/Prom" granted December 30, 1980 to W. C. Seelbach. USP 4,264,828 entitled "Mos Static Decoding Circuit" granted April 28, 1981 to G. Perlegos et al. USP 4,287,575 entitled "High Speed High Density, Multi-Port Random Access Memory Cell" granted September 1, 1981 to D. H. Eardley et al. USP 4,308,595 entitled "Array Driver" granted December 29, 1981 to R. J. Houghton. USP 4,323,986 entitled "Electric Storage Array Having DC Stable Conductivity Modulated Storage Cells" granted April 6, 1982 to S. D. Malaviva. USP 4,326,270 entitled "Preset Circuit For Information Storage Devices" granted April 20, 1982 to W. K. Owens et al. USP 4,330,853 entitled "Method of and Circuit Arrangement for Reading and/or Writing An Integrated Semiconductor Storage With Storage Cells In MLT (I²L) Technology" granted May 18, 1982 to H. H. Heimeier et al. Publications [IBM Technical Disclosure Bulletin (IBM TDB)] "Static Cell Array Circuit to Enable Write by Turning Off The Cell Load Devices" by D. B. Eardley, IBM TDB, Vol. 24, No. 6, Nov. 1981, pages 3044-47. "AC Write Scheme For Bipolar Random-Access Memories Using Schottky Coupled Cells" by J. A. Dorler et al, IBM TDB, Vol. 23, No. 11, April 1981, pages 4960-2. "Constant Voltage, Current Sensing Circuit" by V. Marcello et al, IBM TDB, Vol. 24, No. 1B, June 1981, pages 483-4. "Tri-State Read/Write Control Circuit" by V. Marcello et al, IBM TDB, Vol. 24, No. 1B, June 1981, pages 480-2. "Read/Write Control Circuit Reference Voltage Generator" by V. Marcello et al, IBM TDB, Vol. 24, No. 1B, June 1981, pages 478-9. "Bit Current Steering Network" by V. Marcello et al, IBM TDB, Vol. 24, No. 1B, June 1981, pages 475-77. "Complementary Transistor Switch Memory Cell" by J. A. Dorler et al, IBM TDB, Vol. 16, No. 12, May 1984. "Memory Cell" by S. K. Wiedmann, IBM TDB, Vol. 13, No. 3, August 1970, pages 616-7. "A 1024 Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell" by J. A. Dorler et al, IBM Journal of Research and Development, Vol. 25, No. 3, May 1981, pages 126-34. Random access memories employing CTS type memory cells are known to the art. See for the example, the Gersbach patent 3,863,229, the Dorler et al IBM TDB publication, and the Dorler et al IBM Journal of Research and Development Article, each fully identified hereinabove. The known random access memories and the in particular those employing CTS memory cells have two relatively serious bit selection short comings. First, the bit decode transistor has to drive a number of bit columns across the chip. Due to long metal line and large fan out current, voltage drop along the bit decode line is high. The cells at the end of the bit decode line may have insufficient voltage across their "1" bit rail resistors to provide adequate gate currents into the cells. This may lead to potential data retention problems on the selected cells. Secondly, both selection and deselection of the bit rails are slow due to the fact that the bit decode transistor has large fan-out loadings. Discharge speed of the bit rails is limited by the bit rail resistors. The bit selection scheme in accordance with the invention obviates the above recited short comings of known RAMs and in particular RAMs using CTS cells. In high performance arrays using cells like CTS selection of a cell is accomplished by lowering its word lines and raising its bit rails. Known designs use a fixed current source to pull down the selected word lines. There are three problems usually associated with this method of word selection in "current mode". (1) Slow speed. With CTS cells, the word lines are very capacitive. (For word lines having 60 to 80 cells, this word line capacitance could be as high as 30 to 40 pf.) A constant current source pulls down the selected word lines according to its large RC time constant. Hence cell selection is very slow, and its drive capability is often limited by the fixed source of current. (2) Instability. Since the selected word lines are held down by a current source, their voltage levels are easily affected by noise or current source variations. If the word line levels drift to a degree that they no longer track with those of the bit rails, data retention problems could result. (3) Long address set up time to "write". During write operation, the bit line voltage of the side to be written a "1" is driven high. This causes the bit rail and the drain line levels to rise. A long address set up time is needed to wait for the previous selected cell to get out of the way before writing can start in order to avoid write-through problems. From IEEE DIGEST OF PAPERS, SPRING COMPCON 82, TWENTY FOURTH COMPUTER SOCIETY INTERNATIONAL CONFERENCE, San Francisco, California, 22nd-25th February 1982, pages 58-61, IEEE, New York, US; R.D. DUSSAULT et al.: "Novel circuit techniques for dense bipolar RAMs" a CTS memory array is known having improved word line selection and bit line selection circuits and comprising the features of the first part of claim 1. The invention as claimed solves the problems of the slow speed of the, and the long address set up time in "write" operation occurring in known RAMs, preferably in RAMs employing complementary transistor switch (CTS) cells. In summary the invention provides for an improved selection circuitry, whose word line selection part has a "voltage mode word selection scheme" for a RAM, in particular one using CTS (Complementary Transistor Switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto bit select circuit means, each of said bit select circuit means being connected to an output of said second level decoder, a bit up level clamp circuit connected to each of said bit select circuit means of each pair of bit lines, each of said bit select circuit means including first circuit means for increasing the speed of selection of the selected pair of bit lines, said bit up level clamp circuit cooperating with said bit select circuit means of said selected pair of bit lines for positively limiting the upper potential level of said selected pair of bit lines, and each of said bit select circuit means including second circuit means for increasing the speed of deselection of the selected pair of bit lines. The invention also includes voltage mode word selection means in a RAM preferably employing CTS type memory cells. The invention is set forth in claim 1. The invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings. Figure 1 illustrates bit select and word select circuitry in accordance with known RAMs employing CTS memory cells. Figure 1A illustrates the circuit of a known CTS memory cell. Figure 2 illustrates a 1k x 4 random access memory in accordance with the invention. Figure 3 illustrates the bit path circuitry of the random access memory shown in Figure 2. Figure 3A (to be reviewed in conjunction with Figure 3) illustrates the sensing and write control circuitry of the random access memory in accordance with Figure 3 and with the invention. Figure 4 is a circuit diagram of bit address receiver circuits which may be employed in a RAM (Figure 3) in accordance with the invention. Figure 5 is a circuit diagram of a bit decoder circuit which may be employed in a RAM (Figure 3) in accordance with the invention. Figure 6 is a circuit diagram of a bit select circuit which may be employed in a RAM (Figure 3) in accordance with the invention. Figure 7 is a circuit diagram of the bit up-level clamp which may be employed in a RAM (Figure 3) in accordance with the invention. Figure 8 illustrates the circuit diagram of "voltage mode" word selection scheme which may be employed in a RAM (Figure 3) in accordance with the invention. Figure 9 illustrates the circuit diagram of the word decoder circuit in accordance with Figure 8 and with the invention. Figure 10 illustrates the circuitry of a sense amplifier which may be employed in a RAM (Figure 3) in accordance with the invention. Figure 11 is a rearrangement of, and further illustrates the senses amplifier circuitry of Figure 10. Figure 12 is a further diagram referred to hereinafter in the explanation of the voltage mode READ operation of the RAM (Figures 3 & 8) in accordance with the invention. Figure 13 is a further diagram referred to hereinafter in the explanation of the voltage mode WRITE operation of the RAM in accordance with the invention. Figure 14 discloses idealized wave forms of the "WRITE" operation timing. Figure 14 is to be viewed in conjunction with the explanation of the WRITE operation (Figure 13) of the RAM (Figure 3) in accordance with the invention. In high performance arrays using CTS cells, selection of a cell is done by lowering its word lines and raising its bit rails. As depicted in Figure 1, known designs use a fixed current source to pull down the selected word and drain lines. There are the foregoing mentioned three problems frequently associated with the "current mode" method of word selection. These problems are overcome and obviated by the "voltage mode word selection technique" in accordance with the invention and as disclosed herein. Figure 8 shows the schematic diagram of this scheme. Also known high performance arrays using CTS cells have bit selection concerns or short comings. Again referring to Figure 1, these concerns are as follows: 1. The bit decode transistor (TB) has to drive a number of bit columns across the chip. Due to long metal line and large fanout current, voltage drop along the bit decode line (BD) is high. The cells at the end of the bit decode line may have insufficient voltage potential across their "1" bit rail resistors to define adequate gate currents (I1) into the cells. This may lead to potential data retention problems on the selected cells. 2. Both selection and deselection of the bit rails are slow, due to the fact that the bit decode transistor has large fanout loadings. Discharge speed of the bit rails is limited by the bit rail resistors RBL and RBR. The above problems are overcome by using distributive bit select circuits and word line selection circuits illustrated in Figures 3, 3A, 8 and 9. For purpose of illustration, Figure 2 shows a 1k x 4 RAM in accordance with the invention. This RAM has an array density of 4096 cells arranged in 64 words (rows) by 64 bit (columns). The 64 bit columns are further divided into 4 data groups, so that it will write 4 bits (therefore 4 data inputs) and read 4 bits (4 data outputs) at a time. The RAM has 6-bit word addresses (to select 1 out of 64 rows) and 4-bit bit addresses (to select 4 out of 64 bits). Read and write operations are controlled by the RW input. Referring to Figure 3, a two level matrix decode scheme is employed for bit address decoding. The first level decode includes two groups of 4 address lines (BA0 - BA3 and BA4 - BA7) formed from output emitter dotting of the four bit address receivers. The bit address receivers are current switch emitter follower circuits as shown in Figure 4. They convert the address inputs to true and complement signals. By means of emitter follower output dotting of the address receiver pairs, a partial decode of 1 out of 4 is formed from each group, hence, giving a total of two selected (low level) lines. The second level decode function is performed by the 16 bit decoders (Figure 5), which have current switch inputs and high speed push-pull outputs. Input 1 of the bit decoder is connected to one of the 4 lines in BA0 - BA3 address group, and input 2 is connected to one in the BA4 - BA7 group. Of the 16 BD output lines, only one is decoded to a selected up level. Each BD line fans out to drive four bit columns (one from each data group), so that four cells are selected at a time for READ or WRITE operation. Each bit column has a bit select circuit (Figures 3 and 6) to perform bit line select and deselect functions. The selected bit lines up level is set by a bit up level clamp circuit (Bit UPCL, Figure 7), so that the cells' read and write operating points can be readily adjusted by changing the up clamp (UC) level. The bit select circuit's modes of operation are described below. Unselected state: In an unselected state, the BD line is held low by its corresponding bit decoder to a voltage close to V N . Node 1 of the bit select circuit is clamped down by the base-collector diode T4. Bit lines BL and BR are also pulled negative to unselected levels by Schottky diodes D1 and D2. With node 1 being down, transistor T1 and T2 are shut off, and no current will flow into the bit rail resistors RBL and RBR. In this state, resistor R1 provides a small DC current that conducts through T4 into the BD line. Since T4 conducts in saturation mode, it develops large diffusion capacitance (due to storage charge) across its B-C junction. The storage charge will be used to boot strap node 1 up rapidly when the BD line is selected high. Selected READ: When a bit column is selected, its BD line is actively pulled up by the corresponding bit decoder to a voltage about a V BE below V P . This forces diode T4 to move up quickly at the same rate as the BD line. The rapid discharge of T4's large B-C saturation capacitance provides very fast push up action on node 1, hence turning ON T1 and T2 hard to drive the bit lines up through resistors RBL and RBR. During a READ operation, both PDL and PDR lines are high (at around V P ), Schottky diodes D3 and D4 are OFF and will be out of the way. Node 1's level is clamped by the transistor diode T3 to a voltage set by the UC line (Figure 12). This READ reference level is generated by the bit up level clamp circuit in such a way that it will track with the selected cells' voltages to ensure proper READ currents (load current I L and gate current I G ). The read currents are supplied by T1 and T2 through resistors RBL and RBR into the cell. Typical READ currents are set at I L ≈ 1.0 mA and I G ≈ 0.2 mA. This results in a voltage differential of about 500-600 mV across the bit lines for READ sensing by the sense amplifier. In the selected state, since the BD line's voltage level is higher than node 1, diode T4 as well as Schottky D1 and D2 are OFF. No current will flow into or out of the BD line, hence no voltage drop will exist along this line (as compared with prior designs). Furthermore, the selected cell's read currents are sourced directly from V P power supply and are distributed evenly across the array independent of BD line's voltage level. Selected WRITE: In the WRITE mode, bit lines selection is similar to that of the READ mode as described above. The only difference here is that one of the WRITE control lines (either PDL or PDR, depending on the data to be written) is driven negative to a voltage close to V N by the write control circuit prior to bit line selection (Figure 13). The lowered PDL or PDR line will clamp down BL or BR through Schottky diode D3 or D4 respectively, so that when the bit column is selected, only one side of the bit lines will go high to drive write current I W into the cell. The other side will stay at negative down level in order to shut off the bit line current that normally flows into the cell. This mode of write operation is denoted "Differential Mode Write" hereinafter. During WRITE mode, node 1's up level is also clamped by diode T3 to a voltage set by the UC line. The write reference voltage is typically 600-800 mV above the READ reference voltage, so that sufficient write current is always guaranteed to ensure fast write performance. As in READ mode, the write current is also sourced directly from V P through T1 and T2. The write performance is therefore not affected by the BD line's level variations. Deselecting: When a bit column is not selected, its corresponding bit decoder output falls to a low level. Node 1 of the bit select circuit is pulled negative by diode T4 to turn OFF T1 and T2. The bit lines, at the same time, are also pulled down actively by Schottky diodes D1 and D2 and will discharge into the BD line. After the bit lines are fully discharged to unselected down level, D1 and D2 will stop conducting. The bit column is said to be in an unselected state. The disclosed bit select scheme has particular utility in arrays using CTS (Complementary Transistor Switch, Figure 1A) cells. With this scheme, at least the following two advantages have been achieved over the known designs. (I) Improved bit line "select/deselect" speed, hence faster bit path access time. (II) Eliminates bit decode up level line drop, hence reduce data retention concerns for the selected cells. The improved bit selection circuit means, includes the following elements: 1. Two level matrix decode (Figure 3) - First level is emitter dotting of the current switch emitter follower address receivers. Second level is the bit decoders with current switch input and high speed push-pull outputs. 2. Distributive bit select circuit (Figures 3 and 6) - It utilizes capacitive discharge mechanism of a saturated base-collector diode (T4) to enhance selection speed and reduce circuit power. It has transistors T1 and T2 to source the READ and WRITE currents directly from power supply V P . It uses Schottky Barrier Diodes (SBD) D1 and D2 for active bit rail pull down during deselect. It also uses Schottky diodes D3 and D4 in conjunction with the write control circuit to enable "Differential Mode Write" for fast write performance. 3. Bit up level clamp (Figures 3 and 7) - The selected bit lines' read and write up levels are controlled by a reference circuit (Bit UPCL) so as to enable easy operating point adjustment. This circuit is also designed, as more fully explained hereinafter, to meet various tracking requirements (such as tracking with selected drain line level in read mode). The improved word line decoder and control circuitry represented by the block labelled "Word Decode" in Figure 3 is shown in detail in Figures 8 and 9. Figure 8 shows the voltage mode word selection scheme whereas Figure 9 discloses in detail the circuit of the word decoder. Referring to Figure 8, there are 6 bit word addresses to decode 1 out of 64 rows. A two level matrix decode scheme similar to that of the bit path is employed for word address decoding. The first level decode includes three groups of 4 address lines (WA0 - WA3, WA4 - WA7, and WA8 - WA11) formed from output emitter dotting of the 6 word address receivers. The word address receivers are current switch emitter follower circuits (Figure 4). They convert the address inputs to true and complement signals. By means of emitter follower output dotting of the address receiver pairs, a partial decode of 1 out of 4 is obtained from each group, hence giving a total of three selected (low level) lines. The second level decode function is performed by the 64 word decoders (Figure 9). Each word decoder has three current switch inputs (IN1 - IN3) and two high speed high power push-pull outputs (WL and DL). IN1 of the word decoders is connected to one of the four lines in WA0 - WA3 address group. IN2 is connected to one in the second group (WA4 - WA7), and IN3 is connected to one in the third group (WA8 - WA11). All these three inputs have to be low in order to select a row line. The two outputs of the word decoder are connected to the word line (WL) and drain line (DL) of the memory cells as shown. Operations of the word decoder, in accordance with the invention, are explained hereinafter. Unselected state: An unselected word decoder will have at least one of its three inputs high. Decoding transistors T5, T6 or T7 are turned ON to pull down node 1. Transistors T9 and T10 form a dual phase level shifter, so that node 4 is also pulled negative to a voltage close to V N and node 3 is pulled positive to V P . With node 4 being down, the open collector transistor TL is shut off, allowing the word line WL and drain line DL to move up to their unselected (high) levels. In this state, the cells' stand-by current, as well as word and drain line voltages are defined by the current sources I SBH and I SBL . To enable fast switching speed, transistors T9 and T10 are never shut OFF but kept in slight conduction. The active pull up devices (T11 and T H ) are OFF when the word line reaches its full unselected DC level (about one and half V BE below V P ). Selected state: When a word decoder is selected, all its three inputs are low. Transistors T5, T6 and T7 are OFF. Node 1 goes high to turn ON T9 and T10 hard. Node 3 is pulled down by T9's collector to keep T11 - T H OFF, so that WL and DL are allowed to move down to their selected levels. At the same time, node 4 is driven high to turn ON TL. It is this high power open collector pull down action on the drain line that enables the cells to be selected fast. While the drain line is being driven low, the word line follows it at the same rate with a voltage offset defined by the cells. When the word and drain lines are fully selected, T11 - T H are OFF and TL is maintained ON to sink the large READ/WRITE currents conducting from the selected cells. In this state, the word and drain line voltages are defined by following two equations: V (DL) = V N + V CE (TL) (1) V (WL) = V (DL) + V (CELL) (2) Since the selected drain line is pulled down by a high power open collector transistor (T L ), word selection is therefore very fast and its drive capability is not limited by fixed current sources as in prior designs. Furthermore, the selected drain and word line levels are solidly defined to voltages offset from power supply V N , they are more stable than those of the prior art. This technique of word selection is denoted herein as "Voltage Mode Word Selection". Deselected state: After a row line has been selected for a READ or a WRITE operation, it is deselected back to its stand-by state. A deselecting word decoder will have at least one of its inputs go positive. Decoding transistors T5, T6 or T7 are turned ON again, driving node 1 down to shut OFF the open collector transistor T L . At the same time, node 3 is pulled positive to V P , driving the emitter follower devices T11 - T H transiently ON to pull up word line WL until it reaches its unselected DC level. While the word line is being pulled positive, drain line DL follows it up at the same rate with a voltage offset defined by the cells. When the word and drain lines are fully up at their stand-by levels, T11 - T H and T L are all OFF. The row line is now said to be in an unselected state. READ operation: A cell is selected for the READ operation when its row lines (WL, DL) and bit lines (BL, BR) are both selected (Figure 12). The row lines are selected by the voltage mode word selection scheme as previously described. The bit lines are selected by the bit selection scheme explained earlier (Figure 3). After a cell is fully selected, read currents I L and I G are fed into its bit rail Schottky SL and SR, which then couple the cell's internal voltage ("0" and "1") on to the bit lines for READ sensing. In order to guarantee cell stability during READ, I L and I G currents have to be controlled within a chosen operating range. This is accomplished by a READ reference level applied to the bit rail driving transistors (T₁ and T₂ of Figure 12) from the UC line. The READ reference is generated by a bit up level clamp circuit (Bit UPCL, Figure 7) which tracks fully with the selected cells, so that sufficient voltage potentials (V"0" and V"1") are always ensured across bit rail resistors RBL and RBR to define I L and I G currents. Generation of this READ reference level, and the operation of the bit up level clamp circuit, will be more fully explained in the following sections. WRITE Operation: With voltage mode word selection and technique, WRITE operation is performed in three sequential steps (Figures 13 and 14). 1. The row lines are selected/deselected as previously described. 2. After crossing of the selecting and deselecting drain lines (see Figure 14), WRITE operation is initiated. The RW clock switches the bit up level clamp circuit to generate a WRITE reference voltage on the UC line. This RW signal is also applied to a write control circuit, which depending on its data input, will drive either one of its two output lines PDL or PDR low. The lowered PDL or PDR line will then pull down bit line BL or BR respectively by Schottky diodes D3 or D4, so that bit current into this side of the cell is shut off prior to WRITING. The shutting off of the gate current that normally flows into the cell before WRITING is essential for a successful write operation. With the presence of gate current during WRITE, the presently ON NPN transistor in the cell will remain ON and will not be able to be overcome by the write current I W . 3. After gate current is shut OFF, the side of the bit line to be written a "1" is raised high by the bit rail transistor (T1 or T2 of Figure 13). Write current I W is then injected into the cell through bit rail resistor RBL or RBR until the desired cell state is reached. As in READ operation, the magnitude of write current I W is also controlled by a WRITE reference level applied to the bit rail driving transistors T1 and T2 through the UC line. This write current can readily be adjusted by changing the bit up level clamp WRITE reference level. The above write scheme is denoted "Differential Mode Write", since one side of the bit line is raised high while the other side is being held low during write time. The key advantage of this write scheme is that since the drain line is selected to a fixed voltage offset from V N , when write current is injected into the cell, the level of this line will not move up but remain stable. The chasing effect with the deselecting cells as exists in "current mode" word selection scheme used by prior art designs is hence eliminated. The write pulse can now come in sooner (as soon as the selecting and deselecting drain lines cross over) without waiting for the deselecting cells to get out of the way. This minimizes address set up time required prior to write. Due to faster word selection and shorter address set up time, write performance is therefore greatly improved. Furthermore, since the selected drain line is solidly held to a voltage level, and the deselected one is actively pulled up quickly to its unselected level, no "write through" (i.e., writing into the deselecting as well as the stand-by cells) problems exist. As is submitted to be evident from the above description the use of the voltage mode word selection technique, in accordance with the invention, particularly in CTS RAMs, provides the following benefit and advantages: (1) Enables very high speed word select and deselect, hence faster "READ" performance. (2) Provides large row lines drive capability, hence very desirable for high density applications. (3) Stabilizes the selected drain line level, hence eliminates possible data retention and WRITE through problems. (4) Enables faster "WRITE" performance. Bit up level clamp circuit The proper operation of a voltage mode word selection scheme in a CTS RAM requires a bit up level clamp circuit to define a selected cells' operating levels. This is particularly important for the READ operation. A read reference voltage is generated by the bit up level clamp to track with the selected cells in temperature, power supply (V N ) and device (V BE and V FSBD ) variations, so that proper read currents (I G and I L ) are always guaranteed under all conditions to ensure cell stability. The bit up level clamp circuit (Figure 7) represented in Figures 3 and 3A by the block labelled "BIT UPCL" will now be explained with particular reference to Figures 8, 12 and 13. (1) READ REFERENCE: Referring to Figure 12, the voltage level required at the emitter of the clamping diode T12 in READ mode can be determined by summing up the potential rises/falls from V N in the word decoder. Voltage V T12 = V N + V BE (TL) - V F (S2) = V BE (TR) + V F (SL) + V"1" + V BE (T1) - V BE (T3) Cancelling the V BE rises/falls and V F rises/falls in the above expression, a simplified equation defining the READ reference voltage is obtained: Voltage V T12 = V N + 2 V BE + V"1" (1) For a READ operation, the R/W control input of the bit up level clamp circuit (Figure 7) is high. Transistor T15 is ON and T16 is OFF, so that node 3 is up to turn ON T12, T13 and T14. The output line UC is clamped down by T12 to generate a READ reference voltage defined by the equation below. Equating expressions (1) and (2), we have: Voltage V T12 = V UC (READ) ⇒ V N + 2 V BE + V"1" = V N + 3 V BE - V F ⇒ V"1" = V BE - V F (3) V"1" is the voltage across the "1" side of the bit rail resistor. It is this voltage potential across RBL that defines the gate current I G to maintain cell stability during READ. The read currents I G and I L are related by the following expressions: and V"0" = V"1" + V F As seen from equation (3), since V"1" is defined by the voltage difference between a V BE (forward mode Base-Emitter voltage of NPN transistor) and V F (forward conduction voltage of a Schottky diode), it is therefore independent of power supply and temperature variations. (2) WRITE REFERENCE: In a WRITE mode, the R/W input is low. Transistor T15 is OFF and T16 is ON. Node 1 is high to pull up T17 while node 3 is down to shut OFF T12. The WRITE reference level at the UC line is given by: V UC (WRITE) = V P - V BE (T12) (4) This WRITE reference voltage is applied to the bit rail driving transistors (T₁ and T₂, Figure 13) to define the write current I W . Read Sensing Circuitry The operation of circuitry represented in Figure 3 by the block labelled "sensing circuitry" will now be explained with particular reference to Figures 10 and 11. Figure 3A illustrates the sensing scheme employed for the RAM shown in Figure 2. The 64 bit columns of this RAM is divided into four data groups of 16 bits. Each data group contains a sense amplifier (Figure 10) for READ sensing. The state of the sense amplifier is determined by the selected cell within its data group. Data read by the sense amplifier is output off chip through an off chip driver (OCD) circuit. Figure 11 illustrates the sense amplifier arrangement for a data group. Within a data group, each bit column has a pair of sensing transistors (TL and TR) attached to its bit lines for voltage sensing. When a cell is selected for READ, its row lines (WL and DL) are pulled down by its corresponding word decoder, and its bit lines (BL and BR) are raised up by its bit select circuit. Since there are 16 bit columns per data group, bit selection is always 1 out of 16. Of the thirty-two bit lines, only two are up at any one time. The higher of these two selected bit lines turns on the corresponding sensing transistors of the sense amplifier circuit. Sense Amplifier Circuit Operation Figure 10 illustrates a high speed sense amplifier circuit designed for the above sensing scheme. The circuit uses current steering technique to enable very fast switching performance. Its sensing speed is independent of the number of bit columns in the data group. Referring to Figure 10, the thirty-two sensing transistors TL1 to TL16 and TR1 to TR16 form a big current switch input for the sense amplifier. The bases of these transistors are connected to the sixteen bit columns in the data group. Transistors T18 and T19 are emitter followers providing dual-phase outputs to drive the off chip driver. Transistors T20 and T21 are set to be ON all the time to define a fixed voltage at nodes A and B, so that switching of these two devices is done in current mode. At any time, either bit-left or bit-right of a selected bit column is up at a high voltage level. The higher voltage bit line turns on its corresponding sensing transistor. The sense current I S from the current source T22 is then steered by the ON sensing transistor through either T20 or T21, pulling node 1 or 2 down accordingly. Since voltage levels at node A and B will never be switched but remain fixed, any capacitance at these nodes, therefore will have no effect on the switching time. In fact, the circuit's delay will stay constant, disregarding the number of sensing transistors attached to its input stage. Furthermore, transistors T18, T19 and T20, T21 are active all the time; hence, their switching delay is kept to a minimum. The features of the sense amplifier circuit in Figure 10 are summarized as follows: 1. The sensing transistors are configurated as a bit current switch, with their bases connected to bit lines within the data group. This forms the input stage of the sense amplifier. 2. The switching of the circuit is done in current mode, i.e., input voltages at A and B are fixed, and switching is performed by steering sense current I S through T20 or T21. This mode of operation enables very large fan-in capability, as well as high circuit speed independent of input loadings. 3. All switching devices (T18, T19 and T20, T21) are kept active at all times to minimize circuit delay.

Claims: A high-speed selection circuit for a random access memory, said memory comprising: an array of memory cells having m columns and n rows, where m and n are positive integers, and said memory array including m x n memory cells, where each of said memory cells has the capacity to store one binary bit and each of said n rows of memory cells has the capacity to store m binary bits; m pairs of bit lines, each pair of said m pairs of bit lines including a first bit line (BL) and a second bit line (BR): n pairs of word lines (WL), each pair of said n pairs of word lines including an upper word line (WL) and a lower word line (DL); each of said memory cells of said m x n array of memory cells being connected to the first bit line (BL) and the second bit line (BR) of a predetermined one of said m pairs of bit lines; each of said memory cells of said m x n array of memory cells also being connected to the upper word line (WL) and the lower word line (DL) of a predetermined one of said n pairs of word lines; and said selection circuit comprises a word line decoder circuit means coupled to said n pairs of word lines for selecting one of said n pairs of word lines, said word line decoder circuit means being effectiv by voltage mode word line selection, including a push-pull voltage drive function on the upper word line (WL) and lower word line (DL) of the selected word line pair; bit address decoder circuit means having a plurality of select lines coupled to said m bit select circuits for selecting at least one of said m bit select circuits; and a circuit for discharging stored charges of one bit line of said n pairs of bit lines prior to initiation of a write operation, m bit select circuits, each of said m bit select circuits being connected to a discrete one of said m pairs of bit lines, a switchable bit line up level clamp circuit having an output terminal connected to each of said m bit select circuits and for limiting the upper potential of said selected pair of bit lines; each of said bit select circuits (Figure 6) comprises: first (T1) and second (T2) transistors, each having an emitter, base and collector, a first resistor (RBL) connected between said emitter of said first transistor (T1) and said first bit line (BL) of said pair of bit lines connected to said bit selection circuit, a second resistor (RBR) connected between said emitter of said second transistor (T2) and said second bit line (BR) of said pair of bit lines connected to said bit selection circuit, a first diode (T3) connected between said common connection of said bases of said first and second transistors (T1, T2) and said output terminal of said bit up level clamp circuit, characterised in that said collectors of said first and second transistors being connected in common to a potential source (V P ), a third resistor (R5) being connected between said potential source (V P ) and a common connection of said bases of said first (T1) and second (T2) transistors, a second diode (D1) being connected between a predetermined one of said plurality of select lines (BD) and the first bit line (BL) of said bit line pair connected to said bit select circuit, a third diode (D2) being connected between said predetermined one of said plurality of select lines (BD) and the second bit line (BR) of said bit line pair connected to said bit select circuit, a capacitive means (T4) being connected between said one of said plurality of select lines (BD) and the common connection of said bases of said first (T1) and second (T2) transistors of said bit select circuit. The circuit according to claim 1 comprising n push-pull transistor pairs (T11, TL in Figure 9), each of said n push-pull transistor pairs including an emitter follower transistor (T11) whose emitter is coupled to the upper word line (WL), and an open collector transistor (TL) whose collector is coupled to the lower word line (DL) of a discrete one of said n word line pairs. The circuit according to claim 1 or 2, characterised by said word line decoder having a first level of circuitry for receiving a word address and a second level of circuitry connecting said first level of circuitry to said n pair of word lines, whereby the operation of said bit address decoder circuit means in conjunctions with the operation of said word line decoder circuit means effects the selection of at least a predetermined one of said m x n array of memory cells. The circuit according to claim 3, wherein said second level of circuitry of said word line decoder circuit (Figure 9) includes n decoder circuits each of said n decoder circuits having at least one or more and preferably three inputs and providing one of said n outputs, each of said at least three input decoder circuits comprising: third (T5), fourth (T6), fifth (T7), sixth (T8), seventh (T9), eighth (T11) and ninth transistors (TL), each transistor having an emitter base and collector, said collector of said sixth transistor (T8) being connected to said first source of potential (V P ), said collector of said eighth transistor (T11) being connected to said first source of potential (V P ), said emitter of said ninth transistor (TL) being connected to a second source of potential (V N ), said base of said eighth transistor (T11) being connected to said collector of said seventh transistor (T9), said base of said sixth transistor (T8) being connected to a reference source of potential (V REF ), said bases of said third (T5), fourth (T6) and fifth (T7) transistors providing said three inputs of said decode circuit; a fourth resistor (R1) connected between a common connection of the collectors of said third (T5), fourth (T6) and fifth (T7) transistors and said base of said seventh transistor (T9), and said first source of potential (V P ); a fifth resistor (R2) connected between a common connection of the emitters of said third (T5), fourth (T6), fifth (T7) and sixth (T8) transistors and said second source of potential (V N ); a sixth resistor (R3) connected between said collector of said seventh transistor (T9) and said first source of potential (V P ); a seventh resistor (R4) connected between said base of said ninth transistor (TL) and said second source of potential (V N ); a fifth diode (T10) connected between said emitter of said seventh transistor (T9) and said base of said ninth transistor (TL); a sixth diode (TH) connected between said emitter of said eighth transistor (T11) and said upper word line (WL) of said predetermined one of said n pairs of word lines; and said collector of said ninth transistor (TL) connected to said lower word line (DL) of said predetermined one of said n pairs of word lines. The circuit according to claim 4, wherein said fifth (T10) and sixth diodes (TH) are respectively provided by first and second "diode connected" transistors. The circuit according to claim 1, comprising of a first circuit for increasing the "select speed" of the bit line pair selected and further including a second circuit means for enhancing the discharge rate of the bit line pair upon deselection thereof. The circuit of claim 6 , wherein said capacitive means (T4) connected between said juncture of said second (D1) and third (D2) serially connected diodes and said common connection of said bases of said first (T1) and second (T2) transistors is the base-collector diode of a third transistor (T8) having an emitter, base and collector. The circuit of claim 7, wherein said base of said third transistor (T4) is connected to said common connection of said bases of said first (T1) and second (T2) transistors, and said emitter and collector of said third transistor (T4) are connected in common to said juncture of said serially connected second (D1) and third (D2) diodes. The circuit of anyone of the claims 1 to 8, wherein said second (D1) and third (D2) diodes are respectively Schottky diodes, said first diode (T3) is a baseemitter diode of a fourth transistor having an emitter, base and collector, said collector and base of said fourth transistor being connected in common to said common connection of said bases of said first (T1) and second (T2) transistors, and said emitter of said fourth transistor being connected to said switchable bit up level clamp circuit. The circuit of claim 1, wherein said switchable bit line up level clamp circuit (Figure 7) comprises: third (T15), fourth (T16), fifth (T12) and sixth (T17) transistors, each of said third, fourth, fifth and sixth transistors having an emitter, base and collector, said emitters of said third and fourth transistors (T15 and T16) being connected in common, said read/write control input of said switchable bit up level clamp circuit being connected to said base of said first transistor (T15), said base of said fourth transistor (T16) being connected to a first reference source of potential (V R ), said collector of said fourth transistor (T16) being connected to said base of said fifth transistor (T12), and said collector of said fifth transistor (T12) being connected to said emitter of said sixth transistor (T17), said collector of said sixth transistor (T17) being connected to said first source of potential (V P ), and said base of said sixth transistor (T17) being connected to said collector of said third transistor (T15); a fourth resistor (R6), said fourth resistor (R6) connecting said collector of said third transistor (T15) to said first potential source (V P ); a fifth resistor (R7), said fifth resistor (R7) connecting said common connection of said emitters of said third and fourth transistors (T15 and T16) to a second source of potential (V N ); a sixth resistor (R8), said sixth resistor (R8) connecting said collector of said fourth transistor (T16) to said first source of reference potential (V P ); a seventh resistor (R9), said seventh resistor (R9) connecting said collector of said fifth transistor (T12) to said first source of potential (V P ); an eighth resistor (R10), said eighth resistor (R10) connecting said emitter of said sixth transistor (T17) to said emitter of said fifth transistor (T12); fifth and sixth serially connected diodes (T13 and T14), said fifth and sixth serially connected diodes (T13 and T14) being connected between said emitter of said fifth transistor (T12) and said second source of potential (V N ); and said switchable bit up level clamp circuit output terminal (UC) being connected to said emitter of said sixth transistor (T17) and each of said m bit select circuits. The circuit of claim 10, wherein said fifth and sixth serially connected diodes (T13 and T14; Figure 7) are respectively provided by diode connected transistors.

Inventors: CHAN, YUEN HUNG, STRUK, JAMES ROBERT
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1985
Main classification: G11C11
IPC codes: G11C11