ACTIVE LEAKAGE RESISTANCE CONTROL TO IMPROVE NUMERICAL CONVERGENCE IN AN ELECTRONIC CIRCUIT SIMULATOR WHICH SEEKS CIRCUIT SOLUTIONS ITERATIVELY

Abstract: Operation of an electronic circuit simulator is improved by actively controlling the test leakage resistance values at junctions (12) of active devices while seeking stable circuit solutions of modeled circuitry. By choosing an initial junction leakage resistance value lower that the actual value in each active device being modeled, convergent circuit solutions can be easily obtained, which may in turn be used as initial conditions to achieve the circuit solution for the real circuit with a significantly improved effectiveness.

Description: ACTIVE LEAKAGE RESISTANCE CONTROL TO IMPROVE NUMERICAL CONVERGENCE IN AN ELECTRONIC CIRCUIT SIMULATOR WHICH SEEKS CIRCUIT SOLUTIONS ITERATIVELY Background of the Invention This invention relates to electronic circuit simulators and particularly to the SPICE electronic circuit simulator used for the simulation of VLSI circuit operational behavior. VLSI circuit simulation has become a critical tool in the development of operational VLSI circuits. In VLSI circuit design, circuit simulation has essentially replaced circuit bread boarding as a tool for determining the operational characteristics of very large scale integrated circuitry consisting of hundreds of thousands of active devices, such as metal oxide semiconductor (MOS) transistors. The SPICE electronic circuit simulator originated at the University of California, Berkeley about 1972. It has now been in use in at least.2,000 facilities throughout the United States and the world. The SPICE simulator is a public domain simulator typically implemented on a general purpose digital computer, minicomputer or microcomputer having a keyboard terminal input device and display, printer or graphics output devices. The public domain SPICE program is documented in a publication entitled "SPICE2: A COMPUTER PROGRAM TO SIMULATE SEMICONDUCTOR CIRCUITS" by Laurence W. Nagel Memorandum No. ERL-M520, 9 May 1975; Electronics Research Laboratory College of Engineering, University of California, Berkeley and available from the ERL Publications Office, 433 Cory Hall, University of California, Berkeley, California 94720 for a nominal handling charge. The SPICE simulator is generally available in the industry. The published SPICE2 documentation and program listing is incorporated herein by reference and made a part hereof. The typical implementation of the SPICE simulator is as a Fortran program comprising about 20,000 lines of coding compiled for operation on an IBM-type 3081 computer to which are coupled display devices, terminals and printers. A circuit simulator could be a special purpose hard-wired apparatus, but such an apparatus is generally considered to be so complex and expensive as to be impractical as a useful tool. A circuit in a SPICE simulator is defined by a set of equations specifying the operational characteristics of each circuit element and data specifying nodes and branches interconnecting various such circuit devices. A key portion of the simulator is the solution of nonlinear differential equations characterizing the circuit elements employing numerical methods in which a solution is computed iteratively from relatively arbitrary initial conditions. A general purpose computer programmed with SPICE is treated as a dedicated simulation device having defined features and characteristics. A SPICE simulator is well-known to exhibit convergence problems with complex circuits. Specifically, a steady state (D.C.)_solution of a circuit with many active devices is difficult to obtain with the SPICE simulator because of characteristics of the simulator relating to its numerical computation properties. These serious problems frequently discourage VLSI circuit designers and result in unwanted waste of time as well as critical and expensive schedule delays. Consequently, the ability of circuit design teams to perform according to expectations in highly competitive environments is seriously hindered. The problems with SPICE have remained unsolved for many years despite widespread use of the simulator and its well-known shortcomings. However, the SPICE simulator is not the only circuit simulator known to have convergence problems. Nevertheless, the SPICE simulator, because it is in the public domain and so widely used, is a representative environment addressed by the present invention. Summary of the Invention According to the invention, a method is provided for achieving convergence in the circuit solutions of very large scale circuit designs in a SPICE simulator or the like which models circuits employing elements from which is it difficult to obtain convergence of solutions. The technique models real circuits with a smaller junction leakage resistance than is known to exist in the real circuit in order to easily generate circuit solutions to be used as the initial conditions to assist the convergence of the real circuit solution. In the SPICE-like simulators, the typical initial condition is zero volt at each circuit node, which is identified to be a major source of nonconvergence. The present circuit simulator employs an active internal junction leakage resistance control scheme for each active circuit which can select among two strategies for achieving convergence based on intermediate iterative results. The method of the invention is to actively modify the initial junction leakage leakage resistance during computation of a circuit solution to approach the known junction leakage resistance value while maintaining the circuit solution within boundaries calculated to be within conditions for convergence to a stable solution. Two different methods are disclosed. One method which alternatively attempts to obtain a solution with known actual junction leakage resistance values and with a fraction of known actual junction leakage resistance value, which fraction is iteratively increased to develop a set of initial conditions for subsequent iterative computation. A second method attempts to obtain a solution by employing a circuit model wherein a fraction of the known actual junction leakage resistance is a parameter, and then iteratively increased the fraction until a solution is obtained with the known actual junction leakage resistance parameter. In a specific embodiment, active devices with known high internal leakage resistances of are simulated as having an initial leakage resistance of considerably smaller value. The method according to the invention has been tested and proven to assist the convergence toward solutions of numerous difficult to converge circuits. This method will operate with any circuit simulator which seeks solutions to circuit equations iteratively. The invention will be better understood by reference to the following detailed description taken in conjunction with the accompanying drawings. Brief Description of the Drawings Figure 1 is a schematic diagram of a circuit model of a diode showing a model for junction leakage resistance value. Figure 2 is a flow chart of methods according to the invention. Figure 3 is a flow chart for explaining relevant iteration methods of a computer simulation program such as SPICE. Description of Specific Embodiments With reference to Figure 1 there is shown a schematic diagram of a circuit model of a diode showing a diode symbol having a p-n junction 12 defining a cathode terminal 14 and an anode terminal 16. This is a generalized form of a p-n junction model and serves to illustrate models for all other devices, including a variety of transistors, including both junction transistors and field effect transistors. In normal operation, there is a forward biasing voltage V applied between the anode terminal 16 and the cathode terminal 14. Figure 1 shows further a diode model 110 having a cathode terminal 114 and an anode terminal 116 and all relevant features of a p-n junction. In particular, the diode model 110 can be simulated by a bulk resistance R in series with the parallel combination of a junction capacitance C , a current source I_ and a leakage resistance R τ . The bulk resistance in a diode is typically in the range of a few ohms or less. The leakage resistance in a real circuit is typically in the range of one million megohms {1 x 10 12) . The diode current corresponding to the diode current source I_ is given by the well-known relationship: -B = -S (S M - ~ - The solutions of network problems involving such relationships requires the application of iterative numerical techniques which were found to be inadequate to obtain stable solutions consistently. The present invention is a technique for achieving convergence of iterative numerical methods to stable circuit solutions with improved consistency. In accordance with the invention, convergence to a stable solution of an electronic circuit simulator is improved by actively controlling the internal leakage resistance R_ of the active device, such as in the diode model 110, while seeking the stable circuit solutions during normal iterative computation of a nonlinear solution using linearized circuit equations. The method according to the invention dictates that the junction resistance R_ in all diodes and transistors is preset and then subsequently modified in the process of solution. According to a specific aspect of the invention, the junction resistance R τ is initially selected to be one megohm, which is on the order of one millionth of the actual leakage resistance in a real circuit. A strategy is then applied which progressively modifies the junction resistance Rϋ-,. to its final normal junction resistance value of one million megohms. According to specific aspects of the invention, two different strategies may be employed. More specifically, the two different strategies can be employed together serially in an attempt to achieve convergence with minimal outside intervention. With reference to Figure 2, a flow chart illustrating the two strategies according to the invention, the invention is explained. Initially values are preassigned to be used in the generation of the solutions. The value INX is an index for controlling the number of iterations between an initial value of junction resistance RJ and a final value for junction resistance RJFNL. A binary flag is provided under the designation ICONVG. Where ICONVG = 1, a first strategy is employed. Where ICONVG = 2, a second strategy according to the invention is employed. The method of the invention may be so organized so that the second strategy is instituted if the first strategy fails to achieve convergence. Initial values are assigned to an array junction resistance values intermediate of the initial value and the final value for use in the second strategy. In a specific embodiment, the array may consist of ten values indexed from one to ten. The values stored in this array are the initial conditions to be used for each indexed attempt to achieve a convergent solution during the iterative process. The immediately preceding value in the array serves to help develop initial conditions for the next iteration. The last members of the array may be equal to one another and equal to the final normal junction resistance for several iterations of the attempted solution in order to allow the circuit solution to converge to the desired final values for all voltages and currents in the circuit. This characteristic will be apparent upon an examination of the flow chart as hereinafter explained. Finally, an initial value for an update on junction resistance is selected, such as the value RJUP = 0.2. RJUP is a multiplication factor for the junction resistance RJ which is used if the initial strategy does not generate a convergent solution during iteration. Its function will be apparent upon reference to the flow chart. An example of the method according to the invention is as follows. Initially, after assignment of values, the index INX is set to one(l) (Step A) and then tested to see if it is greater than the final desired value for the index, which in this case is 10 (Step B) . If not, thereafter the value ICONVG is tested to determine which strategy is to be used (Step C) . If the first strategy is used, a call is immediately made to the subroutine employed to compute the circuit solution under the given circuit conditions. In a specific embodiment of a SPICE circuit simulator, the subroutine is known as ITER8. If ICONVG is equal to one the initial conditions are those set by the assignment statement without reference to the values in the array. If ICONVG is equal to two, the current value of the junction resistance RJ is set to the array value of junction resistance corresponding to the current index value (Step D) . In either case, a call is subsequently made to the solution computation subroutine, such as the subroutine ITER8 (Step E) . The ITER8 subroutine performs its computations in a conventional manner, returning a flag indicating whether or not a solution has been achieved which is characterized by convergence. The flag used is called IGOOF (Step F) . A convergent solution is indicated by a value IGOOF = 0. A nonconvergent solution is indicated by a value IGOOF = 1. In the event IGOOF equals one, then a test is made using the ICONVG test to determine whether the first strategy or second strategy is in use (Step G) . If the first strategy is in use, the initial value for RJ is updated by decreasing the junction resistance value by a factor according to the value RJUP (Step H) . In this example, the RJUP is equal to 0.2. An initial value of one megohm would therefore be reduced to an initial value of 200 kilohms. The method would then be reinitiated by returning to Step A and incrementing the index INX (Step A) . Alternatively, if the second strategy is in use, there is no need to use RJUP, since in the second strategy, it has already been determined whether an initial value for junction resistance exists which produces a convergent solution. Returning to Step F, assuming that a convergent solution has been generated using the ITER8 subroutine, a test is made to determine if the current value for junction resistance RJ is equal to the designated final value for junction resistance (Step J) . If the circuit simulator is operating in its conventional mode, the junction resistance RJ will equal the final junction resistance and therefore this exercise was not necessary. However, in accordance with the invention, the initial junction resistance is not equal to the final junction resistance and at least one iteration is required to determine whether the convergent solution has been achieved. Therefore, a test is made to determine whether the first strategy or the second strategy is in use (Step K) . If the first strategy is in use, then the value for junction resistance RJ is set to the final value RJFNL (Step L) . Thereupon, Step A, Step B, Step C and Step E are performed as before. The circuit solution routine returns the value IGOOF indicating whether or not a convergent solution has been found (Step F) . If in this instance, a convergent solution is also found, then the test is performed to determine if the current value junction leakage resistance is equal to the final value junction leakage resistance RJFNL (Step J) . If the test is affirmative, then an output indication is given in the form of a suitable signal indicating that the solution is convergent (Step M) . Thus according to the invention, at least two iterations of the circuit solution subroutine are required to establish existence of a convergent solution. The power of the invention, however, lies in its ability to adjust the value of junction leakage resistance during attempts to solve the circuit iteratively. For example, it has already been shown that the initial junction resistance can be downwardly adjusted (Step H) to adjust the circuit conditions toward a point where a convergent solution is more likely to be achieved. This downward adjustment can take place at any time an indication is given that a nonconvergent solution has been obtained. Thus, as an attempt is made to increment the junction leakage resistance toward the desired high value, the update step (Step H) can be used to re-adjust downwardly the junction resistance whenever the ITER8 subroutine fails to retain its range of solutions within the conditions defining convergence. According to the first strategy, an attempt is made to determine whether convergence can be achieved by substituting the final junction resistance value for the current junction resistance value whenever a convergent solution has been obtained through Step E. Because of the circuit solution obtained after the first ITER8 subroutine call will form a good guess of the real solution, there is a reasonable chance that the final solution can be achieved relatively rapidly for the real circuit with RJ=RJFNL during the second visit to the ITER8 routine. However, if after ten iterations of the index INX, a convergent solution has not been achieved by this method of adjusting junction resistance using Step L and Step H to modify the junction resistance value, a different strategy is used to attempt to achieve convergence. In this second strategy, the first step is to test whether the second strategy has already been used (Step N) . If it has been used, then the consequence is that no convergent solution has been found (Step P) . The computation is then terminated (Step Q) . If on the other hand the second strategy has not yet been used, the convergence index is set to 2 (Step R) and the iteration index INX is reset to zero(0) (Step S) . Control then returns to Step A and the various tests are instituted once again. Step C, for example, tests to determine whether the first strategy or second strategy is to be utilized. If the second strategy is to be utilized, then the junction resistance RJ is updated to correspond to the predetermined value stored in the junction resistance array RJARY(INX) of the corresponding index (Step D) . Thereupon a call is made to the ITER8 routine (Step E) , and a value is returned indicating whether or not convergence has been achieved. If convergence has not been achieved, the process is repeated beginning with Step A through the test of Step F until such time as a convergent solution is found which corresponds to the final value of the junction resistance RJFNL. For any of the strategies employed, the procedure is complete and a good solution is obtained as soon as the convergent criteria have been satisfied with the final junction resistance RJFNL. For purposes of explaining the environment, reference is made to Figure 3. Figure 3 illustrates a typical circuit solution subroutine, such as the ITER8 subroutine employed by the SPICE circuit simulator. It is a subroutine which employs linearized circuit equations to solve nonlinear equations. Referring to the first step (Step AA) , initial counters are preset, such as a counter called ITER, to initial values. In this case ITER is initially set to zero. Thereafter, the counter ITER is incremented (Step BB) . A test is made to determine whether the counter ITER exceeds a maximum preselected iteration, such as a value of 200, which is stored in a register represented by a value ITMAX (Step CC) . If the convergence criteria are not satisfied, the subroutine is terminated and a flag is set indicating that no solution has been obtained. This is the flag IGOOF = 1 (Step DD) used to signal the method according to the invention. If on the other hand the maximum allowable number of iterations has not been exceeded, the circuit matrix coefficients and source terms for the circuit under consideration are loaded into the designated registers for computation (Step EE) . Thereafter, the linearized circuit equations may be solved, as for example by direct matrix inversion (Step FF) . Direct matrix inversion solutions have an advantage of exact solutions to a system of linear equations. However, other methods of solving the circuit equations may also be used. After the solution of the linearized circuit equations have been obtained, convergence tests are applied to the solutions to determine whether the convergence criteria have been satisfied (Step GG) . Examples of convergence criteria are small differences in successive solutions obtained by iterative computation. If the convergence criteria are not satisfied, then the steps beginning with Step BB are repeated until the convergence criteria are satisfied or the number of iterations exceeds the maximum number allowable. If a solution is obtained which satisfies the convergence criteria then the value IGOOF = 0 is returned for use by the method according to the invention (Step HH) . The invention has now been explained with reference to specific embodiments. For example, selected embodiments may be used in the environment of a SPICE circuit simulator. The invention may also be implemented in connection with other circuit simulators which attempt to solve circuit equations which are subject to concerns about convergent solutions. Such circuit simulators are always iterative in nature. Therefore it is not intended that this invention be limited except as indicated the appended claims.

Claims: CLAIMS : 1. For use in a circuit simulator which seeks solutions to circuit equations iteratively, a method for improving convergence of circuit evaluation solution comprising the steps of: (a) modifying models of junctions of semiconductor devices in said circuit simulator so as to render a test junction leakage resistance value equal to substantially less than an actual junction leakage resistance value thereby to allow for the 0 simulation of less stringent current conditions of said circuit model; thereafter (b) employing said circuit model so modified to generate reasonable initial conditions at each circuit node and on each circuit branch of said circuit 5 model; thereafter (c) iteratively computing circuit node voltages and circuit branch currents to seek a convergent circuit solution; thereafter (d) whenever a convergent circuit solution is 0 attained, remodifying said junction models so as to render said test junction leakage resistance value more like said actual junction leakage resistance value and otherwise remodifying said test junction leakage resistance value less like said actual junction leakage 5 resistance value; and thereafter (e) repeating Steps (c) and (d) until a convergent circuit solution is attained with said test junction leakage resistance value equal to said actual junction leakage resistance value. Q 2. The method according to claim 1 wherein said remodifying step comprises setting said test junction leakage resistance value to said actual junction leakage resistance value whenever a convergent circuit solution. 3. The method according to claim 1 wherein said remodifying step comprises incrementally increasing said test junction leakage resistance value toward said actual junction leakage resistance value after every said computing step. 4. The method according to claim 1,2 or 3 wherein said modifying step comprises setting said test junction leakage resistance value to an initial value of less than one ten thousandth of said actual junction leakage resistance value. 5. The method according to claim 1,2 or 3 wherein said modifying step comprises setting said test junction leakage resistance value to an initial value of less than one millionth of said actual junction leakage resistance value.

Inventors: BURKHARDT ROBERT JOHN, FANG SHENG, WANG SANG S, BURKHARDT, ROBERT, JOHN, FANG, SHENG, WANG, SANG, S.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1985
Main classification: G06G7
IPC codes: G06F17, G06F19