DATA DELAY/MEMORY CIRCUIT

Abstract: A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters (I1-I7). The data delay/memory circuit also includes a clock generator (CG) for supplying the clocked inverters (I1-I7) with clock signals (1-7, 1 - 7 ). These clock signals (1-7, 1 - 7 ) have individual clocking phases and are sequentially generated such that the clocking phase for a final stage (I7) of the data latch circuits is ahead of that for an initial stage (I1) thereof.

Description: The present invention relates to a data delay/memory circuit which memorizes input data for a given period of time and, thereafter, outputs the memorized data. Signal processing for temporary memorizing and delaying a digital signal is conventionally effected in a digital 1H memory which delays by one horizontal period of time (1H) a horizontal video signal of a digital TV, in a digital filter, in a deinterleave circuit of a compact disc player, or in the like. In a prior art data delay/memory circuit used for the above exemplified applications, a plurality of cascade-connected one-bit shift registers are conventionally adapted. The number of the cascade connections depends on the circuit design. Each of these one-bit shift registers comprises a pair of clocked inverters for latching input data. One clocked inverter of the pair operates in synchronism with a clock signal, while the other clocked inverter operates in synchronism with an antiphase clock signal. According to such a prior art data delay/memory circuit, a one shift register is inevitably provided for storing each one bit data. Consequently, the necessary number of the data latching, clocked inverters has to be twice the number of the one bit shift registers. If a 1H memory of a digital TV which requires a large memory capacity of, e.g., 1135 bits is constituted by such a data delay/memory circuit, the number of circuit elements becomes numerous. For this reason, when such a data delay/ memory circuit is circuit-integrated, a prominently large chip size is required, resulting in a decrease of the yield of IC manufacture while incresing the cost thereof. Prior art document JP-A-59 119 594 (Patent Abstracts of Japan, vol. 8, no. 248 (P-313) (1985), 14th November 1984) discloses a dynamic shifting circuit which is equipped with an initial stage CMIS circuit consisting of a first N-channel MIS transistor, a second P channel MIS transistor and a trailing stage CMIS circuit consisting of a third N channel MIS transistor and a fourth P channel MIS transistor. The source of the second transistor is connected to an electric power source, and an input signal is applied from the source of the first transistor. Further, a clock pulse is supplied to the gates of the first, second and third transistors. The drains of the first and second transistors are connected in common, led out as an output of the initial stage CMIS circuit, and inputted to the gates of the third and fourth transistors. The drains of the third and fourth transistors are connected to each other and let out to an output terminal. It is an object of the present invention to provide a data delay/memory circuit which allows for a decrease in the necessary number of circuit elements for one bit, thereby reducing the size of the IC chip and improving the yield of IC manufacture. To solve this object the present invention provides a data delay/memory circuit as stated in claim 1. A data shift circuit is formed with a plurality of multiply or serially cascade-connected data latch circuits, the plural data latch circuits being controlled by different clock signals. These clock signals have individual clocking phases and are sequentially generated in such a manner that the clocking phase for a final stage of the data latch circuits is ahead of that for an initial stage thereof. According to the present invention (N + l) data latch circuits satisfactorily constitute an N bit data delay/ memory circuit. The necessary number of circuit elements per one bit can be effectively decreased, thereby reducing the chip size of the IC and lowering the manufacturing cost. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a basic configuration of a data delay/ memory circuit according to an embodiment of the present invention; Figs. 2A to 2 O show a timing chart explaining the circuit operation of Fig. 1; Fig. 3 shows a circuit configuration of one application of the Fig. 1 circuit; Figs. 4A to 4V show a timing chart explaining the circuit operation of Fig. 3; Fig. 5 shows an arrangement of the wiring for feeding clock signals applied to the circuit of Fig. 3; Fig. 6 shows a digital low-pass filter utilizing the circuit of Fig. 3; Fig. 7 shows a digital high-pass filter utilizing the circuit of Fig. 3; Fig. 8 shows a deinterleave circuit for a CD (compact disc) to which the circuit of Fig. 3 is applied; Fig. 9 is a timing chart partially showing the relation between input data and output data; and Figs. 10A to 10E respectively show modifications of each of the latch circuits (I1 to I7) in Fig. 1. In the following, preferred embodiments of this invention will be described with reference to the accompanying drawings. Fig. 1 shows a circuit configuration of a data delay/memory circuit according to one embodiment of the present invention. This circuit is designed to memorize and to delay 6-bit data. In the figure, seven clocked inverters I1 to I7 are multiply or serially cascade-connected. Each of these clocked inverters may be made of a CMOS circuit formed with P-channel and N-channel MOS transistors. The gates of the N-channel MOS transistors receive clock signals 1 to 7. The gates of the P-channel MOS transistors receive clock signals 1 to 7 , which are antiphased to clock signals 1 to 7, respectively. Clock signals 1 to 7 and 1 to 7 are obtained from a clock generator CG. (The generation timing of these clock signals 1 to 7 and 1 to 7 are shown in Figs. 2A to 2G.) Input data Din is supplied to the initial stage clocked inverter I1 and, after a certain time delay, the final stage clocked inverter I7 delivers output data Dout corresponding to the input data Din. As seen from the timing chart of Figs. 2A to 2G, and from the circuit configuration of Fig. 1, the individual phase delays of clock signals 1 to 7 (or 1 to 7 ) are gradually increased from the final stage side (17) toward the initial stage side (I1). The above clocked inverters I1 to I7, which are controlled by clock signals 1 to 7 and by antiphase clock signals 1 to 7 , constitute a dynamic data latch circuit. Figs. 2A to 2 O show a timing chart illustrating the clock signals as well as the contents of data latched in the clocked inverters of Fig. 1. The circuit operation of the Fig. 1 embodiment will be described below with reference to this timing chart. Assume that, immediately after the generation of clock signal 7, which is supplied to initial stage clocked inverter I1 at time t10, the contents of data D1, output from initial stage clocked inverter I1 becomes α6 (after t10 in Fig. 2I). Also assume that output data D2 to D7, from the following clocked inverters I2 to I7, are α5 , α4 , α3, α2 , α1 and α0 , respectively, at time t10 (Figs. 2J-2 O ). According to the Fig. 1 circuit, initial clock signal 1, to be generated first, is supplied to clocked inverter I7 which constitutes the final stage of the cascade-connected seven clocked inverters I1 to I7. When clock signal 1 is generated under the above assumption (t12 in Fig. 2A), final stage clocked inverter I7 inverts the phase of data D6, output from preceding clocked inverter I6 (from α1 to α1 in Figs. 2N and 2 O ). Thus, after the generation of clock signal 1, the contents of output data Dout from final stage clocked inverter I7 are changed from α0 to α1 (after t12 in Fig. 2 O ). Further, when the subsequent clock signal 2 is generated (t12 in Fig. 2B), clocked inverter I6 is operated so that the phase of data D5, output from clocked inverter I5, is inverted. After generation of clock signal 2, the contents of data D6, output from clocked inverter I6, are changed from α1 to α2 (after t14 in Fig. 2N). Similarly, clocked inverters I5 to I2 are sequentially operated by the subsequent generation of clock signals 3 to 6 (Figs. 2C to 2F), so that the respective outputs from the preceding stages are sequentially phase-inverted. After completion of the generation of these clock signals, the contents of output data D5 to D2 from clocked inverters I5 to I2 are set at α3 (after t16 in Fig. 2M), α4 (after t18 in Fig. 2L), α5 (after t20 in Fig. 2K) and α6 (after t22 in Fig. 2J), respectively. When clock signal 7 is generated (t24 in Fig. 2G), the initial stage clocked inverter I1 is operated so that the phase of input data Din is inverted (from α7 to α7 in Figs. 2H and 2I). After the generation of clock signal 7, the contents of output data D1, from initial stage clocked inverter I1, are changed from α6 to α7 (after t24 in Fig. 2I). During the period from time t10 to t24, seven clocked inverters I1 to 17 store at least 6 bits of data. The minimum bit number 6 of the stored data is obtained when the same data is stored in two clocked inverters. For instance, at time t17, clocked inverter I4 stores data α3 (Fig. 2L) which is substantially the same as the data α3 (Fig. 2M) stored in clocked inverter I5, except for its phase. According to the circuit configuration of the above embodiment, storing and delaying of 6 bits of data can be achieved only by seven clocked inverters. When the number of the circuit elements of the present invention is compared with that of the said prior art circuit, five clocked inverters can be saved according to the present invention. Generally speaking, according to the present invention, (N + l) clocked inverters are satisfactory to achieve the storing and delaying of N bits data. From this, the number of elements required for the circuit integration is considerably reduced when the bit number of the circuit is large. Accordingly, the IC chip size and IC manufacturing cost can also be effectively reduced. In the above embodiment, many data transferring clock signals 1 to 7 are employed. These clock signals may be simply obtained by frequency-dividing a master (or system) clock signal delivered from an oscillator. In this case, the period of these transferring clock signals 1 to 7 is longer than that of the master clock signal, and the required data transfer rate can be lowered beyond that required when the data transfer is carried out with the master clock signal in conjunction with its phase-inverted signal, this being one of the advantages obtained by the configuration of Fig. 1. Fig. 3 shows a circuit configuration of a typical application of the present invention. According to this circuit application, a high data transferring rate based on master clocks (s1, s2) can be obtained while enjoying the advantage (reduction in the required number of the circuit elements) of this invention. According to a data delay/memory circuit of this application, six data delay/memory circuits, DMC1 to DMC6, each of which may have the same configuration as Fig. 1, are parallel arranged, thereby achieving 6 bits data storing and delaying. The data input side of DMC1 to DMC6 is coupled to a data serial/parallel converter circuit SPC. Converter SPC includes 6 sets of cascade-connected data delay circuits DL10 to DL20. Circuits DL10 to DL20 are respectively formed with CMOS clocked inverter pairs I10 to 121, each pair of which is controlled by dual-phase master clock signals s1 and s2. The data output sides of DMC1 to DMC6 are coupled to a data parallel/serial converter circuit PSC. Converter PSC includes 6 sets of cascade-connected data delay circuits DL22 to DL32. Circuits DL22 to DL32 are respectively formed with CMOS clocked inverter pairs I22 to I33, each pair of which is controlled by dual-phase master clock signals s1 and s2. Respective outputs Din1 to Din6, from data delay circuits DL10 to DL20, in SPC are supplied to DMC1 to DMC6. Respective delayed output data Dout1 to Dout6, from DMC1 to DMC6, are supplied to the corresponding data delay circuits DL22 to DL32 in PSC. The above converter circuit SPC distributes to DMC1 to DMC6 the serial data (numbered by 0-41) supplied to the initial stage (DL10) of data delay circuits, in accordance with the dual-phase master clock signals s1 and s2. Conversely, converter circuit PSC progressively delays output data Dout1 to Dout6 for each one bit of the data delay circuits in synchronism with the dual-phase master clock signals s1 and s2, so that the delayed parallel data Dout1 to Dout6 are sequentially converted into serial data, and transferred to the circuit end (I33) of PSC. Data Dout1 to Dout6 are obtained by the distributing operation of SPC, and are stored and delayed in parallel by DMC1 to DMC6. Figs. 4A to 4V show a timing chart explaining the circuit operation of Fig. 3. Assume a case wherein 41st to 36th data, as shown at time t4O in Figs. 4J to 4 O , are supplied to DMC1 to DMC6 as input data Din1 to Din6. Assume further that DMC1 to DMC6 respectively store individual data numbered as shown in Fig. 3. In this case, the respective contents of parallel output data Dout1 to Dout6, from DMC1 to DMC6, become 5th to 0th data as shown in Figs. 4P to 4V. Output data Dout1 to Dout6, from DMC1 to DMC6, are sequentially transferred via respective data delay circuits DL22 to DL32, operated in synchronism with master clock signals s1 and s2. Then, final output data DY which is synchronized with master clock signals s1 and s2 is delivered from the circuit end of PSC. Thus, the rate of data transfer can be made substantially the same as the master clocking rate, according to the circuit configuration of Fig. 3. In addition, according to this circuit arrangement, only 66 circuit elements (42 elements for DMC1 to DMC6, 12 elements for SPC, and 12 elements for PSC) are necessary to constitute a 36 bits data delay/memory circuit (which is formed with 6 bits x 6 DMC blocks). In contrast, according to a prior art circuit depending on master clock signals alone, 72 circuit elements (= 36 bits x 2) are required. Thus, 6 circuit elements can be saved according this embodiment, the number of saved circuit elements being much increased as the number of bits becomes large. Fig. 5 shows a wiring arrangement for clock signals when DMC1 to DMC6 in the embodiment of Fig. 3 are arranged in parallel in the IC. As may be seen from Fig. 5, wirings W10 to W23, for feeding respective clock signals (1-7 & 1 - 7 ), are arranged perpendicular to the data transferring direction (horizontal in the figure) of seven cascade-connected clocked inverters I1A to I7A. When such a wiring arrangement is employed, the total area of the wiring pattern is smaller than that where respective data delay/memory circuits utilize individual wirings which are parallel along the data transferring direction of clocked inverters I1A to I7A. Fig. 6 shows a digital low-pass filter utilizing the circuit of Fig. 3. A digital input signal DX is supplied to a data delay/memory circuit 100 which may have the circuit configuration of Fig. 3. Input signal DX may be obtained by A/D converting an analog voice signal, video signal or the like. A digital output signal DY is supplied to an adder 60. Input signal DX is added to output signal DY in adder 60. An output signal DZ from adder 60 has an amplitude component double that of input signal DX. Prescribed high frequency components of signal DZ are filtered off by the circuit operation of Fig. 6. Fig. 7 shows a digital high-pass filter utilizing the circuit of Fig. 3. Digital input signal DX is supplied to data delay/memory circuit 100 having the circuit configuration of Fig. 3. Input signal DX may be obtained by A/D converting an analog video signal or the like. When input signal DX is a video signal, the delay time of the Fig. 3 circuit is selected to be one horizontal scanning period (1H) of a TV system. Digital output signal DY is supplied to the negative input of a subtracter 70. Input signal DX is supplied to the positive input of subtracter 70. Output signal DZ from subtracter 70 corresponds to DX - DY. Prescribed low frequency components of signal DZ are filtered off by the circuit operation of Fig. 7. Fig. 8 shows a deinterleave circuit for a CD (compact disc) to which the circuit of Fig. 3 is applied. Fig. 9 is a timing chart showing the relation between input data IN and output data OUT of the Fig. 8 circuit. In this deinterleave circuit, a delay time D is assumed to be 4T, where T denotes a period of each of the data of the CD. Since D = 4T, five clock signals 0 to 4 are provided. Each of these clock signals 0 to 4 has an individual phase, as in the case of the Fig. 3 embodiment (cf. Figs. 4C-4G), and is supplied to data delay/memory circuits DMC1 to DMC27. According to the circuit operation of Fig. 8, interleaved data IN is deinterleaved as shown in Fig. 9. Figs. 10A to 10E, respectively, show modifications of each of latch circuits I1 to I7 in Fig. 1. The latch circuits of Fig. 1 are dynamic clocked inverters. In contrast, the latch circuit of Fig. 10A is a static latch formed of a clocked inverter. The latch circuit of Fig. 10B is a dynamic latch formed of a transmission gate being formed with P and N channel MOS transistors. The latch circuit of Fig. 10C is a dynamic latch formed of a transmission gate being formed with an N channel MOS transistor. The latch circuit of Fig. 10D is a static latch formed of a transmission gate being formed with P and N channel MOS transistors. The latch circuit of Fig. 10E shows another static latch formed of a clocked inverter. The present invention should not be limited to the above-mentioned embodiments, various modifications can be made thereof. Although the circuit of Fig. 3 employs six data delay/memory circuits DMC1 to DMC6 arranged in parallel with each storing and delaying 6 bits of data, the number of bits of each DMC1 to DMC6 may differ from the number of the parallel arranged data delay/memory circuits. For instance, twelve data delay/memory circuits, each of which stores and delays 6 bits of data, may be parallel arranged. In this case, the period of clock signals used for controlling the clocked inverters of the respective data delay/memory circuits becomes double the period needed when six data delay/memory circuits are parallel arranged, thereby increasing the margin of circuit operation. If the above circuits are circuit-integrated, and the design center of an operation speed is set at low, small size circuit elements can be used in the IC. From this, reduction in both the size of the IC chip and the cost of IC manufacturing can be achieved.

Claims: A data delay/memory circuit comprising: a data shift circuit formed of a plurality of at least three clock-controlled data latch circuits (I1-I7) which are cascade-connected; characterized by means (CG) for supplying said plurality of at least three data latch circuits (I1-I7) with clock signals (1-7) having individual clocking phases and being sequentially generated such that the clocking phase (1) for a final stage (I7) of said data latch circuits (I1-I7) is ahead of that (7) for an initial stage (I1) of said data latch circuits (Fig. 1). A data delay/memory circuit according to claim 1, characterized in that each of said data latch circuits is of a dynamic type. A data delay/memory circuit according to claim 2, characterized in that said dynamic data latch circuits include clocked inverters. A data delay/memory circuit according to claim 1 , characterized in that said supplying means (CG) is provided with wirings (W10-W23) for feeding said clock signals (1-7) which geometrically cross the data transfer direction of said cascade-connected plural data latch circuits. A data delay/memory circuit according to claim 1, characterized by comprising: a plurality of data delay/memory circuits (DMC1-DMC6) each being formed of said plurality of at least three clock-controlled and cascade-connected data latch circuits (I1A-I7F); serial/parallel converter means (SPC), coupled to said data delay/memory circuits (DMC1-DMC6) and responsive to serial input data (DX), for supplying respective input terminals of said data latch circuits (I1A-I1F) with data (Din1-Din6) having individual phases with respect to said serial input data (DX); and parallel/serial converter means (PSC), coupled to said data delay/memory circuits (DMC1-DMC6), for converting data (Dout1-Dout6) delivered from the respective output terminals of said data latch circuits (I1A-I1F) into serial output data (DY). A data delay/memory circuit according to claim 5, characterized in that each of said serial/parallel converter means (SPC) and said parallel/serial converter means (PSC) is controlled by a master clock signal and formed of a plurality of cascade-connected data delay circuits (DL10-DL20, DL22-DL32). A data delay/memory circuit according to claim 5, characterized in that each delay time of the respective signals in said plural data delay/memory circuits (DMC1-DMC6), which are associated with said serial/parallel converter means (SPC) and said parallel/serial converter means (PSC), is set at a prescribed value.

Inventors: NOSE, SIGERU C/O PATENT DIVISION, SUZUKI, SEIGO C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: G11C19
IPC codes: G11C19, H03K5