A RATIOLESS FET PROGRAMMABLE LOGIC ARRAY

Abstract: A ratioless, zero d.c. power dissipating FET programm­ able logic array including a column boost capacitor for main­ taining the columns of selected AND array transistors at ap­ proximately their precharged voltage while their associated OR array transistors are being evaluated.

Description: This is an invention in integrated circuits. In particularly, the invention concerns a logic array including a plurality of FETs connected in sets to perform AND functions and OR functions, each FET having a gate and first and second conducting regions, the gates of said AND FETs serving as inputs for said logic array, a separate column conductor for each AND set connecting together one of the conducting regions of each FET in its associated AND set, a separate row conductor for each OR set connecting together the first conducting region of each FET in its associated OR set, selection means selecting a particular combination of one or more AND sets for operation in conjunction with the operation of one or more OR sets. From e.g. the digest papers of the ISSCC, 10 th of February 1982, pages 60-61 it is known that programmable logic arrays are arranged in two matrices usually referred to as the AND and OR matrices or the AND and OR arrays. The matrices show vertical and horizontal conductors called columns and rows. Field effect transistor (FET) programmable logic arrays (PLAs) have been made with a resistance ratio between their input and their load transistors. These usually operate by precharging only one array, either the AND array along the vertical column conducting lines or the OR array along the horizontal row conducting lines. FET PLAs are also known which operate by precharging both the AND array and the OR array but these require multiple clock signals and/or additional logic circuitry between the AND and OR arrays to operate properly. It is an object of this invention to provide a ratioless FET PLA in which both its AND and OR arrays are precharged. It is a further object of the invention to provide a self-timed PLA, which does not require multiple clock signals or additional logic between its AND and OR arrays in order to operate. Another object of the invention to provide a PLA, which operates without quiescent, i.e. direct current, power dissipation. The invention is set forth in independent claim 1. One of the advantages of the invention is that the FETs which comprise the arrays can be made of minimum size. Other objects, features and advantages of the invention will become apparent to those skilled in the art from the following description when considered in conjunction with the appended claims and the accompanying drawing in which: Figure 1 is a schematic diagram of an input circuit of the invention; Figure 2 is a schematic diagram of a PLA comprising an AND or OR array of the invention, and Figure 3 is a timing diagram of representative signals of the invention. Referring to Figure 1, there is shown a latch 11 which produces a binary 1 output from terminal Q or Q depending upon whether a binary 1 signal or a binary 0 is applied along line IN. A binary 1 signal from output Q causes transistors Q1, Q2 and Q3 to produce a binary 1 along line I i whenever a binary 1 signal appears along line EV. At the same time a binary 0 is applied from output Q and transistors Q4, Q5 and Q6 produce a binary 0 along line I i . A binary 1 signal from output Q and a binary 0 from output Q when a binary 1 signal appears along line EV causes transistors Q1, Q2 and Q3 to provide a binary 0 along line I i and transistors Q4, Q5 and Q6 to produce a binary 1 along line I i . Binary 0's appear along both lines I i and I i whenever a binary 0 appears on line EV. As is understood lines I i and I i and other input lines are connected as inputs to the AND arrays as representatively shown for line I i in Figure 2. Transistors Q1, Q2 and Q3 and transistors Q4, Q5 and Q6 comprise two AND gates whose inputs are the signal along line EV and the signals from outputs Q and Q , respectively. In Figure 2 an embodiment of a programmable logic array 1 in accordance with the invention has been shown. Shown in Figure 2 are FETs QA 1i , QA mi ...QA 1n which represent all of the FETs of the sets of FETs which perform an AND function. In the disclosed embodiment each AND FET is an n-channel IGFET. Also shown in Figure 2 are FETs QO 1l QO 1z , QO mz , which represent all of the FETs of the sets of FETs connected to perform an OR function. In the disclosed embodiment each OR FET is an n-channel IGFET. As those skilled in the art understand in accordance with the functions it is desired that the PLA 1 perform, the AND array will comprise one or more sets 1...n of FETs connected such as transistor QA 1i , QA mi , QA 1n . Each separate AND set's FETs are connected in parallel between ground and an associated column conductor such as COL₁ and COL m . Each column conductor such as COL₁, COL m connects together one of the conducting regions such as the drain of each FET such as QA 1i in its associated AND set (e.g. QA 1n ). The OR array of the PLA 1 comprises a plurality of FETs such as QO 1l connected in parallel between associated row conductors such as ORROW l and common conductor VG l . Each row oonductor such as ORROW l ; ORROW z connects together the first conducting region such as the drain of each FET such as QO 1l ; QO 1z , QO mz in its associated OR set. Common conductor VG l ,VG z connects together the second conducting region such as the source of all FETs such as QO 1l , QO 1z , QO mz , which perform an OR function in the PLA1. It is also possible to interconnect all common conductors VG l , VG z . Transistors QPA₁, QPO l and QPG l serve as means for precharging the column conductors such as COL₁, the row conductors such as ORROW l and the common conductor VG l . If all common conductors VG l to VG z are interconnected only a single precharge transistor QPG will be necessary. If so the size of the PLA1 will be reduced. Transistors such as QPA₁...QPA m , QSA₁...QSA m , QPO l ...QPO z and QSO l ...QSO z are provided for each column 1...m and each row l...z in the PLA1. Transistor QPR provides a means for charging line TREFC to the voltage VDD. Transistor QAR provides a means for pulling line TREFC to ground upon the application of a binary 1 signal along line TRR. Transistors QSA₁...QSA m QSR and QSO l ...QSO z are high resistance devices used as sustaining transistors. If the cycle rate of the PLA₁ were fast enough to refresh the storage nodes before any leakage occurs these last mentioned devices may be eliminated thereby further reducing the size of the PLA₁. A separate column boost capacitor such as CB₁...CB m is provided for each column conductor COL₁.. COL m in the array. Column boost line COLB connects to the bottom plate of all the column boost capacitors such as CB₁ ... CB m of the PLA₁. Inverter INV1 applies a binary 1 signal to the gates of transistors QDG l ...QDG z and along column boost line COLB to the column boost capacitors such as CB₁...CB m upon the application of a binary 0 along line TREFC. Output inverters such as INV l ...INV z produce binary 1 signals along their associated output lines such as PO l ...PO z upon the application of a binary 0 along their associated row conductors such as ORROW l ...ORROW z . A separate row conductor such as ORROW l , an inverter such as INV l and an output line such as PO l is provided for each OR set l...z of the PLA₁. In operation prior to an evaluation mode, with line EV low, lines PC go high and causes column conductors COL₁...COL m , row conductors ORROW l ...ORROW z and common conductors VG l ...VG z approach V DD voltage. The precharging of common conductor VG l ...VG z allows OR array outputs such as ORROW l ...ORROW z to be precharged even though gates of its associated OR array transistors such as QO 1l are at a binary 1 level (due to the precharge of the column conductors COL₁...COL m ). If the FETs QO 1l ...QO mz have a sufficient high conductivity (have a sufficient width to length ratio) then the transistors QPG l ...QPG z can be dispensed with, After the forementioned prechargings, lines PC go low and the evaluation mode can begin. To start an evaluation, line EV goes high (binary 1) keeping line I i low and causing line I i to go high (binary 1) provided a binary 0 is on output Q. (All, selected AND transistors have binary 0's on their gates via the selected I i lines since binary 0's are applied to the inputs of their associated latches such as 11 of Figure 1 select their associated transistors). At the same time that the unselected lines (1 ≦ i ≦ n) I i go high, line TRR goes high (binary 1) causing transistor QAR to turn on, A binary 0 on line I i and all other selected input lines keep transistor QA 1i ...QA mi and all other selected transistors in the AND array turned off. Being turned off the selected transistors in the AND array cause their column conductors such as COL₁...COL m to remain high at approximately their precharge voltages. The column conductors for unselected transistors in the AND array are driven to ground (binary 0) by the fact that their unselected transistors are turned on (e.g. COL₁ is driven to ground if QA 1n is turned on via unselected line I n ). At the same time, transistor QAR drives line TREFC to ground after having been turned on by the binary 1 on line TRR. A binary 0 on line TREFC causes inverter INV1 to produce a binary 1 at its output. This produces a boosting voltage on both plates of the boost capacitors, such as CB₁...CB m , associated with each of the selected AND array column such as COL₁...COL m . As a result the selected columns such as COL m are maintained at a high voltage (see Figure 3). The unselected AND array columns e.g. COL₁ at this time are at ground (binary 0) by reason of their transitors QA 1n being on. These columns, therefore, will discharge any coupled voltage on the top plate of their associated boost capacitors (CB₁) and stay at binary 0. When transistors QDG l ...QDG z are turned on by the binary 1 at the output of inverter INV1, they drive common conductors VG l ...VG z to ground. This allows the OR FETs QO mz connected to selected columns to turn on and drive their associated conductors such as ORROW z to binary 0. Selected rows such as ORROW z by being driven to binary 0 cause their associated inverters such as INV z to produce binary 1's on the associated array output lines such as PO z . The OR FETs QO 1z , QO 1l associated with unselected columns COL₁ are not turned on and consequently their row lines ORROW₁ may remain at their precharged voltages (see Figure 3). As a consequence, the array outputs PO l associated with such rows remain at binary 0. As can be seen, the inputs to the array such as I i act as a selection means which enable the selection of a particular combination of one or more AND sets for operation in conjunction with the operation of one or more OR sets in accordance with a particular function it is desired that the array perform.Included in the selection means are a delay means comprising transistor QAR, line TREFC, inverter INV1, boosting capacitors such as CB₁...CB m , the precharge transistor QPG l ...QPG z common conductors VG₁...VG z and discharge transistors QDG l ...QDG z . By designing the delay means to operate more slowly than any AND set in the PLA the delay means delays the operation of all of the OR sets associated with any particular function of the PLA until the selected one or more AND sets associated with that function have all operated. It is to be understood by those skilled in the art that the disclosed array may be implemented in NMOS or CMOS. Various modifications of the above arrangement will be evident to those skilled in the art. In one of these a delay circuit could be substituted for transistors QAR, QPR and QSR and inverter INV1. This delay circuit would be operated when the signal on line TRR goes high and after its delay would provide a boosting voltage on all selected boosting capacitors such as CB₁...CB m . From the foregoing it can be seen that there is no quiescent or direct current power dissipation in this PLA. It is to be understood that the arrangement described herein is for illustrative purposes and is not to be considered restrictive.

Claims: A logic array including a plurality of FETs (QA,QO) connected in sets to perform AND functions and OR functions, each FET having a gate and first and second conducting regions, the gates of said AND FETs (QA) serving as inputs for said logic array, a separate column conductor (COL) for each AND set connecting together one of the conducting regions of each FET in its associated AND set, a separate row conductor (ORROW) for each OR set connecting together the first conducting region of each FET in its associated OR set, selection means (I) selecting a particular combination of one or more AND sets for operating in conjunction with the operation of one or more OR sets, the logic array including a common conductor (VG) connecting together second conducting regions of all FETs performing an OR function, and precharging (QPA,QPO) precharging said column conductors and row conductors, characterized in that said precharging of said column conductors and said row conductors takes place simultaneously, said selection means including delay means (QAR,TREFC,INV₁,CB,QPG,VG,QDG) the delay means being actuated in synchronism with the signals on the inputs of said logic array, for delaying the operation of all said one or more OR sets associated with a particular function until said selected one or more AND sets associated with that function have all operated. A logic array according to Claim 1, characterized in that said delay means includes means (QDG) for discharging said common conductor line prior to the operation of said one or more OR sets. A logic array according to Claim 2, characterized in that said selection means includes a boosting capacitor (CB) for each column conductor, each said capacitor associated with a selected AND set being charged by the operation of said delay means to assure proper operations of the selected one or more AND sets. A logic array according to Claim 3, characterized in that said delay means includes a pulldown transistor (QAR) whose output is connected to an inverter (INV₁) the operating time of said transistor and inverter being longer than the operating time of any AND set in the array. A logic array according to Claim 4, characterized in that said delay means includes a FET (QDG) which is turned on by the operation of said inverter to connect said common conductor to ground. A logic array according to Claim 5, characterized in that during each operation all selected AND sets and all selected OR sets have their gates precharged whereby no quiescent or d.c. power is dissipated in the array during operation. A logic array according to Claim 1, characterized in that the common conductors are precharged via FETs (QPG) in the OR sets during precharge of the row-conductors.

Inventors: MAHMUD, SYED TAYYEB
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1985
Main classification: H03K19
IPC codes: H03K19