MONOLITHIC SERIES FEEDBACK LOW NOISE FET AMPLIFIERS

Abstract: A monolithic low noise amplifier (10) is provided having at least one stage. Said stage including a Field Effect Transistor (FET) (12) and an inductive series feedback element comprising a transmission line (32,34) having an end connected to the FET source (30) and an end connected to ground (36,38). A load matching network (not shown) is attached to the FET drain (28) to provide simultaneous noise match and power match.

Description: This invention relates to amplifiers and more particularly to a low noise amplifier for microwave receivers. In the past, front-ends for conventional radar, phased-array radar, uplink and downlink stages of satellite communication receivers, television receivers, intrusion alarm systems, microwave point-to-point relay systems, and mobile radio receivers have required both low noise signal amplification and low input voltage standing wave ratios. To meet these requirements, low noise amplifiers having a balanced configuration have been used. Both hybrid and monolithic circuits have been used to implement the balanced configuration. A schematic circuit for a balanced amplifier stage is shown in the prior art (Fig. 1); each stage consists of two Field Effect Transistors (FETs), two input circuits, two output circuits and two 3-dB couplers. An alternative approach of meeting the front-end specifications is to use an isolator with a single-ended, noise matched monolithic low noise amplifier. As the isolator cannot be implemented on the monolithic substrate and as the invention of this application utilizes the monolithic form, the latter (isolator) approach will not be discussed in detail. The disadvantages of balanced low noise amplifiers are their high cost and large size owing to the duplication of circuit elements and the use of 3-dB couplers. The 3-dB couplers also degrade RF performance due to the loss associated with the couplers (0.3 dB at X-band). In DIGEST OF TECHNICAL PAPERS, FOURTH EUROPEAN MICROWAVE CONFERENCE, September 1974, pages 385-389; J. ENGBERG "Simultaneous input power match and noise optimization using feedback", a low noise amplifier is described which is optimized for minimum noise conditions. The theory described in this document has been experimentally verified at UHF-frequencies only, so that possible problems existing at considerably higher frequencies still exist. Further, the amplifier according to the before-mentioned document is not described as a monolithic amplifier and makes use of field effect transistors rather than bipolar transistors. The problem to be solved by the invention is to provide a low noise amplifier capable of being reproduced consistently and reliably, which has decreased device noise figure with constant noise measure, and decreased equivalent noise resistance to reduce the sensitivity of the device noise match. According to the invention the low noise amplifier comprising a monolithic structure including a field effect transistor having a drain, source and gate terminal, and an inductive series feedback means operatively connected between the source of the field effect transistor and ground, the inductive series feedback means having an inductance such that the optimum impedance (Z opt ) for minimum noise figure of the field effect transistor with feedback is approximately equal to the conjugate (S₁₁*) of the input impedance of the field effect transistor between the gate and ground with feedback when proper loading is presented at the drain terminal. The low noise amplifier according to the invention is of reduced cost and size and has improved RF performance due to the elimination of 3-dB couplers or an isolator. One way of carrying out the invention is described in detail below with reference to the drawings in which: Figure 1 is a schematic view of a prior art balanced amplifier stage; Figure 2 is a physical layout of the monolithic inductive series feedback around a FET; Figure 3 is a Smith chart mapping the impedance of S₁₁* and Z opt at 10 GHz; and Figure 4 is a three stage monolithic low noise amplifier using inductive series feedback to achieve a simultaneous noise and gain match over a 10 % bandwidth at 10 GHz. The design of a monolithic inductive series feedback low noise amplifier requires: measuring FET data, mapping the effect of inductive series feedback on S₁₁* and Z opt , determining the proper load impedance for a simultaneous noise and gain match, designing the monolithic inductive series feedback around a FET and finally designing input and output matching networks and interstage matching circuits for a multistage low noise amplifier. To obtain the necessary data a FET is mounted in a standard S-parameter test fixture. An automatic network analyzer is used to measure the FET's S-parameters over the frequency band of interest. The minimum NF of the FET is measured on a noise measurement test-set using precision slide screw tuners. These tuners are locked in position and measured on the automatic network analyzer. Mathematically removing the electrical length of the S-parameter test fixture and the devices's bond wires yields Z opt . The NF and Z opt measurement process is repeated at a number of different frequencies. The NF of the device with a 50 Ohm generator impedance is also obtained at each frequency. This data is loaded into a computer program sold under the trademark SUPER-COMPACT by Compact Software Incorporated where the effect of inductive series feedback on S₁₁* and Z opt is analyzed. Figure 3 shows a Smith chart plot of the change in impedance that occurs for both S₁₁* and Z opt for various values of inductive feedback at 10 GHz. As indicated in Figure 3, 0.23 nH of inductive series feedback with a 50 Ohm output load results in S₁₁* being equal to Z opt at 10 GHz. At another frequency a different load and/or a different amount of inductive series feedback would be needed to achieve this simultaneous match. Thus, the amount of feedback that is needed is determined by factors as follows: (1) the frequency of interest, (2) the bandwidth and (3) the availability of appropriate output loads i.e., loads that can be physically realized. With respect to the effect of inductive series feedback on noise figure, the feedback element is lossless and adds no noise to the circuit. For a detailed discussion of feedback and its effect on noise figure (NF) see J. Engberg, SIMULTANEOUS INPUT POWER MATCH AND NOISE OPTIMIZATION USING FEEDBACK, Digest of Technical Papers, Fourth European Microwave Conference, pp. 385-389, Sept. 1974. Thus the minimum noise measure, M min , for a lossless feedback circuit should remain constant, M min = (F min - 1) / (1 - 1/G av ) where G av is the available gain of the FET with the input noise matched. Verification was made experimentally for FETs at 10 GHz. Referring now to Figure 2, a series feedback inductor in series with field effect transistor (FET) 10 includes a field effect transistor (FET) 12 having a gate 14 connected to a gate pad 16 through gate feeds 18, 20 and 22 and air bridges 24 and 26. A drain 28 is connected to an RF output terminal. A source 30 completes the FET. Series feedback elements 32 and 34, which are transmission lines, connect the source 30 to ground through vias 36 and 38, respectively. The width and length of the transmission lines forming the series feedback elements 32 and 34 are determined using SUPER-COMPACT. Using a III-V compound such as for example GaAs, a 0.2nH inductor is realized on a 150 µm thick GaAs substrate as a 25 µm wide transmission line with a length of 270 µm. As series feedback elements 32 and 34 are in parallel, their actual length is doubled to 540 µm to present an equivalent 0.2nH inductance between the source and ground. In a single stage low noise amplifier the simultaneous noise and gain match is achieved at the expense of output VSWR. For a specific amount of feedback, an output load impedance can be determined which yields S₁₁* equal to Z opt . Output VSWR is accepted for what it is. In a two stage design, the input FET of the low noise amplifier can be presented with the proper loading at its drain terminal to satisfy the S₁₁* equal to Z opt equation by designing a correct interstage network. The output of the second FET can then be matched for low VSWR. In the two stage low noise amplifier the load impedance that the drain of the input stage needs to achieve a simultaneous noise and gain match is the same as in the single stage. The difference is that this load impedance is presented by an interstage circuit which transforms S₁₁ of the second device to the required value. Although series feedback is used only on the input stage to achieve a simultaneous noise and gain match, it can be used on the second stage to obtain other advantages that inductive series feedback provides, such as, for example, decreased sensitivity to components, increased device stability, decreased equivalent noise resistance, and the elimination of the need for a blocking capacitor as would be required with a parallel feedback element. A three stage monolithic low noise amplifier design is shown in Figure 4. The low noise amplifier is fabricated on a semi-insulating material substrate such as, for example, a 150 µm thick GaAs substrate or an AlGaAs substrate. The low noise amplifier includes three stages 40, 42 and 44 with interstages 46 and 48 interconnecting stages 40-42 and 42-44, respectively. In the first stage 40, input matching inductances are provided by transmission lines 50 and 52 connected in shunt and series to the gate of FET 12. A series feedback inductance is provided by transmission line 54 connected to the source of FET 12. As the structure of the series feedback inductance is that of Figure 2, i.e., two parallel transmission lines 32 and 34, the length of transmission lines 32 and 34 are 540 µm in length to provide the 270 µm equivalent length shown in the schematic and denoted by transmission line 54. The drain of FET 12 (Fig. 4) is connected to the first interstage 46 which includes interstage matching inductances provided by transmission lines 56, 58, 60 and 62. The second stage includes a FET 12' having its gate connected to the output of interstage 46, its source connected to a series feedback inductance provided by transmission line 54', and its drain connected to the input of the second interstage 48. It will be appreciated by those skilled in the art that the transmission line 54' can be omitted without detracting from the invention; it is included to provide among other things increased device stability. The second interstage 48 employs a similar circuit topology to the first interstage 46 structure described above and therefore need not be repeated in the description. The third stage 44 includes a FET 12'' having its gate connected to the output of the second interstage 48, its source connected to series connected feedback inductance provided by transmission line 54'' and its drain connected to output matching inductance provided by transmission lines 64 and 66. This third stage provides additional gain and also gain flatness. It will be noted in Figure 4 that the FETs have gate widths of 300 µm, the lengths of the transmission lines are in microns, are 25 µm wide and have a characteristic impedance of 83 Ohms. Each transmission line is less than a quarter wavelength and the values of the capacitors are as stated. The low noise amplifier of Figure 4 has been fabricated and tested. The measured results were: Frequency Band 9 - 10 GHz Input VSWR (max.) 1.5 Output VSWR (max.) 2.0 NF (dB) max. 1.9 Gain (dB) 27 ± 4

Claims: A low noise amplifier comprising a monolithic structure including a field effect transistor (12) having a drain, source and gate terminal, and an inductive series feedback means (32, 34) operatively connected between the source of the field effect transistor (12) and ground, the inductive series feedback means (32, 34) having an inductance such that the optimum impedance Z opt for minimum noise figure of the field effect transistor (12) with feedback is approximately equal to the conjugate S₁₁* of the input impedance of the field effect transistor (12) between the gate and ground with feedback when proper loading is presented at the drain terminal. A low noise amplifier as claimed in claim 1 wherein the proper loading is achieved by means of a matching network. A low noise amplifier according to claim 1 or claim 2 wherein the inductive series feedback means is a transmission line having a length less than a quarter wavelength. A low noise amplifier according to claim 3 wherein the transmission line of the inductive series feedback means comprises a plurality of parallel connected segments. A low noise amplifier according to any one of the preceding claims wherein the monolithic structure is fabricated on a semi-insulating substrate. A low noise amplifier according to claim 5 wherein the semi-insulating substrate is a group III-V compound of the periodic chart. A low noise amplifier according to claim 5, wherein the semi-insulating substrate is GaAs. A low noise amplifier according to claim 5, wherein the semi-insulating substrate is AlGaAs. A low noise amplifier according to any one of the preceding claims wherein the field effect transistor (12) includes a semi-insulating substrate, a gate pad (16), a gate (14) with said gate pad (16) being connected by a lead to the junction of a plurality of air bridges (24, 26) and the gate (14), said plurality of air bridges (24, 26) having ends connected to the gate (14), a source (30) having a plurality of segments, said source segments connected to ground through series feedback transmission lines (32, 34), and said segments being in operative association with the gate (14), and the drain (28) being in operative association with the gate (14).

Inventors: HESTON, DAVID D., LEHMANN, RANDALL E.
Applicants: TEXAS INSTRUMENTS INCORPORATED
Application year: 1985
Main classification: H03F3
IPC codes: H03F3, H01L27