EMITTER-COUPLED LOGIC (ECL) CIRCUITS

Abstract: An improved ECL circuit in which reference voltages have been eliminated is provided. The base of the reference switching transistor which is usually connected to a refer­ ence voltage is instead connected to the emitter of an emitter follower transistor coupled to the input switching transistor. The need for a reference voltage is thus eliminated because the emitter of such emitter follower transistor, and thus the base of the reference switching transistor, will be at the opposite level of the input to the base of the input switching transistor.

Description: This invention relates to emitter-coupled logic (ECL) circuits. In a standard ECL circuit as shown in Figure 1, two switching transistors 12 and 14 are connected at their emitters with the base of switching transistor 14 being connected to a reference voltage. The base of switching transistor 12 is connected to an input voltage. The connected emitters are connected to a current source transistor 24 which provides the current to the two switching transistors. The collectors of emitter-coupled transistors 12, 14 are connected via resistances to a power supply V cc . An output is obtained at the collector of each switching transistor upon application of an input voltage with one transistor providing a non-inverting output, and the other providing an inverting output. Each output is connected to an emitter follower transistor which isolates the switching transistor's collector from the output. The emitter of each emitter follower is the output and is also connected to a current source transistor. The reference voltage is referenced to the V cc supply and is normally generated at a single spot in an ECL integrated circuit and supplied throughout the whole chip via a bus line. Thus, the reference level has a high capacitance associated with it due to the extent of bus routing required. Additionally, the use of a reference voltage requires more power for the circuit. The V cc supply voltage can vary due to noise, particularly due to noise generated by a large number of outputs changing states at the same time. Because of the capacitance associated with the reference voltage lines, the reference voltage is slow to respond to noise on the V cc power supply line. Thus, during dynamic operation of the chip, malfunctions or oscillations can occur due to the V cc noise. In addition, because of the noise present on the reference voltage line, the high and low levels used must be sufficiently far apart to provide a margin for such noise. This results in a large voltage swing and thus a slow switching time. One solution to some of the problems of a reference voltage is shown in an article appearing in the February, 1977 issue of IEEE Journal of Solid-State Circuits , entitled "Improved Feedback ECL Gate with Low Delay-Power Product for the Subnanosecond Region," authored by Hans-Martin Rein and Roland Ranfft which shows an ECL gate without a reference voltage (the "Rein circuit"). The base of the transistor usually connected to a reference voltage is instead coupled to the collector of the input switching transistor. The circuit shown, however, does not include the emitter follower transistors found in an ECL circuit. The Rein circuit is not suitable to drive capacitive loads because of the slow response time due to the collector resistance, R2, limiting the current which can charge a load capacitance. The need for the reference voltage in the Rein circuit is eliminated by utilizing feedback from the collector of the input transistor to provide the reference voltage level. When the input is low, the input transistor is off and its collector is thus high, resulting in a high reference voltage. When the input changes to a high state, the input transistor turns on, simultaneously pulling its collector, and thus the reference voltage, low. Thus, the input will exceed the reference voltage and the transistor will switch states. A drawback, however, is that the high level of the output is reduced due to a voltage drop from current flowing through the collector resistor to the base of the reference transistor. This voltage drop is not present where a reference voltage is used and there is no such connection to the collector resistor. The voltage drop is increased by current flowing into a connected load. The lower high-level voltage makes the circuit more susceptible to noise and thus less reliable. US-A-3,509,362 shows a single level ECL circuit in which the base of the reference transistor is connected to the emitter of an emitter follower transistor, the base of the emitter follower transistor being connected to the collector of an inverting amplifier transistor in a signal translating circuit preceding the current mode switch. Noise is even a greater problem where two-level operation of ECL gates is used. In two-level operation, a first level of circuits operate between a logic low and high of given voltages. The second-level circuits operate between different low and high voltages. An understanding of two-level circuits may be aided by considering the operation of an AND gate in two-level circuits. An AND gate would indicate a logic high only if both inputs were high, and otherwise would indicate a logic low. In two-level operation, the same rules apply except that the logic high of one input is at a different level than the logic high of the other input. Additionally, logic outputs are provided at each voltage level. Two-level operation requires two reference voltage levels. Thus the problems discussed above for a single reference voltage are doubled. In addition, only two voltage levels are practical with a standard five-volt supply because of the need to provide sufficient separation between the high and low of each level to avoid noise problems. An article in the 25th August 1983 issue of Electronics International, Vol. 56, No. 17, pp71-72 entitled "Cell array sports 230-ps gate delay and 2,600 functions" shows a three-level CML switching circuit in which the reference voltages for each level are delivered by on-chip bias generators. Japanese Patent Specification No 55-145438 discloses a ECL transistor logic circuit with true and complementary outputs according to the preamble of Claim 1. In this document the base of the reference transistor is connected via a resistor to the complementary output whereby the complementary output voltage serves for providing a reference voltage to the reference transistor. According to the present invention there is provided an emitter coupled logic ECL gate circuit with true and complementary outputs, having a first level pair of emitter coupled switching transistors comprising a first input transistor and a first reference transistor, with their emitters connected to a constant current source, the base of the first input transistor forming a first level input of the gate; and having respective emitter follower output transistors for the true and complementary outputs of the gate, the bases of the true and complementary emitter followers being connected respectively to the collectors of the first input and first reference transistors and their emitters forming respectively the true and complementary outputs; characterised in that the base of the first reference transistor is connected directly to the complementary output whereby the complementary output voltage is applied as a reference voltage to the first reference transistor. The need for a reference voltage is thus eliminated because the emitter of the emitter follower output transistors, and thus the base of the respective reference switching transistors, will be at the opposite level of the input to the base of the respective input switching transistors. The use of the emitter follower, rather than the switching transistor, to provide feedback improves the performance of the circuit. In operation, when the input is low, the input transistor is turned off and its collector is high, thus the emitter of the emitter follower is pulled high, giving a high level at the base of the reference switching transistor and a high output equal to the voltage supply level V cc , less the voltage drop across the emitter follower transistor's base-emitter junction, V be . When the input changes to a high level, the input transistor turns on, pulling its collector low by the voltage drop, V s , across the collector resistor. The low collector voltage results in a low voltage at the emitter follower's emitter of V cc -V be -V s . This low voltage turns off the reference switching transistor and gives a low level output. The dynamic operation of the circuit has re-generative feedback action due to the reference voltage changing states simultaneously with the input. This results in a quick transition which is facilitated because the emitter follower can supply the needed current. Since no reference voltage with its noise margin requirement is present, the voltage swing V s (which is the difference between the high and low outputs) can be chosen to be smaller than in conventional ECL gates, further improving the transition time. Because the emitter follower has no collector resistor, the high-level output is not reduced by a collector resistor voltage drop. The lack of degradation of the high-level output gives an improved noise margin. In addition, the emitter follower can easily supply the current requirements of the base of the reference switching transistor and the load, and can charge the load capacitance quickly. In one preferred embodiment, the referenceless ECL circuit is used to form a two-level AND gate by inserting another emitter-coupled switching transistor pair between the first switching transistor pair and the current source transistor. The collector of the second input transistor is connected to the coupled emitters of the first switching transistor pair, while the collector of the second reference transistor is connected to the collector of the reference transistor for the first switching transistor pair. The base of the second reference transistor is also coupled to the emitter follower of the first input transistor through a diode. The diode provides a voltage drop sufficient to provide a second reference level and an inverting output at such second level. A diode coupled to the emitter of the non-inverting emitter-follower output provides a second-level non-inverting output. In operation, the two-level referenceless AND gate works for the first-level input in the same manner as the single-level referenceless ECL gate described above. However, the first emitter-coupled switching transistor pair will not change output states unless the second switching transistor pair allows current to be conducted. The second switching transistor pair will allow current to be conducted only when the second-level input changes to a high state relative to the voltage level provided to the base of the second reference transistor by the diode described above. Thus a high-level output will be generated only if a high level is applied to each input. Additional levels can be added in a similar manner as desired. Because no reference voltages are used, and thus no allowance for reference voltage noise need be made, a two-level circuit can operate with less than a standard five-volt supply. Alternately, three-level operation can be achieved with a standard five-volt supply. The difference between the reference voltage levels is determined by the voltage drop across a diode, thus allowing voltage levels which are much closer together. The use of closer voltage levels reduces the voltage swing when output states are changed and thus increases the speed of the circuit. Power usage of the circuit is reduced because no reference voltages are used. The chip circuitry is easier to lay out because there is no need to route reference voltage lines. In the accompanying drawings, by way of example only:- Figure 1 is a schematic drawing of a prior art ECL gate. Figure 2 is a schematic drawing of a preferred embodiment of a referenceless ECL gate. Figure 3 is a schematic drawing of the preferred embodiment of a two-level AND gate utilizing referenceless ECL logic. Figure 4 is a schematic diagram of the preferred embodiment of a three-level AND gate utilizing referenceless ECL logic. The present invention is best understood with reference to the operation of a conventional ECL gate as shown in Figure 1. An input 10 is connected to the base of an input switching transistor 12. Transistor 12 has its emitter coupled to the emitter of a reference switching transistor 14. Transistors 12 and 14 form the emitter-coupled switching transistor pair. Emitter follower transistors 16 and 18 are coupled to the respective collectors of transistors 12 and 14 to isolate such collectors from the output loads. Emitter follower transistors 16 and 18 are coupled to current source transistors 20 and 22, respectively. A third current source transistor 24 is coupled to the emitters of the emitter-coupled transistors 12 and 14. The base of transistor 14 is connected to a reference voltage V bb . The collectors of transistors 12 and 14 are coupled to a supply voltage V cc via resistors 26 and 28, respectively. The collectors of transistors 12 and 14 are also coupled to the bases of emitter follower transistors 16 and 18, respectively. The emitters of emitter follower transistors 16 and 18 are connected to outputs 30 and 32, respectively. Output 30 is an inverting output while output 32 is a non-inverting output. The emitters of emitter followers 16 and 18 are also coupled to the collectors of current source transistors 20 and 22, respectively. The emitters of current source transistors 20, 22 and 24 are coupled to ground 34 via resistors 36, 38 and 40, respectively. Alternately, rather than ground a voltage which is low relative to the supply voltage, V cc , could be used. The bases of current source transistors 20, 22 and 24 are connected to a current source voltage V cs . In operation, a current I is pulled from the emitters of emitter transistors 12 and 14 to ground 34 by current source transistor 24. The value of this current is determined by the voltage drop across resistor 40, which is equal to V cs less the base-emitter voltage of transistor 24. Substantially all of this current will flow through one or the other of emitter-coupled transistors 12 and 14, depending upon whether input 10 is above or below reference voltage V bb . The voltage at the coupled emitters of transistors 12 and 14, node 42, is determined by the value V bb less the base-emitter voltage drop of transistor 14. When input 10 is low, the voltage at node 42 reverse biases the base-emitter junction of transistor 12, thus shutting off transistor 12 so that substantially all current flows through transistor 14. When input 10 is high, the base-emitter junction of transistor 12 is forward biased, causing current to flow through transistor 12. The high input voltage has the effect of raising the voltage level of node 42, thereby reverse biasing the base-emitter junction of transistor 14. Thus, transistor 14 is turned off and substantially all of the current flows through transistor 12. For purposes of example, consider input 10 going from a low to a high state. As discussed before, transistor 12 will turn on, thereby forcing all of current I to flow through resistor 26. This forces node 44 to a low state determined by the voltage drop, V s , across resistor 26. At the same time, transistor 14 is turned off as discussed above, and virtually no current flows through resistor 28. Therefore, node 46 is pulled up to the value of V cc . The high voltage at node 46 causes a high voltage at the base of emitter follower transistor 18, resulting in a high voltage at its emitter which causes current to flow through transistor 18 to output 32. This current will charge the capacitance of the load connected to the output to a high state. The time required to charge such capacitance is directly proportional to the voltage difference between the low state and the high state. Returning to node 44, when it changes to a low state, the base of emitter follower transistor 16 is forced to a low state, and thus output 30 is brought to a low state equal to the low voltage at node 44 less the base-emitter voltage drop of transistor 16. When output 30 changes to a low state, the capacitance of the load connected to such output is discharged. The current from such capacitance flows through current source transistor 20 to ground. The amount of such current is determined by the value of resistor 36, in the same manner as discussed above for resistor 38. The amount of time required to discharge such capacitance is directly proportional to the voltage difference between the low state and the high state. In Figure 2 there is shown a first preferred embodiment of the present invention. The circuit is similar to the prior art circuit of Figure 1 except that the output of the inverting emitter follower 16 is coupled to the input of the non-inverting transistor 14 at a node 48, thereby eliminating reference voltage V bb of Figure 1. The operation of the circuit can be understood by considering low and high inputs. When input 10 is low, transistor 12 is turned off and node 44 is pulled up to V cc . The voltage at node 48 is thus V cc -V be , where V be is the base emitter voltage drop across transistor 16. This is a logic high which turns on transistor 14 and pulls current through the collector of transistor 14 and resistor 28. Node 46 is pulled down by an amount equal to the voltage drop across resistor 28, giving a voltage swing V s . The voltage at output 32 is thus V cc -V s -V be . This is a logic low which results when a logic low has been applied to input 10. Similarly, when input 10 is high, transistor 12 will be conducting and node 44 will be low. Node 48 will be equal to V cc -V s -V be , or a logic low. This logic low will turn off transistor 14 and thus node 46 will be pulled high to V cc , causing the emitter of emitter follower 18 to go high. Output 32 will be equal to V cc -V be , which is a logic high. The dynamic operation of the circuit is as follows. When input 10 goes from a low to a high state, node 44 is initially high. Node 42 is initially at a level of V cc -2V be . As the input nears V cc -V be , the base-emitter junction of transistor 12 becomes forward biased and current begins to flow in resistor 26, thus reducing voltage at nodes 44 and 48. As the voltage at node 48 is lowered, the current flowing through transistor 14 is reduced, shutting off transistor 14, allowing less current to flow through resistor 28, and forcing more current to flow through resistor 26. Thus, regenerative feedback action occurs which causes the transition to become completed very quickly. A similar effect occurs during a high to low transition at input 10. But in the case of a high to low transition, the regenerative effect starts when the input voltage 10 is near to the logic low voltage, V cc -V be -V s . Thus, the circuit exhibits little hysteresis which can be further reduced by reducing the amount of voltage swing V s . Conventional ECL circuits require large voltage swing V s because the voltage is referenced around a reference voltage. This large voltage swing is responsible for causing large delays in conventional ECL circuits. The present circuit is referenceless, and thus can use a much lower voltage swing (approximately 0.4 volts or less). This not only reduces the hysteresis but also reduces the delays significantly. By coupling the base of transistor 14 to the emitter of transistor 16, a higher high-level output is possible than if said base were connected to node 44 and a load. This is because a voltage drop across resistor 26 due to a load being coupled to node 44 is avoided. Thus emitter follower 16 can easily supply the needed current to the base of transistor 14 and a load. Another advantage of the present invention is that it can be operated at a reduced supply voltage level. Conversely, with conventional 5-volt supply, a three-level gate can be constructed and operated as opposed to the two-level gate presently possible. A schematic diagram of a preferred embodiment of a two-level AND gate utilizing referenceless ECL circuitry is shown in Figure 3. The circuit is identical to that of Figure 2 except as follows. A second pair of emitter-switching coupled transistors consisting of a transistor 50 and a transistor 52 with a second-level input 54 have been added. A diode 56 couples node 48 to the base of transistor 52 at a node 60 and a diode 58 is coupled between output 32 and the collector of transistor 22 to provide a second-level output 62. Node 60 is coupled to the collector of current source transistor 20 and provides a second-level inverting output 64. The operation of the circuit with respect to input 10 and outputs 32 and 30 is identical to that described for the circuit of Figure 2 above, except that transistor 12 cannot turn on and thereby cause output 32 to go high unless transistor 50 is also turned on. Transistor 50 will turn on when input 54 is at a second level logic high, thereby giving the AND operation of requiring that both inputs 10 and 54 be at logic highs to give a logic high output for output 32. The voltage level for input 54, however, is a lower level operation since to turn on input transistor 50, the input high at 54 need not exceed the node voltage at 48 as the input at input 10 is required to. Rather, input 54 need exceed only the reference voltage at node 60, which is the voltage at node 48 less the voltage drop across diode 56. It can be seen that the voltages at nodes or outputs 60 and 62 merely track the voltages at outputs 32 and 30, but at a lower voltage level or lower level operation. Referring to Figure 4, an additional voltage level input 66 can be added to the circuit of Figure 3 with emitter-coupled transistors 68 and 70 and diodes 72 and 74 producing third-level outputs 76 and 78. The coupled emitter of transistors 68 and 70 are coupled to the collector of current source transistor 24. The collector of transistor 68 is coupled to the emitters of transistors 50 and 52. The collector of transistor 70 is coupled to the collector of transistors 52 and 14. Diode 72 has its anode coupled to node 60 and its cathode coupled to the base of transistor 70 and the collector of current source transistor 20 to give third-level inverting output 78. Diode 74 has its anode coupled to output 62 and its cathode coupled to the collector of current source transistor 22 to give output 76. The operation of this circuit is again similar to that of the circuit of Figure 3 with the added requirement that transistor 68 must be turned on in order for transistors 12 and 50 to conduct. Thus, a logic high is required at all three inputs 10, 54 and 66 in order to produce a logic high output at outputs 32, 60 and 76. Diode 72 provides a reference level for input 66 which is the reference voltage at node 60 less voltage drop across diode 72. The value of the supply voltage V cc which is required to operate a referenceless ECL gate such as that of Figure 4 is shown by the following equation: V cc (n) ≧ (n+3/2) V be +V r where: V cc (n) = V cc required for n level operation n = number of levels; V be = base-emitter voltage of a transistor; V r = voltage across the current source resistor which is equal to the voltage swing V s (if resistor 26 and resistor 28 are equal to resistor 40 in value). A voltage swing of 0.4 volts is used to provide enough margin for noise and to make sure the transition occurs, although theoretically a lower value could be used. Considering the worst-case condition at a cold temperature where V be equals approximately 0.9 volts, the minimum values for V cc are as follows: V cc (1) = 2.65 volts; V cc (2) = 3.55 volts; V cc (3) = 4.45 volts. Thus, it can be seen that three-level operation as shown in Figure 4 is possible with a standard 5-volt supply. As will be understood by those familiar with the art, the present invention may be embodied in other specific forms. For instance, a number of input switching transistors could be coupled in parallel to give a OR/NOR function. Accordingly, a disclosure of the preferred embodiments of the invention is to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.

Claims: An emitter coupled logic (ECL) gate circuit with true and complementary outputs (32, 30), having a first level pair of emitter coupled switching transistors comprising a first input transistor (12) and a first reference transistor (14), with their emitters connected to a constant current source (24, 40), the base of the first input transistor forming a first level input (10) of the gate; and having respective emitter follower output transistors (16, 18) for the true and complementary outputs of the gate, the bases of the true and complementary emitter followers being connected respectively to the collectors of the first input and first reference transistors and their emitters forming respectively the true and complementary outputs; characterised in that the base of the first reference transistor is connected directly to the complementary output whereby the complementary output voltage is applied as a reference voltage to the first reference transistor. An emitter coupled logic gate circuit as claimed in Claim 1, characterised by one or more further level pairs of emitter coupled switching transistors each further pair comprising a further level input transistor (50, 68) and a further level reference transistor (52, 70) with each further input transistor connected collector to emitter in series between the emitter of said first input transistor and said constant current source, and the base of each further input transistor forming a respective further level input (54, 66) to the gate; and in that the true and complementary outputs of each such further level switching pair are taken in sequence by way of a respective voltage step device (56, 72, 58, 74) from the respective outputs of the previous switching pair, the base of each further level reference transistor being connected to the respective complementary output to apply that complementary output voltage to that base as a reference voltage. An emitter coupled logic gate circuit as claimed in Claim 2, characterised in that each said voltage step device comprises a diode (56, 72, 58, 74).

Inventors: MAZUMDER, NIKHIL C., YEE, DAVID H.B.
Applicants: ADVANCED MICRO DEVICES, INC.
Application year: 1985
Main classification: H03K19
IPC codes: H03K19, H03K17