SYSTEM FOR BY-PASS CONTROL IN PIPELINE OPERATION OF COMPUTER

Abstract: A system for computer pipeline operation, in which a plurality of instructions are executed in parallel by com­ mencing, before the termination of execution of the preced­ ing instruction, the execution of the present instruction, in­ cludes a conflict detection unit (3), a data establishment in­ dication unit (41, 42), and a source data by-pass unit (62, 64, 66, 67). The source data by-pass unit by-passes a source data to the processing stage which requires this source data im­ mediately after conflict is detected between the result data of the preceding instruction and the source data of the present instruction and the establishment of the source data of the present instruction is detected.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention. The present invention relates to a system for by-pass control during pipeline operation of a computer. 2. Description of the Related Arts. During a pipeline operation of a computer, a register conflict can occur when a register in which a change of data is under execution through a preceding instruction is referred to by a present instruction. When such a register conflict occurs, reference to this register by the present instruction can be carried out only after completion of the execution of the preceding instruction for a change of data. Usually, the flow of instructions in the pipeline operation consists of the decoding stage D for decoding the instruction, the calculate address stage A for calculating the operand address, the transform address stage T for transforming an operand address into an actual address, the read from buffer stage B for reading an operand from the buffer memory controlled by the storage control portion, the execute stage E for executing the calculation, and the write result stage W for checking the result of the calculation and writing the result. An example of a by-pass control system operative in an arithmetic calculation pipeline is described in EP-A-0 097 956. In this system, the arithmetic unit executes a given number N of arithmetic instruction in the pipeline for up to that number N of instructions. Initiation of a new instruction in the arithmetic unit is indicated by an indicator which detects that each instruction executed in the arithmetic unit occurs N cycles before completion of the execution, and allows the arithmetic unit to be initiated for a new instruction in the succeeding cycle. Here, the by-pass acts to omit delay stages in an instruction flow path when the result of a preceding instruction is required for the execution of a following instruction. The delay stages are otherwise necessary to abide by the rule of strict sequential control. SUMMARY OF THE INVENTION It is the object of the present invention to realize an improved pipeline operation of a computer in which a delay in operation due to a register conflict during the flow of the pipeline operation is reduced, and to increase the speed of control of the execution of the instructions in the pipeline operation. According to the fundamental aspect of the present invention, this object is achieved by the system defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, Fig. 1 illustrates examples of the prior art pipeline flow; Fig. 2 is a schematic clock diagram of the system for by-pass control during pipeline operation of a computer according to an embodiment of the present invention; Fig. 3 illustrates the pipeline flow for explaining the operation of the system shown in Fig. 2; Fig. 4 illustrates another embodiment of the present invention; Fig. 5 illustrates the pipeline flow for the operation of the system shown in Fig. 4; Fig. 6 illustrates the prior art pipeline flow for explaining the difference between that flow and the pipeline flow shown in Fig. 5; and Fig. 7 illustrates a further embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The system for by-pass control during the pipeline operation of a computer according to an embodiment of the present invention is shown in Fig. 2. The system of Fig. 2 comprises an instruction register 1, a register file 2, a coincidence circuit 3, a decoding portion 41, a by-pass valid flag register 42, register writing address holding registers 51, 52, 53, 54, and 55, and a writing operation portion 56. The system of Fig. 2 also comprises a base register 61, an operand address holding register 62, an index register 63, an operand address holding register 64, a displacement register 65, selectors 66 and 67, an adder/subtracter 68 for calculating addresses, an instruction portion 71 for instructing data reading from a memory, an instruction portion 72 for instructing an execution of calculation, and an instruction portion 73 for instructing the writing of the result of the calculation. According to the system of the present invention, an instruction fetched from the main storage is registered in the instruction register 1. This instruction consists of, for example, an operation code OP, a first operand OPR1, and a second operand OPR2. Where the instruction is a load type instruction, the first operand OPR1 is an operand to be written, and the second operand OPR2 is an operand for referral. In the example of a stored instruction shown in the instruction register 1 of Fig. 2, the second operand OPR2 comprises an index register number X2, a base register number B2, and a displacement D2. The register file 2 is a storage circuit consisting of a general use register, a floating point register, and the like. The output of the register file 2 is supplied to the base register 61 and the index register 63. The selector 66 receives the outputs of the base register 61 and the operand address holding register 62 as inputs to be selected and the output of coincidence circuit 3 as a control input, and the selector 67 receives the outputs of the index register 63 and the operand address holding register 64 as inputs to be selected and the output of coincidence circuit 3 as a control input. The adder/subtracter 68 receives the data from the selectors 66 and 67, and the displacement register 65, and carries out addition or subtraction on the basis of the received data to obtain an operand address. The operand address calculated by the adder/subtracter 68 is supplied to the registers 62 and 64 for holding the operand address. In the prior art, the registers for holding operand addresses, such as the registers 62 and 64 in Fig. 2, are provided for temporarily holding and updating an operand address in order to facilitate the treating of an operand address having a variable length in the main storage. In the system of Fig. 2 according to the present invention, these registers are utilized for holding by-pass data. The coincidence circuit 3 detects the identification between a register which stores the result of the execution of the preceding instruction and a register to be used for calculating the operand address of the present instruction. The selections in the selectors 66 and 67 are controlled by the outputs of the coincidence circuit 3. The decoding portion 41 is for analyzing the operation code of an instruction. The decoding portion 41 decides whether or not the preceding instruction is an instruction which can realize the execution of the calculation of the register writing data, on the basis of the output of the adder/subtracter 68 for calculating addresses. The valid flag register 42 is set or reset on the basis of this decision. For example, when the instruction can obtain the result of the execution of the instruction at a relatively early cycle of the execution of the instruction, such as a load-address (LA) instruction, the valid flag is set in the valid flag register 42. When the valid flag is set, the by-pass control enable signal is supplied from the decoding portion 41 to the coincidence circuit 3. The register writing addresses are stored as follows: A1 for stage A in register 51; T1 for stage T in register 52; B1 for stage B in register 53; E1 for stage E in register 54; and W1 for stage W in register 55. The coincidence circuit 3 consists of a base coincidence circuit 31 and an index coincidence circuit 32. The base coincidence circuit 31 detects the coincidence between the register writing address A1 of the preceding instruction, such as that of the load-address instruction and the base modification register address, shown as the I3 portion of the present instruction. When coincidence is detected, the data of the register 62, (not the data read from the register file 2), is supplied to the input port EA1 of the adder/subtracter 68 to carry out the by-pass operation. The index coincidence circuit 32 detects the coincidence between the register writing address A1 of the preceding instruction and the index modification register address, shown as the I2 portion of the present instruction. When coincidence is detected, the data of the register 64, (not the data read from the register file 2), is supplied to the input port EA2 of the adder/subtracter 68 to carry out the by-pass operation. Thus, in the system of Fig. 2, a pipeline flow having a minimum delay, as shown in Fig. 3, (B), is realized. The time required for the operation shown in Fig. 3, (B) is reduced by 5 cycles less than that shown in Fig. 1, (B), and by 4 cycles less than that shown in Fig. 1, (C). Even if the register writing address A1 coincides with the base or the index, the by-pass operation is not carried out when the valid flag is reset in the valid flag register 42, and the operation is carried out with the usual waiting time. Although in the above description the load-address (LA) instruction is adopted as an instruction which can instruct the calculation of the register writing data on the basis of the output of the adder/subtracter 68 for calculating addresses, other instructions can be adopted provided that the adopted instruction can obtain the result of the execution of the instruction at an early cycle of the execution of the instruction. The system for by-pass control in the pipeline operation of a computer according to another embodiment of the present invention is shown in Fig. 4. The system of Fig. 4 comprises an instruction register 1, a register file 2, a coincidence circuit 3, a decoding portion 41, by-pass valid flag registers 421, 422, 423, 424, and 425, and register writing address holding registers 51, 52, 53, 54, and 55. The system of Fig. 4 also comprises a base register 61, an index register 63, selectors 661, 662, 671, and 672, a displacement register 65, and an adder/subtracter 68 for calculating addresses. The system of Fig. 4 further comprises by-pass registers 811, 812, 813, and 814 corresponding to the stages of the operation, selectors 821, 822, 823, and 824, a result of calculation storing portion 741, a calculation executing portion 742, and a data reading from memory portion 743. The adder/subtracter 68 for calculating addresses carries out addition or subtraction on the basis of the data from the base register 61, the index register 63, the displacement register 65, and the by-pass registers 811, 812, 813, and 814 for holding an operand address, and calculating an operand address. The operand address calculated by the adder/subtracter 68 is used for a memory address and is supplied successively to the by-pass registers 811, 812, 813, and 814. The number of by-pass registers corresponds to the number of stages of the pipeline after stage A. The coincidence circuit 3 comprises coincidence elements 311 to 314 and 321 to 324, and NOR gates 331 and 341. The coincidence elements carry out the comparison between the base modification portion I3 or the index modification I2 of the instruction, and the register writing addresses A1 to E1 in the stages of the operation. For example, the coincidence element 311 detects the coincidence between the register writing address A1 of the preceding instruction, such as a load address (LA) instruction, and the base modification address I3 of the present instruction. If coincidence is detected, the data of the by-pass register 811 (TBYR) is supplied to the input port EA1 of the adder/subtracter 68 to cause the by-pass operation. If no coincidence is detected in the coincidence elements 311 to 314, the data of the base register 61 is supplied to the input port EA1 of the adder/subtracter 68. Thus, in the system of Fig. 4, a pipeline flow having a minimum of delay, as shown in Fig. 5, is realized. To illustrate the difference between the embodiment of the present invention and the prior art, the pipeline flow for the prior art is shown in Fig. 6. A further embodiment of the present invention is illustrated in Fig. 7. The system shown in Fig. 7 comprises selectors 911, 912, and 913, by-pass registers 921, 922, and 923, and identification number registers 931, 932, and 933. The control circuit including the coincidence circuit and decoding portion, such as shown in Fig. 4, is denoted as CC. The identification numbers (ID) 0, 1, and 2 are assigned to the by-pass registers 921, 922, and 923, respectively, for the read from buffer stage B, the execute stage E, and the write result stage W. The transfer of the data from the by-pass register 811 (TBYR) to the registers 921, 922, and 923 is carried out by changing the identification number successively with the sequence 0, 1, 2, 0, 1, 2, .... Only the identification numbers are held in the identification number registers 931, 932, and 933. These identification numbers are used for selecting registers where the by-pass control is carried out with reference to the data in the identification number registers. In the system shown in Fig. 7, when a register conflict occurs, a by-pass operation of the data of the by-pass register as a register read data and the operand address calculation are carried out, provided that the corresponding by-pass valid flags in the by-pass valid flag registers 422 to 425 indicate the valid state and that the data is registered in the by-pass register, thus enabling the pipeline operation to proceed satisfactorily.

Claims: A system for by-pass control in a pipeline operation of a computer that uses a plurality of processing stages, an instruction being executed in a plurality of periods, a plurality of instructions being executed in parallel by commencing, before the termination of execution of the preceding instruction, the execution of the present instruction, said system comprising: an instruction register (1) for storing successive instructions and delivering different components thereof; input means (61,63) receiving, from said instruction register (1), respective address components relating to a present instruction; an address calculator (68) connectable to said input means (61, 63) and having an output to a calculation portion of said computer; data holding means (62, 64; 811, 812, 813, 814; 811, 921, 922, 923) for holding the output of said address calculator, said output being by-pass data relating to a previous instruction; a writing address register (51) for storing the address into which the result from a previous calculation is to be written; a coincidence circuit (3) for comparing the address component of the present instruction with the address data from said writing address register (51), and producing respective output signals indicative of a coincidence in the corresponding address components thereof; respective selectors (66, 67; 661, 662, 671, 672) acting on each pair of said input means and data holding means for selectively connecting, for each address component, the outputs of the input means (61, 63) or data holding means (62, 64; 811, 812, 813, 814; 811, 921, 922, 923) to the address calculator (68) as a function of the respective outputs of said coincidence circuit (3), the output of a data holding means being selected in a case of a coincidence; said coincidence circuit (3) being enabled by a decoder (41) that receives an operation code portion of an instruction from said instruction register (1), said decoder determining therefrom whether or not a preceding instruction is of a type that is usable for the calculation of data to be written into said data holding means. A system according to claim 1, wherein data holding means (811, 812, 813, 814) are provided in correspondence with the operation cycle periods, to carry out shift processes. A system according to claim 2, wherein a plurality of coincidence circuits (311, 312, 313, 314, 321, 322, 323, 324) are provided in correspondence with the operation cycle periods. A system according to claim 1, wherein data holding means (921, 922, 923) are arranged in parallel, means (931, 932, 933) for storing identification numbers corresponding to said data holding means are provided, and said identification numbers are shifted in correspondence with the operation cycle periods. A system according to claim 1, wherein said address components comprise a base address and an index address. A system according to claim 5, wherein said coincidence circuit (3) comprises a base coincidence circuit (31) and an index coincidence circuit (32), each controlling a respective one of said selectors (66, 67), whereby in the event of a base address coincidence, the data holding means (62) receiving a base address is selected to input data into said address calculator (68), and in the event of an index address coincidence, the data holding means (64) receiving an index address is selected to input data into said address calculator (68).

Inventors: KITAMURA, TOSHIAKI, OINAGA, YUJI, ONISHI, KATSUMI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F9
IPC codes: G06F9