A SOLID STATE INVERTING CIRCUIT HAVING A BIPOLAR TRANSISTOR FOR RAPIDLY PROCESSING I/O SIGNALS

Abstract: An improved inverter circuit capable of quickly attain­ ing complete inversion is shown. The circuit comprises bipolar transistors (27, 29) by which an inverted output takes a level near the rated level and MOS transistors (23, 25) by which the inverted output reaches the rated level from the near level. The MOS transistors (23, 25) have large gate region dimensions and are driven by a bipolar transistor (31) which possesses high current driving capacity.

Description: The present invention relates to a inverter circuit in particular to a solid state inverting circuit having a bipolar transistor for rapidly processing I/O signals. Recently, there has been proposed an inverter circuit which, through mixed use at the output stage of a bipolar transistor and a CMOS transistor, makes it possible to carry out fast operation for a capacitative load as well as to obtain an output level which is the same as that of the CMOS output circuit, without increasing the size of the circuit (see, for example, Japanese Patent JP-A-59-2O5828). In such a circuit construction, a pair of bipolar transistors serially connected to each other between high and low voltage sources are turned-on or turned-off in the reverse manner to each other thus obtaining an inversed output signal at the intermediate connection therebetween. In practice a turn-on state of the bipolar transistor holds a certain remanent voltage V BE , between its base and emitter, instead of being in an entirely conductive condition. To compensate for such a remaining voltage bias, a subsidiary MOS transistor is employed which is capable of being substantially completely conductive. Thus it is desired to accomplish an increased switching speed of the MOS transistor to improve inversion speed. Fast operation of the MOS transistor depends on the dimensions of the gate region. However, increasing the dimensions of the MOS transistor means that the gate capacity of the transistors is increased. This results in an inconvenience since a driving circuit with high current driving capability has to be connected to the input terminal to drive the transistor. Thus, when the driving circuit is to be constructed, for example, by the use of CMOS transistor, it will give rise to a problem that the driving circuit has to be made large. It is an object of the present invention to provide an inverter circuit which can carry out inverting operation at high speed. It is another object of the present invention to construct an inverter circuit that can carry out inverting operation at high speed in a small size. It is still another object of the present invention to provide a high speed inverting circuit which can be driven by a driving circuit that possesses an ordinary driving capability. According to the present invention, there is provided an inverter circuit, comprising: an input terminal; a first bipolar transistor having a collector terminal for connection to a high level voltage source, and an emitter terminal; a second bipolar transistor whose collector terminal is connected to said emitter terminal of the first transistor and whose emitter terminal is for connection to a low level voltage source; an output terminal which is connected to said emitter terminal of the first transistor; means which is connected to the bases of said bipolar transistors for switching said bipolar transistors in response to the voltage level of said input terminal; and an MOS transistor which is provided in parallel to at least one of said bipolar transistors; characterized by a third bipolar transistor whose emitter is connected to the gate of said MOS transistor; and said third bipolar transistor having its base connected to said input terminal, and being switchable depending upon the level of the input signal. These and other objects, features and advantages of the present invention will be more apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings, in which: Fig 1 is a block diagram of a prior art inverter circuit, Fig. 2 is a block diagram of the inverter circuit relating to a first embodiment of the present invention. Fig. 3 is an explanatory diagram for illustrating the operation of the inverter circuit shown in fig. 2, Fig. 4 is a block diagram of the inverter circuit relating to a second embodiment of the present invention, and Fig. 5 is a block diagram of the inverter circuit relating to a third embodiment of the present invention. To facilitate the understanding of the present invention a brief reference will be made to a prior art. In Fig. 1 is shown the circuit inverter which is proposed in Japanese Patent JP-A-59-205828. In such a circuit construction, if, for example, the output voltage is to be inverted from the high level (power source potential V DD ) to the low level (potential V SS which is O V ordinarily), the output voltage is lowered from a potential V DD to a potential (V SS + V BE2 ) (here, V BE2 is the voltage between the base and emitter of a bipolar NPN transistor 7 which is about 0.7 V) by the action of a bipolar NPN transistor 7. It is then lowered from the potential (V SS + V BE2 ) to the potential V SS by means of an N-channel MOS transistor 11. Now, when such an inverter circuit is to be used together with the so-called TTL digital circuit, as well as maintaining the fast operation of the TTL digital circuit, the lowering of the ouput voltage form the potential (V SS + V BE2 ) to the potential V SS has to be carried out quickly,since the low level ouput voltage V OL of the TTL digital circuit is generally about 0.4 V. In order to accomplish this, the dimensions (the ratio of W to L) of the N-channel MOS transistor 11 have to be large. Further, when the output voltage is to be inverted from the low level to the high level, the output voltage is raised from a potential (v DD - V BEl ) (here, V BEl is the voltage between the base and the emitter of a bipolar NPN transistor 5) to the potential by a P-channel MOS transistor 9. Accordingly, if the inverting operation of the output voltage from the low level to the high level is to be carried out quickly, then the dimensions of the P-channel MOS transistor have to be large. However, increasing the dimensions of the P-channel MOS transistor 9 and the N-channel MOS transistor 11 means that the gate capacity of both transistors 9 and 11 is increased. This results in an inconvenience since a driving circuit with high current driving capability has to be connected to the input terminal IN to drive both transistors 9 and 11. Thus, when the driving circuit is to be constructed, for example, by the use of a CMOS transistor, it will have to be made large, which is a disadvantage. A description of some envisaged embodiments of the present invention follows. Fig. 2 shows the inverter circuit as it relates to a first embodiment of the present invention. First, its construction will be described. In Fig. 2, reference numeral 21 illustrates a conversion circuit for carrying out an inverting operation on an input signal by a mixed use of bipolar and CMOS transistors. The input stage of the conversion circuit 21 is constituted by a first P-channel MOS transistor 23 and a first N-channel MOS transistor 25. The first P-channel MOS transistor 23 has its gate terminal connected to the input terminal IN to which is input a signal to be inverted, and its source teminal connected, for example, to a voltage source V DD which supplies a potential V DD . The first N-channel MOS transistor 25 has its gate terminal connected to the input terminal IN, and its drain terminal connected to the ouput terminal OUT from which the inverted signal is output. The output stage of the conversion circuit 21 is constituted by a first bipolar NPN transistor 27 and a second bipolar NPN transistor 29. The first NPN transistor has its base terminal connected to the drain terminal of the first P-channel MOS transistor 23, its collector terminal connected to the voltage source V DD , and its emitter terminal connected to the ouput terminal OUT. The second NPN transistor has its base terminal connected to the source terminal of the first N-channel MOS transistor 25, its collector teminal connected to the ouput terminal OUT, and its emitter teminal connected to a voltage souce V SS which gives a potential V SS (ordinarily 0 V). A third bipolar NPN transistor 31 has its base terminal connected to the input terminal IN and its collector terminal connected to the voltage source V DD . Between its emitter terminal and the drain terminal of a second N-channel MOS transistor 39 are connected in series diodes 33, 35 and 37. The gate terminal of the second N-channel MOS transistor 39 has its gate terminal connected to the output terminal OUT and its source terminal connected to the V SS terminal. A second P-channel MOS transistor 41 has its gate terminal connected to the anode of the diode 35, its source terminal connected to the V DD terminal, and its drain terminal connected to the ouput terminal OUT. A third N-channel MOS transistor 43 has its gate terminal connected to the drain terminal of the second N-channel MOS transistor 39, its source terminal connected to the V SS terminal, and its drain terminal connected to the ouput terminal OUT. In addition, the diodes that are connected in series are used to adjust the threshold potential of the voltage that is input to the gate terminal of the second P-channel MOS transistor 41 and to the gate terminal of the third N-channel MOS transistor 43. The operation of the inverter circuit according to a first embodiment of the present invention (and whose construction has been previously described) will now be explained in conjunction with Figure 3. To begin, the case in which the signal state at the input terminal IN changes from the low level (referred to as "L" level hereafter) to the high level (referred to as "H" level hereafter) will be described. Here, it is to be noted that prior to the above change in the signal state, the first NPN transistor 27 and the second N-channel MOS transistor 41 were in on-state, the second NPN transistor 29 and the third N-channel MOS transistor 43 were in off-state, and the potential of the ouput terminal OUT was at V DD due to feeding from the voltage source V DD . When an "H" level signal input to the input terminal IN is supplied respectively to the gate terminals of the first P-channel MOS transistor 23 and the first N-channel MOS transistor 25 and to the base terminal of the third NPN transistor 31, the first P-channel MOS transistor 23 becomes off-state while the first N-channel MOS transistor 25 and the third NPN transistor 31 become on-state. In this state, due to the change to the off state of the first P-channel MOS transistor 23, the first NPN transistor 27 becomes off-state. Also, due to the change of the first N-channel MOS transistor 25 to the on-state, the charge that had been accumulated, during the "H" level state of the signal from the ouput terminal OUT, in a load capacity (not shown) connected to the ouput terminal OUT is supplied to the base terminal of the second NPN transistor 29 via the first N-channel MOS transistor 25, as the base current. As a result, the second NPN transistor 29 becomes on-state. On the other hand, due to the change to on-state of the third NPN transistor 31, the second P-channel MOS transistor 41 is changed to off-state and the third N-channel MOS transistor 43 is changed to on-state. Furthermore, due to the change of the third N-channel MOS transistor 43 to on-state, the second N-channel MOS transistor 39 is changed to off-state. By these changes, the charge that was accumulated in the load capacitor connected to the output terminal OUT flows into the voltage source V SS via the second NPN transistor 29. At the same time, a portion of the charge that was accumulated in the load capacitor flows into the voltage source V SS via the third N-channel MOS transistor 43. Then the potential at the output terminal OUT (output voltage) is lowered rapidly. When the ouput voltage drops from the potential V DD to the potential (V SS + V BE2 ),(where, V BE2 is the forward base-emitter voltage of the second NPN transistor 29, curve A of Fig. 3), the voltage between the base terminal and the emitter terminal of the second NPN transistor 29 becomes V BE2 . Then, the second NPN bipolar transistor 29 becomes off-state. Therefore, the charge that was accumulated in the load capacitor flows into the voltage source V SS via the third N-channel MOS transistor 43 alone. By arranging that the dimensions (ratio of W to L) of the third N-channel MOS transistor 43 are large, the output voltage is dropped rapidly from the potential (V SS + V BE2 ) to the potential V SS (curve B of Fig. 3). It should be noted here that since the third N-channel MOS transistor 43 is driven by the third bipolar NPN transistor 31 with large current driving capability, the third N-channel MOS transistor 43 can positively be driven even if the dimensions of the third N-channel MOS transistor 43 are made large. Consequently, the ouput voltage is dropped from the potential V DD to the potential (V SS + V BE2 ) mainly by the action of the second NPN transistor 29, and from the potential (V SS + V BE2 ) to the potential V SS mainly by the action of the third N-channel MOS transistor 43. Therefore, by the combined action of the bipolar transistor with high current driving capability and the MOS transistor whose current driving capability is enhanced through increase in the dimensions of the transistor, the falling behavior of the ouput voltage from the potential V DD to the potential V SS can be accomplished rapidly. Next, the case in which the signal state at the input terminal IN changes from "H" level to "L" level while the ouput voltage is at the potential V SS , will be described. When an "L" level signal is supplied to the respective gate terminals of the first P-channel MOS transistor 23 and the first N-channel MOS transistor 25 as well as to the base terminal of the third NPN transistor 31, the first P-channel MOS transistor 23 becomes on-state, and the first N-channel MOS transistor 25 and the third NPN transistor 3l become off-state. In this condition, due to change of the first P-channel MOS transistor 23 to on-state, the first NPN transistor 27 is changed to on-state and due to change of the first N-channel MOS transistor 25 to off-state the second NPN transistor 29 is changed to off-state. Then, a current is supplied from the voltage source V DD , via the first NPN transistor 27, to the load capacitor and the gate terminal of the second N-channel MOS transistor 39, which are connected to the ouput terminal OUT. As a result, along with a rapid rise in the output voltage, the potential of the gate terminal of the second N-channel MOS transistor 39 is raised and the second N-channel MOS transistor 39 becomes on-state. Then, the third N-channel MOS transistor 43 becomes off-state and the second P-channel MOS transistor 41 becomes on-state, and a portion of the charge to be accumulated in the load capacitor is supplied by the voltage source V DD via the second P-channel MOS transistor 41. When the output voltage is raised in this way from the potential V SS to the potential (V DD - V BEl ),(where V BEl is the forward base-emitter voltage of the first NPN transistor 27, curve C of Fig. 3 ), the first NPN transistor 27 becomes off-state because the voltage between the base terminal and the emitter terminal of the first NPN transistor 27 becomes equal to V BEl . Then, charge to be accumulated in the load capacitor is supplied by the voltage source V DD only through the second P-channel MOS transistor 41. Therefore, the ouput voltage can be made to rise rapidly from the potential (V DD - V BEl ) to the potential V DD by increasing the dimensions of the second P-channel MOS transistor 41 (curve D of Fig. 3). The gate terminal of the second N-channel MOS transistor 39 that drives the second P-channel MOS transistor 41 to on-state is connected to the ouput terminal OUT which is connected to the load capacitor. Since the dimensions of the second N-channel MOS transistor 39 can be made large, the second N-channel MOS transistor 39 can drive positively the second P-channel MOS transistor 41 even if the dimensions of the second P-channel MOS transistor 41 are increased. Consequently, the ouput voltage is raised from the potential V SS to the potential (V DD - V BEl ) mainly by the action of the first NPN transistor 27, and from the potential (V DD - V BEl ) to the potential V DD by the second P-channel MOS transistor 41. Thus, analogous to the falling behavior of the output voltage, the rising behavior of the ouput voltage from the potential V SS to the potential V DD can also be carried out rapidly. Fig. 4 illustrates the inverter circuit relating to a second embodiment of the present invention. Here, the level of the ouput voltage is arranged to be comparable with the input-output level of the so-called TTL digital circuit. First, the construction of the circuit will be described. As shown in Fig. 4, the input terminal IN to which is input a signal to be inverted is connected to the base terminal of a first NPN transistor 45, and to the respective gate terminals of a P-channel MOS transistor 47 and a first and a fourth N-channel MOS transistors 49 and 57. The first NPN transistor 45 has its collector terminal connected, for example, to a voltage source V DD supplying a potential V DD , and its emitter terminal connected to the anode terminal of the diode 51. The P-channel MOS transistor 47 has its source terminal connected to the voltage source V DD and its drain terminal connected to the drain terminal of the first N-channel MOS transistor 49. The source terminal of the first N-channel MOS transistor 49 is connected to a voltage source V SS that supplies a potential V SS (ordinarily 0 V). A second N-channel MOS transistor 53 has its gate terminal connected to the drain terminal of the P-channel MOS transistor 47, its drain terminal connected to the cathode terminal of the diode 51, and its source terminal connected to the voltage source V SS . A third N-channel MOS transistor 55 has its gate terminal connected to the drain terminal of the second N-channel MOS transistor 53, its source terminal connected to the voltage source V SS , and its drain terminal connected to the ouput terminal OUT from which is output the inverted signal. A fourth N-channel MOS transistor 57 has its drain terminal connected to the output terminal OUT and its source terminal connected to the drain terminal of a fifth N-channel MOS transistor 59. The fifth N-channel MOS transistor 59 has its source terminal connected to the voltage source V SS and its gate terminal connected to the gate terminal of the second N-channel MOS transistor 53 as well as to the base terminal of a second bipolar NPN transistor 61. The collector terminal of the second NPN transistor 61 is connected to the voltage source V DD and its emitter terminal is connected to the cathode terminal of a diode 63. The anode terminal of the diode 63 is connected to the output terminal OUT. A third bipolar NPN transistor 65 has its base terminal connected to the source terminal of the fourth N-channel MOS transistor 57, its collector terminal connected to the ouput terminal OUT, and its emitter terminal connected to the V SS terminal. The operation of the second embodiment of the inverter circuit according to the present invention (constructed as previously described) will now be explained. First, the case in which the signal condition at the input terminal IN is changed from the "L" level to the "H" level will be described. It is to be noted here that prior to this change in the signal condition, the second NPN transistor 61 was in on-state, the third and fourth N-channel MOS transistors 55 and 57 and the third NPN transistor 65 were in off-state, and the potential of the output terminal OUT was in the "H" level due to feeding from the voltage source V DD via the second NPN transistor 61. When the "H" level signal that is input to the input terminal IN is supplied to the base terminal of the first NPN transistor 45 and the respective gate terminals of the P-channel MOS transistor 47, first N-channel MOS transistor 49, and the fourth N-channel MOS transistor 57, the P-channel MOS transistor 47 becomes off-state-and the first NPN transistor 45, the first and fourth N-channel MOS transistors 49 and 57 become on-state. In this state, due to the change of the P-channel MOS transistor 47 to off-state the second NPN transistor 61 is changed to off-state, due to the change of the first N-channel MOS transistor 49 to on-state the second N-channel MOS transistor 53 and the fifth N-channel MOS transistor 59 are changed to off-state. Due to the change of the first NPN transistor 45 to on-state, the third N-channel MOS transistor 55 is changed to on-state. Further, due to the change of the fourth N-channel MOS transistor 57 to on-state, the charge that had been accumulated in the load capacitor (not shown) connected to the onput terminal OUT while the output terminal OUT had been in the "H" level signal state, is supplied to the base terminal of the third NPN transistor 65 as a base current. Because of this, the third NPN transistor 65 is changed to on-state. By these changes, the charge accumulated in the load capacitor which is connected to the output terminal OUT flows into the voltage source V SS via the third NPN transistor 65. Also, a portion of the charge accumulated in the load capacitor flows into the voltage source V SS via the third N-channel MOS transistor 55. Therefore, analogous to the first embodiment, the output voltage drops quickly from the potential V DD to the potential V SS by the combined action of the bipolar transistors with high current driving capability and the MOS transistors whose current driving capability is enhanced by increasing its dimensions. Moreover, the third N-channel MOS transistor 55 is driven by the first NPN transistor 45 which has high current driving capability so that it is possible to allow to increase the dimensions of the transistor. In the following situation, whilst the output voltage is at the potential V SS , the signal state at the input terminal IN changes from the "H" level to the "L" level. This level is supplied to the base terminal of the first NPN transistor 45 and to the respective gate terminals of the P-channel MOS transistor 47, the first N-channel MOS transistor 49, and the fourth N-channel MOS transistor 57. The P-channel MOS transistor 47 becomes off-state and the first NPN transistor 45, the first N-channel MOS transistor 49, and the fourth N-channel MOS transistor 57 become on-state. In this state, due to the change of the first NPN transistor 45 to off-state the third N-channel MOS transistor 55 is changed to off-state. In addition, due to the change of the P-channel MOS transistor 47 to on-state, the second NPN transistor 61, the second N-channel MOS transistor 53, and the fifth N-channel MOS transistor 59 are changed to on-state. Since the fifth N-channel MOS transistor 59 changes to 0n-state, the third NPN transistor 65 is changed to off-state. By these changes, a current is supplied from the voltage source V DD to the load capacitor which is connected to the output terminal, via the second NPN transistor 61 and the diode 63. Then, the output voltage is raised rapidly to an "H" level output voltage VOH, i.e. to about 3V, for instance. This "H" level voltage is at least on the TTL logic level which is lower than the potential VDD by the sum of the forward base-emitter voltage of the second NPN transistor 61 and the forward voltage of the diode 63. Accordingly, by the use of a circuit constructed as previously described, it becomes possible to obtain an "L" level output voltage V OL and an "H" level output voltage V OH that are comparable to those of the corresponding levels for the TTL logic circuit. Therefore, the present circuit becomes compatible with the TTL digital circuit. Fig. 5 shows a third embodiment of the inverter circuit in accordance with the present invention. In contrast to the second embodiment in which the output voltage V OH of the inverter circuit is comparable to the "H" level of the TTL digital circuit, the inverter circuit of the third embodiment can raise the output voltage up to the potential V DD . Its feature is that a P-channel MOS transistor 67 is converted in parallel to the second NPN transistor 61 of the inverter circuit shown in Fig. 4, with its gate terminal connected to the emitter terminal of the first NPN transistor 45. Thus, when the second NPN transistor 61 becomes on-state, the P-channel MOS transistor 67 is brought to an on-state. There, a portion of the charge to be accumulated in the load capacitor (not shown), which is connected to the output terminal OUT is supplied to the load capacitor by the voltage source V DD via the P-channel MOS transistor 67. In a manner analogous to that of the first embodiment, it is designed to rapidly raise the output voltage to the potential V DD by enhancing the current driving capability of the P-channel MOS transistor 67 through an increase in its dimensions. In other words, by constructing an inverter circuit as described above, it becomes possible to achieve effects that are similar to those in the first embodiment. It should be noted that the parts with identical symbols represent the same components as in Fig. 4, and further explanation on them was omitted by so arranging. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

Claims: An inverter circuit, comprising: an input terminal; a first bipolar transistor (27,61) having a collector terminal for connection to a high level voltage source, and an emitter terminal; a second bipolar transistor (29,65) whose collector terminal is connected to said emitter terminal of the first transistor (27,61) and whose emitter terminal is for connection to a low level voltage source; an output terminal which is connected to said emitter terminal of the first transistor (27,61); means (23,25, 47,49,57,59) which is connected to the bases of said bipolar transistors for switching said bipolar transistors (27,29,61,65) in response to the voltage level of said input terminal; and an MOS transistor (41,47,55,67) which is provided in parallel to at least one of said bipolar transistors (27,29,61,65); characterised by: a third bipolar transistor (31,45) whose emitter is connected to the gate of said MOS transistor (41,43,55,67); and said third bipolar transistor (31,45) having its base connected to said input terminal, and being switchable depending upon the level of the input signal. An inverter circuit according to claim 1, wherein said MOS transistor is a first N-channel transistor (43,55) whose drain terminal is connected to said output terminal and whose source terminal is connected to said low level voltage source. An inverter circuit according to claim 1 or 2, wherein the emitter terminal of said third bipolar transistor (31) and the gate terminal of said MOS transistor (43) are connected to said low level voltage source via an N-channel MOS transistor (39) whose gate terminal is connected to said output terminal. An inverter circuit according to claim 1, 2 or 3 further comprising: a P-channel MOS transistor (41,67) with its drain terminal connected to said output terminal, its source terminal connected to said high level voltage source, and its gate terminal connected to the emitter terminal of said third bipolar transistor (31,45). In inverter circuit according to any one of claims 1 to 4, wherein at least one of said MOS transistors (41,43,55) is connected to the emitter of said third bipolar transistor (31,45) via at least one voltage regulating diode (33,35,37,51). An inverter circuit according to claim 2, wherein said switching means comprises a first P-channel MOS transistor (23,47) with its source terminal connected to said high level voltage source, its drain terminal connected to the base terminal of said first bipolar transistor (27,61), and its gate terminal connected to said input terminal, and a second N-channel MOS transistor (25,57) with its source terminal connected to the base terminal of said second bipolar transistor (29,69), its drain terminal connected to the collector terminal of said second bipolar transistor (29,65), and its gate terminal connected to said input terminal. An inverter circuit according to claim 6, wherein the emitter terminal of said third bipolar transistor (31,45) and the gate terminal of said first N-channel MOS transistor (43,55) are connected to said low level voltage source via a third N-channel MOS transistor (39,53). An inverter circuit according to claim 6 or 7, wherein the base terminal of said second bipolar transistor (65) is connected to said low level voltage source via a fourth N-channel MOS transistor (59) whose gate terminal is connected to the base terminal of said first bipolar transistor (61). An inverter circuit according to claim 8, wherein the base terminal of said first bipolar transistor (61) is connected to said low level voltage source via a fifth N-channel MOS transistor (49) whose gate terminal is connected to said input terminal. An inverter circuit according to claim 8 or 9, wherein the emitter terminal of said first bipolar transistor (61) is connected to said output terminal via a voltage lowering diode (63). An inverter circuit according to Claims 6 to 10 further comprising: a P-channel MOS transistor (41,67) whose drain terminal, source terminal, and gate terminal are connected to said output terminal, said high level voltage source, and the emitter terminal of said third bipolar transistor (31,45) respectively.

Inventors: SUGIMOTO, YASUHIRO
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1985
Main classification: H03K19
IPC codes: H03K19, H03K17