LOGIC CIRCUIT

Abstract: A logic circuit includes an inverter circuit including a first enhancement type field effect transistor (21) having a gate connected to an input and a first depletion type transistor (22) having a gate and a source which are directly connected together and to a drain of the first enhancement type field effect transistor (21); a source follower circuit including a second enhancement type field effect transistor (23) having a gate which is connected to a connecting point of the first enhancement type field effect transistor (21) and the first depletion type field effect transistor (22) and a second depletion type field effect transistor (25) having a gate and a source which are directly connected to each other and a drain which is connected to a source of the second depletion type field effect transistor (23); a circuit which supplies power to the drains of the first depletion type field effect transistor (22) and of the second enhancement type field effect transistor (25) and to the sources of the first enhancement type field effect transistor (21) and of the second depletion type field effect transistor (23); and, an output is formed at the connecting point (26) of the second enhancement type field effect transistor (23) and the second depletion type field effect transistor (25) which form the source follower circuit.

Description: The present invention relates to an improvement of a logic circuit which utilises a field effect transistor. Various types of semiconductor logic circuits exist, and in many cases, these logic circuits are formed as an integrated circuit. Therefor, these logic circuits should be suitable for formation as an integration circuit. Further, when the logic circuit is formed by unit logic circuits, the power dissipation of the unit logic circuit is low(i.e., low power supply voltage), and the number of power sources for supplying the power should be kept as small as possible to improve the suitability of these unit logic circuits for the above integration circuit. Further, it is required that the unit logic circuit has only a small delay, operates at a high speed, provided a high load driving ability, provides a high logic function, and provides a high margin. The conventional circuit is formed by depletion type field effect transistors (hereinafter called D-FET transistor), and examples will be described subsequently, and therefore, two power sources are required, and a level shift is required for the source follower circuit. Further, the power dissipation is high, the output logic function is low, and the load driving ability is not satisfactory. According to this invention a logic circuit comprises an inverter circuit including a first enhancement type field effect transistor having a gate connected to an input and a first depletion type transistor having a gate and a source which are directly connected to each other and to a drain of the first enhancement type field effect transistor, a source follower circuit including a second enhancement type field effect transistor having a gate which is connected to a connecting point of the first enhancement type field effect transistor and the first depletion type field effect transistor and a second depletion type field effect transistor having a gate and a source which are directly connected to each other and a drain which is connected to a source of the second depletion type field effect transistor, the drain of the first depletion type field effect transistor and of the second enhancement type field effect transistor are connected to a first power source, and the sources of the first enhancement type field effect transistor and of the second depletion type field effect transistor are connected to a second power source, and an output is formed at the connecting point of the second enhancement type field effect transistor and the second depletion type field effect type transistor which form the source follower circuit. An advantage of the present invention is that it provides a logic circuit which utilises only one power source without using a level shift. Another advantage is that it provides a logic circuit which is operated with a low power dissipation and a high output logic function. It also has a satisfactory load driving ability. Particular examples of circuits in accordance with this invention will now be described and contrasted with the prior art with reference to the accompanying drawings; in which:- Fig. 1 is a circuit diagram of an example of a conventional logic circuit; Fig. 2, Fig. 3 and Fig. 4 are circuit diagrams showing other examples of conventional logic circuits; Fig. 5A is a graph showing the characteristics of the circuit shown in Fig. 1; Fig. 5B is a graph showing the characteristics of the circuit shown in Fig. 2; Fig. 6 is a circuit diagram of one example of the present invention; Figs. 7A and 7B are graphs showing the characteristics of the present invention; Figs. 8A and 8B are circuit diagrams showing a logic circuit in which many source follower dots are obtained from the circuit shown in Fig. 6; and Figs. 9A and 9B are diagrams showing modified examples of the logic circuit according to the present invention. Figure 1 shows a conventional unit logic circuit which uses MES field effect transistors (i.e., Schottky junction type field effect transistor). The circuit shown in Fig. 1 comprises an inverter circuit circuit formed by a driver transistor (D-FET) 1 and a load transistor (D-FET) 2, a source follower circuit formed by a source follower transistor 3, a level shift diode 4, and a current source using a D-FET 5. Hereinafter the former will be called an inverter circuit formed by a D/D construction and the latter a source follower circuit formed by a D/D construction. In the conventional circuit shown in Fig. 2, an enhancement type field effect transistor 6 (E-FET) is used as a driver transistor and a D-FET 7 is used as a load resistor. Hereinafter, this will be called an inverter circuit formed by an E/D construction. Further, the circuit shown in Fig. 3 (disclosed in IEE PROC., Vol. 127, Pt. I, No. 5, October, 1980) is formed by an inverter circuit 8 formed by an E/D construction and a source follower circuit 9. The source follower circuit 9 uses an E-FET 10 as a source follower transistor, a level shift diode 11, and a D-FET 12. Hereinafter, this will be called a source follower circuit formed by an E/D construction with level shift. The circuit disclosed in SSD84-63 of the technical Research Report of the Institute of Electronic and Communication Engineering in Japan as shown in Fig. 4 comprises an inverter circuit 13 formed by an E/D construction and a source follower circuit 14 which uses an E-FET 15 as a source follower transistor, an E-FET 16 as a current source, and no level shift diode is included. Hereinafter, this will be called a source follower circuit formed by an E/E construction. The conventional circuit shown in Fig. 1 is formed by a D-FET construction, and therefore, two power sources are required and a level shift is required for the source follower circuit. Further, the power supply voltage is high, i.e., |V DD | and |V SS are 2 to 3 volts, and the power dissipation is high. Also, the output logic function is low. For example, although FI = 8 and F0 = 8, the output source follower dot (hereinafter, called the output dot) ≅ 2. In addition to the above drawbacks, the driving ability for the load is not satisfactory. This due to the following: A sufficient margin is provided for the high level (V OH ) side of the output voltage, and the operation is then carried out at the point where the diode characteristic of the Schottky diode between the gate and the source of the input FET of the gate circuit at the next stage is sufficiently clamped. Therefore, at the rising of the output, the greater part of the load driving current is dissipated as a diode current so that the load driving ability becomes limited. Further, as the source follower circuit is formed by a D/D construction with the level shift diode and the circuit is formed in such a manner that the current source is operated even in the low level (V OL ) state, the driving ability is not satisfactory at a falling time as shown in Fig. 5A. That is the current I GS flows into the next stage. Further, as mentioned above, the output dots cannot be increased for the following reason. When the output is at high level (V OH ), as the source follower circuit is formed by a D/D construction, the voltage V GS between the source and gate of the source follower transistor decreases, therefore the high level V OH increases, and the diode current in a next stage increases. When the output is in low level (V OL ), the low level (V OL ) rises so that the margin on the low level side decreases. In the conventional circuit shown in Fig. 2, as the margin in the low level (V OL ) side is small as seen from Fig. 5B, the logic function is as low as FI≦4, FO≦4, and a sufficient output dot cannot be obtained because of the circuit construction. In Fig. 5B, curve A denotes an input output transmission characteristic, curve B denotes an inverted input output transmission characteristic, and point C denotes a crosspoint of the two curves A and B. Also in Fig. 5B, "a" shows an operation margin at the high level (V OH ) side and "b" shows an operation margin at the low level (V OL ) side. Further, as in the conventional circuit shown in Fig. 1, the diode current flows in the gate input in the next stage in a high level state, the power dissipation is intended to increase and the driving ability in the rising time is not satisfactory. When V DD is decreased to, e.g., |V DD | < 2V F (V F is a forward voltage V GS Schottky diode between the source and the gate in a MES FET), the driving ability deteriorates particularly in the rising time, and the driving abilities in the rising time and in the falling time become unbalanced. In another conventional circuit example, the circuit is formed by the inverter circuit and the source follower circuit as in Fig. 1, and a part of the D-FET's is changed to an E-FET. One such circuit is shown in Fig. 3, which comprises the inverter circuit formed by an E/D construction 8 and a source follower circuit 9 formed by an E/D construction with level shift diode. The circuit shown in Fig. 4 comprises an inverter circuit 13 formed by an E/D construction and a source follower circuit 14 by E/E construction. In these conventional circuits, as shown in Figs. 3 and 4, E-FET's are used, so that the power source voltage can be slightly decreased, but the other drawbacks cannot be resolved, as explained hereinafter. That is, in the circuit shown in Fig. 3, when the output is high level (V OH ), the diode current flows to a next stage. Further, as the source follower circuit includes a level shift diode, the power source voltage V DD cannot be set to |V DD | < 2V F , and thus a voltage such as V DD ≅ 3V F (≅ 2.5 volts) is required to obtain an optimum performance. Moreover, as the source follower circuit includes a level shift diode, the driving ability is deteriorated. In the circuit shown in Fig. 4, when the output is at high level (V OH ), the diode current flows to the next stage, but, when the output is at low level (V OL ), the source follower current flows. When the output dot is set, as in Fig. 1, when the output is low level (V OL ), the low level (V OL ) rises and decreases the margin at the low level (V OL ) side. Because the E-FET is used in the source follower circuit, the degree of rise of the low level (V OL ) is smaller than in the case shown in Fig. 1, however, this rise of the low level (V OL ) restricts the number of output dots. Further, to obtain an optimum performance, a power source voltage such as 2V F < |V SS | ≅ 2V is required. Thus, when the output is at high level (V OH ), the diode current flows to the next stage, and when the output is at low level (V OL ) , the current flows in the source follower circuit, and accordingly, the load driving ability is unsatisfactory. As mentioned above, in both of the conventional circuits shown in Fig. 3 and Fig. 4, there is a limit to a decrease in the power source voltage, and accordingly, there is a limit to the low power dissipation. According to the present invention, the driver comprises an inverter circuit formed by an E/D construc­ tion, a buffer which receives the output of the inverter circuit and which comprises a source follower circuit formed by an E/D construction having no level shift diode, and the logic of the inverter circuit is output from the source follower circuit. Therefore, the load driving ability is high, the speed is high, the power dissipation is low (low source voltage), and the logic function is excellent. Therefore, the circuit can be formed by one power source and a sufficient margin can be obtained, so that a logic circuit suitable for a high integrated circuit can be obtained. Figure 6 shows one embodiment of the present inven­ tion. In Fig. 6, reference numeral 21 designates a first E-FET having a gate connected to an input. Reference numeral 22 designates a first D-FET having a drain and source connected to the E-FET 21. These FET's 21 and 22 form an inverter circuit. Reference numeral 23 designates a second E-FET having a gate connected to a connection point between the transistors 21 and 22, reference numeral 25 designates a second D-FET having a drain connected to a source of the E-FET 23 and a gate and a source which are connected to each other. These FET's 23 and 25 form a source follower circuit. A connection point 26 between the FET's 23 and 25 is used as an output of the whole circuit. These FET's 21, 22, 23, and 25 are MES FET's in which a threshold voltage V thE = 0 ∼ 0.3 volt and V thD = -1.0 ∼ -0.3 volt. A reference potential, for example, ground potential, is supplied to the drains of the FET's 22 and 23, and the sources of the FET's 21 and 25 are placed at V SS (|V SS | < 2V F ; where V F is a forward voltage (V GS ) of the MES FET, and the value thereof is usually 0.7 ∼ 0.8 volt in a GaAs MES FET.), that is the V F of the E-FET 21 plus the V F of the E-FET 23. For example, one power source is used to supply -1.2 volts. Further, the gate width of each FET and the threshold voltage V th are parameters for carrying out the desired operation of the present invention; in Fig. 6, these values are as follows. When the gate width of the FET 21 is W₀ , the gate width of the FET's 22, 23, and 25 are W₀/2, 2W₀ and 2W₀ , respectively, the V th of the FET's 21 and 23 is +0.1 and the V th of the FET's 22 and 25 is -0.5 volt. The values of the parameters are shown by one example in which, when the predetermined high level is supplied to the input, the voltage appearing at the output of the inverter is designated as V OLN , a threshold voltage of the transistor forming the source follower circuit 23 is designated as V thE , and the power source voltage is designated as V SS , and therefore, the following equation is satisfied. V OLN - V SS ≦ V thE · The whole circuit formed in the present invention has the function of an inverter circuit. That is, when the high level voltage is input to the input of the FET 21, a low level voltage appears at the connection point 24, and this low level voltage is output via the source follower circuit (buffer circuit) from the connection point 26, maintaining the corresponding level in the junction 24. A similar function is carried out when the input level is inverted. In the circuit having such a function, |V SS | < 2V F , then the diode characteristic in the gate input of the next stage cannot be easily clamped. Then, as shown in Fig. 7A, the driving ability at the rising time is large and is actuated in a low resistance region, as shown in Fig. 7A, at the falling time, then similarly, the driving ability becomes large. The current of the source follower circuit formed by an E/D construction, as shown in Fig. 7A, is as follows: I DS in E-FET (23) = I DSI in D-FET (25), and the current of conventional source follower circuit formed by a D/D construction, as shown in Fig. 1 (Fig. 5A), is as follows: I DS in the source follower D-FET = I DSI in the current source D-FET + gate current I GS (diode current) of the input D-FET of the next gate circuit. In the high level V OH , the diode current in the next gate is zero, and in the low level state V OL , the source follower power is zero. Then the power dissipation required for obtaining the same function (driving function) can be made smaller than in the conventional circuit shown in Figs. 1 to 4. Through the afore-mentioned feature, when the predetermined high level is supplied to the input, the output of the inverter circuit is designated V OLN , the threshold voltage of the source follower FET is designated V thE , and the power source voltage is designated V SS , and thus the following equation stands; V OLN - V SS ≦ V thE so that the current of the source follower circuit becomes zero and V OL equals V SS when the output is at low level. As the source follower circuit is formed as shown above, the margin of the low level state (V OL ) becomes large compared to the circuit shown. (see Figs. 5B, 7B). Further, as the source follower circuit formed by an E/D construction is used as the buffer and |V SS | < 2V F , when the output is high level at the time of dot output, the V GS of the source follower FET in the source follower circuit decreases, however, this amount is small because an E-FET is used. Further, the diode current in the next stage is small and the low level V OL does not rise even if the current of the source follower circuit becomes zero when the output is low level V OL , then the source follower outputs more than twice as many dots than in the conventional circuit (Figs. 1 and 4) can be obtained (see Figs. 8A and 8B). Further, the ratio of delay times (including the driving ability) in the rising and the falling can be changed by changing the ratio of the gate widths of the E-FET and D-FET in the inverter circuit formed by an E/D construction and the source follower circuit formed by an E/D construction. Therefore, in the optimum design, the ratio of the delay times in the rising and the falling can be set as ≅ 1. Figures 9A and 9B show other embodiments of the invertion wherein the above parameters are changed. The number of elements in the circuit of the present invention is smaller (no diode exists) than in the conventional circuit (Fig. 1 and Fig. 3), and therefore, it is more suitable for the high density integrated circuit. Further, in the circuit of the present invention, the inputs are formed as an AND circuit (the number of the inputs ≅ 2), and aplurality of source follower circuits can be connected to the inverter circuit, so that multi-source follower circuit outputs can be obtained. Moreover, in the voltage range |V SS | < 2V F , the object of the present invention can be similarly realized by separating the source of the inverter circuit and the source of the source follower circuit, by making the source of the source follower circuit deeper in the negative direction than the source of the inverter circuit, and by suitably combining the V th of each FET and the gate width thereof. Further, the field effect transistors may be Metal Insulator Semiconductor field effect transistors (MISFIT's). When the MISFET is used, a source follower circuit formed by an E/D construction without a level shift diode is connected to an inverter circuit formed by an E/D construction, and thus the following holds true: (V OLN - V SS ) ≦V thE as mentioned above, so that a low power dissipation, high load driving ability, and many output dots can be obtained. As can be understood from the above explanation, it is clear that Fig. 6 and Figs. 8A, 8B the number of inputs of each logic circuit and the supply voltage is not defined. (In each drawing, GND can be changed to +V DD and V SS to GND.) As mentioned above, according to the present invention, the following effects can be obtained. 1 the load driving ability can be increased and a low power dissipation can be promoted; 2 the logic function can be improved by achieving a high operation speed; 3 the circuit can be formed by one power source and a sufficient margin can be obtained; and, 4 the circuit is suitable for use with high density integration circuits.

Claims: 1. A logic circuit comprising: an inverter circuit including a first enhancement type field effect transistor (21) having a gate connected to an input and a first depletion type transistor (22) having a gate and a source which are directly connected to each other and to a drain of the first enhancement type field effect transistor (21), a source follower circuit including a second enhancement type field effect transistor (23) having a gate which is connected to a connecting point of the first enhancement type field effect transistor and the first depletion type field effect transistor (22) and a second depletion type field effect transistor (25) having a gate and a source which are directly connected to each other and a drain which is connected to a source of the second depletion type field effect transistor (23), the drain of the first depletion type field effect transistor (22) and of the second enhancement type field effect transistor (23) are connected to a first power source, and the source of the first enhancement type field effect transistor (21) and of the second depletion type field effect transistor (25) are connected to a second power source, and an output (26) is formed at the connecting point of the second enhancement type field effect transistor (23) and the second depletion type field effect type transistor (25) which form the source follower circuit. 2. A logic circuit according to claim 1, wherein, when a predetermined high level is supplied to an input, an output voltage of said inverter circuit is denoted as VOLN, said second power source voltage is denoted as VSS, and a threshold voltage of said second enhancement type field effect transistor is denoted as VthE, the following relationship exists: VOLN - VSS ≦ VthE 3. A logic circuit according to claim 1 or 2, wherein said field effect transistors are MES field effect transistors, and when a said first power source voltage is denoted as VDD, higher than said VSS, a following relationship exists; VDD - VSS < 2 VF where VF is the forward voltage of a Schottky diode between a gate and a source of said MES field effect transistor. 4. A logic circuit according to claim 1 or 2, wherein said field effect transistors are MOS field effect transistors.

Inventors: HAYASHI, TOSHINARI, SAITO, SEIICHI, SATO, TOSHIRO, TAKAO, HISOKA
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H03K19
IPC codes: H03K19