DELAY CIRCUIT FOR GATE-ARRAY LSI

Abstract: A delay circuit for a gate-array LSI including at least one in­ verter having a plurality of P-channel transistors (Q₁ p to Q₄) and a plurality of N-channel transistors (Q₁ n to Q₄ n ) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of an innermost pair (Q₄ p, Q₄ n ) of P-channel/N-channel transistors generates an output (OUT).

Description: The present invention relates to a delay circuit applied to, for example, a gate-array large-scale integrated circuit (LSI). In a gate-array LSI, a delay circuit is used for delaying the propagation of a signal for a definite time period. Such a delay circuit must offer an optimum delay time period, a small mounting area, and minimum fluctuation of the delay time period. In general, a delay time period t pd of one gate of a metal-insulator-semiconductor (MIS) transistor can be represented by t pd ∝ C/g m where C is a load capacity, and g m is the conductance of the transistor. Further, if the load capacity C is definite, g m ∝ W/L where W and L are the width and length, respectively, of a gate of the transistor. Therefore, it is possible to increase the delay time period by using an inverter of MIS transistors having a small gate width W and a large gate length L. However, in a gate-array LSI, since only transistors having a definite size are used, it is impossible to arbitrarily change the size of the transistors. In other words, in a gate-array LSI, it is impossible to decrease the gate width W and increase the gate length L only for special transistors. There is a prior art delay circuit of a gate-array LSI comprised of a series of inverters of MIS transistors having a definite size. However, when a series of such inverters are simply connected to obtain a delay time period, the larger the delay time period, the greater the number of transistors, and thus the larger the area occupied. Note that it is also possible to construct a delay circuit by using a resistance-capacitance (RC) circuit. In this case, the delay time period must be adjusted by the resistance of polycrystalline silicon or the resistance of a diffusion region. However, such an adjustment is also impossible in a gate-array LSI. Accordingly, it is impossible to use an RC circuit as a delay circuit for a gate-array LSI. An article by R.H. Krambeck et al in IEEE journal of Solid-State Circuits, Vol SC-17, No. 3, June 1982 entitled "High-Speed Compact Circuits with CMOS" discloses a pseudo-NMOS circuit having a plurality of FET's connected in series as part of an 8-bit ALU critical path. According to the present invention, there is provided a delay circuit comprising: an input terminal; an output terminal; first and second power supply means; and inverter circuitry comprising a plurality of transistors connected in series between the first and second power supply means and providing first and second inverters connected in series between said input terminal and said output terminal; characterised in that each of said first and second inverters comprises a number of P-channel transistors and an equal number of N-channel transistors connected in series between said first and second power supply terminals; and in that common outputs of pairs of P-channel/N-channel transistors of said second inverter are fed back to inputs of pairs of P-channel/N-channel transistors of said first inverter. An embodiment of the present invention can provide a delay circuit, suitable for a gate-array LSI, having a small area. In the present invention, two inverters having series-connected P-channel/N-channel transistors, in which the outputs of the post-stage inverter are fed back to some of the inputs of the pre-stage inverters, are provided. In this case, since the outputs of the post-stage inverter are fed back to the pre-stage inverter, the driving ability thereof is reduced, thereby increasing the delay time period. Also, a large fan-out is obtained. Reference is made, by way of example, to the accompanying drawings, wherein: Fig. 1 is a partial circuit diagram of a gate-array LSI having no delay circuit; Figs. 2A, 2B, 2C, and 2D are timing diagrams showing the operation of the circuit of Fig. 1; Fig. 3 is a partial circuit diagram of a gate-array LSI having a delay circuit; Figs. 4A, 4B, 4C, 4D, and 4E are timing diagrams showing the operation of the circuit of Fig. 3; Fig. 5 is a circuit diagram of a prior art delay circuit; Fig. 6 is an equivalent circuit diagram of an example of one basic cell used in a complementary MIS gate array LSI; Fig. 7 is a plan view of the basic cell of Fig. 6; Figs. 8 and 9 are cross-sectional views taken along the lines VIII - VIII and IX - IX, respectively, of Fig. 7; Fig. 10 is a circuit diagram of a delay circuit not in accordance with the present invention; Figs. 11A and 11B are circuit diagrams for explaining the operation of Fig. 10; Fig. 12 is a circuit diagram of another delay circuit not in accordance with the present invention; Figs. 13 through 16 are timing diagrams showing the operation of the circuit of Fig. 12; Fig. 17 is a circuit diagram of a further delay circuit not in accordance with the present invention; Fig. 18 is a circuit diagram of an embodiment of the delay circuit according to the present invention; Figs. 19 and 20 are circuit diagrams for explaining the operation of Fig. 18; Figs. 21 through 24 are timing diagrams showing the operation of the circuit of Fig. 18; Fig. 25 is a circuit diagram of another embodiment of the delay circuit according to the present invention; Fig. 26 is a circuit diagram of a further embodiment of the delay circuit according to the present invention; and Figs. 27 and 28 are timing diagrams for explaining the operation of Fig. 26. In Fig. 1, which is a partial circuit diagram of a gate-array LSI, it is assumed that a clock signal CK₀ is delayed by time periods t₁ and t₂ to generate clock signals CK₁ and CK₂ , as shown in Figs. 2A, 2B, and 2D, thereby latching flip-flops FF1 and FF2. In this case, after the flip-flop FF1 is latched by the clock signal CK₁ as shown in Fig. 2C, if the delay time period t₂ of the clock signal CK₂ is large, a latch operation for the flip-flop FF2 by the clock signal CK₂ may be performed upon the next data. This means that the hold time period of the input data of the flip-flop FF2 by the clock signal CK₂ may be reduced. In order to secure a sufficient hold time period, a delay circuit DL is interposed between the flip-flops FF₁ and FF₂ , as illustrated in Fig. 3. As a result, the data output Q of the flip-flop FF1 is delayed by a time period t d . Thus, the data input D of the flip-flop FF2 is delayed by the time period t d as compared with the data output Q of the flip-flop FF1, as shown in Figs. 4C and 4D, and the hold time period of the flip-flop FF2 by the clock signal CK₂ becomes sufficiently large. Figure 5 shows a prior art delay circuit used in a gate-array LSI. A series of inverters INV are provided. Each of the inverters INV is constructed by a basic cell, which consists, for example, of four two-input gates. An example of a basic cell will now be explained with reference to Figs. 6, 7, 8, and 9. Figure 6 is an equivalent circuit diagram of a complementary MIS (CMIS) basic cell. The basic cell is comprised of a pair of P-channel transistors Q 1p and Q 2p having a common source and a pair of N-channel transistors Q 1n and Q 2n having a common source. In this case, the gates of the P-channel transistor Q 1p and the N-channel transistor Q 1n are connected to each other, and the gates of the P-channel transistor Q 2p and the N-channel transistor Q 2n are connected to each other. Referring to Fig. 7, which is a plan view of the basic cell of Fig. 6, and Figs. 8 and 9, which are cross-sectional views, reference numeral 1 designates an N⁻-type monocrystalline silicon substrate 1 having a P⁻-type well 2 for the N-channel transistors Q 1n and Q 2n . Further, a field oxide layer 3 for isolating transistors (active areas) from each other is formed thereon, and a gate oxide layer 4 is formed on each active area. Further, P⁺-type impurity diffusion regions 5 are formed for the P-channel transistors Q 1p and Q 2p , and N⁺-type impurity diffusion regions 6 are formed for the N-channel transistors Q 1n and Q 2n . Finally, polycrystalline silicon layers 7 are formed for the connection of the gates of the transistors Q 1p and Q 1n and the connection of the gates of the transistors Q 2p and Q 2n , thus completing the bulk process of a gate-array LSI. After that, as occasion demands, that is, as customers demand, connection patterns are formed on the basic cell as shown in Figs. 6 through 9. Returning to Fig. 5, as stated above, each inverter INV is constructed by a basic cell as shown in Figs. 6 through 9. In this case, each inverter INV uses only two gates, e.g., the transistors Q 1p and Q 1n , and does not use the other two gates, e.g., the transistors Q 2p and Q 2n . In Fig. 5, when the potential at the input terminal IN is changed from high to low, the delay time period of the first stage is 0.77 ns; the delay time period of the second stage is 0.43 ns; the delay time period of the third stage is 0.77 ns; and the delay time period of the fourth stage is 0.71 ns. Therefore, the total delay time period is 2.68 ns. On the contrary, when the potential at the input terminal IN is changed from low to high, the delay time period of the first stage is 0.43 ns; the delay time period of the second stage is 0.77 ns; the delay time period of the third stage is 0.43 ns; and the delay time of the fourth stage is 1.32 ns. Therefore, the total delay time period is 2.95 ns. In order to obtain a large delay time period, the delay circuit of Fig. 5 requires a large number of inverters stages, i.e., basic cells, occupying a large area. In Fig. 10, P-channel transistors Q 1p , Q 2p , Q 3p , and Q 4p are connected in series between a power supply terminal V cc and an output terminal OUT, and N-channel transistors Q 1n , Q 2n , Q 3n , and Q 4n are connected in series between the output terminal OUT and the ground. Further, a load capacity C L is connected to the output terminal OUT. The P-channel transistors Q 1p , Q 2p , Q 3p , and Q 4p and the N-channel transistors Q 1n , Q 2n , Q 3n , and Q 4n are all driven by the potential at the input terminal IN. For example, when the potential at the input terminal IN is low, the transistors Q 1p , Q 2p , Q 3p , and Q 4p are in an on state, and the transistors Q 1n , Q 2n , Q 3n , and Q 4n are in an off state. Therefore, the load capacity C L is charged at V cc by the transistors Q 1p , Q 2p , Q 3p , and Q 4p , so that the potential at the output terminal OUT is high. On the other hand, when the potential at the input terminal IN is high, the transistors Q 1n , Q 2n , Q 3n , and Q 4n are in an on state, and the transistors Q 1p , Q 2p , Q 3p , and Q 4p are in an off state. Therefore, the load capacity C L is discharged by the transistors Q 1n , Q 2n , Q 3n , and Q 4n , so that the potential at the output terminal OUT is low. When the potential at the input terminal IN is changed from high to low, the P-channel transistors Q 1p , Q 2p , Q 3p , and Q 4p are sequentially turned on, in that order, and the N-channel transistors Q 4n , Q 3n , Q 2n , and Q 1n are sequentially turned off, in that order, since the gate-source voltage of a P-channel transistor (N-channel transistor) on the outside is not smaller than the gate-source voltage of a P-channel transistor (N-channel transistor) on the inside. As a result, the output terminal OUT is charged by the P-channel transistors Q 1p , Q 2p , Q 3p , and Q 4p , so that its potential rises in the same way as the rise operation in a four-input NOR circuit as shown in Fig. 11A. On the other hand, when the potential at the input terminal IN is changed from low to high, the N-channel transistors Q 1n , Q 2n , Q 3n , and Q 4n are sequentially turned on, in that order, and the P-channel transistors Q 4p , Q 3p , Q 2p , and Q 1p are sequentially turned off in that order, since, also in this case, the gate-source voltage of a P-channel transistor (N-channel transistor) on the outside is not smaller than the gate-source voltage of a P-channel transistor (N-channel transistor) on the inside. As a result, the output terminal OUT is discharged by the N-channel transistors Q 1n , Q 2n , Q 3n , and Q 4n , so that its potential falls in the same way as the fall operation in a four-input NAND circuit as shown in Fig. 11B. Thus, since the P-channel transistors (or the N-channel transistors) are sequentially turned on from the outside to the inside, and the N-channel transistors (or the P-channel transistors) are turned on, the change of the potential at the output terminal OUT is delayed. Note that the fluctuation in the operation of the circuit of Fig. 10 is about the same as in conventional logic circuits. In Fig. 12, two inverter circuits as shown in Fig. 10 are provided. That is, an inverter INVA is comprised of P-channel transistors Q 1p , Q 2p , Q 3p , and Q 4p and N-channel transistors Q 1n , Q 2n , Q 3n , and Q 4n connected in series, and an inverter INVB is comprised of P-channel transistors Q 1p ' , Q 2p ' , Q 3p ' , and Q 4p ' and N-channel transistors Q 1n ' , Q 2n ' , Q 3n ' , and Q 4n ' connected in series. In Fig. 12, the potential at the input terminal IN is applied to the gates of the transistors Q 1p , Q 2p , Q 3p , Q 4p , Q 1n , Q 2n , Q 3n , and Q 4n of the inverter INVA. Accordingly, these transistors are driven by the potential at the input terminal IN. Also, the common output C of the innermost pair of the P-channel/N-channel transistors Q 4p and Q 4n of the inverter INVA is applied to the gates of the transistors Q 1p ', Q 2p ', Q 3p ', Q 4p ', Q 1n ', Q 2n ', Q 3n ', and Q 4n ' of the inverter INVB. Accordingly, these transistors are driven by the potential at the output C. Also, the common output of the innermost pair of the P-channel/N-channel transistors Q 4p ' and Q 4n ' of the inverter INVB is connected to the output terminal OUT. Note that, if the circuit of Fig. 12 is constructed by basic cells each having four two-input gates, as shown in Figs. 6 through 9, the transistors Q 1p , Q 2p , Q 1n , and Q 2n can be constructed by one basic cell; the transistors Q 3p , Q 4p , Q 3n , and Q 4n can be constructed by one basic cell; the transistors Q 1p ', Q 2p ', Q 1n ', and Q 2n ' can be constructed by one basic cell; and the transistors Q 3p ', Q 4p ', Q 3n ', and Q 4n ' can be constructed by one basic cell. Therefore, the circuit of Fig. 12 can be constructed by four basic cells in the same way as in the circuit of Fig. 5. The operation of the circuit of Fig. 12 is shown in Figs. 13 through 16. Figure 13 shows the case wherein the fan-out (F/O) is 0 and wherein the potential at the input terminal IN is changed from low to high; Fig. 14 shows the case wherein the fan-out (F/O) is 0 and wherein the potential at the input terminal IN is changed from high to low; Fig. 15 shows the case wherein the fan-out (F/O) is 5 and wherein the potential at the input terminal IN is changed from low to high; and Fig. 16 shows the case wherein the fan-out (F/O) is 5 and wherein the potential at the input terminal IN is changed from high to low. Referring to Fig. 13, first, if the potential at the input terminal IN is low, the P-channel transistors Q 1p , Q 2p , Q 3p , and Q 4p are in an on state, and the N-channel transistors Q 1n , Q 2n , Q 3n , and Q 4n are in an off state, and, accordingly, the potential at the node C is high. Therefore, in the inverter INVB, P-channel transistors Q₁ ' / p , Q₂ ' / p , Q₃ ' / p and Q₄ ' / p are in an off state, and the N-channel transistors Q₁ ' / n , Q₂ ' / n , Q₃ ' / n , and Q₄ ' / n are in an on state, and accordingly, the potential at the output terminal OUT is low. In this state, when the potential at the input terminal IN is changed from low to high, the N-channel transistors Q 1n , Q 2n , Q 3n , and Q 4n tend to be in an on state, while the transistors Q 1p , Q 2p , Q 3p , and Q 4p tend to be in an off state. At this time, when the change of the potential at the input terminal IN is rather rapid, the potentials at the nodes A₁ , A₂ , A₃ , and C temporarily rise up to a level higher than the power supply potential V cc by the gate-source capacitance of each of the transistors Q 1P to Q 4P and Q rn . Then, as the transistors Q 1n , Q 2n , Q 3n , and Q 4n become in an on state, the node C is discharged via these transistors. As a result, the potential at the node C is reduced, and simultaneously, the potentials at the nodes B₁ , B₂ , and B₃ change toward their DC stable points determined by the impedance ratio of the transistors. In addition, as the potential at the node C is reduced, the transistors Q 1p ', Q 2p ', Q 3p ', and Q 4p ' tend to be in an on state, and accordingly, the potentials at the nodes D₁ , D₂ , and D₃ change toward a DC stable point determined by the impedance ratio of the transistors Q 1p ', Q 2p ' , Q 3p ' , and Q 4p '. At this time, the potentials at the nodes E₁ , E₂ , and E₃ become lower than the ground level due to the rapid reduction of the potential at the node C. Next, when the potential at the input germinal IN becomes a sufficiently high level, the transistors Q 1n , Q 2n , Q 3n , and Q 4n are completely in an on state. Therefore, the potentials at the nodes C, B₁ , B₂ , and B₃ are reduced by the discharging operation. Note that, at this time, since the transistors Q 1p , Q 2p , Q 3p , and Q 4p are completely in an off state, the potentials at the nodes E₁ , E₂ , and E₃ become levels in accordance with the impedance determined by the leakage currents of the transistors Q 1n ', Q 2n ', Q 3n ', and Q 4n ' after a sufficient time period passes. Thus, the potential at the output terminal OUT is changed by the (charging and) discharging operation of the transistors Q 1p ' , Q 2p ' , Q 3p ' , and Q 4p ' and the transistors Q 1n , Q 2n , Q 3n , and Q 4n . However, in this case, a charging and discharging operation is carried out by a large number of transistors, thereby increasing the delay time period. In addition, when the potential at the input terminal IN is changed from high to low, the potential at each node is changed as shown in Fig. 14. A detailed explanation is omitted, since it is similar to that of Fig. 13, however, in this case, the potential at the output terminal OUT is changed by the discharging operation of the transistors Q 1p , Q 2p , Q 3p , and Q 4p and the transistors Q 1n ' , Q 2n ' , Q 3n ' , and Q 4n '. Note that, in the case wherein the fan-out is 5, Fig. 13 is replaced by Fig. 15, and Fig. 14 is replaced by Fig. 16. That is, the waveform at the output terminal OUT is blunt and the delay time period is further increased. In any case, a delay time period having a time larger than 5 ns can be obtained, and therefore, is larger than that of the circuit of Fig. 5. Note that, in the above-mentioned embodiments of Figs. 10 and 12, each of the inverters has the same number of P-channel transistors and N-channel transistors connected in series. Any number can be, of course, selected, however. In Fig. 17, two inverters INVA' and INVB' are added to the circuit of Fig. 12. That is, the inverter INVA' is interposed between the inverters INVA and INVB, and the inverter INVB' is connected to the output of the inverter INVB. The inverters INVA' and INVB' serve as wave-shaping means. Each of them may be constructed by two gates of one basic cell, for example as shown in Figs. 6 through 9. In Fig. 18, which illustrates an embodiment of the present invention, two inverters INVA and INVB are provided. In the inverter INVA, each pair of P-channel/N-channel transistors Q 1p and Q 1n ; Q 2p and Q 2n ; Q 3p and Q 3n ; and Q 4p and Q 4n form one inverter. Similarly, in the inverter INVB, each pair of P-channel/ N-channel transistors Q 1p ' and Q 1n ' ; Q 2p ' and Q 2n '; Q 3p ' and Q 3n '; and Q 4p ' and Q 4n ' forms one inverter. Here, if the pairs of the transistors Q 1p and Q 1n ; Q 1p ' and Q 1n '; Q 2p and Q 2n ; Q 2p ' and Q 2n ' ; Q 3p and Q 3n ; Q3p' and Q 3n ' ; Q 4p and Q 4n ; and Q 4p ' and Q 4n ' were defined by inverters INV₁ , INV₂ , INV₃ , INV₄ , INV₅ , INV₆ , INV₇ , and INV₈ , respectively, the circuit of Fig. 18 would be as schematically illustrated in Fig. 19. Note that the P-channel transistors Q p and N-channel transistors Q n of Fig. 19 are absent in Fig. 18. They are provided in Fig. 19 only for easy understanding of the operation thereof. Further, if the inverters INV₃ to INV₈ were defined by transfer gates, the circuit of Fig. 18 would be as schematically illustrated in Fig. 20. That is, in Fig. 18, the inverter INV₁ (Q 1p , Q 1n ) is driven by the potential at the input terminal IN; the inverter INV₂ (Q 1p ', Q 1n ') is driven by the output A of the inverter INV₁; the inverter INV₃ (Q 2p , Q 2n ) is driven by the output B of the inverter INV₂; the inverter INV₄ (Q 2p ', Q 2n ') is driven by the output C of the inverter INV₃; the inverter INV₅ (Q 3p , Q 3n ) is driven by the output D of the inverter INV₄; the inverter INV₆ (Q 3p ', Q 3n ') is driven by the output E of the inverter INV₅; the inverter INV₇ (Q 4p , Q 4n ) is driven by the output F of the inverter INV₆; the inverter INV₈ (Q 4p ', Q 4n ') is driven by the output G of the inverter INV₈; and the output of the inverter INV₈ becomes the potential at the output terminal OUT. Thus, the output of each inverter of the post-stage inverter INVB is fed back to the input of each inverter of the pre-stage inverter INVA. Accordingly, the driving power of each inverter (INV₁ to INV₈) is reduced, thereby increasing the delay time period. Note that, if the circuit of Fig. 18 is constructed by basic cells each having four two-input gates as shown in Figs. 6 through 9, the circuit of Fig. 18 can be constructed by four basic cells in the same way as in the circuit of Fig. 12. The operation of the circuit of Fig. 18 is shown in Figs. 21 through 24. Figures 21 through 24 correspond to Figs. 13 through 16, respectively. That is, Fig. 21 shows the case wherein the fan-out (F/O) is 0 and wherein the potential at the input terminal IN is changed from low to high; Fig. 22 shows the case wherein the fan-out (F/O) is 0 and wherein the potential at the input terminal IN is changed from high to low; Fig. 23 shows the case wherein the fan-out (F/O) is 5 and wherein the potential at the input terminal IN is changed from low to high; and Fig. 24 shows the case wherein the fan-out (F/O) is 5 and wherein the potential at the input terminal IN is changed from high to low. Referring to Fig. 21, it is assumed that the potentials at the input terminal IN, the outputs B, D, F, and the output terminal OUT are low, and the potentials at the outputs A, C, E, and G are high. At this time, when the potential at the input terminal IN is changed from low to high, the transistor Q 1p is turned off and the transistor Q 1n is turned on. As a result, the potential at the output A of the inverter INV₁ (Q 1p , Q 1n ) is reduced. At this time, since the transistors Q 2p , Q 3p , and Q 4p are still in an on state, the potentials at the outputs C, E, and G are also reduced. Such a potential reduction continues until the output B of the inverter INV₂ (Q 1p ', Q 1n ') reaches the threshold value of the P-channel transistor Q 2p . On the other hand, as the potential at the output A is reduced, the potential at the output B of the inverter INV₂ (Q 1p ', Q 1n ') rises. However, in this case, since the transistors Q 2n ', Q 3n ', and Q 4n ' are still in an on state, the potentials at the output D, F, and the output terminal OUT are increased simultaneously with the rise of the potential of the output B. When the potential at the output B reaches the above-mentioned threshold value, the transistor Q 2p is cut off, and the discharge at the outputs C, E, and G temporarily ceases. Further, when the potential at the output B increases, the potential at the output C remains temporarily at the same level and, accordingly, the transistor Q 2n ' is cut off. As a result, only the potential at the output B increases. Therefore, the output C of the inverter INV₃ (Q 2p , Q 2n ) is again reduced. At this time, since the transistors Q 3p and Q 4p are still in an on state, the potentials at the outputs E and G are also reduced. Such a potential reduction continues until the output D of the inverter INV₄ (Q 2p ', Q 2n ') reaches the threshold value of the P-channel transistor Q 3p . When the potential at the output D reaches this threshold value, the transistor Q 3p is cut off, and the discharge at the outputs E and G temporarily ceases. Further, when the potential at the output D increases, the potential at the output E remains temporarily at the same level, and accordingly, the transistor Q 3n ' is cut off. As a result, only the potential at the output E increases. At this time, since the transistor Q 4p is still in an on state, the potential at the output G is also reduced. Such a potential reduction continues until the output F of the inverter INV₆ (Q 3p ', Q 3n ') reaches the threshold value of the P-channel transistor Q 4p . When the potential at the output F reaches this threshold value, the transistor Q 4p is cut off, and the discharge at the output G temporarily ceases. Further, when the potential at the output F increases, the potential at the output G remains temporarily at the same level. Accordingly, the transistor Q 4n ' is cut off. As a result, only the potential at the output F increases. Therefore, the output G of the inverter INV₇ (Q 4p , Q 4n ) is again reduced, so that the potential at the output terminal OUT rises. Contrary to the above, in a state where the potentials at the input terminal IN, the outputs B, D, F, and the output terminal OUT are high and the potentials at the outputs A, C, E, and G are low, when the potential at the input terminal IN is changed from high to low, the potential at each node is changed as shown in Fig. 22. A detailed explanation thereof is omitted, since it is similar to that of Fig. 21. Thus, since saddle points are generated in the change of the potentials at the outputs C, E, and G and at the outputs B, D, and F, the delay time period is increased. Note that, in the case wherein the fan-out is 5, Fig. 21 is replaced by Fig. 23 and Fig. 22 is replaced by Fig. 24. That is, the waveform at the output terminal OUT is blunt and the delay time period is further increased. In any case, a delay time period having a time larger than 5 ns can be obtained and therefore, is larger than that of Fig. 5. In Fig. 25, which illustrates another embodiment of the present invention similar to the embodiment as shown in Fig. 18, the inverters INV₃ (Q 2p , Q 2n ), INV₅ (Q 3p , Q 3n ), and INV₇ (Q 4p , Q 4n ) of the inverter INVA are driven simultaneously by the output B of the inverter INV₂ (Q 1p ', Q 1n ') of the inverter INVB, and the inverters INV₄ (Q 2p ', Q 2n '), INV₆ (Q 3p ', Q 3n '), and INV₈ (Q 4p ', Q 4n ') of the inverter INVB are driven simultaneously by the output (C) of the inverter INV₇ (Q 4p , Q 4n ) of the inverter INVA. In this circuit of Fig. 25, in a state where the potentials at the input terminal IN and the output B are high, and the potentials at the outputs A and C are low, when the potential at the input terminal IN is changed from high to low, the output A is changed from low to high. At this time, since the potential at the output C is low, the P-channel transistors Q 2p ', Q 3p ', and Q 4p ' are in an on state, while, since the potential at the output A is high, the N-channel transistor Q 1n ' is in an on state. Therefore, the potential at the output B changes toward the DC stable point determined by the impedance ratio of the transistors Q 2p ', Q 3p ', and Q 4p ' to the transistor Q 1n '. As a result, the P-channel transistors Q 2p , Q 3p , and Q 4p tend to be in an on state and the N-channel transistors Q 2n , Q 3n and Q 4n tend to be in an off state, and accordingly, the high potential at the output A is transmitted to the output C. Therefore, the output C becomes high, so that the potential at the output terminal OUT becomes low. In such a configuration, unstable waveforms are hardly ever generated in the output terminal OUT as compared with the embodiment of Fig. 18. Thus, in Figs. 18 and 25, since the driving power of each inverter included in the inverters INVA and INVB is reduced by feedback control thereof, the delay time period is increased as compared with the circuit of Fig. 12. In Fig. 26, which illustrates a further embodiment of the present invention similar to the embodiment of Fig. 25, the inverters INV₃ (Q 2p , Q 2n ), INV₅ (Q 3p , Q 3n ), and INV₇ (Q 4p , Q 4n ) of the inverter INVA are driven by the potential at the output terminal OUT, not the output of the inverter INV₂ (Q 1p ', Q 1n ') of the inverter INVB. The operation of the circuit of Fig. 26 will be explained with reference to Figs. 27 and 28. In Fig. 27, in an initial state, the potentials at the input terminal IN and the output terminal OUT are low. At this time, since the transistors Q 1p to Q 4p are in an on state, the potentials at the nodes A, C₁ , C₂ , and B are high, and accordingly, the transistors Q 1n ' to Q 4n ' are in an on state, so that the potentials at nodes F₁ , F₂ , and F₃ are low. In this state, when the potential at the input terminal IN is changed from low to high, the potential at the output A of the inverter INV₁ (Q 1p , Q 1n ) is reduced. At this time, since the transistors Q 2p , Q 3p , and Q 4p are still in an on state, the potentials at the nodes C₁ and C₂ and at the node B are also decreased with the decrease of the potential A. As a result, as the potential at the node B falls, the transistors Q 4p ', Q 3p ', and Q 2p ' tend to be in an on state, so that the nodes E₁ , E₂ , and E₃ are discharged to decrease the potentials thereof. Whereas, the potentials at the output terminal OUT and the nodes F₁ , F₂ , and F₃ are increased. Such an unstable state continues until the potential at the output terminal OUT reaches the threshold value of the P-channel transistor Q 2p . When the potential at the output terminal OUT reaches this threshold value, the transistors Q 2p , Q 3p , and Q 4p are cut off to again decrease the potential at the node B. Thus, although the potential at the node A rapidly ends its fall, there is generated a temporary saddle point in the potential at the node B, thereby increasing the delay time period. In Fig. 28, in an initial state, the potentials at the input terminal IN and the output terminal OUT are high. At this time, since the transistors Q 1n to Q 4n are in an on state, the potentials at the nodes A, D₁ , D₂ , and B are low. Accordingly, the transistors Q 1p ' to Q 4p ' are in an on state, so that the potentials at nodes E₁ , E₂ , and E₃ are high. In this state, when the potential at the input terminal IN is changed from high to low, the potential at the output A of the inverter INV₁ (Q 1p , Q 1n ) is increased. At this time, since the transistors Q 2n , Q 3n , and Q 4n are still in an on state, the potentials at the nodes D₁ and D₂ and at the node B are also increased with the increase of the potential A. As a result, as the potential at the node B rises, the transistors Q 4n ', Q 3n ', and Q 2n ' tend to be in an on state, so that the nodes F₁ , F₂ , and F₃ are charged to increase the potentials thereof. Whereas, the potentials at the output terminal OUT and the nodes E₁ , E₂ , and E₃ are reduced. Such an unstable state continues until the potential at the output terminal OUT reaches the threshold value of the N-channel transistor Q 4n . When the potential at the output terminal OUT reaches this threshold value, the transistors Q 2n , Q 3n , and Q 4n are cut off to again increase the potential at node B. Thus, although the potential at the node A rapidly ends its rise, there is generated a temporary saddle point in the potential at the node B, thereby increasing the delay time period. Note that the reason why the delay time period in Fig. 27 is larger than that in Fig. 28 is that the driving power for P-channel transistors is smaller than that for N-channel transistors. Thus, when the potential at the input terminal IN is changed from low to high, the delay time period is larger than 17 ns, while when the potential at the input terminal IN is changed from high to low, the delay time is larger than 7 ns. In any case, a delay time period having a time larger than 5 ns can be obtained and therefore, is larger than that of Fig. 5. Figures 27 and 28 show the case where the fan-out is 0. However, if the fan-out is larger than 1, the delay time period is further increased. As explained hereinbefore, according to the present invention, the delay time period can be increased as compared with the prior art where a plurality of inverters are simply connected in series. In other words, with the same delay time period, it is possible to reduce the area occupied by the delay circuit.

Claims: A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc ,GND); and inverter circuitry comprising a plurality of transistors connected in series between the first and second power supply means and providing first and second inverters (INVA, INVB) connected in series between said input terminal and said output terminal; characterised in that each of said first and second inverters (INVA,INVB) comprises a number of P-channel transistors (Q 1p ....Q 4p ,Q' 1p ....Q' 4p ) and an equal number of N-channel transistors (Q 1n ...Q 4n , Q' 1n ...Q' 4n ) connected in series between said first and second power supply terminals (V cc , GND); and in that common outputs of pairs of P-channel/N-channel transistors of said second inverter (INVB) are fed back to inputs of pairs of P-channel/N-channel transistors of said first inverter (INVA). A delay circuit as claimed in claim 1, wherein: an outermost pair (Q 1p ,Q 1n ) of P-channel/N-channel transistors of said first inverter (INVA) is operable to be driven by a potential at said input terminal (IN); pairs of P-channel/N-channel transistors of said second inverter (INVB) are operable to be sequentially driven from the outside to the inside by common outputs of pairs of P-channel/N-channel transistors of said first inverter (INVA); the pairs of P-channel/N-channel transistors of said first inverter (INVA), except for the outermost pair (Q 1p ,Q 1n ), are each operable to be sequentially driven by a common output of a respective pair of P-channel/N-channel transistors of said second inverter (INVB); and the common output of an innermost pair (Q' 4p ,Q' 4n ) of P-channel/N-channel transistors of said second inverter is connected to said output terminal (OUT) (Fig.18). A delay circuit as claimed in claim 1, wherein: an outermost pair (Q 1p ,Q 1n ) of P-channel/N-channel transistors of said first inverter (INVA) is operable to be driven by the potential at said input terminal (IN); an outermost pair (Q' 1p ,Q' 1n ) of P-channel/N-channel transistors of said second inverter (INVB) is operable to be driven by the common output (A) of the outermost pair (Q 1p ,Q 1n ) of P-channel/N-channel transistors of said first inverter (INVA); inside pairs of P-channel/N-channel transistors of said first inverter (INVA) are operable to be driven by the common output (B) of the outermost pair (Q' 1p ,Q' 1n ) of P-channel/N-channel transistors of said second inverter (INVB); inside pairs of P-channel/N-channel transistors of said second inverter (INVB) are operable to be driven by the common output (C) of an innermost pair (Q 4p ,Q 4n ) of P-channel/N-channel transistors of said first inverter (INVA); and the output of an innermost pair (Q' 4p ,Q' 4n ) of P-channel/N-channel transistors of said second inverter (INVB) is connected to said output terminal (OUT) (Fig.25). A delay circuit as claimed in claim 1, wherein: an outermost pair (Q 1p ,Q 1n ) of P-channel/N-channel transistors of said first inverter (INVA) is operable to be driven by the potential at said input terminal (IN); an outermost pair (Q' 1p ,Q' 1n ) of P-channel/N-channel transistors of said second inverter (INVB) is operable to be driven by the common output (A) of the outermost pair (Q 1p ,Q 1n ) of P-channel/N-channel transistors of said first inverter (INVA); inside pairs of P-channel/N-channel transistors of said first inverter (INVA) are operable to be driven by the common output of an innermost pair (Q' 4p ,Q' 4n ) of P-channel/N-channel transistors of said second inverter (INVB); inside pairs of P-channel/N-channel transistors of said second inverter (INVB) are operable to be driven by the common output (B) of an innermost pair of P-channel/N-channel transistors of said first inverter (INVA); and the output of the innermost pair (Q' 4p ,Q' 4n ) of P-channel/N-channel transistors of said second inverter (INVB) is connected to said output terminal (OUT) (Fig.26).

Inventors: FUJII, SHIGERU, OOZEKI, MASANORI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H03K5
IPC codes: H03K5