GATE ARRAY INTEGRATED DEVICE

Abstract: A gate array integrated device incuding a plurality of single column type arrays (BC1), a plurality of matrix type arrays such as double column type arrays (BC2), and longitudinal connection areas (CH) provided between the arrays (BC1, BC2). One of the single column type arrays faces at least one side of each of the matrix type arrays (BC2).

Description: The present invention relates to a gate array integrated device. In general, since large integrated circuits (LSI) such as complex integrated logic circuits are manufactured in accordance with customers' requirements for a preferred design or development requirements, a small quantity of a large number of different circuits are manufactured. In order to promptly manufacture such circuits at a low cost, a gate array (master slice) method has been suggested. According to the gate array method, a large number of basic cells are regularly manufactured in advance, and as customers' requests, or as development requests, connection masks for unit cells are designed and manufactured, so that the inner connections within the basic cells and the connections therebetween are manufactured. Therefore, since the configuration of the basic cells is common, the manufacturing or development term is reduced, and accordingly, the manufacturing or development cost is reduced. Note that a basic cell configuration is determined by impurity diffusion regions within a semiconductor substrate and indispensable connections therein, and accordingly, this is called a bulk configuration. The present invention is directed to improving such a bulk configuration. A prior art bulk configuration comprises a plurality of single column type arrays each of which includes a series of basic cells arranged along the column direction of the device. In such a bulk configuration, however, when unit cells are constructed, the longitudinal length thereof is increased and this causes deterioration of the characteristics of the signal transmission speed and the like. In addition, the connections between the basic cells become long, and it sometimes becomes necessary to increase the connection areas between the single column type arrays, which is disadvantageous from the viewpoint of integration. To avoid the disadvantages in the above-mentioned single column type, a bulk configuration has been suggested, comprising a plurality of matrix type arrays such as double column type arrays. In a matrix type array bulk configuration, however, it sometimes becomes impossible to arrange the connections for unit cells, since the redundancy of connections for unit cells is small, as will be later explained. IBM Technical Disclosure Bulletin vol. 26, no. 5, October 1983, pp 2404-2407, J P Bansal "MOS(N-Well) master image chip" discloses a gate array device formed from columns of cells. Each column of p-type devices is flanked on both sides by columns of n-type devices. EP-A-0119059 (Toshiba) discloses an alternative arrangement in which column type arrays are formed adjacent to each other whereby columns of devices with the same conductivity type of neighbouring column type arrays are next to each other. No wiring region is provided between two adjacent arrays. According to the present invention, a gate array integrated device is provided comprising: a plurality of single column type arrays each comprising a series of basic cells arranged along the column direction of said device; a plurality of matrix type arrays each comprising a plurality of column arrays in proximity to each other along the row direction of said device, each of said column arrays comprising a series of basic cells arranged along the column direction of said device; a plurality of first power supply lines arranged along the column direction of said device over said single column type arrays and said matrix type arrays; and longitudinal connection areas, arranged along the column direction of said device between said single column type arrays and said matrix type arrays, for providing areas of connections for connecting said basic cells to each other, thereby creating unit cells, each matrix type array being arranged between single column type arrays. The present invention provides a gate array integrated device having a redundancy of connections for connection areas, and excellent characteristics such as the signal transmission speed, and high integration. The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings, wherein: Fig. 1 is an equivalent circuit diagram of an example of a complementary metal insulator semiconductor (CMIS) basic cell; Fig. 2 is a plan view of the basic cell of Fig. 1; Figs. 3 and 4 are cross-sectional views taken along the lines III-III and IV-IV, respectively, of Fig. 2; Fig. 5 is a plan view of a prior art gate array integrated device; Fig. 6 is a diagram of connections for unit cells applied to the basic cells of Fig. 5; Fig. 7 is a diagram of connections for unit cells applied to double column type basic cells; Fig. 8 is a plan view of an embodiment of the gate array integrated device according to the present invention; Fig. 9 is an enlargement of the double column type array of Fig. 8; Fig. 10 is a diagram of connections for unit cells applied to the single column type array of Fig. 1; Fig. 11 is a diagram of connections for unit cells applied to the double column type array of Fig. 1; Fig. 12A is a plan view of connections of two basic cells for a 4-input NAND circuit unit cell; Fig. 12B is an equivalent circuit diagram of the unit cell of Fig. 12A; Figs. 13 and 14 are logic circuit diagrams for explaining a clip method; Fig. 15 is an enlargement of the single column type array of Fig. 8, in which impurity diffusion regions are provided for avoiding the latch-up phenomenon; Fig. 16 is a modification of Fig. 15, in which a power supply line is added thereto; Fig. 17 is a plan view for explaining a clip method according to the present invention applied to the single column type array of Fig. 15; Fig. 18 is a plan view taken along the line XVIII-XVIII of Fig. 17; Fig. 19 is a plan view for explaining a clip method according to the present invention applied to the single column type array of Fig. 16; Fig. 20 is a plan view taken along the line XX-XX of Fig. 19; Fig. 21 is an enlargement of the double column type array of Fig. 9, in which impurity diffusion regions are provided for avoiding the latch-up phenomenon; Fig. 22 is a modification of Fig. 21, in which a power supply line is added thereto; Fig. 23 is a plan view for explaining a clip method according to the present invention applied to the single column array of Fig. 21; Fig. 24 is a plan view taken along the line XXIV-XXIV of Fig. 23; Fig. 25 is a plan view for explaining a clip method according to the present invention applied to the single column array of Fig. 22; Fig. 26 is a plan view taken along the line XXVI-XXVI of Fig. 25; and Fig. 27 is a plan view of another embodiment of the gate array integrated device according to the present invention; Fig. 28 is a plan view illustrating additional power supply lines according to the present invention; Fig. 29 is a plan view of a gate array integrated device to which the power supply lines of Fig. 28 are applied; and Fig. 30 is an enlargement of the device of Fig. 29. First, an example of a basic cell will now be explained with reference to Figs. 1, 2, 3, and 4. Figure 1 is an equivalent circuit diagram of a CMIS basic cell. The basic cell is comprised of a pair of P-channel transistors Q p1 and Q p2 having a common source and a pair of N-channel transistors Q n1 and Q n2 having a common source. In this case, the gates of the P-channel transistor Q p1 and the N-channel transistor Q n1 are connected to each other, and the gates of the P-channel transistor Q p2 and the N-channel transistor Q n2 are connected to each other. Referring to Fig. 2, which is a plan view of the basic cell of Fig. 1, and Figs. 3 and 4, which are cross-sectional views, taken along the line III-III and IV-IV, respectively, of Fig. 2, reference numeral 1 designates an N⁻-type monocrystalline silicon substrate 1 having a P⁻-type well 2 for the N-channel transistors Q n1 and Q n2 . Further, a field oxide layer 3 for isolating transistors (active areas) from each other is formed thereon, and a gate oxide layer 4 is formed on each active area. Further, P⁺-type impurity diffusion regions 5 are formed for the P-channel transistors Q p1 and Q p2 , and N⁺-type impurity diffusion regions 5 are formed for the N-channel transistors Q n1 and Q n2 . Finally, a polycrystalline silicon layer 7 is formed for the connection of the gates of the transistors Q p1 and Q n1 and the connection of the gates of the transistors Q p2 and Q n2 , thus completing the bulk process of a gate array LSI. After that, as occasion demands, that is, as customers demand or development demands, connection patterns are formed on the basic cell as shown in Figs. 1 through 4. As illustrated in Fig. 5, in the prior art, basic cells are arranged at the center of a chip. That is, each single column type array BC1 is comprised of a series of basic cells, along the column direction of the chip, and connection (channel) areas CH are provided between the arrays BC1. In Fig. 5, I/O designates an input/output circuit for the connection to the exterior, and P designates a pad. Examples of unit cells formed on the above-mentioned single column type arrays BC1 are illustrated in Fig. 6. That is, connections LA parallel to the arrays BC1 indicated by solid lines are formed by a first aluminium layer, and connections LB perpendicular to the arrays BC1 indicated by dotted lines are formed by a second aluminium layer. Thus, connections within the unit cells and connections therebetween are formed by the connections LA and LB. However, when unit cells are formed on the single column type arrays BC1, the length of one unit cell becomes large, thereby increasing the length of the above-mentioned connections LA and LB, and reducing the characteristics such as the signal transmission speed and the like. In addition, as the result of the increased length of the connections LA and LB, each connection channel area CH between the single column type arrays BC1 must be large, which is disadvantageous from the viewpoint of integration. Note that, in order to remove the above-mentioned disadvantages, one approach is to construct a basic cell array as a matrix type array, such as a double column type array, thereby reducing the length of the unit cells, and improving the characteristics such as the signal transmission speed and the like by reducing the length of the connections LA and LB. In addition, since the connection areas between the matrix type arrays are decreased, the integration is improved. However, as illustrated in Fig. 7, when all of the basic cell arrays are constructed by such double column type arrays BC2-1, BC2-2, BC2-3, ..., in a double column type array such as BC2-2, connections for unit cells must be on one side of this array BC2-2, so that even if there is no room on one side of the double column type array BC2-2, i.e., in a connection area CH₁ , and there is room on the other side of the double column type array BC2-2, i.e., in a connection area CH₂ , it sometimes becomes impossible to arrange the necessary connections for unit cells of the double column type array BC2-2. In Fig. 8, which illustrates an embodiment of the present invention, double column type arrays BC2, as illustrated in detail in Fig. 9, are arranged between single column type arrays BC1. As illustrated in Figs. 8 and 9, a connection area CH is provided on the outside of the double column type array BC2, however, there is no connection area between the single column type arrays BC1-1 and BC1-2 of the double column type array BC2. In addition, the single column type arrays BC1-1 and BC1-2 within the double column type array BC2 have a symmetric configuration. Figure 10 is a plan view of an example of connections for unit cells applied to the single column type array BC1 of Fig. 8, and Fig. 11 is a plan view of connections for the same unit cells applied to the double column type array BC2 of Fig. 8. Comparing Fig. 10 with Fig. 11, in Fig. 10, the number of stages of used basic cells is 8, while in Fig. 11, the number of stages of used basic cells is 4. Therefore, the connections made of the first aluminium layer within the basic cell array (which is indicated by solid lines and whose contacts are indicated by single rounds) in Fig. 11 are relatively short as compared with those in Fig. 10. In addition, the connections LB₁ to LB₅ of the second aluminium layer for unit cells (which are indicated by dotted lines and whose contacts are indicated by double rounds) in Fig. 11 have a smaller interval as compared with those in Fig. 10. As a result, the number of connections arranged at the connection areas CH for other unit cells can be reduced, and the length of the connections can be also reduced. In Fig. 10, all the connections LB₁ through LB₅ are located on both sides of the single column type array BC1, and therefore, any connection channel areas on either side of the single column type array BC1 can be used. On the other hand, in Fig. 11, the connections LB₁ , LB₂ , and LB₃ are located on one side of the double column type array BC2, and the connections LB₄ and LB₅ are located on both sides thereof. That is, the connections LB₁ through LB₃ must be connected at a connection area on one side thereof. In Fig. 8, a single column type array BC1 faces to at least one side of a double column type array BC2. Therefore, since the single column type array BC1 can use one connection area at either side thereof, the limitation of use of the connection areas on the sides of the double column type array BC2 can be sufficiently covered. That is, if the determination of connections of unit cells for the double column type arrays BC2 is carried out prior to the determination of connections of unit cells for the single column type arrays BC1, the possibility of non-connections can be reduced. Usually, basic cells are divided by each unit cell such as a 4-input NAND circuit, a 4-input NOR circuit, a 6-input NAND circuit, a 6-input NOR circuit or the like. In this case, a 3-input NAND circuit is allocated to the same area as a 4-input NOR circuit, a 3-input NOR circuit is allocated to the same area as a 4-input NOR circuit, and a 5-input NOR circuit is allocated to the same area as a 6-input NOR circuit. For example, as illustrated in Fig. 12A, a 4-input NAND circuit comprises four P-channel transistors Q p1 through Q p4 and four N-channel transistors Q n1 through Q n4 . The common gate of the transistors Q p1 and Q n1 serves as an input terminal IN₁ , the common gate of the transistors Q p2 and Q n2 serves as an input terminal IN₂ , the common gate of the transistors Q p3 and Q n3 serves as an input terminal IN₃ , and the common gate of the transistors Q p4 and Q n4 serves as an input terminal IN₄. An output OUT is taken from the drain of the transistor Q n4 via a contact CONT₂ by an aluminium connection for unit cells. Figure 12B shows an equivalent circuit of Fig. 12A. In order to apply the unit cell for a 4-input NAND circuit to a 3-input NAND circuit, one input terminal such as IN₄ can be connected to a power supply line LA₂ (V SS ). Thus, a logic circuit as illustrated in Fig. 13 is obtained. Similarly, in order to apply the unit cell for a 4-input NOR circuit to a 3-input NOR circuit, one input terminal can be connected to a power supply line LA₁ (V CC ). Thus, a logic circuit of Fig. 14 can be obtained. The connection of one input terminal to a power supply line as explained above is called a "clip". In Fig. 15, which is an enlargement of the single column type array BC1 of Fig. 8, traverse connection areas CH' are provided between the basic cells of the single column type array BC1. Formed in each of the traverse connection areas CH' are impurity diffusion regions R₁ and R₂ for avoiding the latch-up phenomenon peculiar to the CMIS configuration. That is, the impurity diffusion region R₁ , which is, in this case, N⁺ type, is used for producing a negative bias voltage in the substrate 1 (Figs. 2 to 4), and the impurity diffusion region R₂ , which is, in this case, P⁺ type, produces a positive bias voltage in the P well 2 (Figs. 2 to 4). For this purpose, the N⁺ impurity diffusion region R₁ is connected via a contact to the power supply connection layer LA₁ (V CC ), and the P⁺ impurity diffusion region R₂ is connected via a contact to the power supply line LA₂ (V SS ). In Fig. 16, which is a modification of Fig. 15, in addition to the longitudinal power supply connection layers LA₁ and LA₂ , a traverse power supply connection layer LB is added to reduce the impedance of the power supply lines for unit cells. In Fig. 16, note that the traverse power supply connection layer LB (V CC ) is connected at its interconnection via a contact to the longitudinal connection layer (in this case, LA₂), but the connection layer LA₂ is not connected to the P⁺ impurity diffusion region R₂. That is, to avoid disconnections, double contacts are prohibited. A clip method for a single column type array having traverse connection areas for impurity diffusion regions and traverse power supply connection layers will be explained below. A clip is performed upon the single column type array as illustrated in Fig. 15, thereby obtaining a single column type array as shown in Fig. 17. Note that Fig. 18 is a cross-sectional view taken along the line XVIII-XVIII of Fig. 17. In this case, a gate G is clipped at V SS when no power supply line is provided along the traverse connection area CH'. That is, N⁺ impurity diffusion region R₂ is connected via a contact CONT₃ to the power supply line LA₂ (V SS ). Therefore, in the case of clipping the gate G to V SS , the gate G is connected by a layer LA₂', which is the same layer as the line LA₂ , through a contact CONT₄ to the impurity diffusion region R₂. Thus, the gate G is connected to the power supply V SS . Also, in Fig. 17, in the case of clipping the gate G to V CC , the left side of the gate G is connected to the N⁺ impurity diffusion region R₁. A clip is performed upon the single column type array as illustrated in Fig. 16, thereby obtaining a single column type array as shown in Fig. 19. Note that Fig. 20 is a cross-sectional view taken along the line XX-XX of Fig. 19. In this case, a gate G is clipped at V SS when a power supply line LB (V SS ) is provided along the traverse connection area CH'. That is, the power supply line LA₁ is connected via a contact CONT₅ to the N⁺ impurity diffusion region R₁ , but the power supply line LA₂ is not connected to the P⁺ impurity diffusion region R₂ , and is connected via a contact CONT₆ to the traverse power supply line LB (V SS ), since double contacts area prohibited for avoiding disconnections. In this case, the P⁺ impurity diffusion region R₂ is connected via the high resistance P well 2 to another P⁺ impurity diffusion region, so that the region R₂ remains at V SS . Therefore, a clip is carried out by connecting the gate G via the contact CONT₇ to the traverse power supply line LB, which is also connected to the power supply line LA₂. Also, in Fig. 19, in the case of clipping the gate G to V CC , the left side of the gate G is connected to the N⁺ impurity diffusion region R₁. Thus, in the case of clipping a gate to V SS , when a power supply line for V SS is provided in a traverse connection channel adjacent thereto, the gate is connected to that power supply line, and when no power supply line is provided in the traverse connection channel, the gate is connected to an impurity diffusion region for avoiding the latch-up phenomenon. Similarly, in the case of clipping a gate to V CC , when a power supply line for V CC is provided in a traverse connection channel adjacent thereto, the gate is connected to that power supply line, and when no power supply line is provided in the traverse connection channel, the gate is connected to an impurity diffusion region for avoiding latch-up. In Fig. 21, which is an enlargement of the double column type array BC2 of Fig. 8, traverse connection areas CH' are provided between the basic cells of the double column type array BC2. Note that such traverse connection areas CH' are common to those of Fig. 15. Also, formed in each of the traverse connection areas CH' are impurity diffusion regions R₁ , R₂ , R₃ , and R₄ for avoiding the latch-up phenomenon peculiar to the CMIS configuration. That is, the impurity diffusion regions R₁ and R₄ , which are, in this case, N⁺ type, is used for producing a negative bias voltage in the substrate 1 (Figs. 2 to 4), while the impurity diffusion regions R₂ and R₃ , which are, in this case, P⁺ type, produce a positive bias voltage in the P well 2 (Figs. 2 to 4). For this purpose, the N⁺ impurity diffusion regions R₁ and R₄ are connected via contacts to the power supply connection layers LA₁ (V CC ) and LA₄ (V CC ), respectively, and the P⁺ impurity diffusion regions R₂ and R₃ are connected via contacts to the power supply lines LA₂ (V SS ) and LA₃, (V SS ), respectfully. In Fig. 22, which is a modification of Fig. 21, in addition to the longitudinal power supply connection layers LA₁ , LA₂ , LA₃ , and LA₄ a traverse power supply connection layer LB is added to reduce the impedance of the power supply lines, for unit cells. In Fig. 22, note that the traverse power supply connection layer LB (V CC ) is connected at its interconnection via a contact to the longitudinal connection layers (in this case, LA₂ and LA₃), but the connection layers LA₂ and LA₃ are not connected to any of the P⁺ impurity diffusion regions R₂ and R₃. That is, also in this case in order to avoid disconnections, double contacts are prohibited. A clip method for a double column type array having traverse connection areas for impurity diffusion regions and traverse power supply connection layers will be explained below. Note that, in a double column type array BC2, since the transistors are formed in the sequence P type - N type - N type - P type or N type - P type - P type - N type, i.e., have an "image by inversion" relationship, thereby avoiding the latch-up phenomenon, the power supply potential on the outside is usually different from the power supply potential on the inner side. Therefore, a request is generated for clipping the inside of a gate to a desired potential. A clip is performed upon the double column type array as illustrated in Fig. 21, thereby obtaining a double column type array as shown in Fig. 23. Note that Fig. 24 is a cross-sectional view taken along the line XXIV- XXIV of Fig. 23. In this case, a gate G is clipped at V SS when no power supply line is provided along the traverse connection area CH'. That is, the N⁺ impurity diffusion region R₂ is connected via a contact CONT₃ to the power supply line LA₂ (V SS ). Therefore, in the case of clipping the gate G to V SS , the gate G is connected by a layer LA₂', which is the same layer as the lines LA₂ and LA₃ , through a contact CONT₄ to the impurity diffusion region R₂. Thus, the gate G is connected to the power supply V SS . Also, in Fig. 23, in the case of clipping the gate G to V CC , the left side of the gate G is connected to the N⁺ impurity diffusion region R₁ , in the same way as in a single column type array. A clip is performed upon the double column type array as illustrated in Fig. 22 thereby obtaining a double column type array as shown on Fig. 25. Note that Fig. 26 is a cross-sectional view taken along the line XXVI-XXVI of Fig. 25. In this case, the gate (G) is clipped at V EE when a power supply line LB(V SS ) is provided along the traverse connection area CH'. That is the power supply line LA, is connected via a contact CONT₅ to the N⁺ impurity diffusion region R₁, but the power supply line LA₂ is not connected to the P⁺ impurity diffusion region R₂, and is connected via a contact CONT₆ to the traverse power supply line LB (V SS ), since power double contacts are prohibited for avoiding disconnections. In this case, the P⁺ impurity diffusion region R₂ is connected via the high resistance P well 2 to another P⁺ impurity diffusion region, so that the region R₂ remains at V SS . Therefore, a clip is carried out by connecting the gate G via the contact CONT₇ to the traverse power supply line LB which is also connected to the power supply line LA₂. Also, in Fig. 25, in the case of clipping the gate G to V CC , the left side of the gate G is connected to the N⁺ inpurity diffusion region R₁. Thus, in the case of clipping an inside gate to V SS , when a power supply line for V SS is provided in a traverse connection channel adjacent thereto, the gate is connected to said power supply line, and when no power supply line is provided, in the traverse connection channel, the gate is connected to an impurity diffusion region for avoiding the latch-up phenomenon. Similarly, in the case of clipping an inside gate to V CC , when a power supply line for V CC is provided in a traverse connection channel adjacent thereto, the gate is connected to said power supply line, and when no power supply line is provided, in the traverse connection channel, the gate is connected to an impurity diffusion region for avoiding latch-up. In the above-mentioned embodiments, the arrangement of transistors within a basic cell is N channel - P channel - P channel - N channel, however, the clip method according to the present invention can be also applied to the arrangement of P channel - N channel - N channel - P channel. As explained above, in a double column type array, it is necessary to clip the inside of the gate. Therefore, it is preferable to provide a space specially for clips inside of the gates in advance, for the design of unit cells. Also, in the above-mentioned embodiments, although the arrangement of a single column type array, a double column type array, and a single column type array are repeated, various modifications are possible if a single column type array is opposed to a double column type array. For example, the arrangement of a single column type array and a double column type array can be repeated. Further, other matrix type arrays such as three column type arrays, four column type arrays, and the like can be used instead of double column type arrays. For example, a gate array integrated device using four column type arrays BC4 instead of double column type arrays BC2 is illustrated in Fig. 27. However, in such a matrix type array such as a three column type array or the like, manual design of connections within a basic cell is carried out as occasion demands. Further, in the above-mentioned embodiments, although a basic cell is constructed by two P-channel transistors and two N-channel transistors, each P-channel/N-channel transistor pair having commonly connected gates, such a basic cell can be constructed by more than three P-channel transistors and the same number of N-channel transistors, each P-channel/N-channel transistor pair having commonly connected gates. In the above-mentioned description, to reduce the impedance of power supply lines, the traverse power supply lines LB are provided. However, to further reduce the impedance of power supply lines, additional longitudinal power supply lines can be provided. That is, as illustrated in Fig. 28, longitudinal power supply lines LC₁ (V CC ) and LC₂ (V SS ) are provided over the longitudinal power supply lines LA₁ (V CC ) and LA₂ (V SS ), respectively. The power supply lines LC₁ (V CC ) is connected via appropriate contacts to the longitudinal power supply line LA₁ (V CC ) and the traverse power supply line LB₁ (V CC ), and the power supply lines LC₂ (V SS ) is connected via appropriate contacts to the longitudinal power supply line LA₂ (V SS ) and the traverse power supply line LB₂ (V SS ). Of course, in this case, double contacts are prohibited. Further, the power supply lines LA₁ and LA₂ are made of a first aluminium layer, the power supply lines LB₁ and LB₂ are made of a second aluminium layer, and the power supply lines LC₁ and LC₂ are made of a third aluminium layer. Since the power supply lines LC₁ and LC₂ of the third layer are deposited on insulating layers having a relatively large step, the power supply lines LC₁ and LC₂ can be easily disconnected. To avoid this, the power supply lines LC₁ and LC₂ are wider than the power supply lines LA₁ , LA₂ , LB₁ , and LB₂ , which is possible since only a small number of lines other than the power supply lines such as LC₁ are made of the third aluminium layer. Thus, the power supply impedance between the basic cells and the power supplies can be remarkably reduced. As illustrated in Figs. 29 and 30, the configuration of the power supply lines can be applied to the entire device of Fig. 8. Note that, in Figs. 29 and 30, the power supply lines such as LA₁ of the first aluminium layer are omitted. A main power supply line (V SS ), which is arranged in the input/output circuits I/O, is made of the third aluminium layer, and a main power supply line (V CC ), which is also arranged in the input/output circuits I/O, is made of the first or second aluminium layer. The main power supply lines are connected directly or via appropriate contacts to the power supply lines LA₁ , LA₂ , ..., LB₁ , LB₂ , ..., LC₁ , LC₂ , .... Further, the main power supply lines in the input/output circuits I/O are wider than the power supply lines LC₁ , LC₂ , ..., thereby further reducing the power supply impedance between the basic cells and the power supplies. As explained above, according to the present invention, since single column type arrays and matrix type arrays such as double column type arrays are mixed, the integration is improved by the reduction of connection areas due to the reduction of the length and number of connections of the matrix type arrays. Also, non-connections due to the limitation of use of the connection areas of the matrix type arrays can be avoided.

Claims: A gate array integrated device comprising: a plurality of single column type arrays (BC1) each comprising a series of basic cells arranged along the column direction of said device; a plurality of matrix type arrays (BC2, BC4) each comprising a plurality of column arrays in proximity to each other along the row direction of said device, each of said column arrays comprising a series of basic cells arranged along the column direction of said device; a plurality of first power supply lines (LA1, LA2,...) arranged along the column direction of said device over said single column type arrays (BC1) and said matrix type arrays (BC2, BC4); and longitudinal connection areas (CH), arranged along the column direction of said device between said single column type arrays (BC1) and said matrix type arrays (BC2, BC4), for providing areas of connections for connecting said basic cells to each other, thereby creating unit cells, each matrix type array being arranged between single column type arrays. A device as set forth in claim 1, wherein each of said basic cells comprises P-channel transistors and N-channel transistors. A device as set forth in claim 2, wherein the sequence of P-channel and N-channel transistors across one column array within one of said matrix type arrays is inverted with respect to its adjacent column array. A device as set forth in claim 1, 2 or 3, further comprising: traverse connection areas (CH') arranged along the row direction of said device between the basic cells of said single column type arrays (BC1); impurity diffusion regions (R1, R2), formed on said traverse connection areas crossing said single column type arrays (BC1), for providing a substrate bias thereto; a plurality of second power supply lines (LB) arranged on said traverse connection areas (CH'); when it is required to clip one gate of said basic cells of said single column type arrays thereby electrically connecting said gate to a source of a desired potential and a power supply line having said desired potential is located at the traverse connection area adjacent to said gate, there being provided conductive means extending between and electrically connecting said gate and said power supply line having said desired potential; and when it is required to clip one gate of said basic cells of said single column type arrays thereby electrically connecting said gate to a source of a desired potential and no power supply line having said desired potential is located at the traverse connection area adjacent to said gate, there being provided conductive means extending between and electrically connecting said gate and one of said impurity diffusion regions formed in the traverse connection area adjacent to said gate. A device as set forth in claim 4, further comprising a plurality of third power supply lines (LC1, LC2,...) each arranged over and connected to one of said first power supply lines (LA1, LA2,...). A device as set forth in claim 5, wherein said third power supply lines (LC1, LC2,...) are wider than said first power supply lines (LA1, LA2,...). A device as set forth in claim 1, 2 or 3, further comprising: traverse connection areas (CH') arranged along the row direction of said device between the basic cells of said matrix type arrays (BC2, BC4); impurity diffusion regions (R1, R4), formed on said traverse connection areas crossing said matrix column type arrays (BC2, BC4), for providing a substrate bias thereto; a plurality of second power supply lines (LB) arranged on said traverse connection areas (CH'); when it is required to clip one gate of an inside one of said basic cells of said matrix type arrays thereby electrically connecting said gate to a source of a desired potential and a power supply line having said desired potential is located at the traverse connection area adjacent to said gate, there being provided conductive means extending between and electrically connecting said gate and said power supply line having said desired potential; and when it is required to clip one gate of an inside one of said basic cells of said matrix type arrays thereby electrically connecting said gate to a source of a desired potential and no power supply line having said desired potential is located at the traverse connection area adjacent to said gate, there being provided conductive means extending between and electrically connecting said gate and one of said impurity diffusion regions formed in the traverse connection area adjacent to said gate. A device as set forth in claim 7, further comprising a plurality of third power supply lines (LC1, LC2,...) each arranged over and connected to one of said first power supply lines (LA1, LA2,...). A device as set forth in claim 8, wherein said third power supply lines (LC1, LC2,...) are wider than said first power supply lines (LA1, LA2,...).

Inventors: FUJII, SHIGERU, KAWAUCHI, KAZUYUKI, TAKAYAMA, YOSHIHISA, YOSHIDA, TOSHIHIKO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H01L27
IPC codes: H01L27, H01L23