NONVOLATILE MEMORY CELL

Abstract: An electrically programmable nonvolatile memory cell (30) includes a semiconductor substrate (31) provided with a highly doped region forming a control electrode (35), overlying which are a first write electrode formed from a first polysilicon layer and forming a capacitor C1, and a portion of a floating gate (33) formed from a second polysilicon layer and forming a capacitor C2. A second write electrode (32) is formed from the first polysilicon layer. Dielectric layers (38, 39) composed of silicon nitride or silicon oxynitride are formed on the write electrodes (34, 32) and are in contact with portions of the floating gate (33) to form capacitors C3, C4. The cell is programmed to a selected high or low state by controlling the voltages applied to the electrodes (35, 34, 32) such that charge is selectively transferred between the floating gate (33) and a selected one of the write electrodes (34, 33). A simple, two-level polysilicon structure is achieved. In a modification, the floating gate is formed from a first polysilicon layer, and the write electrodes from a second polysilicon layer. The second write electrode may be formed by a substrate region (42).

Description: NONVOLATILE MEMORY CELL Technical Field This invention relates to electrically programmable memory cells of the kind including: a substrate having a surface adjacent control electrode formed therein and having a dielectric region formed on said 'surface; an electrically isolated floating gate formed in said dielectric region and in capacitive relationship with said control electrode and in capacitive relationship with the floating gate; a first write electrode formed in said dielectric region and adapted to receive a selected reference voltage and being in capacitive relationship with the ^ floating gate; and control means adapted to apply a selected voltage to said control electrode to effect transfer of charge between said floating gate and said first or second write electrodes, thereby effecting writing of said floating gate to a first or a second voltage level. Background Art The first generation of floating gate programmable ROMs were poly (polycrystalline silicon) structures which were programmed by driving the drain junction to avalanche breakdown to generate so-called "hot" electrons which has sufficient energy to tunnel through the thick gate oxide between the drain and the isolated floating gate. These devices were termed FAMOS as an acronym for their floating gate, avalanche injection MOS characteristics. FAMOS devices, which are members of the class of devices known as electrically programmable ROMs, are erased by irradiating the device with ultraviolet light. The second generation of programmable ROMs include electrically erasable (EEPROM) devices. EEPROM technology includes both two-level and three- level structures. In the two-level approach, the second-level polysilicon control gate is capacitively coupled to the underlying gate of a floating gate MOS transistor structure during electrical writing and erasing. As a consequence, the floating gate can be written by applying high voltage to the control gate and ground to the underlying drain. The cell is erased by reversing the polarities. An electrically programmable nonvolatile memory cell of the kind specified is known from U.S. Patent No. 4,274,012. The known memory cell is a three-level poly EEPROM structure. The first level poly layer includes a reference/ground conductor, the second layer poly includes the floating gate and the third level poly includes a programming/erase electrode. The reference conductor and the floating gate are processed to have upper surface regions containing asperities. These regions generate small currents at locally high electric fields which are sufficient for tunneling charge between the conductors. This structure provides an efficient floating gate cell in terms of size and density. Referring now to Fig. 1, there is shown schematically a version of a three-level nonvolatile memory cell which is disclosed in the aforementioned U.S. Patent No. 4,274,012. The cell 10 features a diffused bias electrode which is used to effect programming and erasing by capacitive coupling. The relevant elements of the cell include the n+ bias electrode 15 formed in p-type substrate 11, and the overlying, stacked three-layer sandwich elements comprising program electrode 12, floating gate 13 and store/erase electrode 14. Regions 16 and 17 of asperities are formed on the upper surfaces of the program electrode 12 and the floating gate 13 for creating the localized electric fields which permit tunneling through the relatively thick oxide regions 18 and 19. The asperities may be produced by oxidation of the polysilicon. The use of the asperities to enhance tunneling characteristics avoids the necessity of forming thin tunneling oxide layers in large volume commercial production operations. To write the structure 10, program electrode 12 and transistor gate 20 are set at system ground, Vgg, and a positive high voltage +V^ is applied to the store/erase gate electrode 14. The program voltage is capacitively coupled via the electrically-floating bias electrode 15 to the floating gate 13, thereby causing electrons to tunnel from the low-potential, program plate 12. To erase, Vgg is applied to the bit line 21 and the associated transistor 20 is turned on _ to connect the Vgg low potential bit line 21 to the bias electrode 15 so that the floating gate 13 is held at Vgg by capacitive coupling. Simultaneously, the positive write voltage, +V-- is applied to the store/erase electrode 14 to tunnel electrons from the low potential floating gate 13 to the store/erase electrode 14. Thus, the known cell has the advantage of a "direct-write" capability, that is, the cell can be directly written to selected high and low threshold states. The floating gate 13 also serves as the gate of a MOS sense transistor (not shown). In the above WRITE 1 of VT1 state, with electrons maintaining the floating gate 13 at a low potential, the sense transistor is held off. Conversely, in the WRITE 0 or VT0 state, floating gate 13 is at a relatively high potential for turning on the associated MOS sense transistor. The primary advantage of the known cell appears to be that the oxides in the charge transfer regions are or can be of a relatively large thickness, for example, about 800 angstroms, thereby enhancing process reproducibility and yields. However, this advantage in the use of asperities or textured polysilicon is accompanied by relatively low endurance (that is, the maximum number of write and erase cycles for which the thresholds VT1 and VTO can be reliably set) . Also, the formation of the asperities involves additional process and structure complexity including a three-level polysilicon arrangement. Other disadvantages include- the stringent processing controls which are necessary to maintain a uniform, reproducible surface texture for field emission from the polysilicon and the reliability of the textured polysilicon oxide. Disclosure of the Invention It is an object of the present invention to provide an electrically programmable nonvolatile memory cell of the kind specified wherein the aforementioned disadvantages are alleviated. Therefore, according to the present invention, an electrically programmable nonvolatile memory cell of the kind specified is characterized in that said first and second write electrodes are in capacitive relationship with said floating gate through respective first and second dielectric layers selected from silicon nitride and silicon oxynitride. It will be appreciated that a nonvolatile memory cell according to the invention has the advantage of a simple, two-level polysilicon structure. A further advantage of the invention is the provision of a simplified direct-write EEPROM cell, that is, an EEPROM memory cell which can be written to a high or low threshold state regardless of the previous threshold state and without first erasing the cell. Yet another advantage is that the cell has improved programming characteristics and endurance. Furthermore, the known cell can use a relatively low programming voltage generation from a single, five volt power supply. Brief Description of the Drawings Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:- Fig, 1 is a schematicized cross-sectional representation of a prior art three-level polysilicon nonvolatile memory cell; Fig. 2 is a circuit schematic of one embodiment of the direct-write EEPROM cell of the present invention; Figs. 3 and 4 are alternative embodiments of the EEPROM cell of Fig. 2; Fig. 5 is a schematicized cross-sectional representation of the basic EEPROM cell structure illustrated in Figs. 2 through 4; Fig. 6 illustrates an alternative construction to that shown in Fig. 5 in which the roles of the first and second level polysilicon layers are reversed; Fig. 7 is an alternative construction to that shown in Fig. 5 in which the ground or reference plate is replaced by a grounded diffusion line; and Fig. 8 is still another alternative construction, in this case, a combination of the structures of Figs. 6 and 7 in which the grounded reference plate of Fig. 6 is replaced by the grounded diffusion line of Fig. 7. Best Mode for Carrying Out the Invention A schematic of one embodiment 30 of the direct-write nonvolatile memory cell of the present invention is shown in Fig. 2. A cross-section of the basic structure of the corresponding cell is shown in Fig. 5. As used here, "direct-write" means no erasing of the memory cell is required. Regardless of the existing state of the memory cell, a VT1 or a VT0 threshold state can be programmed directly into the cell without first erasing. Typically, the cell 30 shown in Figs. 2 and 5 is formed on a p-type substrate 31. A highly-doped, n+ substrate diffusion control electrode 35 is formed in the substrate and a grounded reference plate/electrode 32 and a program gate/electrode 34 are formed from the first-level polysilicon. Overlapping floating gate 33 is formed from the second-level polysilicon. These gates are 0 conventionally formed within, that is, electrically isolated by,silicon dioxide layer(s) 40. In a depar¬ ture from conventional technology and structure, silicon nitride layers 38 and 39 are used as the dielectric between program electrode 34 and the 5 overlying portion of the floating gate 33, and between the overlying portion of the floating gate 33 and grounded reference electrode 32. The respective electrode-nitride-electrode structures form capacitors C3 and C4, which are in the critical current 0 conduction paths used to program the EEPROM to high and low voltage threshold states. Typically, the silicon nitride is formed to a thickness of about 100- 200 Angstroms to allow Poole-Frenkel conduction. The circuit also includes a pair of n-channel 5 enhancement mode transistors Ql and Q2 and floating gate transistor Q3. Note that the transistors Q2 and Q3 are not shown in the cross-sectional view of Fig. 5. However, these transistors are constructed in conventional form and are connected to the elements ° shown in Fig. 5 according to the circuit schematic shown in Fig. 2. CQ3 is the active gate capacitance of the floating gate transistor Q3. Two additional critical path capacitances are Cl, which is formed by the silicon dioxide dielectric between bias control 5 electrode 35 and program electrode 34; and C2, which is formed by the silicon dioxide dielectric between bias control electrode 35 and the floating gate electrode 33. The structure of the cells is such that C2 - Cl » C3 - C4. In addition, the active gate capacitance CQ3 « Cl or C2. To program a low threshold VTO into the EEPROM memory cell of Figs. 2 and 5, the bit line is held near ground potential and the word line is taken to VQQ (approximately +5 volts) to turn on transistors Ql and Q2, while the program line is raised high, to a voltage V--/τ- of about +20 volts. When the program line is raised high, the bias control electrode 35 and associated node A are held at ground potential by <_2. Vc3 and VQ 4 across the critical nitride dielectric capacitors C3 and C4 are then given by: V C3 = C 2 + C 4 + C Q3 V W/E (1) C 2 + C 4 + C 3 + CQ 3 V C4 = C3 V W/E (2) C 2 + C 4 + C 3 + CQ 3 Since C 2 is much greater than C3, C or C Q 3, a large percentage of the applied programming voltage VW E appears by capacitive coupling across C3. Specifical¬ ly, the voltage V Q 3 is given by the capacitive voltage divider relationship (1) and is a relatively large percentage of the applied programming voltage VW E for the given capacitance values. Referring to Fig. 5, the positive programming voltage V-#/E pulls negative charges, electrons, off the floating gate, which is coupled to ground, Vgg, by electrode 32, leaving the floating gate positively charged. During a subsequent READ operation, when the cell is accessed the positive charge on the floating gate maintains floating gate transistor CQ3 in the "on" state to pull the bit line low indicating threshold voltage state VTO. As mentioned above, silicon nitride dielectric layers 38 and 39 are used in capacitor C3 and C 4 . Although it is an excellent insulator, sili¬ con nitride provides a higher current level than does silicon dioxide. The Poole-Frenkel conduction current through the nitride 38 requires lower program voltages than are required for conventional EEPROM programming. In addition, the current direction is bidirectional, depending upon the potential difference across elec- trodes 32/33 (or 34/33), and eliminates the third poly level which is utilized in the cell disclosed in the aforementioned U.S. Patent No. 4,274,012. To program a high threshold voltage, VT1, into the memory cell 30, both the bit line and the word line are held at VQ Q during the program opera¬ tion, while (as before) the program line is brought to the positive programming voltage, V^/g, of about +20 volts. With both the bit line and the word line high, transistor Q2 will turn off as node A begins to rise above Vcc d e to capacitive coupling from the program line through capacitor C]_. The following voltages appear across capacitors C3 and C 4 : (Ci C 2 )/(Cι + C 2 ) + C 3 + C 4 + C Q3 V C4 = (Ci C 2 )/(Cι + c 2 ) + c 3 Vw/E (4) (C X C2 . / . C1 + C 2 ) + C 3 + C 4 + CQ 3 In this case, according to the capacitive voltage divider relationship (4), a large percentage of the programming voltage appears across capacitor C4 rather than across C3. This voltage causes the float¬ ing gate 33 to acquire negatively-charged electrons from the grounded reference plate 32. In particular, since the application of V QQ to both the bit line and the word line turns off transistor Q2 as node A begins to rise above Vcς, the control electrode 35 is float¬ ing. Therefore, the program voltage applied at the program electrode 34 is capacitive-coupled by Ci to bias control electrode 35, and further coupled by C 2 to floating gate 33. The potential between floating gate 33 and grounded reference plate 32 causes elec¬ trons to tunnel across the nitride dielectric layer 39 to provide the necessary transport of electrons to the floating gate to raise the threshold voltage of CQ3 to VT1. Reading of the state stored in the cell is performed by bringing the word line to VQQ , bringing the read gate, where present, to Vcc. holding the program line at a fixed potential and sensing by way of the bit line whether or not a conductive path exists between the bit line and ground potential. Those of skill in the art will appreciate that silicon oxynitride is a viable alternative to silicon nitride for the dielectric layers such as 38 and 39. An alternative direct-write EEPROM cell 40 is shown in Fig. 3. Cell 40 is identical to cell 30 of Fig. 2 except that transistor Q2 is a depletion mode transistor, typically with a threshold voltage of -1 volt to -3 volts and a grounded gate. In this config¬ uration, Ql alone is controlled by the word line. The capacitive divider relationships of expressions (1)- (4) and the method of programming described above for EEPROM cell 30 apply to the embodiment 40 as well. A second alternative embodiment 50 of the present direct-write EEPROM cell is shown in Fig. 4. Again, the capacitive divider relationships (l)-(4) and the programming sequence for EEPROM cell 30 apply. in this case, Ql is controlled by the word line and Q2, which is controlled by the signal applied to the read gate line, is interposed between the ground reference voltage and the floating gate transistor Q3. The positioning of Q2 is necessary because the control electrode, node A, is an integral part of the current path between the bit line and ground during programming. The control electrode must be allowed to float during the programming sequence and Q2 allows this to happen. As described previously, the use of silicon nitride eliminates the need for a three-layer polysilicon structure such as that used in U.S. Patent No. 4,274,012. The three-layer polysilicon stack structure is required in the known cell because the surface asperities can be formed only on the upper polysilicon surface. Charge can flow only from one polysilicon layer to an overlying polysilicon layer by means of the enhanced fields associated with the textured upper surface on the lower layer. That is, electron flow is essentially unidirectional from the textured upper surface. In contrast, because of the use of silicon nitride in the structure of the present embodiment, current flow through the nitride is controlled by the internal nitride field and not by field emission from a textured surface. The current flow is not limited to one direction but rather can flow from one polysilicon layer through the silicon nitride and to a second polysilicon layer beneath it or to the single crystal substrate. In addition to eliminating the need for a third polysilicon layer, the use of silicon nitride improves reliability be- cause of the higher breakdown voltage of silicon nitride as compared to that of the oxide on the tex¬ tured polysilicon. Also, endurance is improved be¬ cause the silicon nitride conductivity is not reduced by write-erase cycling. Alternative embodiments of the Fig. 5 structure are shown in Figs. 6, 7 and 8. In each case, the capacitive voltage divider relationships of equations (l)-(4) and the direct-write VT1 and VTO programming operations are preserved. Specifically, in Fig. 6, the roles of the first-level polysilicon and second-level polysilicon layers are reversed. The floating gate 33A comprises the first-level polysilicon layer, whereas the grounded reference electrode 32A and the program electrode 34A are formed from overlying portions of the second-level polysilicon layer. The silicon nitride dielectric layers 38A and 39A of capacitor C3, C4 are unchanged. Typically, the choice between the structures of Fig. 6 and Fig. 7 would be dictated by the particular processing and layout considerations. Fig. 7 is also similar to Fig. 5 except that the grounded reference electrode plate 32 is replaced by a grounded diffusion region 42. Here, capacitor C4 is formed by the poly 2 floating gate, silicon nitride layer 39B and the diffusion line 42. The choice between the structures in Fig. 6 and Fig. 8 would be dictated typically by cell layout considerations. Finally, the structure of Fig. 8 is essentially a combination of the structures of Figs. 6 and 7 in which the program electrode 34A is part of the second polysilicon layer, the floating gate 33A is part of the first polysilicon layer, and the grounded reference electrode is formed by substrate diffusion line 42. As mentioned, the basic direct-write EEPROM cell shown in various embodiments in Figs. 5 through 8 is common to the different electrical configurations of Figs. 2 through 4 and the same program operation applies in each case. The program operation, which was described at length above, is summarized in the following table. TABLE PROGRAMMING AND READ OPERATION CONNECTIONS BIT WORD PROGRAM READ MODE LINE LINE * LINE GATE READ SENSE AMP CC ov CC PROG. VT1 CC VCC V W/E PROG. VTO 0V CC V W/E Those skilled in the art will realize that various modifications can be made. For example, the opposite substrate and control electrode conductivity types can be used.

Claims: CLAIMS 1. An electrically programmable nonvolatile memory cell, including: a substrate (31) having a surface adjacent control electrode (35) formed therein and having a dielectric region (40) formed on said surface; an electrically isolated floating gate (33) formed in said dielectric region (40) and in capacitive relationship with said control electrode (35); a first write electrode (34) formed in said dielectric region (40) and adapted to receive a program voltage, said first write electrode (34) being in capacitive relationship with said control electrode (35); a second write electrode (32) adapted ^ to receive a selected reference voltage; and control means (Qi) adapted to apply a selected voltage to said control electrode (35) to effect transfer of charge between said gloating gate (33) and said first (34) or second (32) write electrodes, thereby effecting writing of said floating gate (33) to a first or a second voltage level, characterized in that said first and second write electrodes (34, 32) are n capacitive relationship with said floating gate (33) through respective first (38) and second (39) dielectric layers selected from silicon nitride and silicon oxynitride. 2. A nonvolatile memory cell according to claim 1, characterized in that said first and second dielectric layers (38, 39) are formed by silicon nitride having a thickness in the range of about 100- 200 Angstroms. 3. A nonvolatile memory cell according to claim 1, characterized in that said first (34) and second (32) write electrodes include a first layer of • polysilicon, and in that said floating gate (33) includes a second layer of polysilicon which overlies said first layer of polysilicon in the region of said first and second dielectric layers (38, 39) (Fig. 5). 4. A nonvolatile memory cell according to claim 1, characterized in that said floating gate (33A) is formed from a first layer of polysilicon (33A) and in that said first and second write electrodes (34A, 32A) are formed from a second layer of polysilicon and overlie said floating gate (33A) in the region of said first and second dielectric layers (38A, 39A) (Fig. 6). 5. A nonvolatile memory cell according to claim 1, characterized in that said first write electrode is formed from a first layer of polysilicon, in that said floating gate is formed from a second layer of polysilicon and overlies said first layer of polysilicon in the region of said first dielectric layer, in that said second write electrode includes a region (42, Fig. 7) of said substrate (31), in that said second dielectric layer (39B) overlies said ° region (42, Fig. 7) of said -substrate (31) and in that said floating gate overlies said region (42, Fig. 7) of said substrate (31) in the region of said second dielectric layer (39B) (Fig. 7). 6. A nonvolatile memory cell according to claim 1, characterized in that said floating gate (33A, Fig. 8) is formed from a first layer of polysilicon, in that said first write electrode is formed from a second layer of polysilicon and overlies said floating gate in the region of said first dielectric layer, in that said second write electrode ' includes a region (42, Fig. 8) of said substrate (31) and in that said floating gate (33A, Fig. 8) overlies 0 said region (42, Fig. 8) of said substrate in the region of said second dielectric layer (Fig. 8).

Inventors: CYNKAR THOMAS EDWARD, LOCKWOOD GEORGE CORBIN, TOPICH JAMES ANTHONY, TURI RAYMOND ALEXANDER, CYNKAR, THOMAS, EDWARD, LOCKWOOD, GEORGE, CORBIN, TOPICH, JAMES, ANTHONY, TURI, RAYMOND, ALEXANDER
Applicants: NCR CO, NCR CORPORATION
Application year: 1985
Main classification: H01L29
IPC codes: G11C16, H01L27, H01L29