PROCESS FOR PRODUCING AN INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR DEVICE

Abstract: Planarization of an insulating layer (10) formed on a lower wiring layer (8-6, 8-4, 8-2) and having steps at the shoulders of the wiring patterns, can be attained. On a lower wiring layer (8-6, 8-4, 8-2), a lower insulating layer (10) is formed and a heat resistive material (16) is coated over the lower insulating layer, to form a substantially planar top surface and to fill cavities (22) appearing in the surface of the lower insulating layer with material (16). Then, etching is carried out to preserve the profile of the surface of the coating layer (16) and to remove the coating layer at portions (18) where through-holes (26) are to be formed. The cavities (22) are still filled with the material (16) after etching. An upper insulating layer (24) is deposited on the exposed lower insulating layer (10) and the remaining part of the coating layer (16). Through-holes (26) and an upper wiring layer (28) are formed. Thus, the upper wiring layer (28) has no contact with the remaining part of the coating layer (16) and the remaining part of the coating layer is never externally exposed.

Description: The present invention relates to a process for fabricating a multilayer interconnection structure of a semiconductor device. At present, a typical multilayer interconnection structure of a semiconductor device, such as for integrated circuits (IC), is fabricated in the following manner. For example, an aluminum alloy is deposited onto a selectively surface-oxidized silicon semiconductor bulk and patterned to form a lower wiring layer of given patterns. Phospha-silicate glass (PSG) is then deposited onto the lower wiring layer and the exposed bulk by chemical vapor deposition (CVD) to form an insulating layer. After the necessary through-holes are opened in the insulating layer, an aluminum alloy is again deposited onto the insulating layer and in the through-holes and patterned to form an upper wiring layer of given patterns electrically connected with the lower wiring layer through the through-holes. In such a process, the lower wiring layer of given patterns has abrupt steps at the shoulders of the patterns and narrow grooves between adjacent patterns in the same proximity. These steps and grooves cause insufficient coverage of the upper wiring layer on the insulating layer, since the insulating layer also has steps and grooves or cavities corresponding to those of the lower wiring layer. Such insufficient coverage of the upper wiring layer results in a decreased thickness and possible breakage of the upper wiring layer and causes migration and melting (resulting in breakage) of the upper wiring layer due to a concentration of the current. To prevent such insufficient coverage of an upper wiring layer, a planarization process has been proposed in which, after forming the PSG insulating layer, a resin is coated onto the PSG insulating layer, thus planarizing the top surface of the insulating layer. In this process, however, an upper wiring layer is formed on the resin layer and, therefore, the material of the upper wiring layer, such as an aluminum alloy, is placed in contact with the resin layer just under the upper wiring layer and at the through-holes, thereby deteriorating the material of the upper wiring layer due to a chemical reaction therebetween. Further, exposed portions of the resin layer are subjected to contact with chemicals or gases in later processes, causing cracks and etching etc. of the resin layer. These problems make the process unsuitable for practical use. A process for planarizing a PSG layer on a polysilicon wiring layer is described by A.C. Adams and C.D. Capio, in the paper "Planarization of Phosphorus-Doped Silicon Dioxide" (J. Electrochem. Soc., Vol. 128, No. 2, February 1981). In this process, after an organic material such as a photoresist is coated on a PSG layer, the coating material having a relatively smooth top surface, the sacrificial coating of the organic material is etched using conditions in which the organic material and the PSG are etched at nearly the same rates, whereby the original profile of the coating material is maintained, leaving the PSG surface with only smooth, gentle steps. This process necessitates the use of a relatively thick PSG layer so as to at least fill the spaces between lower wiring layers. Such a thick PSG layer cannot be made without forming vacancies therein. Formation of vacancies in the PSG layer may occur above the portions where two patterns of the lower wiring layer are spaced in the same proximity, and sometimes above near abrupt steps of the lower wiring layer. When etching for planarization is finished, vacancies may be opened at the top surface of the etched PSG Layer, leaving open cavities and steps. Thus, insufficient coverage of an upper wiring layer when formed on the PSG layer having such cavities and steps again occurs. Furthermore, the organic material such as a photoresist may enter the vacancies and remain there after the etching is completed, leaving organic material exposed on the top surface of the PSG layer. This exposed organic material may give rise to the same problems as mentioned previously. Thus, this planarization process is also insufficient for practical use. US-A-4 222 792 discloses a planar deep oxide isolation process for providing deep wide SiO₂-filled trenches in the planar surface of a silicon substrate. The process includes steps of: forming trenches in the substrate; forming a thin SiO₂ Layer on the planar surface of the substrate and within the trenches; applying resin glass over the substrate and within the trenches; spinning off at least some of the resin glass on the substrate planar surface; baking the substrate; converting the resin glass in the trenches to SiO₂ by E-beam exposure, solvent developing and heating in oxygen; depositing an SiO₂ layer all over the substrate; and planarizing the exposed SiO₂ surface. EP-A-O 021 818 by the present applicant discloses a multilayer wiring structure having an interlayer insulation layer made of a cured polymer coating giving improved levelling on a pattern. According to the present invention, there is provided a process for producing an interconnection structure of a semiconductor device, comprising the steps of:- forming a lower wiring layer of given patterns on a substrate; forming a lower insulating layer on the lower wiring layer and the substrate; forming a coating layer of a heat resisting material on the lower insulating layer thereby filling cavities appearing in the top surface of the lower insulating layer with the heat resisting material and giving a substantially planar top surface to the coating layer; etching the entire surface of the coating layer until a portion of the coating Layer where through-holes to the lower wiring layer are to be formed is completely removed, whereby the cavities remaining after the etching remain filled with the heat resisting material, and the resultant top surface after the etching is substantially planar; forming an upper insulating layer on the lower insulating layer and the remaining heat resisting material; forming through-holes passing through the upper and lower insulating layers and reaching the lower wiring layer; and forming an upper wiring layer of given patterns on the upper insulating Layer and in the through-holes, the upper wiring layer being electrically connected with the lower wiring layer through the through-holes. An embodiment of the present invention can provide good coverage of an upper wiring layer of given patterns on an insulating layer in a multilayer interconnection structure. An embodiment of the present invention can reduce abrupt steps of an insulating layer on which an upper wiring layer is to be formed in a multilayer interconnection structure; that is, to provide an insulating layer with a substantially planar, smooth top surface when formed on a lower wiring layer of given patterns. An embodiment of the present invention can remove problems caused by an organic material remaining on the surface of an insulating layer on which an upper wiring layer is formed. Reference is made, by way of example, to the accompanying drawings, in which:- Figs. 1A to 1F are partial sectional views of a semiconductor device during fabrication thereof by a process according to the present invention; and Fig. 2 is a partial sectional view of another semiconductor device fabricated by a process according to the present invention. The description of a preferred embodiment of the present invention is made with reference to Figs. 1A to 1F. Referring to Fig. 1A, a semiconductor bulk or substrate 2, for example, a silicon semiconductor bulk, has an insulation Layer 4, for example, a silicon dioxide (SiO₂) layer, on the surface of the bulk 2. The insulating layer 4 is selectively formed and a portion 6 of the bulk 2 is exposed. Such an SiO₂ layer 4 may be formed by, e.g., CVD or selective oxidization of the surface of the silicon bulk 2. A lower wiring layer of given patterns 8-2, 8-4, and 8-6 is formed on the SiO₂ layer and the exposed portion 6 of the bulk 2. The lower wiring layer has a typical thickness of approximately 1 micrometer and a typical line pattern width of approximately 4 micrometers. For example, some patterns 8-2 and 8-4 of the lower wiring layer are spaced at a distance of approximately 1.5 micrometers. A pattern 8-6 of the lower wiring layer is not a line and has a width wider than the typical width of a line of approximately 4 micrometers, e.g., 14 micrometers. The lower wiring layer may be of aluminum, an aluminum silicon alloy (for example, 1% silicon), an aluminum copper alloy (for example, 1% copper), gold, tungsten, or any other metal, or a conductive semiconductor such as doped poly-silicon, or of a multilayer such as titanium tungstenide-aluminium. However, the material and patterns of the lower wiring layer are not limited to the above. Referring to Fig. 1B, for example, PSG is deposited onto the lower wiring layer having patterns 8-2, 8-4, and 8-6 and the exposed SiO₂ layer 4 to form a lower insulating layer 10 having a thickness of approximately 0.7 micrometer by CVD. That is, the thickness of the lower insulating layer may be relatively thin in comparison to the prior art mentioned previously. A lower insulating layer 10 such as a PSG layer formed by CVD etc. in a conventional process does not have good coverage at portions where steps are formed by the thickness of the patterns of the lower wiring layer and at narrow groove-like portions formed by patterns in the same proximity. As seen in Fig. 1B, insufficient coverage of the lower insulating layer 10 results in recesses or cavities 12 near the steps and a recess or cavity 14 between patterns 8-2 and 8-4 in the same proximity. Accordingly, the top surface of the insulating layer 10 is not planar and has abrupt steps and cavities. (If an insulating layer on the lower wiring layer having patterns 8-2, 8-4, and 8-6 is formed in a thickness more than that shown in Fig. 1B, as in the prior art planarization process mentioned previously, the recess or cavity 14 and even the recesses or cavities 12 may grow and become closed pores or vacancies in that thick insulating layer.) A thickness of a lower insulating layer according to the present invention is preferably less than half the shortest distance between adjacent patterns of the lower wiring layer. If the former is more than the latter, a closed pore or vacancy may be formed in the lower insulating layer at least between the narrowest adjacent patterns. A lower insulating layer 10 may be of SiO₂, PSG, SiN or SiON, and may be formed by CVD, sputtering or bias sputtering, plasma CVD, ion plating, or the like. Referring to Fig. 1C, a layer 16 of a heat resisting material is coated over the lower insulating layer 10. The heat resisting material should be able to be applied as a coat, especially by spin coating, in such a manner that the top surface of the coating layer 16 of the heat resisting material becomes substantially planar and smooth, having no abrupt steps, and the material enters and fills the recesses or cavities 12 and 14. The heat resisting material should be resistant to temperatures used in later procedures. Preferably, the material should be resistant to a temperature of approximately 500°C. The resultant thickness of the thus-coated layer 16 will not be uniform, and the thickness will be relatively thin on a flat portion 18 having a relatively small size and relatively thick on a flat portion 20 having a relatively large size. For example, PLOS (a silicone system resin produced by Fujitsu Limited) may be used as a heat resisting material, and may be deposited on the PSG layer 10 by spin-coating at 5000 rpm, and heated at 120°C for 30 minutes to dry the coating layer. The dried coating layer having the thickness of approximately 0.5 micrometer is then heated at 300°C for 30 minutes to change it to an SiO₂-like material. The heat resisting material used for filling recesses or cavities and forming a substantially planar and smooth top surface may be an organic or inorganic material, such as organic or inorganic resins and includes silicon system resins, polyimide (system) resins, for example, PIQ (produced by Hitachi Kasei Kogyo K.K.) and Pyralin PI-2545, PI-2555 (produced by Du-Pont), photosensitive polyimides, heat resistant photoresists, and other resins. Referring to Fig. 1D, when the coating layer 16 is etched, the profile of the surface of the coating layer 16 is preserved during and after the etching so that the resultant surface after the etching is substantially planar, as was the original surface of the coating layer 16 before etching. The coating layer 16 should be removed at least at portions where through-holes are to be formed. This is necessary in order to prevent contact of the material of an upper wiring layer which is formed later with the heat resisting material such as a resin at the through-holes. In Fig. 1D, a through-hole is to be formed at a thickest portion 20 of the coating layer 16. Therefore, etching should be carried out until the coating layer at the thickest portion 20 is completely removed. Further, the lower insulating layer 10 under the thickest portion 20 of the coating layer may be etched in a thickness of a part of the entire thickness thereof. During such etching, thinner portions 18 of the resin layer 16 will be entirely removed and the underlying lower insulating layer 10 will be partially etched at those portions corresponding to the portions 18. The lower insulating layer 10 under the thinner portions 18 of the coating layer 16 is necessarily partially etched since the thicker portion 20 of the coating layer 16 must be etched completely. Therefore, in order to prevent the formation of steps at exposed-by-etching boundaries between the coating layer 16 and the lower insulating layer 10 due to differences in the etching rates thereof, the etching conditions should be selected so that the materials of the coating layer 16 and the lower insulating layer 10 are etched at nearly the same rates. Such a selection of conditions for etching allows preservation of the profile of the substantially planar top surface during and after etching. After etching, the coating layer 16 may be substantially removed or may remain at some portions, but, in any case, the recesses or cavities 12 and 14 which may remain at least partially are filled with the heat resisting material 22 of the coating layer 16. The remaining material 22 of the coating layer 16 in the recesses or cavities 12 and 14 is exposed but does not exist at portions where through-holes are to be formed. The etching conditions mentioned above may be attained in many etching methods including reactive ion etching, plasma etching, ion milling etc. For example, where the coating layer 16 is of PSG formed by CVD, and the lower insulating layer 10 is of SiO₂-like material formed from PLOS, the conditions of a gas mixture of CF₄(130SCCM) + CHF₃(70SCCM), a pressure of 0.3 Torr, and a supply power of 600W in reactive ion etching are suitable to obtain nearly the same etching rates of those two materials. This etching is continued for approximately 2 to 3 minutes, leaving the lower insulating layer 10 having a thickness of approximately 200 nm to 300 nm under the portions 18 and a thickness of approximately 550 nm to 650 nm under the portion 20. The most suitable conditions for etching depend upon the materials of the coating layer 16 and the lower insulating layer 10. Referring to Fig. 1E, an upper insulating layer 24 is then formed on the lower insulating layer 10 and the remaining heat resisting material 22 in the recesses or cavities 12 and 14. This upper insulating layer 24 has a substantially planar top surface, due to the substantially planar top surface of the underlying layer on which the upper insulating layer 24 is formed. The upper insulating layer 24 may be made of the same material and by the same process as those used for the lower insulating layer 10. The thickness of the upper insulating layer 24 is not particularly limited. Referring to Fig. 1F, through-holes 26 are opened in the upper and lower insulating layers 24 and 10 and reach the lower wiring layer having patterns 8-4 and 8-6. The through-holes may be formed by any conventional process. The upper wiring layer 28 of given patterns is formed on the upper insulating layer 24 and in the through-holes 26 by any conventional process. The material of the upper wiring layer 28 may be the same as that of the lower wiring layer having patterns 8-2, 8-4, and 8-6. As can be seen in Fig. 1F, there is no contact between the resultant upper wiring layer 28 and the heat resisting material 22 of the coating layer 16, even under the upper wiring layer 28 or in the through-holes 26. Further, no surface portions of the heat resisting material 22 or the coating layer 16 are exposed, which prevents any reaction between those materials and the chemicals or gases used in later procedures. In the above example, the PLOS used for forming the coating layer 16 is heated at 300°C before etching, to change it to an SiO₂-like material. In such a case, however, the heat treatment used to change a starting material to a final material is preferably carried out after etching is finished (and before the step of forming the upper insulating layer). If the heat treatment is carried out before etching, cracks may appear due to contraction of the material caused by the change from a starting material to a final material. Heat treatment after etching prevents the formation of cracks in the heat resisting material remaining after etching, due to a reduced volume or thickness of the material. It should be noted, however, that the use of such a heat treatment to change a coating layer from a starting material to a final material is not always necessary in a process according to the present invention. In that, in the present invention, materials which do not need such heat treatment may be used as an alternative material. Figure 2 illustrates another multilayer interconnection structure according to the present invention. As shown in Fig. 1C, if etching is stopped shortly after the relatively thinner portions 18 of the coating layer 16 are completely removed, the relatively thicker portion 20 of the coating layer 16 remains on the lower insulating layer 10. This is acceptable if no through-hole is to be formed at the portion 20 where a part 30 of the coating layer (Fig. 2) remains in the form of a layer. In this case, the recesses or cavities 12 and 14 are also filled with the heat resisting material 32, and an upper insulating layer 34, through-holes 36, and an upper wiring layer 36 of given patterns may be formed as in the preceding example. Thus, according to the present invention, an upper wiring layer 28 or 38 can provide good coverage of an underlying insulating layer since the underlying insulating layer has a substantially planar and smooth top surface, preventing the many problems occurring because of insufficient coverage in multilayer interconnection structures, as mentioned previously. Further, the many problems resulting from a material such as an organic resin, e.g., a photoresist, being exposed or having contact with metal etc. of a wiring layer, as in the prior art, can be also eliminated in a process according to the present invention. In the above embodiments, a two wiring layer structure is illustrated, but the process according to the present invention is not limited thereto and may be applied to a multilayer interconnection structure having three or more wiring layers. In that, an upper wiring layer as shown in the above embodiments may be considered to be a lower wiring layer, above which a further wiring layer and intervening insulating layer can be formed according to a process similar to that described in the above embodiments. Or, the substrate may include a further wiring layer below the lower wiring layer with an insulating layer between the further wiring layer and the lower wiring layer.

Claims: A process for producing an interconnection structure of a semiconductor device, comprising the steps of:- forming a lower wiring layer (8) of given patterns on a substrate (2); forming a lower insulating layer (10) on the lower wiring layer and the substrate; forming a coating Layer (16) of a heat resisting material on the lower insulating layer (10), thereby filling cavities appearing in the top surface of the lower insulating layer with the heat resisting material and giving a substantially planar top surface to the coating layer (16); etching the entire surface of the coating layer (16) until a portion of the coating layer where through-holes (26) to the Lower wiring layer (8) are to be formed is completely removed, whereby the cavities remaining after the etching remain filled with the heat resisting material, and the resultant top surface after the etching is substantially planar; forming an upper insulating layer (24) on the lower insulating layer (10) and the remaining heat resisting material (16); forming through-holes (26) passing through the upper and lower insulating layers (24, 10) and reaching the lower wiring layer (8); and forming an upper wiring layer (28) of given patterns on the upper insulating layer (24) and in the through-holes (26), the upper wiring layer being electrically connected with the lower wiring layer (8) through the through-holes (26). A process according to claim 1, wherein the lower and upper insulating layers (10, 24) are made of silicon dioxide, phosphosilicate glass (PSG), silicon nitride, or silicon nitride oxide. A process according to claim 1 or 2, wherein the lower and upper insulating layers (10, 24) are formed by CVD, plasma CVD, sputtering, bias sputtering, or ion plating. A process according to claim 1, 2 or 3, wherein the heat resisting material (16) is a silicone system resin, a polyimide system resin, a photosensitive polyimide, or a heat resisting resist. A process according to claim 1, 2, 3 or 4, wherein the coating layer (16) is formed by spin coating. A process according to any of claims 1 to 5, wherein the coating layer (16) is made by coating a starting material on the lower wiring layer (8) and the exposed substrate (2) and heating the resultant layer of the starting material to cause it to change into a final material. A process according to claim 6, wherein the starting material is a silicone system resin and the final material is a silicon dioxide-like material. A process according to claim 6 or 7, wherein the step of heating for changing the starting material to the final material is effected after the step of etching the coating layer (16) and, if necessary, a part of the lower insulating layer (10), before the step of forming the upper insulating layer (24). A process according to any preceding claim, wherein the etching of the coating layer (16) and a part of the lower insulating layer (10) is carried out with substantially the same etching rates for the coating layer and the lower insulating layer. A process according to any preceding claim, wherein the etching is effected by ion milling, or plasma etching. A process according to any preceding claim, wherein the substrate includes a further wiring layer below the lower wiring Layer with an insulating Layer (4) between the further wiring layer and the lower wiring layer (8). A process according to claim 11, wherein the insulating layer (4) to be formed between the further wiring layer and the lower wiring layer (8) is itself made by a process according to claim 1. A process according to any preceding claim, wherein the lower insulating layer (10) is formed on the lower wiring layer (8) and the exposed substrate (2) in a thickness less than the half of the least space between adjacent patterns of the lower wiring layer (8). A process according to any preceding claim, wherein the lower wiring layer (8) has patterns of different widths. A process according to any preceding claim, wherein the lower wiring layer (8) is of metal or polysilicon. A process according to any preceding claim, wherein the upper wiring Layer (28) is of metal or polysilicon.

Inventors: GOTO, HIROSHI, TAKADA, TADAKAZU, TUCHIYA, TAKAHIRO, TUKUDA, KAZUAKI ROOM 2501 FUJITSU-AOBASAI-RYO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: H01L21
IPC codes: H01L21, H01L23