SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device comprising an error correcting circuit (SEL, VPG, HPG, PCA, CMP) employing a virtual two-dimensional matrix for correcting read data, and a redundant memory cell (RMC₁ ... RMC s ) to replace a defective memory cell (MC), wherein when the selected memory cell (MC) has a previously determined hard error, the selected memory cell is replaced by the redundant memory cell, and when the selected memory cell has a soft error or a hard error occurring after the determination of the previously determined hard error, the read data is corrected by the error correcting circuit.

Description: The present invention relates to a semiconductor memory device having an error correction function. A redundant (redundancy) technique is widely known which improves the yield of semiconductor memory devices. In the redundant technique, a redundant memory cell array storing correct data is added to a regular memory cell array, and when a defective memory cell is selected to be read, a redundant memory cell is actually read in place of the defective memory cell, so that the correct data can be read. However, this redundant technique can be applied only to previously determined defective memory cells. That is, once defective memory cells are determined, other defective read data caused by hard errors or soft errors after the determination of the defective memory cells can not be corrected. An increase in the capacity of a dynamic-type memory device causes increased occurrence of soft errors due to α rays. Whether the data read from the memory is correct or incorrect can be determined by means of parity checking. However, although the presence of an error bit may be determined by the parity checking, the position (address) of the error bit cannot be determined, and accordingly, error correction cannot be performed. To determine the error bit and to make it correctable, an improved parity checking technique employing a parity-checking two-dimensional virtual matrix has conventionally been incorporated into a conventional semiconductor memory device (see, for example, Patent Publication FR-A- 2 502 377, Inventor: Junzo Yamada et al., applicant:- NTT. This conventional semiconductor memory device employing a parity-checking two-dimensional virtual matrix, however, can correct only a single bit error, as later described in more detail, and since the redundant technique is not employed, it provides a low yield. It is desirable for the redundant technique to be combined with the improved parity checking technique so as to be able not only to correct the previously determined hard errors but also to correct soft errors or hard errors caused after the determination of the previously determined hard errors. However, since the parity-checking two-dimensional virtual matrix has a predetermined logic for outputting data in response to a selected memory cell, it is impossible to simply replace a defective column with the redundant column. Therefore, unless a great number of circuit elements for preventing the previously determined defective hard errors from entering the two-dimensional virtual matrix are used, it is difficult to combine the redundant technique with the improved parity checking technique. According to the present invention, there is provided a semiconductor memory device comprising:- a memory cell array including a plurality of memory cells arranged in a matrix; an error correcting circuit including:- a data selector, operatively connected to said memory cell array, for receiving read data from a plurality of memory cells including a selected memory cell, and for selectively outputting a part of said read data which forms horizontal and vertical parity checking groups corresponding to a parity-checking two-dimensional virtual matrix; a vertical parity generator and a horizontal parity generator, operatively connected to the data selector, for generating a vertical and horizontal parity of said data group, respectively; a parity storing memory for storing a previously determined vertical and horizontal parity; a comparator, operatively connected to said vertical and horizontal parity generators and to said parity storing memory, for comparing the outputs thereof to detect an error in said read data; a data correcting gate for correcting said error in said read data in response to an output of said comparator; and a data bus for transferring read data from said data selector to said data correcting gate; characterised by:- a redundant memory cell for replacing a defective memory cell of said memory cell array; a switching circuit for switching between the output of the redundant memory cell and the data bus, connected between the data bus and an input of the data correcting gate; and an inhibit and parity generating circuit, comprising:- an inhibit circuit, operatively connected between said data selector and said vertical and horizontal parity generators; a redundant-cell parity generating circuit, operatively connected to said redundant memory cell and to said vertical and horizontal parity generators; and an inhibit control circuit, operatively receiving an external address signal for selecting a memory cell in said memory cell array, and operatively connected to said switching circuit, to said inhibit circuit and to said redundant-cell parity generating circuit; said inhibit control circuit being operable to generate, in response to an external address which specifies a defective memory cell, a redundant switching signal to be applied to said switching circuit, inhibit signals to be applied to said inhibit circuit, and a control signal to be applied to said redundant-cell parity generating circuit; whereby:- said switching circuit selects the correct data from the redundant memory cell; said inhibit circuit carries out an inhibit operation in which data including error data read from a defective memory cell is inhibited from entering said vertical or horizontal parity generator; and said redundant-cell parity generating circuit generates a redundant vertical or horizontal parity based on said read data not including said inhibited data plus the data from the redundant memory cell. The object of the present invention is to provide a semiconductor memory device in which the redundant technique and the two-dimensional parity checking technique are combined, whereby not only previously determined hard error's along a predetermined bit (column) line but also other soft and hard errors occurring after the occurrence of previously determined hard errors can be corrected, and whereby the yield of the device is improved. This is achieved by adding a relatively simple circuit. Reference is made, by way of example, to the accompanying drawings, wherein: Figure 1 is a circuit diagram showing a conventional semiconductor memory device having a conventional error correction function; Fig. 2 is a table diagram showing the contents of a parity-checking two-dimensional virtual matrix in a data selector in the device shown in Fig. 1; Fig. 3 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention; Fig. 4 is a circuit diagram showing an example of a basic constitution of an inhibit circuit in the device shown in Fig. 3; Fig. 5 is a block diagram showing an example of an inhibit control circuit in the device shown in Fig. 3; Fig. 6 is a circuit diagram showing a semiconductor memory device according to another embodiment of the present invention; and Fig. 7 is a circuit diagram showing an example of an inhibit control circuit in the device shown in Fig. 6. Before describing the embodiments of the present invention, a conventional semiconductor memory device employing a parity checking two-dimensional virtual matrix is described with reference to Fig. 1. In the Figure, MCA is a memory cell array in which a number of dynamic-type memory cells MC are arranged in a matrix fashion, wherein there are provided a number of k x m bit lines BL (wherein k and m are integers) in the horizontal (column) direction and a plurality of word lines WL in the vertical (row) direction. Simultaneously with a selection of one word line WL, data is read out from the memory cells MC of ( k x m ) bits connected to the selected word line WL. In a multiplexer MPX, only one bit thereof is selected in accordance with a selected bit line. DSG s are data selecting gates for effecting this selection of one bit, which is controlled by an output of a not-shown column decoder. DBUS is a data bus for transferring the data of the selected memory cell to an output EOR gate G₁. Simultaneously with the above-mentioned read-out operation, a selector SEL virtually (or logically) rearranges the data of all ( k x m bits) memory cells connected to the selected word line into a parity-checking two-dimensional matrix (hereinafter referred to as an H-V matrix) with m bits in the vertical direction and k bits in the horizontal direction. The contents of the H-V matrix are diagramatically shown in Fig. 2. In the data selector SEL, VSG is a vertical select gate for selecting m -bit data on a selected vertical row of the H-V matrix; and HSG is a horizontal select gate for selecting k -bit data on a selected horizontal column of the H-V matrix. Assume that a memory cell MC (j-1)k+i connected to the left-most word line WL₁ is selected. Then, the vertical select gate VSG selects, by a not shown decoder, m number of memory cells MC i , MC k+i , ..., MC (j-1)k+i , ..., and MC (m-1)k+i virtually arranged on the i-th row of the H-V matrix shown in Fig. 2; and the horizontal select gate HSG selects, by a not-shown decoder, k number of memory cells Mc (j-1)k+1 , MC (j-1)k+2 , ..., MC (j-1)k+i , ..., and MC j virtually arranged on the j-th column of the H-V matrix shown in Fig. 2. Examples of the memory cells selected by the vertical select gate VSG and the horizontal select gate HSG, when i=1 and j=1, for example, are illustrated by shaded circles in Fig. 1. The selected m bits from the vertical select gate VSG are intput to a vertical parity generator VPG; and the selected k bits from the horizontal select gate HSG are input to a horizontal parity generator HPG. The vertical parity generator VPG generates a vertical parity for the m bits; and the horizontal parity generator HPG generates a horizontal parity for the k bits. PCA is a parity cell array including parity cells each storing a correct vertical parity or a correct horizontal parity. The correct parities have been previously written into the parity cells during the writing of data into all of the memory cells MC in the memory cell array MCA. In the construction of the parity cell array PCA, there are m bits of horizontal parity cells HPC and k bits of vertical parity cells VPC connected to each word line WL. BL a represents ( k + m ) bit lines related to these cells HPC and VPC. When the memory cell, for example, MC (j-1)k+i is selected, j-th bit line in the m bit lines BL a is selected; and i-th bit line in the k bit lines BL a is selected so that a horizontal parity cell HPC j and a vertical parity cell VPC i is selected (see Fig. 2). This selection of the parity cells is carried out by parity select gates PSG s in the data data selector SEL. A comparator CMP compares the vertical parity output from the vertical parity generator VPG with the correct vertical parity output from the vertical parity cell VPC i ; and compares the horizontal parity output from the horizontal parity generator HPG with the correct horizontal parity output from the horizontal parity cell HPC j . The comparator outputs "0" when these coincide and outputs "1" when they do not coincide. The output "1" of the comparator CMP is generated, in the H-V matrix shown in Fig. 2, when both of the vertical parity comparison and the horizontal parity comparison simultaneously represent the noncoincidence of the vertical parity of the read data with the correct vertical parity and of the horizontal parity of the read data with the correct horizontal parity. This means that the data read from the memory cell MC (j-1)k+i on the intersection of the selected vertical row and the selected horizontal column in the H-V matrix is not correct. Accordingly, for example, when the output "1" is input to the EOR gate G₁ having another input connected to the data bus DBUS, the read data at that time, that is, the read data generating an error, is inverted. Thus, corrected data D out can be obtained. The error correction function by means of the above-described H-V matrix is effective not only for a soft error due to α rays but also for a hard error caused by a hard defect of a memory cell or for a bit line defect. However, there is a disadvantage in the above-described H-V matrix that the correctable error is only one bit in the memory cells belonging to a common horizontal or vertical parity group. That is, an error can be corrected only when a single bit in any H-V parity check data group in the above-mentioned H-V matrix is an error. To correct a plurality of hard errors, a redundancy technique for remedy of the hard errors, for improving the yield, is publicly known. In a redundant construction in which a row redundancy, i.e., a redundant word line, is provided to replace a defective word line, the conventional technique can be combined with the redundant technique without any difficulty, whereby, hard defects along a predetermined defective word line can be remedied by the redundancy technique, and a soft error or a hard error caused after the determination of the defective word line can be realized by means of the two-dimensional parity checking using the above-mentioned H-V matrix. However, it is difficult to combine the construction of a column (bit line) redundancy with the above-described two-dimensional parity checking. When only the conventional column redundant technique is used, the switching from the defective column to the redundant column could be done merely by controlling the switching of the coupling to the data bus lines from the regular column (defective column) to the redundant column. However, to simply combine the two-dimensional parity checking with the column redundancy, the logic of the switching from the regular column (the memory cells connected to the selected bit line), which must be expressed in a number of H-V matrixes, to the redundant column, becomes too complex. That is, to effect the switching to the redundant column and to also effect the two-dimensional parity checking using the H-V matrix, a defective-column data must be inhibited from mixing with a column-data group from which a parity is to be taken, and the defective column data must be replaced by the redundant column data. Since the location of the generation of the defective column is indefinite, the correspondence between the redundant column and the H-V matrix is difficult to establish without assembling a switching control circuit, thus disadvantageously needing a great number of circuit elements to realize this very complex logic. According to the present invention, however, the combination of the two-dimensional parity checking with the column redundancy can be realized by employing a relatively simple circuit. The embodiments of the present invention are now described in the following. Figure 3 is a circuit diagram illustrating an embodiment of the present invention, in which the same portions as those in Fig. 1 are provided with the same symbols. In Fig. 3, in addition to the memory cell array MCA, the data selector SEL, the multiplexer MPX, the parity cell array PCA, the vertical parity generator VPG, the horizontal parity generator HPG, the comparator CMP, and the EOR gate G₁ , which are included in the conventional device shown in Fig. 1, the semiconductor memory device of this embodiment shown in Fig. 3 further includes a redundant cell array RCA (redundant column) having an output connected to inputs of inhibit circuits IC₂ and IC₃; the outputs of the inhibit circuits IC₂ and IC₃ and the outputs of the horizontal and vertical parity generators HPG and VPG are respectively input to EOR gates G₂ and G₃; inhibit circuits IC₀ and IC₁ are inserted between the data selector SEL and the horizontal and vertical parity generators HPG and VPG; a switching circuit SW for switching between the output of the redundant cell array RCA and the data bus DBUS is connected between the data bus DBUS and an input of the EOR gate G₁; and, these inhibit circuits IC₀ through IC₃ and the switching circuit SW are controlled by an inhibit control circuit CTL. In the redundant cell array RCA, the same number s of redundant memory cells RMC₁ , RMC₂ , ..., and RMC s as that of the memory cells connected to each regular bit line in the memory cell array MCA are arranged, each redundant memory cell being selected by a word line WL common to the memory cell array MCA. EOR gates G₄ and G₅ and AND gate G₆ constitute the comparator CMP, which is the same as that shown in Fig. 1. The outputs of the EOR gates G₂ and G₃ are, respectively, one of the inputs of the EOR gates G₄ and G₅. The other inputs of these EOR gates G₄ and G₅ respectively receive a horizontal parity HP and a vertical parity VP from the parity cell array PCA. Figure 4 shows an example of a basic circuit for constituting the inhibit circuits IC₀ through IC₃. The inhibit circuits IC₂ and IC₃ are respectively formed by one set of the basic circuit; the inhibit circuit IC₀ is formed by k sets of the basic circuits; and the inhibit circuit IC₁ is formed by m sets of the basic circuits. DB represents an input of the basic circuit; and DBP represents an output of the basic circuit. In practice, since each of the outputs of the data selector SEL are complementary, an inverted input DB and inverted output DBP also occur. V cc is a power supply voltage for providing a high (H) level. GND is the ground potential for providing a low (L) level. MOS transistors Q₁ and Q₂ are for inhibiting inputs DB and DB . When these transistors Q₁ and Q₂ are ON, the inputs DB and DB are permitted to pass through to the outputs DBP and DBP . When the transistors Q₁ and Q₂ are OFF, the inputs DB and DB are inhibited and cannot pass through to the outputs DBP and DBP . The control of these transistors Q₁ and Q₂ is effected by the output N₁ of a MOS inverter consisting of transistor Q₅ and Q₆. The transistor Q₅ is a depletion-type MOS transistor. That is, when an inhibit signal IS, given by the inhibit control circuit CTL, is at the high (H) level, the output N₁ of the inverter becomes low (L) level so that the transistors Q₁ and Q₂ are OFF, thus preventing the levels of the inputs DB and DB from passing through Q₁ and Q₂ to reach the outputs DBP and DBP . Instead, the transistors Q₃ and Q₄ are turned ON so that the output DBP is fixed at the low (L) level and the output DBP is fixed at the high (H) level. In the following, assume that the memory cell MC (j-1)k+i arranged on the intersection between a word line WL₁ and a bit line BL (j-1)k+i , that is, on the coordinate (i, j) of the H-V matrix (see Fig. 2), is a previously determined defective memory cell. In other words, the bit line, to which the memory cell MC (j-1)k+i is connected, is the previously determined bit line. The reading operation of the semiconductor memory device shown in Fig. 3 is described with reference to Figs. 2, 3, and 4. (1) When the defective memory cell MC (j-1)k+i is selected to be read, the inhibit circuit IC₀ receives the error data from the i-th line in the k lines connected to the output of the horizontal select gate HSG; and the inhibit circuit IC₁ receives the error data from the j-th line in the m lines connected to the output of the vertical select gate VSG. In the inhibit circuit IC₀ , the error data is received by the i-th basic circuit in the k sets of the basic circuits; and in the inhibit circuit IC₁ , the error data is received by the j-th basic circuit in the m sets of the basic circuits. The i-th inhibit signal IS in the k bits of inhibit signal data IS k generated by the inhibit control circuit CTL is at the H level in accordance with the external address a₁ through a n for specifying the defective bit line. Therefore, the inhibit circuit IC₀ inhibits the error data from passing through to the i-th output in the k-bit output thereof; and the inhibit circuit IC₁ inhibits the error data from passing through to the j-th output in the m -bit output thereof. In other words, the j-th output of the inhibit circuit IC₀ and the k-th output of the inhibit circuit IC₁ are both fixed at the L level, i.e., at "0". Therefore, the horizontal parity generator HPG and the vertical parity generator VPG respectively generate horizontal and vertical parities of the read data, without taking the inhibited error data into account. On the other hand, the inhibit control circuit CTL generates redundant-cell inhibit signals RAS k and RAS m of the H level in accordance with the external address for specifying the defective bit line. In response to the redundant-cell inhibit signals RAS k and RAS m , the inhibit circuits IC₂ and IC₃ pass the correct data stored in the redundant memory cell array RCA. The correct data in the redundant memory cell RMC₁ is selected in response to the selected word line WL₁. The EOR gate G₂ generates a horizontal parity of the correct read data; and the EOR gate G₃ generates a vertical parity of the correct read data. In the comparator CMP, the EOR gate G₄ compares the horizontal parity of the correct data with the correct horizontal parity transferred from the parity cell array PCA through the parity select gate PSG; and the EOR gate G₅ compares the vertical parity of the correct data with the vertical parity transferred from the parity cell array PCA. Unless the parity of the remaining data group obtained at the output of the horizontal parity generator HPG or the vertical parity generator VPG represents an error, the output of the comparator becomes "0". The switching circuit SW selects the correct data from the redundant cell array RCA in response to a redundant switching signal RS of "0" applied from the inhibit control circuit CTL. Thus, the correct data is read out at the output D out . In conclusion, for the previously determined hard errors, the redundant technique is effectively used to read correct data in the semiconductor memory device shown in Fig. 3. (2) When a memory cell other than the defective memory cell MC (j-1)k+i is selected to be read, the reading operation is as follows. Assume that the selected memory cell is MC (j-1)k+i+p arranged on the coordinate (i+p, j) of the H-V matrix. Referring to Fig. 2, the memory cell MC (j-1)k+i+p is arranged on the same horizontal column of the H-V matrix as the defective memory cell MC (j-1)k+i , while the vertical row (i+p) on which the selected memory cell is arranged is different from the vertical row i of the defective memory cell MC (j-1)k+i . If a soft error or a hard error occurs on the selected memory cell MC (j-1)k+i+p after the determination of the defective bit line, the horizontal parity generator HPG and the vertical parity generator VPG receive the error data passed through the inhibit circuits IC₀ and IC₁. If the inhibit circuit IC₀ is not provided as in the conventional device shown in Fig. 1, the error data of the defective memory cell MC (j-1)k+i also is transferred through the i-th line of the k lines from the horizontal select gate HSG, so that the horizontal select gate HSG receives two error bits, causing the parity checking to become impossible. However, since the inhibit circuits IC₀ and IC₁ are provided in this embodiment, the i-th inhibit signal IS in the k bits of the inhibit signal data IS k generated by the inhibit control circuit CTL is at the H level because the selected memory cell MC (j-1)k+i+p and the defective memory cell MC (j-1)k+i are both arranged on the same j-th horizontal column in the H-V matrix. Therefore, the inhibit circuit IC₀ inhibits the error data of the defective memory cell MC (j-1)k+i from passing therethrough. Note, since the vertical row (i+p) to which the selected memory cell MC (j-1)k+i+p belongs is different from the vertical row (i) of the defective memory cell MC (j-1)k+i , the inhibit circuit IC₁ does not effect the inhibit operation. The redundant-cell inhibit signal RAS k is set to "1" in accordance with the external address a₁ through a n , particularly with a part of the external address for specifying the j-th column in the H-V matrix, so that the inhibit circuit IC₂ passes the correct data from the redundant memory cell RMC₁ to the EOR gate G₂. The redundant-cell inhibit signal RAS m is set to "0" in accordance with another part of the external address for specifying the (i+p)-th row in the H-V matrix, so that the output of the inhibit circuit IC₃ is fixed to "0". Thus, the EOR gate G₂ outputs a parity obtained based on the output of the horizontal parity generator HPG and the correct data from the redundant cell array RCA; and the EOR gate G₃ outputs a parity obtained based on only the output of the vertical parity generator VPG. The comparator CMP compares these parities with the horizontal parity HP and the vertical parity generated from the parity cell array PCA. If the read memory cell MC (j-1)k+i+p has a soft error or a hard error caused after the determination of the defective bit line, these parities do not coincide so that the comparator CMP outputs "1". If the read memory cell MC (j-1)k+i+p has no error, the comparator CMP outputs "0". The switching circuit SW selects the data from the data bus DBUS in response to the redundant switching signal RS of "1". If the comparator CMP outputs "1", the EOR gate G₁ inverts the data from the data bus DBUS; and if the comparator CMP outputs "0", the EOR gate G₁ passes the data from the data bus DBUS without inversion. As a result, regardless of whether the read memory cell MC (j-1)k+i+p has a soft or hard error, correct data can be read at the output D out . When a memory cell MC (j-1+q)k+i , arranged on the intersection of the (j+q)-th horizontal column and the i-th vertical row, is selected, the parity checking is also possible in the same way as described above. The signals IS k , IS m , RAS k , RAS m , and RS are generated by the inhibit control circuit CTL. Figure 5 shows a practical example of the inhibit control circuit CTL. In Fig. 5, the inhibit control circuit CTL comprises a read only memory (defective-column address memory) ROM for previously storing the address of the defective column line (defective bit line) having a hard defect (in the following, this address is referred to as a defective column address), and an inhibit signal generating circuit ISG which compares the defective column address with the external column address a₁ through a n for selecting a bit line BL, and when there is a coincidence, turns the corresponding inhibit signal IS to H. The inhibit signal generating circuit ISG includes two comparators CMP₁ and CMP₂ , two decoders DEC₁ and DEC₂ , two AND gates G₁₁ and G₁₂ , two OR gates G₁₃ and G₁₅ , two inverters G₁₄ and G₁₆ , and an AND gate G₁₇. The external address a₁ through a n for specifying a bit line are divided into two groups, i.e., a₁ through a i and a i+1 through a n , where 2 i =k and 2 n-i =m. The first group of address a₁ through a i (in the following, referred to as a horizontal external-column address) is used for specifying the i-th vertical row from k rows in the H-V matrix shown in Fig. 2. The second group (in the following, referred to as a vertical external-column address) a i+1 through a n is used for specifying the j-th column from m columns in the H-V matrix shown in Fig. 2. The horizontal external-column address a₁ through a i is input to the vertical-address comparator CMP₂. The vertical external-column address a i+1 through a n is input to a horizontal-address comparator CMP₁. The defective-column address stored in the memory ROM is expressed by A₁ through A n . The number of bits of the defective-column address A₁ through A n is, from the nature of the case, the same as the number of bits of the external column address a₁ through a n . The defective-column address A₁ through A n is also divided into two groups, i.e., A₁ through A i and A i+1 through A n . The first group of the defective-column address A₁ through A i (horizontal defective-column address) is compared with the horizontal external-column address a₁ through a i by the vertical-address comparator CMP₂. The second group of the defective-column address (vertical defective-column address) A i+1 through A n is compared with the second group of the external column address a i+1 through a n by the horizontal-address comparator CMP₁. the horizontal-address comparator CMP₁ generates a horizontal column inhibit-activating signal IAS k of "1" when a i+1 through a n coincides with A i+1 through A n . The vertical-address comparator CMP₂ generates a vertical column inhibit-activating signal IAS m of "1" when a₁ through a i coincides with A₁ through A i . The horizontal defective-column address A₁ through A i and the vertical defective-column address A i+1 through A n are respectively transferred to a horizontal address decoder DEC₁ and a vertical address decoder DEC₂. The horizontal address decoder DEC₁ decodes the address A₁ through A n to provide a k -bit decoded signal DFA k in which only one bit is "1", which represents the position of the defective row in the H-V matrix shown in Fig. 2. The output DFA m of the vertical address decoder DEC₂ has m bits in which, also, only one bit becomes "1", which represents the position of the defective row in the H-V matrix. The cross point on the H-V matrix, indicated by the outputs DFA k and DFA m , represents the position of the defective memory cell. For example, when the bit line BL (j-1)k+i is defective and, therefore, the memory cell MC (j-1)k+i is defective, the i-th bit in the k-bit signal DFA k becomes "1", and the j-th bit in the m-bit signal DFA m becomes "1". In this case, the i-th column and the j-th row in the H-V matrix are defective. When the horizontal column inhibit-activating signal IAS k is applied to a horizontal-column AND gate G₁₁ , that is, when the horizontal external-column address a₁ through a n coincides with the horizontal defective-column address A₁ through A n , the decoded signal DAF k is passed through the AND gate G₁₁ so that, in the output signal IS k of k bits, only one bit (i-th bit) becomes "1". Also, when the vertical column inhibit-activating signal IAS m is applied to a vertical-column AND gate G₁₂ , that is, when the vertical external-column address a i+1 through a n coincides with the vertical defective-column address A i+1 through A n , the decoded signal DFA m is passed through the AND gate G₁₂ so that, in the output signal IS m of m bits, only one bit (j-th bit) becomes "1". When the inhibit-activating signals IAS k and IAS m are not generated because of noncoincidence of the external address and the defective address, all bits of the signals IS k and IS m are "0". The signals IS k and IS m are applied as inhibit signals to the inhibit circuits IC₀ and IC₁ (Fig. 3), respectively. The inhibit signals IS k and IS m are also transferred to the inputs of OR gates G₁₃ and G₁₅ , respectively. When one of the k bits in the inhibit signal IS k is "1", the output of the OR gate G₁₃ becomes "1". Also, when one of the m bits in the inhibit signal IS m is "1", the output of the OR gate G₁₅ becomes "1". In the other case when all bits of the inhibit signal IS k or IS m are "0", the output of the OR gate G₁₃ or G₁₅ is "0". The outputs of the OR gates G₁₃ and G₁₅ are respectively inverted by inverter gates G₁₄ and G₁₆ so that redundant-cell inhibit signals RAS k and RAS m are generated from the outputs of the inverters G₁₄ and G₁₆. The redundant-cell inhibit signals RAS k and RAS m are respectively applied to the inhibit circuits IC₂ and IC₃ (Fig. 3). The inhibit signal IS shown in Fig. 4 is one of the k -bits of the inhibit signal IS k , one of the m -bits of the inhibit signal IS m , the redundant-cell inhibit signal RAS k , or the redundant-cell inhibit signal RAS m . The redundant switching signal RS is generated when both of the inhibit-activating signals IAS k and IAS m become "1", that is, when the external address a₁ through a n coincides with the defective column address A₁ through A n . In response to the signal RS, the switching circuit SW (Fig. 3) selects from the redundant cell array RCA the correct data to be transferred to the EOR gate G₁. As is apparent from the foregoing description, according to the first embodiment, parity checking can be carried out and correct data can be read not only when the redundant memory cell is accessed in place of the previously determined defective memory cell, but also when another memory cell is accessed which may have a soft or a hard error produced after the determination of the defective bit line. Figure 6 is a circuit diagram showing another embodiment of the present invention in which a hard defect in the parity cell array PCA can be remedied. In the first embodiment shown in Fig. 3, the case where a memory cell MC is replaced by a redundant memory cell RMC was shown. In the second embodiment shown in Fig. 6, this concept is further expanded so that not only a defective memory cell MC but also a defective parity cell connected to the same defective bit line can be replaced by the redundant memory cell. Practically, an inhibit circuit IC₄ for the horizontal parity cells HPC and an inhibit circuit IC₅ for the vertical parity cells VPC are added, the outputs of which, and the outputs of the parity generators HPG and VPG, are, at first, input to the EOR gates G₂ and G₃. The additional inhibit circuits IC₄ and IC₅ are respectively controlled by additional parity inhibit signals PIS m and PIS k . The outputs of the EOR gates G₂ and G₃ are connected to one of the inputs of the EOR gates G₄ and G₅ , respectively. The output of the redundant cell array RCA is connected, through the inhibit circuit IC₂ , to another input of the EOR gate G₄ , and, through the inhibit circuit IC₃ , to another input of the EOR gate G₅. A modified inhibit control circuit CTL a generates the inhibit signals PIS m and PIS k , as well as inhibit signals IS ka , IS ma , and a redundant parity cell switching signal RS a , which are similar to the inhibit signals IS k , IS m , and the redundant switching signal RS shown in Fig. 3. Figure 7 is a circuit diagram illustrating an example of the modified inhibit control circuit CTL a . In Fig. 7, in addition to the elements in the inhibit control circuit shown in Fig. 5, an OR gate G₂₁ , an inverter gate G₂₆ , and AND gates G₂₂ through G₂₅ are provided. The ROM stores, in addition to the defective column address A₁ through A n of the defective bit line of the defective memory cells, data RVP and RHP. When the data RHP or RVP is "1", the parity cells arranged on the defective address A₁ through A i or A i+1 through A n are defective, respectively. By this constitution, the parity inhibit signal PIS k is generated when both conditions, i.e., when the vertical external-column address a i+1 through a n coincides with the vertical defective-column address A i+1 through A n and when the data RVP is "1" expressing that the vertical parity cells VPC are defective, are satisfied; and the parity inhibit signal PIS m is generated when the horizontal external-column address a₁ through a i coincides with the horizontal defective-column address A₁ through A i and when the data RHP is "1" expressing that the horizontal parity cells VHC are defective. The modified inhibit-activating signal IAS ka of "1" is generated in both conditions when the parity cells are not defective (RHP="0" and RVP="0") and when the external address a i+1 through a n coincides with the defective address A i+1 through A n ; and the modified inhibit-activating signal IAS ma of "1" is generated in both conditions when the data RHP and RVP are "0" and when the external address a₁ through a i coincides with the defective address A₁ through A i . The AND gate G₁₁ passes the decoded output DFA k which becomes the modified inhibit signal IS ka in response to the inhibit-activating signal IAS ka of "1", and the AND gate G₁₂ passes the decoded output DFA m which becomes the modified inhibit signal IS ma in response to the inhibit-activating signal IAS ma of "1". The modified inhibit signal RAS ka is "1" when all of the bits in the signal IS ka and the parity inhibit signal PIS k are "0"; and the signal RAS ka is "0" when at least one of the bits in the signals IS ka and PIS k is "1". The modified inhibit signal RAS ma is "1" when all of the bits in the signal IS ma and the signal PIS m are "0"; and the RAS ma is "0" when at least one of the bits in the signals IS and PIS m is "1". The redundant parity cell switching signal SW a is generated when both data RHP and RVP are "0" and when the external address a₁ through a n coincides with the defective address A₁ through A n . Referring back to Fig. 6, the operation of the semiconductor memory device according to the second embodiment is described in the following. (1) When the parity cell array PCA does not include a hard error, the data RHP and RVP (Fig. 7) are "0" and thus the parity inhibit signals PIS k and PIS m are "0". Therefore, the inhibit circuits IC₄ and IC₅ pass the horizontal parity and the vertical parity therethrough. (i) In this state, when the external address a₁ through a n does not coincide with the defective address A₁ through A n , the comparators CMP₁ and CMP₂ output "0" and thus the inhibit-activating signals IAS ka and IAS ma are "0", fixing all bits in the inhibit signals IS ka and IS ma at "0", and fixing the redundant address signals RAS ka and RAS ma at "1" (see Fig. 7). As a result, the outputs of the inhibit circuits IC₂ and IC₃ are fixed at "0" in response to the "0" of the signals RAS ka and RAS ma . Accordingly, the EOR gates G₄ and G₅ pass the horizontal parity and the vertical parity without inversion to the inputs of the AND gate G₆. The switch circuit SW selects the data bus DBUS in response to the redundant selecting signal RS a , which is "0" because the comparators CMP₁ and CMP₂ output "0". (ii) When the external address a₁ through a n coincides with the defective address A₁ through A n , the comparators CMP₁ and CMP₂ output "1". The data RVP and RHP of "0" are inverted by the inverter gate G₂₆. Therefore, the AND gates G₂₂ and G₂₃ output "1". As a result, the signal DFA k is passed through the AND gate G₁₁ to become the signal IS ka ; the signal DFA m is passed through the AND gate G₁₂ to become the signal IS ma ; the signals RAS ka and RAS ma are "1" because the signals IS ka and IS ma respectively include at least one bit of "1"; the signal RS a becomes "1"; and the signals PIS k and PIS m are "0" (see Fig. 7). Thus, the correct data from the data bus DBUS can be read at the output D out in a similar way to the first embodiment. (2) Contrary to this, when the parity cell array PCA has a hard defect, the redundant cell array RCA is used in place of the parity cell array PCA, and, to this end, when the defective bit is read from the parity cell array PCA, the fixed "0" is output from the inhibit circuit IC₄ or IC₅ in response to "1" of the parity inhibit signal PIS k or PIS m . And, instead, the inhibit circuit IC₂ or IC₃ is made to through state in response to "0" of the redundant address signal RAS ka or RAS ma , enabling the use of the output of the redundant cell array RCA as the parity data. That is, when the external address a₁ through a n coincides with the defective address A₁ through A n , and when the RVP or RHP is "1", the AND gates G₂₂ or G₂₃ outputs "0" because the output of the inverter gate G₂₆ is "0". Therefore, the signal IS ka and IS ma are "0"; the signal RS a is "0"; the signals PIS k and PIS m are "1"; and the signals RAS ka and RAS ma are "0" (see Fig. 7). From the foregoing description, it will be apparent that, according to the present invention, in a semiconductor memory device having a function of parity checking by employing an H-V matrix, since previously determined hard defects can be replaced by redundant memory cells, the parity checking function can be advantageously used for a soft error or a hard error occurring after the determination of the previously determined hard defects. Further, the yield of the semiconductor memory device having a function of parity checking with an H-V matrix can be improved by employing a redundant memory cell array. Still further, the redundant technique and the parity checking technique using an H-V matrix can be combined by adding a relatively simple circuit. As explained above, an embodiment of the present invention can provide a semiconductor memory device comprising an error correcting circuit employing a virtual two-dimensional matrix for correcting read data, and a redundant memory cell to replace a defective memory cell, wherein when the selected memory cell has a previously determined hard error, the selected memory cell is replaced by the redundant memory cell, and when the selected memory cell has a soft error or a hard error occurring after the determination of the previously determined hard error, the read data is corrected by the error correcting circuit. The embodiment of the present invention provides a semiconductor memory device having an error correction function, which device can process both a soft error and a hard error by adding an error correction code (ECC) and redundant bits.

Claims: A semiconductor memory device comprising:- a memory cell array (MCA) including a plurality of memory cells arranged in a matrix; an error correcting circuit including:- a data selector (SEL), operatively connected to said memory cell array, for receiving read data from a plurality of memory cells including a selected memory cell, and for selectively outputting a part of said read data which forms horizontal and vertical parity checking groups corresponding to a parity-checking two-dimensional virtual matrix (VSG, HSG); a vertical parity generator (VPG) and a horizontal parity generator (HPG), operatively connected to the data selector, for generating a vertical and horizontal parity of said data group, respectively; a parity storing memory (PCA) for storing a previously determined vertical and horizontal parity; a comparator (CMP), operatively connected to said vertical and horizontal parity generators and to said parity storing memory, for comparing the outputs thereof to detect an error in said read data; a data correcting gate (G₁) for correcting said error in said read data in response to an output of said comparator (CMP); and a data bus (DBUS) for transferring read data from said data selector (SEL) to said data correcting gate (G₁); characterised by:- a redundant memory cell (RMC) for replacing a defective memory cell of said memory cell array (MCA); a switching circuit (SW) for switching between the output of the redundant memory cell (RMC) and the data bus (DBUS), connected between the data bus (DBUS) and an input of the data correcting gate (G₁); and an inhibit and parity generating circuit (IC₀-IC₃, CTL, G₂, G₃), comprising:- an inhibit circuit (IC₀, IC₁), operatively connected between said data selector (SEL) and said vertical and horizontal parity generators (VPG, HPG); a redundant-cell parity generating circuit (IC₂, IC₃, G₂, G₃), operatively connected to said redundant memory cell and to said vertical and horizontal parity generators (VPG, HPG); and an inhibit control circuit (CTL), operatively receiving an external address signal for selecting a memory cell in said memory cell array, and operatively connected to said switching circuit (SW), to said inhibit circuit (IC₀, IC₁) and to said redundant-cell parity generating circuit (IC₂, IC₃, G₂, G₃); said inhibit control circuit (CTL) being operable to generate, in response to an external address which specifies a defective memory cell, a redundant switching signal (RS) to be applied to said switching circuit (SW), inhibit signals (IS) to be applied to said inhibit circuit (IC₀, IC₁), and a control signal (RAS) to be applied to said redundant-cell parity generating circuit (IC₂, IC₃, G₂, G₃); whereby:- said switching circuit (SW) selects the correct data from the redundant memory cell (RMC); said inhibit circuit (IC₀, IC₁) carries out an inhibit operation in which data including error data read from a defective memory cell is inhibited from entering said vertical or horizontal parity generator; and said redundant-cell parity generating circuit (IC₂, IC₃, G₂, G₃) generates a redundant vertical or horizontal parity based on said read data not including said inhibited data plus the data from the redundant memory cell. A semiconductor memory device as set forth in claim 1, wherein said data selector (SEL) comprises:- a vertical select gate (VSG), operatively connected between said memory cell array and said vertical parity generator, for selecting m-bit data on a selected vertical row of said parity-checking two-dimensional virtual matrix from a selected k x m bits input from said memory cell array to said data selector; and a horizontal select gate (HSG), operatively connected between said memory cell array and said horizontal parity generator, for selecting k -bit data on the horizontal row on said parity-checking two-dimensional virtual matrix from said selected k x m bits. A semiconductor memory device as set forth in claim 2, wherein said inhibit circuit comprises:- a first inhibit circuit (IC₀), operatively connected between said horizontal select gate and said horizontal parity generator, for inhibiting one of said k -bits from passing from said horizontal select gate into said horizontal parity generator in response to a first inhibit signal (IS k ) of said inhibit signals (IS), said first inhibit signal being generated in said inhibit control circuit when said defective memory cell is accessed; and a second inhibit circuit (IC₁), operatively connected between said vertical select gate and said vertical parity generator, for inhibiting one of said m bits from passing from said vertical select gate into said vertical parity generator in response to a second inhibit signal (IS m ) of said inhibit signals (IS), said second inhibit signal being generated when said defective memory cell is accessed. A semiconductor memory device as set forth in claim 3, wherein said redundant-cell parity generating circuit comprises:- a third inhibit circuit (IC₂), operatively connected to said redundant memory cell, for inhibiting data read from said redundant memory cell from passing through said third inhibit circuit in response to a third inhibit signal (RAS k ) of said inhibit signals, said third inhibit signal being generated when said defective memory cell is not accessed; a fourth inhibit circuit (IC₃), operatively connected to said redundant memory cell, for inhibiting data read from said redundant memory cell from passing through said fourth inhibit circuit in response to a fourth inhibit signal (RAS m ) of said inhibit signals, said fourth inhibit signal being generated when said defective memory cell is not accessed; a first redundant parity gate (G₂) having inputs operatively connected to the outputs of said horizontal parity generator and said third inhibit circuit, for generating said redundant horizontal parity; and a second redundant parity gate (G₃) having inputs operatively connected to the outputs of said vertical parity generator and said redundant memory cell, for generating said redundant vertical parity. A semiconductor memory device as set forth in claim 4, wherein said comparator comprises:- a horizontal parity gate (G₄), having inputs operatively connected to the output of said first redundant parity gate and to said parity storing memory, for effecting a horizontal parity processing based on said redundant horizontal parity and said previously determined horizontal parity; a vertical parity gate (G₅), having inputs operatively connected to the output of said second redundant parity gate and to said parity storing memory, for effecting a vertical parity processing based on said redundant vertical parity and said previously determined vertical parity; and an AND gate (G₆) having inputs operatively connected to the outputs of said horizontal parity gate (G₄) and said vertical parity gate (G₅), for providing a coincidence signal when said outputs of said horizontal parity gate and said vertical parity gate coincide. A semiconductor memory device as set forth in claim 4 or 5, wherein said inhibit control circuit comprises:- a defective-column address memory (ROM) having a storing area for storing the defective column address (A₁-A n ) of said defective memory cell; and an inhibit-signal generating circuit (ISG), operatively receiving said defective column address of said defective memory cell and an external column address signal for specifying a memory cell, for providing said inhibit signals when said defective column address coincides with said external column address. A semiconductor memory device as set forth in claim 6, wherein said inhibit-signal generating circuit comprises: a horizontal address decoder (DEC₁) operatively receiving a part (A₁-A i ) of said defective column address from said defective-column address memory, for providing k bits of decoded output; a vertical address decoder (DEC₂) operatively receiving another part (A i+1 -A n ) of said defective column address from said defective-column address memory, for providing m bits of decoded output; a first comparator (CMP₁) for comparing said another part (A i+1 -A n ) of said defective column address with a corresponding part (a i+1 -a n ) of said external column address; a second comparator (CMP₂) for comparing said part (A₁-A i ) of said defective column address with a corresponding part (a₁-a i ) of said external column address; a first AND gate (G₁₁) for passing said k -bits of decoded output from said horizontal address decoder through said first AND gate only when said first comparator generates a first coincidence signal (IAS k ), one of said k -bits passed through said first AND gate being said first inhibit signal (IS k ); a second AND gate (G₁₂) for passing said m -bits of decoded output from said vertical address decoder through said second AND gate only when said second comparator generates a second coincidence signal (IAS m ), one of said m -bits passed through said second AND gate being said second inhibit signal (IS m ); a first inverter gate (G₁₄) for inverting said first inhibit signal so as to provide said third inhibit signal (RAS k ); and a second inverter gate (G₁₆) for inverting said second inhibit signal so as to provide said fourth inhibit signal (RAS m ). A semiconductor memory device as set forth in claim 3, wherein said redundant-cell-parity generating circuit comprises: a third inhibit circuit (IC₄), operatively connected to said parity storing memory, for inhibiting data read from said parity storing memory from passing through said third inhibit circuit in response to a third inhibit signal (PIS m ), said third inhibit signal being generated when said previously determined horizontal parity has a hard error; a fourth inhibit circuit (IC₅), operatively connected to said parity storing memory, for inhibiting data read from said parity storing memory from passing through said fourth inhibit circuit in response to a fourth inhibit signal (PIS k ), said fourth inhibit signal being generated when said previously determined vertical parity has a hard defect; a first parity gate (G₂) having inputs operatively connected to the outputs of said horizontal parity generator and said third inhibit circuit, for generating a horizontal parity; a second parity gate (G₃) having inputs operatively connected to the outputs of said vertical parity generator and said fourth inhibit circuit, for generating a vertical parity; a fifth inhibit circuit (IC₂), operatively connected to said redundant memory cell, for inhibiting data read from said redundant memory cell from passing through said third inhibit circuit in response to a fifth inhibit signal (RAS ka ) of said inhibit signals, said fifth inhibit signal being generated in both conditions wherein said defective memory cell is not accessed and said previously determined vertical parity has a hard defect; a sixth inhibit circuit (IC₃), operatively connected to said redundant memory cell, for inhibiting data read from said redundant memory cell from passing through said sixth inhibit circuit in response to a sixth inhibit signal (RAS m ) of said inhibit signals, said sixth inhibit signal being generated in both conditions wherein said defective memory cell is not accessed and said previously determined horizontal parity has a hard defect; a horizontal parity gate (G₄), having inputs operatively connected to the output of said first parity gate and to the output of said fifth inhibit circuit, for effecting a horizontal parity processing; a vertical parity gate (G₅), having inputs operatively connected to the output of said second parity gate and to the output of said sixth inhibit circuit; and, for effecting a vertical parity processing; an AND gate (G₆) having inputs operatively connected to the outputs of said horizontal parity gate (G₄) and said vertical parity gate (G₅), for providing a coincidence signal when said outputs of said horizontal parity gate and said vertical parity gate coincide. A semiconductor memory device as set forth in claim 8, wherein said inhibit control circuit comprises: a defective-column address memory (ROM) having a storing area for storing the defective column address (A₁-A n ) of said defective memory cell and another storing area (RHP, VHP) for storing parity data expressing whether said previously determined vertical or horizontal parity has a hard defect or not; an inhibit-signal generating circuit (ISG), operatively receiving said defective column address (a₁-a n ) of said defective memory cell, said parity data (RHP, VHP), and an external column address signal for specifying a memory cell, for providing said inhibit signals when said defective column address coincides with said external column address and when said parity data expresses that said previously determined vertical or horizontal parity does not have a hard defect. A semiconductor memory device as set forth in claim 9, wherein said inhibit-signal generating circuit comprises: a horizontal address decoder (DEC₁) operatively receiving a part (A₁-A i ) of said defective column address from said defective-column address memory, for providing k -bits of decoded output; a vertical address decoder (DEC₂) operatively receiving another part of said defective column address from said defective-column address memory, for providing m -bits of decoded output; a first comparator (CMP₁) for comparing said another part (A i+1 -A n ) of said defective column address with a corresponding part (a i+1 -a n ) of said external column address; a second comparator (CMP₂) for comparing said part (A₁-A i ) of said defective column address with a corresponding part (a₁-a i ) of said external column address; a first AND gate (G₁₁) for passing said k -bits of decoded output from said horizontal address decoder through said first AND gate in both conditions wherein said first comparator generates a coincidence signal (IAS ka ) and said parity data expresses a hard defect in the previously determined parity (RHP, VHP), one of said k -bits passed through said first AND gate being said first inhibit signal (IS k ); a second AND gate (G₁₂) for passing said m -bits of decoded output from said vertical address decoder through said second AND gate in both conditions wherein said second comparator (COMP2) generates a coincidence signal and said parity data expresses a hard defect in the previously determined parity (RHP, VHP), one of said m -bits passed through said second AND gate being said second inhibit signal (IS m ); a first inverter gate (G₁₄) for inverting a logic OR of said fourth inhibit signal (PIS k ) and said first inhibit signal so as to provide said sixth inhibit signal (RAS k ); and a second inverter gate (G₁₆) for inverting a logic OR of said third inhibit signal (PIS m ) and said second inhibit signal so as to provide said fifth inhibit signal (RAS m ).

Inventors: TAKEMAE, YOSHIHIRO
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F11
IPC codes: G11C29, G06F11, G06F12, G11C11