IMPROVED FREQUENCY RESPONSE AMPLIFIER

Abstract: An operational amplifier or comparator is provided in which internal parasitic capacitances are buffered to increase the gain bandwidth product of the amplifier.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit according to the first part of claim 1. Such an amplifier circuit is known from Electronics Design, vol. 31, no. 12, 09.06.83, pp 153 to 158. 2. Description of the Prior Art The bandwidth of an amplifier can be defined as the difference between the maximum and minimum input frequencies at which a reasonably non-distorted output signal can be obtained. The gain of the amplifier is a measure of the amplification of the output signal relative to the input signal to the amplifier. The product of these two parameters defines a third parameter often referred to as the gain bandwith product. Because the gain bandwidth product (GBWP) is often a constant for a particular amplifier, increasing the gain of the amplifier typically causes a corresponding reduction in the bandwidth of the amplifier. Accordingly, it would be desirable to increase the GBWP of an amplifier in order to increase the gain or bandwidth without having an adverse effect on the other factor. The GBWP of a typical complementary metal oxide semiconductor field-effect transistor (CMOS) two-stage operational amplifier (Fig. 1) is usually limited by internal capacitances of various transistors within the operational amplifier circuit. These capacitive loads create "poles" in the transfer function of the amplifier, each of which causes an attenuation and phase shift in the output signal at a particular "pole frequency". Due to various design constraints, the pole frequencies of one or more of the transfer function poles is often sufficiently low to adversely affect the GBWP of the amplifier. SUMMARY OF THE INVENTION It is an object of the present invention to provide an operational amplifier having an improved gain bandwidth product (GBWP). It is a further object to improve the slew rate of operational amplifiers. These and other objects and advantages are achieved in an amplifier circuit, as claimed, in which internal parasitic capacitive loads are buffered. As a consequence, the pole frequencies associated with the parasitic capacitive loads are moved to significantly higher frequenices thereby improving the gain bandwidth product and slew rate over many previous operational amplifiers. In the illustrated embodiment, an emitter follower circuit buffers the output of an input transistor of a two-stage operational amplifier to the gates of a current mirror transistor pair. The increased gain of the emitter follower circuit has been found to shift the pole frequency associated with the parasitic capacitance of the transistors of the current mirror pair. In another aspect of the present invention, a second emitter follower circuit buffers the output of an input stage to the input of an amplification stage of the two-stage amplifier. This arrangement has also been found to shift the pole frequency of a parasitic capacitance of a transistor of the amplifier stage to a higher frequency with a corresponding favorable effect on the GBWP of the amplifier. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a prior art two-stage CMOS operational amplifier; Figure 2 is a schematic diagram of the amplifier of Figure 1 illustrating various internal parasitic capacitances of elements of the amplifier of Figure 1; Figure 3 is a schematic diagram of a CMOS two-stage operational amplifier in accordance with a preferred embodiment of the present invention; and Figure 4 is a schematic diagram of constant current sources for the amplifier of Figure 3. DETAILED DESCRIPTION OF THE DRAWINGS Figure 1 shows a prior art CMOS two-stage integrated circuit operational amplifier (or comparator) which is indicated generally at 10. The first stage of the amplifier 10 is a differential input gain stage 12 and is followed by the second stage which is a single-ended common source amplification stage 14. The differential input stage 12 has an inverting input 16 and a non-inverting input 18. The difference between first and second voltages applied to the amplifier inputs 16 and 18, respectively, is amplified at an output 20 of the differential input stage 12. The input stage 12 has a first input leg 22 which includes a p-channel input transistor P1 having a gate electrode coupled to the inverting input 16 of the input stage 12. The leg 22 further includes an n-channel load transistor N1 coupled to the output 30 of the input transistor P1. A second leg 24 similarly includes a p-channel input transistor P2 having a gate electrode coupled to the non-inverting input 18, and an n-channel load transistor N2 coupled to the output of the input transistor P2. A third p-channel transistor P3 provides a constant bias current to the two differential input legs 22 and 24 of the input stage 12. The input transistors P1 and P2 convert the voltage difference applied to their gate electrodes to an output drain current difference. As shown in Figure 1, the load transistors N1 and N2 are configured as current mirrors so that the transistors N1 and N2 convert the output drain current difference of the input transistors P1 and P2 to a voltage difference signal at output 20. Specifically, the gates of the load transistors N1 and N2 are coupled to a common node 26 which is coupled by an interconnection 28 to the output 30 of the load transistor N1. The voltage signal at output 20 is applied to the gate electrode of an n-channel input transistor N3 of the amplifier second stage 14. The input transistor N3 operates as a common source amplifier biased by a p-channel transistor P4. The coupled outputs of the second stage transistors P4 and N3 provide an output of the amplifier 10 as indicated at 40. Optionally, an npn bipolar transistor Q0 and a constant current source 42 can be added to the output 40 to buffer the output as indicated in phantom, providing a buffered output at 40'. Various circuit elements such as the transistors of the amplifier 10 have parasitic capacitances associated with them which create poles in the transfer function of the amplifier 10. Because these poles cause phase shifts as well as attenuation of the output, the parasitic capacitances can lead to unstable operation where a feedback loop is utilized. In order to increase the stability of the operation of the amplifier 10, a series-connected resistor 44 and compensation capacitor C c are coupled between the amplifier output 40 and the first stage output at 20. The capacitance of the capacitor C c is chosen sufficiently large so that the pole frequency of the pole created by the capacitor C c is lower than the pole frequencies of the parasitic capacitances. Consequently, the pole created by the compensation capacitor C c dominates the effect of the parasitic capacitances to increase the stability of the amplifier. This circuit design technique is often referred to as dominant pole compensation. Although the compensation capacitor C c inhibits the destabilizing effect of the parasitic capacitances, several of these parasitic capacitances nonetheless limit the gain bandwidth product (GBWP) of the amplifier. The amplifier 10 of Figure 1 typically has a GBWP of 1.5 to 2 megahertz. Figure 2 is an AC model of the amplifier 10 of Figure 1, in which various parasitic capacitances have been represented as capacitors drawn in phantom and coupled to AC ground. One such parasitic capacitance indicated at C1 is caused by the capacitance of the source regions of the input transistors P1 and P2 and the drain region of the biasing transistor P3, relative to the substrate of the amplifier. In Figure 2, the biasing transistors P3 and P4 are represented as constant current sources 34 and 38, respectively. The pole frequency of the pole created by the parasitic capacitance C1 is directly related to the transconductances of the first stage input transistors P1 and P2. Assuming the transconductances of the input transistors P1 and P2 to be substantially equal, the pole frequency F TP for the pole (often referred to as the "tail pole") of the capacitance C1 is set forth in equation (1) below: where gm(P1) represents the transconductance of the input transistor P1 (or P2). Because the transconductance of the input transistors P1 and P2 is relatively high, the pole frequency F TP of the tail pole is correspondingly high so that the tail pole does not significantly affect the gain bandwidth product (GPWP) of the amplifier. Another parasitic capacitance C2 is caused by the capacitance of the drain regions of the input leg transistors P1 and N1 relative to the substrate. The gates of the input stage load transistors N1 and N2 also have capacitances associated with them, and these gate capacitances are collectively represented by the capacitor C3 of Figure 2. The parasitic capacitances C2 and C3 create a pole referred to as a "mirror pole" which has a pole frequency F MP as set forth in equation (2) below: where the gate capacitances of the first stage load transistors N1 and N2 are approximately equal so that the capacitance of C3 is equal to twice the gate capacitance of either N1 or N2. As indicated above, the pole frequency F MP of the mirror pole associated with C2 and C3 is directly related to the transconductance of the load transistor N1. In the amplifier 10 of Figures 1 and 2, the transconductances of the load transistors N1 and N2 should be relatively small due to various design constraints including the minimization of noise and DC offset. As seen from equation (2) above, these constraints cause the mirror pole frequency F MP to be correspondingly low, thereby resulting in the mirror pole having a significant effect on the GBWP of the amplifier. The transfer function of the amplifier 10 also has a "split" pole resulting from the load capacitance on the second stage 14 in addition to the load capacitance on the first stage 12. The second stage load capacitance is caused by the drain diffusion region capacitance of the second stage transistors N3 and P4 as represented by the capacitor C4, and the capacitance of any load coupled to the output 40 of the amplifier 10. This load capacitance is represented by the capacitor CL in Figure 2. The load capacitance of the first stage 12 is provided by the capacitance of the drain diffusion regions of the transistors P2 and N2, which is represented by the capacitor C5, and the gate capacitance C6 of the second stage input transistor N3. The poles created by the first stage load capacitances C5 and C6 on the one hand and the second stage load capacitances C4 and CL on the other hand, are, absent the compensation capacitor C c , fairly close together due to the relatively large output impedances of the respective driving transistors, N2 and N3. However, the addition of the compensation capacitor C c moves the pole frequency of the first stage load capacitance to a much lower frequency due to the Miller effect of the gain of the second stage input transistor N3 on the compensation capacitor C c . On the other hand, the compensation capacitor C c acts like a short at high frequencies so that the gate of the second stage input transistor N3 is effectively shorted to its drain. Consequently, the output impedance of the input transistor N3 is lower at the higher frequencies so that the pole frequency of the second stage load capacitance is correspondingly moved to a higher frequency. In this manner, the poles of the first and second stage load capacitances are split. Although the split pole frequency F SP of the second stage load capacitances is moved to a higher frequency, it has been found that the second stage load capacitance pole still has a significant effect on the amplifier GBWP as shown below: where the transconductance of the second stage input transistor is represented by gm(N3). If the load capacitance CL is buffered by a buffer amplifer as represented by the transistor Q0 of Figure 1, the split pole frequency F SP is given by the following relationship: In accordance with the present invention, the gain bandwidth product (GBWP) of the amplifier shown in Figures 1 and 2 can be significantly improved by pushing both the split and the mirror poles to higher frequencies. Figure 3 illustrates an amplifier 100 which is a preferred embodiment of the present invention. Those elements in common with the amplifier 10 of Figures 1 and 2 have been designated with like numerals. Like the amplifier 10 of Figures 1 and 2, the amplifier 100 includes an input stage 12' having a first differential input leg 22' and a second differential input leg 24'. However, instead of the interconnection 28 coupling the output 30 of the load transistor N1 to the node 26 of the gates of the load transistors N1 and N2, the amplifier 100 has an npn bipolar transistor Q1 which drives the gates of the load transistors N1 and N2. As shown in Figure 3, the transistor Q1 is configured as an emitter follower stage or amplifier with the emitter of the transistor Q1 coupled to the node 26 at the gates of the transistors N1 and N2. A constant current source 102 also coupled to the node 26 biases the transistor Q1. It has been found that the provision of the transistor Q1 to drive the gates of the load transistors N1 and N2 typically increases the pole frequency of the mirror pole by a factor of 2 to 3. Although the transistor Q1 introduces a new pole, this new pole is at a very high frequency due to the higher gain or transconductance typical of bipolar transistors and is therefore not particularly significant. The pole frequency F Q1 of the new pole is set forth below: where gm(Q1), the transconductance of the transistor Q1, is typically 10 times the transconductance gm(N1) of the load transistor N1. Accordingly, the effect of the gate capacitance C3 is substantially reduced because the gate capacitances C3 are buffered by the transistor Q1 rather than driven by the load transistor N1. The pole frequency F MP of the mirror pole can now be approximated as: instead of equation (2) above. Thus, where the parasitic capacitance C3 is approximately 2 to 3 times larger than the parasitic capacitance C2, it is seen that the mirror pole frequency F MP is correspondingly 2 to 3 times higher as a result of the addition of the transistor Q1. The pole frequency F SP of the split pole may also be pushed to substantially higher frequencies. In accordance with the present invention, a second npn bipolar transistor Q2 has been added which buffers the output 20 of the load transistor N2 to the gate of the second stage 14' input transistor N3. Like the transistor Q1 of the differential input stage 12', the transistor Q2 is configured as an emitter follower with the emitter of the transistor Q2 coupled to the gate of the input transistor N3 and a constant current source 104. The bipolar transistor Q2 drives the parasitic capacitance C6 arising from the gate capacitance of the transistor N3, thereby reducing the effective capacitance of that node. Specifically, the pole frequency F Q2 for the gate capacitance of the input transistor N4 is set forth below: where the transconductance gm(Q2) of the transistor Q2 is typically 10 times greater than the transconductance gm(N3) of the second stage input transistor N3. Consequently, the effect of the gate capacitance C6 on the split pole frequency is substantially reduced so that the split pole frequency F SP can be represented as follows: instead of by equation of (4) above. As seen above, the split pole frequency F SP is significantly increased. Furthermore, the transistor Q2 voltage-shifts the output of the differential input stage 12' to drive the second stage input transistor N3. The above described amplifier 100 achieves a wider bandwidth and therefore a larger gain bandwidth product by buffering internal capacitive loads with emitter follower stages. In particular, the current mirror and split poles are moved to two or three times higher frequencies in the illustrated embodiment, improving the gain bandwidth product and slew rate by a factor of two over many prior art two-stage CMOS amplifier/comparators. The transistors Q1 and Q2 added to the circuit of Figure 1 operate at the same current density to maintain balanced operation on the input stage 12'. Furthermore, the addition of the emitter follower amplifiers Q1 and Q2 does not significantly degrade the noise performance or the DC accuracy of the amplifier. It is noted that the negative common mode range is somewhat reduced however. As previously mentioned, the bipolar transistors Q1 and Q2 are configured as emitter follower stages and are biased by the constant current sources 102 and 104 respectively. Figure 4 illustrates a circuit for implementing the constant current sources of 102 and 104 of Figure 3. As shown therein, the gate of a p-channel transistor P5 similar to the constant current source transistors P3 and P4 of Figure 3, is coupled to the biasing voltage V B with the source of transistor P5 coupled to the biasing voltage V+. The drain of the transistor P5 is coupled to a diode-connected n-channel transistor N5, the source of which is coupled to the biasing voltage V-. The gate of the transistor N5 is coupled to the gates of two additional n-channel transistors N6 and N7. The drains of the n-channel transistors N6 and N7 are coupled to the emitters of the transistors Q1 and Q2, respectively, with the sources of the transistors N6 and N7 coupled to the negative biasing voltage V-. In operation, the voltage induced on the gate of the n-channel transistor N5 by the p-channel transistor P5 is applied to the gates of the constant current source transistors N6 and N7 producing a constant current through each bipolar transistor. These currents provide the biasing currents for the transistors Q1 and Q2 as previously described. In the illustrated embodiment, the entire amplifier circuit 100 is fabricated as a monolithic integrated circuit. An amplifier in accordance with the illustrated embodiment is well suited for fabrication with a "P-well" process where vertical substrate npn bipolar transistors are readily available. It should be noted that an "N-well" process may also be used by substituting pnp transistors for the npn transistors shown and changing all other transistor types in the circuit. It will, of course, be understood that other modifications of the present invention, in its various aspects, will be apparent to those skilled in the art, some being apparent only after study and others being merely matters of routine electronic design. For example, MOS transistors can be used as source followers in place of the bipolar emitter follower transistors shown. Furthermore, it is recognized that the present invention should not be restricted to common source type amplifiers but can also be applied to amplifiers cascoded to increase gain, for example.

Claims: An amplifier circuit which includes a MOS transistor having a gate and further includes a differential amplifier comprising field-effect transistors having an internal output providing a signal to the MOS transistor gate, the transistor gate having a parasitic capacitance associated therewith and the MOS transistor being configured within the amplifier circuit such that the gate capacitance creates a pole in the transfer function of the amplifier circuit, characterized by bipolar transistor means (Q1, Q2, 102, 104) for coupling the differential amplifier internal output to the MOS transistor gate to buffer the signal to the MOS transistor gate so that the pole frequency of the pole associated with the transistor gate capacitance is increased. The circuit according to claim 1 characterized in that the bipolar transistor means comprises an emitter follower stage having a bipolar transistor (Q1, Q2) and a constant current source (102, 104) coupled to the emitter of the transistor for biasing the bipolar transistor. The circuit according to claims 1 or 2 characterized in that the differential amplifier has an input stage (12') and an amplification stage (14), the input stage comprising first and second legs (22', 24'), the first leg comprising a first MOS input transistor (P1) and a first MOS load transistor (N1) coupled to the output of the first MOS input transistor, the second leg comprising a second MOS input transistor (P2) and a second MOS load transistor (N2) coupled to the output of the second MOS input transistor, the first and second load transistors having gates; a first bipolar transistor (Q1) having a base coupled to the output of the first input transistor and an emitter coupled to the gates of the first and second load transistors; a first constant current source (102) coupled to the emitter of the first bipolar transistor for biasing the first bipolar transistor; the second stage (14) including a third MOS input transistor (N3) having an output and a gate; a second bipolar transistor (Q2) having a base coupled to the output of the second MOS input transistor and an emitter coupled to the gate of the third MOS input transistor; and a second constant current source (104) coupled to the emitter of the second bipolar transistor for biasing the second bipolar transistor. The circuit according to any one of claims 1 to 3 characterized in that the circuit is fabricated as an integrated circuit.

Inventors: DOLUCA, TUNC
Applicants: INTERSIL INC.
Application year: 1985
Main classification: H03F1
IPC codes: H03F3, H03F1