VERSATILE GENERIC CHIP SUBSTRATE

Abstract: A variety of semiconductor devices and technologies can be integrated conveniently using a generic modular substrate (16). The substrate contains modules (10) that can be isolated from each other and from the substrate. This design approach is especially useful for combining high and low voltage functions in the same chip and for integrating analog and digital devices. It is well adapted for CMOS implementations.

Description: VERSATILE GENERIC CHIP SUBSTRATE Background of the Invention There are growing applications for circuits that integrate families of devices, e.g. MOS-bipolar, or diverse functions, e.g. digital-analog, high voltage-low voltage, in the same chip. Statement of the Invention We have invented a versatile generic chip substrate that can accommodate a wide variety of device families in a convenient integrated standard array. The substrate contains an intra-isolated array of device sites each of which may contain one or more devices of the variety of device families. In a preferred embodiment the generic chip substrate is used to form pairs of high voltage and low voltage CMOS devices. Brief Description of the Drawings FIGS. 1A-1C are schematic representations of the generic chip substrate (GCS) which comprises the broad aspect of the invention; FIGS. 2A-2K ("I" omitted) are schematic representations of an exemplary group of devices that can be formed in a selected site of the GCS; FIG. 3 is a schematic view of a preferred embodiment of the invention showing low voltage and high voltage complementary transistors in a GCS implementation; FIG. 4 is a schematic representation of a CMOS device integrating digital and analog functions. Detailed Description The standard generic chip substrate (GCS) is shown in FIG. 1A and comprises a semiconductor n-substrate 16 with an array of device sites 10 formed as shown. Regions 11 isolate the sites from one another. Each site comprises a sequence of p-n-p tubs 12, 13, 14 formed within a p-well 15. Dimensions of the tubs and doping levels of the various regions are a function of the actual semiconductor devices to be integrated. A slight variation of the monolithic array illustrated in FIG. 1A would have varying dimensions and doping from site to site with selected sites optimized for a given device family. However the basic ingredients would be common to each site, i.e. n and p tubs in a p-well. (Complementary structures can be used as well. ) The sites may be completely isolated from the nearest neighbor as shown schematically in FIG. 1B (plan view) or they can be isolated in groups or rows as indicated in FIG. 1C. Exemplary of the wide variety of device families that can be accommodated by the GCS are those shown in FIGS. 2A-2K (Legend "21" has been omitted). Other possibilities are possible. The devices in each site have the capability of being totally isolated from other devices in the array. This feature is especially useful when integrating analog and digital devices or high voltage and low voltage devices on the same chip. This layout scheme is shown in plan view in FIG. 1B. Applications will be found in which a series of, for example, low voltage CMOS pairs are advantageously laid out in a row or rows where it is unnecessary to isolate each channel from the others but it is still desirable to isolate the row from other devices, i.e. to isolate the row from the remainder of the chip substrate. In that case the isolating p-well can be formed as a continuous elongated well as shown in FIG. 1C. The basic structure of FIG. 1A is common to either layout. Referring to FIG. 1A there is shown in dashed lines an n-tub in the separation between the p-wells. While the n-tub in itself provides a degree of isolation, it is often desirable to add the more heavily doped (n + ) region 11 to insure against surface inversion and inter- device leakage. Alternatively, the n + region can be used alone and the inter modular spacing optimized for the type and degree of isolation desired. A high voltage-low voltage CMOS device is shown in FIG. 3. The high voltage device comprises source-substrate connected structures which are built within p-wells, (11 and 11 ') across n-tub - p-tub boundaries, utilizing polysilicon as the gate electrodes (12 and 12 1 )- The device -structures are as follows: 1) High voltage p-channel: the n-tub region 16 under the polysilicon gate 12 and 2000A gate oxide 13 serves as the inversion region (channel), and the p-tub region 14 under the polysilicon gate 12 and field oxide 15 serves as the drift region. The source and drain are shown at 17 and 18 respectively. 2) n-channel: the p-tub region 16 1 under the polysilicon gate 12' and 2000A gate oxide 13' serves as the inversion region (channel) , and the n-tub region 14' under the polysilicon gate 12' and field oxide 15' serves as the drift region. The source and drain are shown at 17' and 18 * respectively. The portion of the polysilicon gate which runs over the drift region serves as a field plate and insures that the drift region does not become inverted due to stray electric fields. The n + and p + guard rings 19 and 20 serve as channel stops, i.e. serve to raise the field inversion threshold. Metal contacts are shown at 20. (The gate contacts do not appear in this view.) 3) Low voltage p-channel: the n-tub region 30 under the polysilicon gate 31 provides the channel between source 32 and drain 33. 4) Low voltage n-channel: the p-tub region SO- under the polysilicon gate 31' provides the channel between source 32' and drain 33'. Metal contacts (gate contacts not shown) are denoted 34. We have fabricated both n- and p-channel HV-CMOS devices with drain to source breakdown voltages greater than 100 volts. Device characteristics are presented in the following Table. Devices had these dimensions: width = 200 -_m, length = 15 μm, drift region 10 μm. Additional details on device structure and fabrication • appear in IEEE Journal of Solid-State Circuits, E. Habekotte, B. Hoefflinger, W. Renker, and G. Zimmer, Vol. SC-16, No. 3, June, 1981. R O-.,N.- in the Table is on-resistance measured with GS ** - 'l0v an* 3 V ns~ 1V * C GD in the Table is the gate/drain overlap capacitance. HV CMOS Device Characteristics IL. (HV-PCH) 10.1k _ -14 C„ Λ 7.67 x 10 '*F —16 C„--/Width 3.84 x 10 F/μirt of width The addition of a p-well to the CMOS process affords a variety of additional design capabilities. For example: 1 ) Low voltage p-channel devices can be fabricated in n-tubs contained within a p-well (FIG. 2B) , thus providing individually isolated p-channel devices. 2 ) Low voltage digital circuits can be fabricated in one large p-well (FIG. 4), thus providing a vehicle for isolating analog and digital portions of a circuit. 3) Complementary bipolar transistors (npn and pnp) can be fabricated within the p-well (FIG. 2H) . These devices are also individually isolated from each other and the substrate. 4) If one utilizes the substrate, a controlled pnpn SCR is also available (FIG. 2H) .

Claims: Claim An integrated semiconductor structure comprising a semiconductor substrate (16) of a first conductivity type having a plurality of repeating cell units, CHARACTERIZED IN THAT each unit comprises a relatively deep well (15) having a second conductivity type opposite to that of the substrate, each said well contains at least three contiguous tubs (12, 13, 14) of alternating conductivity type, isolating means (11) between at least selected wells for electrically isolating those wells from each other, and at least one p-n junction device (e.g., FIG. 3) formed in at least one of said tubs.

Inventors: MEYER WILLIAM GEORGE, OLSON KAREL HUGH, MEYER, WILLIAM, GEORGE, OLSON, KAREL, HUGH
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1985
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L29