A SEMICONDUCTOR DEVICE HAVING A RELIABLE BONDING PAD STRUCTURE

Abstract: A semiconductor device includes a semiconductor subs­ trate in which one or more circuit elements are formed, a first insulating layer (13) covering the semiconductor substrate and having holes exposing the one or more circuit elements, a first metal layer (14) selectively deposited on the first insulating layer and contacting with the circuit element through the holes to form wirings, a second insulating layer (15) covering the first insulating layer and the first metal layer except for a limited portion of the first metal layer, and a second metal layer (16) formed on the limited portion of the first metal layer and extended to the second insulating layer on the first insulating layer, a conductive wire (17) being bonded on the extended portion of the second insulating layer.

Description: A SEMICONDUCTOR DEVICE HAVING A RELIABLE BONDING PAD STRUCTURE The present invention relates to a semiconductor device having a reliable bonding pad structure, and more particularly to an integrated circuit having a bonding pad which protects the insulating layer thereunder from cracking in a wire bonding process. A semiconductor device in the prior art is formed in a semiconductor substrate. One or more electrical elements are constructed in the semiconductor substrate by selectively diffusing impurities. A wiring layer is applied on an insulating layer and connected to the circuit element through holes in the insulating layer. The wiring layer is covered by another insulating layer except for bonding pad regions. A bonding pad metal is deposited to cover the exposed bonding pad region of the wiring layer. The bonding wire is bonded onto the bonding pad metal. The other insulating layer is a paseivation layer in a case where the semiconductor device is a discrete circuit element or an integrated circuit having a small integration density, and is an intermediate layer in a case of an integrated device in which the bonding pad metal is used as an uppermost wiring layer. In any case, the other insulating layer is interposed in the peripheral portion of the bonding pad region between the lower wiring layer and the bonding pad metal. Therefore, the bonding stress is applied to the interposed insulating layer to cause cracking in the interposed insulating layer, when the bonding wire is bonded onto the bonding pad metal. The generation of cracking is enhanced by uneven surface of the bonding pad region. The unevenness is caused by the interposition of the other insulating layer at the periphery of the bonding pad region. The e cracking allows moisture to permeate into the wiring metal and corrode the wiring metal. Due to this corrosion, the resistance of the wiring metal becomes high and, in the worst case, the wiring become open to destroy the electrical function of the semiconductor device. The primary object of the present invention is to provide a semiconductor device having a bonding pad structure which does not damage the electrical function of the semiconductor device in a wire bonding process. The other object of the present invention is to provide a bonding pad structure by which the insulating layer at the periphery thereof is prevented from cracking in a wire bonding process. According to the present invention, there is provided a semiconductor device comprising a semiconductor substrate in which one or more electrical elements are formed, a first insulating layer covering the semiconductor substrate and having first holes for wiring, a first metal layer running on the first insulating layer and connected to the one or more electrical elements to form a wiring, a second insulating layer covering the exposed first insulating layer and the first metal layer except for a limited area of the first metal layer, and a second metal layer covering the limited area of the first metal layer and extended to the surface of the second insulating layer to. form a bonding pad on the second insulating layer. In accordance with the present invention, the bonding pad is formed on the second insulating layer. All the layers under the bonding pad can be made flat. When the bonding stress is applied to the bonding pad, this flatness uniformly distributes the bonding stress over the second insulating layer under the bonding pad. Therefore, the generation of the cracking in the second insulating layer is prevented. If the bonding pad covers an edge of the limlted area of the first metal, a step is formed in the second insulating layer and the cracking is easily generated in the second insulating layer at this step area. However, the step area is widely covered with the second metal. Therefore, if the crack is generated in the second insulating layer, the crack is covered with the second metal to.prevent the penetration of moisture, resulting in a perfect prevention of the electrical function of the semiconductor device. The invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a sectional view of the semiconductor device in the prior art; Fig. 2 is a sectional view of the semiconductor device according to a first embodiment of the present invention; and Fig. 3 is a sectional view of the semiconductor device according to a second embodiment of the present invention. The semiconductor device in the prior art shown in Fig. 1 uses a semiconductor substrate 1 of silicon having one conductivity type. One or more circuit elements are formed in the semiconductor substrate 1 by one or more times of impurity diffusion. One example is a diffusion region 2 which is a base region of a bipolar transistor or a resistor. The diffusion region 2 may be a channel stopper region in a MOS integrated circuit. The surface of the substrate 1 (the surface of the diffusion region 2 in Fig. 1) is covered with a first insulating layer 3 which has some holes (not shown in Fig. 1) to expose parts of circuit element to connect with wiring metal 4. The wiring metal 4 is selectively formed on the first insulating layer 3 and is contacted with the exposed part of circuit element to form a wiring. A second insulating layer 5 is further covered over the first insulating layer and the wiring metal 4 except for a limited portion. At the periphery of the limited portion of the wiring metal 4, the second insulating layer 5 covers the wiring metal 4. A bonding pad metal 6 is deposited on the limited portion of the wiring metal 4 so as to extend on the second insulating layer 5 at the periphery of the limited portion of the wiring metal 4. On the bonding pad metal 6, a gold fine wire 7 is bonded to connect with external lead of the package of the semiconductor device. The bonding pad metal 6 may be used as upper most wiring layer in an integrated circuit having a high integration density. At the periphery of the bonding pad metal 6, the second insulating layer 6 is interposed between the bonding pad metal 6 and the wiring metal 4 and the edge of the second insulating layer 6 exists under the bonding pad metal 6 to form a step. When the gold fine wire 7 is bonded onto the bonding pad metal 6, the bonding stress concentrates at the edge portion of the second insulating layer 5 to generate cracks in the second insulating layer 5. Those cracks allow moisture to permeate to reach the wiring metal 4. The moisture oxidizes the wiring metal 4 to make wiring resistance high. In the worst case, the moisture corrodes the wiring metal 4 to make the wiring open. DETAILED DESCRIPTION OF THE INVENTION In accordance with the first embodiment of the present invention shown in Fig. 2, one or more circuit elements are formed in a semiconductor substrate 11 by forming a diffusion region 12 by one or more times of impurity diffusion process, as similarly to the prior art shown in Fig. 1.. A first insulating layer 13 is formed on the semiconductor substrate 11 (in the case of Fig. 2, the first insulating layer 13 covers the diffusion region 12). A wiring metal 14 of Ass is selectively deposited on the first insulating layer 13. The wiring metal 14 is connected with the circuit element through holes in the first insulating layer 13 to form wirings. At a portion of bonding pad, the wiring metal 14 is formed as a ring-shape surrounding the bonding pad portion. A second insulating layer 15 is formed on the first insulating layer 13 and the wiring metal 14 except for center portion of the ring-shape. The second insulating layer 15 is flat at the bonding pad portion surrounded by the ring-shape wiring metal 14. A bonding pad metal 16 of AQ is deposited on the ringshape wiring metal 14 and the bonding pad portion of the second insulating layer 15. A gold fine wire 17 is bonded onto the bonding pad metal 16 upon the second insulating layer 15 surrounded by the ring-shape wiring metal 14. The other end of the gold fine wire 17 is connected with an external lead of package or directly with other electrical circuit element. The bonding pad metal 16 may be used as an uppermost wiring metal in a case of integrated circuit in which a multi-layer wiring is employed. All the layers, such as the bonding pad metal 16 and the second and first insulating layers 15 and 13, are made flat at a portion where the gold fine wire 17 is bonded. The bonding stress#is uniformly applied to anywhere in the second insulating layer 15 under the gold fine wire 17. It is hard to generate crack in the second insulating layer 15. Furthermore, even if a crack is generated in the second insulating layer 15, the cracking portion is covered with the bonding pad metal 16 and is not extended outside the bonding pad metal 16 by the separation of the second insulating layer 16 on the ring-shape portion of the wiring metal 14. Therefore, the wiring metal 14 is kept separation from moisture to prevent from being oxidized or corroded. The electrical characteristics of the semiconductor device is not affected by the bonding process. A second embodiment of the present invention shown in Fig. 3 has fundamentally similar structure to Fig. 2. The bonding pad metal 16' contacts with the wiring metal 15' at one portion only. The exposed portion of the wiring metal 15' from the second insulating layer 14 does not surroundbutb separated from the bonding portion of the bonding pad metal 16'. By this embodiment, the flatness under the bonding portion where the gold fine wire 17 is bonded is kept. The cracking of the second insulating layer is sufficiently prevented. The cracking of the second insulating layer 14 at the edge of the wiring metal 15' may be extended, but since the bonding pad metal 16' widely covers the second insulating layer 14, the cracking does not extend outside the bonding pad metal 16'. The cracking does not extend beyond its separation on the wiring metal 15'. Therefore, the wiring metal 15' is sufficiently prevented from contacting moisture. The electrical characteristics of the semiconductor device is kept unchanged. The present invention is equally applied to a discrete semiconductor device or an integrated circuit having a single wiring layer by using the second insulating layer 14 as a passivation layer and to an integrated circuit having a multi-layer wirings by using the bonding pad metal 15, 15' and the second insulating layer 14 as an uppermost wiring layer and an interposed insulating layer, respectively.

Claims: What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate in which at least one electrical circuit element is formed; a first insulating layer covering said semiconductor substrate and having holes exposing portions of said electrical circuit element; a first metal layer selectively formed on said first insulating layer and contacted with said electrical circuit element through said holes to form wirings; a second insulating layer covering said first insulating layer and said first metal layer except for a limited portion of said first metal layer; and a second metal layer formed on said limited portion of said first meal and extended on a part of said second insulating layer which is on said first insulating layer, a conductive wire being bonded on said extended portion of said second metal layer on said part of said second insulating layer. 2. A semiconductor device as claimed in claim 1, wherein said part of said second insulating layer is made flat, said conductive wire being bonded on a portion of said second metal layer which covers said part of said second insulating layer. 3. A semiconductor device as claimed in claim 1, wherein said first metal layer has a ring-shape portion, said conductive wire being bonded on said second metal layer on said part of said second insulating layer which is sorrounded by said ring-shape portion. 4. A. semiconductor device as claimed in claim 3, wherein said second metal layer contacts with said first metal layer at the center portion of said ring-shape portion so that said second insulating layer inside said ring-shape portion is separated from said second insulating layer outside said ring-shape portion. 5. A semiconductor device as claimed in claim 1, wherein said second metal layer includes a contact portion contacting with said first metal layer and a bonding portion where said conductive wire is bonded, said bonding portion being continuous to said contact portion at one side and free at another side.

Inventors: TOMITA, YUKIO
Applicants: NEC CORPORATION
Application year: 1985
Main classification: H01L23
IPC codes: H01L23, H01L21