A MULTIPROCESSOR SYSTEM

Abstract: A multiprocessor system of a vector processor type including two or more scalar units (SU0, SU1) and one vector unit (VU). Priority for use of the vector unit by the scalar units is switched from one scalar unit (SU0) to another scalar unit (SU1) by detecting an interruption in the instructions under execution in the vector unit. The discontinuance detection may be performed by adding an instruction at the end of a packet of instructions being executed or to be executed in the vector unit, or performed by detecting the absence of instructions in a buffer (1063) which stores instructions to be executed. The quantitative throughput characteristic and operating ratio of the vector unit of the multiprocessor system is improved in comparison with known multi­ processor systems.

Description: A Multiprocessor System The present invention relates to a multiprocessor systempln the form of a large-scale general purpose data processing system or an ultra-high-speed data processing system, in particular, to a configuration allowing an increase in the processing power of a given hardware resource. In scientific data processing systems, the following techniques are used for obtaining a high-speed processing capability. a) Providing the unit responsible for processing instructions relevant to scientific computations with a relatively large data processing power; or b) Forming a system with a multiprocessor configuration. The processing speed achieved by the former technique varies depending on the proportion of instructions relevant to scientific computations (referred to as scientific instructions, hereinafter) in the totality of instructions processed in a system. Exemplary qualitative comparisons are given in FIGs.8A and 8B, wherein system (2) has a processing power twice that of system (1) in terms of the processing of scientific instructions. FlG.8A illustrates a case wherein the proportion of the scientific instructions, vector instructions, for example, is dominant over other instructions, scalar instructions, for example, and the whole processing time of the system (2} is reduced to about one half of the system (1). On the other hand, in acase where the proportion of the scalar instructions is dominant, a significant reduction in the whole processing time is not obtained, as shown in FIG.8B. Thus, to siir##y increase the processing power for scientific instructions does not always improve the total through-put but may even worsen the optimum balance of a data processing system. Accordingly, a multiprocessor configuration is generally devised to attain a further increase in the processing speed when an optimization of the system balance has been achieved in a single processor configuration. However, even in a two-processor multi-system, the total through-put can be increased twice at - best. Moreover, the through-put of a multiprocessor system becomes the same as that of a single processor system when only a single program runs on the system. The abovementioned problems of known multiprocessor systems will be discussed further by considering an example of a vector processing system as follows. A vector processor comprises a vector instruction processing unit (simply referred to as vector unit !W) hereinafter) for processing instructions relevant to scientific computations (vector instructions), a scalar instruction processing unit (simply referred to as scalar unit (SU) hereinafter) for processing other instructions (scalar instructions), and respective one common main storage unit MSU and main storage control unit MCU. A vector processor of a single processor configuration is shown by the block diagram of FIG.2. The configuration of FIG.2 is referred to as VPl, hereinafter. A vector processor comprising a vector unit W having a processing power twice that of the vector unit in FIG.2 is shown by the block diagram of FIG.3. The configuration of FIG.3 is referred to as VP2, hereinafter. The hardware resource of VU {amount of vector processing hardere) in VP2 is twice that in the configuration VP1 of /FIG.2. Further, a multiprocessor configuration comprising two vector processing units VPU0 and VPUl each including a scalar unit (SU) and a vector unit (VU) which are the same as those in VPl is shown by the block diagram of FIG.4. The multiprocessor configuration of FIG.4 is referred to as VPl-M, hereinafter. Program executions in the above processing systems are now compared with reference to FIGs.5A--5C;- which schematically illustrate the time periods during which vector and scalar instructions are executed in the respective SUs and VUs of the processing systems shown in FIGs.2, 3 and 4. FIGs.5A, 5B and 5C respectively correspond to VPl, VP2 and VPl-M, wherein each white bar indicates an execution time during which scalar instructions are processed and each shaded bar indicates an execution time during which vector instructions are processed. Comparing FIG. 5B with sA, the execution time of vector unit W in VP2 is one half of that of the W in VP1, while the execution time of the scalar unit SU in VP2 remains unchanged with respect to that in VPl. In VPl-M as shown in FIG.4, vector processor units VPUO and VPUl execute different respective programs, and the respective execution times of vector units WO and W1 and scalar units SU0 and SUl are the same as those in VPl, as shown in FIG. SC, hence the total throughput of jobs of VPl-M is twice that of VPl. FIG.6 is a block diagram for illustrating an exemplary configuration of a vector unit (VtJ) in a vector processor. In FIG.6, each ofm main storage unit (MSU1 600, main storage control unit (MCU) 610, scalar unit (SU) 620 and vector unit (VU) 630 is equivalent to the corresponding unit in FIG.2 Vector instruction control unit (VCU) 640 controls the fetch of instructions from SU 620 and also controls instruction execution in a vector instruction executing unit (VEU) 650 by control signals sent via a bus line 641. The vector instruction executing unit (register) PVEU 650 comprises a vector resistor/(VR) 670 for holding vector data, a load pipeline 660 for transmitting data from MSU 600 to VR 670, and a store pipeline 661 for transmitting data from VR 670 to MSU 600. VEU further comprises various pipelines including an add pipeline 680, a multiply pipeline 681 and a divide pipeline 682, all for executing instructions including those relevant to computations on the vector data read from the vector register VR 670 and others relevant to the write-in of the results in VR 670. In the vector processor unit (VPU) , the scalar unit (SU) 620 performs the fetch of instructions from MSU 600. Of the fetched instructions, scalar instructions are executed in SU 620, while vector instructions are sent to VCU 640 in W 630. FIG.7 is a block diagram for illustrating an exemplary configuration of the vector instruction control unit (VCU) 640 of FIG.6, which receives vector instructions from a scalar unit. Referring to FIG.7, each one of consecutive vector instructions fetched by an associated scalar unit (SU) 700 is input to a vector instruction fetch stage register (VFSR) 711 in VCU 640 via a line 701. When a vector instruction pre-decoding stage register {VPSR) 715, which is provided for storing instructions to be decoded by the decoder 718 and subjected to check by an exception check 719, is empty, the instruction stored in VFSR 711 is sent to VPSR 715. If VPSR 715 is occupied by a preceding instruction, or, if there is at least one preceding instruction in the vector instruction fetch buffer (VFB) 712, the vector instruction in the register VFSR 711 is stored in VFB 712. Each of the instructions stored in VFB 712 is input to VPSR 715 via a selector (SEL) 714 at a to timing subsequent/when the preceding instruction passes through VSPR 715. The above operation is controlled by a fetch control 713. That is, if there is no space in VFB 712, the fetch control 713 sends a W Full signal 702 to SU 700 to stop the transmission of the vector instructions, and also instructs SEL 714 to select an instruction stored either in VFSR 711 or VFB 712, according to information on the state of occupation of VPSR 715 and VFB 712. The vector instruction supervisor 717 stores the instructions sent from a vector instruction queuing stage register (VQSR) 716 and controls transmission of the stored instructions to the vector instruction executing unit (VEU) 650 shown in FIG.6 via a bus line 641, according to information sent from a decoder (DEC) 718 and VQSR 716. The vector instruction supervisor 717 is also responsible for supervising the operation of VEU 650. The vector unit (VU) in each of the aforesaid processors VP1, VP2 and VP1-M comprises a vector instruction control unit (VCU) as shown in FIG.7. In VP2, the vector instruction executing unit (VEU) controlled by VCU has twice the hardware (twice the power) compared with the others and can process two units of data in each cycle. As described above, VP1-M includes two pairs of a scalar unit (SU) and a vector unit (W) as shown in FIG.4, one pair including SU0 and WC and the other pair SU1 and Vul, and has a throughput twice that of VP1. Although increased compared with VP1 as shown in FIG.5B, the total throughput of VP2 is always lower than that of VP1-M in a multiprogramming environment wherein the vectorization ratio (the ratio of vector instructions to all instructions including scalar instructions in a program) is less than 100%. A quantitative comparison of throughput characteristics of VP1, VP2 and VP1-M together with the multiprocessor system of the present invention will be discussed in detail later. According to the present invention, there is provided a multiprocessor system including first and second type processing units operable for processing independently different kinds of instructions, comprising: a plurality of said first type processing units; and one said second type processing unit having a plurality of respective interfaces with said first type processing units, wherein said second type processing unit is operable to switch to select one of said interfaces receiving instructions sent from its respective said first type processing unit, and to process the received instructions therein. An embodiment of the present invention may provide a multiprocessor system having increased processing efficiency of a vector unit in a multiprocessing environment without a substantial increase in hardware resources. The present invention incorporates the insight that the operating ratios of the vector units WO and VU1 in a VP1-M configuration system remain at a low level, in general. Therefore, in a multiprocessor system, a plurality of a first type of processor, scalar units, for example, are coupled with a second type of processor, a vector unit, for example, via corresponding interfaces provided in the second type of processor, and the second type processor operatively selects one of the first type processors by switching the connections to the interfaces, according to a discontinuance (interruption) detected in the instructions fetched by a selected one of the first type processors. Thus, the second type processor can alternatingly process instructions sent from the plurality of first type processors so as to maximize its operating ratio. The selection control of the first type processors may be carried out by attaching an additional end-indicating instruction to each packet of queued instructions to be processed by the second type processor, or by detecting a blank in the packet of queued instructions sent from the selected first type processor to the second type processor. The right (priority) to use the second processor is automatically switched from a present selected first type processor to another first type processor, according to the detection of the end-indicating instruction or blank. Thus, contention (competition) among operations of the plural first type processors is eliminated and a reduction in the processing speed due to an overhead for contention control can be eliminated. Therefore, an embodiment of the present invention may provide a multiprocessor system having a capability of speedy switching of its constituent processors. Reference is made, by way of example, to the accompanying drawings in which: FIG,1 is a block diagram illustrating a simplified configuration of a vector processor embodying the present invention; FIGs.2 and 3 are block diagrams of known vector processors of different single-processor configurations VP1,VP2; FIG.4 is a block diagram of a known vector processor of a multiprocessor configuration VP I-M; FIGs.5A, SB and 5C are schematic illustrations for comparing time periods for executing instructions by respective scalar and vector units of the processing systernsshown in FIGs 2, 3 and 4; FIG.6 is a block diagram of an exemplary configuration of a vector unit VU in a vector processor; ; FIG.7 is a block diagram of an exemplary configuration of a vector instruction control unit (VCU) 640 in FIG.6; FIGs 8A and 83 are schematic comparisons showing the relationshipbetween the proportion of vector instructions and the effect of increase in the vector instruction processing power; FIG.9 is a block diagram showing the essential configuration of a vector unit (W) in an embodiment of the present invention; ; FIG.10 is a block diagram showing an exemplary circuit configuration of a VCU according toan embodiment of the present invention FIGs.llA and 113 are schematic comparisonsof program execution by the vector processor VP-M shown in FIG.1 with that by the multiprocessor VP1-M shown in FIG.4; FIG.12 is a schematic illustration of the execution time of a program including scalar instruction packets and vector instruction packets in a VP1 configuration; FTGs.13 and 14 illustrate execution time of concurrent processing of programs each being as shown in FIG. 12 in a VP-M configuration; ; FIGs.15 and 16 are graphs showing throughput characteristics of VP2, VP1-M and VP-M configurations relative to VP1 as functions of a variable h; FIG. 17 is a block diagram showing an exemplary circuit configuration in accordance with a second embodiment of the present invention, allowing contention control independent from a control program; FIG.18 is a chart illustrating an execution sequence of instructions according to the second embodiment of the present invention; FIG. 19 is a block diagram showing another exemplary circuit configuration in accordance with a third embodiment of the present invention; and FIG.20 is a chart illustrating an execution sequence of instructions according to the third embodiment of the present invention. FIG.1 is a block diagram illustrating a simplified configuration of a vector processor embodying the present invention In FIG.1, symbols MSU, MCU, SUO and SU1 designate corresponding parts to those in FIG.4. The essential configuration of the vector unit (W) of FIG.1 is shown in the block diagram of FIG.9. In FIG.9, each of a main storage unit (MSU) 900, main storage control unit (MCU) 910, and scalar units (SUS) the 920 and (SU1) 921 is equivalent to SU 600, MCU 610 and SU 620 in FIG.6. A vector instruction executing unit (VEU) 950 in vector unit (vu) 930 is substantially equivalent to VEU 650 in FIG.6, and, therefore, the parts designated by references 960-982 correspond to the respective equivalents 660-682 in FIG.6. A second vector instruction executing unit (VEU) 951 is the same as VEU 950; accordingly, twice the VEU hardware is incorporated in W 930 compared with VEU 650 in FIG.6. This means that the number of VEUs 950 and 951 in this embodiment is the same as the number of vector executing units VEU in the VP2 configuration shown in FIG.3. A vector instruction control unit VCU 940 is different from known vector instruction control units; however, a control signal 941 may be the same as in a known vector processor, VP2, for example. An exemplary circuit configuration of the MCU 940 is shown -in the block diagram of FIG.10. In FIG. 10, the parts designated by references 1000-1002 and 1010-1012 correspond to the respective equivalents 700-702 in FIG.7, and each of first and second vector instruction fetch control units (VFU0 and VFU1) 1030 and 1040 has a configuration and functions essentially equivalent to the circuit composed of 711-715 and 718-719 in FIG.7. That is, the parts designated by references 1031-1039 and 1041-1049 correspond to the respective equivalents 711-719 in FIG.7. VFU0 1030 and VFU1 1040 can operate independently of each other to control instruction fetch by scalar units suo 1000 and respectively SUI 1019'. They also receive and buffer the respective fetched instructions and perform decoding and exception the vector instruction fetch control units check of the received instructions. Thus,/VFU0 1030 and VFU1 1040 function as interfaces with the respective scalar units SU0 1000 and SUI 1010. An instruction switching control 1050 controls the selection of vector instructions sent either from SUO 1000 or SU1 1010. The respective vector instructions sent from SU0 1000 and SU1 1010 are referred to as 0-system vector instructions and system vector instructions. Either the 0-system or l-system vector instructions are selected to be input to a vector instruction supervisor 1060 and vector instruction queuing stage register (VQSR) 1061 in accordance with a control signal (select signal) 1051 sent from the instruction switching control 1050 to selectors 1052 and 1053. The vector instruction supervisor 1060, VQSR 1061, and a control signal 1062 sent to a vector instruction executing unit (not shown) have equivalents 717, 716 and 641 in FIG.7. The logic of the instruction switching control 1050 is established for. example so that priority is given to 0-system vector instructions in an initial state and transferred to the l-system vector instructions when a discontinuance occurs in the 0-system vector instructions or a wait is requested for the program for executing the 0-system vector instructions by an event. In FIG.llA, an example of concurrent execution of programs by the vector processor VP-N of the present invention is schematically illustrated and compared with FIG.llB schematically illustrating the execution of the same programs by the conventional multiprocessor VP1-M as shown in FIG.4, wherein programs used to run on the processors are the same as used in FIG. SC. Referring to FIG.llA, the scalar units scalar instructions are executed in/SU0 and SU1 during the period from TO to T1, and no - vector instructions are the vector unit input to/W. At T1, vector instructions are sent from both SUO and SU1 to W and are respectively input to corresponding VFu0 1030 and VFU1 1040 both shown in FIG.10. As described with reference to FIG.10, since for example 0-system vector instructions are given priority by the instruction switching control 1050 in an initial state, execution of the 0-system vector instructions, i.e. the vector instructions sent from SU0, starts first in W ata time T1, and execution of the 1-system vector instructions, i.e. the vector instructions sent from SU1, is made to wait during the period of tw, until execution of all of a sequence of consecutive 0-system vector instructions (referred to as an instruction packet) is completed.At a time T2, the execution of 0-system vector instructions in the first packet ends and the instruction switching control 1050 operates to switch execution to the first packet of l-system vector instructions. The execution time of instructions in VP-M compares with that in VP1-M as follows. Referring to FIG.11 again, the execution time of each scalar instruction packet in VP-M is equal to that in VP1-M, however, the execution time of each vector instruction packet in VP-M is one half of that in VPl-M. This is because W in VP-!wí has twice as much VEU hardware as each of WO and VU 1 in VP1-M. That is, VU in VP-M is equal to the sum of WO and Vu 1 in VPl-M in (vector instruction processing power) terms of the power of VEU; In FIG.11, each of the periods between T1-T2 and T2-T3 is one half of the period between Tl'-T2'. As a result, the total execution time in VP-M is shorter by tE than that in VP1-M. The throughput time of a program is shorter by ts in VP-M than in VP1-M. The throughput ratio of VP-M and VPl-M is given by (in this example): 1/(T2 - TO) : 1/(T2' - TO') = 4 : 3 The reason for the increased throughput in VP-M is discussed further in the following. As mentioned above, the time necessary to complete the execution of both 0-system and l-system vector instruction packets is the same in VP-M and VP1-M. therefore, the following relation is established. T3 - T1 = T2' - T1' However, in VP-M, execution of the first 0-system vector instruction packet ends at T2 at which execution of the subsequent scalar instruction packet can start. On the other hand, in VP1-M, both of 0-system and l-system vector instruction packets are executed during the period T1'-T2' and then the respective subsequent scalar instruction packets are executed during T2'-T3'. That is, neither of (next) executions of theS0-system and 1-system scalar instruction packets can startuntil T2!. Accordingly, the operating ratio of W in VP-M is as large as 67% while the respective operating ratios of WO and W1 in VP1-M remain at 50%, as derived below. (T2' - T1')/(T3' - T1') x 100 = 50% (T3 - T1) /(T4 - T1) x 100 = 678 Quantitative performance comparison of VP-M with VP1-M, VP2 and VP1 is discussed in the following, wherein the relative performance of each of the processors is derived as a function of a variable "h" which indicates the amount spent Xproportion)of execution time/on vector instruction packets in a program running on VP1. Therefore, h has a value in the range of o < h < 1 and the respective execution times of a scalar instruction packet and a vector instruction packet executed in VP1 are represented using h (i.e. by (1-h) and h respectively) as shown in FIG.12. It should be remembered that when vector instruction packets in the program shown in FIG.12 are executed in VP-M, the execution time of the vector instruction packets is one half of that in VP1. That is, the vector instruction packet execution time in VP-M may be represented by h/2. Therefore, if the execution time (1 - h) of the scalar instruction packets in the program shown in FIG.12 is ecual to the vector instruction packet execution time (h/2), the respective operating ratios of SUO, SU1 and VU in VP-M on which two programs each being shown in FIG. 12 run concurrently are 100%. In this situation, h becomes 2/3. Thus, the maximum operating ratio of VP-N, can be attained at h = 2/3. In the range of h larger or smaller than 2/3, the operating ratio decreases. Accordingly, the throughput of VP-M will now be evaluated in the respective ranges of h # 2/3 and h 2 2/3 with reference to FIGs. 13 and 14. FIG. 13 is a schematic illustration of the execution time of concurrent processing of the FIG. 12 program in VP-M under the condition h < 2/3. As mentioned before, the execution time of vector instruction packets in VP-M is one half of that in VP1, as represented by h/2, therefore, the execution time (tr) of all packets (a scalar packet and a vector packet) is given by tr = 1 - h/2 and the total throughput (P) is represented as follows. P = (1/tr) x 2 = 4/(2 - h) ........... (1) FIG.14 is a schematic illustration of the execution time of a concurrent processing of FIG. 12 programs in VP-M under the condition h 2 2/3. In this case, since the vector instruction packet execution time becomes larger than the scalar instruction packet execution time, a waiting time (th) occurs prior to the execution of each vector instruction packet except a preceding packet as shown in FIG.14. The waiting time (th) is represented by th = (h/2) - (1 - h) = (3h/2) - 1 Accordingly we obtain tr = 1 - h + th + (h/2) = h and the total through put (P) is given by P = (l/tr) x 2 = 2/h ................ (2) Total throughput (P) of VP2 for the program as shown in FIG. 12 is given as follows. P = 1/(1 - h + (h/2)) = 2/(2 - h) ..... (3) The throughput characteristics of VP2, VP1-M and VP-M relative to VPI are shown in FIG. 15 as the functions of h as represented by the equations (1), (2) and (3). As shown in FIG. 15, the throughput of VP-M has a value ranging between 2-3 and is always larger than 2 of VP1-M. In particular, the throughput of VP-M becomes 1.5 times that of VP1-M at h = 2/3. Also, the throughput of VP-M is always larger than that of VP2, showing a two-fold value in the range of h equal to or smaller than 2/3. In the multiprocessing environment as in FIG. 15, VP-M and VP1-M have respective throughput characteristics always larger than those of VP1 and VP2, however, VP1-M can no longer have a larger throughput compared with VP1 and VP2 under a condition where only one program is executed therein. The throughput characteristics of these processors in execution of a single program are discussed below. The execution time of VP-M for a single program can be represented by taking the execution of either 0-system or I-system instructions in FIG.13. Accordingly, total throughput (P) is given by P = l/tr = 2/(2 - h) ................ (4) Similarly, the throughput (P) of VP2 is given by P = 2/(2 - h) ............. ,,.... (5) The execution time of the single program in VP1-M can be represented by taking the execution of either 0-system or 1-system instructions in FIG. 113, and the total throughput (P) is given by P = 1 .................... (6) The throughput characteristics of VP2, VP1-M and VP-M relative to VP1 are shown in FIG.16 as the functions of h as represented by the equations (4), (5) and (6). As shown in FIG.16, the throughput of VPI-M is equal to thatof VP1 in the whole range of h. On the other hand, the relative throughput of VP-M, which always has the same throughput when a single program is executed characteristic as VPt, increases as h becomes large, approaching twice the throughput of VP1-M at h near 1. In a multiprocessor VP-M according to an embodiment of the present invention, an increase in hardware is required comprising the additional VFU1 and the circuits 1050-1053 relevant to the instruction switching in VCU as shown in FIG.10,when compared with VP2. The total hardware amount is equivalent to that of VP1-M. On the other hand, the throughput of VP-M in a practical multiprocessing environment is assured to be around twice compared with that of VP2 and to be 1-1.5 times compared with that of VP1-M, as shown in FIG.15. When only a single program is running on the processors, the throughput of VP-M is assured to be as good as that of VP2, whereas the throughput of VP1-M decreases to the same level as that of VP1, as shown in FIG.16. The increase in the amount of hardware in VP-M does not cause any significant problem, if the VU circuitry including the additional hardware can be mounted all together on a printed circuit board. Although the above-. described embodiment is provided with a W having a processing power twice that of each W in VP1-M, in another embodiment, if a W having the same power as that of the w in VP1-M (which is equivalent to the W in VP1) is used for VP-M, the same throughput as that of VP1-M can still be obtained with a hardware amount decreased by one VEU. Thus, a multiprocessor system having an improved throughput characteristic compared with a known multiprocessor system such as VP1-M, or alternatively a multiprocessor system requiring less hardware, can be provided thanks to the increase in the operating ratio of a W according to the present invention. As explained with reference to FIG.10, in a first embodiment of the present invention the instruction switching control 1050 provides control signals for the selectors 1052 and 1053, both of which operate to select either vector anstructions sent from the scalar unit SUO 1000 via VFU0 1030 or those sent from the scalar unit Sijl 1010 via VFU1 1040. The selected vector instructions are input to the vector instruction supervisor 1060 and then sent to a vector instruction executing unit (VEU) as 950 or 951 in FIG. 9. Thus, contention (coetition or conflict) between the vector instructions sent from SU0 and SU1 to VEU can be avoided. However, if contention control is carried out under a control program as in knawn multiprocessor systems, the processing speed must be decreased because of the overhead time required for the control. FIG. 17 is a block diagram showing an exemplary circuit configuration in accordance with a second embodiment of the present invention, wherein like numerals designate like to those or corresponding parts/in FIG.10. The circuit of FIG.17 allows the aforesaid contention control to be performed independently from a control program. In this embodiment, each of the firsttype processing units, i.e. scalar units, outputs an extra instruction added at the end of each vector instruction packet to indicate the end of the packet. The extra instruction is referred to as a pac#ket end instruction, hereinafter. When a second :type processing unit, i.e. a vector unit, detects the packet end instruction in a vector instruction packet, it switches interfaces from one corresponding to the scalar unit which has sent the vector instruction packet including the detected packet end instruction to the other interface, corresponding to the other scalar unit. FIG.18 is a chart illustrating an example execution sequence of instructions according to the second embodiment. In FIG.18, respective strings of instructions (1)-(14) and (1')-(14') are fetched by the respective scalar units Sv0 and SU1. V and S designate a vector instruction and a scalar instruction, respectively, and VE designates the aforesaid packet end instruction added to each of the vector instruction packetsacorpris ng consecutive vector instructions (1)-(2) or (1')-(6') for example. The packet end instruction VE may arbitrarily be inserted in the consecutive vector instructions according to the programmer's requirement. That is, it is not cox¯sory for a packet end instruction VE to be included in a sequence of instructions. If priority to use a vector unit (W) has been given to SUO, the vector instructions (1)-(2) fetched by SU0 are sent first to the vector instruction executing unit VEU (not shown), according to the input of a START command, and executed therein. When a packet end instruction VE (3) is detected, priority is transferred to SU1, and the vector instructions (1')-(6') fetched by SU1 are sent to VEU and executed therein. When the packet end instruction VE (7') is detected, priority is transferred back to SUO. During the execution of the vector instructions (1')-(6') in VU, the scalar instructions (4)-(5) are executed in SU0; therefore, the vector instructions (6)-(7) are sent to W after the completion of the execution of the scalar instructions (4)-(5), and executed therein. Since there is no packet end instruction VE subsequent to the vector instruction (7), the priority is held by SUO, and the vector instructions (10)-(11) are sent from SUO to VU after the scalar instructions (8)-(9) are e:ec¯;ed. When packet end instruction VE (12) is detected, the priority is transferred again to SI. Therefore, Cui sends vector instructions (11')-(13') to VU after the e: < ecution of the scalar instructions ( & )-(10') therein. SO ends its operation upon the completion of the execution of the scalar instruction (14), and SU1 upon the sending out of the packet end instruction VE (14') Thus, contention control, i.e. the dispatching of the priority to use the vector unit to either scalar unit, can be carried out speedily by simple software means such as the packet end instruction VE according to this embodiment, and hence, an optimum scheduling of the vector unit W can be achieved. Referring back to FIG.17, when consecutive vector instructions are sent from a scalar unit (SU) 1000 to a vector instruction fetch stage register (VFSRO) 1031 via a line 1001, the instructions are transmitted to a vector instruction issuing buffer 1063 in the vector instruction supervisor 1060 via a selector (SEL) 1034, AND gate 10520 in the selector (SEL) 1052 and vector instruction queuing stage register (VQSR) 1061, when vector instruction fetch buffer (VFBO) 1032 and vector instruction pre-decoding stage register (VPSR0) 1035 are empty and the latch 1054 is in the set state so as to provide SU0 with the priority to use VU. Each of the vector instructions stored in the buffer 1063 is transmitted to a vector instruction VEU excusing unit/(not shown) via a bus litre 1C62 anc executed therein as explained with reference to FIG.10. The set-reset states of latches 1054 and 1055 are opposite to each other. That is, when the output of the latch 105- is logically "1", the output of the latch 1055 is logically "0". Accordingly, when the priority to use VU is given to SUO, the vector instructions fetched by SU1 must wait in a vector instruction fetch buffer (VFB1) 1042 until the priority is given to SU1. When SUO holds the priority to use VU, the two " signal output from the latch 1055 is sent to SUl via an inverter 1057, OR gate 1046 and line 1012 as a signal to inhibit the fetch of vector After instructions. /receiving the fetch inhibiting signal, SU1 stops sending vector instructions to W. The vector instructions fetched before the fetch inhibiting control are stored in VFB1 1042 via VFSR1 1041. When an aforesaid packet end instruction (VE) is sent from SU0 to VU, the output of decoder (DEC) 1038 becomes logically "1", and AND gate 1059 outputs a signal of logically "1". As a result, the latch 1054 turns to the reset state and the latch 1055 turns to the set state. Accordingly, the "OR signal output from the latch 1054 is sent to SU0 via an inverter 1056, OR gate 1036 and line 1002 as a fetch inhibiting signal, and thus, the priority to use W is transferred to SUI, The vector instructions stored in VFB1 are transmitted to the vector instruction issuing buffer 1063 in the vector instruction supervisor 1060 via a selector (SEt) 1044, AND gate 10521 in the selector (SEL) 1052 and vector instruction queuing stage register (VQSR) 1061, and then, issued to the vector execution unit VEU (not shown) via a bus line 1062. In FIG.17, a VEU control unit 1064 in the vector instruction supervisor 1060 manages the execution condition (controls operation of) in/VEU, according to the information provided by the decoder 1038 and 1048 via the selector (SEL) 1053 comprising AND gates 10530 and 10531. The AND gates 10530 and 10531 are respectively activated by the set signals of the latches 1054 and 1055. FIG. 19 is a block diagram showing another exemplary circuit configuration in accordance with a third embodiment of the present invention, wherein like numerals to those designate like or corresponding parts/in FIGs.10 and 17. The circuit of FIG.19 also allows the aforesaid contention control to be performed independently from a control program. In this embodiment, the second type processing unit, i.e. a vector unit, is provided with means for (discontinuity or interruption) detecting a discontinuance/in each of the strings of the vector instructions sent from the first type processing units, i.e. scalar units, to the vector unit. The end of each packet of the vector instructions is identified by the discontinuance, and thus, switching of the priority for use of the vector unit is performed based on the discontinuance detection. FIG.20 is a chart illustrating execution of an example sequence of instructions according to the third enbodiment. In FIG.20, V and V' indicate vector instructions fetched by scalar units SUO and SU1, respectively, and S and S' indicate scalar instructions fetched by SU0 and SU1, respectively. If the priority to use a vector unit (W) has been given to SU0, the vector instructions (V1-V3) fetched by SUO are sent first to the vector instruction executing unit VEU (not shown) according to input of a ; START command and executed therein. When the subsequent scalar (discontinuance) instructions (S1-S2) are executed in SU0, an interruption 7 occurs in the processing of the vector instructions being executed in VU. Hence, VU judges the discontinuance to be the end of the packet of vector instructions (V1-V3) and transfers priority to Sul. As a result, Su1 sends vector instructions (V1'-V4') to W to be executed therein. When - SUI executes the subsequent scalar instructions (S1'-S3'), VU detects a discontinuance in the processing of the vedtor instructions (V1'-V4') and, hence, transfers back the priority to SU0. Similarly, the vector instructions (V4-V6) subsequent to the scalar instructions (S1-S2) are executed in VU, and further, the vector instructions (V5'-V71) subsequent to the scalar instructions (S1'-S3') are executed in W after priority transfer to SU1 according to the discontinuance detected during execution óf the scalar instructions (S3-S4), In this embodiment, detection of the discontinuance may be carried out by using a flag attached to each of the vector instructions stored in the vector instruction issuing buffer 1063. Referring back to FIG. 19, registers 1068 and 1065 for storing flag bits are provided for the vector instruction issuing buffer 1063 in the vector instruction supervisor 1060. That is, each bit of the registers 1068 or 1065 is allotted for a flag bit corresponding to each stack of the vector instruction issuing buffer 1063. When the priority to use VU is given to SUO, vector instructions fetched by SU0 are transmitted via selector (SEL) 1034 and AND gate 10520 in the selector (SEL) 1052 to the vector instruction issuing buffer 1063 and stored therein. Synchronizing with the input of each vector instruction into the vector instruction issuing buffer 1063, the output signal of the latch 1054 which is in the set state is input to the register 1068 and stored in each bit thereof as a . corresponding flag of logical " As the vector instructions stored in the vector instruction issuing buffer 1063 are sent out to a vector instruction executing unit (VEU; not shown) via a bus line 1062 so as to be executed therein, the vector instruction (when buffer 1063 is completely empty) issuing buffer 1063 becomes empty. At this moment, all of the flag bits in the register 1068 are logically "0" because the flags corresponding the instructions which have been issued to VEU are made invalid, and hence, a signal of logical "1" is output from NOR gate 1066. As a result, the output of AEUP gate 1059 becomes logically "1", and latch 1055 turns to the set state. Accordingly, the priority to use VU is transferred to SU1 in the same manner as in the second embodiment explained with reference to FIG.17, and the vector instructions stored in vector instruction fetch buffer (VFB) 1042 are transmitted via selector (SEL) 1044 and AND gate 10521 in the selector (SEL) 1052 to the vector instruction issuing buffer 1063 and stored therein. In this sequence, the output signal of the latch 1055 which is now in the set state is input to the register 1065 and stored in each bit thereof as the corresponding flag of logical " The vector instructions stored in the vector instruction issuing buffer 1063 are sent to VEU (not shown) via the bus line 1062 so as to be executed therein, and the vector instruction issuing buffer 1063 becomes empty. At this moment, all the flag bits in the register 1065 are logically "0", and NOR gate 1067 outputs a signal of logical "1". Accordingly, the latches 1054 and 1055 are turned to the set and reset states, respectively, and the priority is transferred back to SU0. T#he above described transfer process of the priority to use VU can be repeated as necessary. As described above, in this embodiment, the instruction switching control 1050 operatively switches to select the connections to the interfac"es, the vector instruction fetch control units VFU0 and VFU1, according to flags informing of the absence of vector instructions in the vector instruction issuing buffer 1063 provided in the vector instruction supervisor 1060. Thus, the present invention may provide a multiprocessor system including first and second kinds processing units operable independently each other for processing different kinds of instructions, comprising: a plurality of said first kind processing units; and one said second kind processing unit having a plurality of respective interfaces with said first kind processing units, wherein said second kind processing unit operatively switches to select one of said interfaces receiving instructions sent from one said first'kind processing unit corresponding to selected said inter face and processes the received instructions therein. It will be understood that the invention is not limited in its application to the details of construction and arrangement of parts illustrated in the accompanying drawings, since the invention is capable of other embodiments and of being practiced or carried out in various ways. For example, in other embodiments of the present invention three or more scalar units (SU) may be provided in the multiprocessor configuration. Also, it is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. The scope of the present invention, therefore, is to be determined solely by the following claims. In particular, embodiments of the present invention may provide a multiprocessor system of a vector processor type including two or more scalar units and one vector unit. Priority for use of the vector unit by the scalar units is switched from one scalar unit to another scalar unit by detecting an interruption in the instructions under execution in the vector unit. The discontinuance detection may be performed by adding an instruction at the end of a packet of instructions being executed or to be executed in the vector unit, or performed by detecting the absence of instructions in a buffer which stores instructions to be executed. The quantitative throughput characteristic and operating ratio of the vector unit of- the multiprocessor system is improved in comparison with known multiprocessor systems.

Claims: CLAIMS 1. A multiprocessor system including first and second type processing units operable for processing independently different kinds of instructions, comprising: a plurality of said first type processing units; and one said second type processing unit having a plurality of respective interfaces with said first type processing units, wherein said second type processing unit is operable to switch to select one of said interfaces receiving instructions sent from its respective said first type processing unit, and to process the received instructions therein. 2. A multiprocessor system as set forth in claim 1, wherein said first type processing units are scalar instruction processing units for processing scalar instructions and said second type processing unit is a vector instruction processing unit for processing vector instructions. 3. A multiprocessor system as set forth in claim 1 or 2, wherein said second type processing unit is operable to switch from a selected one of said interfaces to another of the interfaces when a discontinuance interruption occurs in the processing of instructions sent from the first type processing unit corresponding to said selected interface. 4. A multiprocessor system as set forth in any preceding claim, wherein consecutive instructions are grouped in plural instruction packets and the said first type processing unit corresponding to a currently selected interface is operable to send out the instructions in one of the instruction packets one after another to said second type processing unit, wherein each instruction packet is provided with an additional instruction, for indicating end of the packet, at the end of the packet and said second type processing unit is operable to switch from the selected interface to another one upon detecting said additional instruction, whereby instructions in respective instruction packets sent from said first type processing units may be selectively processed in said second type processing unit. 5. A multiprocessor system as set forth in any of claims 1 to 3, wherein consecutive instructions are grouped in plural instruction packets and the said first type processing unit corresponding to a currently selected interface is operable to send out the instructions in one of the instruction packets one after another to said second type processing unit, further comprising a buffer provided in said second type processor, said buffer being provided for storing instructions of the instruction packet sent from the first type processing unit corresponding to the currently selected interface, wherein said second type processing unit is operable to switch from the selected interface to another one upon detecting an absence of instructions in said buffer, whereby instructions in respective instruction packets sent from said first type processing units may be selectively processed in said second type processing unit. 6. A multiprocessor system as set forth in claim 5, wherein said buffer comprises a plurality of extra bits each of which may correspond to an instruction stored in said buffer, there being an AND gate having inputs each connected to a respective one of said extra bits, said extra bits being provided for storing information of the presence or absence of corresponding instructions in said buffer, and said second type processing unit being operable to switch said interfaces in accordance with the output signal of said AND gate.

Inventors: ITOH, MIKIO C/O FUJITSU LIMITED, OKAMOTO, TETSURO C/O FUJITSU LIMITED, SAKAMOTO, KAZUSHI C/O FUJITSU LIMITED
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F15
IPC codes: G06F15, G06F9