SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY CIRCUIT

Abstract: A semiconductor memory device including a random-­ access memory (RAM) having at least one redundancy column for replacing a defective column, a serial output circuit (SR₁...SR n ) for reading out in parallel and outputting serially data stored in the random access memory, and a redundancy circuit (RA, 4,5,6,7,DC₁,RSA) for replacing data of the defective column with data of the redundancy column.

Description: The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device having a redundancy circuit. There is known a semiconductor memory device consisting of a combination of a random-access memory (RAM) and a shift register group. This type of semiconductor memory device is, in general, used as an image memory. The shift register group is attached to the RAM for high-speed read-out of the data stored therein. The RAM is, for example, provided between a central processing unit (CPU) and a cathode-ray tube display (CRT). The data stored in the RAM is read out in parallel to the shift registers in accordance with control of a system. The read-out data is output serially from the shift register group to the CRT. IBM T.D.B., Vol. 24, No. 9, pp 4776-8, discloses a system for dynamic allocation of redundant memory components in a multiple-bit-output memory device, having features corresponding to those of the preamble of accompanying claim 1. A defective memory array element and its associated I/O circuitry are replaced as a whole by a redundant memory array element and I/O circuity; thereafter, defective data is blocked and replaced by data from the redundant memory array element before reaching a data bus. EP-A-0 030 245 by the present applicant discloses a random access memory device with provision for replacing a defective memory cell by a redundant memory cell. However, this memory device does not include a serial output means and therefore does not provide redundancy control of a serial output mode. IBM T.D.B., Vol. 13, No. 7, pp 1880-1, discloses a redundancy scheme for a shift register memory, including a so-called reconfiguring shift register which stores information identifying a defective memory shift register. The data intended for the defective memory shift register is handled by a redundant memory shift register. Even in view of the above disclosures, there is still no known RAM having both random access and serial data output functions and a redundancy function. According to the present invention, there is provided a semiconductor memory device comprising:- a memory cell array having a plurality of regular columns and at least one redundancy column, for replacing a defective one of said regular columns; and serial output means for reading out data from said regular and redundant columns in parallel and serially outputting the read-out data; characterised in that:- the memory device is a random-access memory device having random-access input and output means, operatively connected to said memory cell array, for inputting data and outputting data from a selected one of the regular or redundant columns; said serial output means being operatively connected to said memory cell array independently of said random-access input and output means, whereby the memory device is operable either in a random access mode or a serial output mode; and in that redundancy control means are provided, operatively connected to said serial output means and responsive to the address of defective one of said plurality of regular columns for replacing data of said defective one of said plurality of regular columns, after it has been read out by said serial output means, with data from said at least one redundancy column. The embodiment of the present invention provides a semiconductor memory device which enables both low-speed random access by a CPU and high-speed serial data transmission between RAM and a CRT. It also provides a circuit giving a redundancy function to a semiconductor memory device. Such a redundancy circuit enables an increase of the yield in production of semiconductor memory devices. The embodiment of the present invention provides a semiconductor memory device having a serial output means for high-speed read-out of data and a redundancy circuit for raising the yield. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1 is a schematic block diagram of a semiconductor memory device according to an embodiment of the present invention; Fig. 2 is a schematic block diagram of a semiconductor memory device according to another embodiment of the present invention; Fig. 3 is a schematic block diagram of a semiconductor memory device according to another embodiment of the present invention; and Fig. 4 is a schematic block diagram of a semiconductor memory device according to still another embodiment of the present invention. A semiconductor memory device according to an embodiment of the present invention will be explained in detail with reference to the accompanying drawings. Figure 1 is a schematic block diagram of a semiconductor memory device according to an embodiment of the present invention. In Fig. 1, reference numeral 1 represents a column decoder, 2 a row decoder, 3 an image memory (RAM), 4 a multiplexer, 5 a counter, 6 a redundancy read-only memory (redundancy ROM), and 7 a comparator. Reference letters SA₁ to SA n represent sense amplifiers, RSA a redundancy sense amplifier, DC₁ a drive circuit, SR₁ to SR n shift registers, and RA a redundancy amplifier. In the RAM 3, MC is a memory cell connected between word lines WL and bit lines BL, BL . The bit lines BL are connected to the corresponding shift registers SR₃ through the transfer gate TG, and the word lines WL are connected to the row decoder 2. The slanted line portion in the RAM 3 indicates a redundancy column (column of redundant cells). In this embodiment, a redundancy circuit is constituted by the drive circuit DC₁ , the redundancy sense amplifier RSA, the redundancy amplifier RA, the multiplexer 4, the counter 5, the redundancy ROM 6, and the comparator 7. In the inspection of the manufacture of the RAM, when a defective column is found, the column address indicating the defective column is stored in the redundancy ROM and the redundancy ROM is enabled. That is, the redundancy ROM 6 is enabled to provide the column address (or addresses) corresponding to the defective column (or columns) of the RAM 3. Storage of the defective column address in the redundancy ROM 6 may be performed by cutting a polycrystalline silicon fuse. There are two known methods for cutting a polycrystalline silicon fuse, i.e., one utilizing a laser beam and another method utilizing electrical current. A semiconductor memory device according to the present invention basically operates such that, when a defective column in the RAM is accessed by an address ADD sent from the CPU, this defective column is replaced by a redundancy column in the RAM, indicated by slanted lines in Figure 1. That is, an area of the memory is reserved for the redundancy function. Accordingly, even if a defective column is found in the RAM, the device can operate as a normal memory. The operation of tie device of Figure 1 will now be explained in detail. If a defect is found in the column corresponding to, for example, the sense amplifier SA₂ , the corresponding column address is stored in the redundancy ROM 6. In the random access mode, in read-out when the input address ADD from the CPU is applied to the column decoder 1 and the comparator 7, if no defective column address is included in the input address, data corresponding to the input address is output from the RAM to the data bus DB through the corresponding sense amplifiers and output from the amplifier AMP₀. In writing, write data corresponding to the input address is input to the RAM from the data bus DB. Assume a defective column address corresponding to the sense amplifier SA₂ is included in the input address. The comparator 7 compares the input column addresses with the stored defective column address in the redundancy ROM 6. As one of the input column addresses coincides with the stored defective column address, a coincidence signal COM is input to the drive circuit DC₁ and an inverted coincidence signal COM is input to the column decoder 1. When the coincidence signal COM is input to the drive circuit DC₁ , the drive circuit DC₁ activates the redundancy sense amplifier RSA for use of the redundancy column. Accordingly, data from the data bus DB is read out from or written to the RAM using the redundancy column instead of the defective column. In the serial output mode, data stored in the RAM is simultaneously read out in parallel to the shift registers SR₁ to SR n through the transfer gates TG. Accordingly, data corresponding to the defective column is also read out to one of the shift registers, for example, to the shift register SR₂. Each shift register sequentially transfers the input data to the next shift register every clock signal S CLK . Finally, the input data is shifted to the final shift register SR n and input to the multiplexer 4. Data corresponding to the redundancy column, i.e., the correct data, is latched in the redundancy amplifier RA. When the data corresponding to the defective column, i.e., the defective data, is shifted to the multiplexer 4, that is, the data of the shift register SR₂ is transferred to the multiplexer 4 through the shift register SR n , the multiplexer 4 replaces the defective data with the correct data latched in the redundancy amplifier RA for output to the CRT. Accordingly, correct serial outputs S OUT can be obtained at a high speed. The data replacement operation in the multiplexer 4 will be explained in more detail below. As mentioned above, the defective column address is previously stored in the redundancy ROM 6. That is, the number of the defective column counted from the final column (final shift register SR n ) is also stored in the redundancy ROM 6. The number of columns between the final column and the defective column is read out from the redundancy ROM 6 and input to the counter 5. Accordingly, the counter 5 is initially set to that number of columns after it is preset by the transfer gate signal STG. The clock signal S CLK is input to the counter 5 and input in parallel to the shift registers SR₁ to SR n . The counter 5 subtracts one from the number of columns every clock signal S CLK . At the same time, the data in each shift register is shifted to the next shift register every clock signal S CLK . When the count becomes "0", the counter 5 outputs a coincidence signal SCOM to the multiplexer 4. At this time, since the defective data shifted by the shift registers arrives at the multiplexer 4, the multiplexer 4 can replace the defective data with the correct data based on the coincidence signal SCOM. Accordingly, serial output of the correct data can be obtained from the multiplexer 4 and transmitted to the CRT. When the transfer gate control signal STG is ON, all transfer gates TG are simultaneously turned ON so as to transfer the data in the RAM in parallel to the shift registers SR₁ to SR n . Figure 2 is a schematic block diagram of a semiconductor memory device according to another embodiment of the present invention. In Fig. 2, the same reference numerals and letters as in Fig. 1 indicate the same elements. In this embodiment, a decoder 8, flip-flop circuits FF₁ to FF n , gates G₁ to G n , and data bus RDB are provided instead of the multiplexer 4 and the counter 5 shown in Fig. 1. As mentioned above, the defective column address is previously stored in the redundancy ROM 6. In this embodiment, in the random access mode, the same read/write operations of the redundancy column as the redundancy column shown in Fig. 1 are performed. Accordingly, explanations of the operations will be omitted. In the serial output mode, when data corresponding to the defective column is read out from the RAM to one of the shift registers, for example, to the shift register SR₂ , the defective data is compulsorily replaced by the correct data sent from the redundancy amplifier RA through the redundancy data bus RDB and the gate G₂ in the first next shift operation. That is, information regarding the defective column address stored in the redundancy ROM 6 is applied to the decoder 8. The decoder sets the corresponding flip-flop circuit. In this case, the flip-flop circuit FF₂ is set by the decoder 8. Since all flip-flop circuits FF₁ to FF n have been reset in the initial state, only the flip-flop circuit FF₂ is set, and the corresponding gate G₂ is turned ON by the output of the flip-flop circuit FF₂. Other gates G₁ and G₃ to G n are turned OFF. Accordingly, as explained above, the correct data latched in the redundancy amplifier RA is sent to the output of the shift register SR₂ through the data bus RDB and the defective data is replaced with the correct data. Consequently, the correct serial outputs can be obtained from the final shift register SR n and transmitted to the CRT. Figure 3 is a schematic block diagram of a semiconductor memory device according to another embodiment of the present invention. In this case, a new redundancy column (slanted lines portion in the Figure) is added to the memory area in the RAM 3. As can be understood, the yield of devices can be raised by the addition of the new redundancy column over the single redundancy column shown in Figs. 1 and 2. In Fig. 3, reference letter m represents an m-bit address. With the addition of the new redundancy column, the redundancy sense amplifier RSA₂ , the drive circuit DC₂ , the comparator COMP4, and the redundancy ROM 2 are newly added to the redundancy circuit. In the same way as explained above, a second defective column address is previously stored in the redundancy ROM 2. Of course, the first defective column address is previously stored in the redundancy ROM 1. In this embodiment, in the random access mode, the same read/write operations of the redundancy columns as the redundancy column shown in Fig. 1 are performed. Accordingly, explanation of the operations will be omitted. Reference letters PR₁ to PR₂m represent so-called pointers functioning as a ring counter in the serial output mode. Reference letters FF₁ to FF₂m represent flip-flop circuits. These pointers and flip-flop circuits perform the same function as the shift register group shown in Figs. 1 and 2. Each of the pointers PR₁ to PR₂m can shift the signal "1" in response to the clock signal S CLK . That is, the signal "1" is sequentially shifted from the first pointer PR₁ to the final pointer PR₂m. Accordingly, only one pointer at a time becomes "1". The other pointers become "0". In this case, a preset means may be provided in order to preset the pointer PR₁ so as to become "1" as the start position of the serial operation. When a pointer becomes "1", the corresponding gate is turned ON and the data latched in the flip-flop circuit is read out through a shift data bus SDB. Accordingly, the data in the RAM is sequentially read out through the shift data bus SDB by the sequential turning ON of each gate in response to the signal "1" of the pointer. If defective data is latched in the flip-flop circuit FF₂ for example, then when the pointer PR₂ becomes "1", the gate G₂ is turned ON and the defective data is sent to the multiplexer MPX through an amplifier AMP₁. Also, when the pointer PR₂ becomes "1", the gate G R1 is turned ON by the coincidence signal SCOM1 sent from a comparator COMP1. Accordingly, the correct data latched in a redundancy flip-flop circuit RFF₁ is read out to an amplifier AMP₂ through the gate G R1 and the redundancy data bus RDB. Since the coincidence signal SCOM1 is simultaneously input to the multiplexer MPX, the multiplexer MPX can replace the defective data with the correct data. In this case, as explained in Fig. 1, the coincidence signal SCOM1 is generated when the comparator COMP1 compares the number of the defective column address stored in the redundancy ROM 1 with the number of the m-bit counter and detects coincidence therebetween. The m-bit counter is preset by the transfer gate signal STG. As can be understood, the same explanations apply to the second redundancy column using the redundancy ROM 2, a comparator COMP2, and a coincidence signal SCOM2. This method using pointers can reduce power consumption compared with the method using shift registers shown in Figs. 1 and 2. This is because each shift register must sequentially transfer data to the next shift register. Conversely, only one selected pointer and flip-flop need transfer data to the output. Figure 4 is a schematic block diagram of a semi-conductor memory device according to still another embodiment of the present invention. In Fig. 4, the same structure as that of Fig. 3 is applied for the random access mode. In the serial output mode, the shift data bus SDB is used instead of a redundancy data bus RDB. Accordingly, the redundancy data bus RDB is eliminated and the redundancy flip-flop circuits RFF₁ and RFF₂ are connected to the shift data bus SDB through the gates G R1 and G R2 . In this embodiment, the gate corresponding to the defective data, for example, the gate G₂ , is not turned ON since the corresponding pointer PR₂ does not output the signal "1". In this case, all pointers become "0" because the clock signal S CLK is not applied to them (for instance by means of the signals SCOM1, SCOM2). Alternatively, the gate G R1 is turned ON at the same time based on the coincidence signal SCOM1 explained above, so that the correct data latched in the redundancy flip-flop circuit RFF₁ is output to the amplifier AMP₁ through the gate G R1 and the shift data bus SDB. Regarding the pointers coupled with the column decoder, since the start position of the signal "1" pointer can be arbitrarily selected by the column decoder, the corresponding gate can be turned ON so that the data stored in the RAM can be read out from the corresponding column. That is, an arbitrary head address can be designated by the pointer. This is advantageous for so-called "scrolling" of the image data. As can be understood, similar advantages to the embodiment shown in Fig. 3 are obtained by this embodiment.

Claims: A semiconductor memory device comprising:- a memory cell array (3) having a plurality of regular columns and at least one redundancy column, for replacing a defective one of said regular columns; and serial output means for reading out data from said regular and redundant columns in parallel and serially outputting the read-out data; characterised in that:- the memory device is a random-access memory device having random-access input and output means (1, 2, SA₁, ..., SA n , RSA, DB), operatively connected to said memory cell array, for inputting data and outputting data from a selected one of the regular or redundant columns; said serial output means being operatively connected to said memory cell array independently of said random-access input and output means, whereby the memory device is operable either in a random access mode or a serial output mode; and in that redundancy control means are provided, operatively connected to said serial output means and responsive to the address of a defective one of said plurality of regular columns for replacing data of said defective one of said plurality of regular columns after it has been read out by said serial output means, with data from said at least one redundancy column. A semiconductor memory device as claimed in claim 1, wherein said serial output means comprises:- a plurality of flip-flop circuits (FF₁, FF₂, ...,FF₂m; fig.3), operatively connected to said memory cell array (3), for latching the data read out from said memory cell array (3); a data bus (SDB, fig.3) for outputting said read-out data sequentially; a plurality of gates (G₁, G₂, ..., G₂m, fig.3), operatively connected between said data bus (SDB, fig.3) and said plurality of flip-flop circuits (FF₁, FF₂, ...FF₂m, fig. 3) for transferring said read-out data latched in said plurality of flip-flop circuits; and a plurality of pointers (PR₁, PR₂, ...PR₂m, fig.3), mutually connected in a ring and each connected to a corresponding one of said gates (G₁, G₂, ...G₂m, fig.3), one of said pointers containing a predetermined signal which is transferred around the pointers in turn, so as to activate each one of said gates (G₁, G₂, ...G₂m, fig.3) sequentially. A semiconductor memory device as claimed in claim 2, further comprising a redundancy flip-flop circuit (RFF₁, RFF₂, fig.3), operatively connected between said redundancy column and said data bus (SDB, fig.3), for latching data read out from said at least one of said redundancy column. A semiconductor memory device as claimed in claim 2, further comprising:- at least one redundancy flip-flop circuit (RFF₁, RFF₂, fig.3), operatively connected to said at least one of said redundancy columns, for latching data read out from said at least one of said redundancy columns; and a redundancy data bus (RDB, fig.3), operatively connected to said redundancy flip-flop circuit (RFF₁, (RFF₂, fig.3), for outputting said read-out data latched therein. A semiconductor memory device as claimed in claim 2, 3 or 4, wherein a start position of said predetermined signal in said pointers (PR₁, PR₂, ...PR₂m, fig.3) is arbitrarily selected. A semiconductor memory device as claimed in claim 1, wherein said redundancy control means comprises:- a read-only memory (6, fig.2) for storing a defective column address; latching means (RA, fig.2), operatively connected to said at least one redundancy column, for latching the data read out from said at least one redundancy column; a decoder (8, fig.2), operatively connected to said read-only memory (6, fig.2), for decoding said defective column address; a plurality of flip-flop circuits (FF₁, FF₂, ..., FF m , fig.2 operatively connected to said decoder (8, fig.2), for receiving outputs of said decoder; a plurality of gates (G₁, G₂, ..., G m ,fig.2), operatively connected to corresponding ones of said flip-flop circuits (FF₁, FF₂, ...FF m , fig.2), selectively turned on in accordance with the outputs of said flip-flop circuits; and a data bus (RDB, fig.2), operatively connected to said plurality of gates (G₁, G₂, ...,G m , fig.2) and to said latching means (RA, Fig.2), for replacing data of said defective column with the data of said at least one redundancy column. A semiconductor memory device as claimed in claim 1, wherein said redundancy control means comprises:- a read-only memory (6, fig.1) for storing a defective column address; latching means (RA, fig.1), operatively connected to said at least one redundancy column, for latching data read out of said at least one redundancy column; a counter (5, fig.1), operatively connected to said read-only memory (6, fig.1) and operatively connected to receive a clock signal (S clk ), for counting the clock signal and outputting a coincidence signal (SCOM, fig.1) when the number in said counter corresponds to a column number indicating said defective column; and a multiplexer (4, fig.1), operatively connected to said counter (5, fig.1), for replacing data in said defective column with data in said at least one redundancy column upon receipt of said coincidence signal (SCOM, fig.1).

Inventors: OGAWA, JUNJI
Applicants: FUJITSU LIMITED
Application year: 1985
Main classification: G06F11
IPC codes: G11C29, G06F12