WAFER-SCALE-INTEGRATED ASSEMBLY

Abstract: The silicon wafer (54) of a wafer-scale-integrated assembly is doped to render it highly conductive. Additionally, a conductive layer (56) is formed on the bottom of the wafer. The bottom-side layer forms an easily accessible ground plane of the assembly. Moreover, this layer and the conductive silicon constitute one plate of an advantageous wafer-size decoupling capacitor. A nearly continuous power layer (58) and a relatively thick layer (60) of silicon dioxide on the top side of the assembly form the other elements of the decoupling capacitor. Additionally, the nearly continuous power layer constitutes an effective a-c ground plane for overlying signal lines.

Description: WAFER-SCALE-INTEGRATED ASSEMBLY Background of the Invention This invention relates to integrated-circuit chips and, more particularly, to an assembly of interconnected chips. It is known to utilize a pattern of lithographically formed conductors on a semiconductor wafer to interconnect a number of semiconductor chips. In some cases, the chips to be interconnected are mounted on the surface of the wafer or in recesses formed in the wafer surface. In other cases, the chips are formed in the wafer as integral parts thereof. Herein, all of these and similar arrangements are referred to as wafer-scale- integrated (WSI) assemblies. In a WSI assembly, it is desirable to include large-area power and ground conductors in the conductive pattern formed on one surface of the wafer. Separate power and ground metallization planes at respectively different levels would be ideal from an electrical standpoint. But since separate X- and Y-signal metallization levels are also typically required in the assembly, the electrically ideal structure would include four separate metallization levels on the one surface of the wafer. However, such a four-level-metallization structure is quite complex from a fabrication standpoint. Therefore, in practice, one feasible WSI assembly includes large-area power and ground conductors suitably separated from each other in a common plane in a three- level-metallization structure formed on one surface of the wafer. While not electrically ideal, such a structure is considerably easier and less costly to manufacture than a four-level-metallization one. Virtually all WSI assemblies require decoupling capacitors. It " is known to include such a capacitor under or adjacent to each chip on the wafer. For high-speed operation, it is vital that these capacitors be located as close as possible to their respective chips. But even relatively short leads extending between a decoupling capacitor and its associated chip may have sufficient inductance to deleteriously affect the performance of very- high-speed circuits. Additionally, the intrinsic inductance of the multiple individual capacitors also tends to limit the speed of operation of the circuits included in the WSI assembly. This invention provides WSI assemblies of improved structure and performance. A silicon wafer is highly doped to render it relatively conductive. A substantially planar and continuous metallization layer is formed overlying the top surface of the wafer. A continuous metallization layer is formed on the bottom surface of the wafer. Spaced-apart X- and Y-signal metallization layers are formed overlying the top surface. The resulting WSI assembly thus includes three metallization layers on the top surface of the wafer and one such layer on the bottom surface thereof. Interconnected chips of the assembly are included on the top surface of the wafer. The assembly can also include a dielectric layer underlying a major extent of the top surface metallization layer. This layer thus constitutes one plate of a wafer- size capacitor. The conductive wafer itself and the bottom-surface layer form the other plate of this capacitor. Hence, whenever an electrical connection is made between a pad on the chip and the upper surface layer, the wafer-size capacitor is also thereby connected to the chip in a low-inductance way to provide effective decoupling. Brief Description of the Drawing FIG. 1 is a generalized overall schematic representation of a conventional WSI assembly; FIG. 2 schematically depicts a three-layer metallization structure as heretofore proposed for an assembly of the FIG. 1 type; FIG. 3 represents a portion of the FIG. 2 assembly in the immediate vicinity of one of the component chips thereof; FIG. 4 shows the details of a portion of a WSI assembly made in accordance with the present invention; and FIG. 5 is a generalized overall schematic representation of a larger portion of the FIG. 4 assembly. Detailed Description The conventional WSI assembly represented in FIG. 1 comprises a wafer 10 made of silicon having a thickness _t of approximately 500 micrometers (μm). By way of example, the wafer 10 is square, measuring about 7.5 centimeters (cm) on a side. The resistivity of the conventional wafer 10 is relatively high, being, for example, greater than ten ohm-centimeter. For assembly interconnection purposes, it is usually desired to provide a square wafer. But to maximize the available wafer area, it is advantageous in some cases to provide a generally square wafer with rounded corners, as shown, for example, in FIG. 13 on page 1619 of "A 1-Mbit Full-Wafer MOS RAM," IEEE Transactions on Electron Devices, Volume ED-27, No. 8, August 1980, page 1612. A number of standard integrated-circuit chips 12 are included in the FIG. 1 assembly. Advantageously, the chips are also made of silicon thereby to achieve a chip/wafer assembly with a matched coefficient of thermal expansion. Illustratively, each chip is also about 500 μm thick and is square, measuring about 0.6 cm on a side. A number of ways are available for incorporating the chips 12 in the assembly depicted in FIG. 1. The technique illustrated here involves conventional face-down solder-ball bonding in which microminiature solder posts each about 50 μm high and having a diameter of approximately 125 μm are utilized to connect bonding pads on the face of each chip to lithographically defined conductors included in a three-level metallization - 4 - structure 14 (FIG. 1) formed on the top surface of the wafer 10. The WSI assembly shown in FIG. 1 is depicted as being associated with a standard package 16. By way of example, the package includes instrumentalities (not shown) for making electrical contact with peripheral portions of the metallization structure 14 on the wafer 10. The package also typically includes a suitable heat sinking arrangement for cooling the assembly. The standard metallization structure 14 depicted in FIG. 1 includes three levels insulated from each other. One level, which will be described in detail below in connection with FIG. 2, includes spaced-apart planar power and ground conductors. The other two levels respectively contain signal conductors. Typically, the signal conductors in one of these levels are all disposed parallel to each other in the X direction, and the conductors in the other level are disposed parallel to each other in the Y direction. These X-signal and Y-signal conductors are, for example, each about 2 μm thick and 10-to-20 μm wide. By standard integrated circuit fabrication techniques, connections are made between selected ones of the X-signal and Y-signal conductors and between selected signal conductors and patterned portions of the power/ground metallization included in the structure 14 of FIG. 1. Interconnections are also formed from these patterned portions and from the power/ground metallization to contact areas in a chip-mounting site. Thus, when a chip is attached to the wafer-size interconnection assembly (for example, by face-down solder-ball bonding), bonding pads on the chip are thereby connected to selected ones of the power, ground, X-signal and Y-signal conductors of the WSI assembly. FIG. 2 shows an illustrative single-level power/ground metallization pattern including spaced-apart large-area planar conductors 18 and 20. Illustratively, the conductor 18 comprises the power conductor of the depicted WSI assembly and the conductor 20 comprises the ground conductor of the assembly. As indicated in FIG. 2, portions of these power and ground conductors surround each of nine mounted chips 21 through 29. Two X-signal leads which are formed in a metallization level that overlies the aforedescribed power/ground level are schematically represented in FIG. 2 by dashed lines 30 and 31. Similarly, two Y-signal leads which are formed in yet another overlying metallization level are depicted in FIG. 2 by dashed lines 32 and 33. In an overall system that includes the WSI assembly shown in FIG. 2, the conductor 20 is connected to a point of reference potential such as d-c ground. The conductor 18 is connected to a positive (or negative) potential with respect to ground. But, since the conductor 18 is also typically connected to ground via decoupling capacitors, the conductor 18 is in effect thereby maintained at a-c ground. Ideally, the signal leads 30 through 33 should overlie a continuous ground plane. In such an ideal structure, signals propagated in the leads 30 through 33 are minimally distorted. It is apparent from FIG. 2, however, that the representative signal leads 30 through 33 of the actual depicted WSI assembly overlie discontinuities in the underlying metallization level that includes the power and ground conductors 18 and 20. With respect to the signal lead 33, for example, these discontinuities occur at breaks in the underlying metal. These break points are identified in FIG. 2 by reference numerals 34 through 43. Because of these and similar discontinuities in the underlying metallization, signals propagated in the X and Y leads represented in FIG. 2 suffer distortion. In some systems, this distortion may be sufficient to deleteriously affect the desired operation thereof. One standard way of achieving the aforementioned decoupling capacitors is schematically suggested in FIG. 3 which in enlarged form shows portions of the power and ground conductors 18 and 20 in the immediate vicinity of the mounted chip 22 of FIG. 2. In particular, FIG. 3 represents a decoupling capacitor underlying the chip 22. This capacitor is shown in dashed outline and designated by reference numeral 44. One way of achieving the decoupling capacitor 44 (FIG. 3) is to form two metal plates under the chip 22 separated by a dielectric layer of silicon dioxide, tantalum oxide, or other suitable dielectric. Alternatively, the bottom plate of such a capacitor may be formed by suitably doping a localized portion of the underlying silicon wafer. In either case, the dielectric material thickness required to realize the required decoupling capacitance in such a small-area capacitor is typically only about 400 Angstrom units (A) . But, in practice, it has been found that 400-A-thick layers of dielectric material in capacitor structures in a WSI assembly of the type represented in FIGS. 1 through 3 are characterized by troublesome pin-holes. In turn, these pin-holes can fill up with metal and thereby cause plate-to-plate shorts in the capacitor structure. The occurrence of such pin-holes in the capacitor dielectric has been determined to be a significant factor standing in the way of economically achieving highly reliable high-speed assemblies. Additionally, it is necessary in a standard WSI assembly of the type described herein to connect the plates of each under-chip decoupling capacitor to the adjacent power and ground conductors of the assembly. Thus, as schematically shown in FIG. 3, multiple leads are lithographically defined to connect the respective plates of the capacitor 44 to the power and ground conductors 18 and 20. By way of example, leads 46 through 48 connect one plate of the capacitor 44 to the power conductor 18, and leads 50 through 52 connect the other plate of the capacitor to the ground conductor 20. The inductance of even relatively short leads such as the leads 46 through 48 and 50 through 52 of FIG. 3 can be limiting in a high-performance WSI assembly. In particular, the inductance of these leads can impose an undesirable limit on the high-speed operating capabilities of the assembly. FIG. 4 shows a portion of a WSI assembly made in accordance with the present invention. Illustratively, the FIG. 4 assembly comprises a square single-crystal silicon wafer 54 about 500 μm thick and measuring approximately 7.5 cm on a side. The wafer 54 is highly doped to render it relatively conductive. By way of example, the wafer 54 is doped with an n-type impurity such as arsenic to a level of approximately 10 19 atoms per cubic centimeter. Advantageously, this doping is done at the time of forming the silicon ingot from which the wafer is subsequently cut. Such doping imparts a relatively low resistivity of approximately 0.006 ohm- centimeter to the wafer 54. In general, wafer resistivities less than approximately 0.01 ohm-centimeter are used. A conductive layer 56 such as a 2-μm-thick layer of aluminum is deposited on the entire bottom surface of the wafer 54 of FIG. 4. The planar layer 56 functions as a continuous ground conductor for the assembly and, additionally, constitutes a part of one plate of a wafer- size decoupling capacitor included in the assembly. Advantageously, the metallic layer 56 (FIG. 4) is deposited on the bottom surface of the wafer 54 during the same processing step in which another layer of the same material and thickness is being deposited on or overlying the top surface of the wafer 54. Thus, by way of example, the aforementioned 2-μm-thick aluminum layer 56 is deposited at the same time that a layer 58 of the assembly is being deposited. The layer 58 constitutes a large-area planar power conductor. The planar nature of the power conductor is typically interrupted only in regions immediately under mounted chips or in regions directly adjacent thereto, as appears hereinafter. Significantly, because the layers 56 and 58 (FIG. 4) are deposited at the same time and on opposite sides of the wafer 54, the likelihood of bowing occurring in the wafer 54 during or after deposition is substantially reduced. This advantageous result stems from the fact that the layers 56 and 58 subject the wafer 54 to forces that tend to counterbalance each other. As a result, no net force or no appreciable net force acts to distort the planar top surface of the wafer 54. A dielectric layer 60 comprising, for example, a 1500-A-thick layer of thermally grown silicon dioxide directly underlies a major extent of the conductive layer 58. Because of its relative thickness (compared, for example, to 400 A) the layer 60 constitutes an excellent virtually pin-hole-free dielectric. However, even if the relatively thick dielectric layer 60 cannot be made perfectly pin-hole free over such large areas, it is feasible in practice easily to repair a capacitor structure that includes such a dielectric. This is done, for example, by applying a controlled current to the structure sufficient to vaporize any metal filling the pin-holes. The layer 60 of FIG. 4 comprises the dielectric of a large-area decoupling capacitor whose upper plate is the power conductor 58. As mentioned above, the lower plate of this capacitor includes the highly doped wafer 54 and the ground conductor 56. The large-area nature of this capacitor permits the dielectric layer to be relatively thick (1500 A) while the structure still achieves the required large value of decoupling capacitance. In effect, the aforedescribed capacitor is distributed over virtually the entire extent of the wafer 54 of FIG. 4. Wherever the power conductor 58 extends, there is -formed an underlying decoupling capacitor. Thus, whenever a connection is made between a bonding pad on a mounted chip and the power conductor 58, decoupling capacitance is connected directly to the pad at the same time. This is illustrated in FIG. 4 wherein solder balls 62 and 64 are shown interposed between pads on chip 66 and portions of the power conductor 58. (In practice, multiple such power connections are typically made between each chip and the conductor 58.) The only "leads" between the pads and the aforedescribed wafer-size capacitor are the solder balls themselves which inherently possess very little inductance. Also, the magnitude of the fringing fields of such a large-area capacitor is less than that of the fields associated with multiple discrete small- area capacitors of the type heretofore proposed. Hence, the depicted capacitor exhibits advantageous high-speed characteristics. Illustratively, lithographically defined interruptions in the power conductor 58 of FIG. 4 occur directly under the chip 66. One such type of interruption is made to achieve ground connections between pads on the chip 66 and the ground conductor 56. Thus, as indicated in FIG. 4, a portion of the dielectric layer 60 is removed from the top surface of the wafer 54 before the power conductor layer is deposited thereon. Subsequently, the power conductor layer is patterned to provide isolated metallic regions such as region 68. Since the conductive region 68 rests directly on the highly doped wafer 54 which in turn has the ground conductor 56 formed on the bottom surface thereof, the region 68 constitutes a top-surface ground portion in the depicted WSI assembly. Thus, solder ball 70 is effective to connect a mating pad on the chip 66 to ground in an effective relatively low-inductance manner. In practice, multiple such ground connections are made between each chip and the ground conductor 56. In one embodiment of the invention, each ground connection such as the region 68 of FIG. 4 is designed to have a relatively large-area top surface measuring about 1.25 mm on a side. As a result, the resistance measured between the region 68 and the ground conductor 56 is relatively low (in one example, only about 19 milliohms). Additionally, since, as mentioned above, each chip typically includes multiple such ground connections, the net overall resistance of multiple parallel ground paths through the wafer 54 to the bottom-surface conductor 56 is many times lower. In one illustrative example in which eight such ground connections are provided to each chip, the net resistance between the ground connections associated with each chip and the bottom-surface conductor 56 measures only about 2.4 milliohms. The actual doping level used in the wafer 54 is a function of such factors as the particular technology from which the chips of the WSI assembly is made, the required noise margins of the chip circuits, the specified operating power levels of the chip circuits, etc. It can be appreciated that it is feasible also simply to dope heavily only selected portions of the wafer to permit high conductivity between metallic, regions 68 and the bottom surface layer 56 in those instances where for some reasons it is desirable to limit the conductivity of portions of the wafer 54. Another type of lithographically defined interruption in the deposited power conductor layer is represented in FIG. 4. This type of interruption provides isolated metallic regions on the dielectric layer 60. These regions are the instrumentalities by which X- and Y- signal leads are connected to bonding pads on the mounted chips. One such region 72 is shown in FIG. 4. FIG. 4 also shows one conductor 74 of multiple X- signal leads and one conductor 76 of multiple Y-signal leads included in the illustrative WSI assembly. By way of example, these leads are lithographically defined in a conductive material such as aluminum. Each such lead is typically about 2 μ thick and 10-to-20 μm wide. A dielectric layer 78 (FIG. 4) is interposed between the X-signal leads including the conductor 74 and the conductive layer that includes the regions 58, 68 and 72. Further, another dielectric layer 80 isolates the X- signal metallization level from the Y-signal metallization level. Illustratively, each of these dielectric layers comprises a 5-to-20-μm-thick layer of polyimide material. Such a relatively thick low-dielectric-constant material ensures that the X- and Y-signal leads have relatively low values of parasitic capacitance associated therewith. Significantly, this enhances the high-speed performance characteristics of the unique depicted assembly. By way of example wherein two signal leads at different levels are designed to be connected together and then connected to a pad on the chip 66 of FIG. 4, the Y- signal conductor 76 is shown connected by a metallic via 82 to the X-signal conductor 74. In turn, the conductor 74 is connected to the region 72 by a conductive portion 84. In that way, the conductors 74 and 76 are electrically connected together and to the region 72. Further, solder ball 86 connects the region 72 to a specified one of the bonding pads included on the chip 66. A significant advantage of the illustrative FIG. 4 assembly is that the signal leads thereof are designed wherever possible to overlie uninterrupted portions of the large-area conductor 58 which therefore constitutes in effect a continuous a-c ground plane. As a result, signals propagated in these overlying leads are minimally distorted. FIG. 4 also schematically indicates that the depicted WSI assembly includes input/output terminals. One such illustrative terminal 87 overlying insulating layer 91 is shown disposed along one edge of the assembly. By means of such terminals, the WSI assembly can be connected to other such assemblies and/or to other equipment included in a system configuration. The structure schematically represented in FIG. 4 constitutes only a one-chip portion of an overall WSI assembly. In some applications, as many as 100 chips are mounted and interconnected in such an assembly. The chips in a particular assembly may comprise only bipolar devices, metal-oxide-semiconductor (MOS) devices, complementary-MOS devices, laser devices, integrated-optical devices, etc., or a mixture of some or all of such different devices. FIG. 5 illustrates an inventive assembly that includes three chips 88 through 90. Layer 92 schematically represents the three-level metallization (layers 76, 74 and 58-68-72) shown in FIG. 4. Wafer 94 is indicated by dots as being relatively highly doped, as specified above. Layer 96 represents the bottom-surface ground conductor. Lastly, the entire WSI assembly is depicted as being supported on a base member 98 which is part of a package that includes, for example, contacting and cooling capabilities. Numerous modifications and alternatives are possible. For example, other chip mounting techniques can be employed. Thus, the chips may be mounted face-up on a wafer and connections made between the chips and the wafer by standard wire-bonding or tape-automated-bonding techniques. Or the chips may be mounted in sloped-wall recesses formed in the wafer or may be fabricated as integral parts of the wafer itself. In these latter cases, the connections between the chips and the metallization pattern on the wafer may be lithographically formed. Additionally, in some cases it may be advantageous to employ the bottom-surface conductor of the assembly as a power plane and to utilize the large-area metallization on and overlying the top surface of the wafer as a ground plane. Other semiconductor materials can be used. Also, the conductor 56 can be formed directly on the top surface of the wafer. The remainder of the structure overlying such a top-surface conductor is the same as described above and shown in FIG. 4 with a dielectric layer 60 separating the top-surface layer 56 from layer 58. Such an alternative structure also provides a readily accessible large-area decoupling capacitor in a WSI assembly. Additionally, it is feasible to deposit a conductive layer over the opposite or top surface of each face-down-mounted chip to provide connection to the substrate portion of each chip, since it is often desirable to maintain such substrate at a specified potential. Further, various alternatives to the making of direct electrical connections between the chip bonding pads and patterned portions of the power conductor layer are possible. For example, the chips can be mounted in the assembly farther above the top surface of the wafer 54, in which case the chip bonding pads are directly connected to respective upper portions of the multilayer conductive pattern. These portions are above and insulated from the power conductor layer. Conductive vias or other structures are then utilized to connect these upper portions to respective portions of the power conductor layer. Additionally, other dielectric materials or combinations of dielectric materials can be used.

Claims: Claims 1. A wafer-scale-integrated assembly comprising a wafer (54) having integrated-circuit chips (66) mounted on or in a top surface of said wafer, each of said chips including conductive regions, characterized by a conductive pattern (58,68,72) overlying said surface of said wafer, said pattern including portions connected (via 62, 70, 86) to said regions and other portions (87, 58) constituting terminals of said assembly, a conductive layer (56) on the bottom surface of said wafer, and said wafer being sufficiently conductive to constitute an effective electrical connection between said conductive layer (56) and ones (68) of said conductive pattern portions. 2. An assembly as in claim 1 wherein said top surface contains thereon a dielectric layer (60) except under said one of said conductive pattern portions. 3. An assembly as in claim 1 wherein said conductive pattern includes spaced-apart relatively small- area portions (72) insulated from each other on said dielectric layer and a continuous relatively large-area portion (58) covering a major extent of said dielectric layer. 4. An assembly as in claim 3 wherein said large- area portion and said conductive layer comprise power and ground conductors of said assembly, and wherein said large- area portion, said dielectric layer and said wafer together with said conductive layer comprise, respectively, one plate, the dielectric and the other plate of a decoupling capacitor of said assembly. 5. An assembly as in claim 4 wherein said conductive pattern includes X-signal leads (74) and Y- signal leads (76) in spaced-apart levels insulated from each other.

Inventors: HERRERO VICTOR, SCHAPER LEONARD WILLIAM, HERRERO, VICTOR, SCHAPER, LEONARD, WILLIAM
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1985
Main classification: H01L23
IPC codes: H01L23