AMPLIFIER WITH RAIL-TO-RAIL INPUT CAPABILITY AND CONTROLLED TRANSCONDUCTANCE

Abstract: A differential amplifier operable between a pair of supply voltages that define a rail-to-rail supply range contains a pair of differential portions (20 and 22) that together provide representa­ tive signal amplification across the supply range, although neither differential portion individually does so. A current control (24) regulates operating currents (I N and Ip) for the differential portions in such a way that the amplifier transconductance can be controlled in a desired manner as the common-mode part (V CM ) of the amplifier input signal (V I+ and V I- ) varies across the supply range. The transconductance is typically controlled to be largely constant. A summing circuit (26) selectively combines internal currents (I A , I B , I C and I D ) from the differential portions to generate at least one output signal (I O+ and I O- ) representative of the input signal.

Description: This invention relates generally to differential amplifiers suitable for operational amplifiers made in semiconductor integrated circuit form and especially to differential amplifiers employing pairs of transistors to achieve rail-to-rail input capability. In particular this invention relates to an amplifier operable between first and second supply voltages which define a supply range consisting of (a) a first end range extending from the first supply voltage to a first specified voltage between the supply voltages, (b) a middle range extending from the first specified voltage to a second specified voltage between the first specified voltage and the second supply voltage, and (c) a second end range extending from the second specified voltage to the second supply voltage, the amplifier having: first differential means for amplifying a differential input signal by largely dividing a first operating current into first and second internal currents whose difference is representative of the input signal when its common-mode voltage varies across the middle and second ranges; second differential means for amplifying the input signal by largely dividing a second operating current into third and fourth internal currents whose difference is representative of the input signal when the common-mode voltage varies across the first and middle ranges; and summing means for selectively combining the internal currents to generate at least one output signal. Such an amplifier is known from the Japanese patent application no. 45706/84. It is often desirable that an operational amplifier ("op amp") utilize a low power supply voltage. This severely constrains the voltage range of the common-mode part of the differential input signal supplied to many prior art bipolar op amps, particularly those whose input stage is a differential amplifier. In many cases, the common-mode voltage V CM of the input signal cannot use the entire range of the power supply voltage. In the known amplifier the V CM range is extended to the full supply range by utilizing complementary pairs of input transistors. Fig. 1 shows the known amplifier. This amplifier has a differential input section containing complementary differential portions 10 and 12 which amplify the differential input signal defined by voltages V I+ and V I- . Voltage V I+ is V CM + ΔV, and voltage V I- is V CM - ΔV, where 2 ΔV is the differential part of the input signal. Current sources 14 and 16 respectively connected to points (or terminals) of low and high supply voltages V L and V H provide the supply current for the input section. The input section is connected to a summing circuit 18 containing transistors QA, QB, QC, and QD configured as shown in Fig. 1. Equal-valued resistors RA, RB, RC, and RD are also part of circuit 18. As described more fully in the foregoing patent application, circuit 18 is a modulated current mirror for combining signal currents from differential portions 10 and 12 to provide an output current I O . The range for the power supply voltage V PS -- i.e., V H -V L -- is divided into three ranges. A low range goes from V L up to slightly more than V L +V BE , where V BE is the absolute value of the standard base-to-emitter voltage of a bipolar transistor when it is just turned on A high range goes from V H down to slightly less than V H -V BE . With V PS being greater than 2V BE , a middle range extends between the two end ranges. Differential portion 10 contains NPN transistors Q1 and Q2 which amplify the input signal by dividing operating current provided from current source 14 on interconnected lines SA and SB into respective currents I A and I B transmitted on lines LA and LB. The difference between currents I A and I B is representative of the input signal when V CM is in the middle and high ranges where the operating current is at a constant supply level I L . As V CM drops into the low range, first one and then the other of transistors Q1 and Q2 turn off to shut down current source 14. Similarly, differential portion 12 has PNP transistors Q3 and Q4 which divide operating current provided from current source 16 on interconnected lines SC and SD into respective currents I C and I D transmitted on lines LC and LD. The difference between current I C and I D is representative of the input signal when V CM is in the low and middle ranges where the operating current for transistors Q3 and Q4 is at a constant supply level I H . They turn off to shut down current source 16 when V CM goes into the high range. Accordingly, portions 10 and 12 are both active in the middle range, but only one is active in each end range. A measure of the amplification capability of a differential amplifier is its transconductance G MA (i.e., the ratio of the incremental change in total current through the input section to input voltage change ΔV). Inasmuch as the individual transconductance of a bipolar transistor is approximately proportional to its collector current, G MA for Fig. 1 is approximately proportional to I A +I B +I C +I D . The total supply current transmitted by current sources 14 and 16 is the sum of the operating currents which, in turn, largely equals the sum of currents I A - I D . Since the current supply for the input section partly shuts down when V CM is in either end range, the total supply current is greater when V CM is in the middle range. The amplifier transconductance then varies in the same manner. While the rail-to-rail input capability of the foregoing amplifier is advantageous, the G MA variation as V CM moves across the V PS range is sometimes a disadvantage. The variation in transconductance makes it difficult to optimize the frequency compensation for the amplifier when used in an op amp with negative feedback. Signal distortion occurs when one of current sources 14 and 16 shuts downs It is therefore the object of the invention to provide a differential amplifier arranged in a relatively simple configuration that achieves rail-to-rail input capability without G MA varying greatly across the supply range. According to the invention, an amplifier of the type set forth in the preamble is characterized in that the amplifier further comprises control means for providing amplifier supply current to generate the operating currents, at least part of the amplifier supply current being diverted from the first differential means to the second differential means in case of the common-mode voltage being in at least the first end range, and at least part of the amplifier supply current being diverted from the second differential means to the first differential means in case of the common-mode voltage being in at least the second end range. According to the invention, an amplifier for amplifying a differential input signal has rail-to-rail input capability with a transconductance that can be controlled as the common-mode voltage of the input signal varies across the power supply range. When, for example, the differential portions are embodied in bipolar technology, the current control optimally maintains the sum of the operating currents largely constant as the common-mode voltage varies across the rail-to-rail range. This enables the amplifier transconductance to be largely constant. This facilitates optimization of the frequency response by enabling the loop gain to be largely constant when the amplifier is used with a negative feedback network and reduces signal distortion in negative feedback applications. The basic technique involves diverting at least part of the supply current away from the supply lines for one of the differential portions as the common-mode voltage goes into the end range where the input transistors in that differential portion are non-conductive. This is preferably done with one or more steering transistors differentially configured with respect to one or both pairs of input transistors. The supply lines for the other differential portion are then provided with current derived from the current diverted away. As a result, the portion of the current control that provides the supply current normally does not partially shut down. The configuration of the amplifier is quite simple. It typically uses just a few more transistors than the prior are device described above. Consequently, the present amplifier is especially suited for use as an op amp input stage in low power supply applications. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawing, in which Fig. 1 shows a circuit diagram of a prior art differential amplifier, Fig. 2 shows a block diagram of a differential amplifier in accordance with the invention, Figs. 3a, 4a and 5a show circuit diagrams of three different bipolar embodiments of part or all of the amplifier of Fig. 2, and Figs. 3b, 4b and 5b show respective asymptotic graphs of operating currents as a function of the common-mode voltage for these embodiments, Fig. 6 shows a circuit diagram of a preferred bipolar embodiment of the amplifier of Fig. 2, Fig. 7 shows a circuit diagram of a bipolar embodiment of part of the amplifier of Fig. 2 in which Darlington transistor pairs are employed, Fig. 8a shows a circuit diagram of a complementary metal-oxide semiconductor (CMOS) embodiment of part of the amplifier of Fig. 2, and Fig. 8b shows an asymtotic graph of operating currents as a function of the common-mode voltage for this embodiment. Like reference symbols are employed to identify the same or very similar item or items in the drawings and description of the preferred embodiments. Referring to the drawings, Fig. 2 shows a general differential amplifier having rail-to-rail input capability with controlled transconductance. This amplifier has a differential input section consisting of a pair of differential input portions 20 and 22 that commonly receive the differential input signal formed by voltages V I+ and V I- . A current control 24 responsive to one or both of control voltages V RN and V RP is connected between points for low and high supply voltages V L and V H . A summing circuit 26 connected between the V L and V H terminals provides one or more output current signals representative of the input signal. Differential portion 20 contains identical like-polarity input transistors Q1 and Q2, while differential portion 22 contains identical like-polarity input transistors Q3 and Q4. Although transistors Q1 - Q4 are shown as bipolar transistors, they may be field-effect transistors (FET's) of the insulated-gate or junction type. Transistors Q3 and Q4 are typically complementary to transistors Q1 and Q2, particularly if the amplifier is embodied in bipolar or CMOS technology. Transistors Q1 - Q4 may, however, all be of the same polarity in some circumstances. For example, transistors Q1 and Q2 could be depletion-mode FET's, while transistors Q3 and Q4 are enhancement-mode FET's. A transistor such as any of transistors Q1 - Q4 or the other transistors described below has a first flow electrode, a second flow electrode, and a control electrode for regulating current transmission between the flow electrodes. For a bipolar transistor its base, emitter, and collector are respectively the control, first, and second electrodes. These are the gate, source, and drain for an FET. Transistors Q1 - Q4 are all turned on when V CM is in a middle range extending from a specified voltage greater than V L to a specified voltage less than V H . Transistors Q1 and Q2 are also conductive when V CM is in a high range extending from the top of the middle range to V H . They are non-conductive when V CM is in part or all of a low range extending from the bottom of the middle range to V L . The reverse is true for transistors Q3 and Q4. They are turned on in the low range but are turned off in part or all of the high range. Responsive to the input signal differentially supplied to their control electrodes, transistors Q1 and Q2 jointly control current flow between supply and internal lines SA and LA and between supply and internal lines SB and LB. Lines SA and SB are connected together to carry an operating current I N for portion 20. It amplifies the input signal by largely dividing operating current I N into internal currents I A and I B which are respectively transmitted on lines LA and LB and whose difference is representative of the input signal when V CM is is the middle and high ranges. For the low range, current I N is substantially zero so that portion 20 provides no signal amplification. Responsive to the input signal differentially supplied to their control electrodes, transistors Q3 and Q4 jointly control current flow between supply and internal lines SC and LC and between supply and internal lines SD and LD. Lines SC and SD are similarly connected together to carry an operating current Ip for portion 22. It amplifies the input signal by largely dividing operating current Ip into internal currents I C and I D which are respectively transmitted on lines LC and LD and whose difference is representative of the input signal when V CM is in the low and middle ranges. For the high range, current Ip is substantially zero so that portion 22 provides no signal amplification. For purpose of illustration, the direction of current flow for currents I A and I B is indicated as being toward portion 20 in Fig. 2, whereas the flow direction for currents I C and I D is shown as being away from direction 22. Depending on the configuration of portion 20, the flow direction for currents I A and I B may, however, be opposite to that shown. In this case, the flow direction for current I N is also reversed from that shown. The same holds for currents I C , I D and Ip. Their flow directions with respect to portion 22 may all be reversed depending on its configuration. Summing circuit 26 receives the currents on internal lines LA-LD at respective nodes A, B, C and D and suitably combines these currents to generate one or more output currents. Complementary output currents I O+ and I O- may be provided if circuit 26 is a double-ended device as indicated in Fig. 2. Circuit 26 could also be a single-ended device (such as depicted in Fig. 1) that provides single output current I O . Current control 24 provides amplifier supply current that is utilized in generating operating currents I N and Ip for the differential input section. The supply current is substantially constant when V CM is in the rail-to-rail range. The portion of control 24 that provides the supply current normally does not partially shut down in any part of the V PS range. Current control 24 which is connected to portion 20 by way of lines SA and SB and to portion 22 by way of lines SC and SD controls the transconductance of the amplifier by regulating operating currents I N and Ip. When V CM is in at least one part of the V PS range, control 24 steers at least part of supply current through itself and provides currents I n and Ip at values depending on the steering of the supply current. In particular, control 24 operates by steering supply current away from one of portions 20 and 22 as V CM goes into the end range where the input transistors of that differential portion turn off and provides the other of portions 20 and 22 with current derived from the current steered away. This steering may be done with either or both of portions 20 and 22. The discussion below of particular embodiments of the amplifier of Fig. 2 further clarifies the steering mechanism. Fig. 3a shows an embodiment of Fig. 2 in which transistors Q1 and Q2 are NPN transistors whose bases receive the input signal, whose emitters are respectively connected to lines SA and SB to receive current I N , and whose collectors are respectively connected to lines LA and LB to provide currents I A and I B . Transistors Q3 and Q4 are PNP transistors whose bases receive the input signal, whose emitters are respectively connected to lines SC and SD to receive current Ip, and whose collectors are respectively connected to lines LC and LD to provide current I C and I D . Control 24 in Fig. 3a consists of current source 16 that provides the amplifier supply current at constant level I H , a current mirror 28, and a PNP steering transistor QP. Reference voltage V RP is supplied to the base of transistor QP. Its emitter is connected to a steering line LH connected in common with lines SC and SD to current source 16. This places transistor QP in a differential configuration with transistors Q3 and Q4. Mirror 28 contains identical NPN transistors Q5 and Q6 whose bases are connected to the Q5 collector which is connected through a steering line LN to the QP collector. The Q6 collector is connected to lines SA and SB. The emitters of transistors Q5 and Q6 are coupled through respective equal-valued resistors R1 and R2 to the V L terminal. Resistors R1 and R2 reduce sensitivity to noise. The current flow through transistor QP is in the wrong direction for providing current by way of lines SA and SB to transistors Q1 and Q2. Mirror 28 largely mirrors (duplicates) the current on line LN at the Q5 collector and provides the mirrored current at the Q6 collector in the right direction for transistors Q1 and Q2. Fig. 3b shows a graph helpful in understanding the operation of control 24 in Fig. 3a. Voltage V RP is at a selected value within the range extending from V L +V BE +V SM to V H- V BE- V SM where V SM is a small safety-margin voltage typically about 0.2 - 0.3 volt, V PS must be at least 2V BE +2V SM . V BE is about 0.6 - 0.8 volt. The middle range where transistors Q1 - Q4 are all conductive is an approximate 50-millivolt range centering on voltage V RP . This is the case when the QP emitter area equals the sum of the emitter areas of transistors Q3 and Q4. Letting 2V W (which equals 50 millivolts) be the width of the middle range, it extends from V RP -V W to V RP +V W . As the QP emitter-base voltage rises from V BE -V W to V BE +V W , transistor QP switches from substantially fully off to fully on, while transistors Q3 and Q4 do the opposite. In the following discussion for this embodiment as well as the similar discussions below of other embodiments, base currents are ignored in comparison to collector or emitter currents. To the extent that base currents are involved, indicated equalities mean that items indicated as being equal are only largely equal. In addition, the various graphs only show asymptotes for the variation of currents I N and Ip. The rounding that occurs at the ends of the middle ranges is generally not shown in these graphs. In the low V CM range where transistors Q3 and Q4 are turned on, transistor QP is off since its emitter-base voltage is less than V BE -V W . Current source 16 supplies current Ip to portion 22 at level I H . The sum of currents I C and I D is thereby I H . Transistors Q5 and Q6 are off because transistor QP is off. Since current I N is thereby zero, transistors Q1 and Q2 are off. As V CM moves up through the middle range, transistor QP turns on and progressively becomes more conductive. It steers a progressively increasing part of current I H away from transistors Q3 and Q4, causing them to become progressively less conductive as current Ip progressively decreases toward zero. The I H part steered away from portion 22 is transmitted through transistor QP to transistor Q5 so as to turn on transistors Q5 and Q6. Mirror 28 duplicates this I H part and provides the duplicated current portion by way of lines SA and SB to transistors Q1 and Q2 which progressively turn on. Current I N which equals the duplicated I H part progressively increases towards level I H . When V CM is in the high range, all of current I H is steered away from transistors Q3 and Q4 so that they are off and current Ip is zero, Transistor QP is fully on and steers all of current I H to mirror 28. It provides current I N to portion 20 at a value equal to I H . The sum of currents I A and I B thereby equals I H . As shown m Fig. 3b, the sum of currents I A to I D is Ip + I N which equals the constant supply current I H across the entire rail-to-rail range for V CM . The transconductance G MA of the amplifier of Fig. 3a is approximately (I A +I B +I C +I D )/V T which equals I H /V T . V T is kT/q where T is temperature, k is Boltzmann's constant, and q is the electronic charge. As a result, G MA is largely constant across the V PS range. Summing circuit 26 in Fig. 3a contains a modulated current mirror 30 consisting of transistors Q7, Q8, Q9, and Q10, an identical modulated current mirror 32 consisting of transistors Q11, Q12, Q13, and Q14, and equal-valued resistors RA - RD and R3, R4, R5, and R6 connected as shown to provide complementary currents I O+ and I O- . The bases of transistors Q7, Q8, Q11 and Q12 receive bias voltage V BP . Mirrors 30 and 32 operate in the manner described in U.S. Patent Application Ser. No. 525,181, except that transistors Q8, Q9, Q12, and Q13 do not receive signal inputs. When the differential portion of the input signal changes from zero to 2 ΔV, currents I A - I D change by respective increments ΔI N ,- ΔI N ,- ΔIp, and ΔIp which are all non-zero only in the middle range. However, G MA is 2( ΔI N + ΔIp)/ΔV which approximately equals I H /V T across the entire supply range. Accordingly, currents I O+ and I O- which respectively equal ΔI N + ΔIp and -ΔI N - ΔIp are not a function of the location of V CM in the V PS range. Fig. 4a depicts a partial embodiment of the present amplifier in which portions 20 and 22 are configured the same as in Fig. 3a. The principal difference is in current control 24 where current sources 14 and 16 provide supply currents at constant levels I L and I H . The amplifier supply current for the differential input section is the sum of I L and I H . A summing circuit (not shown in Fig. 4a) is connected to nodes A-D of the input section to generate the output current(s). Control 24 in Fig. 4a contains transistor QP and mirror 28 configured the same as in Fig. 3a except that anti-noise resistors R1 and R2 are omitted in Fig. 4a. Control 24 further includes a current mirror 34 and an NPN steering transistor QN. Reference voltage V RN is supplied to the base of transistor QN. Its emitter is connected to steering line LL connected in common with lines SA and SB to current source 14. This places transistor QN in a differential configuration with transistors Q1 and Q2. Mirror 34 contains identical PNP transistors Q15 and Q16 whose bases are connected to the Q15 collector which is connected through a steering line LP to the QN collector. The Q16 collector is connected to lines SC and SD. The emitters of transistors Q15 and Q16 are tied to the V H terminal. Fig. 4b shows a graph that facilitates understanding the operation of control 24 in Fig. 4a. Voltages V RP and V RN are both at selected values within the range extending from V L +V BE +V SM to V H -V BE -V sm . V RN is less than V RP -2V W . V PS is again at least 2V BE +2V SM . The middle range extends from V RN -V W up to V RP +V W . As the QN base-emitter voltage drops from V BE +V W to V BE -V W (at the lower portion of the middle range), transistor Qn switches from fully on to substantially fully off while transistors Q1 and Q2 do the opposite. As the QP emitter-base voltage rises from V BE -V W to V BE +V W (at the upper portion of the middle range), transistor QP switches from substantially fully off to fully on while transistors Q3 and Q4 do the reverse. In the low V CM range, transistors Q1 and Q2 are off so that current I N is zero Transistor QN is on and steers current I L away from portion 20 to transistor Q15 so as to turn on transistors Q15 and Q16. Mirror 34 duplicates current I L at the Q15 collector and provides the duplicated current from the Q16 collector to portion 22. Transistors Q5 and Q6 are off since transistor QP is off. Current source 16 then provides current I H directly to portion 22. As a result, current Ip equals I L +I H . As V CM moves up through the lower middle-range portion extending from V RN -V W to V RN +V W , transistor QN becomes progressively less conductive and steers a progressively decreasing part of current I L away from transistors Q1 and Q2. Mirror 34 duplicates the I L part steered away from portion 20 and supplies the duplicated current to portion 22 so that current I P progressively decreases toward I H . Meanwhile, current source 14 provides a progressively increasing part of current I L to transistors Q1 and Q2, causing them to turn on and become progressively more conductive. Current I N progressively increases toward I L . In the central middle-range portion extending from V RN +V W to V RP -V W , transistors QN and QP are both off. Mirrors 28 and 34 are therefore both off. No steering occurs. Current source 14 provides current I N to portion 20 at level I L . Current source 16 provides current Ip to portion 22 at level I H . In the upper middle-range portion extending from V RP -V W to V RP +V W and in the high V CM range, transistor QN and mirror 28 operate on current I H in the same way that transistor QP and mirror 34 respectively operate on current I L in the lower middle-range portion and in the low range. In particular, current Ip decreases progressively toward zero and then stays there as V CM rises through the upper middle-range portion and the high range. Current I N increases progressively towards I L +I H and then stays there. The sum of currents I A to I D is constant at level I L +I H . The transconductance for Fig. 4 is therefore constant when V CM varies across the rail-to-rail range. Fig. 5a shows an embodiment of the present amplifier in which portion 20 is configured the same as in Fig. 4a, but portion 22 is configured differently. Portion 22 in Fig. 5a contains a level shifter that translates the input signal into a shifted differential signal whose common-mode voltage is at least 1V BE closer to V H . The level shifter contains PNP transistors Q3 and Q4 whose bases differentially receive the input signal and whose collectors are connected to the V L supply point. The emitters of transistors Q3 and Q4 are connected to the lower ends of respective resistors R7 and R8 whose upper ends provide the shifted differential signal and are respectively coupled through constant current sources 36 and 38 to the V H supply point. The shifted signal is differentially supplied to the bases of identical NPN transistors Q17 and Q18. Their collectors are respectively connected to lines LC and LD to provide currents I C and I D , and their emitters are respectively connected to lines SC and SD to carry current Ip. The direction of current flow in lines LA and LB relative to portion 20 is the same as the direction of current flow in lines LC and LD relative to portion 22. Accordingly, a double-ended summing circuit is achieved by simply connecting lines LA and LC together to provide output I O+ and by connecting lines LB and LD together to provide output I O- . Control 24 in Fig. 5a consists of current source 14 and NPN steering transistor QN whose base receives voltage V RN . The QN collector is connected through line LP to lines SC and SD. The QN emitter is connected to line LL connected commonly with lines SA and SB to current source 14 so that transistor QN is in a differential configuration with transistors Q1 and Q2. Fig. 5b shows a graph helpful in understanding the operation of control 24 in Fig. 5a. Voltage V RN is at a selected value within the range extending from V L +V BE + V SM to V H -V BE -V SM . In the low range where transistors Q1 and Q2 are off, transistor QN is on along with transistors Q3 and Q4. The shifted signal is provided to transistors Q17 and Q18 which are also on Transistor QN diverts current I L from current source 14 away from portion 20 to portion 22 to generate current Ip at level I L . As V CM moves through the middle range extending from V RN -V W to V RN +V W , transistor QN becomes progressively less conductive and does progressively less current steering, while transistors Q1 and Q2 turn on and become progressively more conductive. Current I N progressively increases from zero to I L . Current Ip does the reverse. In the high range, transistor QN is off so that transistors Q17 and Q18 are off. Current source 14 supplies current I N to portion 20 at level I L . If V CM rises high enough, transistors Q3 and Q4 turn off. This, however, does not affect operation in the high range. The sum of currents I A - I D is constant at level I L . As a result, G MA for Fig. 5a is largely constant. Fig. 6 illustrates a preferred embodiment of the amplifier of Fig. 2 in which portions 20 and 22 and control 24 are configured as in Fig. 3a except that the input signal is supplied through resistors R9 and R10 to portions 20 and 22. Current source 16 consists of a PNP transistor QS and a resistor RS connected as shown. Summing circuit 26 in Fig. 6 contains PNP transistors QA and QB and NPN transistors QC and QD connected as shown in Fig. 1 except that the bases of transistors QC and QD receive a bias voltage V BN . This enables circuit 26 to provide output I O+ from the QB and QD collectors and output I O- from the QA and QC collectors. Circuit 26 in Fig. 6 operates as follows. As seen from line LA, resistor RA is a high impedance whereas transistor QA is a low impedance. The same holds for lines LB - LD with respect to resistors RB - RD and transistors QB - QD. When incremental currents ΔI N , - ΔI N , - ΔIp, and ΔI p occur respectively on lines LA - LD, opposite incremental currents respectively flow through transistors QA - QD. As a result, currents I O+ and I O- respectively equal ΔI N + ΔIp and - ΔI N - ΔIp. Since G MA which equals 2(ΔI N + ΔIp)/ΔV is constant across the rail-to-rail range, currents I O+ and I O- are largely independent of the location of V CM in the V PS range. A set of Schottky diodes D1, D2, D3 and D4 in combination with resistors R9 and R10 prevents the polarities of outputs I O+ and I O- from inverting when V CM drops below V L or rises above V H . Typically, this protection occurs in ranges extending about 10 volts below V L and 10 volts above V H . Diodes D1 and D2 are cross coupled as shown between transistors Q3 and Q4. Diodes D3 and D4 are connected between current source 16 and respective resistors R9 and R10. A pair of PN diodes D5 and D6 in combination with resistors R9 and R10 prevent large Zener currents from detrimentally affecting transistors Q1 - Q4 when the differential part (2 ΔV) of the input signal becomes too large. Diodes D5 and D6 are connected in parallel in opposing directions between resistors R9 and R10. Each of diodes D5 and D6 is preferably an NPN transistor having its base connected to its collector. In Fig. 6, voltages V H and V L are preferably greater than 0.9 volt and less than -0.9 volt. Voltage V RP or V BN is 0.8 volt above V L , and voltage V BP is 0.8 volt below V H . Resistors R5/R6, R9/R10, RA/RB/RC/RD and RS are respectively 1,000, 3,000, 50,000 and 50,000 ohms. In portions 20 and 22, as for example, embodied in Figs. 3a - 5a or 6, each pair of corresponding transistors such as transistors Q1 and Q2 may be replaced with a pair of groups of transistors arranged in identical voltage following configurations. Such a bipolar group typically consists of a lead transistor whose emitter is coupled directly or through one or more other transistors to the base of a trailing transistor. The input signal to the group is supplied to the base of the leading transistor to control current flow between lines connected to the emitter and collector of the trailing transistor. If a pair of corresponding transistors in portion 20 or 22 is in a differential configuration with a steering transistor in control 24, that transistor may also be replaced with a group of transistors arranged in a corresponding voltage following configuration. Fig. 7 illustrates how this replacement can be done in the embodiment of Fig. 5a. As indicated in Fig. 7, transistor Q1 is replaced with a Darlington transistor pair in which the emitter of transistor Q1 is connected to the base of an NPN transistor Q21 whose emitter and collector are respectively connected to lines SA and LA. Voltage V I+ is still provided to the base of transistor Q1 but its collector is tied to the V H terminal. Transistor Q2 is replaced in the same manner with a Darlington pair consisting of transistor Q2 and an NPN transistor Q22 which is identical to transistor Q21. Transistors Q3, Q4, Q17, and Q18 are similarly replaced with Darlington pairs respectively consisting of transistor Q3 and a PNP transistor Q23, transistor Q4 and a PNP transistor Q24 identical to transistor Q23, transistor Q17 and an NPN transistor Q27, and transistor Q18 and an NPN transistor Q28 identical to transistor Q27. Since transistors Q1 and Q2 in Fig. 5a are in a differential configuration with transistor QN, it is normally replaced in the same manner with a Darlington pair consisting of transistor QN and an NPN transistor QN'. Because Darlingtons are used in portions 20 and 22 in Fig. 7, V PS must be at least 4V BE +2V SM . Voltage V RN is at a selected value within the range extending from V L +2V BE +V SM to V H -2V BE -V SM . Alternatively, voltage V RN could be reduced 1V BE instead of replacing transistor QN with a Darlington pair. Aside from the foregoing differences, the amplifier of Fig. 7 operates the same as described above for the amplifier of Fig. 5a. The present amplifier may be embodied partly or wholly with FET's, Fig. 8a depicts a partial embodiment similar to that of Fig. 4a but using CMOS technology. All the transistors in Fig. 8a are preferably enhancement-mode MOS FET's, Each N-channel FET is indicated by an arrow on its source pointing away from the FET. Each P-channel FET is indicated by an arrow on its source pointing toward the FET. The input section in Fig. 8a contains portions 20 and 22 interconnected with control 24 in the same way as the corresponding items are interconnected in Fig. 4a. Mirror 28 of Fig. 4a is replaced with a reversing circuit 42 in which a resistor RN is connected between the Q5 source and the V L terminal. Circuit 42 provides the Q6 drain with current of greater magnitude than, but opposite flow direction to, the current through the Q5 drain. Similarly, mirror 34 is replaced with a reversing circuit 44 in which a resistor RP is connected between the Q15 source and the V H supply point. Circuit 44 provides the Q16 drain with current of greater magnitude than, but opposite flow direction to, the current through the Q15 drain. The current amplifications in circuit 42 and 44 depend on the values of resistors RN and RP. Control 24 then consists of current sources 14 and 16, transistors QN and QP, and circuits 42 and 44. Fig. 8b shows a graph that facilitates understanding the operation of control 24 in Fig. 8a. The operation is generally the same as that of Fig. 4a. The V CM ranges are qualitatively the same. The width 2V W of the lower and upper middle range portions depends on the types of FET's used. The steering in the input section of Fig. 8a is the same as that in Fig. 4a except for the current amplifications provided by circuits 42 and 44. In the central portion of the middle range, the sum of operating currents Ip and I N equals I L +I H . Because of the current amplification at the Q16 drain, the sum of currents Ip and I N progressively increases as V CM decreases from V RN +V W to V L . Likewise, the current amplification at the Q16 drain causes the sum of currents Ip and I N to progressively increase as V CM increases from V RP +V W to V H . Consequently, the sum of currents I A - I D is greater when V CM is at V L or V H than when V CM is in the middle of the supply range. The transconductance for a MOS FET is approximately proportional to the square root of its drain current. If circuits 42 and 44 were simply current mirrors that provided no current amplification, G MA would decrease as V CM moves from the central portion of the middle range out to V L or V H . The current amplification provided at the Q6 and Q16 drains increases G MA in the parts of the V PS range outside the central portion of the middle range. The G MA variation as V CM moves across the V PS range can be controlled upward by adjusting the amplifications of circuits 42 and 44. Suitable choice for their amplifications makes the amplifier transconductance relatively constant. As an example, G MA is largely constant if the amplifications of circuits 42 and 44 increase from 1 when they are just turned on to about 3 when they are fully conductive. Furthermore, one or both of circuits 42 and 44 can be configured to give current reduction rather than amplification. G MA would then decrease even more as V CM moves outward from the central portion of the middle range. Such a G MA variation might be desirable in some applications. The foregoing comments concerning transconductance regulation apply to other FET embodiments of the present invention as well as to bipolar embodiments. Within certain limits, connecting a suitable current-reversing circuit between line LN and lines SA and SB if current source 16 is used and/or connecting a suitable current-reversing circuit between line LP and lines SC and SD if current source 14 is used allow G MA to be regulated in a desired manner. Methods for manufacturing the various elements of the present amplifier are well known in the semiconductor art. The amplifier is preferably fabricated as part of a monolithic integrated circuit using PN-junction isolation to separate active regions in a semiconductor wafer. While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, semiconductor elements of opposite polarity to those described above may be employed to accomplish the same results Proper signal amplification typically occurs in the present amplifier when V CM extends somewhat outside the power supply range. Each input transistor pair can be replaced with four transistors arranged in a quad configuration to reduce the input offset voltage.

Claims: An amplifier operable between first (V L ) and second (V H ) supply voltages which define a supply range consisting of (a) a first end range extending from the first supply voltage (V L ) to a first specified voltage between the supply voltages, (b) a middle range extending from the first specified voltage to a second specified voltage between the first specified voltage and the second supply voltage (V H ), and (c) a second end range extending from the second specified voltage to the second supply voltage (V H ), the amplifier comprising first differential means (20) for amplifying a differential input signal (V I+ , V I- ) by largely dividing a first operating current (I N ) into first and second internal currents (I A , I B ) whose difference is representative of the differential input signal when its common-mode voltage varies across the middle and second end ranges, second differential means (22) for amplifying the differential input signal by largely dividing a second operating current (Ip) into third and fourth internal currents (I C , I D ) whose difference is representative of the differential input signal when its common-mode voltage varies across the first end and middle ranges, and summing means (26) for selectively combining the internal currents to generate at least one output signal (I O ), characterized in that the amplifier further comprises control means (24) for provided amplifier supply current to generate the operating currents (I N , Ip), at least part of the amplifier supply current being diverted from the first differential means (20) to the second differential means (22) in case of the common-mode voltage being in at least the first end range, and at least part of the amplifier supply current being diverted from the second differential means (22) to the first differential means (20) in case of the common-mode voltage being in at least the second end range. An amplifier as in Claim 1 characterized in that the supply current is largely constant as the common-mode voltage varies across the supply range. An amplifier as in Claim 2, characterized in that the control means maintains the sum of the operating currents largely constant as the common-mode voltage varies across the supply range. An amplifier as in Claim 1, 2 or 3, characterized in that each differential means (20, 22) has a pair of input transistors (Q1, Q2; Q3, Q4) differentially responsive to the differential input signal, the input transistors (Q1, Q2) in the first differential means (20) are substantially off when the common-mode voltage is in at least part of the first end range, and the input transistors (Q3, Q4) in the second differential means (22) are substantially off when the common-mode voltage is in at least part of the second end range, and in that the control means (24) (a) at least partially provides the operating current for at least one specified one of the differential means from the supply current, (b) diverts at least part of the supply current away from each specified differential means as the common-mode voltage goes into the end range where the input transistors in that differential means turn substantially off, and (c) provides at least part of the operating current for the other differential means at a level derived from the current so diverted. An amplifier as in Claim 1, 2, 3 or 4, characterized in that the first differential means has first and second like-polarity input transistor (Q1, Q2) having respective control electrodes differentially responsive to the differential input signal for jointly controlling current flow (a) between a first supply line (SA) and a first internal line (LA) that provides the first internal current (I A ) and (b) between a second supply line (SB) and a second internal line (LB) that provides the second internal current (I B ), the first and second supply lines coupled together for carrying the first operating current (I N ) which is substantially zero when the common-mode voltage is in at least part of the first end range, and the second differential means has third and fourth like-polarity input transistors (Q3, Q4) having respective control electrodes differentially responsive to the differential input signal for jointly controlling current flow (c) between a third supply line (SC) and third internal line (LC) that provides the third internal current (I C ) and (d) between a fourth supply line (SD) and a fourth internal line (LD) that provides the fourth internal current (I D ), the third and fourth supply lines coupled together for carrying the second operating current (Ip) which is substantially zero when the common-mode voltage is in at least part of the second end range, the flow direction of the first operating current (I N ) relative to the first differential means is opposite to the flow direction of the second operating current (Ip) relative to the second differential means and in that the control means comprises a current source (16), coupled to a supply point for the second supply voltage (V H ), for providing the supply current, steering means in which a steering transistor (QP) of like polarity to the third and fourth transistors has a control electrode for receiving a reference voltage (V RP ) to control current flow between a pair of steering lines (LH, LN) which one (LH) is coupled in common with the third and fourth supply lines (SC, SD) to the current source (16), and reversing means (Q5, Q6) for providing an electrode thereof coupled to the first and second supply lines (SA, SB) with current dependent on, but of opposite flow direction to, current through another electrode thereof coupled to the other steering line (LN). An amplifier as in Claim 5, characterized in that the currents through the electrodes of the reversing means are of largely equal magnitude, the sum of the operating currents being largely constant as the common-mode voltage varies across the supply range. An amplifier as in Claim 5 or 6, characterized by means (D5, D6) for preventing large Zener currents from damaging the input transistors. An amplifier as in Claim 5, 6 or 7, characterized by means (D1-D4) for preventing polarity inversion of each output signal when the common-mode signal is within specified limits outside the supply range. An amplifier as in Claim 1, 2, 3 or 4, characterized in that the first differential means has first and second like-polarity input transistors having respective control electrodes differentially responsive to the differential input signal for jointly controlling current flow (a) between a first supply line and a first internal line that provides the first internal current and (b) between a second supply line and a second internal line that provides the second internal current, the first and second supply lines coupled together for carrying the first operating current which is substantially zero when the common-mode voltage is in at least part of the first end range, and the second differential means has third and fourth like-polarity input transistors having respective control electrodes differentially responsive to the differential input signal for jointly controlling current flow (c) between a third supply line and a third internal line that provides the third internal current and (d) between a fourth supply line and a fourth internal line that provides the fourth internal current, the third and fourth supply lines coupled together for carrying the second operating current which is substantially zero when the common-mode voltage is in at least part of the second end range, in that the flow direction of the first operating current relative to the first differential means is opposite to the flow direction of the second operating current relative to the second differential means and in that the control means comprises first and second current sources (14, 16), respectively coupled to supply points for the first and second supply voltages, for respectively providing first and second supply voltages (V L , V H ), for respectively providing first (I L ) and second (I H ) supply currents whose sum is substantially the amplifier supply current, first steering means (QN) in which a steering transistor of like polarity to the first and second transistors has a control electrode for receiving a first reference voltage (V RN ) to control current flow between a pair of steering lines (LL, LP) of which one (LL) is coupled in common with the first and second supply lines (SA, SB) to the first current source (14), first reversing means (Q15, Q16) for providing an electrode thereof coupled to the third and fourth supply lines (SC, SD) with current dependent on, but of opposite flow direction to, current through another electrode thereof coupled to the other steering line (LP) of the first steering means, second steering means (QP) in which a steering transistor of like polarity to the third and fourth transistors has a control electrode for receiving a second reference voltage (QRP) to control current flow between a pair of steering lines (LN, LH) of which one (LH) is coupled in common with the third and fourth supply lines (SC, SD) the second current source (16), and second reversing means (Q5, Q6) for providing an electrode thereof coupled to the first and second supply lines (SA, SB) with current dependent on, but of opposite flow direction to, current through another electrode thereof coupled to the other steering line (LN) of the second steering means. An amplifier as in Claim 9, characterized in that the currents through the electrodes of the first reversing means are of largely equal magnitude, and the currents through the electrodes of the second reversing means are of largely equal magnitude, the sum of the operating currents being largely constant as the common-mode voltage varies across the supply range. An amplifier as in Claim 1, 2, 3 or 4, characterrized in that the first differential means has first and second like-polarity input transistors having respective control electrodes differentially responsive to the differential input signal for jointly controlling current flow (a) between a first supply line and a first internal line that provides the first internal current and (b) between a second supply line and a second internal line that provides the second internal current, the first and second supply lines coupled together for carrying the first operating current which is substantially zero when the common-mode voltage is in at least part of the first end range, and the second differential means has third and fourth like-polarity input transistors having respective control electrodes differentially responsive to the differential input signal for jointly controlling current flow (c) between a third supply line and a third internal line that provides the third internal current and (d) between a fourth supply line and a fourth internal line that provides the fourth internal current, the third and fourth supply lines coupled together for carrying the second operating current which is aubstantially zero when the common-mode voltage is in at least part of the second end range, in that the flow direction of the first operating current relative to the first differential means is the same as the flow direction of the second operating current relative to the second differential means and, in that the control means comprises a current source (14), coupled to a supply point for the first supply voltage (V L ), for providing the supply current, and a steering transistor (QN) having a control electrode for receiving a reference voltage to control current flow between a pair of steering lines (LP, LL) of which one is coupled in common with the first and second supply lines (SA, SB) to the current source and the other is coupled to the third and fourth supply lines (SC, SD). An amplifier as in Claim 11, characterized in that the second differential means (22) comprises shifting means (Q3, Q4) for translating the differential input signal into a shifted differential signal whose common-mode voltage is closer than the common-mode voltage to the second supply voltage, and fifth and sixth like-polarity transistors (Q17, Q18) having respective control electrodes differentially responsive to the shifted signal, respective first flow electrodes coupled respectively to the third and fourth supply lines (SC, SD), and respective second flow electrodes coupled respectively to the third and fourth internal lines (LC, LD). An amplifier as in Claim 1, characterized in that the transconductance of the amplifier is largely constant as the common-mode voltage varies across the supply range.

Inventors: HUIJSING, JOHAN HENDRIK, VAN DE PLASSCHE, RUDY JOHAN
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1985
Main classification: H03F3
IPC codes: H03F3