STATIC RANDOM-ACCESS MEMORY DEVICE

Abstract: A static random-access memory device is disclosed which employs MESFETs formed on a gallium arsenide substrate. The memory device includes a plurality of memory cells C₁₁-Cmn interconnected by word lines W₁ - W m and bit lines R₁₁-Rn₁, R₁₂-Rn₂. Each memory cell C₂₂ includes a flip-flop 14 and a pair of transfer gates connected between the flip-flop 14 and a pair of bit lines R₂₁, R₂₂. The transfer gates are formed by Schottky barrier gate field-effect transistors (MESFETs) 17, 18 having their gates connected to word line W₂. Schottky barrier gate diodes D₁, D₃ are connected in a forward bias direction between ground potential and the word lines W₂ to clamp the date voltages to the MESFETs 17, 18 forming the transfer gates and to suppress current flow form the gates toward the sources or drains of the MESFETs 17, 18 to thereby prevent destruction of data stored in the memory cells and improve read-out reliability. Additional Schottky barrier gate diodes D₂ are connected in a forward bias direction between ground potential and drive line B₂ for driving the gates of MESFETs 35, 36 forming switching circuit 3 for selecting the bit lines R₂₁, R₂₂ connected to the transfer gates. These additional diodes D₂ serve the same purpose as the diodes D₁, D₃ con­ nected to the word lines W₂.

Description: STATIC RANDOM-ACCESS MEMORY DEVICE The present invention relates to a static random-access memory device formed by Schottky barrier gate field-effect transistors on a gallium arsenide substrate. Schottky barrier gate field-effect transistors (hereinafter referred to as "MESFET") on a gallium arsenide substrate are known for their high speed operation. Accordingly, a high speed memory device, such as a static random-access memory device, can be fabricated by integrating a number of MESFETs on a gallium arsenide substrate. A static random-access memory device formed by such MESFETs has a matrix of memory cells, each memory cell including a flip-flop and a pair of transfer gases. The flip-flops include a pair of cross-coupled normally-off switching MESFETs connected to a pair of normally-on load MESFETs. The transfer gates are normally-off MESFETs which are connected to input/output nodes of the flip-flop. The gates of the MESFETs which constitute the transfer gates are coupled to word lines and the source or drains of these MESFETs are connected to bit lines. The word lines receive control signals from an X-addressing circuit constituted by MESFETs. The bit lines receive date through a MESFET switching circuit having gates connected to receive control signals from a Y-addressing circuit. The memory cells are read through the bit lines by a sense amplifier. In the above high speed memory device, the memory cells, X- and Y-addressing circuits and the sense amplifier are usually energised by a common power supply. llowever, it has beeh found that, when the voltage of the Comnron power supply is elected to be about 2 volts, the data stored in the memory cells can be easily destroyed by external disturbances such as power supply voltage changes, or this data may not be readable by the sense amplifier. Accordingly, the present invention seeks to provide a static ramdom-accesss memory device formed on a gallium arsenide substrate which is stable and has high speed operating capability. The present invention also seeks to provide a static ramdon-access Memory device which is not susceptible to the destruction of data stored in the memory cells. The present invention also seeks to provide a static random-access memory device in which the data stored in the memory cells can be easily and reliably read out by a sense amplifier. Accordingly the applicants have conducted studies to determine the possible causes of data destruction and data read-out failure in static random-access memory devices (SRAM) constituted by MESFETs formed on a gallium arsenide substrate. It has been found that, when. a control signal of a positive voltage higher than the forward breakdown voltage of a Schottky barrier gate, for example 0.8 V, is applied to each of the gates of the MESFETs constituting the transfer gates in the memory cells and/or the MESFETs constituting the switching circuit connected to the bit lines, a current flows from the gates of the MESFETs into their sources or drains to change the potential at either the input/output nodes of the flip-flop of eaçh memory cell or the bit lines. However the applicants have determined that this control signal voltage can be eliminated by connecting a Schottky barrier gate diode in a for@@@d bias direction between a reference potential and at least one of the word lines to clamp the gate voltage of the MESFET constituting the transfer gate. Alternatively, or in addition to the above connection of a Schottky barrier gate diode to one of the word lines, a Schottky barrier gate diode can be connected between the reference potential and at least one of the drive lines connected to the gates of the MESFETs forming the switching circuit for actuating the bit lines. More specifically, according to the present invention, there is provided a static ramdon-access memory device which is formed on a gallium arsenide substrate comprising: (a) a plurality of memory cells connected in a matrix by bit lines and word lines, each memory cell including a flip-flop having a pair of input/output nodes and a pair of cross-coupled normally-off Schottky barrier gate field-effect transistors connected to said input/output nodes, said memory cell further including a pair of transfer gates formed by normally-off Schottky barrier gate field-effect transistors having their gates connected to said word lines and their sources and drains connected between said input/output nodes of said flip-flop and said bit lines; (b) first addressing circuit means for supplying control signals to said transfer gates through said word lines; ; (c) data input means for writing data into said memory cells through said bit lines; (d) data output means for reading data out of said memory cells through said bit lines; (e) switching means formed by normally-off c#oLtky b;-r.rier gate field--effect transislors for selecting said bit lines; and (f) second addressing circuit means for supplying control signals through drive lines to said switching means; characterised in that the memory device further comprises (g) a Schottky barrier gate diode connected in a forward bias direction between at least one of said word lines and a reference potential to clamp the gate voltage on the gates of said Schottky barrier gate field-effect transistors forming said transfer gates. In the memory device of the present invention, current flow from the word lines into the sources or drains of the MESFETs of the transfer gates is prevented. Current flow is also prevented from the drive lines into the sources or drains of the MESFETs of the switching circuits for selecting the bit lines. It is noted that, since it is necessary to turn on the MESFETs of the transfer gates and the switching circuits, the forward breakdown voltage of the Schottky barrier gate diodes must be equal to or higher than the threshold voltage of the MESFETs. Also, to sufficiently suppress current flow, it is preferable that the forward breakdown voltage of the Schottky barrier gate-diodes be substantially equal to the forward breakdown voltage of the Schottky barrier gate of the MESFETs of the transfer gates or the switching circuits. Furthermore, in order to reduce the number of fabricating steps and to increase production yield, it is preferable that the diodes and the Schottky barrier gates of the MESFETs be fabricated in the same processing steps. The Schottky barrier gate diodes are preferably connected to the word lines or drive lines at a location as close to the first or second addressing circuits as possible. This location is preferable because the output voltage from the first or second addressing circuits drops along the length of the word lines or drive lines, which could result in data destruction and data read-out failure in some of the memory cells depending on the location and number of diodes. This output voltage is applied to the diodes to decrease the current bypass effect of the diode when the diodes are located in the memory cell array. The diodes used in the present invention differ from well known protecting diodes for preventing breakdown of MESFETs due to an over-voltage. While the present invention employs Schottky barrier gate diodes, protecting diodes normally comprise P-N junction diodes having excellent surge-resistant capability. In contrast to the normal arrangement of protecting diodes, the diodes of the present invention are located within the static RAM, whereas protecting diodes are normally located in the vicinity of a bonding pad on a peripheral portion of the substrate in order to protect transistors on the substrate. Some embodiments of the present invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a block diagram showing a basic construction of a static, random-access memory device according to an embodiment of the present invention; Figure 2 is a circuit diagram of a typical memory cell and the circuit for driving the memory cell in the static random-access memory device shown in Figure 1; Figures 3(a) to 3(c) are enlarged cross-sectional views of two transistors and a diode forming the cirucit arrangement of Figure 2; Figures 4(a) to 4(c) are enlarged cross-sectional views of additional transistors and a diode forming the circuit arrangement of Figure 2; and Figure 5 is a circuit diagram of a modification of a portion of the circuit arrangement illustrated in Figure 2. In Figure 1, a matrix of memory cells Cij (i = 1 to m; j = 1 to n, m and n being positive integers) is disposed on semi-insulating substrate 1 of gallium arsenide (GaAs). Each memory cell Cij is connected to word line Wi and a pair of bit lines Rji, Rj2. Word lines Wl-Wrn are connected to first addressing circuit (X-addressing circuit) 2 for selecting a designated memory cell according to coded X-address signals X1-XU. Bit lines Rll-Rnl, R12-Rn2 are connected to switching circuit 3 for selecting the bit lines. Switching circuit 3 is controlled by second addressing circuit (Y-addressing circuit) 4 through drive lines Bl-Bn. Second addressing circuit 4 selects a designated memory cell according to coded Y-address signals Yl-Yv. Sense amplifier 5, which reads data out of memory cells Cll-Cmn, and data input buffer 6, are connected to switching circuit 3. Sense amplifier 5 provides an output to data output buffer 7. Memory cells Cll-Cmn, first and second addressing circuits 2 and 4, switching circuit 3, sense amplifier 5, data input buffer 6 and data output buffer 7 are formed together on the same substrate 1. Figure 2 specifically illustrates one memory cell, i e. memory cell C22, and its peripheral drive circuits. The other ./emory cells and their peripheral drive circuits have the same construction as shown in Figure 2. Memory cell C22 comprises flip-flop 14 formed by a pair of cross-coupled normally-off Schottky barrier gate field-effect switching transistors (MESFETs) 10 and 11, a pair of normally-on load MESFETs 12 and 13 connected to MESFETs 10 and 11, and a pair of transfer gates formed by normally-off MESFETs 17 and 18 connected between input/output nodes 15 and 16 of flip-flop 14 and bit lines R21 and R22. First addressing circuit 2 comprises address buffer 20, decoder 21 and driver 22, all of which are known in the art. Address buffer 20, which includes normally-off MESFETs 23, 24 and normally-on MESFETs 25, 26, generate signal X1 or X1 in response to an X1 input. Decoder 21 comprises a NOR gate formed by a plurality of normally-off MESFETs 28, 34 and normally-on MESFET 29. The gates of MESFETs 28 receive signals from address buffer 20 and other address buffers of the same construction. Driver 22, which includes normally-off MESFETs 30, 31 and normally-on MESFETs 32, 33, supplies a sufficient driving current to word line W2. Switching circuit 3 includes normally-off switching MESFETs 35, 36 connected to bit lines R21, R22, respectively. The gates of MESFETs 35 and 36 are connected in comon to an output terminal of second addressing circuit 4 via drive line B2. Second addressing circuit 4 includes address buffer 40, decoder 41 and driver 42, all of which are known in the art. These elements of second addressing circuit 4 are formed by a combination of normally-off MESFETs 43-47, 55 and normally-on MESFETs 50-54 as shown in Fire 2. Sense amplifier 5 is a kno*7n sense amplifier including a pair of normally-off switching MESFETs 60, 61, normally-on MESFET 62 connected between the sources of MESFETs 60, 61 and ground potential, and a pair of normally-on MESFETs 63, 64 coupled to the drains of MESFETs 60, 61 respectively. Data input buffer 6 is a known circuit for supplying data to switching MESFETs 35, 36 when data is to be written into the memory device. Data input buffer 6 includes normally-off MESFET 70 for receiving data, a pair of normally-off MESFETs 71,- 72 for receiving signal WE which is an inverted writing command signal, a pair of MESFETs 68, 69 for receiving signal CS which is an inverted chip select signal (described in further detail below), normally-off MESFET 73 driven by MESFET 70, and cross-coupled normally-off MESFETs 76-80. Data output buffer 7 includes a pair of NOR gates 81, 82, inverters 83-86, and output circuit 87, which comprises normally-off switching MESFETs 89-100 and normally-off load MESFETs 101-106. Signal CS is a signal for selecting a plurality of chips including the above static RAM and a common 2-volt power supply for supplying VDD. Schottky barrier gate diodes D1, D2 are connected in a forward bias direction between word line W2 and drive line B2 and ground potential. Diodes D1, D2 clamp the gate voltage of MESFET switches 35, 36 and MESFET transfer gates 17, 18 to about 0.8 V to prevent an overcurrent from flowing into the sources and drains of these MESFETs from word and drive lines W2, B2. For this purpose, diodes D1 and D2 preferably have a forward breakdown voltage which is equal to or higher than the threshold voltage (0.1-0.2 V) of MESFETs 17, 18, 35, 36, and which is substantially equal to the forward breakdown voltage (about 0.8 V, for exa,rple) of these MESFETs. Diode D1 may be connected to word line W2, for example, at a position D3 indicated by broken lines. In such an arrangement, however, a current is likely to flow into the sources or drains of the transfer gates of the memory cells which are located nearer to address circuit 2 than the position of diode D3. Similar diodes are connected to the other word lines W1, W3-Wm and drive lines B1, B3-Bn. The constuction of normally-on and normally-off MESFETs and a Schottky barrier gate diode of the aforementioned static RAM is illustrated in Figures 3(a) through 3(c). Figure 3(a) shows a normally-on MESFET fabricated on gallium arsenide substrate 200. N-conductive-type source and drain regions 201, 202 are formed by implanting silicon ions into substrate 200 having an impurity dose value of 3x1013 cm¯2. N-conductive-type channel region 203 is formed by implanting silicon ions into substrate 200, for example, at an acceleration voltage of 100 KV with an impurity dose value of 3 x 1012 cm¯2. Channel region 203 has a depth of about 0.2 yam. Electrodes 204, 205 of a gold-germanium alloy are disposed on the source and drain regions 201, 202, respectively, in ohmic contact therewith. Electrode 206 of aluminium is disposed on channel region 203. Electrode 206 forms a Schottky barrier together with channel region 203. Figure 3(b) shows a normally-off MESFET fabricated on gallium arsenide substrate 200. The normally-off MESFET has course and drain regions 211, 212 which have the same construction as the source and drain regions 201, 202 shown in Figure 3(a), respectively. Electrodes 214, 215, 216 have the same construction as electrodes 204, 205, 206 shown in figure 3(a), respectively. The normally-off SET has N-conductive-type channel region 213 of a construction different from that of channel region 203 of Figure 3(a). Channel region 213 is formed by implanting silicon ions into substrate 200 of an acceleration voltage of 50 KV with an impurity dose value of 1 x 1013 cm¯2. Channel region 213 has a depth of about 0.1 um. The Normally-off MESFET has a threshold voltage in the range of 0.1 to 0.2 V. Figure 3(c) illustrates a Schottky barrier gate diode having N-conductive-type source region 221 and N-conductive-type channel region 223 fabricated on gallium arsenide substrate 200. Electrode 224 of gold-germanium alloy is disposed on source region 221 in ohmic contact therewith. Electrode 226 of aluminium is disposed on channel region 223. Electrode 226 forms a Schottky barrier together with channel region 223. The diode has the same construction as the MESFET of Figure 3(a) except that the diode does not have drain region 202 and its corresponding electrode. The diode can therefore be fabricated easily and with a high production yield by utilising the fabrication process for the MESFET shown in Figure 3(a). Various experiments carried out to confirm the advantages and results of the present invention will now be described. The ratios (W/L) of gate width (W) to gate length (L) of the MESFETs shown in Figure 2 were as follows: W/L of MESFETs 10, 11 : 20/1 W/L of MESFETs 12, 13 : 4/8 W/L of MESFETs 17, 18 : 10/1 W/L of MESFETs 35, 36 : 50/1 The junction area of diodes 91, D2 5 x 5 (pom2), and power supply voltae VD was 2 V. Data was written and stored in memory cell C22, and the potentials at nodes 15, 16 in Figure 2 were 0.1 V and 0.7 V, respectively. Thereafter, first and second addressing circuits 2, 4 were energised to enable transfer gates 17, 18 and switching MESFETs 35, 36 to read data out of memory cell C22 into sense amplifier 5. As a consequence, the potential of bit line R21 was about 0.2 V and the potential of bit line R22 was about 0.7 V, and the data could be red by an ordinary sense amplifier 5 without any difficulty. The data stored in memory cell C22 was not destroyed when word line W1 was set at a high level to read data out of another memory cell. When data was read out of memory cell C22 with diodes D1 and D2 removed, a low level current flowed into node 15 through the gate of transfer gate 17 and the gate of switching MESFET 35, and thereby increased the potential of node 15 to about 0.5 V. At that time, a high level current also flowed into node 16 through the gate of transfer gate 18 and through the gate of switching MESFET 36. Since this current flowed from the gate to the source of MESFET 10, the potential of node 16 remained substantially unchanged at about 0.8 V. As a result, the potential of bit lines R21, R22 was about 0.7 V, and data could not be read by sense amplifier 5. When word line W1 was set at a high level to read data out of another memory cell, the data stored in memory cell C22 was destroyed by a slight external disturbance such as a change in the power supply voltage. This data jestruction was caused by the small difference between the potential of the low level node 15 and high level node 16. To the contrary, when power supply voltage VDD Ws35 set to 1 V with diodes Dl, D2 r-esiw-vd, the date was not destroyed and could be read out of memory cell C22. Further experiments were carried out using only one of the diodes D1, D2. When first and second addressing circuits 2, 4 were energised with diode D1 connected and diode D2 removed, node 15 was at a potential of 0.15 V and node 16 at a potential of 0.7 V. The potentials of bit lines R21, R22 were 0.5 V and 0.7 V, respectively. The data could then be read out of memory cell C22, because sense amplifier 5 had a sufficient sensitivity. When word line W2 was set at a high level for reading data out of another memory cell, data destruction did not take place in memory cell C22. When first and second addressing circuits 2, 4 were energised with diode D2 connected and diode D1 removed, node 15 was at a potential of 0.3 V and node 16 at a potential of 0.5 V. The potentials of bit lines R21, R22 were 0.4 V and 0.6 V, respectively. The data could be read out of memory cell C22 because sense amplifier 5 had sufficient sensitivity. When word line W2 was set at a high level for reading data out of another memory cell, and when the external disturbances were small, then the data in memory cell C22 was not destroyed. Therefore, it is apparent from the above experimental results that the use of at least one of diodes D1, D2 is required for stable memory operation. While the normally-on and normally-off MESFETs and the Schottky barrier gate diode illustrated in Figures 3(a) through 3(c) were employed in the foregoing embodiment, those shown in Figures 4(a) through 4(c) may also be used. The same parts in F ares 3(a) through 3(c) and Figures 4(a) through 4(c) are denoted by identical reference characters. The construction of the channel regions and electrodes disposed therein of the elements in Figures 4(a) through 4(c) is different than Figures 3(a) through 3(c). Channel regions 207, 217, 227 shown in Figures 4(a) through 4(c) have a substantially equal depth of about 0.2 m. Also, in the normally-on MESFET shown in Figure 4(a), gate electrode 208 is made of platinum. The normally-off MESFET shown in Figure 4(b) has a platinum gate electrode 213 buried in channel region 217 by a heat treating process. The diode illustrated in Figure 4(c) has a platinum electrode 228 disposed on channel region 227. A modified circuit arrangement, as shown in Figure 5, may be employed in place of circuit arrangement 400 enclosed by the dot-dash line in Figure 2. In the circuit arrangement of Figure 5, sense amplifier 500 is connected to bit lines R21, R22 between memory cell C22 and switching circuit MESFETs 535, 536 for selecting bit lines. Sense amplifier 500 includes switching MESFETs 560, 561, 570 and load MESFETs 563, 564. Address buffer 542 is formed by normally-off switching MESFETs 573-576 and normally-on load MESFETs 571, 572. Schottky barrier gate diode D4 is connected between ground potential and drive line B3, which supplies an output signal from address output buffer 542 to the gates of MESFETs 535, 536. Schottky barrier gate diode D4 is connected in a forward bias direction to clamp the output signal. In the circuit arrangement of Figure 5, a sense amplifier is necess-ry for each pair of bit lines. On the other hand, in the circuit arrangement of Figure 2, all of bit lines Rll-Rnl, R n2 can b#beCO.-!--ccted in c.#T#on on toone sense amplifier 5. Although certain preferred embodiments have been shown and described, it should be understood that many changes and modifications may be made therein by one skilled in this art within the scope of the appended claims.

Claims: CLAIMS 1. A static random-access memory device which is formed on a gallium arsenide substrate comprising: (a) a plurality of memory cells (C11-Cmn) connected in a matrix by bit lines (R11-Rn1, R12-Rn2) and word lines (W1-Wm) each memory cell (C22) including a flip-flop (14) having a pair of input/output nodes and a pair of cross-coupled normally-off Schottky barrier gate field-effect transistors (10, 11) connected to said input/output nodes, said memory cell further including a pair of transfer gates formed by normally-off Schottky barrier gate field-effect transistors (17, 18) having their gates connected to said word lines and their sources and drains connected between said input/output nodes of said flip-flot and said bit lines; (b) first addressing circuit means (2) for supplying control signals to said transfer gates through said word lines; ; (c) data input means (6) for writing data into said memory cells through said bit lines; (d) data output means (7) for reading data out of said memory cells through said bit lines; (e) switching means formed by normally-off Schottky barrier gate field-effect transistors (35, 36) for selecting said bit lines; and (f) second addressing circuit means (4) for supplying control signals through drive lines to said switching means; characterised in thazt tM memory device further crjss: (y) a Schottky barrier gate diode (D1, D2) connected in a forward bias direction between at least one of said word lines and a reference potential to clamp the gate voltage on the gates of said Schottky barrier gate field-effect transistors forming said transfer gates. 2. A static randon-access memory device according to claim 1 wherein said diode has a forward breakdown voltage which is equal to or higher than the threshold voltage of said transistors constituting said transfer gates and said switching means, and which is substantially the same as the forward breakdown voltage of the Schottky barrier gates of said transistor. 3. A static random-access memory device according to claim 1 or claim 2 wherein at least one of said first and second addressing circuit means comprises SchottRy barrier gate field-effect transistors. 4. A static random-access memory device according to any preceding claim further comprising a common power supply to supply a positive voltage to said flip-flop and said first and second addressing circuit means, said reference potential being a ground potential. 5. A static random-access memory device CCOe g to any preceding claims Wherein said data output . leans comprises a sense amplifier connected throw said switching means to said memory cells and an output buffer to receive an output signal from said so e amplifier. 6. A static random-access memory device according to any of claims 1 to 4, wherein said data output means comprises a sense amplifier connected to said bit lines between one of said memory cells and said switching means and an output buffer to receive an output signal from said sense amplifier. 7. A static random-access memory device according to any preceding claim wherein said Schottky barrier gate diode is connected to said word line in close proximity to said first or second addressing circuit means. 8. A static random-access memory device according to any preceding claim further comprising a Schottky barrier gate diode connected in a forward bias direction between at least one of said drive lines and said reference potential to clamp the gate voltage on the gates of said Schottky barrier gate field-effect transistors forming said switching means.

Inventors: HOJO, AKIMICHI, KANAZAWA, KATSUE, TOYODA, NOBUYUKI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1984
Main classification: G11C11
IPC codes: H01L27, G11C11