FET POWER AMPLIFYING APPARATUS

Abstract: An FET linear power amplifying apparatus has an FET power amplifier and a distortion generator which produces a distortion signal indicative of a distortion component having the same amplitude and inverted phase as those of a distor­ tion component produced by the FET power amplifier. The amplitude and the phase of the distortion signal are controlled in accordance with a control signal which depends upon the magnitude ratio of the input and output signals of the apparatus. The distortion component which will be produced by the FET power amplifier is compensated by the controlled distortion signal.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET) power amplifying apparatus, particularly to an FET linear power amplifying apparatus for single side band (SSB) multiplex communication systems. 2. Description of the Prior Art In conventional linear power amplifying apparatuses for SSB multiplex communication systems traveling-wave tubes (TWT) are used for linear power amplification. Such an apparatus contains various problems. For example, the characteristics of the TWT change as the TWT ages, the TWT manufacturing costs are high, and the TWT has a high power consumption. Recently, the power amplifying performance of FETs has been up-graded, and FETs are now widely used for linear power amplification. However, FET linear power amplifying apparatuses contain problems in that the distortion characteristics and gain characteristics change in proportion to changes in the ambient temperature. US-A 4 331 928 relates to the generation of a negative feedback signal for sampling the input signal and removing the modulation from the input signal by converting it into a square wave. The output signal is also sampled and the envelope separated therefrom is used to drive a modulator which modulates the square wave. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an FET power amplifying apparatus which can suppress the amount of distortion changes to an extremely low level. According to the present invention, the above object is achieved by a FET power amplifying apparatus comprising: an FET power amplifier for amplifiying an input signal to produce an output signal; control signal producing means for producing a control signal which corresponds to a magnitude ratio of the input signal and the output signal; signal producing means for receiving the input signal and for producing a signal to be added to the input signal, amplitude and phase controlling means for controlling the amplitude and phase of either the signal produced by the signal producing means or of the input signal applied to the signal producing means in accordance with said produced control signal; characterised in that the signal producing means includes an FET amplifier, having substantially the same construction as that of the FET power amplifier, for receiving an input signal and for producing a signal having a signal component of the input signal and an other distortion component, which other distortion component corresponds to the same amplitude and inverted phase as those of a distortion component produced by said FET power amplifier when the input signal is applied thereto; and by distortion compensating means using said other distortion component for compensating the distortion component being produced by said FET power amplifier, in accordance with said controlled distortion signal. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic block diagram of an embodiment according to the present invention; Fig. 2 is a block diagram showing details of the embodiment of Fig. 1; Fig. 3 is a schematic block diagram of another embodiment according to the present invention; and Fig. 4 is a block diagram showing details of the embodiment of Fig. 3. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 is a schematic illustration of an FET linear power amplifying device for an SSB multiplex communication system as an embodiment of the present invention. In Fig. 1, HYB-1, HYB-2, and HYB-5 denote hybrid circuits, DET-1 and DET-2 detectors, COMP a differential amplifier circuit, DG a distortion generator, ATTEN a variable attenuator circuit, PST a variable phase shifter circuit, and PWA an FET power amplifier circuit. An input signal applied to an input terminal IN of this device is divided into two input signals by the hybrid circuit HYB-1. One of the divided input signals is detected by the detector DET-1 to produce the DC voltage component of the input signal. This produced DC voltage component is applied to one input terminal of the differential amplifier circuit COMP. The other divided input signal is applied to the hybrid circuit HYB-2 and further divided into two signals; one of which is applied to the hybrid circuit HYB-5, and the other to the distortion generator DG. The distortion generator DG produces a distortion signal indicating a distortion component equivalent to a distortion component which will be produced by the FET power amplifier circuit PWA. The distortion signal is applied to the hybrid circuit HYB-5 via the variable attenuator circuit ATTEN and the variable phase shifter circuit PST. Therefore, the amplitude and phase of the distortion signal can be changed by the attenuator circuit ATTEN and phase shifter circuit PST irrespective of an input signal. The hybrid circuit HYB-5 superimposes the distortion signal onto the divided input signal applied from the hybrid circuit HYB-2, and this superimposed signal is applied to the FET power amplifier circuit PWA. If the distortion signal applied to the hybrid circuit HYB-2 is adjusted by the attenuator circuit ATTEN and the phase shifter circuit PST so that the amplitude of the distortion signal is the same as the amplitude of a distortion component produced by the FET power amplifier circuit PWA and the phase of the distortion signal is inverse to the phase of a distortion component produced by the FET power amplifier circuit PWA, the distortion component of the FET power amplifier circuit PWA can be cancelled. Therefore, the amount of distortion included in the output signal from the FET power amplifier circuit PWA can be considerably reduced. The output signal from the FET power amplifier circuit PWA is output via an output terminal OUT and also applied to the detector DET-2. The detector DET-2 detects the output signal and produces the DC voltage component of the output signal. The produced DC voltage is applied to the other input terminal of the differential amplifier circuit COMP. The FET power amplifier circuit PWA is controlled to maintain the gain of the FET power amplifying device at a constant in accordance with the input/output signal levels detected by the detectors DET-1 and DET-2. That is a linearity of the input/output level characteristics is maintained. It is important to maintain a linearity of the input/output characteristics of the FET power amplyfying device for amplifying a signal having an amplitude component such as a SSB signal. When the gain of the FET power amplifier circuit PWA changes depending upon the change in the surrounding environment, for example, changes in the ambient temperature, the DC voltages detected by the detectors DET-1 and DET-2 differ from each other and, thus, the output of the differential amplifier circuit COMP also changes, causing an adjustment in the attenuation factor of the attenuator circuit ATTEN and phase shifting amount of the phase shifter circuit PST. Accordingly, change in the amount of distortion of the FET power amplifier circuit PWA, accompanied by change in the gain thereof can be automatically compensated. Figure 2 shows the details of the embodiment of Fig. 1. As shown in Fig. 2, the distortion generator DG is composed of hybrid circuits HYB-3 and HYB-4, an FET amplifier A-1, a fixed attenuator ATT-1, and a fixed phase shifter PS-1. A divided input signal from the hybrid circuit HYB-2 is applied to the hybrid circuit HYB-3, and further divided into two signals. One signal is applied to the FET amplifier A-1 to produce distortion similar to distortion which will be produced by the FET power amplifier circuit PWA. The other signal is applied to the phase shifter PS-1 to invert the phase, i.e., to shift the phase by 180°. Output from the FET amplifier A-1 is applied to the hybrid circuit HYB-4 via the attenuator ATT-1. Output from the phase shifter PS-1 is also applied to the hybrid circuit HYB-4 to be superimposed on the output from the FET amplifier A-1. If the attenuation factor of the attenuator ATT-1 and the phase shifter PS-1 are determined so that the amplitudes of signal components of the outputs applied to the hybrid circuit HYB-4 coincide, the hybrid circuit HYB-4 can produce a distortion signal which includes only the distortion component produced by the FET amplifier A-1. In Fig. 2, the arrows S₁ to S₆ indicate the signal component of the input signal. The input signal includes only the signal component. The arrows D₁ to D₄ indicate the distortion component produced by FET amplifiers. Since the hybrid circuit HYB-4 receives the inverted signal component S₃ from the phase shifter PS-1 and the signal component S₂ plus distortion component D₁ from the attenuator ATT-1, which are superimposed upon each other, the output (distortion signal) from the hybrid circuit HYB-4 becomes only the distortion component D₂ , shown in Fig. 2. The attenuator circuit ATTEN is composed of a variable attenuator ATT-2 and a DC amplifier DA-2, and the phase shifter circuit PST is composed of a variable phase shifter PS-2 and a DC amplifier DA-3. The amplitude and phase of the distortion signal are adjusted by the attenuator ATT-2 and the phase shifter PS-2, and thus the adjusted and inverted distortion signal D₃ is applied to the hybrid circuit HYB-5. The input signal having only signal component S₄ is applied to this hybrid circuit HYB-5 via a delay circuit DL and a fixed attenuator ATT-3, which adjust timing and amplitude of the input signal to be superimposed. Therefore, the output from the hybrid circuit HYB-5 includes, as shown in Fig. 2, the noninverted signal component S₅ and the inverted distortion component D₄. The FET power amplifier circuit PWA is composed of a variable attenuator ATT-4, a FET power amplifier A-2, and a directional coupler C-1, and the differential amplifier circuit COMP is composed of a differential amplifier COM and a DC amplifier DA-1. The attenuator ATT-4 connected between the hybrid circuit HYB-5 and the FET power amplifier A-2 controls the amplitude of the signal applied to the FET power amplifier A-2, in accordance with a control signal fed from the differential amplifier COM via the DC amplifier DA-1. That is, this attenuator ATT-4 carries out an automatic gain control for controlling a gain of the amplifying device at a constant so as to maintain linearity of the device. As mentioned above, since the signal applied to the FET power amplifier A-2 has the inverted distortion component, the distortion component produced by this FET power amplifier A-2 itself can be cancelled. Thus the output signal from the FET power amplifier A-2 includes only the signal component S₆ shown in Fig. 2. The output signal from the FET power amplifier A-2 is output via the directional coupler C-1. A part of the output signal is applied to the detector DET-2 from the directional coupler C-1. The detector DET-2 detects the DC voltage component of the output signal and feeds the detected voltage component to the differential amplifier COM which controls the attenuation factor of the attenuator ATT-4 and etc. During this condition, the output signal level follows the change in the input signal level. When the gain of the FET power amplifier A-2 changes because of, for example, temperature changes, the ratio of the DC voltages from the detectors DET-1 and DET-2 varies, causing the control signal output from the differential amplifier COM to change. As a result, the attenuation factor of the attenuator ATT-4 changes in accordance with the change in the control signal and, thus, the gain of the FET power amplifying device can be stabilized. The control signal is further applied to the attenuator ATT-2 via a DC amplifier DA-2, and to the phase shifter PS-2 via a DC amplifier DA-3, to control the attenuation factor and phase shifting amount thereof. Thus, the change in the amount of distortion in the FET power amplifier A-2 which occurs in accordance with the change in gain of the FET power amplifier A-2 itself can be compensated. As mentioned hereinbefore, the present invention utilizes the phenomenon wherein the change in the characteristics of the distortion component produced in an FET linear power amplifier is similar to the change in the characteristics of the distortion compensating component obtained from a distortion generator using an FET. That is, a control signal for automatic gain control of the FET linear power amplifying device is used to control the amplitude and phase of a distortion signal used to cancel the distortion component from the FET power amplifier. Therefore, an FET linear power amplifying device for an SSB multiplex communicaton system having little distortion can be obtained. Figure 3 schematically illustrates an FET linear power amplifying device for an SSB multiplex communication system as another embodiment of the present invention, and Fig. 4 illustrates the details of the embodiment of Fig. 3. In this embodiment, the variable attenuator circuit ATTEN and the variable phase shifter circuit PST are connected and located ahead of the distortion generator DG. The divided input signal from the hybrid circuit HYB-2 is first applied to the attenuator circuit ATTEN and the phase shifter circuit PST, wherein the amplitude and phase are controlled, and the controlled signal is then applied to the distortion generator DG. The structure, operation, and effect of this embodiment are the same as those of the embodiment of Figs. 1 and 2. Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.

Claims: A FET power amplifying apparatus comprising: an FET power amplifier (A-2) for amplifiying an input signal to produce an output signal; control signal producing means (DET-1, DET-2) for producing a control signal which corresponds to a magnitude ratio of the input signal and the output signal; signal producing means (DG) for receiving the input signal and for producing a signal to be added to the input signal, amplitude and phase controlling means (ATTEN, PST) for controlling the amplitude and phase of either the signal produced by the signal producing means (DG) or of the input signal applied to the signal producing means (DG) in accordance with said produced control signal; characterized in that the signal producing means (DG) includes an FET amplifier (A-1), having substantially the same construction as that of the FET power amplifier (A-2), for receiving an input signal and for producing a signal having a signal component of the input signal and an other distortion component, which other distortion component corresponds to the same amplitude and inverted phase as those of a distortion component produced by said FET power amplifier (A-2) when the input signal is applied thereto; and by distortion compensating means (ATT-4) using said other distortion component for compensating the distortion component being produced by said FET power amplifier (A-2), in accordance with said controlled distortion signal. An apparatus as claimed in claim 1, wherein said control signal producing means includes: a first wave detecting means (DET-1) for producing a first voltage signal indicative of the magnitude of the input signal; and a second wave detecting means (DET-2) for producing a second voltage signal indicative of the magnitude of the output signal. An apparatus as claimed in claim 1 or 2, wherein said control signal producing means includes means (COMP) for comparing said first and second voltage signals and for producing a control signal which corresponds to a voltage ratio of said first and second voltage signals. An apparatus as claimed in any preceding claim, wherein said signal producing means (DG) includes: means (PS-1) for inverting a phase of the input signal; and means (HYB-4) for superimposing the produced signal from said FET amplifier (A-1) onto the inverted input signal to produce said other distortion component. An apparatus as claimed in any preceding claim, wherein said controlling means includes: means (ATTEN) for variably attenuating said produced other distortion signal in accordance with said produced control signal; and means (PST) for variably shifting the phase of said produced other distortion component in accordance with said produced control signal. An apparatus as claimed in any preceding claim, wherein said compensating means (ATT-4) includes means for superimposing said controlled other distortion component onto an input signal to produce a signal having an inverted phase as the phase of a distortion component which will be produced by said FET power amplifier (A-2), said produced signal being applied to said FET power amplifier (A-2).

Inventors: IGARASHI, HIROSHI
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: H03F1
IPC codes: H03F1, H03F3