PARALLEL ADDER CIRCUIT

Abstract: In a parallel adder circuit, first and second full adders (X₁ to X n/2 , Y₁ to Y n/2 ) each having an addend input terminal, an augend input terminal, a sum output terminal, a carry in­ put terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preced­ ing full adder is directly connected to the carry input termi­ nal of the succeeding full adder. In order to shorten the car­ ry propagation delay time, the first full adder (X₁ to X n/2 ) is arranged to receive an inverted carry signal ( C i ) (FALSE) from the preceding stage and to provide a carry signal (C i+1 ) (TRUE) to the succeeding stage, while the second full adder (Y₁ to Y n/2 ) is arranged to receive a carry signal (C i+1 ) (TRUE), from the preceding stage and to provide an iverted carry signal ( C i+2 ) (FALSE) to the succedding stage.

Description: The present invention relates to an adder circuit and, more particularly, to a parallel adder circuit. With a multidigit parallel adder circuit which is to be operated at a high speed, it is required to remarkably shorten the propagation delay time between a carry input and a carry output of an adder circuit. A conventional parallel adder circuit is constituted by using a full adder as shown in, e.g., Fig. 1. In Fig. 1, A i denotes an addend input; B i is an augend input; C i-1 is a carry input from the preceding stage; S i a sum output; C i is a carry output to the succeeding stage; reference numerals 11 and 12 indicate EX-OR (EXCLUSIVE OR) gate circuits; and 13, 14 and 15 are NAND gate circuits. However, in the above full adder, the propagation delay time corresponding to two stages of the NAND gate circuits is involved in the propagation of the carry signal; furthermore, the time delay corresponding to one stage of the EX-OR gate circuit occurs until the sum output S i is obtained. As a full adder to improve such drawbacks, there is such a full adder as shown in Fig. 2 that is disclosed in JP Laid-Open Patent Applications Nos. 147235/1981 and 147236/1981. Namely, this full adder comprises: a control circuit including an OR gate circuit 16, an NAND gate circuit 17 and an inverter 18; an input circuit having an NAND gate circuit 19; and a switching circuit including an inverter 20 and clocked inverters S₁ to S₄. The control circuit is arranged to provide a control signal  which becomes high when an addend input is equal to an augend input, and a control signal  complementary to  . On the other hand, the clocked inverters S₁ and S₄ operates when the control signal  is high, while the clocked inverters S₂ and S₃ operates when the inverted control signal  is high. In this full adder, its arrangement is very simple and the maximum time delay in the carry propagation is involved by only switching circuit including the inverter 20. Also, the clocked inverters S₁ to S₄ whose operating speed is fairly faster than an NAND gate circuit are used as the switching circuit. Consequently, this full adder is very advantageous for a high speed operation. However, even in such a full adder, a maximum time delay for the carry propagation occurs due to the inverter 20 and clocked inverter S₁. Therefore, a conventional multistage adder circuit having such full adders as described above is not satisfactory the carry propagation. Prior art document FR-A-25 16 675 discloses a binary adder with a fastened carry propagation time and having binary adder transmission gates composed of MOSFETs. A three-input binary adder circuit has three couples of input signals, that is addends A, A , augends B, B and carries C, C . Finally, prior art document US-A-3 100 837 describes a binary adder-subtracter which comprises flip-flops, "none"-gates and inverters, and performs an addition or subtraction. It is an object of the present invention to provide parallel adder circuits which can constitute a parallel adder circuit arranged to shorten the carry propagation delay time. To solve this object, the present invention provides a parallel adder circuit as stated in claim 1. In this parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding-stage full adder is connected to the carry input terminal of the succeeding-stage full adder. The first full adder comprises a first control circuit responsive to an addend input signal and an augend input signal applied to the addend input terminal and augend input terminal for providing a first switch control signal which becomes a first logical level when the addend input signal and augend input signal are equal and which becomes a second logical level when the input signals are not equal, a first input circuit connected to receive the addend and augend input signals to provide a NAND output signal or a NOR output signal of the input signals or an inverted signal of one of the input signals as an output signal, and a first switching circuit having first to fourth inverting type switching means, the first and fourth switching means being arranged to conduct when the first switch control signal from the first control circuit is at the first logical level, the second and third switching means being arranged to conduct when the first switch control signal from the first control circuit is at the second logical level, the first and second switching means being connected to respectively receive a carry inverted input signal from the preceding stage that is applied to the carry input terminal and its inverted signal, and having their outputs connected together to the sum output terminal, and the third and fourth switching means being connected to respectively receive the carry inverted input signal from the preceding stage that is applied to the carry input terminal and the output signal from the first input circuit, and having their outputs connected together to the carry output terminal. The second full adder comprises a second control circuit responsive to the addend input signal and augend input signal applied to the addend input terminal and augend input terminal for providing a second switch control signal which becomes the first logical level when the addend input signal and augend input signal are equal and which becomes the second logical level when the input signals are not equal, a second input circuit connected to receive the addend and augend input signals to provide one of the input signals as an output signal, and a second switching circuit having fifth to eighth inverting type switching means, the sixth and eighth switching means being arranged to conduct when the second switch control signal from the second control circuit is at the first logical level, the fifth and seventh stitching means being arranged to conduct when the second switch control signal from the second control circuit is at the second logical level, the fifth and sixth switching means being connected to respectively receive a carry input signal from the preceding stage applied to the carry input terminal and its inverted signal, and having their outputs connected together to the sum output terminal, and the seventh and eighth switching means being connected to respectively receive the carry input signal from the preceding stage applied to the carry input terminal and the output signal from the second input circuit, and having their outputs connected together to the carry output terminal. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1 and 2 show conventional full adders for use in a parallel adder; Figs. 3 and 4 show arrangements of first and second full adders for use in a parallel adder according to the present invention, respectively; Figs. 5 and 6 show practical arrangements of the full adders of Figs. 3 and 4, respectively; Fig. 7 is a circuit diagram of clocked inverters; Figs. 8 shows a partial modification of the full adder; and Fig. 9 shows an arrangement of a parallel adder of the invention. Fig. 9 shows an arrangement of a parallel adder circuit according to the present invention, in which first full adders X₁ to X n/2 and second full adders Y₁ to Y n/2 are alternately connected. The first full adders X₁ to X n/2 receive an inverted carry input C i-1 and provide a carry output Ci. On the contrary, the second full adders Y₁ to Y n/2 receive a carry input C i-1 and provide an inverted carry output C i . Figs. 3 and 4 show basic arrangements of the first and second full adders X and Y, respectively. That is, in the first full adder X shown in Fig. 3, the addend input A i and augend input B i are supplied to a control circuit 21 and an input circuit 22. The control circuit 21 provides a control signal  which becomes high when A i = B i and its inverted control signal  . On the other hand, the input circuit 22 provides a NAND output or NOR output of A i and B i or an inverted signal of one of A i and B i . The output of the input circuit 22 is coupled to a switching circuit S₈. In addition, as mentioned above, the carry inverted input C i-1 is applied to the first full adder X. The carry inverted input C i-1 is applied to switching circuits S₅ and S₇ and through an inverter 23 to a switching circuit S₆. The switching circuits S₅ to S₈ are controlled by the control signals  and  and are inverting type switches which invert an input signal when they are ON. The switching circuits S₅ and S₈ are turned on when the control signal  goes high, while they are turned off when the control signal  goes low. The switching circuits S₆ and S₇ are turned on when the control signal  goes high and are turned off when the control signal  goes low. Outputs of the switching circuits S₅ and S₆ are connected together to provide a sum output S i and outputs of the switching circuits S₇ and S₈ are connected together to provide the carry output C i . Next, in the second full adder Y shown in Fig. 4, the addend input A i and augend input B i are applied to a control circuit 24 as in the first full adder X. An input terminal of a switching circuit S₁₂ is connected to one of the addend input terminal and the augend input terminal at a connecting point 25. On the other hand, the carry input C i-1 is applied to the second adder Y. This carry input Ci-1 is applied to switching circuits S₉ and S₁₁ and through an inverter 26 to a switching circuit S₁₀. These switching circuits S₉ to S₁₂ are controlled by the control signals  and  and are inverting type switches like the switching circuits S₅ to S₈. The switching circuits S₁₀ and S₁₂ are turned on when the control signal  becomes high and are turned off when the control signal  becomes low. The switching circuits S₉ and S₁₁ are turned on when the control signal  goes high and are turned off when the control signal  goes low. Outputs of the switching circuits S₉ and S₁₀ are connected together to provide the sum output S i and outputs of the switching circuits S₁₁ and S₁₂ are connected together to provide the carry inverted output C i . Figs. 5 and 6 show practical circuit arrangements of the first and second full adders X and Y shown in Figs. 4 and 5 respectively. Namely, in the first full adder X shown in Fig. 5A, the control circuit 21 is composed of an OR gate circuit 27 and an NAND gate circuit 28 and an inverter 29, while the input circuit 22 is composed of an NAND gate circuit 30. The output of the input circuit 22 is taken from an output of the NAND gate circuit 30. The switching circuits S₅ to S₈ are constituted by clocked inverters having well-known C-MOS arrangements shown in Figs. 7A to 7D. In the second full adder Y shown in Fig. 6, the control circuit 24 comprises an OR gate circuit 31 and NAND gate circuits 32 and 33 and an inverter 34. The switching circuits S₉ to S₁₂ are constituted by the clocked inverters shown in Figs. 7A to 7D. The operations of the first and second full adders X and Y of Figs. 5 and 6 will now be described below. In the first full adder X, when the addend input A i and augend input B i are applied, the control signals  and  are provided by the control circuit 21, so that the clocked inverters S₅ to S₈ are accordingly controlled. When the carry inverted input C i-1 is input, and A i = B i , the clocked inverters S₅ and S₈ are operative and the clocked inverters S₆ and S₇ are inoperative. Thus, the output of the input circuit 22 is inverted by the clocked inverter S₈ to be output from the carry output terminal C i . On the contrary, when Ai ≠ Bi, the clocked inverters S₅ and S₈ are inoperative and the clocked inverters S₆ and S₇ are operative; therefore, the carry inverted input C i-1 is inverted by the clocked inverter S₇ to be output from the carry output terminal C i . Next, in the second full adder Y, when the addend input A i and augend input B i are applied, the control signals  and  are output from the control circuit 24, so that the clocked inverters S₉ to S₁₂ are accordingly controlled. When A i = B i , the clocked inverters S₁₀ and S₁₂ are operative and the clocked inverters S₉ and S₁₁ are inoperative. Therefore, the addend input A i or augend input B i is inverted by the clocked inverter S₁₂ to be output from the carry inverted output terminal C i . In contrast, when A i ≠ B i , the clocked inverters S₁₀ and S₁₂ are inoperative and the clocked inverters S₉ and S₁₁ are operating. Thus, the carry input C i-1 is inverted by the clocked inverter S₁₁ to be output from the carry inverted output terminal C i . Namely, in each of the first and second full adders X and Y, the carry propagation delay time are caused due merely to one stage of clocked inverter at most. Therefore, as shown in Fig. 9, when the first and second full adders X₁ to X n/2 and Y₁ to Y n/2 are alternately connected, inverting circuits the number of which corresponds to the number of stages can be omitted in the carry propagation path. Consequently, as compared with a conventional adder circuit whereby the delay time corresponding to two stages of gate circuits is needed as the carry propagation delay time of each full adder, the carry propagation delay time of each full adder of this invention merely equals the delay time corresponding to one stage of the switching circuit consisting of the clocked inverter at most. Thus, the carry propagation delay time can be fairly shortened. The invention is very advantageous in case of constituting a parallel adder circuit of a plurality of bits, in particular, an adder circuit having a long bit length. The full adder circuit of Fig. 5A may be modified as shown in Fig. 5B and the full adder circuit of Fig. 6A may be modified as shown in Fig. 6B. As the inverter, a C-MOS type, an n-channel MOS type and a bootstrap type as shown in Figs. 8A to 8C, respectively, may be adopted.

Claims: A parallel adder circuit characterized in that it comprises: first and second full adders (X₁ to X n/2 Y₁ to Y n/2 ) each having an addend input terminal and augend input terminal, a carry input terminal, a sum output terminal, and a carry output terminal, said first and second full adders being alternately connected such that the carry output terminal of a preceding full adder is directly connected to the carry input terminal of a succeeding full adder; each of said first full adders (X₁ to X n/2 ) including: a first control circuit (21) responsive to an addend input signal (A i ) and an augend input signal (B i ) applied to said addend input terminal and augend input terminal, respectively, for providing a first switch control signal (,  ) which goes to a first logic level when the addend input signal and augend input signal are equal and which goes to a second logic level when they are not equal; an input circuit (22) responsive to the addend and augend input signals for providing a NAND output signal or NOR output signal of the addend and augend input signals; and a first switching circuit having first to fourth clocked inverters (S₅ to S₈) responsive to the first switch control signal (,  ), said first and fourth clocked inverters (S₅, S₈) being enabled to invert an input signal applied thereto when the first switch control signal is at the first logic level, said second and third clocked inverters (S₆, S₇) being enabled to invert an input signal applied thereto when the first switch control signal is at the second logic level, said first and second clocked inverters (S₅, S₆) being connected to respectively receive a carry inverted input signal ( C i-1 ) applied to said carry input terminal and a carry input signal (C i-1 ), and having their outputs connected together to said sum output terminal, and said third and fourth clocked inverters (S₇, S₈) being connected to respectively receive the carry inverted input signal (C i-1 ) applied to said carry input terminal and an output signal of said input circuit (22), and having their outputs connected together to said carry output terminal to provide a carry output signal (C i ); and each of said second full adders (Y₁ to Y n/2 ) comprising: a second control circuit (24) responsive to the addend and augend input signals (A i , B i ) for providing a second switch control signal (,  ) which goes to the first logic level when the addend input signal and augend input signal are equal and which goes to the second logic level when the input signals are not equal; a second switching circuit having fifth to eighth clocked inverters (S₉ to S₁₂) responsive to the second switch control signal (,  ), said sixth and eighth clocked inverters (S₁₀, S₁₂) being enabled to invert an input signal applied thereto when the second switch control signal is at the first logic level, said fifth and seventh clocked inverters (S₉, S₁₁) being enabled to invert an input signal applied thereto when the second switch control signal is at the second logic level, said fifth and sixth clocked inverters (S₉, S₁₀) being connected to respectively receive a carry input signal (C i-1 ) applied to said carry input terminal and a carry inverted input signal ( Ci-1 ), and having their outputs connected together to said sum output terminal, and said seventh and eighth clocked inverters (S₁₁, S₁₂) being connected to respectively receive the carry input signal (C i-1 ) applied to said carry input terminal and one of said addend and augend signals (A i , B i ), and having their outputs connected tegether to said carry output terminal to provide a carry inverted output signal ( C i ). A parallel adder circuit according to claim 1, characterized in that said first control circuit (21) is composed of an OR gate (27), a first NAND gate (28) and an inverter (29), and said first input circuit (22) is composed of a second NAND gate (30); two input terminals of both said OR gate (27) and said second NAND gate (30) are connected respectively to said addend input (Ai) terminal and said augend input (Bi) terminal, and one input terminal of said first NAND gate (28) is connected to an output terminal of said OR gate (27) and the other input terminal of said first NAND gate (28) is connected to an output terminal of said second NAND gate (30), and an output terminal of said first NAND gate (28) is connected to an input terminal of said inverter (29), and said output terminal of said second NAND gate (30) is connected to an input terminal of said fourth clocked inverter (S8); and said output terminal of said first NAND gate (28) and an output terminal of said inverter (29) supply a control signal () and an inverted control signal (  ) respectively to said clocked inverters (S5 to S8). A parallel adder circuit according to claim 1, characterized in that said first control circuit (21) is composed of an AND gate (27a), a first NOR gate (28a) and an inverter (29), and said first input circuit (22) is composed of a second NOR gate (30a); two input terminals of both said AND gate (27a) and said second NOR gate (30a) are connected respectively to said addend input (Ai) terminal and said augend input (Bi) terminal, and one input terminal of said NOR gate (28a) is connected to an output terminal of said AND gate (27a) and the other input terminal of said first NOR gate (28a) is connected to an output terminal of second said NOR gate (30a), and said output terminal of said first NOR gate (28a) is connected to an input terminal of said inverter (29), and said output terminal of said second NOR gate (30a) is connected to an input terminal of said fourth clocked interverter (S8); and said output terminal of said first NOR gate (28a) and said output terminal of said inverter (29) supply an inverted control signal (  ) and a control signal () respectively to said clocked inverters (S5 to S8). A parallel adder circuit according to claim 1, characterized in that said second control circuit (24) is composed of an OR gate (31), a first NAND gate (33), an inverter (34), and a second NAND gate (32); two input terminals of both said OR gate (31) and said second NAND gate (32) are connected respectively to said addend input (Ai) terminal and said augend input (Bi) terminal, and one input terminal of said first NAND gate (33) is connected to an output terminal of said OR gate (31) and the other input terminal of said first NAND gate (33) is connected to an output terminal of said second NAND gate (32), and an output terminal of said first NAND gate (33) is connected to an input terminal of said inverter (34); and said output terminal of said first NAND gate (33) and an output terminal of said inverter (34) supply a control signal () and an inverted signal (  ) respectively to said clocked inverters (S9 to S12). A parallel adder circuit according to claim 1, characterized in that said second control circuit (24) is composed of an AND gate (31a), a first NOR gate (33a), an inverter (34), and a second NOR gate (32a); two input terminals of both said AND gate (31a) and said second NOR gate (32a) are connected respectively to said addend input (Ai) terminal and said augend input (Bi) terminal, and one input terminal of said first NOR gate (33a) is connected to an output terminal of said AND gate (31a) and the other input terminal of said first NOR gate (33a) is connected to an output terminal of said second NOR gate (32a), and an output terminal of said first NOR gate (33a) is connected to an input terminal of said inverter (34); and said output terminal of said first NOR gate (33a) and an output terminal of said inverter (34) supply an inverter control signal (  ) and a control signal () respectively to said clocked inverters (S9 to S12).

Inventors: IIDA, TETSUYA C/O PATENT DIVISION, SAHODA, MASAYUKI C/O PATENT DIVISION, TANAKA, FUMINARI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1984
Main classification: G06F7
IPC codes: G06F7