ELECTRONIC CIRCUITS AND SIGNAL GENERATOR USING THEM

Abstract: The present invention relates to electronic circuits and signal generator using them. The signal generator is adapted to generate a signal with pulses having sloping edges and includes a generator circuit (BSG) which is adapted to give the signal (BS+) in the time intervals between the pulses such an amplitude with respect to a second signal (BS-) that this amplitude may be detected by a detector circuit (CO) and in response thereto may be limited by a limiting circuit (S4) to a reference value. The electronic circuits include a comparator circuit (CO) and a modulator circuit (MOD).

Description: ELECTRONIC CIRCUITS AND SIGNAL GENERATOR USING THEM The present invention relates to a signal generator for generating a signal with pulses having sloping edges. Such a signal generator is well known in the art. When operational amplifiers are used therein to realize the sloping pulse edges it may happen, due to a possible offset of the amplifiers, that the signal has an unwanted high amplitude in the time intervals between the pulses. This can be a nuisance in certain applications and give rise to noise. An object of the present invention is to provide a signal generator of the above type, but which does not present this drawback, i.e. wherein the amplitude of the signal generated has a predetermined amplitude, e.g. O Volt, in the interpulse time intervals. According to the invention this object is achieved due to the fact that it includes a generator circuit which is adapted to give said signal in the time intervals between the pulses such an amplitude with respect to a second signal that the amplitude may be detected by a detector circuit and in response thereto may be delimited by a limiting circuit to reference value. By thus choosing the amplitude voluntary high during the interpulse time intervals, the latter are easily detected by the detector circuit and this information is used by the limiter circuit to bring the generator output on the wanted reference value. Another characteristic feature of the signal generator according to the invention is that said signal generator is coupled, on the one hand with said detector circuit which is constituted by a comparator circuit and on the other hand with a generator output which is coupled with said limiting circuit controlled by said comparator circuit, all in such a way that when both said signals are applied to said compara tor circuit the pulse periods and the interpulse time intervals of said first signal are detected as a consequence of which said comparator circuit controls said limiting circuit in such a manner that the latter limits said amplitude to said reference value in said interpulse time intervals. Still another characteristic of the present signal generator is that it includes : a pulse source which generates opposite first and second pulse waveforms, as well as a modulator circuit with a pair of first modulator inputs to which said first and second signals are applied respectively, with a pair of second modulator inputs to which said first and second pulse waveforms are applied, and with a modulator output which is coupled with said modulator output, said first modulator inputs being coupled via a third and a fourth gating circuit to said modulator output respectively and said second modulator inputs constituting control inputs of said third and fourth gating circuits respectively, such that a pulse waveform modulated by said first and second signals is generated at said modulator output. Yet another characteristic of the present signal generator is that said opposite first and second pulse waveforms are pulse density modulated pulse waveforms and that said generator output is coupled with a filter device including a lowpass filter to transform said modulated pulse waveform into a modulated sine waveform. Still another characteristic of the signal generator according to the invention is that said filter device also includes a bandpass filter to allow the passage of said sine waveform and to limit the amount of power in the lower frequency region thereof. Still other characteristics of the present signal generator are that the lower frequency region is the speech region, that the first and second signals are mutually inverse and that the modulated sine wave is used as a metering signal for telecommunication purposes. Because this metering signal has the wanted reference value, e.g. O Volt, in the time intervals between the pulse constituted by sine waves, during these time intervals it cannot be considered in the telephone subset as an effective metering signal, as would be the case if the signal would have a considerable amplitude in these time intervals. Also this signal does not produce clicks in the telephone subset because on the one hand the pulses constituted by the sine waves have sloping edges reducing the amount of power in the speech region and which is responsible for such clicks, and on the other hand because the bandpass filter further reduces this amount of power. The invention also relates to a comparator circuit with a first and a second input and with complementary first and second outputs, characterized in that said first and second inputs are coupled with first and second inputs of first and second inverters via first and second gating circuits, said inverters being coupled in a closed loop, a DC source being coupled via said inverters through a gating device and said complementary outputs being constituted by the inverter outputs. The invention also relates to a modulator circuit with pairs of first and second inputs and with an output, characterized in that each of said first inputs is coupled with said output via first and second gates and that said second inputs constitute respective control inputs of said first and second gates. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of embodiments taken in conjunction with the accompanying drawings wherein: Fig. 1 represents a pulse generator MSG according to the invention; Fig. 2 shows waveforms PW and BSO appearing at terminals PW and BSO of Fig. 1 respectively; Fig. 3 represents comparator CO of Fig. 1 and according to the invention in detail; Fig. 4 shows pulse waveforms PW1 to PW3 controlling this comparator CO. The signal generator MSG shown is a metering signal generator. It forms part of a transcoder and filter circuit which is itself included in a telephone line circuit connected between a telephone line, coupled to a telephone subset, and a telephone switching network and comprising the cascade connection of a subscriber line interface circuit, able to perform line control and supervision, a digital signal processor adapted to execute analog-to-digital and digital-to-analog conversion operations, the above transcoder and filter circuit which is able to generate a metering signal and moreover to transform 13-bit linear PCM signals into 8-bit companded PCM signals and vice-versa, and a dual processor terminal controller to ensure the general control of the line circuit. The trans coder and control circuits are provided in common for eight associated subscriber line interface circuits and digital signal processors. As will be explained hereinafter the metering signaL able to be generated by MSG comprises bursts of 12 kHz or 16 kHz sine waves which are symmetrical about a O Volts reference and have a minimum length of 100 milliseconds. In order that these bursts should not produce audible click in the telephone subset they have gradually varying leading and trailing edges and are moreover suitably filtered, both measures decreasing the powe-r in the audible frequency region of the signal which is responsible for such audible clicks The metering signal generator MPG shown includes a pulse source PS providing at its outputs PW, PDM and PW1 to PW3 a pulse waveform PW (Fig. 2), a Pulse Density Modulated (PDM) binary signal PDM (not shown) and pulse waveforms PW1 to PW3 (Fig. 4) respectively. Pulse waveform PW has a frequency of 3.13 Hz and an amplitude varying between reference voltages (VREF2 = -0.7 Volts and +VREF1 = + 2.5 Volts. The binary signal PDM has an amplitude varying between V- = -5 Volts, and 0 Volt and a selectable frequency of 4096 kHz or of 2048 kHz and is such that when fit is passed through a suitable lowpass filter a pure sine wave with a frequency of 12 kHz or 16 kHz is obtained respectively. The pulse waveforms PWl to PW3 vary between -5 Volts and V+ = + 5 Volts and have a frequency of 256 kHz. The pulse waveform PW is applied to the like named non-inverting output of an operations amplifier CAl forming part of a burst signal generator BSG with outputs BS+ and BS- and further includes constant current sources CSl and CS2, operational amplifiers OA2 and OA3, resistors R1 and R2 of equal value and capacitor C. As schematically indicated by the arrows, the output of OAl controls the current sources CSl and CS2, which are connected in series between V and V-. The junction point of CSl and CS2 is connected to the inverting input of OAl, also to ground via capacitor C and finally to the non-inverting input of unity gain amplifier OA2 which isolates capacitor C from the output of OA2. This output is connected via resistor R1 to the inverting input of OA3 whose output is connected to its inverting input through feedback resistor R2 and whose non-inverting input is grounded. The outputs of OA2 and OA3 constitute the above mentioned outputs BS+ and BS respectively. When the pulse waveform PW is applied to BSG, capacitor C is charged in a linear way by the constant current provided by current source CSl and until its voltage reaches +VREFl or is discharged in a linear way by the constant current flowing to V- through current source CS2 and until its voltage reaches (VREF2. Between these charging and discharging operations the capacitor remains at +VREF1 or at -VREF2. Thus an asymmetrical pulse waveform BS+ which alternately extends at different sides of O Volts as shown in Fig. 2, is obtained, the pulses of this signal BS+ having linearly rising end decaying edges with rise and decay times equal to about 20 milliseconds. The constant amplitude portions between these edges each have a minimum duration of 100 milliseconds. To obtain a pulse waveform which varies symmetrically about 0 Volt, the unsymmetrical pulse waveform 35+ at the output of capacitor C is first reproduced at the output BS+ of OA2 and then inverted in OA3. The latter generates at its output BS- the like named pulse waveform BSvarying between +VREF2 and -VREF1 and also alternately extending at different sides of O Volt as shown in Fig. 2. These pulse waveforms BS and -VS are now applied to the like named control inputs of a modulator circuit MOD comprising two switches S1 and S2 each with a PMOS transistor PM1/2 and an MEMOS transistor NM1/2, The first and second control inputs of these switches S1/S2 are constituted by the gate electrodes of the transistors PM1/2 and Mem1/2 respectively; their data inputs are constituted by the interconnected source of PM1/NM2 and drain of NM1/PM2; and their data outputs are constituted by the commoned drain of PM1/NM2 and source of NM1/PM2. Output 35+ and BS- of BSG are connected to the data inputs of S1 and S2 whose data outputs are commoned and constitute the output BSO of the modulator circuit MOD. The inputs PDM1/2 thereof are constituted by the commoned first/second and second/first control inputs of the switches S1 and S2. The output PDM of the pulse source PS is connected to the input of a level shifter and inverter circuit LSIC having two outputs PDM1 and PDM2 connected to the like named inputs of the modulator circuit MOD respectively. In circuit LSIC the level of the pulse waveform PDM varying between 0 Volts and V- is shifted so that a pulse waveform PDM1 varying between V+ and V- is obtained and PDM1 is then inverted to produce pulse waveform PDM2. These two opposite pulse waveforms PDMl and PDM2 are such that they close either switch S1 or S2 of the modulator circuit MOD, thus applying either 35+ or BS- to the output BSO thereof. As a consequence the PDM pulse waveform BSO at this output BSO is symmetrical about 0 Volts and limited between BS and -BS. In Fig. 2, the envelope of this PDM pulse waveform BSO is represented, this envelope varying between +VREF1 and -VREF1 in the pulse or burst periods and between VREF2 and -VREF2 in the time intervals between these pulses. These pulse periods and interpulse time intervals are determined by the crossings of BS+ and BS- which occur on the 0 Volt axis. Only the PDM signals in the burst periods will be used as metering signals. Therefore the PDM signals in the interpulse time intervals and which could be interpreted in the telephone subset as metering pulses should be eliminated. For this reason the above output signals BS+ and BS- are also applied to the like named inputs of a comparator CO which has outputs CR and CR and is shown in detail in Fig. 3. This comparator CO includes two identical inverters INV1 and INV2 comprising PMOS and NMOS transistors PM5, NM5 and PM6, NM6 respectively. The gate electrodes of the pair of transistors PM5 and NM5, as well as those of the pair of transistors PM6 and NM6 are commoned and constitute the inverter inputs I1 and I2 respectively, and the drain electrodes of the transistors of each of these pairs are also commoned and constitute the inverter outputs 01 and 02 respectively. The inverter output 02 is connected to the inverter input I2 and the inverter output 02 is likewise connected to the inverter input Il. The supply voltage V is connected to the interconnected source electrodes of PMs and PM6 and the source-to-drain path of PMOS transistor PM7 which is controlled by pulse waveform PW3 (Fig. 4), and the commoned source electrodes of NM5 and NM6 are connected to V- through the drain-to-source path of NMOS transistor NM7 which is controlled by PW2 (Fig. 2). The input BS- of the comparator circuit CO is connected to the input I1 of INV1 through the drain-to-source path of NMOS transistor NM7, whilst the input BS+ is likewise connected to I2 via NM9. Transistors NM8 and NM9 are both controlled by pulse waveform PWl (Fig. 4). The above inverter inputs 11 and I2 constitute the outputs CR and CR of the comparator CO respectively. This comparator circuit CO operates as follows when the pulse waveforms BS+ and BS- are applied to the like named inputs thereof. When PW1 is activated (1) the waveform BS+ and BS- are applied to the inverter inputs 11 and I2 via EM8 and NM9 respectively and are thus sampled since they are stored in the parasitic input capacitances which are present at thse inputs. Afterwards, when PWZ is brought on 1 and Pw3 on 0, both the inverters are made operative as both PM7 and NM7 then become conductive as a consequence of which V+ and V- are applied to the drain electrodes of PM5, PM6 and of NM5, NM6 respectively so that both the inverters become operative. Hence, when BS+ is larger than BS-, NM5 and PM6 become fully conductive due to the amplifying action of the interconnected inverters. As a consequence the outputs CR and CR are then substantially at the voltages V+ and V- respectively i.e. they are activated (1) and deactivated (0) respectively. On the contrary, when BS- is larger than BS+, then CR and CR are activated and deactivated respectively. From the above it follows that when the sign of (BS+) - (BS-) changes, the comparator output varies from 1 to O or vice-versa whilst output CR simultaneously changes from O to 1 and vice-versa. Thus the pulse periods and interpulse time intervals of pulse waveform BSO are characterized by CR = 1, CR = 0 and CR = O, CR = 1 respectively. Returning to Fig. 1, the outputs CR and CR of CO are connected to the control inputs of switches S3 and S4 which are similar to the switches S1 and S2 and comprise PMOS and NMOS transistors PM3, NM3 and PM4, NM4 respectively. The data input of S3 is connected to the above mentioned output BSO of the modulator circuit MOD and its data output is connected to output terminal MNTC and to the data input of S4 whose data output is grounded. The first control input of PM3 and the second one of S4 are connected to output CR of CO, whilst the second control input of PM3 and the first one of S4 are connected to output CR of CO. As described above, CR = 1 and CR = 0 during the pulse periods of BSO so that switches S3 and S4 are then closed and open respectively and the output signal BSO appears at output terminam MNTC. On the contrary, in the interpulse time intervals of BSO, CR = 1 and CR = 0 due to which switches S3 and S4 are open and closed respectively. Thus the output BSO is then disconnected from terminal MNTC and the latter is grounded. From the above it follows that starting from a pulse waveform PW which varies between -VREF2 and +VREF1 pulse waveforms BS+ and BS- have been generated which vary between -VREF2 and4VREFl and between +VREF2 and -VREF1 respectively, so that it is then easy to detect the crossings of both these waveforms and use this information to limit the amplitude of the PDM waveform BSO e.g. to zero between in the interpulse time intervals thereof. The reason for proceeding in this way is the following. When one could start from a pulse waveform PW varying between VREF2 = O Volts and VREF1 then it could happen that due to a possible offset of OAl and/or of OA2 the lower ,level of 35+ in the interpulse time;,intervals is not at O Volt but lower, say at DV1. Due to a possible offset of OA3 and the inversion therein it could also happen that the upper level of BS- in the interpulse time intervals is at a higher value than 0 Volt, say + AV2. When the difference between +aV2 and - tV1 is sufficiently large the PDM signal in the interpulse time intervals could then be interpreted in the telephone subset as a metering signal By forcing now the level of BS+ and BS- in the interpulse time intervals to values which are equal to -VREF2 and tVREF2 idenependtly from the operational amplifiers OA1-OA3 having an offset or not, considerable amplitudes of BS+ and BS- are realised so that even when these amplifiers have an offset (always smaller than VREF2 = 0.7 Volts) it will always be possible to detect these amplitudes in the way described above and then limit the voltage amplitude of BSO to zero in the interpulse time intervals. Because the leading and trailing edges of the bursts of the PDM signal in the above metering signal BSO generated at the output MNTC vary slowly, the amount of power contained in the audible frequency region of the metering signal is relatively small and because this power is responsible for audible clicks in the telephone subset also the danger of occurrence of such clicks is thus reduced. However, this measure is still insufficient as this amount of power is still too high. To further reduce it use is made of a filter device which is branched between terminal MNTC in the output terminam MNTB of the generator and includes the cascade connection of lowpass filter LPF1, bandpass filter BPF and lowpass filter LPF2. Filter LPF1 is a simple RC filter and is used as an anti-aliasing filter. Bandpass filter BPF is a sixth order switched-capacitor filter and comprises the cascade connection of a second order lowpass filter and of a fourth order bandpass filter proper (both not shown). This lowpass filter has a cut off frequency at 20 kHz and operates at a sampling,frequency df 4096 kHz. It transforms the, PDM waveform BSO into a waveform with bursts of a 12 kHz or 16 kHz sine wave and acts as an anti-aliasing filter for the bandpass filter proper which has a flat characteristic in a region covering 12 kHz to 16 kHz and operates at a sampling frequency of 256 kHz. The function of this filter is to pass the 12 kHz or 16 kHz sine wave and provide a further attenuation of the amount of power in the audible frequency region of the above signal BSO. Lowpass filter LPF2 is a so-called Rauch filter with a cut-off frequency of 50 kHz. This filter is well known in the art and is used to suppress in the output signal at MNTB residual signals produced by the switchedcapacitor filter clock of the bandpass filter BPF. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims: CLAIMS 1. Signal generator for generating a signal with pulses having sloping edges, characterized in that it includes a generator circuit (BSG) which is adapted to give said signal (BS+) in the time intervals between the pulses such an amplitude with respect to a second signal (BS-) that this amplitude may be detected by a detector circuit (CO) and in response thereto may be limited by a limiting circuit (S4) to a reference value. 2. Signal generator according to claim 1, characterized in that said signal generator (BSG) is coupled, on the one hand with said detector circuit which is constituted by a comparator circuit (CO) and on the other hand with a generator output (MNTC) which is coupled with said limiting circuit (S4) controlled by said comparator circuit, all in such a way that when both said signals are applied to said comparator circuit the pulse periods and the interpulse time intervals of said first signal (BS+) are detected as a consequence of which said comparator circuit (CO) controls said limiting circuit (S4) in such a manner that the latter limits said amplitude to said reference value in said interpulse time intervals. 3. Signal generator according to claim 2, characterized in that said generator circuit (BSG) is coupled via a first gating circuit (S3) with said generator output which is coupled to said reference value through a second gating circuit (S4) which constitutes said limiting circuit, said first (S3) and second (S4) gate circuits being controlled by complementary outputs (CR, CR) of said cbmparator circuit (CO) in such a manner that said first gating circuit (S3) allows the passage of said signals only during the pulse periods and that said second gating circuit (S4) limits the generator output (MNTC) to said reference value in the interpulse time intervals. 4. Signal generator according to claim 2, characterized in that it includes : a pulse source (PS, LSIC) which generates opposite first (PDM1) and second (PDM2) pulse waveforms, as well as a modulator circuit (CO) with a pair of first modulator inputs (BS+, BS-) to which said first (BS+) and second (BS-) signals are applied respectively, with a pair of second modulator inputs (PDM1, PDM2) to which said first (PDM1) and second (PDM2) pulse waveforms are applied, and with a modulator output which is coupled with said modulator output (BSO), said first modulator inputs (BSf, BS-) being coupled via a third (S1) and a fourth (S4) gating circuit to said modulator output (BSO) respectively and said second modulator inputs (PDM1, PDM2) constituting control inputs of said third (S1) and fourth (52) gating circuits respectively, such that a pulse waveform (BSO) modulated by said first (BS+) and second (BS-) signals is generated at said modulator output (BSO) 5. Signal generator according to claim 4, characterized in that said opposite first (PDM1) and second (PDM2) pulse waveforms are pulse density modulated pulse waveforms and that said generator output (MNTC) is coupled with a filter device including a lowpass filter to transform said modulated pulse waveform into a modulated sine waveform. 6. Signal generator according to claim 5, characterized in that said filter device also includes a bandpass filter (BPF) to allow the passage of said sine waveform and to limit the amount of power in the lower frequency region thereof. 7. Signal generator according to claim 6, characterized in that said lower frequency region is the speech region. 8. Signal generator according to claim 1, characterized in that said first (35+) and second (BS-) are mutually inverse with respect to said reference value 9. Signal generator according to claim 8, characterized in that said first (BS+) and second (BS-) signals are trapezoidal. 10. Signal generator according to claims 7 and 9, characterized in that said modulated sine waveform (BSO) is a metering signal for telecommunication purposes. 11. Signal generator according to claim 1, characterized in that said generator circuit include a pulse source (PS) generating a rectangular pulse waveform (PW) whose envelope alternately extend, at different sides of said reference value, an operational amplifier (OAl) to the non -inverting input of which said rectangular pulse waveform (PW) is applied and whose output controls the operation of first (CS1) and second (CS2) current sources which are connected in series between the poles of a DC source (V+, V-), the junction point of said sources being coupled to the inverting input of said amplifier (OAl) and to one plate of a capacitor (C) whose other plate is connected to said reference value, said first signal (BS+) being generated at said junction point. 1t Signal generator according to claim 11, characterized in that said junction point is coupled to the non-inverting input of a unity gain second operational amplifier (OA2) and that the output of said second operational amplifier (OA2) is coupled with an inverting third operational amplifier (OA3) at the output of which said second signal (BS-) is generated. 13. Signal generator according to claims 3 and 4, characterized in that each of said gate circuits is constituted by a switch comprising two mutually coupled PMOS and NMOS transistors. 14. Comparator circuit with a first and a second input and with complementary first and second outputs, characterized in that said first (BS+) and second (BS-) inputs are coupled with first (I1) and second (I2) inputs of first (INV1) and second (INV2) inverters via first (NM8) and second (NM9) gating circuits, said inverters being coupled in a closed loop, a DC source being coupled via said inverters through a gating device (PM7, NM7) and said complementary outputs (CR, CR) being constituted by the inverter outputs (02, 01). 15. Comparator circuit according to claim 14, characterized in that each of said inverters (ins1, INV2) includes a PMOS transistor (PM5, PM6) and an NMOS transistor (NM5, NM6) the gate electrodes as well as the drain electrodes of which are commoned and constitute the inverter input (I1, I2) and output (01, 02) respectively, and the source electrodes of the PMOS transistors (PM5, PM6) and those of the NMOS transistors being coupled with respective poles of said DC source via third (PM7) and fourth gate circuits constituting said gating device, and said first and second gating circuits being conductive when said third and fourth gate circuits are not and vice-versa. 16. Modulator circuit with pairs of first and second inputs and with an output, characterized in that each of said first inputs (BS+, BS-) is coupled with said output (BSO) via first (S1) and second (S2) gates and that said second inputs constitute respective control inputs of said first (S1) and second (52) gates.

Inventors: HASPESLAGH, DIDIER RENE, RABAEY, DIRK HERMAN LUTGARDIS CORNELIUS, Haspeslagh, Didier René
Applicants: ALCATEL N.V., BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE VENNOOTSCHAP
Application year: 1984
Main classification: H04M15
IPC codes: H04M15, H03K7, H03K4, H03C1, H03K3