A SEMICONDUCTOR DIE HAVING UNDEDICATED INPUT/OUTPUT CELLS

Abstract: A semiconductor die (10) including a core cell (14) for processing signals, a plurality of bonding pads (18) positioned about the core cell (14), and a plurality of undedicated interface cells (16) for either inputting the signals from the bonding pads (18) to the core cell (14) or outputting the signals from the core cell (14) to the bonding pads (18), including a plurality of input/output geometries (22) positioned about the core cell (14) in which the input/output geometries (22) and cells (20) have no metallization. By depositing metallization, the geometries (22) and cells (20) can be made into input devices or output devices.

Description: A SEMICONDUCTOR DIE HAVING UNDEDICATED INPUT/OUTPUT CELLS Background of the Invention Field of the Invention This invention relates generally to semiconductor dies having core cells for supporting integrated circuits and, more particularly, to the interface cells of the semiconductor dies for inputting and outputting signals with respect to the core cells. Discussion of Background and Prior Art Semiconductor dies support integrated circuits which are designed for numerous and different signal processing functions. Each semiconductor die usually has at the center of the die at least one core cell which includes the logic circuitry for manipulating or processing the signals. About the periphery of the core cell is a plurality of interface cells for inputting signals to or outputting signals from the core cell. Thus, O PI an interface cell is either an input cell or an output cell. The semiconductor die also has a plurality of bonding pads coupled to the plurality of interface cells, respectively. The plurality of bonding pads of a given semiconductor die are used to couple the signals with respect to the plurality of bonding pads of another semiconductor die. Thus, a signal being inputted to a given semiconductor die will be coupled through a bonding pad and then through an input cell to the core cell. .After the signal processing is performed by the logic circuit in the core cell, the processed signal is coupled from the core cell, through an output cell and then to another bonding pad for conduction, for example, to another si ή eiconductor die. Prior to the manufacture of a given logic circuit on a core cell of a semiconductor die, the design and layout of the plurality of interface cells, i.e., the input and output cells, relative to the core cell is predetermined or prededicated. That is, as one example, the semiconductor die is designed such that all the input cells are positioned around one half of the periphery of the core cell while all the output cells are positioned around the other half of the periphery of the core cell. As another example, sequences of input and output cells are positioned about the periphery of the core cell such that alternate series of, for example, three input cells and three output cells extend about the periphery of- the core cell. One problem with the interface cells being prededicated is that the connections to various components of the logic circuit of the core cell can O ?I ■ be more difficult to implement. More specifically, and as one example, the circuit connection or metallization may have to extend from an input cell at the periphery of one side of the core cell to a circuit component positioned in the core cell at the other side of the core cell. Another problem with the interface cells being prededicated is that the number of input cells and number of output cells are fixed. Thus, for example, if one more input cell is required, or if one more output cell is required, - for connection to a given logic circuit to be implemented on the core cell, then the particular semiconductor die having the fixed number of interface cells cannot be used. Summary of the Invention It is an object of the present invention to provide a semiconductor die having a novel interface cell scheme. Another object of the present invention is to simplify the metallization or connection between a given interface cell and the corresponding circuit component in a core cell. Still another object of the present invention is to provide a semiconductor die having the required number of input cells and output cells that are needed for interfacing with a given circuit in a core cell. Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned of by practice of the invention. The objects and OMPI advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims. Statement of the Invention The above and other objects of the present invention are achieved in accordance with the purposes of the present invention, as embodied and broadly described herein through the use of a semiconductor die comprising a core cell.for processing signals and a plurality of interface cell means, positioned about the core cell and being undedicated, for either inputting the signals to or outputting the signals from the core cell. Preferably, each of the plurality of interface cell means has integrated circuit components without metallization, thereby making the interface cell means undedicated. Furthermore, metallization can be added to the integrated circuit components of any of the interface cell means to make any of the interface cell means an input cell or an output cell. Statement of Derived Benefits and Advantages By manufacturing a semiconductor die with a plurality of interface cell means that are not prededicated, each of these interface cell means can be later adapted to function as an input cell or an output cell depending upon the particular logic circuit to be implemented in the core cell. This undedicated feature provides flexibility in the placement and number of input cells and output cells. Thus, all required input cells and all OMPI required output cells for a given integrated circuit to be implemented in the core cell can be placed relatively close to corresponding circuit components in the core cell by depositing metallization on the undedicated cell means to make the input cells and output cells. Also, the maximum or exact number of input cells and output cells that are needed can be implemented merely by depositing the appropriate metallization on the undedicated interface cell means. Brief Description of the Drawings The accompanying drawings, which are incorporated in and form a part of the specification, illustrate an embodiment of the present invention and, together with the description, serve to explain the principles of the invention. In the drawings: Fig. 1 illustrates a top view of a block diagram of a semiconductor die of the present invention; Fig. 2 is a detailed top view of an undedicated interface cell means of the present invention; Fig. 3 is a detailed top view showing the interface cell means of Fig. 2 implemented as an input cell; Fig. 4 illustrates schematically the circuit of the input cell shown in Fig. 3; Fig. 5 is a detailed top view of the interface cell means of Fig. 2 implemented as an output cell; and Fig. 6 is a schematic of the circuit of the output cell shown in Fig. 5. _OMPF ^_?o" Detailed Description of the Invention Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Fig. 1 shows a semiconductor die 10 which can be, for example, a gate array die 12. The semiconductor die 10 has a core cell or cells 14 which can support any given logic circuit or circuits (not shown) for processing signals. A plurality of interface cell ean≤ 16 are placed about the periphery of the core cell 14 for inputting signals to or outputting signals from the core cell 14, as will be further described. Also shown are a plurality of bonding pads 18 which couple signals to and from other semiconductor dies 10 (not shown). As will be further described, at this point in the manufacture of the semiconductor die 10, the plurality of interface cell means 16 are identical and undedicated in that each can function as an input cell or an output cell depending on the metallization to be applied. While a total of eight interface cell means 16 are shown, the semiconductor die 10 can have other numbers of interface cell means 16. Fig. 2 shows in more detail one interface cell means 16 and one corresponding bonding pad 18. The one interface cell means 16 includes an input/output (I/O) cell 20 and an I/O geometry 22. The I/O cell 20 has a plurality of integrated circuit components shown generally at 24 which, for example, include resistors R, - R-, transistors Q, - Q 5 and a diode D, . The I/O geometry 22 can include, for example, a transistor Q fi and a diode D„. OMPI As illustrated in Fig. 2, there is no connection amongst the integrated circuit components 24 of the I/O cell 20, nor is there any connection between the I/O cell 20 and the I/O geometry 22. Furthermore, there is no connection between the bonding pad 18 and the overall interface cell means 16. Consequently, the interface cell means 16 is not dedicated for inputting signals into or outputting signals from the core cell 14. In accordance with the present invention, the semiconductor die 10 can be manufactured as shown in Fig. 1 and Fig. 2 with a number of bonding pads 18, a number of interface cell means 16, and a core cell 14 which ultimately will support a given logic circuit or circuits. Then, the semiconductor die 10 having the undedicated plurality of interface cell means 16 can be used conveniently in connection with any logic circuit or circuits that are placed in the core cell 14. As will be further described, any one or more of the plurality of interface cell means 16 then can be implemented for inputting signals to or outputting signals from the core cell 14, depending on the logic circuit in core cell 14. The placement of an input cell 20-. and corresponding input geometry 22 χ or output cell 20_ and corresponding output geometry 22 Q , as well as their number, also will depend on the particular logic circuit or circuits implemented in the core cell 14. Fig. 3 is the same as Fig. 2, except that metallization M has been deposited on die 10 to interconnect the integrated circuit components 24 of I/O cell 20, the I/O geometry 22 and the bonding pad 18, as shown. Fig. 4 shows schematically a circuit 26 resulting from the metallization M deposited as shown in Fig. 3, with like reference numerals corresponding to like components. Thus, Fig. 3 and Fig. 4 illustrate that the interface cell means 16 now comprises an input cell 20 τ and an input geometry 22_ for receiving an input signal S, from the> bonding pad 18 and inputting either of two signals S_, S_ to the core cell 14. Transistor Q g of input geometry 22_ is an input transistor in this embodiment. Fig. 5 is the same as Fig. 2, except that metallization M has been deposited on die 10 to interconnect the integrated circuit components 24 of I/O cell 20, .the I/O geometry 22 and the bonding pad 18, as shown. Fig. 6 shows schematically a circuit 28 resulting from the metallization M shown in Fig. 5, with like reference numerals corresponding to like components. As can be seen from Fig. 5 and Fig. 6, now the interface cell means 16 comprises an output cell 20 and an output geometry 22- for receiving two signals S. , S g from core cell 14 and outputting a signal S β to the bonding pad 18. Transistor Q g of output geometry 22 Q is an output transistor in this embodiment. Thus, as illustrated in Figs. 3-6, depending on the metallization M that is deposited, the same interface cell means 16 that is undedicated as manufactured, can subsequently be used for inputting or outputting signals with respect to the core cell 14, depending on the particular logic circuits to be implemented in the core cell 14. A given interface cell means 16 can be made into an input device or an output device, so as to be in close proximity with the portion of the logic circuit in core cell 14 with which it is associated _OM?I for inputting or outputting signals. The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims: Clai s 1. A semiconductor die, comprising a) a core cell for processing signals; and b) a plurality of interface cell means, positioned about said core cell and being undedicated, for either inputting the signals to or outputting the signals from the core cell. 2. A semiconductor die, according to claim 1, wherein said " plurality of interface cell means each has a plurality of integrated circuit components without metallization for interconnecting said plurality of integrated circuit components. 3. A semiconductor die, according to claim 2, wherein any of said plurality of integrated circuit components is adapted to receive metallization to make said any of said plurality of interface cell means an input cell for inputting the signals to said core cell. 4. A semiconductor die, according to claim 2, wherein any of said plurality of integrated circuit components is adapted to receive metallization to make said any of said plurality of interface cell means an output cell for outputting the signals from said core cell. 5. A semiconductor die, comprising: a) a core cell for processing signals; b) a plurality of bonding pads positioned about said core cell; c) a plurality of undedicated interface cell means for either inputting the signals from said plurality of bonding pads to said core cell or outputting the signals from said core cell to said plurality of bonding pads, including i) a plurality of input/output geometries positioned about said core cell; and ii) a plurality of input/output cells positioned about said core cell, said plurality of . input/output geometries and said plurality of input/output cells having no metallization. 6. A semiconductor die, according to claim 5, wherein each of said plurality of input/output cells has a plurality of integrated circuit components having no metallization interconnecting said plurality of integrated circuit components. 7. A semiconductor die, according to claim 6, wherein said plurality of input/output geometries and said plurality of input/output cells have no metallization interconnecting said plurality of input/output geometries and said plurality of input/output cells, respectively. - JΕE OMP 8. A semiconductor die, according to claim 5, wherein any of said plurality of input/output geometries and any of said plurality of input/output cells, respectively, are adapted to receive metallization to make said any of said plurality of input/output geometries an input cell and said any of said plurality of input/output cells an input cell. 9. A semiconductor die, according to claim 5., wherein any of said plurality of input/output geometries and any of said plurality of input/output cells, respectively, are adapted to receive metallization to make said any of said plurality of input/output geometries an output cell and said any of said plurality of input/output cells an output cell. 10. A gate array die, comprising: a) a core cell; b) a plurality of bonding pads positioned about said core cell; c) a plurality of input/output geometries positioned about said core cell and connectable to said plurality of bonding pads, respectively, each of said plurality.of input/output geometries having an integrated circuit component for receiving metallization to make any of said plurality of input/output geometries an input transistor or an output transistor; and d) a plurality of input/output cells positioned about said core cell and connectable to said plurality of input/output geometries, respectively, each of said plurality of input/output [ -__2MPΓ cells having integrated circuit components for receiving metallization to make any of said plurality of input/output cells an input cell or an output cell. ~

Inventors: THOMPSON MICHAEL D, THOMPSON, MICHAEL, D.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1984
Main classification: H01L27
IPC codes: H01L21, H01L23, H01L27