DATA COMPARISON CIRCUIT CONSTRUCTED WITH SMALLER NUMBER OF TRANSISTORS

Abstract: A circuit for comparing first and second binary coded digital data signals has a plurality of first circuits each including first and second transistors of a P-channel type connected in series between a first potential terminal and a first output node, a plurality of second circuits each including third and fourth transistors of an N-channel type connected in series between a second potential terminal and a second output node, and means for precharging the first and second output nodes to first and second logic levels, respectively. The first and third transistors are supplied with one bit data of the first signal, and the second and fourth transistors are supplied with an inverted data of the second signal. A change in the logic level at at least one of the first and second output nodes is detected.

Description: BACKGROUND OF THE INVENTION The present invention relates to a data comparison circuit comparing two binary coded digital signals, and more particularly to a circuit detecting whether or not two binary coded digital signals are coincident with each other. In a digital circuit, a data comparison circuit is often employed to detect the coincidence between first and second binary coded digital signals. Since both of the signals to be compared have binary coded data, the detection of the coincidence is achieved by comparing every corresponding bit. For this purpose, the comparison circuit in the prior art includes a plurality of exclusive-OR (called hereinafter "EX-OR") circuits receiving the comparing bit data and one logic circuit such as a NOR circuit, for example. The NOR circuit has a plurality of input terminals supplied with the outputs of the respective EX-OR circuits. When the logic level of each bit data of the first binary coded digital signal is equal to the corresponding bit data of the second binary coded digital signal, each of the EX-OR circuits takes the output of a low level. The NOR circuit thereby produces an output signal of a high level. On the other hand, if at least one of the bit data of the first signal is different in level from the corresponding bit data of the second signal, at least one EX-OR circuit produces a high level output. As a result, the output signal of the NOR circuit takes a low level. As well-known in the art, one EX-OR circuit constituted by the so-called complementary MOS transistors includes five P-channel transistors and five N-channel transistors. Assuming that each of the first and second digital signals has ten bits, ten EX-OR circuits are necessary, resulting in that one hundred transistors are required. In addition, the NOR circuit has ten input terminals, and requires ten P-channel transistors and ten N-channel transistors. As a result, the data comparison circuit in the prior art requires one hundred and twenty transistors in total. This means that considerable power is consumed in the comparison circuit and that the area occupied by the comparison circuit is large on a semiconductor integrated circuit chip. Moreover, a wiring pattern for interconnecting the respective transistors is very complicated. Stray capacitance is thus large. As a result, the operation speed of the circuit is low. SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a data comparison circuit constructed with a smaller number of transistors. Another object of the present invention is to provide a data comparison circuit whose operation speed is fast and whose power consumption is small. This object is achieved by a data comparison circuit comprising first and second potential terminals, first and second output nodes, at least one first series circuit connected between the first potential terminal and said first output node and including first and second transistors of first conductivity type connected in series, at least one second series circuit connected between said second potential terminal and said second output node and including third and fourth transistors of second conductivity type connected in series, first means for supplying a first digital signal to control electrodes of said first and third transistors, second means for supplying a second digital signal to control electrodes of said second and fourth transistors, third means for precharging said first and second output nodes to different logic levels from each other, and fourth means for detecting a change in the level of at least one of said first and second output nodes. When any one bit data of the first digital signal is equal in logic level to the corresponding bit data of the second digital signal, the first and second transistors of the corresponding first series circuit and/or the third and fourth transistors of the corresponding second series circuit are made conductive to change the logic level at the first output node and/or the second output node. The detecting means detects this change in level at the output node(s) and produces an output signal. When every bit data of the first digital signal is not equal in logic level to every corresponding bit data of the second digital signal, none of the first and second transistors of all the first series circuits and none of the third and fourth transistors of all the second series circuit are made conductive. Accordingly, both of the logic levels at the first and second output nodes do not change. Thus, no change at the output nodes is detected only when all the bit data of the first signal are different from all the corresponding bit data of the second signal, respectively. This means that the circuit according to the present invention is usable as a detection circuit for detecting the coincidence between the respective bit data of the first and second digital signals, by inverting every bit of the first or second signal before comparison. In this case, no change at the output nodes is detected only when all the bits of the first and second signals are equal to each other. The detecting means may be constituted by one NOR circuit having two input terminals and one inverter circuit. The first output node is connected to one of the input terminals of the NOR circuit, and the second output end is connected through the inverter to the other of the input terminals of the NOR circuit. As well-known in the art, the NOR circuit having two input terminals needs two transistors of the first conductivity type and two transistors of the second conductivity type, and the inverter circuit uses two transistors of different conductivity type. Each of two charging means can be constituted by one transistor. Accordingly, the circuit according to the present invention can be constructed by forty-eight transistors if each of the first and second digital signals has ten bit data. In the case where the circuit according to the present invention is applied to the data coincidence detection circuit, ten inverter circuit are further necessary to invert one of two digital signals to be compared, and hence sixty-eight transistors are required. The number of transistors in the circuit according to the present invention is about half that of the prior art circuit. Since the transistors are small in number, the wiring pattern is simplified and the stray capacitances are reduced. Therefore, the circuit according to the present invention compares two digital signals at a high speed and with a small power consumption. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a logic circuit diagram of a digital data comparison circuit according to the prior art; Fig. 2A is a circuit diagram of an exclusive OR (EX-OR) circuit used in the circuit shown in Fig. 1, and Fig. 2B is a circuit diagram of an NOR circuit shown in Fig. 1; Fig. 3 is a circuit diagram of a digital data comparison circuit according to a preferred embodiment of the present invention; Fig. 4 is a voltage waveform diagram at the respective nodes of the circuit shown in Fig. 3, and Fig.5 is a circuit diagram of another output section section according to the present invention. DETAILED DESCRIPTION OF THE PRIOR ART Referring to Figs. 1 and 2, a digital data comparison circuit according to the prior art will be described in order to facilitate the understanding of the features and advnatages of the present invention. The circuit shown in Fig. 1 compares two digital data signals A and B which consist of m bit data, i.e., (a₁, a₂, a₃, ... , a m ) and (b₁, b₂, b₃, ... , b m ), respectively. The first and m-th bit data a₁ and a m correspond to the least and most significant bits of the signal A, respectively, and the first and m-th bits data b₁ and b m correspond to the least and most significant bits of the signal B, respectively. In order to compare the two digital data signals A and B with every bits, this circuit includes m pieces of EX-OR circuits l-1 to l-m each having two input terminals and one NOR circuit 2 having m pieces of input terminals. The m pairs of bit data (a₁, b₁), (a₂, b₂), (a₃, b₃), ... , (a m , b m ) are supplied to the EX-OR circuits l-1 to l-m, respectively. The outputs e₁, e₂, e₃, ... , e m of the EX-OR circuits l-1 to l-m are supplied to the input terminals of the NOR circuit 2, respectively. When the respective pairs of bits data (a₁, b₁) to (a₁, b m ) are equal in the logic level with each other, all the outputs e₁ to e m take a low level. As a result, the NOR circuit produces an output signals Y of a high level. If any one of m pairs of bit data (a₁, b₁) to (a m , b m ) are unequal in the logic level, at least one of the EX-OR circuits l-1 to l-m produces its outputs of the high level to change the output Y of the NOR circuit 2 to the low level. This prior art circuit thus compares two digital data signals A and B, but requires m pieces of EX-OR circuits l-1 to l-m and one NOR circuit 2 having m pieces of input terminals. As well-known in the art and shown in Figs. 2A and 2B, in a complementary logic circuit technique, one EX-OR circuit is constituted by five P-channel insulated gate transistors Q₁ to Q₅ and five N-channel insulated gate transistors Q₆ to Q₁₀, and the NOR circuit having m pieces of input terminals is constituted by m pieces of N-channel insulated gate transistors Q₁₁ to Q 1m and m pieces of P-channel insulated gate transistors Q₂₁ to Q 2m . As a result, the circuit shown in Fig. 1 requires (10 x m + 2 x m) pieces of transistors. Assuming that each of the digital signals A and B has 10 bit data, the circuit explained above requires at least 120 transistors. In the case where the circuit shown in Fig. 1 is formed as an integrated circuit device, the chip area occupied by the circuit is remarkably large. Moreover, the internal wiring pattern is complicated due to the interconnection of a great number of transistors, and the stray capacitances are also made large to lower the operation speed. Particularly, the input gate capacitance of the NOR circuit 2 is considerably large since the NOR circuit 2 has a plurality of input terminals. For this reason, the operation speed at the NOR circuit 2 is very slow. These disadvantages become more serious as the number of the bits is increased. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 3, there is shown a digital data comparison circuit according to an embodiment of the present invention. This circuit is formed as an integrated circuit device and constituted by complementary insulated gate field effect transistors including a first channel type or a first conductivity type (P-channel type, for example) MOS (Metal-Oxide-Semiconductor) transistors and a second channel type or a second conductivity type (N-channel type) MOS transistors. A first digital signal A consisting of m -bit data a₁, a₂, a₃, ... and a m is supplied to a set of first input terminals 20-1, 20-2, 20-3, ... and 20-m, and a second digital signal B consisting of m -bit data b₁, b₂, b₃, ... and b m is supplied to another set of second input terminals 21-1, 21-2, 21-3, ... and 21-m. The first and m-th bit data a₁ and a m correspond to the least and most significant bits of the signal A, respectively, and bit data b₁ and b m correspond to the least and most significant bits of the signal B. All the bit data b₁ to b m are inverted by inverter circuits 32-1 to 32-m, respectively, each of which includes a P-channel MOS transistor Q₄₂₋₁, Q₄₂₋₂, Q₄₂₋₃, ... or Q 42-m and an N-channel MOS transistor Q₄₃₋₁, Q₄₃₋₂, Q₄₃₋₃, ... or Q 43-m connected in series between first and second power potential terminals 24 and 25. The first potential terminal 24 is applied with a first power potential V DD (a positive potential in the embodiment), and a second power potential V SS (a ground potential in the embodiment) is applied to the terminal 25. M pieces of first series circuits 30-1, 30-2, 30-3, ... and 30-m are provided, each of which includes two P-channel MOS transistors Q₃₀₋₁ and Q₃₁₋₁, Q₃₀₋₂ and Q₃₁₋₂, ... or Q 30-m and Q 31-m connected between the first potential terminal 24 and a first output node N₀₁. Further, m pieces of second series circuits 31-1, 31-2, 31-3, ... and 31-m are connected in parallel between the second potential terminal 25 and a second output node N₀₂, each of which includes two N-channel MOS transistors Q₃₂₋₁ and Q₃₃₋₁, Q₃₂₋₂ and Q₃₃₋₂, ... or Q 32-m and Q 33-m . The gates of the transistors Q₃₀₋₁ to Q 30-m are connected to those of the transistors Q 32-1 to Q 32-m , respectively, and further connected to the first input terminals 20-1 to 20-m, respectively. The outputs of the inverter circuits 32-1 to 32-m are connected to the gates of the transistors Q₃₁₋₁ to Q 31-m , respectively, and further connected to those of the transistors Q₃₃₋₁ to Q 33-m , respectively. A P-channel MOS transistor Q₃₄ is connected between the first potential terminal 24 and the second output node N₀₂, and an N-channel MOS transistor Q₃₅ is connected between the second potential terminal 25 and the first output node N₀₁. The gates of the transistors Q₃₄ and Q₃₅ are connected to first and second precharge terminals 22 and 23, respectively, which are in turn supplied with first and second precharge signals P and P , respectively. The first output node N₀₂ is connected to the first input terminal of an NOR circuit 34 whose second input terminal is connected to the second output node N₀₂ through an inverter circuit 33. The NOR circuit 34 includes two P-channel MOS transistors Q₃₈ and Q₃₉ connected in series between the first potential terminal 24 and an output terminal 26 and two N-channel transistors Q₄₀ and Q₄₁ connected in parallel between the output terminal 26 and the second potential terminal 25. A detection output signal Y is derived from the output terminal 26. The inverter 33 includes a P-channel MOS transistor Q₃₆ and an N-channel MOS transistor Q₃₇ connected in series between the first and second power potential terminals 24 and 25. The circuit operation of the comparison circuit shown in Fig. 3 will be described with reference to Fig. 4. For the purpose of presetting initial logic levels at the respective circuit nodes, a controller (not shown) clamps all the input terminals 20-1 to 20-m and 21-1 to 21-m to a low level. The inverters 32-1 to 32-m thereby produce a high level at their outputs, respectively. Accordingly, the transistors Q₃₀₋₁ to Q 30-m and Q₃₃₋₁ to Q 33-m are turned ON, but the transistors Q₃₁₋₁ to Q 31-m and Q₃₂₋₁ to Q 32-m are turned OFF. At this time, the controller further supplies the low level and the high level to the precharge terminals P and P , respectively. The transistors Q₃₄ and Q₃₅ are thereby turned ON to charge the output nodes N₀₂ and N₀₁ to the high level and the low level, respectively. This cause the transistors Q₃₇ to Q₃₉ to turn ON. As a result, the output signal Y takes the high level. In order to compare the binary coded digital signals A and B, the precharge terminals P and P are changed to the high level and the low level to turn the transistors Q₃₄ and Q₃₅ OFF, respectively. Simultaneously with this, the digital signals A and B are supplied to the first and second sets of input terminals (20-1 to 20-m) and (21-1 to 21-m), respectively. If desired, the signals A and B may be supplied after the precharge terminals P and P are changed to the high level and the low level. As shown in the situation (1) in Fig. 4, the first digital signal A is supplied in which only the third bit data a₃ is "0" (i.e., the low level) and the remaining bit data are "1" (the high level). The P-channel transistor Q₃₀₋₃ and the N-channel transistors Q₃₂₋₁ to Q 32-m are thereby turned ON. All the bit data b₁ to b m of the signal digital signal B are "1". The outputs of the inverters 32-1 to 32-m are thereby changed to the low level to turn the transistors Q₃₁₋₁ to Q 31-m ON. In other words, both of the transistors Q₃₀₋₃ and Q₃₁₋₃ connected in series between the terminal 24 and the output node N₀₁ are turned ON in response to the signals A and B shown in the situation (1) in Fig. 4. As a result, the output node N₀₁ is charged to the high level. This causes the transistors Q₃₈ and Q₄₁ to turn OFF and ON, respectively. The output signal Y is thus changed to the low level. If both of the third bit data a₃ and b₃ of the signals A and B are "0" as shown in the situation (2) is Fig. 4, the inverter 32-3 does not turn the transistor Q₃₁₋₃ ON, and Q₃₁₋₃ is maintained in the OFF-state. The signal B has the m-th bit data bm of "0", however. Therefore, the transistor Q 33-m is turned ON. The second output node N₀₂ is thus discharged to the low level. This causes the transistors Q₃₆ and Q₄₀ to turn ON and the transistor Q₃₉ to turn OFF. As a result, the output signal Y takes the low level. Thus, when any one of the bit data of the first signal A is different in the logic level from the corresponding bit data of the second signal B, at least one pair of the P-channel transistors Q₃₀ and Q₃₁ and/or at least one pair of the N-channel transistors Q₃₂ and Q₃₃ are turned ON to change the logic levels at the output node N₀₁ and/or N₀₂. The output signal Y thus changes to the low level. When only the third bit data a₃ and b₃ of the signals A and B are "0" as shown in the situation (3) in Fig. 4, the P-channel transistors Q₃₀₋₃, Q₃₁₋₁, Q₃₁₋₂, and Q₃₁₋₄ to Q 31-m and the N-channel transistors Q₃₁₋₁, Q₃₂₋₂, Q₃₂₋₄ to Q 32-m , and Q₃₃₋₃ are turned ON, and the P-channel transistors Q₃₀₋₁, Q₃₀₋₂, Q₃₀₋₄ to Q 30-m , and Q₃₁₋₃ and the N-channel transistors Q₃₂₋₃, Q₃₃₋₁, Q₃₂₋₂, and Q₃₃₋₄ to Q 33-m are turned OFF. Accordingly, the levels at the output nodes N₀₁ and N₀₂ are held to maintain the output signal Y at the high level. In other words, either one of the series connected P-channel transistors Q₃₀ and Q₃₁ and either one of the series connected N-channel transistors Q₃₁ and Q₃₃ are maintained in the OFF-state when each bit data of the signal A equals in the logic level to the corresponding bit data of the signal B, and the output signal Y maintains to take the high level. The gates cf the transistors Q₃₄ and Q₃₅ may be connected to the terminals 25 and 24, respectively, to maintain them in the ON-state. In this case, the current capacity of the transistor Q₃₄ should be smaller than the series connected transistors Q₃₂ and Q₃₄ to change the level at the node N₀₂. Similarly, the current capacity of the transistor Q₃₅ should be smaller than the series connected transistors Q₃₀ and Q₃₁ to change the level at the node N₀₁. Fig. 5 shows an output section according to another embodiment of the present invention, in which the first output node N₀₁ is connected through an inverter 40 to the first input end of an NAND circuit 45 and the second output node N₀₂ is connected to the second input end of the NAND circuit 45. The inverter 40 includes a P-channel MOS transistor Q₅₀ and an N-channel MOS transistor Q₅₁ connected in series between the power potential terminals 24 and 25. The NOR circuit includes two p-channel MOS transistors Q₅₂ and Q₅₃ connected in parallel between the terminal 24 and the output terminal 26 and two N-channel MOS transistors Q₅₄ and Q₅₅ connected in series between the output terminal 26 and the potential terminal 25. In the initial condition, the levels at the nodes N₀₁ and N₀₂ are the low level and the high level, respectively, and therefore, the output signal Y takes the low level. When each bit data of the signal A is not equal in the logic level to the corresponding bit data of the signal B, at least one of the P-channel transistors Q₅₂ and Q₅₃ is turned ON and at least one of the N-channel transistors Q₅₄ and Q₅₅ is turned OFF. As a result, the output signal Y takes the high level. When the data of the respective bits of the signal A are equal in the logic level to those of the corresponding ones of the signal B, the output signal Y maintains to take the low level. As described above in detail, the digital data comparison circuit according to the present invention detects the coincidence between the respective bit data of two signals A and B, and is constituted by a smaller number of transistors. The number of the transistors required is (4 x m + 2 x m + 8) in a total, where m is the number of bits of each of signals A and B. If m is 10, the number of transistors is 68 (= 4 x 10 + 2 x 10 + 8). Since the circuit according to the present invention is constituted by a smaller number of transistors, the wiring pattern on the semiconductor chip is simplified and the stray capacitance is made small, resulting in a high speed operation. The small number of transistors consume a small quality of power.

Claims: A data comparison circuit comprising first and second potential terminals (24, 25), first and second output nodes (NO1, NO2), at least one first series circuit connected between said first potential terminal (24) and said first output node (NO1) and including first and second transistors (Q30-, Q31-) of first conductivity type connected in series, at least one second series circuit connected between said second potential terminal (25) and said second output node (NO2) and including third and fourth (Q32-, Q33-) transistors of second conductivity type connected in series, first means for supplying a first digital signal (A) to control electrodes of said first and third transistors, second means for supplying a second digital signal (B) to control electrodes of said second and fourth transistors, third means (22, 23) for precharging said first and second output nodes to different logic levels from each other, and fourth means (34) for detecting a change in the level of at least one of said first and second output nodes. The data comparison circuit as claimed in claim 1, wherein said second means includes means for inverting said second digital signal (B) and means for supplying to said second and fourth transistors the inverted signal of said second digital signal. The data comparison circuit as claimed in claim 1 or 2, wherein said third means includes a fifth transistor (Q34) connected between said first potential terminal (24) and said second output node (NO2) and controlled by a precharge signal (P) and a sixth transistor (Q35) connected between said second potential terminal (26) and said first output node (NO1) and controlled by an inverted signal ( P ) of said precharge signal. The data comparison circuit according to claim 3, wherein said first means comprises a plurality of first input terminals (20-1, ..., 20-m) supplied with each bit data (a1, ..., am) of said first digital signal (x), respectively; said second means comprises a plurality of second input terminals (21-1, ..., 21-m) supplied with each bit data (b1, ..., bm) of said second digital signal (B), respectively; said inverting means comprises a plurality of inverting circuits (32-1, ..., 32-m) whose input ends are connected to said second input terminals, respectively; said first to sixth transistors are field effect transistors and pluralities of said first to fourth transistors are provided, wherein said first field effect transistors (Q30-1, ..., Q30-m) are of a first channel type and connected with their gates to said first input terminals, said second field effect transistors (Q31-1, ..., Q31-m) are of said first channel type and connected with their gates to output ends of said inverter circuits, respectively, said third field effect transistors (Q32-1, ..., Q32-m) are of a second channel type and connected with their gates to said first input terminals, respectively, said fourth field effect transistors (Q33-1, ..., Q33-m) are of a second channel type and connected with their gates to the output ends of said inverter circuits, respectively, said fifth field effect transistor (Q34) is of said first channel type and connected with its gate to said first precharge terminal and wherein said sixth field effect transistor (Q36) is of said second channel type and connected with its gate to said second precharge terminal. The data comparison circuit as claimed in claim 4, wherein said output circuit includes an additional inverter circuit (33) and an NOR circuit (34) having two input ends and an output end connected to an output terminal (26), said first output node (NO1) being connected to one input end of said NOR circuit (34), and said second output node (NO2) being connected to the other input end of said NOR circuit (34) through said additional inverter circuit (33). The data comparison circuit as claimed in claim 4, where said output circuit includes an additional inverter circuit (40) and an NAND circuit (45) having a first input end connected through said additional inverter circuit (40) to said first output node (NO1), a second input end connected to said second output node (NO2), and an output end connected to an output terminal (26). The data comparison circuit as claimed in claim 4, wherein each of said inverter circuits (Q32-1, ..., Q32-m) includes a seventh transistor (Q42-1, ..., Q42-m) of said first channel type and an eighth transistor (Q43-1, ..., Q43-m) of said second channel type connected in series between said first and second potential terminals.

Inventors: MORITO, HIROSHI C/O NEC CORP., SHIMADA, JIROH C/O NEC CORP.
Applicants: NEC CORPORATION
Application year: 1984
Main classification: G06F7
IPC codes: G06F7, H03K19