HIGH-BANDWIDTH, HIGH RADIANCE, SURFACE EMITTING LED, AND METHOD THEREFOR

Abstract: An LED including a substrate (200) with an elevated surface portion (204), an epitaxial blocking layer (201) adjacent thereto, and a doubleheterojunction structure (203, 206, 208, 209) thereover, and a method of manufacturing such a device.

Description: HIGH-BANDWIDTH, HIGH RADIANCE, SURFACE EMITTING LED, AND METHOD THEREFOR The present invention relates to light emitting _ diodes (LED's) and more specifically to improved double heterojunction LED's. BACKGROUND OF THE INVENTION Figures 1A and IB illustrate a typical method of manufacturing a double heterojunction LED of the prior art and the structure of such a prior art LED. Turning first to Figure 1A, a substrate 100 of GaAs is doped to have a p+ type conductivity. On a major surface of substrate 100 an epitaxial layer 101 of GaAs, doped to have an n type conductivity, is formed. A masking layer 102 is then formed on epitaxial layer 101. Typically masking layer 102 is formed by placing a. uniform layer of a photosensitive resist material on epitaxial layer 101. Photoresist 102 may then be exposed and developed leaving the resist material covering those regions of epitaxial layer 101 to be retained while leaving exposed those regions of. epitaxial layer 101 which are to be removed by etching. The assembly is then subjected to an etching step which removes unprotected portions of epitaxial layer 101. Following the etching step resist layer 102 is completely removed and the exposed surface of epitaxial layer 101 carefully cleaned to remove the resist material and the etchant. Turning now to Figure IB an epitaxial layer of Al j -Ga _ x As doped to have a p type conductivity 103 is formed on the exposed surface of n type epitaxial layer 101. When epitaxial layer 103 is grown the gap formed in epitaxial layer 101 by etching will be filled creating p type region 104. The upper surface 105 of * epitaxial layer 103 will be substantially, but not completely, planer. In particular, in the region directly over region 104 a small depression will exist due to incomplete filling of region 104. Another p type epitaxial layer 106 Al x Gaι_ x As is then formed on surface 105 of epitaxial layer 103. Epitaxial layer 106 will form the active layer of the LED when construction of the LED is completed. In particular, region 107, indicated by crosshatching, forms the active region of the device. The crosshatching is intended to show where the recombination, and thus light production, will take place, but does not indicate any difference in doping levels between the active region 107 and the rest of active layer 106. An n type epitaxial layer 108 of Al x Gaχ_ x As is formed over layer 107. An n type epitaxial layer 109 of GaAs is formed over layer 108. A portion of epitaxial layer 109 directly over active region 107 is etched away in order to allow light produced in active region 107 to escape. In operation, epitaxial layer 109 serves as a capping layer and is primarily provided to allow good electrical contact with other circuitry. Epitaxial layers 108 and 103 each serve as confining layers, meaning that they tend to hold charge carriers in active layer 106 until recombination occurs. Epitaxial layer 106 acts as the active layer as described above. Epitaxial layer 101 is commonly known as a blocking layer because, during normal operation of the device, a reverse biased p-n junction exists between regions 101 and 103. Thus, current flowing from region 103 to substrate 100 must flow through region 104. It is this limitation of current flow to region 104 that limits the active region to region 107 of active layer 106. Substrate 100 acts to provide electrical contact to other circuitry and to provide structural integrity to the device. The effective modulation bandwidth of the prior art LED shown in Figure 2B is limited by the series resistance presented by regions 100 and 104 and by the minority carrier lifetime in active region 107. The minority carrier lifetime may ' be reduced, thus increasing the modulation bandwidth of the device, by either increasing the doping level in active region 107 or by reducing the size of active region 107. If the doping level in active region 107 is increased to too high of a level an excessive number of non-radiative centers are formed therein and the increase in modulation bandwidth is accompanied by a decrease in quantum efficiency. Therefore, a preferable way of decreasing minority carrier lifetime in active region 107, and thus increasing the modulation bandwidth of the device, would be to reduce the size of active region 107. A second difficulty with the prior art process as described above is that both the thickness of n type epitaxial layer 101 and the etching to form region 104 must be very carefully controlled. If the etching does not form a gap all of the way through layer 101 a reverse biased p-n junction will be formed between region 104 and region 101, at worst preventing effective current flow between region 103 and region 100 and at best substantially increasing the series resistance of the device. Clearly this would prevent proper operation of the LED. Alternatively, if the well etched to form region 104 is very deep, p type epitaxial layer 103 must be very thick in order to insure that region 104 will be completely filled. If epitaxial layer 103 is thick the series resistance of the LED will be substantially increased. in order to keep the well depth as shallow as possible, layer 101 is typically in the range of two to three microns thick. Smaller dimensions for layer 101 may be insufficient to perform the required current blocking. Because etching proceeds laterally as well as vertically the minimum thickness for layer 101 tends to set a minimum width for region 104. Additionally if the aspect ratio, i.e. ratio of the height to the width, of an etched well is too great, liquid phase epitaxial growth in that well will be difficult. This phenomenon further limits the minimum width of region 104 and hence of active region 107. At the same time the fact that epitaxial layer 101 is only two to three microns thick prevents a thorough cleaning job on the surface of that region subsequent to the removal of resist mask 102 but prior to growth of subsequent epitaxial layers because cleaning could damage such a thin layer. Various contaminants left on the surface of region 101 may have a deleterious effect on the quality of epitaxial layers grown thereon. SUMMARY QF THE INVENTION In the present invention a first major surface of a . substrate of semiconductor material, preferably GaAs, is etched so that the substrate is reduced in thickness in all but one or more selected portions. After the etching, the selected portions may be considered to be elevated regions with respect to the remainder of the new surface of the substrate. In a preferred embodiment each selected portion is circular in shape. A semiconductor layer, preferably GaAs, is produced by epitaxial growth techniques on the new surface produced by the etching. The surface of this epitaxial layer should be at the same level as or slightly higher than the level of the elevated portions. A small portion of the epitaxial layer is removed, either by etching or by melt back, so that the surfaces of the elevated portions are exposed. A series of epitaxial layers of semiconductor material, " preferably Al x Ga _. x As are then grown to form a double heterojunction structure. The value of x will commonly vary from layer to layer. Typically a GaAs capping layer is then added to help improve electrical contact. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A and IB show a prior art process for making a double heterojunction LED and a cross-section of the LED thus manufactured; Figures 2A, 2B, 2C, and 2D illustrate the process of making the LED of the invention and the LED thus manufactured; and Figure - 3 is a perspective view of a semiconductor substrate with an elevated portion such as would be formed during the processing of an LED of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Those skilled in the art will realize that LED's such as the LED of the invention are typically produced in arrays with a plurality of such LED's being produced on a single semiconductor substrate. Each individual LED is produced simultaneously using the same process, however, so the process of the present invention will be described with respect to only a single LED. Turning now to Figure 2A, a semiconductor substrate 200, preferably of GaAs doped to have p+ type conductivity, has an etching mask 202 thereon. Typically the etching mask is a developed photosensitive resist material. The substrate is then subjected to an etching process which reduces the height of the substrate in all areas other than those protected by the etching mask. The etching mask is then removed and the surface of the substrate is thoroughly cleaned. The effect of the etching process is to leave a primary surface portion in those regions of the substrate where etching occurred and elevated surface portions in those regions of the substrate protected by the etching mask. Preferably th_ese elevated portions are circular in shape. Figure 3 illustrates substrate 200 with elevated portion 204, following the etching process and removal of the etching mask. As shown in Figure 2B an epitaxial layer 201 of semiconductor material, preferably GaAs doped to have n type conductivity, is then grown on the surface formed by the etching process. Preferably epitaxial layer 201 is grown by known techniques of liquid phase epitaxy. As shown in Figure 2B epitaxial layer 201 slightly covers the top of elevated portion 204. • Preferably epitaxial layer 201 extends approximately 0.1 μm over elevated portion 204. Following the growth of epitaxial layer 201 the surface thereof is subjected to an etching process in order to expose elevated portion 204 and to produce an essentially planer surface. Typically the entire exposed surface of epitaxial layer 201 is to be etched, so no etching mask is required. After the etching the surface thus produced is thoroughly cleaned to remove all contaminants from the etching process. When the surface is sufficiently cleaned, epitaxial layer 203, preferably of A1.2 Ga .8 As doped to have p type conductivity, is grown thereon. Next the active layer, P type epitaxial layer 206, is grown on epitaxial layer 203. Preferably active layer 206 is of Al .025 Ga .975 As « An n type epitaxial confining layer 208, preferably of A1.2 Ga .8 As ' * s °e t grown, followed by the growth of n type epitaxial capping layer 209 of GaAs. Each of layers 203, 206, 208, and 209 are preferably grown by known techniques of liquid phase epitaxy. Although the compositions described above are preferred, those skilled in the art will perceive that a variation in the aluminum to gallium ratio will not prevent operation of the device, but will merely shift the frequency of emitted . radiation. Furthermore other III-V semiconductor materials may be used within the scope of the invention. Figure 2D illustrates a completed LED of the invention. Epitaxial capping layer 209 is etched to form a gap overlying elevated region 204. Metallic electrical contact areas 210 and 211 are formed on capping layer 209 and substrate 200 respectively. Finally, spherical microlens 212 is attached to the device as shown. As in the prior art LED of Figure IB active region 207 of the LED of Figure 2D is indicated by crosshatching. Again, as in Figure IB, this crosshatching does not indicate any difference in the composition or the doping level of region 207, as compared with the rest of active layer 206, but merely indicates that this is the area where recombination occurs and light is emitted. The LED of the invention provides numerous advantages as compared with the prior art LED's for several reasons. Because elevated region 204 is of the substrate material, which is more heavily doped than the material forming region 104 of Figure IB, a lower series resistance is provided. Second, after each etching step a more thorough cleaning process may be performed without fear of entirely removing a necessary layer, thereby reducing contamination and dislocations in the subsequently grown epitaxial layers.. Third, the size of active region 207 may be reduced in both the lateral and transverse dimensions as compared with active region 107 of the LED of Figure IB. In the transverse dimension it may be reduced in size because epitaxial layer 206 is grown on a planer surface rather than a surface with a slight well as in the prior art. In the lateral dimension the size may be reduced because the lateral dimension of region 204 may be made smaller than the comparable lateral dimension of region 104 of the device of Figure IB. Therefore, the modulation bandwidth of the device may be increased both due to decreased series resistance of the device and due to a reduced size active region. At the same time the improved cleaning provides a greater reliability in the manufacturing process. In an alternative embodiment of the manufacturing process described above elevated region 204 is prepared as it was previously. Epitaxial region 201 is then grown, forming the structure shown in Figure 2B. Rather than etching epitaxial layer 201 to expose elevated region 204, however, the surface of layer 201 is immersed in a GaAs melt which is slightly undersaturated with As. Such immersion will melt back a portion of epitaxial layer 201 in order to expose region 204. Thus when layer 203 is grown an electrical contact will be formed between epitaxial layer 203 and region 204. The processing then proceeds exactly as before to form the final structure of. Figure 2D. This alternative procedure provides the advantage that the processing may continue uninterrupted by the etching step thereby decreasing the number of process steps required. Furthermore, there is no possibility of etching contaminants being introduced into the system due to the etching of layer 201 because no such etching occurs. Finally, atmospheric contamination is also reduced because the device need not be removed from the epitaxial growth chamber and exposed to the atmosphere between epitaxial growth steps.

Claims: The embodiments of the invention in which an exclusive property or right is claimed are defined as follows: 1. A double heterojunction light emitting diode comprising: a substrate region of a semiconductor material having a first conductivity type, said substrate region having a primary surface portion and an elevated surface portion; a first layer of a semiconductor material having a second conductivity type, said first layer overlying said substrate primary surface portion and forming a substantially planar surface with said substrate elevated surface portion; a second layer of semiconductor material having said first conductivity type, said second layer overlying said first layer and said substrate elevated surface portion; a third ' layer of semiconductor material having said first, conductivity type said third layer overlying said second layer; a fourth layer of semiconductor material having said second conductivity type, said fourth layer overlying said third layer; a fifth layer of semiconductor material having said second conductivity type, said fifth layer overlying said fourth layer. 2. The light emitting diode of clai 1 wherein said first conductivity type is p type and said second conductivity type is n type. 3. The light emitting diode of claim 1 wherein said substrate,said first layer, and said fifth layer each comprise GaAs, and said second layer, said third layer, and said fourth layer each comprise Al x Gaι_. x As. 4. The light emitting diode of claim 3 wherein said first conductivity type is p type and said second conductivity type is n type. 5. The light emitting diode of claim 4 wherein said substrate elevated surface portion is circular. 6. The light emitting diode of claim 5 wherein said second and fourth epitaxial layers comprise Al # 2Ga # 8As and said third epitaxial layer comprises A1.025 Ga .975 As * 7.. The light emitting diode of claim 5 wherein said fourth epitaxial layer has a first major surface adjacent to said fifth epitaxial layer, said fifth epitaxial layer covering a first portion of said fourth epitaxial layer first major surface and leaving exposed a second portion of said fourth epitaxial layer first major surface, said fourth epitaxial layer first major surface second portion being juxtaposed to said substrate elevated surface portion. 8. A method of manufacturing a double heterojunction light emitting diode, said method comprising the steps of: etching a first major surface of a semiconductor substrate having a first conductivity type so as to form a primary surface portion and an elevated surface portion; forming a substantially planar surface including an exposed surface of a first epitaxial layer of a second conductivity type and said substrate elevated portion; growing a second epitaxial layer of semiconductor material of said first conductivity type on said substantially planar surface; growing a third epitaxial layer of a semiconductor material of said first conductivity type on said second epitaxial layer; growing a fourth epi-taxial layer of a semiconductor material of said second conductivity type on said third epitaxial layer; and growing a fifth epitaxial layer of a semiconductor material of said second conductivity type on said fourth epitaxial layer. 9. " The method of claim 8 wherein said step of forming said substantially planar surface includes the steps of: growing said first epitaxial layer on said substrate 5 primary surface portion, said first epitaxial layer being grown to a height such that said semiconductor substrate elevated surface portion is covered; and etching said " first epitaxial layer to form said Q substantially planar surface. 10. The method of claim 9 wherein said first conductivity type is p type and said second conductivity type is n type. 11. The method of claim 9 wherein said substrate, 5 said first epitaxial layer, and said fifth epitaxial layer each comprise GaAs, and said second epitaxial layer, said third epitaxial layer, and said fourth epitaxial layer each comprise Al x Gaχ_. x As. 12. The method of claim 11 wherein said second epitaxial layer and said fourth epitaxial layer comprise Al # 2 Ga .8 As and said third epitaxial layer comprises A1 .025 Ga .975 As - 13. The method of claim 12 wherein each of said epitaxial layers is formed by means of liquid phase • epitaxy. 14.- The method of claim 13 wherein, said first conductivity type is p type and said second conductivity type is n type. 15. The method of claim 16 wherein said second and fourth epitaxial layers comprise A1.2 Ga .8 As anc = said third epitaxial layer comprises Al # 025 Ga .975 As « 16. The method of claim 8 wherein said step of forming said substantially planar surface includes the steps of: growing said first epitaxial layer on said substrate primary surface portion, said first epitaxial layer being grown to a height such that said semiconductor substrate elevated surface portion is covered; and melting back said first epitaxial layer in order to expose said elevated surface portion and to form said substantially planar surface, said melting back being accomplished by immersing at least a portion of said first epitaxial layer in a GaAs melt, said melt being undersaturated with As. 17. The method of claim 16 wherein said first conductivity type is p type and said second conductivity type is n type. 18. The method of claim 17 wherein said substrate, said first epitaxial layer, and said fifth epitaxial layer each comprise GaAs, and said second epitaxial layer, said third epitaxial layer, and said fourth epitaxial layer each comprise Al x Ga __ x As. 19. The method of claim 18 wherein said second epitaxial layer and said fourth epitaxial layer comprise Al # 2 Ga .8 As and said third epitaxial layer comprise A 1.025 Ga .975 As - 20. The method of claim 19 wherein each of said epitaxial layers is formed by means of liquid phase epitaxy. 21. The method of claim 20 wherein said first conductivity type is p type and said second conductivity type is n type. 22. The method of claim 21 wherein- said second and fourth epitaxial layers comprise Al # 2 G .8 As anc = said third epitaxial layer comprises Al Q25 Ga .975 As *

Inventors: PLASTER JAMES L, PLASTER, JAMES, L.
Applicants: HONEYWELL INC, HONEYWELL INC.
Application year: 1984
Main classification: H01S3
IPC codes: H01L21, H01L33