Method and apparatus for decoding error correction code

Abstract: In method for decoding error correction code in which a first correction code of (n₁, k₁) (where n₁ denotes the code length) is encoded for every k₁ information symbols arranged in each column and a second error correction code of (n₂, k₂) (where n₂ denotes the code length) are encoded for every k₂ information symbols arranged in each row of a two dimentional arrangement of (k₁ X k₂), a first pointer formed by decoding the first error correction code is stored in a memory having n₂ bits, a second pointer formed by decoding the second error correction code is stored in a memory having k₂ bits. When the second error correction code is decoded, an erasure correction is made with respect to each of the code series of the second error correction code by employing the first pointer and a part of the calculation for obtaining an error value in this erasure correction may be carried out only once with respect to each of the code series of the second error correction code.

Description: TECHNICAL FIELD This invention relates to a method and an apparatus for decoding error correction code. BACKGROUND ART Product code are well known such that information symbols are arranged in two-dimensional form, error correction codes are encoded for each row and column of the two-dimensional arrangement so that each information symbol is included in two error correction code series. In decoding the product code, the error correction code is decoded for each column and error correction code can be decoded for each row by employing the decoding information. The decoding information is called a pointer. In the conventional methods since each information symbol is associated with a pointer, it is required that the total number of pointers is at least equal to the number of information symbols. Further, in the case where erasure correction is made by employing the pointers, since the pointers are read out from a pointer memory and the error value is calculated for every row, there exists a problem in that the number of processing steps such as memory accesses, calculations and so on inevitably increases. On the other hand, in the case where complicated codes such as BCH codes are employed as error correction codes, since the operations for obtaining error values become inevitably complicated, there exists a problem in that a great number of program steps are required in the case where the calculations are implemented by hardware. IBM Technical Disclosure Bulletin, Vol. 17, No. 2, July 1974, pages 473-475 discloses an error correction system for taped data in which error pointers from column decoding are used in error correction of rows of the data. EP-A-0096109 (Tokyo Shibaura Denki K.K.) is part of the state of the art by virtue of Article 54(3) E.P.C. and discloses a decoding method using a single Reed-Solomon-Code. GB-A- 210749 discloses an error flag decoder in which the storage required for error flags can be reduced by use of a read address counter and frame read counter set with a particular offset and in which error flags can be stored in parity bits for a preceding frame. IEEE Transactions on Information Theory, Vol. 18, n°1, January 1972, pages 182-185, entitled "Random error and burst correction by iterated codes" by S.M. REDDY et al. describes in paragraph II thereof a method for decoding a product code of C1 (n1,k1) and C2 (n2,k2) Reed-Solomon codes. C1 decoding is first performed and a weight estimating the confidence of the correction is assigned to each column. The positions corresponding to the columns of lowest confidence are considered as erasures and a errors-and-erasures Forney decoding of the C2 codes is then performed on the rows. An object of this invention is to provide a method and an apparatus for decoding error correction codes which can reduce the number of pointers required in decoding as well as reducing the number of memory regions for the pointers and the number of times the pointers need to be read and written to. Another object of this invention is to provide a method and an apparatus for decoding error correction code which can markedly reduce the number of processing steps in dependence upon the fact that the pointers with respect to each row are the same. Still another object of this invention is to provide an apparatus for decoding error correction codes which can reduce the number of calculating steps in an erasure correction. A further object of this invention is to provide a method for decoding error correction codes which can obtain error values in decoding having a simple construction and a small number of processing steps. According to the present invention there is provided a method for decoding a product error correction code as defined in claim 1. The invention also provides an apparatus for decoding a product error correction code as defined in claim 2. Further, in the present invention, paying attention to the fact that in linear non-dualistic code having a root of 1, one of the syndromes is an addition of (mod. 2) of a received symbol series, the apparatus for decoding error correction code can store a syndrome in a syndrome register and form an error value with respect to a single symbol by subtracting other error values from a value stored in the syndrome register in correcting a plurality of erroneous symbols. The invention will be further described by way of non-limitative example with reference to the accompanying drawings in which:- Fig. 1 is a schematic block diagram of an encoder according to an embodiment of the present invention. Fig. 2 is a schematic block diagram showing the operation of an embodiment of the present invention. Fig. 3 is a schematic block diagram showing a decoder according to one embodiment of this invention. Fig. 4 is a block diagram showing an error correcting decoder according to Figure 3. Fig. 5 is a block diagram of a part of the error location and error value calculating circuit of Figure 4. Fig. 6 is a block diagram showing a construction of an arrangement for use with this invention. Fig. 7 is a block diagram for the processing circuit of Fig. 6. An embodiment of the present invention will be described, referring to the drawings. Fig. 1 shows a structure of an encoder for product code. The reference numeral 1 denotes an input terminal, the reference numeral 2 denotes a second error correction code C 2 parity generator. The input data from the input terminal 1 is supplied to the C 2 parity generator 2 and one input terminal of a selector 3. The C 2 parity data formed by the C 2 parity generator 2 is supplied to the other input terminal of the selector 3. The selector 3 repeats k 1 times the operations for selecting (n 2 - k 2 ) parity data after k 2 information symbols are selected. During this operation, the information symbols and the parity data are stored in a RAM (Random Access Memory) 4 in sequence under control of an address controller 5. The data read out from the RAM 4 are supplied to a C 1 (the first error correction code) parity generator 6 and one input terminal of a selector 7 and the C 1 parity data formed by the C 1 parity generator 6 is supplied to the other input terminal of the selector 7. The selector 7 selects ((n 1 - k 1 ) x k 2 ) C 1 parity data after having selected (k 1 x n 2 ) symbols including the C 2 parity data. The digital data derived from an output terminal 8 of the selector 7 are transmitted or recorded on a magnetic tape (not shown) with a magnetic head, for instance. In this case, it is possible to write again the encoded output once into the RAM 4 and to read out it in different sequence for recording. Fig. 2 shows a configuration of code formed by the encoder as described above. The information symbols are arranged in two dimensions of (k 1 x k 2 ). The k 2 information symbols in every lateral direction, that is, in every row of the two-dimensional arrangement are subjected to the encoding process for the C 2 code. The k 1 information symbols in every vertical direction, that is, in every column are subjected to the encoding process for the C 1 code. The C 2 parity data is also encoded into the C 1 code. The C 1 code is, for instance, (n 1 , k 1 ) Reed-Solomon code, by which it is possible to correct errors of up to (n 1 - k 1 )/2 symbols. The general method of decoding the Reed-Solomon code will be described. The hamming distance of the (n,k) Reed-Solomon code (where n denotes the code length and k denotes the number of information symbols) on a Galois Field GF(2 m ) can be expressed as (d = n - k + l) and the generator polynomial can be expressed as If the received words are (r 0 , r 1 , r 2 , ..... , r n-1 ), the syndrome can be obtained by operating the following expression: An error location polynomial σ(z) and an error evaluation polynomial ω(z) are obtained by employing the syndrome S j . As to this method, Euclid's mutual division method, Berlekamp's method, Peterson's method and so on have been proposed. By solving σ(z) = 0, the error location X i can be obtained. For this purpose, a Chien search is employed. Then, the error value Y i can be obtained on the basis of the error location X i and the error evaluation polynomial ω(z). The above calculations in the decoding steps are explained with the error location as X i (i = 1, 2, ....., e : e denotes the number of errors), and the error value as Y i . Since the Reed-Solomon code is a linear code, the syndrome can be expressed as: if the syndrome is expressed by a polynomial as: a following expression is obtained: If the error location polynomial and the error evaluation polynomial are defined as ω(z) = σ(z) S(z) then ω(z) can be expressed as The error value Y i can be obtained by substituting X i -1 into z and by transforming the expression as follows: As an example,a (32,24) Reed-solomon code having roots of α 0 to α 7 will be explained. Since this code is (d=8), it is possible to correct errors of up to 4 symbols. If the error locations of the 4 symbols are X 1 to X 4 and the error values are Y 1 to Y 4 , the syndrome is obtained from following expression. Namely, S 0 is as follows among 4 syndromes: Once the error values Y 1 , Y 2 , Y 3 can be obtained, the remaining error value Y 4 is obtained as follows without implementing complicated calculations: Y 4 = S 0 - Y 1 - Y 2 - Y 3 In codes on GF(2 m ), a subtraction is equivalent to an addition of (mod. 2). Fig. 3 shows a configuration of the decoder of this embodiment. In Fig. 3, the reproduced data are supplied from an input terminal designated by the reference numeral 11 and to a C 1 decoder 12. In the C 1 decoder 12, the decoding of the C 1 code is performed. All errors of up to (n 1 - k 1 )/2 symbols are corrected in the C 1 decoding. In the case, however, where the number of errors in a single series of C 1 code is more than or equal to (n 1 - k 1 )/2, the C 1 pointer of this series is set to "1", the other pointers are set to "0". In Figs. 2 and 3, the reference numeral 13 denotes a pointer memory for storing the pointers of the C 1 code, which has n 2 bits. The output of the C 1 decoder 12 is stored temporarily in a RAM 14 in sequence under the control of an address controller 15. The output read out from the RAM 14 is supplied to a C 2 decoder 16 to be subjected to the decoding of the C 2 code. The C 2 decoder 16 is supplied with the C 1 pointer from the pointer memory 13. Since the C 1 pointer is common to the all of K 1 series of C 2 code, it is possible to decode the C 2 code in accordance with the same procedure in each series. The C 2 decoder 16 corrects errors of up to (n 2 - k 2 )/2 symbols and generates one of three kinds of pointers in the C 2 code which are stored in a pointer memory 17. When error correction is perfomed by the C 2 decoder 16, the C 2 pointer with respect to the series is set to "0". When error correction can not be performed by the C 2 decoder 16 and the C 1 pointers are used because of their high reliability (described below), the C 2 pointer is set to "1". When error correction can not be performed by the C 2 decoder 16 and all symbols are determined to be erroneous symbols because of low reliability of the C 1 pointer, the C 2 pointers are set to "2". Therefore, the C 2 pointers have 2 bits and the pointer memory 17 has 2K 1 bits. The pointer memories 13 and 17 are disposed separately from the RAM 14 for storing information symbols and parity data in decoding or may be disposed in common with the RAM 14 by using a part of the memory regions of RAM 14. Without being limited to 1 bit, the C 1 pointer may have 2 bits or more. Further, it is possible to implement the error correction code processing of the C 2 code for the C 1 parity, while providing a C 2 pointer memory of (2n 1 ) bits. The output data of the C 2 decoder 16 is supplied to an interpolation circuit 18 to conceal errors in the symbols which have not been corrected. The interpolation circuit 18 performs the mean value interpolation, for instance. The interpolation circuit 18 is controlled by a control circuit 19 which is supplied with the C 1 pointers and the C 2 pointers from the pointer memories 13 and 17. The output data of the interpolation circuit 18 is derived at an output terminal 20. The control circuit 19 determines by every information symbol whether interpolation is necessary on the basis of the c 1 pointer and c 2 pointer. In Fig. 2, There exist all the combinations of C 1 pointers designated as 13' and C 2 pointers designated as 17'. When the C 2 pointer is "0" irrespective of the fact that the C 1 pointer is "0" or "1", the interpolation circuit 18 does not work. When the C 2 pointer is "1" and the C 1 pointer is "0", since it is determined that the information symbol has no error, no interpolation is done. When the C 2 pointer is "1" and the C 1 pointer is "1", since it is determined that it is an erroneous symbol, the interpolation operation is performed. Further when the C 2 pointer is "2" irrespective of the fact that the C 1 pointer is "0" or "1", since it is determined that it is an erroneous symbol, the interpolation operation is performed. The reliability of the C 1 pointers is evaluated by the C 2 decoder. For instance, if up to 2 symbol errors can be corrected by the C 2 code, and correction by the C 2 code can not be performed in spite of the fact that only one C 1 pointer is "1", it is determined that the reliability of the C 1 pointer is low because the above is abnormal. Even if errors are not corrected by the C 2 code, it is possible to eliminate the necessity of interpolation by providing three kinds 0, 1, 2 of the C 2 pointers and by discriminating the copies of C 1 pointers from all errors. In the above mentioned C 2 decoder 16, when the C 1 pointers are used, erasure correction is made where the total value of the C 1 pointers is less than or equal to (n 2 - k 2 ) and when the erasure correction is made, the C 2 pointer is set to "0". As described above, the decoding of the Reed-Solomon code is performed by calculation of the error location polynomial σ(z) and the error evaluation polynomial ω(z) in every row and by employing the syndrome obtained by n 2 symbols in each row. In the case of erasure correction, since the locations where the C 1 pointers are "1" are determined as the error locations, it is possible to obtain the error value Y i from the error location X i and the error evaluation polynomial ω(z). That is to say, by substituting X i -1 in place of z, Y i can be obtained as follows,as in expression (8): (where i = 1, 2, 3, ...s ; s denotes the number of symbols) in the above expression, the term of denominator can be determined only by the error locations. For instance, provided that the error locations shown by the C 1 pointer are X 1 , X 2 , X 3 , the terms of denominator of the expressions for obtaining the error values Y 1 , Y 2 , Y 3 are Denominator of Y 1 : (1 - X 2 X 1 -1 ) (1 - X 3 X 1 -1 ) Denominator of Y 2 : (1 - X 1 X 2 -1 ) (1 - X 3 X 2 -1 ) Denominator of Y 3 : (1 - X 1 X 3 -1 ) (1 - X 2 X 3 -1 ) Here, the pointers stored in the pointer memory 13 are the same in all the K 1 series of the C 2 code. Therefore, it is sufficient to implement the calculation of the term of the denominator in the above expression to obtain an error value only once with respect to the k i series. Fig. 4 shows the configuration of an error correcting decoder for use with the above mentioned C 1 and C 2 codes. The received data are supplied to an input terminal designated by the reference numeral 21 and supplied to a delay circuit 22 and a syndrome generating circuit 23. The syndromes formed by the syndrome generating circuit 23 are supplied to an error location and error value calculating circuit 24. The error data from the error location and error value calculating circuit 24 are supplied to an exclusive OR gate 25 and added to the received data from the delay circuit 22 in (mod. 2). The received data from the delay circuit 22 and the error corrected data from the exclusive OR gate 25 are supplied to a selector 26. The selector 26 is controlled by the error location data. At the error locations, the output of the exclusive OR gate 25 is selected by the selector 26 to be derived at an output terminal 27 in place of the received data. In the case of an audio PCM signal recording and reproducing apparatus, the reproduced data are once written in a RAM. By use of the data read out from the RAM, the syndrome is generated and on the basis of which the error locations and the error values are calculated. Fig. 5 shows a part of the error location and error value calculating circuit 24. In Fig. 5, the reference numeral 28 denotes a data bus through which data and syndrome and so on are transferred. In Fig. 5, the reference numeral 29 denotes a syndrome register in which the syndrome S 0 is stored through the data bus 28, a bus buffer 30 and an exclusive OR gate 31. the syndrome S 0 has m bits in the case of Reed-Solomon code on GF(2 m ). The syndrome S 0 from the syndrome register 29 is supplied to the exclusive OR gate 31 and the bus buffer 32. When the syndrome S 0 is stored in the syndrome register 29, the obtained error values Y 1 ,Y 2 ,Y 3 are supplied to the exclusive OR gate 31 in sequence from the data bus 28 through the bus buffer 30. Therefore, the output of the exclusive OR gate 31 is (S 0 ⊕ Y 1 ), (S 0 ⊕ Y 1 ⊕ Y 2 ) and (S 0 ⊕ Y 1 ⊕ Y 2 ⊕ Y 3 = Y 4 ). The error value Y 4 is left in the syndrome register 29. The error value Y 4 is outputted to the data bus 28 through the bus buffer 32 to be employed for error correction. Fig. 6 shows another example of hardware for decoding in an erasure correction. A main RAM 35 is connected to the data bus 28 through a writing register 33 and a reading register 34. The syndrome register 29, a working RAM 36 and an operation logic circuit 37 are also provided to the data bus 28. The erasure correction by Reed-Solomon code can be obtained by solving the following n-order linear simultaneous equations in the same way as in expression (2): where, ν = 0 to d - 2 n : Number of erasures X k : Location of kth S ν : Syndrome Y k : Magnitude of error in the erasure of kth d : Minimum distance of code Here, n, X k , S ν , are known, Y k is unknown. To solve the above equation, the following method has been conventionally adopted: if ω(z) = S(z) Λ(z) mod. Z d-1 Y i can be obtained as in expression (8) as follows: In this method, however, if the number of actual calculation steps is counted when d = 9 and n = 8, for instance. (i) Expansion of Λ(z) Number of multiplications : 1 + 2 + ..... + 7 = 28 Number of additions : 1 + 2 + ..... + 7 = 28 (ii) Previous calculations for obtaining the denominator of Number of reciprocals : 1 x 8 = 8 Number of multiplications : (7 + 6) x 8 = 104 Number of additions : 7 x 8 = 56 (iii) Calculations for obtaining ω(z) = S(z) Λ(z), mod. Z 8 Number of multiplications : 1 + 2 + ..... + 7 = 28 Number of additions : 1 + 2 + ..... + 7 = 28 (iv) Calculations for obtaining ω(X i -1 ) Number of reciprocals : 1 x 8 = 8 Number of multiplications : 7 x 8 = 56 Number of additions : 7 x 8 = 56 (v) Calculations for obtaining Y i Number of division : 1 x 8 = 8 When these calculations each need one step, the number of steps is 408 in total. In the circuit shown in Fig. 6, the roots of expression (9) are calculated by: where Λ nij : Coefficient of Z j of ℓ : Any integer more than or equal to 0 which satisfies ℓ ≦ d - n - 1 That is to say, in order to implement erasure correction, ℓ = 0, i = n are substituted into the expression (11) as follows: By this calculation, Y n is obtained and Y n X ν / n is added to each syndrome S as follows: S ν ←S ν + Y n X ν n where ν = 0 to n-2 Since the data at the location X n are correct, the syndrome includes (n-1) erasures. Therefore, by reducing n by 1, Y n-1 can be obtained: By this calculation, Y n-1 is obtained and Y n-1 X ν / n-1 is added to each syndrome S as follows: S ν ←S ν + Y n-1 X ν n-1 where ν = 0 to n-3 By repeating the above, the last remaining erasure Y 1 can be obtained as Y 1 = S 0 As explained above, an erasure correction can be implemented. In this case, the actual number of operation steps is counted in the same way as in the conventional method, provided that d = 9 and n = 8. (i) Expansion of Λ nnj Number of multiplications : 1 + 2 + ..... + 6 = 21 Number of additions : 1 + 2 + ..... + 6 = 21 (ii) Previous calculations for obtaining the denominator of where it is sufficient to obtain only II 3 to II 8 , since II 2 = X 1 + Y 2 = Λ 331 . Number of multiplications : 1 + 2 + ..... + 6 = 21 Number of additions : 1 + 2 + ..... + 6 = 21 (iii) Calculations for obtaining the numerator of Y n Number of multiplications : 7 + 6 + ..... + 1 = 28 Number of additions : 7 + 6 + ..... + 1 = 28 (iv) Calculations for obtaining Y n , since Y 1 = S 0 Number of divisions : 7 (v) S ν ← S ν + Y n X ν n Number of multiplications : 6 + 5 + ..... + 1 = 21 Number of additions : 7 + 6 + ..... + 1 = 28 The number of the above calculations steps is 202 in total. Therefore, in the case of expression (11), it is possible to reduce the number of calculation steps to 50% of the conventional case in the expression (10). Further, in the case where the above mentioned correction code is a product code, provided that 30 symbols are arranged in the vertical direction, 128 symbols are arranged in the lateral direction, the C 1 code is formed to the vertical direction, and the C 2 code is formed to the lateral direction, the erasure corresponds to the location of the C 1 pointers, and the location X k (k=1 to n) is the same in all the C 2 code series. This means that it is possible to previously calculate Λ nnj and in expression (11)' without calculating these terms every C 2 decoding. That is to say, in this example, the above calculation is implemented only once while the C 2 decoding is performed 30 times. Therefore, in the number of the above calculation steps, since the number of the calculations of (i) and (ii) is only once every 30 times of C 2 decoding, provided that the number of steps of (i) and (ii) is 90/30 = 3, the total number of steps is 115. compared with that in the conventional method, where the number of steps in (i) and (ii) is 224/3 = 74.7 and the total number of steps is 191.5, it is possible to reduce the number of steps by about 40%. Accordingly, the method as above described has advantages such that it is possible to markedly reduce the number of calculation steps, processing time, hardware load for processing and so on as compared with the conventional method. Additionaly, although the above calculations are performed by employing the operation logic 37, in the case where, for example, S ν ← S ν + X ν / i Y i is obtained, an arrangement as shown in Fig. 7 is adopted. In Fig. 7, the reference numerals 38, 39, 40 denote registers, the reference numeral 41 denotes an adder, the reference numeral 42 denotes a multiplier, the reference numeral 43 denotes a selector, which are all built in the operation logic 37. In this circuit, [1] S 0 is set to the register 38, Y i is set to the register 39, and x i is set to the register 40, respectively through the data bus 28 from the syndrome register 29 and the working RAM 36 and so on. S 0 + Y i is outputted from the adder 41 to the data bus 28. [2] The content of the multiplier 42, X i Y i , is fedback to the register 39 through the selector 43, and S 1 is set to the register 38 from the data bus 28. Therefore, S 1 + X i Y i is outputted from the adder 41 to the data bus 28. [3] Further, the content of the multiplier 42, X i 2 Y i is fedback to the register 39 through the selector 43, and S 2 is set to the register 38 from the data bus 28. Therefore, S 2 + X i 2 Y i is outputted from the adder 41 to the data bus 28. [4] By repeating the above steps, S 3 + X i 3 Y i , S 4 + X i 4 Y i , .... are obtained sequentially and supplied to the syndrome register 29 through the data bus 28 so as to rewrite each value. The calculations are implemented as described above. In the above explanation, although all of X 1 to X n are assumed as erasures, in the case where X 1 to X n-1 are erasures and X n is an error, it is possible to correct the symbols. In this case, the number of unknown quantity are (n+1) of Y 1 to Y n and X n . X n can be obtained by using the above Λ nnj as follows: Therefore, the unknown quantity are Y 1 to Y n , and thereafter, this unknown quantity can be obtained in the same way as in the erasure correction. For instance, in the case where d = 9 (6 erasures + 1 error) in product code, [1] Check locations of the erasures X 1 , X 2 , ..... , X 6 . [2] Obtain and store Λ nnj , here 21 symbols in total of Λ 221 =X 1 , Λ 331 =Λ 221 +X 2 , Λ 332 =Λ 221 X 2 , ..... , Λ 771 , ..... , Λ 776 . [3] Obtain and store 5 symbols in total of (n = 2 to 6). The above processings are made once for each of the decoding cycles 30 times. [4] Calculate syndromes S 0 to S 7 . [5] Obtain X 7 by an expression as follows: [6] Obtain Y 7 by the following expression and feedback the syndrome Y 7 X 7 : Thereafter, Y 6 to Y 1 (= S 0 ) are sequentially obtained. Although a case where expression (11)' is used is shown in this example, the operation is the same if 1≠10. As described above, it is possible to implement the correction of errors including erasures and one error. In this case, the number of calculation steps can be reduced as in the erasure correction described above. The proof of the above expressions (11) and (12) will be described hereinafter: [Lemma] If Λ nij = [Λ ni (z)] j the following expression is cleary obtained: [Theorem 1] The n-order linear simultaneous equations: (ν = 0 to n-1 : Y i is unknown quantity) has the roots as: (Proof) (Corollary 1) (Proof) It is clearly proved by substituting into the above: [Theorem 2] If X i to X n-1 : Erasure and X n is an error, (Proof) From Corollary 1, Therefore, it is understood from Theorem 1 that errors can be corrected in the erasure correction by use of any of S 1 to S n , S 2 to S n+1 , ..... , S d-1-n to S d-2 among the series cf S 0 to S n-1 . That is, n continuous syndromes are necessary for n erasure corrections, the remaining syndromes are usable for checking, so that n ≦ d-1. Further, to obtain X n from theorem 2, a total of n+1 syndromes of S ℓ to S n+ℓ are necessary, so that n ≦ d-2. In this case, the number of erasures is n-1 ≦ d-3. The remaining syndromes can be used for checking as in the above case. In the conventional method, the pointer areas are required for the total number of data (n 1 , n 2 ) corresponding to the error correction code. According to the present invention, however it is possible to reduce the number of pointers to (n 2 + 2n 1 ) and further to reduce the capacity of the memory required in decoding Further, according to the present invention, it is possible to reduce the number of steps for writing or reading the pointers. Further, according to the present invention, in the case where the erasure correction in the C 2 decoding is implemented by the use of pointers formed by the C1 decoding, since the pattern of the pointers with respect to each series of C 2 code is common and a part of the operations to obtain error value becomes common, it is possible to implement the operation only once. Therefore it is possible to markedly reduce the number of processing steps in decoding and to realize a high-speed in decoding operation. Furthermore, according to the present invention, without necessity to obtain the whole error values in accordance with complicated error evaluation polynomial in obtaining a plurality of error values, it is possible to obtained one of the error values by a simple construction and to reduce the number of the processing steps. Moreover, according to the present invention, it is possible to markedly reduce the number of calculation steps in erasure correction. The present application describes matter described parent application EP-A-167 627 from which this application was divided.

Claims: A method for decoding a product error correction code of respective first error correction codes (n 1 , k 1 ), where n 1 denotes the code length and k 1 is the number of information symbols, and respective second error correction codes (n 2 , k 2 ), where n 2 denotes the code length and k 2 is the number of information symbols, the first correcting codes being arranged in columns and the second correcting codes being arranged in rows of a two-dimensional arrangement, the method comprising the steps of: receiving at least the respective first error correction codes; first decoding the respective first error correction codes; generating respective first pointers for indicating whether the errors of respective first error correction codes can be corrected; storing the respective first pointers in memory means (13) having at least n 2 bits; second decoding the respective second error correction codes by implementing an erasure correction where the first pointers indicate errors that cannot be corrected; and outputting the information symbols; the step of second decoding includes a step of calculating error values of erasure symbols by an algebraic expression consisting of a first term, which is a common value, and a second term, which comprises individually independent values for the erasure error corrections of the respective second error correction codes; and the step of calculating error values comprises: performing a first calculation of the first term only once for each of the respective first pointers; storing the result of the first calculation of the first term; and performing each calculation to obtain error values for the respective second error correction codes by calculating each second term and using the stored result of the first calculation. An apparatus for decoding a product error correction code of respective first error correction codes (n 1 , k 1 ), where n 1 denotes the code length and k 1 is the number of information symbols and respective second error correction codes (n 2 , k 2 ), where n 2 denotes the code length and k 2 is the number of information symbols, the first correction codes being arranged in columns and the second correction codes being arranged in rows of a two-dimensional arrangement, the apparatus comprising: receiving and output means (28) for receiving at least the respective first error correction codes and for deriving the information symbols; decoding means (12, 14, 16, 29, 33 - 37) connected to said receiving and output means (28) and for first decoding the respective first error correction codes and for generating respective first pointers for indicating whether the errors of respective first error correction codes can be corrected and for second decoding the respective second error correction codes by implementing an erasure correction where the first pointers indicate errors that cannot be corrected and memory means (13) connected to said decoding means (29, 33 - 37) and having a capacity of at least n 2 bits for storing the respective first pointers; said decoding means (12, 14, 16; 29, 33-37) calculating, in said second decoding, error values of erasure symbols using an algebraic expression consisting of a first term, which is a common value, and a second term, which comprises individually independent values for the erasure error corrections of the respective second error correction codes; and said decoding means (12, 13, 16; 29, 33 - 37) performing a first calculation of the first term only once corresponding to each of the respective first pointers, and to storing the result of the first calculation of the first term; and further performing each calculation to obtain error values for the respective second error correction codes by calculating each second term and using the stored result of the first calculation. An apparatus according to claim 2 wherein said decoding means (12, 14, 16, 29, 33-37) comprises first decoding means (12, 14) connected to said receiving means (11) for said first decoding, and second decoding means (16, 14) connected to said first decoding means (12, 14) and said memory means (13) for said second decoding, and said apparatus further comprises storing means for storing the result of the first calculation of the said first term and implements each of the calculations for obtaining error values corresponding to the respective second error correction codes by each of second calculations of the second term and by using the stored result of the first correction. A method according to claim 1 further comprising the steps, for decoding and correcting Reed=Solomon code of: solving the expression where, ν = 0 to d - 2 n : Number of erasure X k : Location of kth element S ν : Syndrome Y k : Magnitude of error in the erasure of kth element d : Minimum distance of code to obtain roots of the expression; making erasure correction of errors encoded in the Reed=Solomon code in accordance with the roots, where the roots are obtained by solving the expression where Λ nij : Coefficient of Z j of ℓ : Any integer more than or equal to 0 which satisfies ℓ < d - n - 1. Apparatus according to claims 2 or 3 for decoding and correcting erasure in Reed-Solomon code in accordance with the roots of where, ν = 0 to d - 2 n : Number of erasure X k : Location of kth element S ν : Syndrome Y k : Magnitude of error in the erasure of kth element d : Minimum distance of the code wherein said decoding means (12, 14, 16; 28, 29, 33-37) further comprises syndrome register means (29) for storing syndrome S ν ; and operating logic means (37) for obtaining the roots Y i by solving the expression: where Λ nij : Coefficient of Z j of ℓ : Any integer more than or equal to 0 which satisfies ℓ ≦ d - n - 1 said operating logic means (37) including register means (38) for storing syndrome S ν ; register means (39) for storing X ν / i Y i ; register means (40) for storing X i ; adder means (41) for adding S ν and X ν / i Y i and for supplying said register means (38) and syndrome register means (29) with S ν + X ν / i Y i ; multiplier means (42) for multiplying X i and X ν / i Y i and for supplying said register means (39) with X ν / i Y i .

Inventors: FUKAMI TADASHI, ODAKA KENTARO, OZAKI SHINYA, FUKAMI, TADASHI, ODAKA, KENTARO, OZAKI, SHINYA
Applicants: SONY CORP, SONY CORPORATION
Application year: 1984
Main classification: H03M13
IPC codes: H03M13