ERROR PROTECTION APPARATUS

Abstract: A Reed-Solomon error correcting apparatus is prog­ rammable to perform several distinct error correction func­ tions, namely, encoding, error detection, syndrome genera­ tion, burst error trapping, and Chien searching. The appar­ atus essentially comprises a set of two t registers (30) where t is the number of errors to be corrected, a set of two t exclusive-OR gates (32), a set of two t top multiplexers (34), a set of two t bottom multiplexers (36), a first set of two t Galois Field multipliers (S₀-S₁₉), a second set of two Galois Field multipliers (G₀-G₁₉), a feedback multiplexer (42), a lead exclusive-OR gate (40), an AND gate (46), t-1 ordered Chien exclusive-OR gates (52) and a controller (12).

Description: The invention relates to an error protection appartus for use as a decoder for Reed-Solomon codes over a Galois field GF(2 m ) and comprising: a set of 2t registers, where t is the number of errors to be corrected, each register adapted to hold m bits, m being an arbitrary number; a set of 2t exclusive-OR gates, each gate adapted to, by order, exclusive-OR two ordered m-bit sets of inputs and provide a set of ordered outputs, the outputs of the respectively ordered gate connected to the inputs of the correspondingly ordered register: a set of 2t top multiplexers, each adapted to select between two ordered sets of m-bit inputs and place the selected set on m ordered outputs, a first set of inputs being an A set, a second set of inputs being a B set, the outputs of the respectively ordered multiplexers connected to a first set of ordered inputs of the correspondingly ordered exclusive-OR gate; a set of 2t bottom multiplexers, each adapted to select between two ordered sets of m-bit inputs and place the selected set on m ordered ouptuts, a first set of inputs being an A set, a second set of inputs being a B set, the outputs of the respectively ordered multiplexer connected to a second ordered set of inputs of the correspondingly ordered exclusive-OR gate; a first set of 2t Galois field GF(2 m ) multipliers, each adapted to multiply an ordered m-bit input by α i , where i corresponds to the order of the multiplier, i = 0, 1, 2, ... 2t-1, and α i is an m-tuple of Galois field GF(2 m ), the inputs of the respectively ordered multipliers connected to the outputs of the inversely respectively ordered registers, and the outputs of the respectively ordered multipliers connected to the A input set of the inversely respectively ordered top multiplexers. K.Y. Liy, Architectur for VLSI design of Reed-Solomon Encoders, IEEE Trans. on Computers, Vol. C31, No. 2, Feb. '82, p. 170-175 describes a Reed-Solomon encoder that also comprises 2t shift registers with 2t attached Galois Field multiplexers and 2t attached OR-gates. Reed-Solomon error correcting apparatus have generally utilised a general purpose digital computer to control peripheral arithmetic units implementing Galois Field manipulation. For large error-correction capability codes, such as a ten-error-correcting code, it is believed that an all hardware implementation of the necessary error correction algorithms would be too expensive. However, an all software implementation of the error correction algorithms would be too slow. According to the present invention the apparatus according to the preamble is characterized in that it comprises a set of 2t bottom multiplexers, each adapted to select between two ordered sets of m-bit inputs and place the selected set on m ordered outputs, a first set of inputs being an A set, a second set of inputs being a B set, the outputs of the respectively ordered multiplexer connected to a second ordered set of inputs of the correspondingly ordered exclusive-OR gate; a first set of 2t Galois Field GF(2 m ) multipliers, each adapted to multiply an ordered m-bit input by α i , where i corresponds to the order of the multiplier, i = 0, 1, 2 ... 2t-1, and α i is an m-tuple of Galois Field GF(2 m ), the inputs of the respectively ordered multipliers connected to the outputs of the inversely respectively ordered registers, and the outputs of the respectively ordered multipliers connected to the A input set of the inversely respectively ordered top multiplexers; a second set of 2t Galois Field GF(2 m ) multipliers, each respectively ordered multiplier adapted to multiply an ordered m-bit input by the correspondingly ordered coefficient of a generator polynomial G(X) derived from the equation a feedback multiplexer adapted to select between two ordered sets of m-bit inputs and place the selected set on m ordered outputs, a first set of inputs being an A set, a second set of inputs being a B set, the outputs connected to the inputs of each of said second set of Galois Field GF(2 m ) multipliers, the outputs of the highest order of said registers connected to the A input set of the feedback multiplexer; a lead exclusive-OR gate adapted to, by order, exclusive-OR two ordered m-bit sets of inputs and provide a set of ordered outputs, a first set of inputs connected to the outputs of the highest order of said registers, the outputs of the lead exclusive-OR gate connected to the B input set of said feedback multiplexer; an ECC output data path connected to the outputs of the highest order of said registers; an ECC input data path comprising m ordered bits connected to a second set of inputs to said lead exclusive-OR gate and to the B input set of each of said bottom multiplexers: an AND gate for logically ANDing an enable detection signal with the m ordered bits of said ECC input data path and providing the ordered resultant to the B input set of the lowest order top multiplexer; t ordered σ-enable signals, σ i, i = 1, 2, 3 ... t, applied to the registers connected to the correspondingly ordered first set of Galois Field GF(2 m ) multipliers; t-1 ordered Chien exclusive-OR gates, each gate adapted to, by order, exclusive-OR two ordered m-bit sets of inputs and provide a set of ordered outputs, a first set of inputs connected to the outputs of the register connected to the correspondingly ordered first Galois Field GF(2 m ) multiplier, a second set of inputs connected to the outputs of the next higher order Chien exclusive-OR gate, save for the highest order gate, whose second set of inputs is connected to the outputs of the register connected to the next highest order Galois Field GF(2 m ) multiplier, the outputs from the lowest order gate comprising a Chien search output data path; and a controller means including means for selectively selecting the A or B input set of each of said multiplexers, for providing said enable detection signal for selectively providing said σ-enable signals, for provdiing a signal for clearing each of said registers, and for providing a signal to clock each of said registers. The invention also relates to such apparatus wherein said controller means includes means for adapting said apparatus to encode data comprising means for selecting the B input set of said top multiplexers, means for selecting the A input set of said bottom multiplexers, and means for selecting the B input set of said feedback multiplexers. By itself, S. Deohar et al., High Speed interleaved Reed-Solomon error detection and correction system, Proceedings of SPIE -The International Society for optical engineering, Arlington VA, USA, 8th-9th June 1989, Vol. 421, pp. 65-78, Bellingham, Washington, USA describes a combined all hardware syndrome-processor and encoder. The feature of providing different modes within a Galois Field processor in therefore principally known. Further aspects of the invention are recited in dependent Claims. The invention is illustrated, merely by way of example, in the accompanying drawings, in which:- Figure 1 is a block diagram of one embodiment of an error correcting apparatus according to the present invention; Figure 2 is a block diagram of the error correcting apparatus of Figure 1 connected to perform a Chien search function; Figure 3 is a block diagram of the error correcting apparatus of Figure 1 connected to perform an Encode function; Figure 4 is a block diagram of the error correcting apparatus of Figure 1 connected to perform a shift-register function; Figure 5 is a block diagram of the error correcting apparatus of Figure 1 connected to perform an Error Detection function; and Figure 6 is a partial block diagram of the error correcting apparatus of Figure 1 connected to perform generation of one syndrome S i . Figure 1 is a schematic diagram of a ten-error-correcting Reed-Solomon error correcting apparatus according to the present invention, The mathematics employed in encoding and decoding has been described elsewhere, see especially Chapter 10 of Berlekamp, Algebraic Coding Theory (1968) and Chapter 6, especially 6.5 and page 278 of Lin and Costello, Error Control Coding: Fundamental and Applications (1983). However, a brief summary is appropriate. Error correction is essentially a three step process: 1) encoding information, 2) decoding it, and 3) correcting any errors. Encoding information comprises forming a codeword C(X) of n symbols for transmission of data to, for example, an optical disk recorder for recording. The codeword C(X) comprises k information symbols I(X) and n-k parity check symbols P(X). Each symbol comprises m bits. The parity check symbols are derived by dividing the information symbols X n-k I(X) by a generator polynomial G(X). Division results in a quotient Q(X) which is ignored and a remainder R(X). The remainder comprises the parity check symbols which are then added to the n-k lowest order locations of the codeword C(X). (Multiplying I(X) by X n-k places the information symbols in the k highest order positions of C(X).) With Reed-Solomon codes the number of parity check symbols to correct an error must be twice the number of errors t that are to be corrected; thus, there must be twenty parity check symbols in a ten-error-correcting code. As the order of the remainder corresponds to the order of the divisor, the generator polynomial implemented for a ten-error-correcting code has an order of twenty. The generator polynomial itself is comprised of twenty roots, each of the form X - α i , where α i is a binary m-tuple α i = A m-1 α m-1 + A m-2 α m-2 + ... A₁α¹ + A₀α⁰ and α is a root of an irreducible polynomial P(x). In the preferred embodiment, the irreducible polynomial is P(X) = X⁸ + X⁴ + X³ + X² + 1 . As P(α) = 0 , α⁸ = α⁴ + α³ + α² + 1 A log table (Table 1) of the elements of Galois Field (2⁸) represented by this irreducible polynomial follows. The field elements are the powers of α i , i = 0, 1, 2 ... 255, modulo (X⁸ + X⁴ + X³ + X² + 1). The number to the left is the number of the field element corresponds to the power of α of the field element. Within a table entry, the bits correspond to the coefficients A i of the α i m-tuple, with the rightmost list being A₀ and the leftmost list being A₇. The generator polynomial for a Reed-Solomon ten-error-correcting code having n = 2 m -1, m-bit symbols where m = 8 in the preferred embodiment is as follows: The code word C(X) thus transmitted is a multiple of both the generator polynomial and each of its factors or roots. Thus, the division of the received word R(X) by the generator polynomial or each of its roots, if the received word contains no errors, results in some quotient and a remainder of zero. To check if a received word contains errors, one may divide the received word either by the generator polynomial or by all of its roots and then test whether the remainder or remainders are all zero. For error correction purposes, it is necessary to generate a number of syndromes equal to twice the number of errors being corrected. In the preferred embodiment, as ten errors are being corrected, twenty syndromes must be generated. The syndrome can be defined as the remainder after dividing the received word R(X) by a root (X-α i ) of the generator polynomial G(X). This is equivalent to evaluating the received word polynomial R(X) at α i , i.e. R(α i ). As there are twenty such roots, there are twenty syndromes. The syndromes are mathematically related to error locations and error values by the relationship: where the X i are the error locations and the Y i are the error values, and S j = R(α j ). Therefore, X i is an element of GF(2⁸) and is a power of α mod (X⁸ + X⁴ + X³ + X² + 1). The power of α corresponds to the location of the symbol in error, i.e., if X i = α⁹⁵, the 95th symbol of R is in error. The error value Y i is also an element of GF(2⁸) and corresponds directly with the error pattern. Thus the code can correct all eight-bit error patterns of a symbol in error. The error locations can be derived from the syndromes in the following manner: first, the coefficients of an error location polynomial are calculated according to Berlekamp's Algorithm given on page 154 of his Algebraic Coding Theory . See also pp. 155-8 of the Lin and Costello reference above. The error location polynomial of the form σ(X) = σ₁₀x¹⁰ + σ₉x⁹ + σ₈x⁸ + ... + σ₂x² + σ₁x + 1 = 0 for a ten error correcting code. This equation is related to the error locations X i by the following: σ(X) = π (1 - X i x) If the polynomial σ(X) is evaluated at α j , where -j corresponds to a received word location, the first form of the error location polynomial will sum to zero when α -j is a root of σ(X), i.e., when 1 - X i α j = 0. This occurs where X i = α -j . A Chien Search for the error locations comprises evaluating the first form of the polynomial σ(X) for each power of α j , j = 0, 1, 2, 3 ... k (k being the number of the information symbols) and checking if the result is zero or non-zero. This search shortened by ignoring errors in the parity check symbols and not evaluating the polynomial at powers of α corresponding to the locations of the parity check symbols. Once the error locations X i have been located through a Chien search, the error values Y i may be evaluated. An error polynominal S(z) is defined by S(z) = 1 + (S₁ + σ₁)z + (S₂ + σ₁S₁ + σ₂)z² + ... (Sν + σ₁S ν-1 + σ₂S ν-2 + ... + σ ν )Z ν where ν is the number of errors (max.). By subsituting the reciprocals of the error locations X i for z, or z = X i⁻¹, in the following error evaluator polynomial, the error values Y i may be determined. Having described the mathematical background for Reed-Solomon error correction, the various elements of the error correction apparatus according to the present invention and shown in Figure 1 will now be described. The operation of the apparatus will be described later. The error correction apparatus indicated by reference numeral 10 is comprised of two major elements: a controller 12 and an ECC array 14. The controller 12 is connected to a microprocessor (not shown) through a bus 16 for the bi-directional transfer of data. It is also connected through a read/write line 18 for controlling the direction of data on the bus 16 and a clear line 20. The controller 12 is connected to the ECC array 14 through an ECC input data path 22, an ECC output data path 24, a Chien search output data path 26, and a miscellaneous control signals 28. The bus 16, the ECC input data path 22, the ECC output data path 24 and the Chien search output data path 26 are all eight line connections for transmitting eight bits in parallel. The ECC array 14 is comprised of twenty registers 30 whose inputs are respectively connected to twenty exclusive-OR gates 32. The two sets of inputs to the exclusive-OR gates are respectively connected one set to the outputs of twenty top multiplexers 34 and another set to the outputs of twenty bottom multiplexers 36. The outputs of each of the registers 30 are inversely respectively connected to twenty Galois Field multipliers S₀ to S₁₉. The outputs of the respective multipliers S₀ to S₁₉ are provided as the A inputs to the inversely corresponding top multiplexers 34. Additionally, a highest order register 38 of the registers 30 has its outputs connected to a lead exclusive-OR gate 40, whose outputs are connected as a feedback connection through a feedback multiplexer 42 ("B" inputs) to a Galois Field parallel multiplier array 44 of the multipliers G₀ to G₁₉. Additionally, the outputs of the registers 38 are provided directly as the A inputs of the feedback multiplexer 42. The outputs of the respective multipliers G₀ to G₁₉ of the parallel multiplier array 44 are provided as the A inputs to the correspondingly ordered bottom multiplexers 36, the outputs of which are, in turn, connected as one set of inputs to the correspondingly ordered exclusive-OR gates 32. The ECC input data path 22 is connected first to the exclusive-OR gate 40; second, in parallel to each of the B inputs of the bottom multiplexers 36; third, to the ECC output data path 24 via the A inputs of an output multiplexer 50; and fourth, as one set of inputs to an AND gate 46, the outputs of which are connected to the B inputs of a lowest order top multiplexer 48. The outputs of the registers 30, save for the register 38, are additionally respectively connected to the B inputs of the top multiplexers 34, save for the multiplexer 48. The outputs of the registers 30 connected to multipliers S₁ to S₁₀ are additionally respectively connected as one set of inputs to nine exclusive-OR gates 52 in the following manner: the outputs from the multiplier s₁₀ and the outputs from the multiplier S₉ are connected as inputs to a first exclusive-OR gate 70 (see Fig. 2). The outputs of this exclusive-OR gate are connected as a first input set to a next exclusive-OR gate 72; the other inputs to this next exclusive-OR gate 72 are from the multiplier S₈; the outputs of this next exclusive-OR gate 72 are provided as a first input set to a subsequent exclusive-OR gate 74; the other input set to this subsequent exclusive-OR gate 74 being the outputs from the register S₇, and so on until an exclusive-OR gate 64. The outputs of this last exclusive-OR gate 64 are provided on the Chien search output data path 26 to the controller 12. All of the inputs and outputs of each register 30, multiplexer 34, 36, 42, 50, exclusive-OR gate 32 and 52, multiplier S₀ to S₁₉, to G₀ to G₁₉ are eight bits wide each line corresponding to a power α i , i = 0, 1, 2 ... 7. The exclusive-OR gates operate on the bits individually, that is, the lowest order bit of one input set is exclusive-ORed with the lowest order bit of the other input set, etc. This is known to the art as Galois Field addition of two symbols. However, the multipliers operate in all eight bits in a group. The logic for the multipliers S₀ to S₁₉ and G₀ to G₁₉ are shown in Table 2: In Table 2, the number to the left of the equal sign represents the number of the output, while the numbers to the right of the equal sign represents the numbers of the inputs. The plus sign represents addition modulo 2, which is equivalent to an exclusive-OR gate. The mathematical meaning of Table 2 can best be illustrated by example. Multiplication of two elements of GF(2 m ), Y(α) and A(α), where Assume A(a) = α¹⁹⁰, which is the coefficient of G₀ of the generator polynomial G(x). Then Each of the α¹ is an 8-tuple, as is the product Y(α)α¹⁹⁰, which can be represented by Z(α), From inspection, it can be seen then these last equations for Z i correspond to the Table 2 entry for G₀ = α¹⁹⁰. It can be seen from Table 2 that the multipliers S₀ to S₁₉ multiply the inputs by the fixed constants α⁰ to α¹⁹, respectively, while the multipliers G₀ to G₁₉ multiply the input by the corresponding coefficients of the generator polynominal G(X); i.e. α¹⁹⁰, α¹⁸⁸ ... α¹⁷. Each of the inputs to the multipliers S₀ to S₁₉ are provided by the associated registers 30. In contrast, each of the inputs to multipliers G₀ to G₁₉ are provided from a single source, the multiplexer 42. This results in the same symbol being multiplied by twenty constants, G₀ to G₁₉, in parallel. The actual implementation of the above multiplier logic attempts to simplify the circuitry and reduce redundancy by sharing repeated logic patterns. For example, in the multiplier S₂, the pattern "6 + 7" is repeated in equations "3" and "4". Only one "6 + 7" circuit need be implemented and its output provided as inputs to both the "3" and the "4" circuits. As can be appreciated, the logic associated with multipliers G₀ to G₁₉ may be greatly simplified by making terms appearing in many different multipliers common to all. The actual choice of circuitry implementing the logic equations is deemed to be within the skill of the art. In addition to the above, the following control lines are connected between the controller 12 and the ECC array 14: an initialise line 56 is connected between the controller 12 and the clear input of each of the registers 30. Activation of the initialised line clears each of the registers 30. A master clock line 58 is similarly connected between the controller 12 and each of the registers 30. Ten σ enable clock signals 60 are connected respectively to ten of the registers 30, beginning with a register 62 connected to the multiplier S1 as shown in Figure 1. A multiplexer select line 1 is connected to a select input of the top multiplexer 34. A multiplexer select line 2 is connected to a select input of the bottom multiplexer 36. An enable detection line is connected to the AND gate 46 and the select input of the feedback multiplexer 42. A read parity syndrome select line is connected to the enable input of the feedback multiplexer 42 and the select input of the output multiplexer 50. When "off" the B input of the output multiplexer 50 is selected and the feedback multiplexer 42 is disabled. When disabled, the feedback multiplexer 42 outputs all zeros. Having briefly described the error correction apparatus, its operation for encoding will now be described. The transmitted code word can be broken down into two parts: the first part, the k information symbols and the second part, the 2t parity check symbols, each symbol being eight bits in length. The maximum number of symbols in a code word is 255 (2 m -1, m = 8). The number of parity check symbols for a ten-error-correcting Reed-Solomon code is twenty (t=10). In the following n is assumed to be equal to the length of the code word to be transmitted, and n-k equal to the number of parity check symbols. The transmitted code word expressed in polynomial form: r(X) being the remainder resulting from the division of X n-k I(X) by G(X), the generator polynomial, i.e. X n-k I(X) + r(X) = Q(X) G(X), or C(X) = Q(X) G(X) , Q(X) being an unused quotient, and r(X) comprising the n-k parity check symbols. The error correcting apparatus divides X n-k I(X) by G(X) and transmits the remainder r(X) so it can be appended to X n-k I(X). The error correcting apparatus 10 encodes the information symbols as follows: the output multiplexer 50 is initially set to output, on the ECC output data path 24, the ECC input data. The top multiplexers 34 are set to pass through the B inputs. The bottom multiplexers 36 are set to pass through the A inputs. The feedback multiplexer 42 is set to pass through the B inputs. The AND gate 46 is disabled. When so conditioned, the ECC array 14 operates as the equivalent circuit shown in Figure 3. The information symbols are transmitted, one by one, highest order first, along the ECC input data path 22. Each information symbol proceeds through the ECC input data path 22 to the lead exclusive-OR gate 40, and then through the feedback multiplexer 42 into the multiplier array 44, where the symbol is multiplied by the twenty multipliers G₀ to G₁₉, which are the coefficients of the generator polynomial G(X). The multiplied outputs are immediately available on the line 54 and pass through the bottom multiplexers 36 to one set of inputs to the exlusive-OR gates 32. For each information symbol, the master clock is clocked once thereby causing the registers 30 to copy the information present at the exclusive-OR gates 32. The copied information is then available on the outputs of the registers 30. The outputs, as aforementioned, are multiplexed through the top multiplexers 34 (B inputs) to a second set of inputs to the exclusive-OR gates 32. When a second information symbol is available on the ECC input data path 22, the results of the first symbol multiplied by the multipliers G₀ to G₁₉ are exclusive-ORed with the results of the second symbol multiplied at the exclusive-OR gates 32. When the second master clock appears, the register 30 copy the results of this exclusive-OR gate. This process continues until all information symbols have been clocked through the multiplier array 44. As is known to the art, the above sequence of operations divides the information symbols, multiplied by X n-k by the generator polynomial G(X). After the division the remainder, which comprises twenty symbols, is left as a residue in the registers 30. To retrieve the remainder, which are the parity check symbols, the controller selects B inputs of the multiplexer 50 to connect the output of the register 38 with the ECC output data path 26; this also disables the feedback multiplexer 42. This sends all the zeros to the exclusive-OR gates 32. The setting Of the top multiplexers 34 remains unchanged. This effectively transforms the exclusive-OR gate 32 into an OR gate to effectively transfer symbols from one register 30 to another unmodified. When so connected, the ECC array 44 functions as the equivalent circuit shown in Figure 4. When the B inputs of the output multiplexer 50 are first selected, the first parity symbol from the register 38 is available. When the master clock clocks the registers, the symbols from preceding registers are copied into the next registers, and the second parity symbol is now available on the output of the register 38. The master clock is pulsed 19 more times or a total of 20 times to clock out each parity symbol to the ECC output data path. After all parity symbols have been clocked out, the code word C(X) is complete. It should he noted that the information symbols I(X) are provided highest order first. Assuming there are k information symbols, I₀ + I₁X + I α X² + ... I k-1 X k-1 , symbol I k-1 X k-1 appears first at the ECC input data path. This symbol is fed to the ECC array 14 for division. It also becomes the highest order C(X) output, which is an order n-k greater than in the I(X) polynomial. This transposition effectively multiplies information symbol I k-1 X k-1 by X n-k, so that C₁X n-1 = X n-k I k-1 X k-1 or C₁X n-1 = I k-1 X n-1 The remainder r(X) is also provided to the ECC output data path 26 highest order first. Thus C n-k-1 X n-k-1 = r₁₉X¹⁹ and C₀ = r o X⁰. It will be appreciated that feeding I(X) from the right end, after the highest order the register 38, is equivalent to dividing X n-k I(X) by G(X), as will became apparent when one considers a conventional division circuit described in the next section. From the process of encoding it is known that the code word C(X) is a multiple of the generator polynomial G(X) or C(X) = G(X) Q(X) . The division of the code word C(X) by the generator polynomial G(X) results in a remainder r(X) having a value of zero if the code word is received without error. Thus, for error detection, the error correcting apparatus is conditioned to divide the code word C(X) by the generator polynomial G(X) and test the remainder r(X) for a zero result by shifting the contents of the registers 30 out to the microprocessor which can perform the text for zero. In operation, the error correcting apparatus is conditioned in a slightly altered fashion to perform the division and testing. The controller 12 enables the AND gate 46 by activation of the enable detection line from the controller 12. The controller selects the A inputs of the bottom multiplexers 36, the B inputs of the top multiplexers 34, and the A input of the feedback multiplexer 42. When so configured, the ECC array 44 appears as in Figure 5. The code word is provided, symbol-by-symbol, highest order first at the ECC data input path 22. The symbols are clocked through the registers 30, lowest order register to highest order register, and then fed back through the feedback multiplexer 42 into the multiplier array 44, where the highest order symbol is multiplied by the multipliers G₀ to G₁₉, the coefficients of the generator polynomial. The process continues until each code word symbol has been clocked into a lowest order register 39, at which time the remainder from the division will be present in the registers 30. Thereafter, the B inputs of the multiplexer 50 are selected to connect the register 38 to the ECC output data path 26. The feedback multiplexer is disabled and 0's are provided for symbols to the exclusive-OR gates 32. The circuit is now equivalent to the circuit of Figure 3. The registers 30 are clocked 20 times providing the remainder to the microprocessor for testing for a zero value. If any of the remainder symbols are non-zero, then an error has occurred in the wode word C(X). Assume that the code word C(X) was transmitted and that word R(X) = C(X) + E(X) is the word received where E(X) is an error word. That is R(X) = C(X) + E(X) As C(X) is a multiple of the generator polynomial G(X) where From the above we know that the code word C(α i ) = 0 when α i = α⁰, α¹, α² ... α 2t-1 . Thus: R(α i ) = 0 + E(α i ) Furthermore, we know that the received word R(X) is the transmitted code word C(X) if and only if the received word evaluated at each α i , i = 0, 1, 2, ... 2 t-1 , is zero. If an error has occurred then one or more of the evaluations of R(X) at α i , i = 0, 1, 2 ... 2 t-1 will result in a non-zero value. The location of the error and its value may be calculated from these non-zero values (otherwise known as syndromes). The 2t syndromes for the preferred embodiment are S i = R(α i ), i = 0, 1, 2 ... 19, t = 10. The syndrome components S i can be computed by dividing R(X) by X - α i . The division results in the equality: R(X) = C(X)(X- α i ) + B i , where the remainder B i is a constant in GF(2 m ). Substituting α i for X in both sides of this equation gives: R(α i ) = C(α i ) (α i - α i ) + B i , S i = 0 + B i = B i . The division can be performed as shown in Figure 6 where the received word R(X) is provided, symbol-by-symbol, as one set of inputs to one Of the exclusive-OR gate 32, which exclusive-OR is bit-by-bit the correspondingly ordered bits of its two input sets. The output of the exclusive-OR gate is stored, bit-by-bit, into one of the registers 30. The output of the register 30 is provided, bit-by-bit, to a multiply-by-α i circuit 62. The eight ordered outputs from the multiplier circuit 62 are provided as the second input set to the exclusive-OR gate 32. After each of the symbols of the received code word R(X) have been clocked through the multiplier circuit 62. A residue or remainder comprising the syndrome S i remains in the register 30. The contents of this register 30 are then clocked out of the ECC array 44 and into the microprocessor where the syndrome S i may be used in conjunction with the other nineteen syndromes to calculate the coefficients of the error locator polynomial. Referring to Figure 1, the control circuit conditions the ECC array to calculate the syndromes S i, i = 0, 1, 2, ... 19 by selecting the A inputs of the top multiplexers 34 and selecting the B inputs of the bottom multiplexers 36. The selection of the A inputs of the top multiplexer 34 latches the multipliers S₀, S₁ ... S₁₉ into the exclusive-OR gates 32 as shown in Figure 6. The selection of the B inputs of the bottom multiplexers causes the ECC input data path 22 to be coupled to the other inputs to the exclusive-OR gates 32. These are equivalent to the R(X) inputs in Figure 6. The received word R(X) is provided, symbol-by-symbol, on the ECC input data path 22, highest order first. Thereafter the ECC array is clocked n times computing the twenty syndromes S₀, S₁ ... S₁₉ in parallel. After the syndromes have been computed, the syndromes are present in the registers 30. The controller 12 then selects the B input of the top multiplexers the 34 A inputs of the lower multiplexers 36 and disables the feedback multiplexer 42 to supply zero symbol data to the exclusive-OR gates 32 and clocks the ECC array 14 twenty times thereby reading out of the array along ECC output data path 24 all twenty syndromes. After the microprocessor has received the syndromes S i, i = 0, 1, 2 ... 19, it calculates the coefficients of the error locator polynomial σ(X) from the syndromes by use of the Berlekamp algorithm. Once the coefficients of σ(X) are known the evaluation of the polynomial: σ(X) = σ₁₀X¹⁰ + σ₉X⁹ + σ₈X⁸ + ... σ₂X² + σ₁X + 1, at α i yields an error location at α -i if σ(α i) = 0. This is equivalent to: σ₁₀(α i )¹⁰ + σ₉(α i )⁹ + .... + σ₂(α i )² + σ₁(α i ) = 1 A circuit as shown in Figure 2 performs the Chien search function. The circuit is comprised of ten registers 30, ten multipliers S₁, S₂, S₃ ... S₁₀, which multiply the contents of the registers 30 by the corresponding power of α and provide feedback into the registers 30, and nine modulo 2 addition gates 52 serially connected to one another and also connected to the outputs of the registers 30. An additional input to register 30 comprises the coefficients of the error locator polynomial σ₁, σ₂ ... σ₁₀. These are initally loaded into the registers 30. Thereafter the registers are clocked once to form in the registers 30 the values σ₁₀α¹⁰, σ₉α⁹, σ₈α⁸ ... σ₁α¹. The modulo 2 addition of these registers by the exclusive-OR gates 52 forms at a Chien search output at the exclusive-OR gate 64 the evaluation of the error locator polynomial at α i.e., σ(α) - 1. The outputs are evaluated by the controller 12. If the results of this evaluation are identical to 1, i.e., the eight-bit symbol at the Chien search output has only its least significant bit with non-zero value, then an error location has been found. The location of the error is α⁻¹. The location of α⁻¹ corresponds to the X²⁵⁴ location in the received word R(X) because α⁻¹ = α²⁵⁵⁻¹ = α²⁵⁴, the code being multiplicative cyclic. When the controller identifies a Chien search output symbol having a value of 1, it signals this fact to the microprocessor. The actual location of the error is established by a counter in the microprocessor. To evaluate the error locator polynomial at α² the registers 30 are clocked one more time thereby again multiplying the contents registers 30 by the powers of α i , i = 1, 2 ... 10. If an error is found, location X²⁵³ is in error. To evaluate the error polynomial at each possible location of the received word R(X) the registers must be clocked a total of 255 times which corresponds to the maximum length of the code word. However, one is not normally interested in errors occurring in the parity check symbols. Therefore, the registers 30 need only be clocked 255 - 2t times, where t is the number of errors, as the parity check symbols occur in the lowest order locations of the code word R(X), i.e., R₀,R₁X,R₂X² ... R 2t-1 X 2t-1 . Referring to Figure 1 the controller 12 conditions the ECC array 14 to perform the Chien search function by initially loading the coefficients of the error locator polynomials σ(X) into the registers 30 corresponding to multipliers S₁ to S₁₀ as follows: the registers 30 are first initialised to zero and the B inputs of the bottom multiplexers are selected thereby connecting the ECC input data path 22 to the exclusive-OR gates 32. As the contents of the registers 30 are zero, the exclusive-OR gates 32 will pass the information on the ECC input data path 22 unchanged into the registers 30 if the information is loaded into the registers from right to left in the figure. Thus the coefficients of the error polynomial σ(X) are presented with the lowest order coefficient σ₁ first and the highest order coefficient σ₁₀ last. When σ₁ is transmitted to the ECC array 14 by the microprocessor, the controller 12 enables and clocks the register 62 via the σ₁ enable clock signals 60. A similar procedure is performed for σ₂ to σ₁₀ individually clocking into the registers 30 the respective coefficients of the error locator polynomial. Once the coefficients have been loaded, the controller 12 presents symbols of zero value on the ECC input data path 22 thereby effectively changing the exclusive-OR gates 32 into OR gates which pass the information presented by the upper multiplexers unchanged into the registers 30. The controller selects the A inputs of the upper multiplexers 34 to connect the multipliers S₁ to S₁₀ into exclusive-OR gates 32. The registers 30 are then clocked once to evaluate the error locator polynomial at α¹. The outputs of the multipliers S₁ to S₁₀ are fed into the exclusive-OR gates 52 connected as shown in Figure 2 so that the modulo 2 sum of the registers appears at the Chien search output. This output is provided as a feedback to the controller 12 which, in turn, provides it as feedback to the microprocessor. Whenever the Chien search output is identical to one, as discussed above, an error location has been found. The controller clocks the registers 2 m - 2t - 1 times where m is the length of the code symbol and 2t are the number of parity check symbols. After the error locations have been found the values of the error at the locations can be found by solving the error value formula for the Y i as described above. The error correcting apparatus of the present invention can also perform burst error trapping. Reed-Solomon codes are cyclic and therefore may be used for trapping single burst errors to a maximum length of t, where t is the error correction capability of the code, provided the errors are confined to contiguous symbols within a code word. To trap a burst error the controller 12 selects the B inputs of the upper multiplexers 34, the A input of the bottom multiplexers 36 and the B input of the multiplexer 42. The arrangement is set to divide the received word X n-k R(X) by the generator polynomial G(X). The incoming received word R(X) is cycled symbol-by-symbol highest order first. The ECC array 14 is clocked n times for the n symbols of the received word R(X). After all the symbols of the received word R(X) have been clocked into the ECC array 14, the controller 12 disables the ECC input data path 22 by providing all-zero symbols. Next the controller clocks the registers 30 an additional n-2t times where n is the length of the code or until t or more zeros are detected at the encoder output data path. At this point the magnitude of the burst error now exists in the next t or fewer registers 30 and may be used for the correction of the burst error by direct modulo 2 addition of the contents of the next t or fewer non-zero symbols to the correspondingly shifted received word symbols. See, e.g., Chapter 11 of Peterson and Weldon, Error-Correcting Codes , 2nd Ed. (1972), especially at Section 11.3.

Claims: An error protection apparatus for use as a decoder for Reed-Solomon codes over a Galois field GF(2 m ) and comprising: a set of 2t registers (30), where t is the number of errors to be corrected, each register adapted to hold m bits, m being an arbitrary number; a set of 2t exclusive-OR gates (32), each gate adapted to, by order, exclusive-OR two ordered m-bit sets of inputs and provide a set of ordered outputs, the outputs of the respectively ordered gate connected to the inputs of the correspondingly ordered register, a set of 2t top multiplexers (34), each adapted to select between two ordered sets of m-bit inputs and place the selected set on m ordered outputs, a first set of inputs being an A set, a second set of inputs being a B set, the outputs of the respectively ordered multiplexer connected to a first set of ordered inputs of the correspondingly ordered exclusive-OR gate (32), a set of 2t bottom multiplexers (36), each adapted to select between two ordered sets of m-bit inputs and place the selected set on m ordered outputs, a first set of inputs being an A set, a second set of inputs being a B set, the outputs of the respectively ordered multiplexer connected to a second ordered set of inputs of the correspondingly ordered exclusive-OR gate; a first set of 2t Galois field GF(2 m ) multipliers (S₀-S₁₉), each adapted to multiply an ordered m-bit input by α i , where i corresponds to the order of the multiplier, i=0, 1,2...2t-1, and α i is an m-tuple of Galois Field GF(2 m ), the inputs of the respectively ordered multipliers connected to the outputs of the inversely respectively ordered registers (30), and the outputs of the respectively ordered multipliers connected to the A input set of the inversely respectively ordered top multiplexers (34), characterized in that there are provided a second set of 2t Galois Field GF(2 m ) multipliers (G₀-G₁₉), each respectively ordered multiplier adapted to multiply an ordered m-bit input by the correspondingly ordered coefficient of a generator polynomial G(X) derived from the equation a feedback multiplexer (42) adapted to select between two ordered sets of m-bit inputs and place the selected set on m ordered outputs, a first set of inputs being an A set, a second set of inputs being a B set, the outputs connected to the inputs of each of said second set of Galois Field GF(2 m ) multipliers (G₀-G₁₉), the outputs of the highest order of said registers connected to the A input set of the feedback multiplexer; a lead exclusive-OR gate (40) adapted to, by order, exclusive-OR two ordered m-bit sets of inputs and provide a set of ordered outputs, a first set of inputs connected to the outputs of the highest order of said registers (30), the output of the lead exclusive-OR gate (40) connected to the B input set of said feedback multiplexer (42); an ECC output data path (24) connected to the outputs of the highest order of said registers (30); an ECC input data path (22) comprising m ordered bits connected to a second set of inputs to said lead exclusive-OR gate (40) and to the B input set of each of said bottom mulitplexers (36); an AND gate (46) for logically ANDing an enable detection signal with the m ordered bits of said ECC input data path (22) and providing the ordered resultant to the B input set of the lowest order top multiplexer (48); t ordered σ-enable signals (60), σ i, i=1,2,3...t, applied to the registers (30) connected to the correspondingly ordered first set of Galois Field GF(2 m ) multipliers (S₀-S₁₉); t-1 ordered Chien exclusive-OR gates (52), each gate adapted to, by order, exclusive-OR two ordered m-bit sets of inputs and provide a set of ordered outputs, a first set of inputs connected to the outputs of the register connected to the correspondingly ordered first Galois Field GF(2 m ) multiplier, a second set of inputs connected to the outputs of the next higher order Chien exclusive-OR gate, save for the highest order gate, whose second set of inputs is connected to the outputs of the register connected to the next highest order Galois Field GF(2 m ) multiplier, the outputs from the lowest gate comprising a Chien search output data path (26); and a controller means (12) including means for selectively selecting the A or B input set of each of said multiplexers, for providing said enable detection signal for selectively providing said σ-enable signals (60), for providing a signal for clearing each of said registers (30) and for providing a signal to clock each of said registers. An apparatus as claimed in claim 1 characterised in that said controller means includes means for adapting said apparatus to encode data comprising means for selecting the B input set of said top multiplexers (34), means for selecting the A input set of said bottom multiplexers (36), and means for selecting the B input set of said feedback multiplexer (42). An apparatus as claimed in claim 1 characterised in that said controller means includes means for adapting said apparatus to detect errors in encoded data comprising means for selecting the B input set of said top multiplexers (34), means for selecting the A input set of said bottom multiplexers (36), means for selecting the A input set of said feedback multiplexer (42), and means for providing an enable detection signal to said AND gate (46). An apparatus as claimed in claim 1 characterised in that controller means includes means for adapting said apparatus to shift data out of said registers (30) unmodified comprising means for selecting the B input set of said top multiplexers (34), and means for supplying m zero bits to each of said exclusive-OR gates (32). An apparatus as claimed in claim 1 characterised in that said controller means includes means for adapting said apparatus to generate syndromes S i , i = 0, 1, 2 ... 2t-1, from encoded data comprising means for selecting the A input set of said top multiplexers (34), and means for selecting the B input set of said bottom multiplexers (36). An apparatus as claimed in claim 1 characterised in that said controller means includes means for loading Chien search error locator polynomial coefficients σ i , i = 1, 2 ... t, into the registers (30) connected to the correspondingly ordered of said first set of Galois Field multipliers (S₀-S₁₉) comprising, means for initialising said registers (30) to a contents of zero, means for selecting the B input set of said bottom multiplexers (36), and means for selectively enabling and clocking the registers (30) connected to the correspondingly ordered of said first set of Galois Field GF(2 m ) multipliers S i, i = 1, 2 ... t, in order, lowest order to highest order. An apparatus as claimed in claim 6 characterised in that said controller means includes means for adapting said apparatus to evaluate the error locator polynomial at α i , i = 1, 2 ... n-k, where n is the length of a code word and k is the number of information symbols, comprising means for selecting the A input set of said top multiplexers (34), means for clocking said registers (30) at least n-k time, and means for monitoring the Chien search output data path (26) for a value identical to one after each clocking corresponding to a symbol in a code word. An apparatus as claimed in claim 1 characterised in that said controller means includes means for adapting said apparatus to trap burst errors in encoded data comprising means for selecting the B input set of said top multiplexers (34), means for selecting the A input set of said bottom multiplexers (36), means for selecting the B input set of said feedback multiplexer (42), means for clocking the registers (30) n-k times to divide input data on the ECC input data path (22) by said generator polynomial G(X), and means for clocking the registers n-k more times or until t or more symbols of zero value appear at the ECC output data path. An apparatus as claimed in claim 1 characterised in that m = 8, said Galois Field GF(2 m ) is Galois Field GF(2 8 ) and α is a root of the irreducible polynomial P (X) = X⁸ + X⁴ + X³ + X² + 1

Inventors: FRITZE, KEITH ROBERT
Applicants: LASER MAGNETIC STORAGE INTERNATIONAL COMPANY
Application year: 1984
Main classification: H03M13
IPC codes: H03M13