Combined computer system

Abstract: The invention deals with the constitution of processors which have a plurality pairs of input ports and output ports, and which are constituted in a looped manner by connecting the output ports and the input ports of the same pairs of any number of processors. The invention further relates to a transmission system in which the data on the same loop is allowed to flow and the data that is required is transferred to different loops, so that the data flows through the loops and across the loops to reach a predetermined processor. Concrete structure of the invention comprises a first group of looped transmission lines (101, 111, 121; 131, 141, 151) consisting of a plurality of looped transmission lines, a second group of looped transmission lines (102, 132; 112, 142; 122, 152) that consist of at least one looped transmis­ sion line and that are arranged to intersect said first group of looped transmission lines, transmission lines that couple said intersecting transmission lines together, and data processing and controlling means (10...15) that controls the transmission of data among the transmission lines and that processes the data, and wherein, as required, the number of building blocks is increased or decreased for each of the looped transmission lines.

Description: Background of the Invention Field of the Invention The present invention relates to a combination of processors that have a uniform transmission processing function, and more specifically to a combined computer system that is constituted in a one-dimensional to three-dimensional manner. Description of the Prior Art Network systems for connecting a plurality of processors (computers) have heretofore been either a bus structure, a loop structure, a star structure, or a mesh structure. The first three of these structures can not be constructed in a three-dimensional configuration. In a mesh structure in which processors are connected through bidirectional transmission lines, routing is complex. In a star structure, the processor at the center of the structure is different from the other processors. In a mesh structure, a particular processor must work to cope with any change in the structure of the system or with any abnormal condition that may occur, thereby making it difficult to expand and maintain the system. US-A-4 380 061 describes a computer system as defined in the preamble of Claim 1. Summary of the Invention To preclude the defects inherent in the conventional art, the present invention provides a computer system of high transmission capacity and speed even if a malfunction in a transmission line occurs. Brief Description of the Drawings Fig. 1 is a diagram of constituent units according to the present invention, Figs. 2 to 13 are diagrams showing a plurality of processors that are connected in the form of networks according to the present invention, and Fig. 14 is a diagram of a data processing and controlling unit according to the present invention. Description of the Preferred Embodiments Fig. 1 shows three kinds of constituent elements (a), (b) and (c) that will be combined in the form of building blocks to constitute a system. The constituent unit consists of a processor and unidirectional transmission lines for transmitting the data therefrom to other processors. Transmission lines of neighboring processors are connected to the unidirectional transmission lines so as to form pairs and so as to receive the data therefrom. Diagrams (a), (b) and (c) of Fig. 1 illustrate constituent units that consist of processors 10, 20 and 30, and two, three and four transmission lines (101, 102), (201, 202, 203), and (301, 302, 303, 304), respectively. To the transmission lines 101, 102, 201, 202, 203, 301, 302, 303 and 304 are connected transmission lines 10k, 10ℓ, 20k, 20ℓ, 20m, 30k, 30ℓ, 30m and 30n of the neighboring processors to form pairs. Figs. 2 to 13 show transmission lines of the processors forming pairs, that are connected successively. The constituent units are all the same, hence, each of the transmission lines constitutes a portion of a closed loop transmission line. Here, the constituent unit may have any number of unidirectional transmission lines in addition to the above-mentioned numbers. Figs. 2 to 5 illustrate examples of connecting the constituent units that have two unidirectional transmission lines. Namely, Fig. 2 illustrates an example in which the processors are divided into two groups consisting of (10, 11, 12) and (13, 14, 15) which are coupled through a loop (101, 111, 121) and a loop (131, 151, 141). The processors (10, 13), (11, 14) and (12, 15) on these different loops are coupled via a loop (102, 132), a loop (112, 142) and a loop (122, 152). Fig. 3 shows an example in which all of the processors are coupled through the same loops. Fig. 4 illustrates an example in which the processors are divided into three groups (10b, 11b, 12b, 13b), (14b, 15b, 16b, 17b) and (18b, 19b, 20b, 21b) which are coupled in the form of loops. Unlike the example of Fig. 2, however, processors (10b, 11b), (12b, 13b), (18b, 19b) and (20b, 21b) on the same loops are coupled. In this regard, the example of Fig. 4 resembles the example of Fig. 3. However, other processors (14b, 15b, 16b, 17b) are connected to constitute loops that traverse the above-mentioned three loops (101b to 131b), (141b to 151b) and (181b to 211b). In this regard, the example of Fig. 4 is the same as the connection method of Fig. 2. Fig. 5 shows an example in which processors are divided into three groups (10c, 11c, 12c, 13c, 14c, 15c), (16c, 17c, 18c, 19c, 20c, 21c) and (22c, 23c, 24c, 25c, 26c, 27c) which are coupled in the form of loops. Unlike the example of Fig. 4, however, the processors 11c, 14c and the processors 23c, 26c exist on the loops (101c to 121c), (221c to 231c) and are not adjacent to each other. In the arrangement of Fig. 2, if the system is to be expanded without changing the constitution of the double loop consisting of a loop (101, 111, 121) and a loop (131, 151, 141), it is necessary to increment the number of processors by one for each of these loops. Hence, it is necessary to increase the number of processors by two. If it is based on loops (102, 131), (112, 142) and (122, 152), the processors can be incremented by one for each of the loops. That is, the processors can be increased by a total of three. In the arrangement of Fig. 3 based upon a double loop structure, the processors can be incremented by a unit of one. Based upon the same idea as that of Fig. 2, the processors in the arrangement of Fig. 4 can be increased by a unit of six or by a unit of four. In the arrangement of Fig. 5, in the same manner, the processors can be increased by a unit of six processors. Increase in the number of processors changes the structure of system. Therefore, the number of processors to be increased may change thereafter. Figs. 6 to 10 illustrate methods for connecting constituent units that have three unidirectional transmission lines. In Fig. 6, the three processors 20, 21 and 22 are connected by loops (202, 212), (211, 221), (203, 223) that connect between the two processors, and by loops 201, 213, 222 of single processors. In Fig. 7, the four processors are connected by triple loops. Fig. 8 shows an example in which a processor is added to the structure of Fig. 6. Fig. 9 shows an example in which three processors are added to the structure of Fig. 6. Fig. 10 illustrates an example in which three processors are added to the structure of Fig. 9. In the structures of Figs. 7 to 10, the processors can be incremented by any integer greater than one. Figs. 11 to 13 illustrate methods of connecting constituent units that have four unidirectional transmission lines. Fig. 11 shows an example in which nine processors are arranged in a two-dimensional manner, Fig. 12 shows an example in which three processors are arranged in a one-dimensional configuration, and Fig. 13 shows an example in which 32 processors are arranged in a three-dimensional configuration. Fig. 13 is an expansion of the structure of Fig. 11. Fig. 14 shows the internal structure of the constituent units 10, 20 and 30. Responsive to the numbers 2, 3, 4 of unidirectional transmission lines of the constituent units 10, 20 and 30, however, there exist two, three or four interfaces connected to the loop transmission lines. The processor consists of a terminal 3000 and a data processing and controlling unit 300 which controls the transmission or reception of information relative to the loop transmission lines. The terminal 3000 consists of a terminal device 3005 and interfaces 3001 to 3004 between the terminal device and the data processing and controlling unit. Here, the four interfaces 3001 to 3004 make connection with different data processing and controlling units, and may be provided in any number greater than one. Described below is a process in which data generated from the terminal device 3005 is transmitted to a predetermined terminal via a loop transmission line. Data generated from the terminal device 3005 is sent to data processing and controlling units via interfaces 3001 to 3004. Data sent from the terminal device via an interface 322 is then stored in a sending buffer 317. Data is provided with an address (receiving address) of a terminal where the data will be received or a code (content code) corresponding to the content of the data. In a routine table 323 has been written a program which determines in which loop direction the data should be transmitted corresponding to the address or the content code. The program has been written onto the routine table 323 prior to sending the data. When data exists in the sending buffer 317, the operational unit 315 sends that data from any one of the interfaces 311 to 314 relying upon the routine table 323. If the data thus sent returns after having circulated through the loop, the operational unit 315 judges that the data is properly transmitted, and erases the data from the sending buffer 317. Here, the data that is to be sent is provided with an address of the interface that sends the data. The address of the interface has been stored beforehand in the ROM of interface address table 321. When data arrives flowing on the loop, the data processing and controlling unit 300 introduces the data through, for example, an interface 311, reads the address of the interface 311 from the interface address table 321, attaches the interface address, and stores the data in a receiving buffer 316. If the data received is not the data that is generated from the data processing and controlling unit 300, the data is then sent through the interface 311 that has received the data. If the data is the data that is generated from the data processing and controlling unit 300, that data is erased from the receiving buffer 316 and from the sending buffer 317 as mentioned above. As the data is taken into the receiving buffer 316, the operational unit 315 transfers the data to the terminal via the interface 322 provided the receiving address or the content code of the data is in agreement with that of a receiving function code table and address 320. Next, if the receiving address or the content code of the data is in agreement with that in the routine table 323, said data is sent in the direction of the transmission loop written thereon through interfaces 311 to 314 of directions other than the loop direction in which the data is received. When the data is sent to the terminal and to the loop direction, the data is erased from the receiving buffer 316. When the data in the sending buffer 317 and the data in the receiving buffer 316 are to be sent for the first time, each on its own loop, the data processing and controlling unit sets the timer 318 for each of the data. If the data does not return even after a predetermined period of time has passed, the data processing and controlling unit sets the flag of an abnormal status register 319 corresponding to the loop into which the data is sent. As the flag is set in the abnormal status register 319, the operational unit 315 broadcasts the abnormal condition on the loop in all directions via the interfaces 311 to 314. Upon receipt of the data which reports the abnormal condition, the data processing and controlling units broadcast the abnormal condition to the loop directions in which the data reporting the abnormal condition has not yet been received. The processor which has received the data that reports the abnormal condition converts the routine table 323 corresponding to the abnormal loop. For instance, a by-pass route may have been determined to cope with the abnormal condition that may take place in the loops, or if an abnormal condition develops somewhere, the data may be broadcast in all loop directions thereafter. In the receiving function code table and address 320 has been stored in advance a content code or an address of the data required by the terminal device 3005 that is connected to the data processing and controlling unit 300. According to the system of the present invention, the defective portion may be separated to be checked. In this case, transmission of data is continued through other portions. Further, since the constituent units are all the same, maintenance can be easily carried out. According to the present invention as described above, identical constituent units are successively connected to each other to form a plurality of looped structures. By changing the method of connection, a communication network can be constituted that can be easily changed into a one-dimensional, two-dimensional or three-dimensional structure. Further since it is based upon a looped network, transmission routing can be easily accomplished. Moreover, all of the constituent units have the same hardware and software, and no apparatus having particular functions such as a master apparatus is needed, thereby offering an advantage in regard to maintenance.

Claims: A computer system comprising a plurality of information processing and controlling units (10...15, 20...22, 30, 300), each unit being connected to a terminal device (3005) and including interface means (311) coupled to an input transmission line (30k) and an output transmission line (301) for receiving messages from, and transmitting messages to, other units, said input and output transmission lines being connected to form a first transmission loop, each message including data, a source address identifying the sending unit, and characteristic information used by the receiving units, wherein each unit includes means (315) for transferring messages from a terminal device connected to the unit onto a transmission loop, a sending buffer (317) for storing the respective message to be sent, a receiving buffer (316) for storing a message received, means (315) for comparing the source address of the received message with the unit's own address and, if these addresses are different, transferring the data stored in the receiving buffer (316) to the receiving interface means (311) for further circulation on the transmission loop and, if the characteristic information contained in the message indicates that the data contained in the message is to be used by a terminal device (3005) connected to the unit, transferring the data from the receiving buffer (316) to that terminal device, and means (315, 318, 319) including an abnormality status register (319) for detecting an abnormality of the system by checking whether a message sent by the unit returns after a predetermined period of time and, when this check is negative, setting said abnormality register (319), characterized in that each of said information processing and controlling units (10...15, 20...22, 30, 300) further includes further interface means (312...314) coupled to input and output transmission lines (301...30n, 302, 304) connected to form at least one second transmission loop, a routine table (323) indicating the interface means (311...314) to be selected for transmitting a given message, and an interface address table (321), wherein each unit provides the source address contained in the message to be sent with the address of the respective interface means (311...314) selected for transmission, and said comparing means (315) compares the interface address contained in a received message with that stored in the interface address table (321) and, if these addresses are different, transfers the data stored in the receiving buffer (316) to the respective interface means selected for transmission on the basis of the routine table (323), and wherein a unit which has its abnormality register (319) set broadcasts abnormality condition data on all transmission loops, while a unit receiving such abnormality condition data broadcasts the data to transmission loops other than those from which it received said abnormality condition data and converts its routine table (323) in accordance with the abnormal transmission loop. The system of claim 1, wherein the plurality of transmission loops intersect each other. The system of claim 1 or 2, wherein the plurality of transmission loops form a three-dimensional structure, preferably defining the surface of a cube. The system of any one of claims 1 to 3, wherein all units (10...15, 20...22, 30) are of identical construction. The system of any one of claims 1 to 4, wherein said characteristic information includes a destination address identifying the terminal device (3005) which is to receive the data contained in the respective message. The system of claim 5 wherein each unit (300) includes a code table (320) and means (315) for comparing the code stored therein with that contained in the received message. The system of any one of claims 1 to 4, wherein the characteristic information includes a content code representing the contents of the data included in the respective message.

Inventors: IHARA HIROKAZU, MIYAMOTO SHOJI, MORI KINJI, IHARA, HIROKAZU, MIYAMOTO, SHOJI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1984
Main classification: G06F15
IPC codes: G06F15, H04L12