IMAGE DATA EXPANDING AND/OR CONTRACTING METHOD AND APPARATUS

Abstract: An apparatus for expanding or contracting image data (x) includes an input register (52) storing the image data to be processed, a first barrel shifter (54) for shifting the output data of the input register (52), a control register (58) storing a mapping pattern (P) which indicates a position of the image data bits to be extracted in the expansion mode or indicates the number of times when the image data are to be copied, an expansion and contraction circuit (55) for expanding or contracting the image data by referring to the mapping pattern, and a second barrel register (56) for shifting the output image data of the expansion and contraction circuit (55) before being loaded in an output data register (57).

Description: The present invention relates to a method for expanding and/or contracting image information or data as well as an apparatus for carrying out the method. In accompaniment to the development of storage or memory devices whose capacity is more and more increased, there are developed an increasing number of apparatuses which are capable of processing rather straightforwarldy image data such as hand-written characters, graphic patterns or the like without resorting to the coding procedure. In this industrial field, a great demand exists for the processing such as expansion or contraction of the image data at an increased speed. An image processing system is disclosed in U.S. Patent No. 4267573, wherein an image is converted into a plurality of image elements which are subsequently arranged in a special pattern to provide a transformed representation of the original image. In such a transformed state, operations can be performed on the image elements to expand or contract an image. In the first place, description will briefly be made of the concept of expansion (or extension) and contraction (or compression) of image information or data (hereinafter referred to as image data). It is assumed that image data X which include a string of n picture elements or pixels X₁, X₂, ..., X n arrayed one-dimensionally on latic points, as shown in Fig. 1, is to be contacted to image data Z including m pixels Z₁, Z₂, ..., Z m . In the case of the illustrated example n = 8 and m = 5. Transformation (mapping) of the data X to Z can be realised in a manner illustrated in Fig. 2, in which 24a, 24b, ..., 24h represent the lattice points which are located closest to a straight line 23 having a slope m/n = 5/8 . The individual pixels X₁, X₂, ..., X n of the original image data are transformed to the indivudual pixels Z₁, Z₂, ..., Z₅ of the output data 22 which are located on the left side to the corresponding lattice points 24a, 24b, ..., 24h. It will be seen that the pixels X₁ and X₂ are, respectively, transformed into the output pixel Z₁, while the original pixels X₆ and X₇ are, respectively, transformed into the output pixel Z₄. For convenience' sake, the output pixel Z₁ is assumed to be constituted by the original pixel X₁ with Z₄ being constituted by X₆. The expansion corresponds to the reversion of the contraction mentioned above. In other words, the expansion may be considered as the reversion of the contraction in which the original image data is replaced by the output data while the latter is replaced by the former. Fig. 3 illustrates a manner in which the original image data 25 of X₁, ..., X₅ are expanded to the output data 26 of Z₁, Z₂, ... Z₈. Heretofore, the expansion or contraction of image data has been arithmetically determined for each of the pixels, as mentioned below. Namely, in the case of the contraction illustrated in Fig. 2, the expression for transformation of a pixel X i of the original image data 21 into a pixel Z j of the output data 22 is, by way of example, given by Z j ← X i j ← [ 5 8 i + 0.5] where [a] represents a maximum integer which does not exceed a . In the case of expansion illustrated in Fig. 3, the expression for transformation of X i into Z i is, for example, given by Z j ← X i [ 5 8 j + 0.5] → i Since the expression for transformation has to be calculated for each of the pixels, the hitherto known method is disadvantageous in that high efficiency can not be attained in the transformation processing. In this connection, reference should be made to Fig. 4. When a two-dimensional image 41 composed of n y pixels in the vertical direction and n x pixels in the horizontal direction is to be transformed into a two-dimensional image 42 which is composed of m y pixels in the vertical direction and m x pixels in the horizontal direction, it will be seen that the manner in which the transformation of n x pixels to m x pixels in the horizontal or rowwise direction can be carried out independent of the location of the pixel in the vertical or columnwise direction. Same holds true in the transformation of n y pixels to m y pixels in the vertical or columnwise direction. Accordingly, by storing the procedure for transformation determined upon transformation of the pixels on the first row or column, the succeeding transformation can be carried out by referring to the stored procedure without necessity for any renewed calculation. However, in the prior art, the calculation was repeated at every transformation, so that much time was required in accomplishing the transformation. Accordingly, an object of the present invention is to eliminate the shortcomings of the prior art and provide a method and apparatus which are capable of performing image expansion and/or contraction at a significantly increased speed. According to one aspect of the present invention there is provided an apparatus for expanding and contracting an image, comprising a first register for storing original image data, a first barrel shifter for shifting said original image data, a register for storing a mapping pattern, an expansion and contraction circuit for expanding or contracting output data of said first barrel shifter under the control of said mapping pattern, a second barrel shifter for shifting output data of said expansion and contraction circuit, and a second register for storing output data of said second barrel shifter, wherein the register stores a mapping pattern which indicates positions of data to be extracted for the contraction of the image and indicates a number of times when the data is to be copied for the expansion of the image, whereby the image data stored in said storage means is expanded or contracted by referring to said mapping pattern, and wherein said register for storing the mapping pattern is implemented as a stack structure, and wherein in expanding or contracting a two-dimensional image, said mapping pattern is arithmetically determined in dependence on the ratio of expansion or contraction only once either in a vertical direction or in a horizontal direction or in both directions, respectively, said expansion or contraction being performed by referring to said mapping pattern. According to another aspect of the present invention there is provided an apparatus for contracting an image, comprising a matrix circuit (A) having n rows and n columns (where n is an integer greater than or equal to 2) data transmission means disposed at positions (a, k, ℓ) of said matrix (A) (wherein k and ℓ are integers), and data selecting means disposed at positions (a, m,q ) of said matrix (A) (where m and q are integers), wherein when the image data (x₁, x₂, ... x n ) to be contracted are moved from the n th row toward the first row, said data transmitting means disposed on the n th row sends out the image data (x) so that said image data (x) can be inputted to the data transmitting means or said data selecting means disposed on the (n-1) th row, while said data transmitting means disposed on the r th row (wherein r is an integer) sends out said image data (x) so that said image data (x) can be inputted to said data transmitting means or said data selecting means disposed on the (r-1) th row, and wherein said data selecting means disposed on the n th row determines whether the image data (x n ) to be contracted is to be discarded or not in dependence on a control signal which corresponds to a mapping pattern indicating portions of data to be extracted for the contraction of the image (P), and wherein said integers k and ℓ are defined by x ≦ k ≦ n and k > ℓ, said integers m and q are defined by 1 ≦ m < n and q > m, said integer r is in the range 3 ≦ r ≦ n - 1 , and wherein said data selecting means disposed at the position (a m-1,q-1 ) of said matrix (A) determines in dependence on said control signal corresponding to said mapping pattern whether said image data (x) outputted from said data transmitting means or data selecting means disposed at the position (a m,q ) of said matrix (A) or said image data (x) outputted from said data transmitting means or said data selecting means disposed at the position (a m,q-1 ) of said matrix (A) is to be received as input data, and wherein said mapping pattern is arithmetically determined in dependence on the ratio of contraction only once and is stored in a register and then used for succeeding transformations without the necessity for renewed calculations. According to a further aspect of the present invention there is provided a method for contracting image data wherein a mapping pattern indicating portions of data to be extracted for the contraction of an image and comprising at least binary data (P₁, P₂, ... P n ) which is applied to image data (x₁, x₂, ... x n ) to be contracted (where n is an integer greater than or equal to 2) is provided, and wherein said image data (x₁, x₂, ... x n ) to be contracted are moved within a matrix (A) including n rows and n columns from the n th row towards the first row, and when said mapping pattern P i (where i is an integer in the range of 1 ≦ i ≦ n) has a first value, the image data (x ) i located at a position (a ii ) of said matrix (A) are disclosed while the image data (x) located at a position (a ij ) (where i + n ≦ j ≦ n ) of said matrix (A) are moved to a position (a i-1,j-1 ) within said matrix (A), and when said mapping pattern (P i ) has a second value, the image data (x) located at a position (a i,j-1 ) of said matrix are moved to the position (a i-1,j-1 ) of said matrix (A), and wherein said mapping pattern is arithmetically determined in dependence on the ratio of contraction only once and is stored and then used for succeeding transformations without the necessity for renewed calculations. According to a further aspect of the present invention there is provided a method for expanding an image, wherein a mapping pattern indicating a number of times the data is to be copied for the expansion of an cage and comprising at least binary data (P m ) (where m is an integer ≧ 1) which is applied to image data (x₁, x₂, ..., x n ) to be expanded (where n is an integer ≧ 1) is provided, and wherein while said image data (x₁, x₂, ..., x n ) to be expanded are moved within a matrix (A) of rows and ℓ ' columns (where ℓ and ℓ ' are integers ≧ 2) in the direction from the first row toward the ℓ-th row, when the mapping pattern (P i ) is of a first value (where i is an integer in the range of 1 ≦ i < ℓ), the image data (x) located at a position (a i,j ) (where j is an integer in the range of i ≦ j < ℓ) are moved to a position (a i+1,j+1 ) of the matrix and the image data (x) located at a position (a i,k ) (where k is an integer smaller than i and equals 1 only when i = 1) are moved to a position (a i+1,k ), and when the mapping pattern (P i ) is of a second value, the image data (x) located at a position a i,p (where p is an integer in the range 1 ≦ p ≦ ℓ) of the matrix (A) are moved to a position (a i+1,p ) of the matrix (A), wherein said mapping pattern is arithmetically determined in dependence on the ratio of expansion only once and is stored and then used for succeeding transformations without the necessity for renewed calculations. According to a still further aspect of the present invention there is provided an apparatus for expanding an image, comprising a matrix (A) of ℓ rows and ℓ' columns (where ℓ and ℓ ' are integers ≧ 2), data transmitting means disposed at positions (a q,r ) (where q and r are integers given by 2 ≦ q < ℓ and q > r) of said matrix, data selecting means disposed at positions (a s,t ) (where s and t are integers given by 1 < s ≦ ℓ and s ≦ t ≦ ℓ') and at the positions of the first row, wherein when the image data (x₁, ..., x n ) to be expanded (where n is an integer ≧ 1) are moved from the first row toward the ℓ-th row, the data selecting means disposed on the first row responds to a control signal corresponding corresponding to a mapping pattern indicating a number of times the data is to be copied for the expansion of an image (P₁) to input one of the image data (x u , x u+1 ) to be expanded (where 1 ≦ u < n and u = 1 only when u + 1 = 1), while the data selecting means disposed at the position (a s,t ) of the matrix responds to the control signal corresponding to the mapping pattern (P s ) to input the image data (x) from the data selecting means which is disposed either at the position (a s-1,t-1 ) or at the position (a s-1,t ) , and the data transmitting means disposed at the position (a q,r ) of the matrix (A) inputs the image data (x) from either one of said data transmitting means and said data selecting means disposed at the position (a q-1,r ), wherein said mapping pattern is arithmetically determined in dependence on the ratio of expansion only once and is stored in a register and then used for succeeding transformations without the necessity for renewed calculations. The present invention will be more apparent upon consideration of the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a view for illustrating the concept of expansion and contraction of an image; Fig. 2 is a view for illustrating a method for contracting image data; Fig. 3 is a view for illustrating a method for expanding image data; Fig. 4 is a view for illustrating the concept of expansion and contraction of a two-dimensional image; Fig. 5 shows in a block diagram a circuit arrangement for performing image expansion and contraction according to an embodiment of the invention; Fig. 6 shows in a block diagram an exemplified construction of the expansion and contraction circuit 55 shown in Fig. 5; Figs. 7A and 7B are views for illustrating the contents of the registers comprised in the expansion and contraction circuit 55 shown in Fig. 6 in its data contraction and expansion modes, respectively; Figs. 8A and 8B are views for illustrating transforming functions of the expansion and contraction circuit according to the invention; Figs. 9A, 9B and 9C are views for illustrating the structure of the barrel shifters shown in Fig. 5; Figs. 10A and 10B are views for illustrating images which are processed by the apparatus according to the present invention; Fig. 11 is a view for illustrating a mapping pattern in the state stored in the mapping pattern register shown in Fig. 5; Fig. 12 shows a sequence chart for illustrating stepwise the process of contracting image data according to the invention; Fig. 13 shows a flow chart for the process of contracting image data according to the invention; Fig. 14 shows a sequence chart for illustrating stepwise the process of expanding image data according to the invention; Fig. 15 shows a flow chart for the process of expanding image data according to the invention; Fig. 16 is a block diagram for illustrating the process of contracting image data according to another embodiment of the invention; Fig. 17 is a block diagram for illustrating the process of expanding image data according to another embodiment of the invention; Figs. 18 and 19 shows respectively a process chart and a flow chart for illustrating the process of determining arithmetically a mapping pattern according to the present invention; Fig. 20 is a view for illustrating a method for expanding or contracting a two-dimensional image; Fig. 21 is a block diagram showing the structure of the mapping pattern register of a stack configuration according to an embodiment of the invention; Fig. 22 is a view for illustrating a method for contracting data according to an embodiment of the present invention; Fig. 23 is a wiring diagram of the data contracting circuit according to an embodiment of the present invention; Fig. 24 is a view showing a circuit configuration of the data selecting means employed in the circuit shown in Fig. 23; Fig. 25 is a wiring diagram including the data selecting means shown in Fig. 24; Figs. 26A to 26H are wiring diagrams for illustrating operations of the data contracting circuit shown in Fig. 23; Fig. 27 is a wiring diagram of the data contracting circuit according to another embodiment of the invention; Fig. 28 is a view for illustrating the data contracting method according to an embodiment of the invention; Fig. 29 is a wiring diagram of the data contracting circuit according to a still another embodiment of the invention; Figs. 30A and 30B are circuit diagrams showing respectively the structure of the data selecting means employed in the circuit shown in Fig. 29; Fig. 31 is a wiring diagram of the data selecting means shown in Figs. 30A and 30B; Figs. 32A to 32H are wiring diagrams for illustrating operations of the data contracting circuit shown in Fig. 29; Fig. 33 is a wiring diagram showing the data contracting circuit according to a further embodiment of the invention; Fig. 34 is a view for illustrating the data expanding method according to an embodiment of the invention; Fig. 35 is a wiring diagram showing the data expanding circuit according to an embodiment of the invention; Fig. 36 is a circuit diagram of the data selecting means employed in the circuit shown in Fig. 35; Fig. 37 is a wiring diagram including the data selecting means shown in Fig. 36; Figs. 38A to 38H are wiring diagrams for illustrating operations of the data expanding circuit shown in Fig. 35; Fig. 39 is a wiring diagram of the data expanding circuit according to another embodiment of the invention; Figs. 40 and 41 are charts for illustrating respective processes of expansion and contraction according to the present invention; Fig. 42 is a circuit diagram for illustrating the utilization of data stored in an auxiliary register in the data expanding operation; Fig. 43 is a circuit diagram for illustrating the utilization of data stored in the auxiliary register for obtaining a logical sum in the contracting operation; Fig. 44 is an explanatory diagram for illustrating stepwise the process of obtaining a logical sum in the contracting operation with the aid of the auxiliary output register; Fig. 45 is a block diagram showing the circuit arrangement of the arithmetic unit; Figs. 46, 47 and 48 are views for illustrating the circuit arrangement and operation of the binary data counting circuit employed in the arithmetic unit shown in Fig. 45; Fig. 49 is a circuit diagram showing the structure of the decoder 246 and the selectors 248 and 241; and Figs. 50A and 50B illustrate respectively the symbol used in the decoder 246 shown in Fig. 49. Now, the invention will be described in detail in conjunction with preferred embodiments thereof by referring to the drawings. In the first place, elucidation will be made concerning the concept of expansion and contraction of an image with the aid of a mapping pattern, namely, a reference mask pattern or a control pattern. The mapping pattern is a vector which includes components "0" and/or "1" and designates positions or locations of the elements of original image data which are to be extracted in the case of the contraction while indicating the number of times at which the individual elements are to be copied. In the case of the example of contraction illustrated in Fig. 2, the mapping pattern P is represented as follows: A logical product of the above mapping pattern and the original image data X is determined for each of the elements to thereby obtain the output data Z by extracting the elements of the original image data X which correspond to "0" of the mapping pattern. More particularly, since P = (1, 0, 1, 1, 0, 1, 0, 1) and X = (X₁, X₂, X₃, X₄, X₅, X₆, X₇, X₈), (P i ·X i ) = (X₁, 0, X₃, X₄, 0, X₆, 0, X₈) Thus, the output data Z is given as follows; Z = (X₁, X₃, X₄, X₆, X₈) Similarly, in the case of the expansion illustrated in Fig. 3, the mapping pattern is given by P = (1, 0, 1, 1, 0, 1, 0, 1) as in the case of the contraction. By referring to the above pattern as of the leftmost element or bit, the original image data corresponding to "1" is renewed, while the original image data corresponding to "0" is copied. More particularly, on the assumption that P = (1, 0, 1, 1, 0, 1, 0, 1) and X = (X₁, X₂, X₃, X₄, X₅), the output data Z are given by Z = (X₁, X₁, X₂, X₃, X₃, X₄, X₄, X₅) In case where the two-dimensional data are to be transformed (i.e. expanded or contracted) on the row-by-row basis in the X-direction, as illustrated in Fig. 4, once the mapping pattern for the first row in the X-direction is arithmetically determined and stored at the beginning, the data transformation for the succeeding rows inclusive of the second row can be performed simply by referring to the stored pattern, whereby a high-speed processing can be accomplished. In the following description, it is assumed that the data to be processed is binary image data in which one bit corresponds to one picture element or pixel. A data bus is assumed to be 8 bits in width, and the processing is performed on the eight-bit basis. Further, input and output operations to and from each register are performed only on the eight-bit basis. (A set of eight bits may also be referred to as a word). Fig. 5 shows in a block diagram a general arrangement of the apparatus according to an exemplary embodiment of the invention. Original image data loaded in an input register 52 through a data bus 51 is shifted by a first barrel shifter 54 under the control of a control circuit 53. The output data of the shifter 54 is expanded or contracted by an expansion and contraction circuit 55 which is controlled in dependence on the mapping pattern. The output data of the expansion and contraction circuit 55 is, after having been shifted by a second barrel shifter 56, stored in an output register 57 to be available on the bus 51 for further processing. The input register 52 has a capacity of two words each of eight bits, wherein the eight more significant bits (MSB) and the eight less significant bits (LSB) can be inputted and outputted independent of each other. In this connection, it is assumed that the most significant bit is located at the leftmost position with the least significant bit being located at the rightmost position in the figures. The output register 57 has a capacity of two words and is so arranged that the more significant word and the less significant word can be inputted and/or outputted independently. The first barrel shifter 54 has an entrance of 16 bits in width and an exit of 8 bits, while the second barrel shifter 56 has an entry of 8 bits and an exit of 16 bits. The expansion and contraction circuit 55 is designed to perform the processing on the eight-bit basis. The mapping pattern 60 is arithmetically determined by a processing unit 60 and stored in a register 59 to be read out by a control register or mapping pattern register 58 on the eight-bit basis for controlling the expansion and contraction circuit 55. Next, the arrangement of the expansion and contraction circuit will be described, only by way of example. It should be mentioned that high-speed processing can not be accomplished to a satisfactory extent solely with the expansion and contraction circuit. The high-speed processing as desired can be accomplished by combining the expansion and contraction circuit additionally with other circuit components such as the barrel shifters. Fig. 6 shows an arrangement of the expansion and contraction circuit 55 according to an exemplary embodiment of the invention. The mapping pattern is read out from a register 61 on the eight-bit basis (i.e. eight-by-eight bits) and stored in a control register 62. On the other hand, the original image data of eight bits is stored in an input register 63. The registers 63 and 62 are constituted by shift registers which respond to clock signals a and d , respectively, for shifting the contents or data to the left, wherein the data appearing at the leftmost position of the register 63 is loaded in a buffer register 65. The clock signals a , b , c and d are of the same frequency and are delayed in phase by a small amount in the order of a , b , c and d . A numeral 67 denotes a switch circuit. In the case of the contraction, the mapping pattern value e outputted from the control register 62 in response to the clock d is transmitted to a line f by way of the switch 67. On the other hand, in the case of expansion, the mapping pattern value e is transmitted to a line g . In the contraction mode, the leftmost one of the original image data in the register 63 is loaded in the buffer 65 in response to the clock a and then responds to the clock b to be written in a register 64 at an address h designated by an address counter 66. When the value f of the mapping pattern outputted from the control register 62 is logic "l", the address counter 66 performs a counting operation, whereby the mapping pattern placed in the control register 62 is shifted to the left in response to the clock d . When the period in which a sequence of the clocks a , b , c and d appears is termed one cycle, the contracted data illustrated in Fig. 7A can be obtained in the output register 64 when eight cycles have elapsed from the starting time point. In the expansion mode, the original image data placed in the input register 63 is transferred to the buffer 65 in response to the clock a when the output value g of the mapping pattern is logic "l". The data in the buffer 65 in turn is written in the register 64 at the address h in response to the clock b . The address counter 66 operates in response to the clock c , which is followed by the shifting of the mapping pattern to the left in the register 62 in response to the clock d . Thus, after eight cycles each defined by the sequence of the clocks a , b , c and d , the expanded data illustrated in Fig. 7B are prepared in the register 64. After the operation for eight cycles in the contraction mode, the registers 62 and 63 are empty, while the register 64 is filled at the most significant five bits, as is illustrated in Fig. 7A. In the case of the expanding operation, the register 62 is found in the empty state after the eight cycles, while the register 64 is fully filled and the register 63 contains three remaining bits, as is illustrated in Fig. 7B. Accordingly, in the case of the contraction mode, it is necessary that the mapping pattern and the original image data are supplied both on the eight-bit basis while the output data have to be read out every time the register 64 becomes full, requiring troublesome processing. (This processing will be referred to as the register overflow processing). In the expansion mode, the mapping pattern is supplied on the eight-bit basis with the output data being read out also on the eight-bit basis. However, the loading of the original image data in the register 63 is required to be performed at the time point when the register 63 becomes empty, rendering the processing troublesome. (This processing will be referred to as the register empty processing). It should also be pointed out that although the memory for storing the original image data is usually so arranged that the reading of data can be performed on the 8-bit basis or on the 16-bit basis, it is impossible to read out the 8-bit data or 16-bit data from an arbitrarily selected position. It is common that the reading of data is permitted only from a predetermined position. (This position will be referred to as a word boundary.) In other words, the original image data as read out is always of eight bits from the word boundary. In this connection, it is noted that such expansion or contraction processing which is so commanded as to start from a word boundary and come to an end at another word boundary is rather rare. In other words, in many practical cases, it is required that the expansion or contraction processing starts from an intermediate bit of a word and terminates at an intermediate bit of another word. This processing is naturally troublesome. (This processing will be referred to as the word boundary processing.) It is for the purpose of performing the troublesome expansion and/or contraction processings mentioned above tactfully at a high speed that two registers 52 and 57 each of the 16-bit-capacity and two barrel shifters 54 and 56 of the equivalent bit capacity are provided, as mentioned hereinbefore in conjunction with Fig. 5. Next, the functions or rolls of these registers and shifters will be elucidated. It is assumed that the expansion and contraction circuit 55 is adapted to transform the original image data of eight bits into the left-aligned 5-bit output data at a contraction ratio of 5 / 8 in the contracting operation mode, as is illustrated in Fig. 8A. On the other hand, in the expansion mode, the expansion and contraction circuit 55 parforms translation of the left-aligned 5-bit original data into 8-bit output data at an expansion ratio of 8 / 5, as illustrated in Fig. 8B. Fig. 9A shows, by way of example, a configuration of the first barrel shifter 54. In the figure, a reference numeral 92 indicates cells each of which is constituted by a transfer gate of a structure schematically illustrated in Figs. 9B and 9C. The transfer gate is designed to interrupt the connection between signal lines p and q in response to control signal S. Referring to Fig. 9A, when a given one of the control signals S1 to S8 is validated, a given set of eight bits can be selected from the two words of 16 bits contained in the original image data register 52. In the illustrated case, the control signal S6 is assumed to be validated or turned on. Although the data bit X'₁ can not be straightforwardly transferred to a bit position of a register 91, this transfer of the bit X'₁ to the register 91 can be accomplsihed by firstly reading out the least significant eight bits and writing them at the most significant eight bit positions, which is followed by the turning-on of the control signal S1, because the original image data register 52 is so arranged that the input/output of the most and less significant eight bits can be realized indepnendent of each other. The second barrel shifter 56 may, be of a configuration corresponding to the one shown in Fig. 9A except that the input and output sides are reversed or exchanged each other so that the 8-bit input can be transferred to given bit positions of the 16-bit output register 57. Next, elucidation will be made concerning the manner in which an input image 103 illustrated in Fig. 10A is contracted to an output image 110 illustrated in Fig. 10B or inversely the input image 110 is transformed to the expanded output image 103 with the aid of the expansion and contraction circuit 55 and the associated circuits such as the barrel shifters. In Fig. 10A, the vertical lines 101 designates the boundary between words each of eight bits, and a hatched area 102 represents a single word consisting of eight bits or pixels (picture elements). In the illustrated case, it is assumed that the image 103 consists of n pixels (where n = 24) and encompasses the sixth pixel of the word 104 to the fifth pixel of the word 107, and that the image 110 consists of m pixels (where m = 15) and includes the third pixel of the word 111 to the first pixel of the word 113. In other words, the contraction at the ratio of 15/24 = 5/8 or the expansion at the ratio of 8/5 is under consideration. When the x-direction is referred to as the horizontal direction with the y-direction as the vertical direction, it is assumed that each of the images 103 and 110 consists of three pixels in the vertical direction. Further, the expansion and/or contraction are effected in such a manner in which the bottom row is firstly processed in the horizontal direction, which is then followed by the processing of the bottom second row and so forth. In precedence to the initiation of the processing, the mapping pattern is arithmetically determined on the basis of the number of original pixels n (= 24) and the number of output pixels m (= 15) and stored in the register 59 (Fig. 5) separately or distinctively for each word. The stored state is illustrated in Fig. 11. Now, the contraction will be elucidated by referring to Figs. 5 and 10 in combination with Fig. 12 which shows data flows. Initialization of the First Row Step (1): In the first place, the leading or first two words 104 and 105 of the original image data 103 are placed in the input register 52 in a manner illustrated at 121 in Fig. 12. Since the bits or pixels which undergo contraction are those which follow the pixel X₆, inclusive, of the first word, the five pixels X₁ to X₅ are unnecessary. To indicate this, the number of unnecessary pixels C i = 5 is set in an input counter 127 (Fig. 12). The remaining member n of the pixels of the original image data is 24. Next, the leading one word 111 of the output image 110 is loaded in the output register 57 at the more significant bit positions, as shown at 125 in Fig. 12. The number of valid pixels C o = 2 contained in the output register is set at an output counter 129 (Fig. 12). The number m of empty pixels in the output image is equal to 15. By the way, the input counter 127 and the output counter 129 are incorporated in the control circuit 53 shown in Fig. 5. Step (2): From the mapping pattern register 59, the first eight bits of a mapping pattern are set at the control register 58, as illustrated in Fig. 12 at 123. The number C p of "1" present in the mapping pattern is set at a counter 128 (Fig. 12) which is also incorporated in the control circuit 53 shown in Fig. 5. Step (3): The eight pixels following the pixel X₆ inclusive thereof are extracted by the first barrel shifter 54. The number of shifting to be effected is given by the value C i = 5 placed in the input counter 127. Step (4): The contracted data shown at 124 is Fig. 12 is derived with the aid of the expansion and contraction circuit 55 which is controlled in dependence on the mapping pattern 123. Step (5): The data thus obtained are loaded in the output register 57 at the bit positions following the bit y₃ through the second barrel shifter 56. The number of shifting to be effected is given by the value C o = 2 contained in the output counter 126. The value C o is updated to C o + C p = 2 + 5 = 7 . Step (6): No transfer takes place because the value C o of the output counter 126 is less than 8. Step (7): The remaining number n of the pixels of the original image data is updated. Since the pixels are consumed eight by eight in the case of contraction, the number n is updated to n-8 = 16. 〈j = 2, ℓ = 1〉 Step (8): The least significant eight bits of the input register 52 are shifted to the most significant eight bit positions, while the eight bits of the (j+1)-th word of the original image data are placed at the least significant eight bit positions, as illustrated at 131 in Fig. 12. Although the first word and the third word are denoted by using the same symbols X₁, X₂, ..., and X₈, it should be understood that these words represent different data. No variation occurs in the value C i of the input counter 127. Step (9): The step (2) mentioned above is regained and the processing is repeated to the step (5). These processing are illustrated at 131 to 134 in Fig. 12. Step (10): The contracted data shown at 134 is shifted by the second barrel shifter, as indicated by the content of the output counter 129, say 7, to thereby prepare the shifted output data shown at 135 in Fig. 12. The value C o of the output counter is updated to C o + C p = 7+5 = 12 . Step (11): Since the value C o of the output counter 129 now exceeds the value "8", the most significant eight bits are transferred to the ℓ-th word 111 of the output image data 110, while the least significant eight bits are shifted to the most significant bit positions. The value C o of the output counter 129 is updated to C o - 8 = 4 with ℓ being updated to ℓ + 1 = 2. Step (12): Again the remaining number n of the original image pixels is updated, i.e. n ← n - 8 = 8. 〈j = 3, ℓ = 2〉 Step (13): The (j+1)-th word of the original image data is loaded in the input register 52 at the less significant bit positions in the manner illustrated at 141 in Fig. 12. Since it is designated that the contraction be effected to the pixel X'₅ of the fourth word, the (j+1)-th word is the last data of the first row. The processing described above in conjunction with the steps (2) to (5) is performed to thereby derive the contracted data illustrated at 144 in Fig. 12. The output data 145 are obtained through the processing of the step (10). The value C o of the ouptut counter 129 is updated to C o + 5 = 9. Step (14): Since the value C o of the output counter 129 is still beyond "8", the most significant eight bits of the output register 57 are transferred to the word 112 of the output image data 110 while the less significant bits are shifted to the more significant bit positions. The count value C o of the output counter 129 is updated to C o - 8 = 1. Thus, ℓ ← ℓ + 1 = 3. Step (15): The remaining pixel number n is renewed. Namely, n n - 8 = 0 End Processing of the First Row Step (16): The first bit of the output data is aligned with the second bit of the word 113 of the output image data 110 and written in the word 113. This can be accomplished, for example, by setting the second bit et seq. of the output data to "0" and the first bit of the word 113 of the output image data to "0" and then by getting the logical sum for each bit position. Processing of the Second Row Step (17): A next row of the original image to be selected is determined in dependence on the expansion or contraction ratio in the vertical direction. For example, in the case of contraction at the ratio of 1/3, the third row upward is selected. On the other hand, in the case of expansion at the ratio of 3/1, the same present row is selected again. When the row of the original image to be selected is determined, the steps (2) to (16) described above are repeatedly executed. The same mapping pattern as that for the first row can be used. Accordingly, it is convenient to construct the mapping pattern register 59, for example, in a stack configuration, whereby upon completion of the processing for one row, a stack pointer is returned to the initial or start position. The flow of the processing described above is summarized in a flow chart shown in Fig. 13. As will be appreciated from the foregoing description, the image expansion or contraction processing can be accomplished at a high speed because the individual steps can be executed on the eight-bit basis, without involving the register overflow processing or word boundary processing, by virtue of the combination of the expansion and contraction circuit 55 with a pair of 16-bit registers 52 and 57 and a pair of the barrel shifters 54 and 56 according to the teaching of the present invention. Next, the expansion procedure will be elucidated by referring to Figs. 5 and 10 in combination with Fig. 14. Initialization of the First Row Step (1): The first two words 111 and 112 of the original image data 110 are placed in the input register 52 in a manner illustrated at 151 in Fig. 14. Since expansion is performed on those bits of the first word which follow y₃ inclusive thereof, the data bits y₁ and y₂ are unnecessary. Accordingly, the number of the unnecessary bits C i (= 2) is set in the input counter 127. The remaining number m of the pixels of the original image data is 15. The leading word 104 of the output image data 103 is loaded in the output register 57 at the more significant bit positions, as illustrated at 155 in Fig. 14. The number of the valid pixels C o (= 5) contained in the output register is set at the output counter 129. The number n of the empty pixels in the output image data is equal to 24. 〈j = 1〉 Step (2): The first eight bits of the mapping pattern is loaded from the mapping pattern register 59 in the control register 58, as illustrated at 153 in Fig. 14. The number C p of "1" included in the mapping pattern is set at a counter 128. In the instant case, C p = 5. Step (3): Eight pixels succeeding y₃ inclusive thereof are extracted by the first barrel shifter 54. The number of shifting to be effected is given by the value C i (= 2) contained in the input counter 127. Step (4): The expanded data 154 is derived from the expansion and contraction circuit 55 under the control of the mapping pattern 153. Step (5): The data 154 thus obtained is placed in the output register 57 at the bit position X₆ et seq. with the aid of the second barrel shifter 56. The number of shift to be effected is given by the value C o (= 5) contained in the output counter 129. Step (6): The most significant eight bits of the output register 57 are transferred to the ℓ-th word 104 of the output image data 103, while the less significant bits are shifted to the more significant bit positions. Thus, the value ℓ is updated to ℓ + 1 = 2. Step (7): The remaining pixel number n of the output image data is updated. Since eight pixels have been produced, n ← n - 8 = 16. Step (8): The value C i of the input counter 127 is updated. Namely, C i ← C i + C p = 2 + 5 = 7 . 〈j = 2〉 Step (9): Since the value C i of the input counter 127 is equal to 7 and not greater than 8, the input register 52 remains intact. Step (10): The step (2) is regained and the processing until the step (8) is repeated, as illustrated at 161 to 166 in Fig. 14. The value ℓ is updated to ℓ + 1 = 3, n is updated to n - 8 = 8, and C i is updated to C i + C p = 7 + 5 = 12 . Step (11): Since the value of C i exceeds "8", the least significant eight bits in the input register 52 are shifted to the more significant bit positions, while the succeeding word 113 of the original image data is placed at the least significant eight bits position of the input register 52. The count value C i of the input counter 127 is updated to C i - 8 = 4 . Step (12): Return is made to the step (2) and the processing to the step (8) is again performed, as illustrated at 172 to 177 in Fig. 14. The value ℓ is updated to ℓ + 1 = 4, n is updated to n - 8 = 0, and C i is updated to C i + C p = 4 + 5 = 9 . End Processing of the First Row Step (13): The five bits (C o ) of the output data 177 are aligned with the least significant three bits of the ℓ -th word 107 of the output image data 103 and written in the word 107. Processing of the Second Row Step (14): In dependence on the expansion or contraction ratio in the vertical direction, the row of the original image data to be subsequently processed is determined, and the processing at the steps (2) to (13) is repeated. The same mapping pattern as that used in the processing for the first row can be used in the processing of the second row. The flow of the processing described above is illustrated as summarized in a flow chart shown in Fig. 15. The expansion processing elucidated above can be executed at a high speed without requiring the register empty processing and the word boundary processing by virtue of the combination of the expansion and contraction circuit 55 with a pair of registers 52 and 57 and a pair of barrel shifters 54 and 56. In the case of the exemplary embodiment described so far, it has been assumed that the first barrel shifter has the entry of 16 bits in width and the exit of 8 bits in width. However, it should be appreciated that when the expansion and contraction circuit performs the processing on n-bit basis in general terms, the entry and the exist of the first barrel shifter may be of more than 2n bits and n bits, respectively. Further, the width of the data bus is not restricted to eight bits. Although the foregoing description has been made on the assumption that data to be processed are binary image data, the invention is never restricted to this type of data. The expansion and contraction according to the invention can equally be applied to the processing of a half-tone image, so far as the data is available in the binary form. Next, a second exemplary embodiment of the present invention will be described. Fig. 16 shows schematically an arrangement of the contraction circuit according to another embodiment of the invention. In the figure, a reference numeral 72 denotes a shift register for storing the original image data, 76 denotes a shift register for storing output data and a numeral 71 denotes a shift register for storing the mapping pattern. These shift registers 71, 76 and 72 are driven in response to the clock signals a , b and c which are delayed in phase relative to one another by a small amount in this order. The clock c applied to the register 72 causes the original image data stored therein to be shifted to the left, resulting in that the data bit located at the leftmost bit position (the most significant bit position) is transferred to a buffer 73. Subsequently, in response to the clock b , the data bit in the buffer 73 is loaded in the output shift register 76, provided that the pattern output d of the register 71 is logic or binary "1". On the other hand, when the pattern output d is "0", the data in the buffer 73 is not written in the output register 76. Defining a sequence of the clocks c , b and a as one cycle, the contracted data X₁, X₃, X₄, X₆, X₇ are prepared in the output register 76 after eight cycles. Fig. 17 illustrates a circuit configuration for the expansion of image data. Only when the pattern output d of the mapping pattern register 71 is "1", the original image register 72 is shifted, whereby the data at the leftmost bit position is transferred to the buffer 73. On the other hand, when the pattern output d is "0", the shifting does not take place in the original data register 72, incurring no change in the content of the buffer 73. The clocks c , b and a are delayed in phase by a small amount in this order, as in the case of the contracting operation illustrated in Fig. 16. When a sequence of the clocks c , b and a is referred to as one cycle, there are prepared the expanded data X₁, X₁, X₂, X₃, X₃, X₄, X₅, X₅ in the output register 76 after eight cycles. The arithmetic determination or calculation of the mapping pattern P (= P₁, P₂, P₃ ...) is performed in the manner mentioned below. (1) In case the original data of n pixels is contracted to m pixels, the expression for transforming the original image data X (= X₁, X₂, ..., X n ) into the output data Z (= Z₁, Z₂, ..., Z m ) is, for example, given by Z j ← X i j ← [ m n (i - 0.5)] + 1 where [a] represents the maximum integer which is not greater than a . Assuming that m/n = 5/8 , the relationships among i, j and Z j are given by i : 1, 2, 3, 4, 5, 6, 7, 8 j : 1, 1, 2, 3, 3, 4, 5, 5 Z j : X₁, X₃, X₄, X₆, X₇ It will be seen that the original image data X i be extracted at the point where j varies and included in the output data Z j . In other words, at the point where j is changed, the mapping pattern bit P i is set to "1". To this end, the initial value of 0.5 is added with 5/8. From the sum, 1 is subtracted. When the resulting difference is positive, P i is set to "1". When the difference is negative or "0", P i of "0" is carried over to the succeeding stage. This procedure of the arithmetic determination or calculation of the mapping pattern is illustrated in Fig. 18. In the figure, stages of calculation are shown at a column 101, while at a column 102 there are shown additions of m/n = 5/8 to the values of the preceding stages, respectively. The results of additions are shown at a column 103. In case the result of addition is greater than 1(one), the part exceeding 1(one) is shown at a column 104. This part (i.e. the difference resulting from subtraction of 1(one) from the result of the addition) is carried over to the succeeding stage. Unless the result of addition exceeds 1(one), the result of addition is carried over to the succeeding stage. At a column 105, elements of the mapping pattern are shown. When the result of addition exceeds 1, the corresponding pattern element assumes "1". Otherwise, the element assumes the value "0". Fig. 19 illustrates in a flow chart the calculating procedure mentioned above. Interim values are represented by a . (2) In case the original data of n pixels are expanded to m pixels, the expression of the transformation of the original image data X(= X₁, X₂, ..., X n ) into Z(= Z₁, Z₂, ..., Z m ) is, for example, given by Z j ← X i [ n m (i - 0.5)] + 1 → i The relationships among i , j and Z j are as follows: j : 1, 2, 3, 4, 5, 6, 7, 8 i : 1, 1, 2, 3, 3, 4, 5, 5 Z j : X₁, X₁, X₂, X₃, X₃, X₄, X₄, X₅ Accordingly, the mapping pattern is the same as in the case of the contraction, wherein only interpretation needs to be changed. More specifically, X k is changed at the position "1" of P i , while X k is left unvaried so long as P i assumes "0". According to the method mentioned above, the same frequency may be employed as the clock signals for driving the registers 71, 72 and 76 shown in Figs. 16 and 17, involving no necessity for generating the frequency such as (m/n)f . Next, expansion and contraction of a two-dimensional image such as shown in Fig. 20 will be considered. In the two-dimensional image, the horizontal direction (x-direction) is referred to as the row, while the vertical direction (y-direction) is referred to as the column. In case the processing is effected in such a manner in which transformation (i.e. expansion or contraction) of one row is followed by the transformation of another row which is displaced from the one row in the vertical direction, the mapping pattern P may be arithmetically determined and stored in a memory when the first row A of the original image is transformed into the first row B of the output image. Then, the transformation of the second row as well as the succeeding rows can be carried out by referring to the mapping pattern as stored. Accordingly, the processing speed can be increased ten or more times as high as the speed of processing in which the mapping pattern is determined for every transformation of the row. Next, the mapping pattern register of a stack configuration will be described by referring to Fig. 21. In many applications, the image information or data is in general stored in a storage or memory device and processed by a computer, wherein arrangement is so made that the image data can be accessed on the 8-pixel basis or 16-pixel basis. Under the circumstances, the access to the mapping pattern should preferably be compatible with the access to the image data. Now referring to Fig. 21, the original image data of 16 bits are stored in the register 72 by way of a data bus 211 of 16 bits in width. The mapping pattern is arithmetically determined by a processing unit 213 on the 16-bit basis and stored sequentially in a first-in, first-out stack 214 of 16 bits in width. For example, when the mapping pattern is required for the fifty bits, calculation of the mapping pattern is effected four times on the 16-bit basis, wherein the resulting four sets of mapping pattern data are sequentially stored in the stack 214. The address of the stored mapping pattern is designated by a stack pointer 215 and outputted to the mapping pattern register 71. The pattern output d of the register 71 is produced on a line e in the case of contraction through a switch 216 while the output d is transmitted to a line f in the case of expansion, thereby controlling the output register 76 in the former case or the original image data register 72 in the latter case. A series of operations taking place in the circuit shown in Fig. 21 will be described below in detail. Step (1): A mapping pattern is calculated and stored in the stack 134. Step (2): Initial address is set at the stack pointer 215, whereby the mapping pattern located at the address designated by the stack pointer 215 is read into the mapping pattern register 71. Step (3): The registers 72, 76 and 71 are driven in response to the clocks c , b and a , respectively, whereby the output data are prepared from the original image data and placed in the output register 76. Step (4): Updating of data is carried out. In the case of contraction, the original image data and the mapping pattern are processed during a period which corresponds to the sixteen clocks. The contracted data is stored in the output register 76. In other words, when the sixteen clocks constitute one cycle, the original image data and the mapping pattern are consumed in one cycle. In the case of expansion, the mapping pattern is consumed in one cycle, whereby the output data of 16 bits is prepared by consuming a corresponding part of the original image data. Accordingly, in the case of contraction, the mapping pattern and the original image data are updated or renewed at every cycle. The output data are read out when the output register is filled. In the case of expansion, the mapping pattern is updated at every cycle with the output data being read out. The original image data are updated at a time point when it has been consumed. The stack pointer may be automatically incremented at every cycle. Step (5): When a two-dimensional image such as illustrated in Fig. 20 is to be processed, the mapping pattern for one row is divided into segments each of 16 bits and stored in the stack 134. Upon completion of the processing for one row, the stack pointer 135 is returned to the starting position. Thus, the succeeding rows inclusive of the second row can be processed in the similar manner. As will be appreciated from the foregoing, by implementing the mapping pattern storing register 71 in the stack configuration, the mapping patterns can be sequentially read out automatically merely by setting the stack pointer 215 at the time point when the processing for the first row is initiated, whereby the processing can be performed smoothly. In the following, other concrete examples of the image contracting method according to the invention will be described. In this connection, it should be noted that the following description is based on the assumption that the registers 63 and 64 and the buffer 65 shown in Fig. 6 and the contraction device shown in Fig. 16 are employed. In the first place, it is assumed for convenience of elucidation that the original image data X includes elements or bits x₀, x₁, x₂, x₃, x₄, x₅, x₆ and x₇ and that the mapping or mask pattern P for the reference consists of 1, 0, 1, 0, 0, 0, 1 and 0, as illustrated in Fig. 22. Further, individual elements of the matrix illustrated in Fig. 22 is represented by M i,j where i designates rows and j designates columns. Referring to Fig. 22, the original image data X are initially present at the row i (= 7) and shifted from the row i to the row (i - 1) and so forth within the matrix, whereby the contracted image Y = x₀, x₂, x₆ is obtained. Upon displacement from the row i to the row (i - 1), the element M i,j where i = j is neglected or discarded when the reference mask pattern P i is "0", wherein all the elements located on the right side to the element M i,j where i = j are shifted to the left by one element. On the other hand, when the reference mask pattern (mapping pattern) P i is "1", all the elements present at that time on the row i are moved to the row (i - 1). This operation is performed for each of the elements of the row i where i = 0, whereby the contracted or compressed image Y is derived as the output data from the matrix. The concept described above will be considered concretely by applying actual values. (1) At the row i (= 7), P₇ is "0". Accordingly, the bit x₇ is neglected or discarded. Since the element M 7,8 is absent on the right side to the element M 7,7 in the instant illustrative example, the element M 6,7 is empty. Accordingly, the row i where i = 6 consists of x₀, x₁, x₂, x₃, x₄, x₅ and x₆. (2) Since P₆ = 1 for the row i (= 6), all the elements of this row is transferred to the row i = 5, which thus includes x₀, x₁, x₂, x₃, x₄, x₅ and x₆. (3) At the row i (= 5), x₅ is discarded since P₅ = "0", resulting in that all the elements located on the right side to the column j (= 5) are shifted to the left. Accordingly, the row i (= 4) includes x₀, x₁, x₂, x₃, x₄, x₅, x₆. In the similar manner, the processing is performed for the rows i (= 4 to 0), whereby the output data Y = x₀, x₅, x₆ are derived from the matrix. By imaging the column j (= 8) which includes elements all of "0", empty elements of the matrix may be set to "0". Next, a data contracting circuit for carrying out the above method will be described. As pointed out hereinbefore, this circuit corresponds to the main portion of the circuit shown in Fig. 6 or the circuit shown in Fig. 16. Fig. 23 shows a wiring diagram of the data contracting circuit according to an exemplary embodiment of the invention. In Fig. 23, reference numerals 10₀ to 10₇ denote input terminals to which image data x₀, ..., x₇ to be contracted are applied, 11₀ to 11₇ denote control input terminals to which a binary control signal corresponding to the reference mask pattern (mapping pattern) P₀, ..., P₇ is applied, and numerals 12₀ to 12₇ denote inverters, respectively. A reference numeral 13 denotes data transmitting means each provided at the location of element M j,k (where j and k are both integers and satisfy the conditions that 1 ≦ j ≦ 7 and that j > k) of a matrix consisting of eight rows and eight columns. The data transmitting means may simply be signal lines and serve for transmitting the data incoming from the above to the elements located below. A numeral 14 denotes data selecting means provided at locations of the matrix elements M s,t (where s and t are both integers and satisfy the conditions that 0 ≦ s ≦ 7 and s ≦ t). The data selecting means may be constituted by logical elements 14a, 14b, 14c and 14d in a manner illustrated in Fig. 24 and serves for selecting one of data located at the matrix element M s+1, t+1 or the matrix element M s+1,t in dependence on the control signals a s and b s which correspond to the reference mask pattern (or mapping pattern) P s supplied through the control signal input terminals 11 s . It should however be noted that the data selecting means 14 provided at the row 7 of the matrix shown in Fig. 23 serves only for determining whether the image data x₇ is discarded or not. Reference numerals 15₀ to 15₇ denote output terminals through which the contracted data Y are obtained. The operation of the data selecting means 14 will be described in detail by referring to Fig. 25. As is seen in Fig. 25, the data selecting means 14 is so arranged that the data signal c present at the matrix element M s+1, t+1 is selected as the input when the control signal a s supplied through the control input terminal 11 s is "0" and when the control signal b s is "1", i.e. when (a s , b s ) = (0, 1), while the data d present at the matrix element M s+1,t are selected as the input when the control signals a s and b s are "1" and "0", respectively, that is, when (a s , b s ) = (1, 0). With the arrangement of the matrix circuit mentioned above, operations are performed in the manner described below in detail. The reference mask pattern (or mapping pattern) P consists of 1, 0, 1, 0, 0, 0, 1, 0 and the contracted data derived finally are represented by x₀, x₂, x₆, as described hereinbefore in conjunction with Fig. 22. Firstly referring to Fig. 26A, the original image data x₀, x₁, ..., x₇ are supplied to the data transmitting means 13₀, 13₁, ..., 13₆ and the data selecting means 14₀ through the data input terminals 10₀, 10₁, ..., 10₇. Since the data selecting means 14₀ is supplied with the control signals (a₇, b₇) = (0, 1) through the control signal input terminal 11₇ at that time point, the data selecting means 14₀ selects as the input data the data on the line C while discarding the original image data bit x₇. Next referring to Fig. 26B, the original image data bits x₀, ..., x₅ located at the data transmitting means 13₀, 13₁, ..., 13₅ are sent to the data transmitting means 13₇, 13₈, ..., 13₁₂. On the other hand, the control signal (a₆, b₆) = (1, 0) are applied to the data selecting means 14₁ by way of the control signal input terminal 11₆, as the result of which the data on the line D are selected, which means that the original image data bit x₆ is inputted. Referring to Fig. 26C, the original image data x₀, x₁, ..., x₄ present at the data transmitting means 13₇, 13₈, ..., 13₁₁ are sent out to the data transmitting means 13₁₃, 13₁₄, ..., 13₁₇. On the other hand, the control signals (a₅, b₅) = (0, 1) are applied to the data selecting means 14₂ through the control signal input terminal 11₅, whereby the data on the line C is selected, resulting in the input of the original image data bit x₆. Next referring to Fig. 26D, the original image data x₀, x₁, ..., x₃ present on the data transmitting means 13₁₃, 13₁₄, ..., 13₁₆ are sent out to the data transmitting means 13₁₇, 13₁₈, ..., 13₂₀. On the other hand, the control signals (a₄, b₄) = (0, 1) are applied to the data selecting means 14₃ through the control input terminal 11₄, which results in that the data on the line C is selected, allowing the original image data bit x₆ to be inputted. Referring to Fig. 26E, the original image data x₀, x₁, x₂ present at the data transmitting means 13₁₇, 13₁₈, 13₁₉ are sent out to the data transmitting means 13₂₁, 13₂₂, 13₂₃. On the other hand, the control signal (a₃, b₃) = (0, 1) is applied to the data selecting means 14₄ through the control signal input terminal 11₃. As the consequence, the data on the line C is selected, allowing the original image data bit x₆ to be inputted. Next referring to Fig. 26F, the original image data x₀ and x₁ present at the data transmitting means 13₂₁ and 13₂₂ are sent out to the data transmitting means 13₂₄ and 13₂₅, respectively. At that time, the control signals (a₂, b₂) = (1, 0) are applied to the data selecting means 14₅ and 14₆ by way of the control signal input terminal 11. Consequently, the data on the lines D₁ and D₂ are selected, thereby allowing the original image data bits x₂ and x₆ to be inputted, respectively. Referring to Fig. 26G, the original image data bit x₀ of the data transmitting means 13₂₄ are sent out to the data transmitting means 13₂₆. On the other hand, the control signals (a₁, b₁) = (0, 1) are applied to the data selecting means 14₇ and 14₈ through the control signal input terminal 11₁, whereby the data on the lines C₁ and C₂ are selected, allowing the original image data bits x₂ and x₆ to be inputted. Referring to Fig. 26H, the data selecting means 14₉, 14₁₀ and 14₁₁ are finally applied with the control signals (a₀, b₀) = (1, 0) through the control signal input terminal 11₀, resulting in that the data on the lines D₁, D₂ and D₃ are selected to allow the original image data x₀, x₂, x₆ to be outputted. By deriving the data through the data selecting means 14₉, 14₁₀ and 14₁₁ as the final output, the contracted data Y can be obtained. By virtue of the matrix-like array of the data transmitting means 13 and the data selecting means 14, data contraction can be carried out at a high speed without requiring the clocking. Further, due to the regular circuit configuration, the matrix circuit is suited to be implemented in the form of LSI (large scale integrated circuit). Besides, merely by varying the control signal applied to the control signal input terminal 11, contracted data Y of the other types can be produced easily. Although the data transmitting means is assumed to be provided in the embodiment described above, this is only for convenience of illustration. Since the data transmitting means 13 may be replaced by simple signal lines, as noted earlier, the circuit shown in Fig. 24 may be modified to a configuration shown in Fig. 27. The above description has been made on the assumption that the invention is applied to the processing of the image data or information. It should however be appreciated that the other type of information can be processed according to the invention. Further, the invention can be applied to the sampling of information and the like processing. Next, the data contracting method according to a fourth embodiment of the invention will be described. At first, it is assumed for convenience of elucidation that the original image data X include elements or bits x₀, x₁, x₃, x₄, x₅, x₆, x₇ and that the reference mask pattern P consists of 1, 0, 1, 0, 0, 0, 1, 0, as is illustrated in Fig. 28. Further, individual elements of the matrix illustrated in Fig. 28 are represented by M i,j where i designates rows and j designates columns. Referring to Fig. 28, the original image data X are initially present at the row i (= 7) and shifted from the row i to the row (i - 1) and so forth within the matrix, whereby the contracted image Y = x₀₁,x₂₃₄₅, x₆₇ is obtained. Upon displacement from the row i to the row (i - 1), elements located on the right side to the element M i,j (where i = j) are shifted to the left by one element, when the reference mask pattern P i is "0". At that time, the element M i,j (where i = j) is ORed with the element M i,j-1 . On the other hand, when the reference mask pattern P i is "1", all the elements present at that time on the row i are moved to the row (i - 1). This operation is performed for each of the elements of the row i where i = 0, whereby the contracted image data Y is derived as the output data from the matrix. The method described here differs from the one described with reference to Fig. 22 in that the logical sum is got. The concept described above will be considered concretely by using actual values. (1) At the row i (= 7), P₇ is "0". Accordingly, the bit x₇ is ORed with x₆, resulting in that the element M 6,6 includes x₆ + x₇. Since the element M 7,8 is absent on the right side to the element M 7,7 in the instant illustrative example, the element M 6,7 is empty. Accordingly, the row i where i = 6 consists of x₀, x₁, x₂, x₃, x₄, x₅, x₆ + x₇. (2) Since P₆ = 1 for the row i = 6, all the elements of this row are transferred to the row i = 5, which thus includes x₀, x₁, x₂, x₃, x₄, x₅, x₆ + x₇. (3) At the row i = 5, x₅ is ORed with x₄ since P₅ = "0", whereby all the elements located on the right side to the column j = 5 are shifted to the left. Accordingly, the row i = 4 includes x₀, x₁, x₂, x₃, x₄, x₅, x₆ + x₇. In the similar manner, the processing is performed for the rows i where i = 4 to 0, resulting in that the output data Y = x₀ + x₁, x₂ + x₃ + x₄ + x₅, x₆ + x₇ is derived from the matrix. By assuming the presence of column j = 8 including elements of "0", empty elements of the matrix may be set to "0". Next, a data contracting circuit for carrying out the above method will be described. Fig. 29 shows a wiring diagram of the data contracting circuit according to an exemplary embodiment of the invention. In Fig. 29, reference numerals 10₀ to 10₇ denote input terminals to which image data x₀, ..., x₇ to be contracted are applied, 11₀ to 11₇ denote control input terminals to which binary control signals corresponding to the reference mask pattern (mapping pattern) P₀, ..., P₇ are applied, and numerals 12₀ to 12₇ denote inverters, respectively. A reference numeral 13 denotes data transmitting means each provided at the location of element M j,k (where j and k are both integers and satisfy the conditions that 1 ≦ j < 7 and j > k + 1) of a matrix consisting of eight rows and eight columns. The data transmitting means may simply be signal lines and serve for transmitting the data incoming from the above to the elements located below. A numeral 14 denotes data selecting means provided at locations of the matrix elements M s,t (where s and t are both integers and satisfy the conditions that 0 ≦ s ≦ 7 and s ≦ t.). The data selecting means may be constituted by logical elements 14a, 14b, 14c and 14d in a manner illustrated in Fig. 30 and serves for selecting one of data located at the matrix element M s+1,t+1 or the matrix element M s+1,t in dependence on the control signals a s and b s which correspond to the reference mask pattern P₅ supplied through the control signal input terminals 11₅. It should however be noted that the data selecting means 14 provided at the row 7 of the matrix M serves only for determining whether the image data is to be discarded or not. A reference numeral 16 denotes data selecting means located at the position of the matrix element M i,i-1 and serving for selecting either one of the logical sum of the data located at the matrix elements M i+1,i and M i+1,i-1 or the data located at the matrix element M i+1,i-1 in dependence on the control signals a i and b i which correspond to the reference mask pattern P i supplied through the control input terminal 11 i . This data selecting means 16 is composed of logical elements 16a, 16b, 16c, 16d and 16e connected in the manner illustrated in Fig. 30. The data selecting means 16 differs from the data selecting means 14 in that a logical sum of data d and c is inputted in place of the data c . Refrence numerals 15₀ to 15₇ denote output terminals through which the contracted data Y are obtained. The operation of the data selecting means will be described in detail by referring to Fig. 31. As will be seen in Fig. 31, the data selecting means 14 is so arranged that the data signal c present at the matrix element M s+1,t+1 is selected as the input when the control signal a s supplied through the control input terminal 11 s is "0" and when the control signal b s is "1", i.e. when (a s , b s ) = (0, 1), while the data selecting means 16 selects as the input the logical sum of data e and f located at M s+1,t and M s+1,t-1 , respectively. On the other hand, the data d present at the matrix element M s+1,t is selected by the data selecting means 14 as the input when the control signals a s and b s are "1" and "0", respectively, that is, when (a s , b s ) = (1, 0), while the data selecting means 16 selects as the input the data f located at the matrix element M s+1,t-1 . With the arrangement of the matrix circuit mentioned above, operations are performed in the manner described below in detail. It is again assumed that the reference mask pattern P consists of 1, 0, 1, 0, 0, 0, 1, 0 and the contracted data derived finally are represented by x₀ + x₁, x₂ + x₃ + x₄ + x₅, x₆ + x₇, as described hereinbefore in conjunction with Fig. 28. Firstly referring to Fig. 32, the original image data x₀, x₁, ..., x7 are supplied to the data transmitting means 13₀, 13₁, ..., 13₅ and the data selecting means 16₀ and 14₀ through the data input terminals 10₀, 10₁, ..., 10₇. Since the data selecting means 14₀ is supplied with the control signals (a₇, b₇) = (0, 1) through the control signal input terminal 11₇ at that time point, the data selecting means 14₀ selects as the input data the data on the line C, while the data selecting means 16₀ selects the logical sum x₆₇ = x₆ + x₇ of respective signals on the lines E and F. (Hereinafter, a logical sum of data x₁, x₂,..., x i will be described as x 12...i .) Next referring to Fig. 32B, the original image data bits x₀, ..., x₄ located at the data transmitting means 13₀, 13₁, ..., 13₄ are sent to the data transmitting means 13₆, 13₇, ..., 13₁₀. On the other hand, the control signals (a₆, b₆) = (1, 0) are applied to the data selecting means 14₁ and 16₁ by way of the control signal input terminal 11₆, as the result of which the data on the line D is selected by the data selecting means 14₁, which means that the original image data x₆₇ is inputted to the data selecting means 14₁, while the data selecting means 16₁ selects as the input the data bit x₅ on the line F. Referring to Fig. 32C, the original image data x₀, x₁, x₂, x₃ present at the data transmitting means 13₆, 13₇, 13₈, 13₉ are sent out to the data transmitting means 13₁₁, 13₁₂, 13₁₃, 13₁₄. On the other hand, since the control signals (a₅, b₅) = (0, 1) are applied to the data selecting means 14₂ through the control signal input terminal 11₅, the data selecting means 14₂ selects the original image data x₆₇ on the line C, while the data selecting means 16₂ selects the logical sum x₄₅ of the signals on the lines E and F. Next referring to Fig. 32D, the original image data x₀, x₁, x₂ present on the data transmitting means 13₁₁, 13₁₂, 13₁₃ are sent out to the data transmitting means 13₁₅, 13₁₆, 13₁₇. On the other hand, the control signals (a₄, b₄) = (0, 1) are applied to the data selecting means 14₃, 16₃ through the control input terminal 11₄, which results in that the data on the line C is selected by the data selecting means 14₃, allowing the original image data bit x₆ to be inputted, while the data selecting means 16₃ selects the logical sum x₃₄₅ of the signals on the lines E and F. Referring to Fig. 32E, the original image data information x₀, x₁ present at the data transmitting means 13₁₅ and 13₁₆ are sent out to the data transmitting means 13₁₈ and 13₁₉. On the other hand, the control signals (a₃, b₃) = (0, 1) are applied through the control signal input terminal 11₃. As the consequence, the data on the line C is selected by the data selecting means 14₄, allowing the original image data bit x₆ to be inputted, while the data selecting means 16₄ selects the logical sum x₂₃₄₅ of the signals on the lines E and F. Next referring to Fig. 32F, the original image data x₀ present at the data transmitting means 13₁₈ are sent out to the data transmitting means 13₂₀. At that time, the control signals (a₂, b₂) = (1, 0) are applied to the data selecting means 14₅, 14₆ and 16₅ by way of the control signal input terminal 11. Consequently, the data on the lines D₁ and D₂ are selected by the data selecting means 14₅ and 15₆, thereby allowing the original image data bits x₂₃₄₅ and x₆₇ to be inputted, respectively, while the data selecting means 16₅ selects the data on the line F, allowing the original image data x₁ to be inputted. Referring to Fig. 32G, the control signals (a₁, b₁) = (0, 1) are applied to the data selecting means 14₇, 14₈ and 16₆ through the control signal input terminal 11₁, whereby the data on the lines C₁ and C₂ are selected by the selecting means 14₇ and 14₈, allowing the original image data bits x₂₃₄₅ and x₆₇ to be inputted, while the data selecting means 16₆ selects the logical sum x₀₁ of the data on the lines E and F. Referring to Fig. 32H, the data selecting means 14₉, 14₁₀ and 14₁₁ are finally supplied with the control signals (a₀, b₀) = (1, 0) through the control signal input terminal 11₀, resulting in that the data on the lines D₁, D₂ and D₃ are selected to allow the original image data x₀₁, x₂₃₄₅ and x₆₇ to be outputted. By deriving the data through the data selecting means 14₉, 14₁₀ and 14₁₁ as the final output, the contracted data Y can be obtained. By virtue of the matrix-like array of the data transmitting means 13 and the data selecting means 14 and 16, data contraction can be carried out at a high speed without requiring clocking. Further, due to the regular circuit configuration, the matrix circuit is suited to be implemented in the form of LSI. Further, by deriving the logical sum of the adjacent data upon contraction of the original image data, the logic "l" data will not disappear. Accordingly, the frame of table prepared by the logic "l" bits is not erased by the data contraction. Besides, merely by varying the control signal applied to the control signal input terminal 11, the contracted data Y of the other type can be produced easily. Although the data transmitting means are assumed to be provided in the embodiment described above, this is only for convenience of illustration. Since the data transmitting means 13 may be replaced by simple signal lines, as described earlier, the circuit shown in Fig. 29 may be modified to a configuration shown in Fig. 33. Although the OR-function is adopted as the arithmetic operation for the data contraction, other logical functions may be adopted. Further, although the above description has been made on the assumption that the invention is applied to the processing of the image data or information, it will be apparent that the other type of information can be processed according to the teaching of the invention. Moreover, the invention can be applied to the sampling of information and the like processing. Next, a data expanding method according to a fifth embodiment of the invention will be described. It is again assumed for convenience of elucidation that the original image data X includes elements or bits x₀, x₁, x₂, x₃, x₄, x₅, x₆ and x₇ and that the mapping or reference mask pattern P consists of 1, 0, 1, 0, 0, 0, 1, 0 as illustrated in Fig. 34. Further, individual elements of the matrix illustrated in Fig. 34 are represented by M i,j where i designates rows and j designates columns. Referring to Fig. 34, the original image data X are initially present at the row i (= 0) and shifted from the row i to the row (i + 1) and so forth within the matrix, whereby the expanded image Y = x₀, x₀, x₁, x₁, x₁, x₁, x₂, x₂ is obtained. Upon displacement from the row i to the row (i + 1), all the elements located on the row i are shifted to the row (i + 1), when the reference mask pattern P i is "1". On the other hand, when the reference mask pattern P i is "0", the elements j (= 0) to j (=i - 2) are transferred to the row (i + 1), while the elements located from j (= i - 1) to the rightmost position are shifted by one element to the right to be transferred to the row (i + 1). This operation is performed for each of the rows up to the row where i = 7, whereby the expanded image Y is derived as the output data from the matrix. The concept described above will be considered concretely by applying actual values. (1) At the row i (= 0), P₀ is "1". Accordingly, all the bits or elements on the row 0 are transferred to the row 1. Accordingly, the row i where i = 1 consists of x₀, x₁, x₂, x₃, x₄, x₅, x₆, x₇. (2) Since P₁ = 0 for the row i = 1, the element M₁₀ is mapped to M₂₀, while M₁₀ to M₁₇ are sequentially mapped to M₂₁ to M₂₇. Thus, the row i = 2 includes x₀, x₀, x₁, x₂, x₃, x₄, x₅ and x₆. (3) At the row i = 2, all the elements on the second row are mapped or moved to the third row, since P₂ = "1". Accordingly, the row i = 3 includes x₀, x₀, x₁, x₂, x₃, x₄, x₅, x₆. (4) In the similar manner, the processing is performed for the rows i = 3 to 7, whereby the output data Y = x₀, x₀, x₁, x₁, x₁, x₁, x₂, x₂ can be obtained from the matrix. Next, a data expanding circuit for carrying out the above method will be described. Fig. 35 shows a wiring diagram of the data expanding circuit according to an exemplary embodiment of the invention. In Fig. 35, reference numerals 10₀ to 10₇ denote input terminals to which image data x₀, ..., x₇ to be expanded are applied, 11₀ to 11₇ denote control input terminals to which a binary control signal corresponding to the reference mask pattern (mapping pattern) P₀, ..., P₇ is applied, and numerals 12₀ to 12₇ denote inverters, respectively. A reference numeral 13 denotes data transmitting means each provided at the location of element M j,k (where j and k are both integers and satisfy the conditions that 1 ≦ j ≦ 7 and j > k) of a matrix consisting of eight rows and eight columns. The data transmitting means may simply be signal lines and serve for transmitting the data incoming from the above to the elements located below. A numeral 14 denotes data selecting means provided at locations of the matrix elements M s,t (where s and t are both integers and satisfy the conditions that 0 ≦ s ≦ 7 and s ≦ t). The data selecting means may be constituted by logical elements 14a, 14b, 14c and 14d in the manner illustrated in Fig. 36 and serves for selecting one of data located at the matrix element M s-1,t-1 or the matrix element M s-1,t in dependence on the control signals a s and b s which correspond to the reference mask pattern (or mapping pattern) P s supplied through the control signal input terminals 11 s . Reference numerals 15₀ to 15₇ denote output terminals through which the expanded image Y are obtained. The operation of the data selecting means 14 will be described in detail by referring to Fig. 37. As will be seen in Fig. 37, the data selecting means 14 is so arranged that the data signal c present at the the matrix element M s-1,t-1 is selected as the input when the control signal a s supplied through the control input terminal 11 s is "0" and when the control signal b s is "1", i.e. when (a x , b s ) = (0, 1), while the data d present at the matrix element M s-1, t is selected as the input when the control signals a s and b s are "1" and "0", respectively, that is, when (a s , b s ) = (1, 0). With the arrangement of the matrix circuit mentioned above, operations are performed in the manner described below in detail. It is again assumed that the reference mask pattern (or mapping pattern) P consists of 1, 0, 1, 0, 0, 0, 1, 0 and the expanded data to be derived finally is represented by x₀, x₀, x₁, x₁, x₁, x₁, x₂, x₂. Firstly referring to Fig. 38A, the original image data x₀, x₁, ..., x₇ are supplied to the data selecting means 14₀, 14₁, ..., 14₇ through the data input terminals 10₀, 10₁, ..., 10₇. Since the data selecting means 14₀ to 14₇ are supplied with the control signals (a₀, b₀) = (1, 0) through the control signal input terminal 11₀ at that time point, the data selecting means 14₀ to 14₇ select as the input data thereto the data on the lines D₀ to D₇, respectively, whereby the original image data x₀, x₁, ..., x₇ are inputted. Next referring to Fig. 38B, the original image data bits x₀ located at the data selecting means 14₀ is sent to the data transmitting means 13₀. On the other hand, the control signals (a₁, b₁) = (0, 1) are applied to the data selecting means 14₈, ..., 14₁₄ by way of the control signal input terminal 11₁, as the result of which the data on the lines C₀, ..., C₆ are selected, which means that the original image data bit x₀, ..., x₆ are inputted. Referring to Fig. 38C, the original image data x₀ present at the data transmitting means 13₀ and the data selecting means 14₈ are sent out to the data transmitting means 13₁ and 13₂. On the other hand, the control signals (a₂, b₂) = (1, 0) are applied to the data selecting means 14₁₅ to 14₂₀ through the control signal input terminal 11₂, whereby the data on the lines D₈, ..., D₁₄ are selected, resulting in inputting the original image data x₀, ..., x₆. Next referring to Fig. 38D, the original image data x₀ and x₁ present on the data transmitting means 13₁ and 13₂ and the data selecting means 14₁₅, respectively, are sent out to the data transmitting means 13₃, ..., 13₅. On the other hand, the control signals (a₃, b₃) = (0, 1) are applied to the data selecting means 14₂₁ to 14₂₅ through the control input terminal 11₃, which results in that the data on the lines C₇, ..., C₁₁ are selected, allowing the original image data x₁, ..., x₅ to be inputted. Referring to Fig. 38E, the original image data x₀ and x₁ present at the data transmitting means 13₃, 13₄, 13₅ and the data selecting means 14₂₁ are sent out to the data transmitting means 13₆, ..., 13₉. On the other hand, the control signals (a₄, b₄) = (0, 1) are applied to the data selecting means 14₂₆, ..., 14₂₉ through the control signal input terminal 11₄. As a consequence, the data on the lines C₁₂, ..., C₁₅ are selected, allowing the original image data x₁, ..., x₄ to be inputted. Next referring to Fig. 38F, the original image data x₀ and x₁ present at the data transmitting means 13₆, ..., 13₉ and the data selecting means 14₂₆, respectively, are sent out to the data transmitting means 13₁₀, ..., 13₁₄, respectively. At that time, the control signals (a₅, b₅) = (0, 1) are applied to the data selecting means 14₃₀, 14₃₁ and 14₃₂ by way of the control signal input terminal 11. Consequently, the data on the lines C₁₆, ..., C₁₈ are selected, thereby allowing the original image data bits x₁, x₂, x₃ to be inputted, respectively. Referring to Fig. 38G, the original image data bit x₀ and x₁ of the data transmitting means 13₁₀, ..., 13₁₄ and the data selecting means 14₃₀, respectively, are sent out to the data transmitting means 13₁₅, ..., 13₂₀. On the other hand, the control signals (a₆, b₆) = (1, 0) are applied to the data selectint means 14₃₃ and 14₃₄ through the control signal input terminal 11₆, whereby the data on the lines D₁₅ and D₁₆ are selected, allowing the original image data x₂, x₃ to be inputted. Referring to Fig. 38H, the image data x₀, x₁, x₂ at the signal transmitting means 13₅, ..., 13₁₆ and the data selecting means 14₃₃ are sent out to the signal transmitting means 13₂₁, ..., 13₂₇, respectively. On the other hand, the data selecting means 14 is applied with the control signals (a₇, b₇) = (0, 1) through the control signal input terminal 11₇, resulting in that the data on the line D₁₉ is selected to allow the original image data x₂ to be inputted. Thus, through the output terminals 15₆ and 15₇, the expanded original image data Y = x₀, x₁, x₁, x₁, x₁, x₂, x₂ can be derived. By virtue of the matrix-like array of the data transmitting means 13 and the data selecting means 14, data expansion can be carried out at a high speed without requiring clocking. Further, due to the regular circuit configuration, the matrix circuit is suited to be implemented in the form of LSI. Besides, merely by varying the control signal applied to the control signal input terminal 11, the expanded data Y of the other type can be produced easily. Although the data transmitting means 13 are assumed to be provided in the embodiment described above, this is only for convenience of illustration. Since the data transmitting means 13 may be replaced by simple signal lines, as described earlier, the circuit shown in Fig. 35 may be modified to a configuration shown in Fig. 39. The above description has been made on the assumption that the invention is applied to the processing of the image data or information. It should however be appreciated that the other type of information can be processed according to the invention. In the data contracting circuit shown in Fig. 23, only the data x₀, x₂, x₆ at the mapping (or reference masking) pattern "1" are extracted with other original image data being lost. In order to make use of the image data which would be lost otherwise, the circuit shown in Fig. 29 is so arranged that the data at the mapping pattern "1" is logically ORed with the data at the succeeding mapping pattern so that the final data x 0,1 , x 2,3,4,5 , x 6,7 may be obtained. Here the notation x i,j,k represents the logical sum of the data x i , x j and x k . To realize this processing, the wiring from a given element M i,i on the diametrical line to an adjacent element M i,i-1 located on the left side of the given element M i,i in the contraction circuit shown in Fig. 23 is changed as shown in Fig. 29. In the circuit shown in Fig. 23, the data at M i+1,i-1 are stored as they are. However, in the circuit shown in Fig. 29, the data at M i+1,i-1 is ORed with the data at M i+1,i in the processing at the mapping pattern "0". In the circuit Shown in Fig. 29, however, the logical sum for the first data is not got. Next, description will be made of an auxiliary register 580 which may be used in the expansion or contraction circuit according to the invention. In the expansion and contraction circuit 55 which is shown in Fig. 5 and constituted by the expansion circuit and contraction circuit, the number of data processed in a single processing corresponds to the number of "1" present in the mapping pattern in the case of the expansion processing, while the number of data processed is always equal to 8 in the case of the contraction processing, as will be seen from Figs. 2 and 3. On the other hand, the number of data produced through a single processing is constantly eight in the case of the expansion processing, while the number of data in question corresponds to the number of "1" present in the mapping pattern in the case of contraction. Referring to Fig. 40, the original image data stored in the input register 52 is shifted upon every processing to the left by a number corresponding to the number of bits "1" included in the mapping pattern (the number of bits "1" included in the mapping pattern will be hereinafter represented by NB), wherein the resulting empty bit positions are filled with the bits of the succeeding original image data. In the case of the expansion processing, data is renewed at the bit "1" of the mapping pattern, while the preceding data are copied at the bit "0" of the mapping pattern. Accordingly, when the leading data bit of the mapping pattern is "0", as illustrated in Fig. 40 by a reference numeral 1910, the final data x₅ which has been produced through the immediately preceding processing becomes necessary. To this end, the auxiliary register 580 for storing the required data bit in the data produced through the immediately preceding processing is provided on the left side to the input register 52, as is shown in Fig. 40. Since the data x₅ is the final pixel data FB generated through the preceding processing, the data FB is extracted with the aid of an arithmetic circuit 590 and loaded in the auxiliary register 580. The arithmetic circuit or unit 590 serves to arithmetically determine the data to be supplied to the auxiliary data register 580 in the expansion or contraction processing. Details of this arithmetic circuit will be described later or by referring to Figs. 45 to 50. In contrast, when the leading bit of the mapping pattern is "1", as indicated in Fig. 40 by a reference numeral 1920, there arises no necessity for returning the final data bit FB to the auxiliary register 580. Referring to Fig. 41, in the case of the contraction processing, the original image data stored in the input register 52 are all referred to and utilized on the eight-bit basis upon every processing inclusive of the processing in which a logical sum is got. Accordingly, the original image data in the register 52 are all replaced by the fresh data upon every processing. However, when the logical sum is to be determined in the contraction processing, the data corresponding to the bit "1" of the mapping pattern is ORed with the data corresponding to the bit "0" of the mapping pattern. Accordingly, when the leading bit of the mapping pattern is "0", as indicated by a reference numeral 2010, the final data bit FB contained in the data prepared through the preceding processing is required for realizing the logical OR-function. Under the circumstances, the final bit FB is extracted by means of the arithmetic circuit 590 and stored in the auxiliary register 580. The number of data bits to be produced corresponds to NB (which represents the number of "1" included in the mapping pattern) plus 1(one). In the second and third processings illustrated in Fig. 41, NB is 4 and 2, respectively, while the number of the produced data is 5 and 3, respectively. In this connection, it should be mentioned that the leading data x₇₈₁, generated through the second processing illustrated in Fig. 41 is in fact a logical product of the final data FB = x₇₈ produced through the preceding processing and x₁'. Thus, x₇₈ should be replaced by x₇₈₁'. In the case of the mapping pattern whose leading bit is "1", as denoted by a reference numeral 2020, there is no necessity for returning FB to the auxiliary register 580. In summary, the arithmetic circuit 590 plays no part when the leading bit of the mapping pattern is "1". In this case, data in the auxiliary register is indeterminate or indefinite. When the leading bit of the mapping pattern is "0" in the expansion processing, the eighth pixel data of those generated through the preceding processing is returned to the auxiliary register 580. When the leading bit of the mapping pattern is "0" in the contraction processing in which the OR-function is included, NB which represents the number of "1" contained in the mapping pattern which was referred to in the preceding processing is determined, and the (NB + 1)-th pixel data among those produced through the preceding processing is returned to the auxiliary register 580, whereby upon completion of the currently performed processing, the final bit of the data resulted from the preceding processing is replaced by the leading bit of the data generated through the currently performed processing. The counting of the number of "1" contained in the mapping pattern may be realized, for example, by shifting the mapping pattern bit by bit and counting the number of times when the carry is set. Next, a concrete circuit configuration in which the auxiliary register 580 is made use of will be described. In the case of the expansion processing, the left input to the top left element M₀₀ shown in Fig. 35 is connected to the ground. This left input is disconnected from the ground and connected to the auxiliary register 580 as indicated by an input line 2110 to the element M₀₀ in Fig. 42. In the contraction processing in which the OR-function is included, a circuit similar to the bottom left element M₀₀ shown in Fig. 23 is additionally provided on the left side of the latter and connected to the output x M of the auxiliary register 580, as is shown in Fig. 43 (where A represent a circuit point to which the logic "l" signal is applied). Then, the leading data x₇₈₁' generated through the second processing shown in Fig. 41 appears at the output y M which is positioned on the left side to the output y₀. Accordingly, one bit position is additionally provided in the output register at the left, to store the output y M . The processing of the generated data may be effected including this data y M . As described earlier, the leading data x₇₈₁' generated through the second processing illustrated in Fig. 41 which is effected for the data contraction and includes the OR function represents the logical sum of the final bit FB=x₇₈ produced through the first processing and x₁', and thus x₇₈ has to be replaced by x₇₈₁'. In this case, the number of data produced through the first processing was not five but in fact four. This fact can be indicated only by the leading bit of the mapping pattern for the second processing, thus involving a difficulty in the execution of the processing. With a view to overcoming the problem mentioned above, an output auxiliary register 2110 is provided on the left side to the output register 57 as shown in Fig. 44, wherein the data produced in correspondence to the leading bit of "1" of the mapping pattern are stored in the output auxiliary register 2110 for replacing the final data produced through the preceding processing by the data stored in the register 2110. More specifically, taking as an example the second processing illustrated in Fig. 44, the data x₇₈ in the auxiliary register 580 is ORed with x₁', resulting in x₇₈₁' which is then stored in the output auxiliary register 2110, whereby the final data x₇₈ produced through the first processing is replaced by x₇₈₁'. Since the number of data produced in the output register 57 equals to the number NB (i.e. 4 in the instant case) indicating the number of "1" included in the mapping pattern, the fourth data x 7'8' is returned to the auxiliary register 580. When the leading data of the mapping pattern is "1", the number of data as generated is equal to NB. Accordingly, the NB-the data bit is returned to the auxiliary register 580. In this manner, by providing two auxiliary registers 580 and 2110, operations for the expansion processing, the contraction processing as well as the contraction processing including the OR function (also referred to contraction-OR processing) can be performed by using a common circuit. In the foregoing, the flow of the processing has been elucidated on the assumption that the output auxiliary register 2110 is separately provided for convenience of description. It will however be appreciated that since the output auxiliary register is operated at the same timing as the output register 57, the former can be realized as an integral part of the latter. In contrast, the data to be stored in the auxiliary register 580 is produced through the preceding processing. Accordingly, a storage means for storing this data is required to be provided independent of the input register. Now, the arithmetic circuit 590 will be described. An exemplary circuit arrangement of this arithmetic unit is shown in the block diagram of Fig. 45. Referring to the figure, a selector 241 is controlled by control signals 242a or 242b which are changed over in dependence on the expansion processing or contraction-OR processing (i.e. contraction processing including the logical OR function), to select the eight data bit 243a of the data 51a generated by the expansion and contraction circuit 55 in the case of the expansion processing. On the other hand, in the case of the contraction-OR processing, the selector 241 responds to a decoded signal 247a outputted from a decoder 246 which is supplied with a singal 245a produced by a binary data counting circuit 244 and representing NB which is the number of bits "1" included in the mapping pattern stored in the control register 58, to thereby select the NB-the data bit 243b of the generated data 51a. Next, the individual circuits represented by blocks in Fig. 45 will be described. Figs. 46, 47 and 48 show an exemplary embodiment of the binary data counting circuit 244. Fig. 46 shows the same in a block diagram. The mapping pattern consisting of 8 bits is divided into two segments each of 4 bits. A pair of one-bit adders 1011 and 1012 provided at the first stage determine the number of "1" included in the respective inputs each of 3 bits (i.e. a₇, a₆, a₅ for the adder 1011, and a₃, a₂, a₁ for the adder 1012), which is followed by the determination of the number of "1" included in 4 bits by incrementers 1021 and 1022, respectively. Finally, a three-bit adder 110 determines the number of "1" included in the mapping pattern of 8 bits, this number being outputted as the four-bit signal 245a. A circuit configuration of the one-bit adder 1012 and the incrementer 1022 for the four bits a₃, a₂, a₁, a₀ is shown in Fig. 47. Details of operation will be described by referring to Fig. 47. Two bits a₃ and a₂ of the 4-bit input data A(a₃, a₂, a₁, a₀) denoted by a numeral 71 are added by means of an adder constituted by an AND (logical product) circuit 921 and an EOR (Exclusive-OR) circuit 922, whereby a sum signal Σ₀₀ and a carry C₀₀ are produced. The sum signal Σ₀₀ and the bit a₁ of the input data 71 are added by an adder constituted by an AND circuit 931 and an EOR circuit 932, resulting in that a sum signal Σ₁₀ and a carry signal C₁₀ are produced. The signals C₀₀ and C₁₀ are combined by a NAND circuit 96 to produce a carry signal C₂₀. The number of "1" included in three bits a₃, a₂, a₁ of the input data 71 is represented by the sum Σ₁₀ and the carry C₂₀. The sum signal Σ₁₀ and the bit a₀ of the input data 71 are added by an adder constituted by an AND circuit 971 and an EOR circuit 972, whereby a sum signal Σ₃₀ and a carry signal C₃₀ are produced. The carry signals C₃₀ and C₂₀ are added by an adder constituted by an AND circuit 981 and an EOR circuit 982, resulting in that sum signals Σ₃₁ and Σ₃₂ are produced. These three bits Σ₃₀, Σ₃₁ and Σ₃₂ are added with other three bits prepared from the other input data of a₄, a₅, a₆, a₇ in the similar manner by a three-bit adder 110 shown in Fig. 48 to thereby produce data of four bits Σ₀, Σ₁, Σ₂ and Σ₃. Fig. 49 shows a circuit diagram of the decoder 246 and the selector 241. The meaning of symbols used in the decoder 246 is illustrated in Fig. 50. More specifically, a circuit configuration shown in 50A is equivalent to that shown in Fig. 50B. Referring to Fig. 49, Σ₃, Σ₂, Σ₁ and Σ₀ represent the number NB of "1" contained in the mapping pattern. When NB is 0(zero), a signal 281a is logic "l", resulting in that y M is outputted as the signal 243b. As the value of NB is increased, y₀, y₁, ..., or y₇ is correspondingly outputted as the signal 243b. In the case of contraction-OR processing, the signal 242b is logic "l", while the signal 242a is "0", whereby the signal 243b is outputted on the line 249a to be subsequently stored in the auxiliary register 580. In the case of the expansion processing, the signal 242b is "0" and 242a is "1", whereby y₇ is constantly outputted on the line 249a to be stored in the auxiliary register.

Claims: An apparatus for expanding and contracting an image, comprising a first register (52) for storing original image data, a first barrel shifter (54) for shifting said original image data, a register (58, 59; 61, 62; 71, 214, 215) for storing a mapping pattern, an expansion and contraction circuit (55) for expanding or contracting output data of said first barrel shifter (54) under the control of said mapping pattern, a second barrel shifter (56) for shifting output data of said expansion and contraction circuit (55), and a second register (57) for storing output data of said second barrel shifter (56), wherein the register (59; 71) stores a mapping pattern (P) which indicates positions of data to be extracted for the contraction of the image and indicates a number of times when the data is to be copied for the expansion of the image, whereby the image data stored in said storage means (52) is expanded or contracted by referring to said mapping pattern, and wherein said register (71) for storing the mapping pattern is implemented as a stack structure (71, 214, 215, Fig. 21), and wherein in expanding or contracting a two-dimensional image, said mapping pattern is arithmetically determined in dependence on the ratio of expansion or contraction only once either in a vertical direction or in a horizontal direction or in both directions, respectively, said expansion or contraction being performed by referring to said mapping pattern. An apparatus for expanding and contracting an image according to claim 1, wherein when an expansion ratio is given by n/m with a contraction ratio being given by m/n (where n > m), each of said first and second registers (52, 57) is of 2n bits, said first barrel register having an entry of 2n bits and an exit of n bits, while said second barrel register has an entry of n bits and an exit of 2n bits. An image expanding and contracting apparatus according to claim 2 including a second register (580) for storing the last pixel data of a pixel data string generated through the expansion or contraction processing and said expansion and contraction circuit (55) is arranged to expand or contract the image by processing simultaneously a plurality of image data stored in said storage means and said second register by referring to said mapping pattern. An image expanding and contracting apparatus according to claim 3, including a logical arithmetic circuit (244, 246, 248, 241) for extracting the last pixel data of the pixel data string generated through the expansion or contraction processing. An apparatus for contracting an image, comprising a matrix circuit (A) having n rows and n columns (where n is an integer greater than or equal to 2) data transmission means disposed at positions (a, k, ℓ) of said matrix (A) (wherein k and ℓ are integers), and data selecting means disposed at positions (a, m,q ) of said matrix (A) (where m and q are integers), wherein when the image data (x₁, x₂, ... x n ) to be contracted are moved from the n th row toward the first row, said data transmitting means disposed on the n th row sends out the image data (x) so that said image data (x) can be inputted to the data transmitting means (13) or said data selecting means disposed on the (n-1) th row, while said data transmitting means disposed on the r th row (wherein r is an integer) sends out said image data (x) so that said image data (x) can be inputted to said data transmitting means (13) or said data selecting means disposed on the (r-1) th row, and wherein said data selecting means disposed on the n th row determines whether the image data (X n ) to be contracted is to be discarded or not in dependence on a control signal which corresponds to a mapping pattern indicating portions of data to be extracted for the contraction of the image (P), and wherein said integers k and ℓ are defined by x ≦ k ≦ n and k > ℓ, said integers m and q are defined by 1 ≦ m < n and q > m, said integer r is in the range 3 ≦ r ≦ n - 1 , and wherein said data selecting means disposed at the position (a m-1,q-1 ) of said matrix (A) determines in dependence on said control signal corresponding to said mapping pattern whether said image data (x) outputted from said data transmitting means or data selecting means disposed at the position (a m,q ) of said matrix (A) or said image data (x) outputted from said data transmitting means or said data selecting means disposed at the position (a m,q-1 ) of said matrix (A) is to be received as input data, and wherein said mapping pattern is arithmetically determined in dependence on the ratio of contraction only once and is stored in a register and then used for succeeding transformations without the necessity for renewed calculations. An apparatus for contracting an image according to claim 5 wherein said integers k and ℓ are defined by 3 ≦ k < n and k > ℓ + 1, said integers m and q are defined by 1 ≦ m < n and q ≧ m - 1 , said integer r is in the range 4 ≦ r ≦ n - 1 , characterised by said data selecting means disposed at the position (a m,q ) of said matrix (A) responds to the control signal corresponding to said mapping pattern to thereby determine whether the output data of the data transmitting means or said data selecting means disposed at the position (a m q ) of the matrix is to be received as input data, the data selecting means disposed at a position (a m-1,m-2 ) adding arithmetic means to the data selecting means disposed at the position (a m-1,q ), said arithmetic means performing logical arithmetic operation as the output data of the data transmitting means disposed of at a position (a m,m-1 ) of said matrix and the output data of the data selecting means disposed at the position (a m,m-2 ) of said matrix (A), said data selecting means responding to the control signal corresponding to said mapping pattern to thereby determine whether the output data of said data transmitting means disposed at the position (a m,m-2 ) of said matrix (A) or the output data of said arithmetic means added to said data selecting means is to be received as input data. An apparatus for contracting an image according to claims 5 or 6, wherein said data transmitting means are composed of wiring conductors. A method for contracting image data wherein a mapping pattern indicating portions of data to be extracted for the contraction of an image and comprising at least binary data (P₁, P₂, ... P n ) which is applied to image data (x₁, x₂, ... x n ) to be contracted (where n is an integer greater than or equal to 2) is provided, and wherein said image data (x₁, x₂, ... x n ) to be contracted are moved within a matrix (A) including n rows and n columns from the n th row towards the first row, and when said mapping pattern P i (where i is an integer in the range of 1 ≦ i ≦ n) has a first value, the image data (x ) i located at a position (a ii ) of said matrix (A) are disclosed while the image data (x) located at a position (a ii ) (where i + n ≦ j ≦ n ) of said matrix (A) are moved to a position (a i-1,j-1 ) within said matrix (A), and when said mapping pattern (P i ) has a second value, the image data (x) located at a position (a i,j-1 ) of said matrix are moved to the position (a i-1,j-1 ) of said matrix (A), and wherein said mapping pattern is arithmetically determined in dependence on the ratio of contraction only once and is stored and then used for succeeding transformations without the necessity for renewed calculations. A method for contracting image data according to claim 8 wherein a logical operation is performed on the image data (x i ) located at a position (a ii ) of said matrix (A) provided that said mapping pattern (P i ) (where i is an integer in the range of 1 ≦ i ≦ n) is of a first value, the result of said logical arithmetic operation being moved to a position (a i-1,i-1 ), while image data x is located at a position (a ij ) (where j is an integer in the range of (i + 1) ≦ j ≦ n ) of the matrix (A) and a position (a i,u ) (where u is an integer in the range of 1 ≦ u ≦ (i-2) ) of the matrix (A) are moved, respectively to positions (a i-1,j-1 ) and (a i-1,u ) of the matrix (A), and when said mapping pattern (P i ) is of a second value, the image data (x) located at a position (a i,v ) (where v is an integer in the range 1 ≦ v ≦ n) of the matrix (A) are moved to a position (a i-1,v ). A method for expanding an image, wherein a mapping pattern indicating a number of times the data is to be copied for the expansion of an image and comprising at least binary data (P m ) (where m is an integer ≧ 1) which is applied to image data (x₁, x₂, ..., x n ) to be expanded (where n is an integer ≧ 1) is provided, and wherein while said image data (x₁, x₂, ..., x n ) to be expanded are moved within a matrix (A) of ℓ rows and ℓ ' columns (where ℓ and ℓ ' are integers ≧ 2) in the direction from the first row toward the ℓ -th row, when the mapping pattern (P i ) is of a first value (where i is an integer in the range of 1 ≦ i < ℓ), the image data (x) located at a position (a i,j ) (where j is an integer in the range of i ≦ j < ℓ) are moved to a position (a i+1,j+1 ) of the matrix and the image data (x) located at a position (a i,k ) (where k is an integer smaller than i and equals 1 only when i = 1) are moved to a position (a i+1,k ), and when the mapping pattern (P i ) is of a second value, the image data (x) located at a position a i,p (where p is an integer in the range 1 ≦ p ≦ ℓ) of the matrix (A) are moved to a position (a i+1,p ) of the matrix (A), wherein said mapping pattern is arithmetically determined in dependence on the ratio of expansion only once and is stored and then used for succeeding transformations without the necessity for renewed calculations. An apparatus for expanding an image, comprising a matrix (A) of ℓ rows and ℓ ' columns (where ℓ and ℓ ' are integers ≧ 2), data transmitting means (13) disposed at positions (a q,r ) (where q and r are integers given by 2 ≦ q < ℓ and q > r) of said matrix, data selecting means (14) disposed at positions (a s,t ) (where s and t are integers given by 1 < s ≦ ℓ and s ≦ t ≦ ℓ') and at the positions of the first row, wherein when the image data (x₁, ..., x n ) to be expanded (where n is an integer ≧ 1) are moved from the first row toward the ℓ-th row, the data selecting means (14) disposed on the first row responds to a control signal corresponding to a mapping pattern indicating a number of times the data is to be copied for the expansion of an image (P₁) to input one of the image data (x u , x u+1 ) to be expanded (where 1 ≦ u < n and u = 1 only when u + 1 = 1), while the data selecting means (14) disposed at the position (a s,t ) of the matrix responds to the control signal corresponding to the mapping pattern (P s ) to input the image data (x) from the data selecting means which is disposed either at the position (a s-1,t-1 ) or at the position (a s-1,t ) , and the data transmitting means disposed at the position (a q,r ) of the matrix (A) inputs the image data (x) from either one of said data transmitting means and said data selecting means disposed at the position (a q-1,r ), wherein said mapping pattern is arithmetically determined in dependence on the ratio of expansion only one and is stored in a register and then used for succeeding transformations without the necessity for renewed calculations. An image expanding apparatus according to claim 11 wherein said data transmitting means are composed of wiring conductors.

Inventors: HIROKAMI, ETSUKO, KAWAKAMI, KATSURA, KOTERA, HIROAKI, OCHIAI, YUETSU, SHIMAZAKI, SHIGEO, SUZUKI, KAZUFUMI
Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1984
Main classification: G06F15
IPC codes: G06T3