SPEED AND PHASE CONTROL SYSTEM

Abstract: Disclosed is a speed and phase control system for a moving apparatus driven by an electric motor, or the like, and provided with a speed control system (22, 23) for controlling the moving apparatus to an initially set speed, a phase control system (25) for synchronizing the phase of the tu moving apparatus with a reference signal (29), and an error correction device (24) storing therein a target value of and for comparing an actual speed or a phase of the moving apparatus with the target value to detect an error therebe­ tween to thereby correct the initially set value in accordance with the error, whereby control is made such that the moving apparatus is operated at the target value of speed and phase thereof. Further, the error correction device is cut off from the speed control system when the speed reaches a value near the target value and at the same time the operation of the phase control system is started.

Description: The present invention relates to a control system for maintaining a moving apparatus such as a rotating apparatus or a traveling apparatus at a predetermined speed and for synchronizing the same with a predetermined reference phase. In a system for performing phase control in addition to speed control, for example, such as a system for controlling rotation of a video head drum, it is required to control the video head drum to perform accurate and regular rotary movement synchronized with a vertical synchronizing signal. The speed control in such a control system is performed in such a manner that an error of an actually measured value in comparison with a reference value is detected and an initial setting value is corrected in accordance with the quantity of the error so as to automatically perform speed error correction so that the speed is always settled at a reference or target value. In a control system for performing phase control in addition to such speed control as described above, it is not preferable to always perform speed error correction. This is because if phase control is initiated in the midst of speed error control, the speed of the object to be controlled is deviated by the output of a phase control circuit and the speed error control acts on such a deviated speed, this operation being repeated so that it takes a long time for phase synchronization. Further, if the system is pulled into phase synchronism in a state where the speed has not sufficiently reached the target value on the way of speed control, the rotation is held at the speed which is deviated from the target value and thereafter speed error correction is not be performed because the offset in speed can not be detected. As a result, the output value of error detection by a speed control system shows an erroneous value and a phase control system produces an output cancelling the erroneous error output to perform phase synchronization. Accordingly, even if the phase is synchronized, the synchronization is effected in a state where the phase is deviated from the correct phase position, that is in a state where a phase offset occurs. If such a phase offset occurs, the dynamic range of phase control becomes unbalanced in the direction of negative and positive amplitude of signal so that it is apt to come out of phase synchronization even if a slight disturbance occurs. Such condition is not an optimum controlled state. In order to overcome such a disadvantage, there is a method in which the phase synchronization control is stopped during the speed error correction. For example, U.S. Patent No. 4,301,395 discloses a method in which when the rotational speed of the motor exceeds a predetermined value the phase control is started. In this method, however, there is a disadvantage that the phase offset becomes large because the phase synchronization is performed under the condition of existence of the speed offset due to erroneous speed setting, while the period of time required from the beginning of pull into phase synchronism to the completion of synchronization may be shortened. Another prior art that is of interest is that disclosed in GB-A-2 006 481 which is concerned with a system for deriving a signal indicative of positional and/or speed errors of a motor. In this prior art, as a first step, the motor is first brought up to approximately its desired speed by means of an external drive source. A tachometer driven by the motor is used to measure its speed and speed error is held in a memory. In a second step when said approximate speed has been reached, the external drive source is removed and a control loop is then brought into operation that serves, as long as the tachometer pulse train has not yet reached its desired frequncy, to ensure that the motor receives a maximum speed correction control signal; whilst from the instant that the desired frequency is reached a phase detector provides fine control of the speed. The motor speed feedback control loop of this prior art will have a speed offset of 1/loop -gain. No counter measures are disclosed for correcting this speed offset. It is an object of the present invention to provide an improved control system for a moving apparatus in which a speed error correction is stopped and a phase control is started at an optimum timing so that control of the apparatus can be rapidly converged to a target value without any offset in speed as well as in phase. The present invention is as defined in the accompanying Claim 1, the claim being divided into a two-part form with those features thereof that are already known from GB-A-2 006 481 appearing in the pre-characterizing part. The present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a speed control circuit, for explaining the operation of the present invention; Fig. 2 is a block diagram showing an embodiment of the present invention; Figs. 3 to 6 are diagrams showing various waveforms for explaining the operation of the circuit of Fig. 2; Figs. 7 and 8 are block diagrams each showing an example of the error detector in Fig. 2; Fig. 9 is a circuit diagram showing an example of the waveform shaping circuit of Fig. 8; Fig. 10 is a diagram showing waveforms of signals at a main part of the waveform shaping circuit of Fig. 10; and Fig. 11 is a flowchart showing the function of the comparator for error detection. Referring to Fig. 1, an operation of a speed control system will be described hereunder in advance of description as to a preferred embodiment of the present invention. In Fig. 1, an electric motor which performs rotational movement is shown, by way of example, as a moving apparatus. In the drawing, there are provided a speed control circuit 1, a frequency generator 2, a pulse generator 3, a preset circuit 4, a speed detecting counter 5, a latch circuit 6, a digital-to-analog (D/A) converter 7, a driving amplifier 8, an electric motor 9, a speed error detecting circuit 11, a speed detecting counter 12, a latch circuit 13, a comparator 14, a low-pass filter (LPF) 15, an up/down counter 16, and a speed reference signal source 17. The operation of this circuit will be described hereinafter. As the motor 9 rotates, a frequency signal f having a frequency proportional to the rotational speed of the motor is produced from the frequency generator 2. The signal f is applied to the pulse generator 3. Upon reception of the signal f , the pulse generator 3 produces a latch pulse L and a preset pulse R, the former being applied to each of the speed counters 5 and 12, and the latter being applied to each of the latch circuits 6 and 13. In response to generation of the pulse L, the counting data in the detecting counters 5 and 12 are held in the latch circuits 6 and 13 respectively. Immediately after this operation, the detecting counter 5 is preset to an initial setting value determined by the preset circuit 4, and the detecting counter 12 is preset to a predetermined value, for example, zero. Immediately after generation of the reset pulse R, each of the detecting counters 5 and 12 begin to count a clock pulse (not shown). Through the above-mentioned operations, the detecting counter 12 and the latch circuit 13 are performing an operation of measuring a period of the signal f . The output of the latch circuit 13 is compared with a reference signal f₀ from the reference signal source 17, by the comparator 14 on the next stage, to thereby detect a speed error component ▵f of the signal f . Only a DC component ▵f₀ is detected by the digital LPF 15 on the still next stage. The up/down counter 16 on the next stage becomes its down-counting stage when the state where the sign of f₀ does not change for a predetermined period of time, for instance, in the case where +▵f₀ is maintained the content of the up/down counter 16 changes from its initial value zero to -1. Therefore, the initial set value, that is the preset value, N₀ stored in the preset circuit 14 is subtracted by 1 (one) so that it becomes N₀ - 1. Subsequently, if the state of +▵f₀ has continued for a predetermined period of time, the up/down counter becomes the state of downward counting, and the count in the up/down counter 16 become -2. When downward counting is performed in this way, the detecting counter 5 begins to measure the period of the signal f on the basis of the preset values N₀ - 1, N₀ - 2, etc., so that the value latched by the latch circuit 6 becomes smaller and the level of a signal produced from the D/A converter becomes lower. Therefore, the rotational speed of the motor 9 becomes slower, and the period of the signal f becomes longer. That is, the preset value is revised repeatedly till the error component becomes zero. As the result of repetition of the above-mentioned operations, the state has been reached in which no ▵f₀ is detected, and the frequency of the signal f is coincident with the reference signal f₀. That is, the speed of the motor has reached the target value. Next, referring to Fig. 2 an embodiment of the present invention will be described hereunder. In Fig. 2, there are provided a motor (an object to be controlled) 21, a frequency generator 22, a speed control circuit 23, an error correcting circuit 24, a phase control circuit 25, an adder 26, a motor driving amplifier 27, a phase detector 28, and a phase reference signal input terminal 29. The speed control circuit 23 is constituted by a pulse generator 30, a D/A converter 31, a latch circuit 32, a speed detecting counter 33, a preset circuit 34, and a reference preset value generator 35. The error correcting circuit 24 is constituted by a speed detecting counter 36, a latch circuit 37, a switching device 38, an error detector 39, and a digital adder 40. The phase control circuit 25 is constituted by a comparison counter 41, a latch circuit 42, a D/A converter 43, a switching device 44, and a phase lock detector 45. The operation of the embodiment will be described hereunder. Referring to Fig. 3, the operation of the speed control circuit 23 will be first described. On the basis of a signal obtained from the frequency generator 22 (hereinafter referred to as an FG signal), the pulse generator 33 successively produces a latch pulse L and a reset pulse signal R to be applied to the latch circuit 32 and the detecting counter 33, respectively, as shown as the waveforms (b) and (c) in Fig. 3. Thus, the counting data Np of the detecting counter 33 is taken into the latch circuit 32 in response to the latch pulse L, and immediately after that, the detecting counter 33 is reset by the reset pulse R. Then the detecting counter 33 begins to count an applied clock signal (not shown) as soon as the reset pulse R disappears. Fig. 3(d) shows the counted value Np in an analog waveform. That is, the ordinate represents the counted value of clock signals. In the error correcting circuit 24, the counting data from the detecting counter 36 is taken into the latch circuit 37 and applied to the error detector 39 through the switching device (hereinafter abbreviated as "SW") in quite the same way as in the speed control circuit 23. At this moment, the contact a of the SW 38 is closed. The error detector 39 holds therein count data corresponding to a reference target value of the frequency of the FG signal, that is a speed target value, and detects an error between the above-mentioned received data and the reference FG signal frequency, the output thereof being applied to the digital adder 40. The adder 40 adds the reference preset value in the reference preset value generator 35 to the above-mentioned error output and applies the sum to the preset circuit 34. The reference preset value corresponds to the reference FG signal frequency in the error detector 39. The preset value in the preset circuit 34 is increased/ decreased in accordance with the error value. That is, the preset value is decreased when the error value has a sign of minus (-), while increased when the sign is plus (+). Thereafter, the same operations as in Fig. 1 are effected. Thus, during a period of time where the contact a of the SW 38 is closed, the error correcting circuit 24 operates to continue the speed control till the motor speed reaches the target value. During this period, the SW 44 is in its opened state. Referring to Fig. 4, the status of speed rising of the motor 21 at that time will be explained. In Fig. 4, the abscissa and the ordinate represents time and the speed (frequency) of the motor 21 respectively. In a conventional system, there are at least three traces of motor speed rising in the state under the condition with no speed control, as shown by dotted curves A' to C' in the same drawing. If the speed control of the embodiment of the present invention is applied to the system having such traces as described above, the traces change as shown by solid curves A to C in the same drawing. In Fig. 4, f₀ represents the normal speed of the motor which is also the target value for the speed correction, and f c represents a minimum speed capable of being subject to the speed correction. When the speed correction is performed in the motor in the state of A' in Fig. 4, the state becomes as shown by A. That is, the motor speed rises in the same manner as the case where no correction is effected till the speed has reached the value f c ' and, when the speed f c is reached, the motor is subject to speed correction in the direction to be accelerated. Then, when the speed becomes over the value f₀, the speed correction acts in the direction to decelerate and the motor is rapidly settled to the normal speed. Similarly, in the motor in the state B' or C', the state changes into B or C of Fig. 4 respectively so that the speed reaches the normal speed f₀. When the motor 21 has been made reach the normal speed f₀ by the error correcting circuit 24, the contact b of the SW 38 is closed in response to the instruction from the error detector 39 to cut off the speed error detecting system (loop) and at the same time the SW 44 is closed to cause the phase control circuit 25 to start its operation. Thereafter, the rotation phase of the motor 21 is synchronized with the phase reference signal REF by the phase control. For example, in the case of rotation control for a head drum in a video tape recorder, the phase reference signal REF is a vertical synchronizing signal. Being known well, this method of phase synchronization control will be described briefly hereunder. Fig. 5 shows various waveforms for explaining the operation of phase synchronization. The phase reference signal REF is applied to the phase control circuit 25 through the reference signal input terminal 29. N I represents the output of the comparison counter 44 for counting a clock signal starting from the leading edge of the reference signal REF, and Tach represents an output signal of the phase detector 28. The comparison counter 41 counts a clock signal (not shown) at the timing of each edge of the phase reference signal REF. The pulse Tach is generated when the motor is in a predetermined phase position, the slanting portion of the count N I is sampled by using the Tach pulse signal as a sampling pulse, and the count is latched in the latch circuit 42. Therefore, the error in phase corresponds to the latched count value. The phase of the pulse Tach has been adjusted to come to the center of the slanting portion of the count N I when the phase error is zero. The thus obtained phase error signal is changed into an analog voltage signal by the digital-to-analog (D/A) converter 43, applied to the adder 26 through the switch 44, and added to the output of the speed control circuit 23 which has not been subject to speed error correction yet, and applied to the motor driving amplifier 27 so that the motor speed is slightly and transiently changed to control the phase toward the target value. The above-mentioned operation is repeated till the phase synchronization is completed. By separating the speed error correction by means of the SW 38, it is possible to prevent a possible maloperation of the speed error correction which might be caused by a slight change in motor speed caused by the output of the phase control system entered the speed control system as a disturbance thereto when the phase control circuit 25 operates. Upon completion of phase synchronization, the contact c of the SW 38 is closed and the error detector 39 begins to detect a phase error. This is performed in order to obviate a phase offset which will be generated when the phase synchronization is started in the state in which a speed offset exists. Upon detection of the fact that the phase lock is completed, that is the phase has been synchronized with a reference signal REF, the phase lock detector 45 causes the SW 38 to close the contact c , and the data of the latch circuit 42 is applied to the error detector 39 in response to the closure of the contact c . The phase lock detector 45 serves to detect whether a Tach pulse has entered the slanting portion of the count signal N I in Fig. 5 and may be constituted by means of, for example, a combination of known gate elements. The term "phase offset" means a stationary offset of phase form a phase reference point, that is, form the center of the slanting portion of the count signal N I and according to the present invention, also the phase offset is automatically corrected. Reference data corresponding to this phase reference point is stored in the error detector 39 and compared with the phase data applied from the latch circuit 42 to thereby detect a phase offset value. The thus detected phase offset value is applied as an error signal to the digital adder 40 so as to correct the motor speed to thereby control the motor speed in the direction to make the phase offset zero in the same manner as the speed error correction. Next, description will be made as to the method of changing-over the mode from the speed error correction to the phase control, that is, the method of determining the timing of closing the SW 44 at the same time when the closed state of the SW 38 is changed over from the contact a to the contact b . In a first method, there are provided threshold speeds f+ and f- at the opposite sides of the stationary target speed f₀ each separated therefrom with a slight speed difference, so that the phase control is performed only when the speed of the motor 21 falls within the range between f+ to f- as shown in Fig. 6. In this method, in the case where the phase control is continuously performed, the speed control system is in the state where the motor speed sufficiently approaches the value f₀ so that phase synchronization is effected in the state there is a very little speed offset as well as a little phase offset. According to this method, the operation can be changed over to the phase control after the speed correction has been surely completed by the speed error correction system. Fig. 7 shows an example of arrangement of the error detector 39 according to the first method. In the drawing, reference numeral 46 designates a comparator 46 for error detection. The error detection comparator 46 compares received data with a reference value stored therein and produces error data to the digital adder 40. Further, the error detection comparator 46 also detects the rising of the speed of the motor 21 and produces a rising detection signal to the digital adder 40 when it detects the motor speed reaches the value f c . Upon reception of the rising detection signal, the digital adder 40 begins to take in the error data which is an output of the error detection comparator 46. Thus, the error detection comparator 46 serves to operate also as a speed correction initiation signal generating means. Reference numerals 47 and 48 designate frequency discriminators, the former producing a high level signal when the speed of the motor 21 is smaller than the threshold speed value f+ of Fig. 6, and the latter producing a high level signal when the speed of the motor 21 is larger than the threshold speed value f-. Accordingly, the SW 44 is closed to perform the phase control only when the speed of the motor 21 falls within the range from f- to f+. At this time, the contact b of the SW 38 is closed. In a second method, aimed at is the fact that the speed of the motor 21 intersects the normal speed f₀ alternately downward and upward, as shown in Fig. 6, in the process it is converged to the target value. That is, in this method, the number of times of downwardly intersecting the stationary speed f₀ (from the f+ side to the f- side) by the speed of the motor 21 is counted and the phase control is performed after the count has reached a predetermined value. In this method, there are various advantages that no special threshold speed is required, and that the judgement as to whether the f+ side or f- side can be attained only by monitoring the correcting direction of the speed correction. Accordingly, the judging means for changing over the mode can be constituted only by a small number of counters. Fig. 8 shows the arrangement of the error detector 39 according to the second method. The error detector 39 is constituted by an error detection comparator 46, a shaper 50, and a timing control counter 51 for determining the timing for effecting phase control system. The operation of the circuit of Fig. 8 will be next described. The data measured by the detection counter 36 and the latch circuit 37 (output of the latch circuit 37) is applied to the error detection comparator 46 through the SW 38. The error detection comparator 46 compares the applied data with the reference value (stored in the error detection comparator 46), as described above to produce error data which is applied in turn to the digital adder 40. At the same time, the error detection comparator 46 applies a logic "1" signal and a logic "0" signal to the shaper 50 when the error data is plus (+) and minus (-) respectively. Fig. 9 shows an example of the shaper 50 and Fig. 10 shows waveforms at various portions h to j in Fig. 9. Assuming a signal h , which has a waveform h shown in Fig. 10, is being transferred to the shaper 50 of Fig. 9 in accordance with the polarity or sign of the error, the signal h is reversed by an invertor 50a and differentiated by a differential circuit constituted by a capacitor 50b and a resistor 50c. Thus, the output signal i of the differential circuit has a waveform i as shown in Fig. 10. The signal i is applied to one input terminal of a NAND circuit 50d with its other input terminal supplied with a "1" level signal. Accordingly, the output signal j of the NAND circuit 50d has a waveform j as shown in Fig. 10. That is, the shaper 50 produces a pulse only when the sign of the error data detected by the error detection comparator 46 changes from positive to negative. The output pulse of this shaper 50 is applied as a sign signal to the trigger input T of the timing control counter 51, and the counter 51 is caused to count up when, for example, the sign signal changes from plus (+) to minus (-) (when the signal changes from the f+ side to the f- side in Fig. 6). In the error detection comparator 46, the rising of speed is also detected as described above and a rising detection signal is produced when the fact that the speed reaches the value f c . This rising detection signal is applied to the reset terminal of the timing control counter 51 to initialize the counter 51. The rising detection signal controls the timing of generation of the output of the error detection comparator 46 and also serves as a speed correction starting signal. Here, the speed error correction is effected, and the level of the sign signal applied to the timing control counter 51 repeatedly alternates between "1" and "o". Thus, having counted a predetermined value N, the counter 51 issues instructions to cause the SW 44 to close and to cause the SW 38 to change the turn-on connection from the contact a to the contact b . The value of the count value N is determined, generally, on the basis of experiments. Soon after the SW 44 is closed to perform the phase control, the rotational phase of the motor 21 is phase synchronized with the reference signal REF. Then the contact c of the SW 38 is closed so that the phase comparison data is applied to the error detector 39 to detect a phase offset. It is possible to automatically correct the phase offset by digitally applying correction to the speed in accordance with the quantity of the detected phase offset. Referring to Fig. 11, description will be made as to the function of the error detection comparator 46 when the comparator 46 is executed by a microcomputer. STEP S1: Judgement is made as to whether the speed f of the motor 21 exceeds the rising detection signal f c or not, and if yes, the operation is advanced to the step S2. STEP S2, S3: The rising detection signal is produced. The difference between the speed f and the stationary speed f₀, that is error data f - f₀ is calculated and the error data is taken into the digital adder 40. STEP S4: Judgement is made as to whether the error data f - f₀ is positive or negative, and if yes, the operation is advanced to the step S5, while if no, the operation is advanced to the step S6. STEP S5: A logic "1" signal is produced. STEP S6: A logic "0" signal is produced. STEP S7: Judgement is made as to whether the connection of the SW 38 has been changed over to the contact b and the SW 44 has been turned on or not, and if yes, the operation is advanced to the step S8, while if no, the operation is returned back to the step S1. STEP S8: Judgement is made as to whether the connection of the SW 38 has been changed over to the contact c and if yes, the operation is advanced to the step S9. STEP S9: The error data ϑ o - ϑ between the reference phase value ϑ₀ and applied phase value ϑ. The error data is taken into the digital adder 40. STEP S10: Judgement is made as to whether the drive of the motor 21 is stopped or not, and if no, the operation is returned back to the step S1, while if yes, the operation is terminated. The above-mentioned function of the error detection comparator 46 in the case where the comparator 46 is executed by a microcomputer is only an example and it is possible to modify it in various ways. For example, the respective functions of the switching devices 38 and 44 may be executed by a software, and it is easy for a skilled person in the art to constitute such switching devices by using mechanical switches or semiconductor switching elements. It is a matter of course that the error detection comparator 46 can be constituted by a wired combination of known logic circuit elements. Further, in Fig. 8, lines for transmitting the detection signals representing the state of change-over of the SW 38 and the turning-on of the SW 44 into the error detection comparator 46 are omitted in order to simplify the drawing.

Claims: A system for controlling the speed and phase of a member driven by a motor in order to eliminate both speed error and phase error, the system comprising: speed control means comprising a first motor speed detecting means (33, 32) for detecting motor speed and producing a first motor control signal, phase control means (25) for detecting the phase position of said motor and comparing said detected phase position with a reference phase (REF) so as to produce a second motor control signal to cause said measured phase position to become equal to said reference phase (REF); means (26, 27) for producing a motor drive signal by adding said first and second motor control signals, characterized in that said speed control system includes a speed error correcting means (24) comprising a second speed detecting means (36, 37) and a comparator means (39) for comparing the output of said second speed detecting means (36, 37) with a reference value, corresponding to a desired speed of the member driven by the motor, and acting on said first speed detecting meams (33, 32) to alter the value of said first motor control signal in a direction to eliminate any speed error, the system further comprising change-over means (38, 44) responsive to detection of the speed error being eliminated, to connect the second motor control signal to said means (26, 27) for adding said first and second motor control signals, and to feed to said comparator means (39) in place of the output signal from said second speed detecting means (36, 37) a signal corresponding to the phase error between the detected phase of the motor and said reference phase (REF). A system according to Claim 1, in which said speed error correcting means (24) includes comparator means (47, 48) storing a pair of threshold values slightly separated from said speed target value in the positive and negative directions respectively, said comparator means being arranged to cause said change-over means (38, 44) to effect said change-over operation upon detecting the fact that said actual speed reaches a range between said pair of threshold values. A system according to Claim 1, in which said speed error correcting means (24) includes means (46, 50) for detecting a case where said error changes in either one of positive and negative directions, and counter means (51) for counting the number of occurrences of said case and for causing said change-over means (38, 44) to effect said change-over operation when the count reaches a predetermined value. A system according to Claim 1, in which said speed error correcting means (24) also stores therein a target value of phase and has means for detecting a phase error between said actual phase and said target value to thereby correct said initially set value in accordance with said error; and phase synchronization detecting means (45) for producing a detection signal upon detection of completion of the phase synchronization by said phase control means, said change-over means (38, 44) applying a value corresponding to a synchronized phase position to said error correcting means in response to said detection signal of said phase synchronization detecting means. A system according to Claim 4, in which said speed error correcting means (24) includes a comparator means (47, 48) storing a pair of threshold values slightly separated from said speed target value in the positive and negative directions respectively, said comparator means being arranged to cause said change-over means (38, 44) to effect said change-over operation upon detecting the fact that said actual speed reaches a range between said pair of threshold values. A system according to Claim 4, in which said speed error correcting means (24) includes means (46, 50) for detecting a case where said error changes in either one of positive and negative directions, and a counter means (51) for counting the number of occurences of said case and for causing said change-over means (38, 44) to effect said change-over operation when the count reaches a predetermined value.

Inventors: FUKUSHIMA, ISAO, KANO, KENJI, KOBORI, YASUNORI, NISHIJIMA, HIDEO, OKAMOTO, KANEYUKI, SAKAE, TETSUO, SEKIYA, MASATAKA
Applicants: HITACHI, LTD.
Application year: 1984
Main classification: G05D13
IPC codes: H02P23, H02P29, G05D13, G05B11