ERROR CORRECTION CIRCUIT

Abstract: An error correction circuit for detecting and correcting a plurality of errors in codewords made up of k data and n - k inspection symbols in the playback data from a recorded medium each symbol made up of m binary bits of informa­ tion using a Reed-Solomon code for error detection and correction so that the error location polynominal σ(x) = x e + σ₁x e-1 + ··· + σ e where e is the number of errors and the coefficients σ₁ to σ e of the error location polynominal σ(x) are related to the error syndromes S i generated by the error correction circuit by the equation S i+e + σ₁S i+e-1 + ··· + σ e-1 S i+1 + σ e S i = 0 where the syndromes S i+e to S i are field elements α i of the Galois field GF(2 m ). The error correction circuit includes: (a) means (12) for generating syndromes S₀, S₁, S₂ and S₃ from the codewords; (b) means (17) for effecting the following three calculations on the basis of the syndromes S₀, S₁, S₂ and S₃ generated by the syndrome generating means S₂S₀ + S₁² = r₃ S₃S₀ + S₁S₂ = r₂ S₃S₁ + S₂² = r₁ where r₃, r₂ and r₁ represent the values of the respective calculations; (c) means (23) for judging whether the condi­ tion r₃ ≠ 0 or r₃ = 0; (d) a first processing means (17, 25 - 32) for finding error locations by determining the roots of the following equation as the error location polynominal, when the conditions r3 ≠ 0 is confirmed in the judging means r₃x² + r₂x + r₁ = 0 where x represents the error locations; and (e) a second processing means (17, 25-32) for finding error location by determining root of the following equation as the error location polynominal, when the condition r3 = 0 is confirmed in the judging means under the condition of r₂ = 0 S₁ + S₀x = 0

Description: The present invention relates to an improvement in an error correction circuit suitable for use in a digital audio disc (referred to hereafter as DAD) playback apparatus of an optical compact disc (referred hereafter as CD). In recent years, its has becoming popular in the field of acoustic technology to adopt digital recording systems making use of a PCM (Pulse Coded Modulation) technique, in order to realize playback with as high a fidelity as possible. This kind of technique, usually referred to as "digital audio system", is known as a technique which exhibits audio characteristics much superior to that of conventional analog type playback systems,without having any dependency on the characteristics of the recording medium. The technique of the type described, making use of a disc as the recording medium, is generally called a "DAD" system, and various types of recording/playback methods have been proposed such as an optical type method, electrostatic type method, and mechanical type method. This new recording/playback technique, on the other hand, requires a playback apparatus which can satisfy various functions and a high standard of performance which could never be achieved by the prior art, regardless of the type of the recording and playback techniques. For instance, in case of the CD system, the disc used as the medium is made of a transparent resin and has a diameter of about 12 cm and a thickness of about 1.2 mm, the disc being coated with a metallic thin film in which are formed pits corresponding to the digital PCM signal. The disc is driven by a system called CLV (Constant Linear Velocity) system at a varying rotation speed of about 500 to 200 r.p.m. An optical pick-up housing a semiconductor laser and a photoelectric conversion element is driven by a linear tracking system so that the laser beam scans radially the disc from the inner side to the outer side of the disc. The disc usually has a track pitch of 1.6 µm and has a program area (radial range of 25 to 58 mm) which is large enough to store the information for a one-hour stereophonic playback on each side of the disc. In addition, index data and other associated data are stored in the lead-in area (radial range 23 to 25 mm). In the DAD system of the type described, it is required to faciliate an easy generation of a pit synchronizing signal during playback and to realize a stable data slice by using narrow band frequency characteristics of the RF signal read by the optical pick-up, the recording of digitized data is conducted after such a modulation that the interval of inversion of polarity always falls between the maximum and minimum polarity inversion interval. In case of DAD playback apparatus of optical CD system, an EFM (Eight to Fourteen Modulation) is ordinarily used as the modulation system. Briefly, this modulation system is to divide the digitized data at a unit of 8-bit and to record the same after modulation to a 14-bit data. In the playback, therefore, the 14-bit data is demodulated into original 8-bit digitized data. The 8-bit digitized data, produced by the demodulation of the 14-bit data reproduced from the disc, is lend to an error correction circuit in which the error correcting operation is conducted. In the optical CD type DAD playback apparatus, cross interleaved Reed-Solomon codes (referred hereafter as CIRC codes) are used as the error correcting code. CIRC codes are obtained by submitting Reed-Solomon codes, which are a kind of Bose-Chaudhuri-Hocquenghem (BCH) codes and are generally regarded as the most effective random error correction codes hitherto known to a signal processing called "cross interleaving." CIRC codes thus obtained are sensitive enough to correct burst errors. Reed-Solomon codes can be decoded in the same way as other BCH codes, thereby correcting errors. A discussion will be made hereinafter as to the method of decoding of typical Reed-Solomon codes consisting of k piece of information data symbols and (n-k) piece of inspection symbols, i.e., consisting of n piece of symbols. It is noted here that these symbols are the elements of a Galois field GF(2 m ) which is a definite field having m piece of binary bits, i.e., 2 m elements. In this case, the generator polynominal H(x) having Reed Solomon code for correcting an error a t number of times is given either by the following Equation (1) for BCH codes or (2) for Reed-Solomon codes, where α is a primitive element of Galois field GF(2 m ): If we let U(x), V(x) and E(x) denote the recording signal polynominal, the playback signal polynominal and the error polynominal, respectively. Then, these polynominals satisfy the following relationship. The coefficients of polynominals are contained in the Galois field GF(2 m ). If we let x j denote an error location, and let Y j denote the value of the error at the error location X j, the error polynominal E(x) can then be given as: where Σ is the sum of the errors at all of the error locations. Here, syndrome S i is defined here by: where, i = 0, 1, ... , 2t-1 . Then, from equation (3) we have: S i = U(α i ) + E(α i ) Both U(x) and H(x) can be divided without leaving a remainder. As a result, the following therefore holds true: S i = E(α i ) From Equation (4) it is evident that syndrome S i may be expressed as follows: Let X j = α j , X j represents the error location at α j . Then The error location polynominal σ (x) is defined as follows. where e is the number of errors. The coefficients σ₁ to σ e of σ(x) are related to the error syncrome S i as shown below: Briefly, the above-explained process of decoding of the Reed-Solomon code is as follows. (I) To calculate syndrome S i in accordance with Equation (5). (II) To obtain coefficients σ₁ to σ e contained in the error location polynominal σ(x) in accordance with Equation (8). (III) To determine the root X j of the error location polynominal σ(x) in accordance with Equation (7). (IV) To determine the error polynominal E(x) in accordance with Equation (4), after determining the value Y j in accordance with Equation (6). (V) To effect an error correction in accordance with Equation (3). By using the steps listed above, the steps needed to decode a Reed-Solomon code consisting of many block data each containing four inspection symbols will be described as a practical example of the error correction. This code is represented by the following generator polynominal H(x): H(x) = (x + 1)(x + α) (x + α²) (x + α³) . In this case, this polynominal H(x) permits the correction of error up to double error, as explained hereinafter. The Reed-Solomon code may be decoded by the following process. (I) To calculate syndromes S₀ to S₃: (II) Equation (8) is rewritten for each of the cases of e = 1 and e = 2 as follows. It is assumed here that the actual decoder commences its operation from the state of e = 1. In this case, it is necessary to determine the solution σ₁ which satisfies the simultaneous Equation (9). If no solution σ₁ is found, the decoder must find solutions σ₁ and σ₂ which satisfy the simultaneous Equation (10). If such solutions cannot be found, it is deemed that the condition of e = 3 is met. The solution σ₁ of simultaneous Equation (9) can be expressed by: σ₁ = S₁/S₀ = S₂/S₁ = S₃/S₂ The solution σ₁ and σ₂ of simultaneous Equation (10) is: σ₁ = (S₀S₃ + S₁S₂)/(S₁² + S₀S₂) , and σ₂ = (S₁S₃ + S₂²)/(S₁² + S₀S₂) (III) If the coefficient σ₁ in the error location polynominal is obtained, find the root of the error location polynominal in accordance with Equation (7). Substituting the elements of the Galois field GF(2 m ) in Equation (11) one after another will yield roots Z₁ and Z₂. (IV) If the roots of the error location polynominal are found, determine the error value Y j in accordance with Equation (6). In the case of e = 1 : S₀ = Y₁ Therefore, Y₁ = S₀ . In the case of e = 2 : S₀ = Y₁ + Y₂ S1 = Y₁Z₁ + Y₂Z₂ Therefore, Y₁ = (Z₂S₀ + S₁)/(Z₁ + Z₂) and Y₂ = S₀ + Y₁ (V) The correction of the error is conducted in accordance with the correction values Y₁ and Y₂ thus obtained. Fig. 1 is a block diagram of a conventional error correction circuit constituted by an actual decoding system of CIRC codes based on the theory heretofore described. Pick-up 11 is adapted to reproduce an RF signal from the disc. The RF signal is converted by a data slice circuit (not shown) into a digitized data and is used for the extraction of the synchronizing signal for the self-locking purpose, and is given to a demodulating circuit 12. As explained before, demodulating circuit 12 carries out the EFM demodulation for converting the 14-bit data recorded in the disc into 8-bit data and delivers the demodulated symbols to the error correcting means 13. Error correcting means 13 is of a cross interleave double correction system constituted by a double correction circuit 14, de-interleave circuit 15 and a double correction circuit 16. Namely, when the result of the error judgement in the double correction circuit 14 has proved that the error is correctable, the error correction is conducted in the manner explained before and the corrected value is delivered to a D/A converter (not shown) through de-interleave circuit 15 and double correction circuit 16. On the other hand, when the error correcting capacity is exceeded, the error correction is not performed but the error flag E f representing the error location is added to the demodulated symbols and is outputted to de-interleave circuit 15 for a de-interleave processing together with the error flag E f . Then the error correction is effected by double correction circuit 16. In the conventional error correction circuit, the coefficients σ i of the error location polynominal σ (x) are determined by the simultaneous Equations (9) and (10) and the number of errors is judged to determine whether the error is singular, double or triple. Then the error location polynominal σ(x) is selected in accordance with the error number and the root (error location) is determined. The error correction is conducted after determination of the error pattern. As stated before, the coefficients σ i are given as follows when the conditions of the simultaneous Equations (9) and (10) are met, respectively. In case of Equation (9) : σ₁ = S₁/S₀ = S₂/S₁ = S₃/S₂ In case of Equation (10) : σ₁ = (S₀S₃ + S₁S₂)/(S₁² + S₀S₂) σ = (S₁S₃ + S₂²)/(S₁² + S₀S₂) In either case, it is necessary to effect a dividing operation. As well known, dividing circuits are rather complicated although multiplying circuits can have a comparatively simple construction. An error correction circuit performing calculations on the basis of the equations mentioned in claim 1 is disclosed in the document EP-A-61 345. In order to obtain products and quotients of the elements of the Galois field, this prior art uses conversion ROMs which become fairly large for storing all the necessary data. This gives a rise to the demand for a simple circuit which can perform the judgement as to whether the error is a singular error, double error or a tripple error. SUMMARY OF THE INVENTION It is on object of the present invention to provide an error correction circuit which can perform an error judgement at a high acuracy with a simple circuit arrangement. Another object of the present invention is to provide an error correction circuit which can perform algebraic operations such as multiplication and addition on the elements of the Galois field thereby finding error locations and error patterns in a short time. These objects are achieved in the error correction circuit of the present invention, as claimed in the single claim. Additional objects, advantages, and features of the present invention will further become apparent to persons skilled in the art from a study of the following description and of the accompanying drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a prior art error correction circuit relating to the field of the invention. Fig. 2 is a block diagram of an embodiment of an error correction circuit according to the present invention. Fig. 3 is a flow chart for explaining the operation of the embodiment shown in Fig. 2. Figs. 4 and 5 are timing charts for explaining the operation of the embodiment shown in Fig. 2. DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention will now be described in detail with reference to the accompanying drawings; Fig. 2 to Fig. 5. Throughout the drawings like reference numerals and letters are used to designate like or equivalent elements for the sake of simplicity of explanation. Before describing an enbodiment of the present invention, an explanation will be made hereinafter as to the principle of the error judging means as used in the error corection circuit of the present invention. By way of example, it is assumed here that the Galois field is GF(2⁸). It is also assumed that the generating polynominal H(x) is given by: H(x) = (x + 1)(x + α)(x + α²)(x + α³) where α represents the root of the polynominal. It is further assumed that the number n of the symbols of the correction blocks is 32, and that the polynominal U(x) of the recording operation as expressed by the following equation is divisible by H(x). H(x) = U₃₁x³¹ + U₃₀x³⁰ + ... + U₁x¹ + U₀x = U₃₁x³¹ + U₃₀x³⁰ + ... + U₁ + U₀ In this case, the following condition is met as described before. U(1) = U(α) = U(α²) = U(α³) = 0 The above-mentibned equation, however, is not satisfied when the error is generated in the reproducing operation. Namely, in the case where the error is singular, the syndromes S₀ to S₃ are represented as follows, when the error locations and the error patterns are expressed by α i and e i , respectively. S₀ = e i S₁ = e i α i S₂ = e i α 2i S₃ = e i α 3i Therefore, the following simultaneous Equation (12) is established. This simultaneous Equation (12) corresponds to simultaneous Equation (9) mentioned before. Therefore, α⁰ to α³¹ are successively substituted for x in the following equation: and the error location is identified as the value x which provides the value 0 of the above-shown formula. In the case where the error is a double error, the syndromes S₀ to S₃ are given as follows, when the error locations are expressed as αa and α b while the error patterns are represented by e a and e b , respectively. S₀ = e a + e b S₁ = e a α a + e b α b S₂ = e a α 2a + e b α 2b S₃ = e a α 3a + e b α 3b Consequently, the condition of the following simultaneous Equation (14) is met. The simultaneous Equation (14) corresponds to simultaneous Equation (10). Representing (α a + α b ) and α a α b by A and B, respectively, the values α a and α b are determined as the roots of the following quadratic equation. Further, the following conditions arc derived from simultaneous Equation (14). A = (S₁S₂ + S₀S₃)/(S₁² + S₂S₀) B = (S₂² + S₃S₁)/(S₁² + S₂S₀) Using r1, r2 and r3 meeting the requirements of the following simultaneous Equation (16): Equation (15) can be rewritten as follows. x² + (r₂/r₃)x + r₁/r₃ = 0 (where r₃ = 0) Since α a and α b are roots of the above quadratic equation, they are also the roots of the following equation. Then, α⁰ to α³¹ are successively substituted for x in Equation (17), and the error location is identified as the value of x which makes the value of Equation (17) zero. Thus, in case of the singular error, α⁰ to α³¹ are successively substituted for the x in Equation (13) and the singular error is judged from the fact that Equation (13) has a root which can make Equation (13) meet. On the other hand, in the case of the double error, α⁰ to α³¹ are successively substituted for the x in Equation (17) and the double error is judged by the fact that Equation (17) has two roots which can make Equation (17) meet. In the case of the singular error, a following equation is derived from simultaneous Equation (12). S₁² + S₂S₀ = S₂² + S₁S₃ = S₁S₂ S₀S₃ = 0 Comparing the above equation with simultaneous Equation (16), it is understood that the following condition is met. r₃ = r₂ = r₁ = 0 Since when the condition: r₃ ≠ 0 is met in the case of a duble error, it is judged that the error is double, triple or of higher degree. On the other hand, when the condition: r₃ = 0 is met, it is judged that the error is singular or triple or of higher degree. Referring now to Figs. 2 to 5, an embodiment of the present invention will be described in detail based upon the principle explained hereinbefore. Fig. 2 shows a block diagram of a circuit for solving Equations (13) and (17). The operation of the circuit will be explained with reference to a flow chart shown in Fig. 3 and timing charts shown in Figs. 4 and 5. In Fig. 2, calculation processing circuit 17 is adpated to calculate data or signals supplied from BUS line 19 in accordance with a program stored in read only memory (referred to as ROM, hereinafter) 18, when operations are commenced at each step in the flow chart shown in Fig. 3. Calculation processing circuit 17 first calculates the syndromes S₀ to S₃ in a step ST₂. Calculation processing circuit 17 then delivers to BUS line 19 the syndrome S₁ out of the syndromes S₀ to S₃ thus determined. Meanwhile, gate circuit 20 controlled by ROM 18 delivers a latch signal to latch circuit 21, so that the first syndrome S₁ is latched in latch 21. Subsequently, calculation processing circuit 17 delivers to BUS line 19 the syndromes S₀ to S₃ thus produced. In consequence, gate circuit 20 delivers a latch signal to latch circuit 22 so that the syndrome S₀ is latched by latch circuit 22. Calculation processing circuit 17 makes a judgement in step ST₃ as to whether all the syndromes S₀ to S₃ are zero. In case that the answer in YES, i.e., when all of the syndromes are zero, the symbols are judged as involving no error, i.e., that the symbols are correct, so that the answer is outputted directly without being subjected to the error judgement and error correction which are to be executed through step ST₄. When the answer is NO, i.e., when not all of the syndromes S₀ to S₃ are zero, calculation processing circuit 17 makes a judgement in step ST₅ as to whether one of the syndromes S₀ to S₃ is not zero or all of the syndromes are not zero. If the answer of this judgement is NO, a judgement is made in step ST₆ to decide that the present error is of triple or of higher degree. On the other hand, if the answer to the judgement in step ST₅ is YES, calculation processing circuit 17 calculates the values r₃, r₂ and r₁ on the basis of the syndromes S₀ to S₃ in step ST₇. Thereafter, a judgement is made in step ST₅ as to whether the value r₃ is zero or not. The judgement in step ST₅ is conducted in the following manner. First, calculation processing circuit 17 delivers r₃ out of the values r₃, r₂ and r₁ thus determined to BUS line 19: Then zero judgement circuit 23, which is under the control of ROM 18, makes a judgement whether the value r₃ outputted to BUS line 19 is zero. Meanwhile, the value r₃ delivered to BUS line 19 is latched by latch circuit 24 controlled by ROM 18. Thereafter calculation processing circuit 17 operates to deliver the values r₂ and r₁ successively to BUS line 19. An explanation will be made first with the case where the condition: r₃ ≠ 0 is met, i.e., with the case where the answer obtained in step ST is NO. In this case, it is judged that the error is double or triple, so that a calculation for determining the root of Equation (17) is conducted in step ST₉. This calculation in step ST₉ is conducted in a manner explained hereinafter. When the condition: r₃ ≠ 0 is confirmed, zero judging circuit 23 operates to drive gate circuit 20 whereby latch signals are delivered to latch circuits 22 and 21 at such timing that the signals r₁ and r₂ are derived from calculation processing circuit 17. Therefore, latch circuits 22 and 21 latch the values r₂ and r₁ instead of the syndromes S₀ and S₁. After the latching of the signals r₃, r₂ and r₁ in respective latch circuits 24,21, 22, set signals r-SP are given to register circuits 25, 26, 27 which are provided to correspond to respective latch circuits 21, 22, 24, so that the signals r₁, r₂, r₃ latched in latch circuits 21, 22, 24 are shifted to register circuits 25, 26, 27. Register circuit 26 is connected to multiplier circuit 28 which is adapted to operate in response to multiplication clock signal r-CK so as to multiply the content, i.e., the value r₂ of register circuit 26 by the error location α i (in this case, α being α⁰ to α³¹) and to set the product in register circuit 26 again. On the other hand, register circuit 27 is connected to multiplier circuit 29 which operates in response to the multiplication clock signal r-CK to multiply the content, i.e., the value r₃ of register circuit 27 by α² and to set the product again in register circuit 27. The outputs from register circuits 25 and 26, obtained for the successive values α⁰ to α³¹ are added by adder 30, and the results of the addition are further added to the output from register circuit 27 by adder 31. Consequently, adder 31 produces an output which is the result of a series of calculations as shown below. The values α which make the result of the calculation zero, i.e., 0 are the root of Equation (17), i.e., the error locations α i and α j . Consequently, a calculation for determining the root of Equation (17) is conducted. After this calculation, a judgement is made in step ST₁₀ as to whether two roots habe been determined. This judgement is conducted by leading the output of adder 31 to zero judging circuit 32 and judging whether the answer: 0 is obtained for two times. In case that two roots are obtained, i.e., when the answer is YES, it is judged in step ST₁₁ that the error is a double error, wheres, when two roots could not be obtained, i.e., when the answer is NO, it is judged in step ST₆ to be triple or higher degree. In the case where the condition of r₃ = 0, i.e., when the answer is YES, the operation is as follows. In this case, since the error is judged to be singular or triple or of higher degree, a judgement is made in zero judging circuit 23 as to whether r₂ is zero in step ST₁₂. In the case where r₂ ≠ 0, a judgement is made in step ST₆ that the error is triple or of higher degree. To the contrary, in the case of r₂ = 0, a calculation is conducted in step ST₁₃ to determine the root of Equation (13). This calculation is conducted in a manner explained hereinafter. When the condition of r₃ = 0 is confirmed as a result of the judgement in zero judging circuit 23, zero judging circuit 23 operates to prohibit the operation of gate circuit 20. Therefore, the values r₁ and r₂ outputted from calculation processing circuit 17 are not latched in latch circuits 21, 22 so that latch circuits 21,22 hold the syndromes S₁ and S₀. Then, as stated before, the contents, i.e., the values S₁ and S₀ of latch circuits 21, 22 are shifted to register circuits 25, 26, and the content S₀ of register circuit 26 is multiplied by the error location α. The content r₃ of latch circuit 24 is shifted to register 27 and is multiplied by α². Since the condition: r₃ = 0 is met in this case, the output from register 27 is zero. Thus, adder 31 produces an output which is obtained by a series of calculations shown below. The value of α which makes the calculation result zero: 0 is the root of Equation (13), i.e., the error location α i. Thus, the calculation for determining the root of Equation (13) is accomplished, a judgement is made in step ST₁₄ as to whether one root for Equation (13) has been obtained. This is made through judging whether zero judging circuit 32 once produced an output: 0. In the case where one root has been obtained, i.e., in the case where the answer is YES, it is judged in step ST₁₅ that the error is a singular error. To the contrary, when the root could not be determined, i.e., when the answer is NO it is judged to be triple or of higher degree. Figs 4 and 5 are timing charts showing the operation in the cases of r₃ = 0 and r₃ ≠ 0, respectively. Referring first to the case: r₃ = 0, when the syndromes S₀ to S₃ are outputted from calculation processing circuit 17 at the timing shown in Fig. 4a, latch circuit 22 latches s₀ at the timing shown in Fig. 4b, while latch circuit 21 latches at the timing shown in Fig. 4c. Subsequently, when the signals r₃ to r₁ are outputted from calculation processing circuit 17 at the timing shown in Fig. 4a, zero judging circuit 23 outputs a judging pulse P₁ for the condition: r₃ = 0 at a timing shown in Fig. 4d so as to inactivate gate circuit 20 thereby to prevent latching of the signals r₂ and r₁ by latch circuits 22, 21. Meanwhile, ROM 18 delivers a latch signal to latch circuit 24 at the timing shown in Fig. 4e, so that latch circuit 24 latches the condition: r₃ = 0 at a timing as shown in Fig. 4f. Thereafter, if the condition: r₂ = 0 is met, zero judging circuit 23 delivers a judging pulse P₂ for the condition: r₂ = 0 at a timing shown in Fig. 4d. After the calculation of the judgement of the condition: r₂ = 0 following the latching operation of all latch circuits 21, 22, 24, a set signal r-SP is outputted at a timing as shown in Fig. 4g, so as to permit the calculation for determining the root of Equation (13). In the event that the condition: r₃ = 0, when the syndromes S₀ to S₃ are outputted at a timing shown in Fig. 5a, latch circuit 22 latches S₀ at the timing as shown in Fig. 5b, while latch circuit 21 latches S₁ at the timing shown in Fig. 5c. Then, as calculation processing circuit 17 outputs the signals r₃ to r₁ at the timings shown in Fig. 5d, the judging pulse P₁ for the condition: r₃ ≠ 0 is not delivered by zero judging circuit 23 becuase the condition is so that gate circuit 20 is allowed to operate, thereby allowing latch circuits 22, 21 to latch subsequent signals r₂ and r₁. In this case, ROM 18 produces latch signals at the timing shown in Fig. 5e, while latch circuit 24 latches r₃ at the timing as shown in Fig. 5f. Thereafter, when calculation processing circuit 17 delivers r₂ and r₁, latch circuits 22, 21 latch the signals r₂ and r₁ in place of the syndromes S₀ and S₁. After the completion of the latching operation of all latch circuits 21, 22, 24, a set signal r-SP is outputted at a timing shown in Fig. 5g, followed by a calculation for determining the root of Equation (17). To sum up, the operation of the described embodiment is as follows. As the first step, a calculation is conducted in accordance with the following equations: r₃ = S₁ + S₂S₀ r₂ = S₁S₂ + S₀S₃ r₁ = S₂² + S₃S₁ When the condition: r₃ ≠ 0 is met, a calculation is made to determine the roots of the following equation. r₃x² + r₂x + r₁ = 0 When two roots are obtained, it is judged that the error is a double error and these two roots are regarded as being error locations α i and α j . When two roots could not be obtained, it is judged that the error is a triple or of higher degree. When the condition: r₃ = 0 is met, a calculation is conducted to determine the root of the following equation under the condition: r₂ = 0. S₁ + xS₀ = 0 If one root could be obtained at the above equation, it is judged that the present error is a singular and the root is regarded as being the error location α i . In case of the condition: r₂ ≠ 0 or when the root could not be obtained, it is judged that the error is triple or of higher degree. It is, therefore, possible to discriminate the singular error and double error only through the multiplication operation and the addition operation, so that it is not necessary to effect the dividing operation which is indispensable in the conventional system. Consequently, the circuit arrangement is simplified and the error judgement is conducted without failure. In the case of a double error, the error locations α i and α j are determined by using Equation (17) as the polynominal. The necessity of dividing operation is eliminated also in this case, so that the simplification of the circuit arrangement is achieved also in this respect. To the contrary, the conventional apparatus requires dividing circuits for determining the coefficients σ₁ and σ₂, because the aforementioned Equation (11) as the error location polynominal had been operated under a following equation. σ(x) = x² + σ₁x + σ₂ = x² + [(S₀S₃ + S₁S₂)/(S₁² + S₀S₂)]x + (S₁S₃ + S₂²)/(S₁² + S₀S₂) That is, calculations for determining the coefficients σ₁ and σ₂ had to be made through the dividing operations. According to the present invention, if r₃ ≠ 0 Equation (13) is conducted with the syndromes S₁ and S₀ latched by latch circuits 21, 22. On the other hand, if the condition: r₃ = 0 is met, r₁ and r₂ are latched in place of the syndromes S₁ and S₀ to perform the calculation of Equation (17). Thus, the parts such as latch circuits 21, 22, register circuits 25, 26, multiplier circuit 28 and adder 30 are commonly used for the error location calculation for the double error. This also contributes to the simplification of the circuit arrangement and the shortening of the processing time. Futhermore, if the condition r₃ = 0 is met, the syndromes S₁ and S₀ latched by latch circuit 21, 22 remain latched by these circuits and the calculation of Equation (13) is executed. However, when the condition: r₃ ≠ 0 is met, the calculation of equation (17) is executed with the values r₁ and r₂ latched in place of the syndromes S₁ and S₀. Consequently, the parts such as latch circuits 21, 22, register circuits 25, 26, multiplier circuit 28 and adder 30 can be used commonly both for the calculation of the error location for a singular error and the calculation of the error location for a double error. This constitutes one of the advantageous features of the present invention. After determination of the root of Equation (13) in step ST₁₄, a judgement is made in step St₁₄ as to whether one root has been determined. When one root has been obtained, it is judged that the error is a singular error, wheres, when one root could not be obtained, it is judged that the error is triple or of higher degeree. It is, therefore, possible to prevent any erroneous judgement of the singular error with a high accuracy. Namely, when an error which is quadruple is erroneously judged as a singular error, the one root may not be obtained because of the conditions: r₃ = 0 and r₂ = 0 being met. In the case where the number n of symbols of the correcting block is 32, while the Galois field isGF(2⁸), the probability of the erroneous judgement of the quadruple error or error of higher degree for singular error can be nullified advantageously. As will be fully realized from the foregoing description, it is possible to provide an error correction circuit which can perform an error correction without failure with quite a simple circuit arrangement.

Claims: An error correction circuit for detecting and correcting a plurality of errors in codewords made up of k data and n - k inspection symbols in the playback data from a recording medium each symbol made up of m binary bits of information using a Reed-Solomon code for error detection and correction so that the error location polynominal is σ(x) = x e + σ₁x e-1 + ... + σ e where e is the number of errors and the coefficients σ₁ to σ e of the error location polynominal σ(x) are related to the error syndromes S i generated by the error correction circuit by the equation S i+e + σ₁S i+e-1 + ... + σ e-1 S i+1 + σ e S i = 0 where the syndromes S i+e to S i are field elements α i of the Galois field GF(2 m ), the error correction circuit comprising: means (12) for generating syndromes S₀, S₁, S₂ and S₃ from the codewords; first and second means (21,22) for holding the syndromes S₁ and S₀; means (17) for effecting the following three calculations on the basis of the syndromes S₀, S₁, S₂ and S₃ generated by said syndrome generating means S₂S₀ + S₁² = r₃ S₃S₀ + S₁S₂ = r₂ S₃S₁ + S₂² = r₁ where r₃, r₂ and r₁ represent the values of the respective calculations; third means (24) for holding the value r₃; means for judging (23) whether the condition r₃ ≠ 0 or r₃ = 0; a control means for making, when the condition r₃ ≠ 0 is confirmed by said judging means, said first and second holding means hold the values r₁ and r₂ in place of the syndromes S₁ and S₀; and means (17) for processing signals to find error locations by determining the root of the following equation as the error location polynominal r₃x² + r₂x + r₁ = 0 or S₁ + S₀x = 0 wherein said calculation effecting means is adapted to calculate first sums by adding to the content of said first holding means (21) successively obtained by multiplying the content of said second holding means (22) successively by the elements α of said Galois field GF (2 m ) and to provide second sums by adding to each first sum a value obtained by multiplying the content of said third holding means (24) by α², whereby that element α which results in a value of zero of a said second sum is used as the error location.

Inventors: INAGAWA, JUN C/O PATENT DIV., TOSHIBA CORP., KOJIMA, TADASHI C/O PATENT DIV., TOSHIBA CORP., NAGUMO, MASAHIDE C/O PATENT DIV., TOSHIBA CORP.
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1984
Main classification: G11B20
IPC codes: H03M13