HALO GENERATION FOR CRT DISPLAY SYMBOLS

Abstract: Apparatus for generating halos about CRT display symbols, to distinguish them from background video, reads, from an image memory (43), video Bit signals corresponding to a CRT picture element P I.J , and the immediately surround­ ing CRT picture elements. A digital signal is generated therefrom representing a first Boolean function (44). The intensity of the background illumination at P I.J is unaltered, in response to a digital signal of zero, and is diminished by one-half, in response to a digital signal of ONE. A preferred embodiment reads additional signals and employs a second Boolean function.

Description: The present invention relates generally to CRT displays, and more particularly to the generation of halos around symbols therein, to distinguish the symbols from video background. Symbols are written on a CRT display which overlay background video. Referring to Figure 1 of the accompanying drawings, which is a negative of an actual display, a symbol 20 is rendered less discernable by background video 21 which surrounds and borders the symbol 20. The obfuscating effect of the background video 21 upon the symbol 20 is particularly pronounced on the right-hand side of the CRT display where the symbol 20 appears to merge with the background video 21. Thus, there is a need for apparatus which precludes symbols on CRT displays from being confused with the background video. The present invention is defined in the appended claims, and a preferred embodiment of the present invention is utilised in conjunction with Applicants' copending EP-A-0146229. The preferred embodiment is analogous to the apparatus described above, with the following distinctions. Each memory address is identified by an X and Y binary coordinate, and video bit signals are stored only in addresses whose X coordinate has a predetermined first binary digit, and whose Y coordinate has a predetermined first binary digit. The video bit signals B X,Y read from the memory correspond to the picture elements P I,J P I-1, J ; P I-1,J+1 ; P I,J+1 and those immediately surrounding them, namely P I-2,J-1 ; P I-1,J-1 ; P I,J-1 ; P I+1,J-1 ; P I-2,J ; P I+1,J ; P I-2,J+1 ; P I+1,J+1 ; P I-2,J+2 ; P I-1,J+2 ; P I,J+2 ; and P I+1,J+2 . The digital signal generated is:- In preferred embodiments of the present invention, the address reader comprises shift registers coupled to delays comprising shift registers or D-type flip-flops. The predetermined fraction of illumination intensity referred to above is preferably one-half. That is, the intensity of the video background at the border of a symbol is preferably reduced by one-half. Such a reduction in intensity creates a halo around a symbol which is black in appearance, and distinguishes the symbol from background, but which does not induce flickering. The invention will now be described in greater detail, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a schematic diagram illustrating confusion of a symbol with background in a CRT display, to which reference has already been made, Figure 2 is a schematic diagram of the picture elements, in a preferred embodiment of the invention, whose memory address contents determine the status of video background at a picture element P I,J , Figure 3 is a block diagram of a preferred embodiment of the invention, Figure 4 is a block diagram of an address reader and a Boolean processor utilised in the preferred embodiment of the invention, Figure 5 is a schematic diagram of the Boolean processor of Figure 4, Figure 6 is a schematic diagram utilised in describing, in a preferred embodiment of the invention, the circumstances in which the intensity of background illumination is reduced at a picture element P I,J , Figure 7 is a block diagram of an alternative address reader and a Boolean processor, and Figure 8 is a schematic diagram, partially in block, of the Boolean processor and a background video dimmer of Figure 7. Identical numerals in different figures of the drawings represent similar elements. The present invention entails apparatus for generating halos around symbols on CRT displays in order to distinguish the symbols from video background. A CRT display is coupled to an image memory. A picture element in the CRT display is illuminated as symbology if the corresponding address in the image memory contains a video bit signal of "1". The picture element is not illuminated as symbology if the corresponding address in the image memory contains a video bit signal of "0". The picture element with which the beam generator of the CRT display is currently aligned may be denoted P I,J . The video bit signal in the address in the image memory corresponding to the currently aligned picture element P I,J may be denoted B I,J . Referring to Figure 2, when the beam generator of the CRT display is currently aligned with the picture element P I,J , the surrounding picture elements, P I-1,J-1 ; P I,J-1 ; P I+1,J-1 ; P I-1,J ; P I+1,J ; P I-1,J+1 ; P I,J+1 ; and P I+1,J+1 , are considered. If the video bit signal B I,J in the address in memory corresponding to the picture element P I,J is a "1" then P I,J is part of a symbol and background video at P I,J is not altered. The background at a picture element comprising an illuminated symbol may be unilluminated, in order to enhance the symbol's clarity. If the video bit signal B I,J in the address in memory corresponding to the picture element P I,J is a zero then P I,J is not illuminated as symbology, and therefore may be part of the border of a symbol. This is the case when any of the surrounding picture elements P I-1,J-1 ; P I,J-1 ; P I+1,J-1 ; P I-1,J ; P I+1,J ; P I-1,J+1 ; P I,J+1 ; P I+1,J+1 is illuminated. Accordingly, when B I,J is zero and any of the addresses in memory corresponding to the picture elements surrounding the presently aligned picture element P I,J contains a video bit signal 1, then P I,J borders an illuminated symbol. In this case, the intensity of the video background illumination at P I,J is diminished, in order to make the symbol more discernable. The above procedure may be described mathematically. The dimming status, denoted DS, of the intensity of the video background illumination at the currently aligned picture element P I,J is either 0 or 1. A "0" indicates the intensity of the video background illumination at P I,J is to be unchanged; and, a "1" indicates the intensity of the video background illumination at P I,J is to be reduced. In conformance with the description above:- The B X,Y addends are the video bit signals in the addresses corresponding to the nine picture elements in Figure 2. The summation represents a Boolean "OR" operation. That is, the sum will be 1 when any one of the B X,Y is 1, and will be zero only when all of the B X,Y are zero. B I,J , as before, is the video bit signal in the address corresponding to the picture element P I,J . The bar above B I,J denotes complement, wherein 1=0. and 0=1. The product represents a Boolean "AND" operation. That is, the product will be 1 only when both factors are 1, and will be zero otherwise. Accordingly, if B I,J is 1, indicating that P I,J is part of an illuminated symbol, then B I,J = 1 = 0, and The zero value for DS indicates that the intensity of the video background illumination at the currently aligned picture element P I,J is to be unaltered, in conformance with the description above. If B I,J is 0, indicating that the picture element P I,J as symbology is unilluminated, and if any video bit signal is 1 in the addresses corresponding to the picture elements in Figure 2 surrounding the picture element P I,J , indicating that P I,J borders a symbol, then B I,J = 1 and and thus, DS = 1. The 1 value for DS indicates that the intensity of the video background illumination at the picture element P I,J is to be reduced, in conformance with the description above. If B I,J is zero and all of the video bit signals of the addresses corresponding to the surrounding picture elements are zero, then picture element P I,J does not border a symbol, and the intensity of the video background illumination at P I,J is to be unchanged. The calculated DS for this situation is 0, which conforms to the description. Thus, the dimming status, DS, of the intensity of the video background illumination at the currently aligned picture element P I,J may be expressed as:- Referring to Figure 3, the above expression may be implemented as follows. A coordinator 40, coupled to a CRT display 41, generates coordinates, and aligns the beam generator of the CRT display with the picture elements corresponding to the generated coordinates. The coordinator 40 is also coupled to an address reader 42 which is coupled to an image memory 43. The address reader 42, in response to a signal from the coordinator 40 indicating the coordinate of the picture element with which the beam generator is currently aligned, reads from the image memory 43 the video bit signals in the nine addresses associated with the currently aligned picture element. That is, denoting, as before, the currently aligned picture element as P I,J the video bit signals B I,J ; B I-1,J+1 ; B I,J+1 ; B I+1,J+1 ; B I+1,J ; B I+1,J-1 ; B I,J-1 ; B I-1,J-1 ; and B I-1,J in the addresses of the image medmory 43 corresponding, respectively, to the picture elements P I,J ; P I-1,J+1 ; P I,J+1 ; P I+1,J+1 ; P I+1,J ; P I+1,J-1 ; P I,J-1 ; P I-1,J-1 ; and P I-1,J ; are read from the image memory 43 by the address reader 42. These nine video bit signals are conveyed to a Boolean processor 44 which generates the dimming status of the video background at the currently aligned picture element P I,J . That is, the Boolean processor 44 generates:- A background video generator 46 is coupled to the coordinator and produces background video signals corresponding to the coordinates provided by the coordinator 40. Each background video signal is designed to produce a predetermined intensity of illumination in a corresponding picture element. A background video dimmer 45 receives, from the background video generator 46, a background video signal corresponding to the currently aligned picture element P I,J . In response to a zero digital signal from the Boolean processor 44, the background video dimmer 45 applies the unaltered video background signal to the beam generator of the CRT display 41, illuminating P I,J accordingly. In response to a ONE digital signal from the Boolean processor 44, the background video dimmer 45 applies a signal to the beam generator of the CRT display 41 which engenders illumination of P I,J having an intensity which is a predetermined fraction of that which the video background signal was designed to produce. This predetermined fraction is preferably one-half. In this fashion, the video background bordering an illuminated symbol is dimmed, creating a distinguishing halo around the symbol. Referring to Figure 4, in a preferred embodiment of the invention the address reader comprises shift registers and delays. A shift register 50 is loaded in parallel, with the video bit signal B I-1,J-1 received by a compartment 51, the video bit signal B I,J-1 received by a compartment 52, and the video bit signal B I+1,J-1 received by a compartment 53. After a first delay, a shift register 55 is loaded in parallel, with the video bit signal B I-1,J received by a compartment 56, the video bit signal B I,J received by a compartment 57, and the video bit signal B I+1,J received by a compartment 58. After a second delay, a shift register 60 is loaded in parallel, with the video bit signal B I-1,J+1 received by a compartment 61, the video bit signal B I,J+1 received by a compartment 62, and the video bit signal B I=1,J+1 received by a compartment 63. The shift register 50 serially outputs the contents of the compartments 51, 52, and 53. After the shift register 50 has begun to output, the shift register 55 serially outputs the contents of the compartments 56, 57 and 58. After the shift register 55 has begun to output, the shift register 60 serially outputs the contents of the compartments 61, 62 and 63. A delay 66 synchronises the outputs of the shift register 55 with the outputs of the shift register 60. That is, the first output of the delay 66, B I-1,J, coincides with the first output of the shift register 60, B I-1,J+1 ; the second output of the delay 66, B I,J , coincides with the second output of the shift register 60, B I,J+1 ; and, the third output of the delay 66, B I+1,J, coincides with the third output of the shift register 60, B I+1,J+1 . Similarly, a delay 67 synchronises the outputs of the shift register 50 with the outputs of the shift register 55, and thereby also the outputs of the shift register 60. After action by the delays 66 and 67, video bit signals from the shift registers 50, 55 and 60 having the same X coordinate are synchronised in time. Each of the delays 66 and 67 preferably comprises a shift register. A delay 70 receives the first output of the delay 67, B I-1,J-1 . The delay 70 outputs the video bit signal B I-1,J-1 in synchronism with the outputing of the video bit signal B I,J-1 by the delay 67. The video bit signal B I-1,J-1 is received by the delay 71, and the video bit signal B I,J-1 is received by the delay 70. The delay 71 outputs B I-1,J-1 , and the delay 70 outputs B I,J-1 in synchronism with the outputing of B I+1,J-1 by the delay 67. In this fashion, the three video bit signals B I-1,J-1 , B I,J-1 , and B I+1,J-1 are simultaneously available for conveying to the Boolean processor 44. The outputs of the delay 66 and the outputs of the shift register 60 are processed similarly by, respectively, delays 73 and 74, and delays 76 and 77 such that the video bit signals B I-1,J , B I,J , B I+1,J , and the video bit signals B I-1,J+1 , B I,J+1 and B I+1,J+1 are all available simultaneously, in synchronism with the video bit signals B I-1,J-1 , B I,J-1 , B I+1,J-1 for conveyance to the Boolean processor 44. Each of the delays 70, 71, 73, 74, 76 and 77 preferably comprises a standard D-type flip-flop. Referring to Figure 5, the Boolean processor 44 comprises a nine input OR gate 120 for receiving the video bit signals B I,J ; B I-1,J+1 ; B I,J+1 ; B I+1,J+1 ; B I+1,J ; B I+1,J-1 ; B I,J-1 ; B I-1,J-1 and B I-1,J , and for generating the Boolean OR sum signal of these input signals. A NOT gate 121 receives the video bit signal B I,J and generates a B I,J video bit signal. The output of the Boolean OR gate 120 and the output of the NOT gate 121 are conveyed to an AND gate 122 which generates the required digital signal:- The present invention may be utilised with the invention disclosed in Applicants' copending European Patent Application No. EP-A-0146229 (based on US No. 553224) referred to above and which is hereby incorporated by reference. In the arrangement of the copending application, each memory address is identified by an X and a Y binary coordinate, and video bit signals are stored only in addresses whose X coordinate has a predetermined first binary digit, and whose Y coordinate has a predetermined first binary digit. Each illuminated picture element is replicated three times. This is achieved, as explained in the description of the copending application, by illuminating the currently aligned picture element P I,J when there is a video bit signal of 1 in any of the addresses in the image memory corresponding to the picture elements P I,J , P I-1, J ; P I-1,J+1 ; and P I,J+1 . Accordingly, if any of the video bit signals B I,J ; B I-1,J ; B I-1,J+1 or B I,J+1 is 1, then P I,J is part of an illuminated symbol, and accordingly, the background video at P I,J is unaltered. If none of the video bit signals B I,J ; B I-1,J ; B I-1,J+1 and B I,J+1 is 1, then P I,J as symbology is unilluminated. If there is a video bit signal of 1 in any of the addresses in the image memory corresponding to the picture elements immediately surrounding the picture elements P I,J ; P I-1, J ; P I-1,J+1 ; P I,J+1 ; then P I,J borders a symbol, and the intensity of the background illumination at P I,J is reduced, to create a distinguishing halo around the symbol. That is, referring to Figure 6, assuming that the video bit signals in the memory addresses corresponding to the picture elements P I,J ; P I-1, J ; P I-1,J+1 ; P I,J+1 are all zero, if there is a video bit signal of 1 in any of the memory addresses corresponding to the surrounding picture elements P I-2,J+2 ; P I-1,J+2 ; P I,J+2 ; P I+1,J+2 ; P I+1,J+1 ; P I+1,J ; P I+1,J-1 ; P I,J-1 ; P I-1,J-1 ; P I-2,J-1 ; P I-2,J ; P I-2,J+1 , then the picture element P I,J borders a symbol. For example, if there is a 1 video bit signal in the memory address of P I-2,J+2 , then the arrangement in the copending application illuminates P I-1,J+2 ; P I-2,J+1 ; and P I-1,J+1 . Thus P I,J borders the illuminated P I-1,J+1 . If there is a 1 video bit signal in the memory address of P I+1,J+2 , then P I+2,J+2 ; P I+2,J+1 ; and P I+1,J+1 are illuminated. Thus P I,J borders on the illuminated P I+1,J+1 . If there is a 1 video bit signal in the memory address of P I-2,J-1 , then P I-1,J-1 ; P I-2,J-2 and P I-1,J-2 are illuminated. Thus P I,J borders on the illuminated P I-1,J-1 . A ONE video bit signal in the memory address of any of the other surrounding picture elements similarly results in an illuminated picture element bordering on the picture element P I,J . The intensity of the background illumination at P I,J is, accordingly, reduced to generate a distinguishing halo for the illuminated symbol that P I,J borders. Mathematically, the dimming status, DS, described above, of the video background at the currently aligned picture elements P I,J may be expressed as:- The expression is the Boolean OR sum of the video bit signals in the memory addresses corresponding to the picture elements P I,J ; P I-1, J ; P I-1,J+1 ; and P I,J+1 . If any of these video bit signals is 1 then the sum is 1. The bar denotes complement. Accordingly, if this sum is 1, the complement is 0 and DS is zero, indicating that the intensity of the background illumination at P I,J is to be unaltered. This conforms to the situation wherein P I,J is illuminated as symbology since one of the video bit signals is 1 in the memory addresses corresponding to P I,J ; P I-1,J ; P I-1,J+1 ; and P I,J+1 ; and, the background video at P I,J is thus left unchanged. If all the video bit signals in the memory addresses corresponding to the picture elements P I,J ; P I-1,J ; P I-1,J+1 ; and P I,J+1 are zero then: This corresponds to P I,J not being illuminated as symbology. If any of the video bit signals is 1 in the memory addresses corresponding to the surrounding picture elements P I-2,J+2 ; P I-1,J+2 ; P I,J+2 ; P I+1,J+2 ; P I+1,J+1 ; P I+1,J ; P I+1,J-1 ; P I,J-1 ; P I-1,J-1 ; P I-2,J-1 ; P I-2,J ; and P I-2,J+1 then indicating that the intensity of the background illumination at P I,J is to be reduced, preferably by one-half. This conforms to the situation wherein P I,J is not illuminated as symbology, but borders on an illuminated symbol and thus, the video background at P I,J is darkened to generate a distinguishing halo around the symbol. Thus, the dimming status, DS, of the video background at P I,J may be expressed as :- Referring again to Figure 3, the above expression may be implemented in a manner analogous to that of the previous dimming status expression. In this case, the address reader 42 reads the addresses in the image memory 43 corresponding to the sixteen central picture elements in Figure 6. The Boolean processor 44 implements the relevant expression for DS above. Referring to Figure 7, the address reader 42 utilised with this preferred embodiment of the invention is analogous to that of Figure 4. A shift register 130, having four compartments, is loaded in parallel, with the video bit signals B I-2,J-1 ; B I-1,J-1 ; B I,J-1 ; and B I+1,J-1 received, respectively, by compartments 131, 132, 133 and 134. After a first delay, a shift register 140 is loaded in parallel with the video bit signals B I-2,J ; B I-1,J ; B I,J ; and B I+1,J received, respectively, by compartments 141, 142, 143 and 144. After a second delay, a shift register 150 is loaded in parallel, with the video bit signals B I-2,J+1 , B I-1,J+1 ; B I,J+1 and B I+1,J+1 received, respectively, by compartments 151, 152, 153 and 154. After a third delay, a shift register 160 is loaded in parallel, with the video bit signals B I-2,J+2 ; B I-1,J+2 ; B I,J+2 ; and B I+1,J+2 received, respectively, by compartments 161, 162, 163 and 164. As before, the contents of the shift registers are serially outputed, staggered in time, with the first output of the shift register 130 occurring first, and the first output of the shift register 160 occurring last. The delays 170, 171 and 172 synchronise, respectively, the outputs of the shift registers 130, 140, and 150 with the outputs of the shift register 160. In this fashion video bit signals having the same X coordinate are aligned in time. Preferably, the delays 170, 171, and 172 each comprises a shift register. The outputs of the delay 170, the delay 171, the delay 172, and the shift register 160 are conveyed, respectively, to a series of delays 180, 181, and 182, a series of delays 184, 185 and 186, a series of delays 190, 191, and 192, and a series of delays 195, 196, and 197 which make all of the video bit signals simultaneously available for conveyance to the Boolean processor 44. Preferably each of the delays 180, 181, 182, 184, 185, 186, 190, 191, 192, 195, 196 and 197 comprises a standard D type flip-flop. Referring to Figure 8, in this preferred embodiment of the invention, the Boolean processor 44 for implementing the expression:- Comprises a sixteen input OR gate 200 which receives the sixteen video bit signals corresponding to the first summation sign in the expression for DS, and generates the Boolean OR sum signal thereof. A four input OR gate 201 receives the four video bit signals corresponding to the second summation sign in the expression for DS, and generates the Boolean OR sum signal thereof. The output of the OR gate 201 is received by a NOT gate 202 which generates the complement thereof. The outputs of the NOT gate 202 and the OR gate 200 are received by an AND gate 203 which generates the Boolean AND product signal thereform. The output of the AND gate 203 is conveyed to the background video dimmer 45. As indicated above, this embodiment of the present invention is utilised in conjunction with the arrangement disclosed in the above-mentioned copending European application . Symbols are generated in accordance with the arrangement of the copending application and halos therearound are generated in accordance with the present invention. The Boolean OR sum signal:- employed in the copending application may be drawn from the output of the Boolean OR gate 201 in Figure 8 of the present invention. The components of the present invention are well-known in the art or readily contrived by one of ordinary skill therein. Referring back to Figure 3, the image memory 43, the coordinator 40, the background video generator 46, and the CRT display 41 are conventional, well-known apparatus. The background video dimmer 45, for conveying background video signals or altering them to diminish illumination intensity, is readily contrived by one of ordinary skill in the art.

Claims: Apparatus for generating a halo about symbols in video display means, comprising: Means (41) for displaying video data comprising a matrix of picture elements, denoted P ,X,Y ; and means for illuminating the picture elements in response to applied signals; means (40), coupled to the video display means, for generating picture element coordinates, for providing signals representative of those coordinates, and for synchronising the illuminating means with the coordinates; means (43) having addresses corresponding to the picture elements, for storing video bit signals, denoted B X,Y ; means (42), coupled to the storage means and to the coordinate generating means, for reading, in response to a signal from the coordinate generating means representing a generated coordinate i,j, the addresses corresponding to picture elements P I-1,J-1 ; P I,J-1 ; P I+1' J-1 ; P I-1,J ; P I, J ; P I+1,J ; P I-1, J+1 ; P I, J+1 ; and P I+1,J+1 ; means (44), coupled to the address reading means for generating a digital signal:- the summation representing a Boolean OR, and the product representing a Boolean AND, means (46), coupled to the coordinate generating means for generating, in response to a signal from the coordinate generating means representative of the generated coordinate i, j, a video background signal for producing a predetermined intensity of illumination of the picture element P I, J ; means (45) coupled to the video display means (41), the digital signal generating means (44), and the video background signal generating means (46), for generating, in response to said digital signal having a value of ZERO and the video background signal, a first signal, and for generating, in response to said digital signal having a value of ONE and the video background signal, a second signal, the picture element P I,J, , being illuminated at a predetermined fraction of said predetermined intensity by the illuminating means of the video displaying means, in response to the second signal, and the picture element P I, J, being illuminated by the illuminating means at said predetermined intensity, in response to the first signal. Apparatus according to claim 1, characterised in that the storage means comprises an image memory (43). Apparatus according to claim 1 or 2, characterised in that the video display means comprises a CRT display (41). Apparatus according to any of the preceding claims, characterised in that the predetermined fraction is substantially one-half. Apparatus according to any of the preceding claims, characterised in that the digital signal generating means comprises a Boolean OR gate (120) having nine input terminals; a Boolean NOT (121) gate; and a Boolean AND (122) gate coupled to receive the output signals from the Boolean OR gate and the Boolean NOT gate. Apparatus according to any of the preceding claims, characterised in that the address reading means comprises a first shift register (50) comprising three compartments (51, 52, 53); a second shift register (55) comprising three compartments (56, 57, 58); a third shift register (60) comprising three compartments (61, 62, 63); a first delay (67) coupled to the first shift register (50); a second delay (70) coupled to the first delay; a third delay (71) coupled to the second delay; a fourth delay (66) coupled to the second shift register (55); a fifth delay (73) coupled to the fourth delay; a sixth delay (74) coupled to the fifth delay; a seventh delay (76) coupled to the third shift register (60); and a eighth delay (77) coupled to the seventh delay. Apparatus according to claim 6, characterised in that the first, and fourth delays each comprise a shift register (67; 66). Apparatus according to claim 6 or 7, characterisd in that the second, third, fifth, sixth, seventh, and eighth delays each comprise a D-type flip-flop. Apparatus according to any of claims 1 to 4, characterised in that each of the addresses is identified by an X and a Y binary coordinate, the video bit signals being stored only in the addresses whose X coordinate has a predetermined first binary digit, and whose Y coordinate has a predetermined first binary digit; in that the addresses correspond to picture elements P I-2, J-1 ; P I-1, J-1 ; P I, J-1 ; P I+1, J-1 ; P I-2 ,J ; P I-1,J ; P I,J ; P I+1, J ; P I-2, J+1 ; P I-1, J+1 P I, J+1 ; P I+1, J+1 ; P I-2, J+2 ; P I, J+2 ;P I-1, J+2 ; P I+1, J+2 ; and in that the digital signal generating means (44) generate a signal:- ` Apparatus according to claim 9, characterised in that the address reading means comprises a first shift register (130) comprising four compartments (131 to 134); a first delay (170) coupled to the first shift register; a second delay (180) coupled to first delay; a third delay (181) coupled to the second delay; a fourth delay (182) coupled to the third delay; a second shift register (140) comprising four compartments (141 to 144) ; a fifth delay (171) coupled to the second shift register; a sixth delay (184) coupled to the fifth delay; a seventh delay (185) coupled to the sixth delay; an eighth delay (186) coupled to the seventh delay; a third shift register (150) comprising four compartments (151 to 154); a ninth delay (172) coupled to the third shift register; a tenth delay (190) coupled to the ninth delay; an eleventh delay (191) coupled to the tenth delay; a twelfth delay (192) coupled to the eleventh delay; a fourth shift register (160) comprising four compartments (161 to 164); a thirteenth delay (195) coupled to the fourth shift register; a fourteenth delay (196) coupled to the thirteenth delay; and a fifteenth delay (197) coupled to the fourteenth delay. Apparatus according to claim 10, characterised in that the first, fifth, and said ninth delays (170, 171, 172) each comprise a shift register. Apparatus according to claim 10 or 11, characterised in that the second, third, fourth, sixth, seventh, eighth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth delays (180 ; 181 ; 182 ; 184 ; 185 ; 186 ; 190 ; 191 ; 192 ; 195 ; 196 ; 197) each comprises a D-type flip-flop. Apparatus according to any of claims 9 to 12, characterised in that the digital signal generating means comprises a first Boolean OR gate (200) having 16 input terminals; a second Boolean OR gate (201) having 4 input terminals. a Boolean NOT gate (202) coupled to receive the output signal from the second Boolean OR gate; and a Boolean AND gate (203) coupled to receive the output signals from the Boolean NOT gate and the first Boolean OR gate.

Inventors: HILBURN, HUGH CAROS, JOHNSON, MICHAEL JOHN
Applicants: HONEYWELL INC.
Application year: 1984
Main classification: G09G1
IPC codes: G09G5, G09G1