DATA PROCESSING SYSTEM

Abstract: A data processing system includes a keyboard having number of keys for entering numeric values and a number of terminator keys for terminating an entered value with the proper exponent, including the proper parameter units, to indicate the weight to be given the entered value. The data processing system is incorporated in an RF vector network analyzer for laboratory and automated production measure­ ments. The data processing system provides for fully coordinated communications between subsystem modules; real time, two channel, precision vector measurements with complete, internal error correction; trace math with stored data; and split screen and combined time and frequency domain analysis and display.

Description: The present invention relates to a data processing system in accordance with the precharacterizing part of claim 1. Such a system is known from US Patent 42 440 24. In the known system the input of a measurement parameter is started by pressing a parameter key such as "center frequency", and the desired value may be entered subsequently via numeric keys. The entry process is terminated by striking one of a selection of terminator keys each defining a selection of power-of-ten multiples or fractional parts of measurement units such as kHz, msec, and mV to be associated with the entered numerical value. TEK products 1983, Tektronix Inc. 1982, p. 68 and 259 describes an oscilloscope which enables plural traces to be displayed. However, this publication nowhere discloses or suggests that the traces can be displayed side-by-side. Also, the displayed variable only concerns a single independent variable displayed along a time axis as abscissa. Accordingly all over-and-under traces have the same independent variable. Relative to the prior art in accordance with US-P-42 440 24, it is an object of the present invention to improve a data processing system in such a manner that a numeric value is automatically terminated with the proper exponent, including the proper parameter units, indicating the weight to be applied to an entered numeric value. This object is, according to the invention solved by the features specified in claim 1. The dependent claims characterize advantageous developments thereof. The control panel uses a number of buttons arranged in a unique hierarcical structure to specify the complete measurement process. Several control buttons are dedicated for functions most commonly used in typical measurement applications, while less common functions are available through a series of logical menus which are accessed via several "softkeys" under control of internal firmware. Altogether, over 70 menus with over 320 functions can be reached by means of the softkeys to provide a wide range of measurements. The present data processing system is incorporated in a vector network analyzer containing intermediate frequency (IF), signal processing, internal computing, and display circuitry, plus the operating panel. A complete measurement system in addition includes a radio frequency (RF) test set, microwave to IF frequency conversion circuitry, and a source of RF signals, such as a synthesized or swept oscillator. The main analyzer includes a display having a variety of display modes including log and linear magnitude versus either frequency or time, linear phase, deviation from linear phase, group delay versus frequency, standard Smith Chart, compressed Smith Chart, expanded Smith Chart, inverted Smith Charts, and "Bull's Eye" polar chart. A variety of marker read out formats is also provided. Examples of the display flexibility provided include a split screen CRT with two independent formats or two responses overlaid on a common format. In addition, any or all of the CRT displays can be directly transferred to a digital printer or plotter without need of an external computer. An embodiment of the invention will now be described in detail with reference to the accompanying drawings. Figure 1 shows a simplified block diagram of an RF vector network analyzer; Figure 2 shows a detailed block diagram of a portion of the RF vector network analyzer shown in figure 1; Figures 3.1 through 3.7 show schematics for portions of the detailed block diagram as shown in figure 2; Figure 4 shows the front panel controls of the RF vector network analyzer shown in figure 1; Figure 5 shows a hierarical CPFR structure used in the RF vector network analyzer shown in figure 1; Figures 6 through 15, 17, and 18 show several of the measurements which can be performed with the RF vector network analyzer shown in figure 1; Figure 16 shows a coaxial line as measured and displayed in figure 15; Figure 19 shows the software signal processing flow used in the RF vector network analyzer shown in figure 1; and Figure 20 shows the software process controller used in the RF vector network analyzer shown in figure 1. Figure 1 shows a block diagram of an RF vector network analyzer system. The measurement system consists first of a main network analyzer 101 with a second IF/detector section 103 and a data processor/display section 105. The main network analyzer 101 is fed by one of four configured test sets 107 which provide the signal separation circuitry 108 and a first IF frequency conversion circuitry 113 for reflection/transmission (one incident signal) or S-parameter (two incident signals) measurements up to either 18 or 26.5 GHz. The frequency converter 113 alone is also available to permit the addition of user supplied signal separation devices 108 for specially configured test needs. The third main component of the measurement system is a compatible RF source 109 such as an HP 8340A synthesized sweeper, available from the Hewlett-Packard Co., Palo Alto, California, which can be used in either a stepped frequency mode, in which synthesizer class frequency accuracy and repeatability can be obtained by phase locking the source 109 at each of the over 400 frequency steps over the frequency range selected by the main analyzer 101 or the swept frequency mode for applications where extreme frequency range, high stability, and spectral purity are important such as in narrow band measurements over sweeps of less than 5 MHz. An HP 8350B sweeper with HP 83500 series RF plug-ins covering the entire desired frequency range or with lesser spans can also be used in applications where a more economical source is sufficient. Both the HP 8340A and the HP 8350B include the necessary analog interface signals as well as full digital handshake compatibility with the main analyzer 101. This digital handshake compatibility allows the main analyzer 101 to act as the controller for the entire system by directly managing the source 109 to provide all of the inputs such as start frequency, stop frequency, centering, span, and modulation, as well as constraints that the source 109 normally places on itself internally. Therefore, the user need only be concerned with his interface to the main analyzer 101 and can use any source 109 that has implemented the required handshake protocols. Because the main analyzer 101 is in control of the source 109, it is also possible to automatically select a different frequency range or mode (stepped or swept) to be applied to each of the ports 1 and 2. Integrated within each test set 107 is the first IF frequency converter 113 with three channels 113a, 113b, and 113c for reflection/transmission measurements and four channels 113a, 113b, 113c, and 113d for S-parameter measurements. RF to IF conversion is achieved through a sampling technique equivalent to harmonic mixing. An harmonic of a tunable local oscillator 115 is produced by an harmonic generator 116 to mix with the incoming RF signal to provide the first IF signal at 20 MHz for the incident signal a1 on the input port 1, the incident signal a2 on the output port 2, the reflected or transmitted signal b1 on the input port 1, and the reflected or transmitted signal b2 on the output port 2. Frequency tuning for the local oscillator 115 is controlled by a phase lock loop 117 that compares the signal a1 or a2 in the reference channel first IF to an IF reference oscillator 119 in the IF/detector section 103. Any difference between the frequency of the signal a1 or a2 in the reference channel first IF and the IF reference oscillator 119 results in an error voltage on the error voltage signal line 121 via switch 123 that tunes the local oscillator 115 to the frequency that produces the desired first IF. Switch 123 is toggled to select the most appropriate signal a1 or a2 to lock on to based either on internal criteria within the system or as defined by the user. When using the internal criteria, if the incident signal port is port 1, a1 is selected by switch 123, and if the incident signal port is port 2, a2 is selected by switch 123. This scheme allows the local oscilator 115 to track the incoming RF when the RF frequency is changing with time as in the swept mode. The integrated test set 107 permits high RF to first IF conversion efficiency even at 26.5 GHz, making possible both high sensitivity and wide dynamic range measurements. The test set architecture eliminates the extensive RF switching needed in previous test sets, removing the significant uncertainties caused by the lack of repeatability of mechanical switches. The reflection/transmission test sets 107 require no internal switching since the fourth channel 113d is not required, and the S-parameter test sets 107 use only one electronic PIN diode switch located inside of the test set 108 such that it cannot contribute to uncertainties as it is switched prior to the ratio node of the power splitter. Several concepts have been incorporated in the IF/detector section 103 of the main analyzer 101 to increase the precision of IF processing and signal detection. Most of the phase lock hardware 125 in the phase lock loop resides in this section 103. Harmonic mixing number and local oscillator pretuning are controlled digitally via lines 127 and 129 and offer phase lock and tracking performance that is precisely repeatable from sweep to sweep. Before the first IF signals proportional to a1, a2, b1, and b2 are sent to the synchronous detectors 131 and 133, they are down converted to a second IF at 100 KHz by mixers 138 and go through a pair of multiplexers 136 and variable gain amplifiers 134 in the second IF section 135. Amplifier gain is controlled and calibrated digitally and is varied by autoranging to optimize the second IF signal levels 130 and 132 available to the synchronous detectors 131 and 133 resulting in an order of magnitude improvement in signal to noise performance and dynamic accuracy for the detector output signals x1, y1, x2, and y2. Likewise, the synchronous detectors 131 and 133 employ a digital architecture that allows for precise control of their 90 degree phase shift function which results in improved accuracy as well as common mode rejection of local oscillator phase noise effects. Finally, the detected signals x1, y1, x2, and y2 are multiplexed with a sample-and-hold/multiplexer (MUX) 137 and then digitized by an analog-to-digital converter (ADC) 139 with 19 bits of resolution. Each ADC conversion takes approximately 40 microseconds and four readings are made for each RF frequency data point to provide the real and imaginary data for both the reference signal 130 and test signal 132. The output of the ADC 139 is then passed on a 16 bit bus 141 to a high speed central processor (CPU) 143 which includes a microprocessor such as a Motorola 68000 as well as the associated microprocesor system interrupt and I/0 control circuitry. Because the CPU 143 is integrated into the main network analyzer 101 it is possible to utilize a multi-tasking architecture to make more efficient use of time than has previously been possible. This architectural integration also permits substantial increases in data processing flexibility and system control performance. Via a dedicated system interface and bus 145, the CPU 143 controls the RF source 109, the test set 107, and, along with the sample selection and timing circuitry 146, all of the IF processing functions including the phase lock hardware 125, autoranging in the IF amplifiers 134, detection by the synchronous detectors 131 and 133, and digitization by the ADC 139. The CPU 143 periodically initiates a self calibration sequence for the IF amplifiers 134, synchronous detectors 131 and 133, and the ABC 139 and the resulting gain, offset, and circularity changes are stored in memory 147, so that the changes in the IF amplifiers 134 can be subtracted from measured results. The CPU 143 also performs all data processing functions for the system. The signals in the IF section 103 are detected as linear real and imaginary components of a vector quantity and the CPU 143 processes the detected data into a variety of formats for presentation on the CRT display 149. By digitally computing the various measurement formats, improvements in dynamic range and meaningful resolution are gained over traditional analog circuit processing techniques. With the known network analyzer systems, an external computer was required in order to characterize and remove systematic errors. With the present RF vector network analyzer, this capability exists internally with enough storage capacity (i.e., 256K bytes of random access memory (RAM) and 256K bytes of bubble memory) in the memory 147 to retain up to two 401 point 12-term error corrected traces of data. In addition, the measured data can be converted to show the response of the DUT 111 as a function of time (time domain) using an internal Fourier transform process. All data processing takes place virtually in real time by means of parallel data processing in the CPU 143 aided by the incorporation of a dedicated, floating point, complex number, vector math processor 151 designed specifically for fast vector computations. The multiplication of two complex numbers by the vector math processor 151 requires only one operation with the product available within 20 microseconds, so that error corrected measurement results are available 1000 times faster than in the prior art. By means of an internal vector graphics generator 153, the real time processed data is then immediately presented on the CRT 149, on a digital printer/plotter 155, or via an IEEE-488 (HP-IB) interface and bus 157 to external devices. Present as well as past states of front panel controls 159, past and present traces of data, and entire system calibrations can also be stored in and recalled from the memory 147 or loaded and read from a built-in tape drive 161 by means of the system 203 interface and bus 215 (Fig.2) of the CPU 143. As explained previously and shown in more detail in figure 2, the built-in CPU 143 with its 16-bit multi-tasking microprocessor 201, I/O interface circuitry 203, and interrupt system and I/O control circuitry 205, and the vector math processor 151 with its math processor circuitry 207 and math controller 209 are key to the high speed performance of the present RF vector network analyzer. To insure maximum processing speed, processing power is distributed among several internal controllers in addition to the microprocessor 201 and the math processor 207. Similarly, both the system bus 145 and the external HP-IB bus 157 have their own internal processors 221 and 223. Finally, controllers 225, 227, and 229 are dedicated to the tape drive 161, the bubble memory 235 within memory 147, and the front panel 159 respectively. Figures 3.1 through 3.7 show detailed schematics of portions of the block diagram shown in figure 2. The front panel interface 229 is shown on figures 3.2-3.3 and the remainder of the front panel 159 is shown on figures 3.5-3.7. Figure 4 shows the front panel 159 of the present RF vector network analyzer with capability to set up and control two independent measurements with two measurement channels selected by channel buttons 405 and 407. When the indicator 401 or 403 above the channel buttons 405 and 407 is lit, the respective channel is selected as the channel controlled by the front panel 159. The CRT 149 is also available for viewing on the front panel 159. Annotation on the CRT 149 includes graticules if desired, labels for one or two data side by side or overlaid data traces, reference line position symbols, and channel labels for the parameter being shown, the format of the display, reference line value, horizontal and vertical scales, and the value of any markers being used. Source frequency or other stimulus information is shown on the CRT 149. An active entry menu area 409 in which no data traces are displayed is also provided on the CRT 149 for identification of the current active functions which may be selected via the CRT softkeys 411. The softkeys 411 therefore extend the accessable instrument capabilities by adding selectable functions without adding to front panel complexity. An Entry Off key 413 clears the active entry state. Prompts, indications of instrument functions, procedural instructions, error messages, and procedural advisories also appear on the CRT 149. If a message is important to the measurement, a beep sound signals the operator to look at the message. A title area 415 is also provided for up to 50 characters of information about the measurement beng viewed. To use the title function, the Auxiliary Menus System button 417 is pressed, followed by one of the softkeys 411 which will be labeled Title. The RPG knob 419 is then rotated to position an arrow symbol below the first letter desired and displayed on the CRT 149. The user then presses a Select Letter softkey 411 and the selected letter will appear in the title area 415. This process is repeated as desired along with desired Space softkeys 411 and Backspace keys 411, terminated with the Done softkey 411 and cleared with the Clear Softkey 411. All basic measurement functions are controlled by the four groups of keys (SPFR) labeled Stimulus 423, Parameter 425, Format 427, and Response 429 which respectively are used to set the stimulus, select the parameter, select the format, and adjust the response for the desired measurement. The Stimulus keys 423 provide direct control of the source 109 to set the frequencies, source power, sweep time, and other related functions. The Parameter keys 425 select the parameter to be measured. With the source 109 applied to port 1, S₁₁ is selected for reflection (return loss) and S₂₁ is selected for transmission (insertion loss or gain). Likewise, with the source 109 applied to port 2, S₂₂ is selected for reflection and S₁₂ is selected for transmission. Appropriate control of the test set 107 is enabled automatically depending on the parameter selected. The Format keys 427 place measured parameter data in the desired format: logarithmic (dB), phase, group delay, and Smith Chart, or, alternatively, SWR, linear magnitude, R + jX impedance, and others. The Response keys 429 set the scale per division, reference value, or reference position, or let the AUTO function via the Auto key 430 automatically place all the measured data on the entire display 149 with pleasing values for a reference value and scale. Additional Response functions include averaging, smoothing, and an electronic line stretcher. An hierarchical Channel-Parameter-Format-Response (CPFR) structure as shown in figure 5 is used in the present invention. Once a particular path through the CPFR structure has been chosen, this path is stored in the memory 147 for later reference. Then, when one of the CPFR structure items is changed, such as changing the Parameter from S₁₁ to S₂₂, the entire path previously associated with the new item is automatically reestablished for use by the entire system. Thus, for example, if Channel 1 is presently being used to measure the Parameter S₁₁ with the display in log magnitude Format and a 0.2 dB/division vertical Scale, and if Channel 1 was previously used to measure the Parameter S₂₂ with the display in linear magnitude Format and a 5 milliunits/division vertical Scale, then when the Parameter is changed from S₁₁ to S₂₂ the Format automatically changes from log magnitude to linear magnitude and the Scale automatically changes from 0.2 dB/division to 5 milliunits/division. In addition, since the CPFR structure is an hierarchical tree and since Parameters are lower in the hierarchy than Channels, the Channel number will not be changed when the Parameter is changed as in the present example. Similarly, if the Channel is changed, the Parameter, Format, and Response are all subject to automatic reestablishment, and if only the Format is changed, only the Response is subject to automatic reestablishment. Naturally, any of the CPFR values may be altered from the front panel 159 as desired by the user. The result of this hierarchical CPFR structure is a substantial added degree of speed and convenience for the user. The numeric Entry keys 431 are used when a numeric value is to be entered, which entered value is terminated by one of the four terminator keys G/n 433, M/u 435, k/m 437 and x1 439. The four terminator keys 433-439 are used when the entered value being terminated has the order of magnitude respectively of either Giga (10⁺⁹) or nano (10⁻⁹), Mega (10⁺⁶) or micro (10⁻⁶), kilo (10⁺³) or milli (10⁻³), or a basic unit (10⁰) such as dB, degree, second or hertz. No particular set of measurement units is permanently assigned to any of the four terminator keys 433-439. Pressing the Save key 441 followed by one of the CRT softkeys 411 saves the current complete state of the network analyzer 101, and the controlled functions of the source 109 and the test set 107. The Recall key 443 followed by a CRT softkey 411 is used to recall the previously stored instrument state. The hierarchical CPFR structure is an integral part of the instrument state. The Tape key 469 in the Auxiliary Menu Block 471 displays labels in area 409 for controlling the internal tape drive 241. The tape functions allow initialization of cassette tapes, storing data to tape, loading data from tape, deleting data on tape, erasing the last deletion of data, and display of a directory of tape contents on the CRT 149. When measurement data is loaded from tape to any point in the Data Processing path, the display on the CRT 149 is updated to show the loaded data with subsequent data processing. Tape data can be a combination of any of the following: 1. Measurement data after second IF and detector correction (raw data), after error correction and/or time domain conversion (data), or after formatting (formatted data) for either or both measurement channels. 2. Memory data stored after time domain conversion and before formatting from an earlier measurement, individually or all at once. 3. Graphics that the user has created on the CRT 149 Figure 4. 4. One or all sets of machine states stored by pressing the Save key 441 Figure 4. 5. One or all sets of error coefficients measured and stored by pressing the CAL key 457, and the subsequent Calibrate softkeys 411 labeled in the area 409. 6. One or all sets of calibration standard descriptions (Cal Kits). 7. A complete machine dump consisting of all sets of all data described in 1 through 6. 8. System, service, or demo software, including options, revised versions, and new software. If an external device has control of the system using the HP-IB interface 157, pressing the Local key 445 returns control of the system to the front panel 159. The Restart key 447 is used to restart any previously started measurement or data handling operation such as sweeping or averaging. Three blocks of the front panel keys along with the softkeys 411 provide an additional feature called MENUS for functions which are used less frequently than the functions to which dedicated keys are assigned. The four Menu keys 449, 451, 453, and 455 provide extensions of the SPFR keys 423, 425, 247 and 429; the keys labeled Cal 457, Domain 459, Display 461, and Marker 463 in the Menus blocks allow selection of various measurement and display modes; and the keys labeled Copy 467, Tape 469, and System 417 under the Auxiliary Menus block 471 provide measurement related input and output operations. Shown in Appendix A is an example which illustrates the various MENUS along with the softkey labels, shown in quotation marks, as displayed in the menu area 409 of the CRT 149 opposite the related softkeys 411. When a MENU is displayed on the CRT 149 any current choices are indicated by a line under the labels and mutually exclusive and/or closely related choices are connected by dots. Pressing the softkey 411 beside any label in area 409 either executes the function or presents another set of MENU labels. If the selected function requests an input, the RPG knob 419 and Entry keys 431 are used to respond. Addtional functions are selected by pressing another key. A Prior Menu key 473 is used to return to the previously displayed MENU in a series of menus. If the previously displayed MENU was the first in a series of MENUS, the MENU is cleared from the CRT 149. Several of the wide variety of displays available either on the CRT 149 or on the printer/plotter 155 are shown in Figures 6 through 15, 17 and 18. Figure 6 shows a typical dual trace measurement of two different parameters S₁₁ and S₁₂ signified by trace number 601 and 602 respectively with the same log magnitude format used for example to adjust a circulator's impedance and isolation simultaneously in real time. Figure 7 shows two overlaid traces 701 and 702 for ports 2 and 3 respectively of a three port multiphase filter. Figure 8 shows a single trace of an amplifier and an attenuator combined to show the total closed loop response of the active circuit. Figure 9 shows a measurement trace of the same active amplifier as in figure 8 calibrated in a user defined reference plane with an electrical delay of 6.0421 nanoseconds making use of the electronic line stretcher. Figure 10 shows a unique split screen of two simultaneous measurements of two different parameters S₁₁ and S₂₁ as displayed on the CRT 149. Figure 11 shows another version of the split screen display, split to simultaneously show the response of a surface accoustical wave filter (SAW device) in both the frequency and time domains. Note the appearance of the triple travel peak 1101 on the time domain response. Figure 12 shows two different parameters displayed with two different formats (i.e., SWR and deviation from linear phase) for traces 1201 and 1202. Figure 13 shows a previous measured trace 1301 from "memory" and the current measurement trace 1302 of the same parameter S₂₁ which can be used for matching transmission lines to within 0.01 degrees. Figure 14 shows the display of group delay for a typical RF communications filter which with the present invention can be viewed and adjusted for optimum group delay flatness in real time. Figure 15 shows a linear display of an RF circuit in the transformed time domain along with a series of five markers 1501-1505 to mark the five different corresponding discontinuities respectively (i.e., connector 1601, connector 1602, adapter 1603, connector 1604, and termination 1606) of a coaxial line 1610 as shown in Figure 16 . Figure 17 shows a split screen of two polar plots as displayed simultaneously on the CRT 149. Each of the Figures 6 through 15 and 17 are displays of actual RF divices as shown in real time on the CRT 149. These same displays can also be printed on the printer/plotter 155 as they are shown on the CRT 149 with whatever size change is desired and in a variety of colors. If desired, various of the CRT displays can also be combined on the printer/plotter 155 as a four quadrant plot as shown in Figure 18. Up to five different markers for the traces on the CRT 149 are accessed via the Marker key 463 along with the softkeys 411 as shown in figure 15 by markers 1501-1505. The markers are controlled in a number of different ways. The numeric entry keys 431 are used to set the markers to an exact numeric position, the RPG knob 419 is used to move the markers along the traces on the CRT 149, the up Step key 475 and the Down Step key 477 move the markers right and left one horizontal division. The precise value of the marker position is also immediately displayed on the CRT 149 as shown in figure 8 by marker 801 and the displayed value 802. The marker annotation is displayed adjacent to the marker 801. In addition, as the markers are moved along the traces, the marker annotation moves with the markers so that the user can always immediately identify which marker and related annotation is which. A further function available through the softkeys 411 is Delta Markers for reading the difference in the trace value between an Reference Marker and a Delta Marker as shown by markers 703 and 706 in figure 7. The RPG knob 419 is used to sequentially position the Reference Marker and the Delta Marker and the difference in trace value is immediately displayed on the CRT 149. Also available with the aid of the softkeys 411 are Marker to Minimum and Marker to Maximum functions to move a selected marker to the minimum or maximum value of the displayed trace as shown by markers 1001 and 1002 in figure 10. A further function is the display of marker frequency, as shown in Figure 10, or other stimulus value, as shown in Figure 15. The equal marker key 479 enters the current stimulus or amplitude value, as appropriate, of the most recently active marker for the current active function. For example, selecting the reference value key (429 Figure 4) followed by the equal marker key 479 causes the amplitude of the marker to be entered for the reference value. Similarly, selecting the stimulus start key (423 Figure 4) followed by the equal marker key 479 causes the frequency, or other stimulus value, of the marker to be entered for the start function. Software Signal Processing As shown in in figure 19, signal processing in the present invention begins at the output of the synchronous detector pair 131 and 133 which provide the real (X) and imaginary (Y) parts of the test and reference signals. Offset, gain, and quadrature errors are corrected for both of the IF/detector chains via software which is arranged as blocks IF gain test 2803 and IF Correction 2805. The resulting test and reference data is then ratioed in block 2807 to produce the appropriate S-parameters and stored in the Raw Array 2809. If requested by the user, subsequent data taken at the same frequency are averaged together in the IF Averaging block 2811 to lower system noise and thus enhance dynamic range. While the Raw Array 2809 is continually filled under control of the data acquisition software which will be discussed shortly, the data processing software concurrently removes data from the Raw Array 2809 and performs additional signal processing. Using a one term model (vector frequency response normalization), a three term model (one port model), and up to a twelve term error correction model (comprehensive two port) of the microwave measurement hardware, the Vector Error Correction software 2813 in conjunction with the Vector Math Processor 151 provides corrected data through application of the Error Array 2815 to the Raw Array. Further data manipulation is provided as desired by the user through Gating 2817 along with the separate Gate Array 2879 Electrical Length/Reference Plane Extension 2821, and Parameter Conversion 2822. The corrected data may also be converted from the frequency domain to the time domain using Chirp Z transforms. Windows 2825 and Window Array 2827 are used to remove the ringing in time domain due to band limited frequency domain input signals and then using the Chirp Z transforms 2823 to transform into the time domain. The data in the Data Array 2829 may be stored into memory in the Memory Array 2833 and used in vector computations with data from a second device. Comparisons of present data (D) and memory data (M) is accomplished through vector computations to provide all four mathematical functions of D * M, D/M, D + M, and D - M. Storage of the corrected and processed data D in the Data Array 2829 and the trace math data M in the Memory Array 2833 allows rapid response to the user when making format or trace math changes. The vector data is then formatted in the Format block 2835 into magnitude, phase, group delay, or other formats as desired. Adjacent formatted points can then be combined if desired in the Smoothing block 2837. The resulting formatted data is stored into the Format Array 2839 which provides convenient access for scale and offset changes provided by the Scale block 2843. Markers are also applied as desired to the formatted data via the Marker Readout block 2841. Scaled data is stored in a Display Array 2845 in the Display Ram 217 from which the display generator 153 hardware repetitively creates a plot on the CRT 149 for a flicker-free display. Input and output access is provided to and from all of the arrays via the HP-IB interface 157 and via tape 161 with S-parameters available from the Data Array 2829 in addition to other applicable arrays. Direct printer output for the printer 155 is made from the Format Array 2839. Direct plotter output for plotter 155 is made from the Display Array 2845. The user may also trade off the data update rate against the number of data points used by selecting resolutions from 51 to 401 points. Selected parts of the operating software are shown in source code format in Appendix B. Appendix B also references publications defining the program languages used in the source code listings. The software is structured as a multi-tasking system to provide a rapid data update rate by allowing data processing to take place when the data acquisition software is not busy. Overlying command and control tasks interleave data processing with data acquisition cycles to provide both two port error correction and dual channel display modes. The software signal process discussed previously is controlled by a process structure as shown in figure 20. This process structure is one of the reasons the present invention can process RF data essentially in real time. For example, low priority processes such as controlling the source 109, controlling the test set 107, and formatting the display 149 are only performed when the data acquisition process is not busy. Previous systems would take data, process it completely through to the display and when the end of each sweep is reached, the processor had to wait for the hardware to reset. Instead, the present invention actually performs processing while the control functions such as resetting for a subsequent sweep or while switching S parameter are proceeding. The Command Sources 2901 accept user commands via the front panel 159 and the HP-IB interface 157, parses and converts the commands to a common internal command token regardless of source and puts the commands into a command queue 2903. The Command Processor 2905 takes the commands from the command queue 2903 and implements them. Any one time precomputation that will later improve run time efficiency is done at this time. The Command Processor 2905 modifies the instrument state and performs one time operations, such as updating a trace after a scale change, outputting an array of data, and copying the Data Array into the Memory Array. Based on the instrument state, Control 2907 is responsible for insuring that the desired data is acquired in the specified manner and conditions. This includes control of source 109, test set 107, phase lock 125, IF multiplexers 136, ADC 139, and set up of the data acquisition and processing. Swept and stepped, alternate and chopped, single and continuous signal sweeps are implemented within Control 2907. Sweep maintenance is also managed in the Control 2907 to keep track of bandcrossings and frequency stepping. Acquisition 2909 services the ABC 139 interrupt, IF gain auto-ranging, ratioing, averaging and storing data into the Raw Array 2809. Processing 2911 processes data from the Raw Array 2809 until the data are displayed on the CRT 149 including vector error correction of external errors, parameter conversion, (gating, windowing, and transformation), trace math (D * M, D/M, D + M, D - M), formatting (log, linear, and delay), and response (scale, reference value, and split screen). The machine state variables that are used to derive control variables 2913 include: parameter descriptions such as test set set-up, receiver set-up, and ratio/non-ratio; user selections for frequency, power, sweep time, formats, scale per division, averaging information, number of points to be taken, error correction type, and time domain factors; and, internal housekeeping pointers to the raw data error coefficients, corrected data, formatted data, memory data, and display data arrays. Acquisition variables 2915 provide data reduced from the control variables 2913 for efficiency that are related to controlling the ADC 139 until the data is stored in the raw array. The Acquisition variables 2915 include: IF gain, receiver error, ratioing, averaging, and current pointer poisition in the raw array. The Processing variables 2917 provide data reduced from the group control variables for efficiency that are related to controlling the processing of data from the raw array through the display. The Processing variables 2917 include: current position pointers for the arrays, error correction type, time domain information, trace math, format, and response. The Signals 2919 provide synchronization between programs that otherwise function independently of one another.

Claims: A data processing system comprising: a keyboard including at least one parameter selection key (425) operable to select a measurement parameter comprising a parameter value and a parameter unit; at least one numeric key (431) operable to enter at least one digit of a mantissa of a digital representation of said parameter value; and at least one terminator key (433, 435, 437, 439) operable to enter an exponent of said digital representation of said parameter value; and further comprising processor means coupled to said keyboard for receiving said measurement parameter; characterized in that said terminator key (433, 435, 437, 439) has associated therewith a pair of reciprocal exponents of said digital representation of said parameter value; and said processor means (143) is adapted to automatically select said parameter unit and one of said reciprocal exponents in response to the selection of said measurement parameter. A data processing system in accordance with claim 1, characterized by further comprising: a plurality of dedicated functional keys (423, 425, 427, 429) selectable by a user for selecting frequently used measurement functions for processing the measurement instrument data; and a plurality of menu keys (411) selectable by a user and used in conjunction with at least one of the plurality of functional keys for selecting less frequently used measurement functions for processing the measurement instrument data. A data processing system in accordance with claim 2, characterized in that each of the plurality of menu keys (411) comprises a plurality of softkeys having functions and labels associated therewith, which functions and labels are alterable by the processor. A data processing system in accordance with one of the claims 1 to 3, characterized in that said processing means comprises memory means (147) coupled to a CPU (143) for storing digitally manipulated data; and a display means (153, 218) coupled to the CPU (143) and the memory means (147) having a visual display (149) for substantially simultaneously displaying side by side two traces of the data. A data processing system as in claim 4, characterized in that the two side-by-side traces of displayed data each comprise real time data. A data processing system as in claim 4, characterized in that the two side-by-side traces of displayed data each comprise historical data stored in the memory means. A data processing system as in claim 4, characterized in that one of the two side-by-side traces of displayed data comprises real time data and one of the two side-by-side traces of displayed data comprises historical data stored in the memory means. A data processing system as in claim 4, characterized in that it further comprises: plotter means (155) coupled to the processor means for producing a hard copy output of the two side-by-side traces of data displayed on the visual display. A data processing system as in claim 8, characterized in that the plotter means (155) produces a hard copy output of a plurality of the two side-by-side traces of data displayed on the visual display. A data processing system in accordance with any one of the claims 4 to 9, characterized in that said display means is adapted to display said trace of data having displayed thereon a reference marker and a delta marker for measuring therebetween the amplitude difference in the value of the trace of data. A data processing system as in claim 10, characterized by further comprising; a keyboard for use by a user to select the positions of the reference marker and the delta marker. A data processing system in accordance with any one of the claims 4 to 11, characterized in that said display means has a visual display for displaying a trace of the data; said trace of data has displayed thereon a marker for indicating a current value of the trace of data; and a keyboard is coupled to the processor, said keyboard having a value key and an equal marker key thereon for sequential use by a user to enter into the processor as the value of the value key the current value of the trace of data indicated by the marker.

Inventors: CANNON, WAYNE C., DONECKER, S. BRUCE, NEERING, MICHAEL J.
Applicants: HEWLETT-PACKARD COMPANY
Application year: 1984
Main classification: G01R23
IPC codes: G01R23