PROGRAMMABLE READ-ONLY MEMORY DEVICE PROVIDED WITH TEST CELLS

Abstract: A programmable read-only memory device of a junction destruction type is provided with a test circuit for the purpose of detecting a parasitic thyristor effect which may occur in the data programming operation by the user. The test circuit includes first and second additional row lines, a first diode connected between the first additional row line and one column line, a second diode connected between the second additional row line and another column line adjacent to the one column line, and a transistor of a base-open type connected between the second additional row line and the one column line.

Description: The present invention relates to a read-only memory device, the content of which can be programmed electrically, that is, a programmable read-only memory device (hereinafter simply called as a "P-ROM"). More particularly, the present invention relates to a test circuit for checking whether or not programming data into P-ROM can be conducted without failure. Recently, P-ROM has been gained an extremely wide range of applications in the field of data processing and control because of its advantage in that a user can freely program the data thereinto. So-called "junction destruction type" and "fuse type" P-ROM's are well-known as bipolar P-ROM's. The junction destruction type P-ROM includes memory cells arrayed in a matrix form and each consisting of one bipolar transistor of a base-open type, which has a collector and an emitter connected to one row line and one column line, respectively. To program data in the P-ROM of this type is performed by supplying a considerably large programming current to the selected memory cell to destroy, i.e., short-circuit the base-emitter junction of the cell transistor. As a result, the transistor of the programmed memory cell operates merely as a diode to allow a reading-out current to flow from the column line to the row line in data read-out operation. On the other hand, the base-emitter junction of the transistor in the non-programmed memory cells prevents the current from flowing from the column to row lines. In the fuse type P-ROM, each memory cell consists of a fuse and a diode connected in series between each column line and each row line. The data program in this type is carried out by supplying a programming current to the selected memory cell to melt the fuse. In the read-out operation, the reading-out current does not flow from the selected column line to the selected row line, when the programmed memory cell is disposed at the intersection of the selected column and row lines. If the selected memory cell is not programmed, the reading-out current flows between the column and row lines. The fuse type P-ROM is, however, disadvantageous in that the melted fuse is scattered over the surface of the P-ROM chip to adversely affect the electrical performances of the P-ROM. The junction destraction type P-ROM is preferable in this respect. It will be apparent that a P-ROM without any programmed cell should be offered to users. Accordingly, any defectiveness in the P-ROM does not appear until the programming is done by the user, who finds that the data program cannot be correctly performed. The mal-function of peripheral circuits or the defect in the memory cells themselves may make the data program impossible. However, even where the peripheral circuits and the memory cells have no defect, there occurs a phenomenon that the data program cannot be correctly carried out to the P-ROM of the junction destruction type. This phenomenon becomes remarkable as the memory capacity of the P-ROM increases. It has been discovered that the cause of the phenomenon is a parasitic thyristor effect based on a particular geometrical relationship among the programmed and unprogrammed cells in the memory cell array. The parasitic thyristor effect occurs when the programmed and unprogrammed cells determined by the user take the particular geometrical relationship. In Japanese Journal of Applied Physics, Vol. 19, Suppl. 19-1, 1980, pp. 175-180, a parasitic thyristor effect in a programmable read-only memory employing base-open transistors as memory cells is described, wherein the parasitic effect occurs between neighbouring post-programmed cells and pre-programmed cells. A memory cell according to the preamble part of claim 1 is disclosed in EP-A-0 055 918. This reference relates to programmable read-only memory employing base-open transistors as memory cells in which further a test cell arrangement including two test word lines is provided. The tests to be performed are to check the defectiveness of a memory cell array and operations of peripheral circuits such as address decoders, an output circuit and so on, and it is not apparent in which way the occurrence of parasitic effects may be checked. It is therefore an object of the invention to provide a programmable read-only memory device in which the occurrence of a parasitic thyristor effect is detectable. This object is achieved by a memory circuit having the features of claim 1; the dependent claims are related to further developments of the invention. The P-ROM according to the present invention is thus provided with the test circuit for detecting the occurrence of a parasitic thyristor effect. According to the inventors' finding, the paracitic thyristor effect occurs in four memory cells which are disposed at the respective intersections of the adjacent two row lines and the adjacent two column lines, when first and second memory cells positioned on one diagonal line are programmed and third and fourth memory cells positioned on the other diagonal line are not yet programmed. The first and second transistors respectively constituting the first and second memory cells then operate merely as diodes. When the third memory cell is to be programmed, the row and column lines between which the third memory cell is coupled are selected to supply a programming current to the third memory cell through the selected column line. It should be noted that the diodes of the first and second memory cells and the fourth transistor constituting the fourth memory cell are coupled in series between the selected row and column lines. The collectors of the second and fourth transistors are common to form the column line to which the second and fourth memory cells are connected, and hence the device structure of the part including the second and fourth transistors is equivalent to a P-N-P-N thyristor structure. In other words, a parasitic lateral transistor formed of the base of the second transistor with the emitter being short-circuited to the base by programming, the common collector and the base of the fourth transistor and a vertical transistor formed by the common collector, the base and the emitter of the fourth transistor consitutes the parasitic thyristor. If the product of current gains of these lateral and vertical transistors is more than 1, the parasitic thyristor is made conductive by the programming current. As a result, the programming current supplied to the selected column line flows, not through the selected third transistor to be programmed, but through the first, second and fourth transistors to the selected row line. The program of the third memory cell is thereby impossible. With the test circuit according to the present invention, the first additional row line is selected by the third means and the second one of the column lines is selected by the second means. A current is supplied to the second one of the column lines. Since the first additional row line is disconnected from the second one of the column lines, the current does not flow to the first additional row line if the thyristor effect does not occur. However, if the parasitic thyristor formed by the second diode and the additional transistor is made conductive, the current will flow from the second column line to the first additional row line through the first and second diodes and the additional transistor. This means that the parasitic thyristor effect may also occur in the memory cell array upon the data programming by the user. Thus, the defectiveness in the P-ROM caused by the parasitic thyristor effect can be detected prior to the shipment of P-ROMs. It is favorable that the first and second diodes are formed of the base-collector junction of a transistor. Further, the distance between the anode region of the second diode and the base region of the additional transistor is favorably shorter than that between the base regions of the adjacent two memory cells connected to the same row lines in order to increase the sensitivity of detecting the parasitic thyristor effect by the test circuit. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Figs. 1A, 1B and 1C are an equivalent circuit, a plan view and a cross-sectional view of one memory cell in a P-ROM of a junction destruction type, respectively; Figs. 2A, 2B and 2C are an equivalent circuit, a plan view and a cross-sectional view of a programmed memory cell respectively; Fig. 3 is an equivalent circuit of a memory cell array in which some of memory cells are programmed; Fig. 4A is a plan view of a part including the transistors Q₁₁, Q₁₂, Q₂₁ and Q₂₂ shown in Fig. 3, and Figs. 4B and 4C are cross-sectional views along the lines A-A' and B-B' of Fig. 4A; Fig. 5A is a circuit diagram showing a parasitic thyristor, Fig. 6 is a circuit diagram representing a memory cell array and a test cell array in a P-ROM according to one embodiment of the present invention; Fig. 7 is a plan view of a part including the test cell array and a portion of the memory cell array shown in Fig. 6; Fig. 8 is a cross-sectional view along the line A-A' of Fig. 7; Fig. 9 is a cross-sectional view along the line B-B' of Fig. 7; and Fig. 10 is a block diagram of the P-ROM according to the present invention. DETAILED DESCRIPTION OF THE INVENTION With reference to Figs. 1 to 5, the defectiveness in the data programming caused by a parasitic thyristor effect made clear by the inventor will be described in detail in order to facilitate the understanding of the features and advantages of the present invention. Fig. 1 shows one memory cell in a P-ROM of the junction destruction type, which consists of one NPN transistor Q. The transistor Q has a collector region 1 of an N-type, a base region 2 of a P-type and an emitter region 3 of an N-type, as shown in Figs. 1B and 1C. The collector 1 is connected to one row line X and the emitter 3 is connected to one column line Y, but the base 2 is in an open-state, as shown in Fig. 1A. The transistor Q is programmed by supplying a programming current PI from the column line Y to the row line X through the transistor Q. The base-emitter junction of the transistor Q is subjected to be destroyed, i.e., to be short-circuited by the programming current PI. On the other hand, the base-collector junction is not destroyed, since the programming current PI flows thereinto in a forward-bias direction. As a result, the programmed transistor Q operates as a diode formed of the base-collector junction. The equivalent circuit, a plan view and a cross-sectional view of the programmed memory cell are shown in Figs. 2A, 2B and 2C, respectively. In Fig. 2A, a resistor R connected between the emitter and base of the transistor Q represents the short circuit of the base-emitter junction. Further, fat lines written across the base-emitter junction in Figs. 2B and 2C also indicate the short circuit thereof. Referring to Fig. 3, there is shown a memory cell array 10 in the P-ROM of the junction destruction type. The memory cell array 10 includes a plurality of row and column lines (X₁ to X n , and Y₁ to Y m ) and a plurality of memory cells (Q₁₁ to Q nm ) disposed at the respective intersections of the row and column lines. As mentioned in Fig. 2, the transistors Q₁₂, Q₁₃, Q₂₁ and Q 2m are programmed by the user. Under such a condition, when the transistor Q₁₁ is thereafter programmed by the user, the programming current PI often flows from the column line Y₁ to the row line X₁ through the transistors Q₂₁, Q₂₂ and Q₁₂, not through the transistor Q₁₁, as shown in Fig. 3. This is caused by a parasitic thyristor effect formed of the transistorsQ₂₁ and Q₂₂. More specifically, the collectors of the transistors Q₁₁ and Q₁₂ (and Q₁₃ to Q 1m ) are connected in common to the row line X₁, and therefore, an N-type region 111 serves as collector regions of the transistors Q₁₁ and Q₁₂ and as the row line X₁, as shown in Fig. 4. Similarly, an N-type region 211 serves as collector regions of the transistors Q₂₁ and Q₂₂ (and Q₂₃ to Q 2m ) and as the row line X₂. The regions 111 and 211 are formed on a P-type silicon substrate and electrically isolated from each other by an isolation region 101 of a P-type. Base regions 112 and 122 of the transistors Q₁₁ and Q₁₂ are formed in the region 111 at a distance, and base regions 212 and 222 of the transistors Q₂₁ and Q₂₂ are formed in the region 211 at a distance. Emitter regions 113 and 213 of the transistors Q₁₁ and Q₂₁ are connected to the column line Y₁ made of a metal such as aluminum through contact holes provided in an insulating film 102, and emitter regions 123 and 223 of the transistors Q₁₂ and Q₂₂ are connected to the column line Y₂ through contact holes. The column line Y₂ is also made of a metal. Since the transistors Q₁₂ and Q₂₁ are already programmed, the base regions 122 and 212 are connected to the column lines Y₂ and Y₁ without a P-N junction, respectively. Therefore, as apparent from Figs. 4B and 4C, a thyristor constituted by four regions 212, 211, 222 and 223 is formed between the column lines Y₁ and Y₂, and the column line Y₂ is coupled to the row line X₁ through the base-collector junction of the transistor Q₁₂. The equivalent circuit of this thyristor is shown in Fig. 5. In Fig. 5, a transistor PQ₁ is a parasitic lateral PNP transistor formed of the P-type region 212, N-type region 211 and P-type region 222, and a transistor PQ₂ is a vertical NPN transistor formed of the N-type region 211, P-type region 222 and N-type region 223 (which is equivalent to the transistor Q₂₂). If the product of current gains of the transistors PQ₁ and PQ₂ is more than 1, the parasitic thyristor 150 constituted by the transistors PQ₁ and PQ₂ is made conductive by a programming power to be used for programming the transistor Q₁₁. As a result, the programming current fed from the column line Y₁ flows through the parasitic thyristor 150 and the transistor Q₁₂ into the row line X₁. In other words, the programming of the transistor Q₁₁ is not carried out. The product of current gains of the transistors PQ₁ and PQ₂ may be designed to be less than 1 by lengthening the distance between the base regions of the adjacent two cell transistors and/or doping impuries serving as a life-time killer into the respective N-type regions operating as the row lines. However, the distance between the base regions as well as the doping quantity of the impurities are deviated from the designed value due to the variation in the manufacturing conditions of the device. In addition, the distance between the base regions should be made short in order to obtain a large memory capacity. This means that the current gain of the parasitic lateral transistor PQ₁ is increased. Accordingly, it is not guaranteed that the parasitic thyristor effect is prevented. The parasitic thyristor effect does not appear until the user carries out the data programming. In order to previously remove P-ROMs in which the parasitic thyristor effect may occur, a test cell array 200 is provided in P-ROM according to an embodiment of the present invention, as shown in Fig. 6. The test cell array 200 is disposed separately from the memory cell array 10 for the user's use, and includes two additional row lines X a1 and X a2 , while column lines used therein is common to the column lines Y₁ - Y m of the memory cell array 10. The test cell array further includes a plurality of transistors of a base-open type and diodes preferably formed of the base-collector junction of a transistor, which are selectively disposed at the intersections of the additional row lines X a1 and X a2 and the column lines Y₁ through Y m to form a pattern configuration in which a parasitic thyristor effect may occur. More specifically, the diodes D₁₂ to D 1m-1 are disposed alternately at the respective intersections of the additional row line X a1 and the column lines Y₁ to Y m . In this embodiment, the diodes D₁₂ to D 1m-1 are disposed at the intersections of the row line X a1 and the even-numbered column lines. Disposed at the intersections of the row line X a2 and the even-numbered lines are transistors Q a2 to Q am-1 of a base-open type, and the diodes D₂₁ to D 2m are disposed at the intersections of the row line X a2 and the odd-numbered column lines. Transistors of a base-open type may be disposed at the intersections of the row line X a1 and the odd-numbered column lines. However, it is preferable that the row line X a1 is disconnected from the odd-numbered column lines in order to improve the sensitivity of detection of the parasitic thyristor effect. Fig. 7 shows a partial plan view of the device structure in the test cell array 200 and a portion of the memory cell array 10. The cross-sectional views along the lines A-A' and B-B' of Fig. 7 are shown in Figs. 8 and 9, respectively. An N-type region 250 serves as the collector regions of the transistor Q n1 to Q nm and as the row line X n , since the collector of them are connected in common to the row line X n . The sheet resistance of the region 250 is relatively high, and hence a metal row line X n is also provided and has a contact with the region 250 through contact holes provided in insulating films 290 and 291 covering the region 250. Each of the transistors Q n1 to Q nm has a P-type base region and an N-type emitter region, as mentioned in Fig. 4. The emitter regions of the transistors Q n1 to Q nm are connected to the column lines Y₁ to Y m made of a metal, respectively. An N-type region 251 serves as the cathode regions of the diodes D₁₂ to D 1m-1 and as the first additional row line X a2 . A metal column line X a2 is further provided and has a contact with the region 251 through contact holes provided in the insulating films 290 and 291 in order to reduce the resistance of the region 251. Each of the diodes D₁₂ to D 1m-1 has an anode region of a P-type formed in the region 251. The anode regions of the diodes D₁₂ to D 1m-1 are connected to the even-numbered column lines Y₂, Y₄, ...., as mentioned above. In the drawings, only two anode regions 255 and 256 of the diodes D₁₂ and D₁₄ are shown, and they are connected to the column lines Y₂ and Y₄, respectively. Since the cathodes of the diodes D₂₁ to D 2m and the collectors of the transistor Q a2 to Q am-1 are connected in common to the second additional row line X a2 , an N-type regions 252 is provided to serve as the cathode and collector regions and as the row line X a2 . A metal row line X a2 is also provide to make contact with the region 252. P-type anode regions 257, 260, 263, .... of the diodes D₂₁, D₂₃, D₂₅, .... are formed in the region 252 and connected to the add-numbered column lines Y₁, Y₃, Y₅, ... Each of the transistors Q a2 , Q a4 , .... has a P-type base region (259, 262, ....) formed in the region 252 and an N-type emitter region (258, 261, ....). The emitter regions of the transistors Q a2 to Q am-1 are connected to the even-numbered column lines Y₂, Y₄, .... Each of the anode regions 255, 256, 257, 260, 263 has the same junction depth as each of the base regions of the transistors Q n1 to Q nm and Q a2 to Q am-1 , and thus made of the base-collector junction of a transistor. The respective cross-over points of the additional metal row lines X a1 and X a2 and the column lines Y₁ to Y m are isolated from each other by the insulating film 291. The films 291 and 292 are made of a silicon-oxide. The regions 250 to 252 are formed on a P-type silicon substrate 270 and electrically isolated from one another by an isolation region 280 of a P-type. As apparent from Fig. 9, a pair of diode and transistor which are adjacent to each other, i.e., D₂₁ and Q a2 , Q a2 and D₂₃, D₂₃ and Q a4 , etc., constitues a parasitic thyristor composed of the anode region 257 of the diode D₂₁, the region 252, the base region 259 of the transistor Q a2 , and the emitter region 258 of the same, for example. Further, the column line Y₂ is coupled to the first additional row line X a1 through the diode D₁₂. Accordingly, the equivalent circuit between the column line Y₁ and the additional row line X a1 becomes substantially equal to that shown in Fig. 5. In the test mode, the column line Y₁ and the first additional row line X a1 are selected. Since the row line X a1 is disconnected from the column line Y₁ as apparent from Figs. 6 and 8, a current fed from the column line Y₁ ought not to flow into the first additional row line X a1 . However, if the parasitic thyristor constituted by the diode D₂₁ and the transistor Q a2 is made conductive by the selection of the column and row line Y₁ and X a2 , the current fed from the column line Y₁ flows into the additional row line X a1 through the diode D₂₁, Q a2 and D₁₂. This means that as shown in Fig. 4, the programming into the transistor Q₁₁ is not performed due to the parasitic thyristor effect caused by the programmed transistors Q₂₁ and Q₁₂ and the unprogrammed transistor Q₂₂. Accordingly, the P-ROM having a defectiveness which may occur in the data programming due to the parasitic thyristor effect is removed prior to the shipment to the user. Moreover, as apparent from Fig. 7, the distance between the anode region (257, 260, 263, ....) of the respective diode D₂₁ to D 2m and the base region (259, 262, ....) of the respective transistor Q a2 to Q am-1 is designed to be shorter than that between the base regions of the adjacent two transistors in the memory cell array 10. In other words, the parasitic thristor effect in the test cell array 200 is ease to occur, as compared with the occurrence of the parasitic thristor effect in the memory cell array 10. Accordingly, the P-ROM having the above-mentioned defect can be removed certainly. It is favorable that the distance between the anode region and base region in the test cell array 200 is designed to be 0.7 to 0.9 times of that between the base regions in the memory cell array 10. In a case where the column line Y₃ and the first additional row line X a1 are selected, if at least one of two parasitic thyristors constituted by the transistor Q a2 and the diodes D₂₃ and the transistor Q a4 and the diode D₂₃ is made conductive, a current fed from the column line Y₃ flows into the first additional row line X a1 . Accordingly, the occurrence of the parasitic thyristor effect between the column lines Y₂ and Y₃ as well as those Y₃ and Y₄ is detected. Fig. 10 shows a block diagram of a P-ROM according to the present invention. This P-ROM is formed as an integrated circuit device 300 which has row address signal input terminalsRA₁ to RA i , column address input terminals CA₁ to CA j , and an output terminal OUT. Memory cell array 10 and test cell array 200 have the same construction as those shown in Fig. 6. A row decoder 310 responds to the row address signals supplied to the terminals RA₁ to RA i and selects either one of row lines X₁ to X n . A column decoder 330 responds to column address signals supplied to the terminals CA₀ to CA j and selects either one of column lines Y₁ to Y m . The column decoder 330 supplies an output buffer 340 with a data appearing at the selected column line. The output buffer 340 thus supplies the data to the output terminal OUT. The column address signals are further supplied to a program circuit 320, which thereby selects one of the column lines Y₁ to Y m in order to supply the selected column line with a programming current supplied through the terminal OUT from the externally provided programming equipment (not shown). In a test mode for testing whether the parasitic thyristor effect occurs or not in the test cell array 200, any one of the row lines X₁ to X n should not be selected. For this purpose, an NPN transistor 351 is coupled between the row decoder 310 and the ground potential, and its base is connected the row address terminal RA i-2 through a resistor 360 and a zener diode 357. The row address signal to be supplied to the row decoder 310 has a voltage amplitude of about 5 V. On the contrary, the zener voltage of the zener diode 357 is about 8 V, and hence the transistor 351 is in a nonconductive state upon the data read operation and the data programming operation. When the signal having a voltage level more than 8 V is applied to the terminal RA i-2 , the transistor 351 is made conductive to inactivate the row decoder 310. Also in the test mode, the first additional row lines X a1 should be selected. For this purpose, the additional row line X a1 is connected through inverters 354 and 363 to the collector of a transistor 352 whose base is connected through a resistor 361 and a zener diode 358 to the terminal RA i-1 . When the signal having a level more than 8 V is applied to the terminal RA i-1 , the transistor 352 is made conductive to select the first additional row line X a1 . In other words, the P-ROM is brought into the test mode by pulling up the potentials at the terminals RA i-2 and RA i-1 more than 8 V. When the P-ROM takes the test mode, the column decoder 330 and the output Buffer 340 is inactivated to inhibit the data read-out operation. On the other hand, the program circuit 320 selects either one of the column lines Y₁ to Y m in response to the column address signals supplied to the terminals CA₁ to CA j , and supplies the selected column line (Y₁, for example) with a testing current derived through the output terminal OUT from the externally provided test equipment (not shown). It is preferable that the testing current is selected to be smaller than the programming current. This is because the base-emitter junction of the memory cell is not destroyed even when the testing current flows therein erroneously. If the parasitic thyristor effect occurs in the test cell array 200 as described hereinbefore, the testing current flows into the ground terminal. Accordingly, the potential at the output terminal OUT is lowered. On the contrary, when the parasitic thyristor effect does not occur, the testing current is prevented from flowing into the ground terminal. The potential at the terminal OUT is thereby held at a high level. Thus, it is detected whether the parasitic thyristor effect occurs or not, by monitoring the potential at the output terminal OUT. Since the second additional row line X a2 is not selected in the test mode for testing the occurrence of the parasitic thyristor effect, the selection circuit composed of a transistor 353, a resistor 362, a zener diode 359, and two inverters 355 and 356 may be omitted. However, if the second additional row line X a2 is selected by this selection circuit, the testing current fed from the column line Y₁ flows into the ground potential to lower the potential at the terminal OUT. Accordingly, the test for the operation of the Program Circuit 320 can be attained. As described above in detail, the present invention provides a P-ROM in which the defectiveness in the data programming operation caused by the parasitic thyristor effect is detected before the user performs the data programming. Furthermore, the embodiment of Fig. 10 may be modified in that the memory cell array 10 and the test cell array 200 may be provided plurally to output a plurality of data simultaneously.

Claims: A memory device comprising a plurality of row and column lines (X1-Xn, Y1-Ym), a plurality of first base-open transistors (Q₁₁-Qnm) disposed at respective intersections of said row and column lines, first means (310) responsive to a first set of address signals (RA1-RAi) for selecting one of said row lines, second means (330) responsive to a second set of address signals (CA1-CAj) for selecting one of said column lines, and a test circuit (200, 351-362) including first and second additional row lines (Xa1, Xa2), characterized in that said test circuit further includes a second base-open transistor (Qa2) of the same conductivity type as said first transistors (Q11-Qnm) disposed at the intersection of said second additional row line (Xa2) and a first one (Y2) of said column lines, a first diode (D21) disposed at the intersection of said second additional row line (Xa2) and a second one (Y1) of said column lines in such a direction of current flow as to form a parasitic thyristor structure with said second base-open transistor (Qa2), a second diode (D12) disposed at the intersection of said first additional row line (Xa1) and said first column line (Y2) in a direction of detecting current through said parasitic thyristor structure if flowing, and third means (352, 354, 358, 361, 363, 300, 320) for supplying a testing current to said second column line (Y1) while said first additional row line (Xa1) is selected, and that a first distance between the base region (259) of said second base-open transistor (Qa2) and a region (257) of said second diode (D21), which region is connected to said second column line (Y1), is not greater than a second distance between the base regions of adjacent first base-open transistors. A memory device as claimed in claim 1 , characterized in that said memory device further comprises a data output terminal (OUT) and that said testing current is supplied to said second column line (Y1) through said data output terminal (OUT) from the external of said memory device. A memory device as claimed in claim 1 or 2 , characterized in that said first distance is smaller than said second distance. A memory device as claimed in claim 3 , characterized in said first distance is 0.7 to 0.9 times as small as said second distance. A memory device as claimed in claim 1, 2 or 3, characterized in that said memory device further comprises a first set of address input terminals supplied with said first set of address signals (RA1-RAi) and that said third means (352, 354, 358, 361, 363, 300, 320) selects said first additional row line (Xa1) in response to a signal (RAi-1) supplied to one of said address input terminal and inactivates said first means (310).

Inventors: MAYUMI, HIROSHI, NATSUI, YOSHINOBU
Applicants: NEC CORPORATION
Application year: 1984
Main classification: G11C29
IPC codes: G11C29, G11C17, H01L27