LIGHT EMITTING DIODE DRIVER CIRCUIT

Abstract: The circuit for driving an LED (6) comprises a differential amplifier having two transistors (3,4) with common emitters. Emitter current is supplied by a circuit (5, R₁₂, R₁₃, R₁₄) under the control of a transistor (5). A first delay circuit (9) delays the input signal A and applies the delayed signal (B) to the base of the transistor 3 and, after inversion, to the base of the transistor 4. A second delay circuit further delays the delayed signal (B). An OR circuit (11) has inputs receiving the input signal (A), the output (D) of the second delay circuit (10) and the output (B) of the first delay circuit (9), and an output connected to the base of the transistor (5). Accordingly, the current source to the amplifier (3,4) is turned on just before the input signal is applied to the amplifier (3,4), and is turned off after the input signal level has returned to zero. Current consumption is thereby reduced without joepardising speed of operation.

Description: The present invention relates to a digital optical transmitter for an optical fibre data link and, more particularly, to a drive circuit for driving a light emitting diode which serves as a light source in the optical transmitter. Practical use of an-optical fibre data link began with relatively Low speeds on the order of 1 Mb/s (10 6 bits per second)and, today, it is extending to speeds as high as several hundreds of Mb/s to provide for a data link between large scale computers. So far as optical transmitters for Low speed optical fibre data links are concerned, light emitting diodes (LED) are now predominant over semiconductor lasers as a light source due to the reliability of operation and the simplicity of the driver circuit used. In parallel with such a trend, a remarkable development of high-speed response LED's is under way and it is believed that a high speed optical fibre data link using such an LED as a light source will soon reach a practical stage. Where a light source for an optical transmitter in an optical fibre data link is implemented by an LED and signal modulation at high speeds above several tens of Mb/s is desired, a driver circuit constructed as shown in Figure 1 is extensively used (Stewart D. Personick, Optical Fiber Transmission Systems: Circuit For LED Transmitters, pages 47-53, Plenum Press, New York And London, 1981). As shown, the driver circuit includes input terminals 1 and 2 to which input signals having phases inverted relative to each other are applied. Transistors 3 and 4 constitute in combination a differential amplifier. An LED 6 is connected to the collector of one 3 of the transistors. A transistor 5 cooperates with resistors R12 and R14 to provide a current source circuit. The reference numeral 7 designates a power source input terminal 7 to which a positive DC voltage is applied. In this construction, the transistors 3 and 4 are alternately turned on and off by an input signal so that smooth charging and discharging occur for the junction capacity of the LED 6. Nevertheless, current consumption by such a driver circuit is undesirably great because one of the transistors 3 and 4 is turned on at all times, regardless of the input signal pattern and, thereby a predetermined current constantly flows through the transistor 5. One approach to cut down the power consumption in the above-described circuit is disclosed in Japanese Patent Laid-Open Publication No. 57-31666, published July 6, 1982. The approach consists in applying a clock signal having a predetermined period to the transistor of the current source circuit of the above-described circuit in order to drive a light emitting element only when the clock signal is at a high level. The problem encountered with the disclosed drive circuit is, however, that it requires synchronization in advance between the input signal and the clock signal in order to trigger the switching transistor for correct sampling. In other words, an asynchronous signal cannot be applied to the input terminal. In addition, since the current source circuit is clocked at a predetermined rate, a current flows therethrough even when an input signal is absent, resulting in wasteful current consumption. It is therefore an object of the present invention to provide an LED driver circuit which reduces current consumption while an input signal is absent. It is another object of the present invention to provide an LED driver circuit which drives an LED at a high speed and, yet, offers output light with a waveform identical with that of an input signal. Still another object of the present invention is to provide an LED drive circuit which is applicable to any type of input signal. In accordance with the present invention, there is provided a light emitting diode driver circuit including a differential amplifier having emitter coupled transistors, a light emitting. diode connected to a collector of one of the emitter coupled transistors, and a current source circuit connected to the common emitters of the emitter coupled transistors characterised by a first circuit responsive to an input signal for generating first and second driving signals of opposite phase, the first and second driving signals being coupled respectively to the emitter coupled transistor whose collector is coupled to the light emitting diode and to the other transistor and by a second circuit responsive to the input signal for generating a driving signal for the current source circuit, the signal going to a high level just before the first driving signal goes to a high level and which goes down to a low level just after the first driving signal goes down to a low level, the current source circuit driving signal being provided to drive a transistor in the current source circuit. The period of time during which the first and second driving signals appear is set to be shorter than the conduction period of the current source circuit. In this construction, the emitter coupled transistors for driving the LED switch the current when the current source circuit is conductive, thereby realizing high speed operation. Further, the conduction period of the current source circuit varies with the input signal and, therefore, hardly any current is allowed to flow through the circuit when an input signal is absent. The invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a diagram of a known LED driver circuit; Figure 2 is a block diagram of an LED driver circuit embodying the present invention; Figure 3 shows waveforms of signals appearing at various points of the circuit shown in Figure 2; and Figure 4 is a circuit diagram showing details of an embodiment of the present invention. Referring to Figure 2, an LED driver circuit embodying the present invention is shown and includes emitter coupled transistors 3 and 4. These transistors 3 and 4 and a transistor 5 in a current source circuit are the same as those of the prior art driver circuit shown in Figure 1. In accordance with the illustrative embodiment, an input signal to the driver circuit is applied to an input terminal 8. The driver circuit further comprises a first delay circuit 9 connected between the input terminal 8 and the bases of the transistors 3 and 4, a second delay circuit 10 which further delays an output of the first delay circuit and couples to an OR gate 11, which is in turn connected to the base of the transistor 5. The operation of the driver circuit shown in Figure 2 will be described with reference also made to Figure 3, which is a timing chart representative of the signal states on the lines A-E of Figure 2. The signal lines labeled A-E correspond respectively to the signals A-E of Figure 3. The first delay circuit 9 delays an input signal A applied to the input terminal 8 by a time t 9 so as to develop a first delayed signal B and a signal C which is opposite in phase to the signal B. The delayed signal B is routed to the base of the transistor 3 and the inverted delayed signal C to the base of the transistor 4. The delayed signal B is also applied to the second delay circuit 10 to be thereby delayed by a time t 10 the circuit 10 producing a delayed signal D. The delayed signals B and D and the input signal A are delivered to the OR circuit 11 which then produces an OR signal E. The OR signal E has been delayed by a time t E by the OR circuit 11. The transistor 5 in the current source circuit is driven by the OR signal E, the transistor 3 by the delayed signal B, and the transistor 4 by the inverted delay signal C. As a result, the source current is allowed to flow through the driver circuit over a period of time between a positive going edge and just after a negative going edge of the input signal A, that is, only when the signal E is kept at a high level. After the signal E reaches a high level and when a positive-going transition of the first delayed signal B appears, the transistors 3 and 4 switch the current and, when the first delay signal B has become high the transistor 3 is turned on to activate the LED 6. Meanwhile, while the signal E maintains the high level and on a negative-going transition of the signal B, another current switching of the transistors 3 and 4 takes place. Such a current switching promotes smooth charging and discharging for the junction capacitance of the LED 6 and transistors 3 and 4, thereby ensuring high-speed operation. Referring to Figure 4, there is shown a circuit in accordance with the present invention which is constructed to drive an LED at a high speed by using a 100 Mb/s NRZ (non-return to zero) signal as the input signal A. As shown, the circuit includes a first delay circuit 9 for generating a first delayed signal B and an inverted version C of the signal B, by delaying the input signal A. A second delay circuit 10, which comprises an OR gate, serves to delay the first delayed signal B. An OR circuit 11 includes an ECL (OR/NOR output) gate 11' and is supplied with the input signal A, the first delayed signal B, and a signal D delayed by an OR gate 10. A level shift circuit 50 is supplied with the first delayed signal B and the inverted delayed signal C to shift the DC level. Further included in the circuit of Figure 4 is a driver circuit 60 which is the same as the driver circuit of Figure 1. The circuit of Figure 4 is now described in relation with the timing chart of Figure 3. The first delay circuit 9 comprises an OR gate 21 and a high-speed ECL (OR/NOR) gate 22 and functions to delay the input signal A by a time t 9 (ns). The delayed signal is routed through resistors R1 and R2 to the bases of transistors Q1 and Q2 of the level shift circuit 50. Resistors R5 and R6 respectively are connected to the bases of the transistors Q1 and Q2, while resistors R7 and R8 respectively are connected to the emitters of the transistors Q1 and Q2, thereby forming an emitter-follower circuit. The level shift circuit 50 is employed for shifting the DC output level at the gate 22 to the base bias level of the transistors 3 and 4, and provides high-speed level shifts by means of the emitter-follower circuit. The OR gate 10 delays the first delayed signal B by a time t 10 and delivers the resulting signal to the ECL gate 11'. Resistors R3 and R4, a Zener diode ZD, a capacitor C2 and a resistor 15 which are connected to the input side of the gate 11' are adapted to set the input level of the gate 11'. Although the gate 11' serves the function of a NOR circuit, the high level of its output is the source voltage, and diodes D1-D5 connected in series are employed to level it down to thereby adjust the voltage level applied to the base of a transistor Q3. A signal E appearing at the collector of the transistor Q3 is delivered to the base of a transistor 5. The signal E is delayed by the delay time t E assigned to the OR circuit 11 relative to the input signal. Therefore, since the inputs of the OR circuit 11 are the signals A, B and D, the signal E rises a time t E after a rise of the input signal A, whereby the transistor 5 is turned on. After the signal E reaches a high level and when a positive-going transition of the signal B appears, the transistors 3 and 4 switch the current. When the signal B becomes high, the transistor 3 is rendered conductive to energize the LED 6. Meanwhile, while the signal E maintains the high level and after a negative-going transition of the signal B appears, the current switching of the transistors 3 and 4 takes place again. Since the current is switched during the conduction of the transistor 5 as described above, charging and discharging for the junction capacitance of the LED 6 occurs smoothly to enable high-speed operation. While setting of the delay times t 9 and t 10 has been implemented by OR gates in the above-described embodiment, they may be replaced with other logical gates or even by coaxial cables. Since Coaxial cables have a delay time of 5 ns/m, they may be used in a driver circuit with a 100 Mb/s or higher operating speed if their length is adequately adjusted. Further, for a driver circuit with an operating speed lower than several tens of Mb/s, the delay may be implemented by a commercially available delay line. In summary, it will be seen that the illustrated LED driver circuit embodying the invention turns on and off a current supply circuit in response to on and off of an input signal and, thereby, remarkably cuts down current consumption during a period in which the input signal is absent, while producing an optical output waveform identical with the waveform of the input signal. In addition, since the current source circuit is activated in advance during the current switching of the emitter coupled transistors, charging and discharging for the junction capacitance of an LED and a drive transistor associated therewith is effected smoothly even at the time of high speed modulation. This provides a high operating speed and, thereby, furnishes a useful LED driver circuit.

Claims: A light emitting diode driver circuit including a differential amplifier (3, 4, 5) having emitter coupled transistors (3, 4), a light emitting diode (6) connected to a collector of one (3) of the emitter coupled transistors, and a current source circuit (5, R 12' R 13' R 14 ) connected to the common emitters of the emitter coupled transistors (3, 4), characterised by: a first circuit (9) responsive to an input signal (A) for generating first and second driving signals (B, C) of opposite phase, the first and second driving signals (B, C) being coupled respectively to the emitter coupled transistor (3) whose collector is coupled to the light emitting diode (6) and to the other transistor (4), and by a second circuit (10,11) responsive to the input signal (A) for generating a driving signal (E) for the current source circuit (5, R 12 , R 13 , R 14 ), the signal (E) going to a high level just before the first driving signal (B) goes to a high level and which goes down to a low level just after the first driving signal (B) goes down to a low level, the current source circuit driving signal (E) being provided to drive a transistor (5) in the current source circuit (5, R 12 , R 13 , R 14 ). A light emitting diode driver circuit as claimed in claim 1, characterised in that the emitter coupled transistors (3, 4) switch the current when the current source circuit (5, R 12 , R 13 , R 14 ) is conductive. A light emitting diode driver circuit as claimed in claim 1 or 2, characterised in that the first circuit comprises a first delay circuit (9) for generating the first driving signal (B) and second driving signal (C) by delaying the input signal (A); and in that the second circuit comprises a second delay circuit (10) for delaying the first driving signal (B), and an OR circuit (11) having inputs receiving the input signal (A), the first driving signal (B) and an output (D) of the second delay circuit (10) and generating the driving signal (E). A light emitting diode driver circuit as claimed in claim 3, characterised in that each of the first and second delay circuits (9, 10) comprises a logic gate circuit. A light emitting diode driver circuit as claimed in claim 3 or 4, characterised in that each of the first and second delay circuits (9, 10) comprises a coaxial cable. A light emitting diode driver circuit as claimed in claim 3, 4 or 5, characterised in that each of the first and second delay circuits (9,10) comprises a delay line.

Inventors: UDA, YOSHIHIRO C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1984
Main classification: H03K5
IPC codes: H04B10, H03K17, H03K5