MULTIPLE INPUT SIGNAL ANALOG-DIGITAL CONVERTER CIRCUITRY

Abstract: Multiple input signal analog-digital converter circuitry for digitalizing, by means of an A/D converter (40), an output signal (S o ) from a multiplexer (30) which successively delivers a set of input signals applied thereto in parallel has two sample/hold circuits (33,35) which receive the output signal from the multiplexer for repeatedly sampling and holding the signal, and a changeover switch (38) for keeping one of the sample/hold circuits on hold while the other sample/hold circuit samples the output signal from said multiplexer. While one of the sample/hold circuits is holding a signal, the other sample/hold circuit is sampling another signal so that the A/D conversion time of the set of input signals is shortened as compared with prior art circuitry.

Description: MULTIPLE INPUT SIGNAL ANALOG-DIGITAL CONVERTER CIRCUITRY This invention relates to multiple input signal analog-digital converter circuitry for converting a number of analog signals into digital signals. Multiple input signal analog-digital converter circuitry finds use in devices such as a combinatorial weighing apparatus. A combinatorial weighing apparatus operates by supplying a plurality of weighing machines with articles to be weighed, computing combinations based on weight values obtained from the weighing machines, selecting a combination giving a total combined weight value equal or closest to a target weight, and discharging the articles solely from those weighing machines corresponding to the selected combination, thereby providing a batch of weighed articles of a weight equal or closest to the target weight. Such a combinatorial weighing apparatus will now be described in brief with reference to Fig.l of the accompanying drawings. The apparatus includes load cells 10 10-2.. 10-n for sensing the weight of articles introduced into the respective weighing hoppers belonging to n weighing machines. Each load cell produces a weight signal, namely an analog value indicative of the weight sensed thereby. The weight signals from these load cells are 10 ... 10-n are applied as multiple input signals S1, S2 .. Sn to a multiplexer 13 via amplifier circuits 11¯1, 11¯2 ... 11-n and filters 12 1 12 , ... 12-n' respectively. The multiplexer 13, which is composed of analog switches or the like, responds to a selection signal Scl from a computation controller, described below, by selectively applying the weight signals S1, S2 ... Sn as a weight data signal SO to a buffer circuit 14 sequentially in a time series. The buffer circuit 14 delivers the weight data signal SO received from the multiplexer 13 to a sample/hold circuit 15 upon subjecting the signal to an impedence conversion. The sample/hold circuit 15 repeatedly samples and holds the weight data signal So subjected to the impedence conversion by the buffer circuit 14 and delivers the weight data signal to a buffer circuit 17. The latter subjects the signal to an impedence conversion, producing an analog weight data signal which is delivered to an analog-digital converter (A/D converter) 18. The latter digitalizes the analog weight data signal Sp to produce a digital output Sd which is applied to a computation controller 20. The latter is composed of a microcomputer and includes a processor 21 for performing combinatorial processing, a read-only memory (ROM) 22 storing a processing program for combinatorial processing, and a random-access memory (RAM) 23 for storing the weight data as well as the results of processing performed by the processor 21. The computation controller 20 computes combinations on the basis of the weight data, selects a combination giving a total combined weight value equal or closest to a target weight, and delivers a drive signal to drive units 2 25 2 25 25 n of respective weighing hoppers belonging to those weighing machines which correspond to the selected combination. Thus, the multiple input signal A/D converter circuitry converts, into a digital value, the analog weight data signal So delivered successively in a time series by the multiplexer 13. As shown in Fig. 2, the A/D converter circuit successively samples and holds the weight data S1, S2, 53 ... 5n by means of the single sample/hold circuit 15 before delivering the data to the A/D converter 18. Unless the sample/hold circuit 15 operates at a sufficiently long sampling time, a capacitor 16 (Fig. 1) for raising sampling precision cannot be charged. Accordingly, the A/D converter 18 is inoperative during sampling time, which is on the order of about 10 psec. This means that the conventional multiple input signal A/D converter circuitry cannot make effective use of the A/D converter 18 despite the fact that the latter is capable of performing a conversion at high-speed. It is accordingly desirable to provide multiple input signal high-speed analog-digital converter circuitry which is capable of subjecting a number of input signals to an A/D conversion at high speed by making effective use of an A/D converter having ± high-speed processing capability. According to an eIx,dment of the present invention there is provided multiple input signal analog-digital converter circuitry having a multiplexer for successively delivering a number of input signals applied thereto, two sample/hold circuits which receive an output signal from the multiplexer for repeatedly sampling and holding the signal, a changeover switch for keeping one of the sample/hold circuits on hold while the other sample/hold circuit samples the output signal of the multiplexer, and an analog-digital converter which receives signals from the two sample/hold circuits for converting the signals into digital values which are then delivered as output signals. With such multiple input signal analog-digital converter circuitry embodying the invention, while one of the sample/hold circuits is holding an input signal, the other sampleXhold circuit is sampling another input signal. Accordingly, the A/D conversion time of the multiplicity of input signals is capable of being shortened by the sampling time of the sample/hold circuits, so that effective use can be made of the A/D converter having the high-speed processing capability. For a better understanding of the invention, and to show how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating a combinatorial weighing apparatus having multiple input signal analog-digital converter circuitry according to the prior art as described above; Fig.2 is a timing chart indicating the operation of a sample/hold circuit of the multiple input signal analog-digital converter circuitry of Fig.l; Fig.3 is a circuit diagram of multiple input signal high-speed analog-digital converter circuitry embodying the present invention; and Fig. 4 is a timing chart indicating the operation of sample/hold circuits in the arrangement of Fig.3. In Fig. 3, weight data from load cells 10 . 10an of a plurality of weighing machines in a combinatorial weighing apparatus as described above with reference to Fig. 1 are applied in parallel as multiple input signals 611, S12 ... Sln multiplexer 30. The multiplexer 30 selectively applies the weight data as a weight data signal So to a buffer circuit 31 sequentially in a time series. The buffer circuit 31 delivers the weight data signal 'So received from the muliplexer 30 to an amplifier/level-shift circuit 32, subjecting the signal to an impedence conversion. The amplifier/level-shift circuit 32 delivers the weight data signal from the buffer circuit 31 after adjusting the mu-factor and zero level of the signal. Numerals 33, 35 denote first and second sample/hold circuits, respectively, both of which receive the output signal SO of the multiplexer 30 via the buffer circuit 31 and amplifier/level-shift circuit 32 for repeating a sample-and-hold action. The first and second sample/hold circuits 33, 35 are equipped with capacitors 34, 36, respectively, for being charged when the weight data signal is sampled and for holding the charge when the signal is held. A changeover switch 38 permits only one of the first and second sample/hold circuits 33, 35 to deliver an output at any time in such a manner that one of the sample/hold circuits is made to perform a holding operation while the other performs a sampling operation. The output of the changeover switch 38, namely a weight data signal from one of the sample/hold circuits 33, 35, is applied to a buffer circuit 39 which delivers the signal as a signal Sp following an impedence conversion. An A/D converter 40 digitalizes the analog weight data signal Sp to produce a digital output signal Sd which is applied to, say, the computation controller 20 of Fig. 1. The computation controller performs a digital computation based on the weight data signals Sll, S12 ... Sln received from the respective weighing machines to decide a combination closest to a target weight value. To perform the foregoing operation, the computation controller produces a control signal 5c and applies the signal synchronously to the multiplexer 30 as a selection signal Scl, to the first and second sample/hold circuits 33, 35 and changeover switch 38 as a changeover command signal Sc2' and to the A/D converter 40 as a control signal Sc3 In response to the selection signal Scl applied to the multiplexer 30, signals from among the multiple input signals S11' S12 ... Sln are selected for application to the sample/hold circuits 33, 35, which also receive the changeover command signal Sic2, with the second sample/hold circuit 35 receiving the signal via an inverter 37. Accordingly, as shown in Fig. 4, while one input signal is being held by the first sample/hold circuit 33 or second sample/hold circuit 35, the following input signal is being sampled by the other sample/hold circuit 35 or 33. Further, in response to the control signal Sc3 applied to the A/D converter 40, the A/D conversion ends. When this occurs, the holding of one input signal ends and the holding of the following input signal begins. In other words, A/D conversion now starts and, at.the same time, so does sampling of the next input signal. This operation is performed repeatedly so that digital computations are carried out while the A/D conversion continues at high speed without a pause. It goes without saying that the same method can be employed when an item of weight data from a single weighing machine is sampled a plurality of times followed by switching the multiplexer to sample weight data from the next weighing machine. In the foregoing it will be appreciated that the multiplexer output signal S as adjusted and applied 0 to the sample/hold circuitry may be regarded as a series of individual input signals derived respectively from the original inputs S11, S,2 Sln to the multiplexer 30. Though an embodiment has been described wherein the present invention is used in a combinatorial weighing apparatus, the invention is not limited to such an embodiment but can be modified in various ways within the scope of the claims.

Claims: CLAIMS: 1. Multiple input signal analog-digital converter circuitry comprises: a multiplexer for successively delivering as an output signal a number of input signals applied thereto; two sample/hold circuits which receive the output signal from said multiplexer for repeatedly sampling and holding the signal; a changeover switch for keeping one of the sample/hold circuits on hold while the other sample/hold circuit samples the output signal from said multiplexer; and an analog-digital converter which receives signals from said two sample/hold circuits for converting the signals into digital values which are then delivered as output signals. 2. Sequential analog-to-digital converter circuitry, for digitalizing in sequence a series of input signals (SOl ) with the aid of a sample/hold stage for sampling such signals and holding them during respective digitalization thereof by an analog-todigital converter (40) of the circuitry, characterised in that the circuitry includes first and second such sample/hold stages (33,35) and means (37,38) for rendering those stages operative alternately, for respective alternate signals of the said series, so that when the first sample/hold stage has completed its sampling of one signal of the said series the second sample/hold stage commences sampling the next signal of the series.

Inventors: NAITO, KAZUFUMI
Applicants: KABUSHIKI KAISHA ISHIDA KOKI SEISAKUSHO
Application year: 1984
Main classification: H03M1
IPC codes: H03M1