APPARATUS FOR EXPANDING ILLUMINATED PICTURE ELEMENTS IN CRT DISPLAYS

Abstract: An apparatus for expanding illuminated picture ele­ ments in a CRT display (91) utilises an image memory (93) wherein video bit signals are written into only addresses whose binary x coordinate has a predetermined first digit, and whose binary y coordinate has a predetermined first digit.Signals in addresses (92) corresponding to picutre ele­ ments P I , J ; P I-1,J ; P I-J,J+1 ; and P I,J+1 are read from the image memory, and a Boolean OR sum signal (94) is generated therefrom which is converted to an analogue signal (95). The picture element P I,J is illuminated in response to an analogue signal representing the Boolean OR sum signal 1.

Description: The present invention relates generally to CRT displays, and more particularly to the expansion of illuminated picture elements therein in order to increase writing speed and eliminate flicker resulting from line pair destruction by higher priority symbols. Lines written on a CRT display comprise discrete picture elements. Each picture element is either illuminated or not. A line is written, picture element by picture element, from left to right. The entire set of lines written on a CRT display, denoted a frame, comprises two fields. The first field comprises the odd numbered lines which are written from the top to the bottom of the CRT display. The second field comprises the even numbered lines which are also written, after the entire first field has been written, from the top to the bottom of the CRT display. Each of the two fields may be written in one-sixtieth of a second, providing a frame in one-thirtieth of a second. The picture information written on the CRT display is read from an image memory. The image memory comprises a number of addresses, each of which contains a "1" or a "0" bit. A one-to-one correspondence exists between the' addresses in the image memory and the picture elements in the CRT display. A "1" read from an address in the image memory produces illumination of the corresponding picture element in the CRT display. A "0" read from an address in the image memory engenders no illumination of the corresponding picture element in the CRT display. When a field is written in a relatively slow time, such as one-thirtieth of a second, illuminated picture elements on a given line create a flicker which is disconcerting to a viewer. Flickering, it has been found, can be eliminated by duplicating the illuminated picture elements on an adjacent line. For example, referring to Figure 1 of the accompanying drawings, a line 12 written in one-sixtieth of a second on a CRT display comprises illuminated picture elements 13, 14 and 15. A viewer perceives the illuminated picture elements 13, 14 and 15 to flicker. The phenomenon is remedied by duplicating the illuminated picture elements 13, 14, and 15 with, respectively, illuminated picture elements 16, 17, and 18 on an adjacent line 19. When the line 12 is written in one field and thereafter the adjacent replica line 19 is written in another field, the viewer does not experience flickering of the picture elements 13, 14, and 15. Moving symbols in CRT displays possess various priority levels. Such symbols are surrounded by a mask, an invisible rectangle, which erases symbols of lower priority. In this fashion, higher priority symbols are precluded from merging with lower priority ones. However, the obliteration of a portion of a lower priority symbol by a higher priority one can produce flickering, by destroying duplicated illuminated picture elements. Referring to Figure 2 of the accompanying drawings, a lower priority symbol 20 comprises illuminated picture elements 21 and 22 on a line 23 in one field, and illuminated picture elements 24 and 25 on an adjacent line 26 in the other field. As indicated above, the illuminated picture elements 24 and 25 duplicate, respectively, the illuminated picture elements 21 and 22 to prevent flickering. A higher priority symbol 28 comprises an illuminated picture element 29 on a line 30 in one field, and a duplicate illuminated picture element 31 on an adjacent line 32, in the other field. A mask 34 extends three lines above, and surrounds the higher priority symbol 28. Referring now to Figure 3, the higher priority symbol 28 may move upwards such that the mask 34 erases the duplicate illuminated picture elements 24 and 25. With the elimination of the duplicate illuminated picture elements 24 and 25, the remaining illuminated picture elements 21 and 22 flicker. Thus, there is a need for apparatus, utilised with a CRT display wherein lines are written relatively slowly, for preventing disconcerting flickering on the display resulting from the erasure of duplicate illuminated picture elements by higher priority symbols. The present invention is defined in the appended claims and a preferred embodiment, the address reading means comprises a first shift register, having two compartments, for loading in parallel with video bit signals from addresses corresponding to picture elements P I,J and P I-1,J ; and comprises a second shift register, having two compartments, for loading in parallel with video bit signals from addresses corresponding to picture elements P I,J+1 and P I-1,J+1 . A first delay, preferably comprising a shift register, is coupled to the first shift register. A second delay, preferably comprising a D type flip-flop, is coupled to the first delay; and a third delay, preferably comprising a D type flip-flop, is coupled to the second shift register. By expanding illuminated picture elements, the present invention increases writing speed and eliminates disconcerting flickering. The invention will now be described in greater detail, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a schematic diagram illustrating duplication of illuminated picture elements in CRT displays in order to eliminate flickering (as already discussed), Figure 2 is a schematic diagram of a higher priority symbol surrounded by a black mask, and a lower priority symbol in a CRT display (as already discussed), Figure 3 is a schematic diagram illustrating the obliteration of duplicate illuminated picture elements of the lower priority symbol by the black mask of the higher priority symbol (as already discussed), Figure 4 is a schematic diagram of a higher priority symbol surrounded by a black mask, and a lower priority symbol written on a CRT display in accordance with the present invention, Figure 5 is a schematic diagram illustrating expansion of an arbitrary illuminated picture element in accordance with the present invention, Figure 6 is a schematic diagram of the picture elements whose memory address contents determine the illumination status of the picture element P I,J , Figure 7 is a block diagram of a preferred embodiment of the present invention, and Figure 8 is a block diagram of an address reader utilised in the preferred embodiment of the present invention. Identical numerals in different figures of drawings represent similar elements. The present invention is concerned with apparatus for expanding illuminated picture elements in a CRT display wherein lines are written relatively slowly. Such expansion increases writing speed and prevents flickering resulting from the erasure of interlaced illuminated picture elements by the mask of a higher priority symbol. An image memory contains a number of addresses which are designated by x and y coordinates. The coordinates are in binary notation. In the present invention, video bit signals for a video character are written in addresses in the image memory such that the picture elements on a CRT display corresponding to these addresses are separated on a given line by one picture elements, and occupy lines which are separated by one picture element. This is achieved by writing video bit signals into only addresses whose x coordinate possesses a fixed first binary digit, and whose y coordinate possesses a fixed first binary digit. For example, to generate spaces between picture elements within a line, and spaces between lines on the CRT display, the corresponding addresses utilised in the image memory may be chosen to possess an x coordinate whose first digit is 0, and to possess a y coordinate whose first digit is 1. Any video character may possess any x , y combination of 1 and 0. Assuming that the memory comprises an eight by eight matrix of addresses, the x coordinate available to a given character of the addresses varies from 000 to 111, and the y coordinate available to a given character varies from 000 to 111. Choosing only those addresses having an x coordinate whose first binary digit is 0, and having y coordinate whose first binary digit is 1 results in addresses available to a given character: (000,001)=(0,1)(010,001)=(2,1)(100,001)=(4,1)(110,001)=(6,1) (000,011)=(0,3)(010,011)=(2,3)(100,011)=(4,3)(110,011)=(6,3) (000,101)=(0,5)(010,101)=(2,5)(100,101)=(4,5)(110,101)=(6,5) (000,111)=(0,7)(010,111)=(2,7)(100,111)=(4,7)(110,111)=(6,7) In this fashion, every other address may be selected in a given row and every other row maybe selected. Video bit signals for the given character may be written into only these addresses in the image memory. By holding the first binary digit of both the x and y coordinates of the addresses fixed, such an alternating pattern of addresses may be generated. The invention entails writing picture information into such selected addresses in the image memory, and expanding the written information so that no gaps appear on the CRT. As indicated in the description of the prior art, to prevent flickering, an illuminated picture element must be duplicated below on the next line of the CRT display. When picture information is written into the addresses in the image memory in the alternating fashion described above, a duplicate illuminated picture element would appear on the CRT display one line below the original illuminated picture element. To prevent flickering resulting from an erasure, by the mask of a higher priority symbol, each illuminated picture element on the CRT display is duplicated on the vacant line immediately therebelow. In this fashion, each illuminated picture element always possesses at least one flicker-eliminating duplicate. For example, referring to Figure 4, a higher priority symbol 40, comprising a "written into memory" and illuminated picture element 41 and duplicate illuminated picture elements 42, 43 and 44, is surrounded by a black mask 45. The black mask 45 comprises picture elements 46a through 46f on a line 46, picture elements 47a through 47f on a line 47, picture elements 48a through 48f on a line 48, picture elements 49a through 49d on a line 49, picture elements 50a through 50d on a line 50, picture elements 51a through 51f on a line 51, and picture elements 52a through 52e on a line 52. A lower priority symbol 53 comprises written into memory and illuminated picture element 54 and its respective duplicates 55, 56 and 57 generated by the invention. Symbols on the CRT display, comprising picture elements corresponding to the selected addresses in the image memory, can occupy any of the interlacing lines comprising the picture. Accordingly, vertical movement of symbols entails one line at a time but is not restricted to such. Thus, referring to Figure 5, if the higher priority symbol 40 moves upward, its second motion results in the picture elements 46e and 46d of the black mask 45 intersecting, respectively, the duplicate illuminated picture elements 56 and 57 in Figure 4. Were it not for pel expansion about the element 54, the picture elements 56 and 57 would produce flickering. This flickering is eliminated by the duplicate illuminated picture elements 56 and 57. Referring again to Figure 4, the illuminated picture element 54 is further expanded into adjacent illuminated picture elements 55 and 57. Such horizontal expansions do not affect flickering, but serve to double the speed of picture generation. Vertical expansions using pels 56 and 57 serve to avoid flicker and to double the writing speed for a net speed increase of 2 horizontally by 2 vertically equals 4 overall. Accordingly, referring to Figure 5, to prevent flickering each illuminated picture element 80 is expanded below in an illuminated picture element 81, and to double writing speed, the illuminated picture element 80 is expanded to the right in an illuminated picture element 82, and expanded below and to the right in an illuminated picture element 83. This is accomplished by considering each picture element as the CRT display beam scans from left to right and from top to bottom. Denoting the current picture element with which the CRT beam generator is aligned as P I,J , the adjacent picture elements P I-1 J, P I-1,J+1' and P I,J+1 are considered. Referring to Figure 6, if there is a video bit signal of 1 in one or more of the four addresses in the image memory corresponding to these four picture elements, then the picture element P I,J' with which the CRT beam generator is currently aligned, is illuminated by the beam. This procedure effects the expansion of each illuminated picture element in the desired fashion depicted in Figure 5. This follows since the procedure implements the illuminated picture element expansion from the perspective of the picture element with which the CRT beam generator is currently aligned. Referring to Figures 5 and 6, if the CRT beam generator is currently aligned with the picture element 80 whose image memory addressed location contains a "1", then the picture element 80 is desired to be illuminated. This situation corresponds to a "1" being in the image memory addressed location of the currently aligned picture element P 1'J. Accordingly, P I,J is illuminated by the CRT beam. If the CRT beam generator is currently aligned with the picture element 82, then the picture element 82 is desired to be illuminated since it is an expansion of the illuminated picture element 80 to its left. This situation corresponds to a "1" being in the image memory address of the picture element P I,J which is to the left of the currently aligned picture element P I,J . Accordingly, P I,J is illuminated. If the CRT beam generator is currently aligned with the picture element 81, then the picture element 81 is desired to be illuminated since it is an expansion of the illuminated picture element 80 above it. This situation corresponds to a "1" being in the image memory address of the picture element P I,J+1 which is above the currently aligned picture element P I,J . P I,J is illuminated accordingly. If the CRT beam gnerator is currently aligned with the picture element 83, then the picture element 83 is desired to be illuminated since it is an expansion of the illuminated picture element 80 which is above and to the left of it. This situation corresponds to a "1" being in the image memory address of the picture element PI-1,J+1 which is above and to the left of the currently aligned picture element P I,J . P I,J is illuminated accordingly. In this fashion, by illuminating the picture element P I,J , with which the CRT beam generator is currently aligned, when any of the image memory addresses of the picture elements P I,J ; P I-1,J ; P I-1,J+1 ; P I,J+1 contains a 1, an illuminated picture element is expanded below to the right, and below and to the right, as required to prevent flickering and increase writing speed. This expansion procedure can be described mathematically. The currently aligned picture element P I,J is illuminated when the Boolean "OR" sum of the video bit signals in the image memory addresses of the picture elements P I,J ; P I-1, J ; P I-1,J+1 and P I,J+1 is 1. When the Boolean "OR" sum is zero the picture element P I,J , is unilluminated. Denoting the illumination status of the currently aligned picture element P I,J by IS, gives:- where B X,Y is the video bit signal in the image memory address of the picture element P X,Y . Referring to Figure 7, the above expansion procedure can be implemented as follows. A coordinator 90, coupled to a CRT display 91, generates, coordinates and aligns the beam generator of the CRT display with picture elements corresponding to the generated coordinates. The coordinator 90 is also coupled to an address reader 92 which in turn is coupled to an image memory 93. The address reader 92, in response to a signal from the coordinator 90 representing the coordinate of the picture element with which the beam generator is currently aligned, reads from the image memory 93 the video bit signals in the four addresses associated with the currently aligned picture element. That is, denoting as before, the currently aligned picture element as P I,J ' the video bit signals B I,J ; B I-1,J ; B I-1,J+1 ; and B I,J+1 in the addresses of the image memory 93 corresponding, respectively, to the picture elements P I,J ; P I-1,J ; P I-1,J+1 ; and P I,J+1 are read from the image memory 93 by the address reader 92. These four video bit signals are conveyed by the address reader 92 to an OR gate 94. The OR gate 94 generates the Boolean OR sum:- of the four video bit signals. A digital-to-analogue converter 95 receives the digital sum signal from the OR gate 94 and converts it to an analogue signal. The beam generator of the CRT display receives the analogue signal produced by the digital-to-analogue converter 95. In response to an analogue signal corresponding to a digitial signal of ONE, a beam is generated which illuminates the picture element P I,J . An analogue signal corresponding to a ZERO digital signal engenders no illumination of the picture element P I,J . Referring to Figure 8, in a preferred embodiment of the invention, the address reader 92 comprises shift registers and delays. A shift register 100 is loaded in parallel, with the video bit signal B I-1,J received by a compartment 101 and the video bit signal B I,J received by a compartment 102. After a delay, a shift register 104 is then loaded in parallel, with the video bit signal B I-1,J+1 received by a compartment 105 and the video bit signal B I,J+1 received by a compartment 106. The shift register 100 serially outputs the contents of the compartments 101 and 102 and the shift register 104 serially outputs the contents of the compartments 105 and 106. The outputs of the shift register 100 are received by a delay 108 which synchronises the outputs of the shift register 100 with those of the shift register 104. That is, the first output of the delay 108, B I-1,J , coincides with the first output of the shift register 104, B I-1,J+1 ; and, the second output of the delay 108, B I,J , coincides with the second output of the shift register 104, B I,J+1 . Video bit signals having the same x coordinate are thereby outputed at the same time. The delay 108 preferably comprises a shift register. The first output of the delay 108, B I-1,J , is conveyed to a delay 110. The outputing of B I-1,J , from the delay 110 coincides with the outputing of B I,J from the delay 108. Similarly, the first output of the shift register 104, B I-1,J+1 , is conveyed to a delay 111. The outputing of B I-1 , from the delay 111 coincides with the outputing of B I,J+1 from the shift register 104. In this fashion, the 4 video bit signals are available for conveyance at the same time to the OR gate 94 of Figure 7. Each of the delays 110 and 111 preferably comprises a standard D-type flip-flop. If desired, the address reader may be altered to accommodate more than two video bit signals from a row of addresses in the image memory. The number of compartments in the shift registers 100 and 104 are merely increased to receive the additional video bit signals. The shift register comprising the delay 108 is similarly expanded, and the delays 110 and 111 are each coupled in series with additional similar delays, each also preferably comprising a D-type flip-flop. The various components described in Figure 7 are well-known in the art or readily contrived by one of ordinary skill therein. The image memory 93, the OR gate 94, the digital-to-analogue converter 95, the CRT display 91 and the coordinator 90 are conventional, well-known apparatus. One of ordinary skill in the art could readily design alternative versions of the address reader 92 described above, which would be suitable for purposes of the present invention.

Claims: Apparatus for expanding illuminated picture elements in video display means, comprising: Means (91) for displaying video data comprising a matrix of picture elements, denoted P X,Y , and means for illuminating the picture elements in response to applied signals; means (90), coupled to the video display means, for generating coordinates, for providing signals representative of the coordinates, and for synchronising the illuminating means with the coordinates; means (93) for storing video bit signals, comprising addresses corresponding to the picture elements, each of the addresses being identified by a x and a y binary coordinate, the video bit signals being stored only in the addresses whose x coordinate has a predetermined first binary digit, and whose y coordinate has a predetermined first binary digit; means (92), responsive to a signal from the coordinate generating means representing a generated coordinate I,J , for reading the addresses corresponding to picture elements P I,J , P I-1,J , P I-1,J+1 , P I,J+1 ; means (94) coupled to the address reading means, for generating a Boolean OR sum digital signal from the video bit signals read from the addresses corresponding to picture elements P I,J ; P I-1,J ; P I-1,J+1 ; and P I,J+1 ; and means (95) coupled to the Boolean OR sum digital signal generating means and said video displaying means for generating, in response to a ZERO digital signal, a first analogue signal, and for generating, in response to a ONE digital signal, a second analogue signal, the picture element P I,J being illuminated by the illuminating means of the video display means in response to the second analogue signal, and the picture element P I,J being unilluminated by the illuminating means in response to the first analogue signal. Apparatus according to claim 1, characterised in that the storing means comprises an image memory (93). Apparatus according to claim 1 or 2, characterised in that the video display means comprises a CRT display (91). Apparatus according to any of the preceding claims, characterised in that the address reading means comprises a first shift register (100) comprising the compartments (101, 102); a second shift register (104) comprising two compartments (105, 106); a first delay (108) coupled to the first shift register (100) ; a second delay (110) coupled to the first delay; and a third delay (111) coupled to the second shift register. Apparatus according to claim 4, characterised in that the first delay comprises a shift register (108). Apparatus according to claim 4 or 5 characterised in that the second delay comprises a D-type flip-flop (110) and the third delay comprises a D type flip-flop (111). Apparatus according to any of the preceding claims, characterised in that the Boolean OR sum digital signal, generating means comprises a Boolean OR gate (94) having four input terminals. Apparatus according to any of the preceding claims, characterised in that the converting means comprises a digital-to-analogue converter (95).

Inventors: HANCOCK, WILLIAM RAY, JOHNSON, MICHAEL JOHN
Applicants: HONEYWELL INC.
Application year: 1984
Main classification: G09G1
IPC codes: G09G5, G09G1