SCHOTTKY GATE FIELD EFFECT TRANSISTOR AND METHOD FOR PRODUCING IT

Abstract: A MESFET comprises an active layer on a semi-insulating semiconductor substrate 2 which is divided into a first portion 12 which has a shallow thickness to provide a pinch-off voltage and is formed directly under a gate electrode 3 and second portions 11, 13 which are doped with a higher dose of impurity per unit area than the first portion and formed on opposite sides of it. The interfaces between the first portion 12 and the second portions 11, 13 are spaced from the gate electrode 3 by substantially the thickness of the first portion 12 thereby to provide an optimum distance between each of the second portions 11, 13 and the gate electrode 3. Such a MESFET has a small gate-source capacity, a small gate-drain capacity, a small gate-source resistance, a small gate-drain resistance, and a large transconductance gm, thereby achieving an ultra-high-frequency operation, an ultra-high-speed operation, and a low noise characteristic.

Description: SCHOTTKY GATE FIELD EFFECT TRANSISTOR AND METHOD FOR PRODUCING IT A Schottky gate field effect transistor (hereinafter called MESFET) is widely used as an amplifier or oscillator device particularly in the ultra-high -frequency band. Further, it is known that MESFET's are ideal basic components of integrated circuits for ultra-high-speed operation. A Schottky gate field effect transistor comprises a semi-insulating semiconductor substrate, an active layer formed on the semiconductor substrate, and a source electrode, a Schottky gate electrode, and a drain electrode all formed on the active layer. Such conventional MESFET's have the disadvantage that a sufficiently large transconductance gm is not obtained because of the large resistance existing between the gate and source or gate and drain. The noise characteristic of such a device is also lowered by the large series resistance that exists between the gate and source. These problems are exacerbated in the normally OFF type of MESFET in which the pinch-off voltage tends to zero. To overcome these problems it has been proposed to etch a part of the active layer to produce a shallower region and then form the gate electrode on this shallower region. However it is difficult to produce repeatable and consistent devices by this technique. According to a first aspect of this invention in a Schottky gate field effect transistor the active layer is divided into a first portion directly under the gate electrode and having a thickness selected to provide the required pinch-off voltage, and second portions located adjacent and on opposite sides of the first portion; the second portions of the active layer being doped with a larger quantity of impurity per unit area than the first portion of the active layer; and, the interfaces between the first portion of the active layer and the adjacent sides of each of the second portions of the active layer being spaced from the Schottky gate electrode substantially by the thickness of the first portion of the active layer. According to a second aspect of this invention a method of producing a Schottky gate field effect transistor comprises the steps of: forming an active layer by implanting an impurity on the semi-insulating semiconductor substrate; forming a pattern on the active layer; implanting an impurity using the pattern as a mask, to form other portions of the active layer on opposite sides of the portion of the active layer shielded by the pattern, the other portions of the active layer having a higher impurity dosage than the portion of the active layer shielded by the pattern, removing the pattern, and forming a gate electrode, a source electrode, and a drain electrode on top of the portion and the other portions of the active layer, the other portions of the active layer being spaced from the gate electrode by a distance substantially equal to the thickness of the portion of the active layer. Such MESFETS have a large transconductance gm, satisfactory high frequency characteristics and are capable of ultra-high-speed logic operations. They can also be produced easily with a high yield. Examples of a MESFET and a method of making it in accordance with this invention will now be described and contrasted with conventional devices in accordance with the accompanying drawings, in which: Figures 1 and 2 are cross-sections through conventional Schottky gate field effect transistors; Figure 3 is a cross-section through an example of a Schottky gate field effect transistor according to the present invention; and, Figures 4A, 4B and 4C are cross-sections illustrating the production steps of a Schottky gate field effect transistor according to the present invention. A most commonly used MESFET has the construction, as shown in Figure 1, comprising a high resistivity or semi-insulating semiconductor crystal substrate 1, a conductive semiconductor crystal layer commonly called an active layer 2, a Schottky electrode 3, and a source electrode 4 and a drain electrode 5 having ohmic characteristics, respectively. Carrier density Nd and thickness a of the active layer 2 has a relationship defined by the following equation (1) with pinch-off voltage Vp of the MESFET: EMI3.1 wherein, Vb denotes built-in voltage, E denotes dielectric constant of the semiconductor crystal, and q denotes quantum of the electric charge. The value of Vp is given by the requirements in the circuit design, and the values of Nd and a are determined by the equation (1) so as to satisfy the value Vp. Conventional MESFET's of the construction shown in Figure 1 have disadvantages that a sufficiently large transconductance gm is not obtained because the resistance between the gate 3 and the source 4 or the gate 3 and the drain 5 is large and that the noise characteristic is lowered by the large serial resistance between the gate and the source. Particularly, when the absolute value of the pinch-off voltage Vp is small or in normally-off (Vp > 0) , the gate-source serial resistance becomes larger because the carrier density Nd or the thickness a of the active layer 2 must be small as evident from the equation (1). When GaAs crystal is used as the active layer 2r a surface state of high density exists in each of crystal surfaces 6 and 7 between the gate and the source and between the gate and the drain, respectively, whereby a surface potential is made substantially constant and a depletion layer is formed in the neighbourhood of the surface within the semiconductor crystal, resulting in that the gate-source series resistance becomes larger. This was a very serious problem particularly in a normally-off type. To overcome the foregoing disadvantages and problems, it was heretofore practiced to make, as shown in Figure 2, active layers 9 and 10 between the gate and the source and between the gate and the drain, respectively, thicker than an active layer 8 directly under the gate electrode. In this conventional practice, while the thickness of the active layer 8 and the carrier density must be determined to satisfy the conditions defined by the equation (1), it is difficult in the current technique as by etching to accurately and repeatably control the thickness of the active layer 8 in such a partially sloped construction. An example of the MESFET according to the present invention shown in Fig. 3 comprises a highly resistive or semiinsulating semiconductor crystal substrate 1, an active layer 12 mounted on said substrate 1 under a Schottky gate electrode 3, an active layer 11 mounted on said substrate 1 extending from under an ohmic source electrode 4 to between the gate electrode 3 and the source electrode 4 and having a larger number of carriers per unit area than that of the active layer 12, and an active layer 13 extending from under an ohmic drain electrode 5 to between the gate electrode 3 and the drain electrode 5 and having a larger number of carriers per unit area than that of the active layer 12. Particularly, between each of the active layers 11, 13 and the gate electrode 3, there is provided a distance approximately identical to the thickness of the active layer 12. In this way, by forming the active layer 11 extending from under the source electrode 4 to between the source and the gate electrodes 4 and 3 and the active layer 13 extending from under the drain electrode 5 to between the drain and the gate electrodes 5 and 3, the resistance between the source and the gate and the resistance between the drain and the gate can be reduced, thereby increasing the transconductance gm. For this purpose, it is preferred to dispose the active layers 11 and 13 as close as possible to the Schottky gate electrode 3. On the other hand, however, when the active layers 11 and 13 are disposed very close to the Schottky gate electrode 3, the capacity between the gate and the source and the capacity between the gate and the drain are rapidly increased to thereby worsen the high frequency characteristics or the ultra-high-speed operation of the MESFET. In order to reduce the capacity, it is required that the active layers 11 and 13 are positioned sufficiently far from the Schottky gate electrode 3. In the present invention, in order to satisfy the two above-mentioned conditions, the distance between each of the active layers 11 and 13 and the Schottky gate electrode 3 is determined optimally. Heretofore, however, optimization of the construction of MESFET has never been discussed with attention to this aspect. Attention must first be paid to that depletion layers under the gate electrode 3 lie toward the active layers 11 and 13, respectively, from the ends of the Schottky gate electrode 3 by approximately the thickness of the active layer 12, in the active state of the MESFET in which the active layers 11 and 13 are positioned sufficiently far from the gate electrode 3 for the purpose of reducing the capacity between the gate and the source and the capacity between the gate and the drain. In this way, by providing a distance substantially equal to or greater than the thickness of the active layer 12 between each of the active layers 11 and 13 and the Schottky gate electrode 3, the rapid increase in the capacity between the gate and the source and the capacity between the gate and the drain can be prevented. In the case where the distance between each of the active layers 11 and 13 and the Schottky gate electrode 3 is approximately equal to the thickness of the active layer 12, the effect to improve the transconductance gm obtained by a further decrease in this distance is very small because the resistance in the channel directly under the Schottky gate electrode 3 is sufficiently large when compared with those between the gate and the source and between the gate and the drain. Accordingly, the optimal distance between each of the active layers 11 and 13 and the Schottky gate electrode 3 is substantially equal to the thickness of the active layer 12. With reference now to Figs. 4A, 4B and 4C, an example of the method for producing MESFET according to the present invention will be described. While the present invention is widely applicable to any of semiconductor materials, for example, elements such as Si and compounds, the method according to the present invention will be described with respect particularly to an example of GaAs as a semiconductor material from among various compounds for semiconductor having an advantage of high operation speed. First, an active layer 15 is formed on a semiinsulating substrate 14 of GaAs as shown in Fig, 4A by ion implantation. The pinch-off voltage of MESFET is determined substantially by the active layer 15 thus formed. To produce a normally-off MESFET aiming at the pinch-off voltage + 0.05 V, conditions of Si ion, implantation energy 50 KeV, and implantation quantity 2.1 x 1012 dosage/cm2 are selected. Then, a pattern 21 of any suitable material is formed as shown in Fig. 4B. Thereafter, ion implantation is performed using the pattern as a mask to form a region 16 under a source electrode to be and intermediate between gate and source electrodes to be (not formed yet at this stage) and a region 17 under a drain electrode to be and intermediate between gate and drain electrodes to be (not formed yet at this stage). Here, in order to reduce the resistance between the gate and the source and the resistance between the gate and the drain, it is required to make as high as possible the number of carriers per unit area in the regions 16 and 17, that is the sheet carrier. In order to satisfy this requirement and to keep the number of carriers per unit area within the limits of GaAs, it is effective to select, in the ion implantation of the active layers of the regions 16 and 17, the acceleration energy to at least larger than 100 KeV and the dosage to at least larger than twice of the ion implantation used for the active layer 15. In the example, the conditions of-Si ion, implantation energy 180 KeV and implanting quantity 1 x 1013 dosage/cm2 are selected. At this time, the distance between the regions 16 and 17 in the mask pattern 21 is determined to provide the distance between each of the regions 16 and 17 and the Schottky gate electrode 18 in the processed MESFET substantially equal to the thickness of the active layer 15. In order to accomplish this object, the distance L' between the regions 16 and 17 at the stage where the mask pattern 21 is formed, that is the widthwise length of the mask pattern 21, is, as shown in Fig. 4B, determined by the following equation (2): L' = LG + 2LA + 2LD -¯¯¯-¯-¯ (2) where, LG : gate length of MESFET LA : thickness of region 15 LD : sum of widthwise scattering length by ion plantation and widthwise thermal diffusion by annealing process. In this example, LA is 0.1 um. LD is selected to a suitable value from 0.1 um to 0.4 um according to the processing conditions. In this example, LD is selected to 0.1 um in consideration of the subsequent annealing process. A resist pattern formed by common photolithography is used most widely as the mask pattern 21. In the example, the pattern is formed of positive photo resist (AZ-1350J) of 1.5 um thickness. After removal of the resist, annealing is performed at 8000C for about 20 minutes to activate the implanted element. At this occasion, in the case where GaAs is used as the crystal substrate, the surface is protected as by proximity method. In Fig. 4B, after completion of the ion implantation to the active layer in the regions 16 and 17 and the subsequent annealing process, the distance L between the regions 16 and 17 is decreased by the length 2LD by the widthwise scattering due to the ion implantation and the widthwise thermal diffusion due to the annealing process. As the result, the final distance L between the regions 16 and 17 is defined by the following equation as shown in Fig. 4C: t L= LG + 2LA ¯-------------- (3) Thereafter, the gate electrode 18, the source electrode 19, and the drain electrode 20 are formed by usual method as shown in Fig. 4C. In the Schottky gate field effect transistor according to the present invention, since the capacity between the gate and the source and the capacity between the gate and the drain are small and since the resistance between the gate and the source and the resistance between the gate and the drain are small, a large transconductance gm is obtained, thereby accomplishing ultra-high-frequency operation, ultra-high-speed operation, and low noise characteristics. The MESFET according to the present invention is most suitable as an ultra-high-speed logical device. Further, the production method according to the present invention provides a valuable industrial applicability because it makes it possible to produce the MESFET's very easily and at a high yield.

Claims: CLAIMS 1. A Schottky gate field effect transistor comprising a semi-insulating semiconductor substrate (1), an active layer (11, 12, 13) formed on the semiconductor substrate (1), and a source electrode (4), a Schottky gate electrode (3), and a drain electrode (5) all formed on the active layer (11, 12, 13), characterised in that: the active layer is divided into a first portion (12) directly under the gate electrode (3) and having a thickness selected to provide the required pinch-off voltage, and second portions (11, 13) located adjacent and on opposite sides of the first portion (12); the second portions (11, 13) of the active layer are doped with a larger quantity of impurity per unit area than the first portion (12) of the active layer; and, the interfaces between the first portion (12) of the active layer and the adjacent sides of each of the second portions (11, 13) of the active layer are spaced from the Schottky gate electrode (3) substantially by the thickness of the first portion (12) of the active layer. 2. A method of producing a Schottky gate field effect transistor, comprising the steps of: forming an active layer (15) by implanting an impurity on a semi-insulating semiconductor substrate (14); forming a pattern (21) on the active layer (15); implanting an impurity using the pattern (15) as a mask, to form other portions of the active layer (16, 17) on opposite sides of the portion of the active layer (15) shielded by the pattern (21), the other portions (16, 17) of the active layer having a higher impurity dosage than the portion (15) of the active layer shielded by the pattern (21); removing the pattern (21); and, forming a gate electrode (18) , a source electrode (19), and a drain electrode (20) on top of the portion (15) and the other portions (16, 17) of the active layer, the other portions (16, 17) of the active layer being spaced from the gate electrode (18) by a distance substantially equal to the thickness of the portion (15) of the active layer. 3. A method of producing a Schottky gate field effect transistor according to claim 2, in which the implantation of the impurity using the pattern (21) as the mask to form the other portions (16, 17) of the active layer is performed with the accelerating energy of at least 100 KeV and a dosage at least twice that used to implant the portion (15) of the active layer. 4. A method for producing a Schottky gate field effect transistor according to claims 2 or 3, in which the pattern (21) is a resist pattern formed by photo-lithography.

Inventors: KIKUCHI, KENICHI OSAKA WORKS, SUZUKI, TOMIHIRO OSAKA WORKS
Applicants: SUMITOMO ELECTRIC INDUSTRIES LIMITED
Application year: 1984
Main classification: H01L21
IPC codes: H01L21, H01L29