ADAPTIVE RADAR SIGNAL PROCESSOR FOR THE DETECTION OF THE USEFUL ECHO AND THE CANCELLATION OF CLUTTER

Abstract: Adaptive radar signal processor apt to detect the useful echo in the presence of an additive disturbance made up of clutter and noise, through which the disturbance can be cancelled and the useful signal can be enhanced by means of the synthesis of a filter, adapted to the useful signal, which rejects the disturbance spectrum frequency components by adapting itself in real time to its variations.

Description: The present invention relates to an adaptive radar signal processor for the detection of an expected signal in a received signal which is made of said expected signal and an additive disturbance due to clutter and/or noise, the processor including a first means for providing on its N outputs a signal which is made of uncorrelated samples, said means receiving at its N inputs N samples of the received signal. Such a processor is known by IEEE Transactions on Aerospace and Electronic Systems, vol. AES-15, no. 4, July 1979, pages 538-546, D.E. Bowyer et al.: "Adaptive Clutter Filtering Using Autogressive Spectral Estimation". It is an object of the invention to realize an adaptive processor which is able to detect the echo of a target in the presence of an additive disturbance made up of clutter and noise. Such processor, in accordance with the invention, should be made integral part of a radar receiver. More in detail, it should be inserted after the coherent detection, in video band, of the radar signal. As a well known fact, surveillance radar performance may be significantly degraded by the presence of clutter echoes, which are characterized by parameters not known a priori and which vary in a random fashon. To counter the effects of such disturbances, the techniques normally resorted to are the fixed MTI and the adaptive MTI. The acronym MTI, "Moving Target Indicator", is commonly in use by experts in the field and shall be used from here on for convenience. In the case of fixed MTI ( L.E.BRENNAN et Al. IEEE Trans. on AES Vol. AES-9, No. 2 March 1973 ) the clutter carrier frequency is assumed to be known and a fixed parameter filter is used to cancel it. In the case of adaptive MTI (USA patent 4.217.584 GALATI LOMBARDI/SELENIA) the clutter carrier frequency is estimated from the signal received by the radar and the filter profile is shifted so as to overlay the disturbance spectrum with its opaque band. These two techniques give way to the following drawbacks: fixed parameter filter, therefore predetermined filter profile; limited performance in the presence of more than one clutter signal; limited sensitivity of the useful signal; partly correlated cancellation residue which is therefore integrated in the following processing stages with a resulting higher false alarm probability. The processor, object of the present invention, eliminates such shortcomings. In fact the processor's parameters, as described in the following, change automatically as a function of the input disturbance and of the Doppler frequency of the expected useful signal. The processor frequency response adapts to the effective need to cancel one or more clutter signals, without penalizing the useful signal. Further, the cancellation residue at the filter output is constituted by an uncorrelated process (white-noise) which is not integrated in the following processing phases. Before describing the present invention in detail, it is opportune to make reference to the working principle of the optimum filter for radar signal processing (Brennan-Reed: Theory of Adaptive Radar, IEEE Trans. AES, March 1973), as the present invention is a processor which makes possible the implementation of such filter. In theory, coherent processing must be performed on the echoes corresponding to the transmission of N pulses, in a given space direction, and at instants t₁, t₂,...t N , which are not necessarily equispaced. The N echoes received by a generic range-bin may be represented in a compact form by the vector: Z T = [Z₁, Z₂,......Z N ] (1) where Z₁, in complex notation, gives amplitude and phase of the echo related to the i-th pulse and therefore it contains the contribution of noise n i , of clutter c i and of useful signal S i (if present). Samples "S i " of the expected useful signal are given by a vector S : S T = [S₁, S₂,.......S N ] (2) Both the thermal noise and the clutter have a Gaussian distribution with zero mean. Thermal noise is uncorrelated from pulse to pulse, whereas clutter may have any autocorrelation function. The covariance matrix M of the disturbance can be derived from the total disturbance correlation proprieties. It can be demonstrated that the optimum processor is the one which carries out the following test: To implement the optimum processor, the signals received must be delayed so as to render them contemporaneously available for processing and to combine them linearly by means of a filter having coefficients which are dependent upon M and S ; such optimum filter output must be amplitude detected. The resulting value must then be compared with threshold α, which is set on the basis of false alarm and correct detection probability requirements. The optimum processor, till now, was known only as a theory because its practical implementation requires the knowledge of an estimated value of the matrix M ⁻¹ on the basis of samples of the input signal. With the present invention, the problem of determination of such matrix is resolved by resorting to the following relationships M ⁻¹ = D T · D* (4) which holds true for Hermitian matrices and therefore also, in particular, for the covariance matrix M (W.F. Gabriel-"Adaptive Arrays, an Introduction" Proc. IEEE, February 1976). Such transformation enables us to express the optimum test as: the implementation scheme of which is given in Fig. 1. In such schematic, segnals Z and S undergo the same transformation D ; the signals thus obtained, respectively Z and b , are combined linearly to produce the output y. The fundamental property of transformation D is that by acting upon samples of the total disturbance, it gives as an output a signal Z ' which is made up of uncorrelated samples having equal power, having a covariance matrix which is an identity matrix. It is also observed that the preceding property is not altered by the presence of the useful signed S present at the input and added to the disturbance, because this alters only the expected values of Z and Z '. It therefore follows that the combination of signals Z' and b corresponds to the enhancement of the useful signal which may be present in Z . The present invention is able to resolve, by means of adaptive techniques, the problem of transformation D implementation, and therefore that of the optimum filter, i.e. the disturbance cancellation function, therefore enhancing the useful signal. In general transformation D is not known a priori, because the disturbance characteristics are unknown; in particular it's the covariance matrix M which is unkown. It is therefore necessary to make recourse to an adaptive implementation of device D . Two characteristics single out the effectiveness of the adap t ive device: precision of the steady state estimate D , high speed to adapt to non stationary disturbance conditions. Such requirements oppose each other, because to have a precise estimate the input data must be averaged over a significantly long observation time. On the other hand, long adaption times are incompatible with the hypothesis made of stationarity clutter which holds true only over limited time intervals. Let us consider the operation of the adaptive processor in the time domain. Let us consider N pulses transmitted by the radar and the related listening intervals. For each interval, the responses obtained in K range bins are utilized, which give way to K independent vectors: Z ₁, Z ₂,........ Z K each one made up of N samples of the signal received. The estimate of the characteristics of the disturbance, and therefore of the transformation D can be derived by averaging the K independent groups of samples. It is therefore necessary that the value K be limited within the interval in which the disturbance is stationary. The typical order of magnitude of "K" is a few tens of cells. The processor, object of the present invention, according to the characterizing part of Claim 1, implements transformation " D " satisfying the two confl cting requirements indicated above. As an example, but not limited to this, in the following the invention will be described by making reference to the figures provided. FIG. 1: General schematic of the optimum processor of radar signals FIG. 2: Implementation of block D. FIG. 3: Implementation of block "A" (elementary decorrelation device) FIG. 4: Example of the processor for N = 2 pulses FIG. 5: General schematic of the processor in its preferred configuration Fig. 1 gives the general schematic of the optimum radar signal processor where Z is the input signal to block D (7) which performs the disturbance decorrelation; S is the expec t ed signal, processed by means of block D (7a); y is the output obtained as a combination of signals Z ' and b through multipliers (9) and the summing circuit (10); block (2) extracts the y modulus which is compared to the threshold in block (3). The present invention regards the implementation of blocks D (7) and (7a), and has, as an aim, the implementation of the optimum processor given in figure 1. Now the invention in its preferred implementation will be described following the illustration in Fig. 2, which is the most significant in highlighting the invention itself. It may be remembered that the function of transformation D is that of obtaining a group of N signals Z i , uncorrelated and having unity power, starting from the input signals Z₁ which are correlated. To this end, different pairs of signals, which are made to be mutually uncorrelated, are taken into examination. The processing is organized in successive levels from 1 to N-1: a signal is taken as reference at each level and is uncorrelated with respect to all further signals having the same level and than its power is normalized. In particular, in the case N = S given as an example in Fig. 2, signal Z₁ is compared in blocks A at level 1 respectively with signals z₂, Z₃, Z₄, Z₅; at the output of each block A a signal corresponding to the component of input signal (Z₂, Z₃, Z₄ and Z₅) is obtained which is uncorrelated with reference signal Z₁. The signals thus obtained are sent to the next level where Z₁ is not modified until it is normalized and the function of the reference signal is performed by the residual component of Z₂ (i.e. is cleared of Z₁) obtained at the output of the first block A. At level 2, the residual components of Z₃, Z₄, Z₅ are freed of the component correlated with the new reference and are sent to the next level and so on till N mutually uncorrelated signals are obtained. The process described corresponds to the cancellation of the clutter component present in the input signals. The last transformation necessary to obtain output Z ¹ is the power normalization of the signals: this requires an estimate of the power of the signals themselves and further their division by an opportune scaling factor. As detailed further ahead, the preferred implementation for block A contains an estimate of the reference signal power; therefore the scaling operation can be made directly on the signals obtained by transformation of Z₁, Z₂, Z₃ and Z₄ by means of coefficients V₁₁, V₂₂, V₃₃ and V₄₄ indicated in Fig. 2. For the signal obtained from Z₅ on the contrary, it is required to have an estimate of power because it never appears as a reference signal. Therefore in ig. 2, N-1 scaling blocks SC, which are meant for signal scaling, have been indicated and also a power normalizing block NP which effects both power estimate and scaling. The structure given in Fig. 2 is particularly useful for a rapid implementation of the adaptive processor. In fact it does not contain any feedback loops which could give way to stability problems, or to an extremely slow adaptation transient. The processing structure has also a high degree of parallelism from which two relevant consequences derive. From the functional viewpoint, blocks A of the same level operate simultaneously and independently; in this way the whole structure reaches steady state within a time limit which depends on the number of levels. Furthermore, the implementation of device D is modular. In all, N(N-1)/2 blocks A are necessary for the implementation, (N-1) scaling blocks SC and one normalizing block NP. In order to describe how the generic block (A) in Fig. 2 may be implemented, let us consider in greater detail which processing activities it must carry out. Let Y K and X K be respectively the input and the reference signals for the generic block A and W K the corresponding output. Output N K must be uncorrelated to reference input X K , i.e.: E { W K X* K } = γ (6) The schematic given in Fig. 3-a gives a preferred implement a tion of block "A", based upon equation (6), giving the follow ing output: W K = X K E { Y K X* K } - Y K E { X K X* K } (7) It is simple to verify that the output thus obtained satisfies condition (6). More in detail, output WK is obtained from the difference of two terms: W K = (X K · U K-1 ) - (Y K · V K-1 ) (8) Coefficients U K-1 and V K-1 represent estimates of the correlation between Y and X and of the power of X. The correlation is obtained by multiplying, within block (13), the signal Y K with the complex coniugate of X K , block (16) and by integrating such product through block (18). Figure 3-b gives the detail, in an illustrative and not limiting manner, a possible implementation of an integrator, (blocks (14) and (18) of figure 3-a), under the assumption that the processing is made adopting digital techniques. The integrator is implemented as a transverse filter, formed by a number of delay elements (blocks (23), (24), (25)) and by a summing block (26) which produces an output (27) equal to the sum of the signals present in the delay blocks themselves. Delay Δ is equal to the time duration of a range-bin and therefore corresponds to integrating the K range-bins nearby. The number of samples summed up together characterizes the integrator memory and is selected so as to satisfy the two opposing requirements, already mentioned, for precise and rapid estimates. The implementation of block "A" by means of the schematic of Fig. 3-a 3-b, confirms the selection of processing struc t ures which are stable and fast, that is without any feedback, as already mentioned for Fig. 2. We emphasize that the calculation of coefficient V K-1 corresponds to the estimate of the reference input power. Such datum may be used for signal normalization, as already explained in the illustration of Fig. 2. In Fig. 4, the most simple configuration of the processor is given, i.e. the case for N = 2 pulses. For all the range-bins taken into examination samples Z₁ and Z₂ at the input to the processor are made up of clutter and noise; the useful signal is on the contrary present in a single range-bin. It is assumed that the time duration of the disturbance is sufficient to take estimates ∪ / U and V of block (7) to a steady state. When also the useful signal is present at the input, it does not affect these estimates for the following reasons: it generally has less power than the disturbance it has a much shorter time duration than the integrator memories. Within the range bins where the useful signal is contained, outputs Z'₁ and Z'₂ contain both the components of such signal and the disturbance components, uncorrelated and at unit power level. At the same time, in block D (7a), the known samples of the expected signal, S,₁ and S₂, undergo the same combination with coefficients U and V already estimated, and further give way in b₁ and b₂ to components matched to those present in Z'₁ and Z'₂. By means of the multiplying blocks (9) and the summing block (10), the linear combination of Z'₁ and Z'₂ is performed with weights b₁ and b₂ respectively, so as to obtain output y, the modulus of which is further compared with the threshold as shown in the general schematic of Fig. 1. It is necessary to emphasize that the coefficients U and V of block (7a) are exact replicas of those of block (7), that is, they depend exclusively on the disturbance signal which is present at Z₁ and Z₂. For this reason it is not necessary to repeat, in block (7a), the estimation structure by means of the integrators present in block (7). Finally, the transformation, made by block (7a) on S₁ and S₂ coincides with that performed at steady state by block (7) on Z₁ and Z₂ and such transformation is just the one indicated by D . To conclude, Fig. 4 shows the calculation of output y starting from signals Z'₁ and Z'₂ and from coefficients b₁ and b₂, on which test (5) is performed as shown in the general schematic of Fig. 1. In Fig. 5, the general schematic of the processor is given in its preferred configuration, to best synthesize the description of the invention, already given in detail as a commentary to Figs 1, 2, 3 and 4. Fig. 5 refers, as an example, to the case of four processed pulses (N = 4). In such figure it is shown how samples Z₁, Z₂, Z₃, Z₄, of the input signal are processed in block (7), whereas samples S₁, S₂, S₃, S₄ which represent the useful signal expected are processed in block (7a); the two blocks (7) and (7a) have the same structure, being made up of 6 blocks (11) and (30) respectively (blocks A in Figs. 2, 3, 4). It is important to note how blocks (30) are a simplified version of blocks (11), as they have the only function of combining the input signals with the opportune coefficients; the coefficients U and V of such combinations are provided by corresponding blocks (11) which also perform the estimate fun c tion as described in detail in the commentary to Fig. 3. Therefore each block (30) contains only multipliers (19) and (15) and summing block (20). Still in Fig. 5, blocks (31) are shown, which carry out the scaling of signals (32) using the power estimates V of blocks (11) and the power normalizing block (2) where the estimate function (33) is distinct from the scaling one (13). Within block (7a) only scaling blocks (31) appear correspond ingly , as the power estimate is provided by the V signals of block (7). Finally the devices which perform the operation of "complex coniugate (8), multiplication (9) and sum (10) are shown to obtain output y. As already described in the commentary to Fig. 2, this signal is further modulus detected (block 2) and compared with the threshold of block (3) to detect the target presence. To conclude, the processor, object of the present invention, gives the following advantages over previous techn i ques: the filtering profile is not rigidly set, but it adapts automatically to the changing and unpredictable characte r istics of the input disturbance; the processor estimates the disturbance parameters in a limited time (a few distance bins), that is, within the stationarity interval of the disturbance itself; the accuracy with which the processor evaluates such parameter enables to reach useful signal detection performances in presence of a disturbance, very close to the optimum value which can be derived from the theory.

Claims: Adaptive radar signal processor for the detection of an expected signal in a received signal which is made of said expected signal and an additive disturbance due to clutter and/or noise, the processor including a first means (D) for providing on its N outputs a signal which is made of uncorrelated samples, said means receiving at its N inputs N samples of the received signal, the processor being characterised in that the first means (D) has a modular structure and comprises N (N-1)/2 decorrelating blocks (A) arranged in a matrix of N rows and N columns, the row of level (i) in the matrix including (N-i) blocks, a block in a given row (i) and column (j) receiving on its first input the output signal from the block in the first column of the preceding row (i-1) and on its second input the output signal from the preceding block in the same column (j), and N power-normalisers (SC-NP) connected to the last blocks in each column; and in that it comprises further a second means (D) identical to the first means, which receives on its N inputs N samples of a signal similar to the expected signal and provides on its N outputs N modified samples; N multiplying means (9) for respectively multiplying each of the N uncorrelated samples with the complex conjugate of the corresponding one of the N modified samples; an summing circuit (10) for adding the output signals from the multiplying means; and a comparator (3) comparing the output signal from the summing circuit to a threshold to detect the presence of the expected signal in the received signal. Adaptive radar signal processor according to claim 1, wherein each decorrelating block (A) is made up of a lattice structure comprising a summing circuit (20) which has two inputs (+,-), each of which is connected to a circuit having in a series connection a multiplier (13,17), an integrator (14;18) and a further multiplier (15, 19).

Inventors: FARINA, ALFONSO, STUDER, FLAVIO ALESSANDRO
Applicants: SELENIA INDUSTRIE ELETTRONICHE ASSOCIATE S.P.A.
Application year: 1984
Main classification: G01S13
IPC codes: G01S13