CLOCK STRETCHING CIRCUITRY

Abstract: In a data processing system (10) which includes a central processing unit (22) capable of operating at a higher speed than memory device (20) associated therewith, method and apparatus provide for sensing and correcting errors generated in the memory device, particularly as a result of operation of the memory at speeds approaching design limits wherein errors may be introduced into the data. Specifically, clock stretching circuitry includes circuitry (36) which operate the central processing unit at a preselected clock rate, circuitry (42, 44, 46) which senses for data errors and circuitry (38) which introduces delays in the clocking of the central processing unit only in the presence of indicated data errors. The clock stretching interval permits error correcting circuitry (48) to correct identified bit errors in the data before the central processing unit accesses the data.

Description: CLOCK STRETCHING CIRCUITRY BACKGROUND OF THE INVENTION Field of Invention This invention relates to data processing, and more particularly to the interaction of central processing units capable of operating at a higher clock rate than memory means connected thereto. In a high speed central processing unit (CPU) running near a maximum design speed, very little time is provided between the interval during which the central processing unit presents a direct memory means with an address and the time the central processing unit requires the data corresponding to the address. Memory means, such as dynamic random access memory (DRAM) elements, may have a design access time longer than a central processing unit. Consequently, as the speed of the CPU and the DRAM clocks is increased, little time margin remains to permit correction of errors in data readout and data transmission, for example, due to external uncontrolled causes. It is possible to correct data errors if sufficient time margin is provided between a CPU request for data and the transmission of data to a CPU. Since errors are inevitable, the performance of the CPU is likely to be penalized and underutilized. Description of the Prior Art Data error checking and correcting (ECC) techniques are well known for increasing the reliability of data extracted from a memory. Such techniques typically involve the addition of check bits to data. A simple example is a parity bit added to a group of data bits to form a byte. Sum checking functions are capable of identifying location and existence of errors in a group of data bits. Error checking and correcting genera-lly produce a performance penalty because a finite time is required to receive and analyze bits of information and to provide correction if necessary. A CPU is penalized by the delay, as it must wait for error checking and correcting even though there may be no errors in the data. In the prior art, the performance of a central processing unit is normally deliberately degraded by the addition of "wait-states" between a request for information and the reception of the information. The use of "wait-states" to provide sufficient _time to allow direct memory to respond to requests for information with error correction may be shown to be extremely wasteful of valuable CPU time. Errors in data are generally rare. Thus, the provision of "wait-states" is useful only during those periods when error correction would be necessary. What is therefore needed is some technique for accommodating error detection and correction while eliminating "wait-states" and minimizing the time lost by a CPU in awaiting receipt of corrected data signals. SUMMARY OF THE INVENTION In a data processing system which includes at least one central processing unit (CPU) capable of operating at a speed higher than memory means with error checking capability associated therewith, a method and apparatus provide for sensing and correcting errors generated in the memory means with minimum penalty to CPU performance. Specifically, clock means and associated circuitry are provided which operate the central processing unit at a clock rate near the maximum clock rate of the memory means. The memory means with associated error checking and correcting capability senses for data errors and then only in the presence of indicated data errors, suspends the clocking of the central processing unit by stretching the interval between CPU clock cycles. The clock stretching interval permits error correcting circuitry associated with the memory means to correct identified bit errors in the data before the central processing unit accesses the data. In a specific embodiment, a clock cycle stretching circuit is provided which receives four (4) parity signals computed according to known means across eight (8) bits of memory data in parallel. The circuit thus provides a rapid indication that an error has occurred. If the circuit indicates that a single-bit error has occurred, the clock signal used to drive the CPU is temporarily frozen or otherwise decoupled from the CPU at its current state, and the data in error is corrected by known techniques. When the data is identified as valid, or after a predetermined time, the clock driving the CPU is released to allow the CPU to continue operation. In this manner, the CPU is driven to run at full speed except at times when an error has been detected which can be corrected. In a further specific embodiment of the invention, a double-bit error check is conducted such that in the rare event a double-bit error is detected the CPU is interrupted to prevent execution of faulty data. The invention will be better understood by reference to the following detailed description taken in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing an exemplary apparatus according to the invention in connection with a central processing unit and a bus means. Figure 2 is a schematic diagram of a portion of memory means, bus control means, and clock stretching circuitry according to the invention. Figure 3 is a timing diagram illustrating one form of a clock stretching function according to the invention. DESCRIPTION OF SPECIFIC EMBODIMENTS Referring to Figure 1, there is shown a portion of a computer 10 which includes internally a memory address bus 12, memory data bus 14, and memory control bus 16, said buses 12, 14 and 16 being operative together in accordance with three-state logic rules of logic one, logic zero and high impedance (High Z) at ports of elements coupled to the memory address bus 12 and the memory data bus 14. A random access memory controller, or RAM controller 18 of conventional design, arbitrates access to the memory data bus 14 and memory address bus 12 as well as to a system bus (not shown) and any peripheral device (not shewn) desiring direct memory access (DMA) to a data RAM 20 through the memory address bus 12 and memory data bus 14. At least one central processing unit (CPU) 22 is coupled to the buses 12, 14 and 16. The CPU 22 includes a data port 24 bi-directionally coupled to the memory data bus 14, an address port 26 coupled to the memory address bus 12, and a control port 28 coupled to the memory control bus 16. The control port 28 is operative to direct bus control signals through, for example, three binary digital lines to the RAM controller 18 and to other elements as hereinafter explained. The CPU 22 communicate directly with the RAM controller 18 over a CPU request line 30 to the RAM controller 18 and by a CPU ready line 32 from the RAM controller 18. The RAM controller 18 may also act as a conduit for a nonmaskable interrupt signal via a nonmaskable inter¬ rupt line 34. _ The CPU 22 is operative in sequential states under program control at a specified clock rate as established by clock means including an oscillator 36 coupled via signal line 103 to gating means 38 coupled via line 62 to a clock port 23 of the CPU 22. According to the invention, the gating means 38 is operative to drive the CPU 22 at a preselected relatively high clock rate except when errors have been detected in data passed to the memory data bus 14 by the data RAM 20. In a specific embodiment, the gating means 38 is responsive to a set of freeze command signals via a freeze command bus 40, which signal is routed through the RAM controller 18. The RAM controller 18 is used out of convenience due to availability of _ integrated circuit parts to perform the tasks of controlling a memory bus means. According to the invention, four (4) func¬ tional elements are provided for detecting data errors and either correcting data errors or terminating execution. These functional elements include a parity generating circuit 42, a parity random access memory (parity RAM) 44, a check bit random access memory (check bit RAM) 46 and error correcting circuitry 48. These functional elements respond to the extra bits provided ' in the data used to establish the existence of error and to register the address of such errors. The parity generating circuit 42 is operative to receive data signals from the memory data bus 14 and to provide parity values as data to the parity RAM 44. The parity RAM 44 receives addresses for the parity generated values off of the memory address bus 12 and receives control signals from the RAM controller 18. The parity control line 50 provides the strobe or pattern of signals needed by the parity RAM 44 to read and write data. The control signals originate with signals applied to the RAM controller 18 from the control bus 16. The parity generator circuit 42 is operative to respond to data at addressed locations in the parity RAM 44 and from the memory data bus 14, such that single-bit errors are promptly signaled via signal line 43 to the RAM controller 18 for initiating a freeze command signal to the CPU 22 via freeze command line 40. In practice the freeze command line is three lines, 40A, 40B and 40 as explained in connection with Figure 2 hereinbelow. The check bit RAM 46 is operative to receive address signals from the memory address bus 12 and control signals through a check bit RAM control signal line 52 from the RAM controller 18 to exchange check bit data through data line 51 with the error correction circuitry 48, where the check bit data is initially generated. The error correcting circuitry 48 is operative to receive check bit data signals previously stored in the check bit RAM 46 via data line 51 and data signals from the memory data bus 14 via data line 53. The error correcting circuitry 48 manipulates the two sets of data signals to correct for any errors in data detected on the memory data bus 14. In the event a single-bit error is detected, corrected data is provided to the memory data bus 14 under strobe control of the RAM controller 18 as if the data placed on the memory data bus 14 by the error correcting circuitry 48 had come from the data RAM 20. This function requires some finite time to execute according to known methods. It is therefore necessary that the RAM controller 18, in connection with the gating means 38, freeze the operation of the CPU 22 to accommodate the placement of data on the memory data bus 14 by the error correcting circuitry 48. This Freeze command is previously initiated by the parity generator circuit 42. In a further embodiment of the invention, the error correcting circuitry 48 is operative to detect for multiple-bit errors in the data by conventional error detecting techniques and, in response, to issue a nonmaskable interrupt signal via signal line 55 through RAM controller 18 and signal line 34 to the CPU 22. The circuitry shown in Figure 2 is merely illustrative of one embodiment of the invention. For example, the gating means 38 may be redefined as a portion of the RAM controller 18, and the circuitry employed to sense and correct data errors may be considered to be a component of either the memory means or of the RAM controller 18 ' . In the particular embodiment herein described, the RAM controller 18 receives an error indication signal from the parity generation circuit 42 via line 43 at a first input of a NOR gate 64 and at the D input of a flip flop 66. A RAM row address strobe ( AMRAS) signal 40B (on signal line 40B) within the RAM controller is provided as a Clear signal to the flip flop 66 and as a signal 40B on the freeze command bus 40. A Clock signal is received at a CLK input of the flip flop 66 from a delay means 67. The principal function of the delay means 67 is to provide a clock pulse at a fixed time delay after the beginning of a cycle, e.g., the RAMRAS signal, so that the parity generator output signal value can be preserved in the flip flop 66. The output of the flip flop 66 is provided to the second input of the NOR gate 64 upon receipt of the strobe signal 40B such that the NOR gate 64 provides a stable parity error indication signal 40A on the freeze command bus 40. A memory read command signal (MEMRD) 40C (on signal line 40C) is provided also from the RAM controller 18, thereby indicating that the data RAM 20 is to be read for data. The gating means 38 comprises principally a delay line means 68 or the equivalent which is driven at a selected clock rate by the oscillator 36 through clock signal line 103 coupled to. a clock input 70. A master reset port 72 of the delay line means 68 receives the RAMRAS signal on line 40B. The delay line means 68, which may be a type 74S174 integrated circuit, includes two data output ports and two data input ports in addition to the master reset port. The first delay line output is a port functionally located at, for example, three time segment delays separation from the master reset input port 72 and is herein represented by a port 74 coupled to a first input of a NAND gate 76. The second input of NAND gate 76 is the parity error signal 40A (on signal line 40A) , and the third input is the memory read signal 40C (on signal line 40C) . The output of the NAND gate 76 is provided as a signal 100 (carried on signal line 101) to a NOR gate 78 and to an inverter 80. The output of the inverter 80 is provided to the second input port 82 of the delay line means 68, which port is functionally disposed, for example, one delay period separated from a second output port 84, the output of which is coupled through an inverter 86 to a signal line 102. The signal line 102 is coupled to a second input of NOR gate 78 and is also fed back to the first input port, herein designated input port 88, at the head of the delay line means 68 and thus ahead of the output port 74. The oscillator clock input signal on signal line 103 is provided through an inverter 90 to a third input of NOR gate 78 via a signal 105. The output of the NOR gate 78 is the CPU clock signal line 62, namely the signal which drives the clock input of the CPU 22. The delay line means 68 is functional as two delay line segments consisting of the segment between ports 88 and 74 and the segment between ports 82 and 84, where the output of port 84 is inverted and fed back to the input port 88. Referring to Figure 3, the gating means 38 is operative as follows. In normal error-free operation, the oscillator 36 generates a clock signal on line 103 and in inverted form on line 105 at a predetermined clock rate. The signal on line 105 (Figure 2) is designated inverted clock signal 105 in Figure 3. The output signal of line 62 of gating means 38 is a clock signal, herein designated CPU CLK 62, which normally tracks the inverted clock signal 105. During -a memory read operation, wherein the memory read signal on line 40C, herein designated MEMRD signal 40C in Figure 3, is active, the system recognizes that the data on the memory data bus 14 (Figure 1) is to be directed to the CPU 22 (Figure 1) . The MEMRD signal 40C places a logic true value at one input of the NAND gate 76. The memory cycle begins with the row address strobe indicated herein as RAMRAS signal 4OB. When RAMRAS signal 40B becomes true, the delay line reset port 72 is reset and the flip flop 66 is clocked. The parity generator 42 (also in Figure 1) performs a conventional check sum to detect for single-bit errors. If a single-bit error is detected, such a signal indication is provided via line 43 to the NOR gate 64 and to the flip flop 66, which in turn propagates the indication of error detection immediately through the NOR gate 64 to the signal line 40A as the parity error signal 40A. The flip flop 66 holds the error state on line 40A if, when the flip flop 66 is clocked, a parity error has been detected by the parity generation circuitry 42. The parity error indicator signal 40A is directed to the NAND gate 76, such that parity error provides a second logic true value to the input of the NAND gate 76 upon detection of a parity error. Normally, signals 101 and 102 are high such that the CPU CLK signal 62 follows the CLK signal 105. However, following the parity error signal 40A, signal 101 goes low, which immediately interrupts the CPU CLK signal 62 through gate 78. One clock cycle later, signal 102 changes state, which state change is fed back to port 88 and begins propagating through the delay line means 68. The change in state is propagated to port 74, which after the predetermined delay, causes the state of gate 76 to change as indicated by the change in signal state on signal 101, which signal is applied in inverted form to the input port 82. After one cycle, the change in state at port 82 propagates through to port 84 which in turn causes a change in state of signal 102. With both signals 101 and 102 high the CPU clock signal 62 again begins to track the clock signal 105. The CPU clock signal 62 then drives the CPU 22, and thereafter the RAMRAS signal 40B clears the delay line means 68 in preparation for the next memory read cycle. The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art. ^ Therefore, it is not intended that this application be limited except by the appended claims.

Claims: CLAIMS 1. In an apparatus having at leas one central processing unit (CPU) , a clock means and a digital memory means, said at least one CPU being capable of generating information cycle signals (read signals) at a clock rate " greater than a clock rate at which said memory means can respond to said information cycle signals free of data errors, a method for maxi¬ mizing cycling speed of said CPU in response to clock signals of said clock means in connection with said memory means, said method comprising: sensing for data errors generated from said memory means in response to said information cycle signals; and in response to said data errors delaying signals of said clock means for cycling said CPU and correcting said data errors during said delaying of said clock means signals. 2. The method according to claim 1 further including the step of providing extra bits of data to said memory means for use in computing existence and address of single-bit data errors generated from said memory means; and generating an indicator signal from said added bits and from data provided by said memory means indicative of existence and address of all single-bit data errors. 3. The method according to claim 2 further including the step of generating an interrupt signal from said added bits and from said data bits indicative of existence of multiple-bit errors in said data, such that operation of said CPU may be terminated. 4. In an apparatus having a central pro¬ cessing unit and a digital memory means, said central processing unit being capable of generating information cycle signals at a clock rate greater than a clock rate at which said memory means can respond free of data errors, a clock means for maximizing cycling speed of said central processing unit in connection with said memory means, said clock means comprising: means for generating system clock signals and central processing unit clock cycles having beginning and ending data boundaries during which received information is valid; means coupled to said memory means for sensing data errors generated from said memory means in response to information request signals, including means for generating an error indicator signal; and means responsive to said error indicator signal for delaying said CPU clock signals, including means for correcting said data errors during delay introduced by said delaying means. 5. The apparatus according to claim 4 wherein said sensing means further includes means for generating an interrupt signal responsive to an indi¬ cation of multiple-bit data errors for use in inter¬ rupting said central processing unit. 6. The apparatus according to claim 4 wherein said delaying means comprises delay line means, and means for sensing the confluence of at least a first signal and a second signal, said first signal indicative of the presence of an error in data and the second signal indicative of the absence of sufficient time to correct said error in data.

Inventors: BURGER JOHN, LOWENTHAL RICHARD, MOMIROV MILAN, SNYDER EDWIN, BURGER, JOHN, LOWENTHAL, RICHARD, MOMIROV, MILAN, SNYDER, EDWIN
Applicants: CONVERGENT TECHNOLOGIES INC, CONVERGENT TECHNOLOGIES, INC.
Application year: 1984
Main classification: G06F1
IPC codes: G06F11