ERROR CORRECTION APPARATUS USING A VITERBI DECODER

Abstract: Received, convolutionally coded bits are grouped and ap­ plied to a branch metric calculator and an adder to provide a plu­ rality (sixteen) of sums of branch metrics over branches defin­ ing two depths of a Viterby trellis diagram corresponding to the convolutional code. Such sums, of the form Z₁₁ + Z₁₁, Z₃₁ + Z₁₁ etc. where the two components of each sum pertain to successive time slots and the index values specify the path branches, are applied to terminals (31-34, 41-44) forming first inputs to sixteen adders (eight shown, 301-304, 401-404) whose other inputs receive appropriate ones of four stored path metrics (M₁ - M₄). The adders all operate in parallel and the stored metrics are updated over two depths of the trellis diagram by an arrangement of comparators and selectors ef­ fecting two levels of comparison and selection. For example, in the first level a comparator (305) compares the sum from one pair of adders (301, 302) and controls both a selector (307) for that pair of adders and a selector (407) for another pair of adders (401, 402). In the second level comparators (309, 409) and corresponding selectors (310, 410) select between out­ puts of pairs of first level selectors. The control signals from all the comparators indicating the determinations made thereby are coupled to a path memory (101) indicating the paths of the selected values and hence the decoded output bits correspond­ ing to the servicing paths.

Description: The present invention relates to an error correction apparatus for use in digital transmission systems, and in particular to a high-speed error correction apparatus for decoding received convolutional code bits using the Viterbi decoding algorithm. Error correction is used in the sense that the decoded bits have been optionally decoded so as largely to nullify the effect of bit errors in the redundant bit-stream which is actually transmitted. Recent advances in digital techniques in telecommunications have brought about numerous proposals and new systems for correcting errors introduced in transmission facilities, particularly satellite communications. The Viterbi decoding algorithm has been employed in these proposed systems and highly evaluated because of its practical utility. The Viterbi decoding algorithm involves interactive operations of sequential selection of one of two metric paths that remerge at a node in the decoder's trellis diagram by detecting the greater of accumulated metric values so that the selected path is taken as one having a maximum likelihood. Metric values, also referred to as metrics, are a measure of the distance of a selected code word from a received code word. Prior art error correction apparatus using the Viterbi decoding algorithm repeats the operations of add, compare and select on each time slot which corresponds to the period of a single bit or a single code word. However, the time taken to effect the add operation imposes limitations on the operating speed of the system, making it unsuitable for high speed data processing. With the current CMOS integrated circuit technology the maximum operating speed does not exceed 10 Mb/sec. SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction apparatus that eliminates the prior art problem by reducing the time involved with adding operations. The invention is defined in claim 1 below, to which reference should now be made. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a convolutional encoder; Fig. 2 is a trellis diagram useful for describing the operation of the present invention; Fig. 3 is a block diagram of an embodiment of a prior art add-compare-select circuit; and Figs. 4A, 4B and 4C are block diagrams of an embodiment of the error correcting apparatus, with Figs. 4B and 4C illustrating the add-compare-select circuit of the present invention. DETAILED DESCRIPTION Before undertaking the detailed description, it is appropriate to describe a convolutional encoder having a constraint length K=3, an output code symbol v=2, and a coding rate r=1/2. In Fig. 1, the convolutional encoder comprises a three-stage shift register 1 having stages K₁, K₂ and K₃, two modulo-2 adders v₁ and v₂ and a commutator 2. A sequence of information bits is applied to terminal 3 and delivered as the code symbol output from terminal 4. The modulo-2 adder v₁ has two inputs which are connected to the K₁ and K₃ shift register stages and modulo-2 adder v₂ has three inputs connected to all the shift register stages. The outputs of modulo-2 adders are alternately coupled to the output terminal 4 by commutator 2. The state of the convolutional encoder is the contents of the first two shift register stages K₁ and K₂ which are given in nodes S i (j) at the end of a time slot t(j) in the trellis diagram which is shown in Fig. 2 as a fixed periodic structure after trellis depth K=3 is reached. There are four possible states 00, 10, 01 and 11 and eight code paths (metric branches), two entering each state. The numerals given in parentheses on the metric paths indicate the information bits received in the associated time slot and those given under the metric paths indicate the output code symbols generated within that time slot. The Viterbi decoder is a maximum likelihood decoder whose algorithm is to calculate the likelihood of each of the two paths entering a given state or node and eliminates from further consideration all but the most likely path that leads to that state. After each decoding operation only one path remains leading to each state. The decoder then proceeds one level deeper into the trellis and repeats the process, leaving four paths at each trellis depth, or time slot. An error correction apparatus incorporating the Viterbi decoding algorithm comprises a path metric detector that converts the received code word to a metric path metric Z i (j) such that code words 11, 01, 10 and 00 are converted to 2, 1, 1 and 0, respectively. Further included are a plurality of add-compare-select (ACS) circuits. Fig. 3 shows an embodiment of a prior art ACS circuit arrangement. In Fig. 3, the arrangement includes four ACS circuits 5a, 5b, 5c, 5d of identical construction. Each ACS circuit includes a pair of adders 6 and 7, a comparator 8 and a selector 9. The adder 6a of ACS circuit 5a reads the previous path metric M₁ (j-1) of node S₁ (j-1) from memory 10a and adds it to the branch metric Z₁₁ (j) of code word 00. The adder 7a reads the previous metric M₃ (j-1) of node S₃ (j-1) from memory 10b and adds it to the branch metric Z₃₁ (j) of code word 11. Comparator 8a compares the combined output of adder 6a with the combined output of adder 7a and determines the highest of the two. A control signal indicating this determination is applied to selector 9a which selects the highest value as the maximum likelihood path and writes it into a metric memory 11a to update the previous value. The updated metric M1 (j) will be read in the next time slot as a path metric for node S₁ (j) . The control signal is also applied to a path memory 12 to store the paths that survive in the trellis diagram over the past until node S₁ (j) is reached. Likewise, in ACS circuit 5b the path metric M₁ (j-1) and the branch metric Z₁₂ (j) of code word 11 are added up in adder 6b and the path metric M₃ (j-1) and the branch metric Z₃₂ (j) are added up in adder 7b. Comparator 8b determines the highest of these combined outputs as most likely and controls the selector 9b to pass it to a metric memory 11b for storage as a path metric M₃ (j) for node S₂ (j) , updating the previous value. Similar ACS operations are performed by ACS circuits 5c and 5d simultaneously with the ACS operations performed by ACS circuits 5a and 5b. The path metric M₂ (j-1) of node S₂ (j-1) is read from memory 10c, summed with the branch metric Z₂₃ (j) of code word 01 and compared with the sum of the path metric M₄ (j-1) of node S₄ (j-1) read from memory 10d and the branch metric Z₄₃ (j) of code word 10. The highest of the compared metrics is stored into memory 11c as a path metric M₂ (j) of node S₂ (j) . The path metric M₂ (j-1) of node S₂ (j-1) is read from memory 10c, summed with the branch metric Z₂₄ (j) of code word 10 and compared with the sum of the path metric M₄ (j-1) of node S₄ (j-1) read from memory 10d and the branch metric Z₄₄ (j) of code word 01. The highest of the compared metrics is stored into memory 11d as a path metric M₄ (j) of node S₄ (j) . In this manner, sequential selection is repeated on each node, so that there remains only one path in the past time slot that occurred four to five times the constraint length K. Binary 1 or 0 generated corresponding to such surviving metric path forms the decoded signal. The prior art add-compare-select circuit is required to operate within a period τ which must not exceeds the time slot period and is given by: τ = τ m + τ a + τ c + τ s + τ w (1) where, τ m is the time taken to read a path metric from metric memory, τ a , τ c ,τ s are the times involved in performing the addition, comparison and selection respectively, and τ w the time taken to write path metric into metric memory. Thus, the bit rate attainable with the prior art ACS circuit is limited to 1/τ bits/second. To achieve high speed decoding, it is necessary to reduce the addition operations since time τ a accounts for a substantial part of the total operating time τ. Figs. 4A to 4C are block diagrams of an embodiment of the ACS circuit of the present invention. The add-compare-select circuit of the present invention reduces the decoding time by providing additions involved with two consecutive time slots in a single operation. For example, a new path metric for node S₁ (j+1) , is derived from path metric sums derived from paths which remerge at nodes S₁ (j) and S₃ (j) and at node S₁ (j+1) as indicated by thick lines in Fig. 2. Specifically, in Fig. 4A, a received bit stream of convolutional code bits is transformed into sequences of code bits P and Q. The code bit P is applied to serial-parallel shift registers 20 and 22 and code bit Q to serial-parallel shift registers 21 and 23. Shift registers 20-23 are clocked by a frequency divider 24 at one half the system clock, with shift registers 22 and 23 being clocked through inverter 25 in opposite phase to shift registers 20 and 21. The parallel outputs of shift registers 20 and 21 are applied to parallel-parallel shift register 26 for proper timing with the parallel outputs of shift registers 22 and 23. A branch metric calculator 27 of any of conventional designs calculates the branch metric for odd-and even-numbered bits from the parallel data received from shift registers 26, 22 and 23, the output of the branch metric calculator being applied to an adder 28. Adder 28 produces a plurality of groups of branch metric sums, each summing branch metrics of two sequential time slots t(j) and t(j+1). The first group consists of four branch metric sums Z₁₁ (j) + Z₁₁ (j+1) , Z₃₁ (j) +Z₁₁ (j+1) , Z₂₃ (j) +Z₃₁ (j+1) and Z₄₃ (j) +Z₃₁ (j+1) . The second group consists of four branch metric sums Z₁₁ (j) +Z₁₂ (j+1) , Z₃₁ (j) +Z₁₂ (j+1) , Z₂₃ (j) +Z₃₂ (j+1) and Z₄₃ (j) +Z₃₂ (j+1) . The third group consists of four branch metric sums Z₁₂ (j) +Z₂₃ (j+1) , Z₃₂ (j) +Z₂₃ (j+1) , Z₄₃ (j) +Z₄₃ (j+1) and Z₄₄ (j) +Z₄₃ (j+1) , and the fourth group consists of four branch metric sums Z₁₂ (j) +Z₂₄ (j+1) , Z₃₂ (j) +Z₂₄ (j+1) , Z₂₄ (j) +Z₄₄ (j+1) and Z₄₄ (j) +Z₄₄ (j+1) . The branch metric sums are transmitted on conductors 31-34, 41-44, 51-54 and 61-64 to an add-compare-select circuit according to the present invention shown in Figs. 4B and 4C. This ACS circuit generally comprises a pair of identical parts which are respectively shown in Figs. 4B and 4C. The first part is subdivided into first and second ACS units generally shown at 30 and 40, respectively, in Fig. 4B. The first ACS unit 30 derives a path metric for node S₁ (j+1) from path metrics of all the nodes in time slot t(j-1), and the second ACS unit 40 derives a path metric for node S₂ (j+1) from these t(j-1)th time-slot nodes. Likewise, the second part is subdivided into third and fourth ACS units generally shown at 50 and 60, respectively, in Fig. 4C. The third ACS unit 50 derives a path metric for node S₃ (j+1) from path metrics of all the nodes in time slot t(j-1), and the fourth ACS unit 60 derives a path metric for node S₄ (j+1) from these t(j-1)th time-slot nodes. The first ACS unit 30 comprises adders 301, 302, 303 and 304, first comparators 305 and 306, first selectors 307 and 308, second comparator 309 and a second selector 310. Adder 301 reads the path metric M₁ (j-1) of node S₁ (j-1) from metric memory 71 and sums it with branch metric sum Z₁₁ (j) + Z₁₁ (j+1) developed on conductor 31. Adder 302 reads the path metric M₃ (j-1) of node S₃ (j-1) from metric memory 73 and sums it with branch metric sum Z₃₁ (j) + Z₁₁ (j+1) developed on conductor 32. The outputs of adders 301 and 302 are compared by comparator 305 which determines the highest of the two and generates a control signal indicating the path of the selected metric. The control signal from comparator 305 is applied to selector 307 to cause it to pass the highest metric sum to the second comparator 309. Similarly, adder 303 reads the path metric M₂ (j-1) of node S₂ (j-1) from metric memory 72 and sums it with branch metric sum Z₂₃ (j) + Z₃₁ (j+1) developed on conductor 33. Adder 304 reads the path metric M₄ (j-1) of node S₄ (j-1) from metric memory 74 and sums it with branch metric sum Z₄₃ (j) + Z₃₁ (j+1) developed on conductor 34. The outputs of adders 303 and 304 are compared by comparator 306 which determines the highest of the two and generates a control signal indicating the path of the selected metric. The comparator 306 output is coupled to selector 308 to cause it to pass the higher metric sum as a second input to comparator 309. The control signals from comparators 305 and 306 are further applied to a path memory control unit 100 to control the path memory 101 with respect to nodes S₁ (j) and S₃ (j) . The two highest metric sums are compared in comparator 309 and the highest of these sums is selected and passed through second selector 310 to a metric memory 81 of node S₁ (j+1) . Control signal from comparator 309 is delivered to a path memory 101 following the control signals from comparators 305, 306 to control path memory during time slot t(j+1). While metric memories 71 and 81 are shown separately for purposes of explanation, these memories are implemented in a single memory cell so that the previous path metric M₁ (j-1) is updated with the new path metric M₁ (j+1) and this updated version will be read from the memory in the next decoding operation. The second ACS unit 40 comprises adders 401, 402, 403 and 404, first selectors 407 and 408, comparator 409 and selector 410. Adder 401 reads the path metric M₁ (j-1) from metric memory 71 and sums it with branch metric sum Z₁₁ (j) + Z₁₂ (j+1) developed on conductor 41. Adder 402 reads the path metric M₃ (j-1) from metric memory 73 and sums it with branch metric sum Z₃₁ (j) + Z₁₂ (j+1) developed on conductor 42. It will be seen from the foregoing that the determination made by comparator 305 of the first ACS unit 30 can also be used to determine the highest of the outputs of adders 401 and 402. This advantageously eliminates the need for a comparator which would otherwise be coupled to the outputs of adders 401 and 402. Thus, the control signal from adder 305 is applied to selector 407 to pass the higher metric sum to comparator 409. In like manner, adder 403 reads the path metric M₂ (j-1) from metric memory 72 and sums it with branch metric sum Z₂₃ (j) + Z₃₂ (j+1) developed on conductor 43. Adder 404 reads the path metric M₄ (j-1) from metric memory 74 and sums it with branch metric sum Z₄₃ (j) + Z₃₂ (j+1) developed on conductor 44. Since the determination by comparator 306 can also be used to determine the highest of the outputs of adders 403 and 404, the output of comparator 306 is applied to selector 408. Comparator 409 functions in a manner similar to comparator 309 by determining the highest of the outputs of selectors 407 and 408, which is passed through selector 410 to a metric memory 82 which updates the previous path metric with the new path metric M₂ (j+1) . The control signal from comparator 409 is also applied to path memory control 100 to store the most likely path leading to node S₂ (j+1) . The third ACS unit 50, shown in Fig. 4C, is identical in construction to the first ACS unit 30. The functions of adders 501 and 502 are similar to those of adders 301 and 302 with the exception that they receive path metric sums Z₁₂ (j) + Z₂₃ (j+1) and Z₃₂ (j) + Z₂₃ (j+1) developed respectively on conductors 51 and 52 and the functions of adders 503 and 504 are similar to those of adders 303 and 304 with the exception that they receive path metric sums Z₂₄ (j) + Z₄₃ (j+1) and Z₄₄ (j) + Z₄₃ (j+1) developed respectively on conductors 53 and 54. The highest metric sums are determined by comparators 505 and 506 as in the previous description and passed through selectors 507 and 508 to comparator 509. The highest metric sum determined by comparator 509 is a new path metric M₃ (j+1) which is passed through selector 510 and stored into a metric memory 83, updating the previous path metric. The control signals from comparators 505 and 506 are further applied to path memory control unit 100 to control the path memory 101 with respect to nodes S₂ (j) and S₄ (j) . The fourth ACS unit 60 is identical to the second ACS unit 40. The functions of adders 601 and 602 are similar to those of adders 401 and 402 with the exception that they receive path metric sums Z₁₂ (j) + Z₂₄ (j+1) and Z₃₂ (j) + Z₂₄ (j+1) developed respectively on conductors 61 and 62 and the functions of adders 603 and 604 are similar to those of adders 403 and 404 with the exception that they receive path metric sums Z₂₄ (j) + Z₄₄ (j+1) and Z₄₄ (j) + Z₄₄ (j+1) developed respectively on conductors 63 and 64. Control signals indicating the determinations made by comparators 505 and 506 are applied to selectors 607 and 608 which pass the highest of the metric sums to comparator 609. The highest metric sum determined by comparator 609 is a new path metric M₄ (j+1) which is passed through selector 610 and stored into a metric memory 84. The time τ' required to complete the above described operations is given as follows: τ' = τ m + τ a + 2τ c + 2τ s + τ w (2) The maximum bit rate v' is thus given by 2/τ' bits/sec. Assuming that a sum τ m + τ a + τ w is greater than a sum 2(τ c + τ s ), v' is greater than 1.5v. Thus, it is possible to increase the bit rate by more than 1.5 times as higher than the bit rate of the prior art circuit. Summarizing the operation of the present invention, the error correcting apparatus comprises a source (71-74, 81-84) of path metrics associated respectively with states (S₁, S₂, S₃, S₄) in a given time slot t(j-1) of a Viterbi trellis diagram, the path metrics (M i (j-1) , where i=1, 2, 3, 4) being updated sequentially in response to new path metrics, branch metric generating means (20-28) for sequentially generating a branch metric in response to input convolutional code data and providing sums of the branch metrics (Z kℓ (j) +Z mn (j+1) , where k, ℓ, m, n, = 1, 2, 3, 4) on at least two successive branches entering each of the states (S1, S2, S3, S4 of a later time slot t(j+1)). First adder means (301-304, 501-504) is coupled to the source and to the branch metric generating means for adding the updated path metrics to a respective one of the branch metric sums to provide a pair of second sums and second adder means (401-404, 601-604) is coupled to the source and the branch metric generating means for adding the updated path metrics to a respective one of the branch metric sums to provide a pair of third sums. The second and third sums have common branches entering an intermediate time-slot state of the trellis diagram and individual branches diverging from the intermediate time-slot state to the states of the later time slot. First comparing means (305, 306, 505, 506) is coupled to the first adder means for comparing the second sums of each pair to provide a plurality of first control signals each representing the highest of the compared second sums and the highest of the third sums. First selecting means (307, 308, 407, 408, 507, 508, 607, 608) is coupled to the first comparing means (305, 306, 505, 506) for selecting the highest second sums and selecting the highest third sums in response to the first control signals. Second comparing means (309, 409, 509, 609) is coupled to the first selecting means (307, 308, 407, 408, 507, 508, 607, 608) for comparing the selected second sums to provide a plurality of second control signals each representing the highest of the selected highest second sums and comparing the selected third sums to provide a plurality of third control signals each representing the highest of the selected highest third sums. Further provided is a second selecting means (310, 410, 510, 610) coupled to the second comparing means (309, 409, 509, 609) for selecting the highest selected second sums in response to the second control signals for generating first new path metrics and selecting the highest selected third sums in response to the third control signals for generating second new path metrics, the first and second new path metrics being applied to the source for updating previous path metrics. Storage means (100, 101) is coupled to the first and second comparing means for storing data indicating the paths associated with the sums selected in response to the first, second and third control signals. It will be seen from the foregoing that the maximum bit rate can be further increased by simultaneously processing the metrics on three or more consecutive time slots. The foregoing description shows only preferred embodiments of the present invention. Various modifications are apparent to those skilled in the art without departing from the the present invention which is only limited by the appended claims. Therefore, the embodiments shown and described are only illustrative, not restrictive.

Claims: Error correcting apparatus comprising a source of path metrics (71-74, 81-84) which are associated respectively with states in a given time slot of a Viterbi trellis diagram and sequentially updated in response to new path metrics; branch metric generating means (20-28) for sequentially generating a branch metric in response to input convolutional code data and providing a plurality of sums of the branch metrics diverging from the states of said given time slot; adder means (301-304, 401-404, 501-504, 601-604) coupled to said source and to said branch metric generating means for adding the updated path metrics to a respective one of the branch metric sums to provide second sums; first comparing means (305,306,505,506) coupled to said adder means for comparing between said second sums to provide a plurality of first control signals each representing the highest of the second sums; first selecting means (307,308,407,408,507,508,607,608) coupled to said first comparing means for selecting said highest second sums in response to said first control signals, and path memory means (100,101) coupled to said first comparing means for storing data indicating the paths associated with the sums selected in response to said first control signals; characterized in that said branch metric generating means (20-28) derives said branch metric sums from two successive time slots (t j , t j+1 ) of the Viterbi trellies diagram; in that the apparatus further comprises second comparing means (309,409,509,609) coupled to said first selecting means for comparing between the selected highest second sums to provide a plurality of second control signals each representing the highest of the selected highest second sums, and second selecting means (310,410,510,610) coupled to said second comparing means for selecting said highest selected second sums in response to said second control signals for supplying path metrics to said source for updating previous path metrics; and in that said path memory means (100,101) is further coupled to said second comparing means for storing data indicating the paths associated with the sums selected in response to said second control signals. Error correcting apparatus as claimed in claim 1, in which said adder means comprises first and second pairs of adders (301-304) and third and fourth pairs of adders (401-404), the adders of each pair being associated respectively with the states of said given time slot (t j ), and said first, second, third and fourth pairs being associated respectively with the states of subsequent time slot (t j+1 ); and in which the adders of each pair add the updated path metrics of the associated given time-slot states to the branch metric sums associated respectively with different branches diverging from said given time-slot states to the one of the subsequent time-slot states with which said each pair is associated. Error correcting apparatus as claimed in claim 1 or 2, in which the branches associated with the adders of said first and second pairs (301-304) share a common state of the Viterbi trellis diagram in an intermediate time slot with the branches associated with the adders of said third and fourth pairs (401-404). Error correcting apparatus as claimed in claim 1 or 2, in which said first comparing means (305,306,505,506) comprises a pair of first and second comparators (305,306) respectively connected to the outputs of the adders (301-304) of said first and second pairs for generating first and second comparator outputs as said first control signals; and in which said first selecting means (307,308,407,408,507,508,607,608) comprises first and second pairs of selectors (307,308,407,408), the selectors (307,308) of the first pair being connected respectively to the outputs of the adders (301-304) of the first and second pairs and being respectively responsive to said first and second comparator outputs to selectively apply the last-mentioned outputs to said second comparing means (309,409,509,609), the selectors of the second pair (407,408) being connected respectively to the outputs of the adders (501-504, 601-604) of said third and fourth pairs and being respectively responsive to said first and second comparator outputs to selectively apply the last-mentioned outputs to said second comparing means (309,409,509,609).

Inventors: OTANI, SUSUMU
Applicants: NEC CORPORATION
Application year: 1984
Main classification: H03M13
IPC codes: H03M13