PROGRAMMABLE READ-ONLY MEMORY DEVICE

Abstract: A programmable read-only memory device comprises a memory cell transistor (Q₃) which has a source, a drain, a floating gate, and a control gate formed over the floating gate. Programming of the device is performed by applying a high voltage (RWS) to the control gate and a high voltage (CLM) to the drain of the memory cell transistor. The high voltages are applied to the memory cell transistor under the control of respective program signals (DPGM, PGM). The device further comprises means (Q₄-Q₁₁, C₁-C₃) for delaying the program signal (DPGM) for the control gate voltage, relative to the program signal (PGM) for the drain voltage, during the pro­ gramming operation. The application of the programming voltage to the control gate is therefore delayed relative to the application of the programming voltage to the drain, which ensures reliable data writing even if the programming voltage level is less than normal.

Description: This invention relates to a semiconductor memory device and, more particularly, to a programmable read-only memory device wherein each memory cell comprises a transistor (referred to as a floating gate transistor hereinafter) having a floating gate and a control gate formed above the floating gate, and wherein data can be programmed into the floating gate transistor reliably even at a low programming voltage. Recently, the programming voltage for an EPROM (erasable programmable read-only memory) having a floating gate transistor as a memory cell has been lowered. This is mainly because transistors in a peripheral circuit are micropatterned and have a low breakdown voltage to realise a high density memory device, and the programming voltage must be lowered in accordance with such a reduced breakdown voltage. However, when the programming voltage is lowered, the programming current is also reduced, in order to realise a high memory density memory device. As a result, data may not be properly programmed into a memory cell. For this reason, the peripheral circuit or the like must be improved to ensure that data are properly programmed into the corresponding memory cell. In a conventional memory device, data are programmed into a memory cell, i.e. a floating gate transistor, by applying high voltages to the control gate and the drain of the transistor. However, since the timing of the application of the high voltages is not particularly determined, the operation of programming the floating gate transistor is not properly performed, especially when the high voltage is applied to the drain after it is applied to the control gate, or after the control gate voltage becomes relatively high. US-A-4282446 discloses a device designed to overcome problems associated with the resistance of elongated diffused regions used as column lines. A distributed capacitance associated with each cell is charged by the selection of the respective column. Subsequently when the row is selected the capacitance discharges to provide a transitory pulse of programming current for the cell. According to the present invention there is provided a programmable read-only memory device comprising a memory cell transistor having a source, a drain, a floating gate, and a control gate formed above the floating gate, a column line for the memory cell transistor, and delay means for controlling and delaying the timing of the application of a high programming voltage to the control gate relative to that of the application of a high programming voltage to the drain of the memory cell transistor when a data programming operation is performed by applying the high programming voltages to the control gate and the drain of the memory cell transistor, the programming voltage applied to the gate of the memory cell transistor rising gradually, and the column line being arranged to provide a load connected to said drain such that the cell is maintained in a saturation state when a high programming voltage is applied to its control gate. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, wherein Figure 1 is a partial circuit diagram illustrating an equivalent circuit in a programming mode of a general EPROM device; Figure 2 is a cross section of a floating gate transistor used in the device of Figure 1; Figures 3A and 3B are graphs depicting the operating states of the circuit of Figure 1 under different operating conditions; Figures 4, 5 and 6 are circuit diagrams showing various circuit portions of a memory device of one embodiment of the present invention; Figure 7 is a waveform diagram illustrating the operation of the memory device including the circuit portions of Figures 4, 5 and 6; and Figures 8, 9, 10, 11, and 12 are circuit diagrams showing various circuit portions of a memory device as another embodiment of the present invention. Before describing the preferred embodiments, an explanation will be given of the operation of programming a floating-gate transistor used as a memory cell of an EPROM device. Figure 1 shows an equivalent circuit diagram of a conventional EPROM in the programming mode. Referring to Figure 1, the reference symbol Q₁ denotes a data programming transistor, Q₂ denotes a column selection transistor, and Q₃ denotes a memory cell transistor having a floating gate (i.e. a floating gate transistor). These transistors are connected in series between a high voltage V PP , for example 25 V, as a write voltage and a voltage V SS as the ground voltage. A program signal IN is applied to the gate of the transistor Q₁. The program signal IN is set at the high voltage V PP when programming data of logic "O" is supplied. However, the program signal IN is set at the ground voltage when programming data of logic "1" is supplied. A column selection signal CLM is applied to the gate of the transistor Q₂, and a row selection signal RWS is applied to the gate of the floating gate transistor Q₃. These signals CLM and RWS are set at the high voltage V PP when the corresponding column and row are selected in the programming mode. However, when the column and row are not selected in the programming mode, the signals CLM and RWS are set at the ground voltage V SS , i.e. 0 V. The signals CLM and RWS are set at a high level, i.e. V CC (e.g. 5 V), when the corresponding column and row are selected in the read mode. However, when the column and row are not selected in the read mode, these signals CLM and RWS are set at the ground voltage V SS . Figure 2 illustrates a structure of the floating gate transistor Q₃ used in the circuit of Figure 1. The floating gate transistor Q₃ comprises an N + -type source region 1 and an N + -type drain region 2,both formed on a P - -type semiconductor substrate 3, a floating gate 4 made of, e.g., polycrystalline silicon, and formed on the P + -type channel region 5 of the substrate 3 via an insulation layer (not shown), and a control gate 6 made of, e.g., polycrystalline silicon, and formed on the floating gate 4 via an insulation layer (not shown). In order to program data into the floating gate transistor Q₃ in the circuit of Fig. 1, the column selection signal CLM and the row selection signal RWS are set at the high voltage V PP , and the program signal IN is set at the high voltage V PP or the ground voltage V SS of 0V inaccordance with the logical state of the programming data. In particular, when data of logic "0" is programmed, the program signal IN is set at the high voltage V PP , and the transistors Q₁ and Q₂ are turned on. For this reason, the drain and gate of the floating gate transistor Q₃ receive the high voltage V PP . Then, as is well known, electrons are injected into the floating gate of the floating gate transistor Q₃ by avalanche breakdown injection (including so-called channel injection), thereby programming data. That is, in the structure of Fig. 2, when the high voltage is applied to the drain region 2, the drain end of the channel region becomes pinched off due to the pinch-off effect and a depletion region extends between the end of the channel region and the drain. Therefore, the intensity of the electric field of the depletion region becomes very large and carriers in the depletion region are greatly accelerated by the electric field so that hot electrons are generated. In this case, if a high voltage is applied to the control gate 6, the hot electrons are attracted toward and injected into the floating gate 4 by the electric field generated by the high voltage of the control gate 6. In the conventional EPROM, the application timings of the column selection signal CLM and the row selection signal RWS are not specifically controlled in the programming mode. In this case, no problem occurs when the programming voltage V PP is as high as, for example, 25 V, and the breakdown voltages of the transistors Q₁ and Q₂ are sufficiently high. However, when the size of the transistors Q₁ and Q₂ is decreased to realize a high density circuit, the programming current is restricted to a small value, so that a programming operation cannot be properly performed. As shown in Fig. 3A, when the row selection signal RWS increases prior to an increase in the column selection signal CLM and has reached the voltage V PP , voltage-current characteristics between the drain-source path of the transistor Q₃ become as given by curve R₄ in Fig. 3A. In this state, when the column selection signal CLM increases, the characteristics of a load circuit of the transistors Q₁ and Q₂ are shifted upward from those of curves L₁ , L₂ ... and reach those of curve L₄ in Fig. 3A. Assuming that the curve L₄ is given as a load curve when the column selection signal CLM has reached V PP . The voltage cannot reach a programming region WA subjected to avalanche injection of the transistor Q₃ although the column selection signal CLM has reached the high voltage V PP . Therefore, the programming operation cannot be performed. This is because the gate voltage at the transistor Q₃ goes to a high level faster than the drain voltage of the transistor. Thus, the current blowing through the transistor Q₃ becomes excessively large, and the programming current of the transistors Q₁ and Q₂ is limited. As a result, the drain voltage will not be set at a high voltage (programming level), and the aforementioned hot electrons are not generated in the depletion region, so that the so-called avalanche injection or channel injection will not occur. Moreover, even when the row selection signal RWS and the column selection signal CLM simultaneously increase, the programming operation cannot be properly performed for the same reason as described above, if the programming current is not sufficiently large. In applying the present invention, in order to eliminate the problem with the conventional memory device, a column selection signal goes to a high level prior to the rising of a row selection signal, thereby effectively programming data. As shown in Fig. 3B, the column selection signal is increased to V PP and is set in a state indicated by a load curve L₅. In this state, the row selection signal RWS goes to a high level to shift the voltage-current characteristics of the transistor Q₃ upward in the order indicated by curves R₁ , R₂ , and R₃. At the leading edge of the row selection signal RWS, even if the conductance of the transistor Q₂ is small, a sufficiently high voltage (about V PP ) is applied to the drain of the memory cell transistor Q₃. Immediately after the transistor Q₃ is turned on, a parasitic capacitor attributed to the drain of the transistor Q₃ and charged with a sufficiently high voltage is discharged through the transistor Q₃, and thus a larger load of curve L₅ than the steady load of curve L₄ determined by the ON resistance of the transistor Q₂ is present during a transition period due to the parasitic capacitor. Therefore, during the transition period, the operating point of the transistor Q₃ can reach inside a programming region (subjected to avalanche injection or channel injection) WA. When electrons are gradually stored in the floating gate by avalanche injection after the programming operation is started, an electrical field acting from the control gate to the channel region of the memory cell transistor Q₃ decreases, thereby decreasing the conductance. Therefore, even if the ON resistance of the column selection transistor Q₂ is sufficiently high, the self-conductance of the memory cell transistor Q₃ is gradually decreased, so that a high voltage substantially the same as the voltage V PP is gradually applied to the drain of the memory cell transistor Q₃, and the operating point falls within the programming region, thereby performing complete programming. To promote this effect, the row selection signal RWS should have a longer rise time in order to prolong the period of the high-efficiency avalanche injection which occurs immediately after the programming operation is started. Thus, even if a low programming voltage or small programming current is used, the operating point can reach the programming region WA in accordance with the method described above. Figures 4, 5, and 6 show a semiconductor memory device using N-channel MIS transistors according to an embodiment of the present invention. Fig. 4 is a circuit diagram of a delay circuit for delaying a programming instruction signal, i.e., a program signal PGM. This delay circuit comprises inverter transistors Q₄ , Q₅ , ..., and Q₁₁ , and capacitors C₁ , C₂ , and C₃ connected to the output terminals of the respective inverters and power supply V SS . It should be noted that the transistors Q₄ , Q₆ and Q₈ are depletion type. The transistor Q₁₀ comprises a high-withstand voltage depletion type transistor, and the transistor Q₁₁ is a high-withstand voltage enhancement type transistor. Figure 5 shows a unit circuit of a row decoder provided to each row of the memory matrix (not shown). This unit decoder circuit comprises a NOR gate G₁ for receiving a unique combination of noninverted address signals (not shown) and inverted address signals ADD, a high-withstand voltage depletion type transistor Q₁₂, a high-withstand voltage deep-depletion type transistor Q₁₄ , and a high-withstand voltage non-dosed type transistor Q₁₃. The transistor Q₁₄ comprises a transistor having a lower threshold voltage than the conventional depletion transistor. The transistor Q₁₃ has a threshold voltage of 0 V. In the circuit shown in Fig. 5, an output from the gate G₁ goes to a high level when the associated row is to be selected. A row selection signal having the level V CC is applied to the gate of the corresponding memory cell transistor through the transistor Q₁₂. In this case, when a delayed program signal DPGM generated from the circuit of Fig. 4 goes to a level of the high voltage V PP , the transistor Q₁₃ is turned on, and the high voltage V PP is generated as the row selection signal through the transistor Q₁₄. This high voltage signal is cut off by the transistor Q₁₂ from the gate G₁. The row selection signal RWS is set substantially at the V CC level in the read mode and is set at the V PP level in the programming mode. However, when the row is not selected, the output of 0 V from the gate G₁ appears as the row selection signal. The programming high voltage V PP is cut off by the transistor Q₁₄ and will not be applied to the gate G₁. During this operation, the power supply voltage V CC is set to be, for example, 5 V, and the programming high voltage V PP is set to be, for example, 12.5 V. Figure 6 shows the arrangement of a unit column decoder circuit. The unit column decoder circuit comprises a gate G₂ for receiving unique combination of noninverted address signals (not shown) and inverted address signals ADD, a high-withstand voltage depletion type transistor Q₁₅ , a high-withstand voltage non-dosed type transistor Q₁₆ , and a high-withstand voltage deep depletion transistor Q₁₇. The transistors Q₁₇ and Q₁₇ are the same as the transistors Q₁₃ and Q₁₄ of the decoder shown in Fig. 5, respectively. Unlike the decoder circuit in Fig. 5, the gate of the transistor Q₁₆ in the decoder circuit shown in Fig. 6 directly receives the program signal PGM. The operation of the decoder circuit in Fig. 6 is basically the same as that of Fig. 5, in that, when the associated column is to be selected, the output from the gate G₂ goes high, and the program signal PGM is set at the high voltage V PP , thereby generating a column selection signal CLM which is set substantially at the high voltage V PP . In the above description, the program signal PGM is directly applied to the transistor Q₁₆ of the column decoder, and the program signal DPGM delayed by the delay circuit in Fig. 4 is supplied to the gate of the transistor Q₁₃ in the row decoder. Therefore, the leading edge of the row selection signal is delayed from that of the column selection signal. As shown in Fig. 7, the row and column selection signals simultaneously rise to the power supply voltage V CC after the level of the address signal ADD changes, and the program signal PGM then rises. The delayed program signal DPGM rises after short period of time has elapsed from the rise of the program signal PGM. The column selection signal CLM rises from the V CC level to the V PP level, and thereafter, the row selection signal RWS rises from the V CC level to the V PP level. Therefore, the data can be properly programmed even if the programming voltage V PP is relatively low. A semiconductor memory device using a CMIS circuit will be described in accordance with another embodiment of the present invention. Figure 8 shows a delay circuit using a CMIS circuit. This delay circuit corresponds to that shown in Fig. 4. In the circuit shown in Fig. 8, the program signal PGMC is inverted by a CMIS inverter 1 consisting of a P-channel MOS transistor Q₁₈ and an N-channel MIS transistor Q₁₉. The inverted program signal is supplied to a parallel circuit of an N-channel MIS transistor Q₂₀ and a P-channel MIS transistor Q₂₁. The parallel circuit of the transistors Q₂₀ and Q₂₁ serves as a resistor, and this parallel circuit and capacitors C₄ and C₅ constitute an integrator. The inverted program signal is delayed by the integrator and is inverted again by a CMIS inverter 2 consisting of a P-channel MIS transistor Q₂₂ and an N-channel MIS transistor Q₂₃, thereby obtaining a delayed program signal PGMR. Figure 9 shows a power switching circuit for generating an internal power supply voltage V PPI (C) to be supplied to the column decoder. The power switching circuit comprises a CMIS inverter 3 consisting of a P-channel MIS transistor Q₂₄ and an N-channel MIS transistor Q₂₅, high-withstand voltage cut off N-channel MIS transistors Q₂₆ and Q₂₇ , a high-withstand voltage P-channel MIS transistor Q₂₈ , a CMIS inverter 4 consisting of a high-withsand voltage P-channel MIS transistor Q₂₉ and a high-withstand voltage N-channel MIS transistor Q₃₀ , a power supply switch consisting of a high-withstand voltage N-channel non-dosed MIS transistor Q₃₁ and a high-withstand voltage N-channel depletion MIS transistor Q₃₂ , and a CMIS inverter 5 consisting of a P-channel MIS transistor Q₃₃ and an N-channel MIS transistor Q₃₄. When the program signal PGMC is set at a high level, the circuit shown in Fig. 9 is set in the programming mode. In this case an output from the CMIS inverter 3 goes to a low level, and an output from the CMIS inverter 4 goes to a high level. The transistor Q₃₁ is thus turned on. Since an output from the CMIS inverter 5 is set at a low level, the transistor Q₃₂ is turned off. Therefore, the high voltage V PP is applied as the internal high voltage V PPI (C) to the column decoder through the transistor Q₃₁. On the other hand, when the program signal PGMC is set at a low level, an output from the CMIS inverter 3 goes to a high level, and an output from the CMIS inverter 4 goes to a low level, so that the transistor Q₃₁ is cut off. Then an output from the CMIS inverter 5 goes to a high level, and the transistor Q₃₂ is turned on. The power supply voltage V CC is applied to the column decoder through the transistor Q₃₂ , and thus the read operation is performed. In this case, since the output from the CMIS inverter 4 is set at a low level, the transistor Q₂₈ is turned on to completely cut off the transistor Q₂₉. Therefore, the input level of the transistor Q₃₁ is completely set at the power supply voltage V PP. Figure 10 shows a power supply switching circuit for generating an internal power supply voltage V PPI (R) to be supplied to the row decoder. The circuit in Fig. 10 has the same arrangement as shown in Fig. 9 and comprises a CMIS inverter 6 composed of the transistors Q₃₅ and Q₃₆ , a separator for transistors Q₃₇ and Q₃₈, a CMIS inverter 7 composed of the transistors Q₃₉, Q₄₀ , and Q₄₁ , a power supply switch for transistors Q₄₂ and Q₄₃ , and a CMIS inverter 8 composed of transistors Q₄₄ and Q₄₅. The operation of the circuit in Fig. 10 is substantially the same as that of Fig. 9, except that the delayed program signal PGMR from the circuit of Fig. 8 is supplied to the CMIS inverters 6 and 8. Therefore, the internal power supply voltage V PPI (R) from the circuit of Fig. 10 is slightly delayed from the internal power supply voltage V PPI (C) from the circuit in Fig. 9. Figure 11 shows a unit row decoder circuit provided to each row of the memory matrix. This unit row decoder circuit comprises an OR gate G₃ , a high-withstand voltage N-channel MIS transistor Q₄₆ , a high-with-stand voltage P-channel MIS transistor Q₄₇ , and a CMIS inverter 9 consisting of a high-withstand voltage P-channel MIS transistor Q₄₈ and a high-withstand voltage N-channel MIS transistor Q₄₉. When the associated row is selected, an output from the gate G₃ in the unit row decoder circuit in Fig. 11 goes to a low level, and an output (i.e., the row selection signal RWS) from the CMIS inverter 9 goes to a high level. In this case, when the memory device is set in the programming mode, the internal power supply voltage V PPI (R) from the power supply switching circuit in Fig. 10 is set at the high voltage V PP , so that the row selection signal RWS becomes substantially the same as the high voltage V PP . On the other hand, in the read mode, the internal power supply voltage V PPI (R) becomes substantially the same as the power supply voltage V CC . Therefore, the row selection signal RWS becomes substantially the same as the power suplly voltage V CC . In this case, the transistor Q₄₇ is kept turned off. When the row is not selected, an output from the gate G₃ goes to a high level, and the row selection signal RWS goes to a low level. In this case, the transistor Q₄₇ is turned on and the input terminal of the CMIS inverter 9 rises. Therefore, the row selection signal RWS is completely clamped to a low level. Figure 12 shows the arrangement of a unit column decoder circuit. This unit column decoder circuit has the same arrangement as the row decoder circuit of Fig. 11, except that the power supply voltage V PPI (C) supplied from the power supply switching circuit in Fig. 9 is used as the internal power supply voltage. As is apparent from the circuits shown in Figs. 11 and 12, the row selection signal RWS is slightly delayed from the column selection signal CLM. Thus, even if the programming voltage V PP is low, data can be properly programmed. According to the present invention, since the high voltage applied to the control gate of the floating gate transistor is delayed from the high voltage applied to the drain, data can be properly programmed even if the programming voltage is low, the sizes of the peripheral transistors can be decreased, and hence a highly integrated memory can be obtained.

Claims: A programmable read-only memory device comprising a memory cell transistor (Q₃) having a source (1), a drain (2), a floating gate (4), and a control gate (6) formed above the floating gate, a column line for the memory cell transistor (Q₃), and delay means (Q₄-Q₁₁, C₁-C₃) for controlling and delaying the timing of the application of a high programming voltage (V PP ) to the control gate (6) relative to that of the application of a high programming voltage (V PP ) to the drain of the memory cell transistor when a data programming operation is performed by applying the high programming voltages to the control gate and the drain of the memory cell transistor, the programming voltage applied to the gate (6) of the memory cell transistor (Q₃) rising gradually, and the column line being arranged to provide a load connected to said drain such that the cell is maintained in a saturation state when a high programming voltage (V PP ) is applied to its control gate (6). A memory device according to claim 1, characterised by means (G₂,Q₁₅-Q₁₇) for generating a column selection signal (CLM) which applies the high programming voltage to the drain of the memory cell transistor of a selected column under the control of a program signal (PGM); and means (G₁,Q₁₂-Q₁₄) for generating a row selection signal (RWS) which applies the high programming voltage to the control gate of the memory cell transistor of a selected row under the control of a delayed program signal (DPGM). A memory device according to claim 2, characterised in that the delay means (Q₄-Q₁₁, C₁-C₃) delays the program signal (PGM) to generate the delayed program signal (DPGM). A memory device according to claim 2 or claim 3, characterised in that the means for generating a row selection signal (RWS) comprises a gate circuit (G₁) for decoding input row addresses (ADD); a first high withstand voltage depletion type transistor (Q₁₂) the source of which is connected to the output of the gate circuit and the gate of which receives a power supply voltage (V CC ); and a series connection of a second high withstand voltage non-dose type transistor (Q₁₃) the gate of which receives the delayed program signal (DPGM) and a third high withstand voltage deep depletion type transistor (Q₁₄) the gate and source of which are interconnected, the series connection being inserted between a high voltage power supply voltage (V PP ) and the drain of the first transistor. A memory device according to claim 2 or claim 3, characterised in that the means for generating a column selection signal (CLM) comprises a gate circuit (G₂) for decoding input column addresses (ADD); a first high withstand voltage depletion type transistor (Q₁₅) the source of which is connected to the output terminal of the gate circuit and the gate of which receives a power supply voltage (V CC ); and a series connection of a second high withstand voltage non-dose type transistor (Q₁₆) the gate of which receives the program signal (PGM) and a third high withstand voltage deep depletion type transistor (Q₁₇) the gate and source of which are interconnected, the series connection being inserted between a high voltage power supply voltage (V PP ) and the drain of the first transistor. A memory device according to any preceding claim, characterised in that the delay means comprises one or more inverters (Q₄,Q₅;Q₆,Q₇;Q₈,Q₉;Q₁₀,Q₁₁) connected in cascade, and one or more capacitors (c₁,C₂,C₃) each connected to the output of a respective one of the inverters. A memory device according to claim 1, characterised in that the memory device further comprises means (G₄,Q₅₀-Q₅₃) for generating a column selection signal (CLM) which applies a high programming voltage to the drain of the memory cell transistor of a selected column; a first power switch circuit (Q₂₄-Q₃₄) for generating an internal power supply voltage (V PPI (C)) which is fed to the column selection signal generating means under the control of a program signal (PGMC); means (G₃,Q₄₆-Q₄₉) for generating a row selection signal (RWS) which applies a high programming voltage to the control gate of the memory cell transistor of a selected row; and a second power switch circuit (Q₃₅-Q₄₅) for generating an internal power supply voltage (V PPI (R)) which is fed to the row selection signal generating means under the control of a delayed program signal (PGMR). A memory device according to claim 7, characterised in that the delay means (Q₁₈-Q₂₃) delays the program signal (PGMC) to generate the delayed program signal (PGMR). A memory device according to claim 8, characterised in that the delay means comprises an integration circuit having a parallel connection of an N-channel MIS taransistor (Q₂₀) and a P-channel MIS transistor (Q₂₁) inserted between an input and an output of the integration circuit, and capacitor means (C₄,C₅) connected between the output and a power source. A memory device according to any one of claims 7 to 9, characterised in that the first power switch circuit comprises first and second high withstand voltage transistors (Q₃₁,Q₃₂) which are alternatively turned on by the program signal (PGMC), the first high withstand voltage transistor (Q₃₂) supplying a high internal power supply voltage (V PPI (C)) to the column selection signal generating means when it is turned on, and the second high withstand voltage transistor (Q₃₂) supplying a low internal power supply voltage (V CC ) to the column selection signal generating means when it is turned on. A memory device according to any one of claims 7 to 9, characterised in that the second power switch circuit comprises first and second high withstand voltage transistors (Q₄₂,Q₄₃) which are alternatively turned on by the delayed program signal (PGMR), the first high withstand voltage transistor (Q₄₂) supplying a high internal power supply voltage (V PPI (R)) to the row selection signal generating means when it is turned on, and the second high withstand voltage transistor (Q₄₃) supplying a low internal power supply voltage (V CC ) to the row selection signal generating means when it is turned on. A memory device according to any one of claims 7 to 11, characterised in that the means for generating a row selection signal (RWS) comprises a gate circuit (G₃) for decoding input row addresses (ADD), a first high withstand voltage type transistor (Q₄₆) the soruce of which is connected to the output of the gate circuit and the gate of which receives a power supply voltage (V CC ); a CMIS inverter comprising high withstand voltage MIS transistors (Q₄₈,Q₄₉) the input of which is connected to the drain of the first transistor (Q₄₆) and which is operated by the internal power supply voltage (V PPI (R)) supplied from the second power switch circuit (Q₃₅-Q₄₅); and a second high withstand voltage type transistor (Q₄₇) which is connected between the second power switch circuit and the drain of the first transistor (Q₄₆) and the gate of which receives the output signal (RWS) of the CMIS inverter. A memory device according to any one of claims 7 to 12, characterised in that the means for generating a column selection signal (CLM) comprises a gate circuit (G₄) for decoding input column addresses (ADD); a first high withstand voltage type transistor (Q₅₀) the source of which is connected to the output of the gate circuit and the gate of which receives a power supply voltage (V CC ); a CMIS inverter comprising high withstand voltage MIS transistors (Q₅₂,Q₅₃) the input of which is connected to the drain of the first transistor (Q₅₀) and which is operated by the internal power supply voltage (V PPI (C)) supplied from the first power switch circuit (Q₂₄-Q₃₄); and a second high withstand voltage type transistor (Q₅₁) which is connected between the first power switch circuit and the drain of the first transistor (Q₅₂) and the gate of which receives the output signal (CLM) of the CMIS inverter.

Inventors: TSUCHIDA, MANABU, YOSHIDA, MASANOBU
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: G11C17
IPC codes: G11C17, G11C16