METHOD OF CONTROLLING A DOMESTIC APPLIANCE

Abstract: In a domestic appliance, such as a washing machine, which is controlled by a solid state processor 1, failure of the mains supply causes the loss of programme-identifying data held in the processor store. A back-up non-volatile store 11 keeps track of the programme status and enables the programme to be continued from where it left off in the event of interruption of the power supply. The arrangement is such that possible corruption of the store contents by the hostile environment is minimal.

Description: This invention relates to a method of controlling a domestic appliance powered from an electric mains supply, in which method a solid state processor processes in succession N potential operating steps of the appliance and thereby controls the appliance to implement a sequence of operating steps selected from these N steps in accordance with a programme selected by a user, a specific data value being stored in a back-up memory as each potential operating step is processed to enable the processing to be continued from the potential operating step reached in the event of a temporary supply failure and a start-up routine being run before any potential operating step is processed to check a test code preloaded into said back-up memory for corruption. The invention also relates to a domestic appliance, such as a washing machine, having means for performing such a method. A problem that can arise in an appliance which is controlled by a solid state processor, e.g. a microprocessor, to perform a sequence of routines is that any failure of the power supply to the processor during a programme results in the destruction of the data in the processor identifying the programme in progress. This means that, when the power supply is restored, the programme has to be restarted from the beginning and that some of the programme steps are repeated unnecessarily. It is known from U.K. Patent Specification No. 1,529,691 to provide the apparatus with a power failure detector and a data-salvaging store to which all the data necessary for the subsequent continuation of the programme are rapidly transferred and in which they are stored if, and only if, a power failure is detected. If the power supply is re-established within a short period, e.g. a few seconds, the programme continues from the point at which it was interrupted. The data-salvaging store may be a permanent (not-volatile) store or may be powered by a capacitor which, in operation of the apparatus, is charged by a current derived from the mains power supply. This means that the power has to be restored within the discharge time constant of the capacitor in order to enable all the data in the temporary salvage store to be read back and stored by the processor. The object of that arrangement is to cater for momentary failure of the power supply, particularly during unattended operation, such that the programme can continue after a brief interruption from where it left off, even though the programme details and status have been lost from the processor. If the power is not restored during this period, the programme is started from the beginning when the power is subsequently restored. Solid state processors such as microprocessors can, however, be affected in severe environments in that the data stored therein can be corrupted by various forms of interference such as voltage spikes, static, and the switching of inductive loads such as motors, solenoids, and electromagnetic relays. Such corruption, e.g. to the programme counter, can result in incorrect programme operation. Thus any power supply interference which results in immediate salvaging of the data may also have corrupted that data before, or during, the salvage operation. The interference can be particularly severe if power is being supplied to inductive devices at the instant the power is disconnected. In this case corruption of the data can be caused by the original interference and additionally by the consequent, and subsequent, large voltage spikes caused by breaking inductive circuits. The corruption may be such that the processor is still able to run although the data stored in its random access memory (RAM), programme counter, etc., is corrupt. This will result in an incorrect programme being run by the processor, with possibly disastrous results. Patent specification EP-A2-27432 discloses a method as defined in the first paragraph, i.e. a method in which the above disadvantages are mitigated to some extent in that a record of the processing stage reached by the processor is maintained continuously in a back-up store as the operation of the appliance proceeds. This record takes the form of a data value stored at a single location, this value being periodically updated and thus being still susceptible to some extent to unforeseen corruption. A similar such record is maintained in a method disclosed in DE-A-2818269. An object of the invention is at least to reduce the possibility of corruption and, hence, its adverse effects. According to one aspect of the invention, a method as set forth in the first paragraph is characterized in that the relevant potential operating step and, if no corruption of the test code is found during the running of the start-up routine, (a) the said storage locations are read in sequence to determine whether data stored in each has a predetermined value which is different from the specific data value which becomes stored therein as the corresponding operating step is processed, and either (b1) if none of said respective storage locations contains data which has the relevant said predetermined value, then data having the relevant said predetermined value is stored in each said storage location and the processing is started from the first potential operating step of the succession, or (b2) if a said storage location is reached which contains data having the relevant said predetermined value, then the processing is started from the corresponding potential operating step of the succession. According to a further aspect of the invention, there is provided a domestic appliance which is operable from an electric mains supply (3) and is provided with control means including a solid state processor (1) and a back-up memory (11), said processor being programmed to process in succession N potential operating steps of the appliance and thereby control the appliance to implement a sequence of operating steps selected from these N steps in accordance with a programme selected by a user, to cause a specific data value to be stored in said back-up memory as each potential operating step is processed to enable the processing to be continued from the potential operating step reached in the event of a temporary supply failure, and to run a start-up routine before any potential operating step is processed to check a test code preloaded into said back-up memory for corruption, characterized in that the back-up memory includes a respective storage location corresponding to each said potential operating step and in that the processor is programmed (a) to cause the specific data value to be stored each time in the said respective storage location corresponding to the relevant potential operating step, (b) if no corruption of the test code is found during the running of the start-up routine, to read the said respective storage locations in sequence to determine whether data stored in each has a predetermined value different from the specific data value which becomes stored therein as the corresponding operating step is processed, and either (c1) if none of said respective storage locations contain data which has the relevant said predetermined value, to store data having the relevant said predetermined value in each said storage location and cause the processing to be started from the first potential operating step of the succession, or (c2) if a said storage location is reached which contains data having the relevant said predetermined value, to cause the processing to be started from the corresponding potential operating step of the succession. An embodiment of the invention will now be described with reference to the accompanying drawings, of which:- Figure 1 is a block schematic circuit diagram of control apparatus including a processor, Figure 2 is a memory map of the non-volatile memory 11 shown in Figure 1, Figure 3 is a flow diagram showing the main programme procedure, and Figure 4 is a flow diagram showing the start-up routine. In Figure 1 a microprocessor 1 is powered from a D.C. supply 2 fed from an A.C. mains supply 3. Input commands to the microprocessor are fed via a bus 4 from a control panel 5. The control output of the microprocessor 1 is fed to the apparatus 6 to be controlled via a bus 7. The apparatus may, for example, be a washing machine in which the control panel 5 comprises a number of push-buttons by means of which the user selects a particular one of several alternative main programmes and also decides upon options within the selected main programme, such as pre-wash, cold wash, and spin delay. The control panel may also accommodate visual indicators which, for example, may indicate the selected programme, the appropriate options for the selected programme, the progress of the programme, and fault conditions. For these functions, information may be fed from the microprocessor via a bus 8. The controlled apparatus 6 may comprise one or more motors, solenoids, electromagnetic relays, and/or valves. Examples of the control panel 5 and washing machine 6 can be found in the above-mentioned U.K. patent 1529691. The particular arrangements of the control panel and the apparatus are not relevant to the invention, however, and will not be detailed further. Microprocessor 1 has a write output 9 to a non-volatile memory, such as a random access memory (RAM), 11 and a read input 12 from RAM 11. RAM 11 is provided with a D.C. supply 13, comprising for example a small rechargeable battery trickle-charged from the A.C. mains supply. The operation of the circuit shown in Figure 1 will now be explained with reference to Figures 2, 3 and 4. In Figs. 3 and 4 the various boxes have the following significances. Fig. 3. 300 - Start 301 - Programme select. 302 - Programme selected? 303 - Run pressed? 304 - Load RAM locations 1 to 72 and status words. 305 - Step required? 306 - Main programme. 307 - Clear step in RAM. 308 - Increment step counter. 309 - Step 72? 310 - Finish routine. Fig. 4. 400 - Reset. 401 - Test RAM 11 for corruption. 402 - Test clear? 403 - Set N to 1. 404 - Read location "N" in RAM 11. 405 - Data read = 0? 406 - Data read = H? 407 - Increment N. 408 - N greater than 72? 409 - Jump to programme select. 410 - Set main programme step counter to N. 411 - Read and store status words. 412 - Return to main programme. 413 - Write all "0"s to RAM 11. 414 - Read RAM. 415 - All "O"s read? 416 - Fault routine. 417 - Write all "1"s to RAM. 418 - Read RAM. 419 - All "1"s read? 420 - Load RAM test code. It is first assumed that any of the selectable programmes and options may be run by the microprocessor by selection from N = 72 basic step routines held in a read-only memory (ROM) portion, not shown, of the processor. Thus the main programme facilities are written into a total of 72 operating steps. As each step is completed, a step counter is incremented by 1 and, by referring to a look-up table, a check is made to see if the next sequential step is required for that particular selected programme and options. If not, the step counter is further incremented and the check is again made. The programme is terminated after step 72. RAM 11 has 72 corresponding locations 1 to 72 (Figure 2). It has two further locations 80, 81 for programme status words and a further 32 locations 96 to 127 which are designated as a RAM test area. The status words identify the particular programme and options selected by the user on control panel 5. The addresses 96 to 127 are loaded with test code, for example alternate 0's and 1's. This test code is loaded during the first start-up routine, which will be described below. Referring now to Figure 3, the user switches on the machine and selects the programme and options. On start-up, the routine checks that a programme has been selected and then waits for the user to operate the "RUN" button to start the programme running. When this is done, RAM locations 1 to 72 are each loaded with their respective location (address) numbers and locations 80 and 81 are loaded with the programme status words. Thus RAM 11 is loaded with the relevant data before any operating step is performed in the main programme. The processor then checks against the look-up table (e.g. an internal read-only memory) to see if the first operating step is required in the main programme. If "yes", then this step is carried out in the main programme and the first RAM location (1) is cleared to 0. If "no" then location 1 is cleared without step 1 being included in the main programme. The counter is then incremented and the process repeated one step at a time until all 72 steps have been processed, whereupon the routine is terminated. At the end of the whole routine, all the 72 step locations in RAM 11 will have been cleared to zero unless there has been a mains supply interruption or other interference. On initial power-up, the start-up routine shown in Figure 4 is run. RAM 11 is first tested for possible data corruption by checking the test code stored in locations 96-127. The check may be effected by a simple correlation method or by a sequence test which checks the code for alternate 0's and 1's. Obviously, other test codes could equally well be used, such as the all-1's code in which the correlator is merely an AND gate. It is preferred, however, to have both 0's and 1's in the code. If the test reveals corruption of the test code, then a further test is carried out which loads up the test code locations with one or more check codes and then reads the check codes to see if they are correctly loaded. For example the all-0's code may be written into the test area locations and the stored code then read from the RAM. If the correct all-0's code is read, then the all-1's code may be stored and, if this is also read satisfactorily, then it is assumed that there is no permanent fault on the RAM and, after loading the test code into the RAM, the start-up routine then jumps (point A) to the programme select stage shown in Figure 3. Thus if a corrupted test code is found in the RAM, the main programme is started from the beginning irrespective of whether or not there has been a mains failure. The reason for this is that if the RAM test code has been corrupted then it is very likely that data in the process has also been corrupted. It is therefore safer to start the new programme from the beginning rather than from a possibly corrupted, and hence arbitrary, starting point. Alternatively, of course, a "yes" response to the "all-1's read" stage could return the start-up routine to the "set N to 1" stage. If the all-0's and all-1's codes are not read satisfactorily, it is assumed that the RAM has an inherent fault and a fault routine comes into operation. This routine would generally cause an audible and/or visible alarm to be given and prevent further operation of the apparatus. It will be appreciated from the above that the test code is automatically loaded into RAM 11 when power is first applied to the appliance. It should be noted that the RAM is tested and loaded before any of the main programme steps is implemented. As explained above, the reason for this is that the stored data is then less likely to be corrupted by, for example, the switching on or off of an electromagnetic relay, pump, or motor. If the RAM corruption test is clear, the data stored at each of the 72 locations of RAM 11 is next tested in sequence by means of a local N-counter which is first set to location 1. If the previous programme has run satisfactorily, the data stored at every location 1 to 72 will be zero since each location is cleared to zero in sequence during the running of the main programme. If, however, there has been a mains failure or switch-off during any step in the running of the previous programme, then the preceding RAM locations would contain zeros and the subsequent locations would still contain their respective addresses. This situation is shown in Figure 2, in which steps 1 to 4 are assumed to have been completed satisfactorily in the previous programme. The data in each of the locations 5 to 72 still corresponds to the respective address, however, and this indicates that these steps were subsequent to the mains failure and were not included in the previous programme. The data at location 4 has been corrupted for some reason or other but, since such corruption can substantially only occur while this location is being addressed (i.e. cleared to zero), it is assumed that the corresponding programme step has been satisfactorily completed. Returning now to Figure 4, with the N-counter set to N=1, location 1 is read. The zero at this location (Figure 2) indicates that this step was performed in the previous programme. The counter is therefore incremented to N=2 and, since N is less than 72, location 2 is read. The process is repeated until step N=4 is reached. The data (13) at this location is neither N (i.e. 4) nor zero and is therefore false. This could have been caused for example by a failure or disturbance during the clearing of the location to zero when step 4 has been performed during the previous programme. Since the data read is neither zero nor N, it is ignored and the N-counter is incremented to step N=5. The data at location 5 is still at N=5 and has not been cleared to zero during the previous programme. Therefore step 5 is the first step that had not been performed in the previous run. The main programme step counter in the processor is now set to 5, the status words are then read and stored in the RAM, and the routine is transferred (point B) to the main programme (Figure 3) which then determines if this step is required. In this manner the earlier programme, during which a mains failure occurred, is now completed automatically without needing the attention of the user. Summarising the operation, the non-volatile memory contains a map of the requested programme information to run and each stage is cleared on completion. During the initial power-up stage, the memory is first read for a previous power supply interruption and, if there has been an interruption, the programme is re-established to continue from where it was discontinued by the interruption. In order to maintain the information stored in RAM 11 when the supply is interrupted, it is provided with its own D.C. power supply 13. The supply 13 may, for example, comprise a rechargeable battery which is trickle-charged, for example, from supply terminal 2. The current taken by the memory 11 is very small and the battery can have a relatively low storage capacity. In a particular embodiment, microprocessor 1 was Philips Type MAB 8400B and RAM 11 was Philips Type PCD 8571. Whilst in the embodiment the step locations are each pre-loaded with their own addresses and then cleared to zero as each step is implemented. This is a matter of convenience and alternative data can of course be used. All that is necessary is that the data at each RAM location is changed from one value to a predetermined different value as each step is satisfactorily implemented. If the user wishes to change a programme during operation and switches off the machine to cancel the existing programme, then on switching on the machine the programme will automatically start from the step at which the previous programme was terminated. This is entirely satisfactory in the most common case where the user wishes to alter a subsequent step in the programme being run, for example to change the spin-drying time. On the other hand, it is possible that the user may select a programme and, having started the programme, decide that a different programme is required - for example to add a pre-wash stage. To provide for the facility, a user-operator escape routine may be included in which the contents of the RAM 11, apart from the test locations, are cleared. This may be achieved, for example, by the provision of a programme CANCEL button which, when operated by the user, clears the RAM. In order to avoid the need for providing a CANCEL button in addition to the RUN button, the latter can conveniently be used for both purposes. Thus, for example, the processor or other timer may be used to detect whether the RUN button is operated for a period of less than or greater than 5 seconds, for example. If the button is held operated for more than 5 seconds then the RAM clearing routine is initiated.

Claims: A method of controlling a domestic appliance (6) powered from an electric mains supply (3), in which method a solid state processor (1) processes in succession N potential operating steps of the appliance and thereby controls the appliance to implement a sequence of operating steps selected from these N steps in accordance with a programme selected by a user, a specific data value being stored in a back-up memory (11) as each potential operating step is processed to enable the processing to be continued from the potential operating step reached in the event of a temporary supply failure and a start-up routine being run before any potential operating step is processed to check a test code preloaded into said back-up memory for corruption, characterized in that the specific data value is stored each time in a respective storage location of the back-up memory corresponding to the relevant potential operating step and, if no corruption of the test code is found during the running of the start-up routine, (a) the said storage locations are read in sequence to determine whether data stored in each has a predetermined value which is different from the specific data value which becomes stored therein as the corresponding operating step is processed, and either (b1) if none of said respective storage locations contains data which has the relevant said predetermined value, then data having the relevant said predetermined value is stored in each said storage location and the processing is started from the first potential operating step of the succession, or (b2) if a said storage location is reached which contains data having the relevant said predetermined value, then the processing is started from the corresponding potential operating step of the succession. A method as claimed in Claim 1, wherein each said predetermined value is the address of the relevant storage location and each said specific data value is zero. A method as claimed in Claim 1 or Claim 2 in which, if corruption of the test code is found, operation of the back-up memory is tested by writing a check code into the memory, reading out the check code and, if the correct code is not read out, initiating a failure routine in which further operation of the appliance is prevented. A method as claimed in Claim 3 in which, if the correct code is read out, the test code is written into the memory and the failure routine is not initiated. A domestic appliance (6) which is operable from an electric mains supply (3) and is provided with control means including a solid state processor (1) and a back-up memory (11), said processor being programmed to process in succession N potential operating steps of the appliance and thereby control the appliance to implement a sequence of operating steps selected from these N steps in accordance with a programme selected by a user, to cause a specific data value to be stored in said back-up memory as each potential operating step is processed to enable the processing to be continued from the potential operating step reached in the event of a temporary supply failure, and to run a start-up routine before any potential operating step is processed to check a test code preloaded into said back-up memory for corruption, characterized in that the back-up memory includes a respective storage location corresponding to each said potential operating step and in that the processor is programmed (a) to cause the specific data value to be stored each time in the said respective storage location corresponding to the relevant potential operating step, (b) if no corruption of the test code is found during the running of the start-up routine, to read the said respective storage locations in sequence to determine whether data stored in each has a predetermined value different from the specific data value which becomes stored therein as the corresponding operating step is processed, and either (c1) if none of said respective storage locations contain data which has the relevant said predetermined value, to store data having the relevant said predetermined value in each said storage location and cause the processing to be started from the first potential operating step of the succession, or (c2) if a said storage location is reached which contains data having the relevant said predetermined value, to cause the processing to be started from the corresponding potential operating step of the succession. A domestic appliance as claimed in Claim 5, wherein the back-up memory comprises a random access memory having its own power supply. A domestic appliance as claimed in Claim 6, wherein said power supply comprises a re-chargeable battery which, in operation of the appliance, is retained in the charged state via a trickle-charger which derives a charging current from the mains supply to the appliance.

Inventors: EASTHILL, STEPHEN PAUL
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN, PHILIPS ELECTRONIC AND ASSOCIATED INDUSTRIES LIMITED
Application year: 1984
Main classification: G05B19
IPC codes: G05B9, G05B19