MAJORITY CIRCUIT

Abstract: A majority circuit is provided with a plurality of memor­ ies in which predetermined data is written, and a plurality of gates. Composite parity check bits are divided into a plurality of sets corresponding to the number of memory address bits. The divided composite parity check bits are supplied to the corresponding addresses in the memories. An output from each of the memories is supplied to the associated gate to decode the composite parity check bits. A threshold value is judged from an output of the gate.

Description: TECHNICAL FIELD This invention relates to the detection of a threshold value in an error correction circuit. BACKGROUND ART In a character and picture image information system such as videotex, teletext and the like, when a character multiplexing of a code system is carried out, it is proposed that the (272, 190) majority-logic decodable code is used to carry out the error correction. The (272, 190) majority-logic decodable code represents that one data packet is formed of 272 bits, in which 190 bits are assigned to information bits and remaining 82 (= 272 - 190) bits are assigned to error correction parity bits. However, when the (272, 190) majority-logic decodable code is used, upon decoding, the parity check is carried out by parity check bits of 17 bits, A1 to A17. Thus, the majority logic circuit must identify whether the number of the bit "1" in the parity check bits of 17 bits, A1 to A17 is not less than 10 or not. As a result, the majority logic circuit must form a logic circuits for all different combinations expressed as ₁₇C₁₀ mathematically, or 19448 different combinations, thus a great number of AND circuits and OR circuits being required. Further, an IC on the market is generally two-input or four-input AND circuits and OR circuits and 17-input AND circuit and OR circuit are not available. Therefore, in practice, the majority logic circuit requires much more AND circuits and OR circuits and this is disadvantageous in a manufacturing cost and size or power consumption standpoint. In addition, if the number of the AND circuits and the OR circuits used is increased, the processing speed of the majority logic circuit becomes low on the whole and this is not preferable in view of reliability. For this reason, this invention is to provide a majority logic circuit of a very simple circuit arrangement. U.S. Patent N o 3 873 971 relates to an error correcting system capable of correcting two out of any twelve information and parity bits having an encoder and a decoder. The encoder comprises a six stage shift register. The first, second, third and sixth stages of which are coupled to a modulo 2 adder which combines the first, fourth, fifth and sixth bits of each six bit group of information digits applied to the register. A switch connected to the shift register and the modulo 2 adder alternately applies the information bits and parity bits generated by the modulo 2 addition to a recording medium or to a transmission channel such as a telephone line or a radio link. The decoder circuit utilizes also a six stage shift register and modulo 2 adder similar to that used in the encoder. The received information bits are applied to the six stage shift register-modulo 2 adder combination to generate a locally generated parity bit which is modulo 2 combined with a received parity bit to provide a syndrome bit. The syndrome bits are applied to a second six stage shift register having a first modulo 2 adder connected to the first and second stages thereof and a second modulo 2 adder connected to the third and fourth stages thereof. A majority logic circuit is connected to the outputs of the first and second modulo 2 adders and to the fifth and sixth stages of the syndrome shift register. If the number of ones applied to the majority logic circuit is less than two, no correction is made, however, if the number of ones is greater than two, a correction signal is generated to reverse the polarity of the information bit emerging from the last stage of the information shift register and to further correct the bits in the first, fourth and fifth stages of the syndrome register to correct the syndrome bits present therein to assure proper correction of subsequent errors. IEEE Transactions on Computers, vol. C-21, N o 2, February 1972 pertains to a synthesis procedure for failure-tolerant sequential circuits using error correcting codes. It is shown that replication redundancy is more reliable and more simply implemented than coding redundancy. The present invention relates to a majority logic circuit for identifying a threshold value of the parity check bits comprising : a plurality of memory means in which predetermined data are written ; means for grouping said incoming parity check bits into a plurality of groups greater than two ; a plurality of first gate means divided into a plurality of groups greater than one each of said first gate means being supplied with selected outputs of said memory means ; and second gate means supplied with all outputs of said first gate means for generating an identifying signal corresponding to a threshold value of the parity check bits ; characterized by supplying all of said plurality of groups less one of said plurality of check bits to address bits of said plurality of memory means and to said plurality of groups of said first gate means whereby the remaining one of said parity check bits is supplied directly to selected one of said plurality of groups of said first gate means without being supplied to said plurality of memory means. In consequence, according to this invention, it is possible to construct a majority logic circuit by several memories and several gate ICs. Further, since a memory and gate IC on the market can be used as those of the majority logic circuit, the majority logic circuit can be made at low cost. Furthermore, since the majority logic circuit can be formed of several memories and several gate ICs, its space factor is excellent and the power consumption can be reduced. In addition, since the number of the circuit stages in the majority logic circuit is small, the processing speed thereof is high and the reliability thereof is satisfactory. BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a circuit diagram showing an embodiment of a majority logic circuit according to this invention and Fig. 2 is a diagram useful for the explanation thereof. Reference numerals 1 and 2 designate ROMs and reference numerals 301 to 315 and 4 designate gates. BEST MODE FOR CARRYING OUT THE INVENTION Fig. 1 shows an embodiment of this invention. In Fig. 1, reference numerals 1 and 2 respectively designate 8 bit-256 bytes (256 addresses) ROMs. Data stored in the ROMs 1 and 2 are same to each other and the data stored at the respective addresses are as shown in Fig. 2. When the address bits of the ROMs 1 and 2 are taken as AD7 to AD0 and the data bits thereof are taken as D7 to D0, if the number of the bits "1" in the address bits AD7 to AD0 is taken as N, N less significant bits of the data bits D7 to D0 are set to "1". In other words, data DATA expressed as DATA = 2 N - 1 are stored at the addresses thereof. For example, since three (N = 3) bits of the address bits AD3, AD2 and AD0 are "1" at address 13, three less significant bits D2, D1 and D0 of the data bits D7 to D0 are set to "1" and hence data expressed as 2³ - 1 = 7 is stored at the address. Parity check bits A1 to A17 are grouped into 8 bits, 8 bits and 1 bit in response to the ROMs 1 and 2, for example, the parity check bits A1 to A8, A9 to A16 and A17. The parity check bits A1 to A8 are supplied to the address bits AD0 to AD7 of the ROM 1 and the parity check bits A9 to A16 are supplied to the address bits AD0 to AD7 of the ROM 2. Further, one of the data bits D7 to D0 of the ROM 1, one of the data bits D7 to D0 of the ROM 2 and the parity check bit A17 are connected to NAND circuits 301 to 315 as follows. If the suffix of the data bits D7 to D0 of the ROM 1 is taken as i , the suffix of the data bits D7 to D0 of the ROM 2 as j , k = 0 when the address bit A17 is not connected and k = 1 when the address bit A17 is connected, the connection thereamong is carried out so as to produce all NAND outputs expressed as For example, the NAND circuit 302 is connected with the data bit D1 of the ROM 1, the data bit D6 of the ROM 2 and the address bit A17 (i = 1, j = 6 and k = 1), while the NAND circuit 309 is connected with the data bit D1 of the ROM 1, the data bit D7 of the ROM 2 and not connected with the address bit A17 (i = 1, j = 7 and k = 0). Then, the outputs of these NAND circuits 301 to 315 are supplied to an OR circuit 4 of negative logic input the OR output of which is fed to a terminal 5. According to the circuitry thus made, when m bits of the parity check bits A1 to A8 become "1", n bits of the parity check bits A9 to A16 become "1" and when A17 = "0" is satisfied, the following condition is established as Thus, when the condition, m + n ≧ 10 is established, the output of the corresponding NAND circuit of the NAND circuits 309 to 315 becomes "0" and hence the output of the OR circuit 4 becomes "1". Further, when the condition, A17 = "1" is established, the following equation is established as Thus, when the condition, m + n ≧ 9 is established, the output of the corresponding NAND circuit of the NAND circuits 301 to 308 becomes "0" and hence the output of the OR circuit 4 becomes "1". As a result, according to this invention, when the bits more than 10 bits of the parity check bits A1 to A17 become "1", the output at the terminal 5 becomes "1" so that it is possible to detect the existence of error. In this case, particularly in accordance with this invention, the majority logic circuit can be formed of the two ROMs 1 and 2 of a small capacity and several gate ICs. In other words, the parity check bits A1 to A17 are grouped, the ROMs 1 and 2 of a small capacity are enough. Further, in the gate IC on the market, four to three 2-input or 3-input NAND circuits are formed on a single IC. Further, the OR circuit 4 can be realized by two 8-input OR circuits and one OR circuit. The IC of the 8-input OR circuit is also sold on the market. Therefore, according to this invention, the majority logic circuit can be made by the two ROMs 1 and 2 of small capacity and several gate ICs. Accordingly, as the ROMs 1 and 2 and the circuits 301 to 315 and 4, it is possible to use ROMs and gate ICs which appear on the market so that the majority logic circuit of this invention can be made at low cost. Further, since the majority logic circuit of this invention can be made by the two ROMs 1 and 2 and several gate ICs, its space factor is excellent and the power consumption can be reduced. Furthermore, since the stage number of the circuits is small, the delay of the processing speed of the majority logic circuit is small and the reliability thereof is excellent. In addition, while the relation between the address and the data as shown in Fig. 2 and the connection relation between the circuits 301 to 315 and 4 can be tabulated and processed by a software, it is possible to carry out the processing at higher speed than that of such case. In the above, it is possible that the ROMs 1 and 2 are exchanged to RAMs and upon use, these RAMs are initialized as shown in Fig. 2. Further, the ROMs 1 and 2 may be 4-bit ROMs or 512 bytes ROMs.

Claims: A majority logic circuit for identifying whether incoming parity check bits (A1-A17) include a plurality of true bits more than a predetermined number comprising : a plurality of memory means (1-2) in which predetermined data are written ; means (1-2) for grouping said incoming parity check bits into a plurality of groups greater than two ; a plurality of first gate means (301-315) divided into a plurality of groups greater than one each of said first gate means being supplied with selected outputs of said memory means ; and second gate means (4) supplied with all outputs of said first gate means (301-315) for generating an identifying signal corresponding to a threshold value of the parity check bits ; characterized by supplying all of said plurality of groups less one (A1-A8 ; A9-A16) of said plurality of check bits (A1-A17) to address bits (AD0-AD7) of said plurality of memory means (1-2) and the respictive data bits of the memory means (1-2) to said plurality of groups of said first gate means (301-315) whereby the remaining one (A17) of said parity check bits (A1-A17) is supplied directly to selected one (301-308) of said plurality of groups of said first gate means (301-315) without being supplied to said plurality of memory means (1-2). A majority logic circuit as cited in claim 1, wherein said incoming parity check bits (A1-A17) are 17 bits and grouped into first (A1-A8), second (A9-A16) and third (A17) groups. A majority logic circuit as cited in claim 2, wherein said memory means includes first memory means (1) and second memory means (2), and said first (A1-A8) and second (A9-A16) groups of the parity check bits are supplied to said first and second memory means (1-2), respectively. A majority logic circuit as cited in claim 3, wherein said first and second memory means (1-2) are 8 bit-parallel 256 bytes ROMs, respectively. A majority logic circuit as cited in claim 4, wherein said first gate means are divided into a first group (301-308) and a second group (309-315). A majority logic circuit as cited in claim 5, wherein said first group (301-308) of the first gate means is supplied with the outputs of said first and second memory means and said third group (A17) of the parity check bits, and said second group (309-315) of the first gate means is supplied with the outputs of the first and second memory means (1-2). A majority logic circuit as cited in claim 6, wherein when the number of true bits at address inputs is N, the N less significant bits of said predetermined data become true bits in said first and second memory means (1-2).

Inventors: MAEDA, SATORU, NOGUCHI, YASUSHI
Applicants: SONY CORPORATION
Application year: 1984
Main classification: G06F11
IPC codes: H04L1, H03M13, G06F7, G06F11, H03K19