APPARATUS FOR GENERATING THE DISPLAY OF A CURSOR

Abstract: The present invention relates to a method and apparatus for generating cursors for display by a color raster graphic system. The cursors displayed can assume any one of a plural­ ity of forms. Each cursor has predetermined boundaries and includes all pixel positions of the raster within its boundaries. One pixel position is designated as the origin of the cursor and selected ones of the pixel positions for each form of the cursor will display the cursor color and intensity. The address of the origin of a cursor and its form are designated by a graphic controller (10) of the system. The address of the origin is compared within a cursor display logic (18) with the addres­ ses of the pixels produced by a raster scan logic (20), and, when the same, the form number and the x and y coordinates, the addresses of the pixel positions of the cursor relative to the origin thereof, are produced and applied to a read-only memory (56) which produces cursor control signals stored at the addressed locations of the cursor memory. The cursor control signals are produced in synchronization with the scanning of pixels, the position of which correspond to selected pixel positions of the cursor and are applied to the color look-up memory (16) of the system. Such pixel control signals cause the color look-up memory to produce color control signals which cause pixels corresponding to a desig­ nated pixel position of the given pixel and form of cursor, to be displayed in the cursor color and intensity.

Description: The present invention relates to an apparatus for generating cursors for a color raster graphic system according to the preamble of claim 1. Such an apparatus is known from US-A-4 259 725. This known cursor generator operates with two independent driving sections which control the image through a mixer. There is provided an image driving section in which the stored image information, both data and graphics, is converted to analog video signals by a D/A converter. The output of this converter is applied to the mixer whose output in turn drives the monitor. Furtheron there is provided a cursor driving section in which the cursor is generated completely separately from the data/graphics image. The cursor information is generated by a program and stored in a RAM in the form of two count numbers per scan line of the cursor. One count number represents the number of the pixel along the scan line at which the cursor starts and the other count number represents the number of pixels in the cursor along the scan line. A X-position counter receives the starting position count from said RAM at the start of the corresponding scan line and when it counts to overflow it generates a signal to a flip-flop. Said flip-flop in its set state delivers a control signal through a gate to said mixer to cause the brightening or dimming of the data/graphics pixel generated by the image driving section. Thus, such control signal is mixed with the composite video signal for the currently existing horizontal line and writing of the cursor line begins. This brightening or dimming of the composite video signal continuous until a width counter underflows and resets that flip-flop. Departing from this prior art it is the object of the present invention to devise an apparatus for generating cursors which allows an independent cursor display with respect to its origin, form and color where a minimum of I/O operations are required. This object is achieved according to the characterizing portion of claim 1. Further advantageous embodiments of said apparatus may be taken from the dependent claims. The present invention provides an apparatus for displaying a cursor on a color raster graphic system. To avoid the necessity of having the graphic controller writing cursor pixel control information into the pixel memory for each pixel corresponding to each cursor position within the boundaries of the cursor to be displayed in the desired cursor color and intensity, cursor pixel control signals are stored in a cursor memory. The addresses of the cursor control signals in the cursor memory are a function of the location of each cursor pixel position within the boundaries of the cursor relative to one such position which is designated as the cursor origin and of the number of the form of the cursor to be displayed. The graphic controller, when it is commanded to display a cursor of a given form, produces a cursor binary number identifying the form, or type, of cursor to be displayed and the x and y binary coordinates of the pixel of the raster which coincides with the origin. Cursor control logic, which includes a cursor memory, each time the address of the pixel being scanned coincides with the origin of the cursor begins producing addresses in the cursor memory of cursor positions within the boundary, or envelope, of the cursor. These addresses are applied to the cursor memory. The cursor memory in response thereto produces cursor pixel control signals which are applied to the color look-up memory in synchronization with the scanning of pixels whose address correspond to pixel positions of the cursor relative to the origin of the cursor. These cursor control signals cause the pixels corresponding to selected cursor positions to be displayed in the cursor color and intensity. As a result, a cursor of the desired form is produced with its origin being positioned to coincide with the designated pixel address as determined by the controller. Other objects, features and advantages of the invention will be readily apparent from the following description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings in which: Figure 1 is a schematic block diagram of a raster graphic system with details of the display device omitted; Figure 2 is a schematic block diagram of the cursor display logic of the invention; Figure 3 is a schematic block diagram of a portion of the color look-up address selector circuit of the system as modified to operate with the cursor display logic; Figures 4a through 4d illustrate various forms of a cursor; Figure 5 is a schematic diagram illustrating the organization of a cursor memory; and Figure 6 is a view similar to that of Figure 2 showing a modification of the cursor display logic for use with an interlaced vertical scan. In Figure 1, there is illustrated apparatus for controlling the images displayed by, or the display of, a computer-generated raster graphic system. Graphic controller 10 has the capability of writing into random-access alphanumeric memory 12, graphic memory 14, color look-up memory 16, and cursor display logic 18, binary digital information, or signals, that is used to control the intensity and color of each picture element, pixel, of a conventional color CRT monitor which is not illustrated. Raster scan logic 20 of a conventional CRT monitor includes conventional digitizing circuits which digitize the horizontal and vertical sweep signals of the CRT monitor so that for each pixel on the face of the CRT there is an address. To uniquely identify each of the 640 pixels in a horizontal line and in the 480 vertical lines of a standard CRT raster requires a 19-bit address with the x component comprising 10 bits and the y component 9 bits. The x address corresponds to the ordinate and the y to the abscissa of the pixels of the substantially rectangular raster. While in Figure 1 alphanumeric memory 12, graphic memory 14, and color look-up memory 16 are indicated as being separate, they may be combined, or located, in a single conventional random-access memory. For this application, alphanumeric memory 12 and graphic memory 14 are collectively referred to as pixel memory 22. Pixel clock 24 produces a clock pulse each time that a pixel in the raster is scanned. The output of pixel clock 24 is used to read data from memories 22 and 16, as well as by the control circuitry of this invention including cursor display logic 18, as will be described below. In the system illustrated, with each clock pulse produced by pixel clock 24, 7 bits of an alphanumeric color address are transmitted from latch and shift register 26 to color look-up address selector 28 with two priority bits, Pr⊘ and Pr1. Simultaneously, 5 bits of a graphic color address are transmitted to color look-up address selector 28, with one bit being shifted out of each of the shift registers 30 with each pixel clock pulse. Based on the values of the two priority bits, Pr⊘ and Pr1, the color look-up address selector 28 will apply to color look-up memory 16 an eight-bit address with the 7 bits of the alphanumeric color address, or the 5 bits of the graphic color address being the lower order bits of a color look-up memory address. In color look-up memory 16 at locations having addresses corresponding to the color addresses applied by selector 28, there are stored color control signals which are used to control the intensity of the electron beams of the color guns of a conventional color CRT monitor and which determine the color and intensity of, or the display of, each pixel of the array as it is scanned. An 8-bit byte is stored in color look-up memory 16 at locations corresponding to the color addresses applied. In synchronism with the scanning of each pixel of the array, or raster, an 8-bit byte, the color control signal, is read out of color look-up memory 16 and applied to D/A converters 32. D/A converters 32 convert 6 of the 8 binary signals into analog signals for controlling the intensity of the red, green and blue electron beam guns of a conventional CRT monitor. In addition, in the preferred embodiment, two bits of the color control signal are applied to a fourth D/A converter which converts these two bits into a monochrome analog signal that can be used to produce a permanent record of the raster display using conventional equipment, as is well known in the art. In Figure 2, details of cursor display logic 18 for a non-interlaced raster scan are illustrated. Graphic controller 10, when commanded by a user, will write into cursor number latch 34 the number assigned to the desired form of cursor to be displayed. Graphic controller 10 also writes into cursor vertical position latch 36 the Y coordinates of the origin of the cursor and into cursor horizontal position latch 38 the X coordinates of the origin. These X and Y coordinates are the address of a pixel in the raster of the system which corresponds to that of the origin "O" of the cursor. The Y coordinate stored in latch 36 is applied as one input to vertical comparator 40. The other input is the Y coordinate of the address of the pixel being scanned as produced by raster scan logic 20. Similarly, the X coordinate of the origin stored in latch 38 is applied as one input to horizontal comparator 42, and the other is the X coordinate of the address of the pixel being scanned as produced by raster scan logic 20. When the X coordinate of a pixel being scanned is the same as the X coordinate of the origin of the cursor to be displayed stored in latch 38, comparator 42 will produce a horizontal compare signal. The horizontal compare signal is applied to the horizontal enable flip flop 44, which when set by the horizontal compare signal produces a horizontal enable signal. The horizontal enable signal is applied to horizontal counter circuit 46 and cursor enable circuit 48. In the preferred embodiment, counter 46 is a 4-bit counter and cursor enable circuit 48 is an And gate. Pixel clock signals from pixel clock 22 are applied to counter 46 so that the output of counter 46 changes with each pixel clock signal. When sixteen pixel clock signals are counted after the horizontal enable signal is produced, or the count equals sixteen, a count equals sixteen signal is applied to the reset input of horizontal enable circuit 44 which resets it, stopping the counter. When the Y coordinate of the pixel of the raster being scanned equals the y coordinate of the origin of the cursor as stored in latch 36, vertical comparator 40 produces a vertical compare signal. The vertical compare signal is applied to a vertical enable flip flop 50 which sets it. As a result, vertical enable flip flop 50 produces a vertical enable signal which is applied to vertical counter 52 and to cursor enable gate 48. Counter 52, a 4-bit counter in the preferred embodiment, when enabled by the vertical enable signal, counts vertical scan clock pulses which are applied to counter 52. When sixteen such vertical scan clock signals are counted, a count equals sixteen signal is applied to the reset terminal of flip flop 50. When both the vertical and horizontal enable circuits 50 and 44 are set, cursor enable circuit 48 produces a cursor enable signal which is applied to cursor shift register 54. Cursor control bits, or signals, are stored in addressable locations of cursor memory 56. In the preferred embodiment, cursor memory 56 is a read-only memory having an eight-bit address and stores four cursor control bits in each addressable location. The eight-bit address for cursor memory 56 is made up of two bits, the cursor number, from cursor number latch 34, four bits from vertical counter 52, the vertical component, and the two higher order bits of the horizontal counter 46, the horizontal component. The lower two order bits of horizontal component from counter 46 are applied to shift register 54, as are pixel clock signals from pixel clock 22. When the cursor enable signal from gate 48 is true, register 52 receives from cursor memory 56 four cursor control bits every fourth clock period. Cursor shift register 54 will produce, or shift out, a cursor control signal during each clock period in synchronization with the scanning of the corresponding pixels by the system. The two lower order bits of horizontal counter 46 are used to count the cursor control bits of each of the four cursor control bits shifted into the shift register 54 by enabling register 54 to store four cursor control bits as read out of the addressed location of cursor memory 56. This happens, in the preferred embodiment, when the lower two order bits produced by counter 46 are both logical zeros. In Figure 3, a portion of color look-up adress selector 28 is illustrated. A more complete description of the system of Figure 1 and of address selector 28, may be taken from the published international patent application PCT/US83/00054. An eight-bit color look-up memory address is stored in graphic address register 58 and in alphanumeric address register 60. Since the graphic and alphanumeric addresses applied to selector 28 need not be of eight bits, higher order bit positions are forced to predetermined logic values so that the output of selector 28 is an eight-bit address. The outputs of registers 58, 60 are applied to one of two eight-bit multiplexers 62, 64. The eight bits selected by multiplexer 62, 64 are determined by the value of the alphanumeric display signal ANDS applied to the select terminal "S" of multiplexer 62, 64. If ANDS is true, the eight bits from alphanumeric display register 60 are applied to color look-up memory 16. If the signal ANDS is false, the eight bits from the graphic display register 58 are applied to color look-up memory 16. Cursor control bits from shift register 52 are applied to the enable terminal "E" of multiplexer 62, 64, and, when true, force all the outputs of multiplexer 62, 64 to logical zeros. Stored in the zero address location of color look-up memory 16 are the color control signals that determine the color and intensity of the pixels forming the cursor. In Figures 4A-D, there are illustrated four forms that the cursor 66 may take. In the preferred embodiment, cursors 66 can have up to 16 pixels to a side. Pixel 66a illustrated in Figure 4A which forms a set of cross hairs, however, has fifteen pixels to a side with each line segment displaying the cursor color and intensity having seven pixels. In Figure 4B, cursor 66b has the top and bottom rows of 16 pixels each displaying the cursor color at the cursor intensity. In Figure 4C, cursor 66c has 8 pixels in the top and bottom rows displaying the cursor color and intensity. In Figure 4D, cursor 66d is in the form of a rectangle of 8 x 16 pixels. In the preferred embodiment, the origin "O" of the cursor is the pixel position in the upper left-hand corner of the 16 x 16 pixels positions forming a cursor 66. In cursor 66a, the pixel corresponding to origin "O" is not displayed in the cursor color and intensity. In all other of the forms illustrated, it is. Obviously, cursors 66 can have forms other than those illustrated and the number of forms can also be varied. In Figure 5, there is illustrated a memory map for a single pixel form. In this particular illustration the memory map is that of cursor 66c illustrated in Figure 4C. Logical ones are written into the bit positions 0-7 of rows 0 and 15. All other bit positions of the segment of cursor memory 56 for this form will be logical zeros. The origin corresponds to bit positions 0, 0 as illustrated in Figure 5. In Figure 6, there is illustrated a modification of cursor display logic 18' for use when the vertical raster scan of the CRT monitor is interleaved. When the vertical scan is interleaved, all even-numbered horizontal lines are scanned in succession followed by all the odd-numbered lines. The least significant bit (LSB) of the y coordinate, or line address, which is also known as the odd/even frame bit, remains constant through each frame, or scan, of the set of odd or even lines. Interleaving the vertical scan creates a problem for the cursor display logic, particularly when the origin is located on an odd line since only the upper eight bits of the nine-bit y coordinate of the cursor origin are compared with the upper eight bits of the y coordinates of the pixel being scanned by comparator 40. Without modification, cursor display logic 18 would not start on the odd line, but on the even line. To solve this problem, the frame bit produced by raster scan logic 20 and the LSB of the y coordinate of the origin stored in cursor vertical latch 36 are applied to exclusive OR circuit 68. The output of gate 68 is the LSB of the y component of the address applied to cursor ROM 56. Another modification of cursor display logic 18' is that vertical counter 52' is a three-bit counter. In the modification of Figure 6, the y component of the address signals applied to ROM 56 consists of three bits from counter 52' and one, the LSB, from gate 68. Another problem that occurs when the vertical scan is interlaced is the need to delay by one line, one vertical scan clock pulse, or end-of-line timing pulse, production of the vertical enable signal when the cursor origin is located on an odd-numbered line of the raster and the frame bit is even. The circuitry that accomplishes this includes D flip-flop 70 and 4-1 multiplexer 72. The frame bit of the pixel being scanned and the least significant bit of the y coordinate of the origin of the cursor are applied to the A and B terminals of multiplexer 72 and select which of the four inputs is applied to enable cursor gate 48 and vertical counter 52'. To do this, the output of vertical enable flip-flop 50 is applied to the D input terminal of flip-flop 70 and to three of the four input terminals of multiplexer 72. The fourth input to multiplexer 72 is the Q output of flip-flop 70. The set terminal of flip-flop 70 has applied to it the count equals eight signal produced by the three-bit vertical counter 52' which also resets flip-flop 50. The clock signal input of flip-flop 70 has applied to it the vertical scan clock pulse produced by raster scan logic 20. The circuit involving exclusive OR gate 68 makes certain that the least significant bit of the y component of the cursor address applied to cursor ROM 56 is such that cursor control signals read out of cursor ROM 56 and produced by shift register 54 begin when the line of pixels being scanned has the same y coordinate as that of the origin of the cursor. Similarly, the circuit involving flip-flop 70 and multiplexer 72 will delay by one horizontal scan line the applilcation of a vertical enable signal to counter 52' and gate 48 if the y coordinate of the cursor origin is an odd binary number and the frame bit is even. From the foregoing, it is clear that the method and apparatus of this invention permit a raster graphic system to display any one of several forms of a cursor while imposing the minimum of requirements on the graphic controller. Changing the form of a cursor can be accomplished by replacing cursor ROM 56. Increasing the size of cursor memory 56 also makes it possible to increase the number of forms of cursor that can be displayed if other appropriate changes are made to cursor display logic 18, 18'. Further, the cursor display logic of this invention can be modified to function properly with an interlaced, or interleaved, vertical scan.

Claims: Apparatus for generating cursors for a color raster graphic system, said system including a display device having a raster of pixels with each pixel of the raster having a pixel address, said apparatus comprising cursor storage means for specifying the form of a cursor and the pixel address of the origin of the cursor, said cursor storage means comprising: a first store (34) for receiving and holding signals representing the form of cursor, and a second store (36,38) for receiving and holding signals representing the pixel address of the origin of said cursor, means for identifying each pixel of the raster which corresponds to a cursor pixel position, said identifying means comprising: a comparator (40,42) coupled to said second store (36,38) and coupled to receive signals representing the raster address of the pixel currently being displayed and for delivering a first signal when the raster address equals the cursor origin address; and cursor control signal producing means operating on said display device, characterized by the following features: said cursor storage means additionally comprising an addressable third store (56) having storage locations for the individual pixels of said cursor, the addresses of said locations corresponding to the display addresses of the pixels of said cursor relative to said origin with each of said storage locations holding control bits uniquely representative of the corresponding cursor pixel; said identifying means further including a first circuit (46,52) coupled to said comparator (40,42) and said third store (56) and responsive to said first signal for applying a succession of addresses to said third store corresponding to the succession of said relative addresses of the pixels of said cursor and for coupling the contents of said first store (34) to said third store (56) as a portion of the address applied thereto for respectively delivering the control bits held in the addressed location thereof; and said cursor control signal producing means comprising: a second circuit (54; Fig. 3) coupled to said third store (56) for selectively applying said control bits to a color look-up memory (16) as a color address to cause it to produce color control signals which cause the pixel being scanned to be displayed in the selected cursor color and at the selected cursor intensity independent of the data/graphics display. Apparatus according to claim 1, characterized in that the addressable memory (56) for storing cursor control bits is a read-only memory. Apparatus according to claim 2, characterized in that the addressable memory (56) for storing cursor control bits stores four control bits at each addressable location. Apparatus according to claim 3, characterized in that the number of forms of the cursor is four.

Inventors: CLARKE, CHARLES J. JR., STAGGS, KEVIN P.
Applicants: HONEYWELL INC.
Application year: 1984
Main classification: G09G1
IPC codes: G09G5