FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS

Abstract: A field effect transistor for integrated circuits has an n-­ type semiconductor layer (12), an amorphous silicon region (13) which is formed on a prospective gate region of a major surface of the n-type semiconductor and which contains at least boron, a metal layer (14) deposited on the amorphous sili­ con region so as to constitute a gate electrode (G) together with the amorphous silicon region, and source and drain elec­ trodes (S, D) formed on those portions of the major surface of the n-type semiconductor layer which are located at the two sides of the amorphous silicon region.

Description: Field Effect Transistor for Integrated Circuits The present invention relates to a field effect transistor and, more particularly, to a field effect transistor for integrated circuits. A typical conventional field effect transistor (to be referred to as an FET hereinafter) formed on a GaAs semi-insulating substrate has a metal electrode which, together with a GaAs-based Group III - V compound semiconductor, constitutes a Schottky barrier. There are only a small number of conventional FETs having an insulating gate film and a p-n junction gate. In the FETs having the insulating gate film this is because deviation in threshold value become large owing to charges trapped at the interface between the GaAs semiconductor and the insulating film. In addition, in the FET having the p-n junction gate, the gate length at the p-n junction cannot be less than I pm due to micropatterning limitations. Therefore, the conventional technique will be exemplified by the conventional GaAs FET having a Schottky barrier junction gate. In the conventional GaAs Schottky barrier junction gate FET (to be referred to as a GaAs MESFET hereinafter), a metal gate electrode is selected from materials such as aluminum, gold, titanium, molybdenum, platinum and tantalum. The Schottky barrier electrical characteristics vary in accordance with different metal electrode materials and are reflected in a Schottky barrier height or energy difference bBN in the relation Io exp [ q(V - fBN)/kTl representing a relationship between the Schottky barrier current Io and the forward biasing voltage V between the Schottky electrode and the n-type semiconductor layer, where q is the magnitude of electronic charge, k is the Boltzmann constant, and T is the absolute temperature. The Schottky barrier height bBN is a factor which determines a biasing voltage at which an abrupt increase in the Schottky barrier forward biasing current occurs. Assuming that neither of an interface layer and interface electron states exists at the interface between a metal electrode and a semiconductor layer, the Schottky barrier height OBN is given by equation (1) below: #BN = ¯M - X ...(1) where #M is the work function of the electrode metal, and X is the electron affinity. According to the ideal model, work functions of metals as electrodes which constitute Schottky junctions directly correspond to the Schottky barrier heights. However, the measured results of the Schottky barrier heights tBN greatly differ from those derived on the basis of the ideal model, as has been described in various references. The conventional measured results of the Schottky barrier potential difference QBN have the following tendency. The Fermi level EF at the Schottky barrier junction interface is almost fixed at an energy level (EG/3) above the valence band when the energy gap is given as EG. In other words, the Schottky barrier height #bBN for an n-type semiconductor tends to be set at about 2EG/3, and, therefore, is restricted by the energy gap EG of the n-type semiconductor. For example, in the case of n-type GaAs, it is generally known that the Schottky barrier height is given to be about 0.07by + 0.49 in accordance with measured values concerning several types of metal electrodes. This is reported by A.M. Lawley and S.M. Sze: "Surface States and Barrier Height of Metal-Semiconductor Systems", J. Appl. Phys. Vol. 36 (1965), P. 3212. Even if a variety of metals are applied to n-type GaAs, only 7/100 times metal work function difference is reflected to the Schottky barrier height difference. Therefore, the available range of the conventional Schottky barrier height 9 BN obtained falls within 0.7 V to 0.85 V. In the general industrial process for fabricating MESFETs, when various types of Schottky barrier junction gate metals are used to vary the Schottky barrier height #BN, more than one gate metal deposition apparatus must be used. In addition to this disadvantage, the type of metal which may be used for wiring connected to the gate electrode is limited, resulting in inconvenience. Therefore, the MESFETs have conventionally been designed under the assumption that the Schottky barrier height OBN is given to be a predetermined value. The relation among the built-in voltage Vbi of the Schottky barrier which is determined corresponding to the Schottky barrier height #BN, the drain current Id, and the gate-source voltage VGS in the current saturation region of an FET is given as follows: Id = 4KVp2F (VGS - VT)/Vp + 2f(l - (VGS - VT)/Vp)3/2 -1}/31 ... (2) K = #iiw/2dtg ... (3) VT = Vbi - Vp ... (4) Vp = d2(qND/2C)...(5) Vbi > VGS > VT where Id: the drain current VT: the threshold voltage of the FET VGS: the gate-source voltage E: the dielectric constant of the semiconductor layer the electron mobility w: the gate width d: the depth of the semiconductor layer Lg: the gate length ND: the donor concentration Vbi: the built-in voltage of the Schottky barrier As is apparent in inequality (6), the upper limit of the gate-source voltage is given as a voltage at which the current flowing in the gate cannot be neglected with reference to the drain current. The upper limit substantially corresponds to the built-in voltage Vbi (##PBN). Therefore, the maximum value (i.e., maximum drain output current Idmax) of the drain current is derived from equation (2) as: Idmax = 4kVbi2 /3 ... (7) when the absolute value of the threshold voltage |VT|is negligible with respect to the built-in voltage Vbi. The maximum drain output current Idmax is determined by the built-in voltage Vbi in accordance with relation Idmax Vbi2. As described above, the Schottky barrier height #BN, that is, the built-in voltage Vbi of the Schottky barrier in a nearly degenerated semiconductor, defines the upper limit of the gate-source voltage of the FET and hence the upper limit of the voltage swing of a logic FET In addition, in the FET arranged in such a manner that the absolute value |VT| of ofthe threshold voltage is negligible with respect to the built-in voltage Vbi, the built-in voltage Vbi determines a maximum drain output voltage thereof in accordance with a squared value of Vbi. Therefore, the Schottky barrier height bBN is one of the most important parameters of the MESFET. However, in the conventional GaAs FET, the Schottky barrier height bBN has been controllable within the narrow range between 0.7 V and 0.85 V. Further, the maximum value of this height is not large enough. As a result, the Schottky barrier height #BN can, in practice, be forcibly preset to be a predetermined constant without changing the type of the electrode metal. The conventional GaAs MESFET has the following disadvantages due to the low Schottky barrier height ORBS, even at the maximum of 0.85 V. The upper limit of the gate-source voltage is set at a low voltage. A maximum drain output current of the FET having a small 1VT| cannot be greatly increased. In general, when a GaAs normally-off MESFET is used as an FET for driving a logic inverter, the upper limit of the signal voltage is set at the built-in voltage Vbi, so that upper and lower values VU and VL of the voltage of the circuit are given by the following inequality: Vbi > VU > VT > VL > O . . - (8) Therefore, when the conventional GaAs MESFET is used as a drive transistor, the upper limit of the logic voltage is set at the upper limit (0.85 V) of the built-in voltage. The allowable range of the threshold voltage which satisfies inequality (8) is narrow. As a result, the operating margin of the circuit is limited to a small value. In addition, a logic voltage amplitude |WiVU 9 cannot be widely preset, so the margin against external 4 noise is also limited. In general, in a MISFET IC using a silicon semiconductor, the principle of scaling down is applied to improve performance thereof and increase the packing density. In particular, when a scale factor representing a reduction ratio is given to be n, various parameters of the MISFET are multiplied by n, 1/n, 1/n2 and so on. The potential parameters such as the power supply voltage VE the logic voltage upper limit W , the logic voltage lower limit VTI, or the threshold voltage VT.of the FET are multiplied by 1/n, thereby obtaining a miniaturized, highly integrated circuit. When the principle of scaling down is applied, a ratio of VDD : VU : VT : VL must be kept constant. However, as previously described, the built-in voltage Vbi is actually set to be a fixed value in the conventional GaAs MESFET, and cannot be increased. Therefore, the ratio of VDD : VU : VT : VL is established only in accordance with the extremely limited power supply condition that VDD < Vbi ( < 0.85 V). In this GaAs MESFET, the principle of scaling down can only be applied subject to the limitation described above, resulting in inconvenience. The same drawback as in the conventional GaAs MESFETs described above exists also in the conventional GaxAll¯xAs MESFETs. In particular, accordingsto the conventional technique, the Schottky barrier height #BN is variable only in the very narrow range such that 0.85 V < L < 1.1 V < 2(EG'/q)/3r where EGT is the energy gap of Ga All As. Therefore, GaxAl1#xAs has the same disadvantage as conventional GaAs. In a conventional Si MESFET having a structure wherein a Schottky barrier junction gate metal is contacted to an n-type silicon semiconductor layer as an active layer, the gate metal generally comprises aluminum on account of an economic advantage thereof. The Schottky barrier height bBN of the Al-Si junction falls within the range between 0.50 V and 0.59 V. Even if the Schottky barrier height ÇBN is increased, on the basis of equation (1), by using a noble metal Pt having a very high work function bM, an actually measured value has an upper limit of about 0.85 V. In other words, in the conventional Si MESFET techniques, the Schottky barrier height #BN can also be increased up to 0.76 times the energy gap (EG = 1.12 eV) of the silicon. Therefore, the conventional Si MESFET techniques have the same difficulties as conventional GaAs MESFET techniques. In an InP MESFET using an InP semiconductor layer as an active layer, it is difficult to form a Schottky barrier junction which satisfies required electrical characteristics such as the leakage current, the reverse breakdown voltage, and the stability. It is, therefore, a principal object of the present invention to pride Åanl improved field effect transistor for an integrated circuit (IC). It¯is another object of the present invention to provide a field effect transistor for an IC, wherein a gate junction barrier height #BN can be adjusted, in accordance with design conditions, to' greater values than those obtainable for conventional metal-semiconductor junctions. It is still another object of the present invention to provide a field effect transistor for an IC, wherein the operating margin of the IC for which the field effect transistor is larger than that of the conventional ICs using the conventional MESFETs. It is still another object of the present invention to provide a field effect transistor for an IC, wherein margin against external noises also is larger the compared with that of the conventional ICs using the conventional MESFETs. It is still another object of the present invention to provide a field effect transistor for an IC, whereto the principle of scaling down can be applied. It is still another obect-of the present invention to provide a field effect transistor for an IC, wherein the'- packing density of the IC is larger than that of the conventional ICs using the conventional MESFETs. In order to achieve these objects of the present invention, an n-type semiconductor layer is used as an active layer, a region of an amorphous silicon containinq boron is formed in a major surface of a prospective gate region of the n-type semiconductor layer, a metal layer which constitutes a gate electrode together with the amorphous silicon region containing boron is formed thereon, and source and drain electrodes are deposited on the major surface portions of the n-type semiconductor layer between which the amorphous silicon region is located. A typical MESFET of the present invention comprises an n-type semiconductor layer as an active layer formed on a substrate, an amorphous silicon (to be referred to as an a-Si hereinafter) region which is formed on part of a major surface of the n-type semiconductor layer and which contains 10 to 60 atom% boron (to be referred to as B hereinafter} or contains 10 to 60 atom% B and germanium (to be referred to as Ge hereinafter), a metal layer formed on the a-Si region so as to constitute a gate together with the a-Si region, and source and drain electrodes formed on portions of the major surface of the n-type semiconductor layer between which the gate is located. Fig. 1 is a longitudinal sectional view of a field effect transistor (FET) for an IC according to an embodiment of the present invention; Fig. 2 is a graph showing the relationship among the flow rate ratio GeH4/(SiH4 + GeH4) and the flow rate ratio B2H/(SiR4 + GeH4) and the junction barrier. height for the present invention; Fig. 3 is a graph showing the relationship between the concentration of B contained in the a-Si film and the flow rate ratio B2H6/(SiH4 + GeH4), with the flow rate ratio GeH4/(SiH4 + GeH4) as a parameter; Fig. 4 is a graph showing the relationship between the flow rate of B2H6/(SiH4 + GeH4) and the junction barrier height Bint; ; Fig. 5 is a graph showing the relationship between the flow rate ratio B2H6/(5iH4 + GeH4) and the resistivity of the a-Si film; Fig. 6 is a graph showing the relationship between the built-in voltage Vbi of the FET and the relative value of the maximum drain current; and Figs. 7 to 19 are longitudinal sectional views for explaining FETs for an IC according to other embodiments of the present invention. Fig. 1 shows a field effect transistor (FET) 10 for an IC according to an embodiment of the present invention. The transistor 10 has a GaAs semiconductor layer (i.e., compound semiconductor layer) 12 which 17 -3 contains n-type impurities of 1 to 5 x 10 cm concentration, which has a thickness of 1,000 A, and which is formed on or in a GaAs semi-insulating substrate 11 having a resistivity of 105 Qcm or more, and an amorphous silicon (a-Si) region 13 which has a thickness of 1,500 and which is in direct contact with part of the surface of the GaAs semiconductor layer 12. A metal layer 14 made of Al or Ti or Mo or W or Pt is deposited on the a-Si region 13. The metal layer 14, together with the a-Si region 13, constitutes a gate electrode G. The FET 10 also has source and drain electrodes S and D which respectively comprise metal layers 15 and 16 The metal layers 15 and 16 are made of AuGe or InAg so as to constitute an alloy-type ohmic contact with the semiconductor layer 12 and are located with the a-Si region 13 in between. The presence of the a-Si region 13 is an important factor in preparing the FET of this embodiment. The a-Si region 13 typically contains 10 to 60 atom% of B, or Ge in addition to 10 to 60 atom% of B. By changing the concentration of B or Ge in a manner to be described later, the barrier height bBN' between the a-Si region 13 and the n-type GaAs semiconductor layer 12 can have values in a wider range and higher value. The above-stated concentration of B is necessary only in such a portion of the a-Si region 13 which has at least a thickness of 50 to 200 A from the interface between the n-type GaAs semiconductor layer 12 and the a-Si region 13. This is because this thickness is sufficient for determining the barrier height #BN1. A process for fabricating the FET shown in Fig. 1 will be described hereinafter. An n-type GaAs semiconductor layer 12 is formed on or in a major surface of a GaAs semi-insulating substrate 11 having a resistivity of 105 Qcm or higher. The GaAs semiconductor layer 12 contains an n-type impurity at a concentration of 1 to 15 -3 5 x 1015 cm 3 and has a thickness of 1,000 . In this case, the semiconductor layer 12 is grown by a vapor-phase epitaxial growth method or a molecular beam epitaxial growth method. Alternatively, an n-type impurity such as Si+, S+ or Se is ion-implanted in the GaAs semi-insulating substrate 11, thereby preparing the GaAs semiconductor layer 12. For example, Si is ion-implanted in the GaAs semi-insulating substrate 11 at a desired dose and at an acceleration voltage of 60 keV. Thereafter, an Si3N4 film is grown by a vapor-phase growth method on the substrate 11 to a thickness of 1,500 A. The resultant structure is then annealed in an N2 gas at a temperature of 8000C for 20 minutes, thereby recovering damage of the crystal lattice and electrically activating the doped impurity. Subsequently, the a-Si region 13 is formed on the GaAs semiconductor layer 12 in the following manner, that is by chemical vapor deposition (CVD) method. The sample having the GaAs semiconductor layer 12 is placed in a reaction tube at a reaction temperature of 450or. Material gases of SH, and 2H6 or SiR4, B2H6 and GeH4 which are diluted by He are supplied to the reaction tube at a total gas pressure of 0.2 Torr so as to form on the GaAs semiconductor layer 12 an a-Si film which contains 10 to 60 atom% of B, or Ge in addition to 10 to 60 atom% of B and Ge. Flow rates of gases described above are given to vary the gate junction barrier height #BN' as follows: GeH4/(SiH4 + Ge#H4) = O to 1 x 10 B2H6/(SiH4 + GeH4) = I x 10 3to 2 x 10 1 A detailed description of gas flow control will be made later. An unnecessary region (a region excluding a portion to be used as the gate electrode) of the a-Si film is removed by a known photo lithography method and a known etching method such as plasma etching using, for example, CF4 and 2 thereby forming the a-Si region 13. Aluminum or any other metal is deposited entirely or locally on the resultant structure and is patterned to prepare the metal layers 14, 15 and 16. In this case, the metal layers 14, 15 and 16 are formed such that the predetermined aluminum pattern is annealed in an N2 gas at a temperature of 4500C for 20 seconds so as to provide a low-resistance ohmic contact. The gate structure as the main feature of the present invention will be described. The gate structure comprises a combination of the a-Si region 13 which is disposed on the GaAs semiconductor layer 12 and which contains 10 to 60 atom% of B, or Ge in addition to 10 to 60 atom% of B, and the metal layer 14 formed on the a-Si region 13. The present inventors found that electrical characteristics of a junction between the n-type GaAs semiconductor layer 12 and the a-Si region 13 which contains 10 to 60 atom% of B or Ge in addition to 10 to 60% of B coincided with the Schottky barrier characteristics or the so-called one-side-abrupt characteristics. We also found that the ideality factor of the current-voltage characteristics was from 1.0 to 1.3, indicating that the current-characteristics were very good. Figure 2 shows a relationship between the gate junction barrier height #BN' obtained in accordance with the current-voltage characteristics between the a-Si region 13 and the n-type GaAs semiconductor layer 12, and the flcx rate ratio of the material gases which is one of the parameters to be controlled for forming the a-Si film. In order to obtain a desired barrier height #BN' of the junction between the a-Si region 13 and the n-type GaAs semiconductor layer 12, the required flow rate ratios of SiR4, B2H6 and GeH4 can be determined in accordance with curves similar to the curves in Fig. 2. The curves 2-a, 2-b, 2-c and 2-d in Fig. 2 indicate the flow rate ratios, when values of the barrier height #BN' are to be 0.90 V, 0.94 V, 0.98 V and 1.10 V, respectively. For example, in order to set the barrier height #BN' to be 1.10 V, the flow rate ratios of B2H6/(SiH4 + GeH4) and GeH4/(SiH4 + GeH4) 1 # s -2 are set to be, for example, about 8 x 10 2 and 1 x 10 respectively. Any other combinations of the flow rate ratios indicated by the curve 2-d are applicable. Figure 3 shows the atom% of B in the a-Si film as a function of the flow rate ratio of B2H6f(SiH4 + GeH4), and Fig. 4 shows the barrier height rPBN' of the junction between the a-Si film and the n-type GaAs semiconductor layer as a function of the flow rate ratio of B2H6/(SiH4 + GeH4). In each of the graphs shown in Figs. 3 and 4, the flow rate ratio of GeH4/(SiH4 + GeH4} is used as a parameter. Curves 3-a and 4-a respectively indicate cases where the flow rate of GeRo is zero (i.e., where the a-Si film contains B but not Ge). Curves 3-b and 4-b respectively indicate cases where SiR4, B2H6 and GeM4 gases are used as the material gases and the flow rate ratio of GeH4/(SiH4 + GeH4) is given to be 5 x 10 (i.e., where the resultant a-Si film contains both B and Ge). Fig. 3 indicates that the B concentration is increased when the flow rate ratio of B2H6/(SiH4 + GeR4) gas is increased. Fig. 3 also indicates that the B concentration in the a-Si film does not greatly change in accordance with a change in flow rate ratio of GeH4/(SiH4 + GeH4). Fig. 4 indicates that the barrier height #BNt of the junction between the a-Si film and the n-type GaAs semiconductor layer is increased to within the range of about 0.90 V to 1.15 V when the flow rate ratio of B2H6/(SiH4 + GeH4) is increased. When GeR4 gas is supplied, the barrier height BN' is decreased in comparison with the case of the curve 4-a. According to this characteristic, it is readily understood that the barrier height #BN' changes in accordance with a change in the flow rate ratio of GeH4/(SiH4 + GeH4). It is also understood that the B concentration should be at least 10 atom% in the a-Si region 13 in order to set the barrier height bBN' to be 0.85 V or higher, which cannot be achieved by the conventional Schottky barrier junctions. For example, as is apparent from the curve 2-a in Fig. 2, in order to obtain the barrier height #BN' of 0.90 V or higher when the flow rate ratio of GeH4/(SiR4 + GeH4) is set to be zero (i.e., when GeH4 gas is not supplied), the flow rate ratio of B2H6/(SiH4 + GeH4) must be set to be about 5 x 10 3or higher. In this case, as is apparent from the curve 3-a i Fig. 3, the resultant a-Si film contains at least about 15 atom% of B. Although not illustrated in Figs. 2 and 4, the flow rate ratio curves for obtaining a barrier height bBN' of 0.85 V, which is equivalent to the maximum value of the conventional Schottky barrier height #BN, lie to the left of curves 2-a and 4-a, respectively. These conditions can be achieved with a reduced flow rate ratio of B2H6/(SiR4 + GeH4), compared to the cases for the curves 2-a and 4-a. In this case, the resultant a-Si film contains B to about 10 atom%. Therefore, in order to obtain a larger barrier height OBN' than the maximum value of the conventional Schottky barrier height bBN, the B concentration in the a-Si film must be higher than at least 10 atom%. In the above embodiment, a-Si containing at least 10 atom% of B or a-Si containing at least 10 atom% of B and Ge constitutes the a-Si region 13. When a-Si containing Ge in addition to B is used, the electric resistance of the a-Si region 13 can be decreased. The upper limit of the B concentration in the a-Si region 13 will now be considered. As is apparent from the characteristics shown in Fig. 4, the barrier height #BN' saturates, when B2H6/(SiH4 + GeH4) is more than about 1 x 10 Now consider the characteristic curve shown in Fig. 5. Figure 5 shows the relationship between the resistivity of the a-Si film and the flow rate ratio of B2H6/(SiH4 + GeR4) when the flow rate ratio of GeH¯/(SiH4 + GeH4) is set to be zero. When the flow rate ratio of B2H6/(SiH4 + GeH4) increases exceeding about 1 x 10 2, the resistivity increases at an accelerating rate. When the resistivity becomes about 10 fl.cm or higher, the a-Si region 13 combined with the metal layer 14 will not serve as a good electrode. Therefore, the B concentration in the a-Si film must have an upper limit of about 60 atom%, as confirmed from Fig. 3. It should be noted that the metal layer is deposited on the a-Si film to provide a practical gate electrode with a low resitivity. For example, when the gate electrode comprises only a-Si and has a length Lg, a width W and a thickness T, its electric resistance is given to be pW/(LgT) where p is the resistivity of a-Si. The minimum resistivity of a-Si is given to be about 1 n¯cm. When the length tg, the width W and the thickness T are given, for example, to.be l pm, 10 pm and 1,500 AO, respectively, the electric resistance of the gate electrode becomes very high, up to about 670 kQ, and becomes impractical. The upper limit of the electric resistance varies in accordance with the specifications of the target circuit. However, the electric resistance of the gate electrode having the length Lg and the width W is preferably less than about 1 kn. On the other hand, when the metal layer is deposited on the a-Si film, the electric resistance of the gate electrode is given by pT/(LgR) and becomes as low as 0.15 kn, The resistivity of a-Si becomes 10 Q-cm or higher in accordance with the composition of a-Si. However, the thickness T can be as small as 50 to 200 without problem, as previously described. Therefore, the electric resistance of the gate electrode can be decreased to be less than 1 kQ by decreasing the thickness T. According to this embodiment as previously described, a barrier junction similar to the conventional Schottky barrier junctions can be obtained. In addition, as is apparent from Fig. 2, when the B concentration in the a-Si film is properly preset (i.e., when the flow rate ratios of the material gases are properly preset), the range of the barrier height OBN t can be widened compared with that of the conventional FETs. Furthermore, the upper limit (1.15 V) of the potential difference becomes higher by 0.3 V than that of the conventional potential difference. Although not illustrated in Fig. 2, the Schottky barrier height bBN obtained using conventional metal can also be obtained using the a-Si film according to the present invention by changing the B concentration thereof. The electronic structure of the a-Si region containing B, which is used in the present invention, and gives a wide range of the barrier height Bobs', will be considered. The electronic structure of this region is the same as that of a metal, except that electron states are spatially localized. In other words, highly dense localized electron states are present in an energy region (width of 2 eV or more) which includes the Fermi level. The localized electron state density at the Fermi level amounts to the order of 1019 cm -eV-1 or 1020 cm .eV-l, as confirmed from both electrical and optical properties of the present a-Si. A part of the localized electron states are due to dangling bands. However, the dangling bond 17 is very 1ow being of the order of 10 17 -3 -1 density is very low being of the order of 1017 cm -3 eV 1 or less, as confirmed from the results of ESR measurement. The other part or almost all the part of the localized electron states are due to Anderson localization. This situation of the localized electron states is one of the characteristic features of the present a-Si which distinguish it from the conventional a-Si. Since the high-density localized electron states of the order of 1019 to 1020 cm 3 rev 1 are present in the wide energy region containing the Fermi level, it is considered that electric conduction at room temperature and even at such a high temperature as 200 C is due to a hopping mechanism. This is another characteristic feature of the present a-Si which distinguishes it from the conventional a-Si. In order to clearly distinguish the present a-Si from the conventional a-Si, properties of the conventional a-Si are described in detail in the following. In conventional a-Si such as a-Si containing hydrogen or fluorine but excluding an acceptor impurity such as boron and a donor impurity such as phosphorus, the localized electron states occurring in the vicinity of the Fermi level are mainly caused by dangling bonding, and not by Anderson localization. The localized electron state density at the Fermi level varies in accordance with the content and bonding state of hydrogen and/or fluorine and is generally of the order of 1016 cm to 17 -3 ev-1, Electric conduction 10 cm 3 eV 1 Electric conduction at room temperature or higher temperature is constituted by band conduction by means of carriers in the valence band and/or conduction band. In conventional a-Si containing an acceptor (e.g., boron) or donor (e.g., phosphorus) impurity in addition to hydrogen or fluorine, the Fermi level can be situated in the energy region in which electron states are localized in accordance with Anderson localization. However, the width of this energy region is at most 0.5 eV. Electric conduction of the conventional a-Si containing an acceptor or donor at room temperature or higher is the same as in conventional a-Si which does not contain the acceptor or donor impurity. In conventional a-Si which contains neither hydrogen nor fluorine, the Fermi level is included in the energy region in which the electron states are localized. However, these localized electron states are mainly caused by dangling bonds. In this case, the dangling bonding density can be as high as of the order of 1019 to 1020 cm-3, In addition, the width of this energy region is at most 1.9 eV. As is apparent from the above description, the present invention has an advantage in that the gate junction barrier height bBNX can be in a wider range and higher value than the conventional Schottky barrier potential difference bBN. In association with this main feature of the present invention, various effects can be obtained as follows. First, a gate-source voltage can be increased up to a maximum of 1.15 V. Second, a maximum drain output current range can be doubled as compared with the range of the conventional FET. This will be explained in more detail in the following. In general, the FET is operated in such a manner that the drain or source current is used as the output signal while the voltage applied to the gate electrode G is the input signal. Fig. 6 shows the relationship between the built-in voltage Vbi of the gate junction and the relative value of the maximum drain current which can be extracted from the drain electrode D while a predetermined biasing voltage is applied between the source electrode S and the drain electrode D of the FET shown in Fig. 1, and a maximum gate voltage is applied to the gate electrode G. The electrical characteristics of the GaAs FET of the present invention and the conventional GaAs MESFET are illustrated for comparison. The relationship in Fig. 6 is obtained, when the built-in voltage Vbi is varied in the FET so arranged that the threshold voltage VT is 0, a typical case for the logic FET. In order to keep the threshold voltage VT constant (in this case zero) while the built-in voltage Vbi is changed, an impurity concentration ND of the n-type GaAs semiconductor layer 12 must be changed so as to satisfy the following equation, as is apparent from equations (4) and (5): 2 ND = ( 2± /q) ¯ (Vbi/d2) ...(9) Referring to Fig. 6, a curve 6-a indicates the range of the relative value of the maximum drain current obtainable by changing the metal material of the gate electrode in the conventional GaAs MESFETs, while a curve 6-b indicates the range of the relative value of the maximum drain current obtained by changing the B and/or Ge concentration in the a-Si region 13. According to the FET of this embodiment, the maximum drain current Idmax can be doubled as compared with that of the conventional FET. Third, along with the effect wherein the upper limit of the gate input voltage can be set at a high voltage, performance of the GaAs normally-off logic circuit can be greatly improved. As described with reference to the conventional technique, the upper and lower values VU and VL of the FET logic voltage are given by the following inequality: Vbi > W > VT > VL > 0 ... (8) The upper limit VU of the conventional FET is at most 0.85 V. However, since the built-in voltage Vbi of the gate junction of the present invention can be set at a higher voltage than that of the conventional FET, the upper limit W of the FET of this embodiment is increased by a maximum of about 0.3 V. As a result, the allowable range of both the threshold voltage to be preset in a predetermined circuit so as to satisfy the condition given by inequality equation (8) and the scattering of the threshold voltage can be increased. Therefore, the operating margin of the circuit can greatly be increased. In addition to this advantage, the logic voltage amplitude IVIT VLI can be increased, so that the margin against external noise can also be increased. Fourth; since the range of the built-in voltage Vbi of the gate junction can be widened by changing the concentration of B and/or Ge contained in the a-Si region 13, the principle of scaling down used for improving performance of the Si MISFET can also be applied to a variety of FETs. In particular, In the conventional GaAs MESFET, the built-in voltage Vbi is actually fixed at a low value, as previously described. When the principle of scaling down is applied, the ratio of VDD : W : VT : VL is given only under the condition VDD < Vbi. In this manner, the application of the principle of scaling down is limited. On the other hand, in the FET of the present invention, since the built-in voltage Vbi of the gate junction can be set to be a wider range and a higher value, the principle of scaling down can be applied in accordance with this wider range. Fifth, the packing density of the FET can be increased. As previously described, the FET according to the present invention has a higher built-in voltage Vbi of the gate junction, so that the maximum drain current Idmas can be doubled at maximum as compared with that of the conventional GaAs MESFET, when the same gate width and the same gate length are used, as shown in Fig. 6. If the same output current is used as in the conventional FET, the gate width of the FET of this embodiment can be decreased, thereby increasing the packing density thereof. In addition, the present invention has the following advantages in the fabrication process. A metal such as Pt or Au which provides a high Schottky barrier height bBN of the conventional FET has a high resistance to chemicals, so that the gate pattern of this metal must be defined by the lift-off method. However, the lift-off method has poor reliability and is not suitable for fabrication of an LSI. Conversely, the a-Si film used in the present invention can be easily etched by plasma etching. Furthermore, Pt used for forming the conventional Schott:y barrier junction reacts with GaAs at temperatures above 200 % 3000C, and the threshold voltage of the resultant FET greatly changes. Similarly, Au is subjected to diffusion at temperatures above 2000C, and the barrier height #BN is decreased. Conversely, the a-Si film used in the present invention is formed at a temperature of about 4500C or higher and has a property of high thermal stability as compared with that of Pt or Au, thereby providing high reliability. Furthermore, on account of poor thermal resistance of the Schottky barrier junction obtained using a metal providing high barrier heights OBN, severe restrictions are imposed on the manufacturing process (e.g., regarding the order of manufacturing steps, and the materials to be used) after the Schottky barrier is formed. Conversely, when the a-Si film according to the present invention is used, such restrictions can substantially be eliminated. The above description has been made with reference to the first embodiment using the n-type GaAs semiconductor layer. Other embodiments can also be realized for the present invention. A second embodiment provides an FET which has an n-type GaxAl As semiconductor layer in place of the n-type GaAs semiconductor layer of the first embodiment. In this case, the n-type GaxAll As semiconductor layer is formed on a GaxAll xAs semi-insulating substrate. A third embodiment provides an FET which has an n-type Si semiconductor layer in place of the n-type GaAs semiconductor layer of the first embodiment. In this case, the n-type Si layer is formed on a sapphire or on or in p -type silicon substrate. When the n-type silicon semiconductor layer is used and an a-Si film is formed thereon, the deposition temperature of the a-Si film can be higher than that in the embodiment using GaAs or Ga Al As, because the n-type silicon is free from such a problem as thermal dissociation of arsenic (As) on the surface of GaAs or GaxAli#xAs. In either of the second and third embodiments, when an a-Si region containing 10 to 60 atom% of B or an a-Si region containing 10 to 60 atom% of B and Ge is used, the gate junction barrier height #BN1 can have a wider range and a higher value (by 0.2 to 0.3 V compared with the Schottky barrier potential difference #BN of the conventional FET). Therefore, the same effects as in the first embodiment can be obtained in the second and third embodiments. A fourth embodiment provides an FET which has an n-type InP semiconductor layer in place of the n-type GaAs semiconductor layer. The InP FET realized in accordance with this invention the above-mentioned advantages. In particular, it should be noted that the InP FET in accordance with this invention has a stable gate junction the characteristics of which resembles those of good Schottky barrier junctions, although such a stable junction cannot be obtained by conventional FET techniques. In the fourth embodiment, a semi-insulating InP substrate is used. A fifth embodiment provides an FET having an acceptor-doped a-Si region wherein an acceptor impurity has an ionization energy of 0.1 V or less with respect to an n-type semiconductor layer which serves as an active layer. The a-Si region is prepared such that an acceptor impurity element is mixed in the material gases used in the manufacture of the FET of Fig. I. The resultant a-Si film contains a p-type impurity element as follows: Be, Zn or the like for GaAs or GaxAl1#xAs; B, Ga or the like for Si; and Be, Zn or the like for InP. This acceptor impurity element constitutes a shallow level localized only on the very limited surface portion of the semiconductor layer at an interface between the a-Si region and the n-type semiconductor layer. Therefore, the Fermi level can be shifted to near the valence band. As a result, the range of the barrier height #Nt can become wider than that of the first embodiment. A greater effect can thus be obtained. The various embodiments based on the descriptions above will be briefly described with reference to Figs. 7 to 19. The same reference numerals denote the same parts throughout Figs. 7 to 19, and a detailed description thereof will be omitted. Figs. 7 to 16 show embodiments wherein n-type GaAs semiconductor layers serve as active layers. The FET shown in Fig. 7 is substantially the same as that in Fig. 1, except that a width of an a-Si region 13 formed on the surface of an n-type semiconductor layer 12 is particularly narrowed, and that a gate length is shorter than that in Fig. 1. In the FET in Fig. 7, after a metal layer 14 is formed so as to constitute a gate electrode G together with the a-Si region 13, the side walls of the a-Si region 13 are etched by plasma etching using an etchant of CF4 and 0,2at a proper etching rate. In the structure of the FET in Fig. 7, a high-melting metal such as Mo or W is preferably used for the metal layer 14 so as to prevent deformation of the metal layer when a source electrode S and a drain electrode D are partially alloyed at a temperature of 3500C to 5000C. The FET shown in Fig. 8 substantially resembles that in Fig. 7 and has a feature wherein a source electrode S and a drain electrode D are self-aligned with respect to a gate electrode G, and a metal layer 14' is deposited on a metal layer 14. In this case, the metal layer 14' is not always necessary to constitute the gate electrode. However, the metal layer 14' is automatically deposited when a source electrode 15 and a drain electrode 16 are formed in a self-aligned manner with respect to the gate electrode. The metal layer 14' need not be removed, so it can be left. In order to manufacture the FET in Fig. 8, an ohmic metal layer is deposited to cover the entire surface of a structure before the source electrode S and the drain electrode D of the FET of Fig. 7 are formed. Thereafter, a photoresist pattern is formed to cover the source electrode S, the drain electrode D and the gate electrode G, and an exposed portion of the metal layer is etched by ion milling or the like. The photoresist pattern is then removed, and alloying of the metal layer to provide an ohmic contact is performed. The FET shown in Fig. 9 substantially resembles that in Fig. 7 and has a feature wherein n+-type regions 17 are formed around an n-type GaAs semiconductor layer or region 12 underlying an a-Si region 13 so as to correspond to a source electrode S and a drain electrode D. The type regions 17 are formed such that n-type impurities are doped or ion-implanted at a high concentration through a mask which has. openings respectively corresponding to the source and drain electrodes S and D. More specifically, Si+ ions are selectively ion-implanted in predetermined regions (prospective source and drain electrode regions) of the n-type semiconductor layer 12 at a dose of 2 x 1013 cm 2 or more and at an acceleration voltage of 100 keV. Thereafter, an Si3N4 film is deposited by the chemical vapor deposition (CVD) method to a thickness of about 1,500 , and the resultant structure is annealed at a temperature of 8000C for 20 minutes, thereby forming the n -type regions 17 each of which has a peak impurity concentration of the order of 1018 cm 3. Thereafter, the Si3N4 film is removed by a known etching method such as plasma etching to expose the surface of the n-type GaAs semiconductor layer 12. The subsequent process is the same as that in Fig. 1, thereby preparing the FET shown in Fig. 9. The FET shown in Fig. 10 substantially resembles that in Fig. 9 and has a feature wherein an insulating region (guard ring) 18 is formed to isolate the FET from other FETs formed outside this element formation region. The insulating region 18 is formed by ion-implanting such ions as oxygen, proton and chrominium. For example, oxygen ions are implanted in the substrate 11 at an acceleration voltage of 100 to 300 keV. In this case, a prospective FET formation region is covered with a resist film of 0.5 to 5 Pm thickness or a combination of a resist film and an SiO2 film or Si 3N4 film, thereby preventing damaging of the FET at the time of implanting. The FET shown in Fig. 11 substantially resembles that in Fig. 10 and has a feature wherein an insulating film 19 such as an SiO2 or Si3N4 film is formed on an n-type semiconductor layer between an a-Si region 13 and a source electrode S and between the a-Si region 13 and a drain electrode D. The FET shown in Fig. 12 substantially resembles that in Fig. 11 and has a feature wherein a plurality of gate structures and gate electrodes are formed. The multi-gate FET serves as an inverter wherein independent input signals are supplied to the respective gate electrodes G so as to generate an inverter output by means of logic OR of multiple inputs in the same manner as in a single gate FET. The feature and effects of this FET are the same as those of other FETs of the present invention, except that the logic OR function is added. The FET shown in Fig. 13 substantially resembles that in Fig. 9 and has a feature wherein metal layers 14 of the gate electrode G are deposited on an a-Si region 13. The function of this FET is the same as that in Fig. 12. In the FET in Fig. 13, the thickness of the a-Si region 13 is extremely reduced, and a high electric resistance must be provided such that potential differences between the metal layers 14 of the gate electrode G can be maintained. For example, since the resistivity of a-Si is set to be higher than about 1 Qcm as shown in Fig. 5, the electrical resistance between two metal layers and the a-Si region 13 can be set to be 1 MQ or higher under the conditions that the thickness of the a-Si region 13 is set to be 50 or less and the two metal layers each having a junction gate width of 10 pm are spaced apart from each other by 5 pm or more. Fig. 14 shows an FET wherein two semiconductor layers serve as active layers, and which have a heterojunction in between. This FET has a high-purity low-impurity-concentration (of the order of 1015 cm 3) semiconductor layer 20, for example, comprizing GaAs, which is formed on a GaAs semi-insulating substrate 11. An type semiconductor layer 21, for example, comprizing Go awl s which constitutes the heterojunction is formed on the semiconductor layer 20. An a-Si region 13, a source electrode S and a drain electrode D are formed on the n -type Ga Al As semiconductor layer 21. A metal layer 14 which, together with the a-Si region 13 constitutes a gate electrode G, is formed on the a-Si region 13. The FET in Fig. 14 has an insulating region 18 for electrically isolating the GaAs semiconductor layer 20 and the n -type GaxAl As semiconductor layer 21 from other FETs formed outside the insulating region 18. The GaAs semiconductor layer 20 and the n -type Go awl xAs semiconductor layer 21 which constitute the heterojunction are used as active layers. In this FET configuration, conduction electrons are generated in-a portion of the GaAs semiconductor layer 21 which is located in the vicinity of the heterojunction interface. In association with the description of the FET of Fig. 1, n-type GaxAl1#xAs and InP are used as n-type semiconductor layers serving as the active layers in the second and fourth embodiments, respectively. The same applies to the FETs shown in Figs. 7 to 13. In these cases, semi-insulating GaAll¯xAs and InP substrates are used as the substrates 11, and n-type Ga Al As and InP layers are used as the n-type semiconductor layers 12, respectively Figs. 15 and 16 show embodiments wherein n-type Si semiconductor layers are used as n-type semiconductor layers, respectively. In the FET shown in Fig. IS, an n-type silicon layer 32 serving as an active layer is formed in a p -type silicon substrate 31 having a resistivity of 100 n¯cm. N -type regions 37 are formed in the n-type silicon layer 32 and correspond to source and drain, respectively. A Pt source electrode S and a Pt drain electrode D are deposited on the n -type regions 37. Pt-Si regions 38 are formed underneath the source and drain electrodes S and D, respectively. For the source and drain electrodes, any other metal can be used. An a-Si region 13 is formed on a portion of the n-type silicon layer 32 which is located between the n+-type'regions 37. The a-Si region 13 contains 10 to 60 atom% of B, or 10 to 60 atom% of B and Ge. In order to manufacture the FET shown in Fig. 15, phosphorus ions are ion-implanted in the silicon substrate, 12 -2 for example, at a dose of 1.4 x 10 cm and at an acceleration voltage of 80 keV. The resultant structure is then annealed at a temperature of 8000C for 30 minutes to obtain the n-type silicon layer 32. An n-type impurity such as phosphorus is selectively diffused in the n-type silicon layer 32 to obtain the n -type regions 37. The a-Si region 13 is formed at a predetermined position of the structure, and Pt is deposited on the n+-type regions 37 to a thickness of 2,000 to 3,000 A0. The resultant structure is annealed at a temperature of 4500C for 30 minutes to obtain ohmic contact. Upon annealing, the Pt-Si regions 38 are also formed. The FET shown in Fig. 16 substantially resembles that in Fig. 15 and has a feature wherein a sapphire substrate 39 is used in place of the p -type silicon substrate 31, and an epitaxial layer grown on the sapphire substrate 39 is used as the n-type semiconductor layer 32. The FET shown in Fig. 17 has an n-type silicon layer 42 of a mesa structure which is formed on an n -type silicon substrate 41. A source electrode S is deposited on a top surface of the mesa structure. This FET has a-Si regions 13 on the lower-level surface portions of the mesa structure of the silicon layer 42. Each a-Si region 13 contains 10 to 60 atom% of B or 10 to 60 atom% of B and Ge. A drain electrode D is formed on the bottom surface of the n -type semiconductor substrate 41. The FET shown in Fig. 18 substantially resembles that in Fig. 17 and has a feature wherein a drain electrode D is not formed on the bottom surface of a substrate 41, but drain electrodes D are formed at outer sides of a-Si regions 13. The electrode arrangement of the FET shown in Fig. 19 substantially resembles that in Fig. 18 and has a feature wherein an n-type semiconductor layer 42 does not have a mesa structure, and n -type regions 47 are respectively formed under source and drain electrodes S and D. In the FETs in Figs. 18 and 19, a semi-insulating GaAs substrate is used as the substrate 41 when GaAs is used as the n-type semiconductor layer 42. When a silicon layer is used as the n-type semiconductor layer 42, a sapphire or p -type silicon substrate is used. The same effects as previously described can be obtained in the embodiments shown in Figs. 7 to 19. The present invention is not limited to the particular embodiments described above. The present invention can be applied to electrodes of various types of semiconductor devices so as to obtain the wide, high range of the barrier height Bun'.

Claims: CLAIMS 1. A field effect transistor for integrated circuits, comprising: an n-type semiconductor layer (12); an amorphous silicon region (13) which is formed on a prospective gate region of a major surface of said n-type semiconductor layer (12) and which contains at least boron; a metal layer (14) deposited on said amorphous silicon region (13) so as to constitute a gate electrode (G) together with said amorphous silicon region (13); and source and drain electrodes (S, D) formed on portions of said major surface of said n-type semiconductor layer (12) so that the said gate electrode (G) is in between. 2. A transistor according to claim I, wherein boron contained in said amorphous silicon region (13) has a concentration with a range of 10 to 60 atom%. 3. A transistor according to claim 1, wherein said amorphous silicon region (13) has a particular electronic structure which has localized electron states mainly caused by Anderson localization in an energy region including the Fermi level, said localized electron state density at the Fermi. level is more than the order 1019 cm 3.eV 1, and the width of said energy region is more than 2 eV. 4. A transistor according to claim 1, wherein said amorphous silicon region (13) is formed by a CVD method. 5. A transistor according to claim 1, wherein said n-type semiconductor layer (12) comprises a compound semiconductor layer (12) which is formed on a semi-insulating substrate (11). 6. A transistor according to claim 5, wherein said compound semiconductor layer (12) and said semi-insulating substrate toll) are made of one material selected from the group consisting of GaAs, GaAli#xAs and InP. 7. A transistor according to claim I, wherein said n-type semiconductor layer (12) comprises a monocrystalline silicon layer which is formed on an insulating substrate or on a p-type silicon substrate or in a p-type silicon substrate. 8. A transistor according to claim 1, wherein said amorphous silicon region (13) contains germanium in addition to boron. 9. A transistor according to claim 1, wherein said amorphous silicon region (13) further contains an element serving as a p-type impurity with respect to said n-type semiconductor layer. 10. A field effect transistor for integrated circuits, comprising: a semi-insulating substrate; a high-purity semiconductor layer on said semi-insulating substrate; an n-type semiconductor layer (12) formed on top of said high-purity semiconductor layer so as to constitute a heterojunction therewith; an amorphous silicon region (13) which is formed on part of a major surface of said n-type semiconductor layer and which contains at least boron; a metal layer (14) formed on said amorphous silicon region so as to constitute a gate electrode (6) together with said amorphous silicon region; and source and drain electrodes (S, D) deposited on portions of said major surface of said n-type semiconductor layer so that said gate electrode is in between. 11. A transistor according to claim 10, wherein boron contained in said amorphous silicon region (13) has a concentration with a range of 10 to 60 atom%. 12. A transistor according to claim 10, wherein said amorphous silicon region (13) further contains germanium in addition to boron. 13. A transistor according to claim 10, wherein said amorphous silicon region (13) further contains an element serving as a p-type impurity with respect to said n-type semiconductor layer. 14. A field effect transistor for integrated circuits, comprising: an n+-type silicon substrate; an n-type silicon layer (12) formed on said n -type silicon substrate; amorphous silicon regions (13) which are formed on one major surface of said n-type silicon layer and which contain at least boron; a plurality of gate electrodes (G) which are respectively formed on said amorphous silicon regions and which constitute a gate structure together with said amorphous silicon regions; a source electrode (S) formed at a portion of said one major surface of said n-type silicon layer which is located between said amorphous silicon regions; and a drain electrode (D) formed on the other major surface of said n -type silicon substrate which is not in contact with said n-type silicon layer. 15. A transistor according to claim 14, wherein boron contained in said amorphous silicon regions (13) has a concentration with a range of 10 to 60 atom%. 16. A transistor according to claim 14, wherein said amorphous silicon regions (13) further contain germanium in addition to boron. 17. A transistor according to claim 14, wherein said amorphous silicon regions (13) further contain an element serving as a p-type impurity with respect to said n-type semiconductor layer.

Inventors: AMEMIYA, YOSHIHITO, ASAI, KAZUYOSHI, KURUMADA, KATSUHIKO, MIZUSHIMA, YOSHIHIKO, MURASE, KATSUMI, OGINO, TOSHIO, SUZUKI, MASAMITSU
Applicants: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1984
Main classification: H01L29
IPC codes: H01L29, H01L21