Method and apparatus for recording a digital information signal

Abstract: A method of recording a digital data signal, such as an audio PCM signal, onto a recording medium in the lon­ gitudinal direction thereof, together with an apparatus which is suitable for this recording method. Even-­ numbered words and odd-numbered words in a digital data signal are recorded on a first track group and a second track group, respectively, which are separated from each other in the widthwise direction of a recording medium, to prevent a series of words becoming error words because of, for example, a flaw in the recording medium in the longitudinal direction thereof. The data format is chang­ ed at the input and output of a recording encoder to enable an error correction code and a recording circuit to be used in common for digital tape recorders which have different numbers of tracks, e.g., n tracks and 2n tracks. When an error correction code is recorded in such a manner that one word in the digital data signal is divided into a plurality of symbols which are formed into an error correction code, a plurality of symbols of the same word are recorded at a position at which error correlation is strong, making effective use of the error correction capacity of the error correction code.

Description: The present invention relates to a method and an apparatus for recording a digital information signal which are suitable for use in the recording of a digital information signal such as an audio PCM signal or the like on a recording medium, particularly, on a magnetic tape. There has been proposed a digital tape recorder which records an audio PCM signal as parallel multitracks on a magnetic tape enclosed in a cassette casing by fixed heads. For digital tape recorders of such a multitrack type, there has been considered a recording method whereby the 16-bit linear quantized two-channel audio PCM signal derived at a sampling rate of 44.1 KHz is recorded at about 1.4 M bits/second on twenty tracks of the magnetic tape which is running at a tape speed of 4.76 cm/sec. There has been considered another recording method whereby the 16-bit linear quantized two-channel audio PCM signal in the sampling rate of 68 KHz is recorded as the recording data of about 1.8 M bits/second on twenty tracks of the magnetic tape which is running at a tape speed of 5.18 cm/sec (hereinafter, referred to as 2M mode). Further, another recording method has been considered whereby the 12-bit non-linear quantized two-channel audio PCM signal derived by a lower sampling rate of, for example, 32 KHz is recorded on the magnetic tape at about 0.9 M bits/second so as not to substantially cause any trouble in the recording and reproduction in the audible frequency band (hereinafter, referred to as 1M mode). These recording methods are set in accordance with the particular end use or the like. In the recording method called the 1M mode, the amount of data which is recorded is one half as compared with that in another recording mode called the 2M mode, in which the number of tracks of recorded data is selected as twenty, the tape speed can be reduced to half (2.6 cm/sec) of the 2M mode, thereby enabling a longer recording time to be obtained. On the contrary, if the tape speed is set to be equal to that in the 2M mode, the same amount of data can be recorded on the ten tracks. If the number of tracks is reduced to half, the track pitch can be doubled. Therefore, this makes it possible to easily perform the tracking operation upon reproduction. It is considered that this recording method using the 10-tracks in the 1M mode will come into wide use before the recording method using the 20-tracks. However, when superiority of the performance of the 20-tracks type is considered, there is a risk such that the 10-tracks type will have been neglected as an old-fashioned method. Therefore, it is a requirement that the magnetic tape recorded by the 1M-mode method using ten tracks can be compatibly reproduced by the 2M-mode tape recorder using twenty tracks. This compatibility is needed to be satisfied as well even with respect to not only the track pattern but also the error correction codes. GB-A-2 082 098 discloses an apparatus as defined in the preamble of the appended claims. In the disclosed embodiment N parallel data sequences are encoded resulting in the addition of n error correction codewords sequences. The N+n parallel sequences are distributed onto M tracks. Especially N, n and M equal to 6, 2 and 4, respectively, is disclosed. GB-A-2 080 997 discloses a method and an apparatus wherein a plurality of digital signal channels is recorded on a recording medium. The number of tracks corresponds to the number of channels. Each word of each channel is converted from parallel to serial. It is an object of the present invention to provide a method and an apparatus for recording a digital information signal in which in case of recording a digital information signal in an n-track mode the same error correction code can be used as for a method and an apparatus using a 2 n -tape mode and thereby to make it possible the error correction codes and the corresponding hardware to be used for both n -track mode and 2 n -track mode. To achieve this object the method of this invention has the features of claim 1 and the apparatus of this invention has the features of claim 2. Therefore the error correction codes can be unified for both n -track mode and 2 n -track mode, and the hardware can be commonly used and further, the tape recorded in the n -track mode can be compatibly reproduced in the 2 n -track mode. Also, even if data is recorded in the n -track mode, a strong error correcting capability can be obtained. Fig. 1 is a tape pattern diagram showing track arrangements in the 20-tracks mode and 10-tracks mode in a digital audio tape recorder; Fig. 2 is a block diagram showing the main part of a recording system of a digital tape recorder showing one embodiment of the present invention; Fig. 3 is a data format diagram showing a data process in a 12-16 converter in Fig. 2; Figs. 4A - 4D are block diagrams showing an encoding section and a track distributor in Fig. 2; Fig. 5 is a schematic diagram showing an arrangement of one block of a recording data; Figs. 6 to 8 are schematic diagrams which are used for explaining a recording format in case of the 20-tracks mode; Fig. 9 is a schematic diagram showing a recording format in case of the 10-tracks mode corresponding to Fig. 7; and Fig. 10 is a block diagram showing an example of an arrangement of the track distributor. One embodiment in the case where the present invention is applied to a digital tape recorder will now be described hereinbelow with reference to the drawings. Fig. 1A shows an arrangement of tracks of a digital tape recorder which can selectively record on and reproduce from twenty tracks, respectively. Tracks in the forward path are formed at positions indicated at T1, T2, ..., T20 in one of the areas of a magnetic tape 60 divided by a longitudinal center line C by means of twenty thin film heads arranged in the widthwise direction of the magnetic tape in correspondence to the twenty tracks. By reversing a tape cassette, tracks in the backward path are symmetrically formed in the other area relative to the center line C. Fig. 1B shows an arrangement of tracks of a digital tape recorder which can selectively record on and reproduce from ten tracks. As shown in Fig. 1B, a track width and track pitch are approximately twice as large as those in case of twenty tracks, so that the degree of accuracy regarding the locations where the magnetic heads are attached and the degree of tracking accuracy may be reduced. In this case assuming that a digital information signal is recorded in the track arrangement shown in Fig. 1B, in order to enable the magnetic tape so recorded to be also reproduced by a tape recorder having the track arrangement shown in Fig. 1A, the locations in both track arrangements must be aligned. Fig. 2 is a block diagram showing an overall recording circuit in which a two-channel audio PCM signal of non-linearly quantized twelve bits in a sampling rate of 32 kHz is supplied to this recording circuit. This audio PCM signal is supplied to an encoding section 30 through a 12-16 converter indicated at 20. Outputs of the encoding section 30 are supplied to a track distributor 40. Recording data corresponding to ten tracks are outputted from the track distributor 40 and are recorded on the magnetic tape by recording heads 50. This encoding section 30 is the same of the encoding section which would be used if recording on twenty tracks. The error correcting processes in the 1M and 2M modes are the same. The 12-16 converter 20 divides the 12-bit input data into the 16-bit time slots and can process the 12-bit input data in a similar manner as the 16-bit quantized data at the sampling rate of 48 kHz, which is the desired input to the encoding section 30. The track distributor 40 serves to distribute the output data of twenty tracks that was processed in the encoding section 30 to the recording heads 50 of ten tracks. This track distributor 40 is, for example, a buffer memory and converts data which should be recorded on two tracks to the data which can be recorded together on one track. The encoding section 30 performs the error correction coding of, e.g., CIRC codes (cross interleaved Reed Solomon codes). Namely, the encoding section 30 is constituted by delay element group 4 for performing the even-odd interleaving and a C2 encoder 6 and delay element group 7 for performing the interleaving and a C1 encoder 10. The converting process of the 12-16 converter 20 will now be described with reference to Fig. 3, in which line A shows a series of two symbols (indicated together with suffixes A and B) each of which has six bits and which are obtained by dividing each of the words (12 bits) L'₀, L'₁ ..., L'₇ of the audio PCM signal in one channel into two parts. This data series is combined into sets each consisting of four symbols which as shown in line B of Fig. 3 are four even numbered words and which have the suffixes of A or B. These sets, each having four symbols, having a length of 24 bits as a whole are respectively constituted by the symbols included in the even numbered words and are having the same suffixes, A or B. The odd numbered words are likewise combined into sets, each of which consists of four symbols and having a length of 24 bits. As shown in line C of Fig. 3, these sets (24 bits) each consisting of four 6-bit symbols are converted into sets each consisting of three eight-bits symbols. More specifically, 24 bits are divided into three parts each consisting of eight bits and each part can be regarded as an 8-bit symbol. As shown in line D of Fig. 3, these 8-bits symbols (L 0,A ; L 2,A ; ...; L 5,B ) after conversion are rearranged to the original sequence and are inputted to the encoding section 30. The execution of this bit conversion enables the even-odd interleaving to be performed just as in the case where one word consists of sixteen bits, thereby preventing reduction of the error correcting capability. The C2 encoder 6 performs the encoding process of the error correction codes C2 for every 16 symbols. Since the foregoing bit conversion is carried out on a three-symbol unit basis, the fraction of one symbol is caused. However, since the information symbols in one block consist of 480 symbois, this fraction is not forced out of one block. Therefore, this makes it possible to prevent the processing cycle from becoming to long by preventing the decoding of the results of adjacent blocks. Fig. 4 shows a detailed arrangement of the encoding section 30. Fig. 4A shows the input side and the signal processes are performed in accordance with the sequence of Fig. 4B, Fig. 4C and Fig. 4D. In Fig. 4A, a reference numeral 1 denotes input symbols of the audio PCM signal to be recorded. Each of eight words per each channel; namely, (L 8n , L 8n+1 , ..., L 8n+7 in the left channel) and (R 8n , R 8n+1 , ..., R 8n+7 in the right channel) is divided every two symbols, and the total 32 symbols are synchronously inputted. As shown in Fig. 4A, the symbols of W 16n+i (where, i = 0, 1, 4, 5, 8, 9, 12, 13) denote the symbols of the even-number designated words. And the symbols of W 16n+j (where, j = 2, 3, 6, 7, 10, 11, 14, 15) indicate the symbols of the odd-number designated words. In addition, the symbols to which the suffix A is added denote the most significant 8-bits of one word. The symbols to which the suffix B is added represent the least significant 8-bits of one word. The above-mentioned input symbols are supplied to a delay element group 2. This delay element group 2 is constituted by sixteen delay elements for delaying only the symbols with the suffix B. The outputs of the delay element group 2 are supplied to a switching circuit 3. The switching circuit 3 alternately selects the inputted 16 symbols having the suffix A and the 16 symbols having the suffix of B, which were delayed by one symbol amount, and outputs the selected symbols, thereby permitting the C2 encoder that is the following stage to operate on a time-sharing basis. The outputs of the switching circuit 3 are supplied to the delay element group 4. The delay element group 4 supplies the symbols W 16n+i,A or W 16n+i,B of the even-numbered words to the C2 encoder 6 (Fig. 4B) without being delayed, and meanwhile it supplies the symbols W 16n+j,A or W 16n+j,B of the odd-numbered words to the C2 encoder 6 after being delayed by amount of D₀. Due to this delay element group 4, the symbols of the even-numbered words and the symbols of the odd-numbered words which are adjacent each other are recorded at the positions which are away from each other by an amount D₀ in the longitudinal direction of a magnetic tape. This process is referred to as even-odd interleaving in the longitudinal direction. The amount D₀ is selected to be, for example, equal to, a length of 900 symbols. Signal lines 5 as the outputs of the delay element group 4 are exchanged and connected to the C2 encoder 6. After the signal lines 5 are exchanged, the symbols of the odd-numbered words and the symbols of the even-numbered words are also alternately located. Fig. 4B shows sixteen symbols inputs to the C2 encoder 6 in which only symbols having the suffix A are selected by the switching circuit 3. The C2 encoder 6 serves to perform the encoding process of the (20, 16) Reed Solomon codes C2. The C2 encoder 6 outputs twenty symbols consisting of four parity symbols of Q 4n , Q 4n+1 , Q 4n+2 , and Q 4n+3 and sixteen information symbols. In the (20,16) Reed-Solomon Code 2 the distance between the error correction codes C2 is (d = 5). On the other hand, the outputs of the C2 on the Galois field encoder 6 are constituted in a manner such that the parity symbols Q 4n , ..., Q 4n+3 are respectively arranged before every four information symbols. The outputs of the C2 encoder 6 are supplied to the delay element group 7 as shown in Fig. 4B. Assuming that a unit delay amount is D₁, the delay element group 7 delays each of the twenty symbols by each of the delay amounts of 0, D₁, 2D₁, ..., and 19D₁ such that these delay amounts are increased sequentially by D₁. Due to this delay element group 7, the twenty symbols forming the same code series from the C2 encoder 6 are interleaved so as to be recorded with the distance of D₁ in the longitudinal direction of the magnetic tape. The amount of delay D₁ is set to, for example, be equivalent in lenght to 30 symbols. The outputs of the delay element group 7 are supplied to a shift register circuit group 8. The shift register circuit group 8 has twenty shift registers of (8 bits x 30 stages), in which each stage has eight parallel output lines. The parallel outputs of the shift register circuit group 8 are supplied to the C1 encoder 10 through a switching circuit 9. The switching circuit 9 sequentially selects the thirty symbols stored in each of the twenty shift registers and supplies them to the C1 encoder 10. In this embodiment, the 30 symbols fetched from each shift register are included in one block and the encoding process of the error correction codes C1 is performed on this block unit basis. The (32, 30) Reed Solomon codes are used as the error correction codes C1, in which distance betwenn the error correction codes C1 on the Galois field is (d = 3). At the outputs of the C1 encoder 10, 32 symbols including two parity symbols (indicated by P) appear. The symbols shown in Fig. 4B are generated when the switching circuit 9 selects, as illustrated, the outputs of the shift registers in which parity symbols Q 4n , Q 4n-4 , ..., Q 4n-116 are stored. The 32 symbols which are outputted from the C1 encoder 10 are supplied to a shift register circuit group 12 through a switching circuit 11 as shown in Fig. 4C. The shift register circuit group 12 has twenty shift registers of (8 bits x 32 stages + 32 bits). Namely, each shift register in the shift register circuit group 12 has 288 bits which are equal to the length of one block. The parallel inputs for adding a block sync signal and the like are supplied to the 32 bits which are first fetched as the serial output of the shift register. Fig. 4C shows an arrangement for this addition with respect to only one shift register; arrangements regarding the others are omitted in the diagram. A flag signal indicative of the control information necessary for process of data in each block or each track is supplied to a terminal 13. For instance, the flag signal indicates the number of bits of a sampled word, sampling frequency, on/off of pre-emphasis, auto-reverse mode or not, discrimination of the 20-track mode or 10-track mode, discrimination of two channels or four channels, and the like of the audio PCM signal recorded. Track addresses representative of track numbers are supplied to a terminal 14. Block addresses are supplied to a terminal 15 and a block sync signal is supplied to a terminal 16. These flag signal, track addresses and block addresses are supplied to the shift registers and a CRC encoder 17, so that the encoding process for error detection is performed. The redundant code (called the CRC code) of these CRC codes is also supplied to the shift registers. Fig. 5 shows a data arrangement of one block which is serially outputted from each shift register in the shift register circuit group 12. The 8-bit block sync signal is arranged at the beginning of one block, then the 4-bit flag signal, 2-bit track address, 8-bit block address, and 12-bit CRC code are arranged sequentially, with number thereof being 32 bits. The track address may serve to discriminate a few adjacent tracks. After these 32 bits, thirty information symbols (240 bits) are located. Two symbols of the paritys P of the error correction codes C1 for these information symbols are arranged at the last in the one block. The data is recorded on the magnetic tape using this one block (288 bits) as a unit. As shown in Fig. 4D, signal lines 18 led from the respective shift registers in the foregoing shift register circuit group 12 are subjected to the exchanging process and are supplied to a recording circuit. In the tape recorder having twenty tracks (see Fig. 1A), the above signal lines 18 are supplied directly to the channel encoder after they were exchanged. However, because this embodiment relates to the tape recorder of the ten-tracks (see Fig. 1B), the outputs of the signal lines 18 must be first time-shared multiplexed by the track distributor 40 so as to have the proper number of outputs for the ten tracks. That is, the outputs of the adjacent two signal lines are combined to one. The track distributor 40 consists of switching circuits 41 and buffer memories 42. Each switching circuit 41 selects the signals which are on the adjacent odd-numbered and even-numbered signal lines 18 in accordance with the transmission timing of the shift register circuit group 12, thereby allowing them to be sequentially stored into a front stage section 42A and a rear stage section 42B of each buffer memory 42. The contents of these front and rear stage sections 42A and 42B are serially outputted and supplied to a channel encoder or modulator 48 corresponding to each track. The channel encoder 48 has ten digital modulators which are equal to the number of tracks to be recorded. The outputs of the channel encoder 48 are supplied to the recording heads 50 through a recording amplifier group 49. The recording heads 50 are constituted by, for instance, thin film magnetic heads having ten gaps corresponding to the tracks respectively. The recording is performed on ten tracks which are numbered sequentially from the upper edge of the magnetic tape. Although in this embodiment the above-mentioned delay processes, exchanging processes of the signal lines, processes in the shift registers in the encoding section 30, and time-shared multiplexing processes by the switching circuits 41 and buffer memories 42 are described as being carried out by discrete circuit components, the necessary functions could also be executed by a random access memory (RAM), which is controlled by a microprogram. The foregoing encoding processes will then be described while comparing the 20-track mode with the 10track mode. The data which is fetched on the signal lines 18 as the outputs of the shift register circuit group 12 in the 20-track mode is fundamentally the same as the data appearing as the outputs of the C2 encoder 6 if the interleaving in the longitudinal direction of the tape by the delay element group 7 is ignored. More specifically, when the twenty signal lines 18 are numbered sequentially from the top, the parity symbols Q of the error correction codes C2 are fetched on the respective 1st, 6th, 11th, and 16th signal lines, and the symbols of the even numbered words are fetched on the respective eight 3rd, 5th, 8th, 10th,13th, 15th, 18th, and 20th signal lines. Further, the symbols of the odd numbered words are fetched on the respective 2nd, 4th, 7th, 9th, 12th, 14th, 17th, and 19th signal lines. On the other hand, by interchanging those signal lines 18, it permits the in case of the 20-track mode, shown in Fig. 7, the parity symbols Q of the error correction codes C2 to be recorded on the 1st to 4th tracks near the upper edge, and the symbols of the odd numbered words to be recorded on the next 5th to 12th tracks, and the symbols of the even numbered words to be recorded on the 13th to 20th tracks near the lower edge. In this way, by exchanging the signal lines 18, the symbols of the odd numbered words are recorded on the eight tracks located on the upper side in the direction of a width of the magnetic tape, while the symbols of the even numbered words are recorded on the eight tracks located on the lower side. Thus, the even-odd interleaving in the longitudinal direction can be performed. Since the parity symbols Q are redundant data that have lower significance than the information data, they are recorded on the tracks near the edge where errors easily occur due to the turn-over, damage or the like of the edge. Fig. 6 shows the data recorded on the magnetic tape. The encoding process of the error correction codes C1 is performed for every one block of the C2 parity symbols and the blocks consisting of the information symbols with the C1 parities P of two symbols being added thereto. Therefore, twenty blocks arranged in the direction of a width of the tape are constituted by the C2 parities Q of (30 x 4 = ]20 symbols), information symbols of (30 x 16 = 480 symbols) and C1 parities P of (2 x 20 = 40 symbols). On the other hand, since two symbols constituting one word are delayed by amount of one symbol by the delay element group 2, these two symbols are recorded as adjacent symbols in the same block. The error correction encoding processes are performed for the sixteen symbols having the suffix of A and for the sixteen symbols having the suffix of B, respectively. In Fig. 6, a C2 series (A) and a C2 series (B) as indicated by oblique lines are produced. For example, in Fig. 6, four symbols indicated by Δ are (Q 4n ; Q 4n+4 ; W 16n+2-16D0,A ; W 16n+2-16D0,B ). The Q 4n and W 16n+2-16D0,A are included in the C2 series (A) and the other two symbols are included in the C2 series (B). As shown in Fig. 8, when it is assumed that the 16 symbols with the suffix of A among the 32 symbols corresponding to the eight successive words per channel of the audio PCM signal are represented by D₀, D₁, ..., D₁₅, respectively, are these 16 symbols recorded on the magnetic tape at the locations shown in Fig. 7. The symbols of the odd-number designated words are delayed by the delay element group 4 (unit delay amount is D₀) in the encoding section 30, so that the symbols D j (j = 2, 3, 6, 7, 10, 11, 14, 15) of the odd-number designated words are recorded at positions behind the even-numbered words designated by the symbols D i (i = 0, 1, 4, 5, 8, 9, 12, 13). In this embodiment, the time difference D₀ between them is set to thirty blocks. Due to the exchanging of the signal lines 5, the lines connecting the twenty symbols which form the common C2 series (A) become the folded lines as shown in Fig. 7. In the two C2 series (A) as illustrated, the symbols to which the signs of the symbols D i and D j are not added denote the other symbols which are outputted from the delay element group 4. One C2 series (A) is distributed so as to be recorded in the intervals corresponding to twenty blocks in the longitudinal direction of the tape. Therefore, the guard space corresponding to ten blocks in the longitudinal direction of the tape is interposed so that the even-odd interleaving is performed in the longitudinal direction of the tape on which the sets of the symbols D i and the sets of the symbols D j are recorded. Due to the exchanging processes of the signal lines 18, the parities Q of the C2 series are recorded on the 1st to 4th tracks, the symbols D j are recorded on the 5th to 12th tracks, the symbols D i are recorded on the 13th to 20th tracks, and the interleaving in the direction of a width is performed. Thus, the C2 series (B) which is formed by the symbols to which the suffix of B is added as shown in Fig. 8 can be represented by parallel folded lines after one symbol of the C2 series (A) shown in Fig. 7. Fig. 6 shows, therefore, a concrete diagram of the first two blocks passed by those parallel folded lines, as shown in Fig. 7 and especially tracks numbered 1 to 4. In the tape recorder having ten tracks in the 1M mode, as described before, the twenty outputs of the encoding section 30 are subjected to the time-shared multiplexing processes by the track distributor 40 and are recorded on the ten tracks. Therefore, the data is recorded in a recording pattern as shown in Fig. 9, such that the tracks with the recording pattern of Fig. 7 are thinned out every other track and the data Q₁, Q₃, D₈, D₉, and the like included in these thinned out tracks are shifted respectively, onto the tracks just preceding those tracks. Namely, the data existing on the 2ith (i = 1, 2, ..., 10) tracks may be shifted onto the (2i-1)th (i = 1, 2 ..., 10) tracks and the (2i-1)th tracks may be numbered like (i = 1, 2, ..., 10). Fig. 9 shows the C2 series (A) which is formed by the even-numbered words of the symbols to which the suffix A is added as shown in Fig. 8. The C2 series (A) by the symbols of the odd-numbered words is formed after thirty blocks similarly to Fig. 7, although it is not shown. Consequently, even in this embodiment of the ten-tracks pattern, the even-odd interleaving in the widthwise direction of the tape and the even-odd interleaving in the longitudinal direction of the tape are carried out. The data recorded on the ten tracks in the 1M mode is reproduced from the magnetic tape 60 and is supplied to a data arrangement converter through a reproducing amplifier and a channel decoder. The data format of this data corresponding to the ten tracks is converted to the data corresponding to the twenty tracks. The converted data is supplied to a reproducing decoder for performing the processes opposite to those in the encoding section 30. This reproducing decoder has the same arrangement as the reproducing decoder which is used in the digital tape recorder of the twenty tracks in the 2M mode, so that it performs the error correcting and deinterleaving processes with respect to the data corresponding to the twenty tracks. Since the two error correction codes C1 and C2 are employed the error correcting operation or error detecting operation is first executed by means of the error correction codes C1. The error correction by the error correction codes C2 is performed using an error pointer indicative of the result of this error detection. The erroneous words including the symbols which cannot be error-corrected are subjected to the mean value interpolation by the error correcting circuit. These processes are quite the same with regard to both digital tape recorders having ten and twenty tracks. The principal part of the hardware in the digital tape recorder in the 10-track mode in this embodiment is common to that of the digital tape recorder of the 20-track mode. Therefore, as shown in Fig. 10, to realize this hardware as an LSI, there are provided a switch 45 to bypass the section of the track distributor 40 and a switch 46 to lead the even-numbered encoding outputs to the recording circuits regarding even-numbered heads 20T2, 20T4, ... of the tape recorder having the twenty tracks. When the tape recorder having the 20 tracks operates in the 2M mode in which the times-sharing multiplexing is not needed, the switches 45 and 46 are connected.

Claims: A method of recording a digital information comprising the steps of: a) supplying the digital signal in the form of sets of a first plurality of inputwords in parallel to an encoding means (30); b) encoding each set of supplied inputwords by performing an error detection and correction coding process, forming a set of 2n parallel outputsymbols for each set of inputwords; c) multiplexing, converting and supplying each set of 2n parallel outputsymbols to n parallel recording means (48, 49, 50), and d) recording said supplied symbols on n parallel tracks which are formed longitudinally on a recording medium, characterized in that said step of supplying the digital signal comprises the step of: e) dividing each inputword into a first word containing the most significant bits of the inputword and a second word containing the least significant bits of the inputword thereby dividing each set of inputwords in a set of first words and a set of second words; and said step of encoding comprises: f) a first step of encoding the set of first words forming a set of 2n parallel outputwords and then a second step of encoding the set of second words forming another set of 2n parallel outputwords. An apparatus for recording a digital information, comprising means for supplying the digital signal in form of sets of a first plurality of inputwords in parallel to an encoding means (30), said encoding means (30) encoding each set of supplied inputwords by performing an error detection and correction coding process, forming a set of 2n parallel outputsymbols for each set of inputwords, means for multiplexing, converting and supplying each set of 2n parallel outputsymbols to n parallel recording means (48, 49, 50), said recording means (48, 49, 50) recording said supplied symbols on a recording medium characterized in that said supplying means being adapted to divide each inputword into a first word containing the most significant bits of the inputword and a second word containing the least significant bits of the inputword, thereby dividing each set of inputwords in a set of first words and a set of second words, and said encoding means (30) comprising a first encoder (6) encoding the set of first words forming a set of 2n parallel outputwords and a second encoder (10) encoding the set of second words forming another set of 2n parallel outputwords.

Inventors: KOJIMA YUICHI, NAKAI JUN, OSAWA EIICHI, TANAKA MASATO, YOSHIZAWA MAMORU, KOJIMA, YUICHI, NAKAI, JUN, OSAWA, EIICHI, TANAKA, MASATO, YOSHIZAWA, MAMORU
Applicants: SONY CORP, SONY CORPORATION
Application year: 1984
Main classification: G11B20
IPC codes: G11B5, G11B20