SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device for example having a multi-bit output structure comprises a plurality of memory cell blocks (10, 12), a data bus (18, 20) corresponding to each memory cell block, a plurality of groups of redundant memory cells (14, 16), and switching circuits (S₁, S₂, S₃). The switch­ ing circuits selectively connect the output of a group of re­ dundant memory cells to the data bus of a memory cell block having a defective column of memory cells, to replace the defective column. The switching circuits can thereby restore defects in the device even when a plurality of defective col­ umns occur in the same memory cell block.

Description: The present invention relates to a semiconductor memory device, in particular, it relates to a semiconductor memory device providing redundant cells. Recently, the capacity of semiconductor memory devices has been and is being greatly increased, and this increase in the capacity of a semiconductor memory device leads to a high probability that some of the memory cells therein will be defective, thus rendering the entire memory defective. To alleviate this problem, there is known a method for providing redundant memory cells and of using these redundant memory cells to replace defective memory cells. The provision of a large number of redundant cell groups is useful if a large number of defective memory cells are produced in a cell block. However, where defective memory cells are not produced, the provision of so many redundant cell groups is unnecessary, in that there is no use for them. Thus, usually, only one column or 2 to 3 columns of redundant cell groups are provided (per cell block). Further, in the conventional system, the redundant cell groups are linked exclusively to individual cell blocks. When a redundant cell group is linked to an individual cell block, the following problems arise. That is, suppose that one column of redundant cells is provided for each cell block, and that two defective memory cells existing in different columns are produced in a first cell block but no defective cells are produced in a second cell block. In this case, although there are two redundant cell groups and two defective memory cells, the two redundant cell groups are linked to different cell blocks, and therefore, the redundant cell group in the second cell block cannot be used for the first cell block. Thus, only one redundant cell group can be utilised, to replace only one of the defective cells of the first cell block; the other defective cell cannot be replaced and the functioning of the memory device is deteriorated. It is desirable to alleviate the above problem by providing a semiconductor memory device in which the redundant cell groups can be used freely by changing the linking of these cell groups to a particular cell block, and thus enabling a larger number of defective memory cells to be replaced by a smaller number of redundant cell groups. PCT/US82/01826 discloses such a semiconductor memory device, in which spare columns of cells can be assigned to replace defective columns in any of eight bit segments. However, in this device, special column address switches are provided to activate each spare column in response to a column address of a defective column, and the outputs of the column address switches are multiplexed together with the output of normal columns of cells. As a result, there is a delay in accessing the device, and accesses take different times depending on whether a normal column or spare column is being accessed. US-A-4,346,459 discloses another such semiconductor memory device, which has special spare column select circuits which are switched during normal operation of the device, and hence has similar drawbacks. According to the present invention there is provided a semiconductor memory device comprising: first and second cell blocks, each comprising a plurality of cell groups, each cell group comprising a plurality of memory cells; a redundant cell group comprising a plurality of memory cells; first and second data buses corresponding respectively to the first and second cell blocks; decoder circuitry for selecting one of the cell groups; and switching circuitry responsive to said decoder circuitry for connecting the redundant cell group to either of said first or second data buses corresponding to the first and second cell blocks; characterised in that the redundant cell group is arranged between the first and second cell blocks; each cell group is connected to the data bus corresponding to its block via a respective selection gate controlled by said decoder circuitry; and in that the switching circuitry comprises gates arranged, and controlled by said decoder circuitry, in parallel with said selection gates, and permanently-settable switch circuits for permanently connecting the redundant cell group to either of said first or second data buses. Thus, by means of the present invention it is possible to provide flexibility in assigning redundant cell groups to defective cell groups, without adversely affecting the overall performance of the device. Reference is made, by way of example, to the accompanying drawings in which:- Figure 1 is a block diagram showing one example of a prior art semiconductor device; Figure 2 is a block diagram showing a partially detailed portion of the device shown in Figure 1; Figure 3 is a block diagram showing an embodiment of the present invention; Figures 4A, 4B, and 4C are circuit diagrams showing partially detailed portions of the device shown in Fig. 3; Figure 5 is another embodiment corresponding to Fig. 4B; Figure 6 is a flowchart explaining the operation of the device shown in Figs. 4A, 4B, and 4C; and Figure 7 is a block diagram showing the present invention applied to a memory device having a multi-bit connection. Figure 1 shows one example of a conventional semiconductor memory device providing redundant cells. In Fig. 1, 10 and 12 represent cell blocks and 14 and 16 redundant cell groups. As is already known, the cell blocks 10 and 12 arrange the memory cells at cross points of many word lines and bit lines (or row lines and column lines), and Y o to Y n are signals for selecting the bit lines. The word lines (not shown in the drawing), extend in a horizontal direction, and redundant cells are provided for one bit line (1 column) and are selected by a selection signal Y a . Numerals 18 and 20 are data buses and 22 and 24 are I/O (input output) buffers. This memory is organized for 2 bit output, so that when memory cells are selected by any address, the corresponding memory cells in cell blocks 10 and 12 are read out, and one bit from each I/O buffer 22 and 24, i.e., a total of two bits, are output at the same time. As the cell blocks and the redundant cell groups are selected by the same address, for simplicity, it is preferable that the word lines are commonly used. Figure 2 shows such a construction, in which WL shows a word line and BL shows a bit line, each are shown as only one line or as a pair of lines. MC is a memory cell, and in Fig. 2, a static random access memory (SRAM) is shown as an example, wherein the MC is formed by a flip-flop. RD is a row decoder, which receives word line selection addresses A o ∼ A n and selects a word line WL when these addresses are at a low (L) level. The word lines WL extend over the cell block 10, the redundant cell groups 14, 16, and the cell block 12, and each word line WL is selected at the same time by the word line address. The I/O buffers include a sense amplifier SA and an input (write) data buffer O/N, etc. These memory devices are tested during manufacture, and when defective cells are found in the cell block, the defective address informations are written in a read-only memory (ROM) (not shown in the drawings). If a defective address is selected while the memory is in use, a column decoder which outputs Y o ∼ Y n is made noneffective (all outputs of the decoder are made at a low level), and a signal Y a for selecting a redundant cell group is generated. The word lines are common to the cell blocks and redundant cell groups, so that the memory cells on the word lines for the redundant memory cell groups are selected instead of the defective memory cells. The provision of a large number of redundant cell groups is useful if a large number of defective memory cells are produced in the cell block. However, where defective memory cells are not produced, the provision of so many redundant cell groups is unnecessary, in that there is no use for them. Thus, usually, only one column or 2 ∼ 3 columns of the redundant cell groups are provided. Further, in the conventional system, the redundant cell groups are linked exclusively to an individual cell block. That is, as shown in Fig. 1, the redundant cell group 14 is linked to cell block 10 and the redundant cell group 16 is linked to cell block 12. This is determined by to which data bus the redundant cell group is connected. When a redundant cell group is linked to a cell block in such a manner, the following problems arise. That is, suppose that one column of the redundant cells is provided for each cell block, and that two defective memory cells linked to different columns are produced in cell block 10 but no defective cells are produced in cell block 12. In this case, although there are two redundant cell groups and two defective memory cells, the two redundant cell groups are linked to different cell blocks, and therefore, the redundant cell group 16 cannot be used for cell block 10. Thus, only one redundant cell group 14 can be used to replace one defective cell , and therefore, the other defective memory cell cannot be replaced and the functioning of the memory device is impaired. Figure 3 shows an embodiment of the present invention in which the same elements as in Fig. 1 are designated by the same symbols. As is clear from a comparison of Figs. 1 and 3, in the present invention, switches S₁ ∼ S₃ are provided to connect the redundant cell groups 14 and 16 to either of the data buses 18 and 20. Immediately after the memory device is manufactured, the switches S₁ ∼ S₃ are open. When no defective memory cell are found in the cell block 10, the redundant cell group 14 is not used, and when the defective memory cell exists in a column in the cell block 10, the switch S₂ is closed and the defective memory cell can be replaced by the redundant cell group 14. The same applies to the cell block 12. Up to this point, the device is similar to the conventional system. However, if two defective memory cells are produced in cell block 10, over two columns and no defective memory cell exists in cell block 12, such a case cannot be handled in the conventional system, but can be dealt with in the present invention, as shown below. That is, when the above feature occurs; the switches S₁ and S₂ are closed. Therefore, the redundant cell group 16 is linked to cell block 10, so that the defective memory cell belonging to one column of cell block 10 can be replaced by the redundant cell group 14, and the defective memory cell belonging to another column of the memory cell group 10 can be replaced by the redundant cell group 16. Therefore, the functioning of the memory device remains unimpaired. When the defective memory cells occur in two columns in the cell block 12, and no defective memory cells occur in the cell block 10, switches S₁ and S₃ are closed. Thus, as mentioned above, the redundant cells replace the defective memory cell, and functioning of the memory device remains unimpaired. Since the switches S₁ ∼ S₃ are initially open, and are closed only when necessary, the switches may be comprised of a poly-crystalline silicon fuse. When a switch is to be closed, the fuse is melted by supplying a current or by a laser beam. The switches S₁ ∼ S₃ are initially open and are closed only when necessary, therefore the structure as shown in Figs. 4A and 4C may be used. Figure 4A shows details of the switching circuit shown in Fig. 3. In Fig. 4A, gate transistors 41a, 42a, 43a; 41b, 42b, 43b; ... 41n, 42n, 43n are connected to Y decoders i, j, ... k, respectively, and gate transistors 44, 45 and 46 are connected between I/O inputs (data buses) (1) and (2). One terminal of each transistor 42a and 42b is connected to the transistor 47, one terminal of each transistor 43a and 43b is connected via transistors 48 and 49 to the transistor 42n, and the transistor 41n is connected to the transistor 50. The transistors 44 and 47 are controlled by an input from a fuse terminal F a , the transistors 46 and 49 are controlled by an input from a fuse terminal F b , and the transistors 45 and 50 are controlled by an input from a fuse terminal F c . Figure 4B shows the construction of the fuse (ROM) in each Y decoder wherein, in Fig. 4B, 51a and 52a represent a high resistance,53a and 54a represent fuses, and 50a represents a gate circuit which receives the outputs of the fuse shown in (b) and (c) of Fig. 4B. Figure 4C shows the construction of the fuses (Fa, Fb, Fc) which correspond to the sequences (groups) of the redundant cells. In Fig. 4C, 55 ∼ 57 represent high resistances, and 58 ∼ 60 represent fuses. Next, referring to Figs. 4A, 4B, and 4C, the case in which column i in cell block (1) and column k in cell block (2) are replaced by the redundant cells will be explained. In this case, the fuse 53a corresponding to F 1i (53a) and the fuse 58 corresponding to F a are melted, so that the sequence of redundant cells a replaces the column i in the cell block (1). Further, the fuse corresponding to F 2k and the fuse 59 corresponding to F b are melted, so that the sequence of redundant cells b replaces the column k in the cell block (2). Next, an explanation will be given for the case in which the columns i and j in the cell block (1) are replaced by the redundant cells. In this case, the fuse 53a corresponding to F 1i (53a) and the fuse 58 corresponding to F a are melted so that the sequence of the redundant cells a replaces the column i in the cell block (1). Further, the fuse corresponding to F 1j and the fuse 60 corresponding to F c are melted so that the sequence of the redundant cells b replaces the column j in the cell block (1). In Figs. 4B and 4C, fuses are made of material such as poly-crystalline silicon, and the transistors are field effect transistors (FETs). As shown in Figs. 4B and 4C, the gate of the transistor is connected via the fuse F to ground, so that it is in an OFF state. When the fuse F is melted, the transistor is pulled up via the high resistances such as 51a, ..., 55, etc. to the electric source V c , so that it becomes in an ON state. When the fuse F is not melted, the current flows from the electric source V c via the high resistance and the fuse to ground. However, if the high resistance is used as the resistor R, this current can be decreased to a small value such as of the order of a pico ampere. Figure 5 is another embodiment corresponding to Fig. 4B. In Fig. 4B, if one fuse such as 53a is melted, the signal F i becomes "L" automatically, so that the transistor 41a is OFF. However, in the embodiment shown in Fig. 5, the structure is such that if at least one fuse corresponding to fuse 53a or 54a is melted, the fuse corresponding to 61a also melts, so that the signal F i becomes "L" and the transistor 41a is OFF. Figure 6 is a flowchart showing the operation of the device shown in Figs. 4A ∼ 4C. In block 71, if a failure is detected, block 71 is transferred to block 72. In block 72, if one column in block 1 is detected, the fuse corresponding to the failed column i and the fuse F a are melted in block 73, so that the entire device is tested (block 74). In block 72, if more than one failed column occurs in block 1, block 72 is transferred to block 75 and the failed columns are examined. When the failed columns are columns i and j in block (1), the fuses corresponding to F 1i , F 1j (F i , F j ), and F a , F b are melted in block 76, the failed columns are replaced by the redundant cells, and the entire device is tested (block 77) . The memory device may have a one bit organization by which one memory cell is selected by one address,or a plurality bit organization by which a plurality of cells are selected at the same time by one address. Figures 1 and 3 show a memory having a two bit construction, and a multibit organization such as 8 bits may exist in a 64 KRAM. In this case, as shown in Fig. 7, the number of cell blocks and I/O buffers provided corresponds to the number of bits. In the Figure , 10A, 12A, ..., 12D are cell blocks and 22A, 24A, ..., 24D are I/O buffers. In this case, for example four circuits as shown in Fig. 2 may be provided, so that a 64 KRAM having an 8 K x 8 bits organization can be obtained. 14A, 16A, ... 16D are redundant cell groups corresponding to each cell block. In this example, the redundant cell groups 14A and 16A can be connected to the cell blocks 10A or 12A, however, they cannot be connected to another cell block, for example, 12D. For the purpose of improving this point and increasing the connection flexibility of the redundant cell groups to any block, wire connections may be provided along the data buses 18 and 20 for switching the redundant cell groups to other cell blocks also. However, the connection layout then becomes rather complex. As explained above, in the present invention, the redundant cell groups are not exclusively linked to a cell block but can be connected to any other cell block. Therefore, the present invention can deal with a frequent occurrence of defective memory cells in a cell block without increasing the number of redundant cell groups needed, and thus, the present invention is very effective for carrying out the stated purpose.

Claims: A semiconductor memory device comprising: first and second cell blocks (10,12), each comprising a plurality of cell groups, each cell group comprising a plurality of memory cells; a redundant cell group (14) comprising a plurality of memory cells; first and second data buses (18,20) corresponding respectively to the first and second cell blocks (10,12); decoder circuitry for selecting one of the cell groups; and switching circuitry (51,52,S₁,S₂,S₃) responsive to said decoder circuitry for connecting the redundant cell group to either of said first or second data buses (18,20) corresponding to the first and second cell blocks (10,12); characterised in that:- the redundant cell group (14) is arranged between the first and second cell blocks; each cell group is connected to the data bus (18,20) corresponding to its block via a respective selection gate controlled by said decoder circuitry; and in that the switching circuitry comprises gates (51,52) arranged, and controlled by said decoder circuitry, in parallel with said selection gates, and permanently-settable switch circuits (S₁,S₂,S₃) for permanently connecting the redundant cell group to either of said first or second data buses. A device as claimed in claim 1, comprising at least one additional cell block, the switching circuitry being operable to link the redundant cell group to any of the cell blocks. A device as claimed in claim 2, comprising at least one additional redundant cell group (16), the switching circuitry being operable to link the or each additional redundant cell group to any of the cell blocks (10,12). A device as claimed in claim 1, having at least one additional cell block and at least one additional redundant cell group (16), the redundant cell groups (14,16) being associated with respective sets, for example pairs, of cell blocks, and the switching circuitry being operable to link a redundant cell group to any member of its associated set of cell blocks. A device as claimed in claim 1, 2, 3 or 4, wherein said permanently-settable switch circuits comprise a first switch (S₁) which is connected between third and fourth data buses corresponding to a first group (14) of redundant cells and a second group (16) of redundant cells respectively, a second switch (S₂) which is connected between said first (18) and third data buses and a third switch which is connected between second (20) and fourth data buses; wherein, when the first group (14) of redundant cells is linked to the first cell block (10), said first switch (S₁) is permanently open and said second switch (S₂) is permanently closed; and when the first group (14) of redundant cells and the second group (16) of redundant cells are linked to said first cell block (10), said first switch (S₁) and said second switch (S₂) are permanently closed and said third switch (S₃) is permanently open. A semiconductor memory device according to claim 5, wherein each of said first, second and third switches (S₁,S₂,S₃) is formed by a field effect transistor (44,45,46), and each is provided with a ROM element (55,58;56,59;57,60). A semiconductor memory device according to claim 6, wherein each of said ROM elements includes a series circuit of a high resistance (55,56,57) and a fuse (58,59,60) formed by poly-crystalline silicon connected between a power source terminal and a ground terminal, such that, when said fuse is melted, a voltage (Vc) at said power source terminal is applied to a control gate of said field effect transistor (44,45,46) so that said field effect transistor is placed in a permanent ON state.

Inventors: AOYAMA, KEIZO
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: G06F11
IPC codes: G11C11, H01L21, G11C29, H01L27