PROCESS FOR BEVELING A METAL LAYER IN AN INTEGRATED CIRCUIT

Abstract: In a process for beveling the sharp corners on an integrated circuit metal layer (2), a photoresist mask (12) used to etch a pattern in a lower level metal layer (2) is retained on the wafer during the beveling operation. With a positive photoresist (12) and an aluminum alloy metal lower level layer (2), an etch with an alkaline photoresist solvent isotropically removes both photoresist and metal, the photoresist (12) being removed at a faster rate than the metal (2). Beveling of the metal corners suppresses the reentry effect otherwise encountered when subsequent dielectric material (16) is deposited over the lower level metal layer (2).

Description: PROCESS FOR BEVELING A METAL LAYER IN AN INTEGRATED CIRCUIT Technical Field This invention relates to a process for manufacturing an integrated circuit wafer. The invention has a particular application to a process for fabricating integrated circuit wafers which have etched patterns of lower level metal cov¬ ered by dielectric and subsequent levels of metal or other conductive interconnects. Bank round of the Invention Among the features characterizing the trend of contemporary integrated circuit designs are those relating to the use of metallic interconnects to reduce resistance and thereby increase operating speed, those relating to reductions in the circuit dimensions, and those relating to increases in the number of interconnect levels. Though such features * improve circuit density and operating speed, they tend to magnify certain fabrication problems heretofore considered manageable. In particular, the use of metal interconnects and smaller dimensions accentuates the effects of the topographical distortion known as reentry or cusping of a dielectric layer formed over a lower level metal layer. This is particularly true for commonly-utilized silicon dioxide (oxide) or silicon nitride (nitride) dielectric layers. To appreciate the nature of the problem, refer to the schematic cross-section in Fig. 1 of the drawings. As depicted, a substantially planar oxide layer 1 has metal layer 2 deposited thereon and etched using conventional photoresists and etchants. The sharp corner, 3, typically formed at the upper surface of metal layer 2 distorts subsequent depositions of oxide or nitride dielectric material to create first a peaking and thereafter a reentry or cusping of the dielectric deposited adjacent corner 3 of metal layer 2. This is illustrated in Fig. 1 by the topographic progressions as the dielectric increases in thickness from that represented by dashed line 4 to that repre¬ sented by dashed line 6. It should be recognized that the sharp corner at 3 is created irrespective of whether a wet or dry etchant is utilized, and is generally ' even more pronounced with the highly aniso- tropic etches which are being utilized with increased frequency. The distortion in the shape of the dielectric does not evidence itself as a problem until subsequent metal or doped semiconductor interconnect levels are deposited and patterned. Referring to Fig. 2, it becomes apparent that reentry of oxide, or nitride, dielectric layer 7 at location 8 causes a significant ~ reduction in the thickness of metal layer 9 at the same location. With the trend towards smaller dimen- sions and the importance of interconnect resistance, it is apparent that performance is degraded and that there is an acute susceptibility to direct or thermal¬ ly-induced open circuits at the reentry locations. Disclosure of the Invention According to the present invention, there is provided a process for manufacturing an integrated circuit wafer, characterized by the steps of: forming a patterned metallic material layer and an overlying masking layer, the metallic layer having at least one corner at the interface between the metallic material layer and the masking material layer; and etching both the metallic material and the masking material using an isotropic etchant which removes the masking mater¬ ial at a rate which is substantially faster than the rate at which the etchant removes metallic material, thereby beveling said corner. It will be appreciated that in a process according to the invention the photoresist mask used to define the lower level metal pattern is retained in place after etching the metal. Thereafter, the wafer is subjected to an isotropic etch using a solution which dissolves photoresist material and exposed metal at measurably different rates. For a preferred alu¬ minum alloy metal layer and positive photoresist, an alkaline photoresist developer is a suitable etch- ant/solvent. Following the preferred practice of the invention, the solution is expressly selected so that the photoresist is removed at approximately twice the rate that the metal is etched. This ratio accelerates curling or lifting of the photoresist etch to expose the top corners of the metal layer to the etching effect of the solution. Adjustments in the compatibi¬ lity of the etch rates can be made by hardening the photoresist, for example, by gas plasma treatment, or by selecting solutions having different pH number. In the preferred embodiment of the invention, the integrity of pure oxide or nitride dielectric deposited directly over the first metal layer is retained, while the reentry problem is alleviated by providing a reliable process for beveling the corner of the lower level metal. Furthermore, the beveling is accomplished without additional masking operations or elaborate fabrication procedures. In addition, the present beveling process is readily controllable by varying the chemical composition of the etchant solu¬ tion or through selective hardening of the photoresist material. Thereby, the beveling process can be adjus¬ ted for variations in the composition of the metal layer, the photoresist composition, or the solution used to perform the etch. It will also be appreciated that a process according to the invention has an advantage as com- pared with the straight application of etching to the patterned metal to remove additional metal, which seldom produces a significant reduction in the sharp¬ ness of the corners. Furthermore, the use of a second masking and etch sequence to effect beveling would obviously complicate the fabrication process and might not be practical with dimensions typically sought from modern integrated circuit processes. Brief Description of the Drawings One embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a schematic cross-section of a wafer at the edge of an etched metal layer with depic- tions of how reentry arises with an increase in the thickness of the dielectric layer. Fig. 2 is a schematic cross-section of the metal layer shown in Fig. 1 with a typical dielectric layer and its classic reentry characteristics. Figs. 3-5 are schematic representations of the structure at incremental stages of the etching sequence according to the present invention. Fig. 6 is a schematic cross-section of the lower level metal layer covered by dielectric and a second level of metal when beveled in the manner of sequence depicted in Figs. 3-5. Best*. Mode for Carrying Out the Invention Fig. 3 schematically illustrates the cross- section at the edge of a patterned metal layer 2 formed on a dielectric layer 1 produced during the processing of an integrated circuit wafer. Prefer¬ ably, dielectric layer 1 is composed of a plasma enhanced low pressure chemical vapor deposition (LPCVD) silicon dioxide. Metal layer 2 is preferably an aluminum alloy containing approximately one-half O percent copper and one percent silicon by volume with a deposited thickness of a nominal 800 nanometers. Masking layer 12 is composed of commercially available positive photoresist (PR) , marketed as AZ4110 by the American Hoechst Corporation. The preferred thickness of layer 12 is in the range of 1 micrometer. The illustration in Fig. 3 represents the structure at the conclusion of the metal etch, performed with a conven¬ tional etchant mixture of phosphoric acid, deionized water, and surfactant. Note that PR layer 12 over¬ hangs metal layer 2 by approximately one micron after the metal etch operation. According to the present process, the structure depicted in Fig. 3 is then subjected to a sequence of operations suitable to bevel the upper corners of metal layer 12 at location 13. The PR mask 12 is retained in place as the wafer is subjected to isotropic etch in a bath of alkaline solvent, a sol¬ vent which is characterized by its dissolution of PR material 12 at approximately twice the rate that it etches exposed metal material 2. As is evidenced by the change in structure in progressing from Fig. 3 to Fig. 4, the selectivity of the etchant exposes the metal corner at location 13 by removing PR 12 in the immediate proximity of the corner faster than it etches metal 2. Consequently, the etchant undercuts PR layer 12 at 13 and causes a curling or lifting at the edge of the joint between PR 12 and metal 2. With the lifting, new regions of PR 12 and metal 2 are exposed to the etchant. Etching in the solution is continued until the corner of metal 2 is substantially removed without unduly depleting the metal layer. The preferred outcome is shown schematically in Fig. 5 as the bevel at location 14. Recognize that the solution inher¬ ently etches both the PR and the metal, with the etch ratio ensuring the appropriate effect on the corner of metal layer 2. The ease with which the present process may be implemented is further substantiated when one notes that the preferred solvent is a commercially marketed material, WX-108-4 photoresist developer manufactured by Hunt Chemical Company, using this solution, at ambient temperature, the beveling process normally entails an etch of approximately one minute duration. The etch is followed by a rinse in deionized water. The Hunt WX-108-4 photoresist developer has a pH in the range of 12. However, the features of the process can be implemented with alkaline solutions having other pH values, preferably those with a pH number greater than 7. As may now be recognized, the precise process conditions, including the etch dura- tion and the form of the PR hardening, depend on the compositions of the metal alloy, the PR, and the solvent, as well as the extent of beveling sought. The chemical solvency of the PR may be modified by hardening techniques to adjust the PR etch rate and the PR curling or lifting characteristics as ^ a means of attaining the degree of beveling sought for different etching solvents or alloy compositions of the metal. For example, the integrity of the PR may be enhanced by utilizing a PR hardening technique, such as a treatment with luminous energy having a 200 nm wavelength or a gas plasma. An example of the latter, preferred, technique employs an inert gas (N2) plasma within a barrel reactor operated at 1 Torr and with 500 watts power for approximately 30 minutes to condition patterned PR on wafers. It will be appreci¬ ated that the PR hardening is produced by cross-link¬ ing the chemical composition of a polymer photoresist. Note, that such PR hardening can be performed either prior or subsequent to the etching of metal layer 2. According to the preferred practice of the present process, where the PR is not expressly hard¬ ened, the wafer with beveled metal as depicted in Fig. OM -* H 5 is thereafter subjected to a conventional PR strip using acetone and an O2 plasma ashing operation. Thereafter, conventional fabrication is resumed. The wafer region illustrated in Fig. 6 shows the wafer topology after plasma enhanced LPCVD oxide layer 16 is deposited. Note the absence of the re¬ entry characteristic. As further shown in Fig. 6, dielectric layer 16 is then covered in conventional manner with another metal layer, 17. It should be recognized that dielectric layer 16 in Fig. 6 is not constrained to an oxide or nitride composition, but may also be comprised of any one of numerous other dielectric materials.

Claims: CLAIMS : 1. A process for manufacturing an integrated circuit wafer, characterized by the steps of: forming a patterned metallic material layer (2) and an overlying masking material layer (12) , the metallic layer (2) having at least one corner at the interface between the metallic material layer (2) and the masking material layer (12) ? and etching both the metallic material (2) and the masking material (12) using an isotropic etchant which removes the masking material (12) at a rate which is substantially faster than the rate at which the etchant removes metallic material (2) , thereby beveling said corner. 2. A process according to claim 1, characterized in that the ratio of etch rates has a " nominal value of 2. 3. A process according to claim 2, characterized in that said metallic material (2) is an aluminum alloy and said masking material (12) is a polymer photoresist. 4. A process according to claim 2, characterized in that said masking material (12) is a positive photoresist, and the etchant has a pH value of 7 or greater. 5. A process according to claim 4, characterized by the step of hardening said polymer photoresist by cross-linking the chemical composition thereof. 6. A process according to claim 5, characterized in that said hardening is effected in an inert gas plasma environment. J J O A^ W 7. A process according to claim 3, characterized in that said metallic material (2) is an alloy of aluminum with minor proportions of copper and silicon, and said etchant has a pH value in the range of 12.

Inventors: HAYWORTH HUBERT OSCAR, MAHERAS GEORGE, HAYWORTH, HUBERT, OSCAR, MAHERAS, GEORGE
Applicants: NCR CO, NCR CORPORATION
Application year: 1984
Main classification: H01L21
IPC codes: C23F1, H01L21, H05K3