A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Abstract: A high speed and low power consumption semiconductor integrated circuit device has a plurality of basic cells (302) each being constructed by at least a plurality of bipolar transistors and a plurality of MOS transistors. One or more of said basic cells, adjacent to each other, are interconnected to form internal circuits such as a NAND gate or a flip-flop. A plurality of such internal circuits are connected in accordance with a logical diagram to form a single LSI.

Description: The present invention relates to a semiconductor integrated circuit, and more particularly to a high speed and low power consumption semiconductor integrated circuit device including MOS transistors and bipolar transistors. In a gate array LSI which is one of the semiconductor integrated circuit devices, only those masks of ten or more photomasks used to manufacture the LSI which correspond to the wiring patterns are prepared in accordance with a type to be developed so that the LSI having a desired electric circuit operation is manufactured. This master-slice concept is said to have existed since the generation of 1960. A construction of the gate array LSI is shown in Fig. 1, a semiconductor substrate 10 has an area 14 for bonding pads and input/output circuits on an outer periphery thereof, and basic cells 11 comprising transistors are arranged in an x-direction to form basic cell lines 12, which are repeatedly arranged in a y-direction leaving wiring areas 13 therebetween. In order to attain a desired electrical circuit operation, one to several adjacent basic cells 11 are connected to form each internal circuit such as a NAND gate or a flip-flop. Various logical gates each comprising a plurality of basic cells 11 are connected in accordance with a logical diagram to form a single LSI. An input/output circuit may comprise independent input circuit and output circuit or a combined input and output circuit. In a prior art CMOS gate array LSI, the basic cell 11 comprises CMOS transistors. The internal circuit comprising the CMOS transistors has a low power consumption, but because of a low mutual conductance of the MOS transistor, it takes a long discharge time when a load capacitance is large and hence an operating speed of the circuit is low. In a prior art bipolar gate array LSI, the basic cell 11 comprises bipolar transistors and resistors. The internal circuit comprising the bipolar transistors has a high operating speed even for a high load capacitance because a mutual conductance of the bipolar transistor is larger than that of the MOS transistor but it has a high power consumption because a large current flows into and out of a low impedance circuit. Japanese Laid-Open Patent Application No. 57-181152 discloses a master-slice semiconductor integrated circuit device in which each unit circuit cell comprises MOS transistors and each input/output circuit comprises bipolar transistors and MOS transistors. However, since the internal circuits which occupy most portions of a semiconductor substrate comprise the MOS transistors, it takes a long charge-discharge time when the load capacitance is high and hence the operating speed thereof is low. It is an object of the present invention to provide a high speed and low power consumption semiconductor integrated circuit device which resolves the problems encountered in the prior art devices. In order to achieve the above object, the semiconductor integrated circuit device of the present invention is characterized in that each basic cell is constructed of a plurality of bipolar transistors and a plurality of MOS transistors. The present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a prior art gate array LSI chip, Fig. 2 shows a bipolar-CMOS hybrid two-input NAND circuit used in an embodiment of the present invention, Fig. 3 shows a pattern of the circuit of Fig. 2 constructed by basic cells used in the embodiment of the present invention, Fig. 4 is a sectional view of Fig. 3, Fig. 5 shows a basic cell used in the embodiment of the present invention, Fig. 6 shows a bipolar-CMOS hybrid two-input NAND circuit used in the embodiment of the present invention, Fig. 7 shows a pattern of the circuit of Fig. 6 constructed by basic cells used in the embodiment of the present invention, Fig. 8 shows a basic cell used in the embodiment of the present invention, Fig. 9 shows a bipolar-CMOS hybrid two-input NAND circuit used in the embodiment of the present invention, Fig. 10 shows a pattern of the circuit of Fig. 9 constructed by basic cells used in the embodiment of the present invention, Fig. 11 is a sectional view of Fig. 10, Fig. 12 shows a bipolar-CMOS hybrid two-input NAND circuit used in the embodiment of the present invention, Fig. 13 shows a pattern of the circuit of Fig. 12 constructed by basic cells used in the embodiment of the present invention, Fig. 14 is a sectional view of Fig. 13, Fig. 15 shows a bipolar-CMOS hybrid two-input NAND circuit used in the embodiment of the present invention, Fig. 16 shows a pattern of the circuit of Fig. 15 constructed by basic cells used in the embodiment of the present invention, Fig. 17 is a sectional view of Fig. 16, Fig. 18 shows a master structure of a gate array LSI in accordance with the embodiment of the present invention, Fig. 19 shows an output circuit used in the embodiment of the present invention, Fig. 20 shows a plane pattern of a basic cell used in the embodiment of the present invention, Fig. 21 is a sectional view of Fig. 20, Fig. 22 shows a bipolar-CMOS hybrid two-input NAND circuit, Fig. 23 shows a plane pattern of the circuit of Fig. 22 constructed by the basic cells shown in Fig. 20, Fig. 24 is a sectional view of Fig. 23, Fig. 25 shows a bipolar-CMOS hybrid two-input NOR circuit, Fig. 26 shows a plane pattern of the circuit of Fig. 25 constructed by the basic cells shown in Fig. 20, Fig. 27 shows a bipolar-CMOS hybrid inverter circuit, Fig. 28 shows a plane pattern of the circuit of Fig. 27 constructed by the basic cells shown in Fig. 20, Fig. 29 shows a plane pattern of a basic cell used in the embodiment of the present invention, Fig. 30 shows a plane pattern of the circuit of Fig. 22 constructed by the basic cells shown in Fig. 29, Fig. 31 shows a master structure of a gate array LSI in accordance with another embodiment of the present invention, Figs. 32A and 32B show structures of the MOS array of Fig. 31, Figs. 33A and 33B show structures of the bipolar array of Fig. 31. The preferred embodiments of the present invention will now be described in detail. Fig. 18 shows one embodiment of the gate array LSI of the present invention. Numeral 300 denotes a semiconductor substrate which comprises input/output circuits 301 arranged on a periphery thereof, a plurality of basic cell lines 303 each having a plurality of basic cells 302 constructed as described hereinafter arranged in an x-direction and wiring zones 304 among the basic cell lines. In order to attain a desired electrical circuit for the LSI, one or more adjacent basic cells 302 are connected to form an internal circuit such as a gate circuit or a flip-flop. The internal circuits themselves and the internal circuits and the input/output circuits are interconnected by an computer-aided wiring to form the desired LSI. In the present embodiment, the input/output circuits are preferably constructed primarily by bipolar transistors such as TTL or ECL in view of high speed and high load drive capability. Fig. 19 shows a typical TTL output circuit. Numeral 310 denotes a power supply terminal, numeral 311 denotes an input terminal, numeral 312 denotes an output terminal, numerals 313, 314 and 315 denote resistors, and numerals 316 - 319 denote NPN bipolar transistors. This circuit is a well-known TTL inverter circuit and hence the operation thereof is not explained here. A known ECL circuit may be used. A similar circuit to that of Fig. 19 may be used as the input circuit. The input/output circuit may be a bipolar-CMOS hybrid circuit which will be described later. Fig. 2 shows a totem pole output two-input NAND circuit which is a basic cell used to construct an internal circuit used in an embodiment of the present invention. In Fig. 2, numeral 20 denotes a first NPN transistor having a collector thereof connected to a power supply terminal 203 and an emitter thereof connected to an output terminal 202, numeral 21 denotes a second NPN transistor having a collector thereof connected to the output terminal 202 and an emitter thereof connected to a fixed potential terminal which is a ground potential GND, numeral 201 denotes input terminals, numerals 22 and 23 denote PMOS's having gates thereof connected to the respective input terminals 201 and sources and drains thereof connected in parallel to the collector and the base of the first NPN 20, numerals 26 and 27 denote NMOS's having gates thereof connected to the respective input terminals 201 and sources and drains thereof connected in series across the collector and the base of the second NPN 21, and numerals 210 and 211 denote resistors connected between the bases and the collectors of the first and second NPN's 20 and 21, respectively. Table 1 shows a logical operation of the present embodiment. When either one of the inputs 201 is "0", either one of the PMOS;s 22 and 23 are ON and either one of the NMOS's 26 and 27 are OFF. Accordingly, the base potential of the first NPN 20 rises and the first NPN 20 is turned on and the base-emitter circuit of the second NPN 21 is shorted by the resistor 211. Thus, the emitter current of the first NPN 20 charges up the load and the output 202 assumes the "1" level. When both inputs 201 are "0", both PMOS's 22 and 23 are ON and both NMOS's 26 and 27 are OFF. Accordingly, the operation is same as that described above and the output 202 assumes the "1" level. When both inputs 201 are "1", both PMOS's 22 and 23 are OFF and both NMOS's 26 and 27 are ON. Accordingly, the base-emitter circuit of the first NPN 20 is shorted by the resistor 210 and the first NPN 20 is turned off, and the base-collector circuit of the second NPN 21 is shorted by the NMOS's 26 and 27 and the current from the output 202 is supplied to the base of the second NPN 21 so that the second NPN 21 is turned on and the output 202 assumes the "0" level. When the NPN transistors are ON, the resistors 210 and 211 shunt the base currents, and when the NPN transistors are turned off, the resistors 210 and 211 serve to discharge the charges stored in the bases. In accordance with the present embodiment, the two-input NAND circuit is constructed by a minimum configuration of the CMOS's and the bipolar transistors. The present embodiment can attain a high speed operation because it uses the NPN bipolar transistors which have an excellent high frequency characteristic. The present embodiment also attains a high input impedance and low output impedance circuit and attains a low power consumption characteristic because a DC path from the power supply 203 to the ground is not formed. Fig. 3 shows a layout pattern for constructing the bipolar-CMOS hybrid circuit, and Fig. 4 shows a sectional view of Fig. 3. Fig. 4 shows an inverter circuit but the like elements are designated by the like numerals to those of Fig. 3. In Fig. 3, a pattern of a buried layer 227 of Fig. 4 is omitted for the sake of simplicity. In an isolation region 212, the PMOS's 22 and 23, the NPN 20, the resistors 210 and 211 and the NMOS's 26 and 27 are formed, and in an isolation region 213, the NPN 21 is formed. The numerals for the MOS transistors corresponding to those of Fig. 2 are shown on gate electrodes 220 and 221 of Fig. 3. A P⁺ region 219 and the gate electrodes 220 and 221 form the PMOS's 22 and 23, and an N⁺ region 223 in a P well 214 and the gate electrodes 221 and 220 form the NMOS's 26 and 27. The NPN 20 has a P region 217 as the base, an N⁺ region 218 in the P region 217 as the emitter and an N⁺ region 215 as the collector. The resistors 210 and 211 are formed by P regions 216 and 222, respectively. The NPN 21 has a P region 225 in the isolation region 213 as the base, an N⁺ region 226 in a P region 225 as the emitter and an N⁺ region 224 as the collector. The interconnection of the elements is now explained. The collector 215 of the NPN 20 and the sources of the PMOS's 22 and 23 are connected to the power supply by an AL wire 42. A symbol indicates a contact between the AL wire and the element. The drains of the PMOS's 22 and 23, the base of the NPN 20 and one end of the resistor 210 are interconnected by an AL wire 228. The other end of resistor 210 and the emitter 218 of the NPN 20 are interconnected by AL wire 229. The emitter 226 of the NPN 21, one end of the resistor 211 and the P well 214 are connected to the ground potential by the AL wire 43. The other end of the resistor 211, the source of the NMOS 27 and the base of the NPN 21 are interconnected by an AL wire 230. The drain of the NMOS 26 and the collector 224 of the NPN 21 are interconnected by an AL wire 231. While not shown, the emitter 218 of the NPN 20 and the collector 224 of the NPN 21 are interconnected by a second level AL wire. Fig. 5 shows a pattern in which the AL wires and the contacts of the layout pattern shown in Fig. 3 have been removed. By applying the AL wires and the contacts of Fig. 3 to the pattern of Fig. 5, the two-input NAND circuit is constructed, and by applying other AL wires and contacts, an inverter or a two-input NOR circuit is constructed. When a flip-flop is to be constructed, as many patterns of Fig. 5 as necessary may be laterally arranged. Accordingly, by arranging the basic cells of Fig. 5 in a manner shown in Fig. 18, the basic cell line of the gate array is constructed. In accordance with the present embodiment, the gate array LSI having the basic cells for constructing the bipolar-CMOS hybrid logic circuit is attained and the high speed and low power consumption gate LSI is provided. Fig. 6 shows another embodiment of the totem pole output two-input NAND circuit. In Fig. 6, the resistor 210 in the embodiment of Fig. 2 has been substituted by an NMOS 240 and a PMOS 242 and the resistor 211 has been substituted by an NMOS 241. A gate of the NMOS 240 is connected to the power supply terminal 203 and a drain and a source are connected to the base and the emitter, respectively, of the NPN 20. A gate of the NMOS 241 is connected to the power supply terminal 203, a drain and a source are connected to the base and the emitter, respectively, of the NPN 21, a gate of the PMOS 242 is connected to the ground potential, and a drain and a source are connected to the emitter and the base, respectively of the NPN 20. The like elements to those of Fig. 2 are designated by the like numerals. The operation is essentially same as that of Fig. 2. The NMOS 241 always operates in a non-saturation region and functions for the resistor 211. When one of the inputs 201 is "0", the PMOS 242 functions to raise the output 202 to the power supply voltage, and when the output 202 is "0", the NMOS 240 functions to short the base-emitter circuit of the NPN 20 to turn off the NPN 20 so that a current flowing from the power supply terminal 203 to the ground through the NPN's 20 and 21 is blocked and the power consumption is reduced. In the present embodiment, since the MOS transistors having a small channel width are used in place of the resistors, an integration density is further improved. Fig. 7 shows a layout pattern for constructing the bipolar-CMOS hybrid circuit. In Fig. 7, a pattern of a buried layer is omitted for the sake of simplification. In an isolation region 242, the PMOS's 22, 23 and 242, the NPN 20 and the NMOS's 26, 27, 240 and 241 are formed, and in an isolation region 244, the NPN 21 is formed. Numerals for the MOS transistors corresponding to those of Fig. 6 are shown on the gate electrodes 253, 254, 255 and 256. The P⁺ region 249 and the gate electrodes 253, 254 and 255 form the PMOS's 242, 23 and 22, and the N⁺ region 250 in the P well 245 and the gate electrodes 254 and 255 form the NMOS's 26 and 27. The N⁺ regions 251 and 252 in the P well 245 and the gate electrode 256 form the NMOS's 240 and 241. The NPN 20 includes the P region 247 as the base, the N⁺ region 248 in the P region 247 as the emitter and the N⁺ region 246 as the collector. The NPN 21 includes the P region 258 in the isolation region 244 as the base, the N⁺ region 259 in the P region 258 as the emitter and the N⁺ region 257 as the collector. The interconnection of the elements is now explained. The collector 246 of the NPN 20, the sources of the PMOS's 22 and 23 and the gates 256 of the NMOS's 240 and 241 are connected to the power supply by the AL wire 42. A symbol indicates a contact beween the AL wire and the element. The drains of the PMOS's 22 and 23, the base 247 of the NPN 20 and the source of the PMOS 242 are interconnected by the AL wire 260. The emitter 248 of the NPN 20 and the drain of the PMOS 242 are interconnected by the AL wire 261. The drain of the PMOS 242, the drain of the NMOS 26 and the source of the NMOS 240 are interconnected by the AL wire 262. The drain of the NMOS 26 and the collector 257 of the NPN 21 are interconnected by the AL wire 263. The source of the NMOS 27, the drain of the NMOS 241 and the base 258 of the NPN 21 are interconnected by the AL wire 264. The emitter 259 of the NPN 21, the source of the NMOS 241, the gate 253 of the PMOS 242 and the P well 245 are connected to the ground potential by the AL wire 43. Fig. 8 shows a pattern in which the AL wires and the contacts of the layout pattern shown in Fig. 7 have been removed. By applying the AL wires and the contacts of Fig. 7 to the pattern of Fig. 8, the two-input NAND circuit is constructed, and by applying other AL wires and contacts, an inverter or a two-input NOR circuit is constructed. When a flip-flop is to be constructed, as many patterns of Fig. 8 as necessary may be laterally arranged. Accordingly, by arranging the basic cells of Fig. 8 in a manner shown in Fig. 18, the basic cell line of the gate array is constructed. In the present embodiment, since the MOS transistors having a small channel width are used in place of the resistors, the gate array LSI of a higher integration density is obtained. In the embodiment of Fig. 6, the PMOS 242 is provided between the base and the emitter of the NPN 20. However, the PMOS 242 may be omitted without affecting the actual operation. Thus, the gate array LSI of higher integration density can be obtained. Fig. 9 shows other embodiment of the totem pole output two-input NAND circuit. The present NAND circuit comprises NPN's 20 and 21, PMOS's 22 and 23, depletion type NMOS transistors (DNMOS's) 24 and 25, NMOS's 26 and 27 and depletion type PMOS transistors (DPMOS's) 28 and 29. The operation is described below. When either one of the inputs 201 is "0", either one of the PMOS's 22 and 23 is ON, either one of the NMOS's 26 and 27 is OFF and the ON-resistance of either one of the DPMOS's 28 and 29 decreases. As a result, the base potential of the NPN 20 rises and the NPN 20 is turned on, and the base-emitter circuit of the NPN 21 is shorted by the DMPOS 28 or 29 so that the NPN 21 is turned off. Thus, the emitter current of the NPN 20 charges up the load and the output 202 assumes the "1" level. When both inputs 201 are "0", both PMOS's 22 and 23 are ON and both NMOS's 26 and 27 are OFF and the ON-resistances of the DPMOS's 28 and 29 decrease. Accordingly, the operation is same as that described above and the output 202 assumes the "1" level. When both inputs 201 are "1", both PMOS's 22 and 23 are OFF and both NMOS's 26 and 27 are ON and the ON-resistances of the DNMOS's 24 and 25 decrease while the ON-resistances of the DPMOS's 28 and 29 increase. As a result, the base-emitter circuit of the NPN 20 is shorted by the DNMOS's 24 and 25 and the NPN 20 is turned off, and the base-collector circuit of the NPN 21 is shorted by the NMOS's 26 and 27 and the current from the output 202 is supplied to the base of the NPN 21. As a result, the NPN 21 is turned on and the output 202 assumes the "0" level. In the present embodiment, when the NPN is turned off, the ON-resistance of the MOS between the base and the emitter of the NPN is reduced so that the stored charge is rapidly discharged, and when the NPN is turned on, the ON-resistance of the MOS between the base and the emitter increases so that the base current is not shunted and the NPN is rapidly turned on. Accordingly, a higher operation speed is attained. Fig. 10 shows a layout pattern for constructing the bipolar-CMOS hybrid circuit and Fig. 11 shows a sectional view thereof. Fig. 11 shows an inverter circuit but the like elements are designated by the like numerals to those of Fig. 10. In Fig. 10, a pattern of a buried layer 50 of Fig. 11 is omitted for the sake of simplification. In the isolation region 30, the PMOS's 22 and 23, the DNMOS 24 and 25 and the NPN 20 are constructed, and in the isolation region 44, the NMOS's 26 and 27, the DMOS's 28 and 29 and the NPN 21 are constructed. The numerals for the MOS transistors corresponding to those of Fig. 9 are shown on the gate electrodes 37 and 38 of Fig. 10. The P⁺ region 34 and the gate electrodes 38 and 37 form the PMOS's 22 and 23, the N⁺ region 35 and the gate electrodes 38 and 37 form the NMOS's 26 and 27, the N⁺ region 33 and the gate electrodes 37 and 38 form the DNMOS's 24 and 25, and the P⁺ region 36 and the gate electrodes 37 and 38 form the DPMOS's 28 and 29. The NPN 20 includes the N⁺ region 39 in the isolation region 30 as the collector, the P well 31 as the base and the source of the DNMOS 25 (at the contact hole 41 in Fig. 10) as the emitter. The P well 31 contains the DNMOS's 24 and 25 and also contains portions of the drain regions of the PMOS's 22 and 23 so that the base of the NPN 20 and the drains of the PMOS's 22 and 23 are interconnected without the AL wires. The NPN 21 includes the N⁺ region 40 in the isolation region 44 as the emitter, the P well 32 as the base and the outer periphery 45 of the P well 32 of the drain of the NMOS 26 as the collector. The P well 32 contains portions of the sources of the DPMOS's 28 and 29 so that the base of the NPN 21 and the sources of the DPMOS's 28 and 29 are interconnected without the AL wires. The P well 32 does not contain any portion of the drain of the NMOS 26 because the collector of the NPN 21 and the drain of the NMOS 26 are interconnected without the AL wire. The collector 39 of the NPN 20 and the sources of the PMOS's 22 and 23 are connected to the power supply by the VCC power supply line 42. The base of the NPN 20 and the drain of the DNMOS 24 are interconnected by the AL wire 46. The emitter 40 of the NPN 21 and the drains of the DPMOS's 28 and 29 are connected to the GND by the GND power supply line 43. The base of the NPN 21 and the source of the NMOS 27 are interconnected to the AL wire 47. The emitter of the NPN 20 (at the contact hole 41) and the collecter of the NPN 21 (at the contact hole 48) are interconnected by a second level AL wire (not shown) to form the output 202. The inputs 201 are the gate electrodes 37 and 38. By using as many layout patterns of Fig. 10 as required and selecting the AL wiring layers and the contact layers for each logical gate, an inverter or a NAND circuit can be constructed. Thus, by arranging the basic cells of Fig. 10 without the AL wiring layer and the contact layer, in a manner shown in Fig. 18, the basic cell line of the gate array is constructed. Since the contact holes for allowing the connection of the source and drain regions of the DMOS's 24 and 25 to the AL wire and the contact holes for allowing the source and drain regions of the DPMOS's 28 and 29 to the AL wire are positioned at the center of the basic cell, the outer surfaces of the source and drain regions of the DNMOS'S 24 and 25, the DPMOS's 28 and 29 can be used as the AL wiring regions. This is equivalent to bury the elements beneath the wiring region and a space efficiency is improved. In the present embodiment, the high density bipolar-CMOS hybrid logic circuit is attained and the high speed, low power consumption and high integration density bipolar-CMOS hybrid gate array LSI is provided. Other embodiment of the present invention is explained below. Fig. 12 shows a two-input NAND circuit having a complementary output stage. The present NAND circuit comprises a PNP transistor 51, an NPN 21, PMOS's 22 and 23, DNMOS's 24 and 25, NMOS's 26 and 27 and DPMOS's 28 and 29. The like elements to those shown in Fig. 2 are designated by the like numerals. The operation is now explained. When either one of the inputs 52 is "0", either one of the PMOS's 22 and 23 is ON and either one of the NMOS's 26 and 27 is OFF and the ON-resistance of either one of the DPMOS's 28 and 29 decreases. Accordingly, the base potential of the PNP 51 drops and the PNP 51 is turned on and the NPN 21 is turned off because the base-emitter circuit is shorted by the DPMOS 28 or 29. Thus, the collector current of the PNP 51 charges up the load and the output 53 assumes the "1" level. When both inputs 52 are "0", both PMOS's 22 and 23 are ON and both NMOS's 26 and 27 are OFF and the ON-resistances of the DPMOS's 28 and 29 decrease. Accordingly, the operation is same as that described above and the output 53 assumes the "1" level. When both inputs 52 are "1", both PMOS's 22 and 23 are OFF and both NMOS's 26 and 27 are ON and the ON-resistances of the DNMOS's 24 and 25 decrease while the ON-resistances of the DPMOS 28 and 29 increase. Accordingly, the PNP 51 is turned off because the base-emitter circuit is shorted by the DNMOS's 24 and 25. Since the base-collector circuit of the NPN 21 is shorted by the NMOS's 26 and 27, the current from the output 53 is supplied to the base of the NPN 21 so that the NPN 21 is turned on and the output 53 assumes the "0" level. Fig. 13 shows a layout pattern for constructing the bipolar-CMOS hybrid circuit, and Fig. 14 shows a sectional view thereof. Fig. 14 shows an inverter but the like elements are designated by the like numerals to those shown in Fig. 13. In Fig. 13, a pattern of the burid layer 50 of Fig. 14 is omitted for the sake of simplification. In the present embodiment, the PNP transistor 51 is a lateral transistor. The numerals for the MOS transistors corresponding to those of Fig. 12 are shown on the gate electrodes 37 and 38. The configuration of the MOS transistor and the NPN 21 is identical to that of Fig. 10. The PNP 51 is a lateral transistor and includes the P⁺ region 62 as the emitter, the N region in the isolation region 60 as the base and the drain of the PMOS 22 (at the contact hole 63) as the collector. The P well 61 does not contain any portion of the source of the DNMOS 24 because the base of the PNP 51 and the source of the DNMOS 24 is interconnected without the AL wire. The emitter 62 of the PNP 51 and the drain of the DNMOS 25 are connected to the power supply by the VCC power supply line 42. The source of the DNMOS 24 and the sources of the PMOS's 22 and 23 are interconnected by the AL wire 64. The connections of the NMOS's 26 and 27, the DPMOS's 28 and 29 and the NPN 21 are identical to those of Fig. 10 and they are not explained here. The collector of the PNP 51 (at the contact hole 63) and the collector of the NPN 21 (at the contact hole 48) are connected by a second line AL wire (not shown) to form the output 53. The inputs 52 are the gate electrodes 37 and 38. By using as many layout patterns of Fig. 13 as required and selecting the AL wiring layers and the contact layers for each logical gate, an inverter or a NAND circuit can be constructed. Accordingly, by arranging the basic cells of Fig. 13 without the AL wiring layer and the contact layer, in a manner shown in Fig. 18, a basic cell line of the gate array is constructed. In the present embodiment, a high speed, low power consumption and high integration density bipolar CMOS hybrid gate array LSI is provided. Fig. 16 shows other embodiment of the present invention for constructing the two-input NAND circuit having the complementary output stage as shown in Fig. 15, and Fig. 17 shows a sectional view thereof. The operation of Fig. 15 is described first. When either one of the inputs 86 is "0", either one of the PMOS's 82 and 83 is ON and either one of the NMOS's 84 and 85 is OFF. Accordingly, the base potentials of the NPN 80 and the PNP 81 rise so that the NPN 80 is turned on and the PNP 81 is turned off. Thus, the emitter current of the NPN 80 charges up the load and the output 87 assumes the "1" level. When both inputs 86 are "0", both PMOS's 82 and 83 are ON and both NMOS's 84 and 85 are OFF. Accordingly, the operation is same as that described above and the output 87 assumes the "1" level. On the other hand, when both inputs 86 are "1", both PMOS's 82 and 83 are OFF and both NMOS's 84 and 84 are ON. Accordingly, the base potentials of the NPN 80 and the PNP 81 drop so that the NPN 80 is turned off and the PNP 81 is turned on and the output 87 assumes the "0" level. Fig. 16 shows a layout pattern for constructing the circuit of Fig. 15, and Fig. 17 shows a longitudinal structure thereof. Fig. 17 shows an inverter but the like elements are designated by the like numerals to those of Fig. 16. The numerals for the MOS transistors corresponding to those of Fig. 15 are shown on the gate electrodes 93 and 94 of Fig. 16. The P⁺ region 91 and the gate electrodes 93 and 94 form the PMOS's 83 and 82, and the N⁺ region 92 and the gate electrodes 93 and 94 form the NMOS's 84 and 85. The NPN 80 includes the N⁺ region 96 as the emitter, the P region 95 as the base and the N⁺ region 99 as the collector. The PNP 81 includes the P⁺ region 98 as the emitter, the N region 97 as the base and the P⁺ region 100 as the collector. The sources of the PMOS's 82 and 83 and the collector 99 of the NPN 80 are connected to the power supply by the VCC power supply line 101. The drains of the PMOS's 82 and 83, the bases 95 and 97 of the NPN 80 and the PNP 81 and the drain of the NMOS 84 are interconnected by the AL wire 102. The collector 100 of the PNP 81 and the source of the NMOS 85 are connected to the GND by the GND power supply line 103. The emitter 96 of the NPN 80 and the emitter 98 of the PNP 81 are interconnected by the AL wire 104 to form the output 87. The inputs 86 are the gate electrodes 93 and 94. By using as many layout patterns of Fig. 16 as required and selecting the AL wiring layers and the contact layers for each logical gate, an inverter or a NAND circuit can be constructed. Accordingly, by arranging the basic cells of Fig. 16 without the AL wiring layer and the contact layer, in a manner shown in Fig. 18, the basic cell line of the gate array is constructed. In the present embodiment, since the isolation region is not necessary, a higher integration density gate array LSI is provided. Fig. 20 shows an expansion of a cell pattern of the basic cell 302 of Fig. 18, and Fig. 21 shows a sectional view thereof. In Figs. 20 and 21, the like elements are designated by the like numerals. In an N well 421 formed in a P type semiconductor substrate, a P⁺ region 423 of a PMOS transistor and a collector region 424, a base region 425 and an emitter region 426 of an NPN bipolar transistor are formed. The PMOS transistor and the NPN bipolar transistor are formed in the same N well. It is used in a circuit which fixes the potential of the collector region 424 to the power supply voltage VCC so that the potential of the substrate (N well 421) of the PMOS transistor is fixed to the collector potential of the NPN bipolar transistor in order to improve the integration density. In the N well 422, the collector region 427, the base region 428 and the emitter region 429 of the NPN bipolar transistor are formed. It is used in a circuit in which the potential of the collector region 427 changes. The N well 421 and the N well 422 must be spaced from each other by a distance determined by a breakdown voltage in order to electrically isolate them by a P region 437 which is at the ground level. The P region 437 at the good potential corresponds to the substrate of the NMOS transistor. Thus, an N⁺ region 430 of the NMOS transistor is formed between the N wells 421 and 422. Similarly, N⁺ regions 431 and 432 of the NMOS transistor are formed. A P⁺ region 433 is provided to fix the potential of the P region 437 to the ground level. Numerals 435 and 436 denote gate electrodes such as polysilicon of the PMOS transistor and the NMOS transistor and they serve as the input regions. So-called dog bones are formed at opposite ends of the gate electrodes 435 and 436 to allow contact to a first wiring such as a first level AL wire so that a signal can be inputted to the basic cell from either top or bottom of the channel region 304. Numeral 434 denotes a gate electrode for the two NMOS transistors. The output region is usually a collector region 427 formed in the N well 422, and the input regions 435 and 436 and the output region 427 are of the same dimension as a wiring pitch of a second wiring layer such as a second level AL wire which extends in a y-direction of Fig. 18 to allow design automation. A first insulation film (not shown) is formed on the poly-Si wiring of the gate electrodes 435, 436 and 434, and a power supply wiring and a first AL wiring (not shown) are formed thereon in parallel to the basic cell line. The first wiring is used for wiring in the logic blocks and wiring of the logic blocks. When the poly-Si wiring 434 or the diffusion layer 423 and the first AL wiring are to be connected, a contact hole (hereinafter simply referred to as a contact) is formed in the first insulation layer. A second insulation layer (not shown) is formed on the first wiring, and a second AL wiring is formed thereon orthogonally to the basic cell line. When the first wiring and the second wiring are to be connected, a contact hole (hereinafter referred to as a thru-hole) is formed in the second insulator layer. A third insulation layer is formed on the top to protect the transistors and the wiring. In a conventional gate array LSI, the first wiring layer and the second wiring layer and the second insulation layer having the thru-holes formed at desired positions to allow the connection of the first wiring and the second wiring are selected for each type to obtain a desired LSI. The first insulation layer having contacts formed to allow the connection of the first wiring and the poly-Si wiring and the diffusion layer may also be selected for each type. By using the basic cell shown in Fig. 20, the logic circuits necessary to design the LSI can be constructed. Examples thereof are explained below. Fig. 22 shows a bipolar-CMOS hybrid two-input NAND circuit. Numeral 450 denotes a first NPN bipolar transistor having a collector thereof connected to a power supply terminal 40 and an emitter thereof connected to an output terminal 443, numeral 451 denotes a second NPN bipolar transistor having a collector thereof connected to an output terminal 443 and an emitter thereof connected to a fixed potential terminal which is a ground potential, numerals 441 and 442 denote input terminals, numerals 444 and 445 denote first and second PMOS transistors having gates thereof connected to the input terminals 442 and 441, respectively, and sources and drains thereof connected in parallel between the collector and the base of the first NPN 450, numerals 446 and 447 denote first and second NMOS transistors having gates thereof connected to the input terminals 441 and 442, respectively, and drains and sources thereof connected in series between the collector and the base of the second NPN 451, numeral 448 denotes a third NMOS transistor having a gate thereof connected to the power supply terminal 440 and a drain and a source thereof connected to the base and the emitter, respectively, of the first NPN 450, and numeral 449 denotes a fourth NMOS transistor having a gate thereof connected to the power supply terminal 440 and a drain and a source thereof connected to the base and the emitter, respectively, of the second NPN 451. The logical operation of the circuit of Fig. 22 is identical to that of Fig. 2 and shown in Table 1. When either one of the inputs 441 and 442 is "0", either one of the first and second PMOS's 444 and 445 is ON and either one of the first and second NMOS's 446 and 447 is OFF. Accordingly, the base potential of the first NPN 450 rises so that the first NPN 450 is turned on, and the second NPN 451 is turned off because the base-emitter circuit is shorted by the fourth NMOS 449 which is in the non-saturation region. Thus, the emitter current of the first NPN 450 charges up the load and the output 443 assumes the "1" level. When both inputs 441 and 442 are "0", both first and second PMOS's 444 and 445 are ON and both first and second NMOS's 446 and 447 are OFF. Accordingly, the operation is same as that described above and the output 443 assumes the "1" level. On the other hand, when both inputs 441 and 442 are "1", both first and second PMOS's 444 and 445 are OFF and both first and second NMOS's 446 and 447 are ON. Accordingly, the first NPN 450 is turned off because the base-emitter circuit thereof is shorted by the third NMOS 448 which is in the non-saturation region, and the second NPN 451 is turned on because the collector-base circuit thereof is shorted by the first and second NMOS's 446 and 447 and the current from the output 443 is supplied to the base of the second NPN 451. Thus, the output 443 assumes the "0" level. The third and fourth NMOS's 448 and 449 may be resistors. Fig. 23 shows the two-input NAND circuit constructed by using the basic cells of Fig. 20. A symbol indicates the contact, a broken line indicates the first wiring, a symbol indicates the thru-hole and a chain line indicates the second wiring. The like elements to those shown in Fig. 20 are designated by the like numerals. The numerals for the gate electrodes corresponding to those of Fig. 22 are designated. The first wiring 452 which is the VCC power supply line is connected to the source of the second PMOS 445 by the contact 453, to the source of the first PMOS 444 by the contact 454, to the collector of the first NPN 450 by the contact 455 and to the gate electrodes of the third and fourth NMOS's 448 and 449 by the contact 456. The drains of the first and second PMOS's 444 and 445, the base of the first NPN 450 and the drain of the third NMOS 448 are interconnected by the first wiring 457 and the contacts 459, 458 and 460. The emitter of the first NPN 450, the source of the third NMOS 448, the drain of the first NMOS 446 and the collector of the second NPN 451 are interconnected by the first wirings 461 and 462 and the contacts 463, 464, 465, 466 and 467. The emitter of the first NPN 450 and the collector of the second NPN 451 are interconnected by the second wiring 468 and the thru-holes 469 and 470. If the second wiring 468 is not present, a sheet resistance of the drain of the first NMOS 444 is inserted between the emitter of the first NPN 450 and the collector of the second NPN 451 and a speed is lowered. The second wiring 468 is, therefore, provided to prevent such a speed reduction. The second wiring 468 is on the grid of the second wiring extending in the y-direction to minimize the impedance to the design automation. The source of the secone NMOS 447, the drain of the fourth NMOS 449 and the base of the second NPN 451 are interconnected by the first wiring 471 and the contacts 472, 473 and 474. The first wiring 475 which is the ground potential line is connected to the source of the fourth NMOS 449 and the emitter of the second NPN 451 by the contacts 476 and 477. The P substrate 437 is fixed to the ground potential by the contact 478. As to the widths of the AL wires, the first wirings 452 and 475 which are the power supply lines are wide, and the first wirings 461 and 462 and the second wiring 468, through which the emitter currents, which are approximately h FE times as large as the base currents, flow are wider than the first wirings 457 and 471 through which the base currents flow. The base wirings are narrowest of the process. A pair of contacts are provided for each of the contacts 453, 454, 466 and 472 to reduce the contact resistances and reduce the sheet resistances of the sources or drains of the MOS transistors to obtain a higher speed. In this manner, the two-input NAND circuit is constructed. Fig. 24 shows a sectional view of Fig. 23 which is the bipolar-CMOS hybrid two-input NAND circuit constructed in accordance with Fig. 22. The elements are designated by the numerals corresponding to those of Fig. 22. In Fig. 24, the wirings are added to the sectional view of Fig. 21 which is unwired. Therefore, no additional explanation will be necessary. Fig. 25 shows an embodiment of the bipolar-CMOS hybrid two-input NOR circuit. Numeral 488 denotes a first NPN having a collector thereof connected to a power supply terminal 490 and an emitter thereof connected to an output terminal 481, numeral 489 denotes a second NPN having a collector thereof connected to the output terminal 481 and an emitter thereof connected to a fixed potential terminal which is a ground potential, numerals 479 and 480 denotes input terminals, numerals 482 and 483 denote first and second PMOS's having gates connected to the input terminals 479 and 480, respectively, and sources and drains thereof connected in series between the collector and the base of the first NPN 488, numerals 484 and 485 denote first and second NMOS's having gates thereof connected to the input terminals 479 and 480, respectively, and drains and sources thereof connected in parallel between the collector and the base of the second NPN 489, numeral 486 denotes a third NMOS having a gate connected to the power supply terminal 490 and a drain and a source thereof connected to the base and the emitter, respectively, of the first NPN 488, and numeral 487 denotes a fourth NMOS having a gate thereof connected to the power supply terminal 490 and a drain and a source thereof connected to the base and the emitter, respectively, of the second NPN 489. Table 2 shows a logical operation of the present embodiment. When both inputs 479 and 480 are "0", both first and second PMOS's 482 and 483 are ON and both first and second NMOS's 484 and 485 are OFF. Accordingly, the base potential of the first NPN 488 rises so that the first NPN 488 is turned on. The second NPN 489 is turned off because the base-emitter circuit thereof is shorted by the fourth NMOS 487 which is in the non-saturation region. Thus, the emitter current of the first NPN 488 charges up the load and the output 481 assumes the "1" level. When either one of the inputs 479 and 480 is "1", either one of the first and second PMOS's 482 and 483 is OFF and either one of the first and second NMOS's 484 and 485 is ON. Accordingly, the first NPN 488 is turned off because the base-emitter circuit thereof is shorted by the third NMOS 486 which is in the non-saturation region. The base-collector circuit of the second NPN 489 is shorted by the first or second NMOS 484 or 485 which is now ON. Thus, the current from the output 481 is supplied to the base of the second NPN 489 so that the second NPN 489 is turned on and the output 481 assumes the "0" level. When both inputs 479 and 480 are "1", both first and second PMOS's 482 and 483 are OFF and both first and second NMOS's 484 and 485 are ON. Accordingly the operation is same as that described above and the output 481 assumes the "0" level. Fig. 26 shows the two-input NOR circuit constructed by the basic cells of Fig. 20. A symbol indicates a contact, a broken line indicates a first wiring such as an AL wire, a symbol indicates a thru-hole, and a chain line indicate a second wiring such as an AL wire. The like elements to those shown in Fig. 20 are not designated by the numerals because they were explained in Fig. 23. The numerals for the gate electrodes corresponding to those of Fig. 25 are designated. The contacts corresponding to those of Fig. 23 are designated by the like numerals. The source of the first PMOS 482, the collector of the first NPN 488 and the gate electrodes of the third and fourth NMOS's 486 and 487 are connected to the VCC potential by the first wiring 452 which is the VCC power supply line and the contacts 454, 455 and 456. The drain of the second PMOS 483, the base of the first NPN 488 and the drain of the third NMOS 486 are interconnected by the first wiring 491 and the contacts 492, 458 and 460. The emitter of the fdirst NPN 488, the source of the third NMOS 486, the drains of the first and second NMOS's 484 and 485 and the collector of the second NPN 489 are interconnected by the first wirings 494 and 496 and the contacts 463, 464, 493, 495 and 467. The emitter of the first NPN 488 and the collector of the second NPN 489 are interconnected by the second wiring 468 and the thru-holes 469 and 470. The second wiring 468 is provided by the same reason as that for the two-input NAND circuit described above. The sources of the first and second NMOS's 484 and 485, the drain of the fourth NMOS 487 and the base of the second NPN 489 are interconnected by the first wiring 497 and the contacts 466, 472, 473 and 474. The source of the fourth NMOS 487, the emitter of the second NPN 489 and the P substrate 437 are fixed to the ground potential by the first wiring 475 which is the ground potential line and the contacts 476, 477 and 478. In this manner, the two-input NOR circuit is constructed. Fig. 27 shows an example of a bipolar-CMOS hybrid inverter which can be used as a basic cell in the present embodiment. In Fig. 27, numeral 4107 denotes a first NPN having a collector thereof connected to a power supply terminal 4100 and an emitter thereof connected to an output terminal 499, numeral 4108 denotes a second NPN having a collector thereof connected to the output terminal 499 and an emitter thereof connected to a fixed potential terminal which is a ground potential, numerals 4101 and 4102 denote first and second PMOS's having gates thereof connected to an input terminal 498 and sources and drains thereof connected to the collector and the base, respectively, of the first NPN 4107, numerals 4103 and 4104 denote first and second NMOS's having gates thereof connected to the input terminal 498 and drains and sources thereof connected the collector and the base, respectively, of the second NPN 4108, numeral 4105 denotes a third NMOS having a gate thereof connected to the power supply terminal 4100 and a drain and a source thereof connected to the base and the emitter, respectively, of the first NPN 4107, and numeral 4106 denotes a fourth NMOS having a gate thereof connected to the power supply terminal 4100 and a drain and a source thereof connected to the base and the emitter, respectively, of the second NPN 4108. Table 3 shows a logical operation of the present embodiment. When the input 498 is "0", the first and second PMOS's 4101 and 4102 are ON and the first and second NMOS's 4103 and 4104 are OFF. Accordingly, the base potential of the first NPN rises so that the first NPN 4107 is turned on. The second NPN 4108 is turned off because the base-emitter circuit thereof is shorted by the fourth NMOS 4106 which is in the non-saturation region. Thus, the emitter current of the first NPN 4107 charges up the load and the output 499 assumes the "1" level. When the input 498 is "1", the first and second PMOS's 4101 and 4102 are OFF and the first and second NMOS's 4103 and 4104 are ON. Accordingly, the first NPN 4107 is turned off because the base-emitter circuit thereof is shorted by the third NMOS 4105 which is in the non-saturation region. The base-collector circuit of the second NPN 4108 is shorted by the first and second NMOS's 4103 and 4104. Thus, the current from the output 499 is supplied to the base of the second NPN 4108 so that the second NPN 4108 is turned on and the output 499 assumes the "0" level. The third and fourth NMOS's 4105 and 4106 function as resistors. When the first and second NPN's are ON, they shunt fractions of the base currents, but when the first and second NPN's are OFF, they operate in the non-saturation region so that the drains and the sources are of the same potential and they serve to rapidly drain off the stored charges. Fig. 28 shows the inverter constructed by the basic cells of Fig. 20. A symbol indicates a contact, a broken line indicates a first wiring, a symbol indicates a thru-hole, and a chain line indicates a second wiring.The numerals for the elements corresponding to those of Fig. 27 are shown on the gate electrodes. The contacts corresponding to those in Figs. 23 and 26 are designated by the like numerals. The sources of the first and second PMOS's 4101 and 4102, the collector of the first NPN 4107 and the gate electrodes of the third and fourth NMOS's 4105 and 4106 are connected to the VCC potential by the first wiring 452 which is the VCC power supply line and the contacts 453, 454, 455 and 456. The drains of the first and second PMOS's 4101 and 4102, the base of the first NPN 4107 and the drain of the third NMOS 4105 are interconnected by the first wiring 457 and the contacts 459, 458 and 460. The emitter of the first NPN 4107, the source of the third NMOS 4105, the drains of the first and second NMOS's 4103 and 4104 and the collector of the second NPN 4108 are interconnected by the first wirings 494 and 496 and the contacts 463, 464, 493, 495 and 467. The emitter of the first NPN 4107 and the collector of the second NPN 4108 are interconnected by the second wiring 468 and the thru-holes 469 and 470, for the same reason as that described for the two-input NAND circuit. The sources of the first and second NMOS's 4103 and 4104, the drain of the fourth NMOS 4106 and the base of the second NPN 4108 are interconnected by the first wiring 497 and the contacts 466, 472, 473 and 474. The emitter of the second NPN 4108, the source of the fourth NMOS 4106 and the substrate 437 are fixed to the ground potential by the first wiring 475 which is the ground potential line and the contacts 477, 476 and 478. The gates of the first and second PMOS's 4101, 4102 and the first and second NMOS's 4103, 4104 are interconnected by the first wirings 4111 and 4112 and the contacts 4109 and 4110. In this manner, the inverter is constructed. The methods for constructing the inverter, the two-input NAND circuit and the two-input NOR circuit have thus been described in detail a further characteristic of the basic cell patterns of Figs. 20 to 28 is one or more internal wiring spaces formed on each side of the VCC power supply line or the ground potential line. These spaces are essential when a complex logic circuit is constructed by a number of basic cells. When a complex logic circuit is constructed, it is sufficient that the NPN bipolar transistors are used only in the portions of the basic cells which are outputted to the wiring channels. Accordingly, when the adjacent basic cells are connected by the first wiring, the first wiring passes above the unused NPN bipolar transistors. Thus, the wiring after the first insulation layer having the contacts thereon may be changed for each type. In the present embodiment, a pair of series-connected PMOS's and NMOS's are arranged for the two NPN bipolar transistors of the basic cell. Alternatively, three or four series-connected MOS transistors may be used, or a pair of one PMOS and one NMOS may be used. Fig. 29 shows other embodiment of the basic cell 302 of Fig. 18. The like elements to those shown in Fig. 20 are designated by the like numerals. The difference from Fig. 20 resides in that the emitter region 426 of the NPN bipolar transistor in the N well 421 is positioned closely to the collector region 424. The emitter region 429 in the N well 422 is also positioned closely to the collector region 427. As a result, the collector resistance is reduced and the operation speed is increased. One or more dog bones for the contacts are provided in intermediate points between the opposite ends of the gate electrodes 435 and 436. This facilitates the construction of a complex logic gate. The base region 428 in the N well 422 is arranged vertically to reduce the x-direction size of the basic cell. This enables a higher integration density. Fig. 30 shows the bipolar-CMOS hybrid two-input NAND circuit of Fig. 22 constructed by the basic cells of Fig. 29. A symbol indicates the contact, a broken line indicates the first wiring, a symbol indicates the thru-hole and a chain line indicates the second wiring. The like elements to those shown in Fig. 29 are designated by the like numerals. The numerals for the elements corresponding to those of Fig. 22 are shown on the gate electrodes. The sources of the first and second PMOS's 444 and 445, the gate electrodes of the NMOS's 448 and 449 and the collector of the first NPN 450 are connected to the VCC potential by the first wiring 4113 which is the VCC power supply line and the contacts 4114, 4115, 4116 and 4117. The drains of the first and second PMOS's 444 and 445, the base of the first NPN 450 and the drain of the third NMOS 448 are interconnected by the first wiring 4118 and the contacts 4119, 4120 and 4121. The emitter of the first NPN 450, the drain of the first NMOS 446, the collector of the second NPN 451 and the source of the third NMOS 448 are interconnected by the first wirings 4122 and 4123 and the contacts 4124, 4125, 4126, 4127 and 4128. The emitter of the first NPN 450 and the collector of the second NPN 451 are interconnected by the second wiring 4129 and the thru-holes 4130 and 4131 by the same reason as that explained in Fig. 23. The source of the second NMOS 447, the drain of the fourth NMOS 449 and the base of the second NPN 451 are interconnected by the first wiring 4132 and the contacts 4133, 4134 and 4135. The emitter of the second NPN 451, the source of the fourth NMOS 449 and the P substrate 437 are fixed to the ground potential by the first wiring 4136 which is the ground potential line and the contacts 4137, 4138 and 4139. In this manner, the two-input NAND circuit is constructed. The present embodiment provides a high speed and high integration density gate array LSI. Fig. 31 shows a gate array LSI in accordance with other embodiment of the present invention. Basic cell lines 511 - 517 are arranged on one main plane of a semiconductor substrate 10 in a y-direction with a predetermined space between the lines. The basic cell lines 511 - 517 each comprises alternate arrangement of a MOS array 521 and bipolar arrays 522, 523-ℓ and 523-r. The MOS array 521 comprises a plurality of MOS basic cells each including at least one MOS transistor, arranged in an x-direction. The bipolar arrays 522, 523-ℓ and 523-r each comprises at least one bipolar basic cell including at least one bipolar transistor, arranged in the x-direction. Input/output pads, a peripheral circuit 524 including input/output circuits as shown in Fig. 19 and channels 541 - 548 which are primarily first level wiring regions are formed on the semiconductor substrate 10. While not shown, wirings for the connection in each basic cell and interconnecting the basic cells through an insulation layer is formed on the semiconductor substrate 10. The MOS array 521 and the bipolar array 522, 523-ℓ and 523-r (hatched areas) can be used as the y-direction second level wiring channels. Figs. 32A and 32B show the MOS array 521 of Fig. 31. It comprises six MOS basic cells 535 arranged in the x-direction with each MOS basic cell 535 comprising a pair of PMOS transistors 531 and 532 having sources or drains thereof connected in series and a pair of NMOS transistors 533 and 534 having sources or drains thereof connected in series. Accordingly, in Figs. 32A and 32B, each MOS array 521 includes 12 PMOS transistors and 12 NMOS transistors. The MOS array 521 itself may be considered as a MOS basic cell. Figs. 33A and 33B show the bipolar array 522 of Fig. 31 constructed by four bipolar transistors and four resistors. The bipolar array 522 itself can be considered as a bipolar basic cell or the bipolar array 522 may be considered to comprise two bipolar basic cells 645 and 646. The two sets of bipolar transistors 640, 642 and 641, 643 are arranged to allow either one of the MOS arrays 521 arranged on the left and right sides of the bipolar array 522 to use the bipolar array 522. The bipolar transistors 640, 641, 642 and 643 are of NPN type because the NPN transistor has a higher switching speed than a PNP transistor. In principle, the PNP transistors or a combination of the PNP and NPN transistors may be used. As shown in the plan view of Fig. 33A, the NPN bipolar transistors 640 and 641 have a common collector 6400 because the collectors of those transistors are connected to the power supply (VCC) and hence the number of contacts is reduced and the pattern size is reduced by the common collector. Registors 603 and 613 are connected between bases 601 and 611 and emitters 602 and 612 of the NPN bipolar transistors 640 and 641, respectively. Only the emitters of the NPN bipolar transistors 642 and 643 are grounded but they are separate because the emitters cannot be commonly formed in the integrated circuit device. The NPN bipolar transistors 642 and 643 include collectors 620 and 630, bases 621 and 631 and emitters 622 and 632, respectively, and resistors 623 and 633 are connected between the respective bases and emitters. As described herein above, according to the present embodiment, the low power consumption and the high speed operation for the low load of the CMOS circuit and the high load drive capability of the bipolar circuit are utilized and the bipolar-CMOS hybrid circuit is used as required for the circuit of the functional circuit block. Thus, the high speed and low power consumption LSI is attained with the minimum increase of the chip area. The present invention is effective to the manual arrangement and wiring of the LSI, and particularly useful to the design automation by the computer where the wiring length differs from signal to signal. As described hereinabove, the present invention provides the low power consumption and high speed semiconductor integrated circuit device.

Claims: A semiconductor integrated circuit device comprising: a semiconductor substrate (300) having a plurality of basic cell rows (303) arranged in parallel on one main plane thereof, said basic cell rows each including a plurality of basic cells (302) each including one or more transistors; a wiring pattern (304) disposed on said semiconductor substrate with an insulating layer being interleaved therebetween for making connections in each of said basic cells and among said basic cells, characterized in that each of said basic cells (302) is constructed of a plurality of bipolar transistors (20,21) and a plurality of MOS transistors (22,23;26,27). A semiconductor integrated circuit device according to Claim 1 wherein each of said basic cells (302) includes a first bipolar transistor (20) having two main terminals and one control terminal, said first bipolar transistor having one main terminal thereof fixed to a highest potential (203) in the semiconductor substrate and a MOS transistor (22,23) in a common well formed in one main plane of the semiconductor substrate, a potential of said well being supplied from aid one main terminal, a second bipolar transistor (21) having two main terminals and one control terminal, said second bipolar transistor having one main terminal thereof connected to an output potential (202) which varies during the operation, arranged in a different well (214) from said well, and a MOS transistor (26,27) arranged between said wells. A semiconductor integrated circuit device according to Claim 2 wherein the other main terminal of said first bipolar transistor having said one main terminal thereof fixed to the highest potential in the semiconductor substrate and said one main terminal of said second bipolar transistor connected to the potential which varies during the circuit operation are interconnected by a metalized low resistance wiring. A semiconductor integrated circuit device according to Claim 1 wherein a plurality of contacts are formed on a first insulation layer on a drain or a source of at least one MOS transistor. A semiconductor integrated circuit device according to Claim 1 wherein a wiring connected to a control terminal of a bipolar transistor is narrower than a wiring connected to any other terminal of that bipolar transistor. A semiconductor integrated circuit device according to Claim 1 wherein at least one space for constructing a logic circuit is formed on each side of a highest potential power supply wiring and a lowest potential power supply wiring running above the MOS transistor. A semiconductor integrated circuit device according to Claim 1 wherein at least one of said basic cells (302) includes a MOS basic cell (521) constructed by MOS transistors and a bipolar basic cell (522) constructed by bipolar transistors. A semiconductor integrated circuit device according to Claim 7 wherein a plurality of said MOS basic cells (521) are arranged to form a MOS array (531,532;533,534), at least one said bipolar basic cell (522) is arranged to form a bipolar array, and at least one of said basic cell lines (511-517) includes said MOS array and said bipolar array. A semiconductor integrated circuit device according to Claim 8 wherein the basic cells at opposite ends of the basic cell line are the bipolar basic cells (523l,523r). A semiconductor integrated circuit device according to Claim 8 wherein each MOS array includes an even number of MOS basic (521) cells and each bipolar array (522) includes an even number of bipolar basic cells (645,646). A semiconductor integrated circuit device according to Claim 8 wherein each MOS array (531,532;533,534) includes an even number of MOS transistors. A semiconductor integrated circuit device according to Claim 8 wherein each bipolar array (522) includes an even number of bipolar transistors. A semiconductor integrated circuit device according to claim 1, wherein one or more of said basic cells (302), adjacent to each other, are interconnected to form internal circuits. A semiconductor integrated circuit device according to claim 13, wherein a plurality of input circuits (301) for receiving external input signals and supplying the received signals to said internal circuits and a plurality of output circuits (301) for receiving output signals from said internal circuits and externally supplying the output signals, are being formed together with said internal circuits in a common semiconductor substrate (300).

Inventors: IWAMURA, MASAHIRO, KATO, KAZUO, KUBOKI, SHIGEO, MASUDA, IKURO, NISHIO, YOJI
Applicants: HITACHI, LTD.
Application year: 1984
Main classification: H01L27
IPC codes: H01L21, H01L29, H01L27, H03K19