SYSTEM AND METHOD FOR STABILIZING ASYNCHRONOUS STATE MACHINES

Abstract: System for stabilizing asynchronous state machines in which the operation passes from state to state as a result of being actuated by digital input signals that are not synchronous with each other. In order to prevent an improper sequence of progression of the machine as a result of input signals occurring nearly simultaneously, the system includes decision logice means (44a-44m, 56a, 56b) which include input terminals (38b-38h) for receiving predetermined ones of the input signals, feedback means (47a-47c) for feeding back signals representing a present state of the machine, and holding signal output means (57). The system also includes latching means (39) for receiving a further one of the input signals, the holding signal output means (57) being arranged to control the latching means (39) to transmit this further input signal to the decision logic means only under predetermined state conditions.

Description: SYSTEM AND METHOD FOR STABILIZING ASYNCHRONOUS STATE MACHINES Technical Field This invention relates to the stabilization of asynchronous state machines, especially those in which the operation passes from state to state as the result of being actuated by a series of signals that are not synchronous with each other and may occur so nearly simultaneously as to cause the machine to follow an i - proper sequence of progression. Background Art Some computing systems operate on the basis of having information transmitted by signals that are syn¬ chronized with each other, and specific amounts of time are allocated to the performance of each operating step or task. However, some steps or tasks can be completed much more rapidly than others, but in synchronous systems the time required to perform the slowest step or task is the minimum time that must be allocated for all others synchronous with the slowest. By allowing various parts of the system to complete their steps or tasks as quickly as possible and allowing them to operate asynchronously with respect to other parts, even closely related ones, the overall speed of operation can be increased. One of the principal dangers in asynchronous operation is that two or more signals that should arrive at a given point in the system at different times will occasionally arrive so nearly simultaneously as to con- stitute a misleading result. Digital signals have two different values, commonly referred to as a 1 and a 0, and digital circuits normally respond to each value of an input signal in a specific way. Although digital signals are frequently described as if the time for such signals to shift from one of the values to the other were OMPI instantaneous, that is not an accurate description. A finite, though small, time is required for a signal to stabilize in its new value, and if another signal arrives with an overlapping transition time, the circuit that is supposed to respond in a certain way to one of the sig¬ nals may not do sσ._ The condition of having two signals contend with each other for control of a digital system or part of such a system on the basis of which signal arrives first is known as a race condition. Disclosure of the Invention One of the objects of this invention is to allow a digital signal processing system to operate asynchronously at a significantly higher speed than if it were restricted to synchronous operation and yet to do so with improved safety against races. Another object is to control a potentially contending signal so that it will ' be in one of its stable conditions and not in a transitional condition at the time it is applied to control a change of state. According to one aspect of the invention, there is provided a stabilization system for an asynchronous state machine, including decision logic means for con¬ trolling the sequencing of the machine from one state to another in dependence on digital input signals, charac- terized in that said decision logic means includes a plurality of input terminals for receiving predetermined ones of said digital input signals, feedback means having a plurality of feedback output terminals for feeding back signals representing a present state of the machine, and holding signal output means; and further characterized by latching means for receiving a further one of said digi¬ tal input signals, said holding signal output means being arranged to control said latching means to transmit said further input signal to said decision logic means only under predetermined state conditions. According to another aspect of the invention, there is provided a method of controlling the state - j - sequence of an asynchronous state machine under potential race conditions due to multiple possible branches from a predetermined state, characterized by the steps of: holding an input to the predetermined state and deter- mining whether any of the branches from the predetermined state are in conditions to allow transmission of a sig¬ nal thereto; transmitting the input signal to a branch in condition to allow such transmission; if no branch is in such condition, transmitting the input signal along a loop path to a follow state; transmitting the output signal of the follow state farther along the loop path to the holding state only after the holding state is in condition to receive it; and continuing around the loop from the holding state to the predetermined state to the follow state until one of the branches is in condition to allow transmission of the looped signal thereto. The present invention was conceived in response to the need to speed up operation of a certain synchronous system, and the new concept successfully allows asyn- chronous operation that is about three times as fast as it would be if the operation had to be controlled on a synchronous basis. Brief Description of the Drawings One embodiment of the invention will now be described by wa of example with reference to the accom¬ panying drawings, in which: Fig. 1 is a state diagram that contains a potential race condition; Fig. 2 is a state diagram that contains a holding state according to this invention; Fig. 3 is a simplified block diagram of an asynchronous system arranged according to this invention; Fig. 4 is a state diagram of one embodiment of this invention; Figs . 5A to 5D are a series of Karnaugh maps corresponding to the state diagram in Fig. 4; and Figs. 6A and 6B taken together show one embodiment of a combinational logic circuit and latching circuit corresponding to the state diagram of Fig. 4. Best Mode for Carrying Out the Invention The state diagram in Fig. 1 is only part of a diagram for a complete, asynchronous state machine, or system, but it is a part in which a race may occur, depending on the relative timing of input signals. A first input signal causes the machine to shift from a starting state to state 12, where it remains as long as a signal X is true. When that signal reverses polarity so that signal, or condition, X is true, the machine shifts to condition 13, where it remains as long as signal Y is true. From condition 13, the machine may follow any one of two or more branches, 14a-14n, de¬ pending on the relationship between signals that control the machine at this point, and this relationship varies due to the asynchronous nature of the controlling sig¬ nals. Thus a potential race between two or more of the signals exists at this point. Fig. 2 shows the simple way the state diagram of Fig. 1 can be modified to obtain the benefits of this invention. Between the states 12 and 13 is a hold¬ ing state 16 that holds the input signal X stable. The machine loops on the holding state 16 as long as a HOLD signal is false, that is, as long as the converse signal, HOLD, is true. The HOLD signal becomes true when the input signal becomes stable at the output, thus automatically compensating for propagation delays and making the state machine independent of the partic¬ ular components of which it is constructed. The input signal to the state 13 remains in the HOLD condition in that state, and, if none of the branches are TRUE, that is, ready to accept a signal from the state 13, the machine branches to a FOLLOW state 17, which allows the latching means that controls - — the state 16 to respond to a current signal X, which may not have the same binary value as the signal that was previously latched. The latching means latches the current, or updated, signal X. In the FOLLOW state 17, component propagation delays would again be compensated for automatically by not allowing the state machine to proceed to the HOLD state 16 until the HOLD signal (which may more accurately be considered as the HOLD INPUT SIGNAL STABLE signal) becomes false. This is equivalent to having the HOLD signal become true. When that happens, the machine jumps to the state 16, allowing the loop path around the states 16, 13, and 17 to repeat until one of the branches 14 is true. The machine then proceeds to that branch state. Only the states 16, 13, and 17 are necessary to form the SAMPLE-FOLLOW-HOLD loop. Fig. 3 shows a circuit capable of performing the sequence just described. This circuit includes several input terminals 18-20 to receive digital signals that control the transitions of the circuit from state to state. The input terminal 18 receives a signal that is likely to become involved in a race, and this ter¬ minal is connected to the data input terminal D of a transparent latch circuit 22. A transparent latch cir- cuit is a type of flip-flop circuit that allows digital signals applied to its data input terminal to proceed to its output terminal (here identified by the letter Q) essentially without modification as long as a control signal of a certain polarity is applied as a HOLD signal to a control terminal CP. When the HOLD signal reverses polarity, the input signal is latched at the one of its two binary values that it happens to have when the HOLD signal becomes effective. The circuit includes a combinational decision logic circuit 23 for which the terminals 19 and 20 and the Q terminal of the transparent latch circuit 22 serve as input terminals. The combinational decision logic circuit 23 includes output terminals 24a-24n and feed¬ back signal output terminals 26a-26n. The latter are connected by a mul iconductor bus 27 to feedback input terminals 28 (illustrated in this simplified represen- tation as just a single terminal) . A further output terminal 29 is connected to the control signal input terminal CP of the latching circuit means 22. Signals applied to the input terminals 18-20, together with feedback signals from the feedback out- put terminals 26a-26n effect state transitions in the logic circuit 23. In fact, the conditions at the feed¬ back output terminals 26a-26n correspond to the state of the system and are, therefore, called PRESENT STATE feedback signals. The combinational logic circuit 23 and the way in which its input and feedback signals control the states are not new in themselves. What is unique in this invention is the latching circuit 22 in conjunction with the combinational decision logic 23 and the holding signal provided by the latter at proper times via the terminal 29 to avoid a race between the signal applied to the input terminal 18 and signals applied to the terminals 19 and 20. Of course, in a more complex system, there can be more than one latching circuit and more than one holding signal output terminal 29. Fig. 4 represents a more complex state machine that requires three digits (more are possible) to repre¬ sent all of its states. The state diagram includes a first state 31 in which three state signals Y-,, Y. , and Y-. are each equal to 0, by definition. As long as a signal TR remains true, the machine stays in the 000 state and only shifts to the state 32 when the signal TR becomes true. The exact nature of the digital signal TR (and its converse TR) is immaterial to this inven- tion, and neither it nor any of the other controlling signals need be described. In the state 32 the signal Y Q = 1, so the state is represented as 001. The machine remains in the 001 state until a signal ACK reverses polarity to become ACK. This shifts the machine to the next state 33 represented by state signals Oil, or Y = 0 and Y. = Y Q = 1. Reversal of a signal CD to CD causes the state to shift to the HOLD state 34. As in Fig. 2, the HOLD state precedes a state in which a race could take place. This is the state 35 and it is reached when a control signal DR reverses polarity to DR. The state 34 is represented by state signals 111, but this fact, which symbolizes that Y =- Y = Y = l is not a necessary condition for latching. The latching state could be the state 35, which is represented by signals 101, corres¬ ponding to Y, = 1, Y, = 0, and Y Q = 0. Or, in a larger system, the latching could be associated with a state represented by any other group of 0' s and 1 ' s. What is necessary is that the signal (which, so far has not been identified) be latched before it gets to the branching state, and in this embodiment, the branching state is state 35. The machine remains in the state 35 until the signal ACK reverses polarity to become ACK, and then the machine branches either to a state 36, having state condition 100, or loops back to state 32, having state condition 001. This means that if the state signal Y n shifts from 1 to 0, the machine shifts from state 35 to state 36. Alternatively, if the signal Y remains 1 and the signal Y_ shifts to 0, the state loops back to the state 32. The latched signal that determines the direc¬ tion of branching from the state 35 is the signal P. If it has been latched in the polarity represented as P, the transition will be to state 36, but if it has the reverse polarity P ~ , the transition will be back to the state 32. While the polarity P or P determines the direction of branching, the transition cannot occur until the signal ACK has reversed to ACK. OMPI If the latched signal is P, the state tran¬ sitions continue to remain in state 35 until the signal ACK becomes true (and ACK false), at which time the state branches to state 36. In this embodiment it hap- pens that a TR latch (not shown) is reset, but any de¬ sired event could take place instead. It also happens that the machine proceeds directly from state 36 back to the initial state 31, but, again, any number of other states could be located in that path, including states that required further latching. The purpose of such latching would be analogous to the purpose of latching in the state 34. Figs. 5A-5D show Karnaugh maps representative of the operation of the state machine represented by the state diagram in Fig. 4. The top mag Fig. 5A is a complete representation of the entire sequence of states in Fig. 4. The signal Y Q is the first state signal to have its polarity reversed in going from the 000 condi¬ tion in state 31 to the 001 condition in state 32, and that transition occurs because the signal TR becomes equal to 1 (according to the logic being used) . The symbol TR thus appears alongside the arrow in the cell representing the state 31. Similarly the symbols ACK, CD, and DR appear alongside respective arrows in the cells 32-34. Transition from the cell 35 to the cell 36 takes place if P is true as represented by the arrow from the cell 35 to the cell 36. Otherwise, if P~ is true, the state machine loops back to the state 32, as indicated by the arrow " P. Fig . 5B represents the conditions in which Y-. = 1, as illustrated by the equation associated with that figure. The cell 35 is representative of two con¬ ditions: the condition in which the signal ACK is true and the state machine remains in the state 35 in which Y Q = 1, and the condition in which ATK becomes true and P " is also true, causing the machine to loop back to the state 32, where Y Q remains at 1. The alternative branch- ing to cell 36 requires that Y become 0 arid need not be represented in the equation in which Y n is 1. The map in Fig . 5C represents the conditions in which Y is 1, which is true only in cells 32-34. The map in Fig. 5D represents the conditions in which the signal Y 2 is 1, which is true in cells 33- 35. In the latter cell, Y-, = I while ACK is true, like Y Q . Unlike Y Q , Y~ remains 1 going to cell 36 when P and ACK are both true, as represented by the conjunction P.ACK. The circuit in Figs. 6A and 6B corresponds to the state diagram in Fig. 4 and the maps in Figs. 5A to 5B. It includes a number of input terminals 38a-38h to which various asynchronous input signals are applied. The terminal 38a is connected to the data input terminal D of a transparent latch 39. The terminals 38b-38h are connected to a first set of logic gates. The terminals 38b and 38c are connected, in this embodiment, directly to input terminals of a NOR gate 41 while the terminals 38d-38h are connected to a grid 42 of connectors to which the output terminal of the gate 41 is also con¬ nected, both directly and through an inverter 43. More specifically, the grid connectors to which the terminals 38b-38h and the output terminal of the NOR gate 41 are connected are illustrated as vertical lines in Figs. 6A and 6B. These vertical lines are illustrated as apparently being connected in groups to single-input NOR gates 44a-44m. Actually, of course, each NOR gate has more than one input terminal . In fact, each NOR gate has at least as many input terminals as the number of dots on the respective horizontal line leading to it. Each of the terminals, such as the ter¬ minal 38e, connected to a NOR gate is connected by a different horizontal line to a respective input terminal of the NOR gate; for example, the terminals 38d and 38e are connected by different horizontal lines to the NOR gate 44a. The input terminals are not simply short- circuited together, as the dots make them appear to be. Showing three or four separate horizontal lines to each NOR gate would make the drawing illegible. The horizontal and vertical lines that consti¬ tute the grid 42 leading from the input terminals 38b- 38h comprise a first circuit means operatively connect¬ ing these components to the first set of NOR gates 44a- 44m. The Q output terminal of the latch 39 is connected via the NOR gate 41 to this first circuit means. A second circuit means 46 consisting of a smaller grid connects output terminals of the NOR gates 44a-44m in sets, or groups, to input terminals of a second set of NOR gates 47a-47c. The same symbolism is used as in the first circuit means 42. Thus, there are actually five (vertical) lines connecting the five output terminals of the NOR gates 44a-44e to the five input terminals of the NOR gate 47a, three lines con¬ necting the three output terminals of the NOR gates 44f- 44h to the three input terminals of the NOR gate 47b, and four lines connecting the four output terminals of the NOR gates 44i-44m to the four input terminals of the NOR gate 47c. The output terminals of the NOR gates 47a-47c are connected by PRESENT STATE feedback lines 48a-48c to vertical lines 49a-49c in the first circuit 42. The feedback lines 48b and 48c are also connected through inverters 51b and 51c to other vertical wires in the grid 42. It happens that no inverter need be connected to the feedback line 48a, although grid 42 might include such an inverter as part of its hardware. The input terminal 38f is connected through an inverter 52 to one of the vertical lines in the grid 42. The terminal 38g is also connected through another inverter 53 to a vertical line in the grid 42 and the terminal 38h is connected directly and through an inver- ter 54 to separate lines in the grid. Another set of NOR gates 56a and 56b have their input terminals connected to the grid 42 and their out- put terminals connected to the input terminals of a NOR gate 57. The output terminal of the latter gate supplies the signal to control the holding, or latching, oper¬ ation of the latch circuit 39 and is connected directly to a terminal C of the latch and, via an inverter 58, to a terminal C. The operation of the circuit in Figs. 6A and 6B will be described in conjunction with the state diagram in Fig. 4. The circuit is placed in state 31 by causing the MR signal at the input terminal 38e to take the value 1. This signal is the correct signal to reset the latch 39 when applied to the reset input terminal R of the latch. The dots on the vertical line connected to the terminal 38e show that the MR = 1 signal is also applied to one input terminal of each of the NOR gates 44a-44m and the NOR gates 56a and 56b. The type of logic used in this circuit is such that, when any input terminal of a NOR gate has a 1 signal applied to it, the output terminal of that gate will go to 0, no matter whether a 1 or a 0 is applied to the other input ter¬ minals of the NOR gate. Thus the output terminal of each of the NOR gates 44a-44m goes to 0 as does the output terminal of each of the NOR gates 56a and 56b. As a result, all of the input signals to every input terminal of each of the NOR gates 47a-47c receives a 0 signal and this is the only condition that causes the output terminals of these NOR gates to take on the value 1. The lines leading from those output terminals are identified as Y , Ϋ " . , and Y~, respectively, which means that, immediately following the MR'= 1 signal, the output terminals of the NOR gates 47a-47c represent the converse of the state condition 000. Similarly, the output terminal of the NOR gate 57 is driven to the value 1, in which condition the input signal PF applied to the latch 39 is not held constant, or latched. m OMPI The Y = 1 signal from the NOR gate 47a is applied, as indicated by dots on its vertical line, to all of the NOR gates 44b-44m and 56a and 56b. As a result, the output terminals of those NOR gates will be held at the value 0 even after the MR signal becomes false, i.e., is terminated, or changed to 0. At this time, the only NOR gate 44 not locked into a 0 condition, that is, a condition in which it has a value of 0 on its output terminal, is the NOR gate 44a. As indicated in the state diagram in Fig. 4, the machine remains in the 000 state as long as the signal TR remains true, that is, at a value of 1. The other two input terminals of the NOR gate 44a have 0's applied to them from the Y_ inverter 51c and the Y. inverter 51b, and so, as soon as the T " R signal becomes false, that is, as soon as the signal applied to the input terminal 38d drops to the value 0, all of the input terminals of the NOR gate 44a will be receiving a 0. This is the condi¬ tion that causes the NOR gate 44a to go to 1, thereby applying a 1 to one of the input terminals of the NOR gate 47a. As a result, the output terminal of the NOR gate 47a changes to 0. Since the status of the output terminal of the NOR gate 47a is the signal n and cor¬ responds to the converse of the state signal Y n , and since the output signals _ = Ϋ, = 1, the machine is now in the state 001. This is the state 32 in Fig. 4. As soon as the ¥„ signal goes to 0, all of the input terminals of the NOR gate 44b are at 0, and so its output terminal goes to 1. » As long as ACK remains true, the machine will stay in state 32 represented by the state signals 001. When ACK becomes true, all of the input signals, which are MR, ACK, Y , and Y 2 , to the NOR gate 44f are 0 and the output signal from that NOR gate to the NOR gate 47b changes to 1. This causes the output signal T.. of the latter NOR gate to change to 0, so that the state sig¬ nals Y 2 Y 1 Y 0 are now 011 " As stLOWI - in Fig* 4 ' t:hat is the proper condition for state 33. When the output signal Ϋ. of the NOR gate 47b becomes 0 while the signal Y 2 from the inverter 51c is still 0, the output signal of the NOR gate 44h also becomes 1, as does the output signal of the NOR gate 44g, if the signal DR is 0. These conditions are consistent with,the fact that the state signals are Oil. As long as the signal CD remains 1, the mach¬ ine will stay in that state, but when the signal CD be¬ comes 0, the output signal of the NOR gate 44i goes to 1, and the output signal Ϋ of the NOR gate 47c goes to 0. This is consistent with the condition in state 34 in Fig. 4 in which the state signals Y„γ,Y π are 111. The NOR gates 56a and 56b are controlled by the signals Y_, γ_ , and Ϋ-,, and for the first time, all of the input signals to both of these NOR gates are 0. This allows their output signals to shift to 1 and causes the output signal of the HOLD NOR gate 57 to go to 0 and latch the signal PF applied to the transparent latch 39. The latched signal (together with the signals PE and TCM) causes the output signal of the NOR gate 41 to be either 1 or 0. When the machine is in state 34 due to state signals 111, it does not matter what the output signal of the NOR gate 41 is. The machine remains in state 34 until the DR signal becomes true, i.e., becomes 1. That causes the output signal of the NOR gate 44g to go to 0, and since the output signals of the NOR gates 44f and 44h are already 0, all of the input signals to the NOR gate 47b are 0, allowing its output signal Y to go to 1. This corresponds to state signals 101, as required when the machine is in state 35. The input signal Y to the NOR gate 56a shifts to 1, which makes the output signal of that NOR gate 0, but since the input conditions to the NOR gate 56b have not changed, its output signal is still 1, and the output signal of the HOLD NOR gate 57 is still 0. The ACK signal is 0, but as soon as it becomes 1, the machine is ready to shift out of state 35. It is at this point that the condition of the latched signal PF becomes important. If the output signal of the latch 39 is 1, the output signal P " of the NOR gate 41 will be 0 and the output signal P of the inverter 53 will be 1. Thus, having ACK become 1 causes the output signal of the NOR gate 44d to go to 0. Since this is the only NOR gate that was applying a 1 signal to the NOR gate 47a, the latter NOR gate is able to change states so that its output signal goes from 0 to 1. The fact that the ACK signal applied to the NOR gate 44e goes from 1 to 0 has no effect because the condition being examined is one in which the P signal applied to the NOR gate 44e is 1 and maintains the out¬ put signal of that NOR gate at 0. The output signals of both of the NOR gates 47a and 47b are now 1, corresponding to state signals 100, as required for entry to state 36. In this state the output signal Ϋ " of the NOR gate is changed to 1, which causes the output signals of all of the NOR gates 44b-44m, as well as NOR gates 56a and 56b, to go to 0. The NOR gate 44a receives a 1 signal from the inverter 51c, so all of the input signals to the NOR gates 47a- 47c are at 0. This shifts the machine back to state 31 in which all of the state signals Y_Y.Y n are 000. The output signals of both of the NOR gates 56a and 56b are 1, causing the output signal of the HOLD NOR gate 57 to return to 0 to release the latch 30 to follow any variation in the signal PF until it is latched again. Going back to state 35, if the signal P has been latched at 0 and P at 1, the subsequent change of the ACK from 0 to 1 causes the last input signal to the NOR gate 44k to go from 0 to 1, driving the output sig¬ nal of that NOR gate to 0. When the signal " P is at 1, the output of the NOR gate 44j is forced to 0, and the combined effect of having the signals P and ACK both at 0 is that the output of the NOR gate 44e will be 1. All of the other NOR gates 44i, 44k, and 44m already have output signals of 0, so the conditions required to change the output signal of the NOR gate 47c from 1 to 0 are fulfilled. This makes the state signals Y 2 γ ι γ n ec 2 ua l to 001, which places the machine back in state 32. It also releases the HOLD NOR gate 57. The machine is free tθι loop around states 32-35 until, at the time it enters the state 34, the signal P is latched in the true, or 1, state before the signal ACK goes true. The horizontal lines of the grid 46 have been labeled with the signals applied to the respective NOR gates 44a-44m, as indicated by the dots. It will be noted that the labels for the lines from the NOR gates 44a-44e, which control the NOR gate 47a and thus the state signal Y 0 , are the same elements that make Y Q = 1 in the equation under the Karnaugh map in Fig. 5B. In the same way, the labels for the signals to the NOR gates 44f-44h correspond to the terms on the right hand side of the equation for Y and the labels for the NOR gates 44i-44m correspond to the terms on the right hand side of the equation for Y .

Claims: - CLAIMS : 1. A stabilization system for an asynchronous state machine, including decision logic means for con¬ trolling the sequencing of the machine from one state to another in dependence on digital input signals, charac- terized in that said decision logic means includes a plurality of input terminals (38b-38h) for receiving pre¬ determined ones of said digital input signals, feedback means (47a-47c) having a plurality of feedback output terminals for feeding back signals representing a present state of the machine, and holding signal output means ' . (57); and further characterized by latching means (39) for receiving a further one of said digital input sig¬ nals, said holding signal output means (57) being ar¬ ranged to control said latching means (39) to transmit said further input signal to said decision logic means only under predetermined state conditions. 2. A system according to claim 1, charac¬ terized in that said latching means (39) is a circuit that either holds said further input signal in one of its two stable values, when said latching means is sub- jected to a control signal of one polarity, or allows said further input signal to pass through, essentially without interference, when said latching means is sub¬ jected to a control signal of the opposite polarity. 3. A system according to either claim 1 or claim 2, characterized in that said decision logic means includes a first plurality of gates (44a-44m) , each having a plurality of input terminals at least one of which is selectively connected to a said input terminal and at least one of which is selectively connected to said feedback means (47a-47c), whereby said decision logic means is controlled by selective combinations of said digital input signals and present state feedback signals to control transition of the machine from one state to another. 4. A system according to claim 3, charac¬ terized in that said decision logic means includes a second plurality of gates (47a-47c) which form said feedback means, said second plurality of gates each having input terminals selectively connected to output terminals of said first plurality of gates (44a-44m) to be controlled by output signals therefrom. 5. A system according to claim 4, charac¬ terized in that said first and second plurality of gates comprise NOR gates. 6. A system according to claim 1, character¬ ized in that said decision logic means includes gate means (56a, 56b) having input terminals selectively con¬ nected to said feedback output terminals to be controlled by the feedback output signals, and having output ter¬ minals connected to said holding signal output means (57). 7. A system according to claim 6, character¬ ized in that said gate means comprise first and second NOR gates (56a, 56b), and in that said holding signal output means is formed by a third NOR gate (57) having input terminals connected to the output terminals of said first and second NOR gates and having an output terminal connected to said latching means (39). 8. A stabilization system for an asynchronous state machine, including a plurality of input terminals (38a-38h) for receiving asynchronous digital input sig¬ nals, characterized by latching means (39) comprising a data input terminal (D) connected to a first one of said input terminals to receive a first one of said digital input signals, a data output terminal (Q), and a control signal terminal (C) ; a first plurality of gates (44a-44m) each comprising a plurality of input terminals and an output terminal; a second plurality of gates (47a-47c) each comprising a plurality of input terminals and an OMPI output terminal, each of the output terminals of said first plurality of gates being connected to a selected input terminal of said second plurality of gates, and said second plurality of gates providing at their output terminals signals representing a present state of the machine; first circuit means (41) connecting the data output terminal of said latching means to a first one of the input terminals of at least first and second gates (44e, 44j) of said first plurality of gates to apply output signals from said latching means thereto in pre¬ determined relative polarity; second circuit means (42) connecting one of said digital input signals to a second one of the input terminals of said first and second gates and to input terminals of third and fourth gates (44d, 44k) of said first plurality of gates, whereby said first gate is active only when the output signal from said latching means applied to said first gate has one effective polarity relative to that of said one of said digital input signals applied to said first gate, and said second gate is active only when the output signal from said latching means applied to said second gate has an effective polarity opposite said one effec¬ tive polarity; third circuit means (46) connecting the output terminals of said first and third gates (44e, 44d) of said first plurality of gates to input terminals of a first gate (47a) of said second plurality of gates, and connecting the output terminals of said second and fourth gates (44j, 44k) of said first plurality of gates to input terminals of a second gate (47c) of said second plurality of gates; and holding means (57) connected to the output terminals of said second plurality of gates to be actuated by the state signals therefrom to allow said first one of said digital input signals to pass through said latching means when the machine is in a certain state and to hold said first one of said digital input signals latched when the machine is in other states. 9. A method of controlling the state se¬ quence of an asynchronous state machine under potential race conditions due to multiple possible branches from a predetermined state, characterized by the steps of: holding an input signal to the predetermined state and determining whether any of the branches from the pre¬ determined state are in condition to allow transmission of a signal thereto; transmitting the input signal to a branch in condition to allow such transmission; if no branch is in such condition, transmitting the input signal along a loop path to a follow state; transmitting the output signal of the follow state farther along the loop path to the holding state only after the holding state is in condition to receive it; and continuing around the loop from the holding state to the predeter¬ mined state to the follow state until one of the branches is in condition to allow transmission of the looped signal thereto. 10. A method according to claim 9, charac¬ terized in that the input signal is held in a state immediately preceding said predetermined state. 11. A method according to claim 9 or claim 10, characterized by the step of supplying a second signal to effect transmission of the input signal from said predetermined state.

Inventors: ECTON WILLIAM WILLIS, ECTON, WILLIAM, WILLIS
Applicants: NCR CO, NCR CORPORATION
Application year: 1984
Main classification: G06F9
IPC codes: G05B19, G06F9, H03K19