A METHOD FOR MAKING LOGIC CIRCUITS

Abstract: A method is provided for reducing an arbitrary Boolean logic expression to static CMOS circuits by the use of a gen­ eral matrix (10 and 12) of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, from a Boolean expression a sum-of-­ products expression giving the 1 binary data outputs of a truth table having a 0 input is found. This is accomplished by com­ plementing, or barring, the literals which are a binary 1 when the output is 1 and leaving true or unbarred the literals that are a binary 0. Then each input (A-D; A - D ) of a given product term is applied to the control gate of a P channel device, which devices are connected in series with one end tied to a source of potential (V H ) and the other end of the series circuit con­ nected to an output terminal (Q). Each product term is arranged in parallel with other P channel device series circuits to form one half of a complete logic matrix (10). Similarly, for the other half of the matrix (12),a sum-of-products expression giving the binary 0 outputs of a truth table having a binary 1 for an input is found. Each input of a given product term is applied to the control gate of an N channel device, which devices are connected in series with one end tied to a potential reference point, such as ground, and the other end of the series circuit is connected to the output terminal. Each pro­ duct term is arranged in parallel with other N channel device series circuits.

Description: This invention relates to a method of designing a logic circuit according to the preamble of claim 1. It is well known that the CMOS technology provides advantages over integrated semiconductor-technologies that use only N channel devices, which may be referred to as NMOS devices, or only P channel devices, which may be referred to as PMOS devices. Some of these advantages include speed and virtually no standby power. In static logic designs using only the N channel device technology, complex random logic circuits are either constructed from simple logic blocks or from AND/OR arrays which consume direct current power and are often slow and inefficient in the use of semiconductor surface area. A basic logic circuit comprising a matrix having a plurality of circuits of serially arranged P channel devices disposed between a power supply and an output terminal and having a plurality of circuits of serially arranged N channel devices disposed between the output terminal and a point of reference potential, such as ground, is taught in U.S. Patent US-A-3,252,011, filed by B. Zuk on March 16, 1964. In U.S. Patent US-A-4,069,426, filed by M. Hirasawa on October 5, 1976, there are taught more complex matrices with more parallel circuits having a higher number of devices for handling a variety of functions. Several logic charts, logic circuits and a truth table are disclosed. Furthermore, this patent discloses logic formulas, one of which relates to the P channel circuit and another which relates to the N channel circuit of a matrix. This complementary MOS logic circuit for obtaining second logic signals corresponding to a large number of logic combinations derived from a group of first logic signals, wherein a plurality of series circuits each formed of a plurality of series circuits each formed of a plurality of series-connected first channel type IG-FET's and a plurality of series each formed of a plurality of series-connected second channel type IG-FET's are jointly connected to the output terminal of said complementary MOS type logic circuit. This complementary MOS logic circuit with IG-FET's does not meet the requirements for making high density circuits which produce any desired Boolean logic function at high speeds with a low power. In "Electronic design" Volume 15, Number 19, 13 September 1967, pages 81-87 is a nanopower IC-logic with complementary MOS arrays described. In this publication is a method described how to design a logic circuit starting with a trues table which determines the logic functions for the performance of which the logic circuits should serve. The proposed circuits of this document do not solve the objective of this invention, particularly each circuit component or its input respectively can not be accessed individually. U.S. Patent US-A-3,945,000 filed by Y. Suzuki et al on July 30, 1974, discloses a logic matrix having all P channel devices formed in one area of a chip and all N channel devices formed in another area of the chip. Also, this patent discloses that the P channel devices are arranged according to a logic function of a certain expression, and the N channel devices are arranged according to a logic function of a different expression. U.S. Patent US-A-3,643,232, filed by J. S. Kilby on June 5, 1967, describes a semiconductor chip having a plurality of devices preformed within a semiconductor substrate and then selected devices are interconnected with metallic strips to form desired circuits. It is the object of this invention to provide a method of designing a logic circuit which produces any desired Boolean logic function at high speeds with low power and allows automation of logic chip designs from truth tables or logic expressions to the chip layout. The solutions of the object are characterized in claims 1, 4 and 5. In accordance with the teachings of this invention, a method is provided for reducing an arbitrary Boolean logic function or expression to, e.g., static CMOS circuits by the use of a general matrix of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, a Boolean expression as a sum-of-products expression is derived from the 1 binary data outputs of a truth table having binary 0 and 1 inputs. This is accomplished by complementing, or barring, in the expression the inputs or literals which are a binary 1 when the output is 1 and leaving true or unbarred the inputs or literals that are a binary 0. Then each input of a given product term in the expression is applied as a voltage to the gate electrode of a P channel device, which devices are connected in series with one end tied to a source of potential and the other end of the series circuit connected to an output terminal. Each product term is arranged in parallel with other P channel device series circuits to form one half of a complete logic matrix circuit. Similarly, for the other half of the matrix, a sum-of-products expression giving the binary 0 outputs of a truth table having binary 1's or 0's for an input is found. Each input of a given product term is applied as a voltage to the control gate of an N channel device, which devices are connected in series with one end tied to a potential reference point, such as ground, and the other end of the series circuit is connected to the output terminal. Each product term is arranged in parallel with other N channel device series circuits to form the other half of the logic matrix. Each of the two halves of the matrix can be minimized by factoring out the common literals in the sum-of-product expressions. Redundant P and N channel devices are eliminated and common nodes are tied together. The foregoing and other objects, features and advantages of the invention will be apparent from the following and more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. Fig. 1 illustrates a basic schematic diagram within which the circuits produced by the present invention are formed, Fig. 2 illustrates a P channel device array and an N channel device array which may be used in the schematic diagram of Fig. 1, Fig. 3 illustrates an arbitrary logic truth table, Fig. 4 illustrates a logic circuit formed by appropriately interconnecting the P and N channel devices of Fig. 2 which relates to the truth table of Fig. 3, and Fig. 5 is a layout or topological view of a semiconductor chip in which the circuit of Fig. 4 is formed. Referring to the drawings in more detail, there is illustrated in Fig. 1 a basic schematic diagram within which the circuits produced by the present invention may be formed. The diagram includes a first switch 10, made of one or more PMOS devices, connected between a source of potential V H , which may have a potential of +5 volts, and an output terminal Q with input signals I P shown in vectorial form to indicate that a plurality of signals or terms may be applied to the input of the PMOS switch 10. The diagram also includes a second switch 12, made of one or more NMOS devices, connected between a point of reference potential, such as ground G, and the output terminal Q. The PMOS and NMOS switches 10 and 12, respectively, generally in the form of PMOS and NMOS logic networks, are duals of each other in that when the PMOS switch 10 is open, the NMOS switch 12 is closed, as indicated in Fig. 1, and vice versa. Thus, it can be seen that in the type of circuit or network illustrated in Fig. 1, there is no static direct current (DC) power dissipated at any time. Fig. 2 illustrates a convenient arrangement of P channel devices or field effect transistors, each being identified by P, which may be used to form the PMOS switch or network 10 shown in Fig. 1. A similar arrangement of N channel devices or field effect transistors, each being identified by N, which may be used to form the NMOS switch or network 12 is also shown in Fig. 2. Fig. 3 illustrates an arbitrary logic truth table having four input signals or literals A, B, C and D and an indication of the output signal Q, a binary 1 or 0, arranged in four rows and four columns, for the various combinations of inputs of the four literals A, B, C and D. The Boolean expression for this truth table may be found to be In accordance with the teachings of this invention, from a truth table, such as the table of Fig. 3, a Boolean logic expression Q P is derived using 1 binary data outputs having binary 1's and 0's as an input. The inputs or literals which are a binary 1 are complemented, or barred, when the output is a binary 1, with the inputs or literals which are a binary 0 remaining true or unbarred. Thus, by referring to the truth table in Fig. 3, it can be seen that By using known algebraic theorems and by factoring out the common inputs in the sum-of-product expression, Having derived this Boolean expression, a voltage representative of each input of a given product term of the expression is applied to the gate electrode of a P channel device P in the PMOS switch or network 10 which are connected in series with one end tied to the source of potential V H and the other end of the series circuit connected to the output terminal Q. Each product term is arranged as a series circuit between the potential source V H and the output terminal Q and in parallel with all other PMOS device series circuits representing other product terms of the expression. By referring to Fig. 4 of the drawings, it can be seen that the inputs A , B, C and D of one term of the expression Q P are connected to the control gates of transistors 14, 16, 18 and 20, respectively, which are serially interconnected between the potential source V H and the output terminal Q. Furthermore, it can be seen that the input A of the other term of the expression Q P is connected to the control gate of transistor 22, while the inputs D , C and B of this other term are connected to the control gates of transistors 24, 26 and 28, respectively, each of which is connected serially with transistor 22 between the potential source V H and the output terminal Q, in accordance with the terms of the expression Q P indicated by formula (2) identified hereinabove. It should be noted that input A could be connected to the gate electrodes of three P channel devices P with each of the transistors 24, 26 and 28 being connected serially with a different transistor rather than with the common transistor 22 to form the PMOS switch or network 10, in accordance with the terms of expression Q P indicated by formula (1) identified hereinabove. However, since fewer transistors are used when forming the PMOS switch or network 10 in accordance with the terms of expression Q P indicated by formula (2), the circuit arrangement for formula (2) is preferred. Further in accordance with the teachings of this invention, from the truth table in Fig. 3, a Boolean logic expression Q N is derived using 0 binary data outputs having binary 1's and 0's as inputs. The inputs or literals which are binary 0 are complemented, or barred, when the output is a binary 0, with the inputs or literals which are a 1 remaining true or unbarred. Thus, by again referring to the truth table in Fig. 3, it can be seen that By using known theorems and by factoring out the common inputs in the sum-of-product expression, With this Boolean expression Q N having been derived from the truth table, a voltage representative of each input of a given product term is applied to the gate electrode of an N channel device N in NMOS switch or network 12 which are connected in series with one end of the series circuit tied to the point of reference potential G and the other end connected to the output terminal Q. Each product term is arranged as a series circuit between the point of reference potential G and the output terminal Q and in parallel with all other NMOS device series circuits representing other product terms of the expression Q N . By again referring to Fig. 4 of the drawings, it can be seen that the inputs A , B , C and D of one term of the expression Q N are connected to the control gates of transistors 30, 32, 34, and 36, respectively, which are serially interconnected between the point of reference potential G and the output terminal Q. Furthermore, it can be seen that the input A of the other term of the expression Q N is connected to the control gate of transistor 38, while the inputs D, C and B of this other term are connected to the control gates of transistors 40, 42 and 44, respectively, each of which is connected serially with transistor 38 between the point of reference potential G and the output terminal Q, in accordance with the terms of the expression Q N indicated by formula (4) identified hereinabove. It should be noted that input A could be connected to the gate electrode of three N channel devices N with each of the transistors 40, 42 and 44 being connected serially with a different transistor rather than with the common transistor 38 to form the NMOS switch or network 12, in accordance with the terms of expression Q N indicated by formula (3) identified hereinabove. Generally, since fewer devices are used, the circuit formed in accordance with formula (4) is preferred. Although the circuit of Fig. 4 was formed from expressions Q P and Q N , formulas (2) and (4), respectively, derived from the truth table in Fig. 3, it should be understood that other logic circuits may be designed in a similar manner from truth tables which differ from that of Fig. 3. Not only can the truth table of Fig. 3 have the input literals with different outputs, but the number of inputs may be fewer or greater than four, as desired. It can be seen that with four inputs or literals, as in the truth table of Fig. 3, there are four columns and four rows of P channel transistors P and four columns and four rows of N channel transistors N in Fig. 4, although many of these transistors are not used for the logic circuit formed in Fig. 4 and, therefore, are available for other circuits. In Fig. 5, there is illustrated a layout or topological view of a portion of a semiconductor chip or wafer 46 in which the circuit of Fig. 4 is fabricated. The chip 46 includes a substrate 48 which may be made of P conductivity type silicon. An N well 50 is formed in the substrate 48 by, e.g., diffusion or implantation of arsenic. A first thin layer of silicon dioxide 52 is grown or deposited over the N well 50 and a second thin layer of silicon dioxide 54 is grown or deposited over substrate 48 outside of the N well 50 but adjacent thereto. A thick oxide layer 56 is grown or deposited by any known technique over the substrate 48 outside of the thin silicon dioxide layers 52 and 54. A plurality of parallely arranged conductive strips 58, preferably made of doped polysilicon, are formed over the insulating layers 52, 54 and 56. Under the first thin silicon dioxide layer 52 and adjacent to each side of each strip 58 is a source/drain P conductivity type region 60 which may be made by implanting boron into N well 50 with the strips 58 acting as a shield for defining the channel regions of the PMOS devices or transistors, each of which includes two adjacent source/drain regions 60 separated by one of the strips 58 disposed over the transistor's channel region. Under the second thin silicon dioxide layer 54 and adjacent to each side of each strip 58 is a source/drain N conductivity type region 62 which may be made by implanting arsenic into the substrate 48 with the strips 58 acting as a shield for defining the channel regions of the NMOS devices or transistors, each of which includes two adjacent source/drain regions 62 separated by one of the strips 58 disposed over the transistor's channel region. A bus V H which may be made of metal, such as aluminum, and which is the source of potential for the logic circuit on chip 46 is formed over the P channel transistors 58, 60 and insulated from the polysilicon strips 58. A ground bus G which also may be made of metal is formed over the N channel transistors 58, 62 and insulated from the polysilicon strips 58. Metallic interconnecting strips 64 are also formed over the P and N channel transistors and are insulated from the polysilicon strips 58. Contacts to the source/drain regions 60 and 62 from the metal buses V H and G and the metallic strips 64 are indicated by an X. The transistors, including the control gates, of the logic circuit of Fig. 4 are indicated in Fig. 5 by the same reference characters. It can be seen that the structure of Fig. 5 forms a very compact CMOS logic circuit which is readily expandible and which adheres to an automated logic methodology. It is apparent that a finite matrix can be used as a program logic array which is programmable at the mask level. This implementation may be used for any CMOS technology. It should be understood that this methodology for rapidly preparing logic circuits from truth tables is valid for any random logic function and also for common logic building blocks such as NOR, NAND, AOI, XOR and multiplexers. The stacking of devices is limited only by performance. For several levels, the output may be buffered and amplified, if desired. The speed of operation of this circuit is enhanced by the processing of the input data in parallel and by its compactness. Static DC power is not dissipated at any time. It should also be understood that the methodology described hereinabove in connection with static CMOS circuits also applies to static and dynamic NMOS circuits and to dynamic CMOS circuits. For static NMOS circuits, the P channel array or PMOS switch 10 is replaced by, e.g., a single N channel load device or transistor. Stacking is limited in this case due to ratioed constraints. Dynamic NMOS and CMOS circuits replace the P channel array 10 with pulsed or clocked load devices of either N or P channel type. Such arrays, however, are leakage and noise sensitive, and must be operated synchronously. The matrix 10 of Fig. 4 provides amplification, a full supply voltage being available at the output terminal Q. Additional amplification may be provided in the matrix if desired, to further improve speed.

Claims: Method of designing a logic circuit which satisfies the requirements of a truth table having a given number of binary input literals and binary output values which comprises the following steps: forming inputs of first and second product terms of a first Boolean function Q P from a truth table by complementing the binary input literals which are a "1" when the output value is a binary "1" and using the true binary input literal which is a "0" when the output value is a binary "1" by forming first and second series circuits respectively comprising a plurality of P channel transistors and connecting them in parallel between a voltage source and an output terminal and by applying a voltage representative of each input of said first and second product terms of said first Boolean function to control gates of said plurality of P channel transistors, forming inputs of first and second product terms of a second Boolean function Q N from said truth table by complementing the binary input literals which are a "0" when the output value is a binary "0" and using the true binary input literal which is a "1" when the output value is a binary "0" by forming third and fourth series circuits respectively comprising a plurality of N channel transistors and connecting them in parallel between said output terminal and a point of reference potential and by applying a voltage representative of each input of said first and second product term of said second Boolean function to control gates of said plurality of N channel transistors. Method as set forth in claim 1, characterized in, that one of said formed inputs is common to the first and second terms of said first Boolean function and that for said first and second series circuits a common P channel transistor is formed. Method as set forth in claim 1, characterized in, that one of said inputs is common to the first and second terms of said second Boolean function and that for said third and fourth series circuits a common N channel transistor is formed. Method as set forth in claim 1, characterized by a voltage representative of each input of each product term of said first Boolean function which is applied to control gates of a plurality of P channel transistors interconnecting them to form a plurality of series circuits, connecting said plurality of series circuits in a parallel arrangement between a voltage source and an output terminal, applying a voltage representative of each input of each product term of said second Boolean function to control gates of a plurality of N channel transistors interconnected to form a plurality of series circuits, and connecting said plurality of series circuits of N channel transistors in a parallel arrangement between said output terminal and a point of reference potential. Method as set forth in claim 4, characterized by forming a first matrix (10) of a plurality of P channel field effect transistors, and forming a second matrix (12) of a plurality of P channel field effect transistors is processed, where one of the inputs is common to two of said product terms of said first Boolean function and at least two of the series circuits of P or N channel transistors have a common P or N channel transistor respectively. Method of designing a logic circuit as set forth in claims 1 or 4, characterized by forming the first Boolean function Q P to a form having a minimum number of inputs, forming the inputs of a plurality of product terms of a second Boolean function Q N from said truth table by complementing the binary input literals which are a 0 when the output value is a binary 0 and using the true binary input literals which are a 1 when the output value is a binary 0, reducing said second Boolean function Q N to a form having a minimum number of inputs, applying a voltage representative of each of said minimum number of inputs of said first Boolean function Q P to control gates of a plurality of P channel transistors interconnected to form a plurality of series circuits, connecting the plurality of series circuits in a parallel arrangement between a voltage source and an output terminal, applying a voltage representative of each of said minimum number of inputs of said second Boolean function Q N to control gates of a plurality of N channel transistors interconnected to form a plurality of series circuits, and connecting the plurality of series circuits of N channel transistors in parallel arrangement between said output terminal and a point of reference potential. Method as set forth in claim 5, characterized by forming said second matrix (12) of N channel transistors in a first region of a P type conductivity semiconductor substrate, forming a N well in a second region of said substrate adjacent to said first region, and forming said first matrix (10) of P channel regions in said N well. Method of designing a logic circuit as set forth in claim 6, characterized by forming a plurality of series circuits of P channel transistors in parallel between a voltage source and an output terminal, applying a voltage representative of each input of each product term of said reduced first function to the control gates of the P channel transistors of a respective one of said series circuits, forming a second function having a plurality of product terms from said truth table, each of said terms having a number of inputs equal to said given number and being formed by complementing the binary input literals which are a 0 when the output value is a binary 0 and using the true binary input literal which is a 1 when the output value is a 0, reducing said second function to a form having a minimum number of product terms, forming a plurality of series circuits of N channel transistors in parallel between a point of reference potential and said output terminal, and applying a voltage representative of each input of each product term of said reduced second function to the control gates of the N channel transistors of a respective one of said series circuits of N channel transistors.

Inventors: GRIFFIN, WILLIAM ROBERT, HELLER, LAWRENCE GRIFFITH
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1984
Main classification: H03K19
IPC codes: H03K19, H01L27, H01L21