SYSTEM FOR CHECKING ABNORMALITY IN PROGRAMMABLE CONTROLLER

Abstract: When a fault occurs in a programmable controller, an address is set so that the status of each of the elements of a circuit can be read out in a sequence relating to the fault. The difference between the status of an address signal stored in an address-setting table (TA) and the actual address signal status is detected by a signal variation detection means (2). Each time there is a signal status difference, the address and the actual signal status are successively written into a signal variation storage table (TB) by a signal variation write means (3). The stored contents are displayed on a display means, enabling investigation of the cause of the fault.

Description: The present invention relates to a sequence abnormality check system for checking abnormality in a programmable controller, allowing a cause of failure to be determined when abnormality occurs in normal operation of the programmable controller. In a conventional sequence control system, a sequence circuit is arranged between a control device and a machine to be controlled. The sequence circuit comprises a heavy current circuit consisting of a number of relays. A predetermined relay is operated in response to an instruction from the control device so as to cause machine members to perform a predetermined operation in accordance with this instruction. In a system using a programmable controller (to be referred to as a PC hereinafter), a representation of a sequence circuit is stored in the form of a program in a memory of the PC, thereby performing sequence control. For example, the sequence circuit is represented by a ladder diagram represented by relay symbols, as shown in Fig. 1. A sequence program having a logical sequence of instruction codes and operands shown in Fig. 2 is stored in a memory of the PC, thereby replacing several relays whilst still achieving proper sequence control. The ladder diagram shown in Fig. 1 comprises part of a ladder diagram of a numerical control (NC) machine tool system. Symbols and denote normally open and closed contacts of relays (not shown) each having a reference symbol. When M03 (spindle forward rotation instruction) is supplied from an NC in the automatic mode, relays MF, M12 and M11 are operated to energize a relay M03X. In this case, since the automatic mode is set, a relay AUT is kept ON. Unless the spindle is rotated in the reverse direction, (a relay SPCCW is kept OFF) and a relay SPCW is turned on. This indicates that the spindle forward rotation instruction is supplied to a machine such as a machine tool. In the conventional system, the heavy current circuit including actual relays represented by the ladder diagram, controls the sequence of the machine tool. The PC creates a sequence program of Fig. 2 in accordance with the ladder diagram, and the sequence program is stored in a memory so as to provide sequence control. "RD", "AND", "WRT", "OR", "AND·NOT", etc. in the sequence program are instruction codes, respectively. More specifically, RD is a read instruction; AND, a logical product operation instruction; WRT, a write instruction; OR, a logical sum operation instruction; and AND·NOT, an inversion/logical product instruction. Numeric values in the operand column represent addresses of a data memory (to be described later) incorporated in the PC. The addresses correspond to relay symbols (MF, M28, etc.) of Fig. 1, respectively. The relationship between the relay symbol and the address is illustrated in Fig. 1. The relay symbols are listed for reference at the right of the table in Fig. 2. The information at the addresses of the data memory which are described in the column of operands is calculated by an instruction group D1 of the sequence program. In other words, a logical operation MF· M28 · M24 · M22 · M21 · M18 · M14 ·M12·M11 is calculated. A calculation result ("1" or "0") is stored at address 10.2 of the data memory which corresponds to the relay M03X. The following operation is performed in accordance with an instruction group D2: AUT·M03X· SPCCW A calculation result is stored at address 20.5 of the data memory which is designated by the operand SPCW. As a result, a spindle forward rotation signal is supplied to the machine tool as an external machine, so that the spindle of the machine tool is rotated in the forward direction. In this manner, the sequence control system having the PC is operated in accordance with the sequence program. In this control system, when an intermittent failure of the sequence occurs during automatic operation of the machine tool, it is difficult to determine the cause. Assume that the machine tool is interrupted while in a feed hold state during NC automatic operation and that the machine tool is not supposed to be stopped. A feed hold circuit is illustrated in Fig. 3A. Reference symbol a denotes a feed hold button; b , a pressure decrease detection switch; and SP, a feed hold relay. This feed hold circuit is represented by a ladder diagram in Fig. 3B. Since the machine tool is interrupted in the feed hold state, the feed hold relay SP is stopped (de-energised). When a signal (i.e., logic level of the signal at address 102.5 of the data memory which represents the feed hold relay SP) representing the operating state of the feed hold relay SP is checked, a "1" is stored at address 102.5. The logic level "1" indicates that the feed hold relay SP should normally be in the operated (energised) state. This indicates that the failure may have been caused by the contact of the feed hold button or the pressure decrease detection switch being accidentally and temporarily opened during automatic operation. However, since the contacts a and b are only instantaneously turned off, it is difficult to check changes in levels of the contacts even though the contacts a and b are monitored. For this reason, detection cannot be performed as to which contact system caused the abnormality. In this sense, the failure check operation becomes cumbersome. In order to solve this problem, a system has been proposed wherein a failure check program is created and stored in the PC to discriminate failures. Even with this system, failure check operation is cumbersome. US-A-4 063 311 discloses a diagnostic apparatus for use with a programmable controller. The diagnostic apparatus operates continously in normal operation of the controller, to display information on any failure condition (i.e. disagreement between programmed and actual logic states) occurring in the current cycle of operation. A numerical representation of the cycle step under test is displayed on a readout for as long as the failure condition continues; or, if more than one failure occurs, each is displayed one at a time for a predetermined period. Therefore, the operator has to observe the readout carefully to note all the failures and then try to work out the underlying cause. JP-A-52-149580 discloses a sequence abnormality check system having features corresponding to those of the preamble of accompanying claim 1. In this system, a history of changes of operation states of all elements in a sequence circuit is produced continuously and automatically. There is no way to restrict attention to a particular part of a sequence circuit where a failure is known to have occurred, and consequently it is difficult for the operator to analyse the generated information in order to diagnose the failure. According to the present invention, there is provided a sequence abnormality check system for a programmable controller, the programmable controller including a sequence program for controlling a machine tool in conjunction with control elements, each control element having an operational state given by a logic level of an actual signal, and having an associated address in the programmable controller; the system comprising:- first memory means for storing operational states of said elements; means for detecting changes in operational states of said elements; second memory means for storing operational states of one of said elements for which a change in operational state has been detected; and signal update writing means for writing into the second memory means an address and the new logic level of the actual operational state for each element having a changed operational state; characterised by:- address setting means for entering the addresses of elements associated with an abnormality, so as to define a set of said elements in which the abnormality has occurred; an address setting table, providing said first memory means, for storing addresses of said set of elements as defined by said address setting means and for storing the operational states of the elements corresponding to the addresses; signal update detecting means, providing said means for detecting changes in operational states of said elements, responsive to the stored contents of the address setting table for generating an output when an operational state of an element stored in said address setting table is different from the logic level of the actual signal for that element when the sequence program is run subsequent to the address of that element being set in the address setting table by the address setting means; and a signal update storage table, providing said second memory means; further characterised in that said signal update writing means is operable to write into the signal update storage table a mark identifying that address which was last updated, and to update the operational states stored in the address setting table to correspond to the logic levels of the actual signals; and in that a display means is operable, in response to the addresses of a set of elements being stored in said address setting table, to display in sequential order the addresses stored in said signal update storage table, together with the corresponding logic levels and said mark identifying the last updated address, thereby facilitating recognition of the element which has caused the abnormality. An embodiment of the present invention may provide a sequence abnormality check system for a programmable controller (PC) which checks for the cause of a failure by displaying the updating of signals associated with the failure when an abnormality occurs during normal operation of the programmable controller. In this way, when an element of the sequence circuit which is not supposed to be operated is instantaneously operated, thereby causing a failure such as a stop of the machine tool, the logic levels of the updated signals at addresses corresponding to the elements subjected to the failure, and an updating order, are displayed upon setting of these addresses. As a result, the cause of the failure can be immediately determined, thereby quickly restoring the system. Reference is made, by way of example, to the accompanying drawings in which:- Fig. 1 is a ladder diagram; Fig. 2 shows a sequence program in accordance with the ladder diagram of Fig. 1; Fig. 3A is a circuit diagram of a feed hold circuit; Fig. 3B is a ladder diagram of the feed hold circuit of Fig. 3A; Fig. 4 is a block diagram of a PC with a sequence abnormality check system embodying the present invention; Fig. 5 is a hardware block diagram of the system of Fig. 4; Fig. 6 is a flow chart for explaining the operation of the system; Fig. 7 illustrates a format of an address setting table TA; and Fig. 8 illustrates a format of an address update storage table TB. Fig. 4 is a block diagram of a PC which employs the present invention. Reference numeral 1 denotes a sequence control means. The sequence control means 1 receives an input signal from a machine such as an NC machine tool through an input circuit 4 and a signal which is supplied from a control relay 6 in the sequence circuit and which is stored in the PC. The sequence control means 1 then generates an output signal to the machine through an output circuit 5 in accordance with the sequence program, thereby controlling the sequence of the machine. The PC of the present invention has a signal update detecting means 2, a signal update writing means 3, an address setting means 7, and a storage means. The storage means has an address setting table TA and a signal update storage table TB. The address setting means 7 sets addresses of the data memory 13(Fig.5) of the PC which store logic levels of the respective elements of the sequence circuit. When a failure occurs, an address associated with the failed element is set by the address setting means 7 in the address setting table TA. The address setting table TA also stores the entered address and the logic level of the signal associated with this address. The signal update detecting means 2 compares the logic level of the signal at the address of the address setting table TA with a corresponding actual signal. In other words, the signal update detecting means 2 compares the logic levels of the signals at addresses of the data memory 13 which respectively correspond to the input circuit 4, the output circuit 5 and the control relay 6. When the signal update detecting means 2 detects updating (change) of the signal, the signal update writing means 3 updates the logic level at the address of the address setting table TA to that of the actual signal. At the same time, this address, the logic level of the signal at this address, and a signal representing the last updated signal are stored in the signal update storage table TB. As a result, the signal update storage table TB stores an updated signal address order and the corresponding logic levels of the addresses. Assume that an intermittent failure occurs to stop the machine while sequence control is performed by the PC in a machine such as an NC machine. An address associated with the failure is entered at the address setting means 7 in accordance with the ladder diagram and is stored in the address setting table TA. The signal update detecting means 2 compares the logic level of the actual signal at the address of the address setting table TA with the logic level (upon initialization, the logic level is set at "0" or "1") corresponding to this address. If these logic levels are different from each other, the updated logic level is stored at the corresponding address of the signal update storage table TB. At the same time, the logic level of the actual signal is stored in the address setting table TA. As a result, after the PC repeats the sequence control a few times, the logic levels of the current signals are stored at the respective addresses of the address setting table TA. The signal update storage table TB stores an address order representing updating of the logic levels and the updated logic levels at the addresses. At the same time, a signal representing the last updated signal is assigned at the last updated address. When the storage contents of the signal update storage table TB are displayed, the address order representing updating of the logic levels, the corresponding logic levels, and the last updated address can be visually checked. Therefore, the operator can check whether or not signal updating is normally performed, i.e., an element which is not to be operated is operated. Fig. 5 is a block diagram of PC hardware according to the present invention. Fig. 6 is a flow chart for explaining the operation of the PC hardware. Referring to Fig. 5, reference numeral 11 denotes a ROM for storing a control program for controlling the overall operation of the PC. Reference numeral 12 denotes a ROM for storing a sequence program and a signal update detection program. Reference numeral 13 denotes a data memory comprising a RAM for storing logic levels of signals representing the respective elements of the sequence circuit which are represented by relay symbols in Figs. 1 and 3B. Reference numeral 10 denotes a microprocessor (MPU) for performing predetermined sequence processing in accordance with the control program and the sequence program. The MPU 10, the ROM 11 for storing the control program, the ROM 12 for storing the sequence program and the signal update detection program, and the data memory 13 for storing logic levels of signals which represent the operating states of the respective elements of the sequence circuit, constitute the sequence control means 1, the signal update detecting means 2 and the signal update writing means of Fig. 4. Reference numeral 14 denotes a storage hold memory for storing the address setting table TA and the signal update storage table TB; and 16, a display unit for displaying the tables TA and TB stored in the storage hold memory 14. The display unit 16 comprises a CRT or a printer. Reference numeral 15 denotes a keyboard input means used as the address setting means 7 of Fig. 4 when the address associated with the failure upon occurrence thereof is entered into the data memory. Reference numerals 4 and 5 denote input and output circuits for connecting the NC machine or a machine tool to the PC, respectively. Reference numeral 17 denotes a bus. The PC having the arrangement described above controls the sequence of the external machine in accordance with the sequence program stored in the ROM 12. Logic signals each having a predetermined logic level are stored at predetermined addresses of the data memory 13 by input and output signals from the input and output cicuits 4 and 5. The logic levels of these signals represent the operating states of the elements of the sequence circuit. When sequence program processing (Fig. 2) is completed, the signal update detection program (Fig. 6) is executed. A cycle of the sequence program and the signal update detection program is repeated. Assume that a sensor such as a limit switch at the machine side is accidentally and temporarily operated against expectation during sequence control, causing the machine to stop. The failure check operation of the PC will be described with reference to the flow chart of Fig. 6. When a failure occurs, the operator determines the address of a sequence element associated with the failure in accordance with the ladder diagram. This value is entered at the keyboard 15 serving as the address setting means 7, and is stored in the address setting table TA in the storage hold memory 14, as shown in Fig. 7. The logic level of the address signal may be entered at the address setting means 7. Otherwise, any logic level "1" or "0" is stored in the address setting table TA. The MPU 10 in the PC checks from the beginning of the address setting table TA whether or not the (any) address is set in the address setting table TA (S1 of Fig. 6) after one sequence control cycle is completed. If YES, the MPU 10 checks whether or not the signal set in the address setting table TA has the same logic level as that of the actual signal (i.e., the MPU 10 compares the logic levels of the signals which represent the operating states of the input and output circuits 4 and 5 and the control relay 6 with those which are stored in the data memory 13) (S2 and S3 of Fig. 6). If YES, the address with the next line number of the address setting table TA is subjected to comparison in the same manner as described above (S4 of Fig. 6). When any signal has a logic level in the address setting table TA different from that of the actual signal, the logic level of this signal in the address setting table TA is updated to that of the corresponding actual signal (S5 of Fig. 6). The MPU 10 searches for a line number which stores the last updated signal in the signal update storage table TB in the storage hold memory 14; if none exists, no last updated signal is stored in the signal update storage table TB, and line number 1 is selected. When the last updated signal is present there, the next line number is selected (S6, S7, S8 and S9 of Fig. 6). The corresponding address and the corresponding logic level are stored in the selected line number memory location in the address setting table TB (S10 of Fig. 6). A signal (e.g., a mark) representing the last updated signal is stored at this memory location. The previously assigned mark in the table is deleted (S11 of Fig. 6). A line number next to the currently selected line number of the address setting table TA is selected (S4 of Fig. 6), and the same operation (S2, S3, S4, S5,... of Fig. 6) as described above will be performed. The MPU 10 repeatedly performs the above processing every time one sequence control cycle is completed. As a result, the address setting table TA stores the logic levels of current signals at the set addresses. The signal update storage table TB stores an address order representing updating of the signals at the addresses of the address setting table TA, and the logic levels of the current signals. Since the memory capacity of the signal update storage table TB is limited and the signal update storage table TB is used in a circulatory manner, a mark is assigned to the address storing the last updated signal in the signal update storage table TB. The mark identifies the beginning of the updated address order. When the resultant contents of the signal update storage table TB are displayed on the display unit 16 or the like, the addresses at which the logic levels of the signals are updated, and an order of updating can be visually checked. Therefore, the operator can easily check for an address that should not have been updated (i.e. an element that should not have been operated), thereby simplifying failure check. A case will be described in which the machine is stopped in the feed hold state shown in Figs. 3A and 3B. Addresses 31.5, 24.5 and 102.5 associated with the feed hold circuit are set in the address setting table TA in accordance with the ladder diagram (Fig. 3B), as shown in Fig. 7. The feed hold button a is turned on(depress) / off(release) once. The MPU 10 checks the address setting table TA (S1 of Fig. 6). In this case, the logic level of the signal stored at address 31.5 with line number 1 of the address setting table TA is set to "1". Since a normally closed contact is opened when the feed hold button a is turned on once, the relay represented at address 31.5 is turned off, so that the actual signal is set at logic level "0"; the logic level of the signal stored at address 31.5 in the address setting table TA is different from that of the actual signal (S2 and S3 of Fig. 6), so that the logic level of the signal stored at address 31.5 is updated to logic level "0"; and, as shown in Fig. 8, the signal update storage table TB stores address 31.5 and logic level "1" (S5, S6, S7, S8, S10 and S11 of Fig. 6). When the relay represented by address 31.5 is turned off, the contact a' is opened, and the feed hold relay SP is turned off. The logic level of the signal stored at the actual address 102.5 becomes "0" and is different from the logic level "1" of the signal stored in the address setting table TA; the logic level of the signal in the address setting table TA is updated to "0" (S3 and S5 of Fig. 6); and, as shown in Fig. 8, address 102.5 and the corresponding logic level "0" are stored in the signal update storage. table TB (S6, S7, S9, S10 and (S11) of Fig. 6). When the feed hold button a is turned off, the relay represented by address 31.5 is turned on, and the corresponding logic level becomes "1". The logic level of the signal in the table TB is different from that in the address setting table TA. In the same manner as described above, the logic level of the signal stored at address 31.5 of the address setting table TA is set to "1". At the same time, the same address and logic level as described above are stored with line number 3 in the signal update storage table TB in Fig. 8. Since the contact of the relay represented by address 31.5 becomes ON, the feed hold relay SP is turned on. The logic level of the actual signal at address 102.5 becomes "1" and is different from that in the address setting table TA. The logic level of the signal stored at address 102.5 of the address setting table TA is updated to logic "1". This address 102.5 is stored as an updated address with line number 4 of the signal update storage table TB. At the same time, the corresponding logic level "1" is also stored in the table TB. The last updated mark is changed from line number 3 to line number 4 of the signal update storage table TB (It should be noted that the mark has not been described in the preceding part of the specification, but that the mark has been actually relabeled from line number 1 to line number 2, line number 2 to line number 3 and line number 3 to line number 4 of the signal update storage table TB). In this state, when automatic operation is started, a signal update order at addresses 31.5, 24.5 and 102.5 and the corresponding logic levels are stored in the signal update storage table TB. When the machine is interrupted in the feed hold state during automatic operation, assume that the storage contents of the signal update storage table TB are displayed on the display unit 16, as shown in Fig. 8. In the storage contents of the signal update storage table TB in Fig. 8, the logic level of the signal at address 102.5 with line number 8 of the signal update storage table TB is updated last. The previously updated address is address 24.5 in line numbers 5 and 7 of the signal update storage table TB; the relay represented by address 24.5 is turned off/on once. This indicates that the pressure decrease detection switch b represented by address 24.5 is temporarily operated. As a result, the operator can determine that the failure is caused by temporary operation of the pressure decrease detection switch. In the above embodiment, the logic levels of the signals from the input and output circuits are stored in the data memory. However, the signals from the input and output signals need not be stored in the data memory. Addresses are assigned to the respective terminals of the input and output circuits. The logic levels of the signals may be read out from the data memory for storing the signals having logic levels representing the operating states of the terminals of the input and output circuits and the control relay in response to the address entered at the address setting means.

Claims: A sequence abnormality check system for a programmable controller, the programmable controller including a sequence program for controlling a machine tool in conjunction with control elements, each control element having an operational state given by a logic level of an actual signal, and having an associated address in the programmable controller; the system comprising:- first memory means for storing operational states of said elements; means for detecting changes in operational states of said elements; second memory means for storing operational states of one of said elements for which a change in operational state has been detected; and signal update writing means for writing into the second memory means an address and the new logic level of the actual operational state for each element having a changed operational state; characterised by:- address setting means (7) for entering the addresses of elements associated with an abnormality, so as to define a set of said elements in which the abnormality has occurred; an address setting table (TA), providing said first memory means, for storing addresses of said set of elements as defined by said address setting means (7) and for storing the operational states of the elements corresponding to the addresses; signal update detecting means (2), providing said means for detecting changes in operational states of said elements, responsive to the stored contents of the address setting table (TA) for generating an output when an operational state of an element stored in said address setting table (TA) is different from the logic level of the actual signal for that element when the sequence program is run subsequent to the address of that element being set in the address setting table (TA) by the address setting means (7); and a signal update storage table (TB), providing said second memory means; further characterised in that said signal update writing means (3) is operable to write into the signal update storage table (TB) a mark identifying that address which was last updated, and to update the operational states stored in the address setting table (TA) to correspond to the logic levels of the actual signals; and in that a display means (16) is operable, in response to the addresses of a set of elements being stored in said address setting table (TA), to display in sequential order the addresses stored in said signal update storage table (TB), together with the corresponding logic levels and said mark identifying the last updated address, thereby facilitating recognition of the element which has caused the abnormality. A system as claimed in claim 1, further including a memory (13), and wherein the address provided by said address setting means (7) comprises a memory address of the memory (13) for storing the operational state of the element corresponding to the address. A system as claimed in claim 1, further including a memory (13), input (4) and output (5) circuits and wherein the address provided by said address setting means (7) comprises memory addresses of the memory (13) for storing the operational state of the control elements and signals corresponding to a state of the input and output circuits (4, 5). A system as claimed in any preceding claim, wherein said system is operable repeatedly in a cycle together with sequence control.

Inventors: KUSUMI, KATSUAKI 35-102, GREEN HILL TERADA
Applicants: FANUC LTD.
Application year: 1984
Main classification: G05B23
IPC codes: G05B19, G05B23