PROCESS FOR THE CONTROLLED ETCHING OF TAPERED VIAS IN BOROSILICATE GLASS DIELECTRICS

Abstract: A process for forming via openings (60) in a relatively thick layer (50) of borosilicate glass while controlling the degree of taper of the side walls of the opening to be not less than 45° by (1) depositing a layer of silicon nitride that contains silicon in an amount in excess of stoichiometric in Si₃N₄, (2) densifying the silicon nitride layer, (3) depositing a layer of resist, (4) exposing and developing the layer of resist to define a desired pattern of openings in the borosili­ cate glass layer, (5) removing the exposed silicon nitride areas, and (6) subjecting the resultant exposed borosilicate glass surface to an etchant for the glass.

Description: Background of the Invention Field of the Invention The present invention relates to a process for the controlled etching of tapered vias (i.e. via holes) in borosilicate glass dielectrics. Description of the Prior Art It is known to use low temperature, low pressure plasma deposited silicon nitride layers as a mask in reactive ion etching (RIE) technology; however, the silicon nitride layer is used primarily as a mask and/or passivation layer to prevent oxidation and solder bridging between metallurgical lines over portions of the device reserved for active devices. Typically, some silicon nitride is removed prior to oxidation by reactive ion etching (RIE) which leaves a hole with essentially vertical side walls. Sloping side walls are avoided because of a "birds beak" problem, and the silicon nitride layer is not silicon rich and nitrogen deficient. IBM Technical Disclosure Bulletin, Vol. 24, No. 11A, April 1982, pages 5547 and 5548 discloses reactive ion etching of silicon nitride. Journal of Electro-Chemical Society, Vol. 127, No. 12, Dec 1980, pp. 2687-2693 with the title "Bilayer Typer Etching of Field Oxides and Passivation Layers" concerns a process for taper etching a PSG layer using a taper control mask layer. The taper control layer of a bilayer process minimizes the effect of the photoresist-oxide interface properties on the tapering process. Control of the taper is determined by the etch ratio of the underlying layer's etch rate to the taper control layer's etch rate. U.S. Patent 3,648,125 discloses the use of silicon nitride for diffusion masks and also for forming recessed isolation regions. U.S. Patent 4,053,351 discloses a method of chemically machining glass and single crystal, polycrystalline and amorphous forms of silica and like materials using acid fluoride etchants. U.S. Patent 4,247,361 discloses the use of a Teflon film as a masking element in semiconductor manufacture. U.S. Patent 4,299,862 discloses a process of etching windows in a glass coating where a precisely etchable silicon nitride coating can be initially applied and windows precisely etched therein. U.S. Patent 4,293,376 discloses a method for manufacturing a perforated glass plate for use in a gas discharge display by providing an etch-resistant coating on a glass plate and subjecting the thus coated glass plate to gaseous hydrofluoric acid. IBM Technical Disclosure Bulletin, Vol. 19, No. 8, January 1977, pages 3039 and 3040 and Vol. 25, No. 1, June 1982, pages 304 and 305 disclose, respectively, barrier layers for multilayer lift-off masks and electron beam mask writing at high exposure doses. It has been found that standard photoresist masking technology cannot be utilized to produce via-holes in multicomponent borosilicate glass layers of substantial thickness. The reason for this is that commonly used organic photoresists for semiconductor fabrication are not chemically durable enough to withstand the attack of etchants as are typically used for complete dissolution of borosilicate glass layers of substantial thicknesses, e.g., on the order of 10 µm. Although the patterned photoresist is not soluble in the etchants, it floats away from the borosilicate glass dielectric surface (because the HF is known to attack at the interface) in a short period of time, e.g., on the order of 45 seconds, when exposed to the etchant, allowing the borosilicate glass dielectric layer to be attacked in undesired areas, thereby creating pinholing problems and problems with undesired variations in borosilicate glass thickness, both of which could lead to electrical problems in the final thin film redistribution-metal fan-out lines on the glass-on-ceramic surface. As the resist is loosened as above, the side walls of the via holes become very tapered, i.e., the angle of the hole becomes very shallow because of excess undercutting of the resist, exceeding the preferred angle of about 45 o , and the taper is uncontrollable. Summary of the Invention In accordance with the present invention, as claimed, tapered vias can be etched in a thick glass dielectric, for example on the order of 10 micrometer thick, utilizing a plasma deposited nitrogen-deficient silicon nitride films as a masking material. One object of the present invention is to overcome problems with conventional organic photoresists which are not chemically durable enough to withstand the attack of etchants used for dissolution of a thick glass dielectric layer which leads to pinholing and undesirable thickness in the glass dielectric layer which can lead to electrical shorts in the final device. One further object of the present invention is to provide a process for etching via-holes in borosilicate glass where the side walls of the via holes are uniformly and controllably tapered, most preferably the taper being on the order of about 45 o , without substantial deviation along the via wall. Brief Description of the Drawing The Figure is a cross-sectional view illustrating, in simplified fashion, a ceramic substrate having vias therein which are metal-filled and having a borosilicate glass dielectric thereon through which the tapered vias of the present invention have been etched. Description of Preferred Embodiments The Dielectrics The present invention finds application to the etching of borosilicate glasses in general, most particularly with respect to multi-component borosilicate glass dielectrics as are used in the fabrication of semiconductor devices of any type. While not to be construed as limitative, typical borosilicate glasses which can be etched per the present invention comprise primarily SiO₂ and B₂O₃, typically on the order of 65 to 80 weight parts SiO₂, 20 to 35 weight parts B₂O₃, with up to about 20 weight parts conventional materials as are used in such glass compositions, e.g., one or more of Al₂O₃, Na₂O, K₂O, CaO, etc. A typical multi-component borosilicate glass composition per the present invention has the following composition (all parts are weight parts): SiO₂ 65.0 B₂O₃ 20.0 Al₂O₃ 6.0 Na₂O 3.0 K₂O 5.0 CaO 1.0 The borosilicate glasses can have varying thicknesses, but, most typically, the present invention finds application in the etching of thick glass layers, on the order of 10 µm up to 25 µm. Of course, the present invention can be applied to thinner borosilicate glasses, but, in such instances, conventional photoresist materials can be used, whereas the same cannot be used with thick borosilicate glasses. Borosilicate glass layers etched per the present invention can be formed in a conventional manner as will be appreciated by one skilled in the art. For example, one merely mixes the various desired oxides in the desired proportions and melts them at about 1000 o C to form the desired borosilicate glass, frits the same and forms a layer thereof by a conventional firing procedure. The Masking Material of the Present Invention The masking material of the present invention is a plasma deposited, nitrogen-deficient (and accordingly, silicon-rich) silicon nitride (hereafter often merely Si₃N₄) film. By nitrogen-deficient and silicon-rich is meant Si₃N₄ that contains silicon in an amount in excess of the stoichiometric amount in Si₃N₄. Usually, the amount of silicon (molar) is up to an Si/N molar ratio of 1.5. Hereafter when Si₃N₄ is referred to, unless otherwise indicated, it is meant to refer to the above nitrogen-deficient, silicon-rich Si₃N₄. While we investigated several inorganic materials as possible masks for etching relatively thick borosilicate glass dielectric layers, due to material processing parameters (heat treatment temperature, durability toward etchant and adhesion to glass and/or Si₃N₄) and incompatible thermal properties (the chemical vapor deposition (CVD) of Si₃N₄ is at a temperature which exceeds the glass transition temperature and a CVD deposited Si₃N₄ film having too low a refractive index, e.g., 1.5 - 2.0, is attacked very rapidly by etchant) between the potential masks and the borosilicate glass dielectric layer, we found that only plasma deposited, silicon-rich, nitrogen-poor Si₃N₄ which had been heat treated in a reducing atmosphere, and which exhibited a refractive index, after heat treatment, of from 2.3 to 2.8, most preferably about 2.5, was a suitable etch mask for borosilicate glass dielectrics. In this regard, standard plasma deposited Si₃N₄ films having a refractive index of equal to or less than 2.0 do not posses the required chemical durability to withstand etchant attack per the present invention. The Plasma Deposition Conditions The Si₃N₄ film of the present invention is formed by plasma deposition in essentially a conventional manner, except that the amount of silicon in the plasma deposition source is greater than stoichiometric with respect to the amount of nitrogen for Si₃N₄. It typically covers the entire surface of the borosilicate glass prior to via etching. Typical plasma deposition conditions are: temperature of about 300 o C; power of about 300 watts; deposition rate of about 30 nm/minute. These conditions can, of course, easily be modified by one skilled in the art using conventional techniques. Si₃N₄ Film Thickness The Si₃N₄ film thickness used for the present invention is not unduly limited. Obviously, the minimum thickness will be established by the particular etchant used and the thickness of the borosilicate glass at issue. Maximum Si₃N₄ film thickness is generally set upon a consideration of process steps, e.g., since reactive ion etching is used to form a via pattern in the Si₃N₄ film, excess thicknesses should be avoided since this will increase process costs due to the need for greater reactive ion etching times. Accordingly, for any particular application, typically the minimum Si₃N₄ film thickness acceptable will be used. Typical preferred Si₃N₄ film thicknesses are on the order of 250 to 450 nm. Greater or lesser thicknesses can be used so long as excessive microcracking is avoided. Heat Treatment to Densify the Si₃N₄ Film Per the present invention, the Si₃N₄ film is heat treated in a reducing atmosphere to densify the Si₃N₄ film. Typical as-deposited refractive indexes are on the order of 1.95 to 2.00, and typical final desired refractive indexes are 2.3 to 2.8, more preferably 2.45 to 2.8 and most preferably about 2.5. The heat treating conditions are not unduly limited to achieve the desired densification, and typically heating is at a temperature of from 500 o C to 535 o C for 2 hours to 2½ hours, generally in a reducing gas atmosphere such as, e.g., hydrogen, nitrogen, a nitrogen-hydrogen mixture, etc., and although heat treating can be in air, this is not preferred. Development of Via Pattern After formation of the Si₃N₄ film of the present invention and densification thereof, a photoresist layer, preferably a composite photoresist layer, is deposited on the silicon nitride film in a conventional manner, exposed through a mask and then developed in a conventional manner to define the via pattern. The term "composite photoresist layer" merely implies two layers of the same negative photoresist. A composite photoresist layer is preferably used because the photoresist is spin coated and it is difficult to sufficiently expose a single 4 µm thick, e.g., layer of photoresist. The photoresist is not limited in any substantial fashion and any conventional negative photoresist as is used in the art for protecting a surface during conventional reactive ion etching can be used in the present invention. The use of a composite photoresist layer or double-coated photoresist layer is beneficial because the same is extremely easy to expose and will reduce pin-holing and defects in the borosilicate dielectric glass layer. Typically, with a composite photoresist layer, the first layer of photoresist is spun on, exposed and developed, whereafter the second layer of photoresist is spun on and exposed and developed, insuring accurate alignment between the two photoresists. The thickness of the photoresist layer or the thickness of a composite photoresist layer is not unduly limited so long as the photoresist protects the Si₃N₄ film during reactive ion etching and during etching of the via holes in the borosilicate glass dielectric layer. Typical thicknesses for a single photoresist layer will be in the order from 1 µm to 2 µm. For a composite photoresist layer, the first photoresist layer will typically have a dry thickness on the order of 1.5 µm to 2 µm and the second (or overcoat) photoresist layer will have a dry thickness of from 2 µm to 2.5 µm. The above thicknesses are not to be construed as limitative, as one skilled in the art can easily determine useful photoresist layer thicknesses compatible with various reactive ion etching conditions and via hole etching conditions. Reactive Ion Etching Conditions Conventional reactive ion etching is used to etch the desired via pattern into the Si₃N₄ film of the present invention down to the surface of the borosilicate glass. The photoresist, of course, protects all other areas of the Si₃N₄ film from etching. Accordingly, reactive ion etching conditions are merely selected so that the Si₃N₄ film is etched and the photoresist is not removed. Typical conditions are: temperature, on the order of 95 to 100 o C, power about 100 watts, etching rate of about 28.5 nm/minute. As one skilled in the art will appreciate, the above conditions are not critical and can be freely modified in a conventional manner. Optional Photoresist Heat Treatment It is highly preferred that the photoresist, be it a single photoresist layer or a composite photoresist layer, be heat treated under vacuum to render the photoresist more resistant to the borosilicate glass etchant and to protect or cover possible pinholes in the Si₃N₄ film. As will be appreciated by one skilled in the art, baking a photoresist to increase the resistance thereof to chemicals and to essentially densify the same is a well known procedure in the art and conventional conditions can be used for this step of the present invention. Of course, the exact heating conditions will have to be tailored to any one particular photoresist, but such information is typically readily available from photoresist suppliers. For a single or composite photoresist layer per the present invention, typically heating is in a slight vacuum, e.g., on the order of 12.4 kPa to 13.8 kPa for about 30 minutes to 1.5 hours at a temperature on the order of 185 o C to 195 o C. The Wet Etchant and Etching Conditions The etchant used per the present invention can be freely selected from etchants as are used in the art to etch borosilicate dielectric glasses. Typical etchants include phosphoric acid and acetic acid based etchants, typically in combination with hydrofluoric acid and water. The present invention should not be construed as limited thereto, however. It is most preferred, however, that the etchant be a relatively rapid etchant for borosilicate glasses, as it is preferred that etching be conducted in a period from about 2 minutes to 5 minutes. Typically etching is conducted at a temperature of about 20 o C to 25 o C at normal pressure. During the etching step the Si₃N₄ adheres firmly to the borosilicate glass, but is slowly etched away, thereby enlarging the via openings. This etching away of the Si₃N₄ layer permits an additional area of the upper portion of the borosilicate glass layer to be exposed to the etchant which provides additional taper. The amount of additional exposed borosilicate glass is precisely controlled and governed by the Si₃N₄ layer. As one skilled in the art will appreciate, in wet etching undercutting will always take place; however, per the present invention the excellent adhesion of the Si₃N₄ to the borosilicate glass dielectric controls the undercutting in a precise fashion. Following etching, the device at this stage is rinsed, e.g., with deionized water, and then blow-dried with a suitable inert gas, e.g., nitrogen, argon, helium, etc., though clean air can also be used. As will be appreciated by one skilled in the art, the exact taper for the via holes through the borosilicate glass dielectric layer can be substantially varied. However, it is most preferred that the taper be in excess of 45 o , the same generally ranging from about 45 o to about 60 o . As shown in the Figure, the term "taper" as used herein refers to the angle α as shown in the Figure. α should be, as indicated, on the order of about 45 o to 60 o , more preferably 45 o to 50 o . If the angle is too low, the metal deposited in the vias will not adhere well thereto. On the other hand, if the angle α is too great, overlap can occur with adjacent vias or metallization lines, leading to shorting. With reference to the Figure, there is shown therein a ceramic substrate 10 which is shown provided with metal vias 20 which are, in turn, overcoated with a metallization pattern 30; also shown are metallization lines 40. Borosilicate glass layer 50 is also shown which has etched tapered via holes 60 provided with a metallization pattern 70 therein and metallization lines 80 thereon. The vias 20 may be Mo and the metallization Cr-Cu-Cr. Except for the tapered vias 60, the above represents a conventional device intermediate. As one skilled in the art will appreciate, various passivating layers, additional metal connections and the like can be provided in the manner which will be apparent to one skilled in the art. In accordance with the present invention, for example with a via hole 60 having a bottom diameter of 50 µm and a top diameter of up to 100 µm, in which case the metal 70 in the via hole would be about 5 µm deep, it is preferred that any pitting in the side of the via, i.e., any erosion near the side of the via, be no greater than 5 µm in depth to avoid any break in the continuity of the metal in the via; an excessively deep pit could lead to this break in the continuity of the metal in the via. It is the side wall 60A where pitting or erosion can create a problem and where taper must be substantially uniform, i.e., pits more than about 5 µm deep can lead to a continuity problem and should be avoided. Per the present invention, a controlled tapering angle is achieved, thus avoiding said problems. Secondary Processing Following processing as above, residual photoresist is removed in a conventional manner, e.g., by oxygen reactive ion etching, whereafter the Si₃N₄ film is removed using conventional reactive ion etching, e.g., in CF₄ down to the surface of the borosilicate glass. Etching is terminated using a conventional end point detector. Following processing as above, the device, with appropriately etched via holes in the borosilicate glass dielectric layer, can be subjected to various conventional treatments such as cleaning, filling of the via holes, application of metallization, for example, Cr-Cu-Cr metallization, etching away of the top Cr layer of the metallization, etc., all of which are conventional. Having thus generally described the invention, the following example is offered of the currently preferred best mode of practicing the invention. Example In this particular instance, a conventional 10 µm thick layer of borosilicate glass dielectric was formed in a conventional manner on a conventional two layer structure comprising an Al₂O₃ substrate having a metallization pattern of chromium-copper-chromium. The borosilicate glass dielectric layer had the following composition (all parts are weight parts): SiO₂ 65.0 B₂O₃ 20.0 Al₂O₃ 6.0 Na₂O 3.0 K₂O 5.0 CaO 1.0 It was formed by sedimenting the glass composition which was in the form of a frit having a particle size of about 8 µm and was then sintered in a hydrogen atmosphere at 820 o C for one hour. The surface of the glass was then planarized in a conventional fashion to render the same flat ± 2 µm. The borosilicate glass dielectric layer was then cleaned with a conventional neutral cleaning solution followed by ashing in an oxygen atmosphere in a manner conventional in the art. The nitrogen-deficient, silicon-rich Si₃N₄ layer was then plasma deposited onto the clean surface of the borosilicate glass dielectric layer. The Si₃N₄ layer had a thickness in the 400 to 500 nm range. It had a refractive index less than 2.3. Plasma deposition was conducted at about 300 o C, using a power of about 300 watts and at an Si₃N₄ deposition rate of about 30 nm/minute. After deposition of the Si₃N₄ layer, the assembly was introduced into a furnace and treated in a hydrogen atmosphere at approximately one atmosphere at 525 o C for two hours to densify the Si₃N₄ film. After densification the Si₃N₄ film exhibited a refractive index of 2.5. After removal from the furnace and cooling to room temperature, a composite (dual) layer of a conventional negative photoresist was spun on in a conventional manner. The upper and lower layers of the photoresist were the same and both layers had a dry thickness of 2 µm. Following each coating, the individual photoresist layers were exposed through an appropriate mask for the desired via pattern and developed in a conventional manner to remove the photoresist where the via holes are to be etched. The via hole "openings" in the photoresist had an initial diameter of about 50 µm. Next, a conventional reactive ion etching was conducted in CF₄ to etch the via pattern into the Si₃N₄ film down to the surface of the borosilicate glass dielectric. A conventional end point detector was used to terminate reactive ion etching. Reactive ion etching was at a temperature of 95-100 o C, a power of 100 watts and at an etch rate of 28.5 nm/minute. Following reactive ion etching, the device at this stage was heated in a vacuum furnace at a vacuum of 12.4-13.8 kPa at 185 to 195 o C for one-half hour to make the composite photoresist layer more resistant to the etchant and to cover possible pinholes in the Si₃N₄ film. Following the above heat treating and permitting the device to cool to room temperature, the via holes were etched in the borosilicate glass dielectric layer by immersing the same in the etchant comprising 35.3% HF, 23.5% glacial acetic acid, 41.2% H₂O. Etching was conducted at 24 o C for from 2.5-3.0 minutes, whereafter the device was removed from the etchant solution, rinsed in running deionized water for 5 minutes and then blow-dried with nitrogen. The via holes had a taper of 45 o , a diameter of 50 µm at the bottom of the via holes and 70 µm at the top of the via holes and showed no substantial pits or erosion. Following the above procedure, residual photoresist was removed by conventional reactive ion etching in an oxygen plasma and then the Si₃N₄ film was reactive ion etched away down to the surface of the borosilicate glass dielectric layer by a conventional CF₄ reactive ion etching. A conventional end point detector was used to determine when to terminate the reactive ion etching. Following the above described processing, the desired via holes were obtained in the borosilicate glass dielectric without any problem resulting from an unacceptable pinhole density. The device at this stage is ready for further conventional processing, as desired, e.g., deposition of conventional metallurgy in the tapered via holes, e.g., 5 µm of copper, etc.

Claims: A process for etching via-openings (60) in a relatively thick layer (50) of borosilicate glass while controlling the degree of taper of the side walls of the opening, the taper being uniform and not less than 45°, characterized by the following steps: depositing a layer of silicon nitride that contains silicon in an amount in excess of stoichoimetric in Si₃N₄, densifying the silicon nitride layer, wherein the refractive index of the densified silicon nitride layer is 2.3 to 2.8, depositing a layer of resist, exposing and developing the layer of resist to define a desired pattern of the bottom geometry of the openings in the borosilicate glass layer, removing the exposed silicon nitride areas, and subjecting the resultant exposed borosilicate glass surface to an etchant for the glass. The process of claim 1 wherein the taper is between 45° and 60°. The process of claim 2 wherein the taper is about 50°. The process of a previous claim wherein the refractive index of the densified silicon nitride layer is about 2.5. The process of a previous claim wherein the silicon-rich layer of silicon nitride is formed by plasma deposition and is densified by heat treatment in a reducing atmosphere. The process of a previous claim wherein the thickness of the borosilicate layer is from 10 to 25 µm, and the thickness of the silicon nitride layer is from 250 to 450 nm.

Inventors: POWELL, JIMMIE L., STANDLEY CHARLES L., SUIERVELD, JOHN
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1984
Main classification: H01L21
IPC codes: C03C15, H05K3, H01L21