SAMPLE AND HOLD CIRCUIT

Abstract: The sample and hold circuit includes a capacitor (C1) and first NPN and PNP transistors (Q10, Q12) for respectively controlling the charge and discharge of the capacitor (C1). The first NPN and PNP transistors (Q10, Q12) are fed with base currents from the second PNP and NPN transistors (Q14, Q18). The sample and hold circuit further includes a driving controller (38). The driving controller (38) periodically bypasses the base currents of the first NPN and PNP transistors (Q10, Q12).

Description: This invention relates to a sample and hold circuit for sampling a high frequency signal, for example, a video signal. Pulse code modulation (PCM) is now primarily used for the transmission of the video signal. In the PCM transmission, the video signal is sampled, quantitized, and coded. To sample a signal such as a video signal at high frequencies, a high speed sample and hold circuit is required. Fig. 1 shows a conventional high speed sample and hold circuit. The sample and hold circuit is provided with a capacitor 10 and a bridge circuit 12 for charging and discharging the capacitor 10. The bridge circuit 12 contains NPN transistors Q1 to Q4 of which the bases are connected to the collectors, respectively. A signal source 14 is connected to a junction of the emitter of the transistor Q1 and the collector of the transistor Q2. A junction between the emitter of the transistor Q3 and the collector of the transistor Q4 is connected to the capacitor 10. A constant voltage supply 16 is connected through a constant current source 18 to the collectors of the transistors Q1 and Q3. The emitters of the transistors Q2 and Q4 are grounded through the constant current source 20. The sample and hold circuit includes a pulse generator 22 for periodically generating first and second control pulses from first and second control terminals, and further includes NPN transistors Q5 and Q6. The first control pulse has an inverted relation to the second control pulse. The voltage at the first control terminal changes from a low to high level when the voltage at the second control terminal changes from a high to low level. The bases of the NPN transistors Q5 and Q6 are connected to the respective collectors of these transistors. With such a connection, those transistors serve as diodes. The first terminal of the pulse generator 22 is connected to the emitter of the NPN transistor Q5. The collector of the NPN transistor Q5 is connected to the collectors of the NPN transistors Q1 and Q3. The second control terminal of the pulse generator 22 is connected to the collector of the NPN transistor Q6. The emitter of the NPN transistor Q6 is connected to the emitters of the NPN transistors Q2 and Q4. In this sample and hold circuit, when the level of the voltages V1 and V2 at the first and second control terminals of the pulse generator 22 are low and high, respectively, the voltage of the input signal is held. When the voltages V1 and V2 are high and low, respectively, the input signal voltage is sampled. When the sample and hold circuit is in a holding mode, for example, a constant current I1 derived from the constant current circuit 18 flows into the first control terminal of the pulse generator 22 through the NPN transistor Q5. On the other hand, a constant current I2 is fed from the second control terminal of the pulse generator 22 into the constant current source 20. At this time, the transistors Q3 and Q4 are nonconductive. Accordingly, the voltage across the capacitor 10 is kept constant without regard to the input signal VIN. A relationship between the input signal VIN and the output signal VOUT will be described by referring to Fig. 2. The output signal VOUT corresponds to the voltage VC1 across the capacitor 10. In Fig. 2, VX designates a voltage difference between the input signal VIN and the output signal VOUT. In Fig. 2, the voltages V1 and V2 at the first and second terminals of the pulse generator 22 are inverted at time To. When the voltage V1 increases above the voltage VC1 across the capacitor 10 and, moreover, the voltage V2 drops below the input signal VIN, the transistors Q5 and Q6 prohibit the current from flowing through the transistors per se. As a result, the constant current I1 from the constant current source 18 flows through the NPN transistor Q3. At the same time, the constant current I2 is supplied from the signal source 14 to the constant current source 20 through the NPN transistor Q2. At this time, no current flows into the transistors Q1 and Q4. Therefore, the capacitor 10 is charged by the constant current I1 irrespective of the input signal VIN, i.e., voltage from the signal source 14. Through this charging, the voltage across the capacitor 10 increases at a fixed rate. The voltage difference VX becomes smaller than a predetermined threshold voltage V of the bridge circuit 12 at time T2. At this time, the transistors Q1 and Q4 are both conductive, and the capacitor 10 is charged by a nonlinearly changing current. A change of current corresponds to a time constant as determined by a capacitance of the capacitor 10 and an impedance of the bridge circuit 12. In Fig. 2, TC1 designates a charge/discharge time by the constant current; TC2, a charge/discharge time by the current as defined by the time-constant. As described above, the two types of modes are present in the charge/discharge of the capacitor 10. For this reason, the conventional sample and hold circuit is unsatisfactory in reliability when it operates in a high speed operation. Specifically, in the sample and hold circuit, when an amplitude of the input signal VIN is large, the constant currents I1 and I2 must be set at large values. Otherwise, it takes a long time for the output signal VOUT to reach the input signal. As a result, the response characteristic is poor. In this condition, it is very difficult to sample a signal such as the video signal in the high frequency band. Prior art document US-A-3 412 263 discloses a derivative circuit in which constant current gating pulses are used for shifting sample and hold operations to each other. In this derivative circuit four transistors are connected between an input and an output, and the gating pulses are applied to nodes between the emitters of first and second transistors and the bases of third and fourth transistors, respectively. The bases of the first and second transistors are connected to the input, and the emitters of the third and fourth transistors are connected to the output, respectively. Further, a capacitor is provided between the output and ground potential. Further, prior art document US-A-3 471 719 describes a gated filter and sample hold circuit. This circuit is operable as either a gated filter wherein the gating signal controls the response time of the filter, or a sample hold to hold the last voltage level applied thereto. When the gating signal is at a low potential, the circuit charges and discharges through a small resistor yielding a fast filter response time. When the gating signal is at a high potential, the circuit charges and discharges through a large resistor yielding a slow filter response time. If the resistor through which the filter charges is removed from the circuit, the response time approaches infinity and a sample hold circuit results. Prior art document IEEE TRANSACTIONS ON COMMUNICATIONS, Volume COM-22, No. 7, July 1974, pages 986-994, New York, US; G.M. BENSON: "Thin-film auto-balance diode gate for voice-band sample and hold and resampler circuits", discloses a thin-film hybrid integrated circuit auto-balanced diode transmission gate used in a voice-band pulse-code modulation terminal. The gate circuit is designed for sample and hold and resampler operations prior to digitalization and after decoding. The diode quad gate is switched by a current routing emitter-coupled transistor pair. The diodes are effectively current switched, resulting in extremely low distortion of the signal samples. Finally, prior art document MIT Lincoln Laboratory Technical Report No. 300, January 30, 1963, R.H. BAKER et al.: "The Diamond Circuit", discloses a circuit arrangement for developing a pulsed gate current required by a diamond circuit as shown in document US-A-3 412 263. In this circuit high collector impedances of a first pair of transistors supply a very nearly constant gate current. A second pair of transistors form "pull-back" transistors, used to ensure that the gate currents into and out of the diamond circuit are of equal duration and simultaneous cutoff. The pull-back transistors are not necessary to the operation of the diamond circuit itself. However, they vastly improve the voltage waveform at the gate inputs and serve to reduce substantially the offset uncertainty due to unequal current fall times. It is an object of the present invention to provide a sample and hold circuit operable at a high speed with high reliability. To solve this object the present invention provides a sample and hold circuit as stated in claim 1. According to the present invention, the charge and discharge currents are not limited to a fixed value, but change a time constant as specified by an impedance of the current path and a capacitance of the capacitor. Therefore, the sample and hold circuit is operable at a high speed with satisfactory reliabiltiy. Thus, according to the present invention, it is possible to sample a high frequency signal such as a video signal. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a conventional sample and hold circuit; Fig. 2 is a graph for illustrating the operation of the sample and hold circuit of Fig. 1; Fig. 3 is a circuit diagram of a sample and hold circuit which is an embodiment of the present invention; Fig. 4 is a graph illustrating a charge/discharge characteristic of the capacitor when the sample and hold circuit is in a sampling mode; and Fig. 5 shows a charge/discharge characteristic of the output capacitor when the sample and hold circuit of Fig. 3 is in a holding operation. An embodiment of a sample and hold circuit according to the present invention will be described referring to Figs. 3 to 5. The sample and hold circuit contains a capacitor C1 and NPN and PNP transistors Q10 and Q12 for controlling the charge and discharge of the capacitor C1. The capacitor C1 is connected between an output terminal OUT and ground. The output terminal OUT is connected to the emitters of the transistors Q10 and Q12. The collector of the NPN transistor Q10 is connected to a constant voltage supply 30, and the collector of the PNP transistor Q12 is grounded. The sample and hold circuit contains PNP and NPN transistors Q14 and Q16 for driving the transistors Q10 and Q12 according to the voltage of a signal source 32. The emitter of the PNP transistor Q14 is connected to a constant voltage supply 30 through a constant current source 34, and a base of the NPN transistor Q10. The collector of the PNP transistor Q14 is grounded. The emitter of the NPN transistor Q16 is also grounded through a constant current source 36 and connected to the base of the PNP transistor Q12. The collector of the NPN transistor Q16 is connected to the constant voltage supply 30. The voltage of the signal source 32 is supplied to the bases of the PNP and NPN transistors Q14 and Q16. The sample and hold circuit includes a drive controller 38 to provide a bypath for the drive currents of the transistors Q10 and Q12. The drive controller 38 includes a pulse generator 40 for generating first and second control pulses at the first and second output ends and, additionally, NPN transistors Q18 and Q20 serving as diodes. The first and second control pulses are related with each other in an inverted fashion and are periodically generated to sample a voltage of the signal source 32. The emitter of the PNP transistor Q14 is connected to the base and the collector of the NPN transistor Q18. The emitter of the NPN transistor Q18 is connected to the first output end of the pulse generator 40. The second output end of the pulse generator 40 is connected to the base and the collector of the NPN transistor Q20, and the emitter of the NPN transistor Q20 is connected to the emitter of the NPN transistor Q16. The operation of the sample and hold circuit thus arranged will be described. For example, during the period that the pulse generator 40 does not produce the first and second control pulses, the voltages V1 and V2 at the first and second output ends of the pulse generator 40 are at ground level (e.g. 0 V) and high level (e.g., 5 V), respectively. At this time, the constant current I1 from the constant current source 34 barely flows through the PNP transistor Q14, but flows mostly through the PNP transistor Q18. The constant current I2 from the constant current source 36 barely flows through the NPN transistor Q16, but flows mostly through the NPN transistor Q20. Therefore, the base currents are not fed to the NPN and PNP transistors Q10 and Q12, so that these transistors Q10 and Q12 are both kept nonconductive. Accordingly, the capacitor C1 is neither charged nor discharged, so that the voltage across the capacitor C1 is kept constant. When the pulse generator 40 generates first and second control pulses, the voltages V1 and V2 at the first and second output ends are set at high level and ground level, respectively. At this time, the constant current I1 from the constant current source 34 barely flows through the NPN transistor Q18, but flows mostly through the PNP transistor Q14. The constant current I2 from the constant current source 36 barely flows through the NPN transistor Q20, but flows mostly through the NPN transistor Q16. Predetermined base currents are fed as bias currents to the NPN transistors Q10 and Q12. When the voltage VC1 across the capacitor C1 is lower than the voltage VI of the signal source 32, voltage is generated across the base-emitter path of the NPN transistor Q10. Then, the charge current IC flows from the constant voltage supply 30 into the capacitor C1, via the NPN transistor Q10, till the emitter voltage of the NPN transistor Q10 is equal to the base voltage of the PNP transistor Q14, i.e., the output voltage of the signal source 32. Since little resistance is present in the path of the charge current IC, the charging speed of the capacitor C1 is very high. When the voltage VC1 across the capacitor C1 is higher than the voltage VI, voltage is generated between the base and emitter of the PNP transistor Q12. Then, the discharge current ID flows from the capacitor C1 to ground via the PNP transistor Q12, till the voltage VC1 across the capacitor C1 is equal to the output voltage of the signal source 32. Since little resistance is present in the path of the discharge current ID, the discharge speed of the capacitor C1 is also very high. In the sample and hold circuit, the charge/discharge current flows not through a constant current source. Therefore, it is not kept at a constant value and changes depending on time. The changing rate of the charge/discharge and current depend on a time constant determined by the capacitance of the capacitor C1 and the impedance of parallel connection of the emitters of the NPN and PNP transistors Q10 and Q12 (e.g., 1/2 x emitter impedance of NPN transistor). In this embodiment, the NPN and PNP transistors Q10 and Q12 are complementarily coupled with each other to self-feed back the voltage of the output terminal OUT. The result of a SPICE simulation of the present embodiment will be comparatively described to conventional embodiments, referring to Figs. 4 and 5. In this circuit, the constant current I1 = I2 = 1 mA, the power supply voltage VE = 5 V, and the capacitance C1 = 100 pF. In the figure, symbol A designates a voltage variation of the input signal; B, a variation of an output signal of a conventional sample and hold circuit; and C, a variation of an output signal of the present embodiment. Fig. 4 shows a charge/discharge characteristic of the capacitor C1 when the sample and hold circuit operates in a sampling mode. During measurement of this characteristic, the NPN transistors Q18 and Q20 were kept in an off state. As seen from the figure, the conventional sample and hold circuit needs 100 ns till it produces an output signal in response to the input signal. In the sample and hold circuit according to the present invention, a much shorter period of time is required than the 100 ns. The output signal of the sample and hold circuit follows a transition of the input signal with satisfactory accuracy. Fig. 5 illustrates a charge and discharge characteristic of the capacitor C1 when the sample and hold circuit operates in a holding mode. For the measurement of this characteristic, the NPN transistors Q10 and Q12 were switched to an ON state at time T1. In the conventional sample and hold circuit, the voltage of the output signal drops to approximately 9 mV through this switching. On the other hand, in the present embodiment, the voltage of the output signal drops only 6 mV. The response speed of this embodiment is higher than the conventional one. As seen from the foregoing description, in this embodiment, the charge/discharge current of the capacitor C1 changes along a characteristic curve, determined by a time constant, without being limited to a specific value. In the sample and hold circuit, the time constant is smaller than that of the conventional one. The output signal of the circuit, when it is accurately operating in a sampling mode, follows a change of the input signal. In this respect, the sample and hold circuit operates with high reliability. Accordingly, the sample and hold circuit is suitable for the sampling of the high frequency signal such as the video signal. In this case, the pulse generator is set so as to generate first and second control pulses at high frequencies. According to the present invention, a high frequency input signal can be sampled at a high speed, and the output signal accurately corresponds to the input signal.

Claims: A sample and hold circuit comprising: input and output terminals (IN, OUT); first and second power source terminals; capacitive means (C1) connected between said output terminal (OUT) and said second power source terminal; a first transistor (Q10) of one conductivity type which has a collector connected to said first power source terminal and an emitter connected to said output terminal (OUT); a second transistor (Q12) of the opposite conductivity type which has an emitter connected to said output terminal (OUT), a third transistor (Q14) of the opposite conductivity type which has a base connected to said input terminal (IN), and an emitter connected to a base of said first transistor (Q10); a fourth transistor (Q16) of the one conductivity type which has a base connected to said input terminal (IN), a collector connected to said first power source terminal, and an emitter connected to a base of said second transistor (Q12); and a driving control circuit (38) including mode setting means (40) for selectively setting sampling and holding modes and current control means (Q18, Q20) to inhibit flow of the respective base currents of said first and second transistors (Q10, Q12) in the holding mode and to permit flow of the respective base currents of said first and second transistors (Q10, Q12) in the sampling mode; characterized in that said mode setting means includes an voltage generating circuit (40) which generates a first voltage (V1) at a high level and a second voltage (V2) at a low level from respective first and second control terminals during the sampling mode and generates the first voltage (V1) at a low level and the second voltage (V2) at a high level from the respective first and second control terminals during the holding mode, said current control means includes first and second switching means (Q18, Q20), said first switching means (Q18) is connected between said first control terminal und the base of said first transistor (Q10), and said second switching means (Q20) is connected between said second control terminal and the base of said second transistor (Q12), a first constant current source (34) is connected between said first power source terminal and a connection point of the base of said first transistor (Q10), said first switching means (Q18), and the emitter of said third transistor (Q14), and a second constant current source (36) is connected between said second power source terminal and a connection point of the base of said second transistor (Q12), said second switching means (Q20) and the emitter of said fourth transistor (Q16), for permitting current to flow in a first direction from said first constant current source (34) to said first control terminal in the holding mode und preventing the flow of current in the first direction in the sampling mode, and for permitting current to flow in a second direction from said second control terminal to said second constant current source (36) in the holding mode and preventing the flow of current in the second direction in the sampling mode, and the collectors of said second and third transistors (Q12, Q14) are connected to said second power source terminal, respectively. A sample and hold circuit according to claim 1, characterized in that said first and fourth transistors (Q10, Q16) are NPN transistors, and said second and third transistors (Q12, Q14) are PNP transistors. A sample and hold circuit according to claim 1 or 2, characterized in that said voltage generating circuit is a pulse generator (40) in which said first and second voltages (V1, V2) are simultaneously and periodically inverted in level to alternate sampling and holding modes. A sample and hold circuit according to claim 3, characterized in that said first and second switching means (Q18, Q20) are NPN transistors, the NPN transistor (Q18) of said first switching means has a collector connected to the base of said first transistor (Q10), an emitter connected to said first control terminal, and a base connected to the collector thereof, and the NPN transistor of said second switching means (Q20) has an emitter connected to the base of said second transistor (Q12), a collector connected to said second control terminal, and a base connected to the collector thereof.

Inventors: SUGIMOTO, YASUHIRO C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1984
Main classification: G11C27
IPC codes: H03K17, G11C27