SEMICONDUCTOR DEVICE COMPRISING A DMOSFET

Abstract: A semiconductor device is disclosed in which the anode and cathode of a diode (D3) are connected respectively to the source (S) and drain (D) of the MOSFET (QM1). The diode (D3) has a set forward voltage drop lower than that of a parasitic diode (D1) formed by the junction between a channel base region (14a, 14b) and a drain region (12) constituting the MOSFET (QM1).

Description: Semiconductor device This invention relates to semiconductor deie such as power MOSFETs (metal-oxide-semiconductor iel effect transistors) used for such purposes as motor control and power control. The power MOSFETs of the type noted generally handle large currents and high voltages. They are of various structures, e.g., a double diffusion type MOS (hereinafter referred to as D MOS), a V MOS or a U MOS. Fig. 1 typically shows the sectional structure of a D MOSFET. It comprises an N+-type high impurity concentration silicon substrate 11, on one surface of which is formed an N -type low impurity concentration silicon epitaxial layer 12. The high impurity concentration silicon substrate 11 and low impurity concentration silicon epitaxial layer 12 constitute a drain region of a MOSFET. A drain electrode 13 is formed on the other surface of the substrate 11 The low impurity concentration silicon epitaxial layer 12 has P-type impurity diffusion regions 14a anc 14b for@@@ at a predetermined distance from each other as a base region of the channel of the MOSFET. N+-type impurity diffusion regions 15a and 15b are formed in the respective regions 14a and 14b as a source region of. the MOSFET. A gate insulation film 16 is formed on the impurity concentration silicon epitaxial layer 12 such that it covers part of the surface of the impurity diffusion regions 14a, 14b, 15a and 15b. A gate electrode layer 17 is formed on the gate insulation film 16. An insulation film 18 is formed on the gate electrode layer 17, and a source electrode layer 19 is formed on the insulation film 18. The source electrode layer 19 is contiguous to part of the impurity diffusion regions 14a and 14b (i.e., channel base regions) and impurity diffusion regions 15a and 15b (i.e., source regions). Fig. 1 shows some D MOSFETs which are formed continuously in a row. Fig. 2 shows an equivalent circuit of the structure described above. The drain D of MOSFET QM1 is constituted by the high impurity concentration silicon substrate 11 and low impurity concentration silicon epitaxial layer 12. The source S of the MOSFET is constituted by the N-type impurity diffusion regions 15a and 15b. The gate electrode G of the MOSFET is constituted by the gate electrode layer 17. A resistor RB is constituted by the resistance of the impurity diffusion regions 14a and 14b. The circuit also comprises an NPN bipolar transistor QB1. The emitter of transistor QB1 is constituted by the N -type impurity diffusion regions 15 and 15b, the base of the transistor is constituted by the P-type impurity diffusion regions 14a and 14b, and the collector of the transistor is constituted by the N -type low impurity concentration silicon epitaxial layer 12. The circuit further comprises a diode Dl. The anode of the diode D1 is constituted by the P-type impurity diffusion regions 14a and 14b. The cathode of the diode is constituted by the N -type silicon epitaxial layer 12. The bipolar transistor QB1 and diode D1 are formed parasitically. The equivalent circuit shown in Fig. 2 applies to other MOSFET structures (i.e., V MOSFETs and U MOSFETs) as well. Fig. 3 shows a motor control cirucit, in which power MOSFETs are used. The circuit uses two MOSFETs QM1 and QM2 which are serially connected between positive and negative power supply terminals. A winding L of the motor is connected between the point of connection between the MOSFETs QML and QM2 and positive power supply terminal. The MOSFETs QM1 and QM2 are selectively on-off controlled according to control signals CS1 and CS2, whereby the winding L is energized. Although not shown, the circuit as described above is provided for each winding of the motor, and the rotation of the motor is controlled according to the state of excitation state of each winding. In this circuit, when the MOSFET QM2 is on while the MOSFET QM1 is off, a current path is formed from the positive power supply terminal through the winding L and MOSFET QM2 to the negative power supply terminal. Thus, a current IL flows through the winding L, and a current IT flows through the MOSFET QM2. When MOSFET QM2 is off, a freewheel current ID flows through the diode D1. While the diode D1 is carrying the forward current ID, carriers are being stored in the cathode region (i.e., the N -type silicon epitaxial layer) 12 shown in Fig. 1. At the time of the transition of the MOSFET QM2 from the off state to the on state, the stored carriers are led from the cathode resion 12 through the anode region (i.e., through the P-type impurity diffusion regions 14a and 14b) to the source electrode layer 19. This constitutes a reverse recovery current IR as shown in Fig. 4. The current IR causes a voltage drop across the resistance RB of the channel base region (i.e., P-type impurity diffusion regions 14a and 14b) under the impurity diffusion regions 15a and 15b. As a result, the base-emitter path of the parasitic bipolar transistor QB1 is forwardly biased, thus turning on the transistor QB1. When the transistor QB1 is turned on, a current concentration is produced under the N-type impurity diffusion regions 15a and 15b which elevates the temperature of the immediate surroundings and, in the extreme case, which can cause a rupture of the MOSFET. An object of the invention is to provide a semiconductor device, which is free from rupture due to the structure of the MOSFET, and which can operate with greater speed and efficiency. According to one form of the invention, there is provided a semiconductor device, which comprises a MOSFET having a source, drain, gate and channel base region, and a diode having the anode and cathode connected respectively to the source and drain of the MOSFET and having a set forward voltage drop which is lower than that across a parasitic diode formed by the junction between the channel base region and drain region of the MOSFET. With this structure, the forward current that flows through the parasitic diode (formed by the junction between the channel base region and drain region of the MOSFET) is branched through the diode to reduce stored carriers, thus preventing the parasitic bipolar transistor from acting and freeing it from rupture in the freewheel operation. In addition, the reverse recovery time of the diode connected between the source and drain of the MOSFET may be set to be shorter than the reverse recovery time of the parasitic diode, thus reducing the speed of the operation as a freewheel diode and reducing the power loss, i.e., increasing efficiency. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a fragmentary enlarged-scale sectional view showing a prior art power MOSFET; Fig. 2 is a circuit diagram showing an equivalent circuit of the MOSFET shown in Fig. 1; Fig. 3 is a circuit diagram showing an arrangement, in which the power MOSFET shown in Figs. 1 and 2 is used for a motor control circuit; Fig. 4 is a graph for explaining the operation of the circuit shown in Fig. 3; Fig. 5 is a view similar to Fig. 1 but showing an embodiment of the semiconductor device according to the invention; Fig. 6 is a circuit diagram showing an equivalent circuit of the embodiment shown in Fig. 5; and Figs. 7 through 11 are views similar to Fig. 5 showing different examples of MOSFET according to the invention. Figs. 5 and 6 are respectively a fragmentary enlarged-scale sectional view and an equivalent circuit diagram of an embodiment of the invention applied to a power MOSFET. In the figures, the same parts as those in Figs. 1 and 2 are designated by like reference numerals. In this instance, a diode D3 has its anode and cathode connected to the source and drain of the MOSFET QM1, respectively. The illustrated power MOSFET comprises an N+-type high impurity concentration silicon substrate 11, on one surface of which is formed an N -type low impurity concentration silicon epitaxial layer 12. The high impurity concentration silicon substrate 11 and low impurity concentration silicon epitaxial layer 12 constitute a drain region of a MOSFET. A drain electrode 13 is formed on the other surface of the substrate 11. The N -type low impurity concentration silicon epitaxial layer 12 has P-type impurity diffusion regions 14a and 14b formed at a predetermined distance from each other, which constitute the channel base region of the MOSFET. The P-type impurity diffusion regions 14a and 14b are formed by diffusing a P-type impurity, e.g., boron. The N -type low impurity concentration silicon epitaxial layer 12 also has a P-type impurity diffusion region 20 which is formed at a predetermined distance form the impurity diffusion regions 14a and 14b (via the adjacent MOSFET). The P-type impurity diffusion region 20 serves as an anode region of diode D3. The surface impurity concentration diffusion regions 14a and 14b is set to be about 1 x 1018 cm 3, 3for instance. The surface impurity concentration diffusion region 20 is set to be about 1 x 1019 to 1 x 1020 cm 3. The impurity diffusion region 20 and silicon epitaxial layer 12 constitute the diode D3. The impurity diffusion regions 14a and 14b have respective N -type impurity diffusion regions 15a and 15b which serve as a source region of the MOSFET. The N -type impurity diffusion regions 15a and 15b are formed by diffusing an N-type impurity, e.g., phosphorus or arsenic. A gate insulation film 16 is formed on the low impurity concentration silicon epitaxial layer 12 such that it covers part of the surface of the impurity diffusion regions 14a, 14b, 15a and 15b. A gate electrode layer 17 is formed on the gate insulation layer 16. An inter-electrode insulation film 18 is formed on the gate electrode layer 17. A source electrode 19 is formed on the interelectrode insulation film 18. The source electrode 19 is contiguous to part of the impurity diffusion regions 14a and 14b (i.e., channel base regions of the MOSFET), impurity diffusion regions 15a and 15b (i.e., source region of the MOSFET) and impurity diffusion region 20 (i.e., anode region of the diode D3). The forward voltage drop VF3 of the diode D3 is set to be lower than the forward voltage drop VF1 of the parasitic diode D1 constituted by the P-type impurity diffusion regions 14a and 14b and N-type epitaxial layer 12. The difference between the forward voltage drops VF3 and VFl is suitably about 0.4 V when the forward current IF is 15 A, for instance, and it is determined by the impurity concentrations of the impurity diffusion regions 14a, 14b and 20. With the structure as described, the forward current IF is branched between the parasitic diode Dl and diode D3, as shown in the equivalent circuit diagram of Fig. 6; it is the sum of the forward currents IF1 and 1F3 through the respective diodes D1 and D3. In other words, the forward current IF1 through the parasitic diode D1 is reduced by the diode D3 when the forward curent IF is fixed. The reverse recovery curent IR1 due to the parasitic diode D1 is thus reduced to reduce the forward vias voltage on the parasitic bipolar transistor QB1 that appears across the base resistance RB, thus preventing the action of the transistor QB1. In particular, the forward voltage drops v and VF3 across the respective diodes D1 and D3 are set such that: VF1 > VF3 to obtain IF1 IF3 so as to permit a great reduction in the carriers stored in the cathode region of the diode D1 (i.e., in the N -type silicon epitaxial layer 12). It is thus possible to prevent rupture of the MOSFET element and to greatly improve the reverse breakdown voltage thereof. Further, by setting the reverse recovery time trr3 of the diode D3 to be shorter than the reverse recovery time trrl of the parasitic diode D1 while having the relation V > VF3 between the forward voltage drops V and VF3 of the diodes D1 and D3, the reverse recovery current 1R and reverse recovery time trr at the time of the freewheel diode operation can be reduced. It is thus possible to realize a great increase in the speed of the switching operation of the MOSFET and to save power, thus increasing efficiency. The forward voltage drops V and VF3 can be suitably set by appropriately setting the difference between the contact resistance of the impurity diffusion regions 14a and 14b and that of the impurity diffusion region 20, the resistance of these regions depending on the impurity concentration thereof. For example, the forward voltage drop VF1 of the diode D1 can be varied by selectively forming barrier layers 10a and 10b of titanium, doped polysilicon, molybdenum silicide, titanium nitride, etc., as shown in Fig. 7. As for setting the reverse recovery times trrl and trr3, the carrier lifetime in the diode D3 may be solely changed by selectively diffusing a lifetime killer, e.g., platinum or gold, in the impurity diffusion region 20 and by surrounding portions of the low impurity concentration silicon epitaxial layer 12, thereby obtaining the best characteristics (i.e., reverse recovery times trrl and trr3) of the MOSFET QM1 and diode D3. Fig. 8 shows a different embodiment of the invention. In this instance, the gate electrode layer 17, gate insulation film 16 and impurity diffusion region 15 adjacent to the MOSFET shown in Fig. 5 are partly omitted. In Fig. 8, the same parts as those in Fig. 5 are designated by like reference numerals. Even with this structure, the equivalent circuit is as in Fig. 6, and the same results as discussed above in connection with the preceding examples can be obtained. Fig. 9 shows a further embodiment of the invention. While in the above examples the MOSFET QM1 and diode D3 are spaced-apart from each other, in this instance the anode region of diode D3 (i.e., P-type impurity region 20) is formed such that it is contiguous to the channel base region of MOSFET QM1 (i.e., P-type impurity diffusion region 14a). On one surface of the N+-type high impurity concentration silicon substrate 11 is formed an N -type low impurity concentration silicon epitaxial layer 12. The high impurity concentration silicon substrate 11 and low impurity concentration silicon epitaxial layer 12 form the drain region of the MOSFET. A drain electrode 13 is formed on the other surface of the high impurity concentration silicon substrate 11. The low impurity concentration silicon epitaxial layer 12 has P-type impurity diffusion regions 14a and 14b formed at a predetermined distance from each other as the channel base region of the MOSFET. The silicon epitaxial layer 12 also has a P-type impurity diffusion region 20 formed contiguous to the impurity diffusion region 14a as the anode of diode D3. The impurity diffusion regions 14a and 14b have respectively N-type impurity diffusion regions 15a and 15b serving as the source region of the MOSFET. A gate insulation film 16 is formed on the low impurity concentration silicon epitaxial layer 12 such that it covers part of the surface of the impurity diffusion regions 14a, 14b, 15a and 15b. A gate electrode layer 17 is formed on the gate insulation film 16. Insulation film 18 is formed on the gate electrode layer 17. Source electrode layer' 19 is formed on the insulation film 18. The source electrode layer 19 is contiguous to the impurity diffusion regions 14a and 14b (constituting the channel base region of the MOSFET), impurity diffusion regions 15a and 15b (constituting the source region of the MOSFET) and impurity diffusion region 20 (constituting the anode region of the diode). With this structure again the equivalent circuit is as in Fig. 6, and the same results as in the preceding examples can be obtained. Further, the insulation film 1 shown in Fig. 9 may be omitted as shown in Fig. 10 to obtain the same results. With the structures shown in Figs. 8 to 10, the forward voltage drops may be set in the manner as described before in connection with the structure shown in Fig. 7. Further, while the above embodiments have concerned MOSFETs of an N-channel type, the invention is of course applicable to the P-type channel MOSFET as well. In this case, the polarity of the diode is reversed. Further, while the D MOSFETs have been described, the same results may also be obtained with MOSFETs of other structures such as a V MOSFET or a U MOSFET so long as a diode of the same polarity as the parasitic diode is connected in parallel between the source and drain of the MOSFET. Fig. 11 shows a further embodiment of the invention applied to a V MOSFET. On one surface of an N -type high impurity concentration silicon substrate 21 is formed an N -type low impurity concentration silicon epitaxial layer 22. A drain electrode 23 is formed on the other substrate surface. The low impurity concentration silicon epitaxial layer 22 has a P-type impurity diffusion region 24 and another P-type impurity diffusion region 29 formed at a predetermined distance from the region 24 and serving as an anode region of the diode. The impurity diffusion region 24 has N+-type impurity diffusion regions 25a and 25b. V-shaped grooves 30a and 30b are formed as shown in the impurity diffusion regions 25a and 25b and 24 by anisotropic etching. Gate electrodes 27 consisting of polysilicon are formed in the grooves 30a and 30b via a silicon oxide film 26. A source electrode 28 of aluminum is formed over the gate electrodes 27 via a silicon oxide film 26. The source electrode 28 extends to cover the P-type impurity diffusion region 29. The P-type impurity diffusion region 29 and N -type low impurity concentration epitaxial layer 22 constitute a diode. With the above structure, the same results can be obtained as with the D MOSFETs described before. In addition, the structure permits similar modifications. Moreover, the invention is applicable to four-layer elements having MOS structures other than the V MOSFET and U MOSFET.

Claims: Claims: 1. A semiconductor device having a MOSFET (QM1) having a source (S), a drain (D), a gate (G) and a channel base region (14a, 14b), characterized by a diode (D3) having an anode and a cathode between which current path of said MOSFET (QMl) is formed, said diode (D33 having a set forward voltage drop lower than that of a parasitic diode (D1) formed by the junction between said channel base region (14a, 14b) of said MOSFET and a source region (12) thereof. 2. A semiconductor device comprising a high impurity concentration semiconductor substrate (11) of a first conductivity type, a low impurity concentration epitaxial layer (12) formed on one surface of said semiconductor substrate (11), a drain electrode (13) formed on the other surface of said semiconductor substrate (11), a first and second channel base region (14a, 14b) of a second conductivity type formed at a predetermined distance from each other in said low impurity concentration epitaxial layer (12), a first and second high impurity concentration source region (15a, 15b) of the first conductivity type formed in said respective first and second channel base regions (14a, 14b), a gate oxide film (16) formed on said low impurity concentration epitaxial layer (12) between said first and second channel base regions (14a, 14b), a gate electrode (17) formed on said gate oxide film (16) and an insulation film (18) formed on said gate electrode (17), characterized by an impurity diffusion region (20) of the second conductivity type formed in said low impurity concentration epitaxial layer (12) and constituting a diode (D3), and a source electrode (19) formed on said insulation film (18), channel base regions (14a, ebb), source regions (15a, 15b) and a second conductivity type impurity diffusion region (20) constituting said diode. 3. The semiconductor device according to claim 2, characterized by burrier layers (10a, 10b) formed in contact areas between said first and second channel base regions (14a, 14b) and first and second source regions (15a, 15b) and said source region (19). 4. The semiconductor device according to claim 2, characterized in that said second conductivity type impurity diffusion region (20) constituting said diode (D3) is formed at a predetermined distance from said first and second channel base regions (14a, 14b) and that an insulation film (18) is formed on said low impurity concentration epitaxial layer (12) between said channel base region (14a) and impurity diffusion region (20). 5. The semiconductor device according to claim 2, characterized in that said second conductivity type impurity diffusion region (20) is formed at a predetermined distance from said first and second channel base regions (14a, 14b) and that said semiconductor device further comprises a gate oxide film of a MOSFET formed on said low impurity concentration epitaxial layer (12) between a channel base region (14a) and impurity diffusion region (20), a gate electrode formed on said gate oxide film, an insulation film formed on said gate electrode, and a high impurity concentration source region of the first conductivity type of said MOSFET formed in said first channel base region (14a). 6. The semiconductor device according to claim 2, characterized in that said first channel base region (14a) and second conductivity impurity diffusion region (20) constituting said diode (D3) are contiguous to each other. 7. The semiconductor device according to claim 2, characterized in that said first channel base region (14a) and second conductivity type impurity diffusion region (20) constituting said diode (D3) are contiguous to each other and an insulation layer is formed on said low impurity concentration epitaxial layer (12) between said channel base region (14a) and impurity diffusion region (20). 8. The semiconductor device according to claim 2, characterized in that the impurity concentration of said second conductivity type impurity diffusion region (20) constituting said diode (D3) is higher than the impurity concentration of said first and second channel base regions (14a, 14b). 9. The semiconductor device according to claim 2, characterized in that said gate electrode (17, 27) is formed in a V-shaped groove formed in said low impurity concentration epitaxial layer (12, 22). 10. The semiconductor device according to claim 2, characterized in that a lifetime killer is selectively diffused in said impurity diffusion region (20) constituting said diode (D3) and a surrounding portion of said low impurity concentration silicon epitaxial layer (12).

Inventors: MIWA, YUKIHARU C/O PATENT DIV. K.K. TOSHIBA, NAKAYAMA, YOSHIHITO C/O PATENT DIV. K.K. TOSHIBA, OHATA, YU C/O PATENT DIV. K.K. TOSHIBA, SUZUKI, KAZUAKI C/O PATENT DIV. K.K. TOSHIBA, TANABE, HIROHITO C/O PATENT DIV. K.K. TOSHIBA
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1984
Main classification: H01L27
IPC codes: H01L27, H01L29