MEMORY SUBSYSTEM

Abstract: A memory system (10) including two memories (30 and 40) addressed in parallel (from latch 20 and bus 21) and a circuit (50) for selecting (selection made by multiplexer 60) between the memories to determine whose output will be transmitted (by output buffer 70) to, for example, processing circuitry. Normally, the output of one of the memories (30) is transmitted. The selection circuit includes a content ad­ dressable memory having a plurality of registers for storing addresses. The addresses which control the memories is also received by the selection circuitry. If a received address matches an address received by the selection circuitry, the selection circuit transmits a signal (51, which controls signal on line 64) which enables the output of the other memory to be transmitted to the processing circuitry.

Description: The present invention deals with memory subsystems for computer systems, and more specifically with memory subsystems utilizing a combination of Read-Only Memory (ROM) and Random Access Memory (RAM) Arrays. Memory technology has focused on the development of larger and faster discrete RAM or ROM arrays. When used in specific computer applications each type of array has inherent disadvantages. RAM arrays take up substantially more room than ROM arrays thus making it difficult to integrate a large RAM array in a very-large-scale-integration (VLSI) computer chip. RAM arrays are also volatile, thus requiring the additional cost of providing refresh media. ROM arrays are non-volatile, but their contents cannot be easily changed. Thus, applications using ROM arrays to store a control program inherently incur a higher cost in implementing changes to the code, which might be necessary to correct problems or improve features. The higher cost comes from replacing the obsolete ROM arrays in the field with a newly coded ROM array, plus the additional cost of the obsolete inventory of ROM arrays containing the old code. Combining discrete RAM and ROM parts into a multi-chip memory subsystem offsets some of these disadvantages, but incurs a high cost in the increased memory part count and interface logic. A prior art constituted by the patent abstracts of Japan, vol. 7, no 90, April 14, 1983 (JP-A-58 16350) discloses an arrangement in which only two elements are connected to receive an address input signal, namely a ROM and an address comparator. The address comparator compares an incoming address with a stored address, and in the case of a match addresses a substitution instruction register part and controls an instruction selection circuit so that instead of the instruction from the ROM the substitution instruction is selected. This arrangement cannot solve the problem solved by the memory system of the invention and disclosed in Claim 1. Independent Claims 4 and 5 define embodiments including the same inventive concept as claimed in Claim 1. SUMMARY OF THE INVENTION The present invention provides for a single semiconductor chip which forms an integrated self-contained memory subsystem that can meet a variety of applications. It comprises three separate memory arrays: a mask-programmable ROM array, a RAM array and a content-addressable-memory (CAM) array. The three arrays share common latched address inputs, but are segmented into different address regions. All three arrays are accessed in parallel on every memory cycle. Based on the specified address region and external control signals, an internal multiplexer connects a selected array to the external data bus. The CAM array combines a write-only register with an exclusive-OR circuit that compares cell contents against incoming address data. If any preloaded CAM register matches an incoming address, the CAM array asserts a match signal, which can be used to provide asynchronous selection between RAM and ROM array outputs. Testing means are provided to verify that the CAM registers are correctly loaded and that the means for producing the match signal are working properly. The combination of large mask-programmed ROM for program storage, smaller RAM for variable data storage, and a cascadable byte structure makes the subsystem an ideal memory building block for microcomputers. The internal address latch simplifies interfacing to multiplexed address/data busses. The common control/data interface for all arrays and the use of a static RAM also minimize the need for discrete control logic. This part can also be used in a CPU's microprogrammed control store. The ROM could be programmed with microinstructions for a manufacturer's standard instruction set, while the RAM could be used as a writable control store for application-specific microcode, or to load and execute microdiagnostics. The integral CAM permits construction of a sophisticated patchable control store. ROM instructions to be corrected or modified are trapped by addresses loaded into the CAM, and replaced by patch instructions loaded into the RAM. The patching mechanism is made transparent by configuring the chip(s) with the MATCH output directly controlling the internal output multiplexer. When a CAM match on a patch address occurs, the output multiplexer automatically switches to replace the bad ROM data with the new RAM data. The cascadability of the CAM array permits the number of trap addresses to expand as more memory chips are added to the system. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to Fig. 1, there is shown the Memory Subsystem 1⊘ of the present invention. Memory Subsystem 1⊘ is preferably implemented into one single integrated circuit. Memory Subsystem 1⊘ includes Address and Chip Select Latch 2⊘, ROM Array 3⊘, RAM Array 4⊘, CAM Array 5⊘, Data Multiplexer 6⊘ and Output Buffer 7⊘. A brief overall explanation of the operation of the various blocks will be given first. The external Address Bus A〈14:⊘〉 and Chip Select Signal 22 are stored in Latch 2⊘. The output of Latch 2⊘ is connected in parallel to ROM 3⊘, RAM 4⊘ and CAM 5⊘ over lines 21; thus, all three memory arrays are accessed simultaneously. Multiplexer 6⊘ selects, in response to three control signals 62, 64 and 66, one of the three memory arrays for connection to Output Buffer 7⊘. During normal operation, control signal 66, generated within CAM 5⊘, is not asserted and as a consequence the output of CAM 5⊘ is not selected by Multiplexer 6⊘, limiting the selection between ROM 3⊘ and RAM 4⊘. If control signals 64 and 66 are both not asserted, then ROM 3⊘ is selected. If either one of control signals 64 and 66 is asserted then RAM 4⊘ is selected. Output Buffer 7⊘ drives the contents of the selected memory array onto the External Data Bus D〈7:⊘〉. During a special mode of operation, the contents of the CAM 5⊘ may be written from the Data Bus lines D〈⊘-7〉, and the status of CAM 5⊘ may be read by asserting CAM Select Control Signal 66. Address/Chip Select Latch 2⊘ holds the fourteen bits of Address Input A〈13:⊘〉, Chip Select Signal 22 and Address Input A〈14〉, which is used as multiplexer control signal 62 to select the RAM 4⊘ if asserted. Latch 2⊘ is controlled by Chip Enable Signal 24, whose pulsing is used to capture the input signals and ignore further transitions on the address bus. ROM 3⊘ is a read-only memory array of predetermined size, for instance 16K x 8 bits. It is addressed by bits A〈13:⊘〉 from the output of the Address Latch 2⊘. After the pulsing of line 24 and if Chip Select 22 is asserted, ROM 3⊘ is accessed and produces the contents of the addressed location, in this case eight bits of data, which are passed to Multiplexer 6⊘. RAM 4⊘ is a random access memory of predetermined size having a width equal to the width of ROM 3⊘; here it has a size of 1K x 8 bits. It is addressed by bits A〈9:⊘〉 from Latch 2⊘. After the pulsing of line 24 and if Chip Select 22 is asserted, RAM 4⊘ is either read or written depending upon an additional control signal called Write Enable 42. If Write Enable 42 is not asserted, a read cycle is initiated, and RAM 4⊘ passes eight bits of read data to Multiplexer 6⊘. If Write Enable 42 is asserted, a write cycle is initiated, and the addressed RAM location is written with the data present on the data bus D〈7:⊘〉 inputs. During the write cycle the Output Buffer 7⊘ is automatically turned off in response to the Write Enable signal 42 to prevent data contention on the External Data Bus D〈7:⊘〉. The end of a write cycle is achieved by deasserting either Write Enable Signal 42 or Chip Enable Signal 24. Note that using a subset of the ROM address inputs for RAM addressing maps the ROM locations to RAM locations in a deterministic manner. Thus, when this subsystem is used as a patchable control store a ROM location and the corresponding patch location in RAM are accessed in parallel. CAM 5⊘ is a content addressable memory array having a width equal to the width of the largest address to be received, here it is a 32 x 14 bit array. The purpose of the CAM 5⊘ is to permit selective detection of certain incoming addresses. When an incoming address matches one stored in the CAM array, the CAM logic asserts the open-collector or open-drain Match Output signal 52, if so enabled by the assertion of Match Output Enable Signal 54. The Match signal 52 can be used in two different ways in a patchable control store to permit substitution of RAM array output data for ROM array output data on the data bus D〈7:⊘〉. In the first way, the Match signal 52 is tied externally to the Multiplexer Control input signal 64. This way, Multiplexer 6⊘ will select between ROM 3⊘ and RAM 4⊘ data as a function of the result of the CAM match. This mode effects the substitution of a patch RAM byte for a wrong ROM byte in a single cycle time of a duration at least as long as the amount of time needed to generate the Match Signal 52 plus the switching time of Multiplexer 6⊘. In the second way, Match signal 52 is processed externally, for instance by a computer's microcode, to set control signal 64 as required in subsequent cycles. Referring now to Fig. 2, there is shown one of the thirty-two 14-bit CAM registers 1⊘⊘ forming CAM 5⊘. The CAM register 1⊘⊘ comprises a 14-bit Latch 1⊘4, that stores the trap addresses to be detected, and an Equals Checker 1⊘2 which compares the Latch 1⊘4 contents to CAM address inputs 〈13:⊘〉, shown as lines 122, in each memory cycle. The Equals Checker 1⊘2, which may be implemented as an exclusive-OR circuit, outputs a Match Signal 52 if the Latch 1⊘4 contents equal the address inputs 122 across all fourteen bits. All 32 CAM registers 1⊘⊘ perform this comparison and output their individual match results in parallel. Referring now also to Fig. 3, address inputs 122 to the CAM array come from the Address Multiplexer 12⊘ which connects either external address inputs 21, for normal operation, or test address inputs 121 for a special test mode described below. Trap addresses are written into the CAM from the external data bus inputs D〈7:⊘〉. Each CAM Register 1⊘⊘ can be uniquely written through a pair of reserved addresses. Two addresses per CAM register are needed since the fourteen bits of CAM data must be written in two discrete parts due to the 8-bit width limitation of the external data interface. Decoding of the reserved CAM addresses is performed by Address Decoder 13⊘ which examines the address inputs on lines 21 on every memory cycle, and enables the appropriate CAM Write Enable Signal 134. Table I lists the sixty-four reserved addresses (in octal notation) for the thirty-two CAM registers 1⊘⊘. Bits 〈8:6〉 of the CAM register address, marked as X in the table, are mask-programmed uniquely for each subsystem 1⊘ used in a system to permit unique access to CAM registers on a per subsystem basis. In other words, the present invention allows the cascading of a plurality of subsystems 1⊘ to build any desired memory system. The three mask programmable bits allow the cascading of up to eight subsystems. If the CAM is not used to trap addresses then there is no limit to the number of subsystems that can be cascaded. The subsystem can be stacked horizontally, to provide for a wider storage location (same number of words but more bits), by using a single Chip Select signal 22 for all the subsystems used. Alternatively the subsystem can be stacked vertically, to provide for more storage locations, by using a plurality of Chip Select Signals 22, one for each subsystem. By using more bits in the mask-programmable portion of the address, more than 8 subsystems can be stacked together. For instance, Fig. 4 shows an embodiment using both types of stacking to produce a M by N matrix of Memory Subsystems 1⊘. With each subsystem providing, for instance, a 16Kx8 ROM, a 1Kx8 RAM and a 32x14 CAM, the MxN matrix shown in Fig. 4 provides overall a (M).(16K) x (N).(8) ROM, a (M).(1K) x (N).(8) RAM and a (M).(N).(32) x 14 CAM. Additional external address lines must be used by Chip Select Decoder 18⊘ to decode the address and assert the required Chip Select for the required row. The open-collector or open-drain Match signals are hard-wired together to generate an overall Match signal if any of them are asserted. Referring now back to Fig. 3, it may be seen that although the write-only CAM Registers 1⊘⊘ cannot be explicitly read back, their contents can be verified through a special test mode. When this test mode is activated, a user-specified address is explicitly compared against the contents of all 32 CAM Registers simultaneously, with the individual match results readable on a per register basis. Thus the contents of any given CAM register can be tested by inputting a test address that is identical to that written previously into the CAM and verifying that the particular CAM register indeed outputs a match response. The test mode is activated by turning on the Test Mode Enable bit in the 15-bit Test Mode Register 14⊘, which is also used to hold the 14-bit test address 121 to be compared against the CAM array. The Test Mode Enable bit signals the Address Multiplexer 12⊘ to pass the test address 121 from Register 14⊘, rather than the normal address lines 21 to the CAM for comparison. The 15 bits of the Test Mode Register 14⊘ are loaded from the external 8-bit data bus in two successive write cycles using the two reserved addresses shown in Table II, which are used by Decoder 13⊘ to generate the two test address register Write Enable Signals 136. The match/no match response 53 of each individual CAM Register 1⊘⊘ to the test address can be examined by performing a read operation to four reserved address locations that output the responses (⊘=no match; 1=match), eight registers at a time, onto the external eight-bit data bus. The response 53 of each register is uniquely assigned to a particular bit location in one of the four reserved address locations (see Table III). Decoder 13⊘ is used to detect those 4 reserved addresses and to control the match output in Multiplexers 15⊘ that direct the individual CAM match responses 53 to the main output Multiplexer 6⊘. Decoder 13⊘ also drives the control line 66 which causes Multiplexer 6⊘ to select the CAM data out 〈7:⊘〉. If a bad location of ROM 3⊘ needs to be patched, the following steps are used. First, the low order 1⊘ address bits (A〈9:⊘〉) of the bad location are used to determine the corresponding RAM location to hold the patch. The new data is then loaded into that particular RAM location. The entire 14-bit ROM address is then loaded into any available CAM register, using the appropriate reserved address pair from Table I. Proper loading of the RAM is checked by reading back the contents of the RAM location, using A〈14〉 to connect the RAM array to the output bus. Proper loading of the CAM array is checked by loading the Test Mode Register 14⊘ with the 14-bit address of the bad ROM location, while also turning on the Test Mode Enable bit. All four reserved test mode match addresses from Table III are then checked to see that only the desired CAM register written above matches the patch address. To return to normal memory operation, the Test Mode Register 14⊘ is rewritten to turn off the Test Mode Enable bit. From this point on, if the bad ROM location is addressed, the CAM array will detect this address and assert the external Match output, which can be used as described above to cause substitution of the good RAM data for the bad ROM data. Note that the addresses for the CAM registers and the Test Mode register occupy the same address region as the ROM. Since the write-only CAM array uses these addresses only for write operations, and since the read-only ROM array uses these addresses only for read operations, there is no conflict in the overlap of these two sets of addresses.

Claims: A memory system for receiving address signals and transmitting data signals in response thereto, comprising: (A) a first memory (30) having an address input terminal, a data output terminal, and a plurality of addressable storage locations; (B) a second memory (40) having an address input terminal, a data output terminal, and a plurality of addressable storage locations; (C) address input means (20) connected to said address input terminals of both said memories for coupling address signals to both said memories in parallel; (D) multiplexer means (60) connected to said data output terminals of both said memories for selectively transmitting the data output signal from one of said memories in response to a selection signal (64,66); and (E) selection signal generating means for generating said selection signal, said selection signal generating means including: content addressable memory means (50) having a plurality of storage locations (104) each for storing an address, the content addressable memory means also receiving the address signals from the address input means, and having comparison means (102) connected to said plurality of storage locations and said address input means, and match detection means for generating said selection signal in response to an address signal from said address input means corresponding to the contents of a storage location in said content addressable memory means. A memory system as defined in claim 1 which further receives data signals and a write enable signal (42), in which said first memory (30) is a read-only memory and said second memory (40) is a read/write memory further including a data input terminal adapted to receive the data signals and latch them in the addressable location identified by the address signals received from said address input means in response to the write enable signal. A memory system as defined in claim 1 which further receives data signals and a write enable signal, in which said content addressable memory means (50) further includes a data input terminal adapted to receive the data signals, said selection signal generating means further including address decoding means (130) for receiving the write enable signal and the address signals for enabling the storage location identified by the address signals to latch the data signal at the data input terminal in response to the write enable signal. A memory system for receiving address signals and transmitting data signals in response thereto, the memory system comprising: (a) a read-only memory (30) (ROM) having an address input terminal connected to receive the address signals, a data output terminal connected to providing ROM data, and a plurality of addressable read-only storage locations; (b) a random access memory (40) (RAM) having an address input terminal connected to receive the address signals, a data output terminal connected to provide RAM output data, and a plurality of addressable read-and-write storage locations; (c) a content addressable memory (50) (CAM) means, including a plurality of storage locations, each location for storing an address, for generating a selection signal in response to the receipt of an address input signal corresponding to the contents of one of the storage locations; (d) address input means connected to provide said address signals to said ROM, RAM, and CAM memories in parallel; (e) test mode means (130, 140, 120) for selectively enabling a test mode wherein the contents of the CAM may be verified by inputting a test address that is identical to an address previously stored in the CAM, and for outputting a test result signal (CAM data out) in response thereto; and (f) data multiplexer means (60) connected to said data output terminals of said ROM, RAM and CAM, for selectively transmitting the data output signal from one of said ROM or said RAM in response to the selection signal when the test mode is not enabled, and for otherwise transmitting the test result signal when the test mode is enabled. A memory system for receiving address signals, data signals and a write enable signal (42) and for transmitting data signals in response thereto, the memory system comprising: (a) first (30) and second (40) memories each having an address input terminal, a data output terminal and a plurality of addressable storage locations; (b) content addressable memory means (50) having an address input terminal, including a plurality of storage locations each for storing an address, for generating a selection signal (64,66) in response to the receipt of address signals corresponding to the contents of one of the storage locations and for further generating at a data output terminal a data output signal; (c) address input means (20) connected to said address input terminals of both said first and second memories for transferring address signals to both said memories in parallel; (d) data multiplexer means (60) connected to said data output terminals of both said first and second memories and said content addressable storage means for selectively transmitting the data output signal from one of said memories or said content addressable storage means in response to the selection signal; (e) address multiplexer means (120) connected to receive said address signals and further connected to said content addressable storage means for transferring said address signals from said address input means or a test address (121) which is transferred to said content addressable storage means in response to a test mode status signal (SEL in 120); and (f) test mode means including test mode information storage means (104) for storing the test address and a test mode status, said test mode means generating said test mode status signal in response to the contents of said test mode status storage means. A memory system as defined in claim 5 wherein said content addressable storage means includes a plurality of address storage means (104) each for storing an address and a corresponding plurality of comparison means (102) each connected to one of said storage means, said comparison means further being connected to said address input means for receiving said address signals and generating said selection signal in response to the address signals corresponding to the address in the associated storage means. A memory system as defined in claim 6 wherein said content addressable storage means further includes a means for receiving data signals and address decoder means (130) connected to receive a write enable signal (42) and further connected to said address input means and to all of said address storage means for enabling one of said address storage means identified by said address signals from said address input to store the data signals in response to the write enable signal. A memory system as defined in claim 7 wherein said test mode means is further connected to receive said data signals and further connected to said address decoder means (130), said address decoder means enabling said test mode means to store the data signals in response to the address from said address input means and said write enable signal. A memory system as defined in claim 6 wherein said content addressable storage means includes data signal generating means gate connected to said address storage means for generating said data output signal in response to one of the address storage means which contains the address corresponding to the contents of said address input means. A memory system as defined in claim 9 wherein said address storage means (104) are divided into a plurality of groups (100A, 100B, ...), said data signal generating means generating the data output signal in response to the contents of the particular address storage means identified by the address signals from said address input means.

Inventors: JOHNSON, WILLIAM N., LACKEY, STANLEY A., NGUYEN, LE TRONG, SITES, RICHARD L.
Applicants: DIGITAL EQUIPMENT CORPORATION
Application year: 1984
Main classification: G06F12
IPC codes: G06F9, G11C8, G11C7, G11C17, G11C29, G06F12, G11C16