REACTANCE MEASUREMENT CIRCUIT WITH ENHANCED LINEARITY

Abstract: Circuit for measuring the reactance of a reactance sensor (C1, C2) which varies responsive to a condition to be sensed, such as pressure, and which provides an output signal representative of the sensed condition. The cicuit comprises an oscillator (218) coupled to the sensor for providing a time varying oscillator signal to the sensor (C1, C2), and a plurality of rectifiers (220A) coupled to the oscillator (218) and to the sensor (C1, C2) for providing charging signals to the sensor and for providing discharging signals from the sensor. A control amplifier (216) is coupled to receive the sensor charging and discharging signals and to the oscillator (218) for providing an input control signal to the oscillator (218) as a function of the sum of at least two sensor signals wherein at least one of the sensor signals is selectively amplified (212) to enhance the relationship between the output signal and the sensed condition.

Description: REACTANCS MEASUREMENT CIRCUIT WITH ENHANCED LINEARITY BACKGROUND OF THE INVENTION 1. Field of the Invention. The present invention relates to linearizing reactance sensor circuitry and more particularly to capacitance transducers for measuring pressure. 2. Prior Art Practical reactance sensors commonly exhibit transfer functions that can be approximated by: O * MX + NX 2 + QX 3 where: 0 = output signal X = sensed variable M = sensitivity constant = second order nonlinearity constant and, Q = third order nonlinearity constant It is desired that N and Q be as low as possible to give a desired linear relationship between the output signal, O, and the sensed variable, X. Prior art circuitry allows the third order constant, Q, to be adjusted as desired to minimize the combined effect of the second order term, N, and the third order term, Q. In the present invention substantially in dependent adjustment of the second and third order nonlinearity constants, N and Q, is made possible, resulting in substantially improved performance. SUMMARY OF THE INVENTION The present invention comprises a reactance measuring circuit for providing an output signal with enhanced linearity. The circuit comprises a reactance means which varies responsive to a condition to be sensed such as pressure. An oscillator provides a time varying signal to the reactance means. A rectifying means is coupled to the reactance means for providing sensor signals as charging signals to and discharging signals from the reactance means, A control means is coupled to the sensor signals and to the oscillator for providing an input control signal to the oscillator as a function of the sun of at least two sensor signals, wherein at least one of the sensor signals is selectively amplified. The selective amplification of at least one of the sensor signals provides an enhanced relationship between the output signal and the sensed condition. In one preferred embodiment, the output signal comprises a second order dependence on the sensed parameter. Selective amplification of at least one of the sensor signals compensates for such second order dependency, enhancing the output signal. In a further preferred embodiment, adjustment of one of the sensor signals is accomplished by an amplifier means. The amplifier means further comprises an impedance network for selective amplification of one of the sensor signals as a function of the impedance of the impedance network. Such selective amplification of one of the sensor signals has a predominant effect on second order linearity of the output signal with respect to the sensed condition. Use of an operational amplifier comprising the amplifier means improves the relationship between the output signal and the sensed parameter without substantially adversely affecting biasing or responses of associated circuitry, providing second order linearity adjustment. The second order linearity adjustment when combined with other existing circuit adjustments provides an improved output signal from lower to upper range limits. Thus, span, zero and range adjustments can be made without need for readjustment of linearity. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation of a reactance measurement circuit according to the present invention, FIG. 2 is a graph of typical data of a prior art circuit, having third order dependence eliminated, expressed as endpoint linearity, and FIG. 3 is a graph of end point linearity of a circuit constructed according to Fig. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a circuit embodiment of the present invention shown generally at 200 preferably is used in conjunction with an AC reactance type differential pressure sensor cell, and preferably has a pair of capacitors C-^ and c 2 at least one of which is variable, responsive to a parameter, preferably pressure. FIG. 1 basically is the circuit of FIG. 3 of U.S. Patent No. 4,381,677, issued May 3, 1983 to Ruesch, Frick and Grindheim, except the differences as noted herein. Basic operation of circuit 200 is fully described in U.S. Patent No. 4,381,677 and is further explained herein. U.S. Patent 4,381,677 has the same disclosure or specification as International Publication No. WO 82/02595. A sum point means 210 also known as current summing node 210 is fed a first discharging signal or, first current i^ responsive of the capacitance of capacitor C- and a second charging signal or, second current i 2 responsive of the capacitance of capacitor C 2 from an amplifier means 212 also known as inverting amplifier 212 for selectively amplifying and inverting second current i 2 » Summing node 210 sums the first and second currents as by arithmetically combining the currents. The first and second currents can be charging or discharging signals in other preferred embodiments. A control means 216, also known as control amplifier 216 has its non-inverting input (as indicated by the plus (+) sign) coupled to circuit common and its inverting input (as indicated by the minus (-) sign) coupled to summing node 210 and produces an output signal to control the frequency of an oscillator means 218, also known as voltage controlled oscillator 218. Oscillator 218 repetitively charges capacitors C^ and C 2 through a rectification means shown generally at 220 with substantially constant amplitude, variable frequency oscillating voltage signals (V peak to peak amplitude) , the frequency of which .is controlled responsive to the changes of the capacitance of C j and C2. Capacitors C^ and C 2 repetitively discharge through rectification means 220 responsive to their repetitive charging. Thus capacitor Cj has first signals for charging and discharging and capacitor C 2 has second signals for charging and discharging. Rectification means 220 rectifies the currents i. and i j , representative of C j and C 2 which result from the repetitive charging and discharging of C j and C2. It is noted that the circuit 200 can also operate with a constant frequency varying voltage provided by oscillator 218, with the voltage controlled by control amplifier 216. An adjustable capacitor C 3 is coupled to summing node 210 through diodes 242 and 244 to provide a current i C3 to summing node 210 through lines 243 and 245 respectively. Diodes 242 and 244 may be included in rectification means 220A for increased thermal stability. It is noted that C 3 is coupled to summing node 210 through two separate paths, diodes 242 and 244 and lines 243 and 245 respectively, such that the capacitance of C 3 need not be doubled as stated in U.S. Patent No. 4,381,677 where capacitor C 3 is coupled to summing node 210 only through diode 244. Coupling capacitor C 3 through both diodes 244 and 242 provides approximately twice the current i C5 therefore eliminating the need to double the capacitance. Amplifier 212 has an output and an inverting input (as indicated by the minus (-) sign) , the output being coupled to the inverting input through a first resistor 250 and, the output being coupled to summing node 210 through second resistor 252, neither of said resistors having been indicated by number in FIG. 3 of U.S. Patent No. 4,381,677. An output amplifier 230 having an output and an inverting input (as indicated by the minus (-) sign) is coupled at its inverting input to rectification means 220 and provides an output signal Q to a suitable implementation means 232, such as a two wire current control, readout, device or the like which draws an output current signal I Q . Amplifier 212 selectively amplifies second current i 2 and capacitor C_ current i cs . Currents i 2 and i cs are preferably amplified by a factor K j which is a ratio of an impedance means comprising the resistance of resistor 250 divided by the resistance of resistor 252. Second current i 2 and current i cs are selectively amplified without substantially adversely affecting the biasing or response of control amplifier 216 or other associated circuitry. Currents i^, ^^2' and the currents from capacitor C 3 , (1 + K j ) i cs are fed into summing node 210 and flow through a resistor 214 to a reference, -V REP, producing a voltage at summing node 210 responsive to the first and second signals. The currents, K j i cs and K j ^ arβ different from that shown in FIG. 3 of U.S. Patent No. 4,381,677. The capacitance of capacitors C and C 2 change in response to a difference in pressure. The output signal I n is of the form: 2 3 ■ MP + NP + QP Equation 1 wwhheerree V:: I n - output signal of amplifier 230 P > differential pressure M - • sensitivity constant N second order nonlinearity constant and. Q ' third order nonlinearity constant Th output signal Ig is essentially a first, second and third order function of differential pressure which can be approximated in terms of capacitance as: C - C x o β c τ * κc 2 i♦ j c s ** tion 2 where: I. » output signal of amplifier 230 O. » capacitance of C. C 2 - capacitance of C. - β*4rt - Λ resistance of resistor 250 *1 nzxo or resistance of resistor 252 and, C_ » capacitance of C 3 The capacitances of C^ and C j can be expressed as: l β 1 - BP * C Equation 3 5 C 2 " 1 - EP * F Equation 4 where: A * active rest capacitance of C j B * normalized inverse spring constant of C j C * stray capacitance of C j 0 D » active rest capacitance of C 2 E « normalized inverse spring constant of C_ F * stray capacitance of C, and P =» differential pressure. Combining Equations 2, 3 and 4 yields: S A-D+C-F * (AE*DB«-(C-F) (E-B)) P-(C-F)BEP 2 J ce 0 ♦ (AE-K 1 DB*(C*K 1 F-C 3 *K 1 )) CE-B)) P - (C*r t F-C 3 (l*K 1 ))BEP 2 ) E piation 5 0 Equation 5 can be simplified using letters G, H, I, J, K and L as coefficients corresponding to the actual coefficients of pressure P in equation 5: G ♦ HP ♦ IP 2 T — 2 5 x ° j . J3» ♦ LP Equation 6 where: G « A-D+C-F H -B' AE+DB+ (C-F) (E-B) I « - (C-F) BE 0 J • A+^ D+C+K j F-C j (1+K j ) * AE-K j DB+ (C-K j F-C 3 ( 1+K j ) ) (B-B) and L m - (C+K j F-C 3 ( 1+K χ ) BE) For Equation 6 to be linear with respect to pressure P, the following two equations should be satisfied: » 0 Equation 7 and, H - - — ♦ G « 0 Equation 8 Equation 8 is derived by setting - 0 in Equation 6 and dividing the numerator in Equation 6 by the denominator in Equation 6 until a first order pressure term appears leaving a remainder which is set equal to zero. Varying K j and varying the capacitance of capacitor G j , provides sufficient flexibility to substantially satisfy Equations 7 and 8. Adjustment of the capacitance of C ύ_ provides a >predominantly third order adjustment which in the past has been used to adjust the linearity of output signal I over selected ranges of pressure. In FIG. 2, a graph of typical data, where the output signal is a 4 to 20 milliampere signal (as for example in FIG. 3 of U»S. Patent Mo. 4,381,677), expressed as terminal based linearity of output signal I versus pressure is shown with capacitor C adjusted to minimize third order dependence. A second order differential pressure dependency remains having a maximum deviation from linear of approximately -.29 percent. Adjustment of ! by selectively trimming resistors 250 and 252 results in a predominantly second order dependency control. In one embodiment resistors 250 and 252 preferably each comprise at least two resistors coupled in parallel, at least one of which is trimaable as by a laser to vary OMPI the parallel resistance. K j is then the ratio of the equivalent resistance of the parallel resistors of resistor 250 divided by the equivalent resistance of the parallel resistors of resistor 252. hen capacitor C_, resistor 250 and resistor 252 are correctly selected, a substantially linearized function results and Equations 7 and 8 are substantially satisfied. Resistors 250 and 252 can also be variable as a function of pressure or other parameter affecting second order differential pressure dependency. The present invention provides enhanced linearity from lower to upper pressure range limits allowing adjustment of span, zero and range (standard process measurement terminology) of the differential pressure transmitter without readjustment of linearity. Linearity is also enhanced when compared to linearizing by only utilizing third order adjustments. To partially compensate for second order linearity by adjusting capacitor C 3 , the third order dependence is not minimized, but optimized to account for both second and third order dependence, leaving both a third order dependence and a second order dependence. By selectively choosing resistors 250 and 252 and capacitor C 3 , both second and third order dependencies are substantially independently minimized resulting in a substantially linear relationship between the output signal I and pressure from lower to upper pressure range limits, enabling span and zero changes to be made over the entire range of pressure from the lower range limit to the upper range limit without need for readjustment of linearity. In FIG. 3 a graph of terminal b^ d linearity of output signal I fl (a 4 to 20 millia pere" signal) from a circuit constructed according to FIG. ). shows enhanced terminal based linearity of output signal I. with capacitor C 3 and resistors 250 and 252 selected to improve linearity. The maximum deviation from linear is less than .04 percent. Capacitor C 3 is selected to minimize third order dependence and resistors 250 and * 252 are selected to minimize second order dependence. Comparing FIGS. 2 and 3 by subtracting their respective maximum deviations from linear (-.29 - (-.04) * -.25 percent) shows that unadjusted second order linearity is the largest uncorrected dependence after third order dependence is compensated. it has been found that a K of between 0.900 and 1.100, is sufficient to compensate for second order nonlinearity without adversely affecting associated circuitry. Preferably, K~, varies between 0.975 and 1.025. With K 1 individually selected between 0.975 and 1.025 second order dependence is minimized in virtually every case. The above constructed circuit comprised resistor 250 having an equivalent resistance of 27,80? ohms and resistor 252 having an equivalent resistance of 28,088 ohms, resulting in a K 1 of 0.990. in a further preferred embodiment of the present invention as seen in FIG. 1 of U.S. Patent No. 4,381,677, resistors 54 and 56 are varied to provide second order linearity adjustment and enhancement of the output signal. Resistors 64 and 66 also can similarly be varied. In FIG. 2 of U.S. Patent No. 4,381,677, it is within the scope of the present invention to adjust C OMPI and amplify i- , i. or both in a manner described above to enhance the output signal.

Claims: WHAT IS CLAIMED IS: 1. λ circuit for measuring a variable reactance means having at least two reactances, at least one of which varies responsive to a condition to be sensed, the circuit providing an output signal representative of the sensed condition, the circuit comprising: oscillator means coupled to the reactance means for providing a time varying oscillator signal to the variable reactance means? recti ication means coupled to the reactance means for providing charging signals to and discharging signals from the reactance means, the charging and discharging signals being a function of the reactances of the reactance meansι and control means coupled to the rectification means and to the oscillator means for providing an input control signal to the oscillator means to adjust the charging and discharging signals as a function thereof wherein one of the charging and discharging signals is selectively amplified to achieve * predetermined relationship between the output signal and the sensed condition. 2. The circuit of Claim 1 wherein the reactance means comprises at least one varying capacitor. OMPI 3. The circuit of Claim 1 wherein the sensed parameter is pressure. 4. The circuit of Claim 1 wherein the reactance means comprises at least a first and a second reactance means responsive to the sensed condition at least one of which is variable. 5. The circuit of Claim 4 wherein at least one of the charging and discharging signals responsive to the reactance means which varies responsive to the sensed condition is selectively amplified. 6. The circuit of Claim 4 further comprising: a first charging signal and a first discharging signal responsive to the first reactance means, and a second charging signal and a second discharging signal responsive to the second reactance means. 7. The circuit of Claim 6 wherein at least one of the first charging, first discharging, second charging and second discharging signals is selectively amplified. 8. The circuit of Claim 6 wherein the first reactance means varies responsive to the sensed condition and wherein at least one of the first charging and first discharging signals is selectively amplified. 9. The circuit of Claim 6 wherein at least one of the first charging and first discharging signals is selectively amplified. 10. The circuit of Claim 7 wherein the output signal has certain nonlinearities with respect to the sensed condition and wherein the selectively amplified signal substantially compensates for the nonlinearities. 11. The circuit of Claim 7 wherein the output signal comprises a second order dependence on the sensed parameter and wherein the selectively amplified signal substantially compensates for the second order sensed parameter dependence of the output signal. 12. The circuit of Claim 9 and further comprising: sum point means coupled to the control means and to the rectification means for combining the selectively amplified signal and at least one of the second charging and second discharging signals. 13. The circuit of Claim 12 further comprising: amplifier means coupled between a selected one of the first charging and first discharging signals and the sum point means for selectively amplifying said signal. 14. The circuit of Claim 13 wherein the amplifier, means further ςo prises: impedance network means for selectively determining the relationship between the selected signal and the selectively amplified signal. 15. The circuit of Claim 13 wherein the amplifier means further comprises a first operational amplifier having an inverting input and an output. 16. The circuit of Claim 15 wherein the impedance network means comprises: first impedance means coupled between the inverting input and the output of the first amplifier; and second impedance means coupled between the output of the first amplifier and the sum point means wherein the relationship between the first and second impedance means determines the selective amplification of the selected signal. 17. The circuit of Claim 16 wherein the selected signal is selectively amplified as a function of the impedance of the first impedance means divided by the impedance of the second impedance means. 18. The circuit of Claim 15 wherein the first and second impedance means comprise first and second adjustable resistors, respectively and wherein the ratio of the first resistor to the second resistor is representative of the selective amplification of the selected signal. 19. The circuit of Claim 9 and further comprising: output amplifier means coupled to the rectification means for differentially summing at least one of the first charging and first discharging signals and at least one of the second charging and second discharging signals. 20. The circuit of Claim 9 and further comprising: output means coupled to the output amplifier means for providing the output signal which has a substantially linear relationship with pressure. 21. The circuit of Claim 12 wherein the control means comprises a second amplifier having an input coupled to the sum point means and an output coupled to the oscillator means for providing the input control signal to the oscillator means. 22. The circuit of Claim 21 wherein the sum point means provides a signal representative of the sum of the selectively amplified signal and at least one of the second charging and second discharging signals to the input of the second amplifier.

Inventors: FRICK ROGER L, FRICK, ROGER, L.
Applicants: ROSEMOUNT INC, ROSEMOUNT INC.
Application year: 1984
Main classification: G01L9
IPC codes: G01L9