NON-LINEAR LOAD ELEMENT FOR MEMORY CELL

Abstract: A bistable circuit element for integration into a static memory cell constructed of two transistors with cross-coupled base and collector regions and having a nonlinear load element (111) wherein the load element is a nonlinear surface load device. In particular, the nonlinear surface load device is a structure comprising a metallized contact segment (124) in semiconductor junction contact with a lightly doped monocrystalline silicon implant (119). The manufacturing technique approximates that of a Schottky diode with implant doping modified to increase the non-ideality factor m relative to the ideal of m = 1. The non-ideality factor m is limited so that the nonlinear surface load device does not degenerate into a linear ohmic.

Description: NON-LINEAR LOAD ELEMENT FOR MEMORY CELL. BACKGROUND OF THE INVENTION This invention relates to bipolar memory devices and in particular to a static memory cell to be integrated in large numbers comprising a semiconductor body having two transistors with cross-coupled based and collector regions, wherein the collector regions are coupled to a load element. Memory cells may be formed by generally known bistable multivibrator circuits or flip-flops in which collectors are connected through load elements to a common conductor, such as a supply line and in which the emitter regions are connected in common to a current source. Second emitter regions are generally used in relation to the transistors for connection to read/write conductors. During reading into a cell, a comparatively large read current, on the order of for example 1mA is employed on the read/write line. A load element having a comparatively small resistance could be used where relatively large read currents are employed. In the standby condition, in which the cell is not read but in which information must remain stored, it is desirable that only a minimal standby current be conveyed through the cell in order to minimize dissipation, which generates undesirable heat and wastes energy. Thus two contradictory requirements are imposed upon a load element, namely a low impedance in connection with comparatively large read currents and a high impedance in connection with comparatively small standby currents. Where linear resistive elements are employed as load elements, a ratio of read current to standby current of approximately five can be obtained. A substantially higher ratio is desirable, but generally cannot be realized using linear elements. In addition, linear elements such as integrated resistors require a relatively large amount of precious space in a miniaturized linear circuit. Therefore, some other type of load element would be desirable. Nonlinear load elements in cross-coupled static bipolar memory cells have been used because they allow a relatively large sense current compared with standby current. Recently, several approaches have been developed. R. Rathbone et al/, "A 1024-bit ECL RAM with 15 ns access time," IEEE ISCC, DIG. TECH. PAPERS, February 1976, pages 188-189, describes the use of a slow silicon p-n diode in parallel with a resistor load. Mukai et al., "Ultra high-speed one K-bit with 7.5 ns access time, " IEEE ISSCC DIG. TECH. PAPERS, February 1977, pages 78-79, describes the use of a fast Schottky diode in parallel with a resistor load. Figure 1 is a cross-sectional view of one-half of a prior art memory cell employing a punchthrough device according to the prior art taken from Figure 4 of Lohstroh, "The Punchthrough Device as a Passive Exponential Load in Fast static Bipolar RAM Cells", IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. SC-14, October 1979, pages 840-843. The Lohstroh paper suggests the use of a punch through load 10 in a translinear circuit 12. The punch through load consists of a n -p-n structure on a p-type substrate. A low-doped epitaxial layer 14 consisting of p-type material is provided as the p region in the load 10. Typical concentration is N^=10 /cm . A shallow maskless ion implant 16 of boron is employed on the surface under the protective oxide 18 to prevent surface channeling. Figure 2 is a schematic diagram of a standard prior art memory cell taken from U. S. Patent No. 4,322,821 issued March 30, 1982 to Lohstroh et al. The diagram shows the use of diode load elements 11. The Lohstroh et al. patent teaches use of p-n junction diodes as load elements 11 wherein at least one of either the cathode or the anode region of the diode is constructed of polycrystalline silicon and in which the collector regions of the cross-coupled transistors Tl and T2 are conductively connected to the polycrystalline silicon region of the diodes 11 and are of the same conductivity type. The subject matter of the Lohstroh et al. patent is incorporated herein by reference and made a part hereof for the purposes of describing relevant background information. Figure 3 is a plan view of a layout of a prior art embodiment of the circuit of Figure 2, taken from Figure 5 of the Lohstroh patent. Figure 4 is a sectional view of a prior art memory cell employing polycrystalline silicon taken from Figure 6 of the Lohstroh patent. • Numerals and letters have been added to show correspondence between features of Figures 2, 3 and 4. Polycrystalline silicon word lines 24 (Figures 3 and 4) of the p-conductivity type form a p-n junction 31 with a highly doped n-type collector contact zone 19 which in turn is coupled to collector regions 16. Various embodiments are taught by Lohstroh so long as one of the materials forming the junction 31 is through a polycrystalline silicon semiconductor. It is a well known fact that an ideal diode produces a constant change in diode voltage per change in current in the translinear range of the diode at constant temperature. For example, at room temperature (25°C) , there is a constant linear change of 60 mV per decade change in current at any point along the voltage curve of an ideal diode. It has furthermore been recognized that a current-independent voltage amplification can be obtained by using a rectifying junction as a load element which has a current-voltage characteristic in the forward bias direction equal I, _ I exp(qV d /mkT) where Id is the diode current; I is the saturation current; s Vα, is the diode voltage; q is the electron charge; k is Boltzmann's constant. T is temperature; and m is the non-ideality factor which represents the deviation of the diode characteristic with respect to an ideal. The stability criterion for bistable flip-flop constructed of a cross-coupled transistor pair 16 met when the non-ideality factor m is greater than 1 in the nonlinear load element where the non-ideality factor in the transistors is equal to 1. Various structures have been suggested for achieving a non-ideality factor greater than one in bistable circuit elements. In addition to the structures suggested by Lohstroh, Seevinck has suggested the application of a translinear principle in a bistable element by connecting two diodes in series as the load element. See for example Seevinck, "Application of the Translinear Principle in Digital Circuits," IEEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. S.C.-13, August 1978, pages 528-530. Attempts to optimize the bistable memory element with nonlinear load elements have encountered a number of problems. There remains a need to reduce the size of the cell without sacrificing reliability or production yield. What is needed is a minimum size bistable memory device constructed with monocrystalline semiconductor load element. SUMMARY OF THE INVENTION According to the invention, . a bistable circuit element is provided for integration into a static memory cell which is constructed of two transistors with cross-coupled base and collector regions and having a nonlinear load element wherein the load element is a nonlinear surface load device. In particular, the nonlinear surface load device is a structure comprising a metallized contact segment in semiconductor junction contact witlf a lightly doped monocrystalline silicon implant. The manufacturing technique approximates that of a Schottky diode with implant doping modified to increase the non-ideality factor m relative to the ideal of m = 1. The non-ideality factor m is limited so that the nonlinear surface load device does not degenerate into a linear ohmic contact characteristic. The invention will be better understood by reference to the following detailed description taken in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a prior art device. Figure 2 is a schematic diagram of a prior art device. Figure 3 is a schematic diagram of a prior art device. Figure 4 is a schematic diagram of a prior art device. Figure 5 is a schematic diagram of a bipolar bistable static memory cell in accordance with the invention. Figure 6 is a plan view of a specific embodiment of a bistable static memory in accordance with the invention. Figure 7 is a cross-sectional view along a line 7-7 of Figure 6. Figure 8 is a cross-sectional view in detail of a portion of Figure 7 for illustrating a specific embodiment of the invention. Figure 9 is a voltage-logarithmic current diagram for showing various characteristics according to the non-ideality factor m. DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENT Referring to Figure 5, there is shown a schematic diagram of a bistable static memory cell in accordance with the invention. Transistors Tl and T2 are cross-coupled from a collector junction A on transistor Tl to a base junction B on transistor T2 by a crossing connection 30 and between a base junction C on transistor Tl and a collector junction D on transistor T2 via crossing connection 30'. First emitter regions E and F are coupled together via conductor line 27. Emitter region G is connected to read/write line 28. Emitter region H is connected to read/write line 29. According to the invention, a first nonlinear surface load device 111 and a second nonlinear surface load device 211 are " respectably coupled to first collector region A and second collector region D from a conductive word line 124, the conductive word line 124 being formed of a simple metallic conductive material such as aluminum. Referring to Figures 6, 7 and 8 together, there is . shown a specific embodiment of a bistable static memory cell in accordance with the invention. The numerals of Figure 5 referred to identical features in Figures 6, 7 and 8. The location of nonlinear surf≤ce load devices 111 and 211 are identified in Figure 6. In Figure 7, a cross-sectional view of one-half of the memory cell is shown, identifying nonlinear surface load element 111. According to the invention, there is provided a nonlinear surface element 111 which comprises a junction 31 between a controlled ion implant 119 and a metal conductive layer for example as formed by conductive line 124. The ion implant is preferably an n ion implant in an n " ~ epitaxial layer forming the collector island 16. The remainder of the structure is conventional. An n buried layer 18 forms a boundary between the n type epitaxial layer 16 and a p type substrate 13. The collector contact A(30) makes ohmic contact with a conventional n collector contact zone 130. The base contact C is connected through conductor 30' (Figure 6) to the corresponding collector contact D of the second transistor. The base is formed by base region 20 of p type material. The regions 21 and 22 are n type emitter regions connected to contacts G and E. Referring to Figure 8, in a preferred embodiment, the metallic conductor 124 is preferably joined with the implant region 119 at junction 31 through metal layers of titanium tungsten 202 and platinum suicide 204. The implant region 119 ' is carefully doped to control the m factor of the junction 31. If the doping density of junction 31 is too high, junction 31 becomes an ohmic contact. If the doping density of junction 31 is too low, the m factor is very close to 1, and junction 31 forms a conventional Schottky diode. It has been found that an m factor between about 1.4 and ' about 2.4 with an ideal m factor of 2.1 is the preferred range requirement of a nonlinear surface load element 111 in accordance with the invention. Nevertheless, any m factor greater than 1 and which is not so high that an ohmic contact is formed will satisfy the requirement of the invention. Referring to Figure 9, there is shown, a voltage vs. logarithmic current diagram with characteristics representing various m factors. The characteristic m=l is the conventional characteristic of a Schottky-type diode. A characteristic along the vertical axis represents an ohmic contact where the resistance is equal to zero. According to the invention, the nonlinear load element 111 is preferably a device which exhibits an m factor in the range 300 between m=1.4 and m=2.4 with a most preferred m factor of m=2.1, where the m " factor of the transistors is equal to 1.0, which is the conventional m factor for a semiconductor device. This m factor can be achieved with a doping in the range of about 3x10 electrons/cm to 2x10 electrons/cm concentration.. For example, a typical dopant is a phosphorus dopant in a n~ type epitaxially grown layer which has 10 16 typical doping. The metal used in the junction 31 (Figure 8) , as for example layers 202 and 204, can be any number of materials such as gold, titaniu tungsten, platinum suicide, or aluminum, in various combinations. An oxidation layer 23 is provided for insulation purposes. The invention herein described provides a nonlinear load element suitable for construction in large quantities and which requires minimal space on an integrated circuit. Furthermore, construction techniques are simple and relatively easily controlled, which contributes to the reliability and production yield of structures incorporating large numbers of memory cells in accordance with the invention. The invention has now been explained with reference to specific embodiment. Other embodiments will be apparent to those of ordinary skill in the art. It -is therefore not intended that this invention be limited except as indicated fay the appended claims.

Claims: CLAIMS 1 Claim; 1. A memory cell for use in an integrated static bipolar memory circuit, which comprises a semiconductor body having two bipolar transistors with cross-coupled base and collector regions, and a load element, said load element being connected to each collector region, said load element comprising a nonlinear load formed by a junction of a metal with a lightly doped ion implant, wherein the ion implant is of a controlled dosage resulting in a diode non-ideality factor of greater than 1 and which is imbedded in an epitaxial layer. 2. The memory cell according to claim 1 wherein said non-ideality factor is in the range of 1.4 to 2.4. 3. The memory cell in accordance with claim 2 wherein the non-ideality factor is 2.1. 4. The memory cell according to claim 1 wherein said junction is formed of a metal taken from the group comprising aluminum, gold, titanium tungsten, and platinum suicide. 5. The memory cell according to claim 4 wherein the metal contact is formed of platinum suicide in contact with the ion implant region and wherein the platinum suicide is overlayed with a layer of titanium tungsten and the titanium tungsten is overlayed with aluminum. 6. The memory cell according to claim 1 wherein said epitaxial layer is an n~ type epitaxial layer and wherein said ion implant is an n-type ion implant. 7. The memory cell according to claim 6 wherein the epitaxial layer is doped with a concentration of 10 16 electrons/cm3 and wherein said ion implant achieves a concentration of greater than 10 16 electrons/cm3. 8. The memory cell according to claim 7 wherein the ion implant achieves a concentration between 3x10 17 electrons/cm3 and 2x101*8 electrons/cm3. 9. The memory cell according to claim 7 wherein the dopant is phosphorus.

Inventors: WONG THOMAS S W, WONG, THOMAS, S., W.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1984
Main classification: H01L29
IPC codes: G11C11, H01L27, H01L29