SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device including word lines (WL), bit lines, and memory cells (in MCA₁, MCA₂) located at each cross point therebetween, wherein each of the word lines (WL) is divided to form segmented word lines (WL₁, WL₂). Each of the word line segments is driven by an individual pri­ vate word driver (Q wd1 , Q wd2 ). The individual private word drivers are activated together in response to a word selection signal.

Description: The present invention relates to a semiconductor memory device (below, "memory"), more particularly to a memory of a static random access memory (S.RAM) type composed of emitter-coupled-logic (ECL) memory cells. Various types of memories have been developed and put into practical use. Recent research and development has concentrated upon achieving greater miniaturization of memory patterns, i.e., increasingly higher densities of packing of integrated circuit (IC) memories. To fabricate a denser IC memory, however, it is not sufficient merely to miniaturize the memory cells and wiring. Miniaturization creates additional problems which themselves must be solved. In a prior art ECL-type S.RAM, increased miniaturization and high integration create the problem of electromigration. More specifically, when the current density exceeds a predetermined threshold level in, for example, aluminium wiring made narrower in width by miniaturization, the inherently solid-state aluminium is transformed by heat into a molten state and will flow elsewhere. When electromigration takes place, the functioning of the memory cannot be guaranteed. Therefore, excessive current density must be prevented, not only for aluminium wiring but for all other wiring of other conductive materials, so as to suppress electromigration. According to the present invention there is provided a semiconductor memory device, operatively connected to a word decoder which generates a word selection signal at a memory selection time, said memory device comprising:- a plurality of memory cells, each of said memory cells comprising a pair of bipolar transistors cross-coupled to form a flip-flop; a plurality of initial word drivers, each operatively connected to the word decoder and activated by the word selection signal from the word decoder; a plurality of bit line pairs operatively connected to said memory cells; a plurality of bit drivers, each operatively and respectively connected to one of said bit line pairs, for sending a bit line selection signal thereto, thereby specifying a desired one of said memory cells in combination with the word selection signal; a plurality of word lines, operatively and respectively connected to said initial word drivers and said memory cells, forming cross points with said bit line pairs, said memory cells being located at the cross points; characterised by:- said word lines being made out of a material in which electromigration may occur and each being divided into a plurality of word line segments, a first word line segment of each of said word lines being directly activated to carry a word line signal by one of said initial word drivers in dependence upon the word selection signal; segment word drivers operatively connected between the word line segments, one of said segment word drivers being activated when the word selection signal activates a corresponding initial word driver operatively connected via a corresponding first word line segment to the one of said segment word drivers, each of said segment word drivers being formed by a single emitter follower transistor operatively connected to a following second word line segment and having a base operatively connected to the corresponding first word line segment; and a plurality of level shifting means, provided respectively for ones of said bit drivers connected to bit line pairs corresponding to said second word line segments, and each operable to lower the level of the bit line selection signal of the respective bit driver relative to the bit line selection signals of ones of said bit drivers connected to bit line pairs corresponding to said first word line segments. An embodiment of the present invention can provide a semiconductor memory device, particularly an ECL-type S·RAM, which can reduce the current density in wiring, even narrow-width wiring used in miniaturized memories. Consideration is given to reducing the current density of all word lines of a memory since there is considerable likelihood of electromigration in word lines due to their inherent roles. Each word line is divided into a plurality of segmented word lines. Each segmented word line is connected to an individual word driver and provided with memory cells, etc. Each of the segmented word lines carries an individual word current from an individual word driver when the word line is rendered to be in a selection state. EP-A 0 025 316 discloses a semiconductor memory device in accordance with the preambuler portion of claim 1. Reference is made, by way of example, to the accompanying drawings, wherein : Fig. 1 is a circuit diagram representing part of a typical semiconductor memory device; Fig. 2A is a partial view of a semiconductor memory device equivalent to that of Fig. 1, but drawn somewhat simpler; Fig. 2B is a diagram depicting the distribution of current density in and along a word line of Fig. 2A; Fig. 3 is a general view of a semiconductor memory device according to the present invention, taking an arbitrary word line as an example; Fig. 4A is a circuit diagram of a part of a semiconductor memory device according to an embodiment of the present invention; Fig. 4B is a diagram depicting the distribution of current density in and along the word line segments of Fig. 4A; Fig. 5 illustrates a detailed example of a known memory cell in Fig. 1; and Fig. 6 is a more detailed circuit diagram of the semiconductor memory device based on the device shown in Fig. 4A . Figure 1 is a circuit diagram representing a part of a typical semiconductor memory device. The memory shown in Fig. 1 is specifically an ECL-type S·RAM. In Fig. 1, reference characters MC indicate memory cells which cooperate with a word line pair WL. Each pair WL is comprised of word lines W+ and W₋. Many identical sets of word line pairs WL and memory cells MC are arranged in the direction along which bit line pairs (BL, BL ) extend. Thus, many memory cells MC are located at cross points of the word lines and the bit line pairs. These memory cells MC constitute a memory cell array, indicated by MCA. In a usual S·RAM, each word line W₋ is arranged with a respective word line W+ as a pair. Each pair of these word lines W+ and W₋ is connected to an individual hold current source HI. The hold current of each source HI enables the maintenance of a logic "1" or "0"/state stored in each memory cell MC. Each word line W+ is selected by a corresponding word selection signal WS given by a word decoder DEC in accordance with an address input AD. The selection is achieved by turning on an individual word driver Q wd connected to the word line W+ at one end. On the other hand, similar drivers, i.e., bit drivers (mentioned hereinafter) are provided for respective bit line pairs BL, BL , in the memory. In a circuit of the Fig.1 type with high integration, there is significant electromogration in the word lines W+. A considerably large current may flow through each word line W+ due to, first, the hold current continually supplied to all the memory cells MC of each word line W+ and, second, a discharge current led to each discharge current source (DI) every time the word line pair WL is selected. In other words, the aforesaid large current along the word line W + is the sum of the hold current (I h ) and the discharge current (I d ) and is generated every time the word line W+ is in a selected state. It should be noted that of the various types of memories, a bipolar ECL-type S·RAM exhibits the largest I h and I d currents. Incidentally, as is well known, the discharge current is useful to effect a quick change from the selection state to the nonselection state. Figure 2A is a partial view of a semiconductor memory device equivalent to that of Fig. 1, but drawn somewhat more simply. Figure 2B is a diagram depicting the distribution of current density in and along the word line WL of Fig. 2A. The memory cell array MCA of Fig. 1 is represented simply as a block "MCA" in Fig. 2A. Also, the hold current source HI and the discharge current source DI are represented simply as a block(current source)"IS" in Fig. 2A. In Fig. 2B, the abscissa denotes positions along the word line WL of Fig. 2A, and the ordinate denotes a current I flowing therethrough. As shown in Figs. 2A and 2B, the peak current density is I max , which is produced at a current supply side of the word line, i.e., the end of the word line to which the word driver Q wd is connected. Figure 3 is a general view of a semiconductor memory device according to the present invention, taking an arbitrary word line as an example. As seen from Fig. 3, the word line WL is divided to form, along its length, a plurality of segmented word lines. Each of the word line segments WL₁ , WL₂ , WL₃ ... WL n , except for the first segment WL₁ activated directly by the word driver Q wd1 , is provided with an individual private word driver, i.e., WD₂ , WD₃ ... WD n . When a word selection signal WS is given to supply a current individually to the memory cells in MCA₁ for the word line segment WL₁ , the first private word driver WD₂ is operated in response to the word line signal appearing at the first word line segment WL₁. At the same time, the second and following private word drivers WD₃ ... WD n are operated in response to the word line signals appearing at preceding word line segments WL₂ , WL₃ ... WL (n-1) (not shown), respectively. In this regard, the memory cell array MCA and the drive current source IS, both shown in Fig. 2A, are segmented as MCA₁ , IS₁; MCA₂ , IS₂; MCA₃ , IS₃; and so on. Figure 4A is a circuit diagram of part of a semiconductor memory device according to an embodiment of the present invention. Figure 4B is a diagram depicting the distribution of current density in and along the word line segments of Fig. 4A. The explanation of Figs. 4A and 4B will, for simplicity, be made taking as an example a case where the memory is segmented into two blocks. That is, a word line WL is divided to form first and second word line segments WL₁ and WL₂. Therefore, the memory cells and the current source are also segmented to form MCA₁ , IS₁ and MCA₂ , IS₂. In a first block, the word driver Q wd1 is connected to the first word line segment WL₁. The word driver WD₂ of Fig. 3 is specifically comprised of a word driver Q wd2 . Other word drivers WD₃ ... WD n of Fig. 3 have identical constructions to that of the word driver WD₂ shown in Fig. 4A, i.e., a single transistor. In the example of Fig. 4A, the distribution of current density is as shown in Fig. 4B. It is important to note that the peak current density in each of the word line segments WL₁ and WL₂ is approximately halved to I max /₂ , the value I max being that obtained in the prior art circuit of Figs.2A and 2B. According to this embodiment of the invention,the word driver transistor Q wd2 is directly connected, at its base, to the preceding word line segment, i.e., WL₁ , so as to activate the transistor Q wd2 in response to the word selection signal WS. That is, when the signal WS is given to the word driver Q wd1 , the word line signal appears with an "H" (high) level at the segment WL₁. The "H" level signal is transferred, via the transistor Q wd2 , to the following word line segment, i.e., WL₂. Thus, the whole corresponding word line WL is selected. The above construction has the advantage that no separate control line is needed to activate the word driver transistor Q wd2 . Referring to Fig. 4A, the word line WL is segmented into WL₁ and WL₂ using the word driver transistor Q wd2 . Therefore, in this case, the voltage level at the word line segment WL₂ is lowered by V BE from that of the word line segment WL₁ , where V BE denotes a base-emitter voltage of the word driver transistor Q wd2 . This lowering of the voltage of the segment WL₂ has a deleterious effect on the operation of the memory cell array MCA₂. This will be further explained with reference to Fig. 5. Figure 5 illustrates a detailed example of the known memory cell MC in Fig. 1. As seen from Fig. 5, each memory cell MC is comprised of multiemitter transistors Q₁ and Q₂ and loads L₁ and L₂. Each of the loads is constituted by both a resistor and a Schottky barrier diode connected in parallel. Assuming here that the transistor Q₁ is now on(the same explanation is similar when transistor Q₂ is on), the voltage difference V WB between the word line W+ and the bit line BL must be higher than a predetermined level so as to maintain the transistor Q₁ conductive during the selection state of the corresponding word line. This predetermined level,V WB , mentioned above is equal to the sum of a voltage drop across the load L₂ and the base-emitter voltage of the transistor Q₁. Even though the predetermined level V WB is assured for the selected memory cell MC in the first memory cell array MCA₁ , it is not assured for the second memory cell array MCA₂. This is because the level V WB is lowered to V' WB expressed as V' WB = V WB - V BE , where V BE denotes the aforesaid base-emitter voltage of the word driver transistor Q wd2 . In this case, an output voltage of each bit driver (mentioned hereinafter) is increased relative to the lowering of V WB , which output voltage is used to determine the voltage of the bit line BL. Due to the relative increase of the output voltage, a bit line driver transistor (mentioned hereinafter) is saturated. Under the saturation state, the read operation speed is reduced. To counter this, in an embodiment of the present invention, a level shifting means is employed in each of the bit drivers cooperating with the memory cell array MCA₂. This also applies to other bit drivers cooperating with the memory cell arrays MCA₃ ... MCA n following thereafter. Thus, the voltage V' WB (= V WB - V BE ) is shifted upward in level by V BE . The aforesaid voltage difference V WB obtained in the memory cell array MCA₁ can thereby also be assured in the memory cell array MCA₂. Figure 6 is a more detailed circuit diagram of a semiconductor memory device based on the device shown in Fig. 4A. In Fig. 6, the bit drivers are specifically illustrated with reference characters BD₁₁ through BD₂₁ through BD 2n . The bit driver transistors in each of the bit drivers are specifically illustrated with reference characters Q BD . The level shifting means is represented by reference characters LS in the block B₂ containing the second Memory cell array MCA₂. It should be understood that only two blocks B₁ and B₂ are illustrated for simplicity and to conform to the example of Fig. 4A. In the first block B₁ , each of the first bit drivers BD₁₁ through BD 1n is constructed by a resistor R, transistor Q, diode D, and a constant current source I. These components are also used in each bit driver in the second block B₂. In the second block B₂ , as previously mentioned, the bit line voltage has a voltage difference of V' WB (= V WB - V BE ) relative to the word line voltage. The thus lowered voltage V' WB must be restored to the nominal voltage V WB , as provided in the first block B₁. For this, a level shift means LS is employed. in each bit driver. The level shift means LS can be realized by diodes, as exemplified in the bit drivers BD₂₁ through B 2n . As is well known, diodes inherently function to shift the voltage level by an amount such as V BE . Therefore, the bit line level can be lowered by V BE with the use of the diode LS, and the voltage difference V' WB can be increased to V WB . In this regard, it will be apparent that, in a third block (B₃), which is not shown but may follow the block B₂ , a similar level shifting means LS should be constituted by two diodes connected in series for producing a shift level of about 2 V BE . As explained above in detail, according to the present invention, the current density in each word line can be considerably reduced. Therefore, the width of each word line can be narrowed further. This enables further miniaturization of an IC memory. It should be noted that the introduction of the individual private word drivers and the buffer gate circuits (BG₁ or BG₂) into the IC memory does not obstruct miniaturization because the word lines usually extend in the IC memory with a considerably large length and considerable space can be saved when reducing the widths of such lengthy word lines. The thus saved space is enough to accommodate the word drivers and the buffer gate circuits.

Claims: A semiconductor memory device, operatively connected to a word decoder (DEC) which generates a word selection signal (WS) at a memory selection time, said memory device comprising:- a plurality of memory cells (MC), each of said memory cells comprising a pair of bipolar transistors (Q₁, Q₂) cross-coupled to form a flip-flop; a plurality of initial word drivers (Q wd1 ), each operatively connected to the word decoder (DEC) and activated by the word selection signal (WS) from the word decoder; a plurality of bit line pairs (BL, BL ) operatively connected to said memory cells (MC); a plurality of bit drivers (BD₁₁, ... BD 2n ), each operatively and respectively connected to one of said bit line pairs (BL, BL ), for sending a bit line selection signal thereto, thereby specifying a desired one of said memory cells (MC) in combination with the word selection signal (WS); a plurality of word lines (WL), operatively and respectively connected to said initial word drivers (Q wd1 ) and said memory cells (MC), forming cross points with said bit line pairs (BL, BL ), said memory cells (MC) being located at the cross points; characterised by:- said word lines (WL) being made out of a material in which electromigration may occur and each being divided into a plurality of word line segments (WL₁, WL₂), a first word line segment (WL₁) of each of said word lines being directly activated to carry a word line signal by one of said initial word drivers (Q wd1 ) in dependence upon the word selection signal (WS); segment word drivers (Q wd2 ) operatively connected between the word line segments (WL₁, WL₂), one of said segment word drivers (Q wd2 ) being activated when the word selection signal (WS) activates a corresponding initial word driver (Q wd1 ) operatively connected via a corresponding first word line segment (WL₁) to the one of said segment word drivers (Q wd2 ), each of said segment word drivers being formed by a single emitter follower transistor operatively connected to a following second word line segment (WL₂) and having a base operatively connected to the corresponding first word line segment (WL₁); and a plurality of level shifting means (LS), provided respectively for ones of said bit drivers (BD₂₁...BD 2n ) connected to bit line pairs (BL, BL ) corresponding to said second word line segments (WL₂), and each operable to lower the level of the bit line selection signal of the respective bit driver relative to the bit line selection signals of ones of said bit drivers (BD₁₁ .... BD 1n ) connected to bit line pairs corresponding to said first word line segments (WL1). A device as set forth in claim 1, wherein each of said level shifting means (LS) provided for bit drivers (BD₂₁...BD 2n ) connected to bit line pairs crossing the second word line segments (WL₂) immediately following the first word line segments, comprises a single diode. A device as set forth in claim 2, wherein each of said bit drivers (BD₂₁...BD 2n ) including one of said level shifting means further includes a first bit driver transistor (Q BD ) operatively connected to one bit line pair in said bit line pairs crossing the second word line segments and having a base operatively connected to said diode in said level shifting means (LS) included therein. A semiconductor memory device as set forth in claim 1,2, or 3, wherein the emitter follower transistor (Q wd1 ) of each first segment word driver has a base operatively connected to receive the word selection signal (WS) and an emitter operatively connected to the first segment (WL₁) of the one of the word lines, and wherein the emitter follower transistor (Q wd2 ) of each second segment word driver has a base operatively connected to the first segment (WL₁) of the respective word line and an emitter operatively connected to the second segment (WL₂) of the respective word line.

Inventors: NAGAHARA, MASAKI, NAKAJIMA, TETSUYA
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: G11C8
IPC codes: G11C8, G11C5, G11C11