DATA COMMUNICATION SYSTEMS

Abstract: In a data communications system an interface unit con­ nects a device to a common communications channel shared with other devices using e.g. a carrier-sense multiple-access protocol. Individual bytes for a predetermined destination de­ vice are supplied by the device to communications controller 6 without any grouping into packets. They are then stored in a RAM 8 under control of a microcomputer 5. As soon as a byte is received, the interface unit attempts to transmit a packet; when the right to transmit is won the interface unit transmits a packet containing that and any subsequent bytes. The length of the packet therefore depends on the delay before a packet can be transmitted, and hence on the loading on the channel.

Description: This invention relates to data communication systems, especially such as are suitable for use as local area computer networks. In such network the devices which are to communicate with one another do so over a communication channel the use of which they share in the time domain. Access to the channel for each device is controlled by some form of interface unit coupled between the device and the channel. Communication takes place by packets transmitted by the interface units according to the particular protocol in use. Though the interface unit often adds information of a framing nature, the data for the packet is supplied by the device, which is responsible for the amount of data to be included in the packet. Various examples of interface devices suitable for use when the protocol is of the type known as carrier-sense multiple-access with collision detection (CSMA/CD) are to be found in Electronics, October 6, 1982, pages 89 to 105. US Patent No. 4 271 507 describes a data communication system in which each interface unit includes a storage buffer for temporarily holding data to be transmitted. When packets are built, all data in the storage buffers, up to a maximum length packet, is sent. This improves the efficiency by reducing the ratio of packet leader length to data length of the packet. The object of the present invention is to provide an improved interface unit for a data communication system, in which the packet length automatically adapts itself to the current conditions in the system. According to the invention there is provided an interface unit (3) for providing an interface between a source device (1) and a communications channel (2), the interface unit comprising: (a) a buffer for storing data received from the source device, (b) means for forming a variable length packet comprising fixed length control information and variable length data, and (c) means for acquiring a right to transmit a packet over the channel and for transmitting a packet when the right is acquired, characterised in that the interface unit initiates action to acquire the right to transmit as soon as data is received and stored in the buffer (4), and in that each transmitted packet includes all the data stored in the buffer and not yet transmitted at the time that the right to transmit is acquired, including any data stored in the buffer subsequently to the initiation of said action. It can be seen that the length of a packet is determined by the loading on the channel. If the loading is very light, packets are likely to contain only one data item. Thus, the overheads imposed by the packet header or other control information are relatively high, but since the channel loading is light this does not matter. However, the delay in transmitting information will be very low. As the load increases, the packets become longer, and hence the fraction of the packets taken up by overheads will decrease. Thus, it can be seen that the length of the packets automatically adjusts itself according to the amount of loading on the channel. The manner in which an interface unit acquires the right to transmit depends on the protocol. For example, the interface unit may initiate action which leads to its acquiring the right to transmit a complete packet. The action may consist in sensing the channel to determine if a signal is already being transmitted (e.g. a carrier-sense multiple access protocol) the right to transmit a complete packet being acquired either when it is detected that there is no such signal, if collision detection is not used, or when transmission has survived the period in which a collision can occur, if collision detection is used. An alternative is for the right to transmit a complete package to be allotted to an interface unit whether or not it wishes to use it. Examples of suitable protocols are polling from a central unit or token passing in a decentralised system. One example of a system constructed and operating in accordance with the invention will now be described in greater detail with reference to the accompanying drawings, in which Figure 1 is an overall block diagram of the system; Figure 2 is a block diagram of the interface unit of the system; and Figure 3 is a diagram of the buffer storage of the interface system. Overall System Referring to Figure 1, this example of a system in accordance with the invention is a local area network in which a number of devices 1 communicate with one another over a common bus 2. The devices may, for example, be computer processors, computer peripherals or terminals. Each device 1 is connected to the bus through an interface unit 3 which transmits data from the device 1 onto the bus and passes data from the bus to the device 1 if the data is addressed to the device. The interface units 3 control access to the bus jointly in a decentralised manner using a protocol of the CSMA/CD (carrier-sense multiple-access with collision detection) type. As shown in Figure 3 there is only one device 1 for each interface unit 3. However a group of devices 1 may share a common interface unit 3. If a device 1 wishes to communicate with another of the devices 1 a connection between the two is first established by messages passed between their interface devices 3. Thereafter either of the devices simply passes data for the other to its own interface unit which formulates the data into packets and transmits them over the bus. The data is passed from a device 1 to its interface unit in individual data units. The interface unit stores the data units as it receives them in a first-in first-out transmit buffer (FIFO) 4. Following the CSMA/CD protocol used in this system, as soon as the interface unit 3 has received and stored a data unit in its buffer 4 it attempts to transmit it. The interface unit senses the bus and if it detects that no signal is being carried by the bus it transmits a packet containing the data unit together with framing, addressing and control information. However, if a signal is detected the interface unit waits until the bus is silent before starting to transmit. Provided no other unit starts to transmit at the same time a complete packet will be transmitted; otherwise the resulting collision is detected by the interface units concerned which abandon their transmissions, back off for differing periods and then make further attempts to transmit. If an interface unit does not acquire the right to transmit as soon as it receives a data unit in the buffer 4 it is likely to receive further data units before it succeeds in transmitting. When it does succeed it will include all these data units in the packet together with the framing information and other overheads. Consequently the length of a packet is not fixed, but varies with the load carried by the bus. If the loading is very light, packets are likely to contain only one data byte. The fraction of the time spent transmitting packets that is occupied by overheads rather than data from the device will therefore be relatively high, but at a time when that does not matter. However, the delay in transferring information across the network will be very low. On the other hand, when the load increases and contention occurs, the packets will become longer and the fraction of the packets taken up by overheads will shrink. The devices themselves are not concerned in determining the packet length: they simply pass the data units to their interface units, which group them into packets without regard to their significance to the originating device. To the devices themselves the data units are likely to form part of longer messages in whatever higher level protocol is in use. These messages may contain actual user data or they may be control messages such as, for example Xon and Xoff. However, the interface units do not know, or need to know, where the breaks between the messages come. Although the system will normally operate as described it is convenient to impose an upper limit on the number of data units that can be included in a packet. Structure of the interface unit Referring to Figure 2 the interface unit has a microcomputer 5, a serial communications controller 6, an external read-only memory (ROM) 7, an external random-access memory (RAM) 8, an address bus 9 and a data bus 10. Address signals for the ROM 7 and RAM 8 are obtained partly from the address bus 9 and partly from an address latch 11 loaded in the known manner from the data bus 10. The ROM 7 holds the program for the microcomputer 5. The RAM 8, in conjunction with address pointers held in the internal storage of the microcomputer 5 (as will be explained in more detail subsequently) implements the transmit buffer 4 and a similar buffer for data received from the network. The microcomputer 5 selects the individual components to write to them or read them by issuing signals to a select logic circuit 12, which consists as is well known in microcomputer based units, of standard combinational logic to decode the signals received and output the required signals to the individual units. Suitable components for the microcomputer 5 and controller 6 are available commercially. For example, the microcomputer 5 may be an Intel 8031 and the controller 6 may be an AmZ8530. The controller 6 has two serial ports. One port is connected by a set of incoming lines 13 and a set of outgoing lines 14 to the device 1 asociated with this controller. One line of each set 13 or 14 carries serial data and the remainder are control lines. These lines may, for example, be in accordance with the RS232C standard interface. The other port outputs serial data for the bus 2 on a line 15 and receives serial data from it on a line 16. Data output on the line 15 is encoded in an encoder 17. Data from the bus 2 is decoded in a decoder 18. The encoding and decoding may be as described in our copending British patent application No.8212263 - publication No. 2 120 053. The encoder 17 and decoder 18 are coupled to the bus 2, which may be a simple twisted pair, through transformers. The signal sent by the encoder 17 is received from the bus by the decoder 18. The carrier-sense part of the access protocol for the bus 2 is carried out by a busy detector circuit 19. This circuit is connected to the lines 15 and 16 from the network and outputs a signal BUSY if it detects activity on the line 16 which has not been generated by the encoder 17. BUSY is applied to the encoder 17 to inhibit transmission from the encoder 17. The busy detector circuit 19 contains a delay circuit, implemented as a counter which is held at zero while there is activity on the line 16 but starts to count when the activity ceases. When the counter reaches a preset value the BUSY signal is removed allowing the controller 6 to start transmission over the line 15. The delay introduced by the counter allows the microcomputer 5 to finish dealing with existing tasks such as the receipt of incoming information. The collision-detection part of the access protocol for the bus 2 is carried out by a mismatch detector 20 connected between the lines 15 and 16 and arranged to compare the signal sent over the line 15 with that received (after encoding and decoding delays) on the line 16. If the two do not match the packet has not been transmitted correctly and a signal CLASH is output and supplied Co the microcomputer 5 as an interrupt. The reason for the mismatch may be a collision with a packet from another station, or the mismatch may have occurred for some other reason, for example because noise has corrupted a transmitted packet. Any attempt to transmit while BUSY is set is also reported to the microcomputer via CLASH since the transmitted message will not equal the silence (or other unit's packet) that is received. Two further inputs to the microcomputer 5 both originate from the controller 6. One, to a second interrupt input, is a signal INT produced by the controller 6 when it starts to receive a packet from the network. The second is a signal DATA AVAILABLE/REQUEST which doubles as an indication that the controller 6 has a byte available from the network (during reception of a packet) or requires the next byte (during transmission of a packet). The microcomputer 5 controls the controller 6 in the known manner by writing data into a command register in the controller. Message format Before describing the operation of the system it is helpful to set out the format of a packet as transmitted by the interface unit. It consists of the following sequence of fields: The control field indicates the type of packet. Only when it has the value 5 does it carry user data from the associated device. Values 1 to 3 are concerned with controlling the link between the two communicating devices. The use of the value 6 inindicates the type of packet. Only when it has the value 5 does it carry user data from the associated device. Values 1 to 3 are concerned with controlling the link between the two communicating devices. The use of the value 6 in the control field and the meaning of the sequence numbers will be described in more detail subsequently. The flags and the cyclic redundancy check field are supplied by the communications controller 6. The intervening fields are supplied by the microcomputer 5; as supplied they have the form given above, but before transmitting them the controller 6 subjects them to bit stuffing to ensure that the flag pattern does not appear between the opening and closing flags. The use of flags and bit stuffing in this manner is well known in bit-oriented protocols such as that used here. When data is received from the network the controller 6 "destuffs" the data (i.e. removes the bits inserted for bit stuffing) and checks the cyclic redundancy check field. Operation of the system The communications controller 6 assembles the individual data bits received from the associated device 1 into bytes in an internal buffer. The microcomputer 5 polls the controller 6 at frequent intervals and if it discovers that a complete byte is held it transfers the byte to itself. The microcomputer 5 also checks if the state of any of the control lines has been changed. When the asociated device 1 wishes to communicate with another device 1 it signals to the interface unit 3 over the control lines and supplies the address of the other device. The microcomputer 5 then sends a packet to the interface unit 3 of the other device. If that is able to make a connection the far interface unit 3 returns an acknowledgement and sets the output control lines to its associated device 1 in response to the line indicators field of the packet to reproduce the state of the incoming control lines at the near end. The far device replies to indicate if it is ready to receive data and, if so, the connection between the two devices is established. The details of the dialogue are similar to those by which a virtual point-to-point connection is established in other networks and will not be described further. In general, for all packets, the microcomputer 5 obtains the source address from a hardwired input and the destination address from internal storage. A change in the state of an input control line always leads to a packet's being sent and the corresponding output control lines at the far end being altered, so that (subject to a delay) the devices 1 seem directly connected by their lines 13 and 14. Assume now that a connection is established between two devices and one wishes to send data to the other. It then simply passes the data bytes bit-serially to the communications controller 6. When that has assembled a byte the microcomputer 5 transfers it to itself and then writes it into a section of the RAM 8 which forms the transmit buffer 4 (see also Fig.3). The byte is written into a location whose address is stored in a location 30 in the internal storage of the microcomputer 5. A location 31 in the internal storage of the microcomputer 5 holds the address of the next byte to be transmitted. As soon as a byte has been transferred into the RAM 8 the microcomputer 5 will signal to the controller 6 to send a packet. If BUSY is asserted the controller 6 will be unable to transmit. Otherwise it will send the opening flag and then call over the DATA AVAILABLE/REQUEST line for the next and each subsequent byte of data as it is needed. The microcomputer 5 monitors this line, and each time a byte is requested supplies it. It supplies the initial control fields itself and then retrieves the data byte from the address indicated by the location 31. Assuming that is the only untransmitted byte the microcomputers then signals the controller 6 to end the packet, which causes the controller 6 to send the check field and the closing flag. If a collision occurs the CLASH signal is generated, a burst of jamming is initiated and the microcomputer 5 is interrupted. It abandons the attempt to transmit and waits for a period before again attempting to transmit in the manner explained. Any suitable known back-off procedure may be used, though we prefer to make the back-off period proportional to the device address, with the constant of proportionality doubled (for two steps) on each failure to transmit and halved on each success. This is an especially simple method of attempting to separate competing stations. If the microcomputer is waiting because the bus is busy or a collision has occurred it will write any further bytes received from the associated device 1 into the RAM 8, incrementing the address pointer in the location 30 as it does so. When it then finally succeeds in transmitting it will retrieve each of these bytes in turn for dispatch to the controller 6. During this procedure, for reasons of speed the address concerned is held in an internal register whose contents are incremented as each byte is stored. At the end of the packet the location 31 is updated with the contents of this register. The arrival of a packet at the interface unit 3 from the network causes the signal INT to interrrupt the microcomputer 5, which then monitors the DATA AVAILABLE/ REQUEST line, and retrieves the bytes of the packet as they are received following the flag. If the packet is addressed to the associated device the data is written into a receiver buffer 32 section of the RAM 8 starting at the address whose value is held in a location 33 in the microcomputer 5. During arrival of the packet the buffer address is again obtained from the internal register and the location 33 is updated at the end of the packet. After the packet has been received the individual bytes are transferred one by one to the associated device using the contents of a location 34 in the microcomputer's internal storage as the address pointer. Bytes for transmission over the network are numbered in sequence modulo the size of the transmit buffer 4, which is filled cyclically, so the sequence number of a byte equals its address in the transmit buffer 4. The sequence number of the first byte of each packet is included in its transmit number field. If the receiving interface unit detects an error in the sequence number (for example because a packet has been lost through noise) it sends a sequence error packet (control field = 6) indicating the lowest sequence number not correctly received. The transmitting unit then sends a packet repeating the data units starting from that number. Provided packets are received in sequence the far device returns the sequence number of the last data byte passed to its device in the acknowledgement sequence number field of its next packet containing data. If the far device is temporarily silent, data frames with no data are sent at regular intervals to acknowledge successful receipt. A limit may be placed on the number of bytes passed to the far device without its interface unit 3 attempting to acknowledge successful receipt. In an alternative arrangement, the acknowledgement sequence number field contains the sequence number of the last data byte received from the bus 2. Unacknowledged bytes must not be overwritten in the transmit buffer 4 since they may need to be retransmitted. So the microcomputer 5 holds the address of the last byte acknowledged in a location 35, and if it is in danger of being overwritten signals the associated device to pause. Various limitations are imposed on the number of bytes in a packet. First, there is an upper limit on the number that may be included. When that limit is reached no more data is included in the packet and the unit must make a later attempt to transmit any further bytes that are stored. Secondly, packets are split at the boundary of the transmit buffer. However, in normal operation while none of these limits are exceeded each packet contains all those bytes stored in the transmit buffer at the time the unit acquires the right to transmit a complete packet; that is, those bytes which have been stored since it last sent a data packet. As an example of suitable numbers, the maximum number of data bytes in a packet may be 32, the transmit or buffer and receive buffer may each hold 256 bytes and the largest allowable number of unacknowledged bytes may be 128. Modifications Any of the known methods of carrier sensing and collision detection may be used in the place of those described. The system described may be modified by applying BUSY to unset a clear-to-send input on the controller 6, thereby inhibiting transmission on the line 15. Another possibility is to supply BUSY to the microcomputer 5. It may then itself cause transmission to be postponed. The system described may be modified to carry out a simple CSMA protocol if the mismatch detector is omitted. Units then depend on the absence of an acknowledgement to detect a collision. It is convenient in that case for an acknowledgement to be returned in the period immediately after the transmission in which other units are prevented from transmitting. If the busy and mismatch detectors are replaced by apparatus for recognising and generating tokens the system may be used as a token ring or bus. As in tee case of a ring, the communications channel may provide a more complicated interconnection medium than a simple passive bus. It will be realised that the address pointers for the transmit and receive buffers may be implemented as special purpose registers rather than in the microcomputer 5. In the system so far described, only data addressed to a device is written into its receive buffer 32. As an alternative, each interface unit 3 writes all received packets into its receive buffer 32. This allows the microcomputer 5 to interrogate the controller 6 in the known manner to test the cyclic redundancy check before examining the packet's address fields. Only if the check shows a valid packet and the packet is addressed to the associated device is the location 33 updated. This arrangement also has advantages in speed during reception of a packet, but does require that all interface units 3 ensure that there is always sufficient free space in their receive buffer 32 to receive a maximum length packet. One or more of the devices 1, instead of being a source or sink of data, may be a gateway to another network. For example, two interface units as described may be connected together to interconnect networks to which they are coupled. The acknowledgement sequence field may be omitted and acknowledgements sent as separate high-level messages to the device itself, which then informs its interface unit. That however requires some involvement of the device in details of the low-level protocol. Alternatively, the interface units themselves may send separate acknowledgement messages.

Claims: An interface unit (3) for providing an interface between a source device (1) and a communications channel (2), the interface unit comprising: (a) a buffer for storing data received from the source device, (b) means for forming a variable length packet comprising fixed length control information and variable length data, and (c) means for acquiring a right to transmit a packet over the channel and for transmitting a packet when the right is acquired, characterised in that the interface unit initiates action to acquire the right to transmit as soon as data is received and stored in the buffer (4), and in that each transmitted packet includes all the data stored in the buffer and not yet transmitted at the time that the right to transmit is acquired, including any data stored in the buffer subsequently to the initiation of said action. An interface unit (3) for providing an interface between a source device (1) and a communications channel (2), the interface unit comprising: (a) a buffer for storing data received from the source device, (b) means for forming a variable length packet comprising fixed length control information and variable length data, and (c) means for acquiring a right to transmit a packet over the channel and for transmitting a packet when the right is acquired, (d) means for detecting an unsuccessful transmission of a packet and for initiating retransmission of the packet, characterised in that each retransmitted packet includes all the data stored in the buffer and not yet transmitted, including any further data stored in the buffer subsequently to the initial transmission of the packet A data communications system comprising: (a) a communications channel (2), (b) a plurality of communicating devices (1), and, (c) a plurality of interface units (3) interconnecting the devices (1) to the channel (2), each of the interface units being as claimed in either preceding claim.

Inventors: RUSSELL, BRIAN MONTGOMERY
Applicants: INTERNATIONAL COMPUTERS LIMITED
Application year: 1984
Main classification: H04L12
IPC codes: H04L12