MICROCOMPUTER INTERFACE ARRANGEMENT

Abstract: An interface arrangement (16) for connecting an external device to an existing microcomputer (14) and, in particular, for interfacing the microcomputer (14) with a local area network (12). The interface arrangement (16) includes a socket (20) for receiving a microprocessor (22) of the microcomputer (14) after removal of the microprocessor from the microcomputer, and interconnection means (26, 28) arranged to plug into the microcomputer socket (24) vacated by removal of the microprocessor (22). The microprocessor (22) when received in the socket (20) of the interface arrangement (16) can communicate, via the interconnection means (26, 28) with the remainder of the microcomputer (14) so as to continue to operate in the same manner as when installed in the microcomputer. The interface arrangement (16) also includes circuitry (47, 100) for enabling data transfer to be selectively established by the microcomputer between itself and an external device, such as a file server, without causing undesired operations within the microcomputer (14). The coupling of the interface arrangement (16) into the vacated microprocessor socket (24) of the microcomputer (14) means that the hardware details of the interface arrangement (16) are dependent only on microprocessor type and not on the microcomputer design.

Description: MICROCOMPUTER INTERFACE ARRANGEMENT. The present invention relates to a microcomputer interface arrangement for connection to an existing microcomputer to enable data to be transferred to/from the microcomputer; in particular, but not exclusively, the invention relates to an interface arrangement for interfacing an existing microcomputer with a microcomputer local area network. Microcomputer local area networks. (LANs) are networks in which a plurality of microcomputers are connected by a link (such as a cable) to a central storage device to which the computers have access as required to read data from or write data into the storage device.. Such networks not only provide administrative and technical advantages stemming from centralised data storage, but also enable the local storage facilities of at least some of the member microcomputers to be enlarged and/or improved. The central storage device, which may at least partially control the access process, is referred to in the art (and also herein) as a "file server". With the current proliferation of various different sorts of microcomputers of different designs and manufacturers and using different microprocessors, the implementation of. LANs can present a severe compatibility problem. This problem is so severe that potential purchasers of microcomputers who contemplate installing a LAN may feel compelled always to purchase the same type of microcomputer as before even if other considerations, technical or commercial, might dictate otherwise. This is because, with known LANs, the file server is generally compatible only with a particular design of microcomputer whereby only microcomputers of that particular design can in practice be integrated into the network. The potential user of a LAN may therefore be faced with the option of either doing without the LAN or spending a great deal of money in replacing otherwise perfectly acceptable microcomputers. More generally, the interfacing of any device with a range of microcomputers will usually present severe compatability problems due to the variety of bus and-- interface designs adopted by different manufacturers. It is therefore an object of the present invention to provide an interface arrangement facilitating the interconnection of an external device (such as a file server) with various different microcomputers. According to the present invention there is provided a microcomputer interface arrangement for connection to an existing microcomputer to enable data to be transferred to/from the microcomputer, characterised in that said interface arrangement comprises: - interconnection means for coupling the interface arrangement to the location in the microcomputer which becomes vacant on removal from the microcomputer of a microprocessor thereof; - receiving means for receiving the said microprocessor of the microcomputer or a functional equivalent thereof, the interconnection means, when coupled to said microcomputer location, serving to interconnect the microcomputer with the microprocessor received by said receiving means, in such a manner that the microcomputer can continue to operate in substantially the same manner as prior to connection to the interface arrangement, and - interface circuitry for enabling data transfer to be selectively established to/from the microcomputer without thereby causing undesired operations within the microcomputer. The coupling of the interface arrangement into the microcomputer location vacated in removal of the microprocessor means that the hardware configuration of the interface arrangement is not dependant on the particular bus structure adopted by the microcomputer manufacture but will be the same for all microcomputers using the same type of microprocessor. Even with different types of microprocessors, the hardware modifications required are generally not extensive . Thus, the interface arrangement of the invention considerably eases the problem of connecting an external device (such as a file server) to a variety of different microcomputers. Although the interface arrangement of the invention will generally be used to interface an external device with a microcomputer (.for which purpose the interface circuitry of the interface arrangement will normally comprise some form of I/O port), the interface arrangement can also be used to interface a microcomputer with an expansion module, such as a specialised processor or memory expansion board, requiring direct access to the microcomputers address and data buseβ. The said receiving means of-.the interface arrangement is preferably a socket that conforms electrically and mechanically to a like socket for the microprocessor provided in the microcomputer. The interconnection means may in this case comprise a cable or the like terminated by a plug that will mate with the socket of the microcomputer. With certain designs of microcomputer and for certain interfacestructures, the situation can arise that the control signals generated in the interface arrangement and fed onto the microprocessor bus during data transfer through the interface, could, if fed back to the remainder of the microcomputer, cause spurious operations within the microcomputer (this is possible since the original design of the - microcomputer would not have envisaged the addition of the circuitryof the interface arrangement). To avoid any possibility of such spurious operations being brought about by this data transfer, the interface arrangement is made transparent to the microcomputer. To this end the said interface circuitry preferably includes control means operative during data transfer to/from the microcomputer to influence or isolate at least certain ones of the control lines passing from the microcomputer to the microprocessor received in the interface arrangement such as to prevent undesired operations within the microcomputer. The interface circuitry can be operated under the control of a piece of software (or firmware) that can be considered as an auxiliary or supplementary operating system to that of the microcomputer and which can be loaded on top of the operating system of the microcomputer, The auxiliary or supplementary operating system can then be considered to be hooked on to the "host" operating system to control a roαtine or loop in which access to the remote storage provided by the file server is desired. The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which like references designate like items throughout, and in which: Figure 1 is a block diagram of a local area network (LAN) ; Figure 2 is a view, partially in perspective, showing how a LAN interface embodying this invention is coupled to a host microcomputer; Figure 3 is a block diagram of a first form of the LAN interface, showing it connected to the host microcomputer and to a cable of the LAN; Figure 4 is a block diagram similar to Figure 3 but showing a second form of the LAN interface, and Figure 5 shows diagrammatically the manner of interaction between the operating system of the host microcomputer and an auxiliary operating system controlling the LAN interface. Figure 1 shows a microcomputer local area network (LAN) that includes a file server 10 connected to a 75 ohm coaxial cable 12. A plurality of microcomputers 14, for example up to 254 of them, are each connected to the cable 12 by a respective LAN interface 16 that includes 3- reed relay 18 connected as shown to enable the associated microcomputer 14 to break the cable 12. Each of the microcomputers 14 can generally operate on a "stand-alone" basis. It can however also obtain access to central storage means within the file server 10 so as to write to and/or read therefrom. Such central storage means may for example comprise one or more high capacity "Winchester" type rigid discs. As well as the central storage means, the file server 10 comprises a random access memory (RAM) and a microprocessor. The file server 10 incorporates software- and/or firmware- controlled circuitry that controls access of the OMPI microcomputers 14 to the central storage means in the file server 10 in the following manner. The file server 10 periodically transmits a form of signal known as a "general poll". This is received by all the microcomputers 14 connected to the file server 10 and all those microcomputers that then require access to the file server 10 respond to the general poll. However, before responding, each microcomputer 14 wishing to do so, isolates that whole part of the LAN downstream of itself (i.e. on the opposite side of itself to the file server 10) by opening the associated reed relay 18. After waiting for an appropriate time interval (e.g. 1 millisecond) for the reed relay 18 to stabilise, the microcomputer 14 responds to the general poll from the file server 10 by outputting a signal that uniquely identifies the responding microcomputer 14, such unique hardware identity being, to this end, coded in the associated LAN interface 16. The reed relay 18 is thereafter closed. Clearly, that microcomputer nearest to the file server 10 is able to answer the general poll first, although all responding microcomputers immediately close their reed relays and wait for an acceptance signal from the file -server 10. The file server 10, on accepting and acknowledging the first data request, that is to say accepting and acknowledging the notification from the first responding microcomputer 14 that it wishes to access the central storage means in the file server 10, issues a second general poll. The second general poll is ignored by the microcomputer 14 whose request has been acknowledged and will instead cause all of the other microcomputers 14 that still require access to repeat their requests as described above. The response of the next nearest microcomputer 14 is the accepted by the file server 10. This process is repeated until n© more access requests are received by the file server 10, which indicates that all the microcomputers 14 wishing to respond now have their identities and access requests lodged in the RAM of the file server 10. The above-described interrogation process ensures optimum, minimal polling of the connected microcomputers 14 and obviates any need for the file server 10 to know the identity and numbers of the attached microcomputers. The RAM capacity within the file server 10 is, for example, adequate to store over 100 such access requests and hardware identities, though the file server 10 may have software that will permit up to 254 microcomputers 14 to be connected by subsequently implementing an "exclusion polling" process after the RAM within the file server 10 is full. The file server 10 is also able to sort the stored access requests into the most appropriate sequence for subsequent minimal disc head movement. That is to say, that request that involves access to the address nearest to the current position of a disc head, reading the Winchester disc within the file server 10 will be processed first; and so on. This sorting operating can be carried out during the polling process, thereby optimising processing time of the microprocessor of the file server 10. Similarly, once accessing of the Winchester disc within the file server 10 is commenced, further time optimisation is possible because the relevant data can be transferred directly to and from the relevant microcomputer 14 (as described below) while the process of disc head movement is being performed. Such data transfer may involve the reading from disc within the file server 10 as a result of a request from a microcomputer 14, or the writing to such disc of data from the microcomputer 14. The LAN of Figure 1 , which is of known construction as so far described, is .a highly efficient data retrieval system for the microcomputers 14 thereof, relieving them of the necessity always to use the slower and less reliable floppy disc storage with which they are generally provided, while also providing them with increased storage capacity, more convenient central files and shared access to common files. A more detailed description will now be given, of the LAN interface 16 with reference to Figures 2 to 5. Referring first to Figure 2, the LAN interface 16 includes a circuit board 19 mounting a socket 20, typically a 40-way socket. The socket 20 is so dimensioned and wired as to accommodate the particular design of microprocessor, chip fitted within the associated microcomputer 14, hereinafter also referred to as. "the host microcomputer". To prepare the microcomputer 14 for connection to the LAN, the LAN interface board 19 is installed in or adjacent to the microcomputer 14. The microprocessor 22 of the host microcomputer 14, which in conventional manner will generally be removably located in a socket 24 in a processor board of the host microcomputer, is removed therefrom and fitted into the socket 20 in the interface board 19. A ribbon cable 26 extends from the LAN interface board 18 to a plug 28. The plug 28 conforms electrically and mechanically to the socket 24 in the microcomputer 14 and is caused to mate with the socket 24. The pattern of connections and so forth is such that, when the microcomputer 14 does not require access to the file server 10 via the LAN, all signals are permitted to go between the.microprocessor 22 (in its new position) and its original socket 24 without impediment, the microprocessor 22 and the microcomputer 14 thus functioning precisely as if the LAN interface 16 were not there. When, however, the microcomputer 14 indicates that it requires access to the file server 10, the behaviour of the microprocessor 22 is modified, as described hereinbelow. This approach has the advantage that a single design of LAN interface board 19 will work for any implementation of a particular microprocessor, whereas a bus-orientated approach would require a different design of board for each bus implementation. For example, different microcomputers 14 employing the whole range of Z80 microprocessors can be handled by a single design of LAN interface board 19. The construction of two forms of the LAN interface 16 (together also with the construction, of the host computer 14, in so far as it is relevant) will now be described in more detail with reference to Figures 3 and 4. Considering first the LAN interface 16 shown in Figure 3, this interface is designed for use with a microcomputer 14 whose microprocessor or central processing unit (CPU) 22 is a Z80 microprocessor. In conventional manner, the microcomputer 14 includes a memory 30, for example a read only memory (ROM) or random access memory (RAM) , in whichit.stores its own operating system, hereinafter also referred to as "the host operating system" , and a RAM 32 having a data bus 34 and an address bus 36 connected thereto. As explained above, the CPU 22 of the microcomputer 14 is re-located on the board of the LAN interface 16. However, the CPU 22 remains connected to the microcomputer 14 by way of the ribbon cable 26, the plug 28 and the socket 24 ' , which connections include the above-mentioned data bus 34 and address bus 36 together with a control OMPI bus 38 and various other conventional connections (e.g. power supply lines and so forth) in conventional manner. The LAN interface 16 includes a serial I/O port 47 of standard form for effecting synchronous communication with the file server 10. In the present example, the I/O port 47 conforms to the SDLC (Synchronous Data Link Control) protocol and is built around an SDLC chip 48 such as the known Western Digital WD 1933B chip. The SDLC 48 interfaces with the reed relay 18 and cable 12 of the local area network through an interface 52 that is connected to the SDLC 48 by a transmit line 54, a receive line 56, and a relay control line 55. Connected to the interface 52 is a .crystal clock 58 that is synchronised by the signals in the cable 12 and that defines an optimum fast data transfer speed that is employed when, in the manner described below, a data transfer is to take place. between the file server 10 and the microcomputer 14. Such transfer speed is independent of the clock or processing speed at which the CPU 22 is operated by the host microcomputer 14. The above-mentioned means for indicating the unique hardware identity of the LAN interface 16 to the file server 10 in response to the aforesaid general poll signal may be embodied in or associated with the SDLC 48. The SDLC 48 interfaces with the microprocessor 22 via the microprocessorsbuses 34, 36, 38 with the data bus 34 and the Read (RD) and Write(WR)control line, 51, 53 being connected directly to the SDLC 48, the address bus 36 and I/O Request (IORQ) line 55 being connected to the SDLC 48 via an address decoder 50, and the WAIT control line (WAIT) 57 being connected via a wait control circuit 59. The address decoder 50 is of standard form and has a chip select output 102 which is enabled whenever any one of the internal registers of the SDLC 48 is addressed; the precise identity of the addressed register is determined by the signals on the three least significant address lines 104. The wait control circuit 59 serves to generate a WAIT signal to temporarily suspend operation of the CPU 22 whenever the CPU 22 attempts to read from, or write to, the SDLC 48 (as indicated by the output 102 of the decoder 50) before the latter is ready to output or receive a data byte (the ready state of the SDLC 48 being indicated, for example, via an interrupt line 106). In addition to the I/O port 47, the circuitry of the LAN interface 16 comprises an electronic switch 100 inserted in the Read, Write, I/O Request, and WAIT control lines of the control bus 38 that pass via the cable 26 to the microcomputer 14. The operation of the electronic switch 100 is controlled by the output 102 of the address decoder 50 such that whenever the SDLC 48 is addressed, the electronic switch 100 is opened to isolate the Read, Write, I/O Request, and Wait lines from the microcomputer 14; in all other circumstances, the switch 100 is closed. Some or all of the various above-mentioned components of the LAN interface 16 may be mounted on the board 19 OMPI - (Figure 2) together with the socket 20. The manner of operation of the LAN interface 16 of Figure 3 will now be described. As mentioned above, when the microcomputer 14 does not wish to access the file server 10 the CPU 22 is connected via the ribbon cable 26 to the remainder of the microcomputer 14 just as if the LAN interface were not there. However, when the microcomputer 14 indicates that it wishes to obtain access to the file server 10, which it does by generating an appropriate data input or output (1/0) request, the LAN interface 16 takes over control. The LAN data transfer is in fact conducted under the control of an auxiliary operating system, in a manner described hereinbelow with reference to Figure 5, which auxiliary operating system is for convenience loaded on top of the host operating system, and which serves to configure the DMAC 40 and SDLC 48 and prepares them for LAN data transfers. The auxiliary operating system may be stored with the host operating system in the memory 30, which is a ROM or RAM. More generally, the two operating systems may be both stored in RAM, both stored in ROM, or stored one in RAM and one in ROM, as desired. The LAN interface 16 effects a LAN data transfer as follows. A LAN data transfer is initiated when the microcomputer causes the CPU 22 to execute the auxiliary operating system. This auxiliary operating system controls the CPU 22 to set up the SDLC 48 for data reception/transmission as required, with data being moved between the microcomputer memory 32 and the SDLC 48 via the CPU 22 itself. The general interaction of the CPU 22 with the remainder of the microcomputer 14 and with the SDLC 48 accords with standard practice "gυREΛ and will not be described in detail herein. Similarly, the handshake routines executed between the interface 16 and the file server 10, and the procedures for data and recovery are all handled by the auxiliary operating system in standard manner. Thus, the first operation set up by the auxiliary operating system is to set the SDLC 48 into a receiving mode to listen for a general poll from the file server 10, the bytes received by the SDLC 48 being transferred by the CPU 22 in turn into the memory 32 and then checked under the control of the auxiliary operating system to see if they constitute a general poll. If this is the case, the SDLC 48 is set up to transmit an access request after which the SDLC is returned to its receiving mode to listen out for an acknowledgement from the file server 10. Once access is gained to the file server, the desired data transfer is effected between the microcomputer 14 and the file server 10. Upon completion of the LAN data transfer, the CPU 22 exits from the auxiliary operating system and normal working of the microcomputer 14 resumes. Note that the LAN data transfer takes place at a speed determined by the clock 58 which is preferably a high value to.provide high-speed LAN data transfer (typically 625,000 bits/sec). Throughout the running of the auxiliary operating system, whenever the SDLC 48 is addressed, the control lines 51, 53, 55 and 57 required for its operation are isolated from the microcomputer 14 thereby ensuring that no undesired operations can possibly occur within the microcomputer as a result of operation of the I/O port 47. In other words, the interface 16 is, for all practical purposes, transparent to the host microcomputer 14. OMPI It will be appreciated that the danger of improper operation of the microcomputer 14 during addressing of the I/O port 47 results from the fact that the design of the microcomputer will not have taken into account the various bus signal states which might arise due to the presence of the I/O port 47. Thus, even though the internal registers of the SDLC 48 are allotted addresses unique to the overall system constituted by the microcomputer 14 and interface 16, problems could still arise, for example, where data bus buffers are used in the host microcomputer 14 since should these be enabled when the CPU 22 attempts to read an internal register of the SDLC 48, a conflict will arise between the buffers and the. SDLC output. Another possible source of conflict is where the microcomputer circuitry tries to impose a WAIT (that is, a ready signal) on the WAIT line when the circuitry 59 wishes to impose a WAIT signal. By interrupting all the control lines used by the SDLC 48 during addressing of the latter, all potential conflicts are avoided. It has been assumed that, with the arrangement of Figure 3, the CPU 22 is sufficiently fast to control LAN data transfer at a speed as high as that employed by the file server 10. However, this will often not be the case since many designs of CPU 22 are not suitably fast in responding to an I/O data transfer (and may not have a suitable software-instruction set). In this case, a DMA (Direct Memory Access) controller will need to be used to transfer data between the SDLC 48 and the microcomputer memory 32, the CPU 22 being inhibited during operation of the DMA controller. Note however that the clock 58 would still dictate the actual LAN data transfer speed. The form of LAN interface 16 shown in Figure 4 utilises a DMA controller (DMAC) 40 for effecting data transfer OMPI between the SDLC 48 of the I/O port 47 and the microcomputer memory 32. The specific example illustrated relates to a CPU 22 constituted by an Intel 8085 microprocessor, the DMAC 40 being,for example, constituted by an Intel 8237 chip. A particular characteristic of the 8085 microprocessor is that eight of the 16 address lines are multiplexed between the low byte of address and the data lines; a control signal ALE (address latch enable) when asserted indicates the presence of an address on the multiplexed lines and is used to set the low address byte into a latch. Thus in Figure 4 the microcomputer 14, in addition to the elements 24, 30, 32, illustrated in Figure 3, is shown as having an address latch which forms part of a unit 81 that also includes bus buffers; the address latch is controlled by the control bus signal ALE and the direction of signal throughput of the buffers is controlled by the control-bus WR (Write) signal. The functional cooperation of the CPU 22 with the DMAC 40 and the 1/0 port 47 during LAN data transfers under the auxiliary operating system, is in general terms fairly standard with the DMAC 40 responding to a data transfer request from the SDLC (via line 82) by gaining mastery of the microprocessor buses 34, 36, 38 using the HOLD and HLDA (Hold Acknowledge) control lines (the latter passing to the DMAC 40 as part of a local control bus referenced 83 in Fig. 4). Once bus mastery has been gained, the DMAC 40 transfers a byte to/from the SDLC 48 and then hands back control to the CPU 22 which then proceeds to check the status register of the DMAC 40 to ascertain whether data transfer is complete. If data transfer is not complete, then the CPU 22 waits to hand back control to the DMAC 40 upon a subsequent OMPI transfer request being received by the DMAC from the SDLC 48. Of course, the illustrated arrangement of CPU 22, DMAC 40 and SDLC is more complicated than is normally the case since the DMAC and I/O port usually reside downstream of the address latch associated with the CPU 22 and thus receive de-multiplexed address and data signals. With the present' LAN interface 16, the signals appearing on the address and data buses 34, 36 on the board 19 are multiplexed address and data signals which must therefore be demultiplexed by an additional latch and buffer unit 85 before feeding to the DMAC 40 and SDLC 48. The position is further complicated by the fact that it is now necessary to generate an ALE signal during DMA transfers to enable address and data signals to pass through both units 81, 85 (such a signal is, of course, unnecessary in a microcomputer where the DMAC and SDLC both reside downstream of the unit 81). The generation of the ALE signal required during DMA transfers is effected by a section 91 of control circuitry 90, the required ALE signal being fed to the relevant line, of the. control bus 38 and via a line 88 to the unit 85 (the section 91 also passes on to the unit 85 the ALE signal provided by the CPU 22). The control circuitry 90 in fact performs a number of functions and is arranged not only to generate the correct control signals for operation .of the DMAC 40, SDLC 48, and unit 85, but also to interrupt or influence certain of the lines of the control bus 38 to cause correct operation of the microcomputer 14 during DMA transfers while avoiding any possibility of undesired operations being initiated within the microcomputer. To enable the control circuitry 90 to carry out its function, it is connected to the demultiplexed address bus 36, the control bus 83 associated with the DMAC 40, a control bus 86 associated with the I/O port 47, lines 88, 89 for controlling the unit 85, and ' the Read (RD), Write (WR), IO/M, HOLD, Hold Acknowledge (HLDA), and Address Latch Enable (ALE) lines of the control bus 38. The control circuitry 90 comprises three sections 91, 92, 93. The first section 91 (already mentioned) is arranged to generate ALE signals and control the unit 85. he second section 92 carries out address decoding for the DMAC 40 and SDLC 48 and generates the appropriate RD, WR and IO/f signals. The third section 93 controls bus arbitration. The function of these sections 91, 92, 93 is described in greater detail below. The first section 91 of the control circuitry 90 generates ALE signals as has already been described, the fact that a DMA transfer is being undertaken being sensed from signals output by the DMAC 40 on the bus 83. In addition, the circuitry section 91 generates the appropriate direction control signal for feeding to the unit 85 on line 89. During a CPU write operation, this direction control signal is the CPU WR signal; however, during a CPU read operation the data buffer of the unit 85 is only opened towards the CPU 22 if the address being read so requires. During DMA transfers, the direction control signal is set as required. The second section 92 of the control circuitry 90 serves to decode the address bus and IO/M signals produced during a CPU read/write operation whereby to appropriately O PI enable internal register of the DMAC 40 and SDLC 48. During a CPU write, the section 92 leaves the WR and IO/M * signals unaltered; however, if a CPU read is addressed to the DMAC 40 or SDLC, the section 92 is arranged to interrupt the RD control line in the bus 38. During a DMA transfer, the circuitry section 92 is arranged to feed appropriate control signals to the SDLC 48 in response to the signals output on the bus 83 by the DMAC 40. In addition, the circuitry section 92 produces the appropriate RD , WR and IO/M signals for feeding to the microcomputer 14 on the corresponding lines of the control bus 38. The third section 93 of the control circuitry 90 is arranged to direct a Hold Acknowledge produced by the CPU 22 either to the microcomputer 14 or to the DMAC 40 depending on the origin of the associated HOLD signal. The aforedescribed operation of the control circuitry 90 ensures that none of the signals produced for controlling operation of the DMAC 40 and SDLC 38 can result in undesired operations within the microcomputer 14. Suitable hardware configuraLons for the circuitry 90 will, of course, be apparent to persons skilled in the art of microprocessor engineering. The above-mentioned auxiliary operating system controlling operation of the LAN interface 16 will now be outlined with reference to Figure 5. As mentioned above, the LAN may employ a range of different LAN interfaces 16 for use with a range of different microprocessors each using a different software instruction set. Although, as mentioned above, there may be differences between the hardware of the LAN interface, for instance due to different CPU operating speeds and/or to cater for microprocessors of different external physical configurations and/or different terminal wiring patterns, the differences between the different LAN interfaces will largely reside in the software of the associated auxiliary operating systems. For example, the software instruction sets may be different for Z80 , 8085, 8080, 8086 and 8088 microprocessors, but it should be appreciated that such software instruction sets need vary only with the nature of the microprocessor and not necessarily with the nature of the host microcomputer. Thus, for example, any form of host microcomputer from any manufacturer that uses, for example, an 8088 microprocessor, uses that particular software instruction set developed, for that particular form of microprocessor. But for any given microprocessor and its software instruction set use may be made of any one of (say) half a dozen operating systems. Any form of host operating system, regardless of the type of microcomputer, provides the user of the microcomputer with a defined set of operating procedures and facilities. As is well known, there are a number of such operating systems that are commonly used by most manufacturers, the operating system that is perhaps most widely used in,microcomputers being that known as CP/M (Trademark). For implementing any operating system in a microcomputer, the manufacturer is provided with a basic kernel of software which defines, controls and formats each peripheral or environment within the microcomputer. For example, the kernel defines and controls the format and accessing of discs, the operation of transient programs run under the control of the operating system, the presentation of a screen display, keyboard functions, and basic facilities providing the user with search capabilities, data handling and information. The design of each operating system is such that addresses for each decision point or process within the basic kernel remain the same irrespective of the associated "hardware. The final or overall hardware operating software is provided by the microcomputer manufacturer in the light of his particular system design, the resultant "variable" software being "linked" into the operating system via appropriate "hooks", provided by that operating system. This process of final configuration is known as "tailoring" the operating system to suit the physical environment. For a given operating system, therefore, the addresses of particular decision points and tailoring hooks and the like is predictable, irrespective of the hardware environment. This feature is employed for associating, in the present interfacing arrangement, the auxiliary operating system with the host.operating system. The auxiliary operating system can be viewed as a minor operating system or routine cό trolling a new peripheral, namely the LAN interface 16, this software being designed or coded in accordance with the microprocessor environment and the host operating system so that it is in effect installed into. he host operating system to control LAN data transfers via the LAN interface 16 when the host microcomputer so desires. The auxiliary operating system that controls the LAN interface 16 and the LAN data transfer operations is written and implemented in the following way. As mentioned above, for any particular standard operating system there are defined points at which that operating system makes decisions and directs logic. A relevant such decision point is when a program or procedure running under the control of the operating system requests disc input or output (I/O) from the operating system. Such a request iri the host operating system is diagrammatically represented at 70 in Figure 4. That is to say, in the step 70, the host operating system receives a disc I/O request, formats the request internally and then passes control to a part of the host operating system that handles disc I/Os, At this point, the auxiliary operating system inserts a "hook". That is to say, at what would normally be the entry point to the disc I/O Procedure, the auxiliary operating system performs a simple decision (step 72) as to whether the drive address of the disc I/O request is within a range that has. been designated for an LAN data request or whether it is within a range indicating that it is an I/O request for a local disc drive controlled directly by the host .microcomputer 14. If the drive address is local, then the operating processing is allowed to continue .through the host operating system's disc I/O routine (step 74). If, however, the drive address indicates that a data transfer via the LAN is desired, then the auxiliary system retains control. Thereafter the CPU 22 is controlled to set the SDLC into a receiving mode to listen for a general poll (step 76) Once access to the file server 10 is established, control remains with the auxiliary operating system until either data or a suitable response is obtained back through the LAN from the file server 10 (step 78). Once data transfer is complete, LAN access is relinquished (step 8) and control is returned to the point in the host operating system where normal control would have passed following completion of local disc drive access. OMPI As already mentioned,during data transmission, the auxiliary operating system caters, in a manner known per se, for error handling and recovery, and contains all communications "hand-shake" routines. The general nature of the auxiliary operating system having been described above, its detailed implementation for a particular set of circumstances ^ will be within the capabilities of one skilled in the art. There may be a respective different form of operating system for each microprocessor type and operating system type. Various modifications to the illustrated forms of LAN interface 16 are, of course, possible. Thus the LAN interface can be arranged to communicate with the file server 10 using a synchronous protocol other than the SDLC protocol, for example the HDLC (High-Level Data-Link Control) protocol, the chip 48 being then constituted by an appropriate HDLC peripheral controller chip. In addition, although the present invention has been described in connection with interfacing a microcomputer 14 with a local area network, it will be appreciated that the interface 16 could be readily modified, to interface the microcomputer 14 either with some other type of external device (through an appropriately configured I/O port) or with expansion modules (such as additional memory or specialised processors) which require direct access to the CPU buses. It will also be appreciated that while the CPU 22 inserted in the LAN interface socket 20 will generally be the one removed from the host microcomputer, the - t JRH OMPI CPU used in the interface. need not, in fact, be the self same one as removed from the microcomputer, nor indeed need it be ' .of identical type so long as it is functionally equivalent in the environment provided by the host computer. Furthermore, while the interface socket 20 serving to receive the CPU 22 has been shown as mounted on the interface cicruit board 29, it would also be possible to provide the socket 20 in the form of a unit which plugged directly into the location in the host microcomput.er vacated by removal of the CPU 22 It should be noted that such a unit, while providing straight-through connections to most of the contacts in the socket 20, would generally interrupt at least some of the control lines in order to enable them to be selectively isolated in the manner already described. The aforesaid unit would, of course, also provide for connection to the various other CPU lines. In certain cases, it may be unnecessary to isolate or influenece any of the control lines passing from the CPU 22 to the microcomputer. As used herein, the ' .expression "microcomputer" is • deemed to include any product incorporating a microcomputer, even if the product itself would not usually be referred to as a microcomputer. - ϊiΪ A OMPI ■<

Claims: CLAIMS 1. A microcomputer interface arrangement for connection to an existing microcomputer (14) to enable data to be transferred to/from the microcomputer (14), characterised in that said interface arrangement (16) comprises: - interconnection means (26, 28) for coupling the interface arrangement (16) to the location (24) in the microcomputer (14) which becomes vacant on removal from the microcomputer of a microprocessor (22) thereof; - receiving means (20) for receiving the said microprocessor (22) of the microcomputer or a functional equivalent thereof, the interconnection means (26, 28), when coupled to said microcomputer location (24), serving to interconnect the microcomputer (14) with the microprocessor (22) received by said receiving means (20), in such a manner that the microcomputer (14) can continue to operate in substantially the same manner as prior to connection to the interface arrangement (16), and - interface circuitry (47J100; ' 40,47,90) for enabling data transfer to be selectively established to/from the microcomputer (14) without thereby causing undesired operations within the microcomputer (14). 2. An interface arrangement according to Claim 1, characterised in that said interface circuitry (47,100; 40,47,90) includes control means(47;90) operative during data transfer to/from the microcomputer to influence or isolate at least certain ones of the control lines (38) passing to the microcomputer (14) from the microprocessor (22) received by said receiving means (20) such as to prevent undesired operations within the microcomputer (14). 3. An interface arrangement according to Claim 2, characterised in that said control means comprises isolation means (100) interposed in said interconnection means (26, 28) and operative to isolate said at least certain ones of the control lines (38) from the microcomputer during read and/or write operations addressed to elements of said interface circuitry. 4. An interface arrangement according to Claim 3, characterised in that said at least certain ones of the control lines comprise the read/write control lines (51, 53), and/or the memory/10 lines (55). 5. An interface arrangement according to Claim 2, characterised in that said interface circuitry (47, 100; 40, 47, 90) comprises an I/O port (47) arranged to interface the microcomputer (14) with an external device (10). 6. An interface arrangement according to Claim 5 , characterised in that said interface circuitry (40, 47, 90) includes a DMA controller (40) for transferring data between the said I/O port (47) and the memory (32) of the microcomputer (14), and has arbitration logic (90) for passing mastery of the microcomputer buses (34, 36, 38) from the microprocessor (22) received by said receiving means (20) to the DMA controller (40) for the duration of data transfer through said I/O port (47). 7. An interface arrangement according to Claim 6, characterised in that said interface circuitry (47, 100; 40, 47, 90) is arranged to interface the microcomputer (14) with a microcomputer local area network that includes a file server (10) constituting said external device, the I/O port being a serial I/O port operating in accordance with a synchronous protocol. 8. An interface arrangement according to Claim 1, characterised in that the said receiving means is a socket (20) for receiving said microprocessor, and the said interconnection means comprises a cable (26) terminated by a plug (28) compatible with the socket (20) constituting the receiving means.

Inventors: POLL EDGAR MICHAEL, POLL, EDGAR, MICHAEL
Applicants: MICROMITE COMPUTERS, MICROMITE COMPUTERS LIMITED
Application year: 1984
Main classification: G06F3
IPC codes: G06F3, G06F13