TIMING SYNCHRONIZING CIRCUIT

Abstract: In a timing synchronizing circuit wherein a timing signal is regenerated from a baseband signal subjected to a bandwidth limitation, there are provided a voltage controlled oscillator (5) whose oscillation frequency varies in accord­ ance with a control signal, an A/D converter (11) which samples and shapes the baseband signal by utilizing the output of the voltage controlled oscillator (5), a decision circuit (10) for deciding the polarity of a differential coeffi­ cient of the baseband signal at an optimum sampling point on the basis of an output of the A/D converter (11), and a logic circuit (9) responsive to the output of the decision circuit (10) to apply a logical operation to a decision signal derived from the A/D converter (11) and which decides whether or not the baseband signal shifts from a level corresponding to the optimum sampling point, thereby producing the control signal for the volatge controlled oscillator (5). The regenerated timing signal contains only a negligible amount of jitter components and always main­ tains an optimum timing without using any phase adjust­ ment.

Description: Background of the Invention This invention relates to a timing synchronizing circuit for regenerating a timings signal from a baseband signal subjected to bandwidth limitation as e.g. described in US-A-4423518. For converting a modulated signal demodulated by a demodulator utilized in a digitial carrier wave transmission system into a digital signal, a timing signal is necessary. Various means have been proposed for regenerating the timing signal, and a circuit to be described later can regenerate a timing signal containing a small proportion of jitter components but this circuit requires phase adjustment. Summary of the Invention Accordingly, it is an object of this invention to provide a novel timing synchronizing circuit capable of obtaining a regenerated timing signal containing less jitter components and always maintaining an optimum timing without using phase adjustment. A timing synchronizing circuit according to this invention and a demodulation apparatus comprising such a circuit is defined in the appended claims. Brief Description of the Drawings In the accompanying drawings: Fig. 1 is a block diagram showing a prior art timing synchronizing circuit; Fig. 2 is a block diagram showing one embodiment of the timing synchronizing circuit according to this invention; Fig. 3a shows waveforms useful to explain the operation of the circuit shown in Fig. 2; Fig. 3b shows sampling points for the waveforms shown in Fig. 3a; Fig. 4 is a block diagram showing examples of a decision circuit and a logic circuit shown in Fig. 2; Fig. 5 is a connection diagram of an amplitude comparator shown in Fig. 4; Fig. 6 is a block diagram showing a modification of the timing synchronizing circuit according to this invention; Fig. 7 is a diagram for explaining the operation of the modification shown in Fig. 6; Fig. 8 is a block diagram showing a decision circuit shown in Fig. 6; Fig. 9 is a block diagram showing a prior art demodulator apparatus including a timing synchronizing circuit and a demodulation circuit in combination, which is adapted for demodulation of 4 PSK (4-phase phase shift keying) waves; Fig. 10 is a block diagram showing a first embodiment of demodulator apparatus according to the present invention which is adapted for demodulation of 4 PSK waves; Fig. 11 is a block diagram showing a second embodiment of demcodulator apparatus according to the present invention adapted for demodulation of 16 QAM (16-level quadrature amplitude modulation) waves, Fig. 12 is a block diagram showing a third embodiment of demodulator apparatus of the invention adapted for demodulation of 4 PSK waves; Fig. 13 is a block diagram showing a fourth embodiment of demodulator apparatus of the invention adapted for demodulation of 16 QAM waves; and Fig. 14 is a block diagram showing a fifth embodiment of demodulator apparatus of the invention adapted for demodulation of 64 QAM waves. Description of the Preferred Embodiments Firstly, a prior art timing signal regenerating circuit will be described with reference to Fig. 1. This circuit comprises a full-wave rectifier 2; a phase synchronizing circuit 3 including a phase comparator 4, a voltage controlled oscillator 5 and a low-pass filter 6; a phase shifter 7; and a one bit A/D converter. Fig. 1 shows a case wherein the modulation wave is a two-phase PSK wave. This circuit operates as follows. An inputted PSK signal is demodulated at a phase detector 1 by using a reference carrier wave to produce a two-value baseband signal. The demodulated baseband signal is supplied to the full-wave rectifier 2 where the frequency of the demodulated baseband signal is doubled to extract a timing signal. The extracted signal is then supplied to the ordinary phase synchronizing circuit 3 to obtain a regenerated timing signal containing less jitter components, the regenerated timing signal being phase synchronized with the extracted timing signal and limited in a narrow bandwidth. The output of the phase synchronizing circuit 3 is supplied to the A/D converter 8 via the phase shifter 7 and used as the timing signal for sampling and shaping the demodulated baseband signal. At this time, it is necessary to adjust the phase of the regenerated timing signal with the phase shifter 7 so that the demodulated baseband signal would be sampled at an optimum timing. With this circuit, although it is possible to regenerate a timing signal containing less jitter components, it is necessary to adjust the phase. The invention contemplates provision of an improved timing synchronizing circuit not requiring phase adjustment. A preferred embodiment of a timing signal synchronizing circuit of this invention shown in Fig. 2 comprises a voltage cotrolled oscillator 5, a low-pass filter 6, a logic circuit 9, a decision circuit 10, and a two-bit A/D converter 11. Figs. 3a shows waveforms for explaining the operation of the embodiment shown in Fig. 2. The operation of this embodiment will now be described. It is now assumed that the demodulated baseband signal m of the output of the phase detector 1 has been somewhat subjected to bandwidth limitation, and that the baseband signal contains signals m₁ to m₄ having waveform response as shown in Fig. 3a. Such a demodulated baseband signal is sampled by the A/D converter 11 and converted into data signals X₁ and X₂ according to reference levels L₁, L₂ and L₃. The reference level L₂ is typically zero volt and binary value of the data signal X₁ is determined with respect to this level L₂. At the levels L₁ and L₃, the maximum margin for the signals m₁ to m₄ is obtained. The relation among the demodulated baseband signal m and data signals X₁ and X₂ is as shown in the following Table I. The data signal X₂ which takes a binary value according to Table I serves to decide whether or not the baseband signal m, particularly, signals m₁ to m₄ shift from levels corresponding to optimum sampling points A₋₁, a₋₁, B₀, b₀, C₁ and c₁ meeting the maximum margin. Demodulated baseband signal m X₁ X₂ m>L₁ 1 1 L₂<m<L₁ 1 0 L₃<m<L₂ 0 1 m<L₃ 0 0 In Fig. 3b, T₋₁, T₀ and T₁ represent optimum sampling points throughout 3 time slots. When the signals m₁ to m₄ having waveform response are sampled at the optimum sampling points T₋₁, T₀ and T₁ meeting the maximum margin, the binary value "1" or "0" of the data signal X₂ that decides whether or not the demodulated baseband signal m shifts from levels corresponding to the optimum sampling points would be outputted at an equal probability. However, when the baseband signal is sampled at a timing T o + Δt or T₀ - Δt , the data signal X₂ assumes binary values as shown in the following Table II in accordance with waveforms of the baseband signal. Table II shows that for the signals m₁ and m₂ having a positive differential coefficient at point T₀, the data signal X₂ is always "1" when the sampling point shifts from the optimum sampling point by + Δt whereas the data signal X₂ is always "0" when the sampling point shifts by - Δt. On the other hand, for the signals m₃ and m₄ having a negative differential coefficient at point T₀, the polarity of the data signal X₂ is inverted in comparison with the polarity of the data signal X₂ obtained with the signals m₁ and m₂. Therefore, the data signal X₂ for the signals m₃ and m₄ is made identical to that for the signals m₁ and m₂ by inverting the polarity of the data signal X₂. As described above, when the polarity of the differential coefficient of the demodulated baseband signal at an optimum sampling point T₀ is decided, and when a logical operation is executed according to results of the decision, a signal representative of a result of the logical operation can be used as an error signal which detects shifting of the sampling point. The decision circuit 10 shown in Fig. 2 decides gradients of signals m₁ to m₄, and provides output signals G and G deciding the gradients of the signals m₁ to m₄. The output signal G becomes "1" for the signals m₁ and m₂ whereas the output signal G becomes "1" for m₃ and m₄. The logic circuit 9 includes a circuit which inverts the polarity of the signal X₂ when the signal G is "1" and holds a data signal X₂ which corresponds to one of the signals m₁ to m₄ and occurs in the nearest precedence when both the signals G and G are zero. The output of the logic circuit 9 produces an error signal APC that detects the shifting of the sampling point in the A/D converter 11. Accordingly, when the output of the logic circuit 9 is supplied through the low-pass filter 6 to the voltage controlled oscillator 5 as a control signal, the circuit shown in Fig. 2 always supplies a timing signal to the A/D converter 11 at an optimum timing. Fig. 4 is a block diagram showing preferred examples of the logic circuit 9 and the decision circuit 10 in which reference numerals 12 to 16 and 24 designate D type flip-flop circuits, 17 an amplitude comparator, 18 an OR/NOR gate circuit, 19 and 20 OR gate circuits and 21 to 23 AND gate circuits. The flip-flop circuits 12 and 14 act as a 3-bit memory circuit, and the outputs Y₁ and Y₋₁ of the flip-flop circuits 12 and 14 are inputted to the amplitude comparator 17. The amplitude comparator 17 decides the polarity of the differential coefficient of the demodulated baseband signal at the optimum sampling point T₀ in the A/D converter by comparing data at points T₋₁ and T₁. Thus, when the data signal X₁ changes from "0" to "1" at the reference level L₂, the polarity of the differential coefficient is positive whereas when the data signal X₁ changes from "1" to "0", the differential coefficient is negative. The output signals G and G deciding the gradients of the signals m₁ to m₄ are outputted from the amplitude comparator 17, wherein G becomes "1" for signals m₁ and m₂ while G becomes "1" for signals m₃ and m₄. When, that is, the gradient of the signal having the waveform response is positive, the gate circuits 20 to 22 pass the data signal X₂ without changing its polarity whereas when signal G is "1", that is, the gradient of the signal having the waveform response is negative, pass the data signal X₂ after inverting the polarity thereof. When either one of the signals G and G is "1", AND gate circuit 23 sends out a timing signal whereas when signals G and G are both "0", indicating that the waveform response signal is flat the output of the AND gate circuit 23 is "0". Consequently, for the waveform response signals m₁ to m₄, the flip-flop circuit 24 outputs the output of OR gate circuit 20 as it is and in the case other than m₁ to m₄, the flip-flop circuit 24 holds a data signal X₂ which corresponds to one of the signals m₁ to m₄ and occurs in the nearest precedence. Fig. 5 shows an example of the amplitude comparator 17 which comprises OR/NOR gate circuits 25 and 26, and AND gate circuits 27 and 28. Fig. 6 shows an embodiment in which the demodulated baseband signal obtained by detecting a QAM wave has four values. In this embodiment, 3-bit A/D converter 29, and a corresponding decision circuit 30 are used. Fig. 7 is a table for explaining the operation of the circuit shown in Fig. 6 and shows the four-value baseband signal in relation to outputs X₁ to X₃ of the converter 29. Four values are present at reference levels L₁₁, L₃₁ (L₁₂), L₃₂ (L₁₃) and L₃₃ representative of the maximum margin for four values. Levels L₂₁ and L₂₃ are reference levels with respect to which binary values "1" and "0" of data signal X₂ are determined. Similarly, level L₂₂ is a reference level with respect to which binary values "1" and "0" of data signal X₁ are determined. Data signal X₃ serves to decide whether or not waveform responses signals shift from levels corresponding to optimum sampling points. Thus, for the demodulated baseband signal having four values, the data signal X₃ is inputted to the logic circuit 9. The decision circuit 30 outputs signals G and G having the same performance as those shown in Fig. 2 and these output signals are inputted to the logic circuit 9. Consequently, the logic circuit 9 outputs an error signal APC that detects shifting of the sampling point. When this error signal is applied to the voltage controlled oscillator 5 as a control signal, the circuit shown in Fig. 6 can be applied to the four-value demodulated baseband signal. Then, the circuit operates as a timing synchronizing circuit. Fig. 8 shows an example of the decision circuit 30 comprising D type flip-flop circuits 31 to 36 and an amplitude comparator 37. The decision circuit operates as follows. As the outputs of flip-flop circuits 31 and 34 can be obtained data Y₁ of the signals X₁ and X₂ at time T₁ while data Y₋₁ of signals X₁ and X₂ at time T₋₁ can be obtained as the outputs of flip-flop circuits 33 and 36 so that these outputs are applied to the amplitude comparator 37 so as to decide the polarity of the differential coefficient of the demodulated baseband signal. Let us denote the four-value signal at time T₋₁ by AT₋₁, the four-value signal at time T₁ by AT₁, AT₁ - AT₋₁ = M is calculated by the amplitude comparator 37. When M is positive, that is, when the differential coefficient at time T₀ is positive, output G is "1", whereas when M is negative, that is, when the differential coefficient at a time T₀ is negative, output G is "1". The four-value signals AT₋₁ and AT₁ can be obtained by the logical operation of the outputs of flip-flop circuits 31, 33, 34 and 36. Although, in the foregoing description, embodiments of this invention applicable to two-value and four-value demodulated baseband signal have been described, it should be understood that the invention is also applicable to much more valued baseband signals. For example, in the case of a 4-phase PSK wave, the PSK wave is branched into two having 90 degree phase difference and then the branched waves are supplied to the circuit shown in Fig. 2. In the case of a 16-value QAM wave, the QAM is branched into two having 90 degree phase difference and these two branched waves are supplied to the circuit shown in Fig. 6 respectively via detectors. As described above, this invention is applicable to a baseband signal subjected to a bandwidth limitation. In the embodiments, it is assumed that waveform response signals as shown in Fig. 3a occur as a result of the bandwidth limitation but it will be clear that as the condition for limiting the bandwidth varies, the waveform response signals shown in Fig. 3a vary. In such a case, it is necessary to modify the decision circuit 10 or 30 so as to satisfy the condition. In the embodiments shown in Figs. 2 and 6, a timing synchronizing circuit utilized in a digital carrier wave transmission system was described, but it should be understood that the invention is not limited to such an application, and the invention is also applicable to a baseband transmission system in which a baseband signal as shown in Fig. 3a is transmitted. Examples of the decision circuits were shown in Figs. 4 and 8, the decision circuit being required to have a performance that decides the polarity of the differential coefficient of the baseband signal at the sampling time. Accordingly, various means other than those shown in Figs. 4 and 8 can be used. Practically, timing synchronizing circuit of the present invention described previously has widespread applications in obtaining data signals from 4-PSK wave 16 QAM wave, or 64 QAM wave. Thus, a prior art demodulation apparatus for 4 PSK wave as shown in Fig. 9 has been available which includes a timing synchronizing circuit 900 being the same as that of Fig. 1 with the only exception that an A/D converter 91 is a two-bit A/D converter and an additional channel comprised of a phase detector 93 and an A/D converter 92 is provided for generation of data 2, and a demodulation circuit 901. The demodulation circuit 901 comprises a carrier synchronizing circuit 94 responsive to the output data signals of the timing synchronizing circuit 900 to produce a reference carrier frequency, and a phase detector 1 and another phase detector 93 which respectively respond to the reference carrier frequency directly and via a 90 degree phase shifter 95 so as to demodulate a 4 PSK wave applied to the phase detectors 1 and 93. The carrier synchronizing circuit 94 comprises a section including an exclusive OR gate 94-1 with its inputs connected via terminals C₃ and C₄ to a data signal Y₁ from the A/D converter 92 and a data signal X₂ from the A/D converter 91, an exclusive OR gate 94-2 with its inputs connected via terminals C₂ and C₁ to a data signal X₁ from the A/D converter 91 and a data signal Y₂ from the A/D converter 92, and a subtractor 94-3 applied with outputs of the exclusive OR gates 94-1 and 94-2. This section is responsive to the outputs of the A/D converters 91 and 92 to generate an error signal for detecting the rotational direction of the respective waveform response signals of the 4 PSK wave. In addition to this error signal generating section, the carrier synchronizing circuit 94 has a low-pass filter 94-4 responsive to the output of the subtractor 94-3, and a voltage controlled oscillator 94-5 controlled by the output of the low-pass filter to produce the reference carrier frequency supplied to the phase detector 1 and 90 degree shifter 95 via a terminal C₅. The carrier synchronizing circuit 94 operates as follows. Data signals Y₂ and X₁ are exclusive ORed at the exclusive OR gate 94-2 so that this gate 94-2 produces an output "0" when the respective waveform response signals of the 4 PSK wave rotate counterclockwise. Data signals X₂ and Y₁ are exclusive ORed at the exclusive OR gate 94-1 which , in turn, produces an output "1" when the respective waveform response signals rotate counterclockwise. Thus, by subtracting the output signals of the two exclusive OR gates 94-1 and 94-2 at the subtractor 94-3, a "0" signal of doubled level can be obtained. This doubled "0" level output is passed through the low-pass filter 94-4 for suppression of noises and supplied to the voltage controlled oscillator 94-5 which then produces a carrier signal in synchronism with the input 4 PSK wave. With the Fig. 9 demodulation apparatus, the input 4 PSK wave can be demodulated at the demodulation circuit 901 and converted into data 1 and 2 at optimum sampling points at the timing synchronizing circuit 900. Disadvantageously, this demodulation apparatus requires phase adjustment as described with reference to Fig. 1. Figs. 10 to 14 show various embodiments of demodulation apparatus according to the present invention which can obviate the prior art drawback. Throughout Figs. 10 to 14, demodulation circuits 109, 113, 123, 133 and 143 each including a carrier synchronizing circuit 94, phase detectors 103 and 104, and a 90 degree phase shifter 107 have the same construction as that of the demodulation circuit 901 shown in Fig. 9 but the connection of the demodulation circuit to timing synchronizing circuit 108, 112, 122, 132 or 142 is different from the connection of the demodulation circuit 901 to the timing synchronizing circuit 900 shown in Fig. 9. Fig. 10 shows an embodiment of demodulation apparatus of the invention adapted for demodulation of 4 PSK waves. The timing synchronizing circuit 108 is constituted by clock synchronizing circuits 101 and 102, and A/D converters respectively associated the circuits 101 and 102. Each of the clock synchronizing circuits 101 and 102 includes a voltage controlled oscillator 5, a low-pass filter 6, a logic circuit 9 and a decision circuit 10 connected to each of the A/D converters 105 and 106 in the same manner as in Fig. 2. Data signals X₁ standing for data 1 and X₂ from the A/D converter 105 are also applied to the carrier synchronizing circuit 94 via terminals C₂ and C₃, and data signals Y₁ standing for data 2 and Y₂ from the A/D converter 106 are also applied to the carrier synchronizing circuit 94 via terminals C₄ and C₁. Fig. 11 shows an embodiment of demodulation apparatus of the invention adapted for demodulation of 16 QAM waves. In this embodiment, a timing synchronizing circuit 112 includes a clock synchronizing circuit 111 including a voltage controlled oscillator 5, a low-pass filter 6, a logic circuit 9 and a decision circuit 30 connected to each of the A/D converters 105' and 106' in the same manner as in Fig. 6. Data signals X₁ standing for data 1-1 and X3 from the A/D converter 105' are also applied to the carrier synchronizing circuit 94 via terminals C₂ and C₃, data signals Y₁ standing for data 2-1 and Y₃ from the A/D converter 106' are also applied via terminals C₄ and C₁. The Fig. 10 embodiment is modified as shown in Fig. 12 which is different therefrom in that the timing signal is supplied in common to the two A/D converters 105 and 106, thereby ensuring that only one clock synchronizing circuit 101 (102) can suffice. The Fig. 11 embodiment is modified as shown in Fig. 13. This modification is different from the Fig. 11 embodiment in that the clock synchronizing circuit 111 is replaced with the circuit 101 (102) to simplify the circuit construction. Fig. 14 shows an embodiment of demodulation apparatus according to the present invention which is adapted for demodulation of 64 QAM waves. This embodiment is the same as the Fig. 13 embodiment with the only exception that the bit number of the A/D converters 105'' and 106'' is increased.

Claims: A timing synchronizing circuit for regenerating a timing signal from a baseband signal (m) subjected to a bandwidth limitation, comprising: voltage controlled oscillator means (5) responsive to a control signal (APC) for providing said timing signal; characterized by A/D converter means (11) responsive to said timing signal for discriminating said baseband signal to output data signals (X1) and discrimination error signals (X2); decision circuit means (10) responsive to an output (X1) of said A/D converter means (11) for deciding the polarity of a differential coefficient reflecting the gradient of said baseband signal (m) at an optimum sampling point (T₋₁, T₀, T₁) and depending on the value of the data signals (X1) at different sampling times; and logic circuit means (9) responsive to the output (G, G ) of said decision circuit means (10) and said discrimination error signals for deciding whether or not said baseband signal (m) has shifted from a level corresponding to said optimum sampling point, thereby providing said control signal (APC), and for deciding the direction in which the timing signal has to be shifted. A timing synchronizing circuit according to claim 1 wherein said control signal (APC) is applied to said voltage controlled oscillator (5) via a low-pass filter (6). A demodulation apparatus comprising in combination a demodulation circuit (109) for demodulating a carrier wave modulated with a baseband signal subjected to a bandwidth limitation and a timing synchronizing circuit (108), for regenerating a timing signal from the demodulated baseband signal (m); said timing synchronizing circuit (108) including at least one clock synchronizing circuit (101, 102) including a voltage controlled oscillator (5) responsive to a control signal for providing said timing signal, characterized by including a plurality of A/D converter means (105, 106) responsive to said timing signal for discriminating said demodulated baseband signal to output data signals and discrimination error signals; and a decision circuit (10) reponsive to said timing signal and an output of said A/D converter means for deciding the polarity of a differential coefficient reflecting the gradient of said baseband signal at an optimum sampling point, and depending on the value of the data signals (X1) at different sampling times, and a logic circuit (9) responsive to said timing signal, the output of decision circuit (10) and said discrimination error signals outputted from said A/D converter means, (105, 106) for deciding whether or not said baseband signal has shifted from a level corresponding to said optimum sampling point, thereby providing said control signal and for deciding the direction in which the timing signal has to be shifted; said demodulation circuit (109) including a carrier synchronizing circuit (94) responsive to the outputs of said timing synchronizing circuit (108) for providing a reference carrier wave, a pair of phase detectors (103, 104) for detecting the modulated carrier wave with said reference carrier wave and providing said demodulated baseband signal. A demodulation apparatus according to claim 3 comprising a plurality of clock synchronizing circuits (101, 102) respectively associated with the plurality of A/D converters (105, 106). A demodulation apparatus according to claim 3 wherein said A/D converters (105, 106) are responsive to the timing signal produced from a single clock synchronizing circuit (101). A demodulation apparatus according to any one of claims 3, 4 and 5 wherein said carrier synchronizing circuit (94) comprises a circuit section (94-1, 94-2, 94-3) responsive to the output signals from said timing synchronizing circuit, (108) for detecting the rotational direction of said baseband signal, a low-pass filter (94-4) responsive to the output of said circuit section, and a voltage controlled oscillator (94-5) responsive to the output of said low-pass filter for providing said reference carrier wave. A demodulation apparatus according to claim 6 wherein said circuit section comprises exclusive OR gates (94-1, 94-2) responsive to the output signals from said timing synchronizing circuit, and a subtractor (94-3) for subtracting the outputs of said exclusive OR gates.

Inventors: YOSHIDA, YASUHARU
Applicants: NEC CORPORATION
Application year: 1984
Main classification: H04L7
IPC codes: H04L7, H04L25, H04L27