PROCESS FOR FABRICATING BIPOLAR TRANSISTOR

Abstract: In the fabrication of a heterojunction bipolar transistor, after forming a collector layer (12), a base layer (13) and an emitter layer (14), ion implantation is carried out into and through the emitter layer except under an emitter electrode (15) formed on the emitter layer, which is used as a mask. Such a self-alignment ion implantation process can serve to provide a transistor with a lower base resistance and a higher cutoff frequency than transistors produced by previously known pro­ cesses.

Description: PROCESS FOR FABRICATING BIPOLAR TRANSISTOR The present invention relates to a process for fabricating a bipolar transistor, more specifically, a heterojunction bipolar transistor. Heterojunction bipolar transistors, in which the emitter bandgap is wider than the base bandgap, have the advantage of higher emitter efficiency since holes (minority carriers for the emitter) flowing from the base to emitter are blocked by the higher barrier in the valence band (cf. W. Schockley, U.S. Patent No. 2,569,347). The wide bandgap emitter allows the base to be heavily doped without sacrificing emitter efficiency. However, their cutoff frequency is relatively low, normally a few Gigahertz. Typical heterojunction bipolar transistors are fabricated by sequentially forming on a substrate a collector layer, a base layer, and an emitter layer. An emitter electrode is forned on the emitter layer. A base electrode is formed on the same side of the substrate as the emitter electrode near-the emitter electrode. However, the base layer is extremely thin, for example, from 50 nm to 100 nm, and the distance from the base electrode or base contact region to the emitter electrode or emitter contact region is, for example, from 1 m to 2 m. As a result, the base resistance becomes high, which limits the cutoff frequency, usually to a few Gigahertz. It is desirable to decrease the base resistance without changing the base thickness in order to increase the cutoff frequency in a heterojunction bipolar transistor with a wide bandgap emitter. An embodiment of the present invention can provide a process for fabricating a bipolar transistor comprising the steps of forming a first semiconductor layer of a first conductivity type on a support layer; forming a second semiconductor layer of a second conductivity type opposite to the first conductivity type on the first semiconductor layer; forming on the second semiconductor layer a third semiconductor layer, of the first conductivity type, made of a semiconductor that forms a heterojunction with the seeped samsurdxts: :er and the d# bandgap of which is wider than that of the second semiconductor layer; forming a first electrode on part of the third semiconductor layer; carrying out doping of part of the third semiconductor layer and therethrough to the second semiconductor layer, using the first electrode as a mask, so as to form an impurity-doped semiconductor region of the second conductivity type in alignment with the first electrode and reaching the second semiconductor layer; and forming a second electrode on said impurity-doped semiconductor region. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is an energy-band diagram of an n-p-n heterojunction transistor; Fig. 2 is an axial sectional view of a prior art heterojunction transistor; and Fig. 3 to Fig. 6 are sectional views of a heterojunction transistor in the sequential steps of a process according to an embodiment of the present invention. Figure 1 is an energy-band diagram of a heterojunction transistor with a wide bandgap emitter which comprises an n-type aluminum gallium arsenide (MxGa l-x## emitter, p-type gallium arsenide (GaAs) base, and n-type GaAs collector. In the diagram, W represents the energy level of the top of the valence band, Ec the energy level of the bottom of the conductive band, and Ef the energy level of the Fermi level. In the figure, the bandgap of the emitter is wider than that of the base. This widc-bandgapemitter heterojunction bipolar transistor has the advantage of higher emitter efficiency since, while electrons (majority carriers for the emitter) easily flow from the emitter to the base over the low barrier in the conductive band, holes (minority carriers for the emitter) flowing from the base to emitter are blocked by the high barrier in the valence band. Figure 2 shows a typical prior art heterojunction bipolar transistor. In the figure, 1 denotes an n-type GaAs collector, 2 a p-type GaAs base, 3 an n-type A1xGal#xA5 emitter, 4 an emitter electrode, 5 a base electrode, and 6 a collector electrode. In the device, the base 2 has a small thickness of, for example, 50 nm to 100 nm, while the horizontal distance L between the base electrode 5 and the emitter electrode 4 or the emitter 3 is over approximately 1ohm. This results from the separate formation of the electrodes 4 and 5 and the mask alignment process used therefor. As a result, the base resistance becomes high, decreasing ttse cutoff frequency of the device. According to an embodiment of the present invention, there is provided a process for fabricati, a bipolar transistor comprising the steps of forming a first semiconductor layer of a first conductivity type on a substrate; forming a second semiconductor layer of a second conductivity type opposite to the first conductivity type on the first semiconductor layer; forming a third semiconductor layer of the first conductivity type on the second semiconductor layer, the third semiconductor layer being of a semiconductor forming a heterojunction with the second semiconductor layer and having a bandgap wider than that of the second semiconductor layer; forming a first electrode having a certain pattern on the third semiconductor layer; doping dopants with the first electrode as a mask into and through the third semiconductor layer to form an impurity-doped semiconductor region of the second conductivity type in alignment with the first electrode and reaching the second semiconductor layer; forming a second electrode on the impurity-doped semiconductor region; and forming a third electrode for the first semiconductor layer. The doping stage may be carried out using ion implantation. In this process, the impurity-doped semiconductor region of the second condctivity type is formed in alignment with the first electrode by a self-alignment process. This allows a decrease in the base resistance and the emitter capacitance. This is made possible by the use, for the first electrode, of material which is heat resistant and allows ohmic contact with the ser#iconductor. Annealing after ion implantation is conducted at about 6000C to l,0000C, for example, at 7000C. Annealing may be effected by flash annealing. The material of the first electrode should withstand this annealing temperature and may be a refractory metal such as tungsten, tantalum, titanium, molybdenum, vanadium, chromium, zirconium, niobium, and hafnium; a silicide such as silicides of refractory metals as mentioned above, platinum silicide, palladium silicide, cobalt silicide, and nickel silicide; germanium; tellurium; silicon; thallium; cobalt, and nickel. Examples of pairs of semiconductors, usually compound semiconductors, which may be used for the second and third semiconductor layers are shown in the table on the next page. The first semiconductor layer is usually made of the same semiconductor and in the same way as the second semiconductor layer except for the doping conditions, since the layer need not form a heterojunction with the second semiconductor layer. Table Second semiconductor layer Third semiconductor layer GaAs (AlGa)As (InGa)As InP (InGa)As (AlIn)As (GaIn)Sb AlSb In(AsSb) AlSb GaAs (SaIn)P However, the first semiconductor layer may also be a seiconductor which forms a heterojunction with the second semiconductor layer and has a bandgap wider than that of the second semiconductor layer and may be, for example, the same semiconductor as the third semiconductor layer. In the latter case, a so-called double heterojunction bipolar transistor is formed. The first semiconductor layer may be used as an emitter or a collector in a double heterojunction bipolar transistor. In a process embodying the present invention, the substrate may be of not only sem insulating or insulating materials, for example, a nondoped compound semiconductor or silicon, or sapphire, but also of conductive materials, -for example, a heavily doped compound semiconductor or silicon. Recently, it has been possible to make excellent compound semiconductors on a silicon or sapphire substrate by using a buffer layer therebetween. An insulating or semi-insulating substrate may be used in the bipolar transistor, an electrode to the first semiconductor layer being provided on the same side of the substrate as the second and third semiconductor layers. If a conductive substrate is used in the bipolar transistor the electrode to the first semiconductor layer may alternatively be on the side of the substrate opposite to the second and third semiconductor layers. In anotherprocess embodying the present invention, another semiconductor layer of the first conductivity type which has a higher carrier concentration may be inserted between the third semiconductor layer and the first electrode to improve ohmic contact therebetween. This other semiconductor layer is preferably etched in the same form as that of the first electrode, since it is diffcult to convert the conductivity type. A further semiconductor layer of the first conductivity type may be inserted as a buffer layer between the substrate and the first semiconductor layer in order to improve the crystallographic characteristics of the first semiconductor layer. The doping to form the impurity-doped region in alignment with the first electrode may be conducted not only by ion implantation but also by heat diffusion, for example. Figure 3 to Fig. 6 illustrate the steps of fabricating a heterojunction bipolar transistor according to a specific embodiment of the present invention. In Fig. 3, on a semi-insulating GaAs substrate 10, an type GaAs buffer layer 11 of the doped impurity concentration of 1 x 1018 ciri# is formed in a thickness of 200 nm. An n-type GaAs collector layer 12 of the doped impurity concentration of 1 x 1017 cm-3 is formed in a thickness of 400 nrr on the n-type GaAs collector layer 12. A. p-type GaAs base layer 13 of the doped impurity concentration of 1 x 1019 e,r#3 is formed in a thickness of 100 nm on the n-type GaAs collector layer 12. An n-type Al0.3-Ga0.7As emitter layer 14 of a doped impurity concentration of 1 x 1017 cm¯3 is formed in a thickness of 300 nn; on the p-type GaAs base layer 13. Finally, an n#type GaAs ohmic contact layer 15 of a doped impurity concentration of 2 x 1018 cm 3 is formed in a thickness of 100 nrn on the rrtype Al0.3Ga0.7As emitter layer 14. These layers 11 to 15 are continuously formed by molecular beam epitaxy. The bandgaps of the p+-type GaAs p-type GaAs base layer 13 and the n-type AL0,3Ga0,7AS emitter layer 14 are 1.4 eV and 1.8 eV, respectively. With respect to the buffer layer 11, alternatively a super lattice layer can be used for improving the crystallographic characteristics of the first semiconductor layer 12. In-Fig. 4, a germanium (Ge) layer 16 of a thickness of 20 nm and a tungsten silicide (h'5Si3) layer 17 of a thickness of 500 nm are deposited on the n+-type GaAs ohmic contact layer 15 and patterned to form an emitter electrode of a desired form by photolithography. The n+-type GaAs layer 15 is selectively etched with the electrode layers 16 and 17 as a mask. The etched type GaAs layer 15 has the same shape as that of the emitter electrode 17. Then, by annealing at 7000C for 10 minutes, ohmic contact between the emitter electrode and the n+-type GaAs layer is formed. In Fig. 5, berylliun ions (Be+) are ion-implanted into or through the n-type A1a3GaO 7As emitter layer 14 with the emitter electrode 17 as a mask at an electron acceleration energy of 150 keV in a dose of 1 x 1014 cm¯2. Selective etching is conducted in an area separated from the emitter electrode 17 where a collector electrode is to be formed. This selective etching is conducted at least until the n-type GaAs collector layer 12 is exposed. Then, a silicon dioxide layer 19 is formed over the emitter electrodes 1G and 17, the n-type Alo 3GaO 7AS emitter layer 14, and the ntype GaAs collector layer 12, and heat treatment is conducted to anneal the implanted Be ions. This heat treatment is conducted at 7000C for 20 minutes. Alternatively, the heat treatment may be conducted by flash annealing over, for example, 5 seconds using, for example, a halogen lamp After this annealing, the ion-implanted portion of the ntype Alo 3GaO 7As emitter layer 14 and the upper part of the ntype GaAs collector layer 12 are changed to a p+-type region 18 including the p-type GaAs base layer 13 except the actual base region under the emitter electrode 17. This p+-type region 18 is formed in alignment with the emitter electrode 17 in accordance with the present invention. As a result, only the actual base region of the p-type GaAs base layer 13 has a small thickness of 100 nm so that the base resistance is decreased. The thus remaining n-type Al0.3Ga0.7 As emitter layer 14 is surrounded by the p+-type region 18 at the sides and by the p-type GaAs base layer 13 thereunder, the p-type Gas base layer 13 waving the same form and area as those of the n-type Al0.3Ga0.7As emitter layer 14. The n-type GaAs collector layer 12 exists under the p type GaAs base layer 13. In this structure of a bipolar transistor, electrons in the n-type Alo 3GaO 7As emitter layer 14 almost all flow through the p-type GaAs base layer 13 and almost never through the p#type region 18, i.e., a p+-type Al0.3Ga0.7As region surrounding the p-type GaAs base layer 13 since the conduction energy band is lower in the p-type GaAs base layer 13 than in the p+-type Al0.3Ga0.7As region 18. As a result, almost all of the electrons in the n-type Alo.3Gao.7As emitter layer 14 are used for operation of the bipolar transistor. In Fig. 5, windows for base and collector electrodes 21 and 23 are opened in the silicon dioxide layer 19, and a zinc (Zn) layer 20 of a thickness of 20 nm and gold (Au) layer 21 of a thickness of 200 nm are deposited and patterned to form a base electrode and an AuGe layer 22 of a thickness of 30 nm and a gold (Au) layer 23 of a thickness of 200 nm are deposited and patterned to form a collector electrode in the before-formed electrode windows. Thus, a heterojunction bipolar transistor is fabricated. In resultant heterojunction bipolar transistors, a current amplification coefficient hFE of 1500 and a cutoff frequency ft of 15 GHz are attained when the emitter size is 3 tm by 30 m ane hFE of 1500 and ft of 50 GHz when the emitter size is lXlm by 30 m. In another embodiment of the present invention, a double heterojunction bipolar transistor can be fabricated easily by replacing the n-type GaAs collector layer 12 by an n-type Al0.3Ga0.7As layer. In such a double heterojunction bipolar transistor, either of the n-type Ala paG7As emitter layer 14 or the n-type GaAs collector layer 12 replaced in this embodiment may be used as an emitter. That is to say, the emitter is not limited to the n-type A10.#Ga0 7As emitter layer 14. In either case, the bipolar transistor is a heterojunction bipolar transistor with a wide bandgap emitter and the base has a lower resistance. Accordingly there can be provided a method of fabricating a heterojunction bipolar transistor having a lower base resistance and a higher cutoff frequency of the transistor. After forming a collector layer, a base layer of small thickness, and an emitter layer, ion implantation is carried out into and through the emitter layer except under the emitter electrode formed on the emitter layer to widen the base layer in alignment with the emitter electrode. The self-alignment ion implantation process gives a lower base resistance and is made possible by using a heat resistant metal for the emitter electrode.

Claims: CLAIMS: 1. A process for fabricating a bipolar transistor comprising the steps of forming a first semiconductor layer (12) of a first conductivity type on a support layer (10, 11); forming a second semiconductor layer (13) of a second conductivity type opposite to the first conductivity type on the first semiconductor layer; forming on the second semiconductor layer a third semiconductor layer (14), of the first conductivity type, made of a semiconductor that forms a heterojunction with the second semiconductor layer and the band gap of which is wider than that of the second semiconductor layer; forming a first electrode (17) on part of the third semiconductor layer; ; carrying out doping of part of the third semiconductor layer and therethrough to the second semiconductor layer, using the first electrode as a mask, so as to form an impurity-doped semiconductor region (18) of the second conductivity type in alignment with the first electrode and reaching the second semiconductor layer; and forming a second electrode (21) on said impuritydoped semiconductor region. 2. A process according to claim 1, wherein said doping is effected by ion implantation followed by heat treatment. 3. A process according to claim 2, wherein said heat treatment is conducted at a temperature from 6000 C to 10000C. 4. A process according to claim 3, wherein said temperature is approximately 700go. 5. A process according to claim 2, wherein said heat treatment is flash annealing. 6. A process according to any preceding claim, wherein said first electrode is made from a heat resistant material. 7. A process according to any preceding claim, wherein said first electrode is made from one of the group of refractory metals and silicides, germanium, tellurium, silicon, cobalt, nickel, and thallium. 8. A process according to claim 7, wherein said refractory metal is tungsten, tantalum, molybdenum, titanium, vanadium, chromium, zirconium, niobium, or hafnium. 9. A process according to any preceding claim, wherein said first semiconductor layer is made of a semiconductor that has a bandgap wider than that of the second semiconductor layer and that forms a heterojunction with the second semiconductor layer. 10. A process according to any preceding claim, wherein said first semiconductor layer is made of a compound semiconductor. 11. A process according to any preceding claim, wherein said second semiconductor layer is made of a compound semiconductor. 12. A process according to any preceding claim, wherein said third semiconductor layer is made of a compound semiconductor. 13. A process according to any preceding claim, wherein said second semiconductor layer is made of gallium arsenide and said third semiconductor layer is made of aluminum gallium arsenide. 14. A process according to any one of claims 1 to 13, wherein said first semiconductor layer is made of aluminum gallium arsenide. 15. A process according to any one of claims 1 to 12, wherein said second semiconductor layer is made of indium gallium arsenide and said third semiconductor layer is made of indium phosphide. 16. A process according to claim 15, wherein said first semiconductor layer is made of indium phosphide. 17. A process according to any one of claims 1 to 12, wherein said second semiconductor layer is made of indium gallium arsenide and said third semiconductor layer is made of aluminum indium arsenide. 18. A process according to claim 15 or 17, wherein said first semiconductor layer is made of indium gallium arsenide. 19. A process according to claim 17, wherein said first semiconductor layer is made of aluminum indium arsenide. 20. A process according to any one of claims 1 to 12, wherein said second semiconductor layer is of gallium indium antimonide and said third semiconductor layer is made of aluminum antimonide. 21. A process according to claim 20, wherein said first semiconductor layer is made of gallium indium antimonide. 22. A process according to claim 20, wherein said first semiconductor layer is made of aluminum antimonide. 23. A process according to any one of claims 1 to 12, wherein said second semiconductor layer is made of indium arsenide antimonide and said third semiconductor layer is made of aluminum arsenide. 24. A process according to claim 23, wherein said first semiconductor layer is made of indium arsenide antimonide. 25. A process according to claim 23, wherein said first semiconductor layer is made of aluminum arsenide. 26. A process according to any one of claims 1 to 12, wherein said second semiconductor layer is made of gallium arsenide and said third semiconductor layer is made of gallium indium phosphide. 27. A process according to any one of claims 1 to 13 or claim 26, wherein said first semiconductor layer is made of gallium arsenide. 28. A process according to claim 26, wherein said first semiconductor layer is made of gallium indium phosphide. 29. A process according to any preceding claim, wherein said support layer comprises a layer of a semi-insulating compound semiconductor. 30. A process according to any preceding claim, wherein said support layer comprises a silicon layer. 31. A process according to any one of claims 1 to 28, wherein said support layer comprises a sapphire layer. 32. A process according to any one of claims 1 to 28, wherein said support layer comprises a layer of a compound semiconductor of the first conductivity type. 33. A process according to any preceding claim, further comprising the step of forming a fourth semiconductor layer (15) of the first conductivity type on the third semiconductor layer, said fourth semiconductor layer having a higher carrier concentration than that of said third semiconductor layer, the fourth semiconductor layer being patterned, in the step of forming the first electrode (17), so as to have the seperipheral form as the first electrode. 34. A process according to claim 1, wherein the support layer comprises a buffer layer (11) formed on a substrate (10) 35. A process according to claim 34, wherein said buffer layer is a semiconductor layer. 36. A process according to claim 34, wherein said buffer layer is a super lattice layer. 37. A process according to any preceding claim, further comprising the step of forming a third electrode (23) for said first semiconductor layer, wherein said third electrode is formed at the same side of the support layer as the first and second electrodes. 38. A process according to claim 37, wherein the third and second semiconductor layers (14, 13) are etched, laterally outwardly of the second electrode (21), to expose part of the first semiconductor layer (12) and wherein the third electrode (23) is formed on the exposed part of the first semiconductor layer. 39. A process according to any one of claims 1 to 28, further comprising the step of forming a third electrode at the side of the support layer opposite to the first and second electrodes.

Inventors: OHSHIMA, TOSHIO, YOKOYAMA, NAOKI
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: H01L29
IPC codes: H01L21, H01L29