A SEMICONDUCTOR CIRCUIT INCLUDING A MEMORY AND A PULSE DRIVE CIRCUIT

Abstract: The present invention concerns a pulse drive circuit in which a primary voltage (V cc ) is supplied as a supply voltage, and which converts primary pulses ( i ) of that primary vol­ tage into secondary pulses ( il ) of a secondary voltage which is different from the primary voltage; and a transistor (Q L ) which is supplied with the secondary pulses as controlling pulses, and with the primary voltage as a supply voltage, and which supplies to a load (C L ) an electric potential limited by the secondary voltage.

Description: Background of the invention The present invention relates to a semiconductor circuit including a memory and a pulse drive circuit. Reductions in the sustain voltage of elements which have resulted from the recent miniaturization of bipolar or MOS transistors have tended to reduce the operating voltages of integrated circuits. From the user's point of view, conventional supply voltages, such as supply voltages in units of 5V, are desirable for ease of use. It is considered that means by which it will be possible to satisfy both the needs of the manufacturers of integrated circuits and the users is a reduction of the external supply voltage Vcc within the chips and the operation of miniaturized elements by a voltage V L which has been lowered thereby. Figure 1A is taken from EP-A-0 063 483. A miniaturized element 12a of Fig. 1B is used in an internal circuit a which determines the effective integration density of chips 10, and the remedy for the reduction in the voltage resistance resulting from miniaturization is to operate the element by a voltage V DP which is the external supply voltage Vcc reduced by a voltage limiter 30. However, it is usually easier to design a drive circuit b which uses a higher supply voltage and which includes, for example, an input-output interface, which does not contribute much to the integration density. Thus, a comparatively large chip 12b, as shown in Fig. 1B, is used for the driving circuit b which is operated by applying Vcc thereto. A chip is a single substrate on which memory, logic or other LSI devices are fabricated. In a memory LSI device, a is a memory array and its related circuits; and in a logic LSI device, a is an area constructed of repeated cells making up the ROM or RAM area of a microcomputer. Details of embodiments of voltage limiters using this voltage limiter system are given in EP-A-0 063 483 When this kind of voltage limiter system is utilized for charging a capacitance load which has only a low voltage resistance in the circuit a , the output V DP of the voltage limiter 30 is supplied to the drain of a charging transistor as a supply voltage and, pulses of the same level as that of the external supply voltage Vcc is applied to the gate of the transistor, turning the transistor on. In Fig. 2, a precharge circuit for a data line of a semiconductor memory is shown as an example of this type of circuit. In Fig. 2, charging transistors Q₆, Q₇ controlled by precharge pulse  P2 of a maximum level of Vcc charge data lines D o and D o to a voltage as large as the output voltage V DP of the voltage limiter 30. Numeral 1 denotes a memory cell array. However, in this circuit, the equivalent internal resistance of the voltage limiter 30 is connected in series to the equivalent resistances of the charging transistors Q₆ or Q₇ when they are on, and thus it is necessary to make these resistances much smaller to enable charging at a higher speed when there is a larger capacitance load. For that purpose, size of the transistors in the voltage limiter 30 and the transistors Q₆, Q₇ must be larger, and thus it can be understood that it is difficult to drive a large capacitance load faster when there must be a high degree of integration. US-A-4 065 678 discloses a pulse driver circuit which produces a limited output voltage from a given supply voltage. This document represents a semiconductor circuit in accordance with the first part of claim 1. SUMMARY OF THE INVENTION It is an object of the invention to apply such a pulse drive circuit to a semiconductor memory, the data lines of which represent a large capacitance, yet are pre-charged at high speed to a voltage lower than the supply voltage. The present invention meets this object by providing a semiconductor circuit as characterized in claim 1. Preferred embodiments of the pulse drive circuit and semiconductor memory included in this semiconductor circuit are set forth in the dependent claims. Brief description of the drawings Fig. 1A is a diagram of the chip structure of a conventional semiconductor circuit. Fig. 1B is a diagram of an example of the structure of two transistors used in the chip of Fig. 1A. Fig. 2 is a diagram of a precharge circuit for data lines of a semiconductor memory. Fig. 3 is a circuit diagram of a pulse drive circuit. Fig. 4 is a circuit diagram of a further pulse drive circuit. Fig. 5 is a graph of the output characteristic of the voltage limiter 30 used in the circuit of Fig. 4. Figs. 6A and 6B illustrate the high-voltage generation circuit (31c) used in the circuit of Fig. 4. Fig. 7 is a circuit diagram of a pulse drive circuit. Fig. 8 is a graph of the output characteristic of the voltage limiter (30D) used in the circuit of Fig. 9. Fig. 9 is a circuit diagram of a pulse drive circuit. Figs. 10A and 10B illustrate the voltage generation circuit (31C) used in the circuit of Fig. 8. Figs. 11A and 11B are circuit diagrams of two parts of a semiconductor memory of the present invention. Fig. 12 is a circuit diagram of the voltage limiter (30E) used in the circuit of Fig. 11B. Fig. 13 is a circuit diagram of the pulse-limiting circuit (G) of Fig. 11B. Fig. 14 is a circuit diagram of the voltage converter circuit (H) of Fig. 11B. Fig. 15 is a circuit diagram of a pulse drive circuit which discharges a charge from a capacitance load. Fig. 16 is a circuit diagram of a discharge circuit. Fig. 17 is a graph illustrating conventional problems encountered when driving a capacitance load. Fig. 3 shows a fundamental circuit. A signal  iℓ whose amplitude is controlled by the operation of a pulse-generating circuit PG is input to a gate of a MOS transistor Q L ', and a capacitance load C L connected to the source of the transistor is driven thereby. The pulse-generating circuit PG inputs pulse  i of a maximum voltage equivalent to the supply voltage Vcc. Details of this pulse-generating circuit PG and its operation are given in "Electronics" March 24th, 1982, pp. 132-136. An outline thereof is provided below. An inverted output of a driver 12 to which the input pulse  i is applied makes a MOS transistor Q D discharge its gate voltage so that its electric potential changes from high to low. Simultaneously, a bootstrap capacitance (not shown) acts so that the gate voltage of a transistor Q L is charged by a non-inverted output of the driver 12 so that its low potential becomes a high potential of at least the level of Vcc, turning the transistor Q L on. An internal supply voltage V DP which is different from the external supply voltage Vcc and is applied to the gate of a transistor Q LL so that a voltage of V DP ―V T is applied to the drain of transistor Q L . Thus, the output  iℓ rises from a low voltage of zero to the drain voltage V DP ―V T of the transistor Q L . V T denotes the threshold voltage of each transistor in this circuit. The external supply voltage Vcc is applied to the drain of transistor Q L ', but the capacitance load C L is charged by a voltage of up to V DP ―2V T which is equal to the high voltage V DP ―V T of the pulse  iℓ reduced by the threshold voltage V T of the transistor Q L '. By suitably increasing the size of transistor Q L ' alone, that is, by increasing the magnitude of W/L (channel width/channel length), it is possible to drive the capacitance load C L at high speed, even a large C L . Concrete details of circuits embodying the voltage limiter 30 are disclosed in EP-A-0 063 483. One example of these will now be described with reference to Fig. 4. This circuit removes the problem often encountered in the prior art that, when charging the capacitance load C L the voltage limiter and the charge-control transistors must all be large-sized transistors. When the voltage with which the capacitance load C L is charged is V out (hereinafter, "signal voltage" denotes any voltage on the high electric potential side, without particular limitations), the voltage of the pulse  iℓ is V in and the threshold voltage of the transistor Q L is V T , V out is generally given by; V out = V in ― V T (1) Accordingly, a control of the output voltage on the high electric potential side can be accomplished by controlling V in which can be defined in response to the essential voltage V out . Thus for V in it is necessary to generate a voltage which is higher than the required charge voltage by the voltage V T . For this purpose, the output voltage V DP of the voltage limiter 30 of Fig. 3 could be modified. Fig. 4 discloses a circuit in which the voltage of V DP ―V T is applied to the capacitance load C L . Fig. 4 differs from Fig. 3 only in that a voltage limiter 30A is designed so that it outputs a voltage V DP + V T which is only V T higher than the output V DP of the voltage limiter 30 of Fig. 3. Fig. 4 shows a concrete example of the voltage limiter 30 which outputs V DP from a contact point between a resistor R LM and a series of n diodes D₁ to D n . The voltage limiter 30 outputs the voltage V DP of which has a characteristic as shown in Fig. 5 with respect to the external supply voltage Vcc. This characteristic shows that if the external supply voltage Vcc is less than V₀, the output of the voltage limiter is equal to Vcc; and if it is greater than V₀, the output thereof varies with a gradient of m which is less than 1. When the standard voltage is 5V, V₀ is selectively defined by a value which is less than 5V; and when Vcc is 5V, V DP can be determined to be, for example, 3.5V by this characteristic. V₀ is equal to the external supply voltage when the n series-connected diodes D₁ to D n of Fig. 4 start to be turned on. The gradient m is defined by the ratio of the resistance R LM in series with the resistance of the group of diodes D₁...D n when on. Returning to Fig. 4, a high-voltage generation circuit 31 generates a voltage V pp which is higher than the external supply voltage Vcc. This circuit will be described later with reference to Figs. 6A and 6B. In Fig. 4, two transistor Q₁₀₃, Q₁₀₁, which are arranged so that the drain and gate of one are connected to the source of the other, and a resistance R p are connected in series between an output terminal of the high-voltage generation circuit 31 and an output terminal of the limiter 30. Thus, the drain voltage of transistor Q₁₀₃ is equal to V DP + 2V T . Since this voltage V DP + 2V T is applied to the gate of a transistor Q₁₀₂ whose drain receives the external supply voltage Vcc, V DP + V T is applied to the gate of the transistor Q LL in the pulse-generating circuit PG. Accordingly, the high electric potential of the pulse  iℓ is equal to V DP and so a charging voltage of up to V DP - V T is applied to the capacitance load C L . The output voltage V pp of the high-voltage generation circuit 31 is set by the formula: V pp ≧ V DP + 2V T The high-voltage generation circuit 31 will now be described with reference to the circuit diagram thereof of Fig. 6A. A circuit C p1 has a construction and operation such that pulse  B is applied through a charge-pump capacitor C B to a node between two transistors Q c1 and Q c2 arranged so that the source of Q c1 is connected to the gate of Q c2 , and pulses higher than Vcc are generated. A circuit C p2 also comprises of two transistors Q ' / c1 and Q ' / c2 connected in the same state as in circuit C p1 and a charge-pump capacitor C ' / B. However, it differs from C p1 in that pulse  B is generated. The sources of transistors Q c2 and Q ' / c2 for a wired OR.  B and  B , respectively are pulses of a certain period and inverses thereof, in a chip. The circuits for producing these pulses are not shown in the drawings for simplicity. C p denotes a parasitic capacitance generated in the output wiring. Nodes N₁ and N ' / 1 respectively of transistors Q c1 and Q ' / c1 of Fig. 6B are precharged to the voltage Vcc―V T . Each of the pulses B and B then reach Vcc during each of time bands T₁, T₂, respectively, when the corresponding nodes N₁ and N ' / 1 are raised to 2Vcc―V T during T₁ and T₂ by the capacitive coupling of charge-pump capacitors C B and C ' / B, respectively. This voltage appears as an output voltage V pp through transistors Q c2 , Q ' / c2 but the voltage is reduced by the threshold voltage V T of the transistors Q c2 , Q ' / c2 and thus V pp is given by the formula V pp = 2(Vcc - V T ) . As a result, the output V pp becomes a d.c. voltage which is greater than Vcc. Since the high-voltage generation circuit 31 receives the charges of the capacitors CB, C ' / B output during both time bands T₁, T₂, the ability of the circuit to supply charge is great, and a ripple noise in its output V pp is low. Fig. 7 shows a circuit which can charge the capacitance load C L to the voltage V DP . The circuit shown in Fig. 7 differs from that of Fig. 4 in that a voltage limiter 30B is constructed so that the output voltage V DP of the voltage limiter 30 is raised to V DP + 2V T . Namely, the circuit in Fig. 7 differs from that of Fig. 4 in that with the drain and gate connected, a transistor Q₁₀₄ is connected in series to transistors Q₁₀₁ and Q₁₀₃ and high voltages V ppA and V ppB generated by voltage generation circuits 31A and 31B are applied to the drain of a transistor Q₁₀₂ and a resistor R p , respectively. The gate voltage of the transistor Q₁₀₃ is made to be V DP + 3V T by activating the transistor Q₁₀₄. Thus, a voltage which is higher by V T than that in the circuit of Fig. 4 is applied to the gates of transistors Q LL , Q ' / L, and the capacitance load C L is charged to the voltage V DP . In addition, the high-voltage generation circuit 31B supplies the transistor Q LL with a voltage V ppB which value is V DP + 2V T , in order to raise the gate voltage of the transistor Q L' to V DP + V T which is higher than that in Fig. 4. The output V ppA from the high-voltage generation circuit 31A must be greater that the drain voltage V DP + 3V T of the transistor Q₁₀₃. Ordinary integrated circuits are subjected to ageing tests after the final production step in order to ensure their reliability. These ageing tests are designed to detect any transistor in which basic problems are likely to occur because of a failure of its gate oxide film, and are performed by deliberately applying to each transistor in the circuit a voltage which is higher than those encountered during normal usage. It is necessary to apply to each element a voltage which is slightly lower than the destructive voltage of a normal element in order to improve the chances of finding failures with these ageing tests. For an integrated circuit chip which is so constructed that a supply voltage is supplied through a voltage limiter within the chip, examples which can accomplish these ageing tests, even for the circuit part a of Fig. 1 which has a low voltage resistance, are disclosed in EP-A-0 063 483. In the circuits shown in Figs. 3, 4 and 7, the voltage limiter 30 varies the output voltage V DP in accordance with the characteristic of Fig. 5. Thus, if the gradient m is selected to have a certain magnitude, the output V DP can be charged to the voltage required for the ageing tests by varying the magnitude of Vcc. This change means that the voltage applied to the load capacitance C L can be varied, and thus the ageing tests can be accomplished for the load capacitance C L . However, when Vcc is near the normal operating voltage 5V, it is better not to change V DP much if Vcc is varied. For this purpose, it is desirable to minimize the gradient m of the characteristic of Fig. 5 as far as possible. Therefore, in the voltage limiter 30 of Figs. 3, 4 and 7, when the external voltage Vcc is greater than Vo', which is greater than the normal operating voltage 5V, it is desirable, as shown in Fig. 8, to generate V DP so that its characteristic varies with respect to the voltage Vcc above the voltage Vo' with a gradient m' that is greater than the gradient m when Vcc is between the voltages Vo and Vo'. Fig. 9 shows a circuit in which the capacitance load C L is supplied with a voltage which varies in accordance with the characteristic of Fig. 8. Fig. 9 differs from Fig. 7 in that a voltage limiter 30D is used instead of the voltage limiter 30 of Fig. 7. The circuit of the voltage limiter 30D is disclosed in EP-A-0 063 483. This voltage limiter 30D outputs a voltage V DP which has the characteristic shown in Fig. 8. Namely, in Fig. 9, VG (for example, Vcc + 2V T ) is applied to the gate of a transistor Q o of the voltage limiter 30D. The magnitude of the voltage V G is selected so that it can turn Q o on. When the magnitude of the external supply voltage Vcc is between 0 and V₀, a transistor Q ℓ is turned off, and thus the output V DP is equal to Vcc. When the external supply voltage Vcc is between V₀ and V ' / 0, the transistor Q ℓ is turned on because transisors Q₁, Q m are on. Accordingly, the output V DP varies according to a gradient m (m < 1) determined by the conductance ratio of transistors Q o and Q ℓ . When the external supply voltage Vcc is above V ' / 0, a transistor Q ' / ℓ is turned on because transistors Q ' / 1 and Q ' / n are on. Consequently, the output is defined by a gradient m' ( m' > m ) which is also determined by the ratio of conductance of transistors Q o and Q ℓ , and also by the sum of the conductances of the transistors Q o and Q ' / ℓ. The circuit shown in Fig. 9 differs from that of Fig. 7 in that a high voltage V ppc generated by a high-voltage generation circuit 31C (which will be described later with reference to Figs. 11A and 11B), is applied to the drain of the transistor Q LL . The voltage V ppc is selected to have a magnitude greater than that of the gate voltage V DP + 2V T of the transistor Q LL even if that gate voltage varies. Thus, in the same way as in the circuit of Fig. 7, the voltage V DP is applied to the capacitor C L even if the magnitude of V ppc varies. As a result, the ageing tests of the capacitance load C L can be accomplished by varying Vcc. It is obvious that the voltage limiter 30C of Fig. 9 can be used instead of the voltage limiter 30 of Figs. 3, 4 and 7, and it also goes without saying that the high-voltage generation circuits 31A and 31B of Fig. 9 must generate output voltages V ppA and V ppB that are higher than V DP + 3V T and V DP +2V T respectively, even if Vcc varies. The high-voltage generation circuit 31C will now be described. A pulse-generating circuit PG', shown in Fig.10A, differs from the pulse-generating circuit PG of Fig. 3 only in that it does not have the transistor Q LL . Pulse  BB output from the pulse-generating circuit PG' are connected to the source of a transistor Q BB by a bootstrap capacitor C BB . The drain and gate of the transistor Q BB are connected to the external supply voltage Vcc. The operation of this voltage generation circuit 31C will now be described with reference to Fig. 10B. An output V ppc is precharged to the voltage V CC ― V T by the transistor Q BB . When an input pulse  i of the pulse generation circuit PG' rises, an output pulse  BB starts to rise simultaneously with an output pulse  iℓ of the pulse generation circuit PG (Fig. 9). The pulse  BB rises as far as Vcc, and  iℓ rises to V DP + V T . In response to the rise of the pulse  BB , V ppc rises because of the capacitive coupling of C BB . The magnitude of C BB is such that the maximum value of V ppc becomes the voltage necessary for obtaining the source voltage V DP + V T of a transistor Q LL (Fig. 9), that is, a voltage higher than V DP + 2V T . It is better to employ the voltage generation circuit 31C than a circuit which outputs V ppc continuously, because V ppc is generated only when a pulse  iℓ is generated, and so the power consumption is reduced. This means that the high-voltage generation circuits 31A and 31B can be constructed of the same circuit. Figs. 11A and 11B show an embodiment of the present invention applied to MOS dynamic memory with a single -transistor type memory cell. In these drawings, a group of circuits 1 enclosed within a dot-dash line comprise a memory array circuit. A group of circuits 2 enclosed within a dot-dot-dash line comprise circuits (direct peripheral circuits) which control the memory array circuit and amplify signals from memory cells. A group of circuits 3 enclosed within a triple-dot dash line denotes circuits (indirect peripheral circuits) which supply signals to the direct peripheral circuits, amplify memory signals from the memory array circuit, and write memory signals into the memory array circuit. In the memory array 1, capacitors C₁ and C₂, transistors Q₈, Q₉ and Q₁₁, Q₁₀ represent dummy cells. Capacitors CM₁, CM₂...CM n-1 , CM n and transistors QM₁, QM₂... QM n-1 , QM n each form memory cells. Pulse  p3 applied to the gates of transistors Q₉ and Q₁₀ are used to discharge the capacitors C₁, C₂ before reading, and is generated in a pulse-generating circuit 33. A denotes a word driver circuit which generates word-selecting signals from address signals. When a transistor QD₁ or QD₂ on a word line W₁ or W₂, respectively, is selected, the word driver circuit A raises the gate voltage of a transistor Q₁₆ on a dummy word line WD₁ to a higher level, and outputs a signal  xℓ to a dummy word line WD₁ and the appropriate word line W₁ or W₂. On the other hand, when a transistor QD n-1 or QD n on a word line W n-1 or W n , respectively, is selected, a transistor Q₁₇ on a dummy word line WD₂ is selected. Transistors Q₂₁, Q₂₂ connect I/0 and I/0 lines to data lines D and D by pulses ₄. Transistors Q₁, Q₂ form part of a sense amplifier and transistors Q₃, Q₄ act as switches to connect data lines to the sense amplifier. Transistors Q₆, Q₇ are used for precharging and will be described later. A transistor Q₅ is used for switching between the short-circuiting of data lines D, D . A transistor Q₁₈ is used for precharging a line ℓ, and transistors Q₁₉, Q₂₀ are used for driving the sense amplifier. A voltage limiter 30E outputs two voltages V L1 and V L2 through a circuit shown in Fig. 12. This circuit is formed by connecting the gate of the transistor Q₁₀₄ of the voltage limiter 30C of Fig. 9 to the transistor Q₁₀₂ of Fig. 4. Each transistor is constructed so as to have a threshold voltage V T of 0.5V, and a voltage limiter 30D is constructed so that V DP is 3.5V when the external supply voltage Vcc is 5V. Thus, the outputs V L1 and V L2 are 4.0V and 4.5V, respectively, when Vcc is 5V. The voltage limiter 30E can generate these two voltage magnitudes within a single circuit. Thus, the area of the semiconductor chip can be reduced, and fluctuations between V L1 and V L2 can be made smaller because the voltage limiter 30E operates on the basis of the same output V DP of the voltage limiter 30D. In Fig. 11B, F denotes a circuit in which is inputted a precharge signal  P2 (5 V) and also V L2 (4.5), and which outputs a precharge signal  P2ℓ whose voltage is V T less than V L2 . F is composed of a circuit which is identical to the pulse-generating circuit PG of Fig. 9. The data lines D, D and a common source terminal of the sense amplifier composed of the transistors Q₁, Q₂ is precharged to a voltage equal to V L2 reduced by only the threshold voltage V T , by transistors Q₆, Q₇ and Q₁₈ to the gates of which pulses are applied. For example when the external supply voltage Vcc is 5V and the threshold voltage is 0.5V, the precharge voltage is 3.5V. Since there are numerous data lines within a memory, the total capacitance thereof is fairly large. However, according to the present invention, these lines can be precharged to a voltage which is lower than Vcc at high speed. In order to prevent any differences in data line voltages caused by the difference between the threshold voltages of transistors Q₆ and Q₇, the gate voltage  P1 of Q₅ can be made higher than  P2ℓ , transistor Q₅ can be turned on to short-circuit lines D and D . I/O, I/O lines are common data input and output lines connected to a plurality of data lines. In Fig. 11B, B denotes a pulse-generating circuit and C denotes another pulse-generating circuit which inputs write data Din and generate pulses din, din which are complementary to each other. Numeral 33 denotes a circuit which inputs external control pulse signals at the voltage Vcc and generates pulses such as  P1 ,  P2 , etc. In Fig. 11B, G denotes a circuit which is inputed a signal  x of a voltage amplitude of 5V and also V L2 (4.5V), and which outputs a signal  Xℓ of the same voltage amplitude as V L2 . This circuit, shown in Fig. 13, is disclosed in EP-A-0 063 483 wherein it is described as a circuit for converting a signal amplitude, employing a self-bootstrapping effect. This signal  xℓ becomes a word line signal of a memory cell. In this embodiment, the pulse drive circuit is not applied to the driving circuit G for word lines W₁ ... W n . That is the reason why, since only one word line should be selected and the capacitance thereof is small, the driving speed is made much faster by the circuit G. However, a component in which the pulse drive circuit is applied must charge all the data lines at once so that the load on it is heavy, and its speed must therefore be made slower by such means as the driving circuit G. If a data line is charged with a pulse drive circuit, it is clearly impossible to make the speed faster than the speed obtained when only one word line is charged by the driving circuit G. In Fig. 11B, H denotes a voltage converter circuit which is inputed V L1 (4.OV) and Vcc(5V), and which generates a set up d.c. voltage of V cp (3.5V). As shown in Fig. 14, it is composed of a so-called source-follower transistor Q ss which inputs Vcc through its drain and V L1 through its gate, and outputs V cp from its source. It is possible to stabilize the operation of the circuit by inserting a large resistance R ss between an output terminal and ground, and by passing a small current therethrough, as shown in Fig. 14. In the Figure, V cp is a precharge voltage supplied to the I/O and I/O lines, or it is a writing voltage in the writing circuit composed of transistors Q₂₃ to Q₂₆, and is set to 3.5V, equal to the data line voltage. In order to precharge the I/O, I/O lines, a conventional method of inputting the controlled voltage V cp to the drains of transistors Q₂₈, Q₂₉ is employed. However, in the same way as in the precharging means for data lines, it is possible to employ the method of controlling the voltages of the I/O, I/O lines at a predetermined magnitude by applying voltage-controlled pulse signals within the chip to the gates of the transistors Q₂₈, Q₂₉. The I/O, I/O lines can be precharged as fast as the data lines, so the pulse drive circuit should be applied thereto. A circuit such as that shown in Fig. 12 is suitable for this purpose because it has a small capacitance and a convenient layout. Circuits for discharging the capacitance load are shown in Figs. 15 and 16. Fig. 15 shows a circuit in which a signal  iℓ , an inversion of the signal  iℓ of Fig. 3, is input to the gate of a transistor Q' D , and an output can be extracted from the drain thereof. In this circuit, the inverted signal  iℓ is output and the capacitance load C' L is driven on the basis of the driving ability of a transistor Q D '' defined by its W/L ratio. Thus, in the same way as in the embodiment of Fig. 3, any size of driving ability can be obtained by selecting a suitable value of W/L. Fig. 16 shows a circuit in which a push-pull type of buffer circuit is constructed from two of the pulse-generating circuits PG of Fig. 3 which form an inverted signal and apply it and the original signal to the gates of transistors Q L '', Q D ''.  iℓ is input to Q L '' and the inverted signal  iℓ of  iℓ is input to Q D ''. An output  o '' therefrom is a signal of the same phase as  iℓ at a voltage controlled by the voltage of  iℓ . In the present embodiment, the rise term of  iℓ of  o '' and is output on the basis of the driving ability of transistor Q L '' determined by the ratio W/L, and the fall term thereof is output according to that of transistor Q D ''. The driving ability required for each section can be easily obtained so that the capacitance load C L can be driven at high speed. Each of these circuits have been described using n-channel MOS transistors as examples, but p-channel MOS transistors can be employed of all the potential relationships are reversed. For example, if p-channel MOS transistors are used for the pulse-generating circuit and the supply voltage is -5V (the circuit operates within the range of -5V to OV), the circuit can be operate under conditions in which -5V is applied to the drain of transistor Q L '' and OV (ground) is applied to the source of transistor Q D ''. In this case, the output voltage is given by the formula V out =V in -V T , in the same way as in formula (1), when the voltage of the input  iℓ is V in ; so that if, for example, V in is -4V and V T is -0.5V (p-channel transistors have negative threshold voltages), V o = -4-(-0.5)=-3.5V. This means that the magnitude of V in can control V out . If an operating range of from OV (corresponding to the previous -5V) to 5V (corresponding to the previous OV) is wanted, the whole range can be shifted intact in the positive direction by 5V. The drain of transistor Q L '' can be set to OV and that of transistor Q D '' to 5V so that V in =1V. The output voltage V out in this case is 1.5V (a signal varied by 1.5V on the basis of +5V). Both n-channel and p-channel MOS transistors are used for in a CMOS type of LSI device, and any of the above circuits can be used therein, according to the purpose of the device. Bipolar transistors can be used instead of MOS transistor, the same operations as those of a MOS transistor can be accomplished by a circuit in which the collector, emitter and base of a bipolar transistor replace the drain, source and gate of a MOS transistor, respectively. When this discharge circuit is used together with the voltage limiter 30 with the characteristics of Figs. 4 and 9, the following effect is obtained, in the same way as in the charging circuit of Fig. 3. The amplitude of the voltage of the pulse signal applied to the gates of the transistors Q D '' (in Figs. 15 and 16) and Q L '' (in Fig. 16) follows the curve of Fig. 5 when the external supply voltage Vcc is higher or lower than V o , to control the operating speeds of the transistors Q D '', Q L ''. For example, in the transistor type of dynamic memory shown in Figs. 11A and 11B, even when the external supply voltage Vcc is varied in order to stabilize the memory operations between the memory array 1 and the direct peripheral circuits 2 and the indirect peripheral circuits 3, it is necessary to maintain the matching between the operating speeds of each of the circuits. However, when not using a voltage limiter having a characteristic such as that of Figs. 5 and 8, in which the gradient m is controlled so that it is less than the variation in the external supply voltage Vcc, the operating speed depends on the operating and manufacturing conditions because each circuit has a different operating mode, so that it is difficult to maintain this matching. In particular in recent years, the wiring resistances within the memory array circuit 1, the direct peripheral circuits 2, etc., have increased because of the increased integration of memories, and also the characteristics of MOS transistors make it more difficult to match them to the circuits which determine the operating speed. This problem is very important, particularly when the external supply voltage Vcc varies. Fig. 17 illustrates this state, with reference to an example in which a signal 101a must be generated when the waveform of a signal 100a has fallen below the voltage V crT . This is equivalent to the relationship between the discharge speed (100a) for the data lines D, D during read-out and the signal ₄(101a) for extracting those signals onto the I/O line. 100b denotes the discharge speed for the data lines D, D when the external supply voltage V cc drops. Since the discharge speed for a data line is mainly controlled by its wiring resistance, the time taken for discharge as far as the voltage V crT hardly varies in comparison with the signal waveform of 100a in a memory array in which the integration density and wiring resistance have been increased. However, since ₄(100a) generated by the peripheral circuits is usually determined by the characteristics of several MOS transistors, the time taken for its generation is greatly delayed, as shown by the signal waveform 101b, when the external supply voltage Vcc drops. In contrast, if an attempt is made to reduce the delay in the generation of the signal waveform 101b when the external supply voltage Vcc is low, the signal waveform 101b is generated earlier than that when the signal waveform 100b reaches V crT when the external supply voltage is high. Thus, if one of the circuits shown in Figs. 9, 15 and 16 is employed as a circuit controlling the delay in the signal waveform 101, the delay in the generation of the signal waveform due to variations in the external supply voltage Vcc can be elminated. This means that, since variations in the voltage output by the voltage limiter 30 are smaller than those in the external supply voltage Vcc, and the operating speeds of the transistors Q L ', Q D '', Q L '' (Figs. 9, 15 and 16) hardly vary, the signal waveform 101b can be generated earlier, as shown by the wave form 101b'. Accordingly, it is possible to realize a memory which can operate stably with no delaying in its access time. The memories of Figs. 11A and 11B have been described by way of example, but this method can be applied to any other type of memory with the same objectives, without any modification. As stated above, details of the present invention have been given in accordance with an embodiment thereof, but the potential application of the present invention should not be limited to these embodiments.

Claims: A semiconductor circuit comprising voltage limiter means (30D) for limiting a supply voltage (Vcc) to form a limited voltage (V DP ) which is substantially equal to the supply voltage (Vcc) when the latter is below a predetermined voltage level and which varies in accordance with the supply voltage (Vcc) with a gradient of change less than 1.0 when the supply voltage (Vcc) is above said predetermined voltage level, and pulse generating means (F) supplied with a first primary voltage (V L2 ) which differs from said limited voltage (V DP ) by a first amount (2V T ) for generating first output pulses (  P2ℓ ) in response to a first input signal (  P2 ), said output pulses (  P2ℓ ) having a voltage level limited by said first primary voltage (V L2 ) and being supplied to control terminals of first transistors (Q6, Q7), characterized in that said transistors (Q6, Q7) are coupled to data lines (D, D ) of a semiconductor memory to determine a precharge voltage level of the data lines, that said first primary voltage (V L2 ) is further supplied to pulse limiter means (G) for generating second output pulses ( xℓ ) in response to a second input signal ( x ), said second output pulses ( xℓ ) having a voltage level limited by said first primary voltage and being supplied to word lines (W₁, W₂) of said semiconductor memory through switching means (Q16, Q17, QD₁, QD₂) which are coupled to a word driver (A) to select at least one of a plurality of memory cells (QM₁, CM₁; QM₂, CM₂) coupled to said word lines, and that a second primary voltage (V L1 ), which differs from said limited voltage (V DP ) by a second amount (V T ), and said supply voltage are, supplied to voltage converter means (H) for generating an output voltage (V CP ) limited by said second primary voltage and supplied to second transistors (Q23, Q25, Q28, Q29) which are coupled to common data lines (I/O, I/O ) of said semiconductor memory to determine the voltage level on these common data lines. The circuit of claim 1, wherein said first and second primary voltages (V L2 , V L1 ) are different. The circuit of claims 1 or 2, wherein the word driver (A) operates in response to address signals. The circuit of any one of claims 1 to 3, wherein each of said memory cells (QM₁, CM₁; QM₂, CM₂) comprises one transistor and one capacitor. The circuit of any one of claims 1 to 4, wherein said first and second transistors (Q6, Q7, Q23, Q25, Q28, Q29) are field effect transistors. The circuit of any one of claims 1 to 5, wherein said second transistors (Q23, Q25, Q28, Q29) are supplied with input signals (din, din ). The circuit of any one of claims 1 to 6, wherein said common data lines (I/O, I/O ) are coupled to a read circuit (60). The circuit of any one of claims 1 to 7, wherein the voltage of said second output pulses ( xℓ ) is higher than that of said first ouput pulses ( P2ℓ ). The circuit of any one of claims 1 to 8, wherein said data lines (D, D ) are arranged substantially in parallel. The circuit of any one of claims 1 to 8, wherein two of said data lines (D, D ) are paired and arranged substantially in parallel, one memory cell (QM₁, CM₁; QM₂, CM₂) being arranged at each cross point between one of the word lines (W₁, W₂) and said paired data lines (D, D ). The circuit of any one of claims 1 to 10, wherein said data lines (D, D ) are coupled to a sense amplifier (Q1, Q2). The circuit of any one of claims 1 to 11, wherein said data lines (D, D ) and said common data lines (I/O, I/O ) are arranged at substantially right angles. The circuit of any one of claims 1 to 12, wherein said common data lines (I/O, I/O ) are paired. The circuit of any one of claims 1 to 13, wherein said supply voltage (Vcc) is directly supplied to the voltage converter means (H) and pulse generating means (F).

Inventors: ETOH, JUN, HORI, RYOICHI, ITOH, KIYOO
Applicants: HITACHI, LTD.
Application year: 1984
Main classification: H03K5
IPC codes: H03K19, G11C11