METHOD FOR FABRICATING HIGHLY CONDUCTIVE SILICON LINES

Abstract: A narrow silicon line which can be in the form of a gate pattern (30) is defined in a thin layer (16) of silicon on a semiconductor element (¦0) by applying a narrow ion beam (22) as provided by a focused-ion-beam source (24). The beam contains an ion which is a dopant in silicon. The layer (18) of silicon overlies a film (16) of oxide on a silicon or indium phosphide substrate (12). The ion beam can have a submicrometer dimension, can be translated to pattern a gate or interconnect line. The dopant ions are implanted into the polysilicon layer and thereby render the exposed portions of the layer preferentially insoluble to wet etchant. The non-exposed portions are preferentially removed to form a line or a gate (30). Standard FET processing may then be performed to provide source (32) and drain regions (34) as necessary to form a transistor device.

Description: METHOD FOR FABRICATING HIGHLY CONDUCTIVE SILICON LINES BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to the resistless fabri¬ cation of conducting lines and, more particularly, to the fabrication of gates and associated conductive lines for self-aligned MOSFET devices with gate lengths extending into the submicrometer region. 2. Description of the Prior Art Density and speed of integrated circuits are advancing rapidly as the Large Scale Integration (LSI) circuits with the current move towards Very Large Scale Integration (VLSI) circuits. These VLSI circuits or circuit elements have features on the order of micrometers which are manufactured by delineating patterns to permit plating, etching and doping. The features are usually defined by forming apertures in resist masks through which dopants, metal contacts, and electrodes are added, and/or to selectively etch material away to form a desired geometry. The use of resist masks defined by optical methods is usually limited to minimum features of about 1 to 2 micrometers. Henderson et al., J. Vac. Sci. Technol. , Vol. 6, p. 260, 1979, describe the use of a PMMA resist and an electron beam to define a submicrometer gate pattern in a resist. The resist pattern was then used as a mask for conventional flood ion implantation. The resist sidewalls were eroded during ion implantation, and consequently, submicrometer features could not be transferred precisely into the underlying gate material. Resolution of the resist is also affected by back- scattering of electrons during resist exposure. Thus, problems associated with the use of resist masks include poor resolution, swelling, susceptibility to pinholes and variances in repeatability. Naturally, resist mask resolution and quality control over the exposed resist material are both limiting factors in obtaining minimum feature dimensions. Recent advances in electron beam lithography have involved the use of direct-writing electron beam tools and systems replacing optical lithography. Electron beam lithography provides production of circuits without using lithography masks. Though some experimental e-beam resists capable of producing submicrometer lines have been announced, most problems associated with resist masks remain unchanged. Although ion beam lithography, as disclosed in U.S. Patent No. 4,383,026, offers some advantages over e-beam lithography, such as less backscatter and some improvement in resolution, it still is a resist-based process. Wang et al. (J. Vac. Sci. Technol., Vol. 19, (4), p. 1158, 1981) disclose a focused ion beam (FIB) for exposure of an ion sensitive resist. Pankove et al. ("Bombardment-Induced Corrosion Resistance of Aluminum," Appl. Phys. Lett., ' Vol. 39, p. 1.19, July 1981) and Gulkeberger (U.S. Patent No., 3,682,729) showed that after bombardment of aluminum films, the films resisted etching. However, there is no prior known self-masked, i.e., resistless etching process in which a focused ion beam has been directly utilized to form high conductive semiconductor features. O PI Many integrated circuits are composed of interconnected metal-oxide-semiconductor (MOS) field- effect transistors (FET). These MOSFETs contain a metal layer, a polysilicon layer, a thin oxide layer, and a diffusion or implant layer. Paths are formed in these layers and contact vias are cut through the insulating layer to permit the connection of certain points between layers. Wherever a path on the polysilicon level crosses a path on the thin oxide layer, bordered by implanted regions on the implant level, a transistor is formed. Circuits of such transistors, connected by patterned paths on these layers, form the basic circuits from which integrated circuit systems are designed. The region where the polysilicon path crosses the thin oxide layer is called the gate. The polysilicon gate masks the region under the gate during the formation of the implanted regions, thereby providing aligned source/drain regions. The gate, separated from the substrate by the layer of thin oxide, effectively forms a capacitor which acts as a switch. When voltage on the gate exceeds a threshold level, charge carriers may flow through the semiconductor region under the gate connecting drain and source regions. The dimension of the gate which separates drain and source regions (known as the length, L) affects both the packing density and the speed of the integrated circuit. Complimentary metal oxide semiconductor (CMOS) ICs, which consist of coupled n-channel MOSFETs and p-channel MOSFETs on the same chip, provide lower power performance, i.e., operate with substantially lower power dissipation, than comparable n-MOS ICs and, therefore, can be utilized to form VLSI circuits with higher scale integrations. One important consideration in fabricating CMOS ICs is selecting as appropriate gate material for both n- and p-channel FETs. Currently, phosphorus-doped n-type polysilicon is commonly used. Although the use of n-polysilicon is appropriate for the n-channel FETs, it is not desirable for the performance of the p-channel FETs. One may use p-type polysilicon for CMOS gates, however, the same problem would occur for the n-channel FETs. In principle, it is possible to use n-polysilicon for the n-channel FETs and p-polysilicon for the p-channel FETs. However, this would require one more masking step and several additional processing steps in IC fabrication. In addition, a larger layout area would be required for the connection between each n-polysilicon and p-polysilicon gate. Inherently, a poorer yield due to the added area and complexity in IC fabrication would also result. SUMMARY OF THE INVENTION An improved method of defining gates and interconnecting lines for semiconductor devices having dimensions in the submicrometer region is provided by the present invention. The method of the present invention eliminates the use of organic resists to define the gates or lines and, therefore, eliminates the problems associated with resist masks such as pinholes, swelling, and poor repeatability. The lines are provided with excellent edge resolution and the line size is not limited by the resolution of the resist. Circuits containing gates formed by the process of the present invention can be densely packed onto a chip. Processing steps and line width variations are substantially reduced. Mask resists and anisotropic etching are not ' required. The process of the invention provides better dimensional control in the submicrometer feature range while significantly increasing the yield of usable devices. Self-aligned gates may be defined by the process of the present invention by directing a narrow ion beam containing a dopant onto a thin layer of polysilicon overlying a semiconductor substrate. The ion beam is translated to selectively define a gate or line pattern at a dose between 0.1 and 50 x 10 15 cm" 2 . The doping ions are implanted into the polysilicon layer and render the polysilicon layer preferentially resistant to liquid etchant. Thus, preferential etching can now 10 be utilized without a mask to remove all surrounding material. The ion implanted polysilicon material remains with essentially vertical edge features. The process of the invention completely eliminates use of organic resist masks to define gates and narrow lines. -*-5 Lines as small as about 500 nm have been produced utilizing the method of the invention. The limit of line size can now be determined only by the ability to focus the spot size of the ion beam rather than resist resolution. MOSFET devices produced according to the 2(3 process of the invention show well-behaved transistor characteristics. The invention provides the unique capability of making p-type doped polysilicon gates for p-channel transistors with a focused acceptor ion beam such as 25 boron and making n-type doped polysilicon gates for n-channel transistors with a focused donor ion beam such as arsenic or antimony. Thus, both p- and n-channel transistors in a single integrated circuit can be optimized for performance. Consequently, the present 0 invention will enhance the utilization of CMOS technology in VLSI submicrometer applications. BRIEF DESCRIPTION OF THE DRAWING These and many other features and attendant advantages of the present invention will become apparent as the invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein like reference numerals designate line parts, and where: FIG. 1 is a cross-sectional view of a semiconductor element for forming a MOS device; FIG. 2 is a schematic view of the step of implanting ions into the element of FIG. 1; FIG. 3 is a cross-sectional view of a self- aligned MOSFET after etching and source/drain doping. FIG. 4 depicts the I-V (current voltage) characteristics of MOS transistors fabricated with a 38 n thick gate oxide layer and having a gate length (L) of 1.0 μ ; and, FIG. 5 depicts the I-V characteristics of MOS transistors prepared with a 12.5 nm thick gate oxide layer and having a gate length of 0.7 μm. DETAILED DESCRIPTION OF THE INVENTION Referring now to FIG. 1 the process for forming a gate on a MOSFET device is illustrated in FIG. 1. A typical partially prepared MOSFET wafer 10 is comprised of a semiconductor substrate 12 containing a channel region 14. The substrate can be doped n or p at the time of processing and can be silicon, germanium or a compound semiconductor, such as indium phosphide (InP). A thin film 16 of insulator such as silicon dioxide remains in the bottom of the channel region 14. The film 16 under the channel region is usually from 100 Angstroms to 1000 Angstroms in thickness and 10 to 20 times thinner than the portion of the film 16 outside the channel region 14. A layer 18 of substantially undoped polysilicon is deposited onto the oxide film 16. The layer 18 is generally from 1,000 Angstroms to 10,000 Angstroms in thickness, and preferably between approximately 2,000 to 5,000 Angstroms thick. Referring now to FIG. 2, a gate pattern 20 is defined in the layer 18 by selectively implanting ions into the layer 18 utilizing a focused ion beam 22 (FIB) from source 24. For example, the beam 22 can contain boron ions to dope the selected portion 20 of the layer 18 p-type. Alternately, the beam can contain antimony, arsenic or phosphorous ions to dope the selected portion 20 of the layer 18 n-type. The minimum top surface dimension of the selected portion 20 to form a gate is generally no more than four micrometers and preferably one or less. Naturally, this ultimate minimum feature dimension is limited to the minimum focusing resolution of the FIB source 24. The beam has an energy generally from 1 to 1000 keV, though preferably between approximately 20 to 500 keV. The dose should be maintained between 0.1 and 50 x 10^ cm" 2 , though preferably between approximately 1 and 10 x lO 5 cm -2 . The area scanned by the FIB is thus preferably heavily doped (>10^ 9 cm"-- ) and becomes n + or p + polysilicon. The wafer 10 is then subjected to an etching step utilizing a wet etchant preferably comprising 1 gram KOH and lOOcc H2O maintained at a temperature of approximately 55°C. According to the present invention, heavily doped polysilicon, even of the small dimensions suggested by the present invention, is preferentially insoluble in wet etchant. OMPI * v Referring now to FIG. 3, after the wafer 10 is subjected to the silicon wet etchant, a narrow gate 30, comprising the heavily doped polysilicon, remains with the undoped polysilicon having been etched away. Device manufacture is completed by standard IC processing to implant ions to form a source region 32 on one side of the gate 30 and a drain region 34 on the other side. The area 36 underlying the gate 30 is not implanted due to the presence of the gate 30. Example A submicrometer polysilicon gate was formed on an n-MOSFET according to the process of FIGS. 1-3. All gate lithography was performed using a three-lens, mass separated, focused ion beam system (Wang et al. supra) with a Pt-B alloy liquid metal ion source ' capable of emitting B + ions from a single ion emitter tip. The current density at the wafer surface was approximately 4 x 10~ 2 A/cm 2 . The shape of the gate lithography and the dose delivered was controlled by a pattern generator coupled to an electrostatic deflector in the FIB system 24. The smallest beam resolution step used was 40 nm and multiple passes were used to provide the total ion doses. The process steps for fabrication of a polysilicon gate on a silicon wafer are as follows: OMΠ _m& Starting Material: (100) Si Wafer Step Process Description 1 Oxide Formation by Wet Oxidation: *5000 A oxide thickness; 2 Etch the oxide away from channel regions, regrow a thin gate oxide (100-400 A) in the channel regions; 3 Undoped poly-Si deposition by LPCVD: -5000 A poly-Si thickness; 4 Patterning and selective ion implantation using focused Boron ion beam at 50 keV to a dose of 5 x 10 15 cm" 2 ; 5 Anneal at ~ 900° C ; 6 Preferential etching using KOH : H2θ;. 7 Rinse by H2O; and 8 Complete MOSFET fabrication utilizing standard IC processing steps. The completed poly-Si gates lengths ranged from 0.05 μm to 4 μm depending on the desired implant pattern and are approximately 50 μm wide for all of the devices. A 50 keV B + beam has a mean depth of penetration of about 2500 Angstroms in poly-Si. The high p + -doped poly-Si was then utilized as the gate material to form self-aligned n-MOSFETs in the subsequent conventional MOS processing, though only in those cases where the gate length was greater than approximately 0.5 μm. Electrical performance of these.devices is shown in FIGS. 4 and 5. The MOSFETs had 38 and 12 nm gate oxide thicknesses and lengths of 1.0 μm and 0.7 ym. Transistors with transconductances as large as 100 mS/mm were obtained. The devices showed well-behaved transistor characteristics. The process of the invention can be utilized to define submicrometer gates (down to the minimum focusing resolution of the FIB) or relatively larger conductor lines on any insulator or semiconductor substrate by forming a pattern in an overlying layer of silicon. The invention eliminates the use of positive or negative organic resist masks. The process of the invention results in 1/1 transfer of pattern from the exposed layer into the underlying layer. The edge walls of the features provided by the present invention are essentially vertical regardless of the minimum top surface dimension of the feature. It is to be realized that only preferred embodiments of the invention have been described and that numerous substitutions, modifications and alterations are permissible without departing from the spirit and scope of the invention as defined in the following claims.

Claims: CLAIMS What is Claimed is: 1. A method of forming a conductive feature of a semiconductor device on a substrate comprising the steps of: a) providing a substantially undoped semiconductor layer on a surface of said substrate; b) directing a narrow ion beam onto a selected portion of an exposed top surface of said layer corresponding to said conductive feature, said ion beam comprising a dopant ion species whereby said selected portion of said layer is highly doped with respect to the remainder of said layer; and c) wet etching said layer so as to preferentially remove the undoped remainder of said layer leaving said conductive feature. 2. The method of Claim 1 wherein the minimum dimension of said elected portion is four micrometers or less. 3. The method of Claim 2 wherein the implant energy of said ion beam is between approximately 1 and 1000 keV, the implant dose is between approximately 0.1 and 50 x 10 15 cm" 2 , and the thickness of said layer is between approximately 0.1 and 1.0 micrometer. 4. The method of Claim 3 -wherein the minimum dimension of said selected portion is approximately one micrometer or less. _ . OMH _ 5. The method of Claim 4 wherein the implant energy of said ion beam is between approximately 20 and 500 keV, the implant dose is between approximately 1.0 and 10 x 10 15 cm" 2 , and the thickness of said layer is between apprOximately 0.2 and 0.5 micrometers thick. 6. The method of Claim 5 wherein said layer comprises silicon. 7. The method of Claim 6 wherein said substrate includes an oxide layer interposed between said semiconductor layer and the remainder of said substrate. 8. The method of Claim 7 wherein said wet etchant comprises potassium hydroxide. 9. The method of Claim 8 wherein said layer comprises polysilicon. 10. The method of Claims 1, 3, 5, or 8 further comprising the steps of: a) annealing said layer after the ion implantation step and prior to the wet etching step; and b) forming source and drain regions in said substrate closely associated with said conductive feature so as to form an FET. 11. A semiconductor device fabricated in accordance with the method of Claim 10. JOM?__

Inventors: CHEN JOHN YUAN-TAI, RENSCH DAVID B, CHEN, JOHN, YUAN-TAI, RENSCH, DAVID, B.
Applicants: HUGHES AIRCRAFT CO, HUGHES AIRCRAFT COMPANY
Application year: 1984
Main classification: H01L21
IPC codes: H01L21