METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract: The invention deals with a semiconductor device which comprises a semiconductor substrate (11) of a first conduc­ tivity type, a semiconductor region (14, 15) formed on said substrate, and a first insulation film (120, 77) provided between said semiconductor region and said semiconductor substrate, wherein said semiconductor substrate is isolated by said insulation film from a polycrystalline silicon layer (79, 121) formed in the periphery of said semiconductor region (14, 15) thereby to reduce the parasitic capacitance, and wherein said insulation film (79, 121) is stretched and arranged on the lower side of said semiconductor region.

Description: Background of the Invention The present invention relates to a method for manufacturing a semiconductor device structure, and more particularly a semiconductor device structure which can be effectively adapted to bipolar transistors in a very small integrated circuit which exhibits a very high switching speed, which dissipates very small electric power, and which has a high breakdown voltage. A conventional representative structure of bipolar transistors is shown in Fig. 1, in which reference numeral 11 denotes a silicon substrate of p conductivity type, and 12a, 12b represent n⁺-type buried layers. The n⁺-type buried layer 12a is connected as a base electrode of a lateral pnp transistor to an electrode 18e via an n⁺-type contact region 13, and the n⁺-type buried layer 12b is connected as a collector electrode of a vertical npn transistor to the electrode 18e via the n⁺-type contact region 13. The lateral pnp transistor is formed by using a p-type region 15a as an emitter, p-type region 15b as a collector, and n-type region 14a as a base. The vertical npn transistor is also formed by using an n⁺-type region 16 as an emitter, p-type region 15c as a base, and n-type region 14b as a collector. Reference numeral 17 denotes an isolation region. In the device of Fig. 1, parasitic regions unnecessary for the transistor action, i.e., regions under the electrodes 18a, 18b and 18c, occupy more than 80% of the total areas to considerably deteriorate the characteristics of the transistors. Namely, in the lateral pnp transistor, excess of emitter current and base current flow through an emitter-base junction under the emitter electrode 18a, so that the consumption of electric power increases and the current gain decreases. Further, the hole charge is stored in large amounts in the base region 14a to strikingly deteriorate high-frequency characteristics. In the vertical npn transistor, on the other hand, the capacitance of base-collector junction increases under the base electrode 18c to increase the propagation delay time of the logic circuit. Moreover, when the vertical npn transistor is operated in the reverse direction so that the emitter comes to the substrate side, the region under the base electrode 18c works as a parasitic diode which deteriorates the current gain and high-frequency characteristics. That is, when the vertical npn transistor is operated in the reverse direction, the injection efficiency from the emitter 12b (the collector in the forward operation becomes the emitter in the reverse operation) decreases. Therefore, the presence of these parasitic regions markedly deteriorates the performance of the npn transistors when they are operated in the reverse direction or are operated in saturation mode like in an I²L (integrated injection logic) circuit or in a TTL (transistor-transistor logic) circuit. Fig. 2 shows another conventional bipolar transistor structure which is free from the above-mentioned defects. According to this example, an oxide film 120 is inserted in the parasitic regions to reduce the dissipation of electric power and to gain a high switching speed. In Fig. 2, reference numeral 121 denotes a polycrystalline silicon containing p-type impurities at a high concentration. An emitter region 15a and a collector region 15b of the lateral pnp transistor, as well as a doped monocrystalline region 15c which serves to connect the base region proper with the polycrystalline region 121, (and which in the following is referred to as a graft base region 15c of the vertical npn transistor) are formed by the diffusion of p-type impurities from the polycrystalline silicon. Reference numeral 19 denotes a p-type intrinsic base region formed by the ion implantation method or the like. The above-mentioned technique has been disclosed in IBM T.D.B. Vol. 23, No. 9, February 1981, pp. 4166-4167, and in EP-A-0 045 848. The structures disclosed in the above-mentioned patent applications still have defects as described below, although their performance is considerably improved compared with the performance of the aforementioned first conventional structure. (1) The graft base 15 and the buried layer 12 often come into contact with each other, giving rise to the occurrence of failure on breakdown voltage and leakage of current, and causing high-frequency characteristics to be deteriorated. In particular, the I²L circuit and the like circuits will be seriously affected, in which the n-type layer 14 has a reduced thickness so that the hole charge is stored in reduced amounts. (2) In the vertical npn transistor, the performance deteriorates just like in (1) above, since the graft base comes into contact with the emitter region 16. (3) The contacting portion between the emitter and the graft base of the vertical npn transistor must be located under the oxide film 122 which is formed on the surface of the substrate. That is, as the contacting portion comes under the emitter electrode 18d, there develops emitter-base short. If the contacting portion enters into the polycrystalline silicon which serves as a base electrode, the current gain decreases due to the difference in built-in potential at the PN junction between a single crystal and a polycrystal. The contacting portion can be controlled by controlling the oxide film 122 on the substrate surface and by controlling the graft base 15c. Namely, it is considerably difficult to control the contacting portion. Another semiconductor device including a vertical bipolar transistor is known from IBM T.D.B. Vol. 23, No. 73, December 1980, pp. 3242-3245. In this structure, doped regions for connection of the base with the polycrystalline regions are provided in lateral portions of the base which are recessed from the opening in the oxide film separating the transistor area against the underlying semiconductor area. Summary of the Invention The object of the present invention is to provide a method which is easy to control, for manufacturing a semiconductor device which is free from the aforementioned defects, and which features a high packing density and improved high-frequency characteristics. The above-mentioned object is achieved by the method defined in claim 1. Relying upon the above-mentioned structure, there is provided a bipolar semiconductor device which features markedly reduced base resistance and parasitic capacitance. Brief Description of the Drawings Fig. 1 is a section view showing the structure of a conventional lateral transistor and a conventional vertical transistor; Fig. 2 is a section view showing the structure of a more evolved conventional transistor which is less affected by the parasitic effect; Fig. 3 is a section view showing the structure of a lateral transistor and a vertical transistor manufactured according to the present invention; and Figs. 4A to 4M are diagrams of steps for manufacturing a semiconductor device according to the present invention. Detailed Description of the Invention Fig. 3 is a section view showing the structure of a first bipolar semiconductor device and a second bipolar semiconductor device according to an embodiment of the present invention. To clearly describe the invention, reference numerals used in the above-mentioned conventional examples of Figs. 1 and 2 are also used in the description, unless otherwise stated. In Fig. 3, reference numeral I denotes a lateral transistor, and II denotes a vertical transistor. In the structure of Fig. 3, the single crystalline semiconductor regions occupy greater areas than the openings of silicon dioxide film, and the upper and lower side surfaces of the graft base regions 15a, 15b and 15c are covered by an insulator. Therefore, the graft base does not come into contact with the buried layer 12, and the aforementioned defect (1) is precluded. Owing to the oxide film 122 on the graft base, furthermore, the pn junction is easily formed, and the aforementioned defect (3) is eliminated. Described below is a manufacturing method according to the present invention. Figs. 4A to 4M illustrate an embodiment for manufacturing the first and second semiconductor devices. Fig. 4A: A silicon substrate of p conductivity type is prepared. The substrate may be of the n type. In this case, however, the impurities must possess the opposite type of conductivity. Further, instead of using an electrically conductive material, the substrate may be the one of the type in which an electrically conductive material is placed on an insulator, as represented by an SOI (silicon on insulator) or SOS (silicon on sapphire), or the like. The inventors have employed the substrate containing the impurities of the p type at a concentration of 5 x 10¹⁴/cm³. The substrate was thermally oxidized to form a thin silicon dioxide film 71 on the surface of the substrate. The inventors have effected the thermal oxidation at a temperature of 1000°C for 150 minutes to obtain a silicon dioxide film which was 600 nm thick. Then, relying upon the customarily employed photolithographic technology, an opening is formed in the silicon dioxide film 71 in order to form an n⁺-type buried layer (n⁺ BL) 12 of a high concentration. The n⁺-type buried layer (n⁺ BL) 12 having a desired impurity concentration is formed through the opening relying upon the diffusion or ion implantation technique. When the ion implantation technique is employed, the thermal annealing is usually effected. According to the present invention, however, the step of thermal treatment is not particularly required, since the same effect is imparted to the ion-implanted layer in a subsequent step. Fig. 4B: Then, the silicon dioxide film 71 is removed to expose the surface of the substrate, and an n-type single crystalline layer (n-Epi) 14 is formed by the epitaxially growing method. The epitaxial layer 14 can be formed in any desired thickness by adjusting the growing time and the temperature. The inventors have obtained the epitaxial layer 14 that was 1 µm thick. Next, a silicon dioxide film 72 is formed by thermal oxidation. Deposition process also could be use. Thereafter, a silicon nitride film 73 is formed by deposition. A silicon dioxide film 74 is then formed by deposition. The inventors have formed three layers, i.e., silicon dioxide film 72, silicon nitride film 73 and silicon dioxide film 74 having thicknesses of 50 nm, 120 nm and 900 nm, respectively. Fig. 4C: The epitaxially grown layer is then subjected to the etching leaving the region 14 for forming elements and the region 13 for taking out the electrode, in order to form protruded regions. Since the protruded regions are formed by the anisotropic dry etching, there takes place almost no side etching. Fig. 4D: A silicon dioxide film 75 is formed again by similar process for film 72. In this case, however, the film 75 may have a slightly different shape. Then, a silicon nitride film 76 is formed thereon by deposition. The inventors have formed the silicon dioxide film and the silicon nitride film having thicknesses of 50 nm and 120 nm, respectively. Fig. 4E: Then, the anisotropic dry etching is effected in such a manner that the silicon nitride film 76 is left only on the side surfaces of the region 14 for forming elements and of the region 13 for taking out the electrode. No photomask is required for effecting the anisotropic dry etching. Fig. 4F: The thermal oxidation is then effected using the silicon nitride film 76 as a mask, thereby to form a thick oxide film 77. The inventors have formed the oxide film that was 700 nm thick. Then, the silicon nitride film 76 is removed and, then, the silicon dioxide film 75 is removed. When the silicon dioxide film is to be removed, the side surfaces of the region 13 for taking out the electrode are covered by a relaxed mask so that the silicon dioxide film 75 is not removed from the side surfaces. Accordingly, the silicon dioxide film 75 is not removed from the covered surfaces. Fig. 4G: An epitaxial layer 78 is formed by the selective epitaxially growing method on only the surfaces where the single crystal is exposed in the regions for forming elements. According to this method, the single crystalline layer can be formed on the desired portions only but not on the silicon dioxide film, by suitably selecting the atmosphere. The inventors have formed the single crystalline layer 78 at a temperature of 850°C by using an SiCl₄ gas. The art related to this method has been closely disclosed in JP-A-126259/1978. Fig. 4H: A polycrystalline silicon layer 79 is deposited on the whole surface. To remove unnecessary portions of the polycrystalline silicon layer 79, the surface of the substrate for forming elements is made flat by using a photoresist film. The inventors have made the surface flat by using two photoresists 80, 81. The photoresist 80 formed earlier should not be dissolved by the photoresist 81 that is formed later. This makes it possible to obtain a sufficiently flat surface with a minimum thickness of photoresist films. Fig. 4I: The anisotropic dry etching is effected up to the portions corresponding to the regions for forming elements. Fig. 4J: A silicon dioxide film 710 is formed by the thermal oxidation method or by deposition. A silicon nitride film 711 is then formed by deposition. The inventors have formed these films in thicknesses or 30 nm and 120 nm, respectively. In order to isolate the elements, furthermore, desired portions of the polycrystalline silicon layer 79 are oxidized to form silicon dioxide film. In this case, the thickness of the polycrystalline silicon layer of the portions to be oxidized should have been reduced to one-half beforehand by etching, so that the thickness after the oxidation will became nearly the same as the thickness of other polycrystalline silicon portions, and so that a flat surface is obtained. This is favorable for forming wirings on the element-forming region. Namely, if the elements have flat surfaces, the wirings are less broken when they are being formed. Then, the structure shown in Fig. 4K is obtained through the oxidation. Fig. 4L: Next, the silicon dioxide film 710 and the silicon nitride film 711 are removed, and boron ions are implanted into the polycrystalline silicon layer 79. Then, a silicon dioxide film 122 is formed by thermal oxidation. A silicon nitride film 713 is then formed by deposition, and the silicon nitride films 713, 73 are removed from the portion 13 where an n-type high-concentration region is to be formed. The surface of the silicon dioxide film 17 is little affected by the implantation of ions, and a roughly shaped mask needs be employed. Fig. 4M: After the silicon nitride film 713 is removed, impurity ions are implanted or are introduced by diffusion via a photoresist 714 to form a base region and an emitter region. By providing the electrodes such as of base, emitter and collector, there is obtained the structure which is shown in Fig. 3. In Fig. 3, the lateral transistor and the vertical transistors are formed separately. In Figs. 4A to 4M, however, the collector of the lateral transistor and the base of the vertical transistor are connected to each other through the same polycrystalline silicon layer. Which structure should be employed has no relation to the nature of the invention, and should be determined depending upon the application. The above-mentioned manufacturing method has employed the anisotropic dry etching method. Generally, however, the dry etching method is susceptible to contamination. To prevent the contamination, therefore, it is recommended to add a step for cleaning the surface after the step of dry etching, to obtain good results. In the above-mentioned embodiment, the insulator is formed by thermally oxidizing the silicon, or is composed of a silicon nitride film, or is composed of an insulating material. The device manufactured according to the invention can also be realized by using other semiconductor materials such as GaAs and the like. In the embodiments of the present invention, furthermore, the conductivity types, i.e., r-type and n-type can be reversed. In the embodiments of the invention, moreover, gallium ions and arsenic ions can be used instead of boron ions and phosphorus ions. In the devices manufactured according to the present invention, the graft base layer of a high concentration does not come into contact with the emitter and collector regions, and it is made possible to realize a bipolar transistor which features reduced parasitic capacitance, increased breakdown voltage, and small noise. In particular, it is allowed to easily form a shallow junction and a thin epitaxial layer, and hence to realize a bipolar transistor which exhibits a switching speed of two or more times faster than that of the conventional devices.

Claims: A method for manufacturing a bipolar semiconductor device including a vertical bipolar transistor (II) on a semiconductor substrate (11) of a first type of conductivity, comprising the following steps: (a) forming a highly doped region (12) of a second type of conductivity on said substrate (11), (b) forming a protruding first single crystal semiconductor region (14) of the second conductivity type on said highly doped region (12), (c) covering the upper surface of said first single crystal semiconductor region (14) with a mask (72, 73, 74) and the exposed surface of said highly doped region (12) with a first insulation film (77), (d) growing single crystal semiconductor material (78) on the exposed side surface of said protruding first single crystal semiconductor region (14) to enlarge the protruding first single crystal semiconductor region (14) above said first insulation film (77), (e) depositing a polysilicon layer (79) of the first conductivity type on said first insulation film (77), covering the side portion of said single crystal semiconductor material (78), (f) covering the polycrystalline silicon layer (79) and said grown semiconductor material (78) by a second insulation film (122), therby forming a doped region (15) the upper and lower surfaces of which are covered by said first (77) and said second (122) insulation film, by diffusion of impurities from said polycrystalline silicon layer (79) into said grown single crystal semiconductor material (78), said doped region (15) not coming into contact with said highly doped region (12), and (g) introducing impurities into surface portions of the enlarged first single crystal semiconductor region (14, 78) to form a first impurity region (16) of the second type of conductivity at its upper surface constituting an emitter or a collector region of said vertical bipolar transistor (II), and a second impurity region (19) of the first type of conductivity in contact with said doped region (15) and constituting the base of said bipolar transistor. The method of claim 1, wherein additionally a lateral transistor is formed by producing, in step (b), a protruding second single crystal semiconductor region (14), and performing the steps (c) to (f) also on said protruding second single crystal semiconductor region (14), wherein said protruding second single crystal semiconductor region (14) constitutes the base and the doped regions (15) formed on opposite sides of said protruding second single crystal semiconductor region (14) constitute the emitter and collector of the lateral transistor. The method of claim 2, wherein the impurities are selected such that the conductivity types of the base, emitter and collector of said lateral transistor are opposite to those of said vertical transistor.

Inventors: MIYAZAKI, TAKAO, NAGATA, MINORU, NAKAMURA, TOHRU, NAKAZATO, KAZUO, NATSUAKI, NOBUYOSHI, OGIRIMA, MASAHIKO
Applicants: HITACHI, LTD.
Application year: 1984
Main classification: H01L21
IPC codes: H01L29, H01L21