Semiconductor memory device

Abstract: A semiconductor memory device comprising a volatile memory cell (1, 11, 11') and a nonvolatile memory cell (16, 17, 20, 21, 22, 23) corresponding to the volatile memory cell, the nonvolatile memory cell comprising a transistor (Q₆₁, Q₇₃, Q₈₁, Q₉₃, T M ) which has a floating gate and is operable to turn on or off in response to memorised data, a tunnel capacitor (TC₆₁, TC₆₂, TC₇₁, TC₈₁, TC₉₁, TCa), one electrode of which is connected to the floating gate, and write circuits coupled to electrodes of the tunnel capacitor. The write circuits are operable to supply writing voltages (V H1 , V H2 ; V H1 , V H ) to the tunnel capacitor in response to the memorised data of the volatile memory cells, and the tunnel capacitor is arranged both to inject electrons to, or remove electrons from, the floating gate of the transistor depending on the writing voltages.

Description: The present invention relates to a semiconductor memory device, more particularly it relates to a nonvolatile memory device constituted by combining a volatile memory cell and a nonvolatile memory cell including a floating gate circuit element. Recently, in a static random access memory device (RAM), a volatile memory cell is combined with a floating gate circuit element to obtain a nonvolatile memory cell which is used to constitute a nonvolatile memory device. In a nonvolatile memory device of this type, the circuit configuration of each memory cell tends to be complex, and so the size of each memory cell tends to be large. However, this tendency leads to degradation in the reliability and integration of the memory device. In view of this problem, this tendency must be eliminated by a special circuit configuration or the like. An example of prior art relevant to this invention is disclosed in U.S. Patent No. 4 300 212, and is explained later in this text. Electronic Design, vol. 29, no. 4, 19.2.81, Waseca, MN, Denville, U.S.A., pages 72 to 82 discloses (Fig.7) a semiconductor memory device according to the preamble of accompanying claim 1. In this device two tunnel capacitors are required in each nonvolatile cell. Another device disclosed in the same document (Fig. 6) employs a single DEIS (Dual Electron Injection Structure) capacitor in a nonvolatile cell. EP-A-0 087 007 discloses a semiconductor memory device in which a nonvolatile cell employs a single DEIS capacitor, to which a positive or negative write voltage is applied depending on the information to be stored. According to the present invention there is provided a semiconductor memory device comprising a volatile memory cell and a nonvolatile memory cell corresponding to the volatile memory cell, said nonvolatile memory cell comprising a transistor which has a floating gate and is operable to turn on or off in response to memorised data, a tunnel capacitor, one electrode of which is connected to the floating gate, and write circuitry coupled to the tunnel capacitor, for supplying a high voltage as a write voltage to said tunnel capacitor in response to the memorised data of said volatile memory cell; characterised in that: said write circuitry includes first and second high voltage sources which are capacitively coupled to the floating gate, one of them being coupled to the floating gate across the tunnel capacitor; said high voltage sources are arranged such that during a write operation, the first high voltage source applies a high voltage first and the second high voltage source applies a high voltage subsequently at a time when the first high voltage is not being applied; and in that said nonvolatile memory cell further comprises means which capacitively couple or do not couple the floating gate to a low voltage source depending on the memorised data of the corresponding volatile memory cell, such that charges are injected via the tunnel capacitor to the floating gate when applying the first high voltage and charges are removed or not removed from the floating gate via the tunnel capacitor depending on the state of the corresponding volatile cell when the second high voltage is subsequently applied during the write operation. An embodiment of the present invention can provide a semiconductor memory device wherein the number of circuit elements is reduced, the area of a cell by which the device is constituted is reduced, high integration of the circuit is obtained, and the number of tunnel capacitors which are the constituent elements are decreased, thereby increasing the production yield. An embodiment of the present invention can increase the discretion of the layout design regarding the memory cell circuit. An embodiment of the present invention can increase the storing efficiency by a plurality of write voltage applications. Reference is made, by way of example, to the accompanying drawings in which:- Fig. 1 shows a circuit diagram of a memory cell used in a conventional semiconductor memory device; Fig. 2 shows a circuit diagram of a memory cell used in a semiconductor memory device according to an embodiment of the present invention; Fig. 3 shows a circuit diagram of a memory cell as a modification of the memory cell in Fig. 2; Fig. 4 shows a partial circuit diagram of a memory cell as another modification of the memory cell in Fig. 2; Fig. 5 shows a circuit diagram of a memory cell used in a semiconductor memory device according to a second embodiment of the present invention; Fig. 6 shows a partial circuit diagram of a memory cell as a modification of the memory cell in Fig. 5; Fig. 7 shows a partial circuit diagram of a memory cell as another modification of the memory cell in Fig. 5; Fig. 8 shows a circuit diagram of a memory cell used in a semiconductor memory device according to a third embodiment of the present invention; Fig. 9 shows a partial circuit diagram of a memory cell as a modification of the memory cell in Fig. 8; Fig. 10 shows a circuit diagram of a memory cell used in a semiconductor memory device according to a fourth embodiment of the present invention; Fig. 11 shows a circuit diagram of a memory cell used in a semiconductor memory device according to a fifth embodiment of the present invention; Fig. 12 shows a sectional view of an EEPROM (electrically erasable programmable read only memory) used in a memory cell in Fig. 11; and Fig. 13 shows an equivalent circuit diagram of an EEPROM in Fig. 12. Before describing embodiments of the present invention, an explanation will be given of the prior art. In Fig. 1, a memory cell used in a conventional nonvolatile memory device is shown. The memory cell in Fig. 1 comprises a volatile static memory cell portion 1 comprising MIS (metal insulator semiconductor) transistors Q₁, Q₂, Q₃, Q₄ and Q G , and a nonvolatile memory cell portion 2 having a MIS transistor Q₆ with a floating gate and the like. The memory cell stores one-bit data. The nonvolatile memory cell portion 2 has, in addition to the MIS transistor Q₆, a MIS transistor Q₅, tunnel capacitors TC₁ and TC₂, a capacitor module CM₁, and capacitors C₁ and C₂. A capacitor which generates a tunnel effect by the application of a voltage between the electrodes thereof will be hereinafter called a tunnel capacitor. In the circuit shown in Fig. 1, the static memory cell portion 1 has a flip-flop configuration which is ordinarily used in a conventional static RAM device. Data read/write is performed through a transfer gate transistor Q G connected to nodes N₁ and N₂. The nonvolatile memory cell portion 2 has a floating state wherein the circuit including the gate of the MIS transistor Q₆ floats from the other circuit components. Data is stored by injecting or not injecting electrons into this floating circuit. Therefore, a high-speed nonvolatile memory device can be realized with a transfer and a recall configuration; i.e., by transferring data of the static memory cell portion to the nonvolatile memory cell portion 2 before a power source V CC for the memory device is cut off and transferring the data from the nonvolatile memory cell portion 2 to the static memory cell portion 1 (recall) when the power source V CC is turned on. Assuming that predetermined data is written in the static memory cell portion 1, the node N₁ is at low level (V SS ), and the node N₂ is at high level (V CC ). Thus, when the data of the static memory cell portion 1 is transferred to the nonvolatile memory cell portion 2 in this state, a control power source voltage V HH is usually boosted from 0 V to between 20 and 30 V. Since the node N₁ is at low level, the transistor Q₅ is cut off, and, since an electrode D₁ of the capacitor module CM₁ is floating, the gate of the transistor Q₆ is boosted to a high voltage due to capacitive coupling by boosting the power source voltage V HH . Since a capacitance C (D₁ , D₂) between the electrodes D₁ and D₂ of the capacitor module CM₁ and a capacitance C (D₁ , D₃) between the electrodes D₁ and D₃ thereof are both sufficiently larger than the capacitances of the tunnel capacitors TC₁ and TC₂ , the gate voltage of the transistor Q₆ is boosted to a voltage close to the power source voltage V HH . A high voltage is then applied across the two ends of the tunnel capacitor TC₁. Electrons are injected into the floating gate of the transistor Q₆ from the power source V SS by the tunnel phenomenon, the floating gate is negatively charged, and the transistor Q₆ is cut off. This negative charge is held after the power sources V CC and V HH of the memory device are cut off, thereby achieving nonvolatile data storage. In contrast to this, when the node N₁ of the static memory cell portion 1 is at high level and the node N₂ thereof is at low level, the transistor Q₅ is ON. Therefore, when the power source voltage V HH is boosted to, for example, 20 to 30 V, the electrode D₁ of the capacitor module CM₁ is kept at low level. A high voltage is then applied across the two ends of the tunnel capacitor TC₂. The tunnel phenomenon causes the electrons to be extracted from the side of the floating gate of the transistor Q₆ to the side of the power source V HH . Thus, the floating gate is positively charged. For example, the operation for transferring the data of the nonvolatile memory cell portion 2 to the volatile memory cell portion 1 upon power source on will be described below. First, of the power source voltages V CC and V HH at 0 V (= V SS ), the power source voltage V CC alone is boosted to, for example, 5 V. If electrons are stored in the floating gate of the transistor Q₆ , the transistor Q₆ is cut off, and the conduction between the capacitor C₂ and the node N₂ is also cut off. Since the node N₁ is connected to the capacitor C₁ , the flip-flop circuit of the volatile memory cell portion 1 is set so that the node N₁ having a larger load capacitance is at low level and the node N₂ is at high level when the power source voltage V CC is boosted. However, if the electrons are extracted from the floating gate of the transistor Q₆ and a positive charge is stored in the floating gate, the transistor Q₆ is turned on and the node N₂ and the capacitor C₂ are connected to each other. Since the capacitance of the capacitor C₂ is sufficiently larger than that of the capacitor C₁ , the flip-flop circuit of the volatile memory cell portion 1 is set so that the node N₂ is set at low level and the node N₁ is set at high level when the power source voltage V CC is boosted. In this manner, the data is set in the volatile memory cell portion 1 in accordance with the charge stored in the floating gate of the transistor Q₆. When the circuit shown in Fig. 1 is used, a nonvolatile memory device can be realized. However, in the conventional circuit shown in Fig. 1, two tunnel capacitors are used. In a tunnel capacitor, the thickness of the insulating film and the film quality must be controlled with high precision. Therefore, the manufacturing yield of the memory device is lowered. The preferred embodiments of the present invention will be now described with reference to the accompanying drawings. Figure 2 shows a circuit diagram of a memory cell of a semiconductor memory device according to an embodiment of the present invention. The memory cell has a volatile static memory cell portion 1 and a nonvolatile memory cell portion 16. The volatile static memory cell portion 1 is the same as the conventional static memory cell, and a detailed description thereof will be omitted. The nonvolatile memory cell portion 16 has a MIS transistor Q₆₂ , a MIS transistor Q₆₁ , a capacitor module CM₆₁ , capacitors C₆₁ and C₆₂ , and a tunnel capacitor TC₆₂ which is a floating gate element. One cross-coupled connecting point, i.e., a first node N₁ , of a flip-flop of the volatile static memory cell portion 1 is connected to a power source V SS (normally grounded) through the capacitor C₆₁. The other cross-coupled connecting point, i.e., a second node N₂ , of the flip-flop is connected to the power source V SS through the transistor Q₆₁ and the capacitor C₆₂. A first high-voltage control power source V H1 is connected to the gate of the transistor Q₆₁ and an electrode D₆₃ of the capacitor module CM₆₁ through the tunnel capacitor TC₆₁. A second high-voltage power source V H2 is connected to the electrode D₆₂ of the capacitor module CM₆₁. An electrode D₆₁ of the capacitor module CM₆₁ is connected to the power source V SS through the transistor Q₆₂. The gate of the transistor Q₆₂ is connected to the node N₁. The capacitor module CM₆₁ has capacitances between the electrodes D₆₁ and D₆₂ and between the electrodes D₆₁ and D₆₃. Each of the capacitances is selected to be sufficiently larger than that of the tunnel capacitor TC₆₁. The capacitance of the capacitor C₆₂ is set to be larger than that of the capacitor C₆₁. The operation of the above-mentioned memory cell will be described. First, data in the volatile static memory cell portion 1 is transferred to the nonvolatile memory cell portion 16 in the following manner. The high-voltage control power source voltage V H2 is set at 0 V (ground potential) and the high-voltage control power source voltage V H1 is boosted from 0 V to about 20 V. The voltage of about 20 V is applied in series with the tunnel capacitor TC₆₁ , the capacitance between the electrodes D₆₃ and D₆₁ , and the capacitance between the electrodes D₆₁ and D₆₂ when the node N₁ is at low level. Most of this voltage is applied to the two ends of the tunnel capacitor TC₆₁ due to the relationship of the magnitudes of the capacitances. When the voltage of about 20 V is applied to the two ends of the tunnel capacitor TC₆₁ , an electric field stronger than 10 MV/cm is applied to the insulating film having a thickness of about 150 Å, so that a tunnel effect is caused. Electrons are extracted from the floating gate circuit, i.e., a node FG₆₁ , of the transistor Q₆₁ by the tunnel effect, and the node FG₆₁ is positively charged. Then, when the power source voltage V H1 is decreased to 0 V and the power source voltage V H2 is boosted to about 20 V, the transistor Q₆₂ is turned on if the node N₁ is set at high level (5 V) by the data of the volatile memory portion, and the electrode D₆₁ is substantially at a level (low level) of the power source voltage V SS . However, the node FG₆₁ is kept unchanged in level. However, if the node N₁ is set at low level by the data of the volatile memory portion, the transistor Q₆₂ is turned off, the electrode D₆₁ is in a floating state, and the levels of the electrode D₆₁ and the node FG₆₁ are boosted to about 20 V due to the relationship of capacitances of the capacitors. Since a voltage opposite in polarity to that in the case described above is applied to the two ends of the tunnel capacitor TC₆₁ , electrons are injected into the node FG₆₁ by the tunnel effect, so that the node FG₆₁ is negatively charged. That is, when the node N₁ is at high level, the node FG₆₁ is positively charged by the data transfer. When the node N₁ is at low level, the node FG₆₁ is negatively charged. The stored charges are held for a long period of time after the power source is cut off. The operation for transferring the data in the nonvolatile memory cell portion 16 to the volatile memory cell portion 1 will be described. When a power source voltage V CC of the flip-flop is boosted from 0 V to 5 V, the flip-flop is set according to the state of the node FG₆₁ as follows. If the node FG₆₁ is positively charged, the transistor Q₆₁ is turned on and the capacitor C₆₂ is connected to the node N₂. If the node FG₆₁ is negatively charged, the transistor Q₆₁ is turned off and the capacitor C₆₂ is disconnected from the node N₂. The capacitance of the capacitor C₆₂ is larger than that of the capacitor C₆₁. When the capacitor C₆₂ is connected to the node N₂ , the load capacitance of the node N₂ is large and the flip-flop is set so that the node N₁ is set at high level. When the capacitor C₆₂ is not connected to the node N₂ , the load capacitance of the node N₁ is large and the flip-flop is set so that the node N₂ is set at high level. That is, when the node FG₆₁ is positively charged, the node N₁ is set at high level, and when the node FG₆₁ is negatively charged, the node N₁ is set at low level. Figure 3 shows a modification of the above embodiment of the present invention. The memory cell has a volatile static memory cell portion 1 and a nonvolatile memory cell portion 17. the volatile static memory cell portion 1 is the same as the conventional static memory cell. The nonvolatile memory cell portion 17 has MIS transistors Q₆₁ and Q₆₄ , capacitors C₆₁ , C₆₂ , C₆₃ , and C₆₄ , and a tunnel capacitor TC₆₂ which is a floating gate element. A first high-voltage control power source V H1 is connected to the gate of the transistor Q₆₁ and one electrode of the tunnel capacitor TC₆₂ through the capacitor C₆₃. The other electrode of the tunnel capacitor TC₆₂ is connected to a second high-voltage control power source V H2 through the capacitor C₆₄ , and is connected to the power source V SS through the transistor Q₆₄. The gate of the transistor Q₆₄ is connected to node N₂. The node connected to the gate of the transistor Q₆₁ is referred to as a node FG₆₂. The operation of the above-mentioned memory cell will be described. Data in the volatile static memory cell portion 1 is transferred to the nonvolatile memory cell portion 17 in the following manner. The high-voltage control power source voltage V H2 is set at 0 V and the high-voltage control power source voltage V H1 is boosted from 0 V to about 20 V. Regardless of the high or low level of the potential of the node N₂ , electrons are injected into the node FG₆₂ by the tunnel effect and the node FG₆₂ is negatively charged. When the power source voltage V H1 is set at 0 V and the power source voltage V H2 is boosted from 0 V to about 20 V, if the node N₂ is at a high level, the voltage of about 20 V is applied only across the capacitor C₆₄. Therefore, the node FG₆₂ is held in a negatively charged state. If the node N₂ is at a low level, the voltage of about 20 V is applied to the tunnel capacitor TC₆₂. Therefore, electrons are extracted from the node FG₆₂ by the tunnel effect and the node FG₆₂ is positively charged. The operation for transferring the data in the nonvolatile memory cell portion 17 to the volatile memory cell portion 1 is the same as that of the memory cell in Fig. 2. The operations other than that in the above description are substantially the same as the operations of the memory cell in Fig. 2. Figure 4 shows another modification of the above embodiment of the present invention. Only a portion of the circuit corresponding to the nonvolatile memory cell portion in Fig. 2 is shown in Fig. 4. This circuit is obtained by inserting a transistor Q₆₃ between the transistor Q₆₁ and the node N₂ in place of the capacitor C₆₂ , and an array recall signal V RC is applied to the gate of the transistor Q₆₃. The transistor Q₆₃ is turned on for a short period of time only when the data in the nonvolatile memory cell portion is transferred to the volatile memory cell portion. That is, the array recall signal is applied to the gate of the transistor Q₆₃ for a short period of time when the power source V CC is turned on. When the data in the nonvolatile memory cell portion is transferred to the volatile memory cell portion in this manner, if positive charges are stored in the floating gate circuit of the transistor Q₆₁ and the transistor Q₆₁ is ON, the transistor Q₆₃ is turned on for a short period of time, thereby decreasing the voltage of the node N₂. By this operation, the data in the nonvolatile memory cell portion can be transferred to the volatile memory cell portion without using the recall capacitor C₆₂ , so that the area occupied in the semiconductor substrate by each memory cell can be decreased. In addition, when the recall transistor Q₆₃ is cut off, the drain voltage of the transistor T₆₁ is at low level (V SS ), and hot electrons may not be injected from the drain to the gate thereof. As a result, variations in the charge amount of the floating gate circuit are prevented, so that the data can be stably held for a long period of time. Figure 5 shows a circuit diagram of a memory cell of a semiconductor memory device according to a second embodiment of the present invention. The memory cell of this type has a volatile dynamic memory cell portion 11′ and a nonvolatile memory cell portion 20. The volatile dynamic memory cell portion 11' consists of a capacitance of a gate circuit of a MIS transistor Q₇₂ as a capacitor portion, and a MIS transistor Q₂₁. The gate of the transistor Q₂₁ is connected to a word line WL. A bit line BL is connected to the gate of the transistor Q₇₂ through the transistor Q₂₁. The transistor Q₇₂ serves both as a capacitor portion in a dynamic memory cell and as a switching transistor of the nonvolatile memory cell portion. It must be noted that a separate capacitor can be provided, as indicated in the figure by a dotted line. The nonvolatile memory cell portion 20 has a MIS transistor Q₇₂ , a MIS transistor Q₇₃ , a MIS transistor Q₇₄ as a recall transistor, a capacitor module CM₇₁ , and a tunnel capacitor TC₇₁ which is a floating gate circuit element. The capacitor module CM₇₁ has electrodes D₇₁ , D₇₂ , and D₇₃ , and has capacitances between the electrodes D₇₁ and D₇₂ , and between the electrodes D₇₁ and D₇₃. These capacitances are selected to be sufficiently larger than that of the tunnel capacitor TC₇₁. A power source V CC (normally at 5 V) is connected to a node N₂₁ as a connecting point between the transistors Q₂₁ and Q₇₂ through the transistors Q₇₃ and Q₇₄. The gate of the transistor Q₇₄ receives an array recall signal V RC . A first high-voltage control power source V H1 is connected to one electrode of the tunnel capacitor TC₇₁. A second high-voltage power source V H2 is connected to the electrode D₇₃ of the capacitor module CM₇₁. The electrode D₇₁ of the capacitor module CM₇₁ is connected to a power source V SS (normally at 0 V) through the transistor Q₇₂. A connecting point between the electrode D₇₁ and the transistor Q₇₂ is designated as a node N₇₂. The other electrode of the tunnel capacitor TC₇₁ is connected to the gate of the transistor Q₇₃ and to the electrode D₇₂ of the capacitor module CM₇₁ , and the connecting point thereof is designated as a node FG₇₁. The node FG₇₁ is a floating electrode surrounded by an insulator. The operation of the memory cell shown in Fig. 5 will be described. First, the power source voltage V H2 is held at 0 V and the power source voltage V H1 is boosted from 0 to about 20 V. The signal V RC is set at low level (about 0 V). The voltage of about 20 V is applied in series with the tunnel capacitor TC₇₁ , and the capacitances between the electrodes D₇₂ and D₇₁ and between the electrodes D₇₁ and D₇₃ when the node N₂₁ is at low level. Most of the voltage is applied to the two ends of the tunnel capacitor TC₇₁ due to the relationship of the magnitudes of the capacitances. Electrons are extracted from the gate of the transistor Q₇₃ , that is, from the node FG₇₁ , to the power source V H1 , and the node FG₇₁ is positively charged. Subsequently, when the power source voltage V H1 is set at 0 V and the power source voltage V H2 is boosted from 0 to about 20 V, if the node N₂₁ is set at high level (about 5 V) by the data written in the volatile memory cell portion, the node N₇₂ is at low level and is kept in the same state as that mentioned earlier. The node FG₇₁ is kept positively charged. If the node N₂₁ is at low level due to the data written in the volatile memory cell portion, the two capacitances of the capacitor module CM₇₁ and the tunnel capacitor TC₇₁ receive a voltage of about 20 V having an opposite polarity to the case mentioned earlier. As a result, most of the voltage is applied to the two electrodes of the tunnel capacitor TC₇₁ due to the relationship of the magnitudes of the capacitances. Electrons are injected to the side of the node FG₇₁ of the tunnel capacitor TC₇₁ by the tunnel effect so that the node FG₇₁ is negatively charged. As a result, in accordance with the data stored in the dynamic memory cell, that is, in accordance with whether the level of the node N₂₁ is at high or low level, the node FG₇₁ is positively or negatively charged. The charged electrons are held for a long period of time after the power source is cut off. The data stored in the nonvolatile memory cell portion 20 is transferred to the volatile dynamic memory cell portion 11' in the following manner. If the node FG₇₁ is positively charged, the transistor Q₇₃ is ON. When the array recall signal V RC is at high level, the transistor Q₇₄ is also turned on and a voltage from the power source V CC (5 V) is applied to the node N₂₁ , so that the capacitor of the dynamic memory cell is charged to high level. When the node FG₇₁ is negatively charged, the transistor Q₇₃ is OFF. In this case, if the signal V RC goes high, the voltage from the power source V CC is not applied to the node N₂₁ , and the capacitor of the dynamic memory cell is not charged. Figures 6 and 7 show modifications of the second embodiment, respectively. In Figs. 6 and 7 only portions in the vicinity of the node N₇₂ of the circuit shown in Fig. 5 are illustrated. In the circuit shown in Fig. 6, an enhancement-type transistor Q₇₅ is inserted between the node N₇₂ and the transistor Q₇₂ , and the voltage from the power source V CC or a control signal is applied to the gate of the transistor Q₇₅. In the circuit shown in Fig. 7, a depletion-type transistor Q₇₆ replaces the enhancement-type transistor Q₇₅ , and a voltage from the power source V SS is applied to the gate of the transistor Q₇₆. With this configuration, the voltage applied to the drain of the transistor Q₇₂ is limited by the transistor Q₇₅ or Q₇₆ so that the influence of the voltage acting on the side of the gate of the transistor Q₇₂ is minimized, thereby reducing adverse effects on the volatile dynamic memory cell. The memory cell according to the second embodiment requires a smaller number of constituent elements for the dynamic memory cell portion as compared with that according to the first embodiment, thereby further simplifying the circuit configuration and reducing the cell occupation area. Figure 8 is a circuit diagram of a memory cell of a semiconductor memory device according to a third embodiment of the present invention. The memory cell of this type has a volatile static memory cell portion 1 and a nonvolatile memory cell portion 21. The volatile static memory cell portion 1 is the same as a conventional static memory cell and a detailed description thereof is omitted. The nonvolatile memory cell portion 21 has a MIS transistor Q₈₄ , a MIS transistor Q₈₁ , a MIS PGM transistor Q₈₃ , a MIS transistor Q₈₂ to be used as a diode means, a tunnel capacitor TC₈₁ , and capacitors C₈₁ , C₈₂ , and C₈₃. The transistor Q₈₂ , the PGM transistor Q₈₃ , and the transistor Q₈₄ as a first switch means are included in a first write circuit. One cross-coupled connecting point, that is, a node N₁ of the flip-flop of the volatile static memory cell portion 1, is connected to a power source V SS (normally grounded) through the transistor Q₈₁ and the capacitor C₈₁. The other cross-coupled connecting point, that is, a node N₂ of the flip-flop, is connected to the power source V SS through the capacitor C₈₂. One electrode of the tunnel capacitor TC₈₁ is connected to the other electrode of the capacitor C₈₃ and to the gate of the transistor Q₈₁. A voltage is applied from a first high-voltage control power source V H1 to the gate and drain of the transistor Q₈₂. A second high-voltage control power source V H2 is applied to a second write circuit. The source of the transistor Q₈₂ is connected to the other electrode of the tunnel capacitor TC₈₁. The other electrode of the tunnel capacitor TC₈₁ is then connected to the drain of the transistor Q₈₃. The source of the transistor Q₈₃ is connected to the power source V SS through the transistor Q₈₄. The gate of the transistor Q₈₄ is connected to the node N₁ and the gate of the transistor Q₈₃ receives a program signal PGM. A voltage from the second high-voltage control power source V H2 is applied to one electrode of the capacitor C₈₃. A node connected to the gate of the transistor Q₈₁ will be referred to as a node FG₈₁. The capacitance of the capacitor C₈₃ is selected to be sufficiently larger than that of the tunnel capacitor TC₈₁ serving as the floating gate circuit element. The capacitor C₈₁ is selected to have a capacitance larger than that of the capacitor C₈₂. The operation of the memory cell mentioned above will be described. First, the operation for transferring data in the volatile static memory cell portion 1 to the nonvolatile memory cell portion 21 is as follows. The signal PGM is set at low level (substantially at 0 V), the power source voltage V H2 is set at low level, and the power source voltage V H1 is boosted from 0 V to about 20 V. Then, a voltage of about 20 V is applied to a series circuit of the tunnel capacitor TC₈₁ and the capacitor C₈₃ through the transistor Q₈₂. From the relationship of the magnitudes of the capacitances of the tunnel capacitor TC₈₁ and the capacitor C₈₃ , most of the voltage is applied to the tunnel capacitor TC₈₁. When a voltage of about 20 V is applied across two electrodes of the tunnel capacitor TC₈₁ , an electric field stronger than 10 MV/cm is applied to an insulating film of about 150 Å, thereby causing a tunnel effect. By the tunnel effect, electrons are extracted from the floating gate circuit of the transistor Q₈₁ , i.e., the node FG₈₁ , so that the node FG₈₁ is positively charged. When the power source voltage V H1 is at low level and the signal PGM is at high level (about 5 V), if the gate of the transistor Q₈₄ , i.e., the node N₁ , is at high level, the charges of about 20 V stored at the nodes of the source of the transistor Q₈₂ and the drain of the transistor Q₈₃ pass through the transistor Q₈₄ , so that the bulk side of the electrode of the tunnel capacitor TC₈₁ is at low level (0 V). When the node N₁ is at low level, the transistor Q₈₄ is turned off, so that the voltage of the electrode at the bulk side of the tunnel capacitor TC₈₁ is substantially held at 20 V. At this time, when the power source voltage V H2 is boosted from 0 V to about 20 V, if the node N₁ is at high level, a voltage of an opposite polarity to that in the case mentioned above is applied to the tunnel capacitor TC₈₁ , and the node FG₈₁ is negatively charged. If the node N₁ is at low level, the voltage at the bulk side of the tunnel capacitor TC₈₁ is also at about 20 V, and the node FG₈₁ is kept positively charged. That is, if the node N₁ is at high level, the node FG₈₁ is negatively charged, and if the node N₁ is at low level, the node FG₈₁ is positively charged. The charges charged in this manner are held for a long period of time after the power source is cut off. The data stored in the nonvolatile memory cell portion 21 is transferred to the volatile static memory cell portion 1 in the following manner. When the power source voltage V CC is boosted from 0 V to 5 V, the flip-flop is set in accordance with the state of the node FG₈₁ in the following manner. That is, if the node FG₈₁ is positively charged, the transistor Q₈₁ is turned on and the capacitor C₈₁ is connected to the node N₁. If the node FG₈₁ is negatively charged, the transistor Q₈₁ is turned off to cut off the capacitor C₈₁ from the node N₁. Since the capacitance of the capacitor C₈₁ is larger than that of the capacitor C₈₂ , the node N₁ has a large amount of load capacitance when the capacitor C₈₁ is connected to the node N₁. Therefore, the flip-flop is set so that the node N₁ is at low level. When the capacitor C₈₁ is not connected to the node N₁ , the node N₂ has a large amount of load capacitance, so that the flip-flop is set so that the node N₁ is at high level. When the node FG₈₁ is positively charged, the node N₁ is set at low level, and when the node FG₈₁ is negatively charged, the node N₁ is set at high level. Figure 9 shows a modification of the third embodiment. In the circuit shown in Fig. 9 a transistor Q₈₅ is inserted between the transistor Q₈₁ and the node N₁ in place of the capacitor C₈₁ , and an array recall signal V RC is applied to the gate of the transistor Q₈₅. The transistor Q₈₅ is turned on for a short period of time when the data in the nonvolatile memory cell portion is transferred to the volatile memory cell portion. That is, the array recall signal is applied for a short period of time when the power source V CC is turned on. In this manner, when the data in the nonvolatile memory cell portion is transferred to the volatile memory cell portion, if the gate circuit of the transistor Q₈₁ is positively charged and the transistor Q₈₁ is turned on, the transistor Q₈₅ is turned on for a short period of time, thereby decreasing the voltage at the node N₁. By this operation, the recall capacitor C₈₁ can be omitted. As a result, the area occupied in the semiconductor substrate by each memory cell can be decreased. Furthermore, since the drain voltage of the transistor Q₈₁ is at low level when the transistor Q₈₅ is cut off, hot electrons will not be injected from the drain to the gate thereof, so that variations in the charge amount of the floating gate circuit are prevented, thereby stably performing data holding for a long period of time. Figure 10 is a circuit diagram of a memory cell of a semiconductor memory device according to a fourth embodiment of the present invention. The memory cell of this type has a volatile dynamic memory cell portion 11 and a nonvolatile memory cell portion 22. The volatile dynamic memory cell portion 11 has a MIS transfer transistor Q₂₁ , the gate of which is connected to a word line as a transfer gate, and another MIS transistor Q C serving as a capacitor portion of the dynamic memory. A bit line BL is connected to the gate of the transistor Q C through the transistor Q₂₁. The nonvolatile memory cell portion 22 has a MIS transistor Q₉₃ , an array recall MIS transistor Q₉₄ , a MIS transistor Q₉₅ as a diode means, a MIS transistor Q₉₆ , a capacitor C₉₁ , and a tunnel capacitor TC₉₁ as a floating gate element. The capacitance of the capacitor C₉₁ is selected to be sufficiently larger than that of the tunnel capacitor TC₉₁. A power source V CC (normally at 5 V) is connected to a node N₂₁ which is a connecting point between the transistors Q₂₁ and Q C through the transistors Q₉₃ and Q₉₄. An array recall signal V RC is supplied to the gate of the transistor Q₉₄. A voltage from a first high-voltage control power source V H1 is applied to the gate and drain of the transistor Q₉₅. The source of the transistor Q₉₅ is connected to one electrode of the capacitor C₉₁. One electrode of the capacitor C₉₁ is also connected to a power source V SS (normally at 0 V) through the transistors Q₉₆ and Q C . A program signal PGM is supplied to the gate of the PGM transistor Q₉₆. One electrode of the tunnel capacitor TC₉₁ is connected to the other electrode of the capacitor C₉₁ and to the gate of the transistor Q₉₃. A voltage from a second high-voltage control power source V H2 is applied to the other electrode of the tunnel capacitor TC₉₁. The operation of the memory cell shown in Fig. 10 will be described. The volatile dynamic memory cell portion 22 stores one-bit data in accordance with whether the node N₂₁ is charged to high level or held at low level without charging in response to signals from the word line and the bit line. First, the operation for transferring the data stored in the manner described above to the nonvolatile memory cell portion 22 will be described. The voltages of the signal PGM and the power source V H2 are set at low level (substantially at 0 V) and the voltage of the power source V H1 is boosted from 0 V to about 20 V. By this operation, the transistor Q₉₅ is turned on and the transistor Q₉₆ is turned off. Accordingly, a voltage of about 20 V is applied to a series circuit of the capacitor C₉₁ and the tunnel capacitor TC₉₁. From the relationship of the magnitudes of the capacitances of the two capacitors, most of the voltage of about 20 V is applied across the two electrodes of the tunnel capacitor TC₉₁. As a result, electrons are injected by a tunnel effect to a node FG₉₁ connected to the gate of the transistor Q₉₃ , and the node FG₉₁ is negatively charged. When the power source V H1 is then decreased to 0 V, the transistor Q₉₅ is turned off and the node of the source of the transistor Q₉₅ and the drain of the transistor Q₉₆ is kept charged at about 20 V. Then, when the signal PGM is set at high level, if the node N₂₁ is at high level, the electrons mentioned above are extracted, so that one electrode of the capacitor C₉₁ is at low level. If the node N₂₁ is at low level, since the transistor Q C is turned off, the charging state of the electrons is maintained. In this state, when the voltage of the power source V H2 is simultaneously boosted from 0 V to about 20 V, if the node N₂₁ is at high level, the voltage of one electrode (at the bulk side) of the capacitor C₉₁ is at 0 V, so that the voltage of the power source V H2 is applied to a series circuit of the tunnel capacitor TC₉₁ and the capacitor C₉₁. Since the capacitance of the capacitor C₉₁ is sufficiently larger than that of the tunnel capacitor TC₉₁ , most of the voltage is applied to the tunnel capacitor TC₉₁ so that a tunnel effect in the opposite direction to that mentioned earlier is caused. Electrons of the node FG₉₁ are extracted, and the node FG₉₁ is positively charged. If the node N₂₁ is at low level, since one electrode of the capacitor C₉₁ is kept at about 20 V, the node FG₉₁ is kept negatively charged. That is, when the node N₂₁ is at high level, the node FG₉₁ is positively charged, and when the node N₉₁ is at low level, the node FG₉₁ is negatively charged. The charges thus charged are held for a long period of time after the power source is cut off. The data stored in the nonvolatile memory cell portion 22 is transferred to the volatile dynamic memory cell portion 11 in the following manner. When the node FG₉₁ is positively charged, the transistor Q₉₃ is also turned on. When the array recall signal V RC is at high level, the transistor Q₉₄ also is turned on, so that the power source voltage V CC is applied to the node N₂₁ to charge the capacitor of the dynamic memory cell, thereby setting the node N₂₁ at high level. When the node FG₉₁ is negatively charged, the transistor Q₉₃ is turned off, and the power source voltage V CC is not applied to the node N₂₁ even after the signal V RC is at high level. The capacitor of the dynamic memory cell is not charged, and the node N₂₁ is kept at low level. In the fourth embodiment, the transistor Q C is commonly used as the switching transistor and as the capacitor portion (utilizing the capacitance of the gate) of the dynamic memory cell. However, the transistor Q C can be used only as a switching means and a separate capacitor can be added as indicated by a dotted line in Fig. 25. The memory cell of the fourth embodiment requires a smaller number of constituent elements for the volatile memory cell portion compared with that of the third embodiment, thereby further simplifying the circuit configuration and decreasing the cell occupation area. Figure 11 shows a memory cell of a semiconductor memory device according to a fifth embodiment of the present invention. The memory cell comprises a volatile dynamic memory cell portion 11' and a nonvolatile memory cell portion 23. The volatile dynamic memory cell portion 11' consists of a MIS transistor Q₂₁ and a gate capacitance of a MIS transistor Q C as a capacitor portion. It is to be noted that a single capacitor also can be used, as indicated by a dotted line. The transfer gate transistor Q₂₁ is connected between a bit line BL and the gate of the transistor Q C . The gate of the transistor Q₂₁ is connected to a word line WL. The source of the transistor Q C is connected to a power source V SS (normally 0 V) which is a common terminal side of the power source. The transistor Q C has both functions of the capacitor portion of the volatile dynamic memory cell portion 11' and a transistor of the nonvolatile memory cell portion 23, which is turned on or off in response to the memorized data in the capacitor portion. The connecting point of the transistor Q₂₁ and the gate of the transistor Q C is represented as a node N₂₁. The nonvolatile memory cell portion 23 has, in addition to the transistor Q C , a recall transistor Q A , a transistor Q E serving as a diode means, a PGM transistor Q P , and an EEPROM (EEPROM cell) (T M ) as a nonvolatile memory cell transistor having a double gate structure. Each transistor is a MIS transistor. A second write power source V H /AR which is capable of two-stage voltage switching is connected to the drain of the EEPROM. The source of the EEPROM is connected to the drain of the transistor Q A . The source of the transistor Q A is connected to the node N₂₁. An array recall signal V RC is supplied to the gate of the transistor Q A . The first write power source V H1 is connected to the drain and the gate of the transistor Q E . The source of the transistor Q E is connected to the control gate CG of the EEPROM and the drain of the transistor Q P , respectively. The gate of the transistor Q p receives a program signal PGM, and the source thereof is connected to the drain of the transistor Q p . The operation of the memory cell described above will now be described. When the data is transferred from the volatile dynamic memory cell portion 11' to the data nonvolatile memory cell portion 23, the signals PGM and V RC , and the power source voltage V H /AR are set at 0 V, and a power source voltage V H1 is boosted from 0 V to about 20 V. The transistor Q E is turned on and the transistor Q P is cut off so that the control gate CG of the EEPROM is boosted to about 20 V. The EEPROM has the configuration shown in Fig. 12 and an equivalent circuit thereof is shown in Fig. 13. Therefore, when a voltage of about 20 V is applied between the control gate CG and a drain D, most of the voltage is applied between the floating gate FG and the drain D by capacitive coupling, since a capacitance between the control gate CG and a floating gate FG is sufficiently greater than the capacitance serving as a tunnel capacitor TCa between the floating gate FG and the drain D. This state serves as an erase state for the EEPROM. Electrons are injected in the floating gate FG to give it a negative charge. Thereafter, when the power source voltage V H1 is decreased to 0 V, the transistor Q E is turned off and the charges of the control gate CG of the EEPROM are not discharged, so that the voltage of the control gate CG is held at about 20 V. When the signal PGM is set at high level under this state, the charges of the control gate CG described above flow to the power source V SS if the gate voltage of the transistor Q C is at high level, so that the voltage is decreased to 0 V. If the gate voltage of the transistor Q C is at low level, since the transistor Q C is OFF, the charges of the control gate CG do not change and the voltage is not decreased. In this state, when the power source voltage V H /AR is boosted from 0 V to about 20 V and when the gate of the transistor Q C is at low level, the voltage of the drain D of the EEPROM is kept at about 20 V, the voltage of the control gate CG is kept at about 20 V, and the EEPROM is kept erased. When the gate of the transistor Q C is at high level, the voltage of the drain of the EEPROM becomes about 20 V, the voltage of the control gate CG becomes 0 V, and the floating gate FG is positively charged, so that a write operation of the EEPROM is performed. As has been described above, the floating gate FG of the EEPROM is positively or negatively charged in accordance with the level of the node N₂₁ of the volatile dynamic memory cell portion 11', thereby holding the content of the dynamic memory cell. When the content stored in the nonvolatile memory cell portion 23 is transferred to the volatile dynamic memory cell portion 11', i.e., in the case of an array recall, the following operation is performed. Namely, the power source voltage V H1 and the signal PGM are set at low level (0 V), the signal V RC is set at high level (5 V), the power source voltage V H /AR is set at voltage V CC (5 V), and the word line is set at low level. When the floating gate FG of the EEPROM is positively charged, a voltage of 5 V from the power source V H /AR is supplied to the node N₂₁ through the drain and source of the EEPROM and the transistor Q A so as to charge the memory capacitor (gate of transistor Q c ), thereby setting the memory capacitor at high level. When the floating gate FG of the EEPROM is negatively charged, the conduction state between the drain D and the source S of the EEPROM is not established, so that the capacitor consisting of the transistor Q C of the volatile memory cell portion 11′ is not charged from the power source V H /AR. In this manner, the data transferred to and stored in the nonvolatile memory cell portion 23 can be reproduced at the volatile dynamic cell portion 11'. The EEPROM used in the nonvolatile memory cell portion 23 will be further described. As shown in Fig. 12, two n⁺-type regions are formed on a silicon substrate (SiSub) to be used as the drain D and a source S, respectively. Furthermore, the floating gate FG is formed between the control gate CG and the silicon substrate in addition to the control gate CG as the gate. A portion of the floating gate FG above the drain is insulated by a thin silicon oxide (SiO₂) film so as to enable a tunnel effect of electrons therebetween. Therefore, the equivalent circuit of the EEPROM is as shown in Fig. 13. In the circuit according to this embodiment of the present invention, the gate capacitance of the transistor Q C is utilized as the capacitor portion of the volatile dynamic memory cell portion 11' and no additional capacitor is used. However, a special capacitor as indicated by the dotted line in Fig. 11 can be provided, enabling decreasing the device size by an area corresponding to the transistor Q C . Although the transistor Q E is used as the diode element, another circuit having a function serving as the diode can be used instead. According to the present embodiment, high integration of the nonvolatile memory device is allowed by decreasing the number of circuit elements, and the number of floating gate circuit elements to be used, such as tunnel capacitors, can be decreased to one, thereby improving the manufacturing yield. A semiconductor memory device in accordance with the present invention includes a nonvolatile random access memory cell constituted by a combination of a static random access memory cell or a dynamic random access memory cell and a floating circuit element. In the device, the circuit constitution and the like are improved. Thus, the number of circuit elements, particularly the number of floating gate circuit elements, is reduced. As a result, the cell area can be decreased, high integration of the device can be achieved, and the production yield of the device can be increased. In addition, improvement of the circuit configuration increases the discretion allowed in the layout design, and repeated application of the write voltages improves the storage efficiency.

Claims: A semiconductor memory device comprising a volatile memory cell (1, 11, 11') and a nonvolatile memory cell (16, 17, 20, 21, 22, 23) corresponding to the volatile memory cell, said nonvolatile memory cell comprising a transistor (Q₆₁, Q₇₃, Q₈₁, Q₉₃, T M ) which has a floating gate and is operable to turn on or off in response to memorised data, a tunnel capacitor (TC₆₁, TC₆₂, TC₇₁, TC₈₁, TC₉₁, TCa), one electrode of which is connected to the floating gate, and write circuitry coupled to the tunnel capacitor, for supplying a high voltage (V H1 , V H2 ; V H1 , V H ) as a write voltage to said tunnel capacitor in response to the memorised data of said volatile memory cell; characterised in that: said write circuitry includes first and second high voltage sources (V H1 , V H2 ; V H1 , V H ) which are capacitively coupled to the floating gate, one of them being coupled to the floating gate across the tunnel capacitor (TC₆₁, TC₆₂, TC₇₁, TC₈₁, TC₉₁, TCa); said high voltage sources (V H1 , VH₂; V H1 , V H ) are arranged such that during a write operation, the first high voltage source applies a high voltage first and the second high voltage source applies a high voltage subsequently at a time when the first high voltage is not being applied; and in that said nonvolatile memory cell further comprises means (Q₆₂, Q₆₄, Q₇₂, Q₈₄, Q c ) which capacitively couple or do not couple the floating gate to a low voltage source (V ss ) depending on the memorised data of the corresponding volatile memory cell (1, 11, 11′), such that charges are injected via the tunnel capacitor (TC₆₁, TC₆₂, TC₇₁, TC₈₁, TC₉₁, TCa) to the floating gate when applying the first high voltage and charges are removed or not removed from the floating gate via the tunnel capacitor depending on the state of the corresponding volatile cell when the second high voltage is subsequently applied during the write operation. A semiconductor memory device as set forth in claim 1, wherein said write circuitry comprises a first write circuit connected to the other electrode of said tunnel capacitor (TC₆₁, TC₆₂, TC₇₁, TC₈₁, TC₉₁, TCa), and a second write circuit capacitively coupled to said one electrode of said tunnel capacitor. A semiconductor memory device as set forth in claim 2, wherein said volatile memory cell (1) comprises two transistors (Q₁, Q₂) cross-connected to each other, the voltages of the gates of the two transistors being supplied to said nonvolatile memory cell (21) as an output of said volatile memory cell (1); said first write circuit comprises a diode means (Q₈₂) for receiving the voltage from said first high-voltage source (V H1 ) and for supplying the same to the other electrode of said tunnel capacitor (TC₈₁), a first switch means (Q₈₄) and a PGM transistor (Q₈₃), said first switch means (Q₈₄) controlling the voltage of the other electrode of said tunnel capacitor (TC₈₁) through said PGM transistor (Q₈₃) in response to memorised data of said volatile memory cell (1); and said second high-voltage source (V H2 ) is applied to said second write circuit (C₈₃). A semiconductor memory device as set forth in claim 2, wherein said volatile memory cell (11) comprises a capacitor portion for storing an amount of electric charge corresponding to data to be memorised, a transfer transistor (Q₂₁) for transferring data of said capacitor portion to a bit line, and another transistor (Q c ), the gate of which is connected to said capacitor portion and which turns on or off in response to memorised data of said capacitor portion; said second high-voltage source (V H2 ) being supplied to said first write circuit as a write voltage; said second write circuit comprises a transistor (Q₉₅) for receiving the voltage from said first high-voltage source (V H1 ), and a PGM transistor (Q₉₆) for relaying and controlling a voltage corresponding to the memorised data of said volatile memory cell (11); and the voltage from said first high-voltage source (V H1 ) or the voltage corresponding to the memorised data of said volatile memory cell (11) is supplied to said second write circuit as a write voltage. A semiconductor memory device as set forth in claim 4, wherein the gate capacitance of said transistor (Q c ) which turns on or off in response to the memorised data of said capacitor portion is used as said capacitor portion. A semiconductor memory device as set forth in any one of claims 2 to 5, wherein a write voltage (V H1 ) is applied to said first write circuit a plurality of times, and a write voltage (V H2 , V H ) is applied to said second write circuit a plurality of times. A semiconductor memory device as set forth in claim 1, wherein in said nonvolatile memory cell (20), one electrode of said tunnel capacitor (TC₇₁) is connected to a high-voltage source terminal (V H1 ), a first capacitor (CM₇₁) is provided, one electrode of which is connected to the other electrode of said tunnel capacitor (TC₇₁), a second capacitor (CM₇₁) is provided, connected between the other electrode of said first capacitor (CM₇₁) and a high-voltage source terminal (V H2 ), and said transistor has a tunnel gate electrode, its gate being connected to a common node between said tunnel capacitor (TC₇₁) and said first capacitor, and a switch means (Q₇₂) is provided for controlling the potential at a common node between said first capacitor and said second capacitor in response to the data stored in said volatile memory cell (11'). A semiconductor memory device as set forth in claim 1, wherein said volatile memory cell (11) comprises a capacitor portion for storing charges in response to data to be memorised, and a transfer gate transistor (Q₂₁) connected between said capacitor and a bit line (BL) and said nonvolatile memory cell transistor (T M ) has a double gate structure constituting said tunnel capacitor (TC a ) and having a control gate (CG) and a floating gate (FG), a recall transistor (Q A ) for transferring data stored in said nonvolatile memory cell transistor (T M ) to said capacitor portion in response to a recall signal (V RC ), a transistor (Q c ) turned on or off in response to the data stored in said capacitor portion, a PGM transistor (Qp) connected between said transistor (Q c ) and turned on or off in response to the stored data and said control gate (CG), and a diode element (Q E ) connected to said control gate (CG); whereby a first write voltage (V H1 ) can be applied to said control gate (CG) through said diode element (Q E ) and a second write voltage (V H ) can be applied to the drain of said nonvolatile memory cell transistor (T M ), and said PGM transistor (Qp) may be set in a conductive state, whereby data stored in said volatile memory cell (11) is written to said nonvolatile memory cell (23).

Inventors: ARAKAWA HIDEKI C O FUJITSU LIM, ARAKAWA, HIDEKI, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1984
Main classification: G11C14
IPC codes: G11C14