FAULT ALIGNMENT CONTROL SYSTEM AND CIRCUITS

Abstract: This permutation circuit can be considered to be a multi­ bit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates (12) with m+y permutation bits to generate m+y input bits accessing a decoder (10) with 2 m output positions. In another embodiment the decoder takes the form of an m-bit adder (14) which adds m address bits to m permutation bits to generate an m-bit actual address. Multiple decoders of both types may be joined together in various combinations to generate higher order addresses. Also, k full-adders of less than m bits can be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2 y rows.

Description: Background of the Invention The present invention relates to permutation logic for changing words with uncorrectable errors (UE's) into memory words that can be corrected by the error correcting code protecting the data in the memory. In EP-A-90219 entitled "Deterministic Permutation Algorithm", a memory address register accesses a memory word by supplying the same logical address to decoders for all bit positions of the word. However, as a result of modification by logic circuitry the address actually applied to the decoder of any particular bit position can differ from the logical address supplied by the address register. The logic circuitry is called permutation logic. Because of the permutation logic, a memory word can contain storage cells located at a number of different physical addresses that are not the logical address supplied by the memory register. The permutation logic of the said EP-A-90219 performs a single Exclusive OR function on each of the n inputs to the decoder of the particular bit position. Each of the n digits of the word address is Exclusive ORed with a different bit to permute the address. If the bit decoder is a two bit decoder, the mentioned permutation logic can provide to the decoder 2 n or four different combinations or sequences of bit inputs. These are shown in Table 1. These four sequences form only a small subset of the possible decoder input sequences. There are actually 2 n ! or 24 possible input sequences for a two bit decoder (where n=2). The decimal equivalents of all possible sequences are shown in Table 2, wherein the columns 1, 12, 17, 22 marked with an asterisk correspond to those of Table 1. It turns out that certain UE conditions cannot be satisfactorily resolved using any of the 2 n input sequences in Table 1 where these same UE conditions could readily be alleviated if one of the other theoretically possible 2 n ! input sequences shown in Table 2 were achievable. EP-A-905028 (state of the art under Article 54(3)(4) EPC) entitled "Fault Alignment Control System and Circuits" discloses logic capable of providing more than the 2 n input combinations listed in Table 1. However, the disclosed permutation devices are not "linear". Unlike the permutation devices in the referenced EP-A-90219, the value of permutation bits needed to access a known actual address with a given logical address cannot be calculated. Instead a table look-up scheme has to be employed to obtain the permutation bits that are necessary to transpose a logical address into an actual address. Furthermore, when expanded beyond two address bits the translation of one address in one group of four addresses will be reflected in all other groups of four addresses. EP-A-105402 entitled "Memory Address Permutation Apparatus" discloses a single permutation apparatus which transposes a single logical address into a different actual address for any number of the bit positions of an accessed memory and this selection scheme allows translation of word lines without affecting data in other pairs of word lines but the actual addresses are selected sequentially and the selection scheme is not linear. The Invention In accordance with the present invention as set out in the appended claims, a new permutation circuit is employed. This permutation circuit can be considered a full group adder without a carry where the group can be considered to be m bits. In one embodiment it takes the form of m address bits being fed to (m + y), 2-way exclusive OR gates with m + y permutation bits to generate 2 m + y translations of 2 m output positions. In another embodiment the permutation circuit takes the form of an m bit adder or n + k bit full adder where n + k > m while n < m which adds m address bits to m permutation bits to generate an m bit actual address or n + k permutation bits to generate 2 n+k translations on 2 m addresses. Multiple decoders of both types may be joined together in different combinations to generate higher order addresses. Therefore it is an object of the present invention to provide a new permutation apparatus for swapping bits in memory words to change uncorrectable errors into correctable error conditions. It is another object of the present invention to swap bits to provide more combinations of permutations of address bits to the input decoder. It is another object of the present invention to provide permutation apparatus capable of swapping bits in blocks independent of other blocks. The Drawings These and other objects of the present invention can be best understood by referring to the figures of the drawings of which: Fig. 1 to 7, 9, 10 and 11 are circuit diagrams of permutation logic in accordance with the present invention, and Fig. 8 is a graphic representation of a permutation bits determination algorithm that can be employed with the embodiments of the invention shown in Figs. 1 to 7. Detailed Description As shown in Figs. 1 and 2 the use of two address bits A0 and A1 and three permutation bits P00, P01 and P1 (or P0, P10 and P11) allows 2³ way address translation on 4 input addresses. The three translated inputs At00, At01, At1 (or At0, At10, At11) when applied to decoder 10 select one input out of 4. Since the translation (permutation) controls P00, P01 in Fig. 1 and P10, P11 in Fig. 2 are independent, they can be used independently in each block of two addresses, whereby these schemes double the number of address translations obtainable by address bits A0 and A1. To generate three input bits for the decoder 10 from two address bits, an address bit A0 or A1 is exclusive-ORed with each of three permutation bits in a 2-way exclusive OR circuit 12. This means that one of the address bits gets exclusive-ORed with more than one permutation bit in each of the embodiments to generate the third input bit to the decoder 10. As can be seen by the tables in the figures, the permutations are extended by these circuits which can provide more than 2 n or four ways of translation of two address bits. The circuits of Fig. 1 and 2 each extend to allow eight ways of address translation of a 2² row space. These two address translation functions are represented by two subsets of columns (1,5,9,12,13,17,20 and 22) and (1,6,7,12,14,17,21 and 22) in Table 2 respectively. These circuit realizations can divide the address space of four rows into two blocks of two rows as divided by the dotted lines in the tables and the schematic. The address translation within any one block can be accomplished independently of the other, by judicious selection of the permutation inputs. For instance, in Fig. 3, control bit P11 allows to swap data on lines 10 and 11 without affecting data on the 00 and 01 word lines. This independence is obtained at the cost of an extra Exor gate, inverter and address translation control bit, but without any additional time delay. The circuit of Figure 3 shows an implementation of the decoder specifications given in Figure 2. To provide a better understanding of the flexibility afforded by these circuits in selecting the address translation control bits, the number of blocks, and the size of blocks in a memory of a given size, the possible variations of address translation functions and their circuit implementations for an address space of 2³ rows are discussed. Fig. 4 shows a 2-block address translation function. The eight row address space is divided into two blocks of four rows. The circuit implementation requires five Exor gates 12 with five address translation control bits P, thereby providing 32 ways of translation of the 8-row address space. It is also possible to construct a circuit such as shown in Fig. 5, capable of providing 64 ways of address translation for the same address space of 8 rows. The decoder 10 here would be two of the decoders of Fig. 3 to accommodate twice the input and provide twice the outputs. This arrangement divides the address space into 4 blocks of two rows each. As in the case of Figs. 1 and 2 address translation within any block is possible without affecting the others, if so desired. Fig. 6 illustrates one of many possible generalizations of the linear circuits to translate using 3 to 8 decoders. Here, the address space of 8 rows can be translated in either 8, 16, 32, 64 or 128 ways. This is accomplished by first subdividing the address space into two blocks. This is followed by subdividing the address space within each such block into two subblocks of two rows each. This circuit implementation requires 7 Exor gates 12 and 7 address translation control bits which are partly grouped together into two permutation modules 11, as shown. If the address translation bits P21 and P22 assume identical values, then the circuit of Fig. 6 behaves like a circuit of Fig. 5. If address translation bits, P21, P22 always assume identical values and P31, P32, P33 and P34 also assume identical values then it results in a circuit behavior as if the circuit has 3 Exor gates and 3 address translation control bits only. The circuit of Fig. 7 comprises a plurality of permutation modules 13 as shown. It divides the address space of 32 chip rows accessed by 5 address bits into 4 blocks of 8 chip rows, thereby confining the logical movement of faults within a specified block of 8 chip rows, if so desired. Since there are 14 address translation control bits the address space of 32 chip rows in a card can be reconfigured in (2 14 =16384) ways. Having all this power of translation, if a highly efficient, and convergent algorithm which can be systematically used in determining the most appropriate value of translation control cannot be devised then such powerful translation circuits are of no use. Fortunately, algorithms such as described in EP-A-95669 entitled "A Method of Memory Reconfiguration for Fault Tolerant Memory" can be efficiently used for any circuit in the class defined as linear. Consider a circuit of Fig. 6, where the address space of 8 rows is divided into 2 blocks of 4 rows, where each block in turn is again sub-divided into 2 sub-blocks. The first step for determining the values of address control bits is to conceptually imaging this circuit of one block with 8 address rows. This is possible by assuming as if P21 and P22 are tied together and P31, P32, P33, P34 are also tied together. Conceptually it implies that at one block level P21 and P22 always assume identical values and P31, P32, P33 and P34 also assume identical values. Let us suppose that the algorithm described in EP-A-95669 finds "101" as the most suitable 3 bit value for address translation control for a section of a memory. In terms of circuit description of Fig. 6 it implies that P1 is found to be equal to "1", P21, P22 are found to be "0,0" and P31, P32, P33 and P34 are found to be "1,1,1,1" respectively. This step can be considered as a step to achieve global reconfiguration of the memory leaving minimum possible fault alignments. Let us suppose that after step 1 two fault alignments are left in block 2, while no faults are left aligned in block 1. In such a situation, the algorithm is once again executed for the memory block 2 only to find the most suitable values of translation control bits P22, P33, P34, equal to 0,1,1 respectively. Suppose this step also leaves one fault alignment in the sub-block 2 of block 2. Therefore, the algorithm is again executed on the 2-row memory sub-block 2 of block 2 to find the value of P34 to be "1" to remove all the alignments. The final values of 7 bit translation controls result by Exoring on bit by bit basis as shown in step 3 of Fig. 8. The exclusive OR circuit can be considered as a half-adder. In a further generalization for obtaining greater flexibility in address translation, an n input full adder 14 can be used for permutation as shown in Fig. 9. The adder receives the address bits A0 to An-1 with the permutation bits P0 to Pn-1 and the resultant sum can be used as decoder access bits. The carry is ignored so that the adder would perform a shift rotate function. The adder could be used as above or used to permute the inputs A0 to An-1 of a permutation device as described in connection with Figs. 1 to 8 to increase the possible permutations. An example is shown in Fig. 10. Adders 14 can also be used in sets to access a decoder as shown in Fig. 11. Many small full adders of less than n bits can thus be used to provide address translation by performing shift rotate translation within the desired block only. This extension will also provide 2 n+k address translations on 2 n address rows where k ≧ 0. Thus allowing an address translation capability similar to (n+k) Exor circuits described in Figs. 1 to 7.

Claims: In a memory system made up of logical data words with all bit positions thereof accessed by the same logical address bits through separate permuting means for each bit position which convert the logical address to actual address bits of a data bit on the basis of separate permutation bits that are selected to distribute faulty data bits among the logical data words and thereby eliminate error conditions in the logical data words that are uncorrectable by the error correcting code protecting the memory system, a permuted decoder means characterized by: decoder means (10) for decoding n address bits controlled by n + m permutation bits into 2 n locations, permutation bit means for supplying n + m permutation bits; and permutation means (12) for receiving n address bits and n + m permutation bits and for providing n + m permuted actual address bits to said decoder means, whereby m > 0. The memory system of claim 1 wherein said permutation means includes n + m Exclusive OR means (12) each responsive to one of the n address bits and a different one of the n + m permutation bits for n + m actual address bits so that at least one of the n address bits is fed to more than one of the Exclusive OR means. The memory system of claim 1 or 2 including full-adder means (14) without a carry adding a set of n address bits with n permutation bits to generate the first mentioned n address bits. The memory of a preceding claim wherein said permutation means includes a plurality of permutation modules (11, 13) at least one of said modules comprising permutation element means for receiving a address bits and a + b permutation bits to provide a + b permuted actual address bits to the decoder means, wherein a < n and b ≧ 0. The memory system of a preceding claim comprising: a plurality m of k-bit full-adders (14) each receiving k address bits and k different permutation bits to generate a k-bit partial sum with no carry, and a decoder (10) for receiving the m x k outputs of said full-adders and Exor (half-adders) outputs and decoding the bits to select one of 2 n outputs.

Inventors: SINGH, SHANKER, SINGH, VINJENDRA P.
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1984
Main classification: G06F11
IPC codes: G06F12, G06F11