SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device has memory cells with MIS transistors (Tr₁ to Tr₄) formed in zones defined by field insulation (FL), each with source (S) and drain (D) regions and a channel region the maximum possible width (Wf) of which is defined by the field insulation (FL). Some of the transistors (e.g. Tr₂, Tr₃, Tr₄) have doped regions (P₁, P₂, P₃), doped with impurity opposite to the conductivity type of the source and drain regions giving them effective channel widths (W₂ for Tr₂; W₃ for Tr₃) less than the maximum possible. This lesser width may be zero (Tr₄). Multi-level information (e.g. base 3 or base 4) can be stored by setting different channel widths corresponding to its different levels. «Half-fabricated» devices, taken to a production stage immediately prior to formation of the doped regions (P₁, P₂, P₃) can be stocked by a manufacturer so that, in response to a customer's order, he need only write in selected information by implanting the doped regions.

Description: SEMICONDUCTOR MEMORY DEVICE This invention relates to a semiconductor memory device, and is more particularly concerned with a multi-level memory device. A mask read-only memory (ROM) is a device that is used for storing fixed information. The information is stored in a memory cell matrix. The basic storage elements of a mask ROM are metal insulator semiconductor (MIS) transistors, metal oxide semiconductor (MOS) transistors being generally used. Current carried by each matrix cell element (transistor) represents stored information. The stored information is written into the ROM during manufacture. Usually, a substrate carrying a matrix arrangement of transistors is prepared, and then each of the transistors is wired according to the information to be stored. This wiring stage is usually executed relatively late in the total ROM fabrication process. This enables manufacturers to stock "half-fabricated" mask ROMs, awaiting the information writing process. Thus, when mask ROMs required to hold new or different information are ordered by a customer, a writing mask corresponding to the new or different information is prepared and "half-fabricated" ROMs from stock are completed by executing the writing process. From the point of view of the customer this provides a reduced fabrication time, and delivery time is shortened. There is a strong demand for a capability to increase the amount of information stored per unit area of a chip. This is leading to the development of multi-level logic circuits which, instead of binary arithmetic, use base 3 or base 4 arithmetic, for example. In a multi-level memory device, cell transistor current has to be capable of taking a number of different values corresponding to the different possible values of the information digits. Cell transistor current can be altered by altering the channel width of the cell transistors. Information concerning multi-level semiconductor memories is given in, for instance, Feb.24/1981 Electronics, page 100, by J.G. Posa and Jun.30/1982 Electronics, page 81, by J.R. Lineback. For example, fabrication of a multi-level mask ROM starts with the formation of a field oxide layer (usually, silicon dioxide layer) on a substrate. After the field oxide layer is grown, metal insulator semiconductor (MIS) transistors and other circuit elements are created in open areas in the field oxide layer. The widths of the channels of the MIS transistors are determined at this stage. For fabricating a new ROM, for storing predetermined information in a multi-level memory device, MIS transistors having various current levels (when the ROM is in use) are formed in a memory matrix of the ROM in accordance with the values or levels of multi-level information digits to be stored. Transistor current levels are determined by the channel widths of the transistors, which widths are defined by the field oxide layers. This means that the stored information is written into the multi-level ROM at an early stage in the total ROM fabricating process; that is, at the stage of field oxide layer information. So, for a binary ROM, a manufacturer can stock ROM slices or substrates having many prefabricated transistors thereon, and when new ROM information is selected by a customer the manufacturer can complete ROMs starting from the slices on which the transistors are already fabricated. The manufacturer has only to wire the ROM transistors to finish the ROM. On the other hand, when new ROM information is selected by a customer for multi-level ROMs, the manufacturer must start with the fabrication of transistors. Thus, from the customer's point of view, it takes a longer time to fabricate a multi-level ROM than a binary ROM. This is a significant disadvantage. According to the present invention there is provided a semidoncuctor memory device, having a plurality of memory cells with metal insulator semiconductor transistors, formed in zones defined by field insulation, each comprising source and drain regions, of a first conductivity type, and a channel region, a maximum possible channel width of the transistor being defined by the field insulation, at least one of the said transistors also having at least one doped region, doped with a dopant of a second conductivity type, opposite to the first conductivity type, giving the transistor concerned an effective channel width less than the maximum possible channel width therefor (which lesser effective channel width may be zero). An embodiment of the present invention can provide a semiconductor multi-level memory device such that fabrication time for responding to an order from a customer can be reduced. In an embodiment of the present invention the memory device is such that gate electrodes and source-drain regions of MIS transistors can be formed on a ROM substrate in advance of a customer's order (that is, before the information to be stored is known to the manufacturer) and the substrates then held in stock waiting for the customer's order. when the order is received, information to be stored is written into the memory matrix in accordance with the customer's wishes by the application of MIS transistors whose channel width is variable. The present invention also provides a method of fabricating such a semiconductor multi-level memory device. The memory storage elements of such a semiconductor multi-level memory device are composed of MIS transistors whose currents are selected to correspond to the multi-level information to be stored. This selection is effected by varying the channel width of the MIS transistors in correspondence to the information to be stored. In a semiconductor multi-level ROM embodying the present invention, at the "half-fabricated" stage the memory matrix has only "standard" type MIS transistors. These standard type MIS transistors correspond to the highest current, and widest transistor channel width, which is usually defined by a field oxide layer. In the writing of information into the ROM, standard type MIS transistors of the "half-fabricated" ROM are selectively converted into the transistors having lower (including no) current, in correspondence to the digit level of the information to be stored. The conversion of standard type transistors is effected reducing their channel widths. This reduction of channel width is attained by a conventional ion implantation method. Dopant having opposite conductivity to that of drain and source region of a standard type MIS transistor is selectively ion-implanted into the channel region of the transistor to form one or more highly doped regions in the channel region such as to reduce the effective channel width. Reference is made, by way of example, to the accompanying drawings, in which: Fig.l shows a schematic circuitry diagram (a) and a schematic plan view (b) of a memory matrix contained in a previous NOR type binary mask ROM; Fig.2 shows a schematic plan view (a) of a memory cell of a previous multi-level mask ROM and schematic sectional views (b) of MOS transistors contained in the ROM; Fig.3 illustrates the structure of a multi-level mask ROM embodying the present invention; in Fig.3 (a) is a schematic plan view of a memory cell of the ROM and (b) gives schematic sectional views of MOS cell transistors and Fig.4 to Fig.9 illustrate a series of fabrication processes for fabricating a mask ROM as illustrated in Fig.3, each Figure schematically showing a part of the memory matrix of the ROM , at the relevant fabrication stage, in a plan view and in sectional views taken along flagged lines designated in the plan views; Fig.4 shows the memory matrix part after field insulator layer formation; Fig.5 shows the memory matrix part after polycrystalline silicon gate electrode formation; Fig.6 shows the memory matrix part after source and drain region formation; Fig.7 shows the memory matrix part after boron dopant is implanted into the substrate at specified regions of original channel regions; ; Fig. 8 shows the memory matrix part after effective channels of MIS transistors are formed by an annealing process ; and Fig.9 shows the memory matrix part at the final fabrication stage. The structures of previous semiconductor memories will first be briefly described. In the previous NOR type binary mask ROM of Fig.l, Tr indicates metal insulator semiconductor (MIS) transistors, generally being metal oxide semiconductor (MOS) transistors. Vss refers to a ground line, G indicates gate electrodes, L indicates drain wiring, C indicates drain contact windows, FL indicates field oxide layers, BL indicates bit lines and WL indicates word lines. In Fig.l(a), at each intersection of a bit line BL and a word line WL, a MIS transistor of the memory cell matrix is formed. The writing of the storage information into a mask ROM is performed during its fabrication. The current carried by each transistor (that is each memory cell) when the device is in use corresponds to the information stored therein. Cell transistors of only one type are used, and writing of information is accomplished by selectively wiring the transistors. The readout of information stored in a particular cell in the matrix is accomplished by sensing the current flow in the cell transistors. For instance, when an information bit stored in a cell at the intersection of an m'th word line (column) and an n'th bit line (row) is to be read out, readout voltage is applied to the m'th column and the consequent transistor current which flows is sensed through the n'th row. All the information bits stored in the ROM can be read out one by one consecutively and thus all the information stored in the ROM read out. The gate electrodes G and drain wiring L shown in Fig.l(b) correspond to the word lines WL and bit lines BL respectively. At each intersection of these lines an MIS transistor is formed. Connection (selective wiring) of a bit line to a cell transistor is performed by contacting the drain wiring L to the drain region of the MIS transistor through a window C. Fig.2 illustrates the memory cell structure of a previous multi-level (three level) ROM and it will now be explained how information is written into the cell. Fig.2(a) is a plan view of a part of the memory matrix of the ROM and Fig.2(b) shows at (1), (2) and (3) structures of cell transistors in sections taken respectively along lines A-A', B-B' and C-C' and viewed in the directions in which the flags on those lines taper in the plan view. In Fig.2, Trl, Tr2, Tr3 are cell transistors having respective different currents when in use , SUB is a silicon substrate, FL is a field oxide layer, OXg is a gate oxide layer, G indicates a gate electrode (word line), Vss indicates ground lines, S is a source region, D is a drain region, OX1 is an insulating layer, C is an electrode window and L is drain wiring (bit line). A multi-level output signal is provided by the cell of Fig.2 by the combination of different output currents of the MIS cell transistors. The source-drain current of an MOS transistor depends on the channel width. With narrower gate channels, channel resistance is increased and the current is lower. So, transistor Trl in Fig.2, having the greatest width W1 (see Fig.2(b)(l)) carries the highest current. The transistor Tr2 has a medium channel width (W2 - see Fig.2(b)2) and medium current. The transistor Tr3 has no channel, so provides no current. As will be clear from Fig.2, the channel width of each cell transistor is determined by the field oxide layer FL, which is created at an early stage of the ROM fabrication process. This gives rise to the disadvantage of long delivery time as previously described. In Fig.3, which illustrates an embodiment of the present invention, (a) is a plan view of the memory matrix of a NOR type multi-level mask ROM seen through electrode wiring (indicated by broken lines) and the gate oxide layer, and (b) shows at (1), (2), (3), (4) structures of four types of cell transistor (Trl, Tr2, Tr3 and Tr4 in sections taken respectively along the flagged lines A-A', B-B', C-C' and D-D' in (a). In Fig.3, P-SUB is a p-type silicon substrate, having a dopant density of approximately 5Xl015(atm/cm3), FL is a field oxide layer; that is, a thick oxide layer for restricting the areas of the cell transistors. OXg 0 is a gate oxide layer (500 to 1000 A thick); that is, a thin oxide layer. G indicates n -type polycrystalline silicon gate electrodes, S is an n type source region containing a Vss line, D is an n type drain region, OX1 is an insulating layer, L is aluminium (Al) drain wiring, P1, P2 and P3 are heavily p doped regions whose surface (doping) density is approximately 1017 (atm/cm3), Wf is the channel width defined by field oxide layers (4pm for instance), W1 is the maximum possible channel width, determined by the field oxide layer FL (4pm for instance), W2 is an effective channel width determined by highly doped regions P1 (3pm for instance), and W3 is an effective channel width determined by highly doped regions P2 (2#im for instance). The mask ROM having structure of Fig.3 has four output levels. The first output level is provided by the cell transistor Trl having the widest channel width W1 (4jim), which is determined by the field oxide layer FL. The second output level is provided by the cell transistor Tr2 having the second widest effective channel width W2 (3pm), which is determined by two heavily p-type doped regions P1. The third output level is provided by the cell transistor Tr3, whose channel has a narrow width W3 (2pm) determined by the two heavily p-type doped regions P2. The fourth output level is provided by the cell transistor Tr4 where the channel is masked completely by the heavily p-type doped layer P3. Now, a method of fabricating an MOS ROM in accordance with an embodiment of the present invention will be described with reference to Figs. 4 to 9. Each of those Figures, corresponding to a particular stage in the fabrication of the ROM, has a plan view, a sectional view (4) taken along a flagged line D-D' , in the plan view, which is perpendicular to gate electrode lines of the MOS ROM, and sectional views ((1), (2), (3)), taken along flagged lines A-A', B-B' and C-C' in the plan view, of three types of cell transistors (Tr1, Tr2, Tr3) formed in the device. A p-type silicon substrate 1 having a dopant 2X1016 3 density of 1 to 2X1016 (atm/cm ), for instance, is prepared. The fabrication begins with the formation of a field oxide (silicon dioxide) layer 3 using a conventional LOCOS (Local Oxidation of Silicon) method. As shown in Fig.4 the field oxide layer 3 is formed on the substrate 1 selectively, by a conventional thermal oxidizing method with a masking pattern of silicon nitride (Si3N4) film formed by conventional photo-lithographic technology. After removal of any remaining masking material by etching, the areas for the formation of cell transistors and other circuitry elements are ready. Usually a channel cut layer is formed underneath the field oxide layer 3, but this is not a direct concern of the present invention and so mention thereof will be omitted from the description and the Figures. As can be seen in sectional views (1), (2) and (3) in Fig.4, about half of the thickness of the field oxide layer 3 grows up above the original top surface of the substrate 1. After the field oxide layer 3 has been grown, another silicon oxide layer of 500 to 1000 AO thickness is formed by a conventional thermal oxidation method on the substrate to form gate oxide layer 4 as shown in Fig.5. This step is followed by the formation of a 0 polycrystalline silicon layer of 4000 to 5000 A thickness a using conventional chemical vapor deposition (CVD) method, and the layer is doped heavily with n-type dopant (phosphorus for instance) by a conventional gas diffusion method or ion implantation method. Next, Next, as shown in Fig.5, the n type polycrystalline silicon is etched to form the silicon gate electrodes 5. A conventional photo-lithographic technology utilizing reactive-ion etching method can be used for this pattern formation. A gas mixture of tetra-fluoro-methane (CF4) and oxygen (02) is suitable for the above etching. Utilizing the n+-type doped polycrystalline silicon gate electrodes 5 and the field oxide layer 3 as + a mask, n -type source region 7 (containing Vss lines) and n-type drain region 8 are created by a conventional ion implantation method as shown in Fig.6. The dopant material is arsenic (As), and is implanted with an acceleration energy of about 80 KeV at a high dose of around 4X1015 (atm/cm2 ) for instance. The implanted dopant, penetrating through the exposed gate silicon oxide layer 4, reaches the silicon substrate 1 and is diffused into it by a predetermined annealing treatment to provide n -type regions of 3000 to 4000 A depth. These are the source regions 7 (including Vss lines) and drain regions 8 of the cell transistors respectively. Now the device is ready for the setting therein of the multi-level information required to be stored. Devices at this stage of production can be stocked by a manufacturer to await an order from a customer specifying the information to be stored. Thus, it is possible to supply the customers with multi-level ROMs quickly as compared with the situation which prevailed previously, when the manufacturer could stock only devices at the stage of Fig 4. The surface of the device at the "half-fabricated" stage of Fig.6 is covered with a conventional photo-resist film 9, and then, corresponding to the specified information to be stored, windows al, a2 and b are opened for the cell transistors Trl, Tr2 and Tr4 for instance, as shown in Fig.7(a). These windows are formed by a conventional photo-lithographic technology on the areas where p -type doped regions are to be created in correspondence to the information level to be stored. Then, p-type dopant, boron (B) for instance, is implanted at the dose of 4 to 5X1013 (atm/cm2) with a high acceleration energy, 160 (KeV) for instance, through the windows a1,a2,h, etc. The photo-resist pattern 9 acts as a mask. for the dopant ions, the above-mentioned acceleration energy is high enough for the ions to penetrate the polycrystalline silicon layer 5 and gate silicon layer 4 and form boron+ implanted regions llal, lla2 and llb in channel areas as shown in Fig. 7. After removing the photo-resist layer 9, the device is annealed to diffuse the implanted dopant + (boron) to form the p -type regions 12a, 12b, 12c etc of 3000 AO thickness at channel areas underneath the gate silicon oxide layer 4 as shown in Fig. 8. The dopant diffuses not only in the thickness direction but also in lateral (sideways) directions and reduces the distance between the original implanted regions (e.g. llal, plan 12a, 12b). Thus, the distance d between implanted a regions (e.g. the distance between the windows al and a2 shown in Fig.7) should be determined to take account in advance of lateral diffusion of dopant. In the particular case shown in the Figures, for the cell transistor Tr2 for example, the window distance is taken to be 3.6 pm and the distance between two p -doped regions turns out to be 3.0 jim. It is preferable to create two p -doped regions, at opposite sides of the channel. This is because if only one p -type doped region is created, at one side of the channel, difficulty can be experienced in obtaining precise dimensional control of channel width because that width depends significantly on mask alignment. By + creating two p regions, the width of an effective channel region d is determined by the window openings a a and a2 (Fig.7) in the mask, and mask alignment is not critical. In Fig.8, three types of cell transistors at this stage of the fabrication process are shown. A cell transistor Trl, which has no p-type regions in its channel area, has the original channel width Wf or W1(Wtr in Fig.4), the widest possible channel width, determined by the field oxide layer 3. Thus, the cell transistor Tr provides the highest gate current and provides the ROM with a first output level. The cell transistor Tr2, which has two p-type doped regions 12a and 12b, has a narrower effective channel width W2 and provides a second output level. The cell transistor Tr4, whose channel area is occupied fully by p-typed doped region 12c, is regarded as being in an OFF stage and provides a fourth output level. A transistor Tr3 (not shown) with a channel width less than W2 can provide a third output level. In a similar way, it is possible to set more levels for an output signal in accordance with information to be stored. Next, another thin sillicon dioxide layer 13 is formed over the device by a conventional thermal oxidizing method, and an insulating layer 14 of phosphosilicate glass (PSG) is formed on the silicon dioxide layer 13. This is followed by etching of electrode contact windows such as drain contact window 15 (other windows are not shown in the Figures) using a conventional photo-lithography method. The edges of contact windows are rounded by heating the device to reflow the PSG layer. Electrode wirings 16 of aluminium or other materials are formed on the PSG layer 14 by conventional photo-lithographic technology and film forming technology as shown in Fig.9. Finally, though it is not shown further in the Figures, circuitry protecting means are formed on the substrate and the multi-level mask ROM is completed. As described above, the present invention can afford the advantage of reduced fabrication time for semiconductor multi-level memory devices to allow quick delivery in response to customers' orders. A manufacturer can stock the slices of semiconductor multi-level ROMs at the "half-fabricated" stage, ready for writing-in of information to be stored. When requested by a customer, the fabrication of multi-level ROMs for the customer effectively starts with the writing process for the ROM. This cuts down fabrication time and shortens the delivery time. For example, the delivery time of a multi-level ROM can be reduced from the current time of 8 weeks to a time of 3 weeks by the application of the present invention. It will be clear that embodiments of the present invention can provide memories offering any chosen number of output signal levels, by providing for an appropriate number of different channel widths in the memory. Even a two-level or binary memory can be provided. Although the described embodiments of the invention are n-channel (i.e. use n-channel transistors), it will be clear that p channel memories can be provided. In addition, it will be clear that conventional semiconductor fabricating methods are applicable to each fabrication step required for a device according to the present invention. An embodiment of this invention provides a multi-level semiconductor read only memory. Effective channel widths of the gates of MIS transistors of the memory are varied corresponding to the levels of information to be stored in the transistors. Variation of the effective channel width is performed by forming doped regions of an original channel region. The time required to fabricate a multi-level ROM can be reduced to less than a half that previously required.

Claims: CLAIMS 1. A semiconductor memory device, having a plurality of memory cells with metal insulator semiconductor transistors, formed in zones defined by field insulation, each comprising source and drain regions, of a first conductivity type, and a channel region, a maximum possible channel width of the transistor being defined by the field insulation, at least one of the said transistors also having a least one doped region, doped with a dopant of a second conductivity type, opposite to the first conductivity type, giving the transistor concerned an effective channel width less than the maximum possible channel width therefor (which lesser effective channel width may be zero). 2. A device as claimed in claim 1, the said transistors each further comprising a gate oxide layer and a gate electrode for example of doped polycrystalline silicon. 3. A device as claimed in claim 1 or 2, wherein the field insulation defines the same maximum possible channel width for all of the said transistors. 4. A device as claimed in claim 1,2 or 3, there being, among the said transistors, transistors having such doped regions giving them respective different effective channel widths (one of which may be zero) each less than the maximum possible channel width. 5. A device as claimed in any preceding claim, wherein the memory cells are multi-level memory cells. 6. A device as claimed in claim 5, wherein the field insulation is provided by field oxide, and each of the said transistors has an effective channel width (which may be the maximum possible channel width therefor as defined by the field insulation, or a lesser width) selected in accordance with information to be stored in the memory cell to which it belongs. 7. A device as claimed in any preceding claim, wherein the or each of the said transistors given an effective channel width less than the maximum possible channel width therefor, has two such doped regions formed in its channel region on opposite respective sides of the channel region, if the effective channel width thereof is greater than zero. 8. A device as claimed in claim 7, wherein the or each of the said transistors has such a doped region formed in its channel region extending across the whole channel width as defined by the field insulation, if the effective channel width thereof is zero. 9. A device as claimed in any preceding claim, wherein the said transistors are all of one channel type, either p-channel type or n-channel type, the or each such doped region being doped to a dopant density greater than 17 atm/cm3 with a dopant opposite to the channel type. 10. A "half-fabricated" semiconductor memory device, being a device as claimed in claim 1 or 2 taken to a stage in its production immediately prior to formation of such doped regions. 11. A method of fabricating a semiconductor memory device from the "half-fabricated" device of claim 10, comprising selectively implanting the said dopant, through gate electrodes and gate oxide layers if necessary, to provide each of the said transistors with an effective channel width selected in accordance with information to be stored in the memory cell to which it belongs. CLAIMS 1. ..A semi conductor memory device, having a plurality ls with metal insulator semiconductor of EMI16.1 memory cel transistors, formed in zones defined by field insulation, each comprising source and drain regions, of a first conductivity type, and a channel region, a maximum possible channel width of the transistor being defined by the field insulation, at least one of the said transistors also having a least one doped region, doped with a dopant of a second conductivity type, opposite to the first conductivity type, giving the transistor concerned an effective channel width less than the maximum possible channel width therefor (which lesser effective channel width may be zero). 2. A device as claimed in claim 1, the said transistors each further comprising a gate oxide layer and a gate electrode for example of doped polycrystalline silicon. 3. A device as claimed in claim 1 or 2, wherein the field insulation defines the same maximum possible channel width for all of the said transistors. 4. A device as claimed in claim 1,2 or 3, there being, among the said transistors, transistors having such doped regions giving them respective different effective channel widths (one of which may be zero) each less than the maximum possible channel width. EMI16.2 EMI16.3 A device as claimed EMI16.4 the field insulation is provided by field oxide, and each of the said transistors has an effective channel width (which may be the maximum possible channel width therefor as defined by the field insulation, or a lesser width) selected in accordance with information to be stored in the memory cell to which it belongs. EMI16.5 A device as claimed in any preceding claim, wherein the or each of the said transistors given an effective channel width less than the maximum possible channel width therefor, has two such doped regions formed in its channel region on opposite respective sides of the channel region, if the effective channel width thereof is greater than zero. EMI17.1 A device as claimed in claim EMI17.2 wherein the or each of the said transistors has such a doped region formed in its channel region extending across the whole channel width as defined by the field insulation, if the effective channel width thereof is zero. EMI17.3 A device as claimed in any preceding claim, wherein the said transistors are all of one channel type, either p-channel type or n-channel type, the or each such doped region being doped to a dopant density greater than 1017 atm/cm3 with a dopant opposite to the channel type. EMI17.4 A "half-fabricated" semiconductor memory device, being a device as claimed in claim 1 or 2 taken to a stage in its production immediately prior to formation of such doped regions. EMI17.5 A method of fabricating a semiconductor memory device from the "half-fabricated" device of claim EMI17.6 comprising selectively implanting the said dopant, through gate electrodes and gate oxide layers if necessary, to provide each of the said transistors with an effective channel width selected in accordance with information to be stored in the memory cell to which it belongs.

Inventors: HIRAO, HIROSHI C/O FUJITSU LIMITED, NAGASAWA, MASANORI C/O FUJITSU LIMITED, SUZUKI, YASUO C/O FUJITSU LIMITED
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: H01L29
IPC codes: H01L29, G11C11, G11C17, H01L27, H01L21