ALU WITH CARRY LENGTH DETECTION

Abstract: An ALU 10, performing selected operations on input operands in a predetermined clock cycle, uses means for detecting 40 a carry propagation path greater than a predetermined number of consecutive bit positions to cause a stretching of the clock cycle. Since such a long carry propagation path is detected for only a very small percen­ tage of all operations, the cycle is normally shorter than otherwise possible, and, thus, the performance of a system using such an improved ALU is increased.

Description: This invention deals with the Arithmetic and Logic Unit (ALU) section of computing systems, and more particularly it deals with synchronous ALUs having a look-ahead carry chain. Presently, one type of computing systems with ALUs use a look-ahead carry chain to improve the performance of the system, i.e. increase the speed of the computations. Very briefly, a conventional look-ahead carry chain is made up of a plurality of serial slices, with each slice having a predetermined number of input bits pairs forming a group. Within each slice the carry bit is propagated serially from the lower input pairs to the higher input pairs. However, the carry input to each successive slice is not taken from this slow propagating carry bit, but is instead generated from the group carry-propagate (P g ) and group carry-generate (G G ) signals produced in the current and all of the prior slices, i.e. the carry chain is "looking ahead" for the carry information between slices by generating a series of group carry signals, thus not waiting for the propagation delay of the carry bit between all of the input bit pairs. A serious problem with this type of system is that the performance of the system is still always limited by the worst case propagation delay of the look-ahead carry chain i.e. the propagation of the group carry. For a synchronous system this means that the smallest cycle time obtainable must be at least as long as the propagation delay for the combination of input bits that produces the longest group carry ripple. In some present day systems, the required cycle time by using a carry-save scheme. In this case, the system obtains all the intermediate (that is, bit or group) sums and carrys is one cycle, and combines them in a subsequent cycle to obtain the final answer. The problem of this approach is that the system must now pay an increased price in the hardware complexity required to implement a carry-save ALU. This is the case of the arrangement disclosed in the document US-A-3 947 671. SUMMARY OF THE INVENTION It is an object of this invention to reduce the cycle time needed for the great majority of ALU operations. It is another object of this invention to minimize the effect of carry propagation delay in the ALU without increasing the hardware complexity and without excessively adding to the number of devices needed. The present invention, then, provides for a system whose ALU uses carry-length detection means that take advantage of the fact that most ALU operations have a largest maximum carry length, i.e. the number of consecutive input bit positions propagating a carry, that is much less than the width of the ALU. Thus, by detecting a "long" carry and providing additional time, i.e. a stretched cycle for synchronous systems, for the ALU to complete the operation for a small percentage of operations, a data path can be run in the present system at a faster rate for most ALU cycles. This invention further provides for means for performing a selected operation on input operands in a predetermined clock cycle, first means for detecting a path for a carry propagation through a number of consecutive bit positions greater than a first predetermined number, and means for stretching the clock cycle by a first predetermined amount in response to a signal generated by the first detecting means. Preferably there are also provided second means for detecting a path for a carry propagation through a number of consecutive bit positions greater than a second predetermined number greater than the first, and second means for stretching the clock cycle by a second predetermined amount in response to a signal generated by the second detecting means. Preferably, the detecting means only detect the carry propagation path for a subset of all bit positions, for excluding preselected bit positions from generating the cycle stretching signal. This invention also provides for means for performing a selected operation on input operands in a predetermined clock cycle, said operands occupying a number of bit positions, means, including a plurality of detection cells, for detecting a carry propagation path through a number of consecutive bit positions at least as great as a predetermined threshold range, the range having as a lower limit the minimum number of consecutive carry propagations within one of a plurality of pre-determined groups of detection cells and as an upper limit the number of consecutive carry propagations that set at least one of the groups, and means for controlling the cycle in response to the detecting means. The invention is mainly directed to an arithmetic and logic unit that includes a timing signal control circuit for controlling a timing signal generator that generates iterative periodic timing signals used to control said arithmetic and logic unit, said arithmetic and logic unit further including means for performing operations in response to said timing signals, said arithmetic and logic unit processing data signals in parallel, performing selected processing operations, and generating carry propagate signals (P₀ - P₅₉) in parallel from pairs of operand input bits, each of said carry propagate signals (P₀ - P₅₉) having an asserted and a negated condition, said timing signal control circuit comprising : A. control signal generating means for generating a control signal ; and B. disabling means connected to said control signal generating means for disabling said timing signal generator for a selected period of time in response to said control signal, thereby to elongate the period between timing signals when a selected number of consecutive ones of said carry propagate signals have the asserted condition, characterized in that said control signal generating means are arranged for monitoring all of said carry propagate signals and for generating a control signal in response to said selected number of consecutive ones of said carry propagate signals having the asserted condition. The invention is also directed to an arithmetic and logic unit that includes a timing signal control circuit for controlling a timing signal generator that generates iterative periodic timing signals used to control the arithmetic and logic unit, said arithmetic and logic unit further including means for performing operations in response to said timing signals, said arithmetic and logic unit processing data signals in parallel and for performing selected processing operations, characterized in that said timing signal control circuit comprises : A. carry propagate signal generating means for monitoring all operand input bits and for generating carry propagate signals from all pairs of operand input bits; B. group carry propagate signal generating means for monitoring all of the carry propagate signals and for generating a group carry propagate signals in response to a selected number of consecutive ones of said carry propagate signals having the asserted condition ; C. control signal generating means for monitoring all of the group carry propagate signals and for generating a control signal in response to a selected number of consecutive, ones of said group carry propagate signals having the asserted condition ; and D. disabling means for disabling said timing signal generator for a selected period of time in response to said control signal, thereby to elongate the period between timing, signals when said selected number of consecutive ones of said carry propagate signals have the asserted condition. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A shows a block diagram of an ALU using the means for detecting the carry length according to the present invention ; Fig. 1B shows a first preferred embodiment of the Carry Length Detection Circuit of Fig. having group carry-propagate signals as inputs ; Fig. 2 shows a second embodiment of the Carry Length Detection Circuit for an ALU using 4-bit groupings, instead of the 5-bit groupings as shown in Fig. 1B ; Fig. 3 shows a third embodiment of the Carry Length Detection Circuit using multi-tier gating ; Fig. 4 shows fourth embodiment of the Carry Length Detection Circuit using additional gates for overlapping bit groupings ; and Fig. 5 shows a cell used to produce an alternative input to the Carry Length Detection Circuit of the prior figures. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to Fig. 1A, there is shown a block diagram for the ALU of the present invention. ALU 1⊘ is shown as having two 6⊘-Bit operands as inputs, A ⊘ -A₅₉ and B ⊘ -B₅₉ respectively. The inputs are fed to a conventional P and G Derivation Circuit 2⊘ which is used to generate a carry-propagate (P i ) signal and carry-generate (G i ) signal for each input bit pair, A i B i . The P i an G i signals are generated to implement the specific function required. For instance, to implement the sum of the A i and B i inputs, the P i signal is generated as the output of an exclusive-OR gate whose inputs are the A i and B i signals, and the G i signal is generated as the output of an AND gate whose inputs are also the A i and B i signals. The P i and G i signals are then fed, in groups corresponding to 5 input bits and referred to as slices, to corresponding slices of Carry Look-Ahead Circuits 22. Carry Look-Ahead Circuits 22 use the P i and G i signals of a slice to provide the group carry-propagate signal P Gi and the group carry-generate signal G Gi for that slice. For the first slice 22A, Look-Ahead Circuit 22 implements the following Boolean expressions: P G⊘ = P ⊘ ·P₁·P₂·P₃·P₄ G G⊘ = G₄+(P₃·G₃)+(P₃·P₂·G₂)+(P₃·P₂·P₁·G₁)+(P₃·P₂·P₁·P ⊘ ·G ⊘ ) where "·" corresponds to the AND function and "+" corresponds to the OR function. The remaining slices 22B, through 22L, implement similar expressions with their corresponding input signals P i and G i . The group carry-propagate signal P Gi and the group carry-generate G Gi are then coupled to a corresponding slice of the Group Carry Chain Circuits 24. Each Group Carry Chain slice has as the main input the carry-in signal C Gi from the previous slice, or, for the first slice, the initial carry condition C in , and processes it according to the corresponding P Gi and G Gi signals. This is implemented by passing through the C Gi signal from the prior slice if P Gi is asserted or by setting C Gi if G Gi is asserted. The individual P i and G i signals and the group carry-in signal C Gi are coupled to corresponding slices of the Local Carry Generation Circuits 26. For example the first stage 26A implements the following Boolean expressions: C ⊘ = C G⊘ = C in C₁ = (C ⊘ ·P ⊘ )+G ⊘ C₂ = (C ⊘ ·P ⊘ ·P₁)+(G ⊘ ·P₁)+G₁ C₃ = (C ⊘ ·P ⊘ ·P₁·P₂)+G ⊘ ·P₁·P₂+G₁·P₂+G₂ C₄ = (C ⊘ ·P ⊘ ·P₁·P₂·P₃)+(G ⊘ ·P₁·P₂·P₃)+(G₁·P₂·P₃)+(G₂·P₃)+G₃ The remaining slices implement similar expressions for the corresponding input signals C Gi , P i and G i . The carry signals C i thus generated are then coupled in corresponding slices of Operation Result Circuits 28 to generate the result signals R i . For example, to implement the sum of the A i and B i inputs the C i signals and the P i signals are coupled to an exclusive-OR gate. The P Gi signals generated by Carry Look-Ahead Circuits 22, slices A-L, are also fed to Carry-Length Detection Circuit 4⊘. The purpose of Carry-Length Detection Circuit 4⊘ is to detect whether the width of the Carry Propagation Path is greater than a threshold value. This is implemented by detecting if the number of consecutive P i signals that are asserted is greater than a predetermined value. If it is, then the ALU operation in progress will not finish within the prescribed cycle, and a clock cycle stutter signal will be generated which will delay the next operation of the system by one additional cycle. This is implemented by ANDing the single signal from Carry-Length Detection Circuit 4⊘ with an Allow Stutter Signal 51 in AND gate 5⊘ and providing a Clock Stutter Signal 54 to Clock Control Circuit 7⊘, which is used by that circuit to extend the clock cycle. As shown, Clock Control Circuit 7⊘ produces the appropriate timing for a four-phase clock. The block diagram for the ALU 1⊘ also shows that the operation code 75 controlling the ALU is input to Decode Circuit 76. Decode Circuit 76 then generates various signals that are needed by the ALU and whose values depend on the operation to be performed. An 8-bit function control signal 77 may be used to determine the function, or operation, to be performed on the input operands A and B. This is achieved by controlling the generation of the P i and G i signal in P & G Derivation Circuit 2⊘ and the generation of the R i signals in Operation Result Circuits 28. For instance, it was shown that for an addition, the function control causes the P i to be the exclusive-OR function of A i and B i , and the G i to be the AND function of A i and B i , while the R i is the exclusive-OR function of the C i and P i signals. An initial carry-in C in is coupled to the first slice 24A of the Group Carry Chain Circuit to be used as C G⊘ . An Enable Double Precision Signal 47 is coupled to the Carry-Length Detection Circuit 4⊘ to be used by that circuit, as explained in more detail below, to ignore the unused bits during a single precision operation. Similarly, the Allow Stutter Signal 51 is coupled to gate 5⊘ to inhibit the stutter signal from propagating during those operations where the carry propagation can be ignored, for example as when transferring a register to itself through the ALU. Decode Circuit 76 may be implemented by a PLA or a ROM. Referring now to Fig. 1B, there is shown in more detail the Carry-Length Detection Circuit 4⊘. The carry-propagate signals P ⊘ -P₅₉, generated by the P and G Derivation Circuit 2⊘, are fed to a first level of AND gates 42 in groups of five to generate intermediate group propagate signals P G⊘ through P G11 . Thus, P ⊘ -P₄ are coupled to a first gate 42A, P₅-P₉ are coupled to a second gate 42B, and so on, with P₅₅-P₅₉ being coupled to gate 42L, the last of the first level gates. Typically these gates are part of Carry Look-Ahead Circuits 22. The outputs of this first level gating, i.e. the intermediate group propagate signals P G1 through P G1⊘ , are fed in pairs to a corresponding gate in a second level of AND gates 44. The outputs of first and last gate 42A and 42L are not used by circuit 4⊘ for reasons that will become clear as the description progresses. Thus, the 5-bit group carry propagate signals P G1 and P G2 , produced respectively by gates 42B and 42C in Carry Look-Ahead Circuits 22B and 22C, are shown coupled to gate 44A, the outputs P G3 and P G4 of gates 42D and 42E are shown coupled to gate 44B, and so on. The reason for the particular two levels of AND gating is that the first level of gating, i.e. gates 42A through 42L and P G⊘ through P G11 , is already present for the 5-bit group carry look-ahead logic. Thus, gates 42 need not actually be provided within Carry-Length Detection Circuit 4⊘, but instead the P G⊘ through P G11 signals may be provided directly from the corresponding slices of Carry Look-Ahead Circuit 22, as shown. The ANDing in pairs of two adjacent group carry-propagate signals P Gi is used to generate a signal which indicates whether or not all of the signals P i in the corresponding group of ten bits are asserted. The outputs P G2⊘ through P G24 of the second level gates 44 are then OR gated in gate 48 to generate the Propagate Stutter Signal 49. Thus, a propagate stutter signal is generated if the two 5-bit carry propagate signal groups associated with any one of gates 44 are asserted. The Propagate Stutter Signal 49 may then be set for as few as ten asserted consecutive signals P i , provided that they fall within a coupled pair of first level gates 42. For example, if P₃₅ through P₄₄ are asserted across gates 42H and 42I, then both signals P G7 and P G8 become asserted and, in turn, signal P G23 from gate 44D becomes asserted. If the ten consecutive signals P i do not fall within a coupled gate pair, then none of group carry propagate signals P Gi might be asserted. For example if P₃₆ through P₄₅ are asserted, then signal P G7 from gate 42H is not asserted, and in turn signal P G23 from 44D will not be asserted. The minimum number of consecutive carry-propagate signals P i that will always generate a propagate stutter signal 49 is nineteen, since that number of P i signals will always straddle a coupled gate pair. For instance if P₃₅ through P₅₃ are asserted, then all inputs to gates 42H and 42I are asserted, allowing the assertion signal to flow through and set the propagate stutter signal 49. The reason for not including the first and last gate, 42A and 42L respectively, in the second level gating should then be clear. The circuit 4⊘ is designed to set the propagate stutter signal 49 for as few as ten consecutive P i signals but might not set for as many as eighteen consecutive P i signals for the worst case. Thus, it is not necessary to monitor the first or last five P i signals. The additional advantage of not gating the two end gates is that an additional performance improvement is obtained when the end bits, either least significant or most significant 5 bits, of the two inputs A i and B i are not random with respect to each other. In this case by not gating these end bits the probability of generating a clock cycle stutter is decreased. The Propagate Stutter Signal 49 is gated in AND gate 5⊘ with an Allow Stutter signal 51, which is normally set. The Allow Stutter signal 51 is not set for ALU operations in which all input bits produce a carry-generate signal G i , thereby preventing unnecessary stutter cycles for ALU operations in which the propagation of the carry is not a factor. A Double Precision Enable signal 47 is also included in the second level detection gates for signals P₅ through P₃₄, to eliminate detection of a long carry over bits unused while calculating in single precision, while all 6⊘ bits are enabled for double precision operation. It should be clear that the principles of this invention are not limited to 60-bit ALUs, but that they can be applied to ALUs of any width and are applicable to designs usings standard parts as well as custom designs. The optimal width of the AND function used to produce the group carry propagate signals depends on the technology in which the ALU is implemented. Referring now to Fig. 2, there is shown a diagram for the Carry-Length Detection Circuit 40 for a 32-bit ALU where the width of the group carry-propagate is 4 bits. AND gates 60A through 60H form the first gating level in Carry Look-ahead circuit 22 and gates 62A through 62C form the second gating level of Carry-Length Detection circuit 40. OR gate 64 is used to propagate a Propagate Stutter Signal 65 if all the eight consecutive carry-propagate signals P i of a first coupled gate pair, i.e. gates 60B-60C, 60D-60E or 60F-60G, are asserted. This circuit, then, sets the stutter signal if as few as eight consecutive P i signals line up in a corresponding coupled gate pair, but might not set it for as many as fourteen consecutive P i signals if they do not line up with a corresponding coupled gate pair. Thus, in the worst case, fifteen consecutive P i signals are needed to generate a Propagate Stutter signal 65. In this implementation the Allow Stutter signal 51 is used as described above to inhibit the clock stutter signal for those ALU operation in which the carry propagation is not a factor. In general, if the individual carry-propagate signals P i are not available, as they are not when using standard part ALU slices such as ALU slices 74181 and 74381 available from Texas Instruments or Microprocessor Slice AMD 29⊘1 available from Advanced Micro Devices, then the ANDing of the P i signals can be used as shown. Since the group carry-propagate signals are already required for any ALU with look-ahead carry, the Group Carry-Propagate signals P Gi can be used directly form the Look-Ahead circuitry, thus, the Carry Length Detection Circuit is very inexpensive to implement. The mode of operation described thus far is synchronous in that the timing of all the operations is controlled by a clock signal, usually in the form of a plurality of phases, occuring at regular intervals. If the current operation cannot complete within one of these time intervals, the clock stutter signal is used to delay the execution of a new operation by one additional time interval, during which time the current operation will finish. Thus in the case of the embodiment of Fig. 1, the ALU must be designed to be fast enough to process the worst case of eighteen consecutive carry propagations within a clock cycle, while for the embodiment of Fig. 2, the ALU must process the worst case of fourteen consecutive carry propagations within a clock cycle. Another mode of operation is possible, however. Since the carry propagate terms become valid after a fixed combinational delay, the Clock Stutter signal 54 is valid early enough in the cycle to extend a phase of the system clock by a predetermined amount allowing just enough time for the current operation to complete if necessary. This additional time, provided if a stutter signal is asserted, must be long enough for the worst case of consecutive carry propagations to complete. In this mode of operation the stutter signal is not used to "stutter" the system clock, to essentially issue a fixed increment of delay, but is used to delay the clock cycle by a variable amount sufficient to assure completion of the current operation. Referring now to Fig. 3, there is shown an embodiment of the invention implementing this feature. The first level gates 42 of Carry Look-Ahead Circuit 22 are coupled to second level gates 44 in Carry Length Detection Circuit 40, and in turn are coupled through OR gate 48 to gate 50 to generate a first Clock Stutter signal 54, as explained before in connection with Fig. 1. Stutter signal 54 is now used by Clock Control 70 to extend a phase of the system clock, by a first predetermined amount, if the current operation can be completed within this additional time. To determine if more time is needed to complete the current operation a second tier of carry-length detection using a wider bit grouping is used, and if needed it provides a second predetermined amount of clock stretch. To implement this, the paired group carry-propagate signals P G20 through P G24 are now also used in consecutive pairs as inputs to a third gating level formed by AND gates 120A through 120D. The wide-group carry-propagate signals P G3⊘ through P G33 are then O Red in OR gates 122 to provide a second Propagate Stutter signal 123. This is in turn gated by AND gate 124 with Allow stutter signal 51 to produce a second stutter signal 126. In the embodiment shown, stutter signal 126 will extend, by a second predetermined amount, a phase of the system clock if as few as twenty consecutive carry-propagate are asserted, but will always set if at least twenty-nine consecutive carry-propagate signals are asserted. Thus, clock control 7⊘ will extend a phase of the ALU clock by a first amount of time equal to at least the propagation delay of an additional ten consecutive carry propagations if stutter signal 54 is set. If stutter signal 126 is set, Clock Control 7⊘ will further extend the phase by a time equal to a second preselected amount to account for the worst case of consecutive carry propagation. Thus, by providing additional gating tiers, the delay of the current clock phase is more closely tuned to the actual time required to complete the current operation. In most cases the additional time is substantially less than the full additional clock cycle as discussed in connection with the prior figures, thus further improving the performance of the ALU. Even by using a single stutter signal, the performance is increased, because most ALU operation (greater than 95%) will not require an additional clock cycle. For example, in the circuit described in Fig. 1, the probability of requiring an additional cycle, a stutter, on random data is approximately: P = ((w-m)/n)(2 (w-n) )/2w Where w = width of ALU m = number of bits not included in a detection gate n = width of the detection gate This reduces to P = ((w-m)/n)(2 -n ) For double precision operations: w = 6⊘, m =1⊘, n = 1⊘ Resulting in P = 5/1⊘24 and for single precision operations: w = 3⊘, m = 1⊘, n = 1⊘, resulting in P = 2/1⊘24. It should be noted that the equation used produces a slightly high probability function since data which sets more than one detection gate is counted more than once. The present invention provides for an ALU that must handle in a unit cycle, without a clock stutter, the maximum number of consecutive carry propagations that will not set the stutter signal. For example, this number is eighteen for the embodiment shown in Fig. 1 and fourteen for the embodiment of Fig. 2. However, it should be understood that this number can be decreased to accomodate slower ALU designs without compromising, i.e. decreasing, the minimum number of consecutive carry propagations that will trigger a clock stutter. Thus the difference between the maximum carry length which always stutters the clock and the minimum carry length which might stutter the clock can be controlled by adding additional sets of AND gates to produce overlapped groupings of consecutive carry propagate signals. This is shown in the embodiment of Fig. 4, where the first level gates 42 are used as before to provide the initial grouping of five carry-propagate signals P i to produce group carry-propagate signals P G⊘ through P G11 . The group carry-propagate signals are paired into a corresponding second level set of AND gates 44 A-F. This time the first and last first level gates 42A and 42L are shown as included in the gating to provide uniform detection across all bit positions. Additionally, gates 14⊘A-E are used, also in the second level, to provide a second set of groupings offset by one gate to overlap with the first set of groupings. All of the outputs P G13 through P G17 of the second level AND gates are gated in OR gate 142 to produce a Propagate Stutter signal 143. With this arrangement, Propagate Stutter signal 143 might be set with a minimum of ten consecutive carry-propagate signals, provided that they line up with any two first level gates (for instance P₃₅ through P₄₄ in gates 42H and 42I). With such an arrangement, the Propagate Stutter signal will always set with fourteen consecutive carry-propagate on the input of the first level gates 42 (for instance, P₃₁ through P₄₄ in gates 42G, 42H and 42I). Thus, the ALU for the embodiment shown in Fig. 4 need only process a maximum of thirteen carry propagations within a clock cycle, without requiring a clock stutter. A modification to the Carry-Length Detection Circuit 4⊘ tray be made, by changing the type of signals monitored to detect the continuous propagation path. for instance, instead of using only the group carry-propagate signals P Gi , the carry generate signals G i could also be used in the first level gating to detect a break in the carry propagation path, which occurs if the G i signal is asserted. In this case, an arrangement using a plurality of cells, a single such cell being shown in Fig. 5, can be used to produce the appropriate signals to be used as inputs to the Carry-Length Detection circuit 4⊘. In each cell an output signal is produced in two stages. First the AND function of individual carry-propagate signals P i with the complement of a corresponding carry-generate signal G i is provided by gates 1⊘⊘A₁ through 1⊘⊘A₅. Second, an AND gate 1⊘2A is used to produce the Boolean expression: CP ⊘ = (P₄·G₄)·(P₃·G₃)·(P₂·G₂)·(P₁·G₁)·(P ⊘ ·G ⊘ ) where CP ⊘ is the first signal provided as an input to the first gate of Carry Length Detection Circuit 4⊘. Each cell, then provides a signal which is asserted only if all its corresponding P i and none of the G i signals are set.

Claims: An arithmetic and logic unit (10) that includes a timing signal control circuit (22, 40) for controlling a timing signal generator (70) that generates iterative periodic timing signals used to control said arithmetic and logic unit (10), said arithmetic and logic unit (10) further including means for performing operations in response to said timing signals, said arithmetic and logic unit (10) processing data signals in parallel, performing selected processing operations, and generating carry propagate signals (P₀ - P₅₉) in parallel from pairs of operand input bits, carry propagate signals (P₀ - P₅₉) having an asserted and a negated condition, said timing signal control circuit (22, 40) comprising : A. control signal generating means (42, 44, 48, 60, 62, 64, 140A-E, 142) for generating a control signal (49, 65, 143) ; and B. disabling means (50) connected to said control signal generating means (42, 44, 48, 60, 62, 64, 140A-E, 142) for disabling said timing signal generator (70) for a selected period of time in response to said control signal (49, 65, 143), thereby to elongate the period between timing signals when a selected number of consecutive ones of said carry propagate signals (P₀ - P₅₉) have the asserted condition, characterized in that said control signal generating means (42, 44, 48, 60, 62, 64, 140-E, 142) are arranged for monitoring all of said carry propagate signals (P₀ - P₅₉) and for generating a control signal (49, 65, 143) in response to said selected number of consecutive ones of said carry propagate signals (P₀ - P₅₉) having the asserted condition. An arithmetic and logic unit (10) as defined in claim 1 wherein said control signal generating means (42, 44, 48, 60, 62, 64, 140A-E, 142) includes a plurality of coincidence gate means (42, 44, 60, 62, 64, 140A-E, 142) each for receiving a pre-determined number of selected consecutive ones of said carry propagate signals (P₀ - P₅₉) and for generating an asserted output signal (P G20 - P G24 ) if none of the received signals are negated, and means (48, 64) connected to the ouput terminals of all of said coincidence gate means (42, 44, 60, 62, 64, 140A-E, 142) for generating said control signal (49, 65, 143) in response to any of said asserted output signals (P G20 - P G24 ). An arithmetic and logic unit (10) as defined in claim 1 which further generates an enable signal (51), said disabling means (50) disabling said timing signal generator (70) in response to the coincidence of said control signal (49, 65, 143) and said enable signal (51). An arithmetic and logic unit (10) as defined in claim 1 wherein said timing signal control circuit (22, 40) further comprising : A. second control signal generating means (120A-D, 122) for generating a control signal (123) ; and B. second disabling means (124) connected to said second control signal generating means (120A-D, 122) for disabling said timing signal generator (70) for a second selected period of time in response to said control signal (123), thereby to further elongate the period between timing signals when said second selected number of consecutive ones of said carry propagate signals (P₀ - P₅₉) have been asserted, wherein, said second control signal generating means (120A-D, 122) monitors all of said carry propagate signals (P₀ - P₅₉) and generates a control signal (123) in response to a second selected number, greater than said first selected number, of consecutive ones of said carry propagate signals (P₀ - P₅₉) having the asserted condition. An arithmetic and logic unit (10) that includes a timing signal control circuit (20, 22, 40) for controlling a timing signal generator (70) that generates iterative periodic timing signals used to control the arithmetic and logic unit (10), said arithmetic and logic unit (10) further including means for performing operations in response to said timing signals, said arithmetic and logic unit (10) processing data signals in parallel and for performing selected processing operations, characterized in that said timing signal control circuit (20, 22, 40) comprises : A. carry propogate signal generating means (20) for monitoring all operand input bits (A₀ - A₅₉, B₀ - B₅₉) and for generating carry propagate signals (P₀ - P₅₉) from all pairs of operand input bits; B. group carry propagate signal generating means (22) for monitoring all of the carry propagate signals (P₀ - P₅₉) and for generating a group carry propagate signals (P G0 - P G11 ) in response to a selected number of consecutive ones of said carry propagate signals (P₀ - P₅₉) having the asserted condition ; C. control signal generating means (40) for monitoring all of the group carry propagate signals (P G0 - P G11 ) and for generating a control signal (49, 65, 143) in response to a selected number of consecutive ones of said group carry propagate signals (P G0 - P G11 ) having the asserted condition ; and D. disabling means (50) for disabling said timing signal generator (70) for a selected period of time in response to said control signal (49, 65, 143), thereby to elongate the period between timing signals when said selected number of consecutive ones of said carry propagate signals (P₀ - P₅₉) have the asserted condition. An arithmetic and logic unit (10) as defined in claim 5 wherein said control signal generating means (40) includes a plurality of first OR gates (44, 62, 140) each for receiving a pre-determined number of consecutive pairs of said group carry propagate signals (P G0 - P G11 ) and for generating a first asserted signal (P G20 - P G24 ) if said pairs are asserted, and a second OR gate (48, 64, 142) connected to the output terminals of all of said first OR gates (44, 62, 140) for generating said control signal (49, 65, 143) in response to the assertion of any first asserted signal (P G0 - P G11 ). An arithmetic and logic unit (10) as defined in claim 5 which further generates an enable signal (51), said disabling means (50) disabling said timing signal generator (70) in response to the coincidence of said control signal (49, 65, 143) and said enable signal (51). An arithmetic and logic unit (10) as defined in claim 5 wherein said control signal generating means (40) includes a plurality of third OR gates (120) each for receiving a pre-determined number of consecutive pairs of said first asserted signal (P G20 - P G24 ) and for generating a second asserted signal (P G30 - P G33 ) if said pairs are asserted, and a fourth OR gate (122) connected to the output terminals of all of said third OR gates (120, 122) for generating a second control signal (123) in response to the assertion of any second asserted signal (P G30 - P G33 ). An arithmetic and logic unit (10) as defined in claim 8 wherein the disabling means (50) further comprises a second disabling means (124) connected to said fourth OR gate (122) for disabling said timing signal generator (70) for a second selected period of time in response to said second control signal (123), thereby to further elongate the period between timing signals when said second selected number of consecutive ones of said carry propagate signals (P₀ - P₅₉) have been asserted.

Inventors: DOBBERPUHL, DANIEL, MCLELLAN, EDWARD J., WOLRICH, GILBERT, YODLOWSKI, ROBERT
Applicants: DIGITAL EQUIPMENT CORPORATION
Application year: 1984
Main classification: G06F7
IPC codes: G06F7