SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device including a nonvolatile random access memory cell constituted by a combination of a static random access memory cell (1) or a dynamic random access memory cell and a floating circuit element (D₅, Q₆), is disclosed. In the device, the circuit constitution, the application of writing voltage (V HH ), and the like, are improved. Thus, the number of circuit elements, particularly the number of floating gate circuit elements (Q₆), is reduced. As a result, the cell area can be decreased, high integration of the device can be achieved, and the production yield of the device can be increased. In addition, improvement of the circuit configura­ tion increases the discretion allowed in the layout design, and repeated application of the write voltage (V HH ) improves the storage efficiency.

Description: The present invention relates to a semiconductor memory device, more particularly, it relates to a nonvolatile memory device constituted by combining a volatile memory cell and a nonvolatile memory cell including a floating gate circuit element. Recently, in a static random access memory device (RAM), a volatile memory cell is combined with a floating gate circuit element to obtain a nonvolatile memory cell which is used to constitute a nonvolatile memory device. In a nonvolatile memory device of this type, the circuit configuration of each memory cell tends to be complex, and so the size of each memory cell tends to be large. However, this tendency leads to degradation in the reliability and integration of the memory device. In view of this problem, this tendency must be eliminated by a special circuit configuration or the like. The prior art regarding this invention is disclosed in United States Patent No. 4,300,212, and will be explained later in this text. An article in "Electronic Design", Vol. 29, No. 4, 19th February 1981, pages 72 to 82, discloses a semiconductor memory device having the features of the precharacterising part of accompanying claim 1. EP-A-0 087 007 discloses a dynamic RAM with nonvolatile back-up storage, using a layer of DEIS (Dual Electron Injection Structure) material to control the charge of a floating gate. According to the present invention there is provided a semiconductor memory device comprising a volatile memory cell and a nonvolatile memory cell corresponding to the volatile memory cell, said nonvolatile memory cell comprising a transistor which has a floating gate and is operable to turn on or off in response to memorised data, a tunnel capacitor, one electrode of which is connected to the floating gate, and a write circuit coupled to an electrode of the tunnel capacitor, said write circuit being operable to supply a high-voltage control power source to said tunnel capacitor in response to the memorised data of said volatile memory cell; characterised in that said write circuit comprises:- a first write circuit connected to the other electrode of said tunnel capacitor, comprising a first capacitor connected between said high-voltage control power source and said tunnel capacitor, and a first switch means connected between a power source and said tunnel capacitor, controlled by the voltage at a data output node of said volatile memory cell; and a second write circuit connected to said electrode of the tunnel capacitor which is connected to the floating gate, comprising a second capacitor connected between said high-voltage control power source and said tunnel capacitor, and a second switch means connected between said power source and said tunnel capacitor, controlled by the voltage at another data output node of said volatile memory cell; whereby, in dependence upon the memorised data of said volatile memory cell, one side of the tunnel capacitor is connected to said high-voltage control power source and the other side is connected to said power source. An embodiment of the present invention can provide a semiconductor memory device wherein the number of circuit elements is reduced, the area of a cell by which the device is constituted is reduced, high integration of the circuit is achieved, and the number of tunnel capacitors which are the constituent elements is decreased, thereby increasing the production yield. An embodiment of the present invention can increase the discretion of the layout design regarding the memory cell circuit. An embodiment of the present invention can increase the storing efficiency by a plurality of write voltage applications. Reference is made, by way of example to the accompanying drawings in which:- Fig. 1 shows a circuit diagram of a memory cell used in a conventional semiconductor memory device; Figs. 2 to 6 show circuit diagrams of memory cells used in a semiconductor memory device according to first to fifth embodiments of the present invention, respectively; Fig. 7 shows a modification of the memory cell in Fig. 6; Fig. 8 shows a circuit diagram of a memory cell used in a semiconductor memory device according to a sixth embodiment; Fig. 9 shows a circuit diagram of a memory cell used in a semiconductor memory device according to a seventh embodiment; Fig. 10 shows a circuit diagram of a memory cell as a modification of the memory cell in Fig. 9; Fig. 11 shows a circuit diagram of a memory cell used in a semiconductor memory device according to an eighth embodiment of the present invention; Fig. 12 shows a circuit diagram of a memory cell used in a semiconductor memory device according to a ninth embodiment of the present invention; Fig. 13 shows a circuit diagram of a memory cell used in a semiconductor memory device according to a tenth embodiment of the present invention; Fig. 14 shows a partial circuit diagram of a memory cell as a modification of the memory cell in Fig. 13; Fig. 15 shows a partial circuit diagram of a memory cell as another modification of the memory cell in Fig. 13; Fig. 16 shows a partial circuit diagram explaining the principle of an eleventh embodiment; Fig. 17 shows a block circuit diagram of a semiconductor memory device as a whole according to the eleventh embodiment; Figs. 18 and 19 show graphs explaining the effect of the device in Fig. 17; Fig. 20 shows a plan view of a pattern layout of the memory cell shown in Fig. 3 on the semiconductor substrate; and Fig. 21 shows a plan view of a pattern layout of the memory cell shown in Fig. 4 on the semiconductor substrate. Prior to the description of the embodiments of the present invention, an explanation is given of the prior art. In Fig. 1, a memory cell used in a conventional nonvolatile memory device is shown. The memory cell in Fig. 1 comprises a volatile static memory cell portion 1 comprising MIS (metal insulator semiconductor) transistors Q₁, Q₂, Q₃, Q₄ and Q G , and a nonvolatile memory cell portion 2 having a MIS transistor Q₆ with a floating gate and the like. The memory cell stores one-bit data. The nonvolatile memory cell portion 2 has, in addition to the MIS transistor Q₆, a MIS transistor Q₅, tunnel capacitors TC₁ and TC₂, a capacitor module CM₁, and capacitors C₁ and C₂. A capacitor which generates a tunnel effect by the application of a voltage between the electrodes thereof will be hereinafter called a tunnel capacitor. In the circuit shown in Fig. 1, the static memory cell portion 1 has a flip-flop configuration which is ordinarily used in a conventional static RAM device. Data read/write is performed through a transfer gate transistor Q G connected to nodes N₁ and N₂. The nonvolatile memory cell portion 2 has a floating state wherein the circuit including the gate of the MIS transistor Q₆ floats from the other circuit components. Data is stored by injecting or not injecting electrons into this floating circuit. Therefore, a high-speed nonvolatile memory device can be realized with a transfer and a recall configuration; i.e., by transferring data of the static memory cell portion to the nonvolatile memory cell portion 2 before a power source V CC for the memory device is cut off and transferring the data from the nonvolatile memory cell portion 2 to the static memory cell portion 1 (recall) when the power source V CC is turned on. Assuming that predetermined data is written in the static memory cell portion 1, the node N₁ is at low level (V SS ), and the node N₂ is at high level (V CC ). Thus, when the data of the static memory cell portion 1 is transferred to the nonvolatile memory cell portion 2 in this state, a control power source voltage V HH is usually boosted from 0 V to between 20 and 30 V. Since the node N₁ is at low level, the transistor Q₅ is cut off, and, since an electrode D₁ of the capacitor module CM₁ is floating, the gate of the transistor Q₆ is boosted to a high voltage due to capacitive coupling by boosting the power source voltage V HH . Since a capacitance C (D₁ , D₂) between the electrodes D₁ and D₂ of the capacitor module CM₁ and a capacitance C (D₁ , D₃) between the electrodes D₁ and D₃ thereof are both sufficiently larger than the capacitances of the tunnel capacitors TC₁ and TC₂ , the gate voltage of the transistor Q₆ is boosted to a voltage close to the power source voltage V HH . A high voltage is then applied across the two ends of the tunnel capacitor TC₁. Electrons are injected into the floating gate of the transistor Q₆ from the power source V SS by the tunnel phenomenon, the floating gate is negatively charged, and the transistor Q₆ is cut off. This negative charge is held after the power sources V CC and V HH of the memory device are cut off, thereby achieving nonvolatile data storage. In contrast to this, when the node N₁ of the static memory cell portion 1 is at high level and the node N₂ thereof is at low level, the transistor Q₅ is ON. Therefore, when the power source voltage V HH is boosted to, for example, 20 to 30 V, the electrode D₁ of the capacitor module CM₁ is kept at low level. A high voltage is then applied across the two ends of the tunnel capacitor TC₂. The tunnel phenomenon causes the electrons to be extracted from the side of the floating gate of the transistor Q₆ to the side of the power source V HH . Thus, the floating gate is positively charged. For example, the operation for transferring the data of the nonvolatile memory cell portion 2 to the volatile memory cell portion 1 upon power source on will be described below. First, of the power source voltages V CC and V HH at 0 V (= V SS ), the power source voltage V CC alone is boosted to, for example, 5 V. If electrons are stored in the floating gate of the transistor Q₆ , the transistor Q₆ is cut off, and the conduction between the capacitor C₂ and the node N₂ is also cut off. Since the node N₁ is connected to the capacitor C₁ , the flip-flop circuit of the volatile memory cell portion 1 is set so that the node N₁ having a larger load capacitance is at low level and the node N₂ is at high level when the power source voltage V CC is boosted. However, if the electrons are extracted from the floating gate of the transistor Q₆ and a positive charge is stored in the floating gate, the transistor Q₆ is turned on and the node N₂ and the capacitor C₂ are connected to each other. Since the capacitance of the capacitor C₂ is sufficiently larger than that of the capacitor C₁ , the flip-flop circuit of the volatile memory cell portion 1 is set so that the node N₂ is set at low level and the node N₁ is set at high level when the power source voltage V CC is boosted. In this manner, the data is set in the volatile memory cell portion 1 in accordance with the charge stored in the floating gate of the transistor Q₆. When the circuit shown in Fig. 1 is used, a nonvolatile memory device can be realized. However, in the conventional circuit shown in Fig. 1, two tunnel capacitors are used. In a tunnel capacitor, the thickness of the insulating film and the film quality must be controlled with high precision. Therefore, the manufacturing yield of the memory device is lowered. The preferred embodiments of the present invention will be now described with reference to the accompanying drawings. Figure 2 shows an example of a memory cell used in a semiconductor memory device according to a first embodiment of the present invention. The memory cell has a volatile memory cell portion 1 the same as that in Fig. 1, and a nonvolatile memory cell portion 3 different from that shown in Fig. 1. The nonvolatile memory cell portion 3 comprises MIS transistors Q₅ , Q₆ , and Q₇ , a capacitor module CM₂ , and capacitors C₁ , C₂ , C₃ , and C₄. The capacitor C₄ and the transistor Q₇ are included in a first write circuit, and the capacitor C₃ and transistor Q₅ are included in a second write circuit. The transistor Q₇ operates as a first switch means and the transistor Q₅ operates as a second switch means. The capacitor module CM₂ is formed by two electrodes D₄ and D₆ located both sides of an electrode D₅ through insulating films (not shown). The insulating film between the electrodes D₄ and D₅ is all or partially thin, having a thickness of, for example, 100 to 200 Å, and a tunnel capacitor is formed between the electrodes D₄ and D₅. The capacitance of the capacitor C₂ is larger than that of the capacitor C₁. The capacitances of the capacitors C₃ and C₄ and a capacitance C (D₅ , D₆) between the electrodes D₅ and D₆ of the capacitor module CM₂ are sufficiently larger than a capacitance C (D₄ , D₅) between the electrodes D₄ and D₅ of the capacitor module CM₂. In the circuit shown in Fig. 2, an operation for transferring the data in the static memory cell portion 1 to the nonvolatile memory cell portion 3 will be described. Assuming that a flip-flop circuit of the static memory cell portion 1 is set so that a node N₁ is at low level and a node N₂ is at high level, therefore, in this state, a high-voltage control power sources voltage V HH is boosted from V SS (e.g., 0 V) to between 20 and 30 V. At this time, since the node N₁ is at low level, the transistor Q₅ is cut off. Since the node N₂ is at high level, the transistor Q₇ is in an ON state. Therefore, the potential at the electrode D₄ of the capacitor module CM₂ is at low level, and a control power source voltage V HH is applied to the series circuit of the capacitor C₃ and the capacitor module CM₂. As described above, since the capacitance of the capacitor C₃ and that between the electrodes D₅ and D₆ of the capacitor module CM₂ are sufficiently larger than that between the electrodes D₄ and D₅ of the capacitor module CM₂ , most of the voltage of the power source V HH is applied to the capacitance between electrodes D₄ and D₅. Therefore, electrons are injected from the electrode D₄ to the electrode D₅ by the tunnel effect, a negative charge is stored in the floating gate of the transistor Q₆ , the transistor Q₆ is turned off, and the data save from the volatile memory cell portion 1 to the nonvolatile memory cell portion 3 is completed. When the node N₁ of the static memory cell portion 1 is at high level and the node N₂ is at low level, the transistor Q₅ is ON and the transistor Q₇ is OFF. Therefore, the power source voltage V HH is applied to the series circuit of the capacitor C₄ and the capacitor module CM₂. Due to the relationship between the capacitances of the respective capacitors, most of the voltage of the power source V HH is applied between the electrodes D₄ and D₅ of the capacitor module CM₂. In this case, unlike the case described above, a voltage is applied having a polarity such that the side of the electrode D₄ is higher in potential than the side of the electrode D₅. Therefore, the electrons of the floating gate circuit of the transistor Q₆ are extracted to the side of the electrode D₄ by the tunnel effect. Thus, the floating gate circuit is positively charged, the transistor Q₆ is turned on, and data save from the volatile memory cell portion 1 to the nonvolatile memory cell portion 3 is completed. The operation for transferring the data in the nonvolatile memory cell portion 3 to the volatile memory cell portion 1 will be described. First, as in the circuit shown in Fig. 1, of the power source voltages V CC and V HH , only the power source voltage V CC is boosted from 0 V to, for example, 5 V. At this time, if the floating gate circuit of the transistor Q₆ is negatively charged, the capacitor C₂ and the node N₂ are disconnected through the transistor Q₆. Since the node N₁ is connected to the capacitor C₁ , when the power source voltage V CC is boosted, the flip-flop circuit of the volatile memory cell portion 1 is set so that the side of the node N₁ having a larger load capacitance is at low level and the side of the node N₂ is at high level. However, if electrons are extracted from the floating gate of the transistor Q₆ and the floating gate is positively charged, the transistor Q₆ is turned on and the node N₂ and the capacitor C₂ are connected to each other. As described above, since the capacitance of the capacitor C₂ is larger than that of the capacitor C₁ , the flip-flop circuit of the volatile memory cell portion 1 is set so that the node N₂ is set at low level and the node N₁ is set at high level when the power source voltage V CC is boosted. In this manner, data corresponding to the charge on the floating gate of the transistor Q₆ is set in the volatile memory cell portion 1, thereby returning the data from the nonvolatile memory cell portion 3 to the volatile memory cell portion 1. In the circuit shown in Fig. 2, since only a single tunnel capacitor is used, the manufacturing yield of the memory devices can be improved as compared to the conventional device. Figure 3 shows the circuit configuration of a memory cell of a semiconductor memory device according to a second embodiment of the present invention. The memory cell shown in Fig. 3 is electrically equivalent to that shown in Fig. 2. However, the memory cell shown in Fig. 3 has two capacitor modules CM₁ and CM₃. The capacitor module CM₁ has three electrodes D₁ , D₂ , and D₃; of which the electrodes D₁ and D₂ constitute a capacitor C₃ shown in Fig. 2, and electrodes D₁ and D₃ constitute a capacitor corresponding to the capacitor constituted by the electrodes D₅ and D₆ of the capacitor module CM₂ shown in Fig. 2. The capacitor module CM₃ has three electrodes D₇ , D₈ , and D₉ , of which the electrodes D₇ and D₈ constitute a capacitor corresponding to the capacitor C₄ shown in Fig. 2, and the electrodes D₈ and D₉ constitute a tunnel capacitor correponding to the tunnel capacitor constituted by the electrode D₄ and D₅ shown in Fig. 2. However, in the memory cell shown in Fig. 2, the capacitor module CM₂ must be formed of a conductive layer such as polycrystalline silicon (poly-Si) having a bilayered structure formed on a semiconductor substrate. However, in the memory cell shown in Fig. 3, the capacitor modules CM₁ and CM₃ can both be made of a single conductive layer. Therefore, the element structure can be rendered simpler. The other construction and operation of the cell shown in Fig. 3 are the same as those of the cell shown in Fig. 2 and will not be described. Figure 4 shows the circuit configuration of a memory cell of a semiconductor memory device according to a third embodiment of the present invention. In the memory cell shown in Fig. 4, the capacitor C₂ of the memory cell shown in Fig. 3 is omitted, and a recall transistor Q₈ is inserted between a node N₂ of a volatile memory cell portion 1 and the drain of a transistor Q₆. The remaining portions of the cell shown in Fig. 4 are the same as those of the cell shown in Fig. 3, and are designated by the same reference numerals. In the circuit shown in Fig. 4, the transistor Q₈ is turned on for a short period of time when data of a nonvolatile memory cell portion 5 is transferred to the volatile memory cell portion 1. A recall voltage V RC is applied to the gate of the transistor Q₈ when a power source V CC is turned on. When data is transferred from the nonvolatile memory cell portion 5 to the volatile memory cell portion 1, if the floating gate circuit of the transistor Q₆ is positively charged and the transistor Q₆ is turned on, the transistor Q₈ is turned on for a short period of time to maintain the voltage of node N₂ at 0 V (= V SS ). With this operation, without using the recall capacitor C₂ , the data of the nonvolatile memory cell portion can be transferred to the volatile memory cell portion 1, and the area of the memory cells on a semiconductor substrate can be reduced to a minimum. In the memory cell shown in Fig. 4, when the recall transistor Q₈ is cut off, the drain voltage of the transistor Q₆ is at low level (V SS ). Therefore, hot electrons will not be injected from the drain to the gate, and fluctuations in the charge amount of the floating gate circuit are prevented, so that data can be held stably for a long period of time. Figure 5 shows the circuit configuration of a memory cell of a semiconductor memory device according to a fourth embodiment of the present invention. The memory cell shown in Fig. 5 is obtained by loading a recall capacitor C₂ to the memory cell shown in Fig. 4. The remaining portions of the cell shown in Fig. 5 are the same as those of the cell shown in Fig. 4 and are designated by the same reference numerals. In the memory cell shown in Fig. 5, the recall capacitor C₂ and a recall transistor Q₈ are both used. Therefore, the area in the nonvolatile memory cell portion cannot be reduced. However, since the recall transistor Q₈ is used, fluctuations in the amount of charge on the floating gate of the transistor Q₆ are reduced as in the cell shown in Fig. 4, and data can be stably held for a long period of time. Figure 6 shows the circuit configuration of a memory cell of a semiconductor memory device according to a fifth embodiment of the present invention. The memory cell shown in Fig. 6 has a volatile memory cell portion 1 and a nonvolatile memory cell portion 7, and the volatile memory cell portion 1 is the same as that in each embodiment described above. The nonvolatile memory portion 7 has enhancement-type MIS transistors Q₅ , Q₆ , and Q₇ , depletion-type or enhancement-type transistors Q₉ and Q₁₀ , capacitors C₁ , C₂ , C₅ , C₆ , and C₇ , and a single tunnel capacitor TC₃. In the circuit shown in Fig. 6, when data is saved from the volatile memory cell portion 1 to the nonvolatile memory cell portion 7, a high-voltage control power source voltage V HH is boosted to a high level. If a node N₁ of the volatile memory cell portion 1 is at high level and a node N₂ is at low level, the transistor Q₅ is ON and the transistor Q₇ is OFF. Therefore, if the power source voltage V HH is boosted, the gate voltage of the transistor Q₉ is not boosted but the gate voltage of the transistor Q₁₀ is temporarily boosted by the operation of the capacitor 7. Therefore, the potential at an electrode D₁₀ of the tunnel capacitor TC₃ is boosted to be closer to the voltage of the power source V HH . However, since the gate voltage of the transistor Q₉ is not boosted, the potential at an electrode D₁₁ of the capacitor C₆ receives only a small boost. Therefore, although a voltage close to the power source voltage V HH is applied to the series circuit having the tunnel capacitor TC₃ , it is mostly applied to the tunnel capacitor TC₃ since the capacitance of the capacitor C₆ is sufficiently larger than that of the tunnel capacitor TC₃ and the capacitor C₇. Therefore, electrons are extracted from the side of the floating gate circuit of the tunnel capacitor TC₃ toward the side of the electrode D₁₀ , and the floating gate circuit is positively charged. In contrast to this, when the node N₁ of the volatile memory cell portion 1 is at low level and the node N₂ is at high level, the transistor Q₇ is turned on and the transistor Q₅ is turned off. Therefore, in accordance with a similar operation to that described above, a voltage close to the power source voltage V HH is applied to the side of an electrode D₁₁ of the capacitor C₆ , and a low level voltage (e.g., 1 to 2 V when the transistors Q₉ and Q₁₀ are depletion type) only is applied to the side of the electrode D₁₀ of the tunnel capacitor TC₃. The electrons are then injected from the side of the electrode D₁₀ of the tunnel capacitor TC₃ to the floating gate circuit side. Since the operation for transferring data from the nonvolatile memory cell portion 7 to the volatile memory cell portion 1 is the same as in the earlier embodiments, it will not be described. When the transistors Q₉ and Q₁₀ are depletion-type, the circuit configuration shown in Fig. 7 can be adopted. Fig. 8 shows the circuit configuration of a memory cell of a semiconductor memory device according to a sixth embodiment of the present invention. A nonvolatile memory cell portion 10 of the memory cell shown in Fig. 8 has MIS transistors Q₆, Q₁₅ and Q₁₆, capacitors C₁, C₂, C₁₂ and C₁₃ and a capacitor module CM₄. As in the case of the capacitor module CM₂ in Fig. 2, the capacitor module CM₄ has a tunnel capacitor between electrodes D₁₂ and D₁₃ and a normal capacitor between electrodes D₁₃ and D₁₄. In the memory cell shown in Fig. 8, when data is saved from the volatile memory cell portion 1 to the nonvolatile memory cell portion 10, it is assumed that a node N₁ is at high level and a node N₂ is at low level. Then, when a high-voltage control power source V HH is boosted to a high level under the application of a power source voltage V CC , the side of the electrode D₁₂ of the capacitor module CM₄ is boosted to a high level voltage by capacitor 12, while the electrode D₁₄ is held at low level. Then, electrons are extracted from the electrode D₁₃ to the electrode D₁₂ , and the floating gate circuit of the transistor Q₆ is positively charged. However, when the node N₁ is at low level and the node N₂ is at high level, electrons are injected from the electrode D₁₂ to the electrode D₁₃ , and the floating gate circuit is negatively charged. The mode of operation for transferring the data from the nonvolatile memory cell portion 10 to the volatile memory cell portion 1 can be easily deduced from the description of the earlier embodiments, and will not be described. A memory cell of a semiconductor memory device according to a seventh embodiment of the present invention is shown in Fig. 9. The memory cell has a volatile dynamic memory cell 11 and a nonvolatile memory cell portion 12. The volatile dynamic memory cell 11 consists of a transfer transistor Q₂₁ and another transistor Q C . The gate capacitance of the transistor Q C constitutes a capacitor portion of this memory cell, so that data is stored in this capacitor portion of the volatile dynamic memory cell 11. A separate capacitor can be alternatively provided in place of the capacitor portion, as indicated by a dotted line. The drain of the transistor Q₂₁ is connected to a bit line BL, and the source thereof is connected to the gate of the transistor Q C . The gate of the transistor Q₂₁ is connected to a word line WL. The source of the transistor Q C is connected to a power source V SS (normally at 0 V). A connecting point of the source of the transistor Q₂₁ and the gate of the transistor Q C is designated as a node N₂₁. The nonvolatile memory cell portion 12 has a transistor Q₂₂ , a transistor Q₃₁ , a transistor Q₂₃ , a capacitor C₃₁ , a tunnel capacitor TC₃₁ , and a capacitor module CM₃₁. The capacitor module CM₃₁ has three electrodes D₃₁ , D₃₂ , and D₃₃. capacitances exist in the module CM₃₁ between the electrodes D₃₁ and D₃₂ and between the electrodes D₃₁ and D₃₃. The drain of the transistor Q₂₂ is connected to a power source V CC (normally at +5 V)), the source thereof is connected to the drain of the transistor Q₂₃ , and the connecting point is designated as a node N₂₃. The voltage applied to the drain of the transistor Q₂₂ need not be of a fixed voltage such as the power source voltage V CC but need only be such that it is increased to the V CC level only during recall. The source of the transistor Q₂₃ is connected to the node N₂₁ of the volatile memory cell. One terminal of the capacitor C₃₁ receives a high-voltage control power source V HH for writing. The other terminal of the capacitor C₃₁ is connected to one electrode of the tunnel capacitor TC₃₁ and a connecting point thereof is designated as a node N₃₁. The capacitances of the capacitors included in the capacitor module CM₃₁ and the capacitor C₃₁ are selected to be sufficiently greater than that of the tunnel capacitor TC₃₁. The electrode D₃₁ of the capacitor module CM₃₁ is connected to the drain of the transistor Q C and to the gate of the transistor Q₃₁. The connecting point is designated as a node N₂₂. The electrode D₃₂ of the capacitor module CM₃₁ is connected to the high-voltage control power source V HH and the electrode D₃₃ thereof is connected to the other electrode of the tunnel capacitor TC₃₁ and to the gate of the transistor Q₂₂. The connecting point is designated as a node N₃₂. The drain of the transistor Q₃₁ is connected to the node N₃₁ and the source thereof is connected to a power source V SS (normally at 0 V). The gate of the transistor Q₂₃ receives a recall (RC) signal. The operation of the memory cell according to this embodiment of the present invention will now be described. The volatile dynamic memory cell 11 stores one-bit data by storing charges in the node N₂₁. First, a case will be described wherein the content of the memorized data in the volatile dynamic memory cell 11 is transferred to the nonvolatile memory cell portion 12. When the word line WL is at low level, the transistor Q₂₁ is cut off. When the node N₂₁ is charged and at high level, the transistor Q C is turned on (conductive) and the node N₂₂ is at low level. The transistor Q₃₁ is cut off and the node N₃₁ is in a floating state. When the high voltage V HH is boosted from 0 V to 25 V, the floating gate (node N₃₂) is at low level (about several volts) due to the capacitive coupling between the electrodes D₃₁ and D₃₃ of the capacitor module CM₃₁. The node N₃₁ is set at about 22 V by the capacitor C₃₁. In this manner, a potential difference of about 20 V is caused between the two electrodes of the tunnel capacitor TC₃₁. Since the thickness of an insulating film between the two electrodes of the tunnel capacitor is about 150 Å, an electric field stronger than 10 MV/cm is applied to the insulating film, thereby causing the tunnel effect. By this tunnel effect, electrons are injected from the node N₃₂ to the node N₃₁ and the high voltage V HH is removed, so that the node N₃₂ is positively charged. When the node N₂₁ is at low level, the transistor Q C is cut off and the node N₂₂ is in a floating state. When the high voltage V HH is boosted from 0 V to 25 V under this state, the node N₂₂ is set at about 22 V due to the electrostatic capacitive coupling between the electrodes D₃₁ and D₃₂ of the capacitor module CM₃₁. As a result, the transistor Q₃₁ is turned on and the node N₃₁ is at low level (0 V). Furthermore, due to the electrostatic capacitive coupling between the electrodes D₃₁ and D₃₃ of the capacitor module CM₃₁ , the floating gate (node N₃₂) is set at about 20 V. As a result, a potential difference of about 20 V is applied across the two electrodes of the tunnel capacitor TC₃₁ and the electrons are injected from the node N₃₁ to the node N₃₂ by the tunnel effect. When the high voltage V HH is removed, the node N₃₂ is negatively charged. In this manner, even if the power supply is cut off, the stored positive or negative charges are held for a long period of time, so that they can be utilized for the nonvolatile memory. The data stored in the nonvolatile memory cell portion 12 is transferred to the volatile memory cell in the following manner. When a recall RC signal is set at high level and is supplied to the gate of the transistor Q₂₃ , the transistor Q₂₃ is turned on. When the node N₃₂ is positively charged, the transistor Q₂₂ also is turned on, and a current is supplied from the power source V CC to the node N₂₁ , thereby charging the capacitor constituted by the transistor Q C . When the node N₃₂ is negatively charged, since the transistor Q₂₂ is cut off, the node N₂₁ is not conductive, so that the transistor Q C is not charged. During recall, the volatile memory cell 11 is initially set at low level, and the word line WL is also set at low level. Figure 10 shows a circuit diagram of a memory cell as a modification of the present embodiment. In the circuit, a transistor Q₃₂ is arranged between the node N₂₂ and the transistor Q C of the circuit shown in Fig. 9 and the power source voltage V CC is applied to the gate thereof. The voltage to be applied to the gate is not a fixed voltage but need only be a signal which goes to a level V CC only when transferring data from the volatile dynamic memory cell to the nonvolatile memory cell. With this configuration, the voltage applied to the drain of the transistor Q C is limited by the transistor Q₃₂ and the effect of the capacitive coupling between the drain and the gate of the transistor Q C , which would cause an undesirable voltage rise at the gate with a voltage rise at the drain, can be reduced, thereby reducing adverse effects (probability of an erroneous operation) on the dynamic memory cell. The drain voltage of the transistor Q C is suppressed at V CC - V th by the transistor Q₃₂. Figure 11 is a circuit diagram of a memory cell of a semiconductor memory device according to an eighth embodiment of the present invention. The memory cell of this type has a volatile static memory cell portion 1 and a nonvolatile memory cell portion 13. The volatile static memory cell portion 1 is the same as the conventional static memory cell including a flip-flop circuit, and a detailed description thereof is omitted. The flip-flop circuit stores one-bit data in accordance with whether the two connecting points cross-coupled to each other, i.e., a node N₁ connected to the drain of a transistor Q₁ and a node N₂ connected to the drain of a second transistor Q₂ , are at high or low level. One of the nodes N₁ and N₂ is at low level when the other is at high level. The nonvolatile memory cell portion 13 has a transistor Q₄₁ , a transistor Q₄₂ , a capacitor C₄₂ , a capacitor C₄₃ , a capacitor TC₄₁ as a floating gate circuit element, a capacitor C₄₁ , a transistor Q₄₃ , a capacitor C₄₄ , and a capacitor C₄₅. The capacitor C₄₁ and the transistor Q₄₁ are included in the first write circuit, and the capacitor C₄₃ and the transistor Q₄₂ are included in the second write-circuit. The capacitors C₄₂ and C₄₃ have a common electrode. The capacitances of the capacitors C₄₁ , C₄₂ , and C₄₃ are selected to be sufficiently larger than that of the tunnel capacitor TC₄₁. The capacitance of the capacitor C₄₅ is selected to be larger than that of the capacitor C₄₄. The node N₁ of the flip-flop of the volatile static memory cell portion 1 is connected to the gate of the transistor Q₄₁ and the drain of the transistor Q₄₃. The source of the transistor Q₄₃ is connected to a power source V SS (normally grounded at 0 V) through the capacitor C₄₅. The node N₂ of the volatile static memory cell portion 1 is connected to the power source V SS through the capacitor C₄₄. One electrode of the capacitor C₄₁ is connected to the power source V SS through the transistor Q₄₁ and is connected to one electrode of the tunnel capacitor TC₄₁ and the gate of the transistor Q₄₂. A voltage from a high voltage control power source V HH is applied to the other electrode of the capacitor C₄₁ and the other electrode of the capacitor C₄₃. One electrode of each of the capacitors C₄₂ and C₄₃ is a common electrode and is connected to the power source V SS through the transistor Q₄₂. The other electrode of the tunnel capacitor TC₄₁ is connected to the other electrode of the capacitor C₄₂ and the gate of the transistor Q₄₃. The operation of the memory cell described above will be described. The data in the volatile memory cell portion 1 is transferred to the nonvolatile memory cell portion 13 in the following menner. When the node N₁ of the flip-flop of the volatile static memory cell 1 is at high level, the transistor Q₄₁ is turned on. Therefore, one electrode of the capacitor C₄₁ ,one electrode of the tunnel capacitor TC₄₁ , and the gate of the transistor Q₄₂ are at a low level substantially equal to the voltage of the power source V SS , since they are connected to the drain of the transistor Q₄₁ (the connecting point thereof is designated as a node N₄₁). The transistor Q₄₂ is therefore turned off. At this time, when the power source voltage V HH is boosted from 0 V up to about 20 V, a voltage of about 20 V is applied to a series circuit of the capacitors C₄₃ , C₄₂ and the tunnel capacitor TC₄₁. Due to the relationship of the capacitances of the series-connected capacitors, most of this voltage of about 20 V is applied between the two electrodes of the tunnel capacitor TC₄₁. When the voltage of about 20 V is applied between the two electrodes of the tunnel capacitor TC₄₁ , an electric field stronger than 10 MV/cm is applied to an insulating film of about 150 Å of the tunnel capacitor, so that the tunnel effect is caused, and the electrons are injected from the node N₄₁ to the gate circuit (to be referred to as a node FG₄₁) of the transistor Q₄₃. In other words, the gate circuit of the transistor Q₄₃ is negatively charged. This state is held for a long period of time after the power source is cut off. When the node N₁ is at low level, the transistor Q₄₁ is turned off and the node N₄₁ is in a floating state. When the power source V HH is boosted from 0 up to about 20 V, the voltage of the node N₄₁ becomes about 20 V due to the capacitive coupling of the capacitor C₄₁. Therefore, the transistor Q₄₂ is turned on, and the drain of the transistor Q₄₂ and one electrode of each of the capacitors C₄₂ and C₄₃ connected thereto are at about 0 V. As a result, the voltage of about 20 V is applied to the series circuit of the capacitor C₄₁ , the tunnel capacitor TC₄₁ , and the capacitor C₄₂. From the relationship of the capacitances of these capacitors, most of the voltage of about 20 V is applied between the two electrodes of the tunnel capacitor TC₄₁. The electrons are injected from the node FG₄₁ to the node N₁₁ by the tunnel effect so that the node FG₄₁ is positively charged. This state is held for a long period of time after the power source is cut off. When the node FG₄₁ is positively charged, the transistor Q₄₃ is turned on. When the node FG₄₁ is negatively charged, the transistor Q₄₃ is turned off. The operation for transferring the data stored in the nonvolatile memory cell portion 13 (corresponding to the charging state of the node FG₄₁) to the volatile memory cell portion 1 will be described. When the power source voltage V CC is boosted from 0 V to 5 V, if the node FG₄₁ is positively charged, the node N₁ of the flip-flop is set at low level since the transistor Q₄₃ is turned on and the capacitor C₄₅ is connected to the node N₁. In other words, since the capacitance of the capacitor C₄₅ is larger than that of the capacitor C₄₄ , the node N₁ is set at low level because the load capacitance of the node N₁ is great. If the node FG₄₁ is negatively charged, since the transistor Q₄₃ is turned off and the capacitor C₄₅ is disconnected from the node N₁ , the node N₁ of the flip-flop is set at high level. That is, the load capacitance of the node N₂ to which the capacitor C₄₄ is connected is large, so that the node N₂ is set at low level, thereby setting the node N₁ at high level. Figure 12 is a circuit diagram of a memory cell of a semiconductor memory device according to a ninth embodiment of the present invention. The memory cell of this embodiment has a volatile static memory cell portion 1 and a nonvolatile memory cell portion 14. The volatile static memory cell portion 1 is the same as that in the first embodiment. The nonvolatile memory cell portion 14 is different from that in the eighth embodiment in that a transistor Q₄₄ is provided at a side of a node N₁ of a transistor Q₄₃ in place of the capacitor C₄₅. An array recall signal V RC is supplied to the gate of the transistor Q₄₄. The array recall signal V RC goes high for a short period of time in synchronism with a timing of the boost of a power source voltage V CC from 0 to 5 V when the data is transferred from the nonvolatile memory cell portion 14 to the volatile memory cell portion 1. The operation of the ninth embodiment will be described. The operation for transferring the data from the volatile static memory cell portion 1 to the nonvolatile memory cell portion 14 is the same as that described in the eighth embodiment and a detailed description thereof is omitted. The same reference numerals and symbols as in Fig. 11 are used to denote the same or equivalent elements of the memory cell. The data is transferred from the nonvolatile memory cell portion 14 to the volatile static memory cell portion 1 in the following manner. When a node FG₄₁ is positively charged, the transistor Q₄₃ is ON. When the power source voltage V CC is boosted from 0 to 5 V and the signal V RC is at high level for a short period of time, the transistor Q₄₄ is turned on and the node N₁ is set at a level of a power source voltage V SS for a short period of time, so that the node N₁ of the flip-flop is set at low level. When the node FG₄₁ is negatively charged, the transistor Q₄₃ is turned off. The node N₁ is floating from the power source V SS irrespective of the state of the transistor Q₄₄. Meanwhile, since a capacitor C₄₄ is connected to a node N₂ , when the power source voltage V CC is boosted from 0 to 5 V, the node N₂ is set at low level and the node N₁ is set at high level. According to this embodiment, the data in the nonvolatile memory cell portion can be transferred to the volatile memory cell portion without using the capacitor C₄₅ , thereby decreasing the occupying area of the substrate per memory cell. In addition, since the drain voltage of the transistor Q₄₃ goes low when the transistor Q₄₄ is cut off, hot electrons will not be injected from the drain to the gate thereof, and variations in the charge amount of the floating gate circuit are prevented, thereby stably holding the data for a long period of time. According to the present embodiment, a memory cell can be formed by using only data in one of the cross-coupled nodes of a volatile static memory cell, so that the layout can be discretionarily determined when the memory cells are integrated, thereby decreasing the area of the substrate occupied by each memory cell. Figure 13 shows a memory cell of a semiconductor memory device according to a tenth embodiment of the present invention. This memory cell has a volatile static memory cell portion 1 and a nonvolatile memory cell portion 15. The voltage static memory cell portion 1 is the same as the conventional static memory cell using the transistors Q₁ and Q₂ , and the like, and a detailed description thereof is omitted. The nonvolatile memory cell portion 15 is almost the same as the nonvolatile memory cell portion 3 shown in Fig. 2, except that the gate of a transistor Q₅₇ is not connected to a node N₂ of the volatile static memory cell portion 1 but to a transistor Q₅₉. The nonvolatile memory cell portion 15 has MIS transistors Q₅₉ , Q₅₇ , and Q₅₈ , a capacitor module CM₅₂ , capacitors C₅₃ , C₅₄ , and C₅₅ , and a tunnel capacitor TC₅₃. The capacitor module CM₅₂ has capacitances between an electrode D₅₄ and each of other electrodes D₅₅ and D₅₆ , respectively. The capacitance of the tunnel capacitor TC₅₃ is selected to be sufficiently smaller than the capacitance between the electrodes of the capacitor module and the capacitance of the capacitor C₅₅. A node N₁ of the volatile static memory cell portion 1 is connected to the capacitor C₅₃ and to the gate of the transistor Q₅₉. The other terminal of the capacitor C₅₃ is connected to a power source V SS (0 V = ground voltage). The drain of the transistor Q₅₉ is connected to the electrode D₅₄ of the capacitor module CM₅₂ and the source thereof is connected to the power source V SS . A write high-voltage control power source V HH is applied to the electrode D₅₅ of the capacitor module CM₅₂ and to the capacitor C₅₅ as needed. The node N₂ of the volatile static memory cell portion 1 is connected to the drain of the transistor Q₅₈ as the floating transistor, the source of the transistor Q₅₈ is connected to one terminal of the capacitor C₅₄ , and the gate of the transistor Q₅₈ is connected to the electrode D₅₆ of the capacitor module CM₅₂. The other terminal of the capacitor C₅₄ is connected to the power source V SS . The gate of the transistor Q₅₇ is connected to the electrode D₅₄ of the capacitor module CM₅₂ , the source thereof is connected to the power source V SS , and the drain thereof is connected to a node N₅₄ which is a connecting point of the capacitor C₅₅ and the tunnel capacitor TC₅₃. One electrode of the tunnel capacitor TC₅₃ is connected to the gate of the transistor Q₅₈ , that is, to a node FG (FG₅₀). The node connected to the electrode D₅₄ of the capacitor module CM₅₂ will be referred to as node N₅₃. In the memory cell shown in Fig. 13, an operation for transferring the data in the volatile static memory cell portion 1 to the nonvolatile memory cell portion 15 will be described. Assume that the node N₁ is at low level, and the node N₂ is at high level. In this atate, the power source voltage V HH is boosted from 0 V to between 20 V and 30 V. At this time, since the node N₁ is at low level, the transistor Q₅₉ is cut off. Although the node N₅₃ is floating, when the power source voltage V HH is boosted from 0 V to between 20 and 30 V, the node N₅₃ is set at high level by the capacitive coupling. Therefore, the transistor Q₅₇ is turned on, the node N₅₄ is set at low level, and the power source voltage V HH is applied to a series circuit of the capacitance between the electrodes D₅₄ and D₅₅ of the capacitor module CM₅₂ , the capacitance between the electrodes D₅₄ and D₅₆ thereof, and the capacitance of the tunnel capacitorTC₅₃. Since the capacitance of the capacitor module CM₅₂ is sufficiently larger than that of the tunnel capacitor TC₅₃ , as described above, most of the power source voltage V HH is applied to the tunnel capacitor TC₅₃. When the voltage of about 20 V is applied to the tunnel capacitor, an electric field of more than 10 MV/cm is applied to the insulating film having a thickness of about 150 Å, thereby causing the tunnel effect. Electrons are injected to the node FG by the tunnel effect, so that the floating gate circuit of the transistor Q₅₈ is negatively charged, the transistor Q₅₈ is turned off, and the saving of the data from the volatile static memory cell portion 1 to the nonvolatile memory cell portion 15 is completed. When the node N₁ of the volatile static memory cell portion 1 is at high level and the node N₂ thereof is at low level, the transistor Q₅₉ is turned on and the node N₅₃ is set at low level, thereby cutting off the transistor Q₅₇. Therefore, the power source voltage V HH (about 20 V) is applied to the series circuit of the capacitances of the capacitor C₅₅ and the tunnel capacitor TC₅₃ , and between the electrodes D₅₄ and D₅₆ of the capacitor module CM₅₂ , so that most of the voltage V HH is applied to the tunnel capacitor TC₅₃ due to the relationship of the capacitances of the capacitors. In this case, since the node N₅₄ is higher in potential level than the node FG, the electrons are extracted from the floating gate of the transistor Q₅₈ to the node N₅₄ by the tunnel effect. As a result, the node FG is positively charged and the transistor Q₅₈ is turned on, and saving of the data from the volatile static memory cell portion 1 to the nonvolatile memory cell portion 15 is completed. An operation for transferring the data from the nonvolatile memory cell portion 15 to the volatile static memory cell portion 1 will be described. First, of the power source voltages V CC and V HH at 0 V, only the voltage V CC is boosted to 5 V. If the node FG is negatively charged, the transistor Q₅₈ is cut off and the node N₂ and the capacitor C₅₄ are then cut off from each other. Since the node N₁ is connected to the capacitor C₅₃ , the flip-flop circuit is set so that the node N₁ having a larger load capacitance is set at low level and the node N₂ is set at high level when the power source voltage V CC is boosted. However, if the electrons are extracted from the floating gate of the transistor Q₅₈ and a positive charge is stored in the floating gate, the transistor Q₅₈ is turned on, and the node N₂ and the capacitor C₅₄ are connected to each other. Since the capacitance of the capacitor C₅₄ is selected to be larger than that of the capacitor C₅₃ , the flip-flop circuit of the volatile static memory cell portion 1 is set so that the node N₂ is set at low level and the node N₁ is set at high level when the power source voltage V CC is boosted. Figures 14 and 15 show modifications of this embodiment. Figures 14 and 15 show circuit portions in the vicinity of the transistor Q₅₈ of the nonvolatile memory cell portion 15 of Fig. 13. When the circuit shown in Fig. 14 is compared with that shown in Fig. 13 a transistor Q₅₀ is inserted between the node N₂ and the transistor Q₅₈ and is turned on/off in accordance with an array recall signal V RC . The array recall signal goes high only for a short period of time when the data in the nonvolatile memory cell portion 15 is transferred to the volatile memory cell portion 1. When the data in the nonvolatile memory cell portion 15 is transferred to the volatile memory cell portion 1 in this manner, if the floating gate of the transistor Q₅₈ is positively charged and the transistor Q₅₈ is turned on, the transistor Q₅₀ is turned on for a short period of time to decrease the voltage applied to the node N₂. By this operation, the recall capacitor C₅₄ can be omitted as in the modification shown in Fig. 15 As a result, the area occupied in the semiconductor substrate by each memory cell can be decreased. In addition, since the drain voltage of the transistor Q₅₈ is at low level when the transistor Q₅₀ is cut off, hot electrons will not be injected from the drain to the gate thereof, so that variations in the charge amount of the floating gate circuit may be prevented, thereby stably holding the data for a long period of time. According to the present embodiment, the design of the layout of the device can be performed at the manufacturer's discretion. An eleventh embodiment of the present invention will be described with reference to Figs. 5, 16 and 17. The constitution of the circuit elements of this embodiment is the same as that of the fourth embodiment. Fig. 16 is a circuit diagram explaining the principle of the present embodiment. Referring to Fig. 16, memorized data in a nonvolatile memory is transferred to a volatile memory portion upon on/off operation between nodes N₁₀₃ and N₁₀₄ when a floating gate section FG is charged. This nonvolatile data is obtained by the application of a high voltage across the electrodes of a tunnel capacitor (formed by CM₃) to inject electrons. Electron injection to the floating gate FG or electron extraction therefrom is determined by whether or not a high voltage is applied to a node N₁₀₁ or N₁₀₂ in accordance with the state of the volatile memory portion. The capacitance of the auxiliary capacitor is far larger than that of the tunnel capacitor. Capacitive coupling or a charge trapping technique is used to apply a high voltage or 0 V to the node N₁₀₁ or N₁₀₂ in such a manner that a high DC voltage current will not flow (a steady current flows for at least 0.1 ms). In this manner, the high voltage is applied to the node N₁₀₁ or N₁₀₂ a plurality of times. Figure 17 is a block diagram showing the overall configuration of a semiconductor memory device including a nonvolatile semiconductor device according to the eleventh embodiment of the present invention. Referring to Fig. 17, reference numeral 201 denotes a memory cell (area) whose memory cells 1 and 6 in Fig. 5 are arranged at intersections of the word lines WL and bit line pairs BL and BL . Reference numeral 202 denotes an address buffer for receiving an X address signal A i (i = 0 to n); 203, an X decoder; 204, an address buffer for receiving a Y address signal A i ' (i = 0 to n); 205, a Y decoder; 206, a Y gate for selectively connecting a sense amplifier 207 from the volatile memory cell 1 (SRAM) to the memory cell 201 and a write enable circuit for connecting the SRAM to the memory cell 201; 209, an output buffer for output data DO; and 210, an input buffer for input data DI. Reference numeral 211 denotes a mode select circuit for receiving a chip select signal CS , a write enable signal WE for the SRAM, a store signal ST for the EEPROM (E²PROM), and the array recall signal AR for the EEPROM, and for selecting an operation mode. More particularly, in the store mode (ST = "1"), the mode select circuit 211 simultaneously renders a booster 212, a timer 213 and a counter 214 in an operative state. The booster 212 generates the voltage V HH of 20 to 25 V by using an internal clock. This voltage is applied to the nonvolatile memory cell 6 (EEPROM cell). In this case, the timer 213 is operated for a predetermined period of time (e.g., 5 msec). When the predetermined period of time has elapsed, the internal clock in the booster 212 is stopped to temporarily set the voltage V HH at 0 V. Thereafter, the booster 212 applies the voltage V HH of 20 to 25 V to the EEPROM cell 6 again. Repeat of the above operation is controlled by the counter 214. For example, when the counter 214 repeats the counting operation twice, it generates a store reset signal as a count-up signal. The store reset signal is supplied to the mode select circuit 211. As a result, the data store operation from the SRAM cell to the EEPROM is completed. On the other hand, when the array recall signal AR is set at logic "1" (i.e., AR = "0"), a mode select recall circuit 215 is enabled. In this case, the array recall signal AR (V RC ) is supplied to the transistor Q₈ (Fig. 5) in the EEPROM cell 6, and the transistor Q₈ is turned on to drive a V CC switch 216. The V CC switch 216 temporarily decreases the voltage V CCC to 0 V and then increases the voltage V CCC to 5 V, thereby recalling the data from the EEPROM cell 6 to the SRAM cell 1. The thus controlled voltage V CCC is the power source voltage supplied to the SRAM cell 1, this is referred to as V CC in the preceeding figures for the sake of simplicity. In the above embodiment, in the store mode (i.e., in the write mode of the EEPROM cell), the power source voltage V HH is applied twice for each ON time of 5 msec. However, the ON time may change, and the number of voltage applications may be 3 or more. The memory modules CM₁ and CM₃ of the EEPROM cell 6 shown in Fig.5 (in one example of the fourth embodiment of the present invention) comprise a semiconductor substrate and a metal layer such as a poly-Si layer. The electrodes E₁ and E₄ comprise separate n-type impurity diffusion regions in a p⁻-type semiconductor substrate. The floating gate is capacitively coupled, i.e., through an insulating film, on the n-type impurity diffusion regions. The electrodes E₂ and E₅ are electrically connected to each other and are also capacitively coupled on the n-type impurity diffusion regions. Therefore, when the data is stored from the SRAM cell 1 to the EEPROM cell 6, substantially the same voltage as the voltage V HH is applied to one of the electrodes E₁ and E₄. In this case, electrons are injected from the substrate to the n-type impurity diffusion regions as an electrode. That is, the potential at the electrode E₁ or E₄ is lowered over a period of time due to junction leakage. As a result, the voltage across the electrodes E₄ and E₆ is lowered at the time of storage, thereby impairing tunnel efficiency and decreasing the memory efficiency of the EEPROM. In addition, since the electrons are mobile between the electrodes E₄ and E₆ , a voltage across the electrodes E₄ and E₆ is lowered. Figures 18 and 19 are graphs explaining the effect of the present embodiment. Referring to Figs. 18 and 19, V N3 and V N3 ' are potentials at the electrode E₄ when the transistor Q₆ shown in Fig. 5 is kept off. More specifically, the potential V N3 is obtained when the tunnel phenomenon does not occur between the electrodes E₄ and E₆ , while the potential V N3 ' is obtained when the tunnel phenomenon does occur. V F and V F ' are potentials at the floating gate. In the same manner as described above, the potential V F is obtained when the tunnel phenomenon does not occur between the electrodes E₄ and E₆ , while the potential V F ' is obtained when the tunnel phenomenon does occur between the electrodes E₄ and E₆. As previously described, when the tunnel phenomenon occurs, the potential at the electrode E₄ is decreased from the potential V N3 to V N3 ', while the potential at the floating gate increases from the potential V F to the potential V F ' by a component corresponding to a decrease in the potential at the electrode E₄. For example, an initial potential at the floating gate is -3 V, while a potential at the floating gate increases to +1.2 V after the voltage V HH (22 V) is applied for 10 msec, thereby indicating that data updating is performed. Figure 19 is a graph showing the results according to the present embodiment. The voltage V HH (22 V) is applied twice for each 5 msec. When the tunnel phenomenon occurs, the floating gate is set at a potential of about +1 V after the voltage V HH is applied for the first time. The floating gate is then set at a potential of +2.6 V after the voltage V HH is applied for the second time. As compared with the nonvolatile RAM having a potential of +1.2 V shown in Fig. 18, the potential at the floating gate is greatly improved. The effect also can be obtained of compensation for a decrease in V N3 due to junction leakage occurring at the time of writing in the EEPROM. Therefore, the degradation of the tunnel efficiency of the EEPROM can be prevented to improve the memory efficiency of the EEPROM. Figure 20 shows a pattern layout of the memory cell shown in Fig. 3 on the semiconductor substrate. Referring to Fig. 20, the depletion-type load transistors Q₃ and Q₄ of the volatile memory cell portion 1 are replaced with poly-Si load resistors R₁ and R₂. In Fig. 20, reference symbol F denotes a diffusion region such as a source or drain which is formed in the semiconductor substrate (not shown), reference symbols P₁ , P₂ and P₃ denote first, second and third conductive layers, i.e., poly-Si layers, the third conductive layer P₃ is indicated by a dotted line, and contact portions between the conductive layer P₃ and the remaining conductive layers are designated by reference symbols H₁ , H₂ , and so on. In the cell shown in Fig. 20, the load resistors R₁ and R₂ of the transistors Q₁ and Q₂ of the volatile memory cell portion 1 of the memory cell in Fig. 3 are formed by making a high-resistance conductive layer from conductive layer portions in the third layer extending from the power source V CC to the contact portions H₁ and H₂; the transistors Q₁ and Q₂ of the volatile memory cell portion and the transistors Q₅ and Q₇ of the non-volatile memory cell portion 4 are formed by the diffusion region F and the second conductive layer P₂; the transistor Q₆ is formed by the diffusion region F and the first conductive layer P₁; the capacitor module CM₁ is formed by the diffusion region F and the first and second conductive layrs P₁ and P₂; and the capacitor module CM₃ is formed of the diffusion region F and the first and second conductive layers P₁ and P₂. In the tunnel capacitor TC constituted by the electrodes D₈ and D₉ of the capacitor module CM₃ , the insulating film between the diffusion region F and the first conductive layer P₁ is as thin as 100 to 200 Å. Figure 21 shows a pattern layout of the memory cell shown in Fig. 4. In the layout shown in Fig. 21, the depletion-type load transistors Q₃ and Q₄ of the volatile memory cell portion 1 are replaced with load resistors R₁ and R₂ of poly-Si or the like. The respective conductive layers, the diffusion region, the contact portions, and the like are designated by the same reference numerals as those in Fig. 20 The remaining portions can be easily deduced from the description regarding Fig. 20 and a detailed description thereof will be omitted. In the layout shown in Fig. 21, since the recall capacitor C₂ is not included, the occupying area of the substrate per memory cell is smaller than the layout shown in Fig. 20. A semiconductor memory device in accordance with the present invention includes a nonvolatile random access memory cell constituted by a combination of a static random access memory cell (1) or a dynamic random access memory cell and a floating circuit element (D s , Q₆). In the device, the circuit constitution, the application of writing voltage (V HH ), and the like, are improved. Thus, the number of circuit elements, particularly the number of floating gate circuit elements (Q₆), is reduced. As a result, the cell area can be decreased, high integration of the device can be achieved, and the production yield of the device can be increased. In addition, improvement of the circuit configuration increases the discretion allowed in the layout design, and repeated application of the write voltage (V HH ) improves the storage efficiency.

Claims: A semiconductor memory device comprising a volatile memory cell (1, 11) and a nonvolatile memory cell (2, 5, 6, 7, 10, 12, 13, 14, 15) corresponding to the volatile memory cell, said nonvolatile memory cell comprising a transistor (Q₆, Q₂₂, Q₄₃ and Q₅₈) which has a floating gate and is operable to turn on or off in response to memorized data, a tunnel capacitor (CM₂, CM₃, TC₃, CM₄, TC₃₁, TC₄₁, TC₅₃), one electrode of which is connected to the floating gate, and a write circuit coupled to an electrode of the tunnel capacitor, said write circuit being operable to supply a high-voltage control power source (V HH ) to said tunnel capacitor in response to the memorised data of said volatile memory cell; characterised in that said write circuit comprises:- a first write circuit connected to the other electrode of said tunnel capacitor, comprising a first capacitor (C₄, CM₃, C₇, C'₇, C₁₂, C₃₁, C₄₁, C₅₅) connected between said high-voltage control power source (V HH ) and said tunnel capacitor, and a first switch means (Q₇, Q₁₇, Q₃₁, Q₄₁ and Q₅₇) connected between a power source (V SS ) and said tunnel capacitor, controlled by the voltage at a data output node of said volatile memory cell (1, 11); and a second write circuit connected to said electrode of the tunnel capacitor which is connected to the floating gate, comprising a second capacitor (C₃, CM₁, C₅, C'₅, CM₃₁, C₄₃, CM₅₂) connected between said high-voltage control power source (V HH ) and said tunnel capacitor, and a second switch means (Q₅, Q₁₆, Q₃₂, Q₄₂ and Q₅₉) connected between said power source (V SS ) and said tunnel capacitor, controlled by the voltage at another data output node of said volatile memory cell; whereby, in dependence upon the memorized data of said volatile memory cell (1, 11), one side of the tunnel capacitor is connected to said high-voltage control power source (V HH ) and the other side is connected to said power source (V SS ). A semiconductor memory device as set forth in claim 1, wherein said nonvolatile memory cell (3) further comprises a capacitor (C₂) for recalling, the source of said transistor (Q₆) having said floating gate in said nonvolatile memory cell is connected to said power source voltage (V SS ) through the capacitor (C₂) for recalling, and the drain of said transistor (Q6) is connected to a data input/output node (N₂) of said volatile memory cell (1). A semiconductor memory device as set forth in claim 1, wherein said nonvolatile memory cell (5) further comprises a transistor (Q₈) for recalling, and the drain of said transistor (Q₆) having said floating gate is connected to a data input/output node (N₂) of said volatile memory cell through said transistor (Q₈) for recalling. A semiconductor memory device as set forth in claim 3, wherein said transistor (Q₈) for recalling is turned on for a short period of time when data transfer is performed from said nonvolatile memory cell (5) to said volatile memory cell (1). A semiconductor memory device as set forth in claim 1, wherein said first write circuit comprises a first transistor (Q₁₀), and said first switch means (Q₇) controls the potential of the gate of said first transistor (Q₁₀) in response to the memorized data of said volatile memory cell (1); the other electrode of said tunnel capacitor (TC₃) is supplied with said high-voltage control power source (V HH ) through said first transistor (Q₁₀); said second write circuit comprises a second transistor (Q₉), and said second switch means (Q₅) controls the potential of the gate of said second transistor (Q₉) in response to the memorised data of said volatile memory cell (1); and said high-voltage control power source (V HH ) is capacitively coupled to said floating gate through said second transistor (Q₉). A semiconductor memory device as set forth in claim 1, wherein said volatile memory cell (1) comprises a capacitor portion for storing the amount of charge corresponding to data to be memorized, a transfer transistor (Q₂₁) for transferring data memorized in said capacitor portion to bit lines (BL), and another transistor (Q C ), the gate of which is connected to said capacitor portion and which turns on or off in response to data memorised in said capacitor portion. A semiconductor memory device as set forth in claim 6, wherein said second switch means includes a transistor and the gate capacitance of said other transistor (Q C ) is used as said capacitor portion of said volatile memory cell (1). A semiconductor memory device as set forth in any of claims 1 to 5, wherein said volatile memory cell (1) comprises two transistors (Q₁, Q₂) cross-connected to each other, the potentials of the gates of the two transistors are supplied to said nonvolatile memory cell (13) as an output of said volatile memory cell (1), and the output of said first switch means of said first write circuit is supplied to control said second switch means of said second write circuit. A semiconductor memory device as set forth in any of claims 1 to 5, wherein said volatile memory cell (1) comprises two transistors (Q₁, Q₂) cross-connected to each other, the potentials of the gates of said two transistors are supplied to said nonvolatile memory cell (15) as an output of said volatile memory cell (1), and the output of said second switch means (Q₅₉) of said second write circuit is supplied to control said first switch means (Q₅₇) of said first write circuit. A semiconductor memory device as set forth in any preceding claim, wherein said high-voltage control power source (V HH ) is applied to said first write circuit a plurality of times, and to said second write circuit a plurality of times. A semiconductor memory device as set forth in claim 1, wherein said first write circuit comprises:- a first transistor (Q₄₁) as said first switch means, a gate of the first transistor (Q₄₁) being connected to a node (N₁) of a flip-flop of the volatile memory cell (1), an electrode of the first transistor (Q₄₁) being connected to said high-voltage control power source (V HH ) through said first capacitor (C₄₁); said second write circuit comprises a second transistor (Q₄₂) as said second switch means, a gate of the second transistor (Q₄₂) being connected to the electrode of the first transistor (Q₄₁) of the first write circuit, an electrode of the second transistor (Q₄₂) being connected to the high-voltage control power source (V HH ) through said second capacitor (C₄₃); one electrode of said tunnel capacitor (TC₄₁) being said floating gate (FG₄₁) and the other electrode being connected to the gate of the second transistor (Q₄₂); and wherein said nonvolatile memory cell further comprises: a third capacitor (C₄₂), one electrode of the second and third capacitors (C₄₂, C₄₃) being a common electrode, another electrode of the third capacitor (C₄₂) being connected to the floating gate (FG₄₁); a fourth capacitor (C₄₅), the node (N₁) being connected to a power source (V SS ) through said memory cell transistor (Q₄₃) and the fourth capacitor (C₄₅), and a fifth capacitor (C₄₄) being connected between the power source (V SS ) and another node (N₂) of the volatile memory cell (1); the capacitances of the first, second and third capacitors (C₄₁, C₄₂ and C₄₃) being selected to be larger than that of the tunnel capacitor (TC₄₁), and the capacitance of the fourth capacitor (C₄₅) being selected to be larger than that of the fifth capacitor (C₄₄). A semiconductor memory device as set forth in claim 1, wherein said first write circuit comprises:- a first transistor (Q₄₁) as said first switch means, a gate of the first transistor (Q₄₁) being connected to a node (N₁) of a flip-flop of the volatile memory cell (1), an electrode of the first transistor (Q₄₁) being connected to said high-voltage control power source (V HH ) through said first capacitor (C₄₁); said second write circuit comprises a second transistor (Q₄₂) as said second switch means, a gate of the second transistor (Q₄₂) being connected to the electrode of the first transistor (Q₄₁) of the first write circuit, an electrode of the second transistor (Q₄₂) being connected to the high-voltage control power source (V HH ) through said second capacitor (C₄₃); one electrode of said tunnel capacitor (TC₄₁) being said floating gate (FG₄₁) and the other electrode being connected to the gate of the second transistor (Q₄₂); and wherein said nonvolatile memory cell further comprises: a third capacitor (C₄₂), one electrode of the second and third capacitors (C₄₂ and C₄₃) being a common electrode, another electrode of the third capacitor (C₄₂) being connected to the floating gate (FG₄₁); a third transistor (Q₄₄), the node (N₁) being connected to the power source (V SS ) through the memory cell transistor (Q₄₃); and a fourth capacitor (C₄₄), and a fifth capacitor (C₄₄) being connected between the power source (V SS ) and another node (N₂) of the volatile memory cell (1); the gate of the third transistor (Q₄₄) being supplied with an array recall signal (V RC ), and the capacitances of the first, second and third capacitors (C₄₁, C₄₂ and C₄₃) being selected to be larger than that of the tunnel capacitor (TC₄₁).

Inventors: ARAKAWA, HIDEKI
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: G11C14
IPC codes: G11C14