EXTENDED THRESHOLD ANALOG TO DIGITAL CONVERSION APPARATUS FOR AN RF RECEIVER

Abstract: A sample and hold circuit (10) receives a low level analog input signal and is gated by a clock (18). The output of the sample and hold circuit (10) is summed with a signal from a noise source (22) and the resulting signal coupled to an analog to digital (A/D) converter (24). The noise source (22) presents a bandwidth restricted signal having no substantial energy in the range of frequencies of the desired analog input signal. The clock (18) also drives the A/D convertor (24) which has a plurality of digital output signals (26) which correspond to varying analog signal levels. The resulting signal contains a signal component corresponding to the input signal which is converted into a digital representation by the A/D convertor (24) even though the magnitude of the input signal is less than the threshold sensitivity of the A/D convertor (24).

Description: EXTENDED THRESHOLD ANALOG TO DIGITAL CONVERSION APPARATUS FOR AN RF RECEIVER Background of the Invention This invention relates generally to the analog to digital (A/D) conversion by an A/D converter of analog signals having a magnitude less than the threshold sensitivity of the A/D converter. Threshold sensitivity refers to the lowest magnitude analog signal which will cause the A/D converter to change the digital state of its output. This invention is specifically, but not exclusively, adapted to convert low level radio frequency (RF) analog signals received by a communications receiver into digital signals wherein such digital signals are processed using digital rather than conventional analog techniques. In a conventional wireless receiver, the low level received signal is processed with analog circuits including conversion to an intermediate frequency, amplification, filtering, and then demodulated to extract the information carried by the signal. With the advancements in digital technology, especially in digital filters and in digital signal processors, many, if not all of the functions of a receiver can be implemented digitally. However, before any digital processing can occur, the normally low level analog signal presented to the receiver must be converted into digital form. OMPI The initial A/D conversion of the received signal presents several problems. In a land mobile system the magnitude of a received signal may be as low as 0.5 microvolts (uV) . This signal level is significantl lower than the threshold sensitivity available in a conventional A/D converter; for example, a commercially available 1 volt 14 bit A/D converter has a threshold wherein the least significant bit (LSB) in its output corresponds to an analog input voltage of 61 uV. A substantial range (0.5uV-60uV) of input signal levels which is useful in conventional analog receivers, would not be detected by such an A/D converter and could not be processed by digital signal processing. Of course, an amplifier could be utilized to amplify low level received signals prior to the A/D conversion. However, such an amplifier would likely give rise to severe intermodulation distortion in a land mobile re¬ ceiver and would itself provide an intermodulation limit. If a stronger signal is present concurrently with a low level desired signal, the A/D quantizing noise will have a narrow frequency spectrum and can result in severe intermodulation distortion. By converting a received RF analog signal into digital form, the A/D converter func¬ tions as a quantizer, that is, it functions to subdivide the analog signal into small but measurable increments. The mathematical relationship between distortion and quantization step size is addressed in an article by W. R. Bennett entitled "Spectra of Quantized Signals" published in the Bell System Technical Journal, July 1948, pages 446-472. In an article by Leonard Schuchman entitled "Dither Signals and Their Effect on Quantization Noise" published in the IEEE Transactions on Communication Technology December 1964, pages 162-165, the mathematical relationship between a dither signal and quanti zation noise is addressed . Arthur Stephenson's article "Digitizing Multiple RF Signals Requires an Optimum Sampling Rate" published in Electronics, March 27, 1972, pages 106-110, discloses a concept for utilizing an A/D converter, digital filter and digital demodulator for receiving and processing RF signals. The disclosed concept envisioned utilizing an automatic gain controlled amplifier to amplify the low level filtered RF signal prior to the A/D conversion. In U.S. Patent No. 3,816,831 to Leonard Mollod, the disclosed invention relates to the processing of Loran signals using hard-limiting techniques. RF noise is added to the input signal to maintain a desired signal to noise ratio. The combined signal and noise is amplified by a hard-limiting amplifier prior to the information decoding. A digital integrating and auto-correlator apparatus is disclosed in U.S. Patent No. 4,2 * 88,857 to Jack Wilterding and John Cozzens and is directed generally to signal-to-noise ratio enhancement. A signal containing noise and a separate reference noise signal are alter¬ nately coupled through an analog switch, a low pass fil¬ ter, and a sample and hold circuit to an A/D converter. Summary of the Invention It is a general object of this invention to provide an apparatus and a corresponding method for enhancing the threshold sensitivity of an A/D converter. Another object of this invention is to provide an apparatus and corresponding method for converting low level RF analog signals into digital form for further processing in a receiver. It is a further object of this invention to minimize the above mentioned problems relating to the conversion of low level RF signals into digital form in a communications receiver. OMPI In one embodiment of this invention, a sample and hold circuit receives a low level analog input signal and is gated by a clock. The output of the sample and hold circuit is summed with a signal from a noise source and the resulting signal coupled to an A/D converter. The noise source presents a bandwidth restricted signal having no substantial energy in the range of frequencies of the desired analog input signal. The clock also drives the A/D converter which has a plurality of digital output signals which correspond to- varying analog signal levels. In another embodiment of the present invention directed to an improvement in a communications receiver utilizing digital processing, a low level received RF signal is filtered by means of a band pass filter or preselector and received by a sample and hold circuit. The output of the sample and hold circuit is summed with a noise source and received by an A/D converter which provides a digital output to a digital signal processor for digital filtering and demodulation. A clock is utilized to drive the sample and hold circuit, A/D converter, and digital signal processor. The noise source is bandwidth restricted so that the noise energy does not occupy the same frequency range as the incoming desired signals. Brief Description of the Drawings Figure 1 is a block diagram illustrating an embodiment of the present invention. Figure 2 is a schematic diagram illustrating a sample and hold circuit suitable for use in the embodiment shown in figure 1. Figure 3 is a block diagram of an embodiment of the present invention in a communications receiver. - s - Detailed Description In the embodiment of this invention shown in figure 1, a sample and hold circuit 10 includes an input port 12 for accepting an analog input signal, an output 14, and a gating control input 16. The purpose of sample and hold circuit 10 is to monitor the varying instantaneous voltage presented by the analog alternating current (AC) input signal and store an instantaneous voltage level of the analog input signal. Output pulses of clock 18 are received by input 16 and determine the instants in time when the analog input signal waveform is sampled. The sample and hold circuit 10 stores the magnitude of the sampled signal until the next sample interval. The output 14 of circuit 10 may consist of the stored voltage level or a signal proportional to the sampled voltage level. A summation circuit 20 sums the signal from output 14 of the sample and hold circuit 10 together with the output from a noise source 22. The output of noise source 22 preferably consists of a moderately wide band noise signal such as a bandwidth of 50 KHz or greater. The bandwidth of the noise signal should be selected so that it does not overlap or occupy part of the range of frequencies in which desired analog input signals occur. For example, low pass or bandpass filtered Gaussian noise can be used. An analog to digital converter 24 receives the resulting composite signal, which contains a signal component corresponding to the analog input signal, from summation circuit 20 and converts it into a digital output signal (data) defined by the binary state of digital outputs 26. The output from clock 18 is received at input 28 of converter 24 which utilizes the clock pulses for gating purposes to control the time when analog to digital conversions are to occur. The amplitude of the noise signal supplied by noise source 22 should be less than the peak to peak voltage range of the A/D converter 24, i.e. the noise signal should not cause the A/D converter to clip. For example, 5 a noise signal approximately 15 decibels (dB) below the maximum peak to peak voltage range of the A/D converter is suitable. Summing a noise signal having a predetermined band¬ width and magnitude level selected relative to the range 10 of the A/D converter permits analog input signals having a magnitude less than threshold sensitivity of the A/D converter to be detected by the converter. The noise signal also has an additional benefit of "whiting" the spectrum of the A/D converter's quantizing noise; that 15 is, the quantizing noise at the output of the A/D conver¬ ter will have an essentially uniform power spectral dens¬ ity. The sampling or clock rate should be high enough so that the spectral power of the quantizing noise in the received analog input signal bandwidth is low; that is, 2.0 the ratio of the sample rate to the bandwidth of the desired signal should be large, preferably 10 or greater. The improvement in threshold sensitivity achieved by this invention increases as this ratio increases. Although noise source 22 is shown being summed with 25 the output of sample and hold circuit 10 by means of summation circuit 20, a noise source could be combined with the desired analog input signal preceding the sample and hold circuit 10 as opposed to after it. That is, the analog input signal could be summed with a noise source 30 and the resulting summed signal applied to a sample and hold circuit having its output coupled directly to the A/D converter. The use of a sample and hold circuit 10 presumes that the rate of change or frequency of the analog input 35 signal is too great or high for the A/D converter 24 to process. If the rate of change or frequency of the - JREΛ O PI analog input signal is within the capability of the A/D converter, then a sample and hold circuit need not be used. In such an application, the analog input signal would be applied directly to the summation circuit 20 in the place of the output 14 of the sample and hold circuit as shown in figure 1. In an exemplary embodiment of the present invention according to figure 1, a commercially available 1 volt ( +_ 0.5 volt) 8 bit A/D converter having 256 steps was utilized. An applied analog RF input signal at 900.455 Megahertz (MHz) having a 10 Kilohertz (KHz) bandwidth was sampled at a clock rate of 20 MHz. A low pass filtered Gaussian noise source having a bandwidth of 0-50 KHz generated a noise signal with a total power 9dB below the root mean square (rms) value of the peak to peak voltage range of the A/D converter. This converter has a threshold sensitivity or step size of 3.9 millivolts (mV) . Without utilizing the present invention, the A/D converter would be unable to recognize the presence of an analog signal which did not exceed 3.9 mV. However, utilizing this invention, an analog input signal having a magnitude of only 0.2 mV was detected and converted into a digital output signal by the A/D converter. Thus, from this particular example of the present invention, it will be apparent that analog input signals having an amplitude significantly lower than the threshold sensitivity of the A/D converter can be achieved. With respect to the low pass filtered Gaussian noise referenced in the above example, its bandwidth should be increased as the sampling rate increases and could be decreased if an A/D converter having a greater number of bits was utilized. Other types of noise sources which meet the following criteria can also be used: 1) no substantial energy at the frequency of the desired signal; 2) causes the quantization noise at the output of the A/D converter to have an essentially uniform power spectral density; 3) magnitude of the noise signal does BTJ E O PI not cause the A/D converter to clip . For example , a plurality of sine waves or a numer ically ( computer ) generated noise signal could be employed . In figure 2 , a particular sample and hold circuit 10 is illustrated . The analog input signal is coupled at input 12 to a diode sampling bridge 30. The clock signal from clock 18 is coupled at input 16 to a pulse generator 31 having its output pulse coupled by means of transform¬ er 32 to sampl ing br idge 30 as shown. The width ( time duration) of the output pul se from the pulse generator should be less than one-half of the reciprocal of the frequency of the analog input signal . Operating bias for br idge 30 is suppl ied by a conventional bias circuit 34. The clock signals as coupled to bridge 30 cause the br idge to alternately be conductive and non-conductive . Thus , bridge 30 acts as a gate which alternately couples and inhibits the coupling of the analog input signal to the input of a dual gate MOS hold integrated circuit 36. When the br idge is conducting , the analog input signal will be coupled to hold IC 36 ; when the bridge is not conducting, analog input signal will be blocked and not coupled to hold IC 36. The output of the hold IC 36 is coupled to a buffer 38 which has an output 14. Figure 3 illustrates another embod iment of the present invention utilized in a " front end" of a communi¬ cations receiver . The front end refer s to the initial signal processing section in a receiver . A received RF signal is sensed by antenna 40 which couples it to a preselector 42 which preferably consists of a band pass filter designed to pass the range of frequencies in which desired received signals may occur . The f il tered signal is coupled from preselector 42 to the input 12 of sample and hold c ircuit 10. The operation of sample and hold circ uit 10 , clock 18 , no ise source 22 , summation cir uit 20 , and A/D conver ter 24 in figure 3 is the same as previously explained with respect to figure 1 and therefore is not repeated . O PI The digital outputs 26 of A/D converter 24 can be coupled to a digital signal processor 44 for filtering and digital information recovery. Various types of digital filtering and digital signal processing are well known in the art and various digital signal processors are commercially available. The output of clock 18 may also provide a clock reference to an input 46 of the digital signal processor. The output 48 of the processor may comprise the desired information carried by the received signal. For example, the desired information may consist of voice communication (speech) or data. The particular implementation of a digital signal processor 44 or other alternative processing techniques do not comprise part of the present invention and hence will not be described in detail. The elements in figure 3 which are common to figure 1 provide the same advantage in a receiver, that is, the magnitude of the analog received signal which can be detected and converted into digital form by A/D converter 24 is substantially lower than the threshold sensitivity of the A/D converter itself. Thus, the present invention provides an improved sensitivity for the receiver. To meet a given receiver sensitivity, the present invention allows a receiver to utilize no amplification (or less amplification depending upon the particular specification) of a received signal prior to the A/D conversion. Even if an amplifier is required, the gain of the amplifier for the same receiver sensitivity level can be considerably less by the use of the present invention. Minimizing the gain required for such an amplifier or eliminating the need for the amplifier will improve the intermodulation distortion characteristic of the receiver. Also the injection of a limited bandwidth noise signal from noise source 22 tends to broaden the spectral content of the quantizing noise of the A/D - iO - converter itself and thus improves the intermodulation characteristic of the A/D converter. Although embodiments of the present invention have been described and illustrated in the drawings, the scope of this invention is defined by the claims appended hereto.

Claims: What is claimed is: 1. An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising: means for generating a noise signal which does not have any substantial energy at said given frequency; and means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter, said analog AC input signal having a magnitude less than the threshold sensitivity of the A/D converter, said summing means producing a resultant signal containing a signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation. 2. The apparatus according to claim 1 wherein said generating means generates a noise signal that produces quantization noise at the digital data output from the A/D converter having an essentially uniform power spectral density. 3. The apparatus according to claim 1 wherein said generating means generates a Gaussian noise signal. 4. The apparatus according to claim 1 wherein said • generating means generates a noise signal having an amplitude less than the maximum voltage range of the A/D converter. 5. The apparatus according to claim 4 wherein the amplitude of the noise signal is approximately 15 decibels less than the maximum voltage range of the A/D converter. 6. The apparatus according to claim 1 further comprising a clock means for generating periodic pulses coupled to said A/D converter causing the latter to make A/D conversions* in response to said pulses. 7. The apparatus according to claim 6 wherein the ratio of the rate of said periodic pulses to the band¬ width of said analog AC input signal is greater than 10. 8. The apparatus according to claim 6 further comprising means for periodically sampling the amplitude of the analog AC input signal and storing the sampled amplitude, said stored amplitude of the analog AC input signal coupled to said summing means. 9. The apparatus according to claim 8 wherein said sampling means includes means for generating sampling pulses which determine the duration of the sampling pulses, the time duration of the sampling pulses being less than 0.5 times the reciprocal of the frequency of said analog AC input signal. O PI_ 10. A method for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data comprising the steps of: generating a noise signal which does not have any substantial energy at said given frequency; summing the analog AC input signal and said noise signal to produce a resultant signal; coupling the resultant signal to the input of the A/D converter, the analog AC input signal having an amplitude less than the threshold sensitivty of the A/D converter, said resultant signal containing a signal component corresponding to said analog AC input signal, and the A/D converter converting said signal component into digital data representative of said analog AC input signal. 11. The method according to claim 10 further comprising the steps of periodically sampling the amplitude of the analog AC input signal, storing the sampled amplitude, and summing the stored amplitude with the noise signal to produce said resultant signal. 12. The method according to claim 10 further comprising the step of generating periodic clock pulses which cause corresponding A/D conversions to be made. 13. The method according to claim 12 wherein the ratio of the rate of the clock pulses to the bandwidth of the analog AC input signal is greater than 10. 14. The method according to claim 11 wherein said sampling step includes the step of generating sampling pulses that determine the duration of the sampling pulses, the sampling pulses being less than 0.5 times the reciprocal of the frequency of said analog AC input signal. 15. In a communications receiver having a band pass filter with a bandwidth which permits the passage of an analog radio frequency (RF) input signal having a frequency within a predetermined range of frequencies and an analog to digital (A/D) converter having a digital data output, the improvement comprising: means for generating a noise signal which does not have any substantial energy within said range of frequencies; and means for summing said filtered analog RF input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter, said analog RF input signal having an amplitude less than the threshold sensitivity of the A/D converter, said summing means producing a resultant signal containing a signal component corresponding to said analog RF input signal which is converted by the A/D converter into a digital data representation. 16." The apparatus according to claim 15 wherein said generating means generates a noise signal that produces quantization noise at the digital data output from the A/D converter having an essentially uniform power spectral density. 17. The apparatus according to claim 15 wherein said generating means generates a Gaussian noise signal. 18. The apparatus according to claim 15 wherein said generating means generates a noise signal having an amplitude less than the maximum voltage range of the A/D converter. 19. The apparatus according to claim 18 wherein the amplitude of the noise signal is approximately 15 decibels less than the maximum voltage range of the A/D converter. 20. The apparatus according to claim 15 further comprising clock means for generating periodic pulses coupled to the A/D converter causing the latter to make A/D conversions in response thereto. 21. The apparatus according to claim 20 wherein the ratio of the rate of said periodic pulses to the bandwidth of said analog AC input signal is greater than 10. 22. The apparatus according to claim 20 further comprising means for periodically sampling the amplitude of the filtered analog RF input signal and storing the sampled amplitude, said stored amplitude coupled to said summing means and summed with said noise signal to produce said resultant signal. 23. The apparatus according to claim 22 wherein said sampl ing means includes means for generating sampling pulses which determine the period ic sampl ing rate , the time duration of the sampling pulses being less than 0.5 times the reciprocal of the frequency of said analog RF input signal . O PI 24. A method for converting an analog radio frequency (RF) signal having a given frequency into digital data comprising the steps of: band pass filtering said analog RF signal; storing a first signal corresponding to an instantaneous magnitude of said filtered analog RF signal; generating a noise signal which does not have any substantial energy at said given frequency; summing said first signal and said noise signal to produce a resultant signal; coupling said resultant signal to an analog to digital (A/D) converter having a given threshold sensitivity, the magnitude of the analog RF signal being less than the given threshold sensitivity of the A/D converter, summing of said first signal and said noise signal producing a resultant signal containing a signal component corresponding to said analog RF signal which can be converted by the A/D converter into a digital data representation. 25. The method according to claim 24 further comprising the step of periodically sampling the instantaneous magnitude of said analog RF signal and storing a first signal corresponding to said sampled magnitude. 26. The method according to claim 24 further comprising the step of generating periodic clock pulses causing corresponding A/D conversions to be made. 27. The method according to claim 26 wherein the ratio of the rate of the clock pulses to the bandwidth of the analog RF signal is greater than 10. 28. The method according to claim 25 wherein said sampling step includes the step of generating sampling pulses that determine the duration of the sampling pulses, the sampling pulses being less than 0.5 times the reciprocal of the frequency of said analog RF signal. -^Cf&EAt O PI_

Inventors: JANC ROBERT VINCENT, JANC, ROBERT, VINCENT
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1984
Main classification: H03M1
IPC codes: H03M1, H04B1, H04B14