A PROGRAMMABLE LOGIC ARRAY CIRCUIT

Abstract: A programmable logic array circuit (10) includes a programmable AND gate array (12) and a programmable OR gate array (14). The respective arrays are made from MOS transistors all of which are either N-type or P-type. They are arranged so that during circuit operation there is no d.c. current path between the supply voltage (Vcc) and ground (GND).

Description: -2- a current path exists through each transistor device from the supply voltage to ground. This d.c. current can be translated into extra power consumption and heating. CMOS transistors can be utilized to overcome this problem. However, a price is paid for the reduced power consumption of CMOS transistor gate arrays. Since the respective PMOS and NMOS transistors in a CMOS array must be electrically isolated from each other, a much larger chip size is required for the same number of transistor devices. Disclosure of the Invention It is therefore an object of the invention to provide an improved programmable logic array circuit. Another object of the invention is to provide an improved programmable logic array that has low power consumption and high performance. Another object of the invention is to provide an improved programmable logic array circuit which has low power consumption and which requires low amounts of integrated chip area. In accordance with the present invention the AND and OR gate arrays are made up of a plurality of MOS transistors of a single type, e.g., either PMOS or NMOS preferably the latter. When strings of such MOS devices are programmably connected, no current paths exist througή the devices which would allow a d.c. current path through them between the supply voltage and ground. That is, the PLA supply voltage is never connected directly to ground through these MOS devices. The only currents which flow are transient currents when the MOS devices are switched. These transient currents result from the capacitive charge or discharge of the transistor devices themselves. -1- Description A PROGRAMMABLE LOGIC ARRAY CIRCUIT Technical Field This invention relates to programmable logic array circuits, and in particular, to programmable logic array circuits utilizing NMOS semiconductor elements. Background Art Recently, programmable integrated circuits have been extended beyond read only memories to logic circuit arrays. These are frequently referred to as programmable logic arrays (PLAs). They can be mask programmable or, utilizing fusible links, can be field programmable. PLAs have a wide variety of uses in the implementation of random logic networks. PLAs typically comprise an array of logical AND and OR gates which can be programmed for a specific function. Each output function is the sum (logical OR) of selected products (logical ANDs) where each product is the product of selected polarities of selected inputs. PLAs are programmed so that any input line can be connected to any AND gate input and any of the products (ANDs) can be summed by any of the OR gates. This is accomplished by providing a programmable array or matrix between the circuit inputs and the AND gate inputs and a programmable array between the outputs of the AND gates and the OR gates, respectively. Existing PLAs suffer from several significant drawbacks. One problem is the steady power consumption of PLAs. Each array comprises strings of serially connected transistor devices. When these transistor devices are conducting a constant d.c. current passes through the devices due to the fact that And by using either P-type or N-type MOS transistor devices instead of both as is the case of CMOS PLAs, the size of the PLA chip is significantly reduced. Brief Description of the Drawings Figure 1 is a schematic diagram of the programmable logic array of the present invention. Best Mode for Carrying Out the Invention Figure 1 shows a programmable logic array 10 in accordance with the present invention. PLA 10 is made up of a first programmable gate matrix 12 and a second programmable gate matrix 14. A plurality, of inputs Io-In are provided to the gate matrix 12 through a plurality of input buffers 16. These buffers consist of a pair of inverters 18 and 20 to additionally provide the complements Ϊo-Tn of each input signal Io-In to the gate array 12. The first gate array 12 as well as the second gate array 14 in Figure 1 are actually both NAND gate arrays. However, it can be shown that from a logic standpoint that the combination of NAND gate arrays is equivalent to an AND gate array in combination with an OR gate array. In both cases the resulting outputs represent the sum of product terms. From an electrical standpoint it is more convenient, in the configuration shown, to configure the arrays as NAND gates. But it should be understood that this is merely a matter of design choice and that the two are equivalent. Thus, the output of the first (AND) gate array 12 is a string of product term lines; line 22 for the first product term line, line 24 for the second product term line, and line 26 for the nth product term line. The signal on each product term line is amplified by an amplifier comprising PMOS transistor Q7 and inverter 28. Thereafter a pair of inverters 30 and 32 provide the product term line signals Ao-An to the second (OR) gate array 14, along with their complements Ao-An. The second gate array provides the logical addition function. Thus the outputs Qo and Ql represent the sum of the products from the (AND) gate array 12. These outputs are provided as the sum term lines 34 and 36 from the gate array 14. The sum term lines 34 and 36 are each amplified by the combination of PMOS transistor Q23 and inverter 38 and then inverted again by buffer 40. While the gate array 14 is shown with only two sum-of-the-products lines, it should be understood that, like gate array 12, the gate array 14 can be of any desired size. Gate array 12 comprises a series of identical cells, three of which are shown in Figure 1, cells 42, 44, and 46. Associated with each input and its compliment is a pair of N-type MOS transistors. Thus transistors Ql and Q2 are associated with inputs ϊo and lo, transistors Q3 and Q4 with inputs Tl and 11 , and transistors Q5 and Q6 with inputs ϊn and In. All of the transistors Q1-Q6 in each of the cells are the same type of MOS transistors, in this case N-type. Supply voltage lines 48 allow individual transistors to be connected with the circuit supply voltage Vcc. Similarly ground lines 50 permit individual transistors to be connected to ground. The "X's" shown in Figure 1 represent connection points allowing transistors Q1-Q6 to be programmably connected by metal connections in the standard manner. In other words, the function of PLA 10 is programmed by a metal mask. The underlying matrix structure allows it to be so programmed. Cells 44 and 46 are shown in the unprogrammed state. Cell 42 is shown programmed for purposes of illustration. The product te-rm line 22 in this case is connected to ground line 50 through three transistors Ql, Q4, and Q5. Input ϊo controls the gate of Ql, input II controls the gate of Q4, and input In controls the gate of Q5. If all three transistors Q1 , Q4, and 5 Q5 are in the conducting state, product term line 22 will be connected to ground and at a logical zero state. If any of those transistors are in the non¬ conducting state, the product term line is connected to the supply voltage line 48, and hence will be in the 10 logical 1 state. " Thus the cell 42 is configured as a NAND gate whose output Ao is given by the logical function: Ao = To • II • Tn 15 It will be apparent that each cell can be programmed to function as an AND gate merely by programming the connections such that the product line 22 is connected to Vcc when all of the transistors Ql, Q4 and Q5 are conducting. 20. If, for example, the value of To goes from high to low, transistor Ql will be rendered non-conducting. At the same time lo is high causing Q2 to become conducting, thereby connecting product term line 22 to Vcc. Transient current passing through Q2 stops once 25 transistor Ql, having an intrinsic capactive value, is "charged." Since there is no direct connection between Vcc and ground through Ql and Q2 no direct currents pass through them. Hence there is very little power consumption by PLA 10. OR gate array 14 is similarly configured. Two OR gate cell 54 and 56 are illustrated. Each contains a plurality of N-type MOS transistors Q10-Q15. Cell 56 is illustratively programmed. The output of the sum of the products line 36 can be represented by the logical equations: Ql = Ao • Al •An or Ql = (lo -II -In) + Al + An

Claims: Claims 1. Programmable logic array circuit comprising: a circuit supply voltage; a plurality of logical AND gates; a matrix of input lines to said AND gates; said matrix being programmable to connect desired inputs to selected AND gates; a plurality of logical OR gates; a matrix of input lines to said OR gates, said input lines being programmably connected with the output of selected AND gates; and wherein said plurality of OR gates and AND gates each comprise a plurality of serially connected MOS transistor devices all of which are either P-type or N-type, and including means for programmably connecting said MOS transistor devices to prevent a d.c. current path through said MOS transistor devices between said supply voltage and ground. 2. In a programmable logic array circuit including a supply voltage; a first gate array; a second gate array; means for programmably connecting a plurality of input lines with said first gate array; means for programmably connecting outputs from said first gate array with said second gate array; and wherein the improvement comprises means for forming said first and second gate arrays of MOS transistors of the same carrier type; and means for permitting programming of said first and second gate arrays so that no direct current path exists between said supply voltage and ground. 3. A programmable logic array circuit as in Claim 2 wherein said MOS transistors of the same carrier type are NMOS transistors. 4. A programmable logic array circuit as in Claim 3 wherein a pair of serially connected NMOS transistors in said first gate array is associated with each input line, said pair of NMOS transistors being serially connected between the supply voltage and ground, and wherein only one of said NMOS transistors is in the conducting state at one time.

Inventors: YU SHIH CHIANG, YU, SHIH, CHIANG
Applicants: SEMI PROCESSES INC, SEMI PROCESSES, INC.
Application year: 1984
Main classification: G11C7
IPC codes: H03K19