SENSE AMPLIFIER

Abstract: A sense amplifier of a differential amplifier type having an input selecting function. The sense amplifier comprises a pair of input circuit portions receiving a plurality of pairs of complementary input signals (S₁, S ₁; S₂, S ₂ ...), one of the input circuit portions comprising a plurality of circuit units (Q₄₁, Q₅₁; Q₄₂, Q₅₂ ...) each generating the amplified output of one (S₁; S₂ ...) of a pair of complementary input signals in response to an address signal (A₁; A₂; ...) applied thereto, and the other input circuit portion comprising a plurality of circuit units (Q₆₁, Q₇₁; Q₆₂, Q₇₂; ...) each generating the am­ plified output of the other one ( S ₁; S ₂; ...) of the pair of the complementary input signals in response to the address sig­ nal (A₁; A₂; ...) applied thereto. The sense amplifier selects one of a plurality of pairs of complementary input signals, i.e. complementary signals on bit lines or on data buses, in accordance with the address signal and generates an output signal (OUT) corresponding to a selected pair of complemen­ tary input signals.

Description: (1) Field of the Invention The present invention relates to a sense amplifier used, for example, in a static-type semiconductor memory device, one of the functions of the sense amplifier being to select one of a plurality of input signals. (2) Description of the Prior Art In a static-type RAM device, a very small voltage difference of, for example, about 0.5 V, output from a memory cell and transmitted to a pair of data buses is amplified by a sense amplifier when readout operation is effected. However, in a conventional static-type RAM device, especially a large capacity RAM device, since a bit line pair, column transfer gates, and a data bus pair are connected to a selected memory cell, the load of the memory cell becomes heavy, and the readout speed is deteriorated. Especially, in a large capacity RAM device, each bit line and data bus become long and thin, and the on-resistance of the column transfer gates becomes large. Therefore, if the drive ability of each memory cell is not large, it takes a long time for the input signal of the sense amplifier to reach a steady state signal level. Various solutions to this problem have been put forward. For instance the use of a sense latch to detect small differential signals on the memory bit lines has been proposed (US 3 953 839). One latch circuit is required for each pair of bit/sense lines, plus a final latch providing a driver output. Another known solution (JP-A-56 29 889) proposes a MOS circuit for mutually inverting the potential of a readout bus line of a sense circuit corresponding to two respective sets of digit lines. This solution utilizes two sense amplifiers per memory cell, each amplifier receiving a mutually inverted digit line. Yet another solution (IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 24, N° 11A, April 1982 pages 5654-5656) proposes a bit line sense amplifier, operating in current mode switching, for each word group. The sense amplifiers' input stages are controlled by sensing transistors configured as a big-current switch, with their buses connected to bit rails of the word group. SUMMARY OF THE INVENTION It is an object of the present invention to decrease the load of each selected memory cell and to speed up the operation of a semiconductor memory device. According to the present invention, there is provided a sense amplifier of a differential amplifier type for receiving pairs of complementary input signals and generating an output signal corresponding to a selected pair of complementary input signals in accordance with received address signals applied thereto, having: a pair of input circuit portions, one of said input circuit portions comprising a plurality of circuit units each generating the amplified output of one of a pair of complementary input signals in response to one of said address signals applied thereto, and the other input circuit portion comprising a plurality of circuit units each generating the amplified output of the other one of said pair of complementary input signals in response to said one of said address signals, each of said circuit units comprising a serial connection of a pair of MIS transistors, one of which receives a decoded address signal at a gate thereof, and the other one of which receives one of said complementary input signals at the gate thereof, each of said input circuit portions being constituted by a parallel connection of a plurality of said serial connections of MIS transistors; load circuits each comprising a MIS transistor respectively connected in series between said parallel connections forming the respective input circuit portions and a power supply terminal; characterized in that the sense amplifier further comprises a constant current circuit comprised of a MIS transistor connected between a common terminal and a terminal of a power source; said MIS transistors that receive a decoded address signal have their sources connected to said common terminal; one of said load circuits has a direct gate-drain connection, and the gates of the load MIS transistors and the gate of the MIS transistor of said constant current circuit being commonly connected. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block circuit diagram illustrating a conventional static-type RAM device; Figure 2 is a schematic circuit diagram illustrating a circuit structure of each memory block used in the RAM device of Fig. 1; and Figure 3 is a circuit diagram illustrating a sense amplifier as an embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Before describing the preferred embodiment, an explanation will be given of a static-type RAM device using conventional sense amplifiers with reference to the drawings. Figure 1 illustrates a general static-type RAM device in which one sense amplifier SA is provided for one memory chip, and memory cells therein are divided into a plurality of memory blocks M₁, M₂, ---. In the memory device of Fig. 1, data bus pairs DB and DB (where DB is an inversion of DB) of each memory block M₁ , M₂, --- are coupled together to a common sense amplifier SA via transfer gates TG₁ , TG₂ , ---, respectively. Therefore, it is possible to selectively connect the data bus pair DB and DB of each of the memory blocks M₁ , M₂ , --- to the sense amplifier SA by using address signals A₁ , A₂ , --- which are added to the transfer gates TG₁ , TG₂ , ---. Each of the memory blocks M₁ , M₂ , --- comprises a matrix arrangement of a plurality of memory cells disposed at the intersections of word lines and bit lines, and it is necessary to increase the number of the memory blocks when a high operation speed and low power consumption are necessitated. There is also known a memory device which comprises a sense amplifier for every data bus pair DB and DB , i.e., for every memory block M i , in which one of the output signals of the sense amplifiers is selected by using a selection logic circuit provided in the output portion of the sense amplifiers. In the cases mentioned above, as illustrated in Fig. 2, the loads of a selected memory cell MC are a bit line pair BL and BL , and the data bus pair DB and DB which is connected to the bit line pair BL and BL via column transfer gates CTG, and the aforementioned transfer gates TG i in the case of the memory device of Fig. 1. Therefore, it takes a long time for the input signal of the sense amplifier to reach a steady state signal level if the drive ability of each memory cell MC, i.e., gm of the transistors constituting the memory cell MC, is small. Especially, since each of the column transfer gates CTG and the transfer gates TG is not completely turned on even in a selected condition and has some resistance, the RC time constant of each transfer gate circuit becomes relatively large and the signal passing through the transfer gate circuit is delayed. In Fig. 2, WL designates a word line, and the input/output terminals of the memory cell MC composed of a flip-flop are connected to the bit lines BL and BL via transfer gate transistors Q a and Q b , whose gate electrodes are connected to the word line WL. These transistors Q a and Q b also become the load of the memory cell MC. As mentioned above, the device shown in Figs. 1 and 2 has the disadvantages of a heavy load for each memory cell and a low operation speed. According to the present invention, there is provided a sense amplifier which overcomes these problems, as described below. Figure 3 is a circuit diagram illustrating a CMOS type sense amplifier as an embodiment of the present invention. The sense amplifier comprises a pair of complementary input terminals IN and IN , P-channel MOS transistors Q₁ and Q₂ operating as loads, an N-channel MOS transistor Q₃ operating as a constant current source, and an output terminal OUT. The sense amplifier of Fig. 3 further comprises x sets of series connections of N-channel MOS transistors Q₄₁ and Q₅₁; Q₄₂ and Q₅₂; ---; Q 4x and Q 5x , which are mutually connected in parallel between the input terminal IN and the drain of the transistor Q₃ , and x sets of series connections of N-channel MOS transistors Q₆₁ and Q₇₁; Q₆₂ and Q₇₂; ---; Q 6x and Q 7x , which are mutually connected in parallel between the input terminal IN and the drain of the transistor Q₃. The transistors Q₅₁ and Q₇₁ , Q₅₂ and Q₇₂ , ---, Q 5x and Q 7x are controlled by the outputs A₁ through A x of an address decoder, respectively. The transistors Q₄₁ , Q₄₂ ,---, Q 4x are controlled by input signals S₁ , S₂ , ---, S x , respectively, and the transistors Q₆₁ , Q₆₂ , ---, Q 6x are controlled by inverted input signals S ₁ , S ₂ , ---, S x , respectively. It should be noted that a conventional CMOS type sense amplifier comprises only the load transistors Q₁ and Q₂ , the transistor Q₃ , and one pair of driver transistors, such as Q₄₁ and Q₆₁ , connected between the input terminal IN and the drain of the transistor Q₃ and between the input terminal IN and the drain of the transistor Q₃. Where the sense amplifier of Fig. 3 is adopted to the memory device of Fig. 1, it is used as a substitute for the circuit portion surrounded by dot-dash line of Fig. 1. Therefore, the data buses DB and DB of the memory blocks M₁ , M₂ , --- are connected to the gates of the transistors Q₄₁ and Q₆₁; Q₄₂ and Q₆₂ , ---, Q 4x and Q 6x , respectively. As apparent from Fig. 3, each set of the transistors Q 4i and Q 5i (i = 1, 2, ---, x) composes an AND gate having two inputs S i and A i , and each set of the transistors Q 6i and Q 7i composes an AND gate having two inputs S i and A i . Therefore, when the outputs A₁ through A x of the address decoder are all low, the transistors Q₅₁ , Q₅₂ , ---, Q 5x , and Q₇₁ , Q₇₂ , ---, Q 7x are all turned off, and the sense amplifier is in a standby status. When an output A i of the address decoder corresponding to the inputs S i and S i becomes high, the potentials of the input terminals IN and IN become high and low, respectively, if the inputs S i and S i are low and high, respectively, and become low and high, respectively, if the inputs S i and S i are high and low, respectively. The potential of the output terminal OUT is the same as that of the input terminal IN and determined by the above relationships of the signals. Where the sense amplifier is provided for every data bus pair DB and DB , the inputs S₁ and S ₁, S₂ and S ₂ , ---, S x and S x are signals from the bit lines in a memory block, and the circuit of Fig. 3 is used as a column sense amplifier. The transistor pairs Q₅₁ and Q₇₁ , Q₅₂ and Q₇₂ , --- Q 5x and Q 7x correspond to column transfer gates CTG. In this case, the load of each memory cell can be greatly decreased because the memory cell does not drive the data buses. It is also possible to combine the outputs of a plurality of column sense amplifiers into one circuit route by further using one stage of a sense amplifier having a similar constitution. Although the CMOS type circuit was explained above, the present invention can be also adopted to an N-MOS type circuit and the like. As mentioned above, according to the present invention, since each sense amplifier itself has the function of selecting inputs, the load of each memory cell can be decreased when the sense amplifier is used as a column sense amplifier whose input terminals are connected to bit lines. When the sense amplifier is used as a sense amplifier whose input terminals are connected to data buses, it is possible to increase the readout speed because the transfer gates TG can be omitted. When the sense amplifiers are used in a two level hierarchical structure including a bit line stage and a data bus stage, it is possible to constitute a readout circuit stage having high response speed and simple connection patterns.

Claims: A sense amplifier of a differential amplifier type for receiving pairs of complementary input signals (S₁, S ₁; S₂, S ₂; ...S x , S x ) and generating an output signal (OUT) corresponding to a selected pair of complementary input signals in accordance with received address signals (A₁,A₂, ... A x ) applied thereto, having: a pair of input circuit portions, one of said input circuit portions comprising a plurality of circuit units (Q41,Q51; Q42,Q52; .. Q4x, Q5x) each generating the amplified output of one of a pair of complementary input signals in response to one of said address signals (A₁,A₂,... A x ) applied thereto, and the other input circuit portion comprising a plurality of circuit units (Q61,Q71; Q62,Q72;... Q6x,Q7x) each generating the amplified output of the other one of said pair of complementary input signals in response to said one of said address signals, each of said circuit units (Q41,Q51; Q42,Q52;.... Q4x,Q5x; Q61,Q71; Q62,Q72; ... Q6x,Q7x) comprising a serial connection of a pair of MIS transistors, one of which (Q51,Q52, ... Q5x Q71,Q72,... Q7x) receives a decoded address signal (A₁,A₂, ... A x ) at a gate thereof, and the other one (Q41,Q42, ... Q4x; Q61,Q62, ... Q6x) of which receives one of said complementary input signals (S₁, S ₁; S₂, S ₂; S₃, S ₃;... S x , S x ) at the gate thereof, each of said input circuit portions being constituted by a parallel connection of a plurality of said serial connections of MIS transistors; load circuits each comprising a MIS transistor (Q1,Q2) respectively connected in series between said parallel connections forming the respective input circuit portions and a power supply terminal (Vcc); characterized in that the sense amplifier further comprises a constant current circuit comprised of a MIS transistor (Q3) connected between a common terminal and a terminal (Vss) of a power source; said MIS transistors (Q51,Q52...Q5x; Q71,Q72,..Q7x) that receive a decoded address signals (S₁, S ₁; S₂, S ₂; ...S x , S x ) have their sources connected to said common terminal; one of said load circuits (Q1) has a direct gate-drain connection, and the gates of the load MIS transistors (Q1, Q2) and the gate of the MIS transistor (Q3) of said constant current circuit being commonly connected. A sense amplifier according to claim 1, characterized in that the said other respective MIS transistors (Q41, Q42, ... Q4x; Q61, Q62, ... Q6x) of each of said circuit units are connected to bit lines of a memory device. A sense amplifier according to claim 1, characterized in that the said other respective MIS transistors (Q41, Q42, ... Q4x; Q61, Q62, ... Q6x) are connected to data buses of a memory device.

Inventors: KOSHIZUKA, ATUO
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: G11C7
IPC codes: G11C7, G11C11, H03K5