A DIGITAL SIGNAL PROCESSING APPARATUS HAVING A DIGITAL FILTER

Abstract: A digital signal processing apparatus with a rate-­ conversion function has at least two digital filters and a memory. A digital signal stored in the memory is selectively transferred to the at least two digital filters. These digital filters perform a filtering operation in parallel, and the results of each digital filters are alternately derived by a multiplexer. Thus, a high-speed filtering can be executed. The memory temporarily stores a time-division-multiplexed signal which is sequentially read out of the memory and selectively transferred to the digital filters. Thus, a plurality of digital signals can be filtered by the same digital filters without an increase in hardware elements. Therefore, the digital filter section can be integrated in a single semiconductor chip. A shift register may be used as the memory, whereby a circuit arrangement of the digital filter section can be extremely simplified.

Description: The present invention relates to a digital processing apparatus according to the preamble part of claim 1. In a typical digital signal processing technique, an audio signal, an image signal, or the like, as an analog signal is, in general, converted to a digital signal by means of a sampling operation and a quantizing operation, and is processed by a digital filter, such as a finite impulse response (FIR) filter (a transversal filter or a non-recursive filter) which is well known in the art. The output of the digital filter is transferred to a digital-to-analog converter, and is converted into an analog signal. The converted analog signal is taken out through a low pass filter, or the like. A rate conversion is required to improve a signal-to-noise ratio or to decrease the burden of the low pass filter. This conversion is performed by, for example, interpolating a new digital data between adjacent sampled digital data by using the digital filter. For instance, if each one digital data is interpolated between sampled digital data, sampled data are doubled, that is, two-times rate-conversion is executed. However, a conventional digital filter having the rate-conversion function has a defect that a high-speed filtering can not be performed since the interpolating operation is required. Further, in order to process a plurality of digital signals, digital filters equal in number to the signals to be processed must be employed. Thus, a large quantity of hardware elements are required for digital-filtering. Therefore, a plurality of semiconductor chips, in which a digital filter circuit is independently formed, must be used. A transversal (non-recursive) digital filter generally comprises a plurality of delay circuits, a plurality of multipliers and an adder. When this filter is produced by a semiconductor device, a read-write memory (RAM) is used as the delay circuits. Further, a read only memory (ROM) is used to store a plurality of coefficients for multiplications. In addition to these memories, a plurality of multiplier circuits and an adder circuit are used. Therefore, it is very hard to integrate a plurality of filters in a semiconductor chip. A digital processing apparatus according to the preamble part of claim 1 is disclosed in "ICASSP 83, Proceedings, Boston, Massachusetts, USA, 14-16 April 1983, Volume 1, pages 224-227, IEEE, New York, USA; C.R. Galand et al.: "Design and evaluation of parallel quadrature mirror filters". This reference discloses parallel quadrature mirror filters for a single channel signal, wherein the single channel signal is sampled at a first rate and splitted into two or more sub-band signals. These sub-band signals thus have a sample rate of a half or less of the first rate. The sub-band signals are then subjected to a filter operation, respectively, and the respective resultant data signals are thereafter added to each other at a rate equal to the first rate. However, this reference is not related to high speed rate conversion. It is therefore the object of the invention to provide a digital processing apparatus in which a rate-conversion can be performed at high speed with a small number of hardware elements. This object is achieved by a digital processing apparatus for processing digital signals comprising a first digital filter and a second digital filter and means for entering the digital signals into said digital filters at a first rate, wherein each of said digital filters perform a filter operation on the digital signal entered therein, and means for selecting in sequence outputs from said digital filters at a second rate, wherein said digital signals are of a plurality of channels which are applied to the apparatus in a time-division manner within one sampling cycle, said first and second digital filters are even-order and odd-order digital filters, respectively, said entering means comprises memory means, and said first rate is equal to the time division rate, wherein one digital signal of said channels is entered into said even-order digital filter at a first timing with another digital signal of said channels being entered into said odd-order digital filter at said first timing and the one digital signal is entered into said odd-order digital filter at a second timing subsequent to said first timing with the other digital signal being entered into said even-order digital filter at that second timing, and wherein the second rate for selecting the outputs is equal to said first rate but different in phase from said first rate. The digital filter circuits are positioned in parallel to each other and perform a filtering operation in parallel. The memory means has a capacity for storing at least two kinds of digital signals, that is, for example a sampling data and an interpolating data, or a first channel data and a second channel data in a multi-channel system, or the like. A pair of random access memories, a pair of registers, a single shift register, or the like, may be used as the memory means. The memory means, digital filter circuits, transferring circuit, and multiplexing circuit can be integrated in the same semiconductor chip. According to the present invention, the digital filter circuits are integrated in a semiconductor chip and are activated in parallel. If two digital filter circuits are employed, one is used to process the filtering operation for the odd number sampled data, while the other is used to process the filtering operation for the even number sampled data. The odd number sampled data and the even number sampled data are alternately stored in the memory means, and are selectively applied to the two digital filter circuits through the transferring circuit. These two digital filter circuits perform a filtering operation in parallel. Outputs of these two digital filter circuits are alternately selected and transferred through the multiplexing circuit. Therefore, a high-speed filtering operation can be obtained. In particular, the present invention is useful for the rate-conversion processing. Further, in a multi-channel system, a plurality of digital signals are time-division-multiplexed and are sequentially stored in the memory means, and thereafter they are selectively applied to the digital filter circuits. Thus, the filter circuits can be used in common for the plurality of digital signals. Therefore, a filtering section is easily integrated in a single semiconductor chip even if a digital signal processing apparatus is used in a multi-channel system. Here, if a shift register is used as the memory means, data transmission to the filter circuits can be very simplified as described herenafter. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a digital signal processing apparatus; Fig. 2 is a block diagram of a prior art non-recursive digital filter employed in a conventional digital signal processing apparatus; Figs. 3(a) and 3(b) are illustrations showing the known concept of the PCM signal rate-conversion operation, Figs. 4 and 5, are block diagrams of a rate-conversion non-recursive digital filter which effects a double rate conversion operntion on a single input according to a fundamental concept of the present invention; Fig. 6 is a timing chart showing the operation of the digital filter shown in Fig. 5; Fig. 7 is a block diagram of a rate-conversion non-recursive digital filter in accordance with an embodiment of the present invention; Fig. 8 is a timing chart showing the operation of the digital filter shown in Fig. 7; Fig. 9 is a block diagram of a digital filter having an array multiplication method according to another embodiment of the present invention; Fig. 10 is a block diagram showing a layout pattern of Fig. 9; Fig. 11 is a block diagram of a prior art rate-conversion non-recursive digital filler which effects an n-times rate conversion operation on a single input; Fig. 12 is a block diagram of a rate-conversion non-recursive digital filter in accordance with a still other embodiment of the present invention which effects an N-times rate conversion operation on an N-channel input; and Fig. 13 is a timing chart showing the operation of the digital filter shown in Fig. 12. DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE PRESENT INVENTION First of all, a typical conventional digital signal processing apparatus is, as shown in Fig. 1, composed of: a sampling circuit 1 which produces a Pulse Admplitude Modulation (PAM) signal plotted along the time axes from an analog input signal; a quantizing circuit 2 which converts the output of the sampling circuit 1 into digital signals (a series of binary codes) digitally plotted along the amplitude axis; a digital filter 3 which effects a digital signal processing such as to shape the output of the quantizing circuit 2 into a desired spectrum; a D/A converter circuit 4 which converts the output of the digital filter 3 into an analog value; and an interpolator circuit 5 such as a low pass filter which obtains a desired analog signal. In the case where a non-recursive digital filter (a known transversal filter) is employed for the spectrum shaping operation as the digital filter 3, the input/output relationship between the input signal x(nT₁) (a digital value) to the digital filter and the output signal y(nT₁) (a digital value) from the digital filter at the time nT₁ is represented as follows: where: n, M are positive integers; T₁ is a sampling period; and a k is a constant. The formula (1) includes three kinds of operation, than is, addition, multiplication and time delaying. The formula (1) can be carried out by a digital circuit arrangement such as that shown in Fig. 2. In the Figure: the reference numerals 211 to 21M denote T₁ time-delay circuits; the numerals 220, 221, ...., 22M-1, 22M denote multipliers respectively having constants a₀, a₁, ...., a M-1 , a M ; and the numeral 23 denotes an adder. The following is a description of a non-recursive digital filter having a rate-conversion function which can be employed as the digital filter 3 shown in Fig. 1. The description will be made of the case where the sampling rate is doubled in order to simplify the description. Assuming now that the input to the filter is sampled digital data arriving thereat at a rate of sampling frequency f s (1/T₁) shown in Fig. 3(a), interpolation by zero data is effected as shown in Fig. 3(b), and the zero data are regarded as sampled values x(nT₂) at a rate of sampling frequency 2f s , where T₂=1/(2f s ). Assuming now that the input/output relationship of the digital filter is represented as follows: when the sampled data (actual data) shown in Fig. 3(a) are applied to the input terminal, the term x[(n-k)T₂], in which k is an odd order, is zero. Therefore, in practice, the output signal y(nT₂) can be obtained by calculating only the term in which k is an even order. On the other hand, when interpolation is effected by the zero data, the output signal y(nT₂) can be obtained by calculating only the term in which k is an odd order. Accordingly, the non-recursive digital filter circuit with the rate-conversion function is equivalently represented by parallel filters such as those shown in Fig. 4 which shows a fundamental circuit of the present invention. This digital filter circuit includes an even-order filter having 2T₂ time-delay circuits 311 to 31m, multipliers 321 to 32m, and an adder 35, an odd-order filter having a T₂ time-delay circuit 330, 2T₂ time-delay circuits 331 to 33m, multipliers 341 to 34m, and an adder 36, and a selector 37. The digital filter is arranged such that a switch 37 is switched over at a rate of 2f s such as to alternately output the results of calculation carried out by the even-order filter and the odd-order filter, thereby obtaining a rate-converted output signal y(nT₂) having a rate of 2f s . In the above, M is assumed to be 2m. This non-recursive digital filter can be constructed as exemplarily shown in Fig. 5. The time sequence of the digital filter is such as that shown in Fig. 6. In Fig. 5, an input signal x(nT₂) is input to both an even-order filter 51 and an odd-order filter 52. The respective outputs of the filters 51 and 52 are input to a multiplexer 53, which provides an output signal y(nT₂) as its output. A timing control circuit 54 controls the timing of the even-order filter 51 and the odd-order filter 52. As shown in Fig. 6, the respective results of an even-order calculation 61 and an odd-order calculation 62 in relation to, for example, an input signal x(nT₁) are delivered as an even-order output 66 and an odd-order output 67 in relation to an output signal y(nT₂). The same is the case with an even-order calculation 63 and an odd-order calculation 64 in relation to an input signal x (n+1) , and therefore, the reference numerals 68 and 69 respectively denote the odd-order output and even-order output in an output signal y(nT₂). Incidentally, the above-described digital filter handles one-channel input signal. To effect a two-fold rate conversion operation on plural-channel input signals, it is, hitherto, disadvantageously necessary to provide a number of hardware units which is channel-number times as large as that for one channel. Namely, many sets of filters 51 and 52 must be employed. Accordingly, it is desired to provide a digital signal processing apparatus which makes it possible to realize a rate change operation for time-division multiplexed plural-channel input signals with a simple hardware. To satisfy this desire, a digital signal processing apparatus comprising a memory circuit which stores for a predetermined period of time a plurality of N-channel PCM signals time-division multiplexed, N digital filters obtained by dividing an m-order non-recursive digital filter into N sections, and a switching circuit which selectively connects together the memory circuit and the N digital filters, wherein the i-th digital filter in the N digital filters is adapted to carry out multiplication with an ℓN+i(<m)th coefficient (ℓ =0, 1, .... ) and addition. A filtering operation is executed by switching over the switching circuit at an interval at which the PCM signals are transmitted such as to obtain N outputs, thereby effecting an N-times rate-recursive digital filter operation on the PCM signals. Fig. 7 is a block diagram of one embodiment of the present invention, while Fig. 8 is a timing chart showing the operation of the embodiment shown in Fig. 7. In this embodiment, time-division multiplexed two-channel input signals are alternately input for the channel 1 and the channel 2. These signals are properly selected by a selector 70 and are written into respective memories 71, 72 which are used as delay circuit means (311 and 31m, 330, 331, .... 33m in Fig. 4). Two digital filters 74 and 75 are provided, each comprising a ROM for storing coefficients, a multiplier, and an arithmetic circuit for addition. At the timing (between the time t₂ and the time t₃) subsequent to the timing (between the time t₁ and the time t₂) when the channel-1 data has been written, the written channel-1 data is delivered to an even-order digital filter 74 through a selector 73, and a calculation output is obtained from the filter 74. At the same timing, the channel-2 data written before the time t₁ is delivered to an odd-order digital filter 75 through the selector 73, and a calculation output is obtained from the filter 75. The respective outputs of the even-order filter 74 and the odd-order filter 75 are delivered in a time-division manner while being, further, properly selected by a selector (a multiplexer) 76 at the time t₂₃ within the subsequent timing (between the time t₃ and the time t₄). At the timing between the time t₂ and the time t₃, the channel-2 data is written into the memory 72 through the selector 70 to renew the contents of the memory 72. At the time t₃, the selector 73 is switched over such that the channel-1 data is delivered to the odd-order filter 75 and the channel-2 data is delivered to the even-order filter 74, thereby obtaining the respective outputs of the filters 75 and 74. The selector 76 is switched over at the time t₄₅ such that the respective outputs of the even-order filter 74 and the odd-order filter 75 are delivered in a time-division manner. These operations are repeated. Thus, a rate-conversion operation and a two-channel multi-operation can be processed at a high speed only with two filters 74 and 75. These filters are not required to include a delay means and may comprise a multiplication means and an addition means. The respective circuits 71, 72, 74 and 75 and the selectors 70, 73 and 76 in Fig. 7 can be easily integrated in a single semiconductor chip. The digital filter as shown in Fig. 7 is possible to efficiently subject two-channel PCM digital signals to a two-fold rate conversion operation by allowing the two-channel signals to multiplexly use filters which are respectively provided for even-order shift steps and odd-order shift steps. Fig. 9 shows another embodiment of the present invention which adopts an Array multiplication method. The Array multiplication method employs a ROM product-summing circuit which includes a ROM previously storing products for respective bits and accessed by input digital signals and a circuit for repeatedly executing shift and addition operations of the outputs of the ROM. A digital filter of Fig. 9 uses an odd-order ROM product-summing circuit 91 and an even-order ROM product-summing circuit 92 instead of the odd-order digital filter 74 and the even-order digital filter 75 in Fig. 7, and use a shift register 90 instead of memory circuits 71 and 72 in Fig. 7. The shift register 90 works as a delay means and includes M+1 stages SRO through SRM. A time-division multiplexed two-channel signal 93 is directly applied to the first stage SRO of the shift register 90, and therefore the selector 70 of Fig. 7 is not required. The outputs of the respective stages SRO to SRM of the shift register 90 are alternately output to the odd-order ROM product-summing circuit 91 and the even-order ROM product-summing circuit 92, whereby the two-channel signals are distributed to the odd-order shift steps and the even-order shift steps. The output of the odd-order ROM product-summing circuit 91 and the output of the even-order ROM product-summing circuit 92 are alternately derived by a multiplexer 95, thereby obtaining a rate-converted output 94. Fig. 10 is a block diagram showing a layout pattern of Fig. 9. The shift register 90 for delaying input signals is disposed on a semiconductor chip 100 between the odd-order ROM product-summing circuit 91 and the even-order ROM product-summing circuit 92 which are respectively disposed on the upper and lower sides of the row of the shift register 90 such that, for example, 16 outputs of the shift register are alternately distributed upwardly and downwardly. In the ROM product-summing circuits 91 and 92, ROM's 91-1 and 92-1 storing multiplied data are respectively disposed on the upper and lower sides of the shift register 90 as viewed in Fig. 10. The products obtained by the ROM's 91-1 and 92-1 are transferred up and down, respectively, to shifting and adding circuits 91-2 and 92-2, and the results of addition are sent to a multiplexer 95, disposed on one side of the shift register 90. Thus, the shift register 90 is disposed in the center, and the ROM product-summing circuits 91 and 92 each constituted by the ROM 91-1 and 92-1 and the shifting and adding circuits 91-2 and 92-2 are respectively disposed on both sides of the shift register 90 such that the outputs of the shift register are alternately delivered to the circuits on both sides of the shift register 90, whereby the wiring region is reduced deposite of a parallel processing, thus advantageously enabling a reduction in area of the semiconductor device. In other words, it is possible to realize a low-cost and high-performance rate-conversion digital filter. In the case where time-division multiplexed N-channel input signals are subjected to an N-times sampling rate conversion operation, it is also possible to realize a digital signal processing apparatus according to the principle similar to the above as follows. Fig. 11 shows a non-recursive digital filter employed to effect an N-times rate conversion operation on a single input. The number of zero-data interpolations is N-1. When actual data are input and are stored in a memory 910, filtering is carried out on only the 0th, Nth, 2Nth .... data, respectively. At the subsequent timing, calculation is carried out on only the first, (N+1)th .... data. Thereafter, calculation is carried in the similar manner. Assuming that the (ℓN+1)th data (ℓ =0,1...., 0 ≦ 1 ≦ N-1) is calculated by the i-order filter, after the actual data are input, the respective outputs of the 0-order filter 920, the first-order filter 921 ...., the i-order filter 921i .... the (n-1)-order filter 92 n-1 are successively input and output by the selectors 930, 940, thereby making it possible to obtain an output signal changed such as to have an N-times sampling rate. Multiplexly using these filters makes it possible to effect a rate conversion operation on time-division multiplexed N-channel input signals. Fig. 12 is a block diagram of a third embodiment of the rate-conversion non-recursive digital filter for use in the above-described case, while Fig. 13 is a timing chart showing the operation of the digital filter shown in Fig. 12. Since time-division multiplexed N-channel input signals are successively input in the order, the channel 1, the channel 2, ...., the channel N, these signals are written into memories 1201 to 120N which correspond to the respective channels. At the timing (between the time t₂' and the time t₃') subsequent to the timing (between the time t₁' and the time t₂') when the channel-1 data has been written, the written channel-1 data is delivered to the 0-order filter 1300 through a selector 1200, and the data of the channel N, ....,the channel i, ...., the channel 2 which have been written before the time t₁' are respectively delivered through the selector 1200 to a first-order filter 1301, .... , an (N-i+1)-order filter 130 N-i+1 , ...., an (N-1)-order filter (1301 to 130 N-1 ), and calculation outputs are obtained therefrom. Then, a selector 1400 is switched over at an interval of 1/N of the sampling rate such that the respective calculation outputs of the 0-order filter to the (N-1)-order filter are delivered in a time-division manner. At the same timing (between the time t₂' and the time t₃'), the channel-2 data is written into the memory 1202 to renew the contents thereof. At the time t₃', the selector 1200 is switched over such that the channel-1 data is delivered to the first-order filter 1301, and in the similar manner, the data of the channel N, ....., the channel i , ...., the channel 2 are respectively delivered through the selector 1200 to the second-order filter 1302, ...., the (N-i+2)-order filter 130 N-i+2 , ...., the 0-order filter 1300, thus obtaining calculation outputs thereof. Then, the selector 1400 is switched over at an interval of 1/N of the sampling rate such that the respective calculation outputs of the first-order filter to the (N-1)-order filter and the 0-order filter are delivered in a time-division manner. Thereafter, the operations are successively repeated in the similar manner. Thus, according to the embodiment, it is possible to realize a rate-conversion digital filtering for time-division multiplexed plural-channel PCM signals with a simple hardware design.

Claims: A digital processing apparatus for processing digital signals comprising a first digital filter and a second digital filter (74,91,920,1300;75,92,921,1301) and means (73,930,1200) for entering the digital signals into said digital filters at a first rate, wherein each of said digital filters perform a filter operation on the digital signal entered therein, and means (76,95,940,1400) for selecting in sequence outputs from said digital filters at a second rate, characterized in that said digital signals are of a plurality of channels (ch 1, ch 2, ...) which are applied to the apparatus in a time-division manner within one sampling cycle, that said first and second digital filters are even-order and odd-order digital filters, respectively, that said entering means comprises memory means (71,72,90,910,1201-120N), and that said first rate is equal to the time-division rate, wherein one digital signal (ch 1) of said channels is entered into said even-order digital filter (74,91,920,1300) at a first timing (t2,t2') with another digital signal (ch 2) of said channels being entered into said odd-order digital filter (75,92,921,1301) at said first timing (t2,t2') and the one digital signal (ch 1) is entered into said odd-order digital filter (75,92,921,1301) at a second timing (t3,t3') subsequent to said first timing with the other digital signal (ch 2) being entered into said even-order digital filter (74,91,920,1300) at said second timing (t3,t3'), wherein the second rate for selecting the outputs is equal to said first rate but different in phase from said first rate. The apparatus as claimed in claim 1, characterized in that said entering means includes a first memory (71,1201) for temporarily storing the one digital signal (ch 1), a second memory (72,1201) for temporarily storing the other digital signal (ch 2), and selector means (73,1200) for controlling the entering of the digital signals from said first and second memories into said even-order and odd-order digital filters. The apparatus as claimed in claim 1, characterized in that said entering means includes a shift register (90) having a plurality of shift stages (SRO to SRM), wherein even-order shift stages (SRO,SR2, ...) are coupled to said even-order digital filter (91) and odd-order shift stages (SR1,SR3, ...) are coupled to said odd-order digital filter (92). The apparatus as claimed in claim 3, characterized in that each of said even-order and odd-order digital filters (91,92) includes a memory (91-1,92-1) for storing multiplied data and a shifting and adding circuit (91-2,92-2).

Inventors: TOMIMITSU, YASUHARU
Applicants: NEC CORPORATION
Application year: 1984
Main classification: H03H17
IPC codes: H03H17