BUFFER-STORAGE CONTROL SYSTEM

Abstract: A buffer-storage control system used in a pipeline data processor comprises a memory system having a two-level hierarchical structure composed of a main storage (3, Figure 1) and a buffer storage (8). The buffer storage (8) has a tag portion (21) and a data portion (22), each portion being com­ posed of a plurality of ways. In the buffer-storage control sytem, the tag portion (21) and the data portion (22) can be independently accessed and the data portion (22) is so consti­ tuted for every way that it is possible to select one of a plurality of address passes and to select an address for a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.

Description: The present invention relates to a buffer-storage control system, more particularly a buffer-storage control system for storing access in a pipeline data processing system from a data processing unit and the like to a memory system having a two-level hierarchical structure composed of a main storage and a buffer storage. A buffer storage generally comprises a tag portion (TAG) and a data portion (DATA), each of these portions comprising a plurality of ways or way portions. Each way of the tag portion and the data portion comprises a plurality of blocks, each block being a data unit of a storing or transferring operation. The tag portion has a plurality of valid bits corresponding to the blocks for indicating block validity, i.e., indicating that data is already transferred to the block from the main storage and a write operation is possible. In a data processing system comprising a two-level hierarchical memory system composed of a main storage and a buffer storage, when the memory system is accessed, every way of the above-mentioned tag portion is read out simultaneously, i.e., the coincidence of addresses is checked, to determine whether or not the buffer storage stores data of a designated address. Noncoincidence of any of the addresses in the ways with the designated address means the target data is not stored in the buffer storage. Therefore, the data of the designated address is read from the main storage and transmitted to the buffer storage. Thereafter, the memory system is generally controlled so that the memory access is effected to the buffer storage. In a buffer-storage control system of a "store-through" type, when store-accessing the main storage, if an address block memorizing the address corresponding to that for the store access is found in the buffer storage, the buffer storage is store-accessed at the same time. If the address block is not found in the buffer storage, the memory system is controlled so that the buffer storage is not store-accessed but only the main storage. If the data processor for performing pipeline processing is continuously storage-accessing the buffer storage, the storing operation and fetching operation caused by a succeeding instruction will overlap and the fetching operation of the succeeding instruction will be delayed. This wastes machine cycles and reduces the processing ability of the overall computer system. US-A-4208716 describes a cache system which enables data to be read from and written to a storage unit. The storage unit or cache is organised into a plurality of levels, each of the levels including a number of multi-word blocks and having associated therewith a corresponding number of address selection switches and address registers. During a cache cycle of operation, an address specifying the cache location to which memory data is to be written is clocked into one address register via a second position of one address selection switch. An address specifying a cache location from which a next instruction is to be fetched is clocked into the remaining address registers via a first position of the other address selection switches. The cache arrangement includes a comparator circuit for comparing signals indicating the level into which memory data is to be written the signals indicating the level from which a next instruction is to be fetched. In accordance with the present invention, a buffer-storage control system in a data processor comprises a main storage (MSU) and a buffer storage which has a tag portion and a data portion, each portion composed of a plurality of ways, characterised in that the buffer-storage control system is so constituted that the tag portion and control system is so constituted that the tag portion and the data portion can be independently accessed, and that the data portion is so constituted for every way that it is possible to select one of a plurality of address paths and to select an address for a read access and an address for a write access for every way, whereby data is stored in the buffer storage in a data storage operation comprising a first step of accessing the tag portion and checking whether or not an address block exists to which a storage operation is to be carried out and a subsequent second step in which data is written to the data portion, the arrangement being such that, except where the ways are the same, the second step of one data storage operation and the first step of a succeeding data storage operation can be carried out simultaneously and in parallel. The present invention provides a system for preventing delays in a read operation when the read operation and the write operation of a buffer storage overlap. Some examples of systems according to the present invention will now be described and contrasted with a conventional system with reference to accompanying drawings, in which:- Figure 1 is a block circuit diagram of an example of a general data processing system comprising a memory system having a two-level hierarchical structure; Figure 2 is a block circuit diagram of the detailed structure of a central processing unit (CPU) used in the data processing system of Figure 1; Figure 3 is a block circuit diagram of a buffer storage used in a conventional buffer-storage control system; Figure 4 is a timing diagram of the storing operation in the circuit of Figure 3; Figure 5A is a time chart of a pipeline processing sequence in a data processing system using a conventional buffer-storage control system; Figure 5B is a time chart of a pipeline processing sequence in a data processing system using a buffer-storage control system according to an example of the present invention; Figure 6 is a combined block circuit diagram of a buffer storage used in a buffer-storage control system according to two examples of the present invention; and, Figure 7 is a block circuit diagram of a way-coincidence detecting circuit used for executing a re-read operation for connection to the circuit of Figure 6. Before describing the preferred embodiments, an explanation will be made of a conventional buffer-storage control system for reference. As illustrated in Figure 1, a general data processing system or a data processor comprises a CPU 1, a channel unit (CHU) 2, a main storage unit (MSU) 3, and a memory control unit (MCU) 4 which couples all these units. The CHU 2 controls one or more channels which are connected thereto and to which one or more input/output apparatuses and the like are coupled. The MCU 4 effects memory-access control between the CPU 1, the CHU 2, and the MSU 3. The CPU 1 comprises, as shown in Fig. 2, an instruction unit 5, an execution unit 6, a storage control unit 7, and a buffer storage or high speed buffer (HSB) 8. In Fig. 2, the instruction unit 5 fetches and decodes instructions sequentially and controls the operation of the execution unit 6, and the storage control unit 7. The execution unit 6 effects operations in accordance with instructions decoded by the instruction unit 5, thereby executing the instructions sequentially. The storage control unit 7 controls the access operation to the HSB 8 and the MSU 3 (Fig. 1) and is connected to the MCU 4 (Fig. 1). The HSB 8 and the MSU 3 compose a memory system having a two-level hierarchical structure. In the above-mentioned system, the storing operation to the HSB 8 is performed by the routine of detecting, first, whether or not the address to which data is stored is in the HSB 8 and of effecting the actual trite operation when the address is found in the HSB 8. Figure 3 is a block circuit diagram of circuit portions relating to the storing operation to the HSB 8 of a conventional system. Figure 4 is a time chart of the storing operation corresponding to the block circuit diagram of Fig. 3. In these drawings, 9 designates an effective address register (EAR) which is provided in the storage control unit 7 and which receives an address for an instruction-fetching operation or operand-access operation from the instruction unit 5 (Fig. 2) in the CPU. In the HSB 8, 21 designates a tag portion; 22 a data portion; 23-0, 23-1, ..., 23-F comparators; 24 an encoder; 25 a way number register (WNR); 10 and 11 a B2 register and an operand address register (OPAR), both provided in the storage control unit 7; and 30-0, 30-1, ..., 30-F gate circuits controlled by the outputs of the comparators 23-0, 23-1, ..., 23-F to pass the read data from the ways 0 through F of the data portion 22, respectively. The tag portion 21 comprises, for example, 16 ways (way 0, way 1, ..., way F) each having, for example, 64 entries. The data portion 22 also comprises, for example, 16 ways (way 0, way 1, ..., way F) each having, for example, 64 blocks. Each of the blocks of the ways in the data portion 22 has a length of 64 byte. Thus, the data portion has, for example, a memory capacity of 64 Kbyte. Each of the blocks of the ways in the tag portion 21 memorizes a validity bit and upper address bits 8 through 19 of the data stored in the corresponding block of the data portion 22. In the storing operation, the HSB 8 is read by using a storing address, and it is checked whether or not the storing address is found in the HSB 8. In this case, the storing address is set into the EAR 9 shown in Fig. 3. By using bits 20 through 25 of the EAR 9 which correspond to a block address of the HSB 8, the content of the tag portion 21 of the HSB 8 is read. In the tag portion 21 are stored validity bits (V bits) indicating whether the contents thereof are valid or not and upper address bits 8 through 19 of the data stored in the corresponding block. If any of the above-mentioned valid bits (V bits) is in the "on" state, the upper address bits 8 through 19 and the bits 8 through 19 of the EAR 9 are compared by the comparators 23-0, 23-1, ..., 23-F, thereby detecting whether the storing address is memorized in the HSB 8 or not. If any comparator indicates coincidence, the number of the corresponding way is encoded by the encoder 24 and set in the WNR 25, which is used for designating the way number to be written when the actual write operation is effected. An explanation will now be made of the storing operation in reference to Fig. 3 using the time chart in Fig. 4. At first, in a pipeline data processing system, a priority flip-flop Popfch which is used for setting a storing address to the EAR 9 and which indicates the priority of using a pipeline is set, and a priority cycle (P-cycle) starts. Thereafter, the content of the tag portion 21 of the HSB 8 is read in two cycles B1 (buffer 1) and B2 (buffer 2). At the end of the B2 cycle, the WNR 25 is subjected to a write operation. The address data set in the EAR 9 is shifted into the B2 register 10 at the B2 cycle and memorized in the OPAR 11 at an R cycle. When the write operation to the HSB 8 is effected, a priority flip-flop Popst is set, the write address is loaded from the OPAR 11 to the EAR 9, and data is written into the block in a corresponding way of the data portion 22 of the HSB 8 designated by the content of the WNR 25. Since there is one EAR 9, when such a storing operation is continuously effected and if the setting timings of setting the afore-mentioned priority flip-flops Popfch and Popst overlap, the setting of the Popfch of the succeeding instruction is delayed, as illustrated in the time chart of Fig. 5A. This wastes machine cycles and reduces the processing ability of the data processor. According to the present invention, the priority flip-flops Popfch and Popst can be simultaneously processed as shown in Fig. 5B, thereby preventing delay of the processing by a priority flip-flop Popfch of a succeeding instruction due to a priority flip-flop Popst of a preceeding instruction. An embodiment of the present invention is explained with reference to the drawings. Figure 6 illustrates a buffer storage and the like used in a system as an embodiment of the present invention. In Fig. 6, reference numerals 8, 9, 21, 22, 23-0, 23-1, ..., 23-F, 24, 25, 30-0, 30-1, ..., 30-F designate the same parts as those explained with reference to Fig. 3. Reference numerals 28-0, 28-1, ..., 28-F designate selectors (SEL) which have the function of switching the address data for accessing a data portion 22 of an HSB 8. In this embodiment, the tag portion 21 of the HSB 8 is accessed by using bits 20 through 25 of an EAR 9. Regarding the data portion 22 of the HSB 8, it is possible to select either use of bits 20 through 25 of the EAR 9 as address data for each way or use of bits 20 through 25 of an OPAR 11 as address data. The circuits for this selection are the SEL 28-0, 28-1, ..., 28-F which are controlled by the output signal of the WNR 25. That is, controlled so that only one way, in the data portion 22 of the HSB 8, designated by the content of the WNR 25, is accessed by using the bits 20 through 25 of the OPAR 11 explained with reference to Fig. 4. The simultaneously processed read operation is controlled so that the tag portion 21 of the HSB 8 and the data portion 22, except for the way designated by the content of the WNR 25, are accessed by using bits 20 through 25 of the EAR 9. By controlling the operation in this way, the read operation from ways other than the above-mentioned way to be written-in and the write operation are executed in the same machine cycle. Another embodiment of the present invention will now explained. The embodiment is implemented by using circuits including an OR circuit 26, a way number register valid bit (WNRV) 27, and a gate circuit 29, shown in Fig. 6. In the above-mentioned embodiment, when buffer-storage control of the "store-through" type is effected, if the storing address is not memorized in the tag portion 21 of the HSB 8, the WNRV 27 is set by using the OR signal of the coincidence signals C0, C1, ..., CF output from the comparators 23-0, 23-1, ..., 23-F corresponding to the ways 0 through F, considering the fact that in this case it is not necessary to write in the data portion 22. If no coincidence signal is obtained from any comparator, the WNRV 27 is kept in an "off" condition. The gate circuit 29 is controlled by the thus obtained WNRV signal so that all the SEL 28-0, 28-1, ..., 28-F select the bits 20 through 25 of the EAR 9. In a write operation controlled in the above-mentioned manner, if no way in the tag portion 21 of the HSB 8 memorizes the storing address and it is not necessary to effect an actual write operation, the read access is allowed unconditionally in the same machine cycle. Even when an actual write operation is effected, it is possible to effect the write operation and a read operation in the same machine cycle if the ways in the tag portion 21 and the data portion 22 do not coincide. Thereby, the processing ability of the system is increased. In the read operation, if the read address is memorized in the tag portion 21 of the HSB 8 and the way number thereof coincides with the way number for the write operation, the system is controlled so that the read operation is again executed by a way-coincidence detecting circuit shown in Fig. 7. In Fig. 7, reference numeral 12 designates a decoder for decoding the way number, reference numerals 13 AND circuits, and reference numeral 14 an OR circuit. In the circuit of Fig. 7, when the read address and the write address use the same way numbers of HSB TAG 21, each of the coincidence outputs C0, C1, ..., CF of the comparators 23-0, 23-1, ..., 23-F for every way of the HSB 8 relating to the read address, each of the outputs which relate to the write address and which are obtained from the decoder 12 decoding the contents of the WNR 25 shown in Fig. 6, and the WNRV 27 corresponding to the content of the WNR 25 are logically operated by the AND circuit 13, so that the re-read request signal REQ corresponding to the above-mentioned read address is generated. As mentioned above in detail, in a data processing system which effects pipeline processing according to the present invention, it is possible to execute a read operation and write operation of a buffer storage in the same machine cycle. Especially in a buffer-storage control system of the "store-through" type, when the storing address is not memorized in the buffer storage, the read operation is executed unconditionally in the same machine cycle. Even when the write operation is effected, the read operation is executed again only when the way of the tag portion of the buffer storage coincides with the way of the read address. Therefore, the pipeline processing in the above-mentioned data processor can be efficiently executed, and the processing ability of the overall system can be increased.

Claims: A buffer-storage control system in a data processor comprising a main storage (MSU) and a buffer storage (8) which has a tag portion (21) and a data portion (22), each portion composed of a plurality of ways, characterised in that the buffer-storage control system is so constituted that the tag portion (21) and the data portion (22) can be independently accessed, and that the data portion (22) is so constituted for every way that it is possible to select one of a plurality of address paths and to select an address for a read access and an address for a write access for every way, whereby data is stored in the buffer storage (8) in a data storage operation comprising a first step of accessing the tag portion and checking whether or not an address block exists to which a storage operation is to be carried out and a subsequent second step in which data is written to the data portion (22), the arrangement being such that, except where the ways are the same, the second step of one data storage operation and the first step of a succeeding data storage operation can be carried out simultaneously and in parallel. A buffer-storage control system according to claim 1, comprising comparators (23-0 ... 23-F) for every way, each of which comparators compares an address for an access operation and an address stored in the corresponding way, and a way number register (25) for memorizing the number of a way corresponding to the comparator which outputs a coincidence signal, the output of the way number register (25) being used to select the address in every way of the data portion (22). A buffer-storage control system according to claim 2, further comprising selectors (28-O ... 28-F), each of which is associated with a respective way of the data portion (22) and each of which selects one of two addresses input thereto from an effective address register (9) and an operand address register (11) of a storage control unit (7) of the control system, the selectors being controlled on the basis of the output of the way number register (25). A buffer-storage control system according to claim 3, further comprising an OR circuit (26) which receives signals of valid bits from the ways of the tag portion (21), and a gate circuit (29) which passes the output of the way number register (25) in accordance with the output of the OR circuit. A buffer-storage control system according to any of claims 2 to 4, further comprising a way-coincidence detecting circuit (13) which detects coincidences between the way number memorized in the way number register (25) and the number of the way memorizing address which corresponds to an input address.

Inventors: TONE, HIROSADA
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: G06F12
IPC codes: G06F12, G06F13