SEMICONDUCTOR DEVICE PAD AREA PROTECTION STRUCTURE

Abstract: Semiconductor device structure comprising a metalization pattern (16) having a pad area (18). The structure provides protection to the pad area (18) from attack by a corrosive environment. The structure comprises a semiconductor body (10) having a first surface (12), there being a first layer (14) of dielectric material (14) covering at least a portion of the first surface (12). A metalization pattern (16) having a pad area (18) covers a portion of the first layer (14) of dielectric material (14). Access pad structure (20 (22, 40, 44)) covers the pad area (18) for providing an access pad (20) and for protecting the pad area (18) from attack by a corrosive environment. The access pad structure (20 (22, 40, 44)) comprises conductive material (40, 44) impervious to attack by the corrosive environment.

Description: SEMICONDUCTOR DEVICE PAD AREA PROTECTION STRUCTURE BACKGROUND OF THE INVENTION The present invention relates to semiconductor device structures and, more particularly, to a structure for providing protection to a pad area from attack by a corrosive environment. Hot caustic etchants used to form structures in semiconductor substrates attack commonly- used pad materials and, for example, cause lift-off of pad features. The present invention prevents this attack of underlying materials within access pads, thereby resulting in greatly improved device integrity and reliability. Although the present invention is partic¬ ularly applicable to protecting a pad area from caustic etches, it also provides protection from other corrosive environments. For example, when the semi¬ conductor device is employed in an environment of corrosive gases, damage to the pad area is prevented by the present invention. SUMMARY OF THE INVENTION The present invention is a semiconductor device structure comprising a metalization pattern having a pad area. The structure provides protection to the pad area from attack by a corrosive environment. The structure OMPI WΠΌ comprises a semiconductor body having a first surface, there being a first layer of dielectric material covering at least a portion of the first surface. A metalization pattern having a pad area covers a portion of the first layer of dielectric material. Access pad structure covers the pad area for providing an access pad and for protecting the pad area from attack by a corrosive environment. The access pad structure com- • prises conductive material impervious to attack by the corrosive environment. BRIEF DESCRIPTION OF THE DRAWINGS The Figures illustrate alternate embodiments of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The Figures illustrate a semiconductor body 10 having a first surface 12, at least a portion of first surface 12 being covered by a layer 14 of dielectric material. Semiconductor body 10 may comprise silicon. Dielectric layer 14 may comprise silicon dioxide or silicon nitride. A metalization pattern 16 such as a serpentine pattern having a pad area 18 covers a portion of first layer 14 of dielectric material (although not shown in the cross-sections of the Figures, metalization pattern 16 and pad area 18 are typically connected) . Metalization pattern 16 and pad area 18 may comprise permalloy or nickel-iron typically composed of 80% nickel and 20% iron. Materials such as permalloyare susceptible to attack by hot caustic etches which may be used to form structures in semiconductor bodies 10. For example, etchants may be applied through vias 24 cut to first surface 12 on either side of metalization pattern 16 in order to undercut the vias and the metalization pattern. Such a process forms a depression 26 under metalization pattern 16 so that the metalization pattern is suspended over depression 26 (see Figure 2) . Access pad structure 20 covers pad area 18 for providing an access pad and for protecting pad area 18 from attack by a caustic etch or other corrosive environment. Access pad structure 20 comprises a conductive material impervious to attack by the caustic etch. Prior art access pads 20 were susceptible to attack by the caustic etch, thus causing lift-off and other deterioration to portions of access pad 20 and/or pad area 18. In the embodiment of Figure 1 access pad structure 20 comprises a second dielectric layer 22 impervious to the caustic etch covering the metalization pattern and a portion of pad area 18. The remainder of pad area 18 and at least a portion of second dielectric layer 22 are covered by a conductive material impervious to the caustic etch. More specifically, as illustrated in the Figures, pad area 18 comprises first and second surfaces 28 and 30 respectively. First surface 28 covers a portion of first dielectric layer 14, Second surface 30 is substantially parallel to and opposite first surface 28. Pad area 18 has a periphery 32. Second surface 30 has an outer portion 34 substantially adjacent to periphery 32, second surface 30 also having an inner portion 36 within outer portion 34. As also illustrated in the Figures, second dielectric layer 22 impervious to the caustic etch covers not only metalization pattern 16 but also periphery 32 and outer portion 34 of the second surface of pad area 18. In Figure 1 access pad 20 comprises conductive structure 40 impervious to the caustic etch and having a first surface 38 covering inner portion 36 of second surface 30 of pad area 18 and a portion of second dielectric layer 22. Conductive structure 40 has a second surface 42 substantially. opposite first surface 38. Conductive structure 40 may comprise a layer of -chromium 40 and may include an optional layer 44 of gold covering at least a portion of second surface 42 of conductive structure 40. Alternately, as illustrated in Figure 2, access pad structure 20 may comprise a first layer 46 of chromium, first layer 46 having a periphery 48, a first surface 50 and a second surface 52, at least a portion of first surface 50 covering at least a portion of pad area 18. Second surface 52 has an outer portion 54 substantially adjacent to periphery 48, second surface 52 also having an inner portion 56 within outer portion 54. Access pad structure 20 of Figure 2 comprises second dielectric layer 22 impervious to the corrosive environment covering metalization pattern 16 and periphery 48 and outer portion 54 of second surface 52 of first chromium layer 46. The access pad structure 20 of Figure 2 further comprises conductive structure impervious to the corrosive environment covering inner portion 56 of second surface 52 of first chromium layer 46 and a portion of second dielectric layer 22. In the embodiment of Figure 2, conductive structure 20 impervious to the corrosive environment and covering inner portion 56 and a portion of second dielectric layer 22 may comprise a second layer 58 of chromium having first and second surfaces 60 and 62 respectively. First surface 60 may cover inner portion 56 of second surface 52 of first chromium layer 46 and at least a portion of second dielectric layer 22. Second surface 62 of second chromium layer 58 is substantially opposite first surface 60 of second chromium layer 58. In the structure of Figure 2 an optional gold layer 44 is shown covering at least a portion of second surface 62 of second chromium layer 58. As was previously indicated pad area 18 may comprise permalloy. In fact, it was the existence of permalloy metalization pattern 16 (and its associated pad area 18 deposited and etched to configuration simultaneously with metalization pattern 16) that gave rise to the need for the present invention. That is, permalloy elements are particularly well suited for sensing and other applications but are easily attacked by corrosive environments. In the process of developing the present invention, it has been found that chromium and gold are particularly suitable for use in structuring the access pad since both of these materials are highly resistant to corrosive environ¬ ments. In addition, it has been found that silicon nitride as opposed to other types of dielectric materials is particularly resistant to hot caustic etches such as potassium hydroxide (KOH) and other corrosive environments. Structures in accordance with the present invention may be fabricated using standard processing techniques, examples of which follow below. These processes and the materials and dimensions given below and in other portions of the present application are illustrative only and are not to be taken as limiting the present invention. Beginning with a semiconductor body or substrate 10 such as silicon, a layer of silicon nitride is sputter deposited using standard techniques onto first surface 12. An 800-1200 angstrom thick layer of permalloy is then sputtered onto layer 12 of silicon nitride. The layer of permalloy will ultimately form metalization pattern 16 and pad ' area 18. For the embodiment of Figure 2, an approxi¬ mately 2000 angstrom thick layer 46 of chromium is then sputter deposited. Using standard photolithographic techniques, the chromium and permalloy layers are delineated to their proper configurations such as those illustrated in Figure 2. As illustrated, chromium layer 46 is left covering only a portion of access pad 18. Chromium layer 46 typicaliy does not cover permalloy runs (not shown) or serpentine pattern 16. An encapsulating layer of silicon nitride is then sputter deposited, and standard photolitho- graphic techniques are used to plasma etch the silicon nitride layer 22 in order to cut a via to inner portion 56 of second surface 52 of first chromium layer 46. Second layer 58 of chromium is then sputter deposited and, if gold layer 44 is used, it is also sputter deposited. Using standard photo¬ lithography, optional gold layer 44 and chromium layer 58 are then delineated. The embodiment of Figure 1 differs in part from the embodiment of Figure 2 in that the embodi¬ ment of Figure 1 uses only one layer 40 of chromium whereas the embodiment of Figure 2 uses two layers 46 and 58 of chromium. Either embodiment has been found to be satisfactory. The embodiment of Figure 2 provides more effective protection to the underlying layers in that, when the via is etched through second dielectric layer 22, the first layer of chromium 46 in the embodiment of Figure 2 protects permalloy, pad 18 from attack by the etchant used to etch the via (the permalloy pad 18 can be attacked by the etchant if great care is not used) . The structure of either Figure 1 or Figure 2, however, are examples of structures which provide protection to pad area 18 from attack by corrosive environments. To form the structure in silicon as illustrated in Figure 2, vias 24 are etched through dielectric layers 22 and 14 down to first surface 12 of semiconductor body 10. Hot caustic etch (typically KOH at 90 degrees C for 1 hour) may then be used to anisotropically etch depression 26 below the encap¬ sulated metalization pattern 16. The silicon etches preferentially along certain crystal planes to form a bridge or cantilever of the encapsulated metalization pattern. Such a bridged or cantilevered structure substantially isolates metalization pattern 16 from semiconductor body 10 and, being very thin, forms a highly sensitive thermal transducer or transmitter having a very fast thermal response time. As was previously indicated, in addition to providing an access pad that is resistant to hot caustic etch, the access pads of the present invention provide protection from other corrosive environments. For example, if sensors such as illustrated in Figure 2 are used in sensing the flow of corrosive gases, access pad structures such as illustrated in the Figures will be resistant to deterioration by such gases.

Claims: CLAIMS The embodiments of the invention in which an exclusive property or right is claimed are defined as follows: 1. A semiconductor device structure comprising a metalization pattern having a pad area, the structure providing protection to the pad area from attack by a corrosive environment, comprising: a semiconductor body having a first surface; a first layer of dielectric material covering at least a portion of the first surface; a metalization pattern having a pad area covering a portion of the first layer of dielectric material; and access pad means covering the pad area for providing an access pad and for protecting the pad area from attack by a corrosive environment, the access pad means comprising conductive material impervious to the corrosive environment. 2. The apparatus of claim 1 wherein the pad area comprises permalloy. 3. The apparatus of claim 1 wherein the access pad means comprises a second dielectric layer impervious to the corrosive environment covering the metalization pattern and a portion of the pad area, the remainder of the pad area and at least a portion of the second dielectric layer being covered by the conductive material OMPI impervious to the corrosive environment. 4. The apparatus of claim 3 wherein the pad area comprises permalloy. 5. The apparatus of claim 4 wherein: the semiconductor body comprises silicon; and the second layer of dielectric comprises silicon nitride. 6. The apparatus of claim 3 wherein: the semiconductor body comprises silicon; and - the second layer of dielectric comprises silicon nitride. 7. The apparatus of claim 1 wherein the- access pad means comprises: a first layer of chromium having a periphery and first and second surfaces, at least a portion of the first surface covering at least a portion of the pad area, the second surface having an outer portion substantially adjacent to the periphery of the layer, the second surface also having an inner portion; a second dielectric layer impervious to the corrosive environment covering the metalization pattern and the periphery and the outer portion of the second surface of the first chromium layer; and conductive means impervious to the corrosive environment covering the inner portion of the second surface of the first chromium layer and a portion of the second dielectric layer. 8. The apparatus of claim 7 wherein the pad area comprises permalloy. 9. The apparatus of claim 8 wherein: the semiconductor body comprises silicon; and the second layer of dielectric comprises • silicon nitride. 10. The apparatus of claim 7 wherein: the semiconductor body comprises silicon; and the second layer of dielectric comprises silicon nitride. 11. The apparatus of claim 7 wherein the conductive means comprises a second layer of chromium having first and second surfaces, the first surface covering the inner portion of the second surface of the first chromium layer and at least a portion of the second dielectric layer, the second surface of the second chromium layer . being substantially opposite the first surface of the second chromium layer. 12. The apparatus of claim 11 wherein the pad area comprises permalloy. - - 13. The apparatus of claim 12 wherein: the semiconductor body comprises silicon; and the second layer of dielectric comprises silicon nitride. 14. The apparatus of claim 11 wherein: the semiconductor body comprises silicon; and the second layer of dielectric comprises silicon nitride. 15. The apparatus of claim 11 wherein the conductive means comprises a gold layer covering at least a portion of the second surface of the second chromium layer. 16. The apparatus of claim 1 wherein: the pad area comprises first and second sur- faces, the first surface covering a portion of the first dielectric layer, the second surface being substantially parallel to and opposite the first surface, the pad area having a periphery, the second surface having an outer portion substantially adjacent to the periphery, the second surface also having an inner portion within the outer portion; the access pad means comprises: a second layer of dielectric impervious to the corrosive environment and covering the' -' ■ < ■ ' metalization pattern including the periphery OMPI and the outer portion of the second surface of the pad area; and conductive means impervious to the corrosive environment and having a first surface covering the inner portion of the second surface of the pad area and a portion of the second dielectric layer, the conductive means having a second surface substantially opposite the first surface. 17. The apparatus of claim 16 wherein the conductive means comprises a layer of chromium. 18. The apparatus of claim 16 wherein the conductive means comprises a layer of gold covering at least a portion of the second surface of the conductive means. 19. The apparatus of claim 16 wherein the access comprises permalloy. 20. The apparatus of claim 19 wherein: the semiconductor body comprises silicon; and the second layer of dielectric comprises silicon nitride. 21. The apparatus of claim 16 wherein: the semiconductor body comprises silicon; and- ' - ' the second layer of dielectric comprises silicon nitride. OMPI 22. A semiconductor device structure comprising a metalization pattern having a pad area, the structure providing protection to the pad area from attack by a corrosive environment, comprising: a semiconductory body having a first surface; a first layer of dielectric material covering at least a portion of the first surface; a metalization pattern having a pad area covering a portion of the first layer of dielectric material; and access pad means covering the pad area, the access pad means comprising.a second dielectric layer impervious to the corrosive environment covering the metalization pattern and a portion of the pad area, the remainder of the pad area and at least a portion of the second dielectric layer being covered by conductive material impervious to the corrosive environment. 23. The apparatus of claim 22 wherein the pad area comprises permalloy. 24. The apparatus of claim 23 wherein: the semiconductor body comprises silicon; and the second layer of dielectric comprises silicon nitride. 25. The apparatus of claim 24 wherein the conduc¬ tive material comprises chromium. 26. The apparatus of claim 22 wherein: the semiconductor body comprises silicon; and the second layer of dielectric comprises silicon nitride. 27. The apparatus of claim 26 wherein the conduc¬ tive material comprises chromium. 28. The apparatus of claim 22 wherein the conduc- tive material comprises chromium.

Inventors: HOLMEN JAMES O, WURM MARK A, HOLMEN, JAMES, O., WURM, MARK, A.
Applicants: HONEYWELL INC, HONEYWELL INC.
Application year: 1984
Main classification: H01L23
IPC codes: H01L23