AN IMPROVED METHOD OF MANUFACTURING FLAT PANEL BACKPLANES, DISPLAY TRANSISTORS AND DISPLAYS MADE THEREBY

Abstract: An improved method of manufacturing active matrix display backplanes with thin film transistors thereon and a drive scheme therefor. A refractory metal covers the indium tin oxide (ITO) layer, patterned to form a gate electrode for the transistors and to protect the pixel pad ITO during forma­ tion of the transistors. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

Description: The present invention pertains to thin film transistors and to an improved flat panel display comprising such transistors and method of making the same. More particularly, the present invention is directed to a method of making improved flat panel display backplanes and the switching transistors thereon. In recent years there has been growing interest in flat panel displays, such as those which employ liquid crystals, electrochromic or electroluminescence, as replacements for conventional cathode ray tubes (CRT). The flat panel displays promise lighter weight, less bulk and substantially lower power consumption than CRT's. Also, as a consequence of their mode of operation, CRT's nearly always suffer from some distortion. The CRT functions by projecting an electron beam onto a phosphor-coated screen. The beam will cause the spot on which it is focused to glow with an intensity proportional to the intensity of the beam. The display is created by the constantly moving beam causing different spots on the screen to glow with different intensities. Because the electron beam travels a greater distance from its stationary source to the edge of the screen than it does to the middle, the beam strikes various points on the screen at different angles with resulting variation in spot size and shape (i.e. distortion). Flat panel displays are inherently free of such distortion, because each pixel element receives the same power. In the manufacture of flat panel displays the circuit elements are deposited and patterned, generally by photolithography, on a substrate, such as glass. The elements are deposited and etched in stages to build a device having a matrix of perpendicular rows and columns of circuit control lines with a pixel contact and control element between the control line rows and columns. The pixel contact has a medium thereon which is a substance that either glows (active) or changes its response to ambient light (passive) when a threshold voltage is applied across the medium control element. The medium can be a liquid crystal, electroluminescent or electrochromic materials such as zinc sulfide, a gas plasma of, for example, neon and argon, a dichroic dye, or such other appropriate material or device as will luminesce or otherwise change optical properties in response to the application of voltage thereto. Light is generated or other optical changes occur in the medium in response to the proper voltage applied thereto. Each optically active medium is generally referred to as a picture element or "pixel". The circuitry for a flat panel display is generally designed such that the flat panel timeshares, or multiplexes, digital circuits to feed signals to one row and column control line of the pixels at a time. Generally one driving circuit is used for each row or column control line. In this way a subthreshold voltage can be fed to an entire row containing hundreds or thousands of pixels, keeping them all dark or inactive. Then a small additional voltage can be supplied selectively to particular columns to cause selected pixels to light up or change optical properties. The pixels can be made to glow brighter by applying a larger voltage or current or a longer pulse of voltage or current. Utilizing liquid crystal displays (LCD's) with twisted nematic active material, the display is substantially transparent when not activated and becomes light absorbing when activated. Thus, the image is created on the display by sequentially activating the pixels, row by row, across the display. The geometric distortion described above with respect to CRT's is not a factor in flat panel displays since each pixel sees essentially the same voltage or current. One of the major problems that arises with respect to the prior art method of manufacture of backplanes for active matrix displays (e.g. those employing thin film transistors at each pixel) is that they generally suffer production yield problems similar to those of integrated circuits. That is, the yields of backplanes produced are generally not 100% and the yield (percentage of backplanes with no defects) can be 0% in a worst case. High quality displays will not tolerate any defective transistors or other components. Also, larger size displays are generally more desirable than smaller size displays. Thus, a manufacturer is faced with the dilemma of preferring to manufacture larger displays, but having to discard the entire product if even one pixel is defective. In other words, the manufacturer suffers a radically increased manufacturing cost per unit resulting from decreasing usable product yield. Typical prior art devices comprising thin film transistors are disclosed in 1982 SID INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Society for SID Information display, 1st Edition, May 1982, pages 40-41, Lewis Winner, Coral Gables, Florida, US; YUKIOSHI OKUBO et al.: "7.4/3:05 P.M.: Large scale LCDs addressed by a-Si TFT array" and in IBM TECHNICAL DISCLOSURE BULLETIN, vol 21, no. 4, September 1978, pages 1666-1667, New York, US; S.G.CHAPMAN: "Self-passivated thin film transistor". These problems of increased cost and decreased yield are dramatically improved in the present invention by providing a method of manufacture of active display backplanes, including the display transistors with a greatly reduced number of defects. According to the present invention, there is provided a thin film transistor (42), comprising: a substrate (56, 56'); a gate electrode (44, 44') formed on said substrate and having at least one exposed edge (68); a gate insulator (64, 64') formed on said gate electrode; a semiconductor material (66, 66') formed on said insulator; a dielectric (70, 70') formed a) to overlie the edge of said gate insulator and said semiconductor material, or b) to overlie said edge of said gate electrode with a portion of said gate insulator and said semiconductor material overlying said dielectric, said dielectric being formed with a central portion thereof removed over a substantially planar portion of said gate electrode, with said insulator and said semiconductor material formed on at least said central portion of said gate electrode; a drain electrode (54, 54') formed on at least a portion of said dielectric and on said semiconductor material adjacent said edge of said gate electrode; and a source electrode (48, 48') formed on another portion of said dielectric and on said semiconductor material and spaced from said drain electrode. The invention further provides a process specially adapted for the manufacture of thin film transistors comprising: providing a substrate (56, 56'); depositing a gate electrode (44, 44') on said substrate having at least one exposed edge (68); and either a) depositing a gate insulator (64, 64') on said gate electrode; depositing a semiconductor material (66, 66') on said gate insulator; depositing a dielectric (70, 70') to overlie the edge of said gate insulator and said semiconductor material; and removing a central portion of said dielectric over a substantially planar portion of said gate electrode, said gate insulator and said semiconductor material being formed over at least said central portion of said gate electrode; or b) depositing a dielectric (70, 70') to overlie at least said edge of said gate electrode; removing a central portion of said dielectric over a substantially planar portion of said gate electrode; depositing a gate insulator (64, 64') on at least said central portion of said gate electrode and overlying said dielectric; and depositing a semiconductor material on said gate insulator, overlying at least said central portion of said gate electrode and overlying said dielectric; and, in either case: depositing a drain electrode (54, 54') on at least a portion of said dielectric and on said semiconductor material adjacent said edge of said gate electrode; and depositing a source electrode (48, 48') on at least a portion of said dielectric and on said semiconductor material and spaced from said drain electrode. As will be seen, to reduce shorts between the gate and the source or drain, a dielectric is deposited over the gate or the gate, gate insulator and semiconductor material. The dielectric is then etched away in the central planar portion of the gate region leaving a region of dielectric overlying the edge of the gate electrode. Edge shorting is eliminated since the following layers are deposited only on the planar portion with the edges isolated therefrom. Also provided is a matrix display backplane comprising a substrate and a plurality of transistors according to the invention, and a method of manufacturing the same in accordance with the above. The present invention will now more fully be described with reference to Figs. 1-11 of the accompanying drawings, wherein: Fig. 1 is a plan view schematic representation of an active matrix display backplane made by a prior art method; Fig. 2 is a cross-section of one transistor of the prior art backplane; Fig. 3 is a plan view schematic representation of one embodiment of a matrix display of the present invention; Fig. 4 is a first embodiment of a backplane transistor of the present invention taken along the line 4-4 of Fig. 3; Fig. 5 is a second embodiment of the backplane transistor of the present invention; Figs. 6-10 are partial plan views of the display backplane manufacturing steps; and Fig. 11 is a schematic diagram of a matrix display drive circuit. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now more particularly to Fig. 1, there is shown a schematic representation of an active matrix flat panel display device 10 made in accordance with conventional photolithographic techniques. One such device 10 and the manufacture thereof is more fully described in Application of Amorphous silicon Field Effect Transistors in Addressable Liquid Crystal Display Panels, A.J. Snell et al., Applied Physics , No. 24, p. 357, 1981. The device 10 includes a substrate 12, sets of contact pads 14 and 16, sets of control lines 18 and 20, and, in this particular example of the prior art, transistors 22 and pixel back contacts 24. The substrate 12 commonly employed in these devices is formed from glass. The control lines 18 and 20 are organized into a matrix of rows 18 and columns 20. The control line rows 18 in this device 10 serve as gate electrodes and the control line columns 20 as source connections. One contact pad 14 is connected to each end of the row control lines 18. One contact pad 16 is connected to each end of the column control lines 20. The display drive control (not shown) is connected to the sets of pads 14 and 16. At each matrix crossover point 26, where a row line 18 and a column line 20 cross, one switching element, transistor 22 is formed to connect the row line 18 and column line 20 to the pixel back contacts 24. The active medium is deposited at least on the contacts 24 which will optically change properties in response to the combined voltages or currents in the respective crossover point 26 formed by the row 18 and column 20. The active medium at a given crossover point 26 will appear as a square or dot in the overall checkerboard type matrix of the display 10. The actual size of the transistors 22 and the contacts 24 are not now drawn to scale, but are shown schematically for illustration only. It should be noted that theoretically there is no limit on the number of rows 18 and columns 20 that can be employed, only a portion of which are illustrated in Fig. 1. Therefore, there is also no theoretical limit on the outside dimensions of such a device 10. However, the present state of the lithographic art places a practical limit on the outside dimensions of these devices. The present alignment techniques allow display devices to be manufactured approximately five inches on a side 28. The problem encountered by the prior art method of manufacture is that if the array of device 10 contains any defective pixel transistors 18 or other circuit elements causing a pixel to be inoperative, it must be discarded. Referring in detail to Fig. 2, several problems occur when the switching element, transistor 22 is manufactured. The substrate 12 is a substantial portion of the backplane cost and hence an inexpensive soda-lime glass is generally utilized. In addition to the problems associated with the source and drain shorting to the gate, it has been demonstrated by liquid crystal display manufacturers that the high sodium concentration can poison the liquid crystal material by diffusing through the overlying ITO layer and hence an SiO₂ suppression layer 30 is generally formed on the substrate 12. There are some high quality low sodium types of substrates available, which would not need the suppression layer 30. An ITO layer 32 is formed and etched to provide an ITO free area on which the gate 18 is deposited. Following the deposition of the gate 18, a gate insulator layer 34 is deposited. Although a smooth uniform coverage of the gate 18 by the insulator 34 is illustrated, in production the gate 18 has or can have sharp edges which lead to pin holes or thinning of the insulator 34 at the gate edges. The source and drain metals can short to the gate 18. The thinning or pin holes produce transistors 22, which if operative, do not have uniform operating characteristics and hence the backplane is worthless. One attempt to solve this problem, is to make the gate 18 very thin, but the resistivity is then too high to make the large arrays necessary for the backplane. A second attempt to solve the probem, is to make the gate insulator 34 very thick, but this decreases the gain of the transistor 22 and is also self defeating. An amorphous silicon layer 36 is then deposited, with the source 20 and a drain 38 deposited thereover. A passivating layer (not shown) would be deposited over the completed structure to complete the transistor 22. During operation the activation of the source 20 and the gate 18 couples power through the silicon alloy 36 to the drain and hence to the contact pad 24 formed by the ITO layer 32. In processing the backplane to form the transistor 22, the ITO layer 32 is subjected to numerous processing steps, both depositing material and etching the material away. This can lead to nonuniformity of the ITO layer 32 which can also cause the backplane to be defective. These problems are overcome by the method and resulting backplane and transistor structure employed in the present invention, which will now be discussed with reference to Figs. 3-10. A matrix display 40 of the present invention is illustrated schematically in Fig. 3. A plurality of transistors 42 are each coupled in columns by one of a plurality of gate lines 44 to one of a plurality of gate contact pads 46. The transistors 42 are each coupled by one of a plurality of source lines 48 to one of a plurality of source gate pads 50. Each transistor 42 is also coupled to a respective one of a plurality of pixels 52 by a respective drain electrode 54. Referring now more particularly to Fig. 4, there is shown a schematic representation of one preferred embodiment of the transistor 42 made in accordance with the present invention. A glass substrate 56 includes a barrier SiO₂ layer 58 thereon. The detailed deposition steps will be described with respect to Figs. 6-10. An ITO layer 60 is deposited and then a refractory metal layer 62 is deposited on the ITO layer 60. The layers 60 and 62 are etched to form the gate electrode 44. A gate insulator 64 and a semiconductor material 66 are sequentially deposited over the gate 44. The material 66 preferably is an amorphous silicon alloy. To avoid the possibility of any gate to source or drain shorts at gate edges 68, an intermetal dielectric 70 is deposited over the gate 44, the gate insulator 64 and the semiconductor 66. The dielectric 70 is deposited to a sufficient thickness to ensure that no shorts or thin spots are formed between the edges 68 of the gate 44 and the source 48 and the drain 54. The dielectric 70 is etched away only on a substantially planar central region 72 of the semiconductor layer 66. This insures uniform operating characteristics for the transistors 42 in the backplane array. A passivating layer 74 is deposited over the whole structure to complete the structure of the transistor 42. During all of the transistor processing steps, the refractory metal layer 62 remains over a pixel contact pad 76 upon which the active material of the pixel 52 is deposited. As a final step, before the active medium (not shown) is added to the backplane to complete the display, the refractory metal is etched off of the pixel pad 76 leaving the ITO layer 60 exposed after all the processing has been completed. An alternate embodiment of the transistor 42' is illustrated in Fig. 5. The major difference is that the intermetal dielectric 70' is deposited before the gate insulator 64', but the dielectric 70' performs the same function as in the Fig. 4 embodiment, as does the refractory metal layer 62'. The detailed deposition procedure will now be described, referring to Figs. 3, 4 and 6-10. Although generally LCD users purchase the substrate 56 with the SiO₂ barrier layer 58 and ITO layer 60 thereon, it is preferred that the glass substrate 56 be purchased without any of the layers deposited thereon. This avoids any nonuniformity or other defects and also allows the layers 58, 60 and 62 to be deposited in one deposition run utilizing semiconductor standards. Defects in the ITO layer 60 under the gate 44 can cause shorts. The substrate 56 is first cleaned, such as by a dionized water rinse and dried. The surface of the substrate 56 is then sputter etched which is followed by depositing the SiO₂ layer 58, to a thickness in the range of about 250-2000Å (10Å=1nm) and preferably about 500 °A, the ITO layer 60 to a thickness in the range of about 100-500Å and preferably about 300Å and then the refractory metal layer 62 to a thickness in the range of 500-2000Å and preferably about 1000Å. The refractory metal 62 is preferably Ni x Cr 1-x , O ≦ X ≦ .8, and preferably Ni₆₀Cr₄₀. Other refractory metals and alloys such as Ti, TiW, Mo or Ta can also be utilized to meet the following functions. The refractory metal 62 shields the ITO layer 60 from the processing gases and etchants to insure that the thickness, integrity, resistivity and optical characteristics of the ITO layer 60 are retained. Therefore the refractory metal must withstand the gas plasmas containing silane (SiH₄), which can be at processing temperatures of greater than 200°C which an unprotected ITO layer 60 will react with. For example, SiH₄ is generally utilized as one of the gases to produce silicon nitride (Si₃N₄) and hence would attack the ITO layer 32 in forming the prior art transistor 22 (Fig. 2). The other steps as described below include metal deposition, plasma etching, chemical etching and photoresist stripping. The refractory metal 62 must have good adhesion to the ITO layer 60 as well as the gate insulator 64, the intermetal dielectric 70 and the drain 54. When light is passed through the substrate 56, then the gate 44 provides a required gate light blocking function since the transistor 42 is light sensitive. If light is directed through the other side of the backplane then the passivating layer 74 will include a light blocking material or another light blocking layer will be added. The refractory metal 62 must be etchable from the ITO layer 60 without effecting it when the structure of the transistor 42 is complete. Further, the refractory metal must serve as a stable gate 44 and should have a low sheet resistivity. For example, Ni₆₀Cr₄₀ about 1000Å thick has a sheet resisitivity of about 10 ohms/square which is necessary for the long gate lines in the backplane. A photoresist is applied to the refractory metal layer 62 which is then soft baked. The photoresist is aligned and exposed through a mask and then is developed and hard baked. The metal layer 62 and the ITO layer 60 are then successively etched, rinsed and dried. Then the photoresist is stripped from the substrate, which is then rinsed and dried leaving the pattern shown in Fig. 6. This leaves a pattern of gates 44, pixel pads 76 (Fig. 4) and contact pads 46 and 50 (Fig. 3). The gate insulator 64 and the semiconductor layer 66 are now sequentially deposited, preferably in a plasma at a substrate temperature of about 275°C. The insulator layer 64 preferably is Si₃N₄ deposited in the range of about 500 to 5000Å thick and preferably about 2500Å thick. The semiconductor layer 66 preferably is an amorphous silicon alloy and is preferably deposited from SiH₄ to a thickness of about 300 to 5000Å and preferably about 2500Å. A photoresist is spun on, soft baked, aligned, exposed, developed and etched. The layers 64 and 66 are preferably plasma etched in a carbon tetrafluoride (CF₄) plasma. The photoresist is then stripped, rinsed and dried. This results in the active semiconductor areas 66 separated along the lengths of the gates 44 as shown in Fig. 7. The intermetal dielectric 70 is then deposited, preferably in a plasma with a substrate temperature of 250°C. The dielectric preferably is SiO₂ with a thickness in the range of 2000-10,000Å and preferably about 5000Å. The photoresist is then applied, soft baked, aligned and exposed. The resist is then developed out from the areas over the central portion 72 of the semiconductor layer 66, the pixel pads 76 and the gate and source contact pads 46 and 50. After hard baking the exposed SiO₂ layer is etched, and then the resist is stripped, rinsed and dried to leave the central portions 72 and the pixel pads 76 exposed as shown in Fig. 8. The gate and source contact pads 46 and 50 (Fig. 3) are also exposed. A plurality of regions 78 between the exposed portions 72 of the semiconductor layer 66 are left covered by the intermetal dielectric layer 70 which adds additional isolation to the transistors 42 when the source electrodes 48 are deposited over these areas (Figs. 3 and 9). An aluminum alloy is then sputter deposited or evaporated to a thickness in the range of about 500 to 5000Å and preferably about 2500Å. A photoresist is then applied, soft baked, aligned, exposed, developed and hard baked. The exposed alloy is then etched. The photoresist is then stripped, rinsed and dried to leave the source and drain lines 48 and 54 as shown in Figs. 3 and 9. The passivation layer 74 is then deposited, preferably SiO₂ or Si₃N₄ from a plasma with a substrate temperature of about 250°C to a thickness in the range of 2000 to 10,000Å and preferably about 5000Å. A photoresist is then applied, soft baked, aligned and exposed. The resist is then developed from the gate and source contact pads 46 and 50 and the pixel contact pads 76. After hard baking the passivation layer is then removed from these areas by plasma or buffered oxide etch, rinsed and dried leaving the pattern shown in Fig. 10. The pixel contact pads 76 and the gate and source pads 46 and 50 are then etched to remove the refractory metal from the ITO layer 60, rinsed and dried. The resist is then stripped, rinsed and dried. The back planes are then ready to be processed to add the active medium. In view of the above discussion, it can readily be seen that the present invention provides a method of manufacturing backplanes for active matrix display devices that radically decreases production costs by substantially increasing the yield of profitable products. Referring to Fig. 11, a drive scheme is illustrated for the completed matrix display 40. The backplanes have the active medium, such as twisted nematic active material, applied between the backplane and a frontplane (not illustrated) which can be another glass substrate. The display 40 then is connected to a controller 80 by a gate line driver 82 and a source line driver 84. The drivers 82 and 84 are connected to each respective gate or source line. The controller 80 provides a gate drive signal over a gate drive line or lines 86 and a source drive signal over a source drive line or lines 88. The desired pixels can then be activated by the controller 80 which also provides a frontplane drive signal on a frontplane line 90. A first drive scheme is illustrated in Table 1. The nonselected gate lines are held at the most negative voltage to insure that the transistor will not turn on when the frontplane is alternated. The frontplane and source line voltages are alternated so a constant direct current is not applied to the pixels, since a long term direct current causes the pixel active material to fail very rapidly. The voltages can be alternated at any frequency, but preferably in the range of 30 to 100 hertz. A second drive scheme is illustrated in Table 2. In this scheme, the source line for the activated pixels is alternated and the rest of the voltages are held constant. Modifications and variations of the present invention are possible in light of the above teachings. As mentioned above, the devices can be of any desired shape and size. Also, any type of thin film semiconductor material can be utilized, not just those formed from silane. The amorphous silicon alloys can be deposited from any suitable reaction gas mixture containing at least silicon and hydrogen. Further, other semiconductor materials can be utilized such as cadmium selenide, (CdSe), which can be deposited by sputtering or evaporation processes. Although the substrate 56 is described as having a barrier layer 58 thereon, a high quality substrate containing a small amount of or no sodium can be utilized, in which case the barrier layer 58 can be eliminated. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

Claims: A thin film transistor (42), comprising: a substrate (56, 56'); a gate electrode (44, 44') formed on said substrate and having at least one exposed edge (68); a gate insulator (64, 64') formed on said gate electrode; a semiconductor material (66, 66') formed on said insulator; a dielectric (70, 70') formed a) to overlie the edge of said gate insulator and said semiconductor material, or b) to overlie said edge of said gate electrode with a portion of said gate insulator and said semiconductor material overlying said dielectric; said dielectric being formed with a central portion thereof removed over a substantially planar portion of said gate electrode, with said insulator and said semiconductor material formed on at least said central portion of said gate electrode; a drain electrode (54, 54') formed on at least a portion of said dielectric and on said semiconductor material adjacent said edge of said gate electrode; and a source electrode (48, 48') formed on another portion of said dielectric and on said semiconductor material and spaced from said drain electrode. The transistor as claimed in claim 1, wherein: said substrate is a glass substrate; an insulator layer (58, 58') is formed on said substrate; a conductive oxide layer (60, 60') is formed on said insulator layer; said gate electrode includes a refractory metal layer (62) formed on said conductive oxide layer; and said refractory metal and said conductive oxide layer form said gate electrode. The transistor as claimed in claim 1 wherein: a drain contact pad, a source contact pad (50) and a gate contact pad (46) are formed on said substrate spaced from one another, said gate electrode and said gate contact pad being formed integral with one another; said drain electrode couples said semiconductor material to said drain pad; said source electrode couples said semiconductor material to said source pad; said drain electrode covers said drain pad; and said source electrode covers said source pad. The transistor as claimed in claim 1 wherein said gate insulator is formed substantially to cover said gate electrode; said semiconductor material is formed substantially to cover said gate insulator; said central portion of said dielectric is formed so as to leave a substantially planar portion of said semiconductor material exposed; and said drain electrode is formed on at least a portion of said dielectric and on said planar portion adjacent said edge of said gate electrode and spaced therefrom. The transistor as claimed in claim 4 wherein; said substrate is a glass substrate; an insulator layer (58, 58') is formed on said substrate; a conductive oxide layer (60, 60') is formed on said insulator layer; said gate electrode includes a refractory metal layer (62) formed on said conductive oxide layer; and said refractory metal and said conductive oxide layer are formed in a pattern so as to form at least one gate electrode, gate contact pad (46), drain contact pad and source contact pad (50) with said gate electrode coupled to said gate contact pad. The transistor as claimed in claim 1 wherein: a drain contact pad (46), a source contact pad (50) and a gate contact pad are formed on said substrate spaced from one another, said gate electrode and said gate contact pad being formed integral with one another; said drain electrode couples said semiconductor material to said drain pad; said source electrode couples said semiconductor material to said source pad; and said source electrode covers said source pad. The transistor as claimed in any of claims 1 to 6 wherein said semiconductor material is an amorphous silicon alloy. A matrix display backplane comprising a substrate and a plurality of transistors (42) as claimed in any preceding claim. The backplane as defined in claim 8 wherein: said gate electrodes have at least two exposed edges; said dielectric covers said exposed edges and has a central open portion on said gate electrode; said central open portion has in successive layers, a gate insulator (64, 64') and a semiconductor material (66, 66); said drain electrode and said source electrode are formed on said semiconductor layer; a passivation layer (74) covers the transistor layers; said gate electrodes are formed in a plurality of lines, each line being connected to a respective gate contact pad (46) and each line having a plurality of transistors (42) formed thereon; said drain electrodes connect each of said transistors to a pixel pad (76); and said source electrodes are formed in lines spaced from said gate electrodes, and connected to a respective source contact pad (50), with each of said transistors being coupled to one of said source electrodes. The backplane as defined in claim 8 wherein: said substrate is glass having in successive layers, a conductive oxide layer (60, 60') and a refractory metal layer (62); said gate electrodes are formed on said successive layers; said gate electrodes have in successive layers a gate insulator (64, 64') and a semiconductor material (66, 66'); said dielectric layer covers said gate electrode, gate insulator and semiconductor material including any exposed edges thereof and said dielectric layer has a central open portion on said semiconductor layer; said central open portion has said drain electrode and said source electrode formed on said semiconductor layer; a passivation layer (74) covers the transistor layers; said gate electrodes are formed in a plurality of lines, each line being connected to a respective gate contact pad (46) and each line having a plurality of transistors (42) formed thereon; said drain electrodes connect each of said transistors to a pixel pad (76); and said source electrodes are formed in lines spaced from said gate electrodes, and connected to a respective source contact pad (50), with each of said transistors being coupled to one of said source electrodes. The backplane as defined in claim 8 wherein: said gate electrodes are formed in a plurality of lines, each line being connected to a respective gate contact pad (46) and each line having a plurality of transistors (42) formed thereon; said drain electrodes connect each of said transistors to a pixel pad (76); and said source electrodes are formed in lines spaced from said gate electrode lines at least by said dielectric layer at the crossover points thereof, and are connected to a respective source contact pad (50), with each of said transistors being coupled to one of said source electrodes. The backplane as defined in claim 11 wherein: said substrate is glass having deposited thereon one layer over another, a conductive oxide layer (60, 60') and a refractory metal layer (62); and said gate electrodes are formed from said successive layers. A process specially adapted for the manufacture of thin film transistors according to any one of claims 1-7 comprising: providing a substrate (56, 56'); depositing a gate electrode (44, 44') on said substrate having at least one exposed edge (68); depositing a gate insulator (64, 64') on said gate electrode; depositing a semiconductor material (66, 66') on said gate insulator; depositing a dielectric (70, 70') to overlie the edge of said gate insulator and said semiconductor material; removing a central portion of said dielectric over a substantially planar portion of said gate electrode, said gate insulator and said semiconductor material being formed over at least said central portion of said gate electrode; depositing a drain electrode (54, 54') on at least a portion of said dielectric and on said semiconductor material adjacent said edge of said gate electrode; and depositing a source electrode (48, 48') on at least a portion of said dielectric and on said semiconductor material and spaced from said drain electrode. A process specially adapted for the manufacture of thin film transistors according to any one of claims 1-7 comprising: providing a substrate (56, 56'); depositing a gate electrode (44, 44') on said substrate having at least one exposed edge (68); depositing a dielectric (70, 70') to overlie at least said edge of said gate electrode; removing a central portion of said dielectric over a substantially planar portion of said gate electrode; depositing a gate insulator (64, 64') on at least said central portion of said gate electrode and overlying said dielectric; depositing a semiconductor material on said gate insulator, overlying at least said central portion of said gate electrode and overlying said dielectric; depositing a drain electrode (54, 54') on at least a portion of said dielectric and on said semiconductor material adjacent said edge of said gate electrode; and depositing a source electrode (48, 48') on at least a portion of said dielectric and on said semiconductor material and spaced from said drain electrode. The process as claimed in claim 13 including: depositing said gate insulator substantially to cover said gate electrode and depositing said semiconductor material substantially to cover said gate insulator; depositing said dielectric over said gate electrode, said insulator and said semiconductor material; removing a central portion of said dielectric to expose a substantially planar portion of said semiconductor material prior to depositing said drain electrode; and depositing said source electrode concurrently with and spaced from said drain electrode; wherein providing said substrate includes providing a glass substrate with an insulator layer (58, 58') on said substrate and depositing a conductive oxide layer (60, 60') on said insulator layer; and depositing said gate electrode includes depositing a refractory metal layer (62) on said conductive oxide layer; and removing portions of said refractory metal and said conductive oxide layer to form at least one gate electrode, gate contact pad (46), drain contact pad and source contact pad (50) with said gate electrode coupled to said gate contact pad. The process as claimed in claim 14 including: depositing said dielectric to cover said gate electrode; removing a central portion of said dielectric to expose a substantially planar portion of said gate electrode prior to depositing said insulator and said semiconductor material thereon; depositing said source electrode concurrently with said drain electrode; wherein providing said substrate includes providing a glass substrate, depositing an insulating layer (58, 58') on said substrate and depositing a conductive oxide layer (60, 60') on said insulator layer. The process as claimed in claim 15 or 16 including: depositing a drain contact pad, a source contact pad (50) and a gate contact pad (46) on said substrate spaced from one another, said gate electrode and said gate contact pad being deposited together integral with one another; depositing said drain electrode to cover, and to connect said semiconductor material to, said drain pad; and depositing said source electrode to cover, and to connect said semiconductor material to, said source pad. The process as claimed in any of claims 13 to 17 wherein depositing said semiconductor material includes plasma depositing an amorphous silicon alloy. A process, specially adapted for the manufacture of matrix display backplanes according to any one of claims 8-12, comprising forming at least one of said transistors utilising the process as claimed in any one of claims 13-18.

Inventors: FLASCK, RICHARD A., HOLMBERG, SCOTT H.
Applicants: ALPHASIL INCORPORATED, HONEYWELL INC.
Application year: 1984
Main classification: H01L21
IPC codes: G02F1, H01L21