SEMICONDUCTOR MEMORY USING MULTIPLE LEVEL STORAGE STRUCTURE

Abstract: A semiconductor memory for reading and writing stored charge in an X-Y address system includes a plurality of memory cells each consisting of one capacitance element (116) and one MOS-FET (115) in a matrix. A multiple level storage structure is used for reading and writing data of more than two levels stored in the capacitance elements (116) by applying a multi-level step voltage to the plateelec­ trode of the capacitance or to the gate electrode of MOS-­ FET (115).

Description: BACKGROUND OF THE INVENTION This invention relates to a semiconductor memory, and more particularly to a semiconductor integrated circuit memory. As typified by a dynamic random access memory (DRAM) or a semiconductor memory using a charge coupled device (CCD memory), a semiconductor memory having a high integration density stores data by making the existence and absence of charge inside a potential well on a semiconductor surface correspond to digital signals "1" and "0". However, this storing method involves the problem that in the case of DRAM, for example, only binary 1-digit (1-bit) data can be handled for each unit memory cell, and hence the amount of total bits per chip is limited. Particularly in the charge storage type memory such as described above, charge leaks from a pn junction formed essentially in a charge storage portion so that the data can be stored only for a limited period of time. This results in another problem that a mechanism for rewriting (refreshing) the stored data on a certain cycle of time within that period is essentially necessary. The CCD memory has a structure in which the stored charge is cycled using a transfer electrode. In order to effect rewrite (refresh), therefore, the stored charge is transferred along a CCD transfer electrode loop arranged cyclicly, and the charge must be read and written at an input-output portion disposed at a predetermined position inside the CCD loop on a certain cycle of time. However, a great deal of power is necessary to charge and discharge the transfer electrodes for transferring the charge in order to refresh all data, and it has therefore been difficult in the past to provide a memory having low power consumption. Semiconductor memories having higher integration density as exemplified by a semiconductor dynamic random access memory (hereinafter called "DRAM") have been developed every year, and miniaturization of unit memory cells (hereinafter called "memory cells") of the semiconductor memory and its peripheral circuits is ever-increasing. In order to improve the integration density by miniaturization such as described above, however, a drastic improvement must be made in device process technique such as photolithography, etching and the like, but a considerably long period of time is generally necessary before improved device process technique is developed. In contrast, demands for very high integration density semiconductor memories are ever-increasing, and semiconductor memories having low power consumption are earnestly required in a novel field of application such as miniature computers for office use and their peripheral terminals that have made a remarkable progress in recent years. For these reasons, existing semiconductors are not entirely satisfactory not only in their integration density but also in their performance such as power consumption. To fulfill the demands described above, semiconductor memories using multiple level storage structure (MLS memories) are believed to be effective means that can realize very high integration density semiconductor memories and are available in accordance with the existing process technique. The memory improves substantially the integration density by storing data of at least more than two levels per memory cell. A multi-level storage memory using charge coupled device (hereinafter called "CCD") has been known in the past. The memory is described in detail in L. Terman et al. IEEE Journal of Solid-State Circuits, Vol. sc-16, No. 5, pp. 472 - 478, October, 1981, and M. Yamada et al, Proceedings of the 9th Conference on Solid-State Devices, Tokyo, 1977, pp. 263 - 268, issued on January, 1978, for example. However, the multi-level storage memory using the charge coupled devices (CCD) has not much been put into practical application for the following reasons. (1) Since signal charge transfer inefficiency is not zero in CCD, analog signal charge corresponding to multi-level data damps with the charge transfer, and hence the number of multi-level can not be increased so much. (2) The amplitude of a driving pulse must be increased in order to improve the signal charge transfer efficiency, and this results in extremely great power consumption in addition to the inherent property of the cell that it has originally large capacitance load. (3) Since A/D and D/A convertors having high accuracy are necessary for each CCD loop, the integration density can not be increased due to the limitation of peripheral circuits, even if the memory cell can be miniaturized. EP-A-0 031 491 discloses a semiconductor memory with the features included in the first part of claim 1. Each individual cell of the known memory is capable of storing charges of any one of at least three charge levels. In reading the information contained in one memory cell, the entire charge is transferred to a peripheral sensing circuit formed in charge coupled device technology and including a floating gate sensor, where the amount of charge derived from the memory cell is detected and converted into a binary output signal. IBM Technical Disclosure Bulletin, vol. 22 no. 7, December 1979, pages 2978 and 2979 further describes a charge coupled device detection scheme according to which a given amount of charges is detected by the use of a stepped multi-level voltage. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory which operates at low power consumption and permits a very high integration density. The semiconductor memory of the invention meets this object by the features recited in claim 1. In an embodiment of the invention, stepped multi-level voltages are applied to the word-lines of the memory matrix so that the stored data are read at the timing at which the stored charge flows from the respective memory cell, and data are written into the memory cell at a timing corresponding to the respective input signal. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a sectional view of a memory cell of a word line driving system; Figures 2A through 2C are schematic views showing the potential with respect to electrons along the surface of a semiconductor layer in the read mode of the memory cell of the word line driving system; Figure 3 is a diagram showing the change of a word line voltage and a bit line voltage in the read mode of the memory cell of the word line driving system; Figures 4A through 4D are schematic views showing the potential with respect to electrons along the surface of a semiconductor layer in the write mode of the memory cell of the word line driving system; Figure 5 is a diagram showing the change of a word line voltage and a bit line voltage in the write mode of the memory cell of the word line driving system; Figure 6 is a sectional view of a memory cell of a plate driving system; Figures 7A through 7D are schematic views showing the potential with respect to electrons along the surface of a semiconductor layer in the read mode of the memory cell of the plate driving system; Figure 8 is a diagram showing the change of a word line potential, a plate voltage and a bit line voltage in the read mode of the memory cell of the plate driving system; Figures 9A through 9E are schematic views showing the potential along the surface of a semiconductor layer in the write mode of the memory cell of the plate driving system; Figure 10 is a diagram showing the change of a word line voltage, a plate voltage and a bit line voltage in the memory cell of the plate driving system; Figure 11 is a circuit diagram showing a memory array, a read circuit and a write circuit of a semiconductor memory using a memory cell of a word line driving system; Figure 12 is a pulse chart showing the voltage waveform at each portion in the read mode of the semiconductor memory shown in Figure 11; Figure 13 is a pulse chart showing the voltage waveform at each portion in the write mode of the semiconductor memory shown in Figure 11; Figure 14 is a diagram showing the surface potential of the memory cell and useful for explaining the read of 4-level charge storage state; Figure 15 is a circuit diagram showing an interface circuit of the semiconductor memory shown in Figure 11; Figure 16 is a circuit diagram showing a memory array, read circuit and write circuit of a semiconductor memory using a plate driving system; Figure 17 is a pulse chart showing the voltage waveform at each portion in the read mode of the semiconductor memory shown in Figure 16; and Figure 18 is a pulse chart showing the voltage waveform at each portion in the write mode of the semiconductor memory shown in Figure 16. DESCRIPTION OF THE PREFERRED EMBODIMENTS First of all, the principle of the reading and storing operations of the multi-level (three or more levels) charge storage state as the basis of the MLS memory of the present invention will be described. Figure 1 illustrates the sectional structure of a memory cell in accordance with the first principle of the invention and the kind of applied voltages. For convenience' sake, the memory based on the later-appearing principle will be hereinafter called a "word gate driving MLS memory". Although the electron is dealt with as the stored charge, the principle can be applied exactly in the same way to the positive hole by converting the conductivity type of a semiconductor and inverting the voltage for operating the memory. In the drawing, reference numeral 10 represents a p-type semiconductor layer (a substrate of a semiconductor layer disposed on the substrate), reference numeral 11 is a gate insulating film (oxidized film or the like), and reference numerals 12 and 13 are electrodes formed on the gate insulating film. Reference numerals 14 and 15 represents highly doped n-type semiconductor layers formed in self-alignment with the electrodes by ion implantation, or the like, respectively. The electrode 13 corresponds to the gate of an insulated gate field effect transistor (MOS-FET), and the n-type semiconductor layers 14 and 15 correspond to the drain or source of the transistor. When a positive voltage is applied to the plate electrode 12, an inversion layer which is induced on the surface of the semiconductor layer 10 is electrically coupled with the n-type semiconductor layer 15, thereby forming a capacitance in cooperation with the electrode 12 and making it possible to store the electrons in the inversion layer. When this memory cell is used in a memory device consisting of a two-dimensional arragnement, the gate 13 of MOS-FET is connected to an address decoded row line (word line) 2, and the drain 14, to an address decoded column line (bit line) 3 to form a memory matrix.The electrode 12 is connected in common to all the memory cells, and a positive D.C. voltage is applied to it. Figures 2A, 2B and 2C illustrate the surface potential to the electrons along the surface of the semiconductor layer of the memory cell shown in Figure 1. Figure 2A illustrates the charge storage mode. The stored charge 20 in the potential well 21 below the plate is isolated from the bit line 23 by a potential barrier 22 below the gate of MOS-FET, and from the other regions by the potential barrier of an isolation region disposed around the memory cell. When reading of the multi-level charge state is effected, multi-level step voltages w (30, 31, 32) that shifts from a low voltage to a high voltage are applied to the word line 22 as shown in Fig. 3. In the drawing, reference numeral 30 corresponds to Figure 2A, 31 to Figure 2B, and 32 to Figure 2C. When the voltage w is increased in a positive direction, the potential barrier below the gate of MOS-FET drops in the sequence of 22 → 24 → 26 as shown in Figures 2A, 2B and 2C, and when it becomes below the surface potential at a storage node 25 (the state represented by 26), the charge flows out (27) from the storage portion to the bit line. Figure 3 illustrates the mode of drop of the bit line voltage VD (33, 34) caused by the outflow of the charge. As described above, the storage state of the charge having three or more levels can be discriminated by detecting the timing at which the difference between the potential barrier below the gate of the word line and the potential at the storage portion, when the former is gradually reduced, is inverted, as the change of the bit line voltage VD. Next, the principle of the writing mode of the multi-level charge storage state will be described. Figures 4A through 4D are schematic views showing the concept of the potential on the surface of the semiconductor layer when the multi-level charge is stored, and Figure 5 shows the change, with time, of the word line and bit line voltages when charge storage is effected. Figures 4A through 4D correspond to the state of application of the voltages represented by reference numerals 50 through 53 in Figure 5, respectively. Before writing is executed, the word line applied voltage w is set in advance to the highest level so that the potential barrier below the gate of the word line becomes minimal (42), while the data line voltage VD is set in advance to the lowest level 54 at which the potential well 41 of the storage portion is filled by the charge 42 (for example, to the ground potential). Next, the multi-level step voltage w (50 - 53) shown in Figure 5 is applied to the word line. Then, the bit line voltage VD is raised from 54 to 55 as shown in Figure 5 at the timing at which the potential barrier (43, 45, 48) below the gate of the word line is in agreement with the surface potential which corresponds to the amount of charge to be stored finally, and the charge is extracted (44) from the bit line 46 as shown in Figure 4C. Figure 4D shows the final charge storage state (stored charge 47). Next, the reading and storing operation of the multi-level (two or more levels) charge storage state in the memory cell in accordance with the second principle will be described. Hereinafter, this principle will be called a "plate electrode driving MLS memory" to distinguish it from the word gate driving system described earlier for convenience' sake. Figure 6 illustrates the sectional structure of the memory cell and the applied voltage. This memory cell is not much different from the word gate driving system described in its cross-sectional structure already, and the difference is that unlike the system described already, the plate electrode 62 forming the charge storage portion is independent for each row and is disposed in parallel with the word line gate 63. Figures 7A, 7B, 7C and 7D illustrate the principle of discriminating the storage states of the multi-level charge in accordance with this system. A low voltage 80 is applied to the word line 5 in order to prevent the leakage of the charge 70 of the storage portion to the bit line during holding of the charge and to sufficiently raise the potential barrier (72) below the word line gate. During the read operation, a voltage 81 which is higher than that during data holding is applied to the selected row to reduce the potential barrier (74, 76, 78) below the word line gate so that the charge flowing out from the storing portion is caused to flow only through the bit line. Under this selected state, when the voltage  PL of the second row address line (plate) 62 disposed in parallel with the word line is decreased gradually and step-wise (82 - 85) as shown in Figure 8, the depth of the potential well on the surface of the semiconductor layer becomes smaller in response to the potential (71 → 73 → 75 → 77), and the surface potential rises. Figures 7B through 7D illustrate this state. When the surface potential at the storage node becomes higher than the potential barrier below the word line gate that is set previously, the flow of charge 79 to the bit line such as shown in Figure 7D occurs. Thus, the charge storage state of the multi-level (two or more levels) can be discriminated by detecting the timing of the change of the bit line voltage VD (change of 86 → 87 in Figure 8) in the same way as in the word gate driving system. Likewise, the principle of the writing operation of the storage state of the multi-level (two or more levels) charge in this plate electrode driving system will be described. Figures 9A through 9E illustrate the potential along the surface of the semiconductor layer of the memory cell during the storing operating, and Figure 10 illustrates the voltage waveform at each portion of the memory cell when the storing operating is conducted. The potential 92 of the bit line is set to a level somewhat lower than the potential barrier (91) below the word line gate in the selected state before the storing operation is effected. Multi-level step voltage  PL (103 - 106) which changes from a low voltage to the high is applied to the plate. The potential well below the plate is thus made deeper gradually (90, 93, 97, 99). When a voltage 104 shown in Figure 10 is applied to the plate, the potential well occurs as shown in Figure 9B, but the charge is not injected. To effect the writing operation, a pulse 108 in a negative direction is applied to the bit line while the multi-level step voltage  PL keeps a constant value 105, as shown in Fugure 10. The mode 94 of injection of the charge 95 in this case is shown in Figure 9C. The amount of charge 96 determined by the potential barrier 91 below the word line gate and the depth of the potential well below the plate can be stored inside the potential well (Figure 9D) by returning the drain voltage to the value 107 during the same period. Figure 9E illustrates the charge storage state. (The word line voltage is reduced; 101 → 102.) Hereinafter, two embodiments of the invention will be described. Embodiment 1 Figure 11 illustrates an example of a memory using a multi-level storage structure in which a memory cell of the word gate driving system is used as each unit memory. In the drawing, a memory cell is shown constituted by n-channel MOS-FET 115 and a charge storing portion 116. Reference numeral 111 represents a row address select circuit, which selects only one row from a plurality of rows. In order to select a word line 117, a predetermined voltage is applied from the row address select circuit to the gate of a row address select transistor 109, which is connected to the word line 117, so as to render the transistor 109 conductive. In the case of the n-channel MOS transistor shown in this embodiment, a power source voltage V cc or a voltage higher than the former is applied to the gate. Reference numeral 113 represents a multi-level step voltage generator, and the output of this generator is connected to the word line 117 through the transistor 109. The multi-level step generator 113 is driven by a triggering pulse 15O. On the other hand, a high sensitive sense amplifier 120 is connected to one of the ends of a bit line 118. This amplifier consists of a pre-sense circuit which amplifies a minute change of the bit line potential by voltage amplification or the like, and a main sense circuit which amplifies the output of the pre-sense circuit to a logic swing inside the memory, and drives level storage cells consisting of n-channel MOS-FETs. In this embodiment, the output line 133 is discharged from the power source potential V cc to the ground potential V ss at the time at which a signal is detected on the bit line. Eight transistors 121 through 128 constitute 4-level temporary storage cells. Two transistors store one level. Accordingly, this embodiment can discriminate and read four levels of charge storage state (2 bits). In the 4-level temporary storage cells, two signal lines for one level (or 8 signal lines in all) are disposed so as to cross the output line of the amplifier described above. Four lines 129 through 132 are read signal lines which operate at the time of data read, while the lines 134 through 137 are write signal lines which operate at the time of data storage, respectively. The read signal lines are connected to a read reference signal generator 114. In this embodiment, a shift register is used as the read reference signal generator, which produces the power source voltage V cc in the time sequence of 129 - 132 in synchronism with the multi-level step voltage under the control of the triggering pulse 15O. When the output line 133 of the amplifier is set in advance to V cc and when it is discharged to the ground potential V ss at the timing of the flow-out of the charge, the logic data of the read signal lines 129 through 132 are temporarily stored as the potentials of the gate terminals of the transistors 122, 124, 126 and 128. In this manner, the mutually different multi-level charge data produced from the memory cells aligned on the same row to the respective data lines are temporarily held as the logic swing data stored in the 4-level temporary storage cells connected to the respective bit lines. Figure 12 illustrates the voltage waveform at each portion corresponding to the read operation. Figures 12(a) through 12(d) illustrate the triggering pulse , the word line potential  R , the bit line potential, and the output voltage of the sense amplifier, respectively. Figures 12(e) through 12(h) illustrate the voltage of read reference signal lines. Figures 12(i) through 12(l) illustrate the gate potentials of the transistors 122, 124, 126 and 128 of the temporary storage cells, respectively. In this embodiment, a potential 217 which is lower by the threshold voltage of the gate of the transistor 123 than the power source voltage V cc is temporarily held at the gate of the transistor 124, making the transistor 124 conductive. Figure 14 illustrates the potential along the memory cell section corresponding to the read operation of the 4-level charge storage state shown in this embodiment. The potential barriers below the word line gate corresponding to the word line voltages ( R ) 201, 202, 203 and 204 are represented by 401, 402, 403 and 404, respectively. When the word line voltage  R is discharged from 401 to 402, the flow-out of charge occurs when the surface potential of the charge storing portion is higher than 411, whereby the amplifier 120 operates and a voltage lower by the threshold voltage of the transistor 121 than V cc is stored at the gate of the transistor 122. Similarly, with the drop of the voltage  R from 202 ← 203, 203 → 204, the flow-out of charge occurs when the surface potential of the charge storing portion is within the potential range of between 411 and 412 and between 412 and 413, and the potentials lower by the threshold voltage than V cc are stored at the gates of the transistors 124 and 126, respectively. If the surface potential of the charge storage portion is below 413, the flow-out charge does not occur to the end. In such a case, the potential of the output line 133 of the amplifier is reduced so as to store a potential, which is lower by the threshold voltage than V cc , at the gate of the transistor 128 in synchronism with the voltage pulse 212. When the operation described above is carried out, the information, in which of the four ranges 420, 421, 422 and 423 in Figure 14 the surface potential of the storage portion is positioned, is transferred to the data of the temporary storage cells outside the memory cell array. These four levels can be made to correspond to the digital binary signals (1, 1), (1, 0), (0, 1) and (0, 0), respectively. Next, the operation at the time of charge storage (writing) will be explained. First, a reset pulse  s is applied to a line 162, and each data line 118 is reduced to V ss (base potential) through MOS-FET 140. Then, the signal generator 151 operates in synchronism with the triggering pulse . This embodiment uses a shift register as the write signal generator, which produces in a time sequence a power source potential V cc from 134 to 137 in synchronism with the multi-level step voltage  R . On the other hand, the temporary storage cell output line 138 is connected to the write signal line 136 through the transistor 124 storing temporarily V cc at its gate. Accordingly, V cc is produced to the temporary storage cell output line 138 for the first time when the write signal line 136 reaches V cc . In other words, the logic data corresponding to the 4-level voltages stored temporarily in the temporary storage cells and the 4-level logic data of the write signal lines are compared, and only when they are in agreement with one another, the temporary storage cell output line 138 shifts to the high logic level, rendering the write transistor 141 conductive through the buffer 139 and raising the potential of the bit line 118 (rises to V cc ). As already described generally, the charge corresponding to the potential barrier below the 4-level word line gate is thus left in the charge storage portion, and the write operation is completed. As described above, this embodiment represents that the rewriting operation (refresh operation) which is essential in a charge storage type semiconductor memory can be accomplished easily. Figure 13 illustrates the voltage waveform at each portion during the writing operation. Figures 13(a) and 13(b) illustrate the waveforms of the triggering pulse  and the word line potential  R , respectively, Figures 13(c) through 13(f) illustrate the waveforms of the potentials of the write reference signal lines 134 through 137, respectively, Figure 13(g) illustrates the waveform of the potential of the temporary storage cell output line 138, and Figure 13(i) does the waveform of the bit line potential 118. To produce the read data outside the semiconductor memory, a column address select circuit 112 is further added. A transistor 142 is connected to the output line 138 of the 4-level temporary storage cell selected by the select circuit 112 and to a common data line 143. Therefore, when the output line 138 of the temporary storage cell shifts to V cc during the writing operation, the common data line 143 shifts simultaneously to V cc (Figure 13(h)). As shown in Figure 15, a 4-level to 2-bit encoder ENC is disposed inside an interface circuit. This encoder ENC produces the 4-level logic data appearing on the write signal lines 134 - 137 in synchronism with the shift of the common data line 143 to the high level as the 2-bit binary signals to input-output terminals 145 and 146. Next, the rewriting operation of the stored data will be described. This rewriting operation is conducted only for the column which is selected by the column address select circuit 112. When the rewriting operation is made, it is necessary to make the temporary storage cells inactive before the start of the rewriting operation. For this purpose, the output line of the amplifier 133 for the selected column is discharged to V ss by a write enable signal  WE through the transistor 149. Accordingly, the data thus read out are not held in the temporary storage cells. The digital binary signals corresponding to the rewrite data that are applied from outside through the terminals 145 and 146 are decoded by a decoder DEC disposed inside the interface circuit 144, and shift one of the output lines of the decoder 163 - 166 to V cc and the rest, to V ss . On the other hand, V cc is produced in the time sequence to the four write signal lines 134 through 137 in the same way as in the rewriting mode in the refresh cycle described already, and the signal and the previous decoder output signals are compared with each other, so that the common data line 143 is changed from V ss to V cc at the timing at which both signals coincide with each other (see Figure 15). In Figure 15, EOR is an exclusive-OR circuit (EOR gate) and NOR is an inversion logic summation circuit (NOR gate). This signal is transmitted to the output line 138 of the temporary storage cells through the transistor 142 to actuate the write transistor 141. As a result of the operation described above, the 2-bit digital signal applied from outside the semiconductor memory can be written as a 4-level voltage state into a memory cell positioned at the point of intersection of one row address line and one column address line. Embodiment 2 Figure 16 illustrates an example of a semiconductor memory using the multiple level storage structure, which uses plate driving type memory cells as the unit memory cells. In the drawing, an n-channel MOS-FET 115 and a MOS type charge storing portion 175 constitute a memory cell. A first row address select line (word line) 173 is connected to the gate of MOS-FET of the memory cell, while a second row address select line 174 is connected to the electrode (plate) of the MOS charge storage portion 175. The first and second row select lines that are parallel to each other are connected to a potential application line  WR 170 of the word line and to the output line  R 119 of the multi-level step wave through the row address select transistors 171 and 172, respectively. The row address select transistors 171 and 172 are simultaneously selected by the row address select circuit 11. The constructions other than the write circuit are the same as those of the embodiment 1 described already. Figure 17 illustrates the voltage waveform at each portion during the read mode. The process in which the charge flows onto the data lines by  WR and  R has been described in detail in the foregoing "Summary of the Invention". The other processes of the read mode are the same as those of the Embodiment 1 and are therefore omitted. Figure 18 illustrates the voltage waveform at each portion during the write mode. In the write mode, the output line 138 of the temporary storage memory cells actuates the pulse generator 176 (in Figure 16) so as to generate a potential change such as shown in Figure 18(j). Since the other operations are the same as those of the Embodiment 1, their description is hereby omitted.

Claims: A semiconductor memory of an XY address system, including a plurality of row address lines (117), a plurality of column address lines (118) disposed parallel to each another and crossing said row address lines (117), memory cells (115, 116) disposed at the crossing points, each memory cell being capable of storing charges of any one of at least three different levels, and write mechanisms (129, 141, 145, 151) and read mechanisms (114, 120) for said cells, characterized in that means (109, 111, 113) for sequentially applying voltages ( R ) of at least three levels (201, 202, 203, 204) to selected memory cells (115, 116) are connected to said row address lines (117). The semiconductor memory of claim 1, wherein a read mechanism and a write mechanism are disposed for each of said column address lines (118), so that data can be simultaneously read from, or written into, a plurality of said memory cells (115, 116) selected by one row address line (117). The semiconductor memory of claim 1 or 2, wherein each of said memory cells is a one-transistor memory cell consisting of one charge storage portion (116) having a metal-insulator-semiconductor (MIS) structure or a PN junction, and an MIS type switching device (115) having the gate thereof connected to said row address line (117) and one semiconductor region thereof connected to said column address line (118), a multi-level step voltage having at least three levels and changing from a low voltage to a high voltage or vice versa is applied to one selected row address line to read the storage state of charge of more than two levels stored in said charge storage portion (116), and a timing detector for detecting the timing at which the charge flows out from each of said memory cells to each of said column address lines is used as said read mechanism. The semiconductor memory of claim 3, wherein a reset transistor (140) for changing the potential of each of said column address lines (118) from a low voltage to a high voltage or vice versa and said timing detector are used as said write mechanism, a multi-level step voltage having at least three levels and changing in the opposite direction to the read mode, that is, from a high voltage to a low voltage or vice versa, is applied to said selected row address line (117), and said reset transistor (140) is operated at the timing at which the potential thereof corresponds to the write data so that the storage states of the multi-level charge of at least three levels are simultaneously written into a plurality of said memory cells (115, 116) by changing the potentials of said column address lines (118). The semiconductor memory of claim 4, wherein a temporary memory cell (121, 122) is disposed as said timing detector at at least one of the ends of each of said column address lines (118) so that said temporary memory cell stores a digital binary signal generated at the timing of flow-out of charge to said column address line (118) or a decoded signal of said digital binary signal, thereby effecting reading of the multi-level charge storage state. The semiconductor memory of claim 5, wherein said timing generator is a signal comparator, which compares the stored data of said temporary memory cell (121, 122) corresponding to each of said column address lines (118) with a digital binary signal generated in synchronism with the multi-level step voltage at the time of write or with a decoded signal of said digital binary signal, and drives said reset transistor(140) when both of said signals coincide with each other, thereby effecting writing of the multi-level charge storage state. The semiconductor memory of claim 1, wherein said row address lines (173, 174) are arranged in pairs and each memory cell (115, 175) consists of one MIS (Metal-Insulator-Semiconductor) type charge storage portion (175) and one insulated gate transistor (MIS-FET 115), the gate of said MIS-FET (115) being connected to a first one (173) of said pair of row address lines, the source or drain of said MIS-FET (115) being connected to said column address line (118), and the plate electrode of said charge storing portion (175) being connected to the second one (174) of said pair of row address lines disposed in parallel with said first row address line (173), wherein a binary voltage corresponding to the selection and non-selection of the rows is applied to said first row address line (173), a multi-level step voltage having at least three potential states and changing from a high voltage to a low voltage or vice versa is applied to the second row address line (174) forming a pair together with a selected first row address line (173), said read mechanism is a timing detector which detects the timing at which the charge flows out from said charge storage portion (175) of each of said memory cells to each of said column address lines (118), and at least three multi-level charge storage states are read out from said charge storage portion. The semiconductor memory of claim 7, wherein a predetermined voltage enabling the transfer of charge is applied to said selected first row address line (173) while a multi-level step voltage having at least three potential states and changing from a low voltage to a high voltage or vice versa in the direction opposite that of the read mode is applied to said second row address line (174) forming a pair together with said first row address line (173), said write mechanism is a charge injection mechanism injecting charge from said column address line (118) to said charge storage portion (175) by applying a voltage pulse to said column address line at the timing at which the potential thereof corresponds to the write data, and writing and reading of the charge storage state of at least three levels are effected for said charge storage portion of an arbitrary unit memory cell.

Inventors: AOKI, MASAKAZU, HORIGUCHI, MASASHI, IKENAGA, SHINICHI, NAKAGOME, YOSHINOBU, SHIMOHIGASHI, KATSUHIRO
Applicants: HITACHI, LTD.
Application year: 1984
Main classification: G11C11
IPC codes: G11C11, G11C19, G11C14