COMPARATOR CIRCUIT

Abstract: A comparator circuit comprises an operational amplifi­ er (10) as a differential amplifier, and a offset voltage com­ pensating capacitor (13) connected to the inverting input (-) of the operational amplifier (10). The offset voltage (V OFF ) of the operational amplifier is held in the offset compensating capacitor (13) during a period when the operational amplifi­ er is made to operate in a voltage follower mode. In a com­ parison sequence, when the operational amplifier is then made to operate in an open-loop mode, the offset voltage component (V OFF ) is superimposed on the signal or refer­ ence voltage input to the inverting input (-), and inverted to be output from the operational amplifier. Thus, the inherent offset voltage (V OFF ) standing on the output (18) of the opera­ tional amplifier (10) is cancelled out. A phase compensating capacitor (15) is made inactive by a switching means (16) connected in series therewith during the comparison sequence.

Description: COMPARATOR CIRCUIT The present invention relates to a comparator circuit. In recent years, a variety of comparator circuits have been widely used in various controlling equipment, for example, as the built-in circuits such as A-D (analog -to-digital) converter, the read-write circuit of a memory device, etc. in the equipment. There are comparator circuits of a type comprising logic ICs such as CMOS inverters or TTL ICs, and of analog type comprising differential amplifiers. For analog type comparators, comparators employing differential operational amplifiers (simply referred to as operational amplifiers, hereinafter) are the most advanced in terms of integration of the circuit involved on a chip, and therefore in terms of cost characteristics. Fig. 1 is a schematic circuit diagram of a comparator circuit comprising an operational amplifier 3 with an open-loop circuit. In operation of the comparator of Fig. 1, a reference voltage is input to an input terminal 1 connected to a non-inverting input (+) of the operational amplifier 3, and a voltage signal to be compared with the reference voltage is input to an input terminal 2 connected to an inverting input (-) of the operational amplifier 3. The operational amplifier 3 compares the input voltages, and outputs a voltage proportional to the difference between the reference voltage and the signal voltage to an output terminal 4. The operational amplifier is usually designed so that, when the difference of the two input voltages is 0, the output is at 0 volt. Therefore, in a case where the (reference voltage) level of the non-inverting input (+) is set to be 0 volt, a negative voltage having a value proportional to the absolute value of the signal voltage input to the inverting input (-) is output at the output terminal 4, if the signal voltage is positive, while a positive voltage having a value proportional to the absolute value of the signal voltage is output, if the signal voltage is negative. Thus, whether the input signal voltage is higher than the reference voltage or not can be determined by identifying the polarity of the output signal at the output terminal 4. However, in general, for operational amplifiers, a so-called offset voltage of a few mV to a few and ten mV appears at the operational amplifier output. On the other hand, there is a requirement for accurate detection (comparison) in relation to a small voltage signal of the order of a few tens to 100 mV, for example, in connection with read-out of data from a memory device or in connection with zero-cross point detection of an analog wave signal for instance. Apparently, the offset voltage places a restriction on the value of detectable signal voltages and reduces accuracy of detection of such small voltage signals. The offset voltage arises due to characteristic imbalances of circuit elements such as transistors consituting an operational amplifier. That is, the characteristics of a circuit element may deviate from design parameters on account of fluctuations in manufacturing processes, and they also change in dependence upon the operating ambient temperature. A method of cancelling the effects of such inherent offset voltage in an operational amplifier has been proposed in IEEE Journal of Solid State Circuits, vol. SC-14, No. 6, p. 965, December 1976. In operation of the proposed circuit shown in Fig. 2, switches 5A and SB are initially turned on and a switch SC is initially turned off. Hence, under these conditions offset voltage on the output of the operational amplifier is fed back to the inverting input (-), and a voltage corresponding to VS - VOFF is held in a capacitor C, where V5 and VOFF designate signal voltage to input INPUT in Fig. 2 and the offset voltage at the output, respectively. Then, the switches 5A and SB are turned off and the SC is turned on, and thus, only the signal voltage VS (a signal of sign and value proportional to V5 as described above) is output from the operational amplifier, because the input voltage V5 - VOFF to the inverting input (-) cancels the offset voltage VOFF standing on the output. Fig. 3 shows a modification of the circuit in Fig. 2, in operation of which switches 6 and 7 are initially turned on (and switch 8 is initially turned off) and voltages VIN1 and VIN2 are input to input terminals 1 and 2, respectively, of operational amplifier 3. Hence voltages at respective nodes A and B become VIN1 and VIN1 + VOFF This means that VOFF is held in a capacitor 5. When the switches 6 and 7 are turned off and the switch 8 is turned on, the voltage at the node B becomes VIN2 + VOFF, therefore, its inverted offset voltage component -VOFF cancels the offset voltage VOFF standing on the output 4, and thus, an output voltage corresponding to VIN1 #VIN2 appears on the output 4. The above-described method of cancelling the offset voltage by introducing a capacitor connected to the inverting input of the operational amplifier of a comparator circuit is advantageous compared to other previously proposed methods which involve the use of an externally attached resistor, because the "capacitor" method functions independently of the amount (size) of the offset voltage and operational ambient temperature. In previously proposed methods using a resistor, the value of resistor must be selected to match the amount (size) of offset voltage of the individual operational amplifier in use in a comparator circuit and the effects of temperature dependence of the offset voltage cannot be nullified by such methods. However, the operational amplifier 3 in the circuit of Fig. 3 is in voltage follower mode, with negative feedback applied, giving unity voltage gain. Therefore, if delay in the transmission of a signal through the operational amplifier 3 is larger than a time period corresponding to a phase lag of 1800 of a signal (an input signal) of frequency f, (i.e. if the delay is larger than l/2f), the operational amplifier 3 may selfoscillate. It is clear that self-oscillation is more probable as signal frequency increases. This self-oscillation can be avoided by providing a phase-compensating circuit comprising a capacitor, and this is general in the operational amplifiers except for the comparator application. The principle of such phase compensation can be explained by reference to Bode diagrams as shown in Figs. 4(a) and 4(b). Fig. 4(a) illustrates the gain (G)- frequency (f) characteristic of an amplifier, represented to logarithmic scales, and Fig. 4(b) shows the relationship between the phase angle (#) in a signal wave and logarithmic frequency (f). In Fig. 4(a), Pl and P2 designate so-called poles corresponding to frequencies at which the gain begins to decrease with the rates 6dB/oct and 12dB/oct, respectively. Referring to Figs. 4(a) and 4(b), if the gain (G) of a negative feedback circuit is larger than OdB (i.e. OdB is the case for the voltage follower circuit shown in Fig. 3 where the switch 6 is closed) in a frequency range wherein phase angle is equal to or larger than 1800, self-oscillation occurs. Therefore, to avoid self-oscillation in a negative feedback circuit, the point of intersection of curve C1 and the line of G = OdB must be leftwards (along the frequency axes of Figs. 4(a) and 4(b)) with respect to the point of intersection of the curve C2 and the line = 1800. A phase-compensating circuit is introduced to shift OdB gain cross point of the curve C1 so as to conform to this requirement. The phase-compensating circuit is constituted by a negative feedback loop partially applied to an inner circuit (internal circuitry) of the negative feedback circuit, for example, the operational amplifier as shown in Fig. 3. If a partial negative feedback loop is appied to the inner circuit (internal circuitry) which determines position of the pole Pl, the gain (G) of the negative feedback circuit is reduced as represented by the curve C1', and it intersects the OdB line at the point corresponding to the frequency fo', lower than fo, the frequency corresponding to the original point of intersection. Thus, the aforementioned condition for avoiding self-oscillation (i.e. G = OdB at a frequency where the corresponding phase angle is smaller than 1800) is achieved. In Figs. 4(a) and 4(b), P1' designates the pole, and the curve C2' represents the ¯ - f characteristic, both newly established when the partial negative feedback is introduced. The positions of the poles P1 and P1' with regard to frequency are approximately determined by the respective time constants of the inner circuit (internal circuitry) to which the phase-compensating circuit is applied (the time constants of the circuit applicable with and without the phase compensation circuit in place). Therefore, by introducing a phase-compensating circuit, the response speed of the negative feedback circuit, for example, the operational amplifier as shown in Fig. 3, is inevitably decreased. According to the present invention there is provided a comparator circuit comprising: a differential amplifier having two inputs and an output; a first switching means connected between said output and one of said inputs of said differential amplifier; an offset voltage compensating capacitor having one end operatively connected to said one of said inputs; a second switching means; and a phase compensating capacitor, said phase compensating capacitor being operatively connected to said differential amplifier via said second switching means; wherein said first and second switching means are arranged and adapted to turn ON and OFF concurrently with one another, whereby said differential amplifier operates in a voltage follower mode when said phase compensating capacitor is made active (when said second switching means is ON), whilst said differential amplifier operates in an open-loop mode when said phase compensating capacitor is made inactive (when said second switching means is OFF). An embodiment of the present invention can provide a comparator circuit, for comparing the levels of two input signals, operative with high response speed and accuracy. An embodiment of the present invention can provide a comparator circuit operative with a high response speed, free from offset voltage effects and protected from self oscillation. An embodiment of the present invention can provide a comparator circuit capable of detection in relation to a very small input signal. Briefly, in an embodiment of the present invention a comparator circuit has an operational amplifier having an inverting input and a non-inverting input and an output; a first switching means connected between the output and the inverting input of the operational amplifier; an offset voltage compensating capacitor connected to one of the inputs; a second switching means; and a phase compensating capacitor connected to the operational amplifier via the second switching means. The first and second switching means are arranged to operate ON and OFF concurrently with each other. A comparator circuit in accordance with an embodiment of the present invention can be used in applications in which detection of a small voltage signal wave of few tens or hundreds mV with a frequency of a order of 1 kHz is required, or in which it is necesary to reform such a signal wave. Reference is made, by way of example, to the accompanying drawings, in which: Fig. 1 is a schematic circuit diagram showing a comparator circuit comprising an operational amplifier with an open-loop circuit; Fig. 2 is a schematic circuit diagram for assistance in explaining cancellation of offset voltage effects in a comparator circuit comprising an operational amplifier; Fig. 3 is a schematic circuit diagram of a modified form of the circuit shown in Fig. 2; Figs. 4(a) and 4(b) are so-called Bode diagrams; Fig. 5 is a schematic circuit diagram of a comparator circuit according to an embodiment of the present invention; Fig. 6 is a schematic circuit diagram of a comparator circuit according to another embodiment of the present invention, modified with respect to the circuit of Fig. 5; ; Fig. 7 is a schematic circuit diagram illustrating an example of internal circuitry which can be employed in the comparator circuits of Figs. 5 and 6; Fig. 8(a) is a schematic circuit diagram of another embodiment of the present invention; Fig. 8(b) is a timing chart for assistance in explaining operations of the circuit of Fig. 8(a); Fig. 9(a) is a schematic circuit diagram of a comparator circuit according to another embodiment of the present invention; and Fig. 9(b) is a schematic circuit diagram of an example of a switch which can be aplied in the comparator circuit of Fig. 9(a). In the schematic circuit diagram of Fig. 5, showing a comparator circuit according to an embodiment of the present invention, VINI is a reference voltage which is input to an input terminal 9 connected to a noninverting input (+) of an operational amplifier 10, whilst VIN2 is a signal voltage, to be compared with the reference voltage VIN1, which is input to a terminal 11 connected to an inverting input (-) of the operational amplifier 10 via a switch 12 and a capacitor 13. The capacitor 13 is for holding the offset voltage of the operational amplifier 10, and hence is referred to as the offset voltage compensating capacitor hereinafter. An output 18 of the operational amplifier 10 is connected (via a switch 14) to the inverting input (-) of the amplifier 10 forming a common node (common connection point) with one terminal of the offset voltage compensating capacitor 13. A switch 17 is connected between the node (common connection point) of the switch 12 and the offset voltage compensating capacitor 13 and the input terminal 9. A serial circuit comprising a capacitor 15 and a switch 16 is connected between other terminals (not shown) of the operational amplifier 10. The capacitor 15 is for compensating phase lag of a signal between the terminals to which the serial circuit is connected and is therefore referred to as the phase compensating capacitor hereinafter. The operation of the comparator circuit of Fig. 5 is as follows. The switches 14, 16 and 17, each formed from MOS (Metal-Oxide-Semiconductor) transistors for example, operate to turn on and off concurrently with one another, according to an external control signal (indicated by S with an arrow in Fig. 5), whilst the switch 12, which is also formed from MOS transistors for example, operates to turn on and off with timing inverse with respect to turn-on and turn-off of the other switches, according to another external control signal indicated by S with an arrow in Fig. 5. Thus, when 14, 16, 17 are on 12 is off, and when 14, 16, 17 are off 12 is on. When the switch 12 is turned off and the switches 14, 16 and 17 are turned on, the operational amplifier 10 operates in a voltage follower mode wherein the inverting input (-) is provided with a negative feedback affording unity voltage gain, and only the offset voltage VOFF at the output 18 is held in the offset voltage compensating capacitor 13, because both the non-inverting input (+) of the comparator and the capacitor 13 are now connected to a common potential source, the reference voltage VIN1 At the same time, the phase compensating capacitor 15 is made active, and functions to prevent the operational amplifier 10 from self-oscillation in the manner explained with reference to Figs. 4(a) and 4(b). This means that the above operation can be stably maintained even when the reference voltage VIN1 is a high frequency voltage, of frequency up to fo', the frequency corresponding to the point of intersection of the curve C1' and the OdB line in Fig. 4(a). Then, when the switch 12 is turned on and the switches 14, 16 and 17 are turned off, the operational amplifier 10 operates in an open-loop mode and the phase compensating capacitor 15 is made inactive. At this time, the inverting input (-) of the operational amplifier 10 receives signal voltage VIN2 with superimposition of the offset voltage VOFF held in the offset voltage compensating capacitor 13. That is, VIN2 + VOFF is compared with VIN1, the reference voltage input to the non-inverting input (+). However, since the inverted output of the above VOFF component cancels the offset voltage VOFF standing on the output 18, a voltage corresponding to the exact difference of VIN2 and VIN1 appears on the output 18. In this sequence, the phase compensation by capacitor 15 does not function, and the comparison operation is carried out at the highest response speed of the comparator circuit. Fig. 6 is a schematic circuit diagram of an embodiment of the present invention modified with respect to the comparator circuit shown in Fig. 5, wherein the switch 12 is connected between the input terminal 9 and the non-inverting input (+) of the operational amplifier 10, while the input terminal 11 is directly connected to the offset compensating capacitor 13. Different from the circuit of Fig. 5, the reference voltage VIN1 and signal voltage VIN2 are respectively input to input terminals 11 and 9 in Fig. 6. However, the operation of the comparator circuit of Fig. 6 is essentially the same as that of the circuit shown in Fig. 5, except for a difference in the polarity of the output voltage corresponding to the comparison result. Fig. 7 is a schematic circuit diagram showing an example of internal circuitry of the comparator circuit (in particular the operational amplifier) of Figs. 5 and 6. Referring to Fig. 7, the operational amplifier 10 of Fig. 5 or 6 comprises a differential amplifier section formed from transistors Q1 to Q2, and an output amplifier section formed from a transistor Q5. The gates of the transistors Q1 and Q2 are respectively connected to an inverting input VIN(-) and a non-inverting input VIN (+) of the operational amplifier. Transistors Q3 and Q4 constitute respective loads for the transistors Q1 and Q2, and transistors Q6 and Q7, both controlled by a reference voltage VR, constitute respective constant current sources for the differential amplifier section and output amplifier section. VO is an output of the operational amplifier. VDD is a power supply voltage. As seen in Fig. 7, each of the switches 14 and 16 in Fig. 5 or 6 is composed of a pair of transistors, one p-channel and one n-channel, whose conduction channels are connected in parallel to each other. A switch formed in this way is referred to as a transmission gate. When the control signal S and its inverse signal S input to the respective gates turn to high level and low level, the switches 14 and 16 are turned on, hence a negative feedback loop from the output Vo to the inverting input VIN(-) and a partial negative feedback loop from the output Vo to the input of the transistor Q5, i.e. the output amplifier, via the phase compensating capacitor 15, are established. On the other hand, when the control signals S and S respective turn to low level and high level, the switches 14 and 16 are turned off, and both negative feedback loops are destroyed. Although the switches 12 and 17 in Figs. 5 and 6 are now shown in Fig. 7, they also may be composed of transmission gates, similarly to switches 14 and 16. Fig. 8(a) is a circuit diagram showing another embodiment of the present invention, wherein the comparator circuit as shown in Fig. 6 is used for reforming an analog signal waveform. Although in the example of Fig. 8(a) the comparator circuit of Fig. 6 is used, it will be appeciated that the comparator circuit of Fig. 5 can alternatively be used, or any other comparator embodying the present invention. The operation of the comparator circuit in Fig. 8(a) with respect to the input signal VIN and the reference voltage VREF is as explained with reference to Fig. 6. Output voltage Vo corresponding to the comparison result is held by a latching circuit 19 which is a D-type flip-flop circuit, for example, and output from a terminal 20. Fig. 8(b) is a timing chart for assistance in explaining operations of the waveform reforming circuit of Fig. 8(a). Referring to Figs. 8(a) and 8(b), the switches 12, 14, 16 and 17 turn on and off according to a clock signal CLK, wherein only the switch 12 turns off when the clock signal is at high level. An analog voltage signal (VIN) is input to the terminal 9, and a reference voltage (V ) is input to the terminal 11. The reference voltage VREF is generally set to be constant, the voltage V ) at the inverting input (-) of the operational amplifier 10 is kept constant at the level VREF + VOFF, VOFF being the offset voltage held in the capacitor 13. When the clock signal CLK is in high level, the voltage VIN(+) at the non-inverting input (+) of the operational amplifier 10 is at the level VREF. On the other hand, when the clock signal is in low level VIN(+) varies to follow the input signal voltage VIN. Therefore, only during a time period when the clock signal CLK is at low level is a voltage wave corresponding to the difference of the analog voltage signal VIN with respect to the reference voltage VREF output as shown by the curve Vo. The latching circuit 19 holds every signal input to its D terminal in accordance with the rise of the clock signal CLR, and outputs a signal wave VOLT from the terminal 20. Consequently, if the clock signal CLK is controlled so that its repetition frequency fcLK is n times the repetition frequency fvIN of the input analog voltage signal VIN wherein n represents a positive integer, and if the reference voltage VREF is set approximately at the mean voltage of the analog signal is VIN, the waveform of the analog voltage signal VIN is reformed as a binary digital signal. When the repetition frequency of the clock signal is sufficiently large compared to that of the signal to be reformed, it is unnecessary to establish such a strict relationship betwen fcLR and fVIN as is mentioned above. Such a wave reforming circuit has been practically employed as a slicer in a modem for a multi-channel access system and a personal radio communication system, as disclosed by authors, including the inventors, in the proceedings of the Custom Integrated Circuit Conference held May 1984 in Rochester, New York State, under the title 'A SINGLE CHIP 1200 BPS MSK MODEM FOR MULTI CHANNEL ACCESS'. In this application, f is approximately 115 CLK kHz, while fVIN is 1.2 to 1.8 kHz. Fig. 9(a) is a circuit diagram showing a further comparator circuit embodying the present invention, and Fig. 9(b) is a circuit diagram of an example of a switch applicable to the comparator circuit shown in Fig. 9(a). In contrast to the embodiments of the present invention shown in Figs. 5, 6, and 8, in the embodiment of Fig. 9(a) the offset voltage VOFF held in the offset voltage compensating capacitor 13 is input to the non-inverting input (+) of the operational amplifier 10 during the comparison sequence. For this purpose, switches 19 and 20 acting like a transfer contact in a electro-magnetic relay are employed. In Fig. 9(a), although each of the other switches 12, 14, 16 and 21 is shown to be constituted the same as the switches 19 and 20, each of them may, of course, be a single-pole switch. Fig. 9(a) shows the switches in the positions which they take for the voltage follower mode operation of the operational amplifier 10, i.e. for the sequence of charging of the capacitor 13 with the offset voltage. In Fig. 9(a), a reference voltage VIN1 and a signal voltage VIN2 are respectively input to the input terminals 9 and 11. In the same manner as in the operation of the circuit of Fig. 5, the output of the operational amplifier 10 is fed back to the inverting input (-) via switch 14, and the offset voltage VOFF is held in the offset voltage compensating capacitor 13. During this charging sequence, the switch 16 is turned on and the phase-compensating capacitor 15 is made active. In the comparison sequence, the switch 12 is turned on, and the signal voltage VIN2 is applied to the inverting input (-). At this time, since the switch 21 is turned off, and the switches 19 and 20 are switched to respective positions opposite to those shown in Fig. 9(a), the polarity of VOFF as applied from the capacitor 13 to the non-inverting input (+) is inverted with respect to the polarity of VOFF as fed back to the inverting input (-). That is, the reference voltage VREF (VIN1) input to the REF INl non-inverting input (+) is partially cancelled by the inverted VOFF Therefore, the difference between the input voltage VIN( ) to the inverting input (-) and the input voltage VIN(+) to the non-inverting input (+) is; VIN(+) VIN(-) = VREF #VOFF IN2 The inverted VOFF component input to the non-inverting input (+) cancels the VOFF standing on the output of the operational amplifier 10, hence, an exact comparison result corresponding to the difference between the reference voltage VREF and signal voltage VIN2 is obtained. The switches 19 and 20, also the others in Fig. 9(a) can be formed from transmission gates 22 and 23, each comprising a couple of FETs (field effect transistors), connected to each other as shown in Fig. 9(b). When respective control signals S and its inversion S applied to input terminals 24 and 25 of the switch are at high level and low level, respectively, the transmission gate 22 turns off and conduction between terminals 26 and 27 is prevented. At the same time, the transmission gate 23 turns on and conduction between terminals 28 and 29 is established. On the other hand, when the control signals S ad# S are of low level and high level, respectively, the transmission gate 22 is turned on whilst the transmission gate 23 is turned off, and conduction is established and prevented between the respective terminal pairs, 26 and 27, and 28 and 29, oppositely to the above case. By connecting the terminals 27 and 28 to form a common terminal 30, the circuit of Fig. 9(b) operates equivalently to an electromagnetic relay having a transfer contact. It is to be understood that modifications of the above-described embodiments of the present invention can be provided within the scope of the present invention. For example, the reference voltage and the voltage signal may be applied to inverting and non-inverting inputs oppositely to the way in which they are applied in the embodiments of Figs. 5, 6, 7, 8(a) and 9(a). For instance, the latching circuit in Fig. 8(a) may comprise a flip-flop circuit of a type other than D-type, for example a R-S (reset-set) type or T (trigger) type flip-flop circuit combined with supplemental gate circuits. In embodiments of the present invention, the reference voltage supplied to one of the input terminals 9, 11 may be ground, for example, or one half the voltage of a positive power source used for operating the comparator circuit, for example.

Claims: Claims: 1. A comparator circuit comprising: a differential amplifier having two inputs and an output; a first switching means connected between said output and one of said inputs of said differential amplifier; an offset voltage compensating capacitor having one end operatively connected to said one of said inputs; a second switching means; and a phase compensating capacitor, said phase compensating capacitor being operatively connected to said differential amplifier via said second switching means; wherein said first and second switching means are arranged and adapted to turn ON and OFF concurrently with one another, whereby said differential amplifier operates in a voltage follower mode when said phase compensating capacitor is made active (when said second switching means is ON), whilst said differential amplifier operates in an open-loop mode when said phase compensating capacitor is made inactive (when said second switching means is OFF). 2. A comparator circuit claimed in claim 1, further comprising: a third switching means connected between the other of said two inputs of said differential amplifier and the other end of said offset voltage compensating capacitor; and a fourth switching means connected to said other end of said offset voltage compensating capacitor; wherein said third switching means is arranged and adapted to turn ON and OFF concurrently with said first and second switching means, whilst said fourth switching means is arranged and adapted to turn OFF and ON respectively when said third switching means turn ON and OFF. 3. A comparator circuit claimed in claim 1, further comprising: a third switching means connected to the other of said two inputs of said differential amplifier and the other end of said offset voltage compensating capacitor; and a fourth switching means connected to said other input of said differential amplifier; wherein said third switching means is arranged and adapted to turn ON and OFF concurrently with said first and second switching means, whilst said fourth switching means is arranged and adapted to turn OFF and ON respectively when said third switching means turn ON and OFF. 4. A comparator circuit claimed in claim 1 further comprising: an external input terminal; third switching means, said third switching means being switchable to connect said one end of said offset voltage compensating capacitor to said one input of said differential amplifier or to said external input terminal; fourth switching means, said fourth switching means being switchable to connect the other end of said offset compensating capacitor to said external input terminal or to the other of said two inputs of said differential amplifier; and fifth switching means connected between said external input terminal and said other input of said differential amplifier; wherein said third switching means is operable to connect said one end of said offset voltage compensating capacitor to said one of said inputs of said differential amplifier, said fourth switching means is operable to connect said other end of said offset voltage compensating capacitor to said external input terminal, and said fifth switching means is operable to connect said other input of said differential amplifier to said external input terminal, during the voltage follower mode of operation of said differential amplifier, whilst said third switching means is operable to connect said one end of said offset voltage compensating capacitor to said external input terminal, said fourth switching means is operable to connect said other end of said offset voltage compensating capacitor to said other input of said differential amplifier, and said fifth switching means is operable to disconnect said other input of said differential amplifier from said external input terminal during the open-loop mode of operation of said differential amplifier. 5. A comparator circuit as claimed in any preceding claim, further comprising: a latching circuit for latching the result of comprison performed by said differential amplifier. 6. A comparator circuit as claimed in any preceding claim, wherein each of said first and second switching means is a transmission gate. 7. A comparator circuit as claimed in any preceding claim, wherein said one input of said differential amplifier and said other input of said differential amplifier are an inverting input and a non-inverting input, respectively. 8. A comparator circuit claimed in claim 7, wherein said non-inverting input is operatively connected to a reference voltage source. 9. A comparator circuit claims in claim 7, wherein said inverting input is operatively connected to a reference voltage source. iO. A comparator circuit as claimed in claim 8 or 9, wherein the value of said reference voltage is one half of a positive power source voltage. 11. A comparator circuit claimed in claim 8 and 9, wherein said reference voltage is ground potential. 12. A comparator circuit claimed in claim 4, wherein each of said third and fourth switching means comprises a pair of transmission gates having a pair of common gates, each of the common gates consisting of a gate of a p-channel transistor in one of said transmission gates and a gate of an n-channel transistor in the other of said transmission gates.

Inventors: GOTO, KUNIHIKO C/O FUJITSU LIMITED, YAMAMURA, TAKESHI C/O FUJITSU LIMITED
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: H03K5
IPC codes: H03F1, G01R17, H03K5, H03M1