HIGH VOLTAGE MOS/BIPOLAR POWER TRANSISTOR APPARATUS

Abstract: A high voltage MOS/BIPOLAR power transistor assem­ bly is described comprising in a monolithic embodiment thereof, an N channel MOSFET which is integrated with a PNP transistor. A P⁺ substrate emitter provides hole injec­ tion into an N base layer thereby insuring through conductiv­ ity modulation a low "on" resistance. The base current I B which is regulated by the channel resistance eliminates hot spots, forward-biased second breakdown and current hop­ ping.

Description: HIGH VOLTAGE MOS/BIPOLAR POWER TRANSISTOR APPARATUS By Chenming Hu Background of the Invention The present invention relates to power transistor apparatus in general and in particular, to MOS/Bipolar power transistor apparatus suitable for high voltage (4007 -- 2000v) applications. .Ideally, power transistors should have insulated yate drive, i,e, high current gain, be free of second breakdown, have low on-state resistance, high current ensities and no commutation time limit, be fast switch ing, have no (or extremely high) dv/dt.limits and ex tremely high difdt limi.ts, be easily adapted to packages for high current or double-side-cooling and, when incOrpo- rated in a monolithic integrated circuit, have optimum utilization of the integrated circuit area. Referring to the drawing and Figs. 1-7 enclosed herewith, prior known Mos-gated power transistor apparatus which are deficient in one or more of the above described ideal characteristics include the MOS-Darlington transistor (Figs. 1 and 2), the parallel MOS-bipolar tran sistor (Figs. 3 and 4), the MOSFET-gated thyristor (Figs. 5 and 6) and the Cascode transistor (Fig. 7). Referring to Figs. 1 and 2, the MOSFET and bipolar transistor devices shown therein are typically fabricated in physically separated cells. With MOSFET cells lumped into separate portions on the integrated circuit, the MOSFETS do not benefit from conductivity modulation. This results in a device having a characteristic high on-resistance (Ron) and low current densities. Moreover, the devices require many metal contacts, interconnections and diffused resistors which occupy large areas, partic ularly, if the MOSFET and bipolar cells are intermixed. For these reasons the use of large current packages is impractical. Referring to Figs. 3 and 4, the parallel MOS-bipolar power transistor apparatus shown therein recuires a four terminal package, and separate MOSFET and bipolar tran sistor drive circuits. The apparatus is subject to second breakdown unless complicated drive circuitry is used to turn off the base B of the NPN transistor before the gate G of the MOSFET. Moreover, the separation of the MOSFET and the bipolar cells, metal contacts and interconnections result in an inefficient use of the available area of an integrated circuit device utilizing the parallel MOS-bipolar technology. i Referrins to Figs. 5 and 6, the MOSFET-gated thyris tor shown therein is deficient in that it cannot be turned off by its gate G, but needs a current reversal to terminate its operation. It has a long commutation time itq limit as does other thyristors. Moveover, its MOSFET-celi to thristor-cell ratio of three-to-one results in an inefficient use of the available area for current conduction While While the thyristor of Figs. 5 and 6 and the appara tus of the present invention, as will be further described below, both use N material on a P+ substrate and rely on hole injection at the bottom PN junction for on-state operation, the prior known MOSFET-gated thyristor incorpo rates "thyristor cells" with floating P regions such that the positive feedback between the NPN and PNP transistors therein achieves latchup. This automatically precludes the possibility of turning off the thyristor by using its gate. Referring to Fig 7, the cascoded transistor appara tus shown therein requires separate bipolar and MOS drive circuitry and in general, is very difficult to embody in a monolithic integrated circuit, although, it does not suffer from second breakdown and can be turned off-very rapidly. Devices of the type shown in Figs. 1, 2 and 7 are discussed in Record of IEEE Power Electronics Specialists Conference, June 1982, pp. 371-377. A Device of the type shown in Figs. 3 and 4 is discussed in Technical Digest of IEEE International Electron Devices Meeting, December 1981, pp. 263-266. A device of the type shown in Figs 5 and 6 is discussed in Technical Digest of IEEE Interna tional Electron Device Meeting, December l980,#pp. 7#-82. SUMMARY OF THE INVENTION A general object of the present invention is to provide an improved MOS/bipolar power transistor. This and other objects are attained, in accordance with one aspect of the invention by a high voltage MOS/BIPOLAR power transistor assembly comprising a MOSFET device having a source, a drain, and a gate; a bipolar device having a collector, an emitter and a base; means for coupling said source and said collector to a common potential; means for coupling said drain to said base; and means for coupling said emitter to a source of potential having a magnitude which is greater than said common potential. The above and other objects features and advantages of the present invention will become apparent from the following detailed description of the invention in which: Figs. 1-7 are equivalent discrete and integrated circuits of prior art MOS-gated power transistor apparatus described above. Figs. 8 and 9 are discrete equivalent and monolithic embodiment respectively of an apparatus according to the present invention. Figs. 10-25 are partial cross sectional and plan views showing the fabrication steps of an apparatus according to the present invention. Figs. 26 and 27 are partial cross sectional and plan views of another alternative embodiment of the present invention. Fig. 28 is a partial cross sectional view of still another alternative embodiment of the present invention. Figs. 29 and 30 are partial cross sectional views of a reverse conducting transistor embodiment according to the present invention. DETAILED DESCRIPTION Referring to Figs. 8 and 9, there is provided in accordance with the present invention, an MOS device having a gate G, a drain D and a source S. The drain D of the Device Q1 is coupled to a base B ofa PNP transistor Q2' The emitter E of Q2 is coupled to a source of positive potential Vcc. The collector C of Q2 and the source of Q1 are toupled to a source of common potential designated by a ground symbol. In the monolithic embociment of the present invention as shown in Fig. 9, there is provided a substrate 1 comprising a semiconductor material having a P + type conductivity. Disposed on substrate 1 there is provided a first layer 2 of semiconductor material having an N type conductivity. Disposed in the layer 2, there is provided a second layer 3 of semiconductor material comprising a P+ type conductivity. Disposed in the layer 3, there is provided a third layer 4 of semiconductor material comprising an N+ type conductivity. Located between the layers 2 and 4 there is provided a region 5 of semiconductor material comprising a P type conductivity. Disposed on the layers 3 and 4, there is provided a metal contact 6. Over the layers 4, 5 and a portion of the layer 2 and insulated therefrom there is provided a gate member 7. As will be apparent from the following description, the MOS device Q1 is an N channel device comprising the layers 4, 5 and 2. The PNP transistor Q2 comprises the PNP layers 1, 2 and 3. In the above description of Figs. 8 and 9 of the present invention, a single cell is described. In practice, however, hundreds and even thousands of cells of the type described will be embodied in an integrated circuit using conventional wafer fabrication techniques as will now be described with respective Figs. 10-22. Referring to Figs 10-22, there is shown partial cross sections and plan views of a monolithic device embodying a plurality of the cells described above with respect to Figs. 8 and 9. Typically, the fabrication of the structure of Figs. 8 B and 9 is started with a layer of P+ semiconductor material 10. On the top of the layer lOr -there is grown an epitaxial layer of N type semiconductor material ll (Fig. 10). On top of the layer 11 there is deposited a layer of masking material 12, such as silicon dioxide (Fig. ill). After the deposition of the silicon dioxide layer 12, a mask is used for removing the polysilicon and silicon dioxide material to form holes therein designated C (Fig. 12). After the holes C are formed, the assembly appears from the top as a layer of silicon dioxide comprising a |plurality of holes C (Fig. 13). Thereafter, a relatively deep deposition 13 of P+ type semiconductor material is made through each of the holes C (Fig. 14). After the depositions 13 are ccmpleted, the silicon dioxide layer 12 is removed (Fig. 15). On top of the layers 11 and 13 there are deposited a new layer of silicon dioxide 12 and a layer 14 of conductive material such as polysilicon (Fig 16). Another mask is used for removing the poly silicon and silicon dioxide maternal to form a new hole D above each of the P+ layers 13 (Fig. 17), and the holes D being slightly larger than the holes C in Fig. 13. A deposition of P type material 15 is made through the new holes D (Fig. 18). After the depositions 15 are completed, the polysilicon layer 14 and the depositions 13 and 15 are coated with a layer of the insulating material 12. (Fig. 19). After the coating of the layer 12 is completed, a mask is again used for forming a pair of holes E above each of the P+and P layers 13 and 15 leaving there between a portion of the oxidized layer 12 (Fig 20). After the holes E are formed, a deposition of N+ type semiconductor material 16 is made through the holes E and into the P+ layer 13 and the P layer 15 Rig. 21). After the layer 16 is deposited, the assembly is again coated with a layer of insulating material 12 (Fig. 22). After the deposition of the layer 12 is completed, a mask is again used for forming a hole F through the layer 12 which extends from over a portion of one N layer 16 to over a portion of an adjacent N+ layer 16 (Fig. 23). After the hole F is formed, the top and bottom of the assembly is coated with a layer of conductive material 17 and 18, such as aluminum, for forming the emitter and collector/source contacts respectively (Fig. 24). A top view of the assembly as fabricated is shown in Fig. 25. Referring to Fig. 25, it may be noted that the device is preferably formed with the polysilicon layer 14 extending beyond conductive layer 17. By extending the polysilicon layer 14 beyond the aluminum layer 17, means are provided for attaching the gates of all of the devices to a source of external control signals. Similarily the front and the back layers of conductive materials 17 and 18 are readily available for connecting the emitter to a source of positive potential and the collector/source to a common potential such as ground. Referring again to Fig. 9, in operation, in the off-state, high voltage, e.g. 400-2000 volts, is sustained by the N- epitaxial or bulk material 11, as in conven tional VDMQS. -In the on-state, with the MOSFET on, the main device is a PNP transistor having a wide N base The base (electron) current 1B is supplied through the MOSFET. The MOSFET current can be large and provides a fast path for the initial current IE, as well as a large base current i for rapid turn-on of the bipolar tran sistor. The injection of holes from the P+ substrate I when the MOSFET is turned on, results in conductivity modulation in the N base layer 2 which insures a low on-resistance RON for the MOSFET and therefore the large 13 in the on-state. The large 13 keeps the bipolar transistor close to saturation and keeps the forward voltage drop VCE low. However, base current 1B is self-regulated. That is, the transistor cannot be saturated such that P-collector is forward biased with respect to the N-base. If this were not so, the MOSFET drain N- would be more negative than the source N+ and 13 would become negative. The bipolar transistor will hence be automatically biased to VCE, where VCE is approximately equal to 0.7v + RCHI/ (1+ #), where RCB is the channel resistance of the MOSFET and ss is the current gain of the bipolar transistor. RCB can be very small even in very high voltage devices. Since the transistor is never in saturation, its turn-off speed is optimized. Because 13 is self-regulated by the local RCH, which has positive temperature coefficient, phenomena such as hot spots, forward-biased second breakdown, and current hopping in parallel devices are eliminated. The wide base structure also eliminates the problem associated with the crowding of current at the edges of emitter fingers; since there are no emitter fingers, and achieves better current density than conventional bipolar trans is tors. At turn-off, when the MOSFET is turned off, the bipolar transistor undergoes an open-base turn-off. This need not be a slow process, since the electrons in the base of a low ss transistor can be dissipated through recombination or through injection into the emitter as quickly as can be achieved by the reverse base current in a high ss transistor. In fact, the rate of removal of storage charge is equal to IBR + IC/ss, where IBR is the reverse base current. In a low ss transistor, the second term can dominate and an open base (IBR = 0) turn-off can still be fast. For example, an open base turn-off in a transistor with ss=5 is equivalent to having IBR = IC/5 in a high ss transistor in terms of the rate of charge removal. The bipolar transistor, therefore, should have a relatively low ss. This may be achieved through lifetime control or through the use of emitter shorts, as described above with respect to Figs. 28 and 29. It is estimated that the storage time and the fall time together will be lower than 2 microseconds. Because the base is open, there is no current crowding under emitter fingers and no reverse-base second breakdown. Additionally, there is no commutation time tq requirement, unlike the case of thyristors. Indeed, the above discussion of turn-off clearly states that the device voltage need not be reversed during or after turn-off. While While the present invention uses an N layer on a substrate and relys on hole injection at the bottom P+/N unction for on-state operation as is utilized in the #OSFET-gated thyristor of Figs. 5 and 6, the apparatus of the present invention not only eliminates the "thyristor cell" with floating P regions, but also takes great care in shorting out the base resistance of the parasitic NPN ransistors in the MOSFET cells. Without these special brecautions, the parasitic transistor could cause latchup nd prevent gate turn-off. A sufficient condition for reventing latchup is to make RB . IC' < O.6v Where RB is he base resistance of the parasitic NPN transistor and IC' is the hole current collected by the P (not the P+) region. Even though the apparatus of the present invention is not a thyristor, it can be turned off by current reversal (line or circuit commutation) with the MOSFET in it the on-state. In this mode, the turn-off of one device may be synchronized with a turn-on with another device without conduction overlay or discontinuity. Referring to Figs. 26 and 27, there is shown another embodiment of the present invention in which both RB and 1C' are reduced. In this embodiment the deep P+ regions make additional connections with a P region in an attempt to reduce the h . They also increase RCH of the MOSFET i,and increase the on-state voltage drop. Referring to Fig. 28, by adding an additional N or N+ layer between the N- and P layers, punch-through can be avoided and more voltage may be sustained for the same N- layer thickness. This N or N layer also reduces the transistor ,Q by increasing the base Gummel number, which may be desirable for achieving short turn-off time and higher open-base breakdown voltage of the PNP transistor. Referring to Figs. 29 and 30, for inverter applica It ions, reverse conducting switches are desirable. The apparatus according to the present invention can be made to conduct in the reverse direction by using structures as shown in Figs. 28 and 29. The "emitter shorts" shown therein will reduce thea of the bipolar transistor and may help with the turnoff speed though increasing the j'on-state voltage drop. If the effect onS is to be minimized, these "shorts" may be placed near the edge of the chip and under the contact pads. While a preferred embodiment and several alternative embodiments of the present invention are disclosed, it is contemplated that other changes may be made to the embodiments described without departing from the spirit and the scope of the present invention. Accordingly, it is intended that the scope of the present invention not be limited to the embodiments described, but be determined by reference to the claims hereinafter provided and their !equivalents.

Claims: WHAT IS CLAIMED IS: 1. A high voltage MOS/BIPOLAR power transistor assembly characterized by: a MOSFET device having a source, a drain, and a gate; a bipolar device having a collector, an emitter and a base; means for coupling said source and said collector to a common potential; means for coupling said drain to said base; and means for coupling said emitter to a source of potential having a magnitude which is greater than said common potential. 2. An assembly according to Claim 1 characterized in that said bipolar device comprises a PNP transistor means and said emitter coupling means comprises means for coupling said emitter to a source of positive potential. 3. An assembly according to Claim 1 or 2 characterized in that said bipolar device is adapted to operate with a positive potential in excess of 400 volts coupled to said emitter. 4. An assembly according to Claim 2 or 3 characterized in that said source, drain and gate of said MOSFET device and said collector, emitter and base of said bipolar device are embodied in a monolithic structure. 5. An assembly according to Claim 4 characterized in that said monolithic structure comprises: a substrate of material comprising a first type of conductivity for providing said emitter; a first layer of material comprising a second type of conductivity on said substrate for providing said base and said drain; a second layer of material comprising said first type of conductivity disposed in said first layer for providing said collector and a channel for said MOSFET; a third layer of material comprising said second type of conductivity disposed in said second layer for providing said source; first means for electrically coupling said second and said third layers to a source of said common potential; second means for electrically coupling said substrate to said source of potential having a magnitude greater than said common potential; ; electrically conductive means overlying said first, said second and said third layers and electrically insulated therefrom for providing said gate; and third means for electrically coupling said electrically conductive means to a source of signals for controlling current flow through said substrate, said first and said second layers. 6. An assembly according to Claim 5 characterized in that said first type of conductivity is p-type conductivity and said second type of conductivity is n-type conductivity. 7. An assembly according to Claim 6 characterized in that said second layer comprises a first portion underlying said first means and said third layer and a second portion located between said first and said third layers, said P type conductivity in said substrate and said first portion of said second layer is p+ type conductivity and said n type conductivity in said third layer is n+ type conductivity.

Inventors: HU, CHENMING
Applicants: FAIRCHILD CAMERA & INSTRUMENT CORPORATION
Application year: 1984
Main classification: H01L27
IPC codes: H01L29, H01L21, H03K17, H01L27