SHORT-CHANNEL THIN-FILM FIELD-EFFECT TRANSISTOR, AND METHOD OF PRODUCING IT

Abstract: Disclosed is a thin film field effect transistor (1) where the horizontal channel length is less then about 10 microns. Also, disclosed is a method of lithographically forming a channel having a channel length less then the resolution the lithographic means (101).

Description: The present invention relates to a method of forming a current conduction channel in a generally planar thin film structure. Such structures are used for the production of field effect transistors (FET) as described e.g. in EP-A-0 090 661. Usually some layers of the thin film structure are deposited e.g. by chemical vapor deposition (CVD) on a substrate. In this connection it is also usual to optically expose a photoresist film in order to remove parts of thin film layers before the photoresist film is removed and further layers are deposited. Photolitographically methods allow dimensions in the range of about 10 µm. Furthermore Siemens Forschungs- und Entwicklungsberichte, 1977, volume 6, pages 156-158, Springer-Verlag, Berlin, describes an alternative method to improve the feature size by wet etching methods of metal layers, thereby undercutting a photoresist layer, provided the metal layer thickness is not thicker than 1 µm. Thin film field effect transistors contain source and drain electrodes electrically in contact with a semiconductor film, and capable of forming a current channel through the semiconductor between the source and drain electrodes under the influence of a gate electrode. The current flow through the current channel in the semiconductor film, between the source electrode and the drain electrode is controlled by the application of a voltage to the gate electrode. The gate electrode is in proximity to the semiconductor current channel but is electrically insulated therefrom. The voltage on the gate electrode produces an electric field which accumulates a charged layer near the semiconductor surface. This charged layer forms the current conducting layer, i.e., the current channel, in the semiconductor. Thin film field effect transistors capable of high output currents and high speed operations are useful in such diverse applications as large area displays, computer memories, central processing units, and random access memory units. In thin film field effect transistors, the device output current and the operating speed are dependent on the length of the semiconductor current conduction channel formed between the source electrode and the drain electrode under the influence of the gate electrode. The source to drain output current is inversely proportional to the channel length, while the operating frequency is inversely proportional to the square of the channel length. Thus, when the channel length of the device is reduced by an order of magnitude, for example, from 10 µm to 1 µm, the output current should increase 10 fold and the operating speed or frequecy should increase 100 fold. The operating speed is also dependent on the interelectrode capacitance of the device, larger capacitance causing slower operation. The extension of the gate electrode over the source and drain electrodes is a common source of interelectrode capacitance, and is referred to as overlap parasitic capacitance. The overlap is a result of limited photolithographic resolution. Large area arrays of multiple thin film field effect transistors may be prepared by standard 10 micron photolithography. When thusly prepared, the minimum channel length which can be achieved in planar thin film transistor arrays is limited by photolithographic feature, typically on the order of 10 microns. One way to overcome the limitations inherent in large area photolithographic resolution is to utilize a vertical structure where channel length is determined by vertical separation of source and drain electrodes. The transistor therein disclosed includes source and drain regions vertically displaced with respect to each other relative to a substrate and having a channel formed therebetween. The length of the channel is a function of the vertical displacement distance between the source and drain and is substantially independent of the constraints otherwise imposed by standard 10 µm photolithography. Further improvement in vertically arrayed thin film field effect transistor structure is described in the commonly assigned copending U.S. Application of Hellmut Fritsche, et al for High Performance, High Voltage, Small Area Thin Film Transistor And Method Of Making Same . The vertical thin film field effect transistor therein disclosed includes source and drain electrodes vertically displaced with respect to each other and relative to the substrate, with an insulating layer therebetween and having a semiconductor current channel extending along the non-coplanar, that is the non-horizontal or diagonal edges of the source and drain electrodes and the insulating layer. A still further improvement in vertically arrayed thin film field effect transistor structure is described in the commonly assigned copending U.S. Application of Zvi Yaniv, et al for High Performance Thin Film Transistor Having Improved Carrier Injection . The transistor therein disclosed includes the source and drain electrodes vertically displaced with respect to each other relative to a substrate, with a deposited semiconductor extending along the non-coplanar, i.e. non-horizontal or diagonal, edges of the source and drain electrodes, where the contacts between the source and semiconductor and the semiconductor and the drain electrodes have a carrier injection material incorporated therein. A further improvement in thin film field effect transistor structure is described in the commonly assigned copending U.S. Application of Gregory Hansell, et al for Thin Film Transistor Having Annealed Gate Oxide And Method Of Making Same . The transistor there disclosed has an annealed insulator layer between the gate electrode and the semiconductor current channel. Common to all of the above described field effect transistors is a vertical structure, that is, a structure where the drain is vertically displaced from the source. It is an object of the present invention to improve the method of forming a current conduction channel by similar means in order to form channel length less than the feature size of industrial photolitographic processes. The invention is claimed in claim 1 and preferred embodiments in sub-claims. The invention provides a method of photolithographically forming a narrow feature device where the smallest dimension of the feature is less then the resolution of industrial photolithographic process. According to the process herein contemplated, a thick film of photoresist is deposited atop a layer of the material to be etched in order to form the feature. The photoresist is exposed and developed and thereafter the underlying material is etched for a time sufficient to undercut the photoresist. The photoresist is wetted with a suitable solvent whereby to form an inward taper in the photoresist, i.e. an overhang at the top, remote from the material to be etched and an undercut adjacent the material to be etched. The underlying material is then etched, so as to form an undercut therein. In this way, a feature may be prepared having one dimension less than the dimension of the corresponding feature in the photomask. Alternatively, without removal of the remaining photoresist, a facing feature may be shadow deposited with a unidirectional or collimated deposition beam. This avoids the deposition of material within the shadow of the remaining photoresist. In this way, a feature is obtained having one dimension defined by the two deposits, the dimension being less than the dimension of the corresponding feature in the photomask. The invention provides a method of fabricating a thin film field effect transistor by forming a thick film of photoresist atop a material to be etched, exposing the photoresist through a photomask, developing the photoresist, etching the underlying material to undercut the photomask and form an electrode of one polarity and thereafter, without removal of the remaining photoresist, shadow depositing the opposite electrode. The shadow deposition is carried out from a unidirectional or collimated source. In this way, deposition is avoided within the shadow of the photoresist and first electrode. The short channel thin film transistor can be formed using a deposited semiconductor, for example an amorphous or polycrystalline semiconductor chosen from the group consisting of silicon, silicon alloys, germanium, and germanium alloys. The gate insulator separates the gate electrode from the semiconductor and may be an electrically insulating oxide. In a preferred exemplification the gate electrode may be formed by depositing a film of conductor, depositing a thick film of photoresist atop the conductor film, exposing and developing the photoresist, and thereafter etching the conductor film so as to undercut the photoresist and form a gate electrode having one dimension less than the corresponding dimension of the photomask. In this way, a device characterized by the substantial absence of overlap parasitic capacitance is formed. Figure 1 is a isometric view of a thin film field effect transistor and Figure 2 is an isometric view of an alternative thin film field effect transistor produced in accordance with the invention. Figures 3A through 3I show a method of preparing a transistor of the invention. There is provided a planar thin film field effect transistor 1, shown in Figure 1 and an integrated circuit, not shown. The integrated circuit contains one or more of the field effect transistors 1. An individual field effect transistor 1 contains a substantially horizontal substrate 21 having a gate electrode 23. A gate insulator layer 25 is in contact with the gate electrode 23, separating the gate electrode 23 from the semiconductor material 27 in which the current channel forms. The semiconductor 27 is a substantially horizonal film of semiconductor material insulated from the gate electrode 23 by the gate insulator 25. The first electrode 31, for example a source electrode, is on the horizontal film of deposited semiconductor material 27 while a second electrode 33, for example, a drain electrode, is also on the horizontal film of deposited semiconductor material 27. The space between these two electrodes defines a current channel 29 in the deposited semiconductor material 27, between the first electrode 31 and the second electrode 33, the current channel forming under the influence of a potential applied to the gate electrode 23. The electrodes 31 and 33 typically have a height 51 of from about 0.05 to about 1.0 µm and preferrably from about 0.1 to about 0.3 µm. The first electrode 31, is formed by deposition and etching, and has a width 55 of from about 3 to about 9.6 µm. The channel 29 has a channel length 53, i.e., a minor horizontal dimension, of less then 10 µm and preferrably from about 0.2 to about 2 µm, where industrial photolithography has a minimum feature size of about 10 µm. The device 1, and more particularly the semiconductor 27 between the two electrodes 31 and 33, has a major horizontal dimension 57 of from about 50 to about 1,000 µm and generally of from about 100 to about 500 µm, the exact length being a function of the current to be passed. Substrate 21 may be an insulator or a conductor with an insulator film thereon. It may further be characterized by having addressing means incorporated therein. The gate electrode 23, has a thickness of from about 0.05 to about 1 µm and preferrably from about 0.1 to about 0.3 µm. It is most commonly formed of a conductive metal that is chemically compatable with the materials used to form thin film field effect transistor, for example chromium, molybdenum, alloys of molybdenum and tantalum, and aluminum. When subsequent metal, oxide or semiconductor layers are deposited after the gate electrode 23, the gate electrode is preferably formed of chromium, molybdenum, or alloys of molbdenum and tantalum. However, when the gate electrode 23 is the last layer to be deposited, it may be formed of aluminum. The insulator 25 is generally from about 0.05 to about 1 µm thick and preferrably from about 0.1 to about 0.3 µm thick. The gate insulator 25 may be prepared of silicon oxide as SiO x , a silicon nitride as Si x N y , a silioxynitride as SiO x N y , or alumina as Al₂O₃. Especially preferred are the silicon oxides and siloxynitrides. When the gate insulator layer 25 is provided by an oxide or oxynitride the gate insulator layer 25 may be prepared by the plasma enhanced chemical vapor deposition of silane and nitrous oxide or silane, ammonia, and nitrous oxide. The deposited semiconductor layer 27 is from about 0.05 to about 1 µm thick, and preferrably from about 0.1 to about 0.3 µm thick. The semiconductor layer 27 may be formed by the plasma assisted chemical vapor deposition of silane, silicon tetrafluoride, and, where required, phosphine, arsine or diborane gases, as described, for example, in US-A-4217 374. The electrodes 31 and 33 are from about 0.05 to about 1 µm thick and preferrably from about 0.1 to about 0.3 µm thick. They may be highly doped amorphous materials, as n+ materials deposited by various unidirectional deposition techniques, or they may be metals, whereby to provide the short channel 29 as well be described more fully hereinafter. When the electrodes 31 and 33 are metal electrodes there may be a thin film of n+ material, e.g. from 0.05 to about 0.1 µm thick, between the electrodes 31 and 33, and the semiconductor 27. The process of preparing the thin film field effect transistors 1 comprises the steps of forming a thick film of photoresist atop a film of etchable material, e.g., material used to form the gate electrode 23 or to form one of the source 31 and drain 33 electrodes, and exposing the photoresist through relatively coarse resolution exposure means, e.g., a photomask having a minimum feature size of about 10 µm. Thereafter, without excluding intermediate steps, the photoresist is developed and the etchable material is then etched under conditions that result in undercut thereof. The extent of undercut is such as to provide at least one dimension of the remaining etchable material less than the minimum feature size of the photomask. That is, the length 55 of the source 31 or drain 33, or the length 59 of the gate electrode 23 is less than the corresponding feature size 131 of the photomask 101. Thereafter, the photoresist 71 may be removed as where further layers of insulator, semiconductor, or metal, or multiple layers thereof are to be subsequently deposited. Alternatively, the shadow of the photoresist 71 and of the deposited feature, e.g., source electrode 31. may be used to shadow a portion of the underlying material, e.g., semiconductor layer 27, or the substrate 21, during the unidirectional beam deposition of the opposite electrode, e.g., drain electrode 33. In this way, there is provided a thin film, field effect transistor 1 having a source 31 to drain 33 dimension 53 in the semiconductor film 27 less than the minimum feature size 131 of the photomask 101. In a particularly preferred exemplification of the invention where the photoresist 71 is to be used to mask a portion of the underlying, non-etched material, the shadow effect of the photoresist 71 may be enhanced by causing the photoresist to swell between exposure and development. According to this exemplification, the process comprises the steps of forming a thick film of a photoresist 71 atop etchable material, and exposing the photoresist 71 utilizing relatively coarse resolution exposure means. Relatively coarse resolution exposure means are exemplified by photomasks 101 having a minimum feature size 131 of about 10 microns. The photoresist 71 is developed whereby the combination of exposure, swelling, soft-baking and development provides a tapered surface having an overhang in portions of the photoresist 71 remote from the etchable material and an undercut in portions of the photoresist 71 adjacent the etchable material. The etchable material, e.g. conductor 31 in Figure 3F, is then etched. Thereafter, without removing the remaining photoresist 71, a deposition 33 is shadow deposited atop the subjacent surface, e.g. , semiconductor 27 in Figures 3A through 3I, facing and spaced from the remaining etchable material 31 and photoresist 71, beyond the shadow of the remaining etchable material 31 and photoresist 71. This forms a channel 29 across the subjacent material 27 between the etchable material 31 and the shadow deposited material 33. The channel 29 is narrower than the feature size 131 of the photomask feature 129. More particularly, the method of the invention may be utilized to fabricate a planar thin film field effect transistor 1 having successive horizontal layers of gate electrode material 23, gate insulator material 25, deposited semiconductor material 27, and deposited conductor material 31 and 33. As herein contemplated and shown in Figures 3A through 3F, the fabrication process includes the steps of: (a1) forming a layer of etchable gate electrode material 23 atop an insulative or non-conducting substrate 21 as shown in Figure 3A; (a) depositing and soft-baking a thick film of photoresist 71 atop the etchable gate electrode material layer 23 as shown in Figure 3B; (b) exposing the thick film of photoresist 71 to light through a photomask 101 having a feature 129 with a feature size 131 greater than the desired size of the corresponding feature to be formed in the etchable gate electrode material 23; (c) developing and hardbaking the photoresist as shown in Figure 3C; (d) etching the etchable gate electrode material 23 to expose substrate 21 and thereafter over-etching the gate electrode material 23 whereby to undercut the photoresist 71, thereby forming a gate insulator 53 having a dimension less than the dimension 131 of the corresponding feature 129 of the photoresist as shown in Figure 3D, the resulting gate electrode, having a short length and substantially reduced overlap, provides a device characterized by substantially reduced overlap parasitic capacitance; (e) removing the photoresist 71, and successively depositing films of gate insulator material 25, semiconductor material 27, optional n+ semiconductor material, and etchable source electrode material 31 atop the gate electrode and substrate as shown in Figure 3E; (f) depositing and soft-baking a thick film of photoresist 71 atop the thin film of etchable electrode material 31 as shown in Figure 3E; (g) exposing the photoresist 71 through a photomask 101 as shown in Figure 3E; (h) optionally soft-baking and swelling the photoresist 71, and thereafter developing the photoresist 71 as shown in Figure 3F; (i) etching the underlying etchable material 31 whereby to expose n+ semiconductor material or semiconductor material 27 and thereafter over-etching the etchable material 31 whereby to form an undercut as shown in Figure 3G; (j) without removing photoresist 71, shadow depositing the opposite electrode 33 with unidirectional or collimated metal deposition means whereby to leave a non-metallized portion 29 between the electrodes 31 and 33 as shown in Figure 3H; (k) removing the photoresist, and optionally removing the unused portions of the electrodes 33, as shown in Figure 3I. The source 31 and drain electrodes 33 may be formed beneath, and before the gate insulator 25 and gate electrode 23, with the gate electrode 23 being above the semiconductor layer 27, and source 31 and drain 33 electrode pairs. According to a still further exemplification the source 31 and drain 33 electrodes may be deposited between the gate insulator 25 and semiconductor 27 layers. Where one of the source and drain electrode pair 31, 33 is shadow deposited, and where the photoresist is swollen, the photoresist is deposited as a very thick film, soft-baked for about 30 minutes at about 90 °C, exposed normally, swollen with an organic solvet, soft-baked again for about 30 minutes at about 90 °C, developed normally, hard-baked at about 125 °C for about 30 minutes, and the masked material over-etched whereby to produce the undercut. The organic solvent is most commonly a saturated hydrocarbon, e.g., an aliphatic or aromatic hydrocarbon. Especially preferred are aromatic hydrocarbons The solvent may be a halogenated, saturated hydrocarbon. Especially preferred are halogenated aromatic hydrocarbons, exemplified by chlorobenzenes, with monochlorobenzene being especially preferred. The solvent wets the photoresist for about 7 to 15 minutes at room temperature. The action of the solvent forms a tapered surface in the photoresist having an overhang in the portions of the photoresist remote from the conductor and an undercut in the portions of the photoresist adjacent to the conductor. The deposited first conductor is etched whereby to expose portions of the deposited semiconductor 27 and then over-etched to form the undercut. A second conductor is then shadow deposited on to the deposited semiconductor using unidirectional deposition techniques, for example, evaporation or sputtering, whereby to deposit the second conductor on exposed portions of the semiconductor beyond the shadow of the remaining photoresist atop remaining first conductor. The photoresist may be a positive or negative photoresist. It is deposited to a thickness of from about 0.5 to about 5 µm and preferrably from about 2 to about 4 µm. The photoresist is soft-baked exposed, developed, and hard-baked normally. Thus according to a method of this invention a layer of photoresist 71, for example Shipleys positive AZ-1350-J is deposited. A mask 101 is then placed over a portion of the positive photoresist 71 and the unmasked portion of the photoresist layer 71 is exposed and developed. The unmasked portion is exposed to a light having an intensity of about 300 to about 500 mJ/cm² for a period of approximately 10 to 15 seconds. Thereafter, the photoresist is hard-baked and developed. A suitable developer has been found to be one part of Shipley developer AZ-311 with three parts of water. The layer is etched in a wet etching process, for example in nitric acid-acetic acid solution, to provide the undercut. By over-etching is meant that the etch time is longer than that normally utilized to uncover the subjacent material. Typically, the etching time is extended to three to fifty fold relative to the time required to uncover the subjacent material. Typical etching materials include pawn solution for aluminum, ammonium nitrate-nitric acide for chromium, and other etchants are well known in the art. For etching chromium, an etchant containing 29.75 g of ammonium nitrate, 11.2 mℓ of deionized water, and 225 mℓ of dionized water, is used for about 5 to 20 minutes at 20 to 30°C. For aluminum pawn etchant is used at 70 to 80 degrees centigrade for 6 to 10 minutes. According to one particularly desirable method of this invention an electrode is prepared on a polyimide coated stainless steel substrate where a gate electrode of suitable conducting material, for example chromium, molybdenum-tantalum alloy or aluminum, and preferably chromium, is deposited atop the polyimide film to a thickness of from about 0.05 to about 1 µm and preferrably between 0.1 and 0.3 µm. A thick film of photoresist, i.e. from about 2 to about 4 µm thick, is then deposited atop the gate electrode material, exposed and developed, the gate electrode etched to undercut the photoresist, and the photoresist removed. An insulating layer of silicon oxide is thereafter deposited atop the chromium or other gate electrode material, for example by the plasma assisted chemical vapor deposition of silane and oxygen, to a depth of from about 0.05 to about 1 µm and preferrably from about 0.1 micron to about 0.3 µm. Thereafter a thin film of an amorphous semiconductor material, for example a semiconductor material containing an alloy of silicon, a density of states reducing material as fluorine, and hydrogen is deposited. The amorphous semiconductor material may be deposited by the plasma assisted chemical vapor deposition of silane and fluorosilane. Preferrably the film is of a thickness of from about 0.05 to about 1 µm and in a preferred exemplification from about 0.1 to about 0.3 µm. Atop the amorphous semiconductor is deposited a relatively uniform film of a metal, for example aluminum or chromium. The metallization may be carried out by the sputtering of chromium or the evaporation of aluminum. The metallized film has a thickness of from about 0.05 to about 1 µm preferrably from about 0.1 to about 0.3 µm. Etching is then carried out by depositing a photoresist, for example a positive photoresist such as Shipley A7-1350-J to a thickness of from about 2 to 4 µm atop the aluminum or chromium. After exposure and before developing, the photoresist is contacted with a halogenated aromatic hydrocarbon, such as monochlorobenzene, for about 7 to 15 minutes at a temperature of about 20 to 50 o C. The photoresist layer is then conventionally developed. The exposed metal is etched. In the case of aluminum, etching is carried out in a solution of 95 mℓ of deionized water, 95 mℓ of nitric acid, 250 mℓ of acetic acid, 1,425 mℓ of phosporic acid, at 45 o C for about 8 minutes whereby to obtain the desired undercut. After etching, and without removing the remaining photoresist, metallization is carried out, for example by evaporative deposition of aluminum or sputtering of chromium. Metallization provides a film of metal of about the same thickness as the original film of etchable material. The photoresist is striped off as is well known in the art, for example with acetone. Optionally another photoresist film may be applied, to protect the shadow deposit of the second metal, adjacent the channel, while the remote shadow deposited metal is etched to remove unnecessary metal, thereby defining the size of the device. Subsequently the exposed surface of semiconductor material and electrodes may be metallized, whereby to form address lines. The length 53 of the channel 29 is believed to be a function of the thickness of the photoresist layer and of the deposited metal layers and of the extent of undercut.

Claims: Method of forming a current conduction channel (29) having a channel length substantially less than a predetermined minimum feature size in a generally planar thin film structure (1) and extending from an etchable material (31) across a subjacent material (27), comprising: a) forming a thick film of photoresist (71) atop deposited etchable material (31); b) optically exposing the photoresist (71) utilizing relatively coarse resolution exposure means having said predetermined minimum feature size; c) wetting the photoresist (71) with a solvent to cause the photoresist (71) to swell and thereafter developing the photoresist (71) thereby forming an inwardly tapered surface on the photoresist (71) having an overhang in portions thereof remote from the etchable material (31); d) etching the etchable material (31) sufficiently to uncover subjacent material (27) and to undercut a portion of the photoresist (71), and to uncover the subjacent material (27); and e) shadow depositing material (33) atop the uncovered subjacent material (27) beyond the shadow of the undercut photoresist (71) and remaining etchable material (31), whereby to form said channel (29) across the subjacent material (27) between the etchable material (31) and the shadow deposited material (33); the channel (29) being narrower than the predetermined feature size of the exposure means. Method as claimed in claim 1, further comprising the step of: (f) soft-baking the photoresist (71) after the wetting step and before the developing step. Method as claimed in claim 1 or 2, characterized in that a positive photoresist (71) is used and that a thickness of the photoresist film is selected of the range of about 0,5 to about 5 µm. Method as claimed in one of the preceding claims, characterized in that a halogenated aromatic hydrocarbon is used as a solvent. Method as claimed in claim 4, characterized in that a monochlorobenzene is used as the halogenated aromatic hydrocarbon. Method as claimed in one of the preceding claims, characterized in that a photomask (101) is used as the relatively coarse resolution exposure means and that the minimum feature size of the photomask is about 10 µm. Method as claimed in claim 6, characterized in that the channel length (53) is in the range from about 0,2 µm to about 2 µm.

Inventors: VESEY, DAVID J., YANG, MOHSHI
Applicants: ENERGY CONVERSION DEVICES, INC.
Application year: 1984
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L27