IMPROVED MULTIPLIER ARCHITECTURE

Abstract: An improved multiplier is disclosed for multiplying a first operand times a second operand, which includes a Booth-­ type translator (22) having an input connected to receive the first operand (Y), for translating the binary expression of the first operand into a sequence of signed digits. The multiplier further includes a partial product generator (30) having a first input connected to the output of the translator and a second input connected to receive the second operand (X), for multi­ plying the translated first operand times the second operand and furnishing partial products consisting of signed digits. The multiplier further includes an array of adders (36), each adder having having its inputs connected to two of the signed digit outputs from the partial product generator, for providing a sum consisting of a sequence of signed digits. The multiplier further includes an inverse translator (40) having an input connected to the output of the adders, for operating on the sequence of signed digits furnished by the adders, for provid­ ing a conventional binary expression for the product of the first and the second operands.

Description: IMPROVED MULTIPLIER ARCHITECTURE The invention disclosed broadly relates to digital multipliers and more particularly relates to binary digital multipliers. Existing multipliers which operate on pairs of binary operands suffer from several deficiencies which contribute to the prolongation of their multiplication operations. For example, the addition of the partial products requires the propagation of carry bits which can require an extensive increment in time necessary for the carry bits to fully propagate through all of the binary bit orders. A second problem is that the addition of the partial products is conventionally done in a sequential manner in order to avoid undue complexity in the adder circuitry. Parallel operations, which could otherwise shorten the duration of the addition of the partial products, cannot be conveniently carried out without complex arithmetic circuitry capable of handling multiple carry bits generated in any particular bit column. It is therefore an object of the invention to provide an improved multiplier. It is a further object of the invention to provide an improved multiplier having a shorter duration for its operation. It is still a further object of the invention to provide an improved multiplier which enables the simplified addition of partial products in parallel. It is yet a further object of the invention to provide an improved multiplier which eliminates the propagation of binary carry bits in the addition of its partial products, in an improved manner. It is yet a further object of the invention to provide an improved multiplier which has a duration for the addition of partial products which grows at a rate less than a linear rate with respect to the size of the operands multiplied. These and other objects, features and advantages of the invention are accomplished by the improved multiplier disclosed herein. This multiplier for multiplying a first operand times a second operand, includes a Boothtype translator having an input connected to receive the first operand, for translating the binary expression of the first operand into a sequence of signed digits. The multiplier further includes a partial product generator having a first input connected to the output of the translator and a second input connected to receive the second operand, for multiplying the translated first operand times the second operand and furnishing partial products consisting of signed digits. The multiplier further includes an array of adders, each adder having an input connected to two of the signed digit outputs from the partial product generator, for providing a sum consisting of a sequence of signed digits. The multiplier further includes an inverse translator having an input connected to the output of the adders, for operating on the sequence of signed digits furnished by the adders, for providing a conventional binary expression for the product of the first and the second operands. The improved multiplier is capable of faster operation than has been available in the prior art because it is capable of adding pairs of partial products simultaneously, in parallel by virtue of the signed digit mode of expression for those partial products and the special rules of addition provided by the adders. In addition, by virtue of the signed digit form for the partial products which are added by the adders, carry bits are not propagated beyond the adjacent higher order signed digit position. In this manner, the time consumed in prior art multipliers in carrying out the process of adding the partial products is significantly reduced because lengthy carry bit propagation is avoided. Indeed, the time necessary to carry out the addition of partial products in the improved multiplier increases at a lower rate proportional to the logarithm to the base 2 of the number of binary bits in the operands, and this can be contrasted with the linear rate of increase of the partial product addition time in prior art multipliers of comparable architectural simplicity. In the sequel, an embodiment of the improved multiplier is described with reference to the drawings listed below: Figure 1 is a functional block diagram of an improved multiplier according to the invention; Figure 2 is a schematic diagram of an improved organization for the addition of the partial products in a multiplier according to the invention; Figure 3 is a detailed view of a portion of the functional elements described in Figure 2. The architectural features of the new multiplier which is faster in operation than are prior art multipliers are disclosed in Figures 1 to 3. The multiplier design summary of Table 1 shows four stages of the design. First is the translate stage for the two inputs X and Y to the multiplier. This translation is similar to the conventional Booth-type of translation. After the Booth translation, the multiplication by single signed digits takes place. The multiplier forms partial products by a shift and a multiplex operation to invert the signs when necessary. Following the multiplication, the adder tree combines the partial products. It is a no ripple adder designed for a pair of signed digit inputs and it absorbs the carry from the previous column of adders. This can be referred to as a carry sponge" adder. After all the additions are completed and the final multiplied number comes out of the last adder stage, the number is still in the signed digit form in which it has both plus and minus digits in various bit positions. Before the result can be furish- ed, an inverse translation is necessary to put it back into standard binary form. That inverse translation does involve a ripple which is intended to be rippled through transmission gates for high speed and which is easily implemented with FET transmission gates. Thus, there are four stages: translate, multiply, add, and inverse translate. The Translation Stage A translation is done by the translator 22 of Figure 1, for every even pair of bits from the Y input, as shown in Table 2. It is possible to translate any pair of bits from the X input. The translation is based upon the following principle. Given a pair of bits Xi and Xil, if the high order bit (Xi+l) is a 1, it would automatically generate a carry-out and replace that bit by a -1. Thus that bit which appears in the "2's" position of that pair of bits will generate a carry-out of four and be replaced by a -2 (4-2 being equivalent to the 2 that was there in the first place). Therefore to determine the proper value for the pair of bits (Xi and Xi+l) we also need to look at bit Xi-l to see if that generated a carry-in. The carry-in from Xi-l has the same weight as Xi. Therefore, the translation of the three bits Xi-l, Xi and Xi+l is shown in Table 2, where a 1 in the column for Xi or Xi-1 corresponds to a 1 in the Xi position and a 1 in the column Xi+l corresponds to a -1 in that column or a -2 in the number. For example on the first row, the Xi+l is a 1, therefore we have a -2, Xi is a 1 and Xi-l is a 1, they add up to a +2 and the net result is Xi'=O. All the outputs then are between +2 and -2. The Multiplication Stage As shown in Table 3, since the multiplier expression coming into the multiply operation has now been translated so that it takes on values between +2 and -2, the multiply operation carried out by the multiplier 30 of Figure 1 consists of either a one-bit shift or no shift or zero and the sign change if the input is minus. So multiplying by Y equal to +2 constitutes shifting the input X values up one position. That is the Xi-l inputs take the place of the Xi inputs, as shown in Table 3. The Adder Stage As shown in Table 4a, the basic adder cell for the adder tree 36 of Figure 1 takes an input between -2 and +3. Although the multiplier provides inputs between -2 and +2, the adder outputs are between -2 and +3. Therefore in the adder tree, the adder inputs must be allowed to be between -2 and +3. The adder will accept two inputs between -2 and +3 and will receive a carry-in of -1, 0 or +1. It will generate a carry-out of -4, 0 or +4, independent of the carry-in (it is very important that it be independent of the carry-in) and an output between -2 and +3. This is carried out in the following way. Add the two inputs A and B, and if the resulting sum is between +3 and +6, generate a plus carry-out. if the resulting sum is between -1 and +2, generate a zero carry-out. If the resulting sum is between -4 and -2, generate a minus carry-out. Then the sum of A+B minus the carry-out that has been generated, represents a + 4 or a 0 and results in a number that is between -1 and +2. And adding the carry-in to that number results in a number between -2 and +3 and the carry-in does not affect the carry-out. When using the adder as shown in Table 4a it is necessary to translate both the X operand and the Y operand as shown in Table 2. However, it is possible to avoid the need for translating the operand X by using the basic adder cell as shown in Table 4b. In this case, the inputs to the adder can both be between -3 and i3 and the output generated by the adder is also between -3 and +3. In both cases the carry-out generated from the adder is independent of the carry-in. The Inverse Translation Stage As shown in Table 5, the inverse translation operation, which is carried out by the inverse translator 40 of Figure 1, receives an input from the last adder that is between -2 and +3. The multiplier expression at the start is assumed to have a positive value for the input. In the translate process, an adjustment is made to turn negative numbers to positive. At the output, the result is made negative when necessary, that is, when a positive number was multiplied by a positive number, the final output is made negative by reversing the signs of the output of the last adder which is the input to the inverse translator. This means that the inverse translator must be capable of operating on numbers between -3 and +3. The purpose of the inverse translator is to eliminate any negative values from this form of the number. The basic principle used is to replace a -1 in any bit column by a -1 in the next higher bit column and a +1 in that bit column. That is, use the fact that -1=-2+1. Thus, if the input to the inverse translator is between -3 and -1, it automatically generates a -1 carry-out. If the value of the input to the inverse translate is zero, the carry-out is equal to the carry-in, and if the value of the input to the inverse translator is positive, the negative carry-out is zero. The outputs for-the values coming into this particular inverse translator are given in Table 5 where the columns represent the output for various input states depending upon whether the minus carry-in is true or false, where the one's row represents true for the minus carry-in and the zero row represents false for the minus carry-in. Notice that where a minus carry-out was generated, +4 was added to the number. That completes the basic concept of the multiplier. Figure 1 illustrates a functional block diagram of the improved multiplier invention. The first operand X can be an eight bit, 16 bit, or a 24 bit binary number input on line 4 to the buffer 8. The second input Y is also a corresponding 8 bit, 16 bit, or 24 bit binary number input on line 5 to the buffer 6. The number of bits in the operand X is not necessarily the same as the number of bits in the operand Y. In addition, as long as the number of bits including sign in each operand is even, there is no limit as to their relative size. The output of each respective buffer, 6 and 8, is furnished on the respective lines 10 and 12. The output of the buffer 6 is input to the absolute value generator 15 which provides the absolute value of the operand Y to a first input of the translator 22. The output 12 of the buffer 8 passes through the multiplexer 14 and will either pass around the translator 22 via line 18 or will pass through the absolute value generator 17 to a second input to the translator 22. The operation of taking an absolute value produces an odd number of bits to be furnished to the translator. The translator 22 carries out the operations described in Table 2. The high order pair always must have a zero in the higher order bit position in order to avoid creating the need for a still higher order pair. First output 26 of the translator 22 is input to the multipliers 30, and the second output 24 of the translator 22 is passed to the multiplexer 20 and then over the line 28 to the second input of the multipliers 30. If the multiplexer 14 had been set so that the operand X passed over the line 18 directly to the multipliers 30, it would then pass through the multiplexer 20. Alternately, if the operand X had passed through the multiplexer 14 to the translator 22, then the output 24 from the translator 22 would have passed through the multiplexer 20 over the line 28 to the multipliers 30. The setting of the multiplexers 14 and 20 is dependent on the functions implemented in the adders 36. If the adders 36 are designed to implement the functions as described in Table 4a, then the multiplexers are set to pass the values of the operand X through the translator. On the other hand, if the adders 36 are designed to implement the functions described in Table 4b, then the multiplexers 14 and 20 are set to bypass the translator 22 and send the values of the operand X over the line 18. The multipliers 30 operate on the principle described in Table 3. When the input operand X has 2M binary bits and the operand Y has 2N binary bits, then a total of NxM partial products each consisting of a single signed digit are produced by the multipliers 30. These partial products are furnished on the lines 3211 through 32NM as is illustrated in Figure 1. The notation used in Table 3 is that I takes on values from 1 through 2M and J takes on values from 1 through 2N. The partial products provided on lines 32ill through 32NM are passed to the adders 36 which operate in accordance with the illustration in Table 4. All partial products where the sum of the two subscripts I and J are equal, are added together in the adders 36 as illustrated in Figure 2. For example, the partial product P62 available on line 3262 will be added to the partial product P44 available on line 3244r and the result of that sum will be added to the partial product P26 available on line 3226 The self-absorptive quality of the carry operations as described above in Table 4 enables the combining of sums in this manner to be done in parallel operating adders, simultaneously. This is schematically illustrated in Figures 2 and 3. The output of the adder is M+N signed digits which are passed through the sign adjuster 39 which restores the appropriate sign to the outputs of the adders 36 corresponding to the signs of the operands X and Y. The output of the sign adjuster 39 is passed over line 41 to the inverse translator 40 whose principle of operation is described in Table 5. The output from the inverse translator 40 on line 42 is the desired product of the operands X and Y, expressed in normal binary notation having 2(M+N)-l binary digits. Figure 2 shows a layout for a physical embodiment of the signed digit partial product generators, signed digit adders and inverse translator shown in Figure 1. A more detailed description of the connectivity of a portion of Figure 2 is shown in Figure 3 which shows the upper right-hand portion of Figure 2 in greater detail. In Figure 2, items 50 through 94 represent partial product generators, each of which has a single signed digit as an output. The inputs to the partial product generators 50 through 94 are the translated values of the operands X and Y shown in Figure 2 as coming from the top of the figure and the left-hand side of the figure. The outputs of the partial product generators 50 through 94 (which are labeled M in Figure 2) provide the inputs to the first set of basic adder cells 100 through 116 (which are labeled 1 in Figure 2), all of which will operate simultaneously. The first set of adder cells to operate simultaneously are the adders numbered 100 through 116. The partial product generators are arranged in two banks, 50 to 70 and 82 to 94. The first set of adders are arranged in two banks, 100 to 108 and 110 to 116. The outputs of partial product generators in the first bank are passed to the adders in the first bank and the outputs of the partial product generators in the second bank are passed to the adders in the second bank. Each of the first adders 100 to 116 receives two signed digits from the partial product generators 50 through 94 and produces a single signed digit output. The signed digit outputs from the adders 100 through 116 constitute the signed digit inputs to the second set of adders numbered 120 to 128 (which are labeled 2 in Figure 2). Thus, each of the adders 120 to 128 receives two signed digit inputs, one from an adder in the first bank 100 to 108 and one from an adder in the second bank 110 to 116, and produces a single signed digit output which goes to one of a third set of adders 140 to 146 (which are labeled 3 in Figure 2) which constitute the third level of adders operating sequentially. Thus, all of the first set of adders 100 to 116 operate in parallel followed by all of the second set of adders 120 to 128 which operate in parallel followed by all of the third set of adders 140 to 146 which operate in parallel to produce signed digit outputs which then go to the inverse translators 150 to 166 (which are labeled IT in Figure 2). In Figure 3, which shows the detailed interconnection of the elements shown in Figure 2, the small numbers in the circles indicate the number of wires which are intended to be used to carry the signed digit values from element to element in Figure 3. Operation of the Invention A sequence of illustrative examples follows for the invention. Example 1 Table 6 shows the example of multiplying the number 23 which will be the X operand, times the number 1 which will be the Y operand. The binary expression for 2 is 010111 and the binary expression for 41 is 00101001. The first step is to carry out the translation of the binary expression for 41 by means of the translate operation as illustrated in Table 2. The eight binary numbers are grouped into four pairs which are labeled from right to left as 2, 4, 6, and 8. The translation is carried out converting the binary expression for 41 into the sequence of numbers from left to right 1, -1, -2, 1, which is otherwise expressed in binary notation as ( (0-1) (-10) (01) With the translated form of Y expressed in this manner, the standard binary multiplication is carried out generating the array of four partial products shown in Table 6. The binary expression for the X operand is shown in line I, the binary expression for the translated form of operand Y is shown in line 2, and the signed binary expression for the four partial products are shown in lines 3 through 6 of Table 6. The multiplication is carried out in accordance with the operation described in Table 3. The partial products are organized in pairs and those pairs having the same sum of I and J are vertically aligned so as to enable their addition to take place as follows. The addition of the partial products is carried out with the first two partial products in rows 3 and 4 being added to form their sum in the row 7 and the addition of the partial products in rows 5 and 6 being added to form their sum in row 8. Then, the respective sums in rows 7 and 8 are added to form the combined sum in row 9. These additions are carried out in accordance with the principle described in Table 4. In the final step, the inverse translation as was described in Table 5 is carried out on the sum in row 9, resulting in the true binary expression of the product of the operand X and Y in row 10. As can be seen from reference to the example in Table 6, a substantial savings in the time necessary to carry out the multiplication is achieved by avoiding the necessity of rippling the carries in the addition of the partial products, this advantage accruing from the absorptive qualities of the carry in each respective pair of signed digits. Example 2 The operands X and Y are shown on lines 2 and 1 of Table 7. Those two operands would be input via lines 4 and 5 to buffers 8 and 6. Line 2 shows the operand X having decimal value 310 and the operand Y shown on line 1 having the value -493. Line 3 shows the translation of the absolute value of Y. The value of Y equal to -493 was passed through the absolute value circuit 15 to give the positive value corresponding to 493 also shown on line I and the translator 22 translated that value of Y according to the rules of Table 2 into the sequence of signed digits shown on line 3. Each of these signed digits takes on a value in the range -2 to +2 and provides one set of inputs to the signed digit multiplier 30. The operand X is sent to the signed digit multiplier bypassing translator 22 via line 18. The five lines 4 through 8 show the value of X being multiplied by each of the signed digits in the translated form of Y shown in line 3. This shows the binary representation of these partial products. The signed digit output of the same partial products is shown on lines 9 through 13. The only difference between lines 4 through 8 and lines 9 through 13 is the translation of the values to signed digit form as opposed to binary form. This is shown for the convenience of the reader. Each digit in rows 9 through 13 represents a partial product of signed digits from the operands X and Y. These partial products are aligned in columns corresponding to the digits which must be added together. It should be noted that because of the properties of the basic adder cell in which the carry-out is determined independently of the carry-in, that pairs of partial products may be added together simultaneously in order to speed up the operation of the multiplier. For example, in the middle column of the array shown in lines 9 through 13, there are five signed digits. Normal serial multipliers would require four consecutive additions in order to add those five digits using the basic adder cell described in Tables 4a or 4b. In particular, in this example, we will use the adder cell described in Table 4b. The first and second signed digits can be added together in parallel to the addition of the third and fourth digits in that column. Having done those two pairs of additions simultaneously, the two sums arrived at may be added together and that sum can then be added to the fifth and last digit in that column, thus require ing only the time of three additions rather than the time of four additions. It should further be noted that the time of three additions is sufficient to add up to eight digits in that column which in normal multipliers would require seven sequential additions to perform. This is the case that is normally found in 16x16 bit multipliers. The sums of lines 9 and 10 are shown on line 14. Notice that in the fourth column from the right, the digits 0 and -3 were added and the sum came out +1 with a carry of -1 being moved to the column immediately to the left, namely the fifth column from the right. It should further be noted that in the fourth column from the left, the input on line 10 took on the value -3 which would not have been allowed had the basic adder cell been built to conform to the rules of Table 4a rather than Table 4b. The sum of lines 11 and 12 is shown on line 15. Again, the fifth column from the right shows the addition of -3 and 0 to be +1 with a carry of -1 being moved to the sixth column from the right and producing the sum of -1 as the output in that column. The sum of lines 14 and 15 is shown on line 17. In this case, in the sixth column from the right, the values -1 and -1 add to produce -2. This is again a difference between the rules of Table 4b and the rules of Table 4a, where the sum of -1 and -1 in Table 4b does not produce a minus carry-out. Finally, the values on line 17 and line 18 are summed and the result is shown on line 19. Since the value of the operand Y was negative, and the value of the operand X was positive, we must do a sign adjust in order to correct the final output to reflect the minus value which is required. The values on line 19 appear at the output of the signed digit adders 36 and pass through the sign adjust 39 to produce the digits shown on line 21 which are passed via line 41 to the inverse translator. The inverse translator then produces the final binary output shown on line 22 which corresponds to the value -152830 in its two's complement form. This final product is then put out via line 42. Thus the invention enables one to use the array of signed digit adders using either the rules of Table 4a or the rules of Table 4b to obtain a number of sequential adds to produce the final multiply which grows only with the log to the base 2 of the length of the operands as opposed to a sequence of add operations which grows linearly with the length of the operands. Table 1 DESIGN SUMMARY Four Stages: (Using Plus and Minus Values) - Translate X and Y (No Ripple, Similar to Booth) - Multiply (Shift and Multiplex for Sign, no Ripple) - Adder Tree (No Ripple Carry) - Inverse Translate (Ripple Through Trans mission Gates) Table 2 TRANSLATE FOR X AND Y o For Positive Number (2's Complement) XI+1 XI XI-1 # XI' 1 1 1 0 1 1 0 -1 1 0 1 -1 1 0 0 -2 0 1 1 +2 0 1 0 +1 0 0 1 +1 0 0 0 0 Translate X for Ever I Translate Y for I Even o For Negative Numbers Use XI for XI and Use X15 for X-1 Table 3 MULTIPLY For yj'= +2; XI' # yj' = +X'I-1 yj' = -2; xI' # yj' = -x'I-1 yj' = +1; xI' # yj' = +xI' yj' = -1; xI' # yj' = -xI' yj' = 0; xi' # yj' = 0 For all I, j pairs with I and j even. Note that -2 # xI' # yj' # +2 for all I, j. Table 4a BASIC ADDER CELL INPUTS: -2 # A # +3 -2 # B # +3 Carry In = -1, 0, +1 OUTPUTS: Carry Out = -4, 0, +4 Independent of Carry In. -2 # C # +3 For +3 # A+B # +6, Carry Out = +4 +1 # A+B # +2, Carry Out= 0 -4 # A+B # -2, Carry Out = -4 Then A+B = (Carry Out) = -1, 0, +1, +2 and -2 # tA+B - (Carry Out)l + Carry In # +3 Table 4b BASIC ADDER CELL INPUTS -3 # A # +3 -3 # B # +3 Carry In = -1, 0, +1 OUTPUTS: Carry Out = -4, 0, +4 Independent of Carry In -3 # C # +3 For +3 # A+B # +6, Carry Out = +4 -2 # A+B # +2, Carry Out = 0 -6# A+B # -3, Carry Out = -4 Then A+B - (Carry Out) = -2, -1, 0, +1, +2 -3 c [A+B - (Carry Out) t (Carry In))# +3 Table 5 INVERSE TRANSLATE - INPUT: -2 # ZI' # +3 - For Negative Output, Change ZI' to -ZI' Thus, -3 # ZI' - +3 - To Eliminate Negative Values, Use -1 = -2 + 1 Thus -3 # ZI' # -1 # -1I OUT = 1 ZI' = 0 # -1I OUT = #1I IN +1 # ZI' # +3 # -1I OUT = 0 - ZI OUT is given by the Table EMI22.1 <SEP> ZI' <tb> <SEP> +3 <SEP> +3 <SEP> +1 <SEP> 0 <SEP> -1 <SEP> -2 <SEP> -3 <tb> -1I <SEP> IN <SEP> 1 <SEP> 2 <SEP> 1 <SEP> 0 <SEP> 3 <SEP> 2 <SEP> 1 <SEP> 0 <tb> <SEP> 0 <SEP> 3 <SEP> 2 <SEP> 1 <SEP> 0 <SEP> 3 <SEP> 2 <SEP> 1 <tb> Table 6 X = 23 - (0 1) (0 2) (1 1) Y = 41 = (0 0) (1 0) (1 0) (0 1) - (0 3) (0 -1) (-1 0) (0 1) ---------------------------------------------------------------------------------- -1 0 -1 -1 -1 0 1 1 0 -1 0 -1 -1 -1 0 1 0 1 1 1 ---------------------------------------------------------------------------------- 0 0 -1 0 -1 0 1 1 1 1 0 1 0 0 1 0 -1 -1 ---------------------------------------------------------------------------------- 0 1 0 0 0 -1 0 -1 0 -1 1 1 ---------------------------------------------------------------------------------- 0 1 1 1 0 1 0 1 1 1 1 Table 7 EMI24.1 Y <SEP> = <SEP> -493 <SEP> = <SEP> Abs. <SEP> Val <SEP> (1000010011) <SEP> = <SEP> (01) <SEP> (11) <SEP> (10) <SEP> (11) <SEP> (01) <tb> X <SEP> = <SEP> 310 <SEP> = <SEP> (01) <SEP> (00) <SEP> (11) <SEP> (01) <SEP> (10) <tb> T(Y) <SEP> = <SEP> 2 <SEP> 0 <SEP> -1 <SEP> -1 <SEP> 1 <tb> <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <tb> <SEP> 0 <SEP> -1 <SEP> 0 <SEP> 0 <SEP> -1 <SEP> -1 <SEP> 0 <SEP> -1 <SEP> -1 <SEP> 0 <tb> <SEP> 0 <SEP> -1 <SEP> 0 <SEP> 0 <SEP> -1 <SEP> -1 <SEP> 0 <SEP> -1 <SEP> -1 <SEP> 0 <tb> <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <tb> <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <tb> <SEP> 1 <SEP> 0 <SEP> 3 <SEP> 1 <SEP> 2 <tb> <SEP> -1 <SEP> 0 <SEP> -3 <SEP> -1 <SEP> -2 <tb> <SEP> -1 <SEP> 0 <SEP> -3 <SEP> -1 <SEP> -2 <tb> <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <tb> <SEP> 2 <SEP> 1 <SEP> 2 <SEP> 3 <SEP> 0 <tb> <SEP> -1 <SEP> 0 <SEP> +1 <SEP> 2 <SEP> -1 <SEP> +2 <tb> <SEP> 0 <SEP> -1 <SEP> -1 <SEP> +1 <SEP> -1 <SEP> -2 <tb> <SEP> 2 <SEP> 1 <SEP> 2 <SEP> 3 <SEP> 0 <tb> <SEP> 0 <SEP> -1 <SEP> -2 <SEP> +1 <SEP> 0 <SEP> 0 <SEP> -1 <SEP> +2 <tb> <SEP> 2 <SEP> 1 <SEP> 2 <SEP> 3 <SEP> 0 <tb> <SEP> 2 <SEP> +1 <SEP> +1 <SEP> +1 <SEP> +1 <SEP> 0 <SEP> 0 <SEP> -1 <SEP> +2 <tb> 0 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 0 <tb> <SEP> -2 <SEP> -1 <SEP> -1 <SEP> -1 <SEP> -1 <SEP> 0 <SEP> 0 <SEP> +1 <SEP> -2 <tb> -10 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 0 <tb>

Claims: CLAIMS 1. An improved multiplier for multiplying a first operand times a second operand, characterized by: a translator (22) having inputs connected to receive the first operand (Y), for translating the binary expression of said first operand into a sequence of signed digits; a partial product generator (30) having first inputs (26) connected to outputs of said translator and second inputs (28) connected to receive said second operand (X) either directly or via said translator (22), for multiplying said translated first operand times said second operand and furnishing partial products consisting of signed digits; an array of adders (36), each adder having its inputs connected to two of said signed digit outputs from said partial product generator, for providing a sum consisting of a sequence of signed quaternary digits; an inverse translator (40) having inputs connected to the outputs of said adders, for operating on said sequence of signed digits furnished by said adders, for providing a conventional binary expression for the product of said first and second operands. 2. An improved method for multiplying a first operand times a second operand, characterized by the following steps: translating the binary expression of said first operand (Y) into a sequence of signed digits, in a translator having an input connected to receive the first operand; multiplying said translated first operand times said second operand (X) in a partial product generator having a first input connected to the output of said translator and a second input connected to receive said second operand either directly or via said translator, and providing partial products consisting of signed digits; providing a sum consisting of a sequence of signed quaternary digits, in an array of adders, each adder having its inputs connected to two of said signed digit outputs from said partial product generator; and inversely translating said sequence of signed quaternary digits furnished by said adders to provide a conventional binary expression for the product of said first and second operands, in an inverse translator having an input connected to the output of said adders.

Inventors: FREY, ALEXANDER H.
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1984
Main classification: G06F7
IPC codes: G06F7