CONTROL SYSTEM FOR AC ELECTRIC CAR

Abstract: A control system for an AC electric car comprising a stored program processor which performs the motor current phase control and additional functions such as speed calcula­ tion, slip and skid detection and monitoring by an interruption based on a timing signal produced by a first timing signal gen­ erator (SYG₁) in synchronism with the power supply voltage or a second timing signal generator (SYG₂) independent of the first timing signal generator so that at least selected functions are carried out by an interruption based on the second timing signal produced by the second timing generator (SYG₂) which is arranged to produce the timing signal (SY₂) even when the power supply voltage is absent.

Description: CONTROL SYSTEM FOR AC ELECTRIC CAR The present invention relates to a control system for an AC electric car using a stored-program processor, e.g., a microprocessor. In the operation of an AC electric car which is powered by a.c. power supplied through the trolley wire, it is a general convention to step down the power voltage with a transformer, and supply the low-voltage power to a controlled rectifier, such as a thyristor bridge or thyristor-diode hybrid bridge, for controlling the d.c. voltage applied to the motors. The control system for the AC electric car is required to have not only the motor current control function in which the controlled rectifier is phase-controlled so that the actual motor current follows the command, but also additional functions including the detection and display of the car speed and the detection of slip and skid of wheels based on the output of a tachometer generator attached to the wheel axle and the processing for tandem control in which a plurality of electric cars are controlled in unison in accordance with the operational command. Furthermore, the recent demand for the enhanced reliability and easiness in maintenance of the electric car requires of the control system to have new functions such as monitor function which logs the operational states of the car and self-diagnostic function. When the aforementioned control system is constructed using a stored-program processor, e.g., a microprocessor, the arrangement is made in general such that individual processings take place in response to periodical interrupt signals provided externally to the processor. The control system needs to determine the phase angle of thyristors in the controlled rectifier at every half cycle of the power voltage and, therefore, the process related to the motor current control function is carried out in general in synchronism with the power voltage cycle, i.e., the interrupt signal for this purpose must be in synchronism with the power voltage cycle. The control program is arranged so that the processes for the other functions as mentioned above take place following the process for the motor current control, and this results in quick processing, satisfactory control characteristics and simplified software that brings enhanced reliability and easiness in maintenance of the control system. However, it is required in the electric railway system to provide a non-powered section at each switching point between two power supply sections associated with respective ground transformer stations, and the control system arranged as mentioned-above does not generate interrupt signals to the processor during a run in the non-powered section. As a result, no interrupt programs are initiated, and those functions which need processing even at the non-powered section will be lost. The absence of interrupt signals will also occur when the pantagraph separates from the trolley wire, or when an electric circuit fails to produce the interrupt signals based on the a.c. power voltage. An object of the present invention is to provide a control system for AC electric car which eliminates the prior art deficiencies and is capable of retaining the necessary functions even in the absence of the timing signals derived from the a.c. pwoer voltage supplied from the trolley wire. According to one aspect of this invention, the control system generates a first timing signal in synchronism with the a.c. power voltage supplied from the trolley wire for performing at least the phase control process for the aforementioned controlled rectifier by the interrupt program and a second timing signal which is used for performing processes other than the phase control process by the interrupt program even if the first timing signal is absent. According to another aspect of the invention, an interrupt signal for initiating the phase control for the controlled rectifier is produced in response to the first timing signal in synchronism with the power voltage, and another interrupt signal based on the second timing signal is produced to carry out processes other than the phase control process. In consequence, the phase control takes place in the presence of the power voltage from the trolley wire, while the other processes needed uninterruptedly are carried out even in the absence of the power voltage from the trolley wire. In this case, if the two timing signals have the same frequency, related processes necessary for the phase control, e.g., computation for producing a current command, may be executed by the interrupt program initiated by the second timing signal with the same frequency as obtained if the related processes are carried out based on the first timing signal. As compared with the phase control, other control processes often suffice to take place less frequently, and in these cases the second timing signal may be set to have a frequency 1/2, 1/3 or so on of the frequency of the first timing signal. If, for example, a 1/2 frequency is selected for the second timing signal, phase angles in the positive and negative halves of each a.c. voltage cycle are calculated based on single data derived from the current control processing. According to still another aspect of the invention, all processes are carried out by the interrupt program in response to the first timing signal so long as it is obtained, and all processes are carried out in response to the second timing signal only if the first timing signal is not obtained, although it is selfevident that the phase control has no meaning if the absence of the first timing signal is caused by failure of the power voltage. The present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram showing the main circuit and control circuit for the AC electric car embodying the present invention; Fig. 2 is a flowchart showing an embodiment of the interrupt program stored in the read-only memory (ROM) within the microprocessor (MPU) shown in Fig. 1; Fig. 3 is a flowchart showing another embodiment of the program; Fig. 4 is a block diagram showing the main circuit and control circuit for the AC electric car according to another embodiment of the invention; Fig. 5 is a flowchart showing an embodiment of the interrupt program stored in the ROM within the microprocessor (MPU) shown in Fig. 4; ; Fig. 6 is a block diagram showing another embodiment of the timing signal generating circuits SYG1 and SYG2 and the timing signal switching circuit SYE shown in Fig. 4; and Fig. 7 is a timing chart showing the operation of the circuit arrangement shown in Fig. 6. In Fig. 1, there are shown schematically electrical main and control devices mounted to an electric car which may be a particular one of train cars (not shown). In the figure, the a.c. voltage received from a trolley wire TW through a pantagraph P is supplied to a transformer MT so that the voltage is stepped down, and the step-down voltage is supplied to a controlled rectifier RF composed of diodes D1 and D2 and thyristors T1 and T2. The controlled rectifier RF is phase-controlled by a controller CE, and a d.c. output voltage is applied to a motor M, in which a motor current IA flows in proportion to the difference between the d.c. output voltage and the counter electromotive force of the motor M. The controller CE includes a microprocessor MPU, interrupt control circuit IRC, analog signal input circuit AIC, speed signal input circuit VIC, gate signal output circuit GSO, tandem signal output circuit STC, analog signal output circuit AOC, and memory circuit MEM, all linked up with each other through the bus lines. The a.c. voltage received by the pantagraph P is also stepped down by an auxiliary transformer PT, and this voltage is supplied to a first timing signal generating circuit SYG1, which provides a rectangular first timing signal SY1 in synchronism with the a.c. power voltage to the interrupt control circuit IRC. A second timing signal generating circuit SYG2 generates a second timing signal SY2 having a frequency equal to that of the first timing signal SY1 divided by an integer, and supplies it to the interrupt control circuit IRC. The second timing signal generating circuit SYG2 includes a quartz oscillator CG for producing clock pulses at a given frequency and a frequency divider CT for dividing the clock pulses so as to produce clock pulses of desired frequency which are used as the second timing signal SY2. The analog signal input circuit AIC is supplied with a reference signal PA generated by a main control MC and a feedback signal FA produced by a d.c. current transformer DCCT in proportion to the motor current IA. The rotational speed of the motor M is detected by a pulse generator PG, which provides pulses at a rate corresponding to the motor speed to the speed signal input circuit VIC. The gate signal output circuit GSO produces gate signals GS1 and GS2 for the thyristors T1 and T2, respectively, while the tandem signal output circuit STC produces a tandem control signal STS for controlling other electric cars connected in tandem with the particular car in accordance with the command of the main control MC. The analog signal output circuit AOC produces a d.c. output voltage in response to the command of the microprocessor MPU so that the car speed is indicated on a speed meter SM. The microprocessor MPU includes a microprocessing unit, a read-only memory (ROM) storing the interrupt program and a clock pulse generator for producing clock pulses determining the timing in operation of the microprocessing unit, although they are not shown in the figure. Fig. 2 shows a flowchart of the interrupt program stored in the ROM, and the program is processed as follows. When the first timing signal generating circuit SYG1 or the second timing signal generating circuit SYG2 provides an output to the interrupt control circuit IRC, causing the microprocessor MPU, to interrupt the currently executed program and transfer its operation to the first step S0 of the program shown in Fig. 2. For example, when the first timing signal SY1 is given to the interrupt control circuit IRC, it is detected in step S1, and the program proceeds to step S3 in which the current control process is carried out for calculating data required for motor current control and step S4 in which the GSO control process is carried out for calculating data required for controlling the gate signal (GSO) output. Then, steps S5 through S9 are carried out for the respective processes as illustrated, and in step S10 the interrupt program ends and the operation returns to the original program. More particularly, in the process of motor current control in step S3, the reference signal PA and feedback signal FA derived from the analog input circuit AIC are compared with each other and the phase angles of the gate signals GS1 and GS2 are determined depending on the difference of the two signals. In step S4, the process for controlling the gate signal output circuit GSO takes place so that the gate signals GS1 and GS2 are produced according to the phase angles obtained by the process for the current control in step S3. In step SS, the frequency of pulses provided by the pulse generator PG and entered through the speed signal input circuit VIC is converted to a value proportional to the car speed by additionally using parameters such as the wheel diameter, and it is given through the analog signal output circuit AOC to the speed meter SM. In step S6, the slip and skip of wheels are detected using the result of the step S5, and in step S7, the tandem control signal STS is produced from the result of the process in step S5 so as to control the tandem signal output circuit STC. Step S8 checks the integrity of the results obtained in steps S3 through S7, and if abnormality is found, control is transferred to a corresponding process for halting the vehicle or inhibiting the change of phase angle in the gate signal output circuit GSO. In step S9, the results of processes in steps S3 through S8 are stored in the memory circuit MEM for the purpose of logging the operational states of the vehicle. The above processes are carried out in wellknown manner and no detailed explanation will be necessary. On the other hand, when the second timing signal SY2 is given to the interrupt control circuit IRC, it is detected in step S2, and the program branches to step Sll for checking whether or not an interrupt by the preceding first timing signal SY1 has normally occurred. Since the first timing signal SY1 is generated at a constant frequency in synchronism with the power voltage, the above check can be readily carried out by checking whether the first timing signal SY1 has occurred within a predetermined time interval corresponding to the constant frequency after the preceding first timing signal. If not occurred, it is determined that the first timing signal has expired. If the timing signal SY1 is found as normally occurred, the interrupt process based on the timing signal SY2 is unnecessary and the operation is returned to the original program in step S10. If the timing signal SY1 is found as expired, the program branches to step S5 and executes the processes in steps S5 through S9. Accordingly, when the car runs through a non-powered section of the trolley wire, the second timing signal generating circuit SYG2 generates the second timing signal SY2 to the interrupt control circuit IRC, so that processes necessary even in the non-powered section (e.g., steps 54 through S8 in Fig. 2) are carried out. Fig. 3 shows a flowchart of another interrupt program which may be used in place of the program shown in Fig. 2. First, when the second timing signal SY2 is given to the interrupt control circuit IRC, it is detected in step S12, and the program branches to step S3 in which the process for the motor current control takes place. Then, the processes in steps S5 through S9 are carried out, and then the operation returns to the original program at step S10. In the process for the motor current control in step S3, the reference signal PA and feedback signal FA received through the analog input circuit AIC are compared with each other, and the phase angles of the gate signals GS1 and GS2 are determined depending on the difference between the two signals. In this program, however, the process for the gate signal output GSO circuit does not take place, and the results of the above processes are stored in the memory MEM. The processes in steps S5 through S9 are the same as those of the program shown in Fig. 2. On the other hand, when the first timing signal SY1 is given to the interrupt control circuit IRC, it is detected in step S13, and the program branches to step S4 for the process of the gate signal output GSO circuit so that the gate signal output GSO circuit is controlled to produce the gate signals GS1 and GS2 according to the phase angles obtained by the process for the current control in step S3. Accordingly, when the car runs through the nonpowered section of the trolley wire, the second timing signal generating circuit SYG2 provides the second timing signal SY2 to the interrupt control circuit IRC, and processes necessary even in the non-powered section (e.g., steps S4 through S8 in Fig. 3) are carried out. Since the control of the gate signal output GSO circuit is carried out in response to the second timing signal SY1 the gate signals GS1 and GS2 for the thyristors T1 and T2 are in synchronism with the power voltage supplied from the trolley wire TW, and the desired control performance is accomplished. Since the second timing signal has a frequency equal to that of the first timing signal divided by an integer, the process necessary for the phase control initiated by the first timing signal (e.g., step S3 for the current control) is always carried out based on the latest data. If, as compared with the process for phase control, the other processes may be carried out less frequently, the above-mentioned integer may be selected to be 2 or larger so that the duty of the processor is reduced while satisfying the desired functions and performance of the system. Although it is not shown in the flowchart, some of the processes other than the phase control process which do not need to be executed in the non-powered section may be executed before or after the phase control process in step S4 in response to the first timing signal SY1. Figs. 4 and 5 show another embodiment of the present invention. In Fig. 4, the same reference symbols are used for the same or like components as those in Fig. 1. The arrangement of Fig. 4 is identical to that of Fig. 1, except that the first and second timing signals SY1 and SY2 are supplied to a timing signal switching circuit SYE made up of a relay RY or the like, which provides a third timing signal SY3 to the interrupt control circuit IRC. In this arrangement, when the car receives an a.c. power from the trolley wire TW, the auxiliary transformer PT provides an output, and the timing signal switching circuit SYE provides the third timing signal SY3 corresponding to the first timing signal SY1, so that the microprocessor MPU is subjected to an interruption by the interrupt control circuit IRC in synchronism with the a.c. power voltage received from the trolley wire TW. Fig. 5 shows a flowchart of the interrupt program for the AC electric car control system. At the occurrence of interrupt, the microprocessor MPU suspends the currently executing program, and its operation is transferred to step S0. The interrupt by the signal SY3 is detected in step S14, and the processes in steps S3 through S9, which are identical to those of Fig. 2, are carried out. As a result, the gate signal output circuit GSO is controlled in synchronism with the a.c. power voltage received from the trolley wire TW. On the other hand, when the car runs through the non-powered section, the auxiliary transformer PT provides no output, and the timing signal switching circuit SYE provides the third timing signal SY3 based on the second timing signal SY2, causing the microprocessor to interrupt its normal program through the interrupt control circuit IRC, and proceed to the same processes as described above. Accordingly, even when the car runs through the nonpowered section, all of the processes S3 through S9 are carried out to perform the tandem control function, monitor function, and car speed detection and indication. In this embodiment, only the timing signal SY3 is used for interruption, and the simplifies the interrupt control circuit as well as the program resulting in minimizing the processing time. Fig. 6 shows still another embodiment of the present invention, illustrating only those portions corresponding to the timing signal switching circuit SYE, first timing signal generating circuit SYG1 and second timing signal generating circuit SYG2 of Fig. 4. Fig. 7 shows a timing chart of the signals produced in the arrangement of Fig. 6. The auxiliary transformer PT provides its output to the first timing signal generating circuit SYG1, which converts the output into a rectangular first timing signal SY1 in synchronism therewith, as shown in Fig. 7, and supplies the timing signal SY1 to an OR gate and also to a one-shot trigger circuit OS. As shown in Fig. 7, the one-shot trigger circuit OS provides a pulse at each transition of the first timing signal SY1, and it is supplied to the reset terminal RES of a counter circuit CT. On the other hand, an oscillation circuit CG provides output pulses of a frequency larger than that of the first timing signal SY1 as shown in Fig. 7, and the output pulses are supplied to the clock terminal CK of the counter circuit CT, which is arranged to count down the received pulses and provide a signal at its output terminal OUT at a frequency equal to the output frequency of the auxiliary transformer PT. In operation, when the car receives the a.c. power voltage, the auxiliary transformer PT provides the output to the circuit SYG1, which in turn produces the first timing signal SY1 so that the one-shot trigger circuit OS provides a pulse at each transition of the SY1, causing the counter circuit CT to reset. Therefore, the counter circuit CT does not provide the output, but the first timing signal SY1 is fed through the OR gate as the third timing signal SY3. On the other hand, when the car is running through the non-powered section, the auxiliary transformer PT and hence the one-shot trigger circuit S0 provide no output. Accordingly, the counter circuit CT is not reset, but it counts down the output of the oscillation circuit CG to produce at its output terminal OUT the signal at a frequency equal to that of the first timing signal SY1. This signal is fed through the OR gate as the third timing signal SY3. This embodiment eliminates any delay in the switching operation between the first timing signal SY1 and the second timing signal. According to the present invention, as described above, all of the desired functions can be accomplished even if the car is running through the non-powered section.

Claims: CLAIMS: 1. A control system for an AC electric car having a transformer (MT) receiving on its primary winding an alternating current from a trolley wire through a pantagraph, a controlled rectifier (RF) having its input terminal connected to the secondary winding of said transformer and operating to convert the alternating current into a direct current, and a DC motor (M) connected to the output terminal of said controlled rectifier for driving the car, said system comprising: means (SYG1) for generating a first timing signal in synchronism with the received alternating current; and a processing unit (MPU) of a stored program type for carrying out phase control for said controlled rectifier by an interruption based on said first timing signal; characterized by means (SYG2) including oscillator means (OS) and frequency division means (CT) for generating a second timing signal; and that said processing unit is arranged to perform processes other than said phase control by an interruption based on said first or second timing signal during a first operating mode in which said transformer receives the alternating current, and perform processes other than said phase control by an interruption based on said second timing signal during a second operating mode in which said transformer does not receive the alternating current. 2. A control system according to claim 1, characterized by that said processes other than said phase control include at least one of speed detection and display process, wheel slip and skid detection process, tandem control process, self-diagnostic process, and monitoring process. 3. A control system according to claim 1, characterized by that said processing unit performs the processes other than said phase control by an interruption based on said first timing signal during said first operating mode. 4. A control system according to claim 1, characterized by that said processing unit performs the processes other than said phase control by an interruption based on said second timing signal during said first operating mode. 5. A control system according to claim 1, characterized by that said processing unit performs the processes including said phase control by an interruption based on said first timing signal so long as said first timing signal is present, and performs the processes by an interruption based on said second timing signal when said first timing signal disappears. 6. A control system according to claim 5, characterized by timing signal switching means (SYE) having an input section for receiving any of said first and second timing signals and adapted to produce said first timing signal, as an output, so long as said first timing signal is received and produce said second timing signal as an output when said first timing signal is not received, and that, said processing unit is arranged to perform said processes by an interruption based on the output of said switching means. 7. A control system according to claim 1, characterized by that said processing unit is provided with an input section for receiving said first and second timing signals and adapted to perform processes including said phase control by an interruption based on said first timing signal and perform at least processes other than said phase control by an interruption based on said second timing signal upon disappearance of said first timing signal. 8. A control system according to claim 1, characterized by that said processing unit performs, in said first operating mode, phase angle determinating process and phase angle memorizing process by an interruption based on said second timing signal and retrieving process for the memorized phase angle and gate signal output process for said controlled rectifier by an interruption based on said first timing signal. 9. A control system according to any one of claims 1 through 8, characterized by that said second timing signal has a frequency equal to the frequency of said first timing signal divided by an integer. 10. A control system according to any one of claims 1 through 9, characterized by means for synchronizing said second timing signal with said first timing signal.

Inventors: KIMURA, AKIRA, SAKAMOTO, HIDEO, TSUTSUI, YOSHIO, YAMADA, KAZUHIRO
Applicants: HITACHI, LTD.
Application year: 1984
Main classification: H02P5
IPC codes: B60L9, H02P7, H02P23