DECODING METHOD AND SYSTEM FOR DOUBLY-ENCODED REED-SOLOMON CODES

Abstract: Disclosed is an error correction in reproducing a digital signal of a digital audio system or a PCM reproducing system. Code words such as doubly-encoded Reed-Solomon code comprise first code blocks including a plurality of information words arranged in a first arrangement and a plurality of first check words generated by a code having a Hamming distance of d₁ to said information words, and second code blocks including a plurality of information words arranged in a second arrangement and a plurality of first check words each having a plurality of information words and a plurality of first check words belonging to different one of said first blocks, and a plurality of second check words generated by a code having a Hamming distance of d₂ to said plurality of information words and said plurality of first check words, are decoded to correct errors. For such a doubly-encoded error correction code, at least error detection is effected in a first decoding and flags indicating decoding conditions are added. In a second decoding, error detection for the first code blocks and error correction for S₂ words at unknown locations and E flagged word erasure, where S₂ and E satisfy a relation of 2S₂ + E ≦ d₁ - 1, are parallelly or sequestially are effected, and a combination of S₂ and E having a high correction capability and a low probability of mis-correction is selected from a plurality of correction results of error locations and the number of flags added at the first decoding, and the word errors are corrected based on the selected combination.

Description: CROSS REFERENCES OF THE RELATED APPLICATIONS This application relates to the U.S. Serial No. 622,711 filed on June 22, 1984, entitled "Error Correction Method and System" by Hiroo Okamoto, Masaharu Kobayashi, Kenzo Nishimura, Takaharu Noguchi, Takao Arai and Toshifumi Shibuya, based on Japanese Patent Application No. 110931/83 filed June 22, 1983, No. 130839/83 filed July 20, 1983 and No. 210858/83 filed November 11, 1983. The present invention relates to an error correction in a digital signal reproduction, and more particularly to error correction method and system suitable to decoding of an error correction code such as a doubly-encoded Reed-Solomon code. The European patent application EP-A-0 072 640 relates to a method of error correction in which a first error correcting block consisting of one word contained in each of pulse code modulated data sequences in a plurality of channels in a first arrangement state and first check words associated therewith is formed, and in which a second error correcting block consisting of one word contained in each of the PCM data sequences in the plurality of channels and the first check word sequences and second check words associated therewith is formed. The method consists of two decoding stages in which the first stage decoding includes the steps of correcting at least one word error contained in the second error correcting block, and detecting errors of more than two words,and adding pointers of two kinds which can distinguish the correction of one word error from the detection of the errors of more than two words to each of the detected words, while the second decoding stage includes the steps of correcting errors of words contained in the first error correcting block, and discriminating the number and arrangement state of the pointers of two kinds contained in the first error correcting block during the error correcting process, so that on the basis of results of discrimination, the error detection is prevented from being missed and the erroneous correction is avoided. In many cases of transmitting digital signals, a check word is added in a transmitting station and an error in a data is detected and corrected in a receiving station of using the check word in order to correct the data error generated in a transmission system. The Reed-Solomon dode which is efficient and easy for decoding and which is one of BCH codes is, in many cases, used as the check word. The doubly-encoded Reed-Solomon code has a high error correction capability and is used in a PCM recorder and a digital audio disc (DAD). The US patent US-A-4 162 480 relates to a system for correcting errors in cyclic code streams of data elements, wherein the Reed-Solomon code is applied. The system consists of an arithmetic unit for performing arithmetic and logical operations upon portions of said data streams to decode said portions, the arithmetic unit comprising data memory means and Galois field logic means, the data memory means being adapted to retain data elements as well as the results of the Galois field logic means operation. The system further comprises an address generator for developing address information for transmittal to said arithmetic unit to address the data memory of the arithmetic unit. The system further comprises a control unit comprising a control memory means for storing the instructions defining the sequence of operations required for effecting corrections in said data streams. Fig. 1 is one example of the doubly-encoded Reed-Solomon code. Numeral 1 denotes information words, numeral 2 denotes first check words and numeral 3 denotes second check words. In encoding, the first check words Q₀, Q₁, Q₂ and Q₃ are added to the twelve information words W₀ - W₁₁. The block consisting of the twelve information words and the four first check words is called a C₂ block 5. Words of the C₂ block 5 are interleaved into an arrangement shown in Fig. 1. The second check words P₀ and P₁ are added to the twelve information words W₀ - W₁₁ and the first check words Q₀, Q₁, Q₂ and Q₃ in each C₂ block 5. The block consiting of the twelve information words, the four first check words and the two second check words is called a C₁ block. In decoding, an error detection and an error correction are made for the C₁ block, it is deinterleaved, an error detection and an error correction are made for the C₂ block, and a decoded signal is outputted. In the doubly-encoded system, a correction capability is enhanced by decoding two or more times for the two different code blocks (C₁ and C₂). Such an error correction system is disclosed in the U.S. Patent US-A-4,437,l85 to Sako issued on March 13, 1984 (British Patent GB-A-2079993). In such a decoding system, however, only one or two words are corrected and the error detection and correction capability inherent to the code is not fully utilized. Since an error detection flag is not fully utilized in the second decoding, the capability of the code is reduced. It is an object of the present invention to provide error correction method and system which can fully utilize the error detection and correction capability inherent to the doubly-encoded error correction code. In accordance with one aspect of the present invention, there are provided error correction method and system in which the number of errors is detected in a second decoding of a doubly-encoded error correction code, and erasure and error correction is effected only when a probability of miscorrection is low based on the result of the detection. In accordance with another aspect of the present invention, there are provided error correction method and apparatus in which an error is corrected in the second decoding of the doubly-encoded error correction code when a probability of error is high and errors are small, errors having small probability of error are sequentially detected, the number of corrections for erasure are increased based on the result of the detection and status of flag representing the result of first decoding so that both error detection capability and error correction capability are enhanced. In accordance with a further aspect of the present invention, there are provided error correction method and system in which the error correction code such as doubly-encoded Reed-Solomon code is used to reproduce a digital signal of a digital audio system, a flag representing a status of the first decoding is added, the signal is decoded more than one time in the second decoding by using the flag to determine an error word location and an error pattern and a result which meets a desired requirement is selected to correct the error in the word. The present invention is outlined below. The first decoding is effected to the doubly-encoded error correction code and the flag representing the decoding status is added. In the second decoding, the decoding is effected more than one times of using the flag and an optimum decoding method is determined based on the decode result and the error correction is made by using the decode result by the optimum decoding method. Thus, the error correction capability and the error detection capability are enhanced. The selection criterion for the second decoding method is determined by a compromise or a requirement for the correction capability and the detection capability determined by the probability of occurrence of the flag added in the first decoding, the probability of failure of error detection, the probability of incapability of correction of codes in the second decoding and the probability of incapability of detection. In the accompanying drawings: Fig. 1 shows a data arrangement of a doubly-encoded error correction code, Fig. 2 is a flow chart of a C₁ decoding; Fig. 3 is a flow chart of one example of the C₂ decoding, Figs. 4 and 5 show error patterns for the C₂ block having four flags, Fig. 6 is a flow chart of the C₂ decoding of the present invention, Figs. 7 and 8 show miscorrectable and incorrectable error patterns for the C₂ block, Fig. 9 shows a detail of Fig. 6, Fig. 10 is a flow chart for another embodiment of the present invention, Fig. 11 is a block diagram of one embodiment of a system for implementing the method of Fig. 10, Fig. 12 shows another example of the doubly-encoded error correction code, Fig. 13 is a flow chart of the C₂ decoding when the present invention is applied to the code of Fig. 12, Fig. 14 is a block diagram of one embodiment of an error correction circuit of the present invention, Fig. 15 is a flow chart for an embodiment of the present invention applied to DAD, Fig. 16 is a flow chart showing a detail of Fig. 15, and Fig. 17 shows comparative characteristic curves of error detection capabilities and error correction capabilities of the embodiment of Figs. 15 and 16, a prior art system and a comparative system. Before the embodiments of the present invention are explained, the invention of the related application U.S. Serial No. 622,711 is briefly explained for a purpose of easy understanding of the present invention. The related invention was not published before the present invention and is not cited as a prior art. The disclosure is incorporated by reference in the present application. In the related European Patent Application EP-A-0 129 849, the decoding method of Fig. 1 uses the Reed-Solomon code in which the C₁ block has a code length of 18, the number of check words of 2 and a Hamming distance of 3 and the C₂ block has a code length of 16, the number of words of 4 and a Hamming distance of 5. Accordingly, in the C₁ decoding, one error word can be corrected and in the C₂ decoding, S errors whose error locations are unknown and E errors whose error locations are known (hereinafter the former is called errors and the latter is called erasures) can be corrected, where 2S + E ≦αµρ¨ 4. Thus, in the C₁ decoding, the error detection and the one-word correction are effected and flags representing the decode conditions are added to the respective words, and in the C₂ decoding, one of the following three decodings is effected depending on the status of the flag added to each word so that the error correction of high capability is effected. (1) S=2 E=0 : up to two errors are corrected. (2) S=1 E=2 : one error and two erasures are corrected. (3) S=0 E=4 : Four erasures are corrected. Fig. 2 is a flow chart for the C₁ decoding. N(E) is the number of errors detected in the C₁ decoding when the number of error is one, one-word correction is effected. F₀ flag and F₁ flag are used as the flags to represent the decode status in the C₁ decoding. The F₀ flag is set to "1" when the error is detected, and the F₁ flag is set to "1" when more than two words are in error and they cannot be corrected. Fig. 3 is a flow chart for the C₂ decoding. N(F₀) and N(F₁) are the numbers of the F₀ flags and the F₁ flags, respectively In the C₂ decoding, the error status is guessed in accordance with the number of flags in the block to determine and select the optimum decoding method. For example, when N(F₀) = 4, that is, when the number of F₀ flags (including those having the F₁ flags added thereto) is four, the locations to which the flags are added are assumed as error locations (errors with known error locations) and the erasure correction of the formula (3) is effected. Fig. 4 shows an example in which three errors are included in one C₂ block. Numeral 4 denotes the C₁ block, numeral 5 denotes the C₂ block, numeral 8 denotes a flagged error word and numeral 9 denotes a flagged word which is actually correct. It indicates that there is an error in the C₁ block to which the word 9 belongs. In the C₁ decoding, if an error is detected, flags are added to all words (symbols) in the block. If only one word is in error, it is corrected by the C₁ decoding. When two or more words are in error, there are correct words and error words. Thus, there are flagged error words and flagged correct words. In the erasure correction of the formula (3), up to four flagged error words can be corrected. However, since it has no error location detection capability, it may miscorrect if a non-flagged error is included as shown by a word X in a block 5 in Fig. 5, because the word at the location X is not recognized as an error word but the erasure correction is effected therefor. Referring to an example shown in Fig. 5, numeral 10 denotes a non-flagged error. The non-flagged error is due to the failure of detection in the C₁ decoding. Accordingly, a problem may arise when the number of check words for C₁ is small such as P₀ and P₁ shown in Fig. 1 and hence a sufficient error detection capability is not provided. In Fig. 1, since the number of check words is two (P₀ and P₁), the failure of detection may occur if three or more errors are included. In order to prevent the miscorrection due to the failure of detection, the error correction (3) is effected when N(F₀) = 4. In this case, non-flagged error due to the failure of detection can be detected, and no more than one flagged error can be corrected. However, when the error correction (1) (S ≦αµρ¨ 2, E=0) is effected after the C₁ decoding, the errors cannot be corrected if three or more errors are included as shown in Fig. 4. The present invention provides a resolution to improve a limit to such a correction capability. One embodiment of the present invention is now explained with reference to the error correction code shown in Fig. 1. As described above, in the decoding of the error correction code of Fig. 1, one-word error can be corrected in the C₁ decoding, and two-word error correction, one-word error correction and two-word erasure correction, or four-word erasure correction can be effected in the C₂ decoding. In the C₁ decoding, the error detection and the one-word error correction are effected in the same manner as shown in Fig. 2, and if the error is detected, the F₀ flags are added, and if the errors are incorrectable, the F₁ flags are added to the respective words. Referring to Figs. 6 and 9 which show flow charts for the C₂ decoding, the procedure of the C₂ decoding is explained. Fig: 9 shows a detail of the error correction method of the present invention shown in Fig. 6. L(F₀) and L(F₁) are number of coincidences of error locations detected by the C₂ decoding and the F₀-flagged or F₁-flagged locations. F is an incorrectable flag to be added to an incorrectable word. When F=1, all words in the C₂ block are flagged, and when F=F₀, only the F₀-flagged words are flagged. For the F-flagged words, error concealment is effected during reproduction by an average interpolation. (1) First, the decoding is effected with S=2, E=0. Up to two-word errors at any location can be detected. If the number of errors is no more than two, a probability of miscorrection is determined based on the flags added to the error locations and the number of flags in the block, and if the probability is low, the correction is effected. If the probability of miscorrection is high, the errors are incorrectable. For example, when the number of error detected is one (N(E) = 1), it is checked if the F₁ flag has been added to the error location detected. If it has been added (L(F₁) = 1), the decoded result is correct and the error correction is effected. If the F₁ flag has not been added (L(F₁) = 0), the number of F₁ flags is checked. If the number of F₁ flags is no more than three (N(F₁) ≦αµρ¨ 3), the decoded result is correct and the error correction is effected. If the number of F₁ flags is larger than three (N(F₁) > 3), the probability of miscorrection is high and the correction is not effected. The thresholds of the numbers of the flags for checking if the decoded result is correct or not are determined by previously calculating probabilities of miscorrections for various values of L(F₁) and N(F₁). A method for calculating the probabilities is disclosed in "Decoding Method for Double-Encoding System" by Hideki Imai and Yasuji Nagasaka, Journal of Association of Electronics and Electrical Communication of Japan, vol. J 65-A, No. 12, pages 1254-1261, December 1982 and "Decoding Properties of Superstrategy for Crossinterleave Reed-Solomon Codes" by Yashiro et al, the same journal Vol. J 66-A, No. 3, pages 284-285, March 1983. In the Reed-Solomon code having a Hamming distance of 5, the probability of miscorrection is high when e + N(E) ≧ 5, where e is the number of actual errors. When N(E) = 1 and one-word error is corrected, the miscorrection occurs if four or more errors are included in the block. When N(F₁) > 3, a probability that four or more errors are included is higher, and the miscorrection may be effected as shown in Fig. 7. In Fig. 7, numeral 90 denotes a case where a correct symbol or word was determined as an error by the miscorrection. (2) If three or more errors are detected in (1), and if the member of F₀ flag is three, two of the three words to which the F₀ flags were added are erased and the decoding with S=1 and E=2 is effected. If errors are detected only in the flagged words, the correction is made by using the decode result. (3) If three or more errors are detected in (1) and if the number of F₀ flags is four, the four flagged words are erased and the decoding with S=0 and E=4 is effected and the four-word correction is made. (4) If three or more errors are detected in (1) and the number of F₀ flags is five or more and the number of F₁ flags is three, two of the three words to which the F₁ flags were added are erased and the decoding with S=1 and E=2 is effected. If the errors are detected only in the F₁-flagged words, the correction is made by using the decode result. (5) If three or more errors are detected in (1) and the correction conditions (2) - (4) are not met, the errors are incorrectable. By decoding twice with different decoding method, errors which are incorrectable or miscorrected by one decoding can be corrected. For example, the example of Fig. 4 is correctable by (3) and the example of Fig. 5 is correctable by (1). The errors are incorrectable by (1) - (5) only when N(F₀)=0, two or more flagged errors are included and a non-flagged error is included, as shown in Fig. 8. Even in such a case, up to three errors may be corrected by increasing the number of times of decoding and effecting the decoding with S=1 and E=2 while changing the location of erasure. While the decoding is effected twice in (1) - (5), two different decodings may be simultaneously effected, the optimum decoding method is determined after the decoding and the error correction may be effected by using the decode result by the optimum decoding method. As shown in Fig. 9, the decode result may be checked by the F₀ flags and the F₁ flags added in the C₁ decoding so that the probability of miscorrection is lowered and the error correction with enhanced error detection and correction capability can be effected. Fig. 10 shows a flow chart for simultaneously effecting two different C₂ decodings. In "Decode 1", the decoding (1) with S=2 and E=0 is effected, and if the number of errors detected is no more than two, the correction is made by using the decode result, and if the number is more than two, no correction is made. In this case, CS is set to "1". In "Decode 2", the decoding (2) with S=1 and E=2 or the decoding (3) with S=0 and E=4 is effected, and if CS=1, the correction is made by using the decode result. In the method of Fig. 10, two decoders for simultaneously effecting two different decoding circuits are necessary but the decoding time can be shortened. Fig. 11 shows an embodiment of an error correction system for correcting errors in accordance with the method of Fig. 10. Numerals 100 and 101 denote error correction circuits shown in detail in Fig. 14. The circuit 100 effects the decoding of "Decode 1" and the circuit 101 effects the decoding of "Decode 2". Numeral 102 denotes an input/output control circuit, numeral 103 denotes a register, numeral 104 denotes an input buffer, numeral 105 denotes an output buffer, numeral 106 denotes an AND circuit and numeral 107 denotes an inverter. A received signal is simultaneously applied to the error correction circuits 100 and 101. The decodings of "Decode 1" and "Decode 2" are effected parallelly. If the number of errors detected in the "Decode 1" is no more than two, "0" is loaded to the register 103, and if the number of errors is more than two, "1" is loaded to the register 103. When the content of the register 103 is "0", the output buffer of the error correction circuit 100 is selected in the error correction mode and the error is corrected or an incorrectable flag is set depending on the result of the "Decode 1". Similarly, when the content of the register 103 is "1", the error is corrected or the incorrectable flag is set depending on the result of the "Decode 2". The error correction method of the present invention is also applicable to other doubly-encoded error correction code than that shown in Fig. 1. Figs. 12 and 13 show another embodiment of the error correction method of the present invention. Numeral 11 denotes an information word, numeral 12 denotes a first check word, and numeral 13 denotes a second check word. In encoding, first check words Qi₀ - Qi₇ are added to 24 information words Wi₀ - Wi₂₃ (i = 0 - 29) to form a C₂ block 15. Then, second check words Poj, P1j (j = 0 - 31) are added to 30 information words w 0j - W 29j (j = 0 - 23) or 30 first check words Q 0k - Q 29k (k = 0 - 7) to form a C₁ block 14. In decoding, error detection and correction are effected for the C₁ block, and then error detection and correction are effected for the C₂ block. The C₁ block uses the Reed-Solomon code having a code length of 32, the number of check words of 2 and a Hamming distance of 3. Accordingly, one-word error correction can be made and the C₁ decoding is same as that shown in Fig. 2. The C₂ block uses the Reed-Solomon code having a code length of 32, the number of check words of 8 and a Hamming distance of 9. Accordingly, the error correction can be made within a range of 2S + E ≦αµρ¨ 8 The procedure of the C₂ decoding is explained with reference to the flow chart shown in Fig. 13. (1) The decoding with S=4 and E=0 is effected. Thus, up to four error word locations can be detected. If the number of errors detected is no more than three, or if the number of errors is four and a probability of miscorrection is low, three or four error words are corrected. (2) If the number of errors detected in (1) is five or more and the number of F₀ flags is four, the four F₀-flagged words are erased and the decoding with S=2 and E=4 is effected, and if the number of errors detected is no more than two, four to six error words are corrected. (3) If the number of errors detected in (1) is five or more and the number of F₀ flags is five, the five F₀-flagged words are erased and the decoding with S=1 and E=5 is effected, and if the number of error detected is no more than one, five to six error words are corrected. (4) If the number of errors detected in (1) is five or more and the number of F₀ flags is six, the six F₀-flagged words are erased and the decoding with S=1 and E=6 is effected, and if the number of error detected is no more than one, six to seven error words are corrected. (5) If the number of errors detected in (1) is five or more and the number of F₀ flags is seven, six of the seven F₀-flagged words are erased and the decoding with S=1 and E=6 is effected, and if errors are detected in only the flagged words, six to seven error words are corrected. (6) If the number of errors detected in (1) is five or more and the number of F₀ flags is eight, the eight F₀-flagged words are erased and the decoding with S=0 and E=8 is effected and eight error words are corrected. (7) when the correction conditions (1) - (6) are not met, the errors are incorrectable (F=1, F=F₀). Referring to Fig. 14, an error correction system for correcting errors by the error correction method of the present invention is explained. Fig. 14 shows a block diagram of the error correction system. Numerals 17 - 19 denote bus lines, numeral 20 denotes a syndrome generator, numerals 21 and 22 denote ROM's, numeral 24 denotes an arithmetic logic unit, numerals 25, 27 and 29 denote RAM's, numeral 26 denotes a counter, numeral 28 denotes a comparator, numeral 30 denotes a jump condition judge circuit, numeral 31 denotes a program ROM and numeral 32 denotes an address counter. The present system comprises three bus lines, circuits connected to the bus lines and a control circuit for controlling the operation of the circuits by programs. The bus line 17 is a data bus for exchanging data such as received signals and error patterns, the bus line 18 is a location bus for exchanging data such as data locations, and the bus line 19 is a flag bus for exchanging flag data to be added to the data. A data input/output terminal 38, a location input/output terminal 39 and a flag input/output terminal 40 are connected to the respective buses. The syndrome generator 20 generates a syndrome by the signal received at the data input/output terminal 38. The arithmetic logic unit 24 determines an error location and an error pattern by the syndrome generated by the syndrome generator. The arithmetic logic unit 24 carries out multiplication, division and addition operations on a Galois field (2⁸). The RAM 25 stores the syndrome and the operation result of the arithmetic logic unit 24. Numeral 23 denotes an eight-input OR circuit which determines whether the data on the data bus 17 is "0" or not. The ROM's 21 and 22 translate data on the data bus 17 (i and α i ) and the location bus 18. The data on the data bus is represented by vector, and the data on the location bus is represented by power. Accordingly, when the data are to be exchanged between the data bus 17 and the location bus 18, the data must be translated from i to α i of from α i to i by the ROM 21 or 22. The counter 26 counts the number of flags in one block. In the second decoding, the number of F₀ and F₁ is counted by the counter 26, and the count is compared with a predetermined number by the comparator 28 to determine the number of words to be corrected or whether the correction is to be made or not to be made (incorrectable). The RAM 27 stores the number of flags counted by the counter 26 and the error locations. The comparator 28 compares the number of flags with the predetermined number as described above and also compares data in the course of decoding with a constant. The RAM 29 stores the flags F₀ and F₁ which indicate the result of the first decoding and added to the data in the second decoding. The status of the flags stored in the RAM 29 is used to check the presence or absence of the flag at the error location determined by the decoding. The jump condition judge circuit 30 determines whether a branch of the program is to be carried out or not in accordance with the result determined by the OR circuit 23 and the comparator 28 and the flag status stored in the RAM 29. The program ROM 31 stores the program which controls the above circuits to effect the decoding. Numeral 33 denotes an instruction signal for determining a RAM address and the constants to be applied to the bus lines and the comparator. Numeral 34 denotes a signal for determining a condition for program branch. The jump condition judge 30 determines whether the branch is to be carried out or not by comparing the signal 34 with the contents of the OR circuit 23, the comparator 28 and the RAM 29. Numeral 35 denotes an instruction signal for determining a branch-to address, and numeral 36 denotes a signal for controlling the buffers and the registers connected to the buses. The counter 32 controls the program address. The counter 32 advances the address of the program ROM 31 by a clock supplied from a master clock input 41 to cause the program to be executed. When the program is to be branched, the branch-to address 35 is loaded in the counter 32 by the branch instruction 37 to branch the program. A reset signal to the counter 32 is applied to an input terminal 42 at a time of start of the program. In correcting the errors, the input signal is received, the syndrome is generated, and in the C₂ decoding, the number of flags is counted and and the flag status is stored in the RAM 29. Then, the decoding is effected by the program, the error locations and the error patterns are determined by the arithmetic logic unit and the error data are corrected. If the errors are incorrectable in the C₁ decoding and the C₂ decoding, flags to be added to the data are outputted from the flag input/output 40. As described above, in accordance with the error correction system of the present embodiment, the circuits are controlled by the program and are similarly applicable to the embodiment of Figs. 15 and 16. Accordingly, a circuit scale may be small and the decoding of different error correction code can be attained by merely changing the program. Figs. 15 and 16 show an embodiment of the present invention applied to a cross-interleave Reed-Solomon code (British Patent Specification GB-A-2076569A) used in a digital audio disc. This code uses a Reed-Solomon code for the C₁ block, which has a code length of 32, the number of check words of 4 and a Hamming distance of 5, and a Reed-Solomon code for the C₂ block, which has a code length of 28, the number of check words of 4 and a Hamming distance of 5. A cross-interleave Reed-Solomon code decode circuit comprises a reproduction signal input terminal, a C₁ decoder, a deinterleave circuit, a C₂ decoder and an output signal terminal. In decoding, 32-word reproduction signal is C₁-decoded. 24-word information and C₂ check words after the C₁ decoding are deinterleaved and then C₂-decoded to produce 24-word information as a decode result. Fig. 15 shows a flow chart for the C₁ decoding. As described above, the C₁ code uses the Reed-Solomon code having the minimum distance of 5. Accordingly, one-word or two-word error correction can be made. In the C₁ decoding, no error, one-word correction, two-word correction or incorrectable error because of three or more error words are possible. Three flags F₀, F₁, F₂ shown in Table 1 are added to the words in the C₁ block as flags for indicating those four types. In actual, the C₁ flag information can be handled as two-bit information per block. Fig. 16 shows a flow chart for C₂ decoding. In the C₂ decoding, the words to which the flags were added in the C₁ decoding are erased and the erasure correction is effected. Accordingly, the error correction is made within the range of 2S + 4E ≦αµρ¨ 4 as is done in the embodiment of Fig. 9. Decoding (1) : Two-word error correction Decoding (2) : Two-word erasure + one-word error correction Decoding (3) : Four-word erasure correction In order to enhance the error correction capability, it is necessary to correct many errors by the decoding (2) and the decoding (3). However, the erasure correction has a low detection capability and the correction capability is deteriorated depending on the erasure selected. In order to enhance the error correction capability and the detection capability, a decoding algorithm may be used so that the decoding (2) or the decoding (3) is effected only when the probability of miscorrection is low. A specific algorithm for the C₂ decoding is explained with reference to Fig. 16. (1) The decoding with S=2 and E=0 is first effected. Thus, up to two-word errors at any locations can be detected. when the number of errors detected is no more than two, the correction is made if the probability of miscorrection is low based on judging from the presence or absence of the flags added to the error locations and the number of flags in the block. If the probability of miscorrection is high, the errors are incorrectable. (2) If the number of errors detected in (1) is three or more and if the number of F₁ flags is three, two or three F₀-flagged words are erased and the decoding with S=1 and E=2 is effected. If the errors are detected only in the flagged words, the correction is made by using the decode result. (3) If the number of errors detected in (1) is three or more and the number of F₁ flags is three or more and the number of F₁ flags is three or more and the number of F₂ flags is two or three, the two F₂-flagged words are erased and the decoding with S=1 and E=2 is effected. If the errors are detected only in the F₁-flagged words, the correction is made by using the decode result. (4) If the number of errors detected in (1) is three or more and the correction condition (2) or (3) is not met, the errors are incorrectable. Fig. 17 shows a comparison of the error correction capabilities and the error detection capabilities in the embodiment of the present invention shown in Figs. 15 and 16 and the prior art system. In Fig. 17, an abscissa represents a word error rate and an ordinate represents an error probability after error correction. A curve I represents the correction capability and the detection capability in the prior art system disclosed in the U.S. Patent US-A-4437185 to Sako et al. In this correction method, only one flag (pointer code signal) is added to each word signal in the first C₁ decoding, and two errors can be corrected in the next C₂ decoding. A curve II represents the correction capability and the detection capability by the correction method disclosed in the above related application. In this method, the C₂ decoding uses the correction procedures by three decodings, that is, error correction, error and erasure correction, and erasure correction. A curve III represents the correction capability and the detection capability by the embodiment of the present invention. The correction procedure of the above related application is further improved to enhance the correction capability. In the characteristics of Fig. 17, the detection capabilities are substantially equal for the respective cases I - III. On the other hand, the correction capability of the characteristic II at word error rate of 10⁻³ is two orders higher than that of the characteristic I, and that of the characteristic III is four orders higher than that of the characteristic I.

Claims: An error correction method for decoding code words having first code code blocks (5) including a plurality of information words arranged in a first arrangement and a plurality of first check words Q (2) generated by a code having a Hamming distance of d₁ to said information words, and second code blocks (4) including a plurality of information words arranged in a second arrangement and a plurality of first check words Q (2), each of said second code blocks (4) having a plurality of information words and a plurality of first check words Q (2) belonging to different ones of said code blocks (5), and a plurality of second check words P (3) generated by a code having a hamming distance of d₂ to said plurality of information words and said plurality of first check words Q (2), said method comprising the following steps: (a) In the first decoding stage, detecting errors for said second code blocks (4) and after detection adding to each information word of said respective code blocks (4) at least one type of flags representing a decoding status based on the number of detected errors; said stage including error detection and correction of up to S₁ words, where 2S₁ ≦αµρ¨ d₂ - 1, wherein S₁ is the number of word errors at unknown locations, the number of types of flags depending on the number of errors which can be corrected in the first decoding stage; (b) In the second decoding stage, detecting errors for said first code blocks (5) and correcting S₂ words errors and E word erasures satisfying 2S₂ + E ≦αµρ¨ d₁ - 1, where S₂ is the number of word errors at unknown locations in the second decoding stage and E is the number of erasures (errors with known locations), determining for a plurality of combinations of S₂ and E errror locations and error patterns based on the number of errors detected in the second decoding stage, on the coincidences of error locations detected in the second decoding stage with the flagged locations and on the number of flags in said first code blocks (5), and selecting the combination of S₂ and E having a high correction capability and a low probability of miscorrection on the basis of the plurality of determined error locations and error patterns, and correcting the word errors in the second decoding stage based on the error location and the error pattern of a selected combination of S₂ and E, and wherein said first code blocks (5) can be decoded more than once in the second decoding. An error correction method according to claim 1 wherein two of said second decoding stage are executed simultaneously for the same input information, and according to the number of errors detected in each one of said two second decoding stages, the decoding result of this one or of the other second decoding stage is used. An error correction method according to Claim 1 wherein, in said second decoding stage, error locations and error patterns are parallelly or sequentially determined for the plurality of combinations of S₂ and E satisfying 2S₂ + E ≦αµρ¨ d₁ - 1. An error correction method according to Claim 1 wherein said code words are doubly-encoded Reed-Solomon codes. An error correction method according to Claim 1 wherein said code words are doubly-encoded cyclic redundancy check codes. An error correction method according to Claim 1 wherein the decode result of the combination of S₂ and E having a minimum probability of miscorrection determined by the decoding result and the number of flags in a unit block is selected out of the plurality of decode results for the error locations and error patterns, and the word error is corrected based on the selected decode result. An error correction system for decoding according to the method of claim 1 an error correcting code with flags, indicating that one error has been corrected in the first decoding stage, and indicating that two or more code words are in error,said error correcting code being produced over a Galois field in which the code length is n words and the number of information words is (n-k) and the number of check words is k, comprising: (a) a syndrome generator (20) for generating k syndromes in response to an input signal including information words and check words of one code block; (b) an arithmetic logic circuit (24) for performing multiplication, division and addition over the Galois field; (c) a counter (26) for counting a plurality of flags for information word and check word of each code block; (d) at least a data memory (25, 27) for storing the values of said syndromes from said syndrome generator (20), the result of the arithmetic operation by said arithmetic logic circuit (24), the numbers of flags counted by said counter (26), and the locations of flags added to said input signal; (f) said comparator (28) comparing the numbers of flags counted by said counter (26) and the numbers of errors determined by said arithmetic logic circuit (24), with predetermined numbers to determine the number of words to be corrected or whether the correction is to be made or not (e) a program memory (31) for storing a program for controlling said arithmetic logic circuit (24), a comparator (28) and said data memory (25, 27) so as to perform the error correcting operation and addition of the flags; (g) a judging circuit (30) for determining in accordance with a first signal supplied from said program memory (31), whether or not to jump the program, depending on the results of the comparison from said comparator (28) and the status of the flags; (h) a control circuit (32) responsive to the output of said judging circuit (30) for controlling program address of said program memory (31); and (i) said arithmetic logic circuit (24) being coupled to said syndrome generator (20), said data memory (25, 27) and said program memory (31) and determining for each of the k syndromes error locations and error patterns based on the syndromes representing the numbers of errors. An error correction system characterized in that it comprises (a) a first error correction circuit (100) as defined in claim 7, (b) a second error correction circuit (101) as defined in claim 7, said first and second error correction circuits (100) and (101) both receiving simultaneously a same input signal to be decoded in parallel; and (c) a memory (103) for storing a second signal received from said first error correction circuit (100) indicating whether the decode result of said first or said second error correction circuit has to be used.

Inventors: ARAI, TAKAO, KIMURA, HIROYUKI, KOBAYASHI, MASAHARU, NOGUCHI, TAKAHARU, OKAMOTO, HIROO
Applicants: HITACHI, LTD.
Application year: 1984
Main classification: G11B20
IPC codes: G06F11, H03M13, G11B20, H04L1