PULSE GENERATING CIRCUIT

Abstract: A pulse generating circuit for generating a pulse signal in response to first and second input signals which have complementary relation, the pulse generating circuit includ­ ing a first logic circuit having a first input teminal for receiving the first input signal, a second input terminal, and an output terminal, a second logic circuit having a first input terminal for receiving the second input signal, a second input terminal connected to the output terminal of the first logic circuit, and an output terminal connected to the first input terminal of the first logic circuit. One of the first and second logic circuits changes its output signal in response to a change of the output signal of the other logic circuit. The pulse generating circuit further includes a third logic circuit having a first input terminal for receiving an output signal from the first logic circuit, a second input terminal for receiving an output signal from the second logic circuit, and an output terminal for outputting the pulse signal when the logic level of the output signals from the first and second logic circuit coincide.

Description: PULSE GENERATING CIRCUIT BACKGROUND OF THE IlRENTION (1) Field of the Invention The present invention relates to a pulse generating circuit, more particularly a circuit for generating a pulse signal in response to a change of two complementary signals which vary in logic levels to inverse levels about at the same time. The pulse generating circuit can be applied to an address transition detecting circuit in a semiconductor memory device and to other pulse circuits for providing an accurate timing pulse generated in accordance with a change of two complementary signals. (2) Description of the Related Art In a semiconductor memory device such as a static-type random access memory (S-RAM), the access time is shortened by the provision of short-circuit transistors between bit lines of each bit line pair, between data bus lines, between sense-amplifier (S/A) lines of each S/A line pair, and between data-out buffer lines of each data-out buffer line pair. The transistors are temporarily turned on in response to a clock pulse which is generated in accordance with a change of an input address signal when a readout of information is effected, so that the potential difference between bit lines or data bus lines of each pair rapidly becomes zero. The clock pulse is also used for initializing a sense-amplifier and an output buffer. To generate the clock pulse in accordance with the change of address signals, an address transition detecting (ATD) circuit is provided in the semiconductor memory device. The reduction of the access time of the memory device depends on operation of the short-circuit transistors at the desired timing and with the predetermined operation time. Accordingly, many pulse generating circuits for the ATD circuit have been proposed for providing the clock signal for triggering the transistors. U.S. Patent No. 4,464,581, "Trigger Pulse Generatorw, issued on August 7, 1984, with the same assignee as the present invention, discloses a preferable pulse generation circuit. The invention, however, still suffers from disadvantages of omissions of pulse generation in the case of two complementary address signals having a considerably different timing of phase change and in the case of the pulse width change depending on the deviation of timing of two complementary address signals inversely changing. The above disadvantages will be explained later in detail with reference to a specific circuit. SUMMARY OF THE INVENTION It is an object of the present invention to provide a pulse generating circuit generating a pulse having a predetermined pulse width in response to a change of two complementary input signals. According to the present invention, there is provided a pulse generating circuit for generating a pulse signal in response to first and second input signals which have a complementary relation, the pulse generating circuit including a first logic circuit having a first input terminal for receiving the first input signal, a second input terminal, and an output terminal; a second logic circuit having a first input terminal for receiving the second input signal, a second input terminal connected to the output terminal of the first logic circuit; and an output terminal connected to the first input terminal of the first logic circuit. One of the first and second logic circuits changes its output signal in response to a change of the output signal of the other logic circuit. The pulse generating circuit further includes a third logic circuit having a first input terminal for receiving an output signal from the first logic circuit, a second input terminal for receiving an output signal from the second logic circuit, and an output terminal for outputting the pulse signal when the logic levels of the output signals from the first and second logic circuits coincide. BRIEF DESCRIPTION OF THE DRAWINGS Other objectives and features of the present invention will be described below in detail with reference to the accompanying drawings, in which: Fig. 1 is block diagram of an S-RAM device including an ATD circuit; Fig. 2 is a circuit diagram of an address buffer and a predecoder with a prior art pulse generating circuit; Figs. 3A, 3B and 4A, 4B are timing charts of signals in the prior art generating circuit; Figs. 5A, 5B are timing charts of the circuit shown in Fig. 1 with a prior art pulse generating circuit applied to the ATD circuit; Fig. 6 is a circuit diagram of an embodiment of the present invention; Fig. 7 is a detailed circuit diagram of a specific example of the circuit shown in Fig. 6; Figs. 8A, 8B, 8C to 10A, 10B, 10C are timing charts of the operation of the circuit shown in Fig. 7; ; Fig. 11 is a detailed circuit diagram of another specific example of the circuit shown in Fig. 6; and Fig. 12 is a detailed circuit diagram of still another specific example of the circuit shown in Fig. 6. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing preferred embodiments of the present invention, an explanation will be given of the prior art, with reference to Figs. 1 to 5A, 5B. Figure 1 is a block diagram of the S-RAM device, In Fig. 1, an S-RAM device includes an address buffer 1, a predecoder circuit 2, a row decoder circuit 3, a column decoder circuit 4, a remory ceil array 5, a column gate portion 6, an S/A portion 7, and a data-out buffer portion 8. The memory cell array 5 includes a plurality of static memory cells each connected to a word line (WL) and between a pair of a bit line (BL) and an inverted bit line (BL). The above components are similar to those of a conventional S-RAM device, accordingly, an explanation thereof will be omitted. The S-RAM device further included an ATD circuit 9 consisting of a plurality of pulse generating circuits (PG) each generating a clock pulse Xi in response to a change of a pair of address bits Ai and A. , and an 1 1 OR gate having inputs connected to outputs of the pulse generating circuits and outputting an OR'ed clock pulse 0. There is also provided a plurality of shortcircuit transistors QBLO to QBL255 , each provided between a pair of bit lines BL and BL in the memory cell array 5; and a short-circuit transistor QDB provided between a pair of a data bus (DB) and an inverted data bus (DB). The transistors mentioned above are turned on in response to the clock pulse 0 from the ATD circuit 9. Figure 2 is a circuit diagram of the address buffer 1 and a pulse generating circuit in the ATD circuit 9. The address buffer 1 receives an address signal consisting of a plurality of address bits, for example 16 bits Ao to A15 for activating 256 word lines and 256 bit lines in a 64K bit S-RAM device, and outputs a plurality of pairs of address bit signals each consisting of a non-inverted and an inverted address bit signal. Figure 2 shows one address buffer of an input address bit Ao and an inverted and non-inverted output address bit signal SAO and SAQ. The address buffer includes a common inverter 11, two tandem inverters 12 and 13, and three tandem inverters 14 to 16, each inverter formed as a complementary metal oxide semiconductor (C-MOS) inverter. The pulse generating circuit in the ATD circuit 9 is substantially identical to that disclosed in U.S. Patent No. 4,464,581. The pulse generating circuit consists of depletion-type metal insulated semiconductor (MIS) field effect transistors (FET's) 91 and 94, inverters 92, 93, 95, and 96, and a NOR gate 97 and in connected as shown in Fig. 2. The operation of the address buffer and the pulse generating circuit shown in Fig. 2 will be explained below in detail. When the input signal Ao at the address buffer 1 changes from high level to low level, the non-inverted output signal SAo rapidly changes from high level to low level and the inverted output signal SAo rapidly changes from low level to high level. When the pulse generating circuit receives both signals SAo and SAO , the gate-source potential of the transistor 94 rises and the gate-source potential of the transistor 91 falls, so that the input signal SA of the pulse generating circuit is transferred to the inverter 95 through the transistor 94 having the large mutual conductance gm (or the large conductivity). In this case, electric charges in the stray capacitance at the input of the inverter 95 are quickly discharged. On the other hand, the input signal SAo is gradually transferred to the inverter 92 through the transistor 91 having the small mutual conductance gm. .The stray capacitance at the input of the inverter 92 is gradually charged with a time constant defined by the stray capacitance and the resistance of the transistor 91. As a result, the input signal SC applied to the inverter 95 falls rapidly and the input signal SB applied to the inverter 92 rises gradually. After a short period elapses, when the input signal Ao at the address buffer 1 rises from low level to high level, the input signal SC to the inverter 95 rises slowly and the input signal SB to the inverter 92 falls quickly. Two pairs of series-connected inverters 92, 93 and 95, 96 perform wave-shaping of the input signals SB and SC, respectively. Wave-shaped signals SB' and SC' are supplied to the NOR gate 97, so that a clock pulse dg synchronized with the falling (or trailing) and rising edge of the input signal A and having a predetermined width is generated. The pulse width Pw of each output clock pulses 00 is substantially defined by mutual conductances gm of the transistors 91 and 94, the threshold potentials Vth of the inverters 92 and 95, and the stray capacitance at the inputs of the inverters 92 and 95. In the above description, it is assumed that two complementary signals SA, and SA, are changed in level at 0 the same time. It should be noted that, in the address buffer shown in Fig. 2, the inverted signal SAO , on one 0 hand, is generated through three series inverters 11, 12, and 13, and the non-inverted signal SAO , on the other hand, is generated through four series inverters 11, 14, 15 and 16. In other words, there is an inherent time delay between the signals Sg and S due to the differ- ence of inverter steps. As a result, there is a time lag of change between the signals SAO and SA , as shown in 0 Figs. 3A and 4A, so that the output signals SB and SC in the pulse generating circuit differ in changing timing. This may vary the pulse width Pw of the clock pulse 0. Variation of the pulse width P of the clock w pulse 0 adversely affects the access time, as shown in Figs. 5A and 5B. Figures 5A and 5B show curves of the transient status of the clock pulse 0, the word line signal WL, the address signal AD, and the pair of bit lines BL and BL. In Fig. 5A, the longer width clock pulse 0 may result in an idle time Td. In Fig. 5B, the shorter width clock pulse X may result in an idle time Td'. In order to overcome the disadvantage mentioned above, in the prior art circuit, the address buffer 1 shown in Fig. 2 must be constructed to output two complementary signals SA and SA with a perfect symmetrical timing of change. This, however, requires a difficult device design and strict manufacturing process. In addition, the pulse generating circuit 9 shown in Fig. 2 may omit generation of the pulse when two complementary signals SA and SA are changed with a considerable time lag. The present invention will now be described with reference to Figs. 1 and 6 to 12. Figure 6 is a circuit diagram of an embodiment of a pulse generating circuit in accordance with the present invention. The pulse generating circuit 100 in Fig. 6 consists of three NAND gates 110, 120, 130. As shown in Fig. 6, a first input signal SA and an output signal SB of a second NAND gate 120 are applied to inputs of a first NAND gate 110, a second input signal SA and an output signal SB of the first NAND gate 110 to inputs of the second NAND gate 120, and the output signals SB and SB to inputs of a third NAND gate 130. The third NAND gate 130 outputs a pulse 0. The pulse generating circuit 100 can be applied to the ATD circuit 9 in Fig. 1 instead of the circuit shown in Fig. 2 mentioned before. Figure 7 is a detailed circuit diagram of the circuit shown in Fig. 6. The pulse generating circuit 101 shown in Fig. 7 is realized by using a plurality of C-MOS type inverters. A first NAND circuit 111 corresponding to the NAND circuit 10 in Fig. 6 is formed by two p-channel enhancement (p-E) type MOS transistors Q1 and Q4 connected in parallel and two n-channel enhancement (n-E) type MOS transistors Q2 and Q3 connected in series. Similarly, a second NAND circuit 121 corresponding to the NAND circuit 120 in Fig. 6 is formed by two p-E type MOS transistors Q5 and Q8 and two n-E type MOS transistors and 07. A third NAND circuit 131 corresponding to the NAND circuit 130 in Fig. 6 is also formed by two p-E type MOS transistors Qg and Q12 and two n-E type MOS transistors Qlo and Qll Reference Vcc indicates a direct current (DC) power supply of 5V and GND a ground level. The operation of the pulse generating circuit 101 shown in Fig. 7 will be explained with reference to Figs, 8A 8B, 8C to lOA, 10B, 10C. First, the operation of the pulse generating circuit 101 will be explained in the case of two complementary input signals SA and SA having symmetrically transient waveforms, as shown in Fig. 8A. At the initial condition, the input signal SA is high level and the input signal SA is thus low level, whereby the transistors Q2 and Q3 in the NAND circuit 111 and the transistors Q5 and Q8 in the NAND circuit 121 are turned on and the transistors Q1 and Q4 in the NAND circuit 111 and the transistors Q6 and Q in the NAND circuit 121 are turned off. As a result, the output signal SB of the NAND circuit 111 is low level, and the output signal SB of the NAND circuit 121 is high level. Receiving the signals SB and SB, in the gate circuit 131, the transistors all and Q12 are turned on and the transistors Qg and Q10 are turned off, consequently the output pulse X is high level, as shown in Fig. 8C. As the input signal SA begins to fall to low level as shown in Fig. 8A, the conductivity for the mutual conductance gm) of the transistor Q4 becomes high and the conductivity of the transistor Q2 becomes low. The resultant signal SB begins to rise as shown in Fig. 8B. Symmetrically, the input signal SA begins to rise to high level. In the NAND circuit 121, even if the transistor Q8 begins to turn off and the transistor begins to turn on, the output signal SB of the NAND circuit 121 is still maintained at high level until the transistor Q5 is turned off and the transistor Q7 is turned on. In this manner, the output signal SB begins to fall when the output signal SB of the NAND circuit Ill fully becomes high level. In this transient con i- tion, the waveforms of the output signals SB and SB are represented as shown in Fig. 8B, i.e., there exists a period when both output signals SB and SB are higher than a predetermined level VL. During the period, the signals SB and SB are applied to gates of the transistors Q12 and Qlo and to gates of the transistors Qg and Qll in the NAND circuit 131, the transistors Q10 and Q11 are turned on, and the transistors Qg and Q12 are turned off. As a result, at the output of the NAND circuit 131, a clock pulse X having a predetermined pulse width Pw corresponding to the above period is obtained. The clock pulse X also indicates a change of the input signals SA and SA. Next, operation of the pulse generating circuit 101 shown in Fig. 7 will be explained in the case of the rising of the input signal SA being delayed from the falling of the input signal SA by a time td, as shown in Fig. 9A. The output signal SB of the NAND circuit 111 begins to rise in response to the falling of the input signal SA. On the other hand, the output signal SB is maintained at high level until the logic level of the output signal SB rises higher than the level VL , as shown in Fig. 9B, since the transistor Q7 is not turned on. As the logic level of the output signal SB reaches the level VL , the transistor Q7 is turned on. As a result, the output signal SB falls to low level. In this case, there is a period when both output signals SB and SB are higher than the level VL , as shown in Fig. 9B. Accordingly, the NAND circuit 131 outputs the clock pulse # having the pulse width Pw equal to the pulse width shown in Fig. 8C. Next, the operation of the pulse generating circuit 101 shown in Fig. 7 will be explained with reference to Figs. 10A to 10C in the case of the falling of the input signal SA being delayed from the rising of the input signal SA by the time td mentioned above. When the input signal SA rises to high level, the transistor Q6 is turned on and the transistor Q is 8 turned off. On the other hand, the output signal SB is still maintained at high level urtil the output signal SB rises higher than the level VL , because when the output signal SB remains at low level, the transistor Q5 is still turned on and the transistor Q7 is also still turned off. As the input signal SA falls, the transistor Q4 is turned on and the transistor Qz is 2 turned off, whereby the output signal SB falls. In response to the above operation, the transistor Q5 is turned off and the transistor Q7 is turned on. As a result, the output signal SB begins to fall as shown in Fig. 10B. The output signals SB and SB vary as shown in Fig. lOB. The NAND circuit 131, thus, outputs the clock pulse d having the pulse width Pw equal to that shown in Fig. 8C. As mentioned above, the pulse generating circuit 101 shown in Fig. 7 can detect the change of the input signals SA and SA and can reliably provide the clock pulse 0 having a constant pulse width in response to the change of both complementary signals SA and SA, not only when the signals SA and SA are changed at a perfectly symmetrical timing, but also an asymmetrical timing. In the above description, the second NAND circuit 120 is controlled by the output signal SB of the first NAND circuit 110 when the input signal SA is high level and the input signal SA is low level at the initial condition. On the other hand, the first NAND circuit 110 is controlled by the output signal SB of the second NAND circuit 120 when the input signal SA is low level and the input signal SA is high level at the initial condition. Generally speaking, the pulse generating circuit 100 shown in Fig. 6 is designed to operate a first NAND circuit, i.e., one of the NAND circuits 110 and 120, in response to the change of one input signal from high level to low level; to operate a second NAND circuit, i.e., the other of the NAND circuits 110 and 120, in the case of an output signal of the first NAND circuit being higher than the predetermined level; and to output a pulse having a predetermined pulse width from a third NAND circuit 130 when the two output signals from the first and second NAND circuits are both higher than the predetermined level. Other embodiments of the circuit 100 shown in Fig. 6 are possible in addition to the C-MOS NAND circuit 101 shown in Fig. 7. Figure 11 is a circuit of another embodiment formed as an n-channel (N-)MOS NAND circuit. The pulse generating circuit 102 consists of three NAND circuits 112, 122, and 132. The NAND circuit 112 includes an n-channel depletion (n-D) transistor #Q21 and two n-channel enhancement (n-E) transistors Q22 and Q23' the NAND circuit 122 an n-D transistor Q24 and two n-E transistors Q25 and Q26; and the NAND circuit 132 an n-D transistor Q27 and two n-E transistors Q28 and Q29' The operations of the pulse generating circuit 102 is similar to the operation of the circuit 101 shown in Fig. 7. Figure 12 is a circuit of still another embodiment of the circuit shown in Fig. 6, formed by N-MOS NAND circuit. The pulse generating circuit 103 consists of three NAND circuits 113, 123, and 133. The circuits 113 and 123 are respectively formed by three n-E transistors to to Q33 and Q34 to Q36. The third NAND circuit 133 is formed by an n-D transistor Q37 and two n-E transistors Q38 and 039. The first logic circuit 113 has three input signals: i.e., the input signal SA to a gate of the transistor Q31 t the input signal SA to a gate of the transistor Q32 t and the input signal SB from the second logic circuit 123. Similarly, the second logic circuit 123 has three input signals. In the circuits shown in Figs. 7 and 11, the first and second logic circuits had only two input signals. This difference between the circuit shown in Fig. 12 and others mentioned above, however, is not significant. The main parts in the first and second logic circuits 113 and 123 shown in Fig. 12 are the transistors Q32 and Q33 and the transistors Q35 and Q36 t thus the first and second logic circuits 113 and 123 substantially function as two-input NAND circuits. Accordingly, operation of the pulse generating circuit 103 is similar to that of circuit 101 shown in Fig. 7, When the pulse generating circuit of the present invention is applied to the ATD circuit 9 shown in Fig. 1, the optimum access time can be obtained by providing a clock pulse, generated by the pulse generating circuit and having a predetermined pulse width adjusted to minimize the access time, to the shortcircuit transistors shown in Fig. 1 and mentioned before. In addition, the pulse generating circuit facilitates the design of other circuits, for example, the row and column address decoders 3 and 4 in Fig. 1, which receive an address signal consisting of a plurality of pairs of address bits composed of two complementary signals. The present invention can be realized by other logic circuit technologies instead of the NAND logic circuit technology mentioned above, for example, a NOR logic circuit technology. The present invention can also be realized by other circuits instead of the MOS circuit, for example, a MIS circuit. The pulse generating circuit in accordance with the present invention can be applied to other systems, for example, asynchronous-type memory systems, such as a mask-ROM device and an erasable programmable ROM (EPROM) device. In these devices, there are no bit lines pair and each data line forms a single line. The pulse generating circuit of the present invention can be used to reset, for example, a data-out buffer and word lines to improve the access time.

Claims: CLAIMS 1. A pulse generating circuit for generating a pulse signal in response to first and second input signals which have complementary relation, said pulse generating circuit comprising: a first logic circuit having a first input terminal for receiving said first input signal, a second input terminal, and an output terminal; a second logic circuit having a first input terminal for receiving said second input signal, a second input terminal connected to said output terminal of said first logic circuit, and an output terminal connected to said first input terminal of said first logic circuit; one of said first and second logic circuits changing its output signal in response to a change of the output signal of the other logic circuit; and a third logic circuit having a first input terminal for receiving an output signal from said first logic circuit, a second input terminal for receiving an output signal from said second logic circuit, and an output terminal for outputting said pulse signal when the logic level of said output signals from said first and second logic circuit coincide. 2. A pulse generating circuit according to claim 1, wherein the one of the first and second logic circuits which receives the input signal which changes in logic level faster than the other input signal changes its output signal level in response to said faster changing input signal and the other logic circuit is controlled by the output signal of said one logic circuit and changes its output signal level to a level inverse to the output signal level of said one logic circuit when the output signal level of said one logic circuit passes the predetermined level 3. A pulse generating circuit according to claim 2, wherein a pulse width of the pulse output from the third logic circuit is defined by an overlapping time wherein both output signals of the first and second logic circuits pass the predetermined level. 4. A pulse generating circuit according to claim 1, wherein each of said first, second, and third logic circuits is formed by a NAND logic circuit. 5. A pulse generating circuit according to claim 4, wherein each of said NAND logic circuits is formed by a C-MOS circuit. 6. A pulse generating circuit according to claim 5, wherein each C-MOS circuit comprises a first and second p-channel enhancement transistor connected in parallel, their common connected sources being connected to a power supply, and a first and second n-channel enhancement transistor connected in series, one end of the series being connected to the commonly connected drains of said first and second p-channel enhancement transistors and the other end being connected to a ground level. 7. A pulse generating circuit according to claim 4, wherein each of said NAND logic circuits is formed by an n-channel MOS circuit. 8. A pulse generating circuit according to claim 7, wherein each n-channel MOS circuit comprises a depletion-type transistor and two enhancement-type transistors, these transistors being connected in series. 9. A pulse generating circuit according to claim 7, wherein each n-channel MOS circuit of the first and second logic circuits comprises three enhancementtype transistors connected in series, and the third n-channel MOS logic circuit comprises a depletion-type transistor and two enhancement-type transistors, these transistors being also connected in series, wherein, in the first logic circuit, a gate of the first transistor receives said one input signal, a gate of the second transistor receives said other input signal, and a gate of the third transistor receives the output signal of the second logic circuit, wherein, in the second logic circuit, a gate of the first transistor receives said other input signal, a gate of the second transistor receives said one input signal, and a gate of the third transistor receives the output signal of the first logic circuit, and wherein, in the third logic circuit, a gate of the first enhancement-type transistor receives the output signal of the first logic circuit, and a gate of the second enhancement-type transistor receives the output signal of the second logic circuit. 10. A pulse generating circuit according to claim 1, wherein each of said first, second, and third logic circuits is formed by a NOR logic circuit.

Inventors: FURUMOCHI, KAZUTO, ITOH, HIDEO, KOSHIZUKA, ATUO
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: H03K5
IPC codes: H03K5, G11C8, H03K3