ELECTRICAL CIRCUIT COMPRISING A HYBRID POWER SWITCHING SEMICONDUCTOR DEVICE INCLUDING AN SCR STRUCTURE

Abstract: Hybrid power switching semiconductor devices advan­ tageously combine SCR structures that have relatively high current-carrying capability but no gate turn-off control, with IGR or MOSFET device structures that have a gate electrode which maintains both turn-on and turn-off control of the device. In one form, an IGR structure is designed, through choice of cathode shorting density, to allow latch on of the integral SCR at a relatively low device current. In another form of device, separate MOSFET and a MOS-gated SCR portions are simultaneously fabricated on a single chip within the same active device area. In one embodiment, an N+ buried layer is included only in the MOSFET section, and serves to avoid bipolar action during high frequency gate-­ controlled switching. In another embodiment, a first main terminal region layer has separate N+ and P+ portions included respectively in the MOSFET and MOS-gated SCR portions of the device. The devices are particularly suited for controlling electrical load devices, such as lamp filaments, of the type which draw a relatively higher inrush current when initially energized, and a relatively lower operating current thereafter. Also disclosed are electrical circuits and methods of using such devices.

Description: HYBRID hybrid POWER SWITCHING SEMICONDUCTOR DEVICES INCLUDING SCR STRUCTURES BACKGROUND OF THE INVENTION The present invention relates to hybrid power switching semiconductor devices which advantageously combine SCR structures, having relatively high current-carrying capability but no gate turn-off control, with other semiconductor device structures for example, IGRs or MOSFETs, of the type having a gate electrode which maintains both turn-on and turn-off control of the device. ; Various types of three-terminal power switching semiconductor devices are known, the various device types in many cases having different operating characteristics and being ; suitable for various and different specific circuit applications. One general type of power switching semiconductor i device is a thyristor, a common example of which is a silicon controlled rectifier (SCR). An SCR is a four-layer PNPN switching device having the advantageous characteristic of relatively high current-carrying capability. Another advantageous characteristic of an SCR is the ability to block reverse voltages. However, as is well known, a disadvantage of a conventional SCR is that the gate electrode controls only turn-on of the device. Once triggered into conduction through application of suitable gate voltage, an SCR latches on through a regenerative switching action and remains conducting, even though gate voltage is thereafter removed. An SCR does not turn off until forward current through the device drops below a certain holding current value characteristic of any given SCR, at which point the regenerative switching action is no longer maintained. A typical SCR or thyristor Comprises, in succession, a P (or highly doped P-type) emitter region which serves as the device anode region, an N (or lightly doped N-type) base region, a P (or P-type, of a reference doping level) base region, and an N+ emitter region which serves as the device cathode region. Particularly relevant in the context of the present invention is a specialized form of thyristor or SCR known as a MOS-gated SCR or thyristor or, more generally, an insulated-gate triggered SCR or thyristor. Such devices are disclosed, for example, in Yamashita et al U.S. Pat. 3,753,055 and Savi ge U.S. Pat. 3,831,187. A MOS-gated SCR is a PNPN thyristor structure in which regenerative turn-on is initiated by-application of a voltage to an insulated gate. These devices combine the current-carrying capability of an ordinary 5CR, with the additional advantage of requiring relatively low gate power to turn on the device via the MOS gate. However, MOS-gated SCRs do not exhibit gate turn-off capability. One of the reasons an SCR has a relatively high current capability is that during forward conduction all three PN junctions within the device are forward-biased and a bipolar conduction mode occurs. In particular, the two device intermediate regions, (one of P conductivity type and one of N conductivity type) each constitute what, for convenience, is herein termed an "active-base" region, signifying that condllstion in such a region involves more than the mere flow of majority carriers, i.e.1 electrons in the case of an N conductivity type region and holes in the case of a P conductivity type region. Rather, both electrons and holes are injected into such .¯active-base" regions, as employed herein, during device operation, and a rapid rate of recombination occurs in these device active-base regions, increasing device conductivity. Deserving mention in the context of the present invention is a two-transistor analogue which as is well known, can for many analysis purposes be employed to represent a four-layer PlUN thyristor structure. The two-transistor analog comprises an upper NPE bipolar transistor and a lower PNP bipolar transistor, with the base of the NPN transistor connected to (and comprising the same device region as) the collector of the PNP transistor, and the base of the PNP transistor corresponding to (and comprising the same device region as) the collector of the NPN transistor. Each of these two bipolar transistors is characterized in part by a common-base current gain. The overall device is regenerative, i.e. can latch into a conducting state, when the device structure and current flow are such that the sum of the common-base current gains of the two transistors is in excess of unity. Also deserving mention is the common inclusion in SCR structures of cathode shorts for the purpose of improving dV/dt capability, i.e. reducing the tendency of the device to switch to its ON state due to a rapidly-increasing anode voltage, even though the magnitude of the anode voltage remains well below device breakover voltage. Specifically, a cathode short" comprises a abort between the device N+ cathode region and the adjacent P base region. A given device has a cathode shorting density determined by the relative contact areas of the cathode electrode with the adjacent base region and with the N+ cathode region itself. In SCRs, a relatively low cathode shorting density is employed, sufficient to enhance the dV/dt capability, but not so high that regenerative switching action is prevented. Another known general type of three-terminal power switching semiconductor device is a power MOSFET, examples of which are disclosed in ishitani U.S. Pat. No. 4,072,975, and in Blanchard U.S.-Pat. No. 4,145,703. Such a device may more generically be termed an insulated-gate field-effect transistor (IGFET), and the two terms, MOSFET and IGFET, are employed interchangeably herein. A typical N-channel power MOSFET includes an N+ (or highly-doped N conductivity type) source region and an N (or high resistivity N conductivity type) drift or drain region separated from each other by a P shield-base region having a channel surface. An insulated gate electrode is disposed over the channel surface. In operation, application of a sufficiently large positive gate electrode bias (with reference to the source region) through a depletion process results in the formation of an N conductivity type inversion layer in the P shield-base region just below the channel surface. The inversion layer thus comprises an induced conduction channel allowing the conduction of electrical current from the source to the drain. Significantly, the gate maintains both turn-on and turn-off control. MOSFETs are unipolar conduction devices. In particular, in MOSFET devices, it is primarily majority carrier (e.g. electron) current which flows between source and drain. The N drain region is merely a drift region, and does not function as an active base region wherein recombination occurs. Because excess charge carriers (electrons and holes) do not accumulate in the N conductivity type drift region, device turn off is extremely rapid, and a power MOSFET is capable of relatively high switching speeds, e.g. in excess of 100 MHz. Related to the unipolar conduction mode is the fact that there is no regenerative turn-on mechanism intended in MOSFET structures, and this is one reason the gate at all times maintains control over MOSFET conduction, in contrast to an SCR. One disadvantage of a power MOSFET is relatively high on-resistance. The reason is that current flow is limited by the majority carrier (electron) concentration in the Nconductivity type induced channel and N conductivity type drift regions, which determines their resistivity. For devices designed for operation at greater than 100 volts, the resistance of the drift region becomes large because, in order to support the device blocking voltages, the majority carrier concentration in the drift region must be small and the drift region width must be large in order to support the device blocking voltages. In consequence, due to the high drift region resistance, high voltage MOSFET devices must be operated at low current densities to obtain low forward voltage drops. Power MOSFETs also include shorts. Specifically, these are source-to-base shorts, corresponding to cathode shorts in an SCR, but with a higher shorting density such that operation of a parasitic SPN bipolar transistor inherent in the MOSFET device structure is inhibited. Operation of this parasitic bipolar transistor would otherhtise degrade the switching speed of the MOSFET device. A third type of three-terminal power switching semiconductor device is known as an insulated-gate rectifier (IGR), various forms of which are disclosed in commonly-assigned German Patent Application P 31 47 075.C, filed November 27, l981 by B.J. Baliga and entitled NEGATE ENHANCED RECTIFIER". (It nay be noted that a agate enhanced rectifier", or GERECT", is alternatively referred to herein as an 'a insulated-gate rectifier", or wIGR". The two terms wGEPECTW and "IGR" are intended to mean the same device.) Briefly, an IGR is a semiconductor device having an insulated gate for controlling flow between its main electrodes, i.e., between its anode and cathode terminals. The gate and conduction channel of an IGR are similar to corresponding elements in a MOSFET with, however, important differences between the two devices (an IGR and a MOSFET), as described in detail in the above-identified Baliga application P 31 47 075.C and summarized below. Previously-disclosed IGRs may appear to be structurally similar to vertical channel MOSFETs. with an important distinction. In particular, assuming the case of an N-channel device, a P anode region, not found in a MOSFET, is included. A four-layer, i.e. PNPN, device therefore results. operation also differs from that of a MOSFET, the most significant consequence of the operational difference being that the IGR has much higher forward conductivity. In particular, as summarized above, a power MOSFET is a unipolar conduction device wherein conduction occurs primarily by simple electron current flow, without the presence of excess carriers. In contrast, in an IGR, the P+ anode region injects minority carriers (e.g. holes) into the N conductivity type region corresponding to the drift region of a MOSFET. As in an SCR as summarized above, the drift region of an IGR constitutes what, for convenience, is herein termed an "active-base" region, signifying that conduction in this particular region involves more than the mere flow of majority carriers, e.g. electrons. Rather, during operation the holes introduced into the active-base region recombine with electrons introduced from the cathode, increasing device conductivity. The conduction mode is therefore bipolar in part. The P base region in an IGR serves primarily to support the induced conduction channel, as in a MOSFET, and thus maintains the same character as an inactive shield-base region, not supporting a bipolar conduction process. An IGR differs from a four-layer PNPN thyristor, even though some forms of IGR are superficially somewhat similar structurally to typical MOS-gated SCR or thyristor structures, and even though an IGR may be considered as including a parasitic SCR. Significantly, in the normal operation of an IGR, the gate electrode maintains both turn-on and turn-off control of current flow through the device, and the parasitic SCR is not permitted to latch into a conducting state. There are various methods by which the parasitic SCR inherent in an IGR structure can be inhibited from operating, which would undesirably latch the IGR into a conducting state with consequent loss of gate control. A primary approach, and one which is described in the above-identified Baliga application P 31 47 075.0, is to employ in the IGR a relatively high cathode shorting density relative to the cathode shorting density which would be employed in an SCR structure. In an IGR, this cathode shorting density is sufficiently high such that the current gain of the upper NPN transistor of the two-transistor analogue mentioned above is maintained at a low-enough value such that regenerative turn-on action of the device is prevented. Alternatively, the cathode shorting density may be viewed as having the effect of preventing the PN junction between the P base region and the Ns cathode region from becoming forward biased to the point where a strong injection of carriers occurs from the N+ conductivity type cathode into the P base region. Nevertheless, in an IGR, there is a tendency for the parasitic SCR to latch on (resulting in loss of gate control) as current through the device is increased. This phenomenon is analyzed in detail in commonly-assigned #Eurc#ear± a#licatiai 83103501.9,filed April 111 1983 by B.J. Baliga, P.V. Gray, and R.P. Love and entitled "SEMICONDUCTOR DEVICE HAVING A DIFFUSED REGION OF REDUCED LENGTH AND METHOD OF FABRICATING THE SAME", and in commonly-assigned European agplicaticn 83103196.8, filed March 31, 1983, by M.S. Adler and B.J. Baliga, and entitled "INSULATED GATE RECTIFIER WITH IMPROVED CURRENT-CARRYING CAPABILITY". Various structures, which are alternatives to cathode shorts, are disclosed in these applications EP 83103501 9 and EP 83103196.8. In pertinent summAry, structurally, there can be a fine line between a MOS-gated SCR and an IGR, depending upon the effectiveness of the measures taken to inhibit turn-on of the parasitic SCR. The factors leading to turn-on of the SCR increase as current flow through the device occurs which, in the normal operation of an IGR, results in the device having a maximum current rating which must not be exceeded if latch-on of the device is to be avoided. Also, as will be appreciated by those skilled in the art, conventional SCRs are characterized by a holding current rating, which is a minimum current which must be maintained through the device in order to sustain the regenerative switching mechanism. Up to this point, the background description herein has been concerned with specific types of semiconductor power switching devices. However, also relevant in the context of the present invention are the characteristics of specific circuits in which these devices are usefully employed. More particularly, there is one type of circuit including a general class of load devices characterized by drawing a relatively higher inrush current when initially energized, and a relatively lower operating current thereafter. A typical example of such a load device is a filament, such as an incandescent lamp filament, a discharge lamp filament, or even a vacuum tube filament. As a typical numerical example applying to a specific discharge lamp filament, upon initial turn-on, a filament current in the order of 10 amperes must be handled by the power switch. As the filament heats up, its electrical resistance increases by 20 times, and the current drops to a level of 0.5 amperes. In one specific lamp control circuit, in order to control filament power at this point the power device must operate in the gate turn-off node at switching frequencies up to SO kHz. It has previously been suggested for this application to employ two separate devices, a MOSFET and an SCR connected in parallel. In this suggested approach, the SCR is used initially to carry the 10 amperes of filament current. When the filament heats up, the current drops to less than one ampere. At this point, the MOSFET is turned on. If the SCR is designed with a holding current rating of one ampere, the SCR will now turn off and the MOSFET can be then used to achieve the high frequency switching. In accordance with the present invention, there are provided approaches which combine both an SCR and a high frequency power switching device into a single semiconductor chip. i 0E TEE INVENTION Accordingly, it is an object of the invention to provide a single semiconductor device advantageously combining the current-carrying capabilities of an SCE with the high speed switching capabilities of another type of semiconductor device. It is a related object of the invention to employ a single device in the place of two devices previously employed, thereby reducing the overall cost of semiconductor chips and packages, as well as simplifying gate drive circuitry. Briefly stated, and in accordance with one- overall concept of the invention, it is recognized that an IGR structure can be specially designed, through choice of appropriate structure such as cathode shorting density, to allow latch on of the integral SCR at a much lower device current than would be the case with previous IGR structures. Thus, in the circuit summarized above, the SCR (corresponding to what is normally viewed as a 1parasitic1 SCR in an IGR) handles the initial filament current. With the cathode shorting density designed such that the SCR holding current is about one ampere, when the filament current drops below one ampere, the SCR stops conducting, and the IGR portion of the device then carries the high frequency switching current. It will be appreciated that, during the high frequency switching operation, thermal inertia of the filament prevents it fror being cooled appreciably during the momentary "off" periods. Briefly, and in accordance with a more particular aspect of the invention, an IGR/SCR hybrid power switching semiconductor device is provided which is characterized by predetermined operating current range extending from zero current up to a maximum current, and by a mode crossover current point within the operating current range. Structurally, the device is comparable to previously-disclosed IGR structures except, rather than the very high cathode shorting densities of previous IGR structures, an intermediate cathode shorting density is provided, allowing latch-up of the integral SCR at currents exceeding the mode crossover current point. Structurally, this form of device comprises a body of semiconductor material including, in succession therein, anode, first base, second base, and cathode regions of alternate conductivity type. The cathode and first base regions are, for example, of N conductivity type, and the anode and second base regions are then, for example, of P conductivity type. The body also has a channel portion defined within the second base (P base) region. The channel portion extends into the P base region from a channel surface contiguous with a surface of the body. The cathode and first base (N base) regions are spaced from each other and define the extent of the channel portion therebetween. An insulated gate electrode is provided over the channel surface and configured for inducing in the channel portion, when gate voltage is applied thereto, a conduction channel of N conductivity type extending between the N+ cathode region and the first base (N base) region. The various regions of the device are configured and arranged such that, for operating currents below the mode crossover current point, the device functions as an insulated gate rectifier, with the gate maintaining both turn-on and turn-off control. At such operating currents below the mode crossover current point, the first base region (N base) functions as an active base region, but the second base region (P base) functions primarily as a shield base region. For operating currents above the mode crossover current point, the device functions as t four-layer PNPN thyristor device which latches into a conduction mode once triggered by voltage applied to the insulated gate electrode. Thus, the mode crossover current point corresponds to the holding current rating of the parasitic PNPN thyristor structure included within the IGR structure. While a variety of structural techniques may be employed, a preferred technique for determining the mode crossover point is by controlling the cathode shorting density, i.e., by controlling the contact area of a cathode electrode with the second base region relative to the overall cathode terminal electrode contact area. Briefly, and in accordance with another aspect of the invention, an electrical circuit comprises an electrical load device, such as a lamp filament, of the type which draws a relatively higher inrush current when initially energized, and a relatively lower operating current thereafter. Electrically connected to the electrical load device for controlling energization thereof is an insulated-gate rectifier of the type including a parasitic PNPN thyristor structure. The parasitic thyristor structure has a holding current rating, and the insulated-gate rectifier is configured and arranged such that the holding current rating is less than the inrush current of the load device and greater than the gate-controlled operating current of the load device. More particularly, the insulated gate rectifier has a pair of main terminals and a control gate terminal, and the main terminals are electrically connected to the electrical load device for controlling energization thereof. When the relatively higher inrush current flows through the insulated-gate rectifier, the parasitic PNPN thyristor is latched into a conducting state uncontrollable by means of the control gate terminal. When the relatively lower operating current flows, the parasitic PNPN thyristor is not latched into a conducting state, whereby conduction through the insulated gate rectifier is controllable by means of the control gate terminal. In accordance with the invention there is also provided a method for operating an insulated-gate rectifier of the type including a parasitic PNPN thyristor structure having a holding current rating. The method includes the steps of selectively operating the insulated-gate rectifier as an insulated-gate-triggered thyristor at operating currents equal to or in excess of the holding current, and as a gate-controlled insulated-gate rectifier at operating current levels less than the holding current. More particularly, the method of the invention contemplates employing the insulated-gate rectifier to control energization of an electrical load device of the type, such as a lamp filament, which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter, and wherein the inrush current is at least as great as the holding current rating of the parasitic PNPN thyristor structure, and the gate-controlled operating current is less than the holding current rating of the parasitic PNPN thyristor structure. For operating frequencies in excess of 100 kHz, the approximate upper limit for an IGR, a faster hybrid device is required. Accordingly, the invention provides further forms of hybrid device which combine, in a single integrated device, an SCR structure and a MOSFET structure. Briefly, and in accordance with a second overall concept of invention, a MOSFET and an MOS-gated SCR are simultaneously fabricated on a single chip within the same active device area. In essence a single power switchi ng semiconductor switching hybrid device results, but with separate MOSFET and SCR portions. The MOSFET and SCR portions are formed within a common guard ring termination, thus resulting in less usage of chip area. The fabrication of the two portions of device is completely compatible. Two specific embodiments of hybrid device in accordance with the second overall concept of the invention are provided. In one such specific embodiment, an N+ conductivity type buried layer significantly is included only in the MOSFET portion of the device, and serves to avoid bipolar action during the high frequency switching. More particularly, an insulatedgate field-effect trans istor/insulated-gate-triggered thyristor hybrid power switching semiconductor device comprises a body of semiconductor material including both a field-effect transistor portion (e.g. a MOSFET portion) and a thyristor portion (e.g. an SCR portion). The body has first and second (e.g. lower and upper) opposed principal surfaces on opposite sides of the body. The body includes a first base layer of one conductivity type, for example, an N base (lightly- doped to N conductivity type) layer. The first base layer has a first portion which is included in the field-effect transistor portion, this first base layer first portion comprising a field-effect transistor drift region. The first base layer also has a second portion which is included in the thyristor portion, this first base layer second portion comprising an active-base region of a thyristor. The body also includes a first main terminal region layer heavily doped to the opposite conductivity type, for example, a P anode region layer. This first main terminal region layer is common to both the field-effect transistor and the thyristor portions. However, the first main terminal region layer is contiguous with the first base layer second portion only within the thyristor portion. The first main terminal region layer extends to the first principal surface, and there contacts anode electrode metallization. Included only in the field-effect transistor portion between the first base region layer first portion and the first main terminal region layer is a buried layer heavily doped to the one conductivity type, e.g., an N+ buried layer. The buried layer is not included within the thyristor portion between the first base layer second portion and the first main terminal region i.e., where the first main terminal region layer and the first base layer second portion are contiguous. This N+ buried layer has the significant function of maintaining unipolar conduction in the field-effect transistor portion of the hybrid power switching semiconductor device, While permitting bipolar conduction in the thyristor portion of the device. In effect, the N+ buried layer underlying the first base layer first portion comprising a field-effect transistor drift region during operation prevents the injection of holes from the P+ conductivity type anode region into the first base layer first portion. Since both the P+ anode region layer and the N+ buried layer are heavily-doped, their interface is essentially a tunnel junction having substantially ohmic conduction characteristics. Since the N buried layer does not underlie the first base layer second portion comprising a thyristor active-base region, there is a PN junction between the anode region layer and the N first base layer second portion allowing, during operation of the device, injection of holes from the P+ anode into the N base whereby the first base layer second portion is free to function as a thyristor active-base region. Also included in the semiconductor body are second base region first and second portions of the opposite conductivity type, e.g., P base regions. The second base region first portion is included in the field-effect transistor portion, is contiguous with the first base layer first portion, and comprises a field-effect transistor shield-base region. The second base-region second portion is included in the thyristor portion, is contiguous with the first base layer second portion, and comprises a thyristor active-base region. These second base regions first and second portions may comprise portions of either the same second base region, or of individual island-like second base regions spaced from each other within the first base layer. The body also includes second main terminal region first and second portions of the one conductivity type, e.g. a MOSFET N+ source region and an SCR ° cathode region. The second main terminal region first portion is included in the field-effect transistor portion contiguous with the second base region first portion, and the second main terminal region second portion is included in the thyristor portion contiguous with the second base region second portion. First and second channel portions are also included. More specifically, the first channel portion is included in the field-effect transistor portion within the second base region first portion and extends into the first base region first portion from a first channel surface contiguous with a surface of the body. The second main terminal region first portion and the first base layer (N base) first portion are spaced to define the extent of the first channel portion therebetween. The second channel portion is similar, but is included in the thyristor portion within the second base region second portion and extends into the second base region second portion from a second channel surface also contiguous with the surface of the body. The second main terminal region second portion and the first base layer (N base) second portion are spaced to define the extent of the second channel portion therebetween. In a hybrid semiconductor device fabricated employing double-diffused MOS (DMOS) fabrication technology, both the first and second channel surfaces are contiguous with the second principal surface of the body. Alternative fabrication techniques may also be employed, as a result of which the first and second channel surfaces are contiguous with body surfaces which are not principal surfaces. One example is the device fabricated employing "V-groove" MOS (VMOs) fabrication techniques, wherein the channel surfaces are along the sides of a V-groove extending all the way through a second base (P base) region and into the first base (Er base) layer. To complete the structure of the hybrid semiconductor device, first and second insulated gate electrodes are respectively disposed over the first and second channel surfaces. The first gate electrode is configured for inducing in the first channel portion, when gate voltage is applied thereto, a fieldeffect transistor conduction channel of the one conductivity type (N channel type) extending between the N+ second main terminal region first portion and the first base layer (N base) first portion, all included within the MOSFET portion of the semiconductor body. The second gate electrode is similarly configured for inducing in the second channel portion, when gate voltage is applied thereto, a thyristor conduction-triggering. depletion region to trigger the thyristor portion of the device into conduction. In another specific embodiment in accordance with the second overall concept of the invention, the above-sunnnarized N+ conductivity type buried layer is not included. Rather, separate MOSFET and SCR portions are defined within the overall device by providing a first main terminal ¯region layer which has two portions of different conductivity types. Both portions of the first main terminal region layer extend to the first principal surface to contact anode electrode metallization. The other regions of the overall device are essentially the same as briefly described just above, i.e., the N base layer, the P base regions, the terminal region portions, the channel portions, and the insulated gate electrode More particularly, in this other specific embodiment, included in the field-effect transistor portion of the hybrid device is a first main terminal region layer first portion heavily-doped to the one conductivity type, for example, an N+ MOSFET drain electrode region. This Ns first main terminal region layer first portion is contiguous with the N first base layer first portion and extends to the device first principal surface to contact anode electrode metallization. Thus, unipolar conduction is maintained in the field-effect transistor portion of the device. Included in the thyristor portion of the hybrid device is a first main terminal region layer second portion heavilydoped to the opposite conductivity type, in this example a P+ thyristor anode region. This P+ first main terminal region layer second portion is contiguous with the N first base layer second portion and extends to the device first principal surface to also contact the anode electrode metallization, which therefore is common to both the thyristor portions of the device. Thus a four-layer PNPN structure is defined within the thyristor portion of the device. BRIEF DESCRIPTION OF THE DRAWINGS While the novel features of the invention are set forth with particularity in the appended claims, the invention, both as to organization and content, will be better understood and appreciated from the following detailed description taken in conjunction with the drawings, in which: FIG. 1 is a highly-schematic sectioned isometric view of an IGR/SCR hybrid power switching semiconductor device in accordance with the invention, connected in a circuit also embodying the invention; FIG. 2 is a highly-schematic sectioned isometric view of one embodiment of a MOSFET/SCR hybrid power switching semiconductor device in accordance with the invention: and FIG. 3 is a similar isometric view of another embodiment of a MOSFET/SCR hybrid power switching semiconductor device in accordance with the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. l, depicted in highlyschematic form is an IGR/SCR hybrid power switching semiconductor device, generally designated lO, included within an electrical circuit 12 comprising, in addition to the device 10, an electrical load device 14, a DC power source represented at 16, and suitable gate drive circuitry 18 for the semiconductor device 10. The hybrid device TO is fabricated, for purposes of example, as a vertical-channel device employing double-diffused metal-oxide-semiconductor (DEMOS) technology. It will be appreciated, however, that other forms of device may be fabricated, for example, employing tV"-groove MOS (vMOS) technology. Further descriptions of DMOS and VMOS structures are found in S.M. Sze, Physics of Semiconductor Devices, second edition, John Wiley & Sons, Inc., publisher, 1981, pages 489, 490, 494 and 495. In structural overview, the hybrid device 10 of FIG. 1 resembles an insulated-gate rectifier such as is disclosed in the above-cited Baliga application P 31 47 O75.Ot However, there is a significant difference in the result of the measures taken to inhibit operation of the parasitic SCR included within the device structure, although the structural differences are somewhat subtle. It will be appreciated, since FIG,. 1 is a highly schematic representation, not to scale, that the geometrical differences are not necessarily readily apparent from the drawing. However, the required structure will be well apparent to those skilled in the art in view of the functional requirements stated herein. In detail, the hybrid device 10 of FIG. 1 includes a body 20 of semiconductor material, such as silicon, including in series, a P+ anode region 22 (highly-doped to P conductivity type), a first or N base region 24 (lightly-doped to N conductivity type), a second or P base region 26 (doped to a reference concentration with P conductivity type impurities), and an WI cathode region 28 (highly-doped to N conductivity type). As shown, preferably the device 10 includes a plurality of individual unit cells 21, all of which share common anode 22 and first base (N base) regions 24, but which have individual second base (P base) 26 and N+ cathode 28 regions. For convenience, and clarity, the structure of only one of the identical unit cells 21, cell 21', is described herein. The body 20 has at least one channel surface 30 which in the illustrated embodiment, is coextensive with the upper principal surface 32 of the body 22. This channel surface 30 may be provided by means of conventional DMOS fabrication technology. At least a portion of the second base (P base) region 26 is adjacent to the channel surface 30, and the cathode region 28 anç the first base (N- base) region 24 are spaced from each other to define a channel portion 34 within and extending into the second base region 26 from the channel surface 30. Positioned over the channel surface 30 is an insulated gate electrode 36 configured for inducing in the channel portion 34, when gate voltage is applied, an N conductivity type conduction channel extending between the N+ cathode region 28 and the first base (N base) region 24. The gate electrode 36 is insulated from the semiconductor body 20 by being encased within an insulating oxide layer 38, for example of silicon dioxide. The gate electrode 36 may, for example, comprise aluminum or highly-doped polycrystalline silicon of either conductivity type, as is known in the art. The gate electrode 36 is electrically connected to a device gate terminal, represented at 40, by any one of various techniques known to those skilled in the art. One representative example is a remote gate contact terminal formed by etching through the oxide layer 38 to the upper surface of the conductive gate electrode layer 36 to apply a metal contact. The gate electrode 36 and encasing oxide 38 cover substantially the entire device surface 32, except where windows are provided for cathode metallization, described next below. The device 10 has two main terminals, a device cathode terminal 42 and a device anode terminal 44, both shown in schematic form. The device cathode terminal 42 is connected to a device terminal electrode 46 comprising metallization, for example aluminum, applied to essentially the entire upper surface of the device (except where there are remote gate contact terminals) and contacting the cathode region 28, forming an dEmic contact therewith. The cathode metallization 46 is prevented from contacting the first base region 24 of N conductivity type and from contacting the gate electrode 36 by virtue of the encasing oxide 38. The device anode terminal 44 is electrically connected to an anode terminal electrode 48 in ohmic contact with the device anode region 22 on the lower device principal surface 50. It will be appreciated that the illustrated electrode arrangement, as well as the surface 32 geometry, is exemplary only, and that numerous alternative arrangements may be employed. As one example, a more complicated metallization pattern may be employed, with the gate electrode directly metallized, and separate patterned metallization areas for the cathode electrode 46. In order to provide cathode shorts, a shorting extension 52 of the P conductivity type second base region 26 extends upward to the principal surface 32, in contact with the cathode metallization 46. An important aspect of the invention is the control of cathode shorting density, which is determined in part by the contact area of the cathode electrode metallization 46 with the second base region 26 relative to the overall cathode terminal electrode contact area including the contact area with the N+ cathode region 28. It will be appreciated that the FIG. 1 device structure 10 can have the characteristics of either an IGR or an SCR, depending upon the level of forward current flow through the device 10 and depending upon the measures taken to inhibit operation of the included parasitic SCR structure. Various such measures are discussed in the above-cited commonly-assigned DE and EP applications the entire disclosures of which are hereby incorporated by reference herein. In brief summary, and as mentioned above, it is well known that a four-layer PNPN thyristor structure may be represented by a two-transistor analogue comprising an upper NPN transistor and d lower PNP transistor, with the base of the NPN transistor connected to (and comprising the same region as) the collector of the PNP transistor, and the base of the PNP transistor corresponding to (and comprising the same device region as) the collector of the NPN transistor. Each of these two transistors is characterized by having a common-base current gain and the overall device becomes regenerative, i.e. latches into a conducting state, when the sum of the two current gains exceeds unity. If the sum of these two common base current gains is less than unity, then the device is not regenerative. Accordingly, in previous SCR device structures, the sum of the two common-base current gains exceeds unity, and the SCRs are therefore regenerative. In previously-disclosed I6R structures such regeneration is undesired, and the characteristics of the two transistors of the analogue are controlled such that the sum of their common-base current gains is less than unity. Moreover, as is well known, the common-base current gains of both the upper NPN and the PNP transistors in the two-transistor analogue increase with increasing device current, and decrease with decreasing device current. It is for this reason that conventional SCRs have a certain holding current rating below which the device is no longer regenerative and the device turns off. Further, this is the general reason that previously-proposed IGR structures have a maximum current rating, above which the parasitic SCR undesirably latches into conduction. Various techniques for controlling and minimizing this effect have previously been disclosed, as summarized in the various United States patent applications cited above. In accordance with the present invention, it is recognized that a useful device structure may be provided by controlling the configuration of the various regions of the device 10, through any suitable technique or conibination of techniques, such that the device 10 behaves as an IGR for operating currents extending from zero current up to a mode crossover current point, and behaves as an SCR for operating currents extending from the mode crossover current point up to a device maximum current range. A typical mode crossover point is one ampere. Significantly, the mode crossover current point is within the device intended operating current range, rather than being at one end or the other. In an SCR, the current below which the device is no longer regenerative, i.e., the holding current, determines the lower end of the device operating current range. In an IGR, the current above which the device undesirably latches into a conducting mode whereby gate control is lost determines the upper end of the device operating current range. To represent the dual nature of the hybrid device 10, an IGR section 54 and an SCR section 56 are shown in FIG. 1. In the 1GR section 54, conduction occurs through the channel portion 34. In the SCR section 56, conduction occurs through the P conductivity type base region 26. More particularly, during the IGR mode of operation, the device 10 supports forward conduction when a positive gate voltage is applied on the gate electrode 36 to induce, through inversion, an N type conduction channel in the channel portion 34 between the N+ cathode region 2B and the N first base region 24. During this mode of operation, electrons from the cathode region 28 are injected via the induced conduction channel 34 into the N conductivity type first base region 24. At the same time, holes are injected from the P+ anode region 22 into the N first base region 24. These electrons and holes recombine in the N first base region 24 in a bipolar conduction mode. Thus, while the N first base region 24 functions as an active-base region, the second base region 26 does not, and serves only as a shield-base region. Thus, the IGR section represented at 54 actively functions. To turn off the device 10 in its IGR mode, positive gate voltage is removed from the gate electrode 36, and the conduction channel 34 is no longer induced. At this point, the device 10 no longer sustains conduction. At higher currents, that is, above the mode crossover current point, the SCE section represented at 56 actively functions as a MOS-gated SCR, which latches into a conduction mode in which gate control is lost. While the SCR mode of operation may be explained in various ways, one way in which the operation of the device 10 in its SCR mode of operation may be explained is as follows- When a positive gate voltage is applied via the gate electrode 36, an electric field across the gate insulating layer 38 produces-a depletion of carriers in the P conductivity type second base region 26 under the gate electrode 36. As a result, the depletion layer in the P conductivity type base region 26 extends closer to the N+ conductivity type cathode region 38 under the gate 36. This reduces the thickness under the gate electrode 36 of the undepleted P conductivity type base region 26 of the upper NPN transistor of the two-transistor analogue, and thus increases its current gain. In the MOS-gated thyristor, as the gate bias is increased, the common-base current gain of the upper NPN transistor increases until the sum of the common-base current gains of the upper NPN and the lower PNP transistors exceeds unity. At this point, strong injection of carriers occurs from the Ns cathode region 28 into the P conductivity type base region 26, and the device switches to the ON state. Once this takes place, removal of gate bias voltage will not cause the device 10 to return to the blocking state because of the self-sustaining regenerative action inherent in the PNPN thyristor structure. It will be appreciated that, during this SCR mode of operation, both the N conductivity type first base region 26 and the P conductivity type second base region 26 function as active base regions, supporting bipolar conduction. There are various methods by which the different regions of the device 10 may be configured such that operation occurs as described above. Preferably, this result is achieved through control of the cathode shorting density. In previous IGR structures, the N+ cathode regions 28 are relatively small, and a a consequently relatively large area of the shorting extension 52 of the P conductivity type second base region 26 is therefore in contact with the cathode metallization 46 for a relatively high cathode shorting density. In previous SCR structures, a relatively low cathode shorting density is employed (with relatively larger cathode regions 28) only to the extent necessary to achieve the desired dV/dt characteristic. In accordance with the present invention, an intermediate value of cathode shorting density is employed, as will be well appreciated by those skilled in the art. Although the FIG. 1 device 10 is depicted as a basic vertical-channel device fabricated enploying DMOS technology, it will be appreciated that a satiety of other device configurations may be employed, and the configuration of FIG. 1 is for representative purposes only. As another variation, to increase turn-off speed, it will be appreciated that anode shorts may also be employed, which are omitted from FIG. 1 for clarity of illustration. "Anode shorts " are shorts between the device P+ ; anode region 22 and the adjacent N base region 24, and can be implemented by downward shorting extensions (not shown) of the N base 24, in contact with the anode metallization 48. Anode shorts aid in improving turn-off speed of an IGR (as well as of an SCR) due to the bipolar conduction mode. In particular, during conduction in an IGR or SCR, there are excess electrons and holes in the N conductivity type first base region 24, which functions as an active-base region. Upon device turn-off, these electrons and holes are momentarily trapped in the N base region 24, prolonging device conduction and therefore degrading turn-off speed. Excess holes in the N base region 24 exit towards the cathode electrode 46 through the P conductivity type base region 26. However, in the absence of anode short, there is no similar path for excess electrons in the I N base region 24. The inclusion of anode shorts overcomes this particular difficulty. Suitable anode short structures are described in the above-identified Baliga Application P 31.47 075.W A structural alternative to conventional anode shorts is disclosed in commonly-assignedEurcp. Patent Application a2108864.8, filed Septeniber 24,1982,by B.J. Baliga and entitled ZSEMICOKDUCTOR DEVICE HAVING RAPID REMOVAL OF MAJORITY CARRIERS FROM AN ACTIVE BASE REGION THEREOF AT DEVICE TURN-OFF AND METHOD OF FABRICATING THIS DEVICE". In the structure disclosed in Europ. Application B2108864.a, highly-doped Ns or diffusions are interspersed within the P+ anode region, which similarly enables the rapid removal of excess electrons in the N conductivity type base region 24 upon device turn-off. considering now the overall circuit 12 of FIG. 1, the electrical load device 14 is of the type which draws a relatively higher inrush current when initially energized, and a relatively lower operating current thereafter. While various load devices have this particular characteristic, for purposes of example the load device 14 of FIG. 1 is the filament of a discharge type lamp. In accordance with the invention, the hybrid semiconductor switching device 10 included in the circuit 12 includes a parasitic PNPS thyristor structure, as described above, characterized by a holding current rating, and this holding current rating is less than the inrush current of the electrical device 14 and greater than the operating current of the load device 14. Thus, in operation, upon initial turn-on the SCR section 56 of the device 10 is initially activated, to supply the load 14 inrush current. Thereafter, at the relatively low operating current ranges, the IGR section 54 of the device 10 takes over, for high-speed duty cycle controlled switching to provide desired control over the energization of the load device 14. The switching frequency can be up to the maximum operating frequency of an IGR, which is presently in the order of 100 kHz. As stated above, there are certain situations in which an IGR has insufficient switching speed, and a faster switching device, such as a MOSFET, is required. In accordance with the invention, a second form of hybrid device is provided which solves this problem. One embodiment is described below with reference to FIG. 2, and another embodiment is described with reference to FIG. 3. Referring to FIG. 2, depicted is a second form of hybrid power switching semiconductor device 110 including a MOSFET portion, generally designated 112, and an SCR portion, generally designated 114, on the same semiconductor chip. It will be appreciated that the MOSFET portion 112 may more generically be described as an insulated-gate field effect transistor, and that the the SCR portion 114 more generically may be described as an insulated-gate-triggered thyristor In general, the FIG. 2 device 110 is annular, although different device geometries may be employed. In contrast to the FIG. 1 device 10 wherein the IGR and SCR structures are overlapping to the point where they are not readily distinguishable from the schematic depiction alone, in the hybrid device 110 of FIG. 2 the MOSFET portion 112 and the SCR portion 114 comprise separate, definable portions of the overall device 110, although, as will be appreciated from the detailed description hereinafter, a number of elements are common to the overall hybrid device 110. Illustratively, the MOSFET portion 112 comprises a plurality of smaller unit cells of rectangular surface geometry, while the SCR portion 114 comprises a single large cell in center of the device 110. Considering the device 110 in detail, such device comprises a body 116 of semiconductor material, such as silicon, having first and second (e.g. lower and upper) opposed principal surfaces 118 and 120 on opposite sides of the body 116. Between the principal surfaces 118 and 120 the body 116 has separate MOSFET and SCR portions corresponding to the MOSFET and SCR portions 112 and 114 of the device 110. For convenience and clarity, these same reference numerals 112 and 114 are employed herein to designate these same portions within the semiconductor body 116. The body 116 includes a first base layer 122 of one conductivity type, for example, an N base layer. The first base layer 122 in turn has a first portion 124 included in the MOSFET portion 112, and a second portion 126 included in the SCR portion 114. In the overall device 110, the N first base layer 122 first portion 124 comprises an N drift region of a MOSFET, and the N first base layer 122 second portion 126 comprises an N active-base region of an SCR. The body 116 additionally includes a first main terminal region layer 128 heavily-doped to the opposite conductivity type, for example, a P+ device anode region 128 extending to the first (lower) principal surface 118 in ohmic contact with anode electrode metallization 130. The P anode region 128 is common to both the MOSFET portion 112 and the SCR portion 114. Within the SCR portion 114, the Pf anode layer 128 is contiguous with the N first base layer 122 second portion 126 at an interface 131. Comparing this particular structure to a conventional SCR or to a MOS-gated SCR, this interface 131 corresponds to the PN junction between an SCR anode region and the adjacent N base region. During device operation, holes are injected from the P+ anode 128 into the N first base layer 122 second portion 126, allowing this second portion 126 to function as an SCR active-base region. However, and in accordance with a significant aspect of the invention, within the MOSFET portion 112 the P+ anode region 128 is not contiguous with the N bÅase 122 first portion 124. Rather, a heavily-doped buried layer 132 of the one conductivity type, e.g., an N+ buried layer 132, is included in the MOSFET portion 112 of the body 116 between the N first base layer 122 first portion 124 and the P+ anode region 128. The N buried layer 132 is not included within the SCR portion 114. In the device structure illustrated, the Nf buried layer 132 is annular, and, during device 110 operation, prevents the injection of holes from the P+ anode region 128 into the N first base layer 122 first portion 124, thereby preventing the accumulation of excess charge carriers in this first portion 124, preserving its character as a MOSFET N- drift region. Since both the P+ anode region 128 and the buried layer 132 are heavily doped, the junction at their interface 134 is essentially a tunnel junction across which conduction readily occurs by means of a tunnelling mechanism as is known in the art. The connection is, therefore, essentially - - ohmic. The buried layer 132 can be formed by employing conventional techniques. For example, a typical fabrication process begins with the P+ anode layer 128 as a substrate. Appropriate impurities, i.e. dopant atoms, are introduced through a suitable mask (not shown) to define the location of the buried layer 132. Thereafter, the mask is removed, and the N first base layer 122, including both portions 124 and 126, is epitaxially grown over the P+ anode region 128 comprising the substrate. As depicted, the buried layer 132 extends slightly up into the N first base layer 122 first portion 124 due to autodoping during vapor phase epitaxial growth. In particular, during the initial stages of epitaxial growth to form the N first base layer 122, some of the N type dopant enters the gas phase, and is then deposited as part of the epitaxial layer. The body 116 additionally includes second base region first and second portions 136 and 138 of the opposite conductivity type, for example, P base region portions. The second base (P base) region first portion 136 is included within the MOSFET portion 112 of the semiconductor body 116 contiguous with the N- first base layer 122 first portion 124. This second base (P base) region first portion 136 comprises a MOSFET shield-base region. The second base (P base) region second portion 138 is included in the SCR portion 114 of the semiconductor body 116 and is contiguous with the N first base layer 122 second portion 126. The second base (P base) region second portion 138 comprises an SCR active base region. In structures embodying the invention, the second base (P base) region first and second portions 136 and 138 may comprise portions of the same second base region, such as the second base region 140, or may comprise individual island-like second base (P base) regions, such as exemplary second base (P base) regions 142 and 144. The exemplary second base region 142 is entirely within the MOSFET portion 112 of the semiconductor body 116 and includes second base region first portion, 136'. The exemplary second base region 144 is also within the MOSFET portion 112 of the semiconductor body 116, and includes second base region first portion 136''. In the particular device 110 embodiment illustrated, within the SCR portion 114 there is only the single second base (P base) region second portion 138, which comprises only a portion of the second base (P base) region 140, which second base region 140 is partly within the MOSFET portion 112 and partly within the SCR portion 114. Also included in the body 116 are second main terminal region first and second portions 146 and 148 of the one conductivity type, for example, a heavily-doped N+ device source region 146 in the case of the MOSFET portion 112 and heavily-doped N t device cathode regions 148 in the case of the SCR portion 114. More particularly, the N+ second main#terminal region first portion 146 comprising a MOSFET source is included in the MOSFET portion 112 of the body 116 and is contiguous with the second base (P base) region first portion 136. The N+ second main terminal region second portion 148 comprising an SCR cathode is included in the SCR.portion 114 contiguous with the second base (P base) region second portion 138. From the device structure illustrated, it will be appreciated that the N+ second main terminal region first and second portions 146 and 148 may be included either within the same second base region, such as the N+ second main terminal region first and second portions 146 and 148 included within the second base (P base) region 140. Alternatively, the N+ second main terminal region portions may be included in separate second base (P base) regions, such as the exemplary tv second main terminal region first portions 146' and 146'' included respectively in the second base (P base) regions 142 and 144, within the MOSFET portion 112 of the semiconductor body 116. Also included in the body 116 are first and second channel portions 150 and 152. More particularly, the first channel portion 150 is included in the MOSFET portion 112 of the semiconductor body 116 within the second base (P base) region first portion 136, and the second channel portion 152 is included in the SCR portion 114 of the semiconductor body 116 within the second base (P base) region second portion 138. considering the first channel portion 150 in greater detail, this first channel portion 150 comprises the controllable conduction channel of a MOSFET and extends into the second base (P base) region first portion 136 from a first channel surface 154 contiguous with a surface of the body 116. In the illustrated embodiment, employing DMOS fabrication technology, the first channel surface 154 is contiguous with the second (upper) principal surface 120 of the body 116. The N+ second main terminal region first portion 146, serving as a MOSFET source region, and the N first base layer 122 first portion 124 are spaced from each other to define the extent of the first channel portion 150 therebetween. Also within the MOSFET portion 112, first channel portions 150' and l5O'' similarly extend into the second base (P base) regions 142 and 144 from additional first channel surfaces 154' and 154' '. Considering the second channel portion 152, the second channel portion 152 is included within the SCR portion 114 of the semiconductor body 116 and serves to support the depletion region which triggers conduction in an SCR. The second channel portion 152 extends from a second channel surface 156, also contiguous with a surface of the body l K, into the second base (P base) region second portion 138. The B'+ second main terminal region second portion 148 serving as an SCR cathode and the N first base layer 122 second portion 126 are spaced to define the extent of the second channel portion 152 therebetween. Although in the device 110 of FIG. 2, the first and second channel surfaces 154 and 156 are co-extensive with the second (upper) principal surface 120 of the semiconductor body 116 as in DMOS fabrication, it will be appreciated that variations are possible, such as in a VMOS form of device. Covering the upper principal surface 120 of the semiconductor body 116 is a gate electrode and cathode metallization structure, generally designated 158, and described in detail below. For convenience in depicting the upper principal surface 120 of the body 116, the gate electrode and cathode metallization structure is further broken away in the drawing to expose the upper surface 120. It will be appreciated, however, in the actual physical configuration of the device the structure 158 completely covers the upper surface 120 of the body 116. In detail, within the structure 158 the device 110 includes first and second insulated gate electrodes 160 and 162 disposed respectively over the first and second channel surfaces 154 and 156 respectively in the MOSFET portion 112 and the SCR portion 114 of the device 110. As in the device 10 of FIG. 1, the insulated gate electrodes 160 and 162 are insulated from the semiconductor body 116 by respective underlying (and encasing) gate oxide layers 164 and 166 which may comprise, for example, silicon dioxide or silicon nitride. The gate electrodes 160 and 162 themselves may, for example, comprise aluminum or highly-doped polycrystalline silicon of either conductivity type, as is known in the art. The gate electrodes 162 and 164 are connected to remote gate contact terminals (not shown) and, for a three-terminal device, are connected together to provide a single gate terminal (not shown). The first gate electrode 160, included in the MOSFET portion 112 of the device 110, is configured for inducing, through an inversion process, When gate voltage is applied thereto, an N conductivity type conduction channel in the first channel portion 150 extending between the N+ second main terminal region first portion 146 serving as a MOSFET source region and the N first base layer 122 first portion 124 serving as the N drift region of a MOSFET. The second gate electrode 162, included in the SCR portion 114 of the device 110, is similarly configured for forming, when gate voltage is applied thereto, a thyristor conduction-triggering depletion region in the channel portion 152 of the second base (P base) second portion 138. The MOSFET portion 112 of the device 110 includes a further first gate electrode 160' disposed over the first channel surfaces 154' and 15411. To complete the terminal structure of the device 110, device 110 cathode (or source) metallization 170 is provided at the second principal surface 120 in ohmic contact with the N+ source regions 146, 146' and 1461 1 in the MOSFET portion 112 of the device 110, and in ohmic contact with the N+ cathode regions 148 in the SCR portion 114 of the device. Consistent with the usual requirements for Nl source-to-P base shorts in power MOSFETs and for N cathode-to P base shorts in SCRs, shorting extensions 172, 174 and 176 of the second base (P base) regions 144, 142 and 140 are provided, also in ohmic contact with the device cathode (or source) metallization 170. As in the device 10 of FIG. 1, the cathode shorting density in the SCR portion 114 of the hybrid device 110 of FIG. 2 is controlled such that the SCR portion 114 has a predetermined holding current rating below which the SCR portion 114 is not regenerative but, at which, the MOSFET portion 112 is free to operate. In the device SCR portion 114 it will be appreciated that a four-layer PEPS structure characteristic of a thyristor is maintained. However, in the MOSFET portion 112 of the device the N+ buried layer l32 in ohmic contact with the P+ anode layer 128 prevents the injection of holes from the Pv anode region 128 into the N first base layer 122 first portion 124, thereby preventing the accumulation of excess of charge carriers in the portion 124, preserving the character of the portion 124 as a MOSFET N drift region. This accumulation, if it were allowed to occur, would be characteristic of an IGR, as summarized above, rather than of a MOSSET. To complete the structure of the device 112, a common guard ring 182 of P+ conductivity type encircles both the MOSFET portion 112 and the SCR portion 114 at the device second principal surface 120. Thus, less usage of chip area results, while usefully obtaining the characteristics of both an SCR and a MOSFET. Moreover, as will be appreciated, the fabrication of the two devices, that is, the MOSFET portion 112 and the SCR portion 114, is completely compatible. Referring finally to FIG. 3, depicted is another embodiment of a hybrid power switching semiconductor device 310 including a MOSFET portion, generally designated 312, and an SCR portion, generally designated 314, on the same semiconductor chip and formed within a common guard ring 382. The FIG. 3 hybrid device 310 has many similarities to the hybrid device 110 of FIG. 2 and accordingly, for convenience, the reference numerals employed in FIG. 3 correspond to those employed in FIG. 2 to designate corresponding device elements, but a "300" number series is employed in FIG. 3 rather than the "100" number series of FIG. 2. Further in view of the similarities of the FIG. 3 device 310 to the FIG. 2 device 110, the detailed device description is generally not being repeated. The primary difference between the hybrid device 310 of FIG. 3 and the hybrid device 110 of FIG. 2 is that the hybrid device 310 of FIG. 3 does not include the N+ buried layer 132 included within the MOSFET portion 112 of the FIG. 2 device. Rather, in the FIG. 3 device 310, a first main terminal region layer 390 has first and second portions 392 and 394 of different conductivity type. More particularly, the first main terminal region layer 390 first portion 392 is included only within the MOSFET portion 312 of the device 310, and is an N+ MOSFET drain electrode region. This N+ portion 392 is contiguous with the N first base layer 322 first portion 324 and extends to the first (lower) principal surface 318 in ohmic contact with device anode metallization 330. The second portion 394 of the first main terminal region layer 392 is a P+ anode region included within the SCR portion 314 of the device 310. This P+ anode region 394 is contiguous with the N first base layer 322 second portion 326 and also extends to the device 310 first (lower) principal surface 318 in ohmic contact with the device anode metallization 330. Thus, a MOSFET portion 312 and an SCR portion 314 comprise a single hybrid device 310 and are formed within the common guard ring termination 382. A single anode metallization layer 330 and a single cathode metallization layer 370 serve both the MOSFET portion 312 and the SCR portion 314 of the hybrid device 310. The FIG. 3 device 310 can be formed by employing conventional techniques. For example, a typical fabrication process begins with the entire semiconductor body 316 as a substrate and initially uniformly doped to N conductivity type as employed for the N- first base layer 322. Then, employing suitable processes, such as diffusion or ion implantation at both the first (lower) principal surface 318 and the second (upper) principal surface 320 of the body 316, the various device regions in addition to the N first base layer 322 are formed. For example, in separate masking and diffusion steps, the N+ region 392 and the P+ region 394 are introduced by diffusion into the body 316 at the first (lower) principal surface 318. Similarly, using double-diffusion techniques, the P conductivity type second base regions 340, 342 and 344, and the N+ cathode and source terminal regions 348, 346' and 346'' are introduced into the second (upper) principal surface 320 of the semiconductor body 316. The FIG. 3 device 310 operates in essentially the same manner as the FIG. 2 device 110. Within the MOSFET portion 312 of the device 310, a unipolar conduction mode is maintained, there being no mechanism for the injection of holes from the first main terminal region layer 390 N first portion 392 into the N first base layer 322 first portion 324. On the other hand, within the SCR portion 312 of the device 310, a four-layer PNPN structure characteristic of an SCR is defined, and, during forward device conduction, holes are injected from the first main terminal region layer 390 P+ second portion 394 into the N- first base layer 322 second portion 326. While specific edbodiments of the invention have been illustrated and described herein, it is realized that numerous modifications and changes will occur to those skilled in the art. For example, the invention applies to complementary devices, wherein P-type regions are used in place of the N-type regions described herein and vice versa. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims: CLAIMS 1. An IGR/SCR hybrid power switching semiconductor device having a predetermined operating current range extending from zero current up to a maximum current, and having a node crossover current point within the operating current range, said device comprising: a body of semiconductor material including, in succession therein, anode, first base, second base, and cathode regions, said cathode and first base regions being of one conductivity type, and the anode and second base regions being of opposite conductivity type; a channel portion within said second base region and extending into said second base region from a channel surface contiguous with a surface of said body, said cathode and first base regions being spaced from each other to define the extent of said channel portion therebetween; ; an insulated gate electrode over said channel surface configured for inducing in said channel portion, when gate voltage is applied thereto, a conduction channel of the one conductivity type extending between said cathode region and said first base region; a cathode terminal electrode contacting said cathode region; an anode terminal electrode contacting said anode region; ; said first and second base regions, said anode regions and said cathode region being configured and arranged such that, for operating currents below the mode crossover current point, said device functions as an insulated-gate rectifier which conduction in a forward direction when the conduction channel is induced and ceases to support forward conduction when the conduction channel is no longer induced, and such that, for operating currents above the mode crossover current point, said device functions as a thyristor which latches into a forward conduction mode once triggered by a voltage applied to said insulated gate electrode. 2. An IGR/SCR hybrid device in accordance with Claim 1, wherein said cathode terminal electrode additionally contacts said second base region to provide a cathode short between said cathode and second base regions, and the mode crossover current point is determined in part by the contact area of said cathode. electrode with said second base region relative to the overall cathode terminal electrode contact area. 3. An IGR/SCR hybrid device in accordance with Claim 2, wherein the contact area of said cathode electrode with said second base region relative to the overall cathode terminal electrode contact area is selected such that said mode crossover current point is in the order of one ampere. 4. An electrical circuit comprising: an electrical load device of the type which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter; and an insulated-gate rectifier of the type including a parasitic PNPN thyristor structure electrically connected to said electrical load device for controlling energization thereof: said parasitic PNP thyristor structure of said insulated-gate rectifier having a holding current rating, and said insulated-gate rectifier being configured and arranged such that the holding current rating is less than the inrush current of said load device and greater than the operating current of said load device. 5. An electrical circuit in accordance with Claim 4, wherein said electrical load device comprises a lamp filament. 6. An electrical circuit comprising: an electrical load device of the type which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter; and an insulated-gate rectifier having a pair of main terminals and a control gate terminal, and being of the type including a parasitic PNPN thyristor structure, the main terminals of said insulated-gate rectifier being electrically connected to said electrical load device for controlling energization thereof; ; said insulated-gate rectifier being configured and arranged such that, when the relatively higher inrush current flows through said insulated-gate rectifier, the parasitic PNPN thyristor is latched into a conducting state uncontrollable by means of the control gate terminal, and such that, when the relatively lower operating current flows through said insulated-gate rectifier, the parasitic PNPN thyristor is not latched into a conducting state, whereby conduction through said insulated-gate rectifier is controllable by means of the control gate terminal. 7. An electrical circuit in accordance with Claim 6, wherein said electrical load device comprises a lamp filament. 8. A method for operating an insulated-gate rectifier of the type including a parasitic PNPN thyristor structure having a holding current rating, said method comprising the steps of: selectively operating the insulated-gate rectifier as an insulated-gate-triggered thyristor at operating current leveIs equal to or in excess of the holding current rating; and selectively operating the insulated-gate rectifier as a gate-controlled insulated-gate rectifier at operating current levels less than the holding current rating. 9. A method in accordance with Claim 8, which comprises utilizing the insulated-gate rectifier to control energization of an electrical load device of the type which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter; the inrush current of the load device being at least as great as the holding current rating of the parasitic PNPN thyristor structure, and the operating current of the load device being less than the holding current rating of the parasitic PEPS thyristor structure. 10. A method in accordance with Claim 9, which comprises utilizing the insulated-gate rectifier to control energization of a lamp filament. 11. An IGFET/insulated-gate-triggered thyristor hybrid power switching semiconductor device comprising: a body of semiconductor material including a field-effect transistor portion and a thyristor portion, said body having first and second opposed principal surfaces on opposite sides of said body; a first base layer of one conductivity type, said first base layer having a first portion included in said fieldeffect transistor portion, said first base layer first portion comprising a drift region, and said first base layer having a second portion included in said thyristor portion, said first base layer second portion comprising an active-base region; ; a first main terminal region layer heavily-doped to the opposite conductivity type, said first main terminal region layer being common to both said field-effect transistor portion and said thyristor portion, said first main terminal region layer being contiguous with said first base layer second portion within said thyristor portion, and said first main terminal region layer extending to said first principal surface; a buried layer heavily-doped to the one conductivity type included in said field-effect transistor portion between said first base layer first portion and said first main terminal region layer, and not within said thyristor portion between said first base layer second portion and said first main terminal region; ; second base region first and second portions of the opposite conductivity type, said second base region first portion being included in said field-effect transistor portion contiguous with said first base layer first portion, said second base region first portion comprising a shield-base region, and said second fi base region second portion being included in said thyristor portion and contiguous with said first base layer second portion, said second base region second portion comprising an active-base region; ; second main terminal region first and second portions of the one conductivity type, said second main terminal region first portion being included in said field-effect transistor portion contiguous with said second base region first portion, and said second main terminal region second portion being included in said thyristor portion contiguous with said second base region second portion; ; first and second channel portions, said first channel 1 portion being included in said field-effect transistor portion within said second base region first portion, said second main terminal region first portion arid said first base layer first portion being spaced to define the extent of said first channel portion therebetween, and said second channel portion being included include in said thyristor portion within said second base region second portion, said second main terminal region second portion and And said first base layer second portion being spaced to define the extent of said second channel portion therebetween: and first and second gate electrodes respectively disposed over said first and second channel portions and insulatingly spaced therefrom, said first gate electrode configured for inducing in said first channel portion, when gate voltage is applied thereto, a conduction channel of the one conductivity type extending between said second main terminal region first portion and said first base layer first portion, and said second gate electrode similarly configured for inducing in said second channel portion, when gate voltage is applied thereto, a thyristor conduction-triggering depletion region. 12. A hybrid semiconductor device in accordance with Claim 11, wherein said second base region first and second portions respectively included in said field-effect transistor portion and in said thyristor portion comprise portions of the same second -base region. 13. A hybrid semiconductor device in accordance with Claim 11, wherein said second base region first and second portions respectively included in said field-effect transistor portion and in said thyristor portion comprise individual island-like second base regions spaced from each other within said first base layer. 14. A hybrid semiconductor device in accordance with Claim 11, wherein: said first base region is of N conductivity type; said second base region is of P conductivity type; said first main terminal region layer is of P conductivity type and comprises an anode region of said device: and said second main terminal region is of N conductivity type and comprises a cathode region of said device. 15. An IGFET/insulated-gate-triggered thyristor hybrid power switching semiconductor device comprising: a body of semiconductor material including a fieldeffect transistor portion and a thyristor portion, said body having first and second opposed principal surfaces on opposite sides of said body; a first base layer of one conductivity type, said first base layer having a first portion included in said fieldeffect transistor portion, said first base layer first portion comprising a drift region, and said first base layer having a second portion included in said thyristor portion, said first base layer second portion comprising an active-base region; ; a first main terminal region layer first portion heavily-doped to the one conductivity type included in said field-effect transistor portion, said first main terminal region first portion being contiguous with said first base layer first portion within said field-effect transistor portion and extending to said first principal surface; a first main terminal region layer second portion heavily-doped to the opposite conductivity type included in said thyristor portion, said first main terminal region layer second portion being contiguous with said first base layer second portion within said thyristor portion and extending to said first principal surface; ; second base region first and second portions of the opposite conductivity type, said second base region first portion being included in said field-effect transistor portion contiguous with said first base layer first portion, said second base region first portion comprising a shield-base region, and said second base region second portion being included in said thyristor portion and contiguous with said first base layer second portion, said second base region second portion comprising an active-base region; ; second main terminal region first and second portions of the one conductivity type, said second main terminal region first portion being included in said field-effect transistor portion contiguous with said second base region first portion, and said second main terminal region second portion being included in said thyristor portion contiguous with said second base region second portion; ; first and second channel portions, said first channel portion being included in said field-effect transistor portion within said second base region first portion, said second main terminal region first portion and said first base layer first portion being spaced to define the extent of said first channel portion therebetween, and said second channel portion being included in said thyristor portion within said second base region second portion, said second main terminal region second portion and said first base layer second portion being spaced to define the extent of said second channel portion therebetween: and first and second gate electrodes respectively disposed over said first and second channel portions and insulatingly spaced therefrom, said first gate electrode configured for inducing in said first channel portion, when gate voltage is applied thereto, a conduction channel of the one conductivity type extending between said second main terminal region first portion and said first base layer first portion, and said second gate electrode similarly configured for inducing in said second channel portion, when gate voltage is applied thereto, a thyristor conduction-triggering depletion region. 16. A hybrid semiconductor device in accordance with Claim 15, wherein said second base region first and second portions respectively included in said field-effect transistor portion and in said thyristor portion comprise portions of'the same second base region. 17. A hybrid semiconductor device in accordance with Claim 15, wherein said second base region first and second portions respectively included in said field-effect transistor portion and in said thyristor portion comprise individual island-like second base regions spaced from each other within said first base layer. 18. A hybrid semiconductor device in accordance with Claim 11, wherein: said first base region is of N conductivity type; said second base region is of P conductivity type; said first main terminal region layer is of P conductivity type and comprises an anode region of said device; and said second main terminal is of N conductivity type and comprises a cathode region of said device.

Inventors: BALIGA, BANTVAL JAYANT
Applicants: GENERAL ELECTRIC COMPANY
Application year: 1984
Main classification: H01L29
IPC codes: H01L29