SEMICONDUCTOR MEMORY DEVICE

Abstract: In a semiconductor memory device wherein a plurality of word lines and a plurality of bit lines (BL) are arranged perpendicular to each other, memory cells are located at the cross positions between each word line and each bit line, and one of the bit lines is selected by the operation of a bit line selection transistor driven with the signal of a column decoder via column selection signal lines (B₁ to B₈); the bit line selection transistors are separated into a plurality of blocks (31, 32, 33, 34) corresponding to each bit line group, the bit line selection transistors in each block are arranged along the direction of the bit lines, the gates of the bit line selection transistors are arranged perpendicular to the direction of the bit lines, and the gates of the bit line selection transistors in one block are commonly connected with the gates of the corresponding bit line selection transistors in the adjoining blocks. Thus, the pitch between transistor blocks is reduced, the pattern of the bit lines is made denser, and the integration density of the semiconductor memory device is increased.

Description: The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device using a pattern of arrangement of elements reducing the pitch of bit lines. In a semiconductor memory device, a plurality of word lines and bit lines are arranged perpendicular to each other. Memory cells are located at the cross positions of each word line and bit line. Each word line is connected to a row decoder circuit. Each bit line is connected to a sense amplifier circuit through a bit line selection transistor. The gate of each bit line selection transistor is connected to a column decoder circuit. Recent demand for higher density integration semiconductor memory devices has necessitated denser patterns of arrangement of word lines and bit lines. To achieve denser patterns of arrangement of bit lines, it is necessary to reduce the pitch between bit lines which requires reducing the spacing of bit line selection transistors associated with the bit lines. GB-A-2 068 638 discloses an arrangement for electrically joining the ends of substantially parallel semiconductor line sets, in one form of which a ROM is provided wherein the connection of bit lines to bit predecoder lines is as specified in the preamble of accompanying claim 1. According to the present invention, there is provided a semiconductor memory device comprising a plurality of bit line groups, each including a plurality of bit lines (BL) extending along a column direction, and a plurality of bit line selection transistor arrays, each including a plurality of bit line selection transistors (QB) corresponding to said bit lines, separated into blocks corresponding to said bit line groups; wherein said bit line selection transistor arrays are arranged one after another perpendicular to the direction of said bit lines (BL); and the gates of corresponding bit line selection transistors in different selection transistor arrays are arranged perpendicular to the direction of said bit lines (B); characterised in that: the plurality of bit line selection transistors (QB) in each bit line selection transistor array are arranged one after another along the direction of said bit lines (BL); and in that said gates are extended and connected to the gates of corresponding transistors (QB) in adjoining bit line selection transistor arrays. An embodiment of the present invention can provide a semiconductor memory device, wherein the pitch between bit lines is reduced, thereby achieving a denser pattern of arrangement of bit lines and increasing the integration density. Reference is made, by way of example, to the accompanying drawings in which:- Figure 1 is a diagram of a pattern of arrangement of bit line selection transistors in a conventional semiconductor memory device; Fig. 2 is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the present invention; Fig. 3 is a diagram of a pattern of arrangement of bit line selection transistors in the semiconductor memory device of Fig. 2; and Fig. 4 is a diagram explaining the pattern of arrangement of Fig. 3. Prior to the description of the preferred embodiment of the present invention, a pattern of arrangement of bit line selection transistors in a conventional semiconductor memory device will be explained for comparative purposes with reference to Fig. 1. In Fig. 1, reference characters BL1, BL2, ..., BL8 show bit lines, and B1, B2, ..., B8 show decode signal lines for supplying decode signals from a column decoder circuit. Reference characters F1, F2, F3, and F4 show fields on which the bit line selection transistors are formed. The hatched portions PSL indicate a first conductor layer, for example, a polycrystalline silicon layer. Two bit line selection transistors are formed in each field. Namely, in each field , drains are located at the right and left ends as seen in the Figure. A common source is provided at the middle for the two transistors. The gates of the transistors are formed by the polycrystalline silicon layer PSL. In the pattern of Fig. 1, the bit line selection transistors are arranged perpendicular to the direction of the bit lines. Therefore, the pitch between adjoining bit lines is determined by the transistor width. Figure 2 is a schematic circuit diagram of a semiconductor memory device according to the preferred embodiment of the present invention. Figure 3 shows pattern of arrangement of bit line selection transistors on an integrated circuit substrate in the semiconductor memory device of Fig. 2. The semiconductor memory device of Fig. 2 comprises a memory cell region 1; a row decoder circuit (RDC) 2; word lines WL; bit line groups, each of which includes eight bit lines (BL); transistor blocks 31, 32, 33, and 34, serving as bit line selection transistor arrays, each of which includes eight bit line selection transistors QB corresponding to the bit line groups; a first column decoder circuit (CDC) 4; a second column decoder circuit (CDC) 5; block selection transistors QA; and a sense amplifier SA. In the memory cell region 1, the plurality of word lines and the plurality of bit lines are arranged perpendicular to each other. A memory cell is located at each cross position of the word lines WL and the bit lines BL. Each word line WL is connected to the row decoder circuit 2. Each bit line BL is connected to a bit line selection transistor QB. The bit line selection transistors QB are separated into four blocks 31, 32, 33, and 34 corresponding to the bit line groups. The gates of the bit line selection transistors QB in each block are connected to column selection signal lines B1, B2, ..., B8 from the first column decoder circuit 4, respectively. The first column decoder circuit 4 decodes the lower columns of address signals a₀ , a₁ , a₂ and selects one of the eight column selection signal lines B1, B2, ..., B8 to raise its potential to a high level corresponding to the pattern of the address signals a₀ , a₁ , a₂. The bit lines are connected together in each block through the bit line selection transistors QB. Each commonly connected line is connected to the sense amplifier circuit SA through the block selection transistors QA. The gates of the block selection transistors QA are connected to block selection signal lines A1, A2, A3, A4 from the second column decoder circuit 5, respectively. The second column decoder circuit 5 decodes upper columns of address signals a₃ , a₄ and selects one of the block selection signal lines A1, A2, A3, A4 to raise its potential to a high level corresponding to the pattern of the address signals a₃ , a₄. Figure 3 is a plan view of the pattern on which the bit line selection transistors QB in the semiconductor memory device of Fig. 2 are formed. In Fig. 3, reference numeral 11 is a memory-cell forming region, 12 is a decoder-circuit forming region, and 13 is a first- and second-column-decoder-circuit forming region. The bit line selection transistors QB are formed in pairs in rectangular fields FL. The bit lines from the memory-cell forming region 11 are connected to the bit selection transistors QB by an aluminum conductive pattern. The decode signal lines B1, B2, ..., B8 from the first column decoder circuit 4 are connected to the bit line selection transistors QB by the polycrystalline silicon layer, arranged perpendicular to the bit lines. Considered three dimensionally, the polycrystalline silicon layer is provided above the transistor forming region with a silicon dioxide SiO₂ insulating layer inserted therebetween. The aluminum pattern is formed above the polycrystalline silicon layer. The polycrystalline silicon layer, shown by the hatched lines, functions in the fields FL as gates of the bit line selection transistors QB. A plurality of transistor blocks are located along the direction perpendicular to the bit lines. The eight transistors QB included in each transistor block are arranged along the direction of the bit lines, as shown in Fig. 3. The gates of the bit line selection transistors in one block, comprised of polycrystalline silicon and connected to the decode signal lines B1, B2, ..., B8, are thus connected to the gates of the corresponding bit line selection transistors in the adjoining transistor blocks. The rectangular fields FL' are for forming the block selection transistors QA. In each field, two transistors QA are located. In the pattern of Fig. 3, since the bit line selection transistors in each block are arranged along the direction of the bit lines, the pitch of the bit lines can be reduced to less than the width of the region forming the bit line selection transistors. Further, in a bit line selection transistor block, the lower a bit line selection transistor is located in the figure, the less the number of crossings of bit lines in the vicinity of the transistor. A wider contact area between the electrode of the transistor and the bit line is possible with a bit line selection transistor having less cross over. Thus, the resistance of the electric connection can be reduced and a more reliable connection achieved. Figure 4 is a diagram explaining the elements of the transistor pattern in Fig. 3. In the figure, the drain of the bit line selection transistors QB1 to QB4 is shown by the reference character D. The source is formed in common between the bit line selection transistors QB1 and QB2 or QB3 and QB4. The source is indicated by the reference character S.

Claims: A semiconductor memory device comprising a plurality of bit line groups, each including a plurality of bit lines (BL) extending along a column direction, and a plurality of bit line selection transistor arrays (31...34), each including a plurality of bit line selection transistors (QB) corresponding to said bit lines, separated into blocks corresponding to said bit line groups; wherein: said bit line selection transistor arrays (31... 34) are arranged one after another perpendicular to the direction of said bit lines (BL); and the gates of corresponding bit line selection transistors (QB) in different selection transistor arrays are arranged perpendicular to the direction of said bit lines (BL); characterised in that: the plurality of bit line selection transistors (QB) in each bit line selection transistor array (31... 34) are arranged one after another along the direction of said bit lines (BL); and in that said gates are extended and connected to the gates of corresponding transistors (QB) in adjoining bit line selection transistor arrays. A device as claimed in claim 1, wherein in each bit line selection transistor array (31...34), the drain of each bit line selection transistor (QB) is connected to its corresponding bit line (BL), and the source of each bit line selection transistor is connected to a sense amplifier (SA), the contact area in said connections gradually increasing along said array in accordance with the decreasing number of bit lines extending that far along the array. A device as set forth in claim 1 or 2, wherein an aluminium pattern connects each said bit line (BL) to the drain of said corresponding bit line selection transistor (QB), and connects the sources of said bit line selection transistors to a sense amplifier (SA). A device as set forth in claim 3, wherein the aluminium pattern is designed so as to minimise the crossing of said bit line selection transistor arrays (31...34) by said bit lines (BL), and to maximise the contact area in connections to the bit line selection transistors (QB). A device as set forth in any preceding claim, wherein the gates of said bit line selection transistors (QB) are comprised of polysilicon, and the gates of corresponding bit line selection transistors in each of said bit line selection transistor arrays (31...34) are formed by a common polysilicon line.

Inventors: ITANO, KIYOSHI, YOSHIDA, MASANOBU
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: G11C5
IPC codes: G11C5, H01L27, G11C11