PMOS INPUT BUFFER COMPATIBLE WITH LOGIC INPUTS FROM AN NMOS MICROPROCESSOR

Abstract: A PMOS input buffer compatible with logic voltage levels provided by NMOS or TTL microprocessor means uses a limited number of transistors of limited size for driving a load in response to such logic and is adapted for use under widely varying operating conditions.

Description: Background of the Invention The field of this invention is that of metal-oxide-semiconductor (MOS) integrated circuits, and the invention relates more particularly to a PMOS input buffer compatible with logic inputs from an NMOS microprocessor. Microprocessors implemented in NMOS integrated circuit technology are typically proposed for use in automotive control applications to meet the speed, complexity and cost requirements of such applications. However the LED or vacuum fluorescent display means and PMOS display driver means which are usually proposed for use in such automotive applications to meet the requirements of cost and sunlight conditions and the like have input requirements which are typically not compatible with the voltage levels of the logic signals provided by such NMOS microprocessor means. That is, conventional input buffer means are not adapted for use between the NMOS microprocessor and the associated PMOS circuit means. For example, the input signals provided by the NMOS microprocessor are referenced to the drain supply voltage so that a conventional input buffer utilizing a grounded source enhancement device and a saturated load with the Beta ratio adjusted for input voltage levels is found to be inappropriate. Similarly, known input buffer means utilizing differential amplifier means are found to provide very little gain and are also considered inappropriate. Accordingly relatively expensive CMOS buffer means and the like have been proposed for use to hermit the preferred microprocessor, display, and driver means to be employed together in automotive control applications. In the IBM Technical Disclosure Bulletin, Vol.22, No.8B, January 1980, pages 3638-3840, there is described an input buffer circuit having a level translating circuit feeding a Schmitt trigger. The level translations circuit comprises a common gate connected MOSFET fed by a constant current source which feeds a drive signal to a transistor of the Schmitt trigger. The current from the constant current source flows through the input terminal. The common source impedance of the Schmitt trigger is a transistor to which the drive signal is also applied. US Patent US-A- 4,379,974 describes a delay stage having a Schmitt trigger with a push-pull buffer stage formed by two MOS transistors with their gates respectively directly connected to the gates of the transistors of the trigger. The transistors of the buffer stage are connected in series between the common source connection of the transistors of the trigger and the power supply conductor. It is an object of this invention to provide an improved input buffer means for connecting output logic signals from one circuit means to other circuit means requiring different logic signals. According to the present invention there is provided an MOS integrated circuit input buffer comprising level-shifting means responsive to logic input signals at selected voltage levels for providing corresponding control signals at level-shifted voltage levels, Schmitt trigger means having selected voltage thresholds and responsive to said control signals crossing the voltage thresholds for providing corresponding trigger output signals with hysteresis, and output means responsive to said trigger signals for providing buffer output signals having improved compatibility for driving selected circuit means, said level-shifting means comprising MOS transistor means (M1,M2) forming voltage divider means for providing a reference voltage at a selected level, a pair of MOS transistor means (M4,M6) forming a current mirror means, MOS transistor means (M3) biased by said reference voltage to provide desired current levels in one said current mirror transistor means, and additional MOS transistor means (M5) connected to receive said logic input signals on its gate and responsive to said current mirror means for ensuring that said corresponding control signals are provided at desired level-shifted voltage levels. The input buffer means to be described is implemented in PMOS integrated circuit technology so as to be compatible with the output voltage levels of logic signals provided by NMOS microprocessor means. The improved PMOS input buffer includes level-shifting means responsive to the logic signals provided by the NMOS microprocessor means for providing corresponding logic signals at substantially improved voltage levels. Preferably the level shifting means are selected to be dependent on the level of the drain supply voltage provided in the input buffer for assuring that the desired level shifting is achieved during variations in drain supply voltage. One embodiment of the invention is a novel and improved input buffer for use between NMOS microprocessor means and integrated circuit means including PMOS display driver means and the like. The embodiment may be an improved input buffer compatible with logic inputs from NMOS and TTL microprocessor means which is characterized by low cost, by the use of a limited number of transistor means of relatively limited size, and by being adapted for use under the widely varying operating conditions typically associated with automotive control applications and the like under widely varying operating conditions such as might be encountered in automotive control applications. The improved input buffer further includes Schmitt trigger means arranged to be responsive to the level-shifted input signals to provide desired hysteresis for improving noise suppression in the buffer. Preferably the Schmitt trigger means are arranged so that the thresholds of the trigger track the outputs of the level shifting means over the range of variation in the drain supply voltage of the buffer system. In the preferred embodiment of the invention, the output stages of the buffer include source follower means and the Schmitt trigger is arranged to be driven by the source follower means for achieving further improved speed characteristics in the buffer. The source follower means also serves to provide current gain and improved level shifting and in the preferred embodiment of this invention, the input buffer further includes an otherwise conventional push-pull output stage for achieving further desired current gain. Description of the Drawings Other objects, advantages and details of the novel and improved input buffer of this invention appear in the following detailed description of preferred embodiments of the invention, the detailed description referring to the drawings in which: Fig. 1 is a schematic circuit diagram of a PMOS input buffer provided by this invention; and Fig. 2 is a graph illustrating operating characteristics of the input buffer of Fig. 1. Description of the Preferred Embodiments Referring to the drawings, the novel and improved MOS integrated circuit of this invention is shown to comprise an input buffer 10 having voltage level shifting means 12 incorporated MOS transistors M₁-M₆. All PMOS transistors are illustrated in Fig. 1 but it should be understood that other circuit components can also be incorporated in the improved input buffer 10 within the scope of this invention. The channels of the transistors M₂ and M₁ are connected in series between the source and drain supply voltages V ss and V dd . In the preferred embodiment, both transistors are depletion-type devices which are always on and the drain of transistor M₂ is connected to the source of transistor M₁ to form the node N₁ as illustrated in Fig. 1. The gates of transistors M₁ and M₂ are connected to the drain supply voltage and to the source supply voltage respectively, preferably through respective current limiting resistors 14 and 16 which serve to protect the input buffer against static electricity. The transistor M₁ is operated in the triode region to serve as a resistor and transistor M₂ is always saturated to serve as a current source. The channels of transistors M₄ and M₃ are also connected in series between the source and drain supply voltages. The gate of transistor M₃ is connected to node N₁. The drain of transistor M₄ is connected to the source of transistor M₃ to form the node N₂ as shown in Fig. 1 and that node N₂ is connected to the gate of transistor M₄. Both of the transistors M₃ and M₄ are enhancement-type devices and are proportioned and arranged so that they are always on to provide a relatively limited level of current. The channels of transistors M₆ and M₅ are also connected in series between the source and drain supply voltages, both of those transistors being enhancement-type devices. The gate of transistor M₅ is connected to the input 18 of the buffer which is typically provided by an NMOS microprocessor or a transistor-transistor-logic (TTL) circuit or the like. The gate of the transistor M₆ is connected to the node N₂ in common with the gate of transistor M₄ so that transistors M₄ and M₆ form a current mirror. The drain of transistor M₆ is connected to the source of transistor M₅ to form node N₃ as is shown in Fig. 1. Transistors M₃-M₆ all operate in the saturation region. In accordance with this invention, the level shifting means 12 cooperates with Schmitt trigger means 20 comprising the PMOS transistors M₇-M₁₂ and M₁₇ which provides the input buffer 10 with desired hysteresis. That is, the channels of transistors M₁₀ and M₉ are connected in series between the source and drain supply voltages as shown in Fig. 1. The gates of the transistors M₉ and M₁₀ are connected to the drain and source supply voltages respectively, preferably through a respective current limiting resistors 22 and 24 for protecting the input buffer against static electricity. The transistor M₉ is an enhancement-type device and transistors M₁₀ and are depletion-type devices and the drain of M₁₀ is connected to the source of M₉ to form the node N₅. Transistor M₁₇ has its drain and gate connected to node N₅ and its source connected to V ss . The channels of transistors M₇ and M₈ are connected in series between the drain supply voltage V dd and node N₅ and the channels of transistors M₁₁ and M₁₂ are also connected in series between the drain supply voltage and node N₅. Transistor M₇ has its gate connected to its source and is also connected to the drain of transistor M₈ to form node N₄. The gate of transistor M₈ is connected to node N₃. Transistor M₁₁ has its gate connected to its source and is also connected to the drain of transistor M₁₂ to form node N₆. The transistors M₇, M₁₀, M₁₁ and M₁₇ are depletion-type devices while transistors M₈, M₉ and M₁₂ are enhancement devices. Transistors M₇ and M₁₁ are saturated while transistor M₁₀ and M₁₇ operate in the linear region. In accordance with this invention, the input buffer 10 further includes the driver means 26 which preferably includes source follower, buffer means 28 comprising the transistors M₁₃ and M₁₄. The driver also includes an output stage 30 comprising the transistors M₁₅ and M₁₆. Preferably, the channels of transistors M₁₄ and M₁₃ are connected in series between the source and drain supply voltages. The drain of depletion device M₁₄ is connected to the source of enhancement device M₁₃ to form the node N₇ which is connected in common to the gate of transistor M₁₂ in the Schmitt trigger 20. The gate of transistor M₁₄ is connected to the source supply voltage, preferably through the static protection resistor 24 and the gate of transistor M₁₃ is connected to node N₄ in the Schmitt trigger. The two enhancement-type transistors M₁₆ and M₁₅ are connected in push-pull configuration between the source and drain supply voltages and the drain of transistor M₁₆ is connected to the source of transistor M₁₅ to form the output 34 of the buffer 10. The gate of transistor M₁₆ is connected to the node N₇ and the gate of transistor M₁₅ is connected to the node N₆ in the Schmitt trigger 20. As thus far described, the input buffer 10 is preferably arranged in an integrated circuit to receive logic signals from an NMOS microprocessor or the like. In a preferred embodiment of the invention where the buffer is used for driving PMOS circuit means including LED or vacuum fluorescent display means in an automotive control application for example, the source supply voltage V ss corresponds to the vehicle supply voltage and typically varies from 8 to 18 volts over an ambient temperature (t a ) range of -30°C. to 85°C. and is typically about 9.5v. The drain supply voltage V dd corresponds to system ground. In that arrangement, voltages at input 18 representing logic inputs "0" and "1" will be within a short range of V dd , typically in a range from V dd + 0.8v. to V dd + 3.5v. and neither input will approach V ss . In one preferred embodiment of the invention, the PMOS transistors M₁-M₁₇ have widths and lengths (W/L) in mils as set forth in Table I below: Transistor W/L Transistor W/L M₁ 0.3/1.0 M₉ 0.3/2.4 M₂ 0.3/.60 M₁₀ 0.7/0.6 M₃ 0.3/1.0 M₁₁ 0.35/0.6 M₄ 18.0/0.60 M₁₂ 3.4/0.3 M₅ 0.3/1.0 M₁₃ 1.2/0.3 M₆ 18.0/0.60 M₁₄ 0.3/1.0 M₇ 0.3/1.0 M₁₅ 1.0/0.3 M₈ 1.4/0.3 M₁₆ 1.0/0.3 M₁₇ 0.7/0.6 With those characteristics, the input buffer 10 has the following input specifications: Min. Max. (1) V ss 8 volts 18 volts (2) t a -30°C. 85°C. (3) V IH 3.5 volts V ss plus .3 volts (4) V IL -0.3 volts 0.8 volts (5) Hysteresis 0.5 volts 0.8 volts (voltages stated with respect to V dd ) That is, where the source supply voltage varies from 8 to 18 volts, the input buffer is adapted to be responsive to logic high input voltages varying from 3.5 volts to V ss + 0.3 volts and to logic low input voltages varying from -0.3 volts to 0.8 volts while providing desired hysteresis of 0.5 volts. As thus described, the buffer 10 provides level shifting, voltage and current gain, and desired hysteresis corresponding to the input specification as set forth above. In the level-shifting means 12, the transistor M₂ is always saturated and serves as a current source while the transistor M₁ operates in the triode region and serves as a resistor, whereby a constant reference voltage V REF is generated at node N₁, that voltage being referenced to V dd . The voltage V REF corresponds generally to the drain to source voltage across transistor M₁ and varies with V dd such that as V dd varies between -8 and -18 volts, the reference voltage V REF varies between 3 volts and 4 volts. That voltage at N₁ then serves to set the gate voltage at transistor M₃ to provide the desired voltage level shifting. That is, the current I M3 in transistor M₃ equals current I M4 in transistor M₄; the current I M5 in transistor M₅ equals current I M6 in transistor M₆; the current I M4 equals the current I M6 ; and the voltage at node N₂ corresponds to the threshold voltage V T of transistor M₄. The voltage at node N₃ therefore corresponds generally to the input voltage at 18 less the reference voltage V REF plus the noted threshold voltage V T . The transistors M₃-M₆ all operate in the saturation region since their gate voltages never exceed the drain supply voltage V dd . In that arrangement, where the reference voltage V REF is set to correspond to V IH , at 3.5 volts as set out in specification (3), the gate voltages provided at node N₃ have logic levels of V T and V T + (V IH (min.) - V IL (max.)) which is ideal to drive the Schmitt trigger stage of the buffer as is illustrated in Fig. 2. That is, the low and high logic voltage levels L₃ and H₃ appearing at node N₃ as voltages V IL (.8 volts) and V IH (3.5 volts) are applied at the input 18 respectively result in a minimum output of the level shifting means 12 as indicated by curves L₃ and H₃ in Fig. 2 as the drain supply voltage V dd varies between -8 and -18 volts. In accordance with this invention, the Schmitt trigger means 20 are further adapted to cooperate with the level-shifting means 12 to assure proper operation of the buffer 10 over a wide range of operating conditions. Thus the thresholds V TH + and V TH - of the Schmitt trigger are described by the following expressions: where I M7 , I M10 and I M11 are the currents in transistors M₇, M₁₀ and M₁₁ respectively, R is a resistance across the parallel combination of transistors M₁₀ and M₁₇, and V TM8 is the threshold voltage of transistor M₈. In that regard, the transistors M₇ and M₁₁, are saturated and transistors M₁₀ and M₁₇ operate in the linear region. The hysteresis provided by the Schmitt trigger corresponds to I M11 R. In that arrangement, transistors M₇ and M₈ form a first leg of the Schmitt trigger and transistors M₁₁ and M₁₂ form the second or alternate leg of the trigger which cooperate with transistors M₁₀ and M₁₇ to provide the trigger with selected hysteresis. The transistor M₉ then acts as a resistor to the drain supply voltage and adds some dependence on drain supply voltage to both of the thresholds of the Schmitt trigger without affecting the hysteresis provided by the Schmitt trigger for noise suppression purposes. In that way, the Schmitt trigger compensates to some extent for the V dd dependence of the voltage at node N₁ (due to the body effect of transistors M₁ an M₅) as previously described. As a result, the thresholds of the Schmitt trigger in the buffer 10 track the output of the level shifting means 12 over the range of variation of the drain supply voltage as is indicated at V TH + and V TH - in Fig. 2. The final output stage 26 of the buffer 10 then cooperates with the Schmitt trigger 20 in providing desired output voltage and drive current capabilities as will be understood. That is, the transistors M₁₃ and M₁₄ serve as a source follower to provide current gain and some additional shift of voltage level at node N₇. The fairly large transistor M₁₂ in the Schmitt trigger is then driven by the source follower as illustrated in Fig. 1 to improve the propogation delay achieved by the Schmitt trigger. The transistors M₁₅ and M₁₆ are arranged in push-pull configuration as shown and comprise a conventional buffer output stage. As thus described, the buffer 10 provides A.C. propagation delay (V IN to V OUT ) as illustrated in Table II: Condition V dd =-8v. V dd =-18v. Output Transition 1→0 0→1 1→0 0→1 Typical 295 195 335 235 Worst Case 655 715 575 475 The data is given in nanoseconds for operation at 120°C. in both cases for the case where 1 = V ss and 0 = V dd . In use, the buffer 10 typically receives a logic input from an NMOS microprocessor or the like so that the input voltage V IN at 18 varies within a short range of the drain supply voltage V dd and does not approach the level of the source supply voltage V ss . The buffer 10 is compatible with such an input from the microprocessor and serves as a noninverting input buffer to provide desired voltage and current levels for driving circuits including PMOS display driver means and the like in automotive applications. In that regard, transistors M₁ and M₂ are always on and serve as a voltage divider to provide a reference voltage V REF at node N₁. That reference voltage varies in the range from 3 volts to 4 volts as the drain supply voltage V dd varies from -8 to -18 volts and the voltage at N₁ biases the level shifting components M₃ - M₆ to provide desirably level-shifted voltages at node N₃. That is, the transistor M₃ has the same size and resistance as transistor M₅ and transistor M₄ has the same size and resistance as transistor M₆. Transistors M₄ and M₆ form a current mirror. Transistor M₃ is biased by reference voltage V REF and serves as a voltage-to-current converter tending to provide a desired current level in transistor M₄ and therefore in transistor M₆. In that arrangement, as the input voltage V IN varies as above described, the voltage across transistor M₅ corresponds to the voltage across transistor M₃ and produces a desired level-shifting of the low and high voltages at node N₃ away from V dd toward V ss as is indicated by curves L₃ and H₃ in Fig. 2. Those voltage levels at N₃ then cooperate with the Schmitt trigger 20 and with the driver means 26 to provide an output 34 at desired voltage and current levels and with desired hysteresis for noise suppression purposes for driving the noted automotive control circuit. For example, when the input voltage V IN at 18 is high corresponding to a logic input "1" nearer to V ss , the voltage at node N₃ corresponds to curve H₃ in Fig. 2 so that the transistor M₈ is turned off. When M₈ turns off, the voltage at N₄ moves toward the level of the drain supply voltage V dd . Transistors M₁₃ and M₁₄ form a source follower and as the voltage at N₄ goes toward V dd , transistor M₁₃ conducts and the voltage at node N₇ also goes close to V dd (near logic "0"). Transistor M₁₆ is therefore turned on and the voltage at output 34 also goes high nearer to V ss . The transistors M₉ and M₁₀ are always on in the Schmitt trigger 20 and the transistor M₁₀ operates in the triode region to function as a resistor. There is accordingly a small current flowing in transistors M₉ and M₁₀ and M₉ applies a selected voltage bias to node N₅. Before transistor M₈ is turned off as noted above, a small current also flows in transistor M₇ and M₈ providing additional voltage at the node N₅ as will be understood. Then, when transistor M₁₂ is turned on as noted above, transistor M₁₁ has slightly less resistance than transistor M₇ and provides a positive feedback so that the voltage at node N₅ goes slightly toward V dd , thereby turning transistor M₈ off more completely to provide the desired minimum .5 volt hysteresis as required by specification (5) noted above. Conversely when the input voltage V IN at 18 goes low corresponding to logic input "0" nearer to V dd , the voltage at node N₃ corresponds to curve L₃ in Fig. 2 so that the transistor M₈ is turned on and current again flows in transistor M₇. The voltage at node N₄ goes toward V ss so that transistor M₁₃ is also turned off and the voltage at node N₇ also moves toward V ss . That voltage at N₇ then turns off transistor M₁₂ and also turns off transistor M₁₆ so that the voltage at output 34 goes toward V dd . As transistor M₁₂ is turned off, the current at node N₅ decreases and voltage at node N₅ decreases. The voltage at node N₆ also goes toward V dd and transistor M₁₁ stops conducting because there is no voltage across the transistor. As thus described, nodes N₄ and N₆ are both outputs from the Schmitt trigger. The inverted output from node N₄ is buffered through the source follower stage formed by transistors M₁₃ and M₁₄ and provides desired current gain while also cooperating with the noninverted output from node N₆ in operating the final output stage of the buffer 10 as formed by the transistors M₁₅ and M₁₆. In that way the input buffer 10 accomplishes the desired results and meets the desired input buffer specification utilizing a limited number of PMOS transistors of relatively limited size.

Claims: An MOS integrated circuit input buffer comprising level-shifting means (12) responsive to logic input signals at selected voltage levels for providing corresponding control signals at level-shifted voltage levels, Schmitt trigger means (20) having selected voltage thresholds and responsive to said control signals crossing the voltage thresholds for providing corresponding trigger output signals with hysteresis, and output means (26) responsive to said trigger signals for providing buffer output signals having improved compatibility for driving selected circuit means, said level-shifting means comprising MOS transistor means (M1,M2) forming voltage divider means for providing a reference voltage at a selected level, a pair of MOS transistor means (M4,M6) forming a current mirror means, MOS transistor means (M3) biased by said reference voltage to provide desired current levels in one said current mirror transistor means, and additional MOS transistor means (M5) connected to receive said logic input signals on its gate and responsive to said current mirror means for ensuring that said corresponding control signals are provided at desired level-shifted voltage levels. A buffer according to claim 1, in which said Schmitt trigger means (20) have first transistor means (M10,M17) therein arranged to define the selected voltage thresholds for the trigger means and second transistor means (M9) connected between said first transistor means and a system supply voltage render the trigger voltage thresholds dependent on the system supply voltage, so that the threshold voltages of the trigger means track changes in said corresponding control signals within due to variations in the supply voltage. A buffer according to claim 2, wherein said means (12) responsive to logic input signals comprise first PMOS circuit means (M5) responsive to logic input signals having voltage levels corresponding to those provided by a PMOS circuit means for providing corresponding control signals at said level-shifted voltage levels, said Schmitt trigger means (20) comprise second PMOS circuit means (M7-M12,M17) responsive to said level-shifted control signals for providing the corresponding trigger output signals with selected hysteresis, and said output means (26) comprise third PMOS circuit means (M13,M14,M15,M16) responsive to said trigger signals for providing the buffer output signals suitable for driving an external PMOS integrated circuit means. A buffer according to claim 2 or 3, wherein said Schmitt trigger means comprises a pair of MOS transistor means (M8,M12) arranged in parallel and having their sources connected to the first transistor means (M10,M17) forming a common source impedance and to the second transistor means (M9), the first and second transistor means comprising MOS transistors. A buffer according to any one of the preceding claims, wherein said output means includes push-pull amplifier means (M15,M16) and source follower means (M13) responsive to the trigger output signals provided by the Schmitt trigger means for driving the push-pull amplifier means, said source follower means (M13) also being arranged to cooperate in operating said Schmitt trigger means for improving the switching speed of the buffer.

Inventors: PRATER, CORDELL ERNEST
Applicants: TEXAS INSTRUMENTS INCORPORATED
Application year: 1984
Main classification: H03K19
IPC codes: H03K19, H03K3