PRINTED CIRCUIT BOARD MAXIMIZING AREAS FOR COMPONENT UTILIZATION

Abstract: A multilayer printed circuit board for TTL logic compo­ nents provides an approximate 100 ohm characteristic impedance between external microstrip signal lines and internal ground and voltage planes. The addition of two internal microstrip signal plane lines permits a much greater interconnectability capability and also saves a large percen­ tage of spatial area for component mounting while still maintaining the 100 ohm impedance characteristic.

Description: PRINTED CIRCUIT BOARD MAXIMIZING AREAS FOR COMPONENT UTILIZATION BACKGROUND OF THE INVENTION This invention involves improvements in printed circuit boards and relates specifically to those types of printed circuit boards which bear multiple conductor arrays. With the constant trend toward miniaturization of electronic components and especially the use of integrated circuitry and integrated circuit chip components which are mounted on printed circuit boards, there is a constant trend toward finding methods of increasing the density of components while minimizing the amount of real estate or printed circuit board area involved both in length, width and also thickness. There is increasingly a trend toward the use of multilayer printed circuit boards whereby conductive material is separated by insulative material and several layers of such materials are interleaved in order to provide multiple capabilities of interconnection between the electronic components which are mounted on the outer area of the printed circuit board. By the use of plated-through apertures or "vias", it is possible to interconnect various of the conductive materials on the different layers of the printed circuit board and at the same time, when necessary, provide insulation when the interconnected elements must not contact a certain layer of the interpenetrating via or aperture. Accordingly, such patents as U.S. Patent 4,362,899 entitled "Printed Circuit Board" indicates types of elements of the construction of multilayered conductive material separated by layers of insulating material and the use of "plated-through holes". Mention here is also made of a ground plane whereby certain shield tracks are connected to the ground plane to provide shielding. Similarly, U.S. Patent 4,328,531 entitled "Thick Film Multilayer Substrate" involves a technique of construction of multiple conductor layers with dielectric layers interleaved between them. Here, a power supply line is formed in the conductor layer and is interposed between the first and third conductor layers. It has been found desirable in the design of high density printed circuit boards, which involve the mounting of multiple components, to provide not only voltage and ground connections to various of the electronic components mounted thereon, but it is also necessary to provide interleaved conductive layers to provide connections between various components with each other, and various components with the voltage plane and the ground plane. Further, in order to minimize signal distortion of pulses or waves traveling in the printed circuit conductors, it is most desirable to maintain a constant impedance between various conductors referenced to the voltage plane and ground plane. To this end, the present disclosure indicates the development of a high density element storage capability on a printed circuit board involving a plurality of conductive layers which may involve up to six conductive layers separated by insulating substrate and wherein there is provided a constant impedance parameter of 100 ohms plus or minus 10% between any conductive line and the voltage plane and between any conductive line and the ground plane of the printed circuit board. This impedance level is a standard requirement for Transistor-Transistor Type (TTL) logic. In addition, there is a standard constraint thickness of printed circuit boards which requires overall thickness of 0.062 f 0.001 inch. CROSS REFERENCES TO RELATED APPLICATIONS This disclosure is related to a patent application entitled "Multilayered Printed Circuit Board With Controlled 100 OHM Impedance", inventor Michael Barrow, filed as as U.S. Serial No. SUMMARY OF THE INVENTION It is an object of this invention to provide a multilayered printed circuit board which, while allowing a high density of component mounting per unit surface area, will provide for more effective interconnection capability between electronic components mounted on the component surface of the printed circuit board. It is a further object of the present invention to provide a circuit board which provides a multilayered substrate wherein a plurality of conductive layers are separated by an insulating substrate and whereby the characteristic impedance between any metallic conduction signal plane and a voltage plane or a ground plane will be of a constant nature, in this particular case approximately a constant 100 ohms characteristic impedance, especially suitable for transistor-transistor type logic. It is a further object of this invention to configure a multilayered printed circuit board having an internal voltage plane and a ground plane on either side of which there is at least two conductive signal layers, again such that the impedance between any signal layer and a voltage plane or any signal layer and a ground plane will always approximate 100 ohms characteristic impedance. It is a further object of the invention to provide an internal voltage plane and ground plane central to a plurality of conductive signal layers such that there will be no attenuation, alteration or distortion of signals which pass through the signal conductive planes and further there will be no cross talk or cross induction from one signal plane to another. It is a further object of the invention to provide a multilayered circuit board having internal voltage and ground planes and at least four separate signal planes, yet the board being restricted to a thickness of only 0.062 of an inch plus or minus 0.007 of an inch. The above objects are accomplished by using an epoxy glass insulating substrate which separates a parallel series of conductive copper signal planes and which also separates an internal conductive copper voltage plane from an internal conductive copper ground plane. The external top conductive layer and the external bottom conductive layer are eight mil width conductive lines, that is to say 0.008 inch. Internally and 0.005 inch away from the top and bottom external conducting planes, there is another conducting layer having a five mil width which is used as a microstrip signal line. Internally at a distance of 0.025 of an inch from the top internal signal line, there is a ground plane conductor having a one ounce weight characteristic. (Note: the NEMA (National Electrical Manufacturers Association) manual defines this as the deposition of one ounce of copper deposited evenly on a one square foot area). Then, inward from the lower (solder side) external signal layer, there is a voltage plane separated by 0.028 inch of substrate. The voltage plane is a conductive layer of one ounce character and is separated from the ground plane by 0.005 inch of substrate. This minimum separation ensures good voltage to ground noise decoupling. It is the particular thickness of the various signal line planes and the separation distances between the signal planes and the voltage plane (and or ground plane) that make it possible for there to exist a constant impedance of 100 ohms between any signal line and the voltage plane or between any signal line and the ground plane. It is desirable that a constancy of impedance be established since this will ensure that all signals operating on the signal lines will see the same impedance and no one signal will be changed or distorted disproportionately in relationship to another signal line. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an expanded cross-section drawing which shows the multilayered printed circuit board with four signal conducting planes, two at the top at the component side and two at the bottom on the solder side, in addition to the internal voltage plane and conductive ground plane; FIG. 2 is an isometric drawing showing a cross-section of the printed circuit board indicating the various conductive planes separated by the substrate and also illustrating examples of plated-through holes whereby it is possible to make electrical connection between various of the inner and outer layers of the multilayered printed circuit board; FIG. 3 is a schematic drawing showing the overall printed circuit board with slide-in connector pins at one edge and also the orientation of the various signal lines of different layers; ; FIG. 4A shows a cross-section of a signal line for an "external" plane while FIG. 4B shows the signal line cross-section for an "internal" plane; FIG. 5 illustrates a concept involving interconnect capability involving the number of conductors per square inch of surface on the printed circuit board; FIG. 6 illustrates a 16 mil grid arrangement. DESCRIPTION OF PREFERRED EMBODIMENT FIG. 2 shows a cross-sectional cutout of a portion of a printed circuit board built according to the subject invention. The printed circuit board 10 is shown having a top external layer plane or "component side" layer 11 and the external lower side or "solder side" layer plane 16. Further, there is shown the internal upper signal layer plane 12, the ground plane 13, the voltage plane 14, the internal lower signal layer plane 15 and the external lower signal layer plane 16 (which corresponds to the sixth layer 16 of deposition on the substrate). The plated-through holes 18 may be used to connect any of the signal planes to the top layer signal plane which holds the components or to the ground plane or voltage plane as may be necessary. Likewise, the hole 18 may not be plated-through, that is it may be insulated so as not to connect, and thus to maintain the insulation as between any two conductive layers. FIG. 3 shows the printed circuit board in perspective and having slide-in connector pins along one edge. The solid lines illustrate the orientation of the top external and the lower internal signal lines while the broken lines show the top internal and lower external signal lines. Referring to FIG. 1 there is seen a cross-sectional view of the multilayered printed circuit board of the present disclosure. The top or component side is a signal plane 11 having a first layer of conductive copper upon which there may be connected or placed various electronic components. It is important to note that the size of this particular plane is critical to the configuration and thus the first layer is an eight mil thickness line (or a plurality of such lines) and is designated as a one ounce weight characteristic, having a width of 0.0014 inches or 1.4 mils. Directly beneath the first signal layer 11 there is a substrate portion 20a having a thickness of 0.003 of an inch (3 mils) after which there is placed another conductive plane 12. This may be called the second signal layer and it is made of a five mil width line (plus or minus one mil) and can be designated as a one-half ounce weight characteristic having a width of 0.0007 inches or 0.7 mils. This second signal layer may consist of a plurality of separate signal lines of 5 mil width which run at right angles to the lines of the first signal layer. Between the second signal layer 12 and the ground plane 13 there is a substrate 20b of thickness equal to 0.025 of an inch (25 mils plus or minus 1.5 mils) after which there is seen the ground plane 13 having a one ounce characteristic or thickness of 1.4 mils. Separating the ground plane 13 from the voltage plane 14 there is a substrate having a thickness of 0.005 of an inch or 5 mils. The voltage plane 14 may be considered as being the fourth layer from the top or component side while the ground plane 13 could be considered the third layer. The voltage plane 14 is used to carry power, that is voltages and currents which are to be connected to various of the elements mounted on the component side of the printed circuit board 10 of FIG. 1. Element No. 15 represents the fifth layer from the top and constitutes a plurality of signal lines in a plane wherein each one of the signal lines is "internal" and constitutes a five mil width line for carrying signals between various components on the component side which may be connected to the signal line through the plated-through connectors 18 shown in FIG. 2. The fifth layer 15 represents a series or plurality of signal lines which run basically at right angles to the second signal layer 12 and to the sixth layer 16 of signal lines. The sixth layer 16 is a signal line which is separated from the fifth layer 15 signal line by the portion of substrate designated 20e which is in the range of 3 mils plus or minus 1.5 mils. The sixth layer is the signal layer 16 and is made of an eight mil width line. A plurality of such 8 mil width lines may constitute the sixth layer as seen as elements 16 of FIG. 1. These lines run at right angles to the lines of the first signal layer 11. This sixth layer represents the solder side where a solder bath may be used to make interconnections at this lower external side. In order to calculate the impedance (FIG. 4A) between an "external" signal line (microstrip) and ground, or the "external" signal line and the voltage plane, it is required that use be made of the impedance formula: EMI9.1 where Er = dielectric constant for material substrate, for example, epoxy glass = 4.2 5.0 W = width of conductor, in mils t = thickness of conductor, in mils C = dielectric thickness, in mils Ln = natural logarithm. The above formula is derived for a rectangular microstrip having width W and thickness t as seen in FIGS. 4A and 4B. Similar type impedance derivations are performed for circular microstrip in an article entitled "Characteristics of Microstrip Transmission Lines" by H.R. Kaupp published in IEEE Transactions on Electronic Computers, vol. EC-16, No. 2, April 1967 at pages 185-193. Thus, for an "external signal line, if the impedance i50 is plotted on a chart for a line having an 8 mil width (W) and a 1.4 mil thickness, then this would require that the dielectric thickness C (distance between the external signal level plane and the adjacent ground plane or voltage plane) should be approximately 28 mils in order to provide a 100 ohm line impedance. For the "internal" signal microstrip line (FIG. 4B), the impedance formula is: EMI10.1 Here, if the impedance Sto is plotted for a line having a 5 mil width and 0.7 mil thickness (one-half ounce characteristic), then the dielectric thickness C (distance between the "internal" signal plane and the adjacent voltage or ground plane) should be approximately 25 mils in order to provide a 100 ohm characteristic impedance. Another feature of the multilayer printed circuit board is its higher capability for interconnections between the mounted component units through the internal layered lines. For example, the component side of the printed circuit board may support a variety of integrated circuit chips which have various configurations of output connection pins. These may vary from a 10 x 10 grid of output connections, or 20 pin output connections, or 28 pin output connections, etc. Thus, the surface of the board must be compatible to permit these type of connections to occur without interference to the conducting lines on the first layer signal plane on the top external component side of the printed circuit board. The density involved in a printed circuit board design can be expressed as line resolution -- i.e., the dimension of the conductor width and the dielectric space. Presently many high density boards are those designed primarily with two conductors routed between holes on 100 mil centers using an 8 mil conductor and an 8 mil dielectric space. For random logic usage the required length of conductor needed per unit board area (or the interconnect capacity) of a printed circuit board to connect a given number of I/O pins has been empirically determined and it can be generally expressed by the formula as follows: EMI11.1 Where M is a constant with certain values as follows: M = 3.0" per pin for two signal layers M = 3.5" per pin for four signal layers Ci = interconnect capacity, inches per square inch N = number of I/O pins within an area A = area available for routing in square inches. The interconnect capacity "Ci" for one signal layer using a 16 mil grid is, on the average, 30" per square inch. Thus, if we let the symbol K16 = 30" per square inch and let Ly = -K16 and Ly is the number of layers required to route a given number of pins in a given area. The concept of interconnect capacity, Ci, is illustrated in FIG. 5 to show that n 30 inches per square inch" means a board area of one square inch having 30 microstrip conductors. Thus, it is possible to determine how many layers Ly are required to route a 68 pin chip carrier on a routing area of 3.4 square inches. Interconnect Capacity EMI12.1 C. = 60 inches per square inch, and EMI12.2 Ly = 2 layers Thus, "two" signal layers are required to successfully route this chip in the particular area provided. It should be noted that as chips are placed closer together on a printed circuit board, the area for routing is decreased and thus "additional" signal layers must be provided in accordance with the above stated equations. The table shown below as Table I shows the minimum routing areas required for various packages using a 16 mil grid on both two and four layer signals. Reference to FIG. 6 will illustrate the 16 mil grid. TABLE I Note: This shows a minimum routine area required for 2 2 and 4 signal layers with a 16 mil grid (FIG. 6). EMI12.3 <tb> <SEP> 2 <SEP> Signal <SEP> 4 <SEP> Signal <SEP> % <SEP> of <SEP> Area <tb> <SEP> Layers <SEP> Layers <SEP> Saved <SEP> With <SEP> 4 <tb> <SEP> Routing <SEP> Routing <SEP> Area <SEP> Layers <SEP> Over <tb> <SEP> Pins/Package <SEP> Area <SEP> In2 <SEP> Area <SEP> In2 <SEP> Saved <SEP> 2 <SEP> Layers <tb> <SEP> 14 <SEP> 0.70 <SEP> 0.40 <SEP> 0.30 <SEP> 43% <tb> <SEP> 16 <SEP> 0.80 <SEP> 0.47 <SEP> 0. <SEP> 33 <SEP> 41% <tb> <SEP> X <SEP> 1 <SEP> 0.3' <SEP> in. <SEP> 18 <SEP> 0.90 <SEP> 0.53 <SEP> 0.37 <SEP> 41% <tb> <SEP> O4 <tb> <SEP> center <SEP> line <SEP> 20 <SEP> 1.00 <SEP> 0.58 <SEP> 0.42 <SEP> 42% <tb> <SEP> 24 <SEP> 1.20 <SEP> 1.04 <SEP> 0.16 <SEP> 13% <tb> <SEP> 016 <SEP> 0.6in. <SEP> 28 <SEP> 1.40 <SEP> 1.12 <SEP> 0.28 <SEP> 20% <tb> <SEP> ,?center <SEP> line <SEP> 40 <SEP> 2.00 <SEP> 1.68 <SEP> 0.32 <SEP> 16% <tb> <SEP> U <SEP> 68 <SEP> 3.40 <SEP> 1.98 <SEP> 1.42 <SEP> 42% <tb> 84 <SEP> 84 <SEP> 4.20 <SEP> 2.45 <SEP> 1.75 <SEP> 42% <tb> <SEP> 120 <SEP> 6.00 <SEP> 3.50 <SEP> 2.50 <SEP> 42% <tb> <SEP> U <SEP> 156 <SEP> 7.80 <SEP> 4.55 <SEP> 3.25 <SEP> 42% <tb> To estimate the number of packages a particular board style can accommodate, the total routing area of the packages must be compared to the available routing area on the printed circuit board. If, for example, it is required to know how many 16-pin "dips" (Dual In-Line Packages) can an electrical interface board accommodate with two signal layers using a 16 mil grid? Let us say the electrical interface board has 14 square inches of usable routine area. Now according to Table I, it can be seen that 16 pin "dips" require 0.8 square inches of routing area when using two signal layers. Number of 16-pin = Usable Area on Board packages Minimum Area Required for 16 Pins = 14 square inches 0.8 square inches = 17.5 = 18 approximately Thus; a board having 14 square inches of area and two layers of signal planes can accommodate 18 "dips" of 16 pins each. The limiting factor for board density may not always be the routability (which itself is limited by profile of the package) but also the power density that the board can dissipate in a given environment. However, using the above data, it is now possible to set design parameters for printed circuit boards to maximize the interconnect capability when knowing the available board area and the type of carrier components to be mounted on the printed circuit board. There has thus been described a multilayer printed circuit board which is capable of high density packaging in that the multiple number of signal conduction planes make it possible to interconnect a large quantity of electronic components; further, the configuration as to the placement and width of the signal conducting lines or layers in relationship to the spacing or width of the dielectric substance used thus makes it possible to design a configuration which provides an essentially 100 ohm characteristic impedance to all signal lines when they are referenced either to the voltage plane or to the reference plane. Thus, there is a constancy of signal fidelity and an absence of leakage or cross talk. While the above described embodiments show the specific usage of the invention, it is to be understood that these embodiments are merely illustrative of the various concepts involved in the subject disclosure and are not limited thereby but the invention is deemed to be embracive according to the following claims.

Claims: What is claimed is: 1. A multilayered printed circuit board 10 providing an essentially constant 100 ohm characteristic impedance between external and internal microstrip signal lines and internal voltage 14 and ground planes 13 said printed circuit board 10 comprising: (a) an internal conducting ground plane 13; (b) an internal conducting voltage plane 14; (c) a central dielectric substrate 20c separating said ground 13 and voltage planes 14; (d) an upper external signal plane 11 which includes: (dl) a plurality of microstrip signal lines; (e) a lower external signal plane 16 which includes: (el) a plurality of microstrip signal lines; (f) an upper dielectric substrate 20a separating said upper external signal plane 11 from said ground plane 3; (g) a lower dielectric substrate 20e separating said voltage plane 14 and said lower external signal plane 16; (h) wherein said upper 20a and lower dielectric substrates 20e have a planar thickness of 0.028 i 0.001 of an inch and a dielectric constant between 4.2-5.0; (i) and wherein said upper 11 and lower signal plane 16 microstrip signal lines have a width of 0.008 i 0.001 inch. 2. The multilayered printed circuit 10 board of claim 1, wherein said ground conducting plane 13 and said voltage conducting plane 14 are separated by a dielectric substrate 20c of 0.005 of an inch, having a dielectric constant in the range of 4.2-5.0. 3. The printed circuit board 10 of claim 1, which includes: (a) an upper internal signal plane 12 having a plurality of microstrip signal lines of 0.005 inch width; (b) a lower internal signal plane 15 having a plurality of microstrip signal lines of 0.005 inch width; (c) an upper dielectic substrate 20a separating said lower internal signal plane 12 from said ground plane 13; (d) a lower dielectric substrate 20e separating said lower internal signal plane 15 from said voltage plane 14; and (e) wherein said upper 20a and lower 20e dielectic substrate have a thickness of 0.025 i 0.0015 inch and dielectric constant in the range of 4.2 to 5.0. 4. The printed circuit board 10 of claim 1, which includes: (a) means 20c to interconnect said upper and lower external signal plane microstrip signal lines to said voltage 14 and ground planes 13 and also to connecting pins of components mounted on said board; (b) components mounted on said printed circuit board 10 having connecting pins connected to said means to interconnect 20c. 5. The printed circuit board 10 of claim 4, which includes: (a) means to connect said upper and lower internal signal plane (12, 15) microstrip signal lines to said voltage 14 and ground planes 13, said external signal plane 11 microstrip signal lines, and to connecting pins of components mounted on said printed circuit board 10; (b) components mounted on said printed circuit board 10 having connecting pins connected to said means to connect. 6. A multilayered printed circuit board 10 providing a 100 ohm characteristic impedance for TTL logic and having a top component plane 11 for connection and insertion of electronic components and having a bottom external connection plane 16 for effecting solder connections, said printed circuit board 10 comprising: : (a) a first plurality of external signal conduct ing lines on the top component plane 16 and a second plurality of external signal conducting lines on the lower solder plane of said printed circuit board 10 wherein each of said first and said second external signal lines have a width of 0.008 i .002 of an inch; (b) an internal ground plane 13 insulated from said first external signal lines 11 by a dielectric substrate having a thickness of 0.028 inches i 0.0015 inches and dielectric constant between 4.2-5.0; (c) an internal voltage plane 14 insulated from said second external signal line 12 by a dielectric substrate having a thickness of 0.028 inches f 0.0015 inches, and dielectric constant between 4.2-5.0. 7, The printed circuit board 10 of claim 6, wherein said board includes: (a) a first internal signal plane 11 and a second internal signal plane 12 wherein each said plane includes a plurality of microstrip signal lines having a width of 0.005 i 0.001 of an inch and wherein said first internal signal plane 12 is separated from said first external conducting signal lines 11 in said top component plane by a dielectric substrate 20a having a thickness of 0.003 i 0.001 of an inch, and dielectric constant between 4.2-5.0. (b) and wherein said second internal signal plane 15 is separated from said bottom connection plane 16 by a dielectric substrate 20a of 0.003 i 0.001 of an inch and dielectric constant between 4.2-5.0. 8. A multilayered printed circuit board 16 having six planes of conducting material separated by dielectric substrate of dielectric constant between 4.2-5.0, said circuit board comprising: (a) first and second external signal planes (11, 16) each of which include: (al) microstrip conducting lines of 8 mil thickness; (b) first and second internal signal planes (12, 15) each of which include: : (bl) microstrip conducting lines of 5 mil thickness; (c) an internal ground plane 13 separated by 28 mils from said first external signal plane 11 and by 25 mils from said first internal plane 12; (d) an internal voltage plane 14 separated by 28 mils from said second external signal plane 11 and by 25 mils from said second internal signal plane 11; (e) wherein said ground plane 13 and voltage plane 14 have a dielectric separation of 5 mils; (f) means on said first external signal plane 11 to mount and connect electronic components having connector pins; (g) means to connect any of said connector pins to any of said six planes of conducting material. 9. The printed circuit board 10 of claim 8, wherein the characteristic impedance between any microstrip conducting signal line on said first external signal plane 11 and said ground plane 13 is 100 ohms f 10%. 10. The printed circuit board 10 of claim 9, wherein the characteristic impedance between any microstrip conducting signal line on said second external signal plane 16 and said voltage plane 14 is 100 ohms i 10%. 11. The printed circuit board of claim 9, wherein the characteristic impedance between any microstrip conducting line on said first internal signal plane 12 and said ground plane 13 is 100 ohms i 10%. 12. The printed circuit board 10 of claim 10, wherein the characteristic impedance between any microstrip conducting line on said second internal signal plane 15 and said voltage plane 13 is 100 ohms t 10%. 13. A multilayered printed circuit board 10 for facilitating the efficient mounting and interconnectivity of dual-in-line packages and chip carriers, and for providing maximum interconnectability of the connecting pins of said packages and carriers, said printed circuit board comprising: (a) an external upper component plane 11 which includes: (al) a plurality of conductive land areas each having a central aperture 18 which extends through the multilayered depth of said printed circuit board 10 said central aperture 18 including: (ala) conductive walls for selectively connecting said land area to one or more conducting signal lines on said external upper component plane 11 and selected signal lines on one or more internal conduction planes; (alb) insulative wall areas for selec tively insulating said land area from selected signal lines in selected internal planes; and (alc) wherein said plurality of land areas are spaced to permit insertion of dual-in-line packages or chip carriers into said central apertures of said land areas; (aid) a plurality of microstrip conductive signal lines for selective connec tion to selected ones of said land areas; (b) an external lower plane 16 which includes: : (bl) a plurality of conductive microstrip signal lines each of which is selectively connected to or insulated from each of said central aperture walls; (c) an internal conducting ground plane 13 insulated from said external upper component plane 11 by a first dielectric substrate 20a; (d) an internal conducting voltage plane 14 insulated from said external lower plane 16 by a second dielectric substrate 20b; (e) a dielectric substrate 20 for insulating conductive planes of said printed circuit board and having a dielectric constant between 4.2 and 5.0, said substrate including: : (el) said first dielectric substrate 20a having a thickness of 28i 1.5 mils; (e2) said second dielectric substrate 20b having a thickness of 28 i 1.5 mils; (e3) a third dielectric substrate 20c of 5 mil thickness for separating said ground plane and said voltage plane. 14. The printed circuit board 10 of claim 13 wherein: (a) each of said microstrip signal lines in said external upper plane 11 and said external lower plane 16 are constituted of 8 mil width and 1.4 mil thickness conductors. 15. The printed circuit board 10 of claim 14, wherein each of said microstrip signal lines in said external upper plane 11 provides an essentially 100 ohm characteristic impedance with reference to said ground plane 14. 16. The printed circuit board 10 of claim 15, wherein each of said microstrip signal lines in said lower external plane 16 provides an essentially 100 ohm characteristic impedance with reference to said voltage plane. 17. The printed circuit board 10 of claim 16, which further includes: (a) an upper internal conduction plane 12 separ ated, by a third dielectric substrate 20c of 3 mils thickness, from said upper external plane 11, said upper internal conduction plane 12 including: (al) a plurality of microstrip conductive signal lines selectively connected to selected walls of said central apertures 18, wherein each of said microstrip signal lines are constituted of 5 mil width and 0.7 mil thick conductors: (b) said third dielectric substrate 20c having a dielectric constant between 4.2-5.0. 18. The printed circuit board 10 of claim 17, which further includes: (a) a lower internal conduction plane 15 separated, by a fourth dielectric substrate 20d of 3 mils thickness, from said lower external plane 12, said lower internal conduction plane 16 including: (al) a plurality of microstrip conductive signal lines selectively connected to selected walls of said central apertures 18, wherein each of said microstrip signal lines are constituted of 5 mil width and 0.7 mil thick conductors; (b) said fourth dielectric substrate 20d having a dielectric constant between 4.2-5.0. 19. The printed circuit board 10 of claim 18, wherein (a) each of said upper internal plane microstrip signal lines 11 provides essentially a 100 ohm impedance with reference to said ground plane 13 and (b) each of said lower internal plane 15 micro strip signal lines provides essentially a 100 ohm impedance with reference to said voltage plane 13. 20. The printed circuit board 10 of claim 19, wherein the space-area required for interconnectability for a chip carrier mounted on said upper external conductive plane 11 is reduced by approximately 42% over the space-area required for a two plane conductive external signal layer printed circuit board. 21. The printed circuit board 10 of claim 19, wherein the space-area required for interconnectability of a dual-in-line package having 0.6 inch distances between opposite side connecting pins and mounted on said upper external conductive plane 12 is reduced by at least 13% over the space-area required for two plane conductive external signal layer printed circuit board 10. 22. The printed circuit 10 board of claim 19, wherein the space-area required for interconnectability for a dual-in-line package having 0.3 inch distance between opposite-side connecting pins and mounted on said upper external conductive plane 11 is reduced by at least 418 over the space-area 18 required for two plane conductive external signal layer printend circuit board 10.

Inventors: BARROW, MICHAEL
Applicants: UNISYS CORPORATION
Application year: 1984
Main classification: H05K3
IPC codes: H05K1, H05K3, H01P3