SEMICONDUCTOR DEVICE HAVING A HETEROJUNCTION, AND METHOD FOR PRODUCING IT

Abstract: A semiconductor device including an FET using a two-­ dimensional electron gas (2DEG), comprising a substrate (1), a first semiconductor layer (2), typically an undoped GaAs layer, formed on the substrate (1), and a second semiconduc­ tor layer (8) typically an n-type AlGaAs layer. Lyers (2) and (9) are typically formed by molecular beam epitaxy. The device also includes a source electrode (10) and a drain electrode (11) formed on the second layer (9) and having alloyed regions (12, 13), and a gate electrode (14) formed on the second layer (9). To decrease the contact resistance between the alloyed reg­ ions (12, 13) and the 2DEG layer in the first layer (2), impurity doped regions (6, 7) are formed in the first layer (2) under the source electrode (10) and the drain electrode (11) by an ion-­ implantation method, prior to the formation of the second layer (9). An internal conductive line (27) or resistor (46) may be formed by doping impurities into the first layer (22 or 42) by an ion-implantation method prior to the formation of the second layer (28 or 47).

Description: The present invention relates to a method of producing a semiconductor device, more particularly an improved field effect transistor (FET) which comprises a compound semiconductor having a heterojunction and which can operate at a high speed using a two-dimensional electron gas (2DEG). An FET having a heterojunction and utilizing a 2DEG is disclosed in, for example, JP-A-57-7165, JP-A-57-176773, JP-A-57-180186, and EP-A-0064370. A main characteristic of the FET is high electron mobility due to accumulation of 2DEG at the heterojunction interface and decrease of the ionized impurity scattering effect. As the temperature of the FET is reduced, the lattice scattering effect is reduced and the mobility is further increased. With an FET of the gallium-arsenide (GaAs) type, however, there is a problem that the parastic source resistance Rs and the parasitic drain resistance Rd are relatively large, since, mainly, an aluminum-gallium-arsenide (AlGaAs) layer having a relatively high resistivity exists between a GaAs layer and source and drain electrodes. To improve the properties of the FET, it is necessary to decrease the source resistance Rs and drain resistance Rd. Accordingly, the source electrode and drain electrode are made of gold-germanium (AuGe) and are heated so that the AlGaAs layer and GaAs layer alloy with the AuGe. Thus, ohmic contact regions including a source region and a drain region and having a relatively low resistivity are formed under the electrodes. The contact resistance between the alloyed regions and the 2DEG layer is still, however, relatively large. IBM Technical Disclosure Bulletin, vol.24, No. 8, January 1982, L. L. Chang "Self-aligned MESFET structure", pages 4071 and 4072 describes a method of producing a semiconductor device having a heterojunction and using a two-dimensional electron gas, comprising the steps of: forming a first semiconductor layer on a substrate; forming a second semiconductor layer as an electron-supply layer having a smaller electron affinity than that of the first semiconductor layer above the first semiconductor layer; forming a source electrode and a drain electrode on the second semiconductor layer, the source and drain electrodes having alloyed regions extending to the first semiconductor layer through the second semiconductor layer. The teaching of this article forms the first part of claim 1. In this example the source and drain regions are formed by implanting impurities through the second layer into the first layer. According to this invention such a method is characterized by the step of forming impurity doped regions by doping impurities into the first semiconductor layer under the location of the source and drain electrodes before forming the second semiconductor layer, and by also forming another impurity doped region to serve as a conductive line or resistor by doping impurities into the first semiconductor layer, the other impurity doped region being connected with another source or drain electrode through the doped regions or to a contact electrode through a supplementary doped region, the contact electrode having an alloyed region extending to the first semiconductor layer. An advantage of the present invention is the reduction of the contact resistance between the alloyed regions and the 2DEG layer, so that the parasitic source and drain resistance are further reduced. This increases the operation speed of the FET and lowers the noise generated in the FET due to the reduction of the parasitic resistances. Various examples of methods in accordance with this invention will now be described with reference to the accompanying drawings; in which:- Figures 1a to 1e are schematic sectional views of a semiconductor device in various stages of production; Figure 2a is a schematic sectional view of a semiconductor device including two FET's and a conductive line; Figure 2b is a circuit diagram of the semiconductor device shown in Figure 2a; Figure 3a is a schematic sectional view of a semiconductor device including an FET and a resistor; Figure 3b is a circuit diagram of the semiconductor device shown in Figure 3a; Figure 4a is a circuit including two FET's and two resistors; Figure 4b is a plan of the semiconductor device shown in Figure 4a; and, Figures 5a and 5b are schematic sectional views of another semiconductor device including an FET. Referring to Figures 1a to 1e, an explanation will be made of a process for producing a semiconductor device of an FET utilizing the 2DEG layer. As illustrated in Fig. 1a, on 6 semi-insulating GaAs substrate 1, an undoped GaAs layer (i.e., a first semiconductor layer) 2 is formed by a molecular beam epitaxy (MBE) method. The GaAs layer 2 has a thickness of from 400 to 1000 nm, e.g., approximately 600 nm. A masking film 3 of silicon dioxide (SiO₂) silicon nitride (Si₃N₄), aluminum nitride (AlN), or the like is formed on the GaAs layer 2 by a chemical vapor deposition (CVD) method, a sputtering method, or a reactive sputtering method. As illustrated in Fig. 1b, the masking film 3 is selectively etched to open two windows 4 and 5 therein by means of a conventional lithography technique, such as a photoetching method. Through the windows 4 and 5, impurities such as silicon (Si) or (selenium) are doped into the GaAs layer 2 by an ion-implantation method to form two impurity doped regions 6 and 7. For example, Si impurities of 5 x 10¹³ cm⁻³ are doped at an ion energy of 150 keV. Then, the masking film 3 is removed by a suitable etchant. Annealing (heat-treatment) is necessary for recovering the damaged crystal of the doped regions. Since arsenic (As) tends to evaporate at a high temperature, as illustrated in Fig. 1c, a protective film 8 of SiO₂ , Si₃N₄ , or AlN is formed on the GaAs layer 2 by a CVD method, a sputtering method, or a reactive sputtering method prior to the annealing. For example, a protective film 8 of AlN having a thickness of approximately 0.1 µm is formed by the reactive sputtering method. The annealing is carried out by means of a heating furnace, e.g., at a temperature of 850°C for approximately 20 minutes or by a lamp annealing method using, e.g., a tungsten halogen lamp for an irradiation time of from 10 to 30 seconds. Lamp irradiation can heat the GaAs layer 2 to a temperature of from 950°c to 1000°c. After the annealing, the protective film 8 is removed by a suitable etchant. It is possible to carry out the annealing without the formation of the protective film 8 by using a decomposition of arsine AsH₃ contained in an atmosphere surrounding the semiconductor device to be annealed. Namely, during the annealing, a mixture gas of hydrogen (H₂), nitrogen (N₂), and AsH₃ is supplied into the heating furnace, wherein As decomposed from the AsH₃ at 600°C or more prevents As of the GaAs layer 2 from evaporating. In the case of lamp annealing, the mixture gas should be heated at 600°C or more near the semiconductor device by using a suitable heating means. It is also possible to carry out the annealing without the formation of the protective film 8 by using an MBE apparatus, in which an As molecular beam strikes the GaAs layer 2 during the annealing. After the annealing, the GaAs layer 2 is etched to remove a surface portion of, e.g., from 10 to 20 nm, by a wet etching method using sulfuric acid (H₂SO₄) or potassium hydroxide (KOH) or by a plasma etching method using an etchant gas such as CCl₄ , CCl₂F₂. The semiconductor device is then placed in an MBE apparatus, where the GaAs layer 2 is further cleaned under a high vacuum condition by etching of hydrogen chloride (HCl) gas or by sputtering of argon (Ar) or helium (He) gas so as to completely remove an undesirable oxide film. Next, as illustrated in Fig. 1d, an n-type AlGaAs layer 9 (i.e., a second semiconductor layer serving as an electron-supply layer) is epitaxially grown on the undoped GaAs layer 2 by an MBE method, so that the AlGaAs layer 9 and the GaAs layer 2 form a heterojunction. The AlGaAs layer 9 has a thickness of from 40 to 100 nm, e.g., approximately 80 nm, and is doped with Si impurities of a dose of, e.g., 1 to 2 x 10¹⁸ cm⁻³. As illustrated in Fig. 1d, a gold-germanium (AuGe) film and a Au film are continuously formed on the AlGaAs layer 9 by a conventional vacuum evaporation method and are patterned by a suitable method to form a source electrode 10 and a drain electrode 11 above the impurity doped regions 6 and 7, respectively. In order to alloy portions of the AlGaAs layer 9 and the doped regions 6 and 7 with the electrodes 10 and 11, heat-treatment is carried out at approximately 450°C for approximately 1 minute. Therefore, alloyed regions 12 and 13 are formed to attain ohmic contact between the alloyed regions and the 2DEG layer. Next, as illustrated in Fig. 1e, a gate electrode 14 forming a Schottky barrier with the n-type AlGaAs layer 9 is formed on the AlGaAs layer 9 by vacuum evaporation of a triple layer of titanium (Ti)/platinum (Pt)/Au or an aluminum (Al) layer and patterning treatment. The resultant FET utilizing the 2DEG has a source or drain contact resistance of from 10⁻⁶ to 10⁻⁷ Ωcm, which is smaller than the approximately 10⁻⁵ Ωcm of a similar FET of the prior art. Accordingly, it is possible to produce an FET having lower noise and higher operating speed as compared with prior art FET's. In the above-described device, the GaAs layer 2 is used as the first semiconductor layer and the AlGaAs layer 9 is used as the second semiconductor layer. However, if the electron affinity of the second semiconductor layer is larger than that of the first semiconductor layer and the lattice constant of the second semiconductor layer is equal or similar to that of the first semiconductor layer, GaAs, germanium (Ge), indium-antimonide (InSb), or indium-arsenide (InAs) may be used for the first semiconductor layer and AlGaAs, GaAs, cadmium-telluride (CdTe), or gallium-antimonide (GaSb) may be used for the second semiconductor layer. It is possible to use combinations of Ge (first layer) and AlGaAs (second layer), Ge and GaAs, InSb and CdTe, and InAs and GaSb in addition to the above-mentioned combination of GaAs and AlGaAs. According to the present invention, a conductive line or a resistor is connected with the FET described above by ion-implantation of impurities into the first semiconductor layer. This ion-implantation is carried out simultaneously with or independently from the above-mentioned ion-implantation for the formation of the impurity doped regions. As illustrated in Figs. 2a and 2b, a semiconductor device comprising two FET's having the heterojunction and utilizing the 2DEG and a conductive line connecting the two FET's is produced in the following manner. An undoped GaAs layer 22 is formed on a semi-insulating GaAs substrate 21 by an MBE method as explained in the above-described embodiment. Si impurities are selectively doped into the GaAs layer 22 to form impurity doped regions 23, 24, 25, and 26 for the two FET's and simultaneously form an Si doped region 27 between the regions 25 and 24 as the conductive line. In this case, a masking film (not shown) used in the ion-implantation has three windows: for the regions 23, 26 and the combined region of 25, 27, and 24. Then, after the annealing step and the cleaning of the surface of the GaAs layer 22, an n-type AlGaAs layer 28 doped with Si is formed on the GaAs layer 22 by an MBE method. Source electrodes 29 and 30 and drain electrodes 31 and 32 of AuGe/Au are formed on the AlGaAs layer. Heat-treatment for alloying is carried out to form alloyed regions 33, 34, 35, and 36 extending into the impurity doped regions 23, 24, 25, and 26, respectively. Then, gate electrodes 37 and 38 of Ti/Pt/Au or Al are formed on the AlGaAs layer. The obtained semiconductor device has the Si doped region 27 serving as an internal conductive line which connects the drain electrode 31 of one of the FET's and the source electrode 30 of the another FET. As illustrated in Figs. 3a and 3b, a semiconductor device of the present invention including a resistor is produced in the following manner. An undoped GaAs layer 42 is formed on a semi-insulating Ga As substrate 41 by an MBE method, as explained in the above-described embodiment. Si impurities are selectively doped into the GaAs layer 42 to form impurity doped regions 43, 44, and 45 by an ion-implantation method using a masking film in which three windows are opened. After removing the masking film, another masking film (not shown) is formed on the GaAs layer 42 and is selectively etched to open a window for the resistor. Then, Si impurities are doped into the GaAs layer 42 through the window to form an Si doped region 46 between the impurity doped regions 44 and 45 by an ion-implantaion method under suitable conditions for attaining a desired resistance of the resistor. After removing the other masking film, an annealing step and cleaning step are performed as mentioned in the above embodiment. Then, an n-type AlGaAs layer 47 doped with Si is formed on the GaAs layer 42 by an MBE method. A source electrode 48, a drain electrode 49, and a contact electrode 50 of AuGe/Au are formed on the AlGaAs layer. Heat-treatment for alloying is carried out to form alloyed regions 51, 52, and 53 extending into the doped region 43, 44, and 45, respectively. Then, a gate electrode 54 of Ti/Pt/Au or Al is formed on the AlGaAs layer. The obtained semiconductor device has the Si doped region 46 serving as an internal resistor. For example, in the case where a circuit of Fig. 4a comprises two of the circuits of Fig. 3b, a semiconductor device as illustrated in Fig. 4b is obtained. In this case, impurity doped regions A, B, and C are connected to metal lines L₃, L₄, and L₅ through alloyed regions D, E, and F, respectively. Impurity doped regions G and H are connected to a metal line L₁ through alloyed regions I and J, respectively. A resistor R₁ of an Si doped region is formed between the impurity doped regions A and G and another resistor R₂ of an Si doped region is formed beteween the regions C and H. A gate electrode of a metal line L₂ is located between the impurity doped regions A and B, and a gate electrode of a metal line L₅ is located between the impurity doped regions B and C. Although the surface of the GaAs layer is cleaned by etching in a conventional etching apparatus and further etching in an MBE apparatus, the interface (i.e., the heterojunction) quality of the GaAs layer and the AlGaAs layer grown at different stages by an MBE method in the cases of the above-mentioned embodiments is inferior to that of the GaAs layer and the AlGaAs layer which are consecutively grown by an MBE method. Accordingly, electron mobility of the 2DEG in the cases of the above-mentioned embodiments is inferior to that in the case of consecutive epitaxial growth. In order to prevent such deterioration, it is preferable to form a thin semiconductor layer of the same material as the GaAs layer (the first semiconductor layer) between the GaAs layer and the AlGaAs layer (the second semiconductor layer) before the formation of the AlGaAs layer and to epitaxially grow the thin layer and the second layer continuously without break of the vacuum. A semiconductor device of an FET utilizing the 2DEG and having low source and drain contact resistances and good electron mobility of the 2DEG is produced in the following manner. As explained in the above-mentioned embodiment with reference to Figs. 1a to 1c, the undoped GaAS layer 2 is formed on the semi-insulating GaAs substrate 1, the impurity doped regions 6 and 7 are formed in the GaAs layer 2, and annealing is carried out. Then, the protective film 8 is removed and the surface of the GaAs layer 2 is cleaned by etching in a conventional etching apparatus and further etching in an MBE apparatus. Next, as illustrated in Fig. 5a, a thin undoped GaAS layer 61 having a thickness of 5 to 20 nm is grown on the cleaned GaAs layer 2 by an MBE method using the same apparatus. Without breaking the high vacuum in the MBE apparatus, an n-type AlGaAs layer 62 is consecutively grown on the thin layer 61 by an MBE method. The AlGaAs layer 62 of the second semiconductor layer is doped with Si of a dose of, e.g., from 1 to 2 x 10¹⁸ cm⁻³, and has a thickness of e.g., 80 nm. As illustrated in Fig. 5b, a source electrode 63 and a drain electrode 64 of AuGe/Au are formed on the AlGaAs layer 62 above the impurity doped regions 6 and 7, respectively. Heat-treatment (approximately 450°C for 1 minute) is carried out so as to alloy portions of the AlGaAs layer 62, and thin GaAs layer 61, and the GaAs layer 2 with the metal of the electrodes 63 and 64. Thus, the obtained alloyed regions 65 and 66 extend into the impurity doped region 6 and 7, respectively. Then, a gate electrode 68 of Ti/Pt/Au or Al is formed on the AlGaAs layer 62. The obtained FET has a good heterojunction between the thin GaAs layer 61 and the n-type AlGaAs layer 62 and the 2DEG generates in the thin GaAs layer 61, so that the electron mobility of the 2DEG is not deteriorated. Since the thin GaAs layer 61 is very thin, the thin layer 61 does not substantially increase the series resistance. Therefore, the source and drain contact resistance can be sufficiently reduced. It is possible to combine a conductive line or a resistor formed in the GaAs layer 2 with the obtained FET in a similar manner to that illustrated in Figs. 2a and 3a. It will be obvious that the present invention is not restricted to the above-mentioned embodiments. For example, an n-type GaAs layer can be formed on the AlGaAs layer of the second semiconductor layer except for the portion on which a gate electrode is formed. Therefore a source electrode and a drain electrode should be formed on the n-type GaAs layer.

Claims: A method of producing a semiconductor device having a heterojunction and using a two-dimensional electron gas, comprising the steps of: forming a first semiconductor layer (2) on a substrate (1); forming a second semiconductor layer (9) as an electron-supply layer having a smaller electron affinity than that of the first semiconductor layer (2) above the first semiconductor layer (2); forming a source electrode (10) and a drain electrode (11) on the second semiconductor layer, the source (10) and drain (11) electrodes having alloyed regions (12, 13) extending to the first semiconductor layer (2) through the second semiconductor layer (9), characterized by the step of forming impurity doped regions (6, 7) by doping impurities into the first semiconductor layer (2) under the location of the source (10) and drain (11) electrodes before forming the second semiconductor layer (9), and by also forming another impurity doped region (27, 46) to serve as a conductive line or resistor by doping impurities into the first semiconductor layer (2), the other impurity doped region (27,46) being connected with another source or drain electrode (30,32) through the doped regions (24,25) or to a contact electrode (50) through a supplementary doped region (45), the contact electrode (50) having an alloyed region (53) extending to the first semiconductor layer. A method according to claim 1, also including the step of forming a thin semiconductor layer (61) of the same material as the first semiconductor layer (2) on the first semiconductor layer (2) before forming the second semiconductor layer (9, 62). A method according to claim 1 or 2 in which the step of forming the impurity doped regions comprises forming a masking film (3) above the first semiconductor layer (2); selectively etching the masking film (3) to open windows; doping the impurities (6, 7)into the first semiconductor layer (2) through the windows by an ion-implantation method; removing the masking film (3); and annealing the first semiconductor layer (2) including the impurity doped regions (6, 7). A method according to any one of the preceding claims, in which the masking film (3) is selectively etched to open another window for said another impurity doped region or in which the step of forming said another impurity doped region comprises forming another masking film above the first semiconductor layer; selectively etching said another masking film to open a window; doping the impurities into the first semiconductor layer through the window in said another masking film by ion-implantation; and removing said another masking film; inbetween the removing step and the annealing step. A method according to any one of the preceding claims, in which before the annealing step, a protective film (8) is formed above the first semiconductor layer (2) and is removed after the annealing step. A method according to any one of the preceding claims, in which during the annealing step, the exposed surface is contacted by a mixture of hydrogen (H₂), nitrogen (N₂) and arsine (AsH₃). A method according to any one of the preceding claims, in which the first semiconductor layer and the second semiconductor layer (9) are formed by molecular beam epitaxy. A method according to any one of the preceding claims, in which the first semiconductor layer (2) is gallium-arsenide, germanium, indium-antimonide, or indium-arsenide; and in which the second semiconductor layer (9, 62) is aluminum-gallium-arsenide, gallium-arsenide, cadmium-telluride, or gallium-antimonide.

Inventors: OKAMURA, SHIGERU
Applicants: FUJITSU LIMITED
Application year: 1984
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27