ELECTRONIC CONTACTS AND ASSOCIATED DEVICES

Abstract: High voltage electronic contacts (S, S′) and associated devices including TRIMOS (MOS TRlacs) devices connected in anti-parallel fashion between two terminals (S₁/S′₂, S₂/S′₁). Each electronic contact (S, S′) is controlled via a control ter­ minal (S₄) by two auxiliary electronic contacts (NA, NB) each able to establish a low or high impedance between the control terminal (S₄) and one of the two other terminals (S₁/­ S′₂, S₂/S′₁), the impedance conditions of these auxiliary con­ tacts (NA, NB) being opposed. A power protection circuit as­ sociated to the TRIMOS device allows the flow of a relative­ ly high current through the electronic contacts (S, S′) for the lower voltage range across it, and minimizes the power dis­ sipation in the contacts in the higher voltage range, i.e. when abnormally high signals are applied to the contact.

Description: The invention relates to electronic contacts enabling to establish a low or high impedance between a first and a second terminal under the control of a control signal applied between a third and a fourth terminal by a control signal source. Such electronic contacts or solid-state relays are for instance used in the Belgian patent BE-A-896 388 published on 07/10/1983 particularly relating to a controlled capacitive charge circuit enabling to positively or negatively charge a capacitance which, in accordance with the sign of this charge, opens or closes an electronic contact constituted by two DMOS transistors (e.g. shown in fig.4 thereof) in series opposition, in such a way that their drains respectively constitute the first and second terminals of the electronic contact while their gates are each tied to a same third terminal connected to one end of the capacitance and their sources both connected to a fourth terminal connected to the other end of the capacitance, with the possibility for the latter capacitance to be constituted by the parasitic capacitance between these paired third and fourth terminals. In such a way, by using transistors able to withstand relatively high voltages, one obtains an electronic contact which can be inserted in a circuit where one or the other polarity may appear at the first and second contact terminals. Indeed, when the polarity of the charge on the control capacitance for the contact is such that it does not offer a low resistance path, i.e. that the two transistors are blocked, the parasitic diodes which appear for this transistor state between the source and the drain are thus connected also in series opposition which maintains a high impedance whatever the polarity applied by the circuit in which the contact is inserted. One of the objects of the present invention is to enable the use of a more advantageous type of electronic contact able also to be controlled by the polarity of the charge of a capacitance, and particularly a solid-state device able to work with high breakdown voltages (300 Volts for instance) as envisaged in the above mentioned patent but which can only pass current in one direction while it can block voltages of one or the other polarity, the transistors of the above mentioned patent having inverse properties, i.e. they can conduct the current in one or the other direction but block only one voltage polarity. The general object of the present invention is to enable the use of such electronic contacts while avoiding a complication of the control circuit. According to the invention this object is achieved due to the fact that it comprises a first biassed electronic contact device connected between said first and second terminals and having an impedance controlling input constituted by said second and fourth terminals, a second biassed electronic contact device connected between said first and second terminals in anti-parallel with said first biassed electronic contact device and having an impedance controlling input constituted by said first and fourth terminals, a first auxiliary electronic contact device connected between said third and second terminals, and a second auxiliary electronic contact device connected between said third and first terminals, said first biassed and auxiliary electronic contact devices being able to be operated for one voltage polarity between said first and second terminals, and said second biassed and auxiliary electronic contact devices being able to be operated for the opposed polarity between said first and second terminals. In this way, depending on the voltage polarity between the first and second terminals and when a control signal is applied between the third and fourth terminals one of the two auxiliary electronic contact devices is operated thereby establishing a low impedance between the third terminal, on the one hand, and the first/second terminal, on the other hand, the other auxiliary contact device remaining in the high impedance condition. As a consequence a control signal applied between the third and fourth terminal is substantially also applied between the first/second terminal and the fourth terminal i.e. across the impedance controlling input of a biassed electronic contact device, thus bringing the latter in the low/high impedance condition. Thus a single control signal controls either one of two biassed electronic contact devices depending on the voltage polarity between the first and second terminals. Still another characteristic feature of the invention is that each of said first/second biassed electronic contact device is of the thyristor type comprising two control terminals to put the contact device in the low or high impedance condition respectively and connected to said second terminal by a respective one and other MOS transistor, said MOS transistors being of complementary conductivity type and having gates interconnected to said fourth terminal whilst the source of said one transistor and the drain of said other transistor are connected to said second/first terminal. A thyristor type device is a semiconductor device constituted by four layers of semiconductive material, i.e. PNPN. The end layers therof are respectively connected to the first and the second terminals whilst the two control terminals are conected to the intermediate layers of this device. Such an arrangement offers the advantage that two electronic contact devices of the thyristor type can be connected top against bottom as a triac and controlled with the help of the same control circuit and particularly that of the above mentioned patent using a positive or negative charge for a capacitance to close or open the electronic contact. Indeed, with the help of the auxiliary electronic contact devices, in accordance with the polarity of the voltage applied to the terminals of the electronic contact constituted by the two two biassed contacts connected in shunt opposition, it will automatically be possible to obtain a connection between a terminal of the control capacitance and the terminal of the main electronic contact having a given polarity. In this manner, the same capacitance charge circuit, i.e. the voltage doubler AC/DC converter described in the above mentioned patent, shall always be used to close or open that of the two polarized contacts which is effectively inserted in a load circuit and depending upon the polarity of the voltage appearing at the terminals of these contacts connected in shunt opposition. On the other hand, the advantage of thyristor electronic contacts able to be controlled in the indicated manner, and with respect to the DMOS transistors connected in series opposition as in the above mentioned Belgian patent, instead of the top against bottom connection proposed, is that the resistance for the closed condition of the contact is distinctly lower, i.e. below 10 ohms instead of 25 + 25 = 50 ohms. Moreover, for the thyristor solution, the necessary surface in an integrated circuit is reduced to one quarter. The present invention also relates to an electronic device forming part of a circuit including also a power source and a load, said device including means to limit the power dissipation therein. Such a device is already known, e.g. from the PCT patent application WO-A1-82/03733. Therein the power limiting means are designed to produce a current versus voltage or I/V characteristic which, starting from the origin, rises to a maximum current at a predetermined voltage, remains on that current until a maximum voltage is reached and then suddenly drops to a current substantially equal to zero. At the last breakpoint of this characteristic the power dissipated in the device is maximum (maximum current and voltage) and in some circumstances this may be inadmissible, e.g. in case the device is to be integrated in an electronic chip. An object of the present invention is to provide an electronic device of the above type, but having a reduced power dissipation. This object is achieved due to the fact that said power limiting means are designed to produce a current versus voltage characteristic for the device which, starting from the origin, crosses the load line of the device and thereafter tends to follow said load line towards the voltage axis without again crossing the load line defined by the short-circuit current through the device and the open-circuit voltage across it. The minimum of power dissipated in the device occurs in the working point thereof, i.e. the point where the I/V characteristic crosses the load line. Unwanted abnormal signals having various origins like lightning striking such a telephone circuit or main power supply accidentally connected to it could affect the characteristics of the circuit. Indeed, such signals are added to the normal signals generated by the power source so that the position of the load line is modified. The working point then moves along the part of the I/V characteristic crossing the load line. In case these unwanted abnormal signals become very large, the load line could be displaced in such a way that the working point reaches the upper end of that part of the I/V characteristic. This working point then becomes unstable and moves to higher voltages. Since the I/V characteristic then follows the load line the power dissipated in the device during this transition of the working point is reduced to a minimum. When the unwanted abnormal signals disappear the load line returns to the position initially mentioned and due to the fact that the part of the I/V characteristic following the load line does not cross the latter, the working point moves from the higher voltages to its initial position. This would not be the same if there was a crossing between that part of the I/V characteristic and the load line. Indeed, such crossing would create a working point distinct from the one mentioned above and affect the normal working of the electronic device. Another object of the present invention is to allow, for relatively small voltages, currents which are much larger than the short-circuit current to flow through the electronic device while keeping the advantages mentioned above for higher voltages. This object is achieved due to the fact that the part of said current versus voltage characteristic crossing said load line has a first portion extending, for voltages which are relatively much smaller than said open circuit voltage, to a current relatively much larger than said short-circuit current and a second portion joining said first portion to the part of the characteristic which follows the load line. The working point of the device may thus move along the first portion of the I/V characteristic so that the current in this device may reach said relatively large value for small voltages without activating the power limiting means. For higher voltage values the device operates as described above. Another object of the present invention is also to use such electronic contacts in telecommunication systems and particularly in telephone line circuits, in order to enable the accomplishment of various supervision and control operations, including the provision of a ringing current, functions which previously were generally accomplished by means of relay contacts even in central exchanges where the rest of the equipment was electronic. Thus, the invention is also related to a telecommunication system line circuit comprising a series impedance in each of the two line conductors and contacts on each side of these two impedances enabling to selectively connect their terminals towards the exchange or the line respectively or alternatively, towards auxiliary circuits. Such a system is to be found for instance in the article published on pages 316 to 324 of the IEEE Journal of Solid State Circuits of June 1983, and more particularly on page 317. It is seen there that the two series resistances serve to feed a telephone subscriber line and also to measure the voltage appearing across these resistances and this for supervision and control operations. On the exchange side of these resistors, a ringing current can be injected by means of the corresponding contacts and by measuring the voltages across the resistances one may thus supervise the ringing operation. On the other hand, on the other side of these resistors, the contacts on the side of the subscriber line enable to have access to busses to perform tests, either internal (towards the exchange and through the series resistors) or external towards the subscriber line. Until now, these contacts were generally realized by means of change over contacts of three relays which automatically implied that when the make part of the contact was closed in shunt towards one of the control circuits, the break part in series with one of the resistors was automatically open and vice versa. In accordance with another characteristic of the invention, these contacts are constituted by four pairs of electronic contacts, the first connecting the line to the impedances, the second connecting these to the exchange, the third connecting the impedances on the line side to a first auxiliary circuit and the fourth connecting them on the exchange side to a second auxiliary circuit. In accordance with yet another characteristic of the invention, only the first pair of electronic contacts is provided with power limiting means such as described above. In accordance with an additional characteristic of the invention, the eight electronic contacts which are always operated in pairs are additionally controlled in such a way that only eight combinations among the sixteen possible for the four pairs are permitted. In accordance with yet another supplementary characteristic of the invention, the control device of the four pairs of electronic contacts comprises a decoder able to be fed by three binary signals in parallel and providing four binary output signals to control the four pairs of electronic contacts, a binary selection circuit being additionally foreseen to enable or inhibit the decoder outputs and in this last case enable connections permitting to the four input binary signals to respectively control the four pairs of electronic contacts. In this manner, it becomes possible in particular to realize in the form of a single integrated circuit, not only a series of eight electronic contacts able to withstand relatively high tensions and operating in pairs, but also to control the operation of these electronic contacts either with the help of a code comprising only three binary elements, or directly by a signal corresponding to the pairs of electronic contacts. This versatility can yet be increased by the incorporation in such an electronic circuit of a clock enabling to operate the control circuits of the electronic contacts in a manner described in the above mentioned patent and thus avoiding to rely on a separate clock circuit. The invention will be best understood and other characteristics thereof appearing in the claims will be better outlined from the following detailed description of preferred embodiments to be read in conjunction with the drawings accompanying the description and which represent : Fig. 1, the circuit of an electronic contact in accordance with the invention; Fig. 2, the electronic contact control circuit of the above mentioned patent and modified in accordance with the invention; Fig. 3, that part of a telephone line circuit incorporating eight electronic contacts in accordance with the invention; Fig. 4, the whole of the circuits enabling to control the eight electronic contacts and shown solely in the form of a single block in Fig. 3; Fig. 5, an input protection circuit shown as a block in Fig. 4; Fig. 6, an electronic gate shown as a block in Fig. 4; Fig. 7, a double electronic gate controlled by clock pulses and shown as a block in Fig. 4; Fig. 8, the circuit producing the clock pulses and shown as a block in Fig. 4; Fig. 9, a first logic circuit used to realize the decoder shown as a block in Fig. 4; Fig. 10, a second logic circuit used in this decoder; Fig. 11, another embodiment of the circuit of an electronic contact of Fig. 1 including power protection circuits according to the invention; Figs. 12 and 13, current versus voltage characteristics of the power protection circuits of Fig. 11, the characteristics being not drawn at scale; Fig. 14, current versus voltage characteristics of the electronic contact shown in Fig. 11, the characteristic being not drawn at scale and Fig. 15, a fault indication circuit FC associated to the power protection circuits represented in Fig. 11 and also shown in Fig. 3. The electronic contact able to withstand relatively high tensions and shown in Fig. 1 can be part of an assembly of eight identical electronic contacts (Fig. 3) arranged as four contact pairs, the two contacts of a pair being always simultaneously open or closed, this combination being able to be used in a telephone line circuit and particularly as described in Belgian patent BE-896 468 published on 17.10.1983. Apart from the eight electronic contacts corresponding to that of Fig. 1 and the eight circuits for such contacts appearing in Fig. 2 which essentially corresponds to the controlled capacitive charge circuit of Belgian patent BE-896 388, Fig. 4 represents a decoder able to be activated either by three or by four binary signals. In the first case, the eight possible combinations of the three binary signals are decoded on four output terminals respectively used to control the four pairs of electronic contacts. In the second case, the enabling signal allows this time to the four input binary signals to be respectively applied to the four electronic gates while the same signal inhibits the decoder operation. Additionally, the circuit of Fig. 4 comprises at the decoder output a converter destined to produce appropriate signals for the capacitive charge circuit of Fig. 2 and this with the help of an oscillator producing complementary clock pulses. The five parts identified above, i.e. the electronic contacts, the control circuit, the decoder, the converter and the clock oscillator can be associated in a same integrated circuit combining a DCMOS low voltage logic and TRIMOS high voltage contacts. The manufacturing technique used can particularly employ the process described in the Belgian patent BE-897 139 published on 27.12.1983. The whole then provides four pairs of electronic contacts able to block in the two directions voltages of 300 Volts and having a dynamic resistance of 10 Ohms when they are conductive, the two terminals of each electronic contact floating with respect to the control circuit. The four contact pairs can be operated in accordance with the 16 possible combinations with the help of four binary signals or in accordance with eight predetermined conditions with the help of three binary signals. By returning to Fig. 1, it is seen that the electronic contact comprises two identical parts S and S' in such a way that only the first has been represented in detail. In function of the control signal, circuit S can present either a low or a high impedance between its two output terminals S₁ and S₂ to which are respectively connected the corresponding terminals S'₂ and S'₁ of S', the two circuits being thus connected in anti-shunt. This enables to operate them under three different conditions : both S and S' present a high impedance between their terminals, S presents a low impedance for one voltage polarity at the terminals of the contact while S' can also present this low impedance but for the other polarity. Circuit S is of the TRIMOS type constituted essentially by a transistor T₁ of the PNP type associated to a transistor T₂ of the NPN type so as to form a thyristor between terminals S₁ and S₂. Manufacture of such a device generally entails the appearance of a parasitic transistor T₃ of the PNP type which is connected in parallel with the first two. This thyristor combination is controlled by transistor N of the DMOS type associated to transistor P of the PMOS type and whose gates interconnected at the same terminal S₄ present a capacitance C towards terminal S₂ of the contact to which the drain of transistor P and the source of transistor N are connected. In this way, assuming that capacitance C has been charged positively at its terminal connected to the two gates of transistors P and N with respect to terminal S₂, and that on the other hand the voltage on terminal S₁ is more positive than that on S₂, transistor N becomes conductive which enables a current to flow from terminal S₁ towards terminal S₂ through transistor T₁ due to transistor N short-circuiting by its drain/source path the base of transistor T₁ to which this drain is connected, the emitter of T₁ being connected to S₁. The effect of this conductibility of T₁ is to pump current into the base of transistor T₂ which is directly connected to the collector of T₁ in such a way that T₂ which is of the NPN type begins to pump current into the base of T₁ which is directly connected to the collector of T₂ whose emitter is directly connected to S₂. In this way, by this cumulative action, the two transistors T₁ and T₂ are placed into a saturation mode offering a low impedance between S₁ and S₂. Transistor T₃ which is also of the PNP type as T₁, the basis and the emitter of these two transistors being respectively interconnected while the collector of T₃ is at the potential of S₂, becomes also conductive but as indicated, this concerns a parasistic element without influence on the main operation of the circuit. The biassed contact S offering a low resistance between S₁ and S₂ can now be put back into its high impedance condition with the help of a negative charge on capacitance C, this negative potential at the gates of transistors P and N with respect to S₂ now entailing conduction of transistor P which is of the PMOS type. While transistor N of the NMOS type has its drain connected to the base of T₁, the source of P is connected to the collector of T₁ is such a way that P draws current from the T₁ collector so that the T₂ base current become insufficient to maintain conductibility of this NPN transistor which, by cumulative effect, entails its blocking and that of T₁ and T₃, thyristor T 1/2 becoming non conductive. It will still be noted from Fig. 1 that the P and N substrates are connected to the N drain and to the P source respectively. The other S' contact shown solely in the form of a block in Fig. 1 operates exactly in the way described but this time under the control of a positive or negative charge on capacitance C' and more particularly at its terminal S₄ with respect to its terminal S'₂. But these operations of half contact S' will this time be produced when the polarity of the circuit in which the switches are inserted in anti-shunt is positive in S'₁ with respect to S'₂. To be noted that the realization of S/S' in a single integrated circuit entails a connection between the common base of T₁ and T₃ for the two contacts S and S'. As already indicated in Belgian patent No 896 388, capacitances such as C and C' can be constituted by parasitic capacitances, particularly those appearing at the gates of transistors P and N in the case of capacitance C. Both C and C' can be charged with a desired polarity by way of the control circuit shown in Fig. 2 and corresponding essentially to a version already described in the Belgian patent last mentioned. Indeed, transistors NA and NB which are both of the NMOS type are shown in Fig. 1 as having their sources directly connected to terminal S₃ while the drains of NA and NB are respectively connected to S₁ and S₂. On the other hand, the gate of NA is connected to S₂ while that of NB is connected to S₁. Such a circuit arrangement has as a consequence that if the potential of S₁ for instance is higher than that of S₂, that of S₃ cannot be outside this range and transistors NB and NA are conductive and blocked respectively which implies in fact that terminal S₃ is practically (0.7 Volt) connected to terminal S₂ and by referring to Fig. 2 it is seen that it is in fact capacitance C which is effectively connected between terminals S₄ and S₃ of the charging device shown in Fig. 2. The parasitic diodes between the source and the drain of transistors NA and NB, i.e. DA and DB such as shown in Fig. 1, are biassed in such a way that they play an analogous role by enabling terminal S₃ to align itself on the potential at terminal S₂ when the latter is less positive than that at terminal S₁. Of course, in view of the symmetry of the circuit constituted by transistors NA and NB, when the potential of S₂ is higher than that of S₁, the conditions are inversed and following the conductibility of NA or DA, terminal S₃ is this time practically connected to terminal S'₂ in such a way that in these circumstances it is capacitance C' which is effectively connected to output terminals S₄ and S₃ of the control circuit of Fig. 2. In this manner, a single control circuit can automatically close or open the half electronic contact S or S' depending on the polarity of the voltage applied between terminals S₁/S'₂ on the one hand and S₂/S'₁ on the other. As already indicated, the circuit of Fig. 2 is essentially described in Belgian patent No 896 388 and particularly in relation to Fig. 6 of this patent which is very similar to Fig. 2. The latter constitues an AC/DC converter in the form of a full wave cascade voltage doubler and fed in push-pull by clock pulses of complementary polarity. The polarity control of the circuit of Fig. 2 is effected by signal DC applied to series capacitance C₃ while the complementary clock signals CL and CL are permanently applied to the two other series input capacitances C₁ and C₂ respectively. In the same way as for the output capacitance C/C' (Fig. 1) present between terminals S₄ and S₂/S'₂, the three input capacitances are not necessarily constituted by discrete physical elements. The first voltage doubler rectifier is essentially constituted by a series capacitance C₁ followed by the series diode D₁, transistor P₁ of the PMOS type to reach shunt capacitance C/C' between terminals S₄ and S₃, the shunt diode of this voltage doubler being D₂ connected as indicated between the junction of C₁ and D₁ on the one hand and that of C₃ and of the gate of P₁ on the other. When the control potential DC applied to series capacitance C₃ corresponds to clock pulses CL applied to series capacitance C₂, it is the described charging circuit which is effective in ensuring a charge of capacitance C/C' in such a manner that the potential at terminal S₄ will be more positive than that at terminal S₃. In the inverse case, when control signal DC applied to series capacitance C₃ corresponds to clock pulses CL permanently applied to series capacitance C₁, the output capacitance C/C' will this time be charged with S₄ more negative than S₃, the elements of this voltage doubler now effective to negatively charge the shunt output capacitance being C₂, D₃, N₁ and D₄, corresponding to C₁, D₁, P₁ and D₂ respectively as shown in Fig. 2, transistor N₁ being of the NMOS type. As in Belgian patent No 896 388, the positive charging circuit using the conductibility of transistor P₁ is completed by transistor N₂ of the NMOS type whose drain is connected to S₃ and its source to capacitance C₂ by means of the series diode D₅, the gate of N₂ being connected to S₄. This connection thus permits to complete the return circuit for the positive charge by offering a path between the "ground" output terminal S₃ and the input "ground" terminal constituted by the right-hand electrode of series capacitance C₂. Similarly, upon a negative charge of the output capacitance between S₄ and S₃, the return path is this time effected by way of transistor P₂ of the PMOS type in series with diode D₆, these two elements corresponding to N₂ and D₅ respectively as indicated by the circuit which is practically identical to that of Fig. 6 of Belgian patent No 896 388 to the exception of diodes D₁ and D₃ which are this time to be found on the source side of transistors P₁ and N₁ respectively instead of being located on the drain side as in the prior patent. Another version of this circuit shown in Fig. 4 of this prior patent already put diodes D₁ and D₃ on the side of the sources of transistors P₁ and N₁, but in this circuit the gates of transistors P₂ and N₂ were interconnected in another circuit and not connected to the drains of transistors P₁ and N₁ (S₄) in such a way that diodes D₅ and D₆ were this time on the drain side of transistors N₂ and P₂. In the version of Fig. 2 on the other hand, the four diodes D₁, D₃, D₅ and D₆ are all located on the source side of the transistors to which they are associated in such a way that with the diodes D₂, D₄ and D₁₀, they are all arranged on the side of the three input capacitances C 1/2/3 . This last diode D₁₀ directly connects capacitances C₁ and C₃ in the same manner as in the prior patent and the Zener diodes D₇, D₈ and D₉ respectively in parallel on the output terminals S 4/3 and the source/drain path of transistors N₂ and P₂ are also connected in the same manner as previously. The integrated circuit IC which may incorporate eight electronic contacts as shown in Fig. 1 as well as eight control circuits as represented in Fig. 2, appears in the form of a block in Fig. 3 which essentially corresponds to a part of Fig. 1 of Belgian patent No 896 468 bearing on a line circuit for an electronic telephone system. As shown by Fig. 3, a subscriber line (not shown) can terminate on terminals LT₁ and LT₂, preferably through an overvoltage protection circuit such as that which is the object of Belgian patent No 896 468. By means of the first electronic contact S₁₁ part of integrated circuit IC, terminal LT₁ can be connected to series resistance R₁ and then by means of a second series electronic contact, i.e. S₂₁, to the SLIC circuit containing other elements of the electronic line circuit. The circuit between the second input terminal LT₂ and the SLIC circuit is exactly similar, S₁₂, R₂, S₂₂ corresponding to S₁₁, R₁, S₂₁ respectively. In addition to the series contacts enabling to connect the resistances between LT 1/2 and the SLIC circuit, these resistances can also be connected via four shunt contacts towards the test circuits TC (S₃₁ for R₁ and S₃₂ for R₂) on the subscriber side (LT 1/2 ) on the one hand and towards the ringing circuit RC (S₄₁ for R₁ and S₄₂ for R₂) on the exchange side (SLIC) on the other. Connections (not shown) going from the terminals of the feed resistors R 1/2 to SLIC enable the latter to supervise the potentials appearing across these resistors. The operation of the eight contacts is controlled from the SLIC through four conductors terminating on terminals IC 1/2/3/4 , the contacts of a pair such as S 11/12 being controlled by the same signals so that the two wires of the connection are switched simultaneously. The fourth conductor reaching IC₄ is however indicated in interrupted lines since this control can be effected in accordance with a control mode using only three binary signals, a mode selection signal applied to terminal IC₅ determining if three or four binary signals are used to control the four contact pairs S 11/12 , S 21/22 , S 31/32 and S 41/42 . This versatility of the IC circuit is based on the fact that the location of these four contact pairs, directly on each side of resistors R₁ and R₂ enables to ensure an adequate control with a number of connecting states which does not go beyond eight. Accordingly, when the four contact pairs of circuit IC are used for any application, line circuit or other, necessitating between 9 and 16 possible conditions for the combination of these 4 pairs in their open or closed conditions, each of the four binary signals at terminals IC 1/2/3/4 can directly control the state of a pair of contacts. On the other hand particularly in the case of the telecommunication line circuit which will be described further, one may be content with a maximum of eight conditions and the selection signal at terminal IC₅ will this time indicate that only the three binary signals at terminals IC 1/2/3 must be taken into consideration and the eight possible combinations of these signals will be transformed with the help of a decoder DEC into four binary signals each of which can control a pair of contacts. This appears in the form of a block in Fig. 4 which represents the constituting elements of circuit IC of Fig. 3, except the electronic contacts and their capacitive charge control circuits already described in relation to Figs. 1 and 2 respectively. In Fig. 4, each of the inputs IC 1/2/3/4/5 is coupled to the input of a corresponding inverter IV 1/2/3/4/5 and except in the case of IC₅ where the connection is direct, through identical protection circuit PC 1/2/3/4 , the PC₁ circuit being detailed in Fig. 5. The latter shows that input terminal IC₁ is directly connected to output terminal A, the input binary code for IC being identified by ABCD, the output terminals B, C, D corresponding to terminals IC 2/3/4 respectively. Input terminal IC₁ is connected to poles V₁ and V₂ of a DC source through diodes D₁₁ and D₁₂ respectively, these limiting the potential on IC₁/A between those applied in V₁ and V₂, this last potential, O Volt for instance, being more negative than that of V₁, 15 Volts for instance. On the other hand, transistor P₃ of the PMOS type has its source connected to V₁, its drain to A and its gate to V₂ in such a way that it is continuously conductive. Transistor T₄ shown in interrupted lines as being of the NPN type and having its collector connected to IC₁ and its emitter to V₂, can be used to bring a binary control signal to IC₁. If its base is at the potential of V₁, it is conductive and enables the current to pass from V₁ to V₂ through P₃ and T₄ in series. The impedance of the latter transistor being lower than that of P₃, terminal A stands at the potential of V₂. On the other hand, if the base of T₄ is at the potential of V₂ so as to block T₄, terminal A is at the potential of V₁ transmitted through P₃. Fig. 4 indicates that the four potentials (ABCD) at the outputs of PC 1/2/3/4 are applied to terminals such as D of a gate GD through inverters such as IV₄, in such a way that a complementary binary code A B C D appears at the inputs of these gates (gates identical to GD being foreseen for the signals at terminals A , B and C ) with respect to the binary code ABCD at the outputs of PC 1/2/3/4 . Three of these binary signals A B C are on the other hand applied to decoder DEC, as well as the two signals A and B complementary to A and B and obtained by inverters IV₆ and IV₇ in cascade with IV₁ and IV₂ respectively. Before explaining with the help of Figs. 9 and 10 how decoder DEC can advantageously transform the eight combinations of three binary signals ABC into particular combinations of four binary signals at its outputs E F G H , the description of the other elements of Fig. 4 will be completed, beginning with the above gate GD the output of which is connected to that of an identical gate GH fed by the H output of decoder DEC, three identical gates (not shown) being used and connected in like manner to outputs E F G . Gates such as GD and GH are controlled from terminal IC₅ determining the operation mode of IC, with or without decoding by DEC, the binary signal in IC₅ being applied to all the gates such as GD/GH as well as the complementary binary signal obtained by inverter IV₅. Fig. 6 shows the circuit of a transmission gate such as GD and GH which connects input terminal D or H to the output terminal DH by the source/drain path of transistors N₃ and P₄ connected in anti-shunt and which are of the NMOS and PMOS type respectively. Their gates are connected to IV₅ and IC₅ respectively for GD and vice versa for GH in such a way that one of these gates is conductive and the other blocked in function of the selection signal of IC₅ which does permit to choose for terminals such as DH, either signal D and part of a four binary element code each identifying a pair of contacts such as S 11/12 (Fig. 3), or the signal H , i.e. one of the four binary elements decoded by DEC from the three binary elements A B C . As indicated by Fig. 4, the signal at the terminal such as DH must still be synchronized by the gate such as GC with the clock pulses provided by oscillator CO to be applied, as well as the complementary clock signals CL and CL , to the three input capacitances C 1/2/3 of the AC/DC push-pull converter (Fig. 2) serving to positively or negatively charge capacitances C/C' controlling the biased electronic contacts S/S' connected in anti-shunt (Fig. 1). Fig. 7 represents the circuit of the clock gate. The binary signal at the terminal such as DH and determining the open or closed condition of the corresponding contact is this time applied to control gates GCA and GCB identical to those of Fig. 6 but to the inputs of which are applied the complementary clock pulses CL and CL used by oscillator CO. Gates GCA and GCB are controlled in complementary fashion by signal DH and its complement produced by inverter IV₉ in such a way that the output signal DC from gate GC is either a CL pulse or a complementary CL pulse in accordance with the value of the binary signal in DH. Fig. 8 represents the clock oscillator CO comprising the three inverters IV 10/11/12 connected in cascade in a loop comprising also the series resistances R₃ and R₄ on each side of inverter IV₁₁, the output of IV₁₂ feeding a second series of three inverters IV 13/14/15 in cascade the last of which provides the clock pulses CL and IV₁₄ the complementary pulses CL . Oscillator CO is also fed by voltages V₂ (not shown) and V₁, this last being connected to inputs of IV 11/12/13 through capacitances C 4/5/6 respectively. These can be of 6 picofarads and R 3/4 of 20 kohms to produce oscillations at a frequency of the order of 1.2 MHz. As indicated by multipling arrows in Fig. 4, oscillator CO feeds the four gates such as GC whose output terminal controls two charging circuits such as those of Fig. 2 to control a pair of contacts such as that of Fig. 1. This last connection is performed by inverter IV₈ providing the signal DC is such a way that the three signals arrive at the capacitances C 1/2/3 of Fig. 2 through the output impedance of an inverter. Decoder DEC of Fig. 4 will finally be described by referring also to Figs. 9 and 10 representing the type of logic circuits advantageously used for its realization. To this end one will first of all define the eight conditions of a telephone line circuit which can be characterized by a combination of the input signals ABC of the decoder DEC. These eight conditions are identified by the truth table which follows : The table comprises three columns corresponding to the input signals ABC, a fourth column for an intermediate Y signal whose usefulness will appear later, and four other columns E F G H defining the signals at the output of decoder DEC, each of these last columns corresponding, as indicated, to the state of a pair of contacts, e.g. E for S 11/12 . The complement bar on top of the references identifying these contacts corresponds to the complementary form of E F G H in such a way that the indication 0 identifies a closed contact for the columns at stake, with 1 for an open contact. The eight conditions for the line circuit appear in the successive rows in increasing order for the binary code from 000 to 111 for ABC, this last code corresponding to the switching through of the line circuit of Fig. 3, i.e. the series contact S 11/12 and S 21/22 are closed and the shunt contacts S 31/32 and S 41/42 are open. The fourth line gives the code 011 for ABC as ringing condition enabling to connect RC (Fig. 3) towards terminals LT 1/2 of the subscriber's line through resistors R 1/2 in such a way that the voltages on the latter can also be used for the supervision of the ringing operation of the called subscriber. The sixth line corresponds to code 101 for ABC and to an internal test (towards the exchange) enabling this time to connect the test bus of TC to the SLIC through resistors R 1/2 . On the other hand, the external test (towards the subscriber) of the fifth line (100 for ABC) produces a connection between TC and terminal LT 1/2 without passing through the resistors while the ringing test (001 for ABC) interconnects this time RC and TC through the resistors. Apart from these five conditions, the line circuit still enables complete isolation of the resistors (000 for ABC), ringing supervision (010 for ABC) where TC is additionally branched by S 31/32 on the above output connection and finally, a supervision (110 for ABC) where TC is also branched but this time on the normal connection. The eight ABC codes enabling these various conditions have been assigned to the eight contact combinations S 11/12 , S 21/22 , S 31/32 , S 41/42 as indicated by the table and this to enable as simple a realization as possible for DEC. Indeed, the correspondence table indicates that E = B and that F = A , except for ABC = 100, that G = 0 except for ABC = 000 and BC = 11, and finally that H = A except for ABC = 000. The realization of decoder DEC is facilitated by these simple correspondence relations and by the introduction of Y = 0 except for BC = 00, Y being an intermediate binary signal appearing at the fourth column of the table. Accordingly, one may write the corresponding Boolean relations : E = B ( A + C) = A B + B C F = A + Y = A + B C G = A Y + BC = A B C + BC H = A + Y = A + B C Y = B C or Y = B + C where the second expression for E (Fig. 9) will facilitate a comparison with G (Fig. 10) and those for F , G and H are obtained by replacing Y by the indicated value, that for Y corresponding more directly to the logic circuits used and more precisely a derivation of that of Fig. 10 for G . Fig. 9 represents the CMOS logic circuit enabling to realize E by using three PMOS transistors connected as indicated between potential V₁ and the output terminal giving function E , as well as three NMOS transistors connected as indicated between the output terminal and the potential V₂. The three transistors are identified by the signals A , B , C applied to their gates, as well for the PMOS as for the NMOS transistors. Their source/drain paths are connected in such a manner that B is in series with a parallel combination AC for the PMOS transistors while the duality of the circuit comprising the NMOS transistors implies that B should be in parallel with the series combination A C . Hence, signals A , B , C being respectively the complement of those intervening in the equation giving E , it is seen in particular that if B is at the low potential, the transistor B among the PMOS transistors is conductive while the corresponding NMOS transistor is blocked. If one forgets transistors A and C among the PMOS transistors by replacing them by a short circuit, while by duality, the NMOS transistors A and C are replaced by an open circuit, E would then be at high potential (V₁) which corresponds to E = B , this latter being the first factor of the expression defining E and a condition which, as previously indicated, is true for all the combinations of ABC except 100. But for this last combination, with A and C at the high potential and B at the low potential, the PMOS transistors controlled by A and C are thus both blocked while the corresponding NMOS transistors are both conductive. For this particular combination, E is thus at the low potential (V₂) which corresponds to E = B. For the seven other combinations, these four transistors A and C (PMOS and NMOS) are irrelevant because they cannot either short-circuit the blocked transistor B (NMOS) nor put the conductive B transistor (PMOS) in an open circuit in such a way that only B is relevant and that one has E = B . Fig. 10 represents the circuit enabling to realize G following principles identical to what has been outlined for Fig. 9, the second form given above for E enabling a direct comparison with the first for G . Indeed, it is readily seen that there are four independent variables A , B, C and Y for G instead of only three (A, B and C ) for E . In this way, four pairs of PMOS and NMOS transistors connected as indicated are this time necessary and one calls on the intermediate variable Y. To obtain the latter from B and C, as well as F and H from A and Y , and from A and Y respectively, it suffices each time to take half the circuit of Fig. 10, e.g. transistors B and C , both for the series PMOS transistors and for the shunt NMOS transistors by controlling them by appropriate signals, e.g. B instead of B and C instead of C to provide Y. In this manner, the whole of decoder DEC which only calls on the five signals A, A , B, B and C by economizing an inverter for C (Fig. 4), uses only 13 PMOS and 13 NMOS transistors. Reference is now made to Fig. 11 which shows the electronic contact S₁₁ of Fig. 3 in detail, this contact being a modification of the one represented in Fig. 1. While being still of the TRIMOS type, the thyristor TRX formed between the terminals S₁ and S₂ differs slightly from the one schematically represented in Fig. 1 in that the PNP transistor T₁ is now replaced by a PNP transistor Q₁ having two distinct collector electrodes respectively connected to the gate electrodes of two NPN transistors Q₂ and Q₃ substituting the NPN transistor T₂, transistor T₃ being not represented. Furthermore, individual power protection circuits which are described below in more detail are associated to TRX. To be noted that contact S₁₂ is identical to S₁₁ but that the other six contacts do not include power protection circuits. Electronic contact S₁₁ of Fig. 11 includes two identical switching circuits S and S' which are coupled in anti-shunt. More particularly, terminal S₁ of S is connected to terminal S'₂ of S', whilst terminal S₂ of S is connected to terminal S'₁ of S'. The control circuit mentioned above is connected to both S and S' via terminal S₄. The switching circuits S and S' are also each provided with a detection output terminal DT₁, DT₂ of which only DT₁ is connected to a fault indication circuit FC via detection terminal DET₁. FC is also included in the integrated circuit IC and will be described later. Because S and S' are identical only one of them, e.g. S is now considered. As already mentioned above, transistor Q₁ of the thyristor TRX has two distinct collector electrodes connected to the base electrodes of the transistors Q₂ and Q₃ respectively. The collector electrodes of the transistors Q₂ and Q₃ are both connected to the base electrode of Q₁. Terminal S₁ is connected to the emitter electrode of Q₁ and terminal S₂ is connected to the emitter electrode of Q₂ directly and to the emitter electrode of Q₃ via a sense resistor R₁₁. The base electrode of Q₂ is also connected to the collector electrode of an NPN transistor Q₄ whose emitter electrode is connected to the terminal S₂. Terminal S₁ is connected to the base electrode of Q₄ via the cascade connection of a diode D₂₁, the collector-to-emitter path of an NPN transistor Q₅ and a resistor R₁₂. The cathode of diode D₂₁ is also connected to the emitter electrode of Q₃ via the series connection of a resistor R₁₃, the drain-to-source path of an NMOS transistor N₁₁ and a resistor R₁₄. The junction point of resistor R₁₄ and the source electrode of N₁₁ is connected to the base electrode of an NPN transistor Q₆ whose collector electrode is connected to the base electrode of Q₃ and whose emitter electrode is connected to the terminal S₂. The cathode of diode D₂₁ is also connected to the drain electrode of an NMOS transistor N₁₂ whose source electrode is connected to the base electrode of Q₅ together with the detection output terminal DT₁. The gate electrodes of N₁₁ and N₁₂ are both connected to the drain electrode of a DMOS transistor N₁₃ having its source electrode connected to the terminal S₄ and its gate electrode connected to the terminal S₂. To be noted that the DMOS transistor N₁₃ has a parasitic diode (not shown) whose anode is connected to the source electrode of N₁₃ and whose cathode is connected to the drain electrode of this transistor, and that the NMOS transistors N₁₁ and N₁₂ have high gate capacitances (not shown). The thyristor TRX is turned ON and OFF by means of MOS transistors (not shown) corresponding to transistors P and N of Fig. 1, controlled via terminal S4. As already mentioned above, the switching circuit S includes power protection circuits which are also able to control TRX and the functioning of which will be described in detail hereinafter. The thyristor TRX is associated to two distinct power protection circuits, called primary and secondary power protection circuits respectively. The primary power protection circuit comprises the components D₂₁, N₁₂, Q₅, R₁₂ and Q₄, and more particularly limits the current through TRX when the voltage across the circuit S exceeds a predetermined value. The secondary power protection circuit comprises the components D₂₁, R₁₃, N₁₁, Q₆, R₁₄ and R₁₁. To be noted that in the following description of the operation of the protection circuits it is assumed that the voltage at terminal S₁ is positive with respect to the one at terminal S₂ so that diode D₂₁ is forwardly biased. The same functioning is valid for S' in case the voltage at S'₂ is positive with respect to the one at S'₁. The primary and secondary protection circuits are brought into and out of service by the respective NMOS transistors N₁₁ and N₁₂ which are themselves controlled by DMOS transistor N₁₃. When the thyristor TRX is in the ON-state, a positive control voltage of about + 20 Volts applied to terminal S₄ is transmitted to the gate electrodes of N₁₁ and N₁₂ via the parasitic diode of transistor N₁₃. As a result, the transistors N₁₁ and N₁₂ are conductive and the protection circuits are in service. To turn OFF the thyristor TRX, the control voltage at S₄ is decreased from its positive value of about + 20 Volts to a negative value of about - 20 Volts. During this voltage transition, TRX turns OFF when the voltage at S₄ reaches about - 3 Volts, whilst the protection circuits remain in service even when the parasitic diode of the DMOS transistor N₁₃ is blocked. Indeed, the NMOS transistors are then still conductive due to the positive voltage latched by their gate capacitance. When the voltage at S₄ reaches about - 8 Volts transistor N₁₃ becomes conductive so that this negative control voltage is applied to the gate electrodes of N₁₁ and N₁₂ and blocks them. The power protection circuits are then out of service. The transistor N₁₃ coupled to the gate capacitances of the transistors N₁₁ and N₁₂ thus constitutes a delay circuit which brings the protection circuits out of service a time interval after the blocking of TRX. Thus the protection of this device remains operative as long as TRX is in the ON-state. When TRX is in the ON-state, no current flows through the primary power protection circuit as long as the voltage across the switching circuit S does not exceed about three diode voltage drops. These three diodes are the diode D₂₁, the base-to-emitter path of transistor Q₅ and the base-to-emitter path of transistor Q₄. To be noted that the current flowing through the primary power protection circuit is so small that the voltage drop across resistor R₁₂ is negligible and that the voltage drop across the drain-to-source paths of conductive transistor N₁₂ is also negligible since this latter voltage drop is proportional to the base current of transistor Q₅ which is still blocked. When the voltage across S increases, transistor Q₄ becomes conductive and the collector current of Q₁ is drained from the base electrode of Q₂ to the terminal S₂. As the base current of transistor Q₂ is reduced, its collector current and, consequently, the base current of transistor Q₁ are also reduced. As a result, the portion Q₁/Q₂ of the thyristor TRX turns OFF whilst its portion Q₁/Q₃ may remain turned ON as will be described later. During the above operation the main current in the transistor Q₄ is limited by resistor R₁₂ and transistor Q₅ which is itself controlled by transistor N₁₂. Considering only the portion Q₁/Q₂ of the thyristor TRX, the current versus voltage characteristic of the switching circuit S would be the one represented in Fig. 12 where part 1 is the normal I/V characteristic of the forwardly biased thyristor TRX. As shown, the voltage V rises to a maximum voltage V D equal to the above mentioned three diode voltage drops (± 2,1 Volts) and corresponding to a maximum current I₁ of 320 milli-amperes. From the above it follows that, transistor Q₄ becomes active at the maximum voltage V D corresponding to the current I₁ so that TRX turns OFF following part 2 of the I/V characteristic shown in Fig. 12. The current in the thyristor TRX and therefore in the switching circuit S is then substantially equal to zero whatever the voltage across this circuit may be so that I/V characteristic then nearly coincides with the voltage axis for voltages exceeding V D . To be noted that this I/V characteristic is valid for the thyristor TRX as well as for the switching circuit S. The DC load line 3 of the switching device S is also represented in the diagram of Fig. 12. It is defined by two points corresponding respectively to the maximum current I L (70 milli-amperes) in the telecommunication line when the latter is short-circuited and to the maximum voltage V L (70 Volts) when this line is open. This DC load line 3 crosses part 1 of the I/V characteristic of the switching circuit S at a stable working point 4. When unwanted abnormal signals are applied to the telecommunication line they are added to the normal signals generated by the telecommunication exchange so that the load line moves in the I/V diagram of Fig. 12. Such abnormal signals may have various origins like lightning striking the telecommunication line or main power supply accidentally connected to these lines. The working point then moves along part 1 of the I/V characteristic. When these unwanted abnormal signals become very large, the load line could be displaced in such a way that the working point reaches the upper end of part 1 of the I/V characteristic. This working point then becomes unstable and moves to higher voltages whilst the TRX turns OFF (part 2). However, the maximum voltage V M across the switching circuit S is limited to about 250 Volts by the overvoltage protection circuit (not shown) mentioned above so that the working point is then located at point V M on the voltage axis. When the abnormal signals disappear the DC load line shifts back into the position drawn in Fig. 12 and the working point moves from V M (250 Volts) to V L (70 Volts) where the part of the I/V characteristic of TRX which coincides with the voltage axis crosses the DC load line 3. The working point thus becomes stable at that voltage V L and since the primary power protection circuit is then still active, it is impossible to turn ON the thyristor TRX. To allow TRX to be turned ON again, the part 2 and the part of an I/V characteristic of the switching circuit S coinciding with the voltage axis should not cross the DC load line 3 so that no stable working point such as V L should exist between V M and the normal working point 4. A solution is to use the secondary power protection circuit described hereinafter. Considering only this secondary power protection circuit, when the switching circuit S is in the ON state a current flows from S₁ to S₂ (Fig. 11) not only via TRX but also via diode D₂₁, resistor R₁₃, drain-to-source path of NMOS transistor N₁₁ and resistors R₁₄ and R₁₁ in series. As long as the voltage between the terminals S₁ and S₂ is relatively so small that the voltage drop produced by the above currents across R₁₁ and R₁₄ in series is smaller than the base-to-emitter saturation voltage V BE of Q₆ the latter remains blocked. The current I flowing through TRX then varies in function of the voltage V measured across the switching circuit S according to part 5 of the I/V characteristic shown in Fig. 13. To be noted that due to the values of the resistors which will be given later the current I (Fig. 11) flowing through TRX is much larger than the current flowing through the secondary protection circuit. Hence, the current I may be considered to be the current flowing through the switching circuit S and, as for Fig. 12, the I/V characteristic of Fig. 13 is valid for the thyristor TRX as well as for the switching circuit S. When the voltage between the terminals S₁ and S₂ is so large that the voltage drop produced across R₁₁ and R₁₄ in series by the above mentioned currents becomes larger than V BE of Q₆, the latter becomes conductive and thereby forms a shunt path to S₁ for the collector current of Q₁. Thus the base current of Q₃ is reduced as a result of which the impedance of TRX increases so that the current I flowing through it varies in function of V in the way represented by part 6 of the I/V characteristic of Fig. 13. This variation is function of the power dissipated in TRX because the voltage drop developped across the switching circuit S not only depends on I because R₁₁ is connected in series with TRX but also on V since an additional current which is function of V flows through R₁₁ via R₁₃ and R₁₄. Without R₁₃ and R₁₄ the current I would remain constant and be equal to the maximum current I₂ as shown by part 7 of the I/V characteristic of Fig. 13. In that case the power dissipated in the switching circuit S may become excessive since part 7 crosses the line of maximum power dissipation 8 of the circuit S. For the reasons mentioned above, part 6 of the I/V characteristic should not cross the DC load line 3. On the other hand, because the minimum power dissipated in the switching circuit occurs in the working point of this circuit, i.e. in the crosspoint of part 5 of the I/V characteristic and the DC load line 3, part 6 of the I/V characteristic should be chosen as close as possible to the DC load line 3 in order to obtain a minimum of power dissipation in the switching circuit S. Therefore, the slope of part 6 of the I/V characteristic is chosen similar to the slope of the DC load line 3. This slope is function of the ratio R₃/R₄. Indeed, when Q₆ starts conducting, its base-to-emitter saturation voltage V BE may be defined by the following expression : Where V and I are the voltage across and the current flowing through the switching circuit S respectively. This expression immediately leads to I.R₁₁.R₁₃ = V BE (R₁₁+R₁₄+R₁₃) - V(R₁₁ + R₁₄) according to the values of the resistances which are R₁₁ = 7.6 ohms R₁₂ = 500 ohms R₁₃ = 145 Kilo-ohms R₁₄ = 1 Kilo-ohms the following assumptions can be made R₁₃ >> R₁₄ >> R₁₁ the final expression is I.R₁₁.R₁₃ = V BE . R₁₃ - V.R₁₄ so that It appears clearly from this expression that the current I is dependent on the voltage Since part 6 of the I/V characteristic is chosen as close as possible to the DC load line 3 in order to limit the power dissipated in the switching circuit S the maximum current I₂ must be chosen slightly above I L and the maximum voltage V₂ must be chosen slightly above V L . In the present example and with the values of the resistors given above I₂ = 100 milli-amperes and V₂ = 100 Volts approximatively. However, according to requirements which are conventional for a telecommunication system the protection circuit should only be activated for a current exceeding 300 milli-amperes. If, for this reason I₂ is chosen higher than the required 300 milli-amperes part 6 of the characteristic should be shifted up and a portion of it may be located above the line of maximum power dissipation 8. In that case, when the power protection circuit becomes active, the power dissipated in S may be so large that the latter is destroyed. The drawbacks of the two power protection circuits taken separately may be eliminated by combining these two circuits, this combination providing the overall I/V characteristic of the switching circuit S represented in Fig. 14. This characteristic has part 1 and partially part 2 of the I/V characteristic related to the primary power protection circuit, and part 6 of the I/V characteristic related to the secondary power protection circuit. From this figure it appears clearly that the I/V characteristic crosses the above mentioned DC load line 3 at a unique stable working point 4 and that the power dissipated in the switching circuit S is reduced to its minimum since part 6 is very close to the DC load line 3. A fault indication circuit FC is shown in Fig. 15, FC has input terminals DET₁ and DET₂, terminals LT₁ and LT₂, output terminal F O and power supply terminals V DD (-33 Volts) and V SS (-48 Volts). The fault indication circuit FC is only associated to the protection circuit S of the switching unit S₁₁ (Fig. 11) and to the corresponding protection circuit of the switching unit S₁₂ (not shown). This is sufficient to detect abnormal signals of any polarity on the telecommunication line loop connected between LT₁ and LT₂. Input terminal DET₁ of FC is connected to the like named detection output terminal of the protection circuit S of the switching unit S₁₁ (Fig. 11), whilst input terminal DET₂ of FC is connected to the detection output terminal of the protection circuit corresponding to S of the switching unit S₁₂ (not shown). The terminals LT₁ and LT₂ of the fault indication circuit FC are respectively connected to the like named line terminals of the subscriber line. The output terminal F O of the fault indication circuit FC is connected to a digital signal processor or DSP circuit (not shown) which forms also part of the telecommunication line circuit. The fault indication circuit FC includes an NPN transistor Q₇ whose base electrode is connected to input terminal DET₁ via a resistor R₁₅ and whose emitter electrode is connected to terminal LT₁. The supply terminal V DD is connected to the collector electrode of Q₇ via resistor R₁₇ and diode D₂₂ connected in series. Another NPN transistor Q₈ has its base electrode connected to input terminal DET₂ via a resistor R₁₆ and its emitter electrode connected to terminal LT₂, whilst the junction point of resistor R₁₇ and diode D₂₂ is connected to the collector electrode of Q₈ via diode D₂₃. This junction point is also connected to the gate electrodes of an NMOS transistor N₁₄ and of a PMOS transistor P₁₁, the source electrode of P₁₁ being connected to V DD and the source electrode of N₁₄ being connected to V SS . The drain electrodes of P₁₁ and N₁₄ are both connected to the gate electrode of an NMOS transistor N₁₅ whose source electrode is connected to V SS via a resistor R₁₈. Output terminal F O is directly connected to the drain electrode of transistor N₁₅. The fault indication circuit FC works as follows. When no abnormal signal is detected by the power protection circuits of the switching circuits S of S₁₁ and S₁₂ or when these power protection circuits are out of service, the voltage at the input terminals DET₁ and DET₂ is not sufficiently positive, with regard to the respective terminals LT₁ and LT₂, to make their associated transistors Q₇ and Q₈ conductive. No current then flows through the diodes D₂₂ and D₂₃ and, consequently, through the resistor R₁₇ so that the voltage (V DD ) applied to the gate electrode of N₁₄ is more positive than the voltage (V SS ) at its source electrode. Transistor N₁₄ is thus conductive, whilst transistor P₁₁ is blocked since it has the same voltage (V DD ) at its source and gate electrodes. As a result, transistor N₁₅ is also blocked and no signal is transmitted to the output terminal F O . Alternatively, when an abnormal signal is detected by the power protection circuits of a switching circuit S a voltage, positive with respect to the one at terminal LT₁ (LT₂), appears at the input terminal DET₁ (DET₂) of FC. To be noted that the voltage at terminal LT₁ (LT₂) is more negative than the voltage at terminal V DD . The transistor Q₇ (Q₈) then becomes conductive and a current can flow from V DD to LT₁ (LT₂) via resistor R₁₇, diode D₂₂ (D₂₃) and the collector-to-emitter path of transistor Q₇ (Q₈). As a consequence, transistor N₁₄ blocks and transistor P₁₁ becomes conductive so that the voltage V DD appears at the gate electrode of transistor N₁₅ which becomes also conductive. The circuit N₁₅/R₁₈ then generates a current which is transmitted via terminal F O to the DSP circuit, the latter being able to take the appropriate actions. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims: Electronic contact (S/S') for establishing a low or high impedance between a first (S₁/S'₂) and a second (S₂/S'₁) terminal under the control of a control signal applied between a third (S₃) and a fourth (S₄) terminal by a control signal source (Fig. 2), characterized in that it comprises a first biassed electronic contact device (S) connected between said first (S₁/S'₂) and second (S₂/S'₁ ) terminals and having an impedance controlling input (S₄, S₂ /S'₁) constituted by said second (S₂/S'₁) and fourth (S₄) terminals, a second biassed electronic contact device (S') connected between said first (S₁/S'₂) and second (S₂/S'₁) terminals in anti-parallel with said first biassed electronic contact device (S) and having an impedance controlling input (S₄, S₁/S'₂ ) constituted by said first (S₁/S'₂) and fourth (S₄) terminals, a first auxiliary electronic contact device (NB) connected between said third (S₃) and second (S₂/S'₁ ) terminals, and a second auxiliary electronic contact device (NA) connected between said third (S₃) and first (S₁/S'₂) terminals, said first biassed and auxiliary electronic contact devices (S, NB) being able to be operated for one voltage polarity between said first (S₁/S'₂) and second (S₂/S'₁) terminals, and said second biassed and auxiliary electronic contact devices (S', NA) being able to be operated for the opposed polarity between said first and second terminals. Electronic contact according to claim 1, characterized in that said first (S)/second (S') biassed electronic contact device is of the thyristor type (T1/2) comprising two control terminals to put the contact device in the low or high impedance condition respectively, the control terminals connected to said second terminal (S₂/S'₁) by a respective one (N) and other (P) MOS transistor, said MOS transistors being of complementary conductivity type and having gates interconnected to said fourth terminal (S4) whilst the source of said one (N) transistor and the drain of said other transistor (P) are connected to said second/first terminal. Electronic contact according to Claim 1, characterised in that each of the biassed contact devices is an electronic device forming part of a circuit including also a power source and a load, said device including power limiting means (R₁₁; R₁₃, R₁₄;Q₆) designed to produce a current versus voltage characteristic (Fig. 13) for the device which, starting from the origin, crosses (5) the load line (3) of the device and thereafter tends to follow (6) said load line towards the voltage axis (V₂) without again crossing the load line defined by the short-circuit current (I L ) through the device and the open-circuit voltage (V L ) across it. Electronic contact according to Claim 3, characterised in that each electronic device includes switching means (Q 1/3 ) able to establish between first (S₁/S'₂) and second (S₂/S'₁) terminals a low or high impedance defined by said current versus voltage characteristic. Electronic contact according to Claim 4, characterised in that said power limiting means (R₁₁; R₁₃, R₁₄; Q₆) are associated to said switching means (Q 1/3 ) and comprise first sensing means (R₁₁) coupled in series with said switching means, second sensing means (R₁₃, R₁₄) coupled in parallel with said switching means and regulation means (Q₆) controlled by said first and said second sensing means and controlling said switching means so as to produce said current versus voltage characteristic. Electronic contact according to Claim 5, characterised in that said first (R₁₁) and second (R₁₃, R₁₄) sensing means are connected in series and that said regulation means include an active device (Q₆) with an input part coupled across said first sensing means and a portion of said second sensing means, and an output part connected to said switching means (Q 1/3 ). Electronic contact according to Claim 6 characterised in that said first sensing means include a resistor (R₁₁), said second sensing means include at least two resistors (R₁₃, R₁₄) connected in series and said regulation means include a transistor (Q₆). Electronic contact according to Claim 5, characterised in that said power limiting means (R₁₁; R₁₃, R₁₄; Q₆) are coupled to disconnection means (N₁₁, N₁₃) controlled by said control signal and able to bring said power limiting means into service and out of service after said switching means (Q 1/3 ) have established said high impedance. Electronic contact according to Claim 3, characterised in that the part (5) of said current versus voltage characteristic (Fig. 14) crossing said load line (3) has a first portion (1) extending, for voltages (V D ) which are relatively much smaller than said open circuit voltage (V L ), to a current (I₁) much larger than said short-circuit current (I L ) and a second portion (2) joining said first portion (1) to the part (6) of the characteristic which follows the load line (3). Electronic contact according to Claims 5 and 9, characterised in that it further includes second power limiting means (D₂₁, Q₅, R₁₂; Q₄) comprising third sensing means (D₂₁, Q₅, R₁₂; Q₄) for sensing the voltage across said electronic device (S/S') and second regulation means (Q₄) controlled by said third sensing means and controlling said switching means (Q 1/3 ) so as to produce said first (1) and second (2) portion of said current versus voltage characteristic. Electronic contact according to Claim 10, characterised in that said third sensing means (D₂₁, Q₅, R₁₂; Q₄) and said second regulation means (Q₄) include common first active device (Q₄) whose output part is connected to said switching means (Q 1/3 ). Electronic contact according to Claim 10, characterised in that said second power limiting means (D₂₁, Q₅, R₁₂; Q₄) are coupled to disconnection means (N₁₂, N₁₃) controlled by said control signal and able to bring said second power limiting means into service and out of service after said switching means (Q 1/3 ) have established said high impedance. Electronic contact according to Claim 4, characterised in that said switching means (Q 1/3 ) are constituted by a second (Q₁), third (Q₂) and fourth (Q₃) active devices, the first output terminals of the third and fourth active devices are coupled to the control terminal of the second active device, the second output terminals of the third and fourth active devices are coupled to said second terminal (S₂/S'₁), the first output terminal of the second active device is coupled to the first terminal (S₁/S'₂) and the second active device has two distinct second output terminals coupled to the control terminals of the third and the fourth active devices respectively. Electronic contact according to Claim 13, characterised in that said second active device (Q₁) is constituted by a PNP transistor whose control, first output and second output terminals are the base, emitter and collector electrodes respectively, and that said third (Q₂) and fourth (Q₃) active devices are each constituted by an NPN transistor whose control, first output and second output terminals are the base, collector and emitter electrodes respectively. Electronic contact according to Claim 2, characterised in that the two biassed contact devices (S/S') are associated to a controlled capacitive charge circuit comprising a source of push-pull AC signals connected by two serial input capacitances (C₁/C₂) to the input of a rectifying circuit (D₁, D₂, D₃, D₄) whose output is coupled to said fourth (S₄) and third (S₃) terminals, in that a third series input capacitance (C₃), having its input terminal coupled to the said source, has its output terminal also connected to the input of the said rectifying circuit which comprises a first (D₁, D₂) and a second (D₃, D₄) part respectively able to produce either a first or a second DC output polarity, enabling in this way the charge of an output capacitance (C/C'), appearing between said fourth terminal and said second/first terminal (S₂/S₁), to a first or a second polarity by control means (IC), in that the first and the second parts of the rectifying circuit are decoupled by first complementary MOS transistors (P₁, N₁) the gates of which are coupled to one third input capacitance (C₃) and include second MOS transistors (N₂, P₂) respectively complementary to the first, the two complementary transistors in the first (P₁, N₂) and the second (N₁, P₂) part being arranged on both sides of the output capacitance (C/C'), the second transistors having their gate coupled to the drain of the first transistor of the same polarity, the sources of the two transistors (P₁, P₂) of a first polarity (P₁, P₂) being each coupled to the first input capacitance (C₁) by a diode (D₁, D₆) and the sources of the two transistors of the second polarity (N₁, N₂) being each coupled to the second input capacitance (C₂) by a diode (D₃, D₅). Electronic contact according to claim 1, characterised in that said auxiliary electronic contact devices are constituted by two transistors of the same conductivity type, in that the first terminal (S₁) is coupled to the first output terminal of the first transistor (NA) and to the control terminal of the second (NB), in that the second terminal (S₂) is coupled to the first output terminal of the second transistor and to the control terminal of the first, and that the third terminal (S₃) is coupled to the second output terminals of the transistors. Electronic contact according to Claim 16, characterised in that the transistors are of the NMOS type. Telecommunication system line circuit comprising a series impedance (R₁; R₂) in each of the two line conductors and electronic contact (S₁₁, S₃₁; S₂₁, S₄₁; S₁₂, S₃₂; S₂₂, S₄₂) according to Claim 1 on each side of these two impedances enabling to selectively connect their terminals towards the exchange (SLIC) or the line (LT₁; LT₂) respectively or alternatively, towards auxiliary circuits (TC; RC), characterized in that these contacts are constituted by four pairs of electronic contacts, the first (S₁₁, S₁₂) connecting the line to the impedances, the second (S₂₁, S₂₂) connecting these to the exchange, the third (S₃₁, S₃₂) connecting the impedances on the line side to a first auxiliary circuit (TC) and the fourth (S₄₁, S₄₂) connecting them on the exchange side to a second auxiliary circuit (RC). Line circuit according to Claim 18, characterised in that the eight electronic contacts which are always operated in pairs are additionally controlled in such a way that only eight combinations among the sixteen possible for the four pairs are permitted. Line circuit according to Claim 19, characterised in that the eight closed and open combinations of the four pairs of contacts are defined by the eight binary codes 1111, 1100, 0100, 0110, 0101, 1001, 0001 and 0011 with the first, second, third and fourth digits from the left corresponding to the first (S 11/12 ), second (S 21/22 ), third (S 31/32 ) and fourth (S 41/42 ) pairs respectively, and the digits 0 and 1 indicating the closure and the opening of the contact pair respectively. Circuit comprising a plurality of electronic contacts according to Claim 1 able to be operated in accordance with different combinations by binary control signals, characterised by a decoder (DEC) included in the circuit and able to be controlled by at least a part of the signals (IC 1/2/3 ) to provide output binary signals to an arrangement of gates (CH) receiving also directly (CD) the binary control signals, a selection signal (IC₅) enabling to control the gates in such a manner as to respectively authorize and inhibit the flow of control and output signals or vice versa. Line circuit according to Claims 20 and 21, characterised in that the eight input (ABC) binary signals 000, 001, 010, 011, 100, 101, 110 and 111 controlling (IC 1/2/3 ) the decoder (DEC) respectively correspond to the eight combinations of binary output ( E , F , G , H ) binary signals 1111, 1100, 0100, 0110, 0101, 1001, 0001 and 0011 provided by the decoder. Line circuit according to Claim 22, characterised in that the decoder output binary codes are obtained in function of the input binary codes by five logic circuits respectively defined by the Boolean equations E = B ( A + C) F = A + Y C = AY + BC H = A + Y Y = B + C where Y is an intermediate signal and where A , B and Y are the complements of A, B and Y respectively. Circuit according to Claim 21, characterised in that the arrangement of gates (GH/GD) provides an output signal controlling two clock gates in opposition in such a manner that either one or the other transmits either a clock signal or its complement. Circuit according to Claim 24, characterised in that the clock signal and its complement are produced by a clock oscillator part of the same integrated circuit as the gate arrangement, the decoder, the electronic contacts and their control circuits. Telecommunication system line circuit comprising a series impedance (R₁; R₂) in each of the two line conductors (LT₁; LT₂) and electronic contacts (S₁₁, S₁₂; S₂₁, S₂₂) according to Claim 1 on each side of these two impedances enabling to selectively connect their terminals towards the exchange (SLIC) or the line (LT₁; LT₂) respectively, characterised in that these contacts are constituted by two pairs of electronic contacts, the first (S₁₁, S₁₂) connecting the line to the impedances and the second (S₂₁, S₂₂) connecting these to the exchange (SLIC), and that only said first pair of electronic contacts (S₁₁, S₁₂) is provided with power limiting means (R₁₁; R₁₃, R₁₄; Q₆) according to Claim 8. Telecommunication system line circuit according to Claim 26 , characterised in that said first pair of electronic contacts (S₁₁, S₁₂) is also provided with second power limiting means (D₂₁, Q₅ R₁₂; Q₄) according to Claim 13. Telecommunication system line circuit according to Claim 26 or 27, characterised in that it further includes detection means (FC) coupled to said first pair of electronic contacts (S₁₁, S₁₂) and able to provide a signal indicating that the voltage across at least one of said electronic contacts exceeds a predetermined value. Telecommunication system line circuit according to Claims 1 and 28, characterised in that said detection means (FC) include a detection circuit (R 15/18 , Q 7/8 , D 22/23 , P₁₁, N 14/15 ) with a first input part (R₁₅, Q₇) coupled to said first biassed contact (S) of the first electronic contact (S₁₁) of said first pair (S₁₁, S₁₂), a second input part (R₁₆, Q₈) coupled to said first biassed contact of the second electronic contact (S₁₂) of said first pair and an output part (Q 7/8 , D 22/23 , R₁₇) connected to an indication circuit (P₁₁, N 14/15 , R₁₈) also included in said detection means and which is able to provide at an output terminal (F O ) said indication signal which is function of the voltage across at least one of said biassed contacts (S). Telecommunication system line circuit according to Claim 29, characterised in that said first (R₁₅, Q₇) and second (R₁₆, Q₈) input parts of said detection circuit (R 15/18 , Q 7/8 , D 22/23 , P₁₁, N 14/15 ) are each constituted by the base and emitter electrodes of an NPN transistor (Q₇; Q₈) respectively coupled between said power limiting means and one of said terminals of said biassed contact (S), that said output part is constituted by the collector electrodes of said NPN transistors to which a first DC supply terminal (V DD ) is connected via a first resistor (R₁₇) in series with respective diodes (D₂₂; D₂₃), that said indication circuit (P₁₁, N 14/15 , R₁₈) includes a PMOS (P₁₁) and a first NMOS (N₁₄) transistors whose gate electrodes are both connected to the junction point of said first resistor (R₁₇) and said diodes (D₂₂, D₂₃), whose drain electrodes are interconnected and whose source electrodes are respectively connected to said first (V DD ) and a second (V SS ) DC supply terminals, and that said common drain electrodes of said PMOS and first NMOS transistors are connected to the gate electrode of a second NMOS transistor (N₁₅) whose source electrode is connected to said second DC supply terminal (V SS ) via a second resistor (R₁₈) and whose drain electrode is connected to said output terminal (F O ). Telecommunication system line circuit according to any of the Claims 26 to 30, characterised in that it includes third and fourth additional pairs of electronic contacts, the third (S₃₁, S₃₂) connecting the impedances (R₁; R₂) on the line side (LT₁; LT₂) to a first auxiliary circuit (TC) and the fourth (S₄₁, S₄₂) connecting them on the exchange side (SLIC) to a second auxiliary circuit (RC).

Inventors: REMMERIE, GUIDO, VAN DEN BOSSCHE, LUC J.L.
Applicants: ALCATEL N.V., BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE VENNOOTSCHAP
Application year: 1984
Main classification: H03K17
IPC codes: H03K17, H02H9, H04M19, H04M3