ON-THE-FLY MULTIBYTE ERROR CORRECTION

Abstract: In the multibyte error correcting system, up to t errors are correctable by processing 2t syndrome bytes. Syndrome bytes are converted into t+1 coefficients of the error locator polynomial by predetermined product operations and exclu­ sive-OR operations involving selected syndrome bytes to produce cofactors that correspond to the desired coefficients when less then t errors occurred in the codeword. The cofactors are combined to produce coefficients when t errors occur and the correct set of coefficients are selected in accordance with the number of errors that are detected. Up to t erroneous bytes in one codeword and corrected during its transfer from the system while the next codeword is entered in the system, so that correction is on-the-fly.

Description: Background of the Invention Field of the Invention This invention relates in general to error correction and, in the preferred embodiment to an error correcting system for correcting multibyte errors in a codeword in which the identity of the error locations and the identity of the error patterns are achieved simultaneously. Description of the Prior Art Most data storage subsystems associated with modern information handling systems employ some type of error correction system in order to obtain cost effective design for high reliability and data integrity. The ability of the data processing system to retrieve data from the storage system, i.e., access time, is a well recognized measure of the efficiency of the overall storage system. In most data processing systems, the decoding time for the error correction code is a direct factor in the total access time. As the capacity of storage devices has increased, the need for increased reliability and availability has also increased. As a result, the time required to process soft errors by the error correcting system becomes a larger percentage of the total access time. Multibyte error correcting systems suggested in the prior art require a relatively long time for decoding of the multibyte errors. This has been one of the main objections to their use in high performance storage systems. The following references disclose basic and significant aspects of prior art error correcting systems: 1. I. S. Reed and G. Solomon, "Polynomial Codes Over Certain Finite Fields", J. Siam, 8 (1960) p. 300-304. 2. R. C. Bose and D. K. Ray-Chaudhuri, "On a Class of Error Correcting Binary Group Codes", Information and Control, 3 (1960) p. 68-79. 3. A Hocquenghem, "Codes Correcteurs d'erreurs", Chiffres (Paris) 2 (1959) p. 147-156. 4. W. W. Peterson, "Encoding and Error Correction Procedures for the Bose-Chaudhuri Codes", IEEE Transaction Information Theory, 6 (1960) p. 459-470. 5. D. C. Gorenstein and N. Zierler, "A Class of Error-Correcting Codes in p m Symbols", Journal of Soc. Indus. Applied Math. 9 (1961) p. 207-214. 6. E. R. Berlekamp, "On Decoding Binary Bose-Chaudhuri-Hocquenghem Codes", IEEE Trans. Info. Theory 11 (1965) p. 577-579. 7. J. L. Massey, "Step-by-Step Decoding of the Bose-Chaudhuri-Hocquenghem Codes", IEEE Trans. Info. Theory 11 (1965) p. 580-585. 8. R. T. Chien, "Cyclic Decoding Procedure for the Bose-Chaudhuri-Hocquenghem Codes", IEEE Trans. Info. Theory 10 (1964) p. 357-363. 9. G. D. Forney, Jr., "On Decoding BCH Codes", IEEE Trans. Info. Theory 11 (1965) p. 549-557. 10. W. W. Peterson and E. J. Weldon, Jr., Error Correcting Codes , 2nd Edition (MIT Press, 1972). References 1, 2 and 3 provide a wide class of cyclic error correcting codes which are commonly known as Reed-Solomon Codes and BCH Codes. These codes, when defined over nonbinary or extended binary finite fields, can be used for correction of symbol errors as binary byte errors. References 4 and 5 provide the basic key to the solution of the multi-error decoding problem by suggesting the use of the "error locator polynomial". These references (4 and 5) suggest the use of a set of linear equations to solve for the coefficients of the error locator polynomial. References 6 and 7 suggest the use of an iterative method to compute the coefficients of the error locator polynomial. The roots of the error locator polynomial represent the locations of the symbols in error. Reference 8 suggests a simple mechanized method, the "Chien Search", for searching these roots using a cyclic trial and error procedure, while reference 9 provides further simplification in the computation of error values in the case of codes with non-binary or higher order binary symbols. The contribution of the error locator polynomial in references 4 and 5 was significant in that the roots of this polynomial represent the locations of the symbols in error for a multibyte error correcting system. The method of decoding multibyte errors in a multibyte error correcting system generally comprises four sequential steps: Step 1 - calculating of the error syndromes. Step 2 - determination of the coefficients of the error locator polynomial from the error syndromes. Step 3 - identifying the error locations from the error locator polynomial by "Chien Search". Step 4 - determination of the byte error values for each of the error loctions. All known methods for decoding multiple errors require completion of step 3 before beginning step 4. Because of that situation, prior art systems also require additional hardware to accumulate the results of step 3 for use subsequently by the hardware that implements step 4. References 6 and 10 provide good discussion on the prior art decoding methods. Summary of the Invention The present invention is directed to an error correcting system in which the problems of the prior art have been eliminated. GB-A-2 093 238 discloses, a system for correcting up to three bits in error in a, conceptually, bit serial word, protected by a BCH code, without generating error locator polynomials. Instead, plural values are calculated for each bit position in turn and bit inversion, or not, is performed depending on the current set of values. The values for each bit position are calculated using feedback shift registers and ROM look-up tables to provide functions of the full word syndrome values and current bit related powers of the selected primitive element of the appropriate GF. In the case of three error correction, a compound function of these functions is also used and the decision to use or not depends on the relationship of selected full word syndrome values. The variable times that would be required to perform the divergent calculations are smoothed out by the use of pre-calculations stored in the ROM tables. Thus, the full word syndrome values are generated as the word is received and buffered and are, in turn, buffered for repeated use during the correcting process. In theory, once the buffering is complete, a new full word could be received provided that the calculations can be done at a rate not slower than the bit reception rate. The patent is silent on this point, buffering of the full word syndrome values being performed because, being shift register generated, they are only available in the shift register at a single clock time and are changed at the very next clock. Clearly, this system does not suffer from the sequential step problem recited since step 2 is also avoided but it is not perceived how this arrangement could be applied to byte, rather than bit, correction. Given the need for data on both the identity and location of the errors, as is the case with byte correction, the above system appears not to be adaptable. Various systems are proposed for correcting errors "on the fly" and for operating on byte errors rather than bit errors. Attention is drawn to IBM Technical Disclosure Bulletin, Vol. 17, No. 2, July 1974, pages 473 to 475, wherein the current inventor discusses a multiple byte tape correction technique using hard and soft pointers and interleaved words. This prior art document however is essentially concerned with how sets of codewords are to be interleaved, and does not discuss decoding of individual codewords, which is the focus of the present invention. Speed of decoding, a major factor in approaching "on the fly" correction, was considered in the context of an SEC/DED Reed-Solomon code, in the 3rd USA-JAPAN Computer Conference, 1978, Session 11-1-1, and reported at pages 203 to 207 of the Proceedings thereof. Parallel decoding logic is proposed and the key comment is that the complexity and delay of the decoder is not impractical. There is no suggestion of an "on-the-fly" decoder. Accordingly, the invention provides an error correcting system, operable to correct up to a given number "t" of errors in a codeword, wherein each character is represented by a byte consisting of a unique combination of "b" binary bits, a codeword containing up to 2 b such characters including data characters and 2t check characters, the roots of the code generator polynomial being α a , α a+1 , ..., α a+2t-1 , where α is an element of the finite field of 2 b elements, by processing 2t syndrome bytes (S₀, S₁, ..., S 2t-1 ), each containing b bits, said system comprising syndrome generating means (6) for generating the 2t syndrome bytes, from which cofactor values Δ tm (m=0,1,2,...t) corresponding to predefined functions of the syndrome bytes can be produced, and characterised by further comprising: (a) means for generating the cofactor values Δ tm (m=0,1,2,..t) by parallel logic for 1 to t errors inclusive; whereby cofactor values Δ tt are formed using predefined functions of syndrome bytes corresponding to cofactor values Δ (t-1)m in accordance with the iteration equation (b) means responsive to said cofactor values Δ tm for 1 to t errors inclusive for selecting coefficient values Δ m according to the actual number of errors (ν) in said codeword such that wherein the coefficients Δ m are selected according to the actual number of errors, based on the non-zero cofactor Δ tt with the highest value of t; (c) means for generating individual error values E i for respective locations i by parallel logic from the syndrome bytes and said selected coefficient values Δ m , independently of the location and value of any other errors, where E i is defined by where and selectively applying to the codeword said generated error values E i at said respective character locations i when the following equation holds: and (d) clocking means for ensuring concurrent entry of an uncorrected codeword into said system and exit of a corrected codeword therefrom, thereby enabling "on the fly" correction of codewords in a continuous stream through said system. The invention also provides an error correcting method for an error correcting system, operable to correct up to a given number "t" of errors in a codeword, wherein each character is represented by a byte consisting of a unique combination of "b" binary bits, a codeword containing up to 2 b such characters including data characters and 2t check characters, the roots of the code generator polynomial being α a , α a+1 , ..., α a+2t-1 , where α is an element of the finite field of 2 b elements, by processing 2t syndrome bytes (S₀, S₁, ..., S 2t-1 ), each containing b bits, said method comprising the step of generating the 2t syndrome bytes, from which cofactor values Δ tm (m=0,1,2,..t) corresponding to predefined functions of the syndrome bytes can be produced, and characterised by further comprising the steps of (a) generating cofactor values Δ tm (m=0,1,2,..t) by parallel logic for 1 to t errors inclusive; whereby cofactor values Δ tt are formed using predefined functions of syndrome bytes corresponding to cofactor values Δ (t-1)m in accordance with the iteration equation (b) in response to said cofactor values Δ tm for 1 to t errors inclusive, selecting coeffient values Δ m according to the actual number of errors (ν) in said codeword such that wherein the coefficients Δ m are selected according to the actual number of errors, based on the non-zero cofactor Δ tt with the highest value of t; (c) generating individual error values E i for respective locations i by parallel logic from the syndrome bytes and said selected coefficient values Δ m , independently of the location and value of any other errors, where E i is defined by where and selectively applying to the codeword said generated error values E i at said respective character locations i when the following equation holds and (d) transferring bytes into and out of the system, and ensuring by clocking means concurrent entry of an uncorrected codeword into said system and exit of a corrected codeword therefrom, thereby enabling "on the fly" correction of codewords in a continuous stream through said system. It must be noted that the formulae given above merely indicate the mathematical basis of the invention, rather strictly specify the actual calculation steps followed. As an example of this, the denominator in the expression for E i involves a sum of Δ m for (m = odd), whereas in one embodiment (see Fig 6 below) the same sum is made with (m = even). Mathematically these two calculations have exactly the same effect. Many other manipulations of the above formulae will be readily apparent to the skilled man for performing the required calculations, which must of necessity be mathematically equivalent to the formulae given above and so be encompassed by the present invention. In accordance with the present invention, an error correcting system is provided in which steps 3 and 4 of the decoding procedure for multibyte errors are completed simultaneously. In particular, the location and value of each error are computed in cyclic order without explicit information regarding the location of the remaining errors which are yet to be determined. Step 3, which involves the "Chien Search" function is expanded into a complete mechanization of the error correcting procedure, and as a result, data characters in the codeword can be transferred from the error correcting system to the data processing system one at a time in synchronism with each cycle of the Chien Search. The access time to the first byte of data is, therefore, not impacted by the time required for the identification of the error locations and development of the error values of the errors. The hardware of the error correcting system is also highly simplified since the results of step 3 which normally had to be stored no longer need to be stored. The same set of hardware obtains the error values and the correction for all errors at the appropriate cycle during the Chien Search even when the actual number of errors is less than the designed maximum. Such an arrangement was only possible in prior art single symbol correcting codes. The improved system also avoids all division operations in obtaining the coefficients of the error location equation when the syndrome processing unit and the error pattern processing circuits of the present invention are employed. The situation where less than a maximum number of errors are present in the code word results in additional simplification of the hardware which becomes important when the circuitry of the error correcting system is being implemented in very large scale integration. The simplification is important in that when the circuitry has been implemented in VLSI to operate with 2t input syndrome bytes, the same VLSI circuitry can be used in environments which provide less than 2t input syndrome bytes. It is therefore possible to provide a multibyte error correcting system which has a minimal effect on the access time of an associated data storage system. It is further possible, to provide a multibyte error correcting system in which the transfer of the codeword from the error correcting system is initiated prior to the time that the identity of all the error locations is known and to provide a multibyte error correcting system in which the location and error pattern of each byte of the codeword that is in error is simultaneously identified as bytes are being transferred from the error correcting system so that errors are corrected on-the-fly. There is disclosed hereinafter an ECC system which is operable to correct any number of errors up to the maximum number for which it has been designed so that the same hardware may be employed to correct less than the maximum number of errors in one application or, alternatively, employed with a different application which employs a fewer number of check bytes and syndrome bytes. Only one inverse operation is involved in developing the error patterns. The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings. Brief Description of the Drawings FIG. 1 is a block diagram of a multibyte error correcting system embodying the present invention; FIGS. 2 and 3 are schematic diagrams of the syndrome processing unit shown in FIG.1 for developing the error locator coefficients of the error locator polynomial; FIG. 4 is a schematic logic diagram of the logic for generating the coefficients for the error value expression; FIG. 5 is a schematic diagram of the circuitry for implementing the error search, determination of the error value, and delivery of data with on-the-fly correction of the erroneous bytes; and FIG. 6 is a schematic diagram constituting a modification of the circuitry shown in FIG 5 in which the order of delivery of the codeword bytes is the reverse of that shown in FIG 5. Description of the Preferred Embodiment A description of the system shown in FIG. 1 will first be provided. The description of the syndrome processing logic for identifying error locations and the method of operating the logic will then be followed by a mathematical explanation and proof of the manner in which the logic has been implemented. This explanation will describe in mathematical terms the operation of the error correcting system for the general case of any number of errors. FIG. 1 shows the block diagram of an on-the-fly ECC system. The syndrome processing unit develops the coefficients for the error locator equation. The correcting process of the FIG. 1 system is continuous. An uninterrupted stream of data enters and leaves the decoder in the form of a chain of n-symbol codewords, hence the name, on-the-fly decoding. From a practical viewpoint, a given decoding process can be considered on-the-fly if it meets the following test, namely, the corrected data bytes of a previously received codeword are delivered to the user system while the data bytes of the following codeword are being received. The decoder, comprising blocks 6, 7, 8, 9, computes syndromes for the incoming codeword as it decodes and corrects errors in the previously received outgoing codeword. Each clock cycle corresponds to an input of one data symbol of the incoming codeword concurrent with an output of one corrected data symbol of the outgoing codeword. A buffer 5 holds at least n-symbols of the uncorrected data in between the incoming and outgoing symbols. A three-error correcting Reed-Solomon Code in GF(2⁸) is used as an example of special interest for applications in computer products. The 256 elements of GF(2⁸) are conventionally represented by the set of 8-bit binary vectors. One such representation is given in Table 1. In a three-error correcting Reed-Solomon code, there are six check symbols corresponding to the roots α⁰, α¹, α², α³, α⁴, α⁵ of the generator polynomial where α is an element of a finite field GF(2⁸) and is represented by an 8-bit binary vector. The corresponding syndromes computed by block 6 are denoted by S₀, S₁, S₂, S₃, S₄, and S₅ respectively. These syndromes are computed from the received codeword in the conventional manner in accordance with any known prior art process. The implementation for this step is well known and makes use of exclusive-OR circuits and shift registers. The details of the block 7 logic circuits are shown in FIGS. 2 and 3. The overall function of the block 7, shown in FIGS. 2 and 3, is first to implement the following four equations in FIG. 2 to develop the locator parameters Δ₃₃, Δ₃₂, Δ₃₁ and Δ₃₀ for the three error case, which also includes the parameters Δ₂₂, Δ₂₁ and Δ₂₀ for the two error case where, for example, the subscript 33 identifies one of four parameters. From these locator parameters, the coefficients Δ₃, Δ₂, Δ₁ and Δ₀ are selected by the logic shown in FIG. 3 in accordance with the exact number of errors that are involved in the particular codeword. The equations for Δ₃₃, Δ₃₂, Δ₃₁ and Δ₃₀ are as follows: Δ₃₃ = S₂ (S₁ S₃ + S₂ S₂) + S₃ (S₀ S₃ + S₁ S₂) + S₄ (S₁ S₁ + S₂ S₀) (1) Δ₃₂ + S₃ (S₁ S₃ + S₂ S₂) + S₄ (S₀ S₃ + S₁ S₂) + S₅ (S₁ S₁ + S₂ S₀) (2) Δ₃₁ = S₀ (S₄ S₄ + S₃ S₅) + S₁ (S₃ S₄ + S₂ S₅) + S₂ (S₃ S₃ + S₂ S₄) (3) Δ₃₀ = S₁ (S₄ S₄ + S₃ S₅) + S₂ (S₃ S₄ + S₂ S₅) + S₃ (S₃ S₃ + S₂ S₄) (4) These parameters are used to determine the coefficients of the error locator equation (17). The error locations and error patterns are then determined by the blocks 8 and 9 of the "on-the-fly" system shown in FIG. 1. The details of block 7 are shown in FIG. 2 and 3. The combinatorial logic shown in FIG. 2 includes two basic logic blocks 10 and 11. The first block 10, represented by an X, corresponds to a product operation in GF(2⁸) involving two 8-bit binary vectors, while the second block 11 represents a sum operation in GF(2⁸) involving two 8-bit binary vectors. The operation of block 11 is a simple bit-by-bit exclusive-OR logical function using eight 2-way exclusive-OR gates. The product operation, on the other hand, represented by block 10 is more complex and involves 76 exclusive-OR circuits and 64 AND circuits. The need for the 76 XOR circuits and 64 AND circuits may be seen from the following explanation of the product function of block 10. The product operation of block 10 involves two 8-bit vectors A and B to produce a third vector C where A = [a₀, a₁, a₂, a₃, a₄, a₅, a₆, a₇] B = [b₀, b₁, b₂, b₃, b₄, b₅, b₆, b₇] C = (c₀, c₁, c₂, c₃, c₄, c₅, c₆, c₇] The product is obtained through a two step process. First, compute the coefficients f i of the product polynomial F where F = A x B, modulo 2. Computation of the coefficients f i (i = 0, ... 14) requires 64 AND gates and 49 EX-OR gates: Second, reduce the polynomial F, modulo p(x), where p(x) is a primitive binary polynomial of degree 8. Use p(x) = 1 + x³ + x⁵ + x⁷ + x⁸ . The reduction of f i modulo p(x) requires at the most 22 EX-OR gates. C₀ = f₀ + f₈ + f₉ + f₁₀ + f₁₂ + f₁₃ C₁ = f₁ + f₉ + f₁₀ + f₁₁ + f₁₃ + f₁₄ C₂ = f₂ + f₁₀ + f₁₁ + f₁₂ + f₁₄ C₃ = f₃ + f₈ + f₉ + f₁₀ + f₁₁ C₄ = f₄ + f₉ + f₁₀ + f₁₁ + f₁₂ C₅ = f₅ + f₈ + f₉ + f₁₁ C₆ = f₆ + f₉ + f₁₀ + f₁₂ C₇ = f₇ + f₈ + f₉ + f₁₁ + f₁₂ The implementation of the product process involves one 2-input AND-gate for each product term required for the coefficient f₀ through f₁₄ and a 2-input exclusive-OR gate for combining the outputs of the AND-gates. Each block 10, therefore, represents 64 AND-gates, 71 exclusive-OR gates. The first term of the error locator polynomial S₂(S₁, S₃ + ○ S₂, S₂) of the Δ₃₃ equation is implemented by dashed block 16 in FIG. 2. The output of block 16 is exclusive-ORed in gate 18 with the second term of the equation and the result exclusive-ORed in gate 19 with the last term of the equation. The blocks involved in developing each of the other parameters Δ₃₂, Δ₃₁ and Δ₃₀ may be traced in a similar manner in FIG. 2. The parameters Δ₂₂, Δ₂₁ and Δ₂₀ for the case when only two errors occur are cofactors in equation (1) for Δ₃₃. These cofactors are: Δ₂₂ = S₁ S₁ + S₂ S₀ (5) Δ₂₁ = S₀ S₃ + S₁ S₂ (6) Δ₂₀ = S₁ S₃ + S₂ S₂ (7) In FIG. 2, the computations for Δ₂₂, Δ₂₁ and Δ₂₀ are shown as the interim byproducts within the computations for Δ₃₃. Similarly, Δ₁₁ and Δ₁₀ are cofactors in equation (48) for Δ₂₂ which are given by Δ₁₁ = S₀ (8) Δ₁₀ = S₁ (9) It is shown later in the specification how the equations for developing locator parameters are derived from the following prior art relationship of the error locator polynomial with the syndromes. FIG. 3 illustrates the logic for selecting the coefficients of the error locator polynomial from the locator parameters Δ₃₃ through Δ₃₀ and the cofactors Δ₂₂ through Δ₁₀. The FIG. 3 logic functions to identify the number of errors from the input parameters Δ₃₃ through Δ₃₀ and the cofactors Δ₂₂ through Δ₁₀ and select the appropriate value Δ m in the general equation When Δ₃₃ is non-zero, indicating the presence of three errors, the coefficients Δ₃ through Δ₀ will assume the values Δ₃₃ through Δ₃₀. As shown, when Δ₃₃ is non-zero, the output of AND-gate 41 is low, permitting the Δ₃₂, Δ₃₁ and Δ₃₀ signals to be gated through AND-gates 42, 43 and 44 respectively since the output of AND-gate 41 is inverted at the input to each gate 42-44 to enable each of the AND-gates. A similar logic function is achieved by Δ₂₂ if Δ₃₃ is zero indicating not more than two errors are present. In such a situation, Δ₂, Δ₁ and Δ₀ will take the values of Δ₂₂, Δ₂₁ and Δ₂₀ respectively through the operation of AND-gates 51, 52 and 53 respectively. This function corresponds to the syndrome equation for two errors. The logic circuitry of FIG. 3 functions similarly if Δ₂₂ is also zero to cause Δ₁ and Δ₀ to assume the values of Δ₁₁ and Δ₁₀. AND-gates 61 and 62 gate Δ₁₁ and Δ₁₀ respectively through OR-gates 71, 72 if Δ₃₃ and Δ₂₂ are both zero since AND-gate 60 provides the enabling signal. The overall logic of FIG. 3, therefore, functions to produce or to select the correct values of the coefficients Δ₃ , Δ₂, Δ₁ and Δ₀ for the error locator equations from the locator parameters developed by the logic of FIG. 2. The hardware for developing the coefficients Φ of the error value equation which is expressed as follows will now be described. The error value equation for the generic case is developed later in the specification. The general equation can be converted to the specific three byte error correcting system set forth in the drawings such that the coefficients may be defined as Φ₀ = Δ₀S₀ (13) Φ₁ = Δ₂S₁ + Δ₃S₂ (14) Φ₂ = Δ₃S₁ (15) The logic circuitry of FIG. 4 in effect implements the above three equations and comprises two basic logic blocks 110 and 111. Block 110 functions to provide the product function of the two 8-bit vectors and is identical to block 10 described earlier in connection with FIG. 2. Block 111 is a sum function of two 8-bit vectors and is identical to block 11 described earlier in FIG. 2. With the error value coefficients Φ and the error location coefficients Δ being developed, the circuitry of FIG. 5 is employed to mechanize the trial and error systematic search, i.e., the Chien Search, for the actual error locations and error patterns. The circuit of FIG. 5 functions to implement the error value equation when that equation is rewritten as As shown, FIG. 5 comprises four feedback shift registers 120-0, 120-1, 120-2 and 120-3 which receive the error location coefficients and three feedback shift registers 130-0, 130-1 and 130-2 which receive the three error pattern coefficients. The block labelled 120 implements the following equation Δ₃α 3i + Δ₂α 2i + Δ₁α i + Δ₀ =  for iε{I} (17) while block 130 implements the numerator of equation 16. The denominator of equation 16 is developed by the inverse block 140 from the output of exclusive-OR gate 125 which is one term developed for equation 17 The function and details of the inverse block 140 are discussed further on in the specification. The output of the exclusive-OR gate 127 functions through AND-gate 128 to provide an indication of an uncorrectable error condition which, depending on the length of the codeword, would occur in some cases if the number of errors exceeds the designed correction capability of the code. The product block 145 multiples the two 8-bit vectors in a manner identical to product blocks 110 and 10 described earlier and comprises 76 exclusive-OR gates and 64 AND-gates, each of which are 2-input gates. The output of product block 145 is the error pattern E i supplied to AND-block 146 comprising eight 2-input AND-gates. The error pattern vector E i supplied to gate 146 is supplied to exclusive-OR block 147 only when the error locator logic indicates that the output of exclusive-OR block 127 is zero. The other input to exclusive-OR block 147 is from buffer 4. As shown in FIG. 5, a clock signal C is supplied to the shift registers and buffers so that the bytes of data in error are each supplied to exclusive-OR block 147 at the appropriate time determined by the recognition that the error is located as indicated by a zero at the output of exclusive-OR block 127, thereby signifying that the output of the product block 145 contains the correct error pattern for that byte position. The operation of the FIG. 5 circuitry is as follows. The computed values of the coefficients Δ₃, Δ₂, Δ₁ and Δ₀ and Φ₂, Φ₁ and Φ₀ are entered into the appropriate shift registers at clock 0 time. Each clock cycle generates a shifting operation of these registers. A shifting operation multiplies the contents of each register by a specific constant, namely α₃, α₂ and α , in the case of the shift registers for Δ₃, Δ₂, and Δ₁ respectively and α₂ and α in the case of registers of Φ₂ and Φ₁ respectively. At the i th clock cycle, the upper set of exclusive-OR circuits 121, 125 and 127 in FIG. 5 at the output of shift registers 120 are presented with all the terms of equation 17. When the sum is 0, equation 17 is satisfied and one error location is identified. Similarly, at the i th clock cycle, the lower set of exclusive-OR circuits 131, 132 at the output of shift registers 130 are presented with all the terms of the numerator in equation 16. The denominator for equation 16 is readily available, as mentioned previously, from exclusive-OR circuit 125. Block 140 for an inverse operation and block 146 for the product operation compute the error pattern E i for each position in accordance with equation 16. The algebraic inverse in GF(2⁸) can be obtained through combinational logic which maps each 8-digit binary sequence into a specific 8-digit binary sequence. This mapping requires, at the most, 304 two-terminal AND-gates and 494 two-terminal OR-gates. The method of developing the inverse is shown later on in the specification. When the error location is identified, data character from buffer 4 is modified by E i through the output-sum network 146-147. For all other values of i, the computed value of E i is ignored since AND-gate 146 is closed. When all bytes of the codeword are delivered (at the final clock cycle c), if an error location was not identified in spite of nonzero syndromes, then there are too many errors. The latch 156 and AND-gate 157 indicates this with an UE (uncorrectable error) signal. The corrected bytes in the decoder of FIG. 5 are delivered in the order B₀, B₁, B₂, ..., B c-1 . This is the reverse order compared to that in the encoding operation since the check bytes correspond to the low-order positions. This reversal can easily be removed by introducing a reversal relationship between clock cycle count j and the byte location number i by substituting (c-J) for i in the decoding equations 17 and 16 and rewriting them as (Δ₃ α 3c ) α -3j + (Δ₂ α 2c )α -2j + (Δ₁α c ) α -j + Δ₀ = 0 (18) In these equations, j represents the clock cycle count, and j=1 to c, successively, correspond to the byte-position values i = (c-1) to 0. This provides delivery of bytes in the order B c-1 , ..., B₁, B₀, which is the same as that in the encoding process. To accomplish the above-mentioned modification, the following changes are made in the logic of FIG. 5: (1) the shift register multipliers α³, α², and α are replaced by α⁻³, α⁻², and α⁻¹, respectively; (2) the coefficients Δ₃, Δ₂, Δ₁, Φ₂, and Φ₁ are premultiplied by the constants α 3c , α 2c , α c , α 2c , and α c , respectively. These premultiplication circuits depend on the value of c and each requires a small number of exclusive-OR gates. Note that when c = 255, this premultiplication is not needed since α²⁵⁵ = 1. The modified logic described above appears in FIG. 6. The following is the mathematical derviation for the equations used in the logic implementation of FIGS. 2 and 3. In the three-error correcting Reed-Solomon Code in GF(2⁸) there are six check symbols corresponding to the roots α⁰, α¹, α², α³,α⁴, α⁵ of the generator polynomial. The corresponding syndromes are denoted by S₀, S₁, S₂, S₃, S₄ and S₅ respectively. We assume that, at the most, three symbols are in error. The error values are denoted by Ei₁, Ei₂ and Ei₃ and the locations of erroneous symbols are denoted by i₁, i₂ and i₃. Then the relationships between the syndromes and the errors are given by Consider the polynomial with roots at α i1 , α i2 and α i3 . This is called error locator polynomial, given by Substituting x = α i in (2A) we get α 3i + σ₂ α 2i + σ₁ α i + σ₀ = 0 for i = i₁, i₂ and i₃ . (3A) From equations (1A) and (3A), we can derive the following relationship between the syndromes S j and the coefficients σ i of the error location polynomial. We can solve Equation (4A) and obtain σ₀, σ₁ and σ₂ as where Δ₃₃, Δ₃₂, Δ₃₁ and Δ₃₀ are given by Δ₃₃ = S₂ (S₁ S₃ + S₂ S₂) + S₃ (S₀ S₃ + S₁ S₂) + S₄ (S₁ S₁ + S₂ S₀) (6A) Δ₃₂ = S₃ (S₁ S₃ + S₂ S₂) + S₄ (S₀ S₃ + S₁ S₂) + S₅ (S₁ S₁ + S₂ S₀) (7A) Δ₃₁ = S₀ (S₄ S₄ + S₃ S₅) + S₁ (S₃ S₄ + S₂ S₅) + S₂ (S₃ S₃ + S₂ S₄) (8A) Δ₃₀ = S₁ (S₄ S₄ + S₃ S₅) + S₂ (S₃ S₄ + S₂ S₅) + S₃ (S₃ S₃ + S₂ S₄) (9A) If the value of Δ₃₃ is 0, then Equation (4A) is a dependent set which implies that there are fewer than three errors. In that case, the syndromes will be processed for two errors Where the parameters Δ₂₂ , Δ₂₁ and Δ₂₀ are derived from similar equations for the case of two errors and are given by Δ₂₂ = S₁ S₁ + S₂ S₀ (10A) Δ₂₁ = S₀ S₃ + S₁ S₂ (11A) Δ₂₀ = S₁ S₃ + S₂ S₂ (12A) Note that these are cofactors of Δ₃₃ as seen from Equation (6A) which can be rewritten as Δ₃₃ = S₂ Δ₂₀ + S₃ Δ₂₁ + S₄ Δ₂₂ (13A) Thus, the values Δ₂₂, Δ₂₁ and Δ₂₀ for the case of two errors need not be computed separately. They are available as byproducts of the computation for Δ₃₃. Similarly, Δ₁₁ and Δ₁₀ for the case of one error are given by Δ₁₁ = S₀ (14A) Δ₁₀ = S₁ (15A) which are cofactors of Δ₂₂ and are also readily available as syndromes. Let v denote the exact number of errors, which may be 3, 2, 1 or 0. The exact number of errors is determined as follows: v = 3 if Δ₃₃ ≠ 0 v = 2 if Δ₃₃ = 0 and Δ₂₂ ≠ 0 v = 1 if Δ₃₃ = Δ₂₂ = 0 and Δ₁₁ ≠ 0 v = 0 if Δ₃₃ = Δ₂₂ = Δ₁₁ = 0 (16A) The special cases of two and one errors can be accomodated automatically by selecting appropriate determinants. To this end, let Δ₃, Δ₂, Δ₁ and Δ₀ be defined as Δ₃ = Δ₃₃ (17A) Then equation (5A) can be rewritten as Conventionally, the error locator polynomial (3A) with the coefficients σ₀, σ₁ and σ₂ of equation (21A) is used to determine error locations through the well known Chien search procedure. However, the error locator equation can be modified in order to avoid the division by Δ v . The modified error locator equation is given as Δ₃ α 3i + Δ₂ α 2i + Δ₁ α i + Δ₀ = 0 (22A) The error location numbers are the set of v unique values of i which satisfy Equation (22A). Next an expression is derived for the error values E i1 , E i2 and E i3 . From Equations (1A) for j = 0, 1 and 2 Solving (23A) for E i1 From Equation (2A) σ₀ = α i1 + i2 + i3 (25A) σ₂ = α i1 + α i2 + α i3 (26A) From Equations (24A), (25A) and (26A) Using Equation (5A) Equation (27A) can be reduced to Notice that the error value E i1 in Equation (28A) is expressed in terms of i₁ and hence it can be computed without explicit values for i₂ and i₃. The other error values E i2 and E i3 have similar expressions. A more general expression for error value is obtained by rewriting Equation (²⁸A) with a running variable i in place of i₁ as follows: where the coefficients Φ₀, Φ₁ and Φ₂ are given by Φ₀ = S₀ Δ₀ (30A) Φ₁ = S₁ Δ₂ + S₂ Δ₃ (31A) Φ₂ = S₁ Δ₃ (32A) The Equation (29A) makes it possible to combine the conventional Step 4 with Step 3 of the decoding process where the error values E i1 , E i2 and E i3 are computed in synchronism with the "Chien Search" of the error locations. The syndrome decoder then consists of computation of various quantities in Equations (22A) and (29A) for each value of i in a cyclic iterative manner and then affecting the correction of an outgoing symbol with E i whenever Equation (22A) is satisfied. The General Case of t Errors The following is the mathematical derivation for the general case to establish that the logic set forth in FIGS. 2, 3, 4 and 5 for the special case of up to three errors is applicable in general for t errors. In a general BCH or Reed-Solomon code, the codeword consists of n-symbols which include r check symbols corresponding to the roots α a , α a+1 , α a+2 , ..., α a+r-1 of the generator polynomial where α is an element of the Galois field GF(256). The integer a will be taken to be zero, although all of the following results can be derived with any value of a. The corresponding syndromes are denoted by S₀, S₁, S₂, ..., S r-1 respectively. The syndromes can be computed from the received codeword as where B and₀, B and₁, B and₂, ..., B and n-1 are the n-symbols of the received codeword. Let v denote the actual number of symbols in error in a given codeword. The error values are denoted by E i where i represents an error location value from a set of v different error locations given by {I} = {i₁, i₂, ..., i v }. The relationship between syndromes and the errors are then given by Any non-zero value of a syndrome indicates the presence of errors. The decoder processes these syndromes in order to determine the locations and values of the errors. Let t denote the maximum number of errors that can be decoded without ambiguity. A set of r=2t syndromes are required to determine the locations and values of t errors. Consider the polynomial with roots at α i where iε{I}. This is called the error locator polynomial defined as where σ₀ = 1, σ v ≠ 0 and for m > v, σ m = 0. The unknown coefficients σ m for m ≦ v can be determined from the syndromes of Equation 1B as shown below. Substituting x=α i in Equation 3B we get Using Equations 2B and 4B , it is easy to show that the syndromes S j and the coefficients σ m of the error locator polynomial satisfies the following set of relationships: The set of equations 5B can be rewritten in matrix notation as Let M denote the tx(t+1) syndrome matrix on left side of Equation 6B. Let M t denote the square matrix obtained by eliminating the last column in matrix M. If M t is nonsingular, then the above set of equations can be solved using Cramer's rule to obtain where Δ tt is the non-zero determinant of matrix M t and Δ tm denotes the determinant of the matrix obtained by replacing the m th column in matrix M t by negative of the last column of the syndrome matrix M for each m = 0, 1, ..., t-1. If matrix M t is singular, (i.e., Δ tt is 0) then Equation 5B is a dependent set which implies that there are fewer than t errors. In that case, σ t is 0. We can delete σ t and last row and last column of the syndrome matrix in 6B. The resulting matrix equation corresponds to that for t-1 errors. This process is repeated if necessary so that the final matrix equation corresponds to that for v errors and M is nonsingular. Then we need the set of determinants Δ vm where m=0, 1, ..., v. It can be easily seen that Δ vm for v=t-1 is a cofactor of Δ tt corresponding to the (m-1) st column and t th row in matrix M t . We can express Δ tt in terms of these cofactors: Thus the values Δ vm for v=t-1 need not require separate computations. They are available as byproduct of the computation for Δ tt . In fact, Δ vm for subsequent smaller values of v are all available as byproducts of the computation for Δ tt through the hierarchical relationships of lower order cofactors. Thus, in case of fewer errors, the decoder finds Δ tt =0 and automatically back tracks into prior computations to the correct value for v and uses the already computed cofactors Δ vm . This is illustrated previously through hardware implmentation of the case t=3. In order to accomodate the special cases of all fewer errors, we will replace Equation 7B by a more convenient general form where v is determined from the fact that Δ mm =0 for all m>0 and Δ vv ≠0; and Δ m is defined with the new notation as Since σ₀ =1, one can determine σ m for all values of m using Equation 9B. However, we will see that the coefficients σ m are not needed in the entire decoding process. To this end, we obtain a modified error locator equation from Equations 4B and 9B as given by The error location values iε{I} are the set of v unique values of i which satisfy Equation 11B. The error locator polynomial as defined by Equation 2B has v roots corresponding to v error location values. Consider a polynomial which has all roots of the error locator polynomial except one corresponding to the location value i=j. This polynomial is defined as When the actual number of error locations v is less than t, the coefficients σ j,m are 0 for m=v,...,t-1. This is done in order to affect processing of all values of v through a single set of hardware. Substituting x=α i in Equation 12B we get Examine an expression similar to one in Equation 5B involving the syndromes S j and the coefficients σ j,m of the new polynomial. Using Equation 2B , we substitute for S m and get Interchanging the order of summing parameters m and i in Equation 14B we get Now using Equations 13B and 15B we obtain Thus we have an expression for the error values The above expression for error values is well-known. We will reduce it further to obtain a more convenient form. To this end, we prove the following Lemmas 1, 2 and 3. In Lemma 1, we obtain a relation which expresses the coefficients σ j,m in terms of the known coefficients σ k of the error locator polynomial. Lemma 1 Proof : From the definitions of polynomials in Equations 3B and 12B we have Comparing the coefficients of each term in the polynomials on the two sides of equation 19B we have Using Equation 20B, we can substitute for σ k and obtain On eliminating the cancelling terms from Equation 21B we get This completes the proof of Lemma 1. Next we rewrite the denominator of the expression in Equation 17B using the result of Lemma 1. Lemma 2 Proof : Using Lemma 1 we obtain Interchanging the order of summing parameters m and k, we get Using Equation 4B, we can rewrite Equation 25B as This completes the proof of Lemma 2. Now we use the result of Lemma 1 and obtain a more convenient expression for the numerator in Equation 17B in the following Lemma. Lemma 3 Proof : Using Lemma 1 we can express σ j,m in terms of σ k . On substituting these values we obtain Let RHS denote the right-hand side of Equation (28B) In order to prove the Lemma, we rearrange RHS. First, we use the result from Equation 4B and rewrite some of the terms in RHS (the terms with m>µ) as Then, substituting k by m+h in the above RHS becomes Interchanging the order of summing parameters m and h, we obtain another form for RHS as Substituting m by k-h, the expression RHS becomes However, from Equation 5B we have Thus using Equation 33B in 32B we have the final form for RHS: This completes the proof of Lemma 3. We also have the following corollary of Lemma 3 from Equation 32B Corollary : where 0 ≦ µ < t and the coefficients  m are given by Lemma 3 and its corollary provides a family of expressions for the numerator in Equation 17B through a choice of values for µ . We make the following observations: (a) The expression in Lemma 3 requires the syndromes S µ+1 , ..., Sµ; whereas the expression in the corollary requires the syndromes S₀, S₁, ..., S t-1 . This is especially important in the case of erasure correction. (b) The expression in the corollary requires fewer number of multiplications of the type σ k S k-m compared to the expression in Lemma 3. In the corollary, this number depends on the choice of µ and is the minimum when µ= µ where u is the largest integer under t/2. The number of multiplications with the choice µ= µ is the integer closest to (t²+2t)/4. (c) The cases of fewer errors (v<t) are automatically processed by the same hardware as that for processing t errors. With a given choice of µ, the same hardware can be also used in applications with a smaller set of syndromes, S₀, S₁, ..., S t1 and up to t1 errors provided that t≧t1>µ. From this point of view, lower values of µ are desirable and the choice of µ=0 offers the maximum flexibility in applicability of the decoder hardware. The number of multiplications required by the expression in the corollary with µ=0 is (t²-t+2)/2 which is less than two times the minimum of (t²+2t)/4 when µ= µ . In view of the above observations, we will use expression in the corollary of Lemma 3 in decoder implementation. For large values of t, it is advisable to use µ= µ for the greatest economy in hardware. In case of small values of t, we use µ=0 for flexibility in being able to reduce the value of t, later if necessary, without modifying the already fabricated hardware. Now we can rewrite Equation 17B using the results of Lemma 2 and the corollary of Lemma 3 with µ=0. As a result, any error value E i can be expressed as where In view of Equation 9B, the above expressions can be normalized to obtain error values in terms of Δ m as follows: where In case of binary base field, the terms with even values of m, (m mod 2=0) in the denomination of Equation 39B vanish. The resultant expression for E j for binary base field is where Note that the computations for the denominator in Equation 41B is already available as a byproduct from the computations of Equation 11B for each value of i in the Chien Search of error locations. The numerator for each value of i can be computed and multiplied by the inverse of the denominator in synchronism with the search for error locations. The resultant E i is used for correction of the outgoing i th data symbol B i whenever the error locator Equation 11B is satisfied. Table 2 which follows lists 255 non-zero elements of GF(2⁸), each with the corresponding inverse element. A primitive polynomial p(x) = x⁸ + x⁷ + x⁵ + x³ + 1 was used to generate these elements. The elements are represented by 8-digit binary vectors which in polynomial notation have the coefficient for the high order term on the left. The inverse function of this table was implemented through block 40 using the conventional 8-bit encode-decode logic. This requires at the most 304 AND-gates and 494 OR-gates.

Claims: An error correcting system, operable to correct up to a given number "t" of errors in a codeword, wherein each character is represented by a byte consisting of a unique combination of "b" binary bits, a codeword containing up to 2 b such characters including data characters and 2t check characters, the roots of the code generator polynomial being α a , α a+1 , ..., α a+2t-1 where α is an element of the finite field of 2 b elements, by processing 2t syndrome bytes (S₀, S₁, ..., S 2t-1 ), each containing b bits, said system comprising syndrome generating means (6) for generating the 2t syndrome bytes, from which cofactor values Δ tm (m=0,1,2,..t) corresponding to predefined functions of the syndrome bytes can be produced, and characterised by further comprising: (a) means (7) for generating the cofactor values Δ tm (m=0,1,2,..t) by parallel logic for 1 to t errors inclusive; whereby cofactor values Δ tt are formed using predefined functions of syndrome bytes corresponding to cofactor values Δ (t-1)m in accordance with the iteration equation (b) means (41-44, 51-53, 60-62, 71, 72) responsive to said cofactor values Δ tm for 1 to t errors inclusive for selecting coefficient values Δ m according to the actual number of errors (ν) in said codeword such that wherein the coefficients Δ m are selected according to the actual number of errors, based on the non-zero cofactor Δ tt with the highest value of t; (c) means (8,9) for generating individual error values E i for respective locations i by parallel logic from the syndrome bytes and said selected coefficient values Δ m , independently of the location and value of any other errors, where E i is defined by where and selectively applying to the codeword said generated error values E i at said respective character locations i when the following equation holds: and (d) clocking means for ensuring concurrent entry of an uncorrected codeword into said system and exit of a corrected codeword therefrom, thereby enabling "on the fly" correction of codewords in a continuous stream through said system. An error correcting system as claimed in claim 1, further comprising a buffer (5), in parallel with said means (a), (b), (c) and (d), for storing bytes of said codeword during generation of said coefficients values Δ m and error values for the codeword. An error correcting system as claimed in claim 2, wherein the buffer is operable to receive up to 2 b bytes of information where each byte is defined by b bits. An error correcting circuit as claimed in any preceding claim, wherein said means (a) comprises logic circuitry comprising a plurality of product blocks (10), each of which is operable to multiply two b-bit byte input signals to provide a product output signal, and a plurality of exclusive-OR gates (11) for combining selected product output signals to generate said cofactor values Δ tm . An error correcting circuit as claimed in claim 4, wherein a first set of product blocks and exclusive-OR gates forms said predefined functions of syndrome bytes corresponding to cofactor values Δ tm , and a second set of product blocks and exclusive-OR gates uses selected outputs from said first set in forming said predefined functions of syndrome bytes corresponding to cofactor values Δ (t+1)m . An error correcting system as claimed in claim 4 or claim 5, wherein said product blocks comprise a plurality of two input AND gates and a plurality of two input exclusive-OR gates. An error correcting system as claimed in any preceding claim, wherein said means (c) includes means (8) for generating Φ m (m = 1,2....t) including a plurality of feedback shift registers (120,130), wherein each calculated value Φ m and each selected coefficient value Δ m is supplied to a separate feedback shift register for the generation of the individual error values. An error correcting system as claimed in claim 7, wherein the clocking means includes a clock pulse generator supplying a clock pulse to each of said feedback shift registers, each shift register having a predetermined feedback pattern to cause values (Δ m , Φ m ) supplied thereto to be shifted a predetermined number of element positions in the 2 b finite field every time a clock pulse is supplied, and said means (c) includes first means (121,125,127) for combining the output of the shift registers associated with the selected coefficient values Δ m , and means (128,146) for selecting when to apply said generated error values to said codeword by detecting when the output of said first means (121,125,127) corresponds to a predetermined element of the finite field. An error correcting system as claimed in claim 8, wherein said means (c) further includes second means (131,132) for combining the outputs of the feedback shift registers associated with the error value coefficient values, and means (140,145) for combining the output of said second means with the inverse of the output of selected feedback shift registers associated with said coefficient values Δ m to produce an error value during the same clock interval in which the first combining means provides its output corresponding to the predetermined finite field element. An error correcting method for an error correcting system, operable to correct up to a given number "t" of errors in a codeword, wherein each character is represented by a byte consisting of a unique combination of "b" binary bits, a codeword containing up to 2 b such characters including data characters and 2t check characters, the roots of the code generator polynomial being α a , α a+1 , ..., α a+2t-1 , where α is an element of the finite field of 2 b elements, by processing 2t syndrome bytes (S₀, S₁, ..., S 2t-1 ), each containing b bits, said method comprising the step of generating the 2t syndrome bytes, from which cofactor values Δ tm (m=0,1,2,..t) corresponding to predefined functions of the syndrome bytes can be produced, and characterised by further comprising the steps of (a) generating cofactor values Δ tm (m=0,1,2,..t) by parallel logic for 1 to t errors inclusive; whereby cofactor values Δ tt are formed using predefined functions of syndrome bytes corresponding to cofactor values Δ (t-1)m in accordance with the iteration equation (b) in response to said cofactor values Δ tm for 1 to t errors inclusive, selecting coeffient values Δ m according to the actual number of errors ( ν ) in said codeword such that wherein the coefficients Δ m are selected according to the actual number of errors, based on the non-zero cofactor Δ tt with the highest value of t; (c) generating individual error values E i for respective locations i by parallel logic from the syndrome bytes and said selected coefficient values Δ m , independently of the location and value of any other errors, where E i is defined by where and selectively applying to the codeword said generated error values E i at said respective character locations i when the following equation holds and (d) transferring bytes into and out of the system, and ensuring - by clocking means concurrent entry of an uncorrected codeword into said system and exit of a corrected codeword therefrom, thereby enabling "on the fly" correction of codewords in a continuous stream through said system. An error correcting method as claimed in claim 10, in which at least one byte of said codeword is transferred from said system (step d) prior to identifying all byte positions of said codeword containing errors.

Inventors: PATEL, ARVIND MOTIBHAI
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1983
Main classification: G06F11
IPC codes: G06F11, H03M13