HIGH-SPEED COMPLEMENTARY SEMICONDUCTOR INTEGRATED CIRCUIT

Abstract: A complementary semiconductor integrated circuit de­ vice includes an electrical insulative substrate (10), a p-­ channel FET (Q₁) formed on the substrate (10) and consists of lead chalcogenide based semiconductive material, for exam­ ple, PbTe, and an n-channel FET (Q₂) consisting similarly of PbTe and to operates mutually and complementarily with the p-channel FET (Q₁). The PbTe constituting the FETs (Q₁, Q₂) has electron and hole mobilities whose values are each greater by at least about one digit place than the value of a corresponding one of the electron and hole mobilities of silicon material. Accordingly, the device has an increased speed of operation.

Description: High-speed complementary semiconductor integrated circuit The present invention relates to a semiconductor device having a high-speed operation. More specifically, the present invention is concerned with a semiconductor integrated circuit device which operates with high-speed and which is of a complementary structure. As is commonly known in the art, the operational speed of a semiconductor integrated circuit device is limited by the carrier mobility of electrons or holes allowed to flow between the elements. Therefore, when it is desired to improve the operational speed of the device, it is necessary to increase the carrier mobility. For the purpose of increasing the carrier mobility to a value greater than that of the carrier mobility of silicon, the semiconductive material currently in use, methods which include (1) using a compound semiconductive material such as GaAs, A±xGal¯xAs, etc. which, in an atmosphere of room temperature, has an electron mobility of 8 x 103 cm2/V.sec or so at maximum to form the active elements, (2) applying a novel impurity addition technique such as a modulation doping technique to a semiconductor device composed of such a compound semi conductive material and thereby improving or increasing the electron mobility in a zone of low temperature, etc. have been studied. However, the carrier mobility of a semiconductor integrated circuit device prepared by the abovementioned methods is several thousands of square centimeters/V. sec to several tens of thousands of square centimeters/V. sec at best. When an attempt is made to further improve the carrier mobility, the manufacturing yield of the semiconductor device decreases due to the technical problem involved in the manufacturing steps. Further, as is well known, the semiconductor device of a complementary circuit structure has excellent characteristics such as a high degree of permissible noise, a low power consumption, etc. and is therefore regarded as being a promising device providing excellent cost performance. On the other hand, however, the operational speed of the complementary semiconductor integrated circuit device is limited by the smaller one of its electron or hole mobility. Accordingly, even when electron mobility greater than the carrier (electron) mobility of silicon has been actualized by using GaAs or AQxGal¯xAs at the time of forming the device as mentioned above, the hole mobility at room temperature of the said compound semiconductive material is only several hundreds of square centimeters/V. sec at most, with the result that the final operational speed of the complementary semiconductor device is not improved because, even when the mobility of one carrier (electron) of the complementary semiconductor device is increased, the final operational speed is limited by this inferiorhole mobility if the mobility of the other carrier (hole) is relatively small. Accordingly, the increase in speed of the complementary semiconductor integrated circuit does not reach the desired speed even if concurrent use is made of a technique for lowering the atmospheric temperature. The object of the present invention is to provide a new and improved semiconductor device which has excellent hole and electron carrier mobilities and which has high-speed operation even when it is applied to a complementary circuit structure. According to the complementary semiconductor integrated circuit device of the invention, the active elements such as FETs or bipolar transistors are preferably formed of lead chalcogenide based semiconductive material such as PbS, PbSe, or PbTe. This type of semiconductive material is higher both in electron mobility and in hole mobility than silicon and the values of its electron and hole mobilities are approximate to each other. The lead chalcogenide semiconductive material has, in a temperature zone of, for example, liquid helium, electron and hole carrier mobilities of several tens of thousands of square centimeters to several hundreds of thousands of square centimeters/Vssec. According to the present invention, therefore, there is provided a semiconductor integrated circuit device which has higher speed than that of the conventional semiconductor integrated circuit device to the extent corresponding to an increase, by at least one digit-place, of the operational speed value of that conventional one. Thus, the above object is attained. The above-mentioned active elements constituting the complementary semiconductor integrated circuit of the present invention are, as mentioned above, constituted by FETs or bipolar transistors. In a pair of transistors, which perform a logical switching operation on a mutually complementary basis, one of such transistors operates with the holes as its "active carrier" and the other thereof operates with the electron as its "active carrier". The wording "active carrier" used in this specification and claims is defined to mean "carrier directly serving to perform the active function of the transistor". For example, when mention is made of an FET or unipolar transistor operating with the holes as "active carrier", it means a p-channel FET whose channel region is formed by the holes. On the other hand, when reference is made of a bipolar transistor operating with the holes as "active carrier", such transistor means a pnp type transistor. The same applies to the case of "electron This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: The present invention is best understood by reference to the accompanying drawings, in which: Fig. 1 is a sectional view schematically showing the construction of a main part of a complementary integrated inverter device according to one preferred embodiment of the invention; Fig. 2 is a circuit diagram showing an equivalent circuit of the inverter circuit device of Fig. 1, and Figs. 3 and 4 are sectional views schematically showing the constructions of the complementary integrated inverter devices modified from the embodiment of Fig. 1, respectively. Referring now to Fig. 1 a monocrystalline substrate 10 consisting of an electrically insulative substrate such as BaF2 has a cleavage plane 10a corresponding to a specified crystalline face on its upper surface. On the cleavage plane 10a of this BaF2 substrate 10, an n-conductivity type thin monocrystalline film A1 and a p-conductivity type monocrystalline thin film A2 are each deposited by being selectively epitaxially grown thereon through the use of, a molecular beam epitaxy technique, for example. These films A1 and A2 are each formed of a semiconductor crystalline body which has higher carrier mobility or electron and hole mobilities than silicon and the electron and hole mobilities are approximate to each other. This semiconductor crystalline body is preferably formed of lead chalcogenide. In Fig. 1, for example, PbTe is utilized as the lead chalcogenide constituting the films A1 and A2. P-conductivity type impurities are introduced into the PbTe monocrystalline film A1 except a middle film region 12, corresponding to a channel region, by a known selective diffusion or ion-implantation technique, whereby two outer film regions 16 and 18 of the film A1 has a p+-conductivity type. The two outer film regions 16 and 18 correspond to source and drain, respectively. As a result, a p-channel FET Ql is formed on the insulative substrate 10 to have the PbTe monocrystalline channel region 12 of n-conductivity type and the PbTe monocrystalline source and drain films 16 and 18 of p+-conductivity type. In the same manner as described above, n-conductivity type impurities are introduced into the other PbTe monocrystalline film A2 except a channel region 14 so as to cause two outer film regions serving as source and drain regions 20 and 22 to have an n+-conductivity. Gate insulation films 24 and 26 are each formed on the films A1 and A2 each having a pnp junction structure and npn junction structure. These gate insulation films 24 and 26, preferably, are each formed of a thin film having a high dielectric constant such. as that made of Si3N4, Ta2O5 and the like. Gate electrodes 32 and 34 are further deposited on these films 24 and 26, respectively. Thus, the p-channel metal-insulator semiconductor (MIS) FET Ql and the n-channel MISFET Q2 are finally formed on the insulative substrate 10. Thereafter, wiring patterns 36-1, 36-2 and 36-3 consisting of metallic material such as platinum are formed on the above structure by a known technique. The patterns 36-1 and 36-2 are in contact with the PbTe films 16 and 22, thereby providing a source electrode (36-1) for the MISFET Ol and a drain electrode (36-2) for the MISFET Q2 respectively. The PbTe films 18 and 20 are electrically connected to each other by means of the platinum layer 36-3. Further, the source electrode 36-1 of the MISFET Ql is connected to a power source terminal 40 to which a grounding potential or a potential V55 is applied, while the drain electrode 36-2 of the MISFET Q2 is connected to another power source terminal 42 which a voltage VDD is applied. The gate electrodes 32 and 34 of the MISFETs Q1 and Q2 are commonly connected, and at the same time, connected to a signal input terminal 44. The platinum layer 36-3 electrically connecting the drain 18 and source 20 included respectively in the MISFETs Ol and Q2 is connected to a signal output terminal 46. With such a construction, the complementary inverter integrated circuit is actualized. Fig. 2 shows an equivalent circuit of the integrated circuit of Fig. 1. The complementary inverter circuit including MISFETs Ql and Q2 and having the foregoing construction of one embodiment of the invention, exhibits an excellent high-speed characteristic as compared with a conventional integrated CMOS inverter circuit. The reasons for this are as follows: the monocrystalline thin films consisting of lead chalcogenide such as PbTe and formed by selective molecular beam epitaxy, which have an electron carrier mobility of approximately 1700 cm2/V.sec and a hole carrier mobility of approximately 900 cm2/V.sec at room temperature have, in the zone of liquid helium temperature, an electron carrier mobility as high as 5 x 105 cm2/V.sec and a hole carrier mobility as high as approximately 3 x 105 cm2/V.sec. Thus, it is possible to easily manufacture (without using any special techniques a semiconductor integrated circuit of a complementary type exhibiting an ultrahigh speed characteristic by using a relatively simple existing thin-film forming technique. The lead chalcogenide based semiconductor materials generally have a high specific dielectric constant of several hundred. PbTe, one of the lead chalcogenide compounds, also has a specific dielectric constant as high as approximately 400. An increase in capacitance of the electrode section, which is attributable to such a high dielectric constant may therefore occur. According to the embodiment shown in Fig. 1, however, the monocrystalline thin film made of PbTe and constituting an active layer was formed on the insulative substrate 10 and therefore the increase in capacitance of the electrode section can be largely suppressed. Further, the above-mentioned layer structure according to the invention makes it easy to manufacture a ballistic device because the mean free path of the electron and hole carriers of lead chalcogenide in the temperature zone of liquid helium is as large as scores of microns. The fact that the mean free path of the carriers is long makes it possible to enlarge the scale of an active region of the ballistic device. The existing integrated element fabrication technique is therefore sufficient for manufacturing the ballistic device. Further, according to the invention, when the monocrystalline thin film such as that made of BaF2, SrF2 and the like is formed as the gate insulative layer on the lead chalcogenide made film, it is possible to further improve the operational characteristics of MISFET because the interface property of MISFET is improved. In Figs. 3 and 4, there are shown modifications of the complementary integrated inverter circuit shown in Fig. 1, respectively. In Fig. 3, the MISFETs Ql and Q2 are provided on a substrative body 50 comprised of an electrical conductive substrate 52 and an electrical insulative thin film 54 formed on the surface 52a of that substrate 52. The substrate 52 is composed of a monocrystalline bulk of PbTe or one of the lead chalcogenide compounds which is the same material as that used for the FETs Ol and Q2 Further, the insulative thin film 54 consists of a monocrystalline material which is lattice-matched with the lead chalcogenide based semiconductive material, for example, BaF2. In the embodiment shown in Fig. 1, the MISFETs Ol and Q2 are formed directly on the cleavage plane 10a of the BaF2 substrate 10 and therefore the PbTe thin film structures A1 and A2 constituting the FETs Ol and Q2 are very likely to have imperfections and lattice defects due to stress on the cleavage plane 10a. As a result, the operation speed of the MISFETs Ol and Q2 decreases. In contrast, according to the modification of Fig. 3, the irregularities in crystalline structure of the surface 52a of the PbTe substrate 52 are removed in the growth process of the BaF2 insulative thin film 54 on the PbTe substrate 52. This reliably prevents lattice defects from being produced in the PbTe thin film structures A1 and A2. In Figs. 1 and 3, there has been shown the complementary integrated inverter circuit comprised of MISFETs Ol and Q2. However, the transistor elements constituting the logic circuit such as inverter circuit are not limited to MISFETs but may be junction-gate field effect transistors (abbreviated as J-FET). In Fig. 4, there is shown one example of the complementary inverter circuit constructed of a pair of J-FETs Q3 and Q4. The J-FET Q3 at one side is constructed such that p+-type monocrystalline PbTe thin films 60 and 62 are formed on the substrate 10 and a p-type PbTe thin film 64 corresponding to a channel constituting a current path is formed between the films 60 and 62 so as to be joined to the films 60 and 62 from both sides thereof. An n+-type PbTe thin film 66 and a gate electrode 32 are deposited on the intermediate PbTe thin film 64 in the order mentioned. When a voltage signal is applied to the PN junction consisting of the thin films 64 and 66, a depletion region D1 changes within the channel 64, controlling the carrier current between the source and drain. The J-FET Q4 at the other side also includes n+-type monocrystalline PbTe thin films 68 and 70, an n-type PbTe thin film 72 formed between the films 68 and 70 so as to constitute the channel, and a p+-type PbTe film 74 formed on the film 72. The notation D2 denotes a depletion region formed in the channel 72. According to the complementary inverter circuit of Fig. 4, it is unnecessary to provide the gate insulation films 24 and 26 of the MISFETs Q1 and Q2 constituting the inverter circuit of Fig. 1. In the inverter circuit of Fig. 1, controlling the thickness of the gate insulation film with high precision is required to precisely set the threshold level involved in the switching operation of FET. This control of film thickness is one of the factors which makes it difficult to manufacture the complementary integrated inverter circuit device. In Fig. 4, however, since the J-FET structure has been adopted, it is not necessary to provide the gate insulation film as mentioned above. This means that the parameters for controlling the threshold level are reduced by one. Thus, it is possible to provide an inverter circuit in which the threshold level involved in the switching operation is set more precisely. Although the present invention has been shown and described with respect to particular embodiments, various changes and modifications which are obvious to a person skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention. The present invention can also be effectively applied to a complementary integrated logic circuit comprised of active elements other than the transistors employed in the above-mentioned embodiments, for example, Schottky gate transistors. Further, the use of PbS or PbSe as the lead chalcogenide provides the same effect as that attainable by the preceding embodiments since the electron and hole mobilities are high in the temperature zone of liquid helium. Further, according to the invention, it is possible to obtain the monocrystalline thin film with fewer lattice defects by adopting the mixed crystal of lead chalcogenide and thereby matching the lattice between the insulative substrate and the monocrystalline thin film formed thereon. Furthermore, the present invention can also be applied to what is called "a three-dimensional semiconductor integrated circuit device" constructed by using the monocrystalline thin film such as that made of the BaF2, SrF2 or the like as interlayer insulative films and stacking the lead chalcogenide monocrystalline thin films. Further, according to the preceding embodiments, the lead chalcogenide monocrystalline thin film serving as an active element is grown on the electrical insulative substrate such as that made of BaF2 to reduce the electrode capacitance. However, it is not always necessary that the substrate be electrically insulative to achieve the effect of the present invention. Because the electrode capacitance can be reduced by minituarizing the area of electrode it can be expected that the active layer consisting of the lead chalcogenide thin film is formed on the monocrystalline bulk of lead chalcogenide. In any of the above-mentioned semiconductor devices, including any of the modifications, it is apparent from Table 1 and Table 2 below that excellent carrier mobility can be obtained compared with the prior art even in a low temperature zone such as in the temperature zone of liquid helium and in that of liquid nitrogen as well. Table 1 given below shows the electron and hole mobilities of each of PbS, PbSe and PbTe in a temperature zone of liquid helium. TABLE 1 Material Electron Mobility Hole Mobility (cm2/V.sec) (cm2/V.sec) PbS 6 x 104 6 x 104 PbSe 1 x 105 1 x 105 PbTe 5 x 105 3 x 105 Table 2 presented below shows the electron and hole mobilities of each of PbS, PbSe and PbTe in a temperature zone of liquid nitrogen. TABLE 2 Material Electron Mobility Hole Mobility (cm2/V.sec) (cm2/V.sec) PbS 1.5 x 104 1.5 x 104 PbSe 2 x 104 2 x 104 PbTe 3 x 104 2 x 104

Claims: Claims: 1. In a semiconductor device having a substrative body (10, 50) and first and second active elements formed on said substrative body (10, 50) and performing a mutual and complementary switching operation, characterized in that said first active element (01, Q3) and said second active element (Q2, Q4) are each made of lead chalcogenide based semiconductive material having electron and hole mobilities whose values are each greater by at least one digit-place than the value of a corresponding one of the electron and hole mobilities of silicon material. 2. The device according to claim 1, characterized in that said first active element includes a first transistor (01, Q3) operating with the holes as its active carriers and said second active element includes a second transistor (Q2, Q4) operating with the electrons as its active carriers. 3. The device according to claim 1, characterized in that said substrative body includes an electrical insulative substrate (10). 4. The device according to claim 1, characterized in that said substrative body (50) includes an electrical conductive substrate (52) and an electrical insulative film (54) provided on said substrate (52). 5. The device according to claim 4, characterized in that said insulative film (54) includes a monocrystalline thin film lattice-matched with the lead chalcogenide based semiconductive material. 6. The device according to claim 1, characterized in that said first active element includes a first field effect transistor (Q1 Q3) having a first semi conductive region corresponding to a channel formed by the holes and said second active element includes a second field effect transistor (Q2 Q4) having a second semiconductive region corresponding to a channel formed by the electrons. 7. The device according to claim 6, characterized in that said substrative body includes an electrical insulative substrate (10) having a surface (lOa) corresponding to a mechanical and chemical finished plane including a cleavage process on which said first and second field effect transistors are so formed as to provide a complementary integrated circuit configuration. 8. The device according to claim 6, characterized in that said substrative body (50) includes an electrical conductive monocrystalline substrate (52) and an electrical insulative monocrystalline film (54) provided on said substrate (52); and wherein said substrate (52) includes monocrystalline bulk which is lattice-matched with said film (54). 9. The device according to claim 8, characterized in that said monocrystalline bulk is made of lead chalcogenide based semiconductive material. 10. The device according to claim 8, characterized in that said lead chalcogenide based semiconductive material is a material selected from the group consisting of lead sulfide (PbS), lead selenide (PbSe), and lead telluride (PbTe). 11. The device according to claim 8, characterized in that said lead chalcogenide based semiconductive material is a mixed crystal of a plurality of materials selected from the group consisting of lead sulfide (PbS), lead selenide (PbSe) and lead telluride (PbTe).

Inventors: HOJO, AKIMICHI, NII, RIRO, TOYODA, NOBUYUKI, YANAI, HISAYOSHI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1983
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21