A FIELD-EFFECT SEMICONDUCTOR DEVICE

Abstract: A field-effect semiconductor device comprises a via-hole electrode (6a) formed so as to penetrate from the top to the back of the semiconductor substrate (1), a dielectric film (10) formed on the semiconductor substrate so as to be opposite to the via-hole electrode, and an electrode (26), forming a via-hole type of passive element, such as a capacitor, so as to improve the integration degree.

Description: A FIELD-EFFECT SEMICONDUCTOR DEVICE The present invention relates to an improvement of a field-effect semiconductor device having a capacitor and a field-effect transistor (FET), at least one electrode of the FET being grounded via the capacitor. More particularly, the capacitor is formed by means of a via hole in the semiconductor substrate. A field-effect semiconductor device generally includes active elements, such as gallium arsenic (GaAs) FETs and diodes, and passive elements, such as capacitors, resistors, inductors, and so forth. For example, when a field-effect semiconductor device employs a self-bias circuit so that the GaAs FET can be driven by a single power supply, a capacitor should be connected between the source electrode of the GaAs FET and the ground, and when the field-effect semiconductor device is a low-pass filter type of matching circuit, capacitors, inductors, and GaAs FETs should be formed in the device. As an active element, a via-hole type of GaAs FET described in detail later is known. In a conventional via-hole type of GaAs FET, one electrode thereof is directly grounded via a via-hole electrode inserted into the via-hole. Therefore, it is impossible to connect a capacitor between the electrode of the via-hole type of GaAs FET and the ground (described in detail later). Accordingly, the conventional via-hole type of GaAs FET cannot employ a self-bias circuit. Conventionally, when a field-effect semiconductor device such as a self-bias circuit or a matching circuit is formed on a semiconductor chip, passive elements, such as capacitors or resistors, are formed at the surface of the semiconductor chip in such a manner that they have planar structures. That is, each passive element itself requires an area which is not used by the other elements. Therefore, these passive elements occupy a considerable area on the semiconductor chip, thereby inhibiting improvement in the integration degree and casuing complex wiring to have bad grounding charac teristics. Thus, there is a heed to realize a field-effect semiconductor device in which passive elements such as capacitors or resistors have lateral structures formed in the same regions as the other elements and also have structures which enable the number of manufacturing steps thereof to be decreased. An embodiment of the present invention can provide a field-effect semiconductor device having via holes in a semiconductor substrate, in which passive elements such as capacitors or resistors are formed by using the via holes so as to improve the integration degree. Another embodiment of the present invention can provide the above-mentioned field-effect semiconductor device having a via-hole type of FET in which a capacitor is formed between an electrode opposite to the via hole of the FET and the ground. Still another embodiment of the present invention can provide the above-mentioned field-effect semiconductor device in which improved grounding characteristics, can be obtained. Still a further embodiment of the present invention can provide the above-mentioned field-effect semiconductor device in which wirings connected to the passive elements can be simplified or eliminated. Reference will now be made, by way of example, to the accompanying drawings, wherein: Figure 1 is a cross-sectional view of a conventional FET; Fig. 2 is an equivalent circuit diagram of the FET of Fig. 1; Fig. 3 is a conventional circuit diagram of FET including a self-bias circuit; Fig. 4A is a cross-sectional view of a field -effect semiconductor device according to a first embodiment of the present invention; Fig. 43 is an equivalent circuit diagram of the device of Fig. 4A; Fig. SA is a cross-sectional view of a field -effect semiconductor device according to a second embodiment of the present invention; Fig. 5B is an equivalent circuit diagram of the device of Fig. 5A; Fig. 6A is a cross-sectional view of a field -effect semiconductor device according to a third embodiment of the present invention; Fig. 6B is an equivalent circuit diagram of the device of Fig. 6A; Fig. 7A is a cross-sectional view of a field -effect semiconductor device according to a fourth embodiment of the present invention; and Fig. 7B is an amplifier circuit including an equivalent circuit diagram of the device of Fig. 7A; and Figs. 8 through 10 illustrate the manufacturing steps of a capacitor included in any one of the above embodiments. Before describing the preferred eoiments of present invention, a conventinal device, and the proileus i jnvoIQS, is first explained with refertece to Figs 1 through 3. Figure 1 is a cross-sectional view of a main portion of a conventional via-hole type of FET. In Fig. 1, 1 designates a semiconductor substrate. 2 a source electrode, 3 a drain electrode, 4 a gate electrode, 5 a via hole, 6 a back-surface electrode formed on the back surface of the semiconductor substrate 1, and 6a a via-hole electrode inserted into the via hole 5 so as to connect the source electrode 2 to the back -surface electrode 6. An equivalent circuit diagram of the device of Fig. 1 is shown in rig. 2, wherein the same reference numerals designate the same portions as in Fig. 1. To operate the FET of Fig. 2, a positive voltage of, for example, T3 V is applied to the drain electrode 3, a negative voltage of, for example, -2 V is-applied to the gate electrode 4, and the source electrode 2 is grounded, i.e., 0 volts are applied to the source electrode 2. Thus, the circuit of Fig. 2 requires two power supplies, i.e., a plus voltage power supply and a minus voltage power supply. Recently, there has been a great need to operate an FET by a single power supply so as to prevent the destruction of the FET and so as to decrease the cost thereof. Figure 3 is a conventional circuit diagram of an FET operated by a single power supply. In Fig. 3, 2a, 3a, and 4a designate a source electrode, a drain electrode, and a gate electrode, respectively, of an FET which is not a viahole type of FET. Reference numerals 7, 8, and 9 designate a capacitor, a resistor, and an inductor, respectively, which form a self-bias circuit. In the self-bias circuit, between the source electrode 2a and the ground, the capacitor 7 and the resistor 8 are connected in parallel. The inductor 9 is connected between the gate electrode Sa and the ground, Flus, with respect to a high-frequency current, the source electrode 2a is almost directly grounded via the capacitor 7. When a positive voltage of, for example, S V is applied to the drain electrode 3aZ the voltage at the source electrode 2a SQccFes 2 V, for exarnplet due to a voltage drop across the resistor 8. The gate electrove 4a is grounded with respect to a direct current so that its voltage is 0 volts. Therefore, the voltage at the gate electrode 4a is lower than the voltage at the source electrode 2a by about 2 V. In other words, the gate electrode 4a is self-biased so that the FET of Fig. 3 can be operated by a single power supply (not shown) connected to the drain electrode 3a. The via-hole type of FET illustrated in Figs. 1 and 2 has an advantage in that the source electrode 2 is easily and surely grounded by the via-hole electrode 6a. However, since the source electrode 2 is directly grounded, a capacitor cannot be connected between the source electrode 2 and the ground. Therefore, the circuit of Fig. 3 including the self-bias circuit cannot be constructed by means of the via-hole type of FET. When an FET without a via hole is used to form the circuit of Fig. 3, it is easy to form a capacitor in the semiconductor device and to connect the source electrode of the FET to the ground via the capacitor so as to cut a direct current. However, in this case, the capacitor occupies an area which is not used by the other elements on the semiconductor chip and thereby the integration degree is deteriorated. Further, wirings such as those between the source electrode of the FET and the electrode of the capacitor, between the electrode of the capacitor and the ground, and so forth, become complex, with the result that the grounding characteristics may be poor. There are many circuits, such as matching circuits, which require capacitors and FETs. Problems similar to those mentioned above occur in such circuits. The ambodilnents of the present invention are described Figure 4 is a cross-sectional view of a field -effect semiconductor device according to z embodiment of the present tnventionfi and Fig. 4B is an equLvalerjt circuit diagram of the device of Fig 4A. In these figures and the following figures, the satt reference numerals designate the same portions as illustrated in Figs. 1 and 2. The difference between this embodiment and the conventional device of Fig. 1 is that in Fig. 4A, between the viahole electrode 6a and one part of a source electrode 2b, a dielectric film 10 of, for example, SiO2 is formed. Another part of the source electrode 2b is in contact with the surface of the semiconductor substrate 1. The source electrode 2b, the dielectric film 10, and the via-hole electrode 6a constitute a capacitor 7a as shown in Fig. 4B. When the back-surface electrode 6 is grounded and when the source electrode Th is grounded via a resistor (not shown), the self-bias circuit shown in Fig. 3 can be easily realized by the device of Fig. 4A. Also, when the source electrove 2b is directly grounded, the circuit of Fig. 2 can be realized. Figure SA is a cross-sectional view of a field -effect semiconductor device according to a second embodiment of the present invention, and Fig. SB is an equivalent circuit diagram of Fig. 5A. The difference between Fig. 4A and Fig. 5A is that, in Fig. 5A, a direct-current grounding electrode 11 is formed near the source electrode 2b and on the surf ace of the semiconductor substrate 1, and under the electrode 11, another via-hole Sa is formed through the semiconductor substrate 1. In the via hole 5a, a via-hole electrode 6b is buried so as to connect the direct-current grounding electrode 11 to the back-surface electrode 6. When a resistor (not shown) is connected between the source electrode 2b and the direct-current grounding electrode 11, the self-bias circuit shown in Flg. 3 can be realized. Also1 when a conductive Isad, instead of a resistor, is connected between the source electrode 2b and the direct-cutrent grounding electrode 11, the circuit of Fig. 2 can be realized. Pigure CA is a cross-sectònal YLebJ Cf a eL- -effect semiconductor device according to a third embodiment of the present invention, and Fig. 6B is an equivalent circuit diagram of Fig. 6A. The difference between Fig. 5A and Fig. 6A is that, in Fig. 6A, a resistive film 12 is formed on the surface of the semiconductor substrate 1 and between the source electrode 2 and the direct-current grounding electrode 11. This resistive film 12 functions as the resistor 8 shown in Fig. 6B. Thus, the self-bias circuit shown in Fig. 3 can be realized. The description of the foregoing embodiments mainly relates to 2 via-hole type of FT used so as to be self-biased. The present invention, however, is not restricted to the above embodiments, and various other applications are possible. For example, in accordance with the circuit design, a capacitor may alternatively be formed between a gate electrode or a drain electrode and a via hole of the viahole type of FET when the via hole is formed so as to be opposite to the gate electrode or the drain electrode. Figure 7A is a cross-sectional view of a low-pass filter type of amplifier circuit device according to a fourth embodiment of the present invention, and Fig. 7B a low-pass filter type of amplifier circuit including an equivalent circuit diagram of the device of Fig. 7A and a matching circuit. In Fig. 7A, part of a low-pass filter type of amplifier circuit device is illustrated. On the surface of the semiconductor substrate 1 and opposite to the second via-hole electrode 6b, a second dielectric film 13 is formed. The gate electrode 4 and the second dielectric film 13 are connected by a con ductive layer 14. Thus, as Fig. 78 shows b a capacitor C is formed betwee the corkductLue layer 14 and the second via-hole electrode 6b. The condoctive layer 14 functions as an inductor L. In Fjg. 7B, a circuit Menclosed by by broken line is an eq,uisralent: circuit; diagrom of the device of Fig. 7A. The circuit of Fig. 7B is a well-known low -pass filter type amplifier circuit including an FET, capacitors C, and inductors L. It will be understood that the series connected two inductors L and one capacitor C connected to these inductors L, constitute a matching circuit, and that all of the elements Q, C, and L can be formed so as to have a structure similar to that of the device of Fig. 7A. In the foregoing embodiments, the dielectric Film 10 or 13 on the via-hole electrode 6a or 6b is used to form a capacitor. However, when impurities which supply carriers are included in the dielectric film 10 or 13, the dielectric film acts as a resistor. The resistance value R(Q) and the capacitance value C(F) are determined by the following well-known equations (1) and (2), respectively: : R = 0L/S .... (1) where p is the specific resistivity (#m) of the resistor, S is the cross-sectional area (m2) of the resistor, and L is the length (m) of the resistor C = @S/d where @ is the dielectric constant of the material between the electrodes of the capacitor, d is the distance between the electrodes of the capacitor and S is the cross-sectional'area (m2) of the electrodes of the capacitor. In a field-effect semiconductor device, the resist- ance value and the capacitance value must be accurate. To obtain an accurate resistance or capacitance, the thickness of the dielectric film must be critically controlled, as will be understood from the above equations (1) mod (2). it is, bowever, & fjtil± to accurately control the thickness of the dielectric film by a conventional technique because, after the dielectric film is formed on the semiconductor substrate l, a via hole is forked by etching frorss the back surface of the semiconductor substrate, and, at the end of the etchinq process, the dielectric film may also be etched or part of the semiconductor substrate may remain under the dielectric film. In order to obtain an accurate capacitance or resistance, according to the present invention, the dielectric film has an etching rate lower than the etching rate of the semiconductor substrate so that the thickness of the dielectric film is accurately predetermined. By this constitution, the etching for forming the via hole is accurately ended at the top surface of the semiconductor substrate Thus, the resultant resistance or capacitance realized by the dielectric film is very accurate. As an example, the semiconductor substrate is made of semi-insulating GaAs, the dielectric film is made of aluminum gallium arsenic (AlGaAs) and is formed by molecular beam epitaxy (MBE), and the via hole is etched by reactive sputtering by means of reactive gas such as dichlorodifluoromethane (CC12F2), etc. Figures 8 through 10 illustrate the manufacturing steps of a capacitor included in any one of the foregoing illustrated embodiments. In Fig. 8, on a semi-insulating GaAs substrate 20 having a thickness of about 400 vm, a dielectric film 22 made of-semi-insulating AlGaAs, where Al is 30% and Ga is 70%, (hereinafter referred to as Al0.3 Gay 7 As) is formed by means of metal-organic compound chemical vapor deposition, MBE, and so forth so as to have a desired thickness. The thickness of the dielectric film 22 is determined by the capacitance of the capacitor to be manufactured . In accordance ;4ith the circuit design an N-type A1GaAs later (not shown) may be fores under the dielectric film 22. frL. S, the semi-insulating CaAs substrate 20 is abrased mechanicaliv or chemically from its back surface to Lkat has a desired thickness of from 10 m through 300 m. Then a via hole 24 extending to the back surface of the dielectric film 22 is formed. The step of forming the via hole is carried out by reactive sputtering by using a reactive gas such as CC12F2 etc. In this step, since the etching rate of the semi-insulating GaAs substrate 20 is two hundred times higher than the etching rate of the dielectric film 22 made of Al0.3 Ga 7 As, only the semi-insulating GaAs substrate 20 is selectively etched. In Fig. 10, under the semi-insulating GaAs sub- strate 20, a back-surrace electrode 26 is formed by means of a well known plated heat sink tecnnique (PES). That is, the back-surface electrode 26 is made of gold germanium formed by means of vacuum evaporation so as to extend into the via hole 24, and gold plating is carried out on the surface of the gold germanium. Then, on the dielectric film 22 of semi-insulating Al0.3 Ga0.7 As, an upper electrode 28 is formed from aluminum (Al), gold An, gold-germanium (AuGe), gold-germanium-nickel (AuGeNi), or other conductive material, by means of sputtering and photo-lithography. Thus, a capacitor according to the present invention is completed. The upper electrode 28 is connected to a selected source, drain, or gate electrode of a GaAs FET formed in an N-type GaAs active layer (not shown) which is selectively formed on or in the semi-insulating GaAs substrate 20 by means of a well known mesa etching or ion injection method. The capacitance of the resultant capacitor is determined by the thickness of the dielectric film 22, the area of the surface of the upper electrode 28 opposite to the the dielectric film and the area of the upper surface of a via-hole electrode 30 in the via hole 24. Assume that the shape of the portion of the upper electrode 28 in contact with the dielectrie film 22 is a square having one side being 50 m, and that the shape of the portion of the via-hole electrode 30 in cantact with the dielectric film 22 is the same as that of the upper electrode 28. In such a case, when a capacitance of about 2.7 PF is to be obtained, the thickness d of the dielectric film 22 is determined by inserting the following numbers into the before-described equation (2): C = 2.7 (PF) = 2.7 x 10 - 12 (F) = 12.2 x 8.854 x 10 12 (F/m) S = 502 (m2) = (50 x 10¯6)2 (m2) Then the thickness d can be obtained as d = es / c = 1,000 x 10 - 10 (m) = 1,000 (A ) In this case, since the thickness of the dielectric film 22 is extremely thin, i.e., 1,000 (A ), it is preferable that the growing speed of a chemical compound such as AlGaAs for forming the dielectric film 22 be relatively slow so as to control the thickness as accurately as possible. When the dielectric film 22 is used as a resistor, a desired resistance can be obtained by introducing impurities of a desired type of conductivity into the dielectric film 22 of AlGaAs. In the before-described equation (1), L is the thickness of the dielectric film 22. Thus, according to the above-mentioned steps, a capacitor or a resistor can be formed together with a via-hole electrode without adding more steps to the conventional steps. From the foregoing description of the embodiments, it will be apparent that, according to the present invention, since a large capacitor is formed by a via -hole electrode to be grounded, an electrode selected from arong a source, a drain, and a sate electrode of a via-hole type of FET, and a dielectric film formed between the via-hole electrode and the selected electrode, a high-froquency current conducted through the selected electrode is grounded via the cactor, and direct current conducted through the selected electrock is not grounded. Accordingly, a field-effect semicon actor device including a passive element such as a self-bias circuits or a matching circuit including passive elements, such as capacitors, can be formed together with via-hole type FETs so that the integration degree of, the grounding characteristics of, and the wirings connected to the passive elements of the field -effect semiconductor device are all improved.

Claims: CLAIMS 1. A field-effect semiconductor device comprising: a semiconductor substrate; a first via-hole electrode selectively formed in said semiconductor substrate so as to penetrate from the back surface to the top surface of said semicon actor substrate; a first dielectric film formed on the surface of said first via-hole electrode; a first electrode of a field-effect transistor, said first electrode being in contact with said first dielectric film and with said top surface of said semiconductor substrate; and a back-surface electrode formed on said back surface of said semiconductor substrate, said back-surface electrode together with said first via-hole electrode being unity. 2. A fieldeffect semiconductor device as set forth in claim 1, wherein said first electrode of said field-effect transistor is one selected from among a source electrode, a gate electrode, and a drain electrode. , 3. A field-effect semiconductor device as set forth in claim 2, said first electrode, said first dielectric film, and said first via-hole electrode constituting a capacitor. 4. A field-effect semiconductor device as set forth in claim 3, wherein said first electrode is said source electrode of said field-effect transistor. 5. A field-effect semiconductor device as set forth in claim 4, wherein said back-surface electrode is grounded. 6. A field-effect semiconductor device as set forth in claim 4, further comprising : a second via-hole slectrot said semiconductor substrate se as to penetrate from the back sorface to the top surface of said semiconductor substrate, said second via-hole electrode together with said back-surface electrode being a unity; and a second electrode formed on said top surface of said semiconductor substrate so as to contact said second via-hole electrode. 7. A field-effect semiconductor device as set forth in claim 6, further comprising a resistive film formed between said first electrode and said second electrode on said semiconductor substrate. 8. A feld-effect semiconductor device as set forth in claim 1, wherein said first electrode is a gate electrode of said field-effect transistor; further comprising: a source electrode of said field-effect transistor, formed on said semiconductor substrate; a second via-hole formed under said source electrode and in said semiconductor substrate so as to penetrate from the back surface to the top surface of said semiconductor substrate; a second via-hole electrode buried in said second via hole, and second via-hole electrode together with said back-surface electrode being a unity; and a conductive layer connected between said gate electrode and said first dielectric film. 9. A field-effect semiconductor device as set forth in claim 8, wherein said conductive layer comprises an inductor. 10. A field-effect semiconductor device as set forth in claim 9, wherein said device constitutes a matching circult. 11. A field-effect semiconductor device as {or06 in claim 3, wherein said semiconducor substrate and said first dielectric film have different rates. 12. A field-effect semiconductor device as set h in claim 6, wherein said semiconducter substrate and said second dielectric film have different etching rates. 13. A field-effect semiconductor device as set orth in claim 7, wherein said resistive film is of a semiconductor material dooped with impurity ions so as to form a resistor. 14. An integrated circuit device comprising at least one capacitor, said capacitor comprising: a semiconductor substrate; a via-hole electrode selectively formed in sala semiconductor substrate so as to penetrate from the back sure to the top surface of said semiconductor substrate; a dielectric film formed on the surface of said via-hole electrode; an electrode of a field-effect transistor, said electrode being in contact with said dielectric film and with said top surface of said semiconductor substrate; and a back-surface electrode formed on said back surface of said semiconductor substrate, said back-surface electrode together with said via-hole electrode being unity.

Inventors: TAKEUCHI, YUKIHIRO, YAMAMURA, SHIGEYUKI
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: H01L27
IPC codes: H01L23, H01L21, H01L27