MEMORY ADDRESS TRANSLATION SYSTEM

Abstract: In a memory addressing system, real and virtual addresses provided on a system bus (10) are stored in a buffer register (20). The stored addresses are provided to an address translator (30) which includes a content addressable memory (32) storing virtual addresses, and a random access memory (34) storing corresponding real addresses. If, in response to an applied address, the address translator (30) provides a match signal, the corresponding real address from the random access memory (34) is applied to a read address register (40). If no match signal is produced, the real address register (40) is provided with the contents of the buffer register (20). A rapid, simple memory address translation system is thus provided.

Description: MEMORY ADDRESS TRANSLATION SYSTEM Technical Field This invention relates to memory addressing systems of the kind including buffer storage means adapted to temporarily store real and virtual addresses provided on a system " bus, address translation means coupled to said buffer storage means and adapted to translate any one of a set of predetermined virtual ad¬ dresses applied thereto into a corresponding real address and to provide a match signal when a translation takes place, and address register means coupled to said buffer storage means and to said address translation means and adapted to receive the contents of said buffer storage means or a translated address from said address trans- lation means. Background Art Virtual addressing techniques are well-known in the computing art. Briefly, a main memory is limited in its storage capability, therefore, a second memory (bulk) such as. a magnetic drum, tape or magnetic core matrix is provided. This additional memory is in all instances much larger than the main memory of the com¬ puter. This virtual or bulk. emory is generally divided.. into parts that are referred to as segments. Each seg- ment is further divided into contiguous and equal modules referred to as pages. Each page is addressable. In operation, pages of information from the bulk memory are addressed by the virtual address and are transferred into the main memory. The locations within main memory are addressed by real addresses. In large computing systems, a number of programs may be running simul¬ taneously and pages from the bulk memory are called for and inserted into the main memory and removed therefrom when usage is no longer needed. Therefore, the addresses in main memory do not change where a virtually called-for page or segment can be located randomly throughout the main storage and swapped in and out of main storage as the pages are needed. The random location of segments and pages in main storage necessitates the translation of virtual addresses into real addresses using a table. The translation tables are typically stored in main memory. The accessing of the translation tables requires a significant amount of time which can degrade system performance. One approach that has been used is to store the translation information in a high speed associative store in order to reduce the number of accesses to main storage. The associative store is generally utilized to store the most recently used, or referenced, bulk data and the corresponding real addresses. Each time the virtual address is supplied by a processor for addressing the main store, search is made of the high speed asso¬ ciative store to determine whether or not rapid virtual- to-real address translation can be made using one of the entries stored therein. A memory addressing system of the kind speci- fied is known from U.S. Patent Specification No. 3,902,164. According to this known system an additional register is used to hold a representation of a boundary in the main store below which virtual and real addresses are equal, so that translation is not required. A com¬ parator compares each input address with the contents of the additional register and if the input address is less, than the boundary value AND gating means are activated to transfer the input address directly to a storage address register, inhibit gating means being rendered effective to prevent .the output of the address translator being entered in the storage address register. If the com¬ parison indicates that the input address is greater or equal to the boundary address, the AND gating means and inhibit gating means are not activated and the output of the address translator is applied to the storage address register via the non-activated inhibit gating means. If under these conditions no match is detected by the address translator, a further AND gate is effec¬ tive to cause the data processing unit to address a stored virtual address segment and page table to deter¬ mine the actual location specified by the input address. Although the known system improves address translation speed the use of inhibit gating means for the output of the address translator does have the dis¬ advantage of introducing some delay. Furthermore, the utilization of an additional register for the boundary value and a comparator has the further disadvantage of adding to the cost and complexity of the known system. Disclosure of the Invention It is an object of the present invention to provide a memory addressing system of the kind specified wherein the aforementioned disadvantages are alleviated. Therefore, according to the present invention, there is provided a memory addressing system of the kind specified, characterized in that said address register means is responsive to said match signal, being adapted to receive a real address provided by said address translation means in response to said match signal being produced and to receive the contents of said buffer storage means in response to said match signal not being produced. It will be appreciated that utilization of the match signal to directly control the address register means enables the provision of a rapid, simple system whereby the use of inhibit gates, an additional register for storing a boundary value, and a comparator, may be avoided. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of the preferred embodiment of the invention; <CU Fig. 2 is a transistor level schematic of a single bit of continuous dynamic address translation circuit; Fig. 3 is a diagram of the continuous dynamic address translation circuit shown in Fig. 1; Fig. 4 is an IC diagram of a buffer/latch circuit used in the preferred embodiment of Fig. 1; Fig. 5 is an IC diagram illustrating the real memory address register used in the circuit shown in Fig. 1; Fig. 6 is a waveform diagram illustrating the relationship of various clocking and bus signals with translation occurring; and Fig. 7 is a waveform diagram illustrating the relationship of various clocking and bus signals with translation not occurring. Best Mode for Carrying Out the Invention Referring to Fig. 1, there is shown in logic diagram form the preferred embodiment of the invention. A 32 bit system bus 10, on which address and/or data information appears, is coupled to the inputs of a buffer/latch 20. The buffer receives as one of its inputs a clocking signal X n . • Signals present on the system bus 10 are latched into buffer 20 upon the oc- currence of. a clocking pulse X_. The latched signals are available at the output of the buffer latch. These signals are coupled, by means of a bus 13 and a bus 11, to the inputs of a continuous dynamic address translator 30. Interposed on buses 13 and 11 are 32 AND gates 14 and 32 NOR gates 16, respectively. During non-Xø time the signal on bus 13 is identical to the signal on bus 11 except for the fact that the signal on bus 11 is inverted. During X0 time both buses are held logically low. * The output of the address translator 30 is coupled along a CAM bus 15 to the input of a real memory address register 40. When the computer/ of which the present invention is a part, is operating with virtual addresses the processor firmware generates a flag signal called VIRTUAL. When the computer is operating only with real addresses the firmware generates a flag signal called REAL. Also signals called CONT R and CONT V are formed by gating segments of the signals REAL and VIRTUAL (illustrated in Figs. 6 and 7). Additionally, match lines numbered 1-16 and the control signal labeled REAL are directed to a NOR gate 31, the output of which goes valid when all inputs are of a like level. The signal VALID is coupled to an input of the real memory address register to indicate that valid address data is present at its inputs. Additionally, the address register 40 receives as inputs the signal VIRTUAL, and a clocking signal X.. along with being coupled to the buffer/latch 20 by means of a bus labeled VAR. The output of the address register 40 is transmittable onto the system bus 10 when either a gate 12 or a gate 18 is activated. Gate 12 can be activated with the signal identified as CONT R. Gate 18 is activated with the signal designated CONT V. The continuous dynamic address translator 30 is comprised of two major memory units, one a content ad¬ dressable memory (CAM) and the other a random access memory (RAM) which will be described in more detail with the description of Fig. 2. In the operation of the circuit of Fig. 1, referring as needed to the waveforms X_ and X 1 of Fig. 6, in both the real and the virtual. odes and- all other, potential modes, any information appearing on the system bus 10 is always clocked into the buffer/latch 20 at the occurrence of pulse X.~. Once the signals are latched into the latch, they are available at the inputs to the AND gates 14 and the NOR gates 16 and to the contin¬ uous dynamic address translator. The signals appearing on the VA bus and VA bus received at the input of the dynamic address translator if they match, that is if a potential virtual address having a corresponding real address is stored within the memory unit, causes a translation, which outputs the real address onto the CAM bus 15. The translation is performed, that is, is attempted regardless of whether the address at the inputs to translator 30 was a virtual or a real address or even an address. If a match occurred, the output of the NOR gate 31 goes valid and the address register 40 is loaded with the information contained on CAM bus 15 if and only if, the information stored in buffer 20 has subsequently been proven to be a virtual address (signal VIRTUAL is active). If no match occurred, indicating that the address was either real or there was an error of some sort, then at the X, clock the same address as received from the system bus and stored in latch 20 will be clocked into the real memory address register 40. At a later machine time, the contents of the real memory address register 40 are outputted onto the system bus 10 as part of the actual memory reference. The control signals CONT R and CONT V are enabled so as to transfer the address onto the system bus following either the real mode and/or virtual mode operation, respectively. In certain systems it may be desirable to implement this control via a single common signal. As shown in Figs. 6 and 7, the real memory address enabled by CONT V is output during the next available X0 time. This is done for performance reasons. The real address on a non-translated (real or error) operation may be used as the memory address on a real mode operation and output as soon as possible.or saved in the real address register 40 for diagnostic purposes at some other time on an error case by CONT R. Referring now to Fig. 2 wherein a single bit slice of the continuous dynamic address translator 30 is disclosed in NMOS transistor (gate) circuits. In the preferred embodiment of the invention there are 16 groups (entries) each consisting of 32 bit slices. In addition, certain ones of the transistor circuits are marked with an asterisk indicating that they are of the depletion mode type. Adjacent to each of the gates, for fabrica¬ tion purposes, is a fraction indicating the gate ratios (conductance ratios). The unit 1 indicates a ratio of surface width equal to surface length. The fractional numbers have the numerator equal to the width and the denominator equal to the length. The transistor gates 1-5 are transfer gates or logic switches. A high signal at the control input opens the gate and allows a signal to pass through. The MATCH line connected to gates 3, 4 and 5 is connected as an input to the NOR gate 31. In practice there are 16 of these match lines, one for each entry. The group of transistor devices 6 is a single bit of an entry in the content addressable memory (CAM) 32. Transistor devices 6 form a static CAM latch which is loaded from the VA and VA lines when the signal called "WRITE VIRTUAL READ REAL" is enabled. This signal is not active during a translation operation, it is active only when an entry in the CAM is being built. However, even while the CAM is being loaded, the con¬ tinuous translation feature of the overall circuit is still in operation. The end result is that the attemp- ted translation is disregarded because no translation was warranted at the time that the entry into the CAM memory was built. The group of transistor devices 7 is a single-bit of an entry in the random access memory (RAM) 34 portion of the dynamic address translator 30. The memory portion 34 is accessed, with teal addresses.. Transistor devices 7 form a static RAM latch which is loaded from the VA and VA lines when the signal called "WRITE REAL" is enabled. This signal is inactive during an actual address translation operation. During all X times, that is, when the X n pulses are positive, an address is potentially being transferred over the system bus 10 and stored in the buffer latch. At that time the MATCH line is held high by the application of +5 volts through gate 4. The gate pulls the MATCH line towards +5 volts during each X Q time to eliminate the electrical charge time delays associated with conventional NMOS switches. During the non-X- time, the MATCH lines will discharge towards ground level unless an actual match occurred. In that instance, the MATCH line or lines as the case may be, will remain high. While the MATCH lines are being pulled high during X_, the VA and VA terms from the AND gates 14 and NOR gates 16 are held at a logical 0 (low) level. This is accomplished on the AND gates by the Xj term which is the invert of the X0 clock, and on the NOR gates by the X0 term. This guar¬ antees that the "wire-OR-ed" connection A between the gates 1 and 2 will be low because one or the other of the two control inputs to gate 1 or gate 2 must be active since they represent both polarities of the data bit in the CAM latch. Either gate 1 or gate 2 must be open. A low input on the control terminal of gate 3 will ensure that the MATCH line is not pulled towards ground via gate 3 while gate 4 is attempting to precharge it to a high level. Following the X_ clock, when the address for the potential translation is guaranteed to be stable on the VA and VA lines, gates 1 and 2 act as an Exclusive- OR circuit. If the contents of the CAM latch do not match the value of the information on the VA and VA lines, then the wired OR connection at gates 1 and 2 will be high, thus enabling gate 3. Gate 3 is connected to ground and when enabled will pull the MATCH line low indicating that there is no valid entry for, that address bit. Multiple CAM entry bits, 32 per entry, are wired- ORed at the MATCH line " connection for as many bits as are required in the translation. Again in this embodi¬ ment, 16 MATCH lines were used so there are 16 sets of 32 bit slices each. Any mismatch on any one of the circuits will cause the corresponding gate 3 to pull the common MATCH line low. If the comparison on the CAM bit and the VA and VA bits match for all translated address bits, then none of the MATCH disable gate 3 transistors will draw the MATCH line to 0 and the MATCH line will therefore remain high. When the MATCH line is high, the gate 5 is enabled so as to transfer the information stored in a corresponding RAM latch onto the CAM bus. Referring to Fig. 3, the continuous dynamic address translator 30 is shown comprised of a matrix of single bit slice circuits 30' . There are 16 entries each having a corresponding MATCH line. The full trans- lator is 32 bits wide. Referring to Fig. 4, the buffer/latch 20 is comprised of four octal latches of the type manufactured under Part No. SN74LS373 by Texas Instruments. Referring to Fig. 5, the real memory address register 40 is shown comprised of four octal latches 42 coupled to eight 2-to-l multiplexers (44 and 46) in the configuration shown; Fig. 5 repeated four times for each of the 8-bits of the 32 bit bus. The multiplexers 44 and 46 are of the type manufactured under Part No. SN74LS157 by Texas Instruments. In Fig. 6 the waveforms depict a timing se¬ quence for a virtual address to a real address trans¬ lation. In Fig. 7 the waveforms depict a timing se- quence corresponding to the receipt of a real address which bypasses the translation operation.

Claims: CLAIMS : 1. A memory addressing system including buffer storage means (20) adapted to temporarily store real and virtual addresses provided on a system bus (10), address translation means (30) coupled to said buffer storage means (20) and adapted to translate any one of a set of predetermined virtual addresses applied thereto into a corresponding real address and to provide a match signal when a translation takes place, and address register means (40) coupled to said buffer storage means (20) and to said address translation means (30) and adapted to receive the contents of said buffer storage means (20) or a translated address from said address translation means (30), characterized in that said address register means (40) is responsive to said match signal, being adapted to receive a real address provided by said address translation means (30) in response to said match signal being produced and to receive the contents of said buffer storage means (20) in response to said match signal not being produced. 2. A memory addressing system according to claim 1, characterized by gating means (12, 18) adapted to couple the contents of said address register means to said system bus (10) at a predetermined time. - 3. A memory addressing system according to claim 1, characterized in that said address translation means (30) includes a content addressable memory element (32) responsive to a virtual address bit provided by said buffer storage means (20) and a random access memory element (34) arranged to store a real address bit and to provide said real address bit as an output in re¬ sponse to a signal from said content addressable memory element (32) . 4. A memory addressing system according to claim 1, characterized in that said address register means (40) includes latching means (42), and multiplexer means (44, 46), said multiplexer means (44, 46) havinq first input means coupled to said address translation means (30), second input means coupled to said buffer storage means (20), and output means coupled to said latching means (42), said multiplexer means (44, 46) being responsive to said match signal to provide at its output means the signals on its first input means or its second input means according to whether said match signal is or is not provided.

Inventors: CELIO JOHN ANTHONY, MALIK ASHGAR KAMAL, SANWO IKUO JIMMY, CELIO, JOHN, ANTHONY, MALIK, ASHGAR, KAMAL, SANWO, IKUO, JIMMY
Applicants: NCR CO, NCR CORPORATION
Application year: 1983
Main classification: G11C9
IPC codes: G06F12