BLOCK COUNTER SYSTEM TO MONITOR DATA TRANSFERS

Abstract: A system is disclosed which is usable to monitor data-being-transferred in terms of blocks (512 bytes or 256 words) wherein the date-being-transferred is temporarily stored in a RAM buffer memory. Thus, data blocks being transferred from a main host computer to a peripheral terminal unit (as a magnetic tape unit) via a Tape Control Unit (TCU) can be monitored to indicate, at certain intervals, the balance of data residing in the buffer memory during moments between cycles where data has been shifted into and/or shifted out of the buffer memory.

Description: FIELD OF THE INVENTION This invention is related to systems where data transfers are effectuated between a peripheral terminal unit and a main host computer wherein an intermediate I/O subsystem is used to perform the housekeeping duties of the data transfer. BACKGROUND OF THE INVENTION A continuing area of developing technology involves the transfer of data between a main host computer system and one or more peripheral terminal units. To this end, there has been developed I/O subsystems which are used to relieve the monitoring and housekeeping problems of the main host computer and to assume the burden of controlling a peripheral terminal unit and to monitor control of data transfer operations which occur between the peripheral terminal unit and the main host computer system. A particular embodiment of such an I/O subsystem has been developed which uses peripheral controllers known as data link processors whereby initiating commands from the main host computer are forwarded to a peripheral-controller which manages the data transfer operations with one or more peripheral units. In these systems the main host computer also provides a "data link word" which identifies each task that has been initiated for the peripheral-controller. After the completion of a task, the peripheral-controller will notify the main host system with a result/descriptor word as to the completion, incompletion or problem involved in the particular task. These types of peripheral-controllers have been described in a number of patents issued to the assignee of the present disclosure and these patents are included herein by reference as follows: U.S. Patent 4,106,092 issued August 8, 1978, entitled "Interface System Providing Interfaces to Central Processing Unit and Modular Processor-Controllers for an Input-Output Subsystem", inventor D.A. Millers, II. U.S. Patent 4,074,352 issued February 14, 1978, entitled "Modular Block Unit for Input-Output Subsystem", inventors D.J. Cook and D.A. Millers, II. U.S. Patent 4,162,520 issued July 24, 1979, entitled "Intelligent Input-Output Interface Control Unit for Input-Output Subsystem", inventors D.J. Cook and D.A. Millers, II. U.S. Patent 4,189,769 issued February 19, 1980, entitled "Input-Output Subsystem For Digital Data Processing System", inventors D.J. Cook and D.A. Millers, II. U.S. Patent 4,280,193 issued July 21, 1981, entitled "Data Link Processor for Magnetic Tape Data Transfer System", inventors K.W. Baun and J.G. Saunders. U.S. Patent 4,313,162 issued January 26, 1982, entitled "I/O Subsystem Using Data Link Processors", inventors K.W. Baun and D.A. Millers, II. U.S. Patent 4,322,792 issued March 30, 1982, entitled "Common Front-End Control for a Peripheral Controller Connected to a Computer", inventor K.W. Baun. The above patents provide a background understanding of the use of the type of peripheral-controllers known as "data link processors", DLP, used in a data transfer network between a main host computer and peripheral terminal unit. In the above mentioned Baun patent, there was described a peripheral-controller which was built of modular components consisting of a common front end control circuit which was of a universal nature for all types of peripheral controllers and which was connected with a peripheral dependent board circuit. The peripheral dependent circuit was particularized to handle the idiosyncrasies of specific peripheral terminal units. The present disclosure likewise uses a peripheral-controller (data link processor) which follows the general pattern of the above described system, in that the peripheral-controller uses a common control circuit or common front end which works in coordination with a peripheral dependent circuit which is particularly suited to handle a specific type of peripheral terminal unit, such as a Tape Control Unit (TCU) which connects to one or more magnetic tape units. US-A-4 293 928 discloses a system using a peripheral-dependent circuit board for providing the specific functions required for data transfers between a peripheral terminal unit and a peripheral-controller including a common control circuit card. The peripheral-dependent circuit board provides logic means for executing micro code word operators received from the common control circuit card and provides means for selecting a source of data that is to be transmitted for temporary storage in a buffer memory. The peripheral-dependent board also provides address logic means for formulating addresses to be used for reading and writing of data out of and into the buffer memory. US-A-4 220 997 discloses apparatus for transferring information between an information store and a data channel. A control magnitude is produced to drive the information store at a predetermined speed in dependence of the quantity of information to be recorded. The control magnitude is derived from the level of fullness of a cyclical operating buffer store provided in the data channel. The invention relates to a network wherein data is transferred between a main host computer and a magnetic tape peripheral unit via a peripheral-controller, wherein said peripheral-controller is initiated by commands from said host computer to execute data transfer operations and said peripheral-controller includes a common control circuit unit for sequencing microcode instructions and a peripheral dependent circuit unit for managing said tape peripheral unit, wherein said peripheral-controller includes buffer memory means for temporarily storing blocks of data being transferred, said buffer memory means having channels of connection to said tape peripheral unit and said host computer, and wherein said peripheral dependent circuit unit includes status means for providing information relating to the amount of data residing in said buffer memory means. The invention is characterised in that signal output means are connected to said status means and function to provide status signals to said common control circuit unit indicating the number of blocks of data residing in said buffer memory means, in that said status means includes: shift register means which shifts up to count the number of blocks of data received into said buffer memory means, in that, when said buffer memory is filled with blocks of data from said host computer, said shift register causes said signal output means to pass information data to said common control circuit unit which then disconnects said host computer from said buffer memory means, after which said common control circuit unit connects said peripheral tape unit to said buffer memory means. A control logic for indicating the state of the buffer memory means is claimed in EP-A-0 109 308 from which the present Specification is divided. Thus, there is disclosed a system for regulating data transfer operations between host and peripheral whereby a peripheral-controller senses blocks of data stored in its RAM buffer in order to choose routines for data transfer appropriate to the data condition of the RAM buffer. The peripheral-controller makes use of a block counter monitoring system which will inform the peripheral-controller and the main host system of the "numerical block status" of data in the RAM buffer memory means. In particular, the present invention discloses a system whereby the common front end (common control) circuit uses routines providing microcode instructions to address registers which access locations in the RAM buffer memory for the insertion of data or the withdrawal of data. There are two address registers, one for addresses of data taken from/to the peripheral unit and one for addresses of data which are to be forwarded from/to the main host computer. A block counter logic circuit receives input from the peripheral address register and the system address register. In addition, a flip-flop output to the block counter logic circuit indicates the direction of data flow as being a "Write" (host-to-peripheral) or a "Read" (peripheral-to-Host). The block counter logic circuit provides two output logic signals which control a block counter. This enables the block counter to be shifted up or shifted down so that the internal signal data indicates the number of blocks of data residing in the RAM buffer memory. Certain parameters may be set to trigger signal output conditions when the amount of data in the RAM buffer memory falls below a certain figure. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates the block counter system of the present disclosure which is used to inform the data transfer system of the status of a buffer memory means. FIG. 2 is a system diagram showing the host computer cooperating with a peripheral-controller in order to control data transfer to and from a peripheral unit. FIG. 3 is a drawing showing an eight bit shift register which can be shifted up or down according to conditions which occur between certain logic signals and clock signals. FIG. 4 is a diagram showing how the block counter logic unit of FIG. 1 is organized to operate during Read or Write operations and the effect of either shifting up or shifting down the shift register. FIG. 5A is a schematic drawing illustrating the significance of each bit-position in the block counter. FIG. 5B is a chart indicating various "shift" relationships of the block counter with regard to "Read" and "Write" operations. A "Read" operation takes data from a peripheral magnetic tape unit and temporarily stores it in a RAM memory buffer for later transfer to the host system. A "Write" operation takes data from the main host system for temporary storage in the RAM buffer memory for subsequent transfer to a selected magnetic tape unit via a TCU or Tape Control Unit. DESCRIPTION OF PREFERRED EMBODIMENTS Referring to FIG. 2, the overall system diagram is shown whereby a host computer 10 is connected through an I/O subsystem to a peripheral unit, here for illustrative purposes shown as a tape control unit 50 tc . As per previous descriptions in the above cited patents which were included by reference, the I/O subsystem may consist of a base module which supports one or more peripheral-controllers, in addition to other connection and distribution circuitry such as the distribution control circuit 20 od and the data link interface 20 i . The peripheral-controller 20 t is shown in modular form as being composed of a common front end circuit 10 c and a peripheral dependent circuit shown, in this case, as being composed of two peripheral dependent boards designated 80 p1 and 80 p2 . In this network situation, it is often desired that data from the main host computer be transferred on to a peripheral unit, such as a magnetic tape unit, for recording on tape. This would be done by a peripheral tape control unit TCU such as 50 tc . Likewise, at times it is desired that data from the magnetic tape unit be passed through the tape control unit to be read out by the host computer. Thus, data is transferred in a bidirectional sense, that is, in two directions at various times in the activities of the network. The key monitoring and control unit is the data link processor 20 t which when initiated by specific commands of the host computer will arrange for the transfer of the desired data in the desired direction. As seen in FIG. 1, the RAM buffer 22 is used for temporary storage of data being transferred between peripherals and the main host computer. In the preferred embodiment this RAM buffer has the capability of storing at least six "blocks" of data, each block of which consists of 256 words. Again referring to FIG. 1, a block counter logic unit 33 c is used to receive input from two address registers designated as the peripheral address register, P a , and the system address register, S a . The peripheral address register, P a , handles addresses required when data is retrieved from the peripheral tape unit or when data is being sent to the peripheral tape unit. The system address register, S a , is used when data is being received from the host system into the buffer 22 when data is being sent to the host system from the buffer 22. These two address registers in FIG. 1 are seen to receive their address data via microcode signals from the common front end circuit 10 c of FIG. 1. The address data outputs from P a and S a are fed to the RAM buffer 22 in order to address the desired location in the buffer memory. Further, the block counter logic unit 33 c receives one input designated "P Carry" from the peripheral address register and another input "S Carry" from the system address register, in addition to a Read/Write control signal from read-write flip-flop 33 f . The flip-flop 33 f is controlled by microcode signals from the peripheral-controller common front end unit 10 c . The block counter logic unit 33 c provides a first logic signal LS₁ and a second logic signal LS₀ which are fed to OR gates G₁ and G₀. These gates also have additional inputs from the microcode of the common front end card 10 c which inputs can be used to simulate the LS₁ and LS₀ signals for diagnostic or other control purposes. The OR gates provide two output signals designated S₁ and S₀ which are fed to the block counter 34 c . As will be seen in FIG. 3, the output signals S₁ and S₀ are combined at certain times on occurrence of rising clock signals in order to provide conditions which will make the block counter either "shift up" or "shift down" or "no shift". Referring to FIG. 3, there is seen a schematic drawing which illustrates the use of the block counter 34 c of FIG. 1. Referring to FIG. 3, there is seen, schematically, an eight bit shift register which will be affected at selected points in time where the clock signal is in its "rising" state as illustrated by the arrows shown in FIG. 3. Referring to the leftmost schematic of the shift register, it will be seen that there are two "ones" which illustrate that the RAM buffer 22 has been loaded with two full blocks of data. At time T₁ it will be seen that conditions are such that "no shift" has occurred and the two "ones" remain in the shift register. At time T₂ there is a "shift up" and the shift register now has three bits with the "1" signal. At time T₃ there is a "shift down" signal and the shift register is back where two bit positions include a "1". At time T₄ there is a "shift up" and the shift register now has three bit positions manifesting the "1" signal, which indicates three full blocks of data residing in buffer 22 at that moment. Referring to FIG. 4, there is seen a chart whereby the block counter logic unit 33 c is organized to show overall operating conditions. Thus, as seen in the FIG. 4 chart, the conditions of the S Carry and P Carry during the "Read" condition show that there is a no shift or no change when S Carry and P Carry are the same, that is to say they are both 0 or they are both 1. However, when S Carry is "0" and the P Carry is equal to "1", then there is an up shift, while if the S Carry is "1" and the P Carry is "0", there is a down shift during "Read" operations. Referring to FIG. 4, it is seen that during "Write" operations, again when the S Carry and the P Carry are equal (both "0" or both "1") to each other, then there is no change or shift in the shift register. However, when the S Carry equals "0" and the P Carry equals "1" there is a down shift in this situation, and when the S Carry is equal to "1" and the P Carry is equal to "0" there is an up shift. The block counter 34 c will reflect the situation that when data is being taken out of the magnetic tape unit in order to be fed to RAM buffer 22 ("Read" operation), the block counter will shift up unless at the same time there is data being removed from buffer 22 for transfer to the main host computer system in which case the block counter will shift down. Thus, the condition of the block counter's numerical status will indicate the "balance" between what data has gone out of and what data has come into the buffer 22. Referring to FIG. 4, if there is a "Write" operation, this determines that data is to be written into the magnetic tape unit. Then, as data is removed from the RAM buffer over to the magnetic tape unit, the block counter will shift down but if more data is transferred from the main host computer into the RAM buffer 22, the block counter will be shifted up. Thus, again the placement of "ones" in various bit positions provides a running balance of the data blocks taken out as against the data blocks taken in at any given period. Referring to FIG. 4 there are certain logic equations which indicate the logic used in the block counter logic unit 33 c . In the following logic equations it should be indicated that the asterisk refers to AND logic operation while the plus sign refers to OR logic operation. (a) If signal counter S₁ equals "1" and signal S₀ equals "0", there occurs what may be called a condition of "Up enable" which is equal to (Read * S Carry * P Carry) + (Write * S Carry * P Carry ). (b) Under the conditions where the signal S₁ equals "0" and the signal S₀ equals "1", this could be considered as a "Down enable" which is equal to (Read * S Carry * P Carry ) + (Write * S Carry * P Carry). (c) In the condition where the signal S₁ equals "0" and the signal S₀ equals "0", there is the condition called "no change". This is equal to (Read * S Carry * P Carry) + (Write * S Carry * P Carry). (d) The condition known as the "host access error", H e , causes the setting of a flip-flop 34 e , FIG. 1. (This is also called a block counter error). Thus, the host access error signal or block counter error signal is a result of: H e = (Read * 6 BLKFUL) + (Write * 1 BLKFUL ). Thus, on a Read operation, a full RAM buffer (six blocks of data) will signal an error condition. Likewise, on a Write operation, a single (one) remaining block of data will trigger an error condition. Referring to FIG. 5A, a schematic drawing of the block counter 34 c is shown to indicate that when a "1" resides in a series of bit positions, it is an indication of how many blocks of data reside in the RAM buffer 22 (FIG. 1). For example, if a "1" resides in each of bit positions 1, 2, 3, 4, this indicates that "4 blocks" of data reside in RAM 22. Each "block" consists of 256 words (512 bytes of eight bits each). In FIG. 5B the chart illustrates that during "Read" operations: (a) As the P Carry increases (data being transferred from peripheral tape to buffer memory 22), the block counter 34 c will "shift up" indicating the buffer is being "loaded". (b) As the S Carry increases (data from buffer memory being transferred to main host system), the block counter 34 c will "shift down" indicating the buffer memory is being "emptied". In FIG. 5B the chart illustrates that during "Write" operations: (c) As S Carry increases (data being loaded in buffer memory from main host system), the block counter 34 c will "shift up" to indicate the number of blocks of data in the buffer. (d) As P Carry increases (data in buffer being unloaded for transfer to peripheral tape unit), the block counter 34 c will "shift down" and show how much data is left remaining in buffer 22. In FIG. 5B, during "Read" operations, when a "1" appears in the 6th bit position of block counter 34 c , then a flip-flop circuit 34 e (FIG. 1) is "set" and provides a signal to the common front end circuit 10 c which will inform the main system of an "access-error" condition. This signifies that the buffer memory 22 was "overfilled" in that the main host system did not accept data quickly enough. During "Write" operations, when the buffer memory 22 has received six blocks of data from the host system, and the 1st bit position (1 BLKFUL) becomes "0", this indicates that the buffer memory has been completely unloaded (cleared) and then the flip-flop 34 e is set to signal the common front end circuit 10 c that more data is required from the host. This indicates the host did not supply data quickly enough to the RAM buffer 22. There has been thus described a system by which it is possible to monitor blocks of data being transferred between peripheral units and a main host computer when there are simultaneous flows of data being put into or taken out of a RAM buffer means.

Claims: A network wherein data is transferred between a main host computer (10) and a magnetic tape peripheral unit (50 tc ) via a peripheral-controller (20 t ), wherein said peripheral-controller is initiated by commands from said host computer to execute data transfer operations and said peripheral-controller includes a common control circuit unit (10c) for sequencing microcode instructions and a peripheral dependent circuit unit (80 p1 & 80 p2 ) for managing said tape peripheral unit, wherein said peripheral-controller includes buffer memory means (22) for temporarily storing blocks of data being transferred, said buffer memory means having channels of connection to said tape peripheral unit and said host computer, and wherein said peripheral dependent circuit unit includes status means (34 c ) for providing information relating to the amount of data residing in said buffer memory means; characterised in that signal output means (34 e ) are connected to said status means and function to provide status signals to said common control circuit unit indicating the number of blocks of data residing in said buffer memory means, in that said status means includes: shift register means (Fig.3) which shifts up to count the number of blocks of data received into said buffer memory means, in that, when said buffer memory is filled with blocks of data from said host computer, said shift register causes said signal output means to pass information data to said common control circuit unit which then disconnects said host computer from said buffer memory means, after which said common control circuit unit connects said peripheral tape unit to said buffer memory means. A network according to Claim 1, wherein, upon connection of said peripheral tape unit to said buffer memory means, said common control circuit unit causes execution of data transfer from said buffer memory means to said peripheral tape unit. A network according to Claim 2, wherein said shift register shifts down each time a block of data is removed from said buffer memory means to said peripheral tape unit. A network according to Claim 3, wherein, when said shift register is reduced by one block count, said signal output means will pass information to said common control circuit causing it to reconnect to said main host computer for enablement of more data transfer to said buffer memory means. A network according to any of the preceding claims, wherein said host system initiates a Write operation command to said peripheral-controller to transfer data from main host computer, and said common control circuit unit initiates routines to transfer data from said host computer to said buffer memory means. A network according to any of the preceding claims, wherein said host system initiates a Read operation command to said peripheral-controller to transfer data from said peripheral tape unit to said buffer memory means.

Inventors: SHETH, JAYESH V.
Applicants: UNISYS CORPORATION
Application year: 1983
Main classification: G06F13
IPC codes: G06F13, G06F3