LATERAL DMOS TRANSISTOR DEVICE HAVING AN INJECTOR REGION

Abstract: A lateral DMOS transistor (1) includes a surface-­ adjoining injector region (32) between the channel region (16) and the drain region (20) of the device. This injector region (32) is connected to an external source of potential and serves to substantially decrease the on-resistance of the device by injecting minority carriers into the drift region when the device is in the "on" state. This improvement in on-resistance is obtained without degrading the breakdown voltage characteristics of the transistor.

Description: Lateral DMOS transistor device having an injector region. Background of the invention The invention is in the field of metal-oxide semiconductor (MOS) field-effect transistor devices, and restates specifically to lateral DbX)S field-effect transistors. Such transistors are often referred to as double-diffused mS- transistors altough one or nlore zones may be made entirely or p:#ttly by ion wplantation, and there gate electrodes may consist of conductive layers other than metals, for instance of polycrystalline silicon Likewise, the insulating material between the gate electrode and the semiconductor surface may be another insulator than an oxide, for instance silicon nitride. A typical high-voltage lateral D > X)S transistor is shown in Fig. 1 of U.S. Patent No. 4,300,150. This device includes a semiconductor substrate of a first conductivity type (p-type), an epitaxial surface layer of a second conductivity type (n-type) on a major surface of the substrate, a surface-adjoining channel region of the first conductivity type in the epitaxial layer, a surface-adjoining source region of the second conductivity type in the channel region, and a surface-adjoining drain region of the second conductivity type in the epitaxial layer and spaced apart from the channel region. An insulating layer is provided on the epitaxial surface layer and covers at least that portion of the channel region located between the source and drain. A gate electrode is provided on the insulating layer, over the portion of the channel region located between the source and drain and is electrically isolated from the eptaxial surface layer, while source and drain electrodes are connected respectively to the source and drain regions of the tranistors. Such prior art high-voltage 1 ] 40S transistors typically have a relatively thick epitaxial layer, of the order of about 25-30 micrometers for a breakdown voltage of about 250V. It has been found that the breakdown characteristics of high-voltage semiconductor devices can be improved by using the REduced SURface Field (or RESURF) technique, as described in "High Voltage Thin Layer Devices (RESURF Devices)", "International Electronic Devices seting Technical Digest", December, 1979, pages 238 - 240, by Appels et al, and U.S. Patent No. 4,292,642, incorporated herein by reference. Essentially, the improved breakdown characteristics of RESURF devices are achieved by employing thinriner but more highly doped epitaxial layers to reduce surface fields. Additionally surface regions having no direct external connections have been used to redistribute surface fields in MOS devices, as shown, for example, in U.S. Patent No. 4,300,150 and Japanese Kokai No. 45074 - 81. The RESEPF technique was applied to lateral SS transistors, as reported in "Lateral DMOS Power Transistor Designtt, "IEEE: Electron Device Letters", Vol. EDL-1, pages 51 - 53, April 1978, by Colak et al, and the result was a substantial improvement in device characteristics. In high-voltage DMOS devices, there is normally a trade-off between breakdown voltage and on-resistance, with the goal being to increase the breakdown voltage level while maintaining a relatively low on-resistance. Using the prior art #ESURF technique, and for reference assuming a constant breakdown voltage, an improvement (e.g. decrease) in on-resistance by a factor of about 3 may be obtained in a device occupying the same area as a conventional (thick epitaxial layer) DMOS device. Nevertheless, a further improvement in the on-resistance characteristics of such devices would be extremely desirable, particularly for high-voltage power devices where on-resistance is an important parameter. Ideally, such an improvewnt in on-resistance should be obtained without degrading the breakdown voltage characteristics of the devices. 5¯OF OFTHE INVENTION It is therefore an object of the present invention to provide a lateral Db50S transistor which features improved on-resistance characteristics. It is a further object of the invention to provide a lateral DMOS transistor with improved on-resistance chacteristics without degrading the breakdown voltage characteristics of the device. In accordance with the invention, these objectives are achieved by a lateral DK)S transistor of the type described above which is characterized in that a surface-adjoining injector region of the first conductivity type is provided in the epitaxial surface layer of the second conductivity type and forms a p-n junction therewith. This injector region is located between the channel region and the drain region, and is closer to the channel region than the drain region. In a preferred embodiment of the invention, the injector region is located adjacent to, but not in contact with, the channel region. An electrical connection is provided to the injector region by an injector electrode so that an external voltage can be applied directly to the injector region. This injector region serves to inject minority carriers (holes) into the drift region of the device when the transistor is in the "on" state, thus resulting in more electrons being emitted from the source to maintain charge neutrality. This in turn will result in a substantial reduction in on-resistance without degrading the breakdown voltage characteristics of the device. Brief. description of the drawing The Figure is across-sectional view of a lateral DSS transistor in accordance with the invention. Description of the preferred embodiment The single Figure of the drawing shows a mS transistor suitable for high-voltage applications. It should be noted that the Figure is not drawn to scale, and in particular the vertical dimensions are exaggerated for improved clarity. Additionally, semiconductor regions of the same conductivity type are shown hatched in the same direction. In the Figure, a lateral DMOS transistor 1 has a semiconductor substrate 10 of a first conductivity type, here p-type, with an epitaxial surface layer 12 of a second conductivity type opposite to that of the first, here n-type, on a first major surface 11 of the substrate. A surface-adjoining channel region 16 of the first conductivity type is provided in the epitaxial layer and forms a p-n junction 17 therewith. A surface-adjoining source region 14 of the second conductivity type is provided in the channel region 16, and a surface-adjoining drain region 20, also of the second conductivity type, is provided in the epitaxial layer 12 at a location which is spaced apart fran the channel region 16. The channel region 16 has a surface-adjacent portion 18 located between the source and drain regions which forms the channel of the device. An insulating layer 22 is provided or the epitaxial surface layer 12 and covers at least that portion of the channel region 16 located between the source and drain regions of the transistor. While insulating layer 22 is shown as a stepped layer and is of silicon oxide, other configurations and insulating materials can be used without departing from the scope of the invention. A gate electrode 24 (terminal G) is provided on the insulating layer 22 over the channel 18, and source (26) and drain (28) electrodes (terminals S and D, respectively) provide electrical connections to the source and drain regions of the transistor. A substrate-electrode 30 (terminal SS) provides an electrical connection to the second major surface 13 of the substrate on its lower side. Devices of this general type (as so far described) are well known in the art, and hence will not be described in further detail. As noted above, the epitaxial surface layer 12 in such devices is typically a relatively thick layer, having a thickness of the order of about 25 to 30 micrcmeters for breakdown voltages of about 250 Volts. Such relatively thick epitaxial layers tend to make these devices subject to reverse avalanche breakdown of the p-n junction 17 in the curved area of the junction beneath the gate electrode 24 due to field crowding in this area. This characteristic is particularly undesirable in high-voltage applications because it l#mits the maximum operating voltage of the transistor. The Reduced Surface Field (REStJRF) technique, as applied to lateral DbDS transistors in the previouslynentioned Colak et al paper, serves to partially overcome this problem. By substantially reducing the epitaxial layer thickness, down to about 3 to 15 micrcmeters, while at the same time increasing the doping level in the epitaxial layer to maintain an acceptable on-resistance value, a substantial iitprovert#nt in highvoltage breakdown characteristics can be obtained. Thus, the Figure, as so far described, may also represent a RESURF DMOS transistor,assuming that the appropriate thickness and resistivity values for the epitaxial layer 12 are selected. In accordance with the RESURF technique, the product of doping concentration and epitaxial layer thickness 12 2 (Nepi x depi) should typically be approximately 10 atorns/an . Using this epi technique, on-resistance can be reduced by a factor of about 3 for a device Occupying the same area as a conventional device, while maintaining the same breakdown voltage. Nevertheless, a further reduction in onresistance would be extremely desirable, particularly for devices intended for high-power applications. The present invention is based upon the discovery that by providing a surface-adjoining injection region in the epitaxial surface layer between the channel region and the drain region of the device, a substantial further reduction in on-resistance can be obtained without degrading breakdown voltage characteristics. While the invention may be applied to conventional D > ] OS transistors, optirrum performance is obtained by providing the injection region of the invention in devices in which the epitaxial layer is selected in accordance with the RESUME technique, as described above. In accordance with the invention, lateral DMOS transistor 1 shown in the Figure is provided with a surface-adjoining injector region 32 of the first conductivity type (n-type) in the p-type epitaxial surface laye#r 12, thus forming p-n junction 33 between the injector region 32 and the epitaxial layer 12. Injector region 32 is located between the channel region 16 and the drain region 20, and, as shown in the Figure, is closer to the channel region than to the drain region. In a preferred embodiment of the device, injector region 32 is located adjacent to, but not in contact with, channel region 16 for optimum operation. In a typical RESURF device, in which the epitaxial layer 12 may have a thickness of about 10 micrometers and a doping level of about 3 1.0 x 1015 atoms/an , and the substrate 10 has a doping level of about 4.0 x 1014 atoms/cm3, the injector region 32 can have a thickness of 3 about 1.0 micrometer and a surface doping level of about 10 atoms/cm In this example, the substrate and injector region are of p-type material, while the epitaxial layer is n-type. The itethod of formation of the injector region is not critical, so that conventional implatantation diffusion techniques may be used in its fabrication as desired. The device construction is carpleted by an injector electrode 34 which is electrically connected to injector region 32 at its upper surface. The injector electrode 34 contacts the injector 32 through insulating layer 22 to provide a direct injector electrode connection (terminal I) at the upper surface of the device. A lateral DE transistor in accordance with the invention, such as that shown in the Figure, will be operated in "on" state with a small positive voltage (in the range of about 1 to 3 volts) applied directly to the injector region by injection electrode 34. With the source electrode 26 and substrate electrode 30 connected to ground, and a high voltage applied to the drain electrode 28, the transistor is turned "on" by placing a suitable positive voltage on the gate electrode 24. Majority carriers (electrons) will then flow fran the source region 14 through the channel 18 and the drift region (that part of the epitaxial layer 12 between the channel and drain) toward the drain region 20. When the device is "on", the voltage in the epitaxial layer 12 in the vicinity of injector region 32 is typically less than a volt, so that the p-n junction 33 will be forward biased, and minority carriers (holes) will be injected from the injector region 32 into the drift region. This will cause nore electrons to enter the drift region from the source region 14 in order to maintain charge neutrality in the drift region, thus resulting in a S ignif cant reduction in on-resistance. In the "off" state, with substantially no conduction between the source and drain, the voltage in the region of the epitaxial layer 12 in the vicinity of the injector region 32 will rise to about 10 volts, thus reverse-biasing the p-n junction 33 and automatically cutting off the injection of minority carriers fran the injection region into the drift region. When the device is switched "off", the holes present in the drift region due to injection in the "on" state will diffuse to and be collected by the grounded substrate, which acts as a hole sink. Turn- off speed is enhanced by both the relative thinness of the epitaxial layer 12 (due to the use of the RESUE technique) and the large interfacial area between the epitaxial layer 12 and the substrate 10. With respect to the injector bias voltage, two nodes of operation are possible. If a relatively low voltage (for example 1.5 volts) is applied to the injector region, this voltage can be maintained constant in both the "on" and "off" states. On the other hand, if a higher voltage is applied to the injector region (for example 3.0 volts) this voltage must either be reduced or removed in the "off" state. While this second itode of operation requires sornewhat nore corrplexivity, it results in a greater reduction in on-resistEhnce. Computer analysis and preliminary testing indicate that use of an injector region in accordance with the present invention can decrease the on-resistance of a lateral XS transistor by a factor of about 10 times, and that this substantial improvement can be obtained with sub stantially no degradation of the breakdown voltage characteristics of the device. While it is believed that devices in accordance with the present invention will have somewhat slower switching speeds than conventional lateral DeX)S devices, it is predicted that switching times will be faster than those for conventional bipolar power transistors and nore than adequate for most applications. Thus, by providing a lateral DE transistor with an injector region between the channel region and the drain region, the present invention serves to substantially reduce the on-resistance characteristics of the device without impairing its high-voltage breakdown characteristics. Finally, while the invention has been particularly shown and described with reference to a preferred embodin#nt thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing form the spirit and scope of the invention.

Claims: 1. A lateral DMOS transistor having a semiconductor substrate of a first conductivity type, an epitaxial surface layer of a second conductivity type opposite to that of the first on a first major surface of said substrate, a surface-adjoining channel region of said first conductivity type in said epitaxial layer and forming a rn junction therewith, a surface-adjoining source region of said second conductivity type in said channel region, a surface-adjoining drain region of said second conductivity type in said epitaxial layer and spaced apart fran said channel region, an insulating layer on said surface layer and covering at least that portion of said channel region located between said source region and said drain region, a gate electrode on said insulating layer, over said portion of the channel region and electrically isolated fran said surface layer, source and drain electrodes connected respectively to the source and drain regions of said transistor, and a substrate electrode on a second major surface of said substrate opposite to the first, characterized in that a surface-adjoining injector region of said first conductivity type is provided in said epitaxial surface layer of the second conductivity type and forms a p-n junction therewith, said injector region being located between said channel region and said drain region and closer to said channel region than said drain region, and that an injector electrode is electrically connected to said injector region so that an external voltage can be applied directly to said injector region. 2 A lateral iSOS transistor as in calim 1 wherein the doping concentration N and thickness d of said epitaxial surface layer are selected in accordance with the REduced SURface Field (RESURF) technique so that approximately N x d = 1012 atans/cm2. 3. A lateral BOS transistor as in claim 1, wherein said surfaceadjoining injector region is located adjacent to, but not in contact with, said channel region. 4. A lateral DMOS transistor as in claim 1, wherein said injector region has a thickness of about one micrometer and a surface doping level 3 of about 1019 atms/cm3.

Inventors: COLAK, SEL, SINGER, BARRY MANA, STUPP, EDWARD HENRY
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1983
Main classification: H01L29
IPC codes: H01L29