PROCESS FOR INTEGRATED CIRCUIT METALLIZATION WITH LOW VIA RESISTANCE

Abstract: Controlling Al₂Cu precipitation in copper doped alumi­ num by evaporating the aluminum metallization containing 3 to 4% copper at about 210°C on SiO₂ coated semiconductor devices reduces via resistance. In multilevel metallization, sintering can be optionally performed at 400°C for 75 minutes to cause intermetal diffusion at vias between the metallization levels.

Description: PROCESS FOR INTEGRATED CIRCUIT METALLIZATION WITH LOW . .. .. . VIA RESI#STANCE#. This invention relates to the fabrication of semiconductor devices, and more particularly to the fabrication of interconnection metallization systems atop the semiconductor devices. Advances in modern semiconductor device technology have allowed increasing numbers of devices and circuits to be fabricated within a single semiconductor chip. This has required increasing miniaturization of the interconnection metallization system connecting the elements within the chip into circuits. Such miniaturization results in decreased costs and improved performance in integrated circuits but is constantly crowding the fabrication technology, particularly the photolithographic and etching techniques of the interconnection metallization. In integrated circuit design, for example, thousands of impurity regions are conventionally fabricated in a silicon chip, approximately 3-5 mm (125-200 mils) square. Such regions form transistors, diodes, resistors and the like which are then connected together by thin film wiring patterns atop the chip to form various circuits and for connection to input-output terminals. This interconnection thin film system atop the chip is extremely complex and usually employs two or three separate levels of conductive patterns, each separated by one or more layers of dielectric material. Ordinarily, the first level conductive pattern on the chip surface interconnects the transistors, resistors, diodes, etc. into circuits and also provides for cir cuit-to-circuit connection. The second level conductive pattern makes contact to the first level by wet or dry etched vias through an insulation layer. With the increase in circuit density such as 10k bit bipolar memories, via size is reduced to 5 ssm. Interfacial contami o nant films (e.g. oxide) 20 A in thickness within such small vias become detrimental to circuit switching speeds. The second level conductive pattern conventionally completes the circuit-to-circuit connections and makes contakt to I/O terminals which are connectable to a support such as a module, substrate or card. Alternatively, a third level may be required for power and I/O connections. Four levels of metallization may be required in future products. Aluminum-copper metallization has been typically used in the prior art to avoid the electromigration problem, as is discussed, for example, by Hall et al, in US Patent No. 3 743 894. In the fabrication of semiconductor devices, a contact metal layer of aluminum is generally used to make ohmic contact to the device. When the device is operated under high current and high temperature conditions, the aluminum contact metal is transported by the current flowing therethrough causing the metal to build up in some areas and to form voids in others. The voids can become large enough to sufficiently increase the resistance of the metal contact in the area where the voids occur to allow resistive heating to cause the contact metal to melt, thereby causing premature failure of the device. Hall et al teaches that, to avoid the electromigration problem, aluminum contact metallization is codeposited with a small percentage of copper in the order of 1 to 10 percent by weight, forming a fine grain structure of CuAl2 grains having a diameter of less than 1000 A interspersed between aluminum grains at the grain boundaries and tripple points thereof. Silicon has been alloyed with the aluminum-copper in the prior art to prevent the aluminum-copper from penetrating into the silicon substrate as is discussed, for example, by Kuiper in US Patent No. 3 382 568. The use of aluminum/copper alloys and their methods of deposition are also discussed in US Patents No. 3 631 305, No. 3 716 469, No. 3 743 894, No. 3 725 309, No. 3 830 657, No. 3 987 216, No. 4 062 720, No. 4 070 501 and No. 4 184 909, which are illustrative of this art. The addition of copper in aluminum and its deposition by conventional techniques employed heretofore results in metallization highly susceptible to corrosion during semiconductor processing and as well in the formation of large A12Cu intermetallics. The preferential formation of Cu rich regions on the metallization surface accelerates oxide growth and corrosion products during normal processing steps or stages. Local A12Cu cells set up by the differences in the electromotive series between Al and Cu rich regions form galvanic cells which exacerbate the problem. It has been found that conventional aluminum/copper metallization techniques employed heretofore, result in the formation of copper rich intermetallics (Al2Cu) on the film surface which result in high resistance regions which detract from the operability of the de vices as well as reducing yield. The severity of the problem is particularly critical with use of multilevel metallization where it is necessary to interconnect the levels at appropriate points, where a high copper concentration occurs at the interfaces of those multilevel interconnections during normal device processing. Such high copper concentrations result in high ohmic connections, which affect circuit functionality. Also it has been found that with multilevel products, the addition of heat treatments (of normal processing) results in formation of intermetallics which, in time, will traverse the entire metallurgical structure thus causing field failure. Further, the presence of large areas of copper rich intermetallics on the film surface is a significant factor in causing high resistance vias (e.g. the interconnection points of multilevel metallization). A thick oxide layer grows during quartz or SiO2 deposition, which oxide layer is extremely difficult to remove during sputter etch cleaning. The thick oxide results in a high via resistance. Accordingly, it is an object of this invention to provide an improved method for formation of aluminum/ copper metallization on semiconductor devices, in particular to form aluminum/copper multilevel films on semiconductor devices with enhanced yield reliability, and corrosion resistance. Other objects of this invention are to provide a method for making multilevel aluminum/copper conductor patterns with low via resistance at the points of metal level interconnections, to provide a method for controlling the formation of Al2Cu intermetallic during the deposition of the aluminum/copper, and to prevent oxide growth on a first level metallization, prior to a second level metal deposition. It has been discovered that a significant reduction of Al2Cu intermetallic platelet formation can be obtained by controlling the copper concentration in the alloy and by shutting off the substrate heaters during first level metallization deposition. By employing this method the Cu (copper) is preferentially evaporated first, thus keeping the high concentration at the bottom of the film. Shutting the heaters off keeps the Cu from reacting with aluminum which coalesces into large compounds. The absence of Cu at the surface eliminates the surface corrosion. At the beginning of evaporation, because of the initial high temperatures of the substrate and due to the high vapor pressure of copper, a copper rich (about 20 wt. %) aluminum alloy is initially deposited on the substrate. On cooling of the substrate, during the deposition time, the copper concentration of the depositing Al/Cu alloy is continually decreased to a level under 1 wt. % in complete solid solutions at final metal film surface. More specifically, this invention comprehends controlling A12Cu precipitation, in copper doped aluminum, by evaporating the aluminum metallization with 3 to 4 wt % at about 2100C on dielectrics (e.g. quartz, SiO2, silicon nitride, etc) coated semiconductor devices. Therefore the A12Cu precipitates are controlled to stay at the lower portion of the cross section of the first level. To further keep the A12Cu at the lower portion in the first level metallization, the second interlevel metallization evaporation is initiated with the heaters off. Therefore, the Cu in the first metal is prevented from diffusing upwards. In conjuction therewith, multilevel metallization heat treatments, usually employed at 4000C for 75 minutes, can be eliminated. Satisfactory via resistance is attained when measured directly after evaporation. Elimination of heat treatments enhances yields by preventing metal penetration at contacts. By reducing the temperature from 2900C as conventionally employed, to 2100C during aluminum/copper deposition of the first level metal, and shutting off the substrate heater, the Al2Cu intermetallic growth is suppressed. Any A12Cu intermetallics formed are reduced in size and disposed at the dielectric surface, and not exposed at the metal surface. A sintering operation at 4000C for 75 minutes is employed, if needed, after a second level Al/Cu alloy deposition solely to reduce the via interface resistance between the double metal layers, by metal diffusion. However, where no Al Cu intermetallics are exposed at the surface, the sintering step is not needed. Embodiments of the invention are described in the following in connection with the accompanying drawings: Figs. 1A are schematic cross-sectional views and 1B illustrating a device fabricated in accordance with conventional techniques. Figs. 2A are schematic cross-sectional views and 2B illustrating a device fabricated in accordance with this invention. Figs. 3 are line data charts for illustrating and 4 the distinctions of this invention. Figs. 5A are microphotographs of the plan and and 5B cross-sectional views, respeCtively, of the aluminum/copper alloy metallization deposited on a semiconductor device in accordance with conventional techniques. Figs. 6A are microphotographs of the plan and and 6B cross-sectional views of the aluminum/ copper metallization formed in accord ance with this invention. Other objects, features and advantages of the invention, in addition to those noted above, will become more apparent from the following description of one preferred embodiment of the invention. The structure shown in the drawings represents a portion of an integrated circuit chip which may be formed by any of the conventional methods. For purposes of simplicity, the drawings show a semiconductor substrate 1 coated with a dielectric or insulator 2 of quartzs, silicon dioxide, silicon nitride or a composite thereof. The substrate 1 comprises an integrated circuit which contains active and passive components (not shown) as well as means for electrically isolating the components from each other (not shown). The dielectric layer 2 will normally have contact holes (not shown) for contacting the active and passive components. Formed on top of the dielectric layer 2 is patterned film 3 of aluminum/copper alloy having a high resistance to electromigration. The conductive film 3 will comprise a por:¯on o± a firs;t,###1eve#l-#conduct-iv# pattern which is generally interconnected through dietectric film 2 to doped impurity regions within the semiconductor substrate 1. The Al/Cu alloy metallization 3 can also be connected to other such films in said pattern on the same level to form device-to-device and circuitto-circuit interconnections, as is well known in the art. A blanket deposition of the metallization 3, on the substrate, can be achieved through use of standard sputter deposition techniques from an alloy electrode, vapor deposition from an Al/Cu alloy source, or by codeposition of aluminum and copper from individual sources. Subsequently the desired conductive pattern can be delineated by photo and E-beam lithographic techniques, utilizing resist or lift-off technology followed by wet or dry etching (e.g. reactive or sputter etching). A second dielectric film 4 (e.g. quartz, SiO3, Si3N4, SiO2, etc) is blanket deposited over the substrate to serve as an insulator between the first level of metallization 3 shown, and a second level of metallization to be applied later, by sputtering, chemical vapor deposition, or other techniques. This dielectric film 4 is then lithographically patterned to form via holes 5 at points of access to the first level metallization 3, as for example at the points of interconnection to higher levels of metallization. The prior art deposition of the metallization pattern 3 (as shown in Fig. 1A) is characterized by the formation of grains 6 of AlzCu platelets, the control of whose size and distribution is one of the objectives of this invention. Fig. lA illustrates the formation of large Al Cu platelets or grains which extend to and on top of the surface of the metallization pattern 3, as results from conventional techniques which deposit an aluminum/ copper alloy containing 5 wt. % copper at a temperature that reaches more than 3000C during the deposition cycle. Fig. 2A shows the resultant Al2Cu intermetallic 6A distribution obtained in accordance with this invention, by reducing the copper content to 3 to 4 wt. % and depositing with the substrate heaters off. By reducing the substrate temperature from an initial temperature of about 1800C to 2100C (at which temperature the substrate can be conditioned for deposition of a first level metallization) toward ambient temperatures (e.g. letting the substrate thermally float) during the Al/Cu deposition of the first level metallization 3, the Al2Cu intermetallic growth is suppressed. Such reduction in substrate temperatures is obtained by discontinuing the substrate heating at the start of the deposition (evaporation) of the first level metallization. As a result, the Al2Cu intermetallics are near the surface of the dielectric 2 and not exposed at its surface. The combination of temperature reduction during evaporation and decreasing the copper content resulted in a low and consistant via resistance reading as shown in Fig. 3. Figs. 3 and 4 represent via resistance readings taken off via chains. The vertical dimension is in ohms which is taken over several test site runs. The data in Fig. 3 and up to the crossbar in Fig. 4 were taken after the 75 minute sinter step at 4000C. The heat treatment step lowers the via resistance by several orders of magni tude by reducing the oxide layer and is a required process step. A yield loss is often taken at this step. The data in Fig. 4 (right of crossbar) were taken prior to sintering and still have a lower average and sigma level than the corresponding sintered test sites. The data were compiled on vias with the metal films processed with 3-4% Cu, reduced evaporation temperature and no sintering, with the results forming oxide free via interfaces. The actual metallographic structures are shown in Figs. 5A, 5B, 6A and 6B. Fig. 5A (corresponding to Fig. 1A) shows the high density of Al2Cu intermetallics on the surface where a via will be etched in dielectric layer 4. Fig. 5B shows, in cross-section the Al2Cu intermetallics extending from the dielectric layer 2 up to the top surface of the Al/Cu film 3. In contrast, Figs. 6A and 6B (corresponding to Fig. 2A) illustrate the absence of Al2Cu compounds on the surface of the Al/Cu film 3, after changes were made in the evaporation conditions and Cu concentrations, as described above. Figs. 1B and 2B illustrate the fabrication of a second level metallization by blanket deposition of an Al/Cu alloy film over the second dielectric film 4, followed by delineation of the desired pattern 9 by conventional techniques as discussed above, but modified in accordance with this invention. Basically, the metallization processing (evaporation) conditions are reversed. To this end, a second via pattern is formed by conventional lithographic technique in dielectric layer 4, followed by dry etching in an inert atmosphere (e.g. argon) to sputter clean the exposed first level metal lization 3 (in the vias) and the dielectric layer 4. With the substrate at ambient temperatures (e.g. no heating) the evaporation of the aluminum-copper metallization is initiated, while simultaneously initiating heating of the substrate to a temperature in the range of about 1500C to about 2000C over the deposition time of evaporation of the second level metallization 9. This results in metal deposition 9 over the dielectric layer 4 and within the vias on the first level metallization 3. Where a blanket metal coating 9 is employed, it can be delineated into a pattern by conventional lithographic techniques as discussed above for the first layer metallization 3. After formation of the second level Al/Cu pattern 9, the structure, if desired, can be processed in a sintering operation at 4000C for 75 minutes, solely to reduce the via or interconnection resistance, at the interface 10 between the double layers 3 and 9 by metal diffusion. However, when the A12Cu intermetallics are not exposed on the surface of the first level Al/Cu metallization 3, the sintering step is not needed. It may be noted that during the sintering operation it is immaterial if the first level copper (in metal layer 3) diffuses up, since its surface is covered, which prevents copper oxidation and corrosion, by the initial low copper in aluminum alloy film of the second level metal deposition while at low temperature at the start of the evaporation cycle.

Claims: CLAIMS 1. A method of fabricating thin film interconnected metallization (3, 9) on a dielectric coated inte grated circuit substrate (1) having ohmic contact via openings through said dielectric coating (2) to elements of a circuit, comprising: heating said substrate (1) in a vacuum environment to a temperature between about 1800C and about 2100C to condition said substrate for deposition of a first level metallization (3); discontinuing- said heating and coincidently ini tiating evaporation of said first level metalli zation (3) to deposit, during cooling of said sub strate (1), a first aluminum-copper film (3) over said dielectric coating (2) and in said ohmic con tact via openings; forming in said first level metallization (3) a predetermined interconnection pattern to said circuit elements; ; depositing a dielectric layer (4) over said first level metallization (3) and said dielectric coat ing (2); forming a second pattern of via openings (5) in said dielectric layer (4) to expose selected por tions of said first level metallization (3); dry etching to sputter clean said exposed first level metallization (3) and said dielectric layer (4) in an inert atmosphere and at ambient tem peratures; initiating evaporation of a second level aluminum copper film (9) at ambient temperatures over said dielectric layer (4) and in said second vias (5) and coincidentally initiating heating of said sub strate (1) to a temperature of between about 1500C and about 2100C over the deposition time of said second level metallization. 2. The method of claim 1, wherein said substrate (1) is heated to a temperature of about 2100C. 3. The method of claim 1, wherein the aluminium copper film (3, 9) contains about 3 to 4 % copper. 4. The method of claim 1 or 2, wherein the dielectric coating (2) is SiO2. 5. The method of claim 1, wherein said inert atmos phere is argon. 6. The method of any of the preceding claims, further including heating the substrate (1) at about 4000C for about 75 minutes to interdiffuse said first and second metallization levels (3, 9) in said second via holes (5).

Inventors: GAJDA, JOSEPH JOHN
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1983
Main classification: H01L21
IPC codes: B23K1, H01L23, H01L21