THERMAL STABILISATION OF NEGATIVE CONDUCTANCE SEMICONDUCTOR DEVICES

Abstract: A bias network (44) having at least two or more selectable bias levels is used to drive a negative conductance semiconductor device (18) in a pulse mode. When a first bias level is selected (40), the semiconductor device (18) dissipates substantially all of the energy provided to it as heat. When a second bias level is selected (42), the semiconductor device (18) radiates a portion of the energy provided to it as electromagnetic energy (20), generally of microwave frequencies. Appropriate selection of bias levels allows the device to be either thermally conditioned directly or operated as a microwave frequency electromagnetic energy source. The selection of bias levels may be dynamically altered so as to change pulse rate frequency, pulse duration, and the degree of thermal conditioning with respect to each pulse.

Description: Thermal stabilisation of negative conductance semiconductor devices- BACKGROUND OF THE INVENTION The present invention generally relates to semi¬ conductor device thermal compensation schemes, ana, in particular, to means for providing for the direct thermal conditioning of negative conductance semiconductor devices. The operational stability of semiconductor devices is often highly sensitive to changes in the temperature of the device. Fluctuations in device temperature are most often caused by variations in the duty factor and operating waveform of the device, thereby causing changes in the amount of thermal energy that the device dissipates. These fluctuations may also result from changes in the ambient temperature of the device's operating environment. In applications requiring semiconductor devices having high operational stability, an ordinary heat sink alone is usually insufficient. As a practical matter, heat sinks having large caloric absorbtion or dissipation capabilities are typ ' ically massive, bulky, and expensive to construct. Further, a heat sink does not compensate for variations in the ambient temperature of its operating environment. As a passive device, it inherently tends to maintain the semiconductor device at a fixed value above the ambient temperature, thereby failing to stabilize the temperature of the device with respect to the long term average ambient tem¬ perature. This tendency to maintain the device at a temperature fixed relative to the short term average ambient temperature may be very disadvantageous if the ambient temperature drops significantly below the desired or optimum operating temperature, or worse, the minimum operating temperature of the semiconductor device. A general approach to improving the operational stabilitiy of a semiconductor device is to thermally couple it to a separate temperature feedback controlled heating element. Early apparatus utilizing this approach provided internally heated, thermally insulated ovens within which the temperature sensitive semiconductor devices were mounted and operated. The continuously controlled internal environment of the oven could effectively eliminate temperature fluctuations due to variations in the operation of the semiconductor and to changes in the external ambient temperature. The thermal insulation and the internal volume it surrounds, however, causes these oven type devices to be typically large, bulky, and heav in comparison to the semicon¬ ductor device. Further, the oven must continuously consume power in order to maintain the internal temperature controlled operating environment. The internal heating element must heat the interior portion of the thermal insulation and the gas that fills the interior of the oven in addition to the semiconductor device mounted therein. Thus, these oven type devices have a long thermal response time (on the order of several seconds) relative to the period of the operating waveform of the semiconductor device due to the effective mass that must be heated. 1 A second type of apparatus, also consistent with the general approach, utilizes a heating element that is thermally coupled to the semiconductor device by means of a high thermal conductivity substrate. ',he -5 substrate is typically mounted on a passive heat sink. The heating element is used to heat the substrate that, in turn, heats the semiconductor device mounted thereon. A heat sensor, also mounted on the substrate, allows a simple temperature feedback circuit to be 0 used to control the amount of thermal energy being dissipated into the substrate by the heating element. The heating element can thus be used to raise and maintain the temperature of the heat sink at an equilibrium value somewhat above the ambient tempera- 5 ture. This mounting arrangement allows the semiconductor device to be operated always at or above a desired minimum operating temperature. The semiconductor device temperature can thereby be maintained substan¬ tially independent of temperature variations due to 0 its operation, as well as from changes in the substrate equilibrium temperature due to changes in the ambient temperature. While this heated substrate type of apparatus is typically much smaller and lighter in comparison to 5 the oven type apparatus, it still requires the constant dissipation of thermal energy in order to provide for the continuous temperature compensation ot the semicon¬ ductor device. Further, the heating element in the heated substrate apparatus is inherently spaced apart 0 from the semiconductor device and both are typically exposeα to some degree to the ambient operating environment. Consequently, the heat transfer between the heating element and the semiconductor device is inefficient due to the dissipation of heat directly 5 from the substrate to the ambient. This inefficiency is heightened by the fact that the heating " element must continuously heat the much greater mass of the heat sink, in addition to that of the semiconductor device, to a temperature above that of the ambient. Both the oven and heated substrate type of apparatus have been used in a wide variety of appli¬ cations to stabilize the operating temperature of an equally disparate variety of semiconductor devices, including those known for their negative conductance operating characteristics. No distinction is drawn with regard to the type of semiconductor device used other than that it exhibits an operational sensitivity to fluctuations in device temperature. Thus, the abrve described apparatus are capable of providing thermal compensation for semiconductor devices irrespective of their mode, i.e., either continuous wave or pulsed. An example of a heated substrate type apparatus being used to temperature stabilize a negative con¬ ductance semiconductor device is provided by U.S. Patent No. 3,953,878 ("Constant Temperature Control For Transferred Electron Devices") Mawhinney et al. , April 27, 1976. SUMMARY OF THE INVENTION The general purpose of the present invention is to provide for the thermal conditioning of a negative conductance semiconductor device being operated in a pulsed mode. Such operation is utilized to procuce discrete pulses of high-frequency energy. Thermal conditioning is accomplished by directly heating the semiconductor device during the interpulse period so that the desired initial operating temperature of the semiconductor device is achieved immediately 1 prior to each pulse. The direct heating of the negative conductance semiconducor device is achieved through the use ' of a bias network having at least two selectable bias levels to drive the semiconductor device at different 5 . operating levels. When a first bias level is selected, corresponding to a net positive conductance or resistive mode of operation, the semiconductor device internally dissipates substantially all of the energy provided to it as heat. When a second bias level is selected, 10 corresponding to a net negative conductance, the semi¬ conductor device enters its primary mode of operation, which may include radiating a portion of the energy provided to it as electromagnetic energy, generally of microwave frequencies. 15 Thus, the negative conductance semiconductor device can be effectively thermally conditioned by selecting the first bias level during the interpulse period at an appropriate time point so that the device is heated to a desired initial operating temperature at 20 the beginning of each pulse. Since the pulse period of the semiconductor device is fairly short (on the order of several microseconds or less) the temperature profile of the semiconductor device during a pulse is substan¬ tially dependent on its initial operating temperature 25 and independent of the length of the interpulse period and the ambient temperature. An advantage of the present invention is that the direct thermal conditioning and pulse operation of the device are non-overlapping so that optimal bias -30 levels can be independently selected. Further, pulse period noise due to heating is effectively eliminated since there is no separate heater that is active during the pulse period. 35 1 Another advantage of the present invention is that the negative conductance semiconductor device is used to heat itself, thereby requiring neither an additional, external heating element nor the controlled "5 heating of any other intervening structure. A further advantage of the present invention is that the negative conductance semiconductor device is thermally conditioned only for a limited time immediately prior to its operation and, therefore, 10 requires only the minimum amount of energy necessary to raise the semiconductor device to its desired initial operating temperature. Still another advantage of the present invention is that by heating the semiconductor device directly 15 and only during the interpulse periods, the thermal response time of the semiconductor device is short enough for it to be preferentially thermally conditioned for each individual pulse. This preferential conditioning permits either a common or a different initial operating 20 temperature, and therefore a corresponding device performance profile, to be dynamically selected for each pulse. BRIEF DESCRIPTION OF THE DRAWINGS 25 These and other attendant advantages of the present invention will become apparent and readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, -30 in which like reference numerals designate like parts throughout the figures and wherein: 35 Λ>-. IPO FIG. 1 is a schematic block diagram of a typical amplifier system that utilizes a negative conductance semiconductor device; FIGS. 2a and b are graphical representations of the direct current to direct voltage and power to direct current characteristics, respectively, of the IMPATT type of negative conductance semiconductor device; FIGS. 3a and b are graphical representations of the direct current to direct voltage and power to direct voltage characteristics, respectively, of the GUNN type of negative conductance semiconductor device; FIG. 4 is a schematic block diagram of the preferred embodiment of the present invention as used in an amplifier system; FIG. 5a is an idealized circuit schematic of a current bias network having two selectable bias levels; FIG. 5b is an idealized circuit schematic of a voltage bias network having two selectable bias levels; FIG. 6 is a graphical representation of the variation of bias current with respect to time during the operation of the preferred embodiment of the present invention; FIG. 7 is a graphical representation of the variation of the temperature of a negative conductance semiconductor device with respect to time during the operation of the preferred embodiment of the present invention; and FIG. 8 is a graphical representation of linear frequency modulated high-frequency pulses. O PI 1 DETAILED DESCRIPTION OF THE INVENTION In order to develop a basic understanding of the preferred embodiment of the present invention, reference is now made to a standard configuration, high-frequency -5 amplifier system, as shown in FIG. 1. The standard amplifier system 10 utilizes a DC power supply and bias network 12 to provide power via a bias power line 14 to a solid state power oscillator 18. The power supply and bias network 12 and the power oscillator 18 are 10 cosϊu-ionly referenced by a bias g round line 16. The solid state power oscillator 18 maybe either a single negative conductance semiconductor device or a power combiner, consisting of several such devices mounted within a high-frequency resonant chamber, both being 15 thermally coupled to an integral heat sink. An example of such a power combiner is disclosed in U.S. Patent No. 3,931,587, which is assigned to the assignee of the present invention. The high-frequency power generated by the solid state power oscillator 18 is 20 transferred to the second port of a standard three-port circulator 22 by way of a power output line 20, which can be a coaxial, waveguide, or other equivalent structure. The design, construction, and operation of circulators, such as the three-port circulator 22, 25 are generally well known in the art. See, Foundation for Microwave Engineering, R. F. Collin, McGraw-Hill, 1966. A low-power, high-frequency signal generator 24 provides an input signal having a desired waveform and frequency characteristic to the first port of the 30 three-port circulator 22 via the input signal line 26. In the configuration shown in FIG.'l, the circulator 22 operates to transfer the signal generator input signal to the solid state power oscillator 18. As a result of the phenomenon known as injection locked 35 oscillation, the solid state power oscillator 18 is 1 induced to resonate at the same frequency as the signal generator input signal. The resulting resonant power output signal is then transferred through the third port of the circulator 22 to the amplifier power output "5 line 28. In an alternate configuration, either the signal generator 24 can be disabled or the signal generator 24 and circulator 22 can be deleted from the amplifer system 10 and the power output line 20 directly connected to the amplifier power output line 28. This 0 allows the power oscillator 18 to operate as a free running oscillator, the frequency of which is directly related to the temperature of the negative conductance semiconductor device or devices contained therein. As previously stated, the active element of the 5 solid state power oscillator 18 is typically a negative conductance semiconductor device. The various semi¬ conductor devices known to exhibit negative conductance are generally well known in the art and include IMPATT and GUNN diodes. See, Solid State Electronic Devices, 0 B. G. Street an, Prentice-Hall, Inc., 1972 and Microwave Semiconductor Devices and Their Circuit Applications, ed. by H. A. Watson, McGraw-Hill, 1969. Negative conductance semiconductor devices as a class, can be viewed as having at least two conductance regions separated by a 5 relatively distinct threshold point. Naturally, the distinct location and nature of the threshold point is somewhat dependent on the electrical resonator circuit associated with the device. A first region can be distinguished in the operation of the device by the 0 exhibition of net positive conductance. That is, useful power supplied to the device is consumed and "waste" thermal energy is dissipated. 5 ^ 1 A second bias region in the operation of the device can be distinguished by the exhibition of net negative conductance. The net negative conductance condition is evidenced by high-frequency oscillation "5 in the operation of the device about a bias point. The exact cause and nature of the oscillatory operation of negative conductance semiconductor devices varies significantly, if not completely, between the different specific types of devices. The physics of the particular 10 mechanism giving rise to the oscillation, however, is not critical in the present invention. It is simply sufficient that the device exhibits an oscillatory operation when operated at a DC bias point within its net negative conductance bias region. 15 Common examples of negative conductance semi¬ conductor devices are the IMPATT and GUNN diodes. The graphs shown in FIGS. 2 and 3 describe the typical operating characteristics of these two devices, respectively. Referring now to FIG. 2a, the static 20 I-V curve of an IMPATT diode is shown. In order to operate the diode, it is driven in a reverse bias condition by a current source. So long as the current driven through the IMPATT diode is less than a threshold current I h' corresponding to the threshold point T 25 on the curve, it exhibits net positive conductance. Once the bias current exceeds the threshold current _th' the device begins to exhibit net negative con¬ ductance resulting in a high-frequency (RF) oscillation in the AC voltage potential across the device. Briefly, -30 this is the result of the current density through the device exceeding the value necessary to start avalanche breakdown. Combined with a voltage/current phase delay inherent in the structure of the device, high frequency oscillation results. Referring now to FIG. 2b, the 35 current bias level can be advanced to an operating OMPI * ! WIPO bias current level, operating point O, corresponding to a desired oscillator output power PRFop * This operating point 0 is typically selected somewhat below the maximum oscillator output power PR f max' corre- sponding to the operating point M, so as to optimize the operating efficiency of the device and to provide an operating margin against unnecessary device burnout. Thus, the typical IMPATT diode possesses the two separate net conductance regions, separated by a thres- hold point T, that are characteristic of negative conductance semiconductor devices. The static VI curve characteristic of a typical ' GUNN diode is shown in FIG. 3a. In operation, a voltage potential is applied across the diode (actually a bulk semiconductor crystal typically consisting of GaAs) by a bias voltage source. Until the bias voltage potential reaches a first threshold voltage potential V^ l r the diode exhibits a simple, rather linear net positive conductance operation. However, as the bias voltage potential is increased somewhat beyond the first thres¬ hold voltage potential Vthl * and until the bias voltage potential slightly exceeds a second threshold volr.age potential V tn 2, a high-frequency oscillation appears in the current conduction through the device, characteristic of a net negative conductance region. Briefly, this is caused by sudden changes in the mobility of electrons being transferred between conduction bands of different potential energies within the bulk crystal. Biasing the device between the two thresholds, corresponding to the voltage potentials of the two conduction bands, results in high frequency oscillatory operation. Once the bias voltage potential exceeds the second threshold voltage potential V^- 2' tne device again begins to exhibit a simple, non-oscillatory, net positive conductance operation. Thus, a desired 1 operating bias voltage potential V 0p , indicated as operating point O, can be selected between the two voltage thresholds so as to provide the desired oscillation power output PRF O ' 2S shown in FIG. 3b. "5 The present invention takes advantage of the distinct positive and negative conductance operating regions of negative conductance semiconductor devices to provide for their thermal conditioning prior to operating as microwave frequency power oscillators. 10 Considering now the preferred embodiment of the present invention as shown in FIG. 4, a thermally conditioned microwave power oscillator 18, 48 forms the central component in a microwave amplifier system 30. Similar ~ to the typical amplifier system 10, shown in FIG. 1, 15 the amplifier system 30 of the present invention is comprised of the solid state power oscillator 18, the low-power, high-frequency signal generator 24, and the three-port circulator 22. Naturally as an alternative, the signal generator 24 can be effectively removed from 20 the amplifier system 30 so that the power oscillator 18 is allowed to operate in the free-running mode. The power supply and bias network 44 differs from its counterpart in the typical amplifier system 10 in that the bias network contained therein can be externally 25 selected to provide a number of different bias levels. The amplifier system 30 is further comprised of a heat sensor 48, a computer 32 and an associated temperature/time look-up table 34. The heat sensor 48 is thermally coupled to the solid state power oscil- -30 lator 18 in as close thermal proximity as possible to the negative conductance semiconductor devices mounted therein. This allows the heat sensor 48 to detect the temperature of the negative conductance semiconductor devices with the greatest possible accuracy. An analog 35 OMPI >* ∞ signal indicative of the temperature of the ' negative conductance semiconductor devices is generated by the heat sensor 48 and transferred to the computer 32 by way of the heat sensor line 50. The computer 32 may be a conventional crystal controlled single-chip microcomputer, such as the INTEL 18022, as described in the Intel Components Data Catalogue, published in 1981 by Intel Corporation, Santa Clara, California, or a controller logic circuit of custom or semi-custom design capable of providing a generally equivalent logic function. As indicated above, the computer 32 receives, as an input, the temperature indicative analog signal generated by the heat sensor 48. Thus, the computer 32 preferably includes an anlog-to-digital converter for developing a digital signal representative of the present temperature of the negative conductance semiconductor devices. Also as inputs, the computer 32 receives digital signals on the pulse duration select input line 52 and the pulse rate frequency (PRF) select input line 54. PRF is here defined as the effective frequency of a continuous pulse train. These signals may be provided from external circuitry including, but not limited to, another computer or a simple electro- mechanical selector switch. Alternately, one or both of these signals may be stored as a fixed or predictably varying value within the computer 32. Preferably, the computer 32 is provided with a stable timing or counting circuit. This is necessary to enable the computer 32 to accurately time both the pulse period, based on the value of the pulse duration selec -signal, and the interpulse period, based on the combined values of the pulse duration and the PRF select signals. In performing this timing function, the computer should develop, at least during the interpulse period, a digital signal representative of the time remaining until the beginning of the next pulse in the pulse train. Finally, the computer 32 interacts with the look- up table 34 over the table bus 36. The computer presents ' the table 34 with the digital signals representing the time remaining until the next pulse and the present " temperature of the negative conductance semiconductor devices. In turn, the table 34 provides the computer 32 with a digital signal representing a projected time point, relative to the end of the interpulse period, when the thermal conditioning of the negative conductance semiconductor devices should begin. The simplest and most direct implementation of the look-up table 34 is as a preprogrammed read only memory, such as an Intel 12708 UVEPROM (ultraviolet erasable program¬ mable read only memory) , as described in the Intel Components Data Catalogue, supra. The computer 32 may form a table data select address by simply providing the time remaining and present temperature digital signals simultaneously and in parallel on the address lines of the table buss 36. This effective address may then be used to access the look-up table 34 and retrieve the corresponding projected time point digital signal as stored in the addressed location. As outputs, the computer 32 provides a heating bias level select signal on the heat bias select . line 40 and an operating bias level select signal on the operating bias select line 42. These signals are provided to the power supply and bias network 44. The power supply contained therein ^ is of conventional design having the capability of generating sufficient direct current at a corresponding voltage potential for driving the negative conductance semiconductor devices contained in the solid state power oscillator 18. The bias network may be of the design shown in 1 either FIG. 5a or b. For IMPATT diodes, and other current controlled negative conductance semiconductor devices, the bias network 60, shown in FIG. 5a, is appropriate. The biss network 60 receives current " 5 on the current input line 70 from the power supply. This current is provided to two separate current sources 62, 64. The current source levels of these current sources 62, 64 are preset to correspond to a heating current bias level in the positive 0 conductance range and an operating bias level in the negative conductance range, respectively, of the particular negative conductance semiconductor devices used in the solid state power oscillator 18. Considering now the heat bias current source 62, the heating bias 5 level current I n is provided to an electron cally activatable switch 66, such as either a magnetic relay or a soild state relay utilizing a JFET, MOSFET, or bipolar pass transistor. In response to the heat bias select signal on the select line 40, the electrically 0 activatable switch 66 conductively connects the output of the heat bias current source 62 with the bias power line 14, thereby providing the solid state power oscillator 18 with a bias drive current, as indicated by the arrow Ij ; ,. Similarly, the electronically activatable 5 switch 68 can be activated in response to the operating bias select signal on the select line 42 so that the operating bias current I 0p provided by the operating bias current source 64 is provided to the solid state power oscillator 18 on the bias power line 14. 0 For GUNN diodes, and other voltage controlled negative conductance semiconductor•devices, the voltage bias network 80 shown in FIG. 5b can be used. Its operation is strictly analogous to that of the current bias network 60 of FIG. 5a with the exception that the 5 power supply maintains an input voltage potential V^ OMPI 1 on the voltage input supply line 90 and that the current sources 62, 64 are replaced by voltage references 82, 84 having preset heating and operating bias voltage potentials, V^ and V OO , respectively. "5 Considering now the operation of the preferred embodiment of the present invention, wherein the power supply and bias network 44 includes the current bias network 60 of FIG. 5a and the solid state power oscillator 18 includes one or more IMPATT diode negative conductance 10 semiconductor devices, the amplifier system 30 is operated so as to provide a series of high-frequency, high-power pulses. Each of these pulses correspond to the period of time that the Impatt diodes present in the power oscillator 18 are biased in their net negative 15 conductance region. A short segment of this pulse train is shown in FIG. 6. The corresponding temperature profile of the semiconductor devices is shown in FIG. 7. Considering as an example the complete pulse cycle period between t3 and tg, the computer 32 derives the 20 length of the interpulse time period, t3 - t5, as well as the current amount of time remaining until t5 from the pulse duration and PRF select signals. Further, the computer 32 repetitively obtains the present temperature of the Impatt diodes at least during the 25 interpulse period, delayed only by the necessary analog-to-digital conversion time. That time delay, however, is short relative to the pulse cycle period of the pulse train. With the above time and temperature data, the - 30 computer 32 can effectuate the principle aspect of the present invention by providing for-the efficient thermal conditioning of the Impatt diodes. Beginning at t3 the Impatt diodes are initially at some maximum temperature, τ max' that begins to decline exponentially with time 35 toward the ambient temperature, T a , as shown in FIG. 7. After t3, the computer 32 determines the present tem¬ perature of the diodes and the amount of time required to heat the diodes to an initial operating temperature, T 0n « As previously explained, this determination is made by accessing the look-up table 34 with the known time remaining before the beginning of the next pulse period, at t5, and the present temperature of the diodes to obtain the corresponding table value for the projected amount of time needed to heat the diodes to the initial operating temperature, T op . The computer 32 can then use this projected time value to further project a heating pulse start time, at t^ , sometime prior to the pulse period, t5 - tg. The computer 32 may complete this procedure any number of times prior to t_|, each time updating the projected time point t4» Once the time point corresponding to the last updated value calculated for t4 is reached, the computer 32 begins heating the IMPATT diodes by driving them at the heat bias current level 1^. This is accomplished by enabling the electronically activatable switch 66 by providing the heat bias select signal on select line 40. The heat bias current 1^, provided on the bias power line 40, drives the IMPATT diodes in their net positive conductance range. Since this bias level is below the threshold current bias level for net negative conductance, substantially all of the use¬ ful power provided to the solid state power oscillator 18 is directly consumed and dissipated by the diodes as thermal energy. This direct heating of the IMPATT diodes results in an exponential increase in their temperature throughout the period of time between t4 and t5» The exact rate of the exponential increase in temperature is dependent on the instantaneous amount of power being provided to the IMPATT diodes and the efficiency at which the solid state power oscillator 18 and its integral heat sink can dissipate thermal energy. This exponential rate can be easily determined through simple and ordinary experimentation with respect to the particular current level, negative conductance semi- conductance device, and solid state power oscillator 18 and intergral heat sink that are used in any particular transmitter system 30. Knowing the exponential rate of temperature increase, the time period values for heating the diodes from a number of different, relatively lower, temperatures to an initial operating temperature, T op , may also be determined through experimentation or easily calculated. These values can then be stored in the look-up table 34 and, thereby, made readily accessible to the computer 32. Typical experimental values for the heating period duration,_ t4 - t5, as required by a proto-type of the present invention, are provided in the table below. The desired initial operating temperature is a preselected value ana the length of the interpulse period can be calculated from the PRF and duration of the pulse periods. Both the rates of exponential temperature decrease prior to heating and of exponential increase during heating can be determined by evaluating the heating period duration time values relative to one another and their corresponding ambient temperature. Thus, based on these rates, simple calculations can be made to determine the amount of time until heating must begin in order for the device temperature to be raised to the initial operating temperature, T 0 p, at t5, for any amount of time remaining in an interpulse period and for any present temperature value. That is, the amount of time that the device temperature can be allowed to exponentially decrease to a point where the subsequent exponential increase in temperature, αue to heating, would cause the device to achieve the initial operating temperature immediately prior to t $ . O TABLE PRF High Medium Low Ambient • Temp ÷25°C 0 6 25 0 0°°CC 4 2 266 38 -25°C 12 35 56 Typical Heating Period Durations -Heating time values in microseconds -Pulse period is four microseconds At ts, the temperature of the IMPATT diodes is approximately equal to the initial operating temperature T op , as shown in FIG. 7, and the computer 32 discontinues the heating of the diodes by deactivating the electron¬ ically activatable switch 66. Simultaneously, the computer 32 initiates the generation of a high-frequency, high-power pulse by activating the electronically activatable switch 68 by providing the operating bias select signal on the bias select line 42. Accordingly, the IMPATT diooes are immediately biased within their net negative conductance range and high frequency oscillation inherently results. Thus, beginnning at t5, the exponential rate at which the diode temperature 1 rises increases significantly. This is the direct result of a larger amount of power being dissipated by the diodes as thermal energy. However, the percentage of energy being consumed by the diodes and dissipated -5 as "waste" heat actually decreases, since a portion of the energy provided is desirably being radiated as high-frequency electromagnetic energy. Although the temperature of the diodes may change during the pulse period, t5 - tg r the thermal conditioning 0 of the diodes is fully achieved by establishing the diodes at their initial operating temperature, T 0 p, at t5« Due to the short duration of the pulse period relative to the thermal response time of the integral heat sink, of the power oscillator 18, the characteristics 5 of the diode pulse period temperature rise are largely dependent on the initial operating temperature of the diodes. Since it is the relative variation of diode operating characteristics as between separate pulses rather than the absolute variation during any given 0 pulse that is critical in the proper operation of the amplifier system 30, the operating characteristics of the diodes can be effectively stabilized by providing that a common diode initial operating temperature is established immediately prior to each pulse period. 5 This effective stabilization is substantially, if not completely, independent of the length of the interpulse period and the ambient temperature. Thus, each pulse, as shown in FIG. 7, has a substantially identical temperature profile with the result that the operating 0 characteristics of the diodes during each pulse are also identical. This allows the particular operating characteristics of the diodes to be, in relevant part, established by selecting their initial operating temperature. 5 V/I O 1 Inherently, the present invention also includes the capability to make dynamic changes in the amplifier system's 30 output waveform, including the length of the interpulse and pulse duration periods as well as -5 the operating characteristics of the diodes. Provided that the computer 32 is_sufficiently fast, the PRF select and pulse duration select signals can be altered for each pulse cycle. Thus, the amplifier system 30 can be used to generate high-frequency, high-power pulses 0 having dynamically variable durations at dynamically variable intervals. Further, by providing the computer 32 with an initial operating temperature factor select signal, analogously to the provision of the PRF and pulse duration select signals, or simply derived there- 5 from, the computer 32 can modify the projected time value obtained from the look-up table 34 by a dynamically variable factor. This would directly alter the time point at which the interpulse heating is begun and, therefore, the initial operating temperature achieved 0 at the beginning of the pulse period. Consequently, the diode operating characteristics are also dynamically variable. This latter capability is of particular use in the amplifier systems 30 that utilize a free- 5 running solid state power oscillator 18. Since the injection locked oscillation phenomenon is not utilized, the frequency of the oscillator 18 is a partial function (typically inverse) of temperature. This results in a phenomenon known as linear frequency 0 modulation, or chirp, involving a roughly linear variation of frequency over time. See, Radar Handbook, Merrill I. Skolnik, McGraw-Hill, 1970. Chirp is useful for the generation of narrow frequency bands. FIG. 8 illustrates "down" chirp that occurs 5 during the high-frequency pulses due to a corresponding increase in the pulse period diode temperature, such as shown in FIG. 7. Thus, by adjusting the initial operating temperature of the diodes, as made possible by the present invention, the direction and rate of chirp can be either effectively stabilized or dynainically varied. The generation of high-frequency power continues until tg, the end of the desired pulse period, when the operating bias level select signal is removed from the bias select line 42. At this point, the diode temperature has exponentially increased to a maximum operating temperature, jπ ax . As the computer 32 returns the bias current level to zero, the temperature begins exponentially dropping toward that of the ambient and the next pulse cycle begins. It should be clear that the present invention does not require the use of a computer 32 in order to be operative. Instead, the present invention requires only a controller circuit that is capable of providing the heat bias select signal on line 40 and the operating bias level select signal on the bias select line 42 at the appropriate times during the operation of the amplifier system 30 in order to effectuate the present invention. Naturally, this controller circuit may be either analog or digital in design as preferred according to its particular application. Further, it should be understood that the computer 32 and bias network 44 can be appropriately modified to be capable of providing either several heat bias levels or several operating bias levels, or both, to the solid state power oscil- lator 18. This would permit several different interpulse heating rates and high-frequency power generation levels to be selected by the computer 32, all being consistant with the present invention. Thus, a method and system for providing for the noncontinuous, direct thermal conditioning of negative conductance semiconductor devices has been described. The thermal conditioning is highly efficient in that the energy is directly consumed and dissipated as heat by the semiconductor devices, that the consumption of energy is only for that period of time necessary to heat the devices to an initial temperature, and that the heating of the semiconductor devices can be dynamically particularized with respect to each pulse within the continuous pulse train. From the foregoing description, it should be obvious that many modifications and variations of the present invention are possible. It is therefore to be understood that, within the scope of appended claims, the invention may be practiced other than as specifically described. OMPI

Claims: CLAIMS What is Claimed is; 1. A direct semiconductor device thermal conditioning system (30) comprising: a) an energy source; b) a bias network (44) having at least two selectable bias levels, said network being driven from said energy source; and c) a semiconductor device (18) having at least two distinct ranges of operation, said device being driven from said bias network (44) such that when a first bias level is selected, said device operates in a first range wherein substantially all of the energy provided thereto is dissipated as heat within said device, and when a second bias level is selected, said device operates in a second range corresponding to its primary mode of operation, said system thereby providing for the direct thermal conditioning of said device. 2. The system of Claim 1 wherein said semiconductor device (18) is a negative conductance element. 3. The system of Claim 2 wherein said first range of operation includes the positive resistance range of said device and said second range of operation includes the negative conductance range of said device. 4. The system of Claim 3 wherein said device (18) radiates a portion of the energy provided to it from said bias network as electromagnetic energy. 5. The system of Claim 4 wherein said radiated energy is generally within the microwave frequency range of the electromagnetic spectrum. OMPI ~ WIPO 6. The system of Claim 5 wherein: a) said semiconductor device (18) is an IMPATT diode; and b) said bias network (60) is comprised of at least two current sources (62, 64) for selectively biasing said device (18) in its positive and negative conductance ranges. 7. The system of Claim 5 wherein: a) said semiconductor device (18) is a GUNN diode; and b) said bias network (44) is comprised of at least two regulated voltage supplies (82, 84) for selectively biasing said device (18) in its positive and negative conductance ranges.

Inventors: EISENHART ROBERT L, EISENHART, ROBERT, L.
Applicants: HUGHES AIRCRAFT CO, HUGHES AIRCRAFT COMPANY
Application year: 1983
Main classification: H03B9
IPC codes: H03B9, H03F1, H03L1