PROCESS FOR FORMING AN INTEGRATED CIRCUIT CAPACITOR

Abstract: In a process for forming a parallel plate capacitor on a semiconductor substrate, a field oxide region (15B) is provided on the substrate. A first polysilicon layer (17) is delineated to provide a first capacitor plate (20). A dielectric layer (23B, 24B) is provided over the first plate (20) and a second polysilicon layer (25) is delineated to form the second capacitor plate (27). Holes (28) are provided extending through the second plate (27) and the dielectric layer (23B, 24B). The structure is then subjected to a doping operation whereby capacitor plates (20, 27) are doped to a desired conductivity level, doping of the first plate (27) being effected utilizing the holes (28) and lateral diffusion in the polysilicon material of the first plate (20). The process is fully compatible with a two level polysilicon process wherein volatile and non-volatile transistors and polysilicon resistors (18) are formed. The capacitor and nonvolatile transistor are suitable for utilizing in a voltage multiplier circuit providing programming voltages for the non-volatile transistors.

Description: PROCESS FOR FORMING AN INTEGRATED CIRCUIT CAPACITOR Technical Field This invention relates to a process for forming a parallel plate capacitor on a semiconductor substrate, of the kind including the steps of forming a first plate over said substrate, forming a dielectric layer over said first plate, and forming a second plate over said dielectric layer. Capacitors formed by such a process are suit- able for use in voltage multiplier circuits incorporated in integrated circuit structures. Background Art MNOS technology and its silicon gate counter¬ part SNOS (hereafter MNOS includes SNOS and vice versa) technology are now well-established for constructing non-volatile memory integrated circuits. Because of its excellent memory operational characteristics MNOS technology is experiencing increasing application to various types of semiconductor integrated circuit memory 2 arrays such as E PROMs and NVRAMs. One disadvantage of the technology, which has somewhat restricted its application, is the requirement of high (of the order of 25 volts or more) program (i.e. write and erase) voltages necessitating dual polarity (+ and -) external power supplies. The goal of the microelectronics industry is to use a single 5 volt external power supply and gener¬ ate, on-chip, the high erase and write voltages thereby eliminating the need for multiple external power supplies and making the MNOS devices economically more viable. One method of on-chip high-voltage generation is by means of the voltage multiplier technique. One such voltage multiplier scheme is shown in Figs. 1A and IB which represent circuits for generating a high posi- tive voltage and a low negative voltage, respectively. Referring to Fig. 1A, V cc represents the input power supply voltages, typically 5 volts and V5.. ™ , is the voltage output of the positive voltage multiplier. V >> - . C, , C 2 ... C are coupling capacitors and Q, , Q„ ... O are rectifying elements (or diodes). In this voltage multiplier arrangement, the rectifying elements were diode-connected enhancement mode MOS transistors. Referring to Fig. IB, V here represents the ground connection and V' ™ , is the voltage output of the negative voltage multiplier. v Ouτ < V σ" As in Fig. 1A, C',, C' 2 ••• C and Q',, Q' 2 ... Q" repre¬ sent coupling capacitors and diodes, respectively. 0, and 0 2 shown in Fig. 1A and 0 1 ' and 0 2 ' shown in Fig. IB designate two clock pulses, of the type shown in Fig. 2 , having a fixed amplitude and in anti-phase with each other. These pulses are applied to the successive nodes of the diode-chain via the coupling capacitors. The amplitude of these clock pulses is typically about 5 volts. Using the voltage multiplier circuit shown in Fig. 1A, in the publication entitled "On-Chip High- Voltage Generation in MNOS Integrated Circuits Using An Improved Voltage Multiplier Technique" by J. F. Dickson and published in IEEE Journal of Solid State Circuits, Vol. SC-11, No. 3, June 1976, pages 374-378, it was demonstrated that it is possible to generate, on-chip, high-voltages of up to +40 volts to enable operation of MNOS integrated circuits. In this circuit, the coupling capacitors could be implemented as depletion mode transistors using the nitride dielectric available in the MNOS process and the diodes implemented as MOS transistors. A drawback of positive and negative voltage multiplier circuits which use depletion mode transistors as coupling capacitors is that they cannot be conven¬ iently used for generating high positive and low negative voltages at the same (output) node. This ability is essential for an on-chip voltage multiplier since devices on an I.C. chip such as NV RAMs invar¬ iably require that the same node of the voltage multiplier go both positive and negative. In other words, in order to generate the requirement voltages, on-chip, the output nodes and ' ™ of Figs. 1A and IB, respectively, need to be connected and this common node be used for programming the devices on the chip. However, if the outputs ouτ and V ouτ of the voltage multiplier circuits, using depletion mode transistors for capacitors are connected together, voltage multiplication is severly hampered, if not, destroyed, since such an arrangement will turn off many of these depletion mode devices. For example, if the (negative) output V' uτ of Fig. IB is connected to the (positive) output V _ of Fig. 1A then this negative voltage, when applied via the diode Q to the gate of the depletion transistor C , will turn off C . Likewise, when this negative gate voltage of C is applied, via diode Qm—l. to the gate of the transistor Cn—l- , it will turn off C , and so on. Thus, a number of depletion n— mode devices C , C -.... will turn off rendering the positive voltage multiplier non-functional. A similar hampering of the negative voltage multiplier (Fig. IB) operation will occur if (the positive) node _ uτ is connected to (the negative) node V' TT Γ Π' One way of overcoming the above voltage multi¬ plier problem is by not connecting together QUT and V and discharging these output nodes separately. However, this necessitates two separate discharging circuits. Another way of overcoming the above voltage multiplier operation problems when the output nodes of the positive and negative multiplier are connected together, is by eliminating depletion mode devices altogether and using in their place permanent capacitors. Since operation of permanent capacitors is not dependent upon the polarity of the voltage applied across their plates, it is possible to connect together the output nodes of the positive and negative multipliers without affecting the performance of either. However, fabrication of such permanent capaci¬ tors, on-chip, requires additional cumbersome processing steps in the prior art single level silicon or metal MNOS process by virtue of limitations of the MNOS process. The cost of these additional steps may outweigh the benefit of building, on-chip, dual polarity voltage multipliers in these earlier MNOS processes. A process for forming a parallel plate capacitor, of the kind specified, is known from U. S. Patent Specification No. 3,864,817. According to this known method a silicon dioxide layer is formed on a silicon wafer. A polycrystalline silicon layer is formed on the silicon dioxide layer and is heavily doped to form the first capacitor plate. A second oxide layer is formed over the polycrystalline silicon layer and an aluminum layer is provided over the second oxide layer to form the second capacitor plate. The known process has the disadvantage that when the capacitor is implemented in an integrated circuit structure, additional process steps are needed to form the capacitor. Disclosure of the Invention It is an object of the present invention to provide a process of the kind specified suitable for forming integrated circuit capacitors, wherein the aforementioned disadvantage is alleviated. Therefore according to the present invention there is provided a process of the kind specified, characterized by the steps of providing a plurality of holes extending through said second plate and said dielectric layer, and subjecting the substrate to a OMPI doping operation, whereby said holes provide for the supply of dopant material to said first plate. An advantage of a process according to the invention is its suitability for forming permanent capacitors, for use in on-chip dual polarity voltage multiplier construction, using a double level silicon SNOS process for fabricating passive devices and active memory and non-memory devices without additional process or mask steps. A further advantage of a pre- ferred embodiment of the process is the capability of forming parallel high conductivity polysilicon plate capacitors by using a single doping step to simultaneous¬ ly dope both the upper and lower polysilicon plates. Yet another advantage of a preferred embodiment of the process is the capability of forming high capacitance per unit area polysilicon-insulator-polysilicon capacitors simultaneously with silicon gate MOS en¬ hancement mode transistors for use as elements of an on-chip positive and negative voltage multiplier. In brief summary of a preferred embodiment of the invention, there is provided a process, which is compatible with a two layer polysilicon monolithic integrated circuit fabrication and provides, as an integral part thereof, silicon gate enhancement mode transistors and polysilicon-insulator-polysilicon parallel plate capacitors for a dual polarity voltage multiplier. Preferably, after the step of doping the first polysilicon (poly I) layer to a low level of conductivity suitable for high ohmiσ value resistors, the poly I layer is patterned into a resistor, a gate for non-memory enhancement mode transistor (diode) and the lower plate of the capacitor. The capacitor plate thus formed is then isolated by forming isolation oxide around the periphery of the plate in the same isolation step used for isolating the non-memory device gate and the resistor. Then, the capacitor insulator is formed in the same step(s) used for forming the memory device's gate insulator (typically, a thin oxide-nitride dual layer) . Next, the upper plate of the capacitor is formed from the second polysilicon (poly II) layer which is conventionally used for forming therefrom gates for the memory devices, interconnecting lines, etc. Thereafter, both the upper and lower polysilicon capacitor plates are doped simultaneously by using the following process. The upper capacitor plate is patterned, in the same step used for defining this plate, to have therein a plurality of holes of a chosen size and separation. Thereafter, the capacitor insu¬ lator is etched, in the same step(s) used for defining the insulator layer into the capacitor insulator and gate insulator such that holes are formed in the capacitor insulator in correspondence with holes in the overlying poly II plate thus exposing portions of poly I plate in correspondence with holes in the overlying poly II plate and the capacitor insulator. Then, the entire poly II capacitor plate and the portions of the poly I plate exposed as indicated above are doped in the same conventional dopant deposition and diffusion steps used to dope the memory gates. Due to rapid lateral diffusion of dopant into the polysilicon, the dopant introduced into the poly I plate through the holes in the insulator and poly II layers will quickly distribute over the entire poly I plate, thereby doping it uniformly to a desired high conductivity level. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Figs. 1A and IB are schematic diagrams of voltage multiplier circuits. Fig. 1A represents a positive voltage multiplier and Fig. IB represents a negative voltage multiplier. CI .PI VV.. JJrrOO Fig. 2 is a schematic representation of the voltage waveforms (clock pulses) applied to successive nodes of the voltage multiplier. Fig. 3 is a partial sectional view of an integrated circuit chip manufactured by a process according to the present invention showing in integral relationship with a polysilicon gate memory device, a polysilicon resistor and interconnect, a parallel polysilicon plate capacitor and a polysilicon gate non-memory device for use as elements of an on-chip, voltage multiplier. Figs. 3A-3H are flow diagrams illustrating by sequential cross-sectional representation the process steps of the present invention culminating in the struc- ture shown in Fig. 3. Fig. 3G, in particular, is a plan view of a portion of Fig. 3F. Best Mode for Carrying Out the Invention Referring now to the drawings and first to Fig. 3 thereof, there is shown in this Figure a partial sectional view of an integrated circuit chip 50 including a capacitor manufactured by a process according to the present invention. The portion of the chip 50 includes an n-channel silicon gate non-volatile memory transistor T, a polysilicon parallel plate capacitor C, an n-channel non-memory silicon gate transistor Q, a polysilicon resistor R and a polysilicon interconnect L. These various active and passive devices are formed on the upper surface of an n-type silicon substrate 10 that includes p-wells 13 and 14 which are isolated from each other by means of n-type diffusion regions 12. Memory transistor T comprises a conductive + polysilicon gate 26 and highly doped n regions 30 and 31, which, respectively, serve as source and drain regions for the device. A thin silicon dioxide (memory oxide) layer 23A and silicon nitride layer 24A insulate the polysilicon gate 26 from the underlying substrate 13. Transis or T further includes metal contacts 35, 36 and 37, respectively, with source 30, drain 31 and gate 26. The capacitor C is disposed atop a thick field isolation oxide region 15B and comprises a lower poly¬ silicon plate 20 and an upper polysilicon plate 27 having therein a plurality of holes 28. A dual silicon oxide layer 23B (of approximately the same thickness as memory oxide 23A) and nitride layer 24B (of the same thickness as gate insulator 24A) having holes therein in registry with the holes 28 in plate 27 insulate plates 20 and 27 from each other. The capacitor C further includes metal contacts 38 and 39 making electrical contact with plates 27 and 20, respectively. The non-memory transistor Q comprises a con- 4. ductive polysilicon gate 19 and highly doped n source and drain regions 32 and 33, respectively. A relatively thick silicon dioxide (gate oxide) 16A insulates the polysilicon gate 19 from the underlying substrate 14. Transistor Q further includes metal contacts 40, 41 and 42 making electrical contact, respectively, with source 32, drain 33 and gate 19 of this device. The polysilicon resistor R is formed on the field oxide 15C and includes a lightly doped polysilicon strip 18 which is electrically isolated from other devices on the chip by isolation oxide 21A. The thick¬ ness of polysilicon 18 is the same as that of the capa¬ citor plate 20 and has sheet resistance of about 10 megohms per square. Interconnect L located atop the resistor R and insulated therefrom by not only the isolation oxide 21A, but also the oxide 23C and nitride 24C (which is of the same thickness as layers 24A and 24B) , is a polysilicon strip 29 having the same thickness and conductivity as gate 26 of transistor T and plate 27 of capacitor C. Structure 50 further includes a thick oxide layer 34 which electrically isolates the various devices T, C, Q, L, etc. from each other. The capacitor C and the non-memory silicon gate MOS transistor (diode) Q may be connected as indi¬ cated in Figs. 1A and IB for generating, on-chip, high positive and low negative voltages. Reference is now made to Figs. 3A-3H wherein the successive steps of the fabrication process of the present invention is illustrated in detail. While the following description is primarily directed to the fabrication of an integrated circuit chip comprised of an n-channel silicon gate memory transistor T, a parallel polysilicon plate capacitor C, an n-channel silicon gate non-memory enhancement mode transistor Q, a polysilicon resistor R, and polysilicon interconnect L, this description is exemplary of the fabrication of a class of devices which embody princi¬ ples of the present invention. In addition, it should be noted that the thickness and other dimensions shown herein are selected for clarity of illustration and not to be interpreted in a limited sense. Referring now to Fig. 3A, the fabrication process of the present invention is initiated starting from an n-type single crystal silicon substrate 10 upon which a p-type epitaxial layer 11 has been grown. A . deep N diffusion 12 (typically phosphorus) is made to isolate portions 13 and 14 of the epitaxial layer 11. Within each of these isolated portions 13 and 14 (also referred to herein as p-wells) will be located various memory and non-memory devices. For example, in the embodiment under consideration, the silicon gate MNOS memory transistor T will be located in the isolated portion 13 and the silicon gate MOS enhancement mode non-memory transistor Q will be located in the isolated portion 14. Isolation of the MOS diodes from other parts of the circuit in this manner is crucial for generating the negative voltages by the voltage multi¬ plier which will be constructed using these MOS diodes. Over the epitaxial layer 11 as separated by the n diffusion 12 is then formed in a conventional manner thick (5,000-20,000 Angstroms) silicon dioxide field isolation regions 15A, 15B, 15C. The coupling capacitor C will be located atop the field oxide 15B and the resistive element R will be located atop the field oxide region 15C. The succeeding step in the process, which is also illustrated with reference to Fig. 3A, is growth of a relatively thin gate oxide layer 16 of thickness about 800 Angstroms over the wafer. Thereafter, using conven¬ tional photolithography and implantation techniques the surface portion of the isolated region 14 is subjected to an enhancement implant through the gate oxide 16 using, for example, boron ions of energy 40 keV and dose 4.3 x 10 per square cm to obtain the desired (positive) threshold of the enhancement mode transistor Q that will be formed thereover. Next, a first layer 17 of poly¬ silicon (poly I) is deposited over the entire structure to a thickness of about 5,000 Angstroms. A preferred technique for forming poly I layer 17 is by low pressure chemical vapor deposition (LPCVD) using silane at a temperature of about 625 β C and pressure of 100 raillitorr. LPCVD of polysilicon is preferred since this insures uniformity in thickness and reproducibility which are vital in a high volume production situation. Since the integrated circuit under consideration is contemplated to contain resistive elements, the poly I layer 17 is subjected to a light doping for the subsequent formation of of poly I resistor elements. A suitable implantation involves phosphorus ions having an energy of approxi- mately 110 keV and dose about 1.6 x 10 14 per square cm. The resulting sheet resistance of poly I will be about 10 megohms per square. In progressing towards the structure shown in Fig. 3B, the resistively doped poly I layer 17 is pat¬ terned using conventional photolithographic and etching techniques into poly I resistor 18, gate electrode 19 for the enhancement mode transistor Q to be formed in the surface region of isolated portion 14 and the lower plate 20 of the coupling capacitor C to be formed atop the central field isolation oxide 15B. Next, referring further to Fig. 3B, a silicon dioxide layer 21 is formed over the entire structure by thermal oxidation at a temperature of about 900°C, to a thickness in the range 2,000-4,000 Angstroms. The oxide layer 21 will serve to isolate the periphery of the poly I capacitor plate 20 from the upper poly II plate that will be subsequently formed thereover and also to iso¬ late the poly I resistor 18 from the poly II intercon¬ nect L that will be subsequently formed thereover, and as such will be referred to hereinafter as isolation oxide. During this oxidation step, a small percentage of the poly I segments 18, 19 and 20 will be consumed. After forming isolation oxide 21, the next step in the SNOS process, as shown in Fig. 3C, is re¬ moval of the isolation oxide 21 (and the underlying gate oxide 16) in the surface portion of the p-well 13 to form the memory dielectric over said exposed portion of the p-well. The present process takes advantage of this process step by additionally forming a wide window 22 in the isolation oxide to expose a surface portion of the poly I capacitor plate 20 as shown in Fig. 3C. Thereafter, referring to Fig. 3D, a very thin (approximately 20 Angstroms thickness) layer 23 of silicon dioxide and a relatively thick (approximately 250-500 Angstroms thickness) layer 24 of silicon nitride are formed over the entire wafer by using a process wherein the oxide layer 23 is formed by thermal oxida¬ tion of the wafer at a temperature of about 750°C and the nitride 24 is formed immediately thereafter at the sa e temperature by LPCVD using gaseous dichlorosilane and ammonia in the ratio of l:(3-4). This dual layer 23-24 constitutes the gate dielectric for the memory device T and the insulator for the capacitor C. Although the oxide layer 23 is shown in Fig. 3D, for clarity of illustration, to have a uniform thickness over the entire structure, in reality this need not necessarily be the case. For example, if oxide 23 is formed by thermal oxidation as discussed in the previous paragraph, due to a lower oxidation rate of the isolation oxide 21 as compared with the remainder of the structure (i.e. the exposed poly I plate 20 and epitaxial region 13), the oxide layer 23 formed over the isolation oxide 21 will be thinner than that over the remainder of the structure. An alternative to the dual oxide 23-nitride 24 layer memory device T gate dielectric and capacitor C insulator is a dual silicon oxide-silicon oxynitride layer. In this embodiment the oxide 23 may be formed, for example, by thermal oxidation of the wafer and the oxynitride may be formed by LPCVD using reactant gases ammonia, dichlorosilane and nitrous oxide in the proportion, for example, of ammonia:dichlorosilane:- nitrous oxide of about 3.5:1:2. Yet another alternative to the dual dielectric layer 23-24 is a multiple layer of silicon oxide-silicon oxynitride-silicon nitride. Regardless of what dielectric (i.e. oxide- nitride dual layer or oxide-oxynitride dual layer or oxide-oxynitride-nitride multiple layer) is selected for the memory device T gate dielectric, the SNOS process step(s) of forming this gate dielectric is advantageous¬ ly made use of in the present process to form also the capacitor C insulator without any additional mask or process steps. On the other hand, if it is desired to form a capacitor C having an insulator layer different from the OMPI memory device T gate dielectric, the present process may be modified to accommodate the same. For example, in¬ stead of the dual oxide 23-nitride 24 layer a single nitride may be formed over the exposed portion of the capacitor plate 20. It is noted that a capacitor having a nitride insulator, for a given insulator thickness, will have a higher capacitance per unit area (C/A) than a capacitor having an oxide-nitride dual layer since C/A is proportional to the dielectric constant of the ca- pacitor insulator and the dielectric constant of the nitride insulator is larger than that of the dual oxide- nitride insulator. The next step in the present process is depo¬ sition of the second polysilicon layer 25 (poly II) over the entire wafer as shown in Fig. 3D. Poly II layer 25 is deposited in the same manner as poly I discussed hereinabove in connection with Fig. 3A. In progressing toward the structure shown in Fig. 3E, the poly II layer 25 is patterned, by conven- tional photolithographic and planar plasma etching techniques, into the gate 26 for the memory device T, the upper plate 27 having therein a plurality of holes 28 for the coupling capacitor C and poly II interconnect 29. The holes 28 in the polysilicon plate 27 will be used for introducing dopant into the underlying poly I plate 20 at a later doping step. Although the poly I plate 20 was initially doped to a low conductivity level suitable for resistors, further doping to a high con¬ ductivity level is essential to avoid the distributive effect of capacitance and resistance in the poly II plate 27-nitride 24-oxide 23-poly I plate 20 structure which gives rise to poor frequency response of the voltage multiplier that will be constructed using this structure as an element. Referring to Fig. 3F, after patterning the polysilicon II layer 25 in the above manner, the etching step is continued to remove the nitride layer 24 everywhere except those regions of the substrate struc¬ ture which are masked by the poly II layer segments 26, 27 and 29. Note, during this nitride etching step, the portions of the nitride layer in correspondence with holes 28 are also etched away. The wafer is then subjected to an oxide etch step using buffered hydrogen fluoride (HF) to remove the exposed portions of the memory oxide 23, isolation oxide layer 21 and the gate oxide 16. Since polycrystalline and monocrystalline silicon are not materially attacked by HF, the exposed polysilicon I and polysilicon II layer segments serve as etchant masks and etchant stops. At the conclusion of the oxide etch step, the wafer structure looks as shown in Fig. 3F where 23A and 24A, respectively, denote the oxide and nitride gate die¬ lectric layers of the memory device T, 23B and 24B are, respectively, the oxide and nitride insulator layers of the capacitor C and 16A is the gate dielectric of the non-memory device Q. Referring now to Fig. 3G, which is a top plan view of the capacitor C, the plate 27 is shown for illustrative purposes, as having twenty four square holes 28. The actual number of holes 28 is determined by the dimension d of holes 28, their relative separa- tion s and the area A of the capacitor plate. The dimension d and separation s are selected to provide doping of the entire poly I plate 20 by lateral dif¬ fusion of the dopant from the dopant-bearing material that will be introduced into plate 20, via holes 28, in the next process step. The extent of dopant lateral diffusion is, in turn, governed by the particular species of dopant selected, the temperature at which diffusion is accomplished and the time of diffusion. For example, if d = 3 microns, the dopant species is phosphorus, the diffusion temperature is 900°C and the diffusion time is approximately 2 hours, the separation s between holes 28 should be 4.25 microns in order to CI- .PI V ΣFO obtain the necessary lateral dopant diffusion in the polysilicon plate 20 to render it highly and uniformly conductive. Because of holes 28, there will be some loss in the capacitor C area. This loss of area, also re¬ ferred to in terms of the area utilization factor U is given by U = (s 2 + 2sd)/(s + d) 2 . In the example discussed above, the loss of capacitor area due to holes 28 is about 17% or U = 0.83. However, the loss in capacitance due to area loss is more then compensated for by using a high dielectric constant capacitor insulator (nitride or oxide-nitride etc.) and by choosing a thin layer of this insulator. Thereafter, the wafer is subjected to a doping step to form sources and drains for the various trans¬ istors and to obtain low sheet resistance polysilicon gates, polysilicon capacitor plates, and polysilicon interconnect. One way of accomplishing this doping is by depositing a layer (not shown) of a phosphorus-bearing substance such as P0C1_ at a temperature of about 900°C over the entire wafer including the surface areas of the poly I capacitor plate 20 which are in correspondence with the holes 28 formed through the overlying thin oxide 23B, nitride 24B and poly II plate 27. Then, the phosphorus dopant from the deposited POC1- layer is thermally diffused by subjecting the wafer for a period of time at a temperature of about 900-1000°C. During this diffusion step, as shown in Fig. 3H, not only the sources and drains 30, 31 of the memory device T and 32 and 33 of the non-memory device Q are formed, but also the poly II gate 26 of the memory device T, the poly I gate 19 of device Q, the poly II interconnect 29 (also designated as L), and both the upper and lower poly II plates 27 and 20 of the capacitor C are doped to a high, O_v.PI uniform conductivity level (corresponding to a sheet resistance of, typically, about 30-50 ohms per square) . The entire lower poly I capacitor plate 20 is uniformly doped due to the rapid lateral diffusion of phosphorus 5 dopant that was introduced into the plate 20 via the holes 28 during the previous phosphorus deposition step. Thus, in this process, high capacitance per unit area capacitors C are formed along with non-memory enhancement mode MOS transistor Q, memory devices T, 10 poly II interconnect L and poly I resistor R without use of additional masking or process steps than those em¬ ployed in conventional SNOS process. The capacitance of the capacitor C formed in • . the manner exemplified above is dictated to a certain 15 extent by the thickness and type (i.e. dielectric con¬ stant) of memory gate dielectric selected for the device T, the area available on the chip for forming the capa¬ citor plates, the loss of area of the poly II capacitor plate 27 due to holes 28 therein (which is called the 20 area utilization factor) etc. When a dual oxide-nitride gate dielectric is used, the capacitance of the capaci¬ tor formed in the present process is given by: w ,here £. n is the dielectric constant of silicon nitride 25 24B, £ ,. -Λ- is the dielectric constant of silicon oxide 23B, tIx is the nitride 24B thickness, tox is the oxide 23B thickness, A is the common area of capacitor plates 20 and 27 and U is the area utilization factor. Typically, in a conventional low power, n- 30 channel double silicon gate 32K density E 2PROM fabri¬ cation p ■ ^rocess, tox = 20 Angstroms, £ox * = 3.8, tn = 380 Angstroms, e. = 5.6. A poly I-oxide-nitride-poly II capacitor formed in this process and having a capacitor plate area A = 75 x 75 square microns and having 3 micron square holes with a relative separation s of 4.25 microns, giving rise to a utilization factor U = 0.83, will have a capacitance of 5.65 x 10 —12 farads or a capacitance per unit area of 1 x 10 -7 farads per square cm. Using the above high capacitance per unit area capacitors C and transistors (diodes) Q (Fig. 3G) as elements of the circuits shown in Figs. 1A and IB, it is possible to construct voltage multipliers which can generate both positive and negative voltages in the range of + (15-25) volts and having a current capability in the range of 0-100 microamps. Such a voltage multi- plier will be suitable for programming E 2PROMs and other devices. After the doping step discussed hereinabove with reference to Fig. 3H, the normal IC fabrication process is then resumed to complete the fabrication of the monolithic chip. Referring to Fig. 3H, these steps include forming a thick (about 10,000 Angstroms thick- ness) isolation oxide 34 over the entire structure to dielectrically isolate each device, forming contact vias in the layer 34 and then forming metallization to pro¬ vide ohmic contact to the various elements of devices T, C and Q, etc. The resulting final structure is as shown in Fig. 3 where 35, 36 and 37 denote the metal contacts for the source 30, drain 31 and polysilicon gate 26, respectively, of device T; 38 and 39 are the metal contacts for the upper and lower polysilicon capacitor plates 27 and 20, respectively; and 40, 41 and 42 are the metal contacts for the source 32, drain 33 and polysilicon gate 19, respectively, of the device Q. Although this process has been described in connection with a double-level polysilicon structure wherein the poly I is initially doped to a relatively low level, suitable for the specific purpose of forming therefrom polysilicon resistors, and the capacitor poly I lower plate 20, poly I gate 19 etc. are doped to a higher level subsequently, this process will be con¬ ducive for incorporation in any process where the plate 20 is not initially doped to the desired level. The above described process may also be prac- ticed by substituting in place of poly II layer 25 (Fig. 3D) other suitable materials such as a metal, polycide or a refractory metal suicide, e.g. tungsten suicide, tantalum suicide or molybdenum suicide. In this case since layer 25 is inherently highly conductive, it will not receive additional doping during the doping step discussed above in connection with Fig. 3H, but the poly I plate 20 and poly I gate 19 will be doped along with the forming of the various sources and drains. C FI /Λ WIi '°

Claims: CLAIMS : 1. A process for forming a parallel conduc¬ tive plate capacitor on a semiconductor substrate (10), including the steps of forming a first plate (20) over said substrate (10), forming a dielectric layer (23B, 24B) over said first plate (20), and forming a second plate (27) over said dielectric layer (23B, 24B), characterized by the steps of providing a plurality of holes (28) extending through said second plate (27) and said dielectric layer (23B, 24B) , and subjecting the substrate to a doping operation, whereby said holes (28) provide for the supply of dopant material to said first plate (20). 2. A process according to claim 1, charac¬ terized in that said doping operation is effected by thermal diffusion. 3. A process according to claim 2, charac¬ terized in that said first plate (20) consists of polycrystalline 1 silicon, and in that said doping operation is effective to dope the entire first plate (20) such that a desired uniform conductivity level is achieved in said first plate (20) by lateral diffusion. 4. A process according to claim 3, charac¬ terized in that said second plate (27) consists of polycrystalline silicon and said doping operation is effective to dope said second plate. (27) to a desired level. 5. A process according to claim 3, charac¬ terized in that said second plate (27) consists of a metal, a refractory metal suicide, or polycide. 6. A process according to claim 1, charac¬ terized in that said dielectric layer includes or consists of silicon nitride (24B). 7. A process of forming an integrated circuit in a semiconductor substrate (10) of a first conductivity type, including a parallel plate capacitor formed according to claim 4 and a field effect transistor (Q), characterized by the steps of: forming a field oxide region (15B) and an active region (14) of a second con¬ ductivity type in said semiconductor substrate (10); forming a gate oxide layer (16) over said active region (14); forming a first polysilicon layer (17) over said gate oxide layer (16); patterning said first polysilicon layer (17) into a transistor gate electrode (19) over said active region (14) and said first plate (20) over said field oxide region (15B); forming an isolation oxide layer (21) over a portion of the first capacitor plate (20); forming said dielectric layer (23, 24) over the structure; forming a second polysilicon layer (25) over said dielectric layer (23, 24); patterning said second polysilicon layer (25) into said second capacitor plate (27) having a plurality of holes therein; patterning said dielectric layer (23, 24) into the capacitor insulator (23B, 24B) having a plurality of holes in correspondence with the holes in said second capacitor plate (27); removing said isolation oxide layer (21) to expose said gate electrode (19) and said active region (14); and providing active impurities of said first conductivity type to dope said first and second capacitor plates (20, 27) and said gate electrode (19) and form a source (32) and a drain (33) in self- aligned relationship with said gate electrode (19). 8. A process according to claim 7, charac¬ terized by the steps of additionally patterning said first polysilicon layer (17) into a resistive 8. (concluded) I element (R), lightly doping said first polysilicon layer (17) and protecting said resistive element (R) during said step of providing active impurities. 9. A process according to claim 8, charac¬ terized by the step of additionally patterning said second polysilicon layer (25) into a gate electrode (26) for a non-volatile memory device (T) having a gate dielectric formed by a portion (23A, 24A) of said dielectric layer (23, 24). 10. A process according to claim 7, charac¬ terized in that said parallel plate capacitor and said field effect transistor (Q) form part of a voltage multiplier circuit. 11. A process according to claim 1, charac¬ terized in that said holes are about 3 microns square in size, the relative separation of said holes is about 4.25 microns, said doping operation utilizes phosphorus, o the diffusion temperature is about 900 C and the diffusion time is about 2 hours.

Inventors: TOPICH JAMES ANTHONY, TOPICH, JAMES, ANTHONY
Applicants: NCR CO, NCR CORPORATION
Application year: 1983
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29, H02M3