SEMICONDUCTOR DEVICE WITH POWER LINES

Abstract: A semiconductor device includes a power line (13) and sub power line (16) pair therein, both lines connected to the same power source. The power line is located on a layer un­ der which a peripheral circuit region, such as input/output buffer circuits and output buffer circuits, is arranged in a semiconductor substrate. The sub power line is located above and electrically shorted with the power line. The electric shorts are formed, at least, at portions under which the output buffer circuits are located and connected to the power line.

Description: SEMICONDUCTOR DEVICE The present invention relates to a semiconductor device, more particularly to power lines distributed on a semiconductor device. Recent large scale integrated circuits (LSI's) have featured larger scales and larger numbers of pins than ever before. The larger scale of LSI's has necessarily increased the length of each power line and, accordingly, made the resistance of the power line a factor for consideration. The increased number of pins has considerably increased the number of input/output pins. The increased number of input/output pins in turn necessarily enlarges the scale of the peripheral circuit region, such as the input/output buffer circuits. The enlarged output buffer circuits may often cause generation of an instantaneous large current. Such an instantaneous large current may flow in the power line, when the output logics of a plurality of output buffer circuits to be connected to external bus lines change from "H" (high) to "L" (low), and vice versa, all at once. The product of the instantaneous large current and the resistance of the power line causes a voltage drop. This results in a deviation in level of a V55 power line, which usually provides, as a ground level, a reference voltage for the whole integrated circuit. Also, in a transistor transistor logic (TTL) circuit driven by a power source of, for example, 5 V, since the threshold levels for discriminating the logics "H" and "L" are ususally 2.4 V and 0.4 V, respectively, although a large margin of (5 - 2.4) V for the output is obtained at the power source level side (i.e., VDD power line side), the margin for the output is as small as (0.4 - O) V at the wound level side (i.e., V55 power line side). Under such conditions, such a voltage drop in the Vss power line may drastically reduce the noise margin, including the margin for each input level at logic "H" side. Similarly, such a voltage drop in the VDD power line may reduce the noise margin, including the margin for each input level at the logic "L* side. This can lead to malfunctions in the SI circuit, Thus, in an L5I circuit, the voltage drop in the power lines, i.e., VDD power line and V55 power line, must be made as small as possible. Above all, repression of a voltage drop in the VSS power line is strongly demanded. In the prior art, two main methods have been proposed for reducing the voltage drop in the power lines. The first is to increase the width of the power lines to lower the resistance of the line. Wide power lines, however, impede high integration of LSI's. Accordingly, a multilayer structure is usually employed in such an LSI circuit. That is, when one of the power ¯lines, for example, the V55 power line, is distributed on a first layer, the other one, e.g., the VDD power line, is distributed on another layer, such as a second layer located thereabove. The second is to intentionally produce a certain delay time in the plurality of outputs from the output pins every time an instantaneous large current is anticipated. Here, the delay time is as short as possible to maintain normal operation of the LSI circuit. In other words, this method, takes an instantaneous large current composed of currents occurring at the same timing and distributes it over time to suppress the overall amplitude of the current to a low level. This method, however, is not suitable for an LSI circuit because it entails the additional provision of a circuit for creating the delay time. Thus, the first method is preferable to the second. However, the first method itself is not sufficient for future LSI circuits with higher degrees of integration and larger numbers of pins than present LSI circuits. It is desirable to provide a semiconductor device with power lines which sufficient for future LSI circuits with higher degrees of integration and large, numbers of pins. In an embodiment of the invention, there is formed a sub-power line in addition to a corresponding original power line, preferably the Vss power line. Thus, the same kind of power lines are arranged as a multilayer structure. This makes it possible to halve the inherent resistance of the original power line. In this case, the original and sub-power lines are electrically shorted at portions to which at least the output buffer circuits are connected. Each output buffer circuit is capable of producing a large current. Reference will now be made, by way of example, to the accompanying drawings, wherein: Fig. 1A is a partial cross-sectional view of a first example of a semiconductor device with power lines distributed thereon, embodying the present invention; Fig. 1B is a partial cross-sectional view of a second example of a formation of power lines, embodying the present invention; Fig. 2 is a plan view of a semiconductor device, taken along its first layer, taking as an example a case where the device has a cross-section of Fig. lAi Fig. 3 illustrates the arrangement of the second layer, in which a sub VSS power line 16 of the present invention is distributed in addition to the original VDD power line 15; Fig 4A is an equivalent circuit diagram of circuit lines, and Vss power source in a case where there are no electric shorts in Fig. 3; ; Fig. 4B is an equivalent circuit diagram of the circuit lines, and Vss power source in a case where there are electric shorts in Fig. 3; Fig. 5 is a circuit diagram of one example of a prior art input buffer circuit shown in Fig. 3; Fig. 6 depicts waveforms for explaining the operation of the circuit shown in Fig. 5; and Fig. 7 is a graph showing the relationship between the input voltage level and the number of buffer circuits. As was previously mentioned, in a transistor transistor logic (TTL) circuit driven by a power source of, for example, 5 V, since the threshold levels for discriminating the logics "H" and L" are usually 2.4 V and 0.4 V, respectively, although a large margin of (5 - 2.4) V for the output is obtained at the power source level side (i.e., VDD power line side), the margin for the output is as small as (0.4 - O) V at the gound level side (i.e., V58 power line side). Under such conditions, such a voltage drop in the Vss power line may drastically reduce the noise margin, including the margin for each input level at the logic "H" side. Similarly, such a voltage drop in the VDD power line may reduce the noise margin, including the margin for each input level at the logic "L" side. This can lead to malfunctions in the LSI circuit. To be specific, the larger the number (N) of the output and input/output buffer circuits which are driven similtaneously, the lower should the input voltage level VIL of logic "LN be, and the higher should the input voltage level VIH of logic "H" be. This will be clarified with reference to Fig. 7, in which the abscissa indicates the number N of the output and input/output buffer circuits which are driven similtaneously and the ordinate indicates an input voltage level VI supplied externally to the pins of the LSI circuit. In this graph, the hatchings represent areas where a normal operation can be guaranteed. Especially, the lines VIHmin and Vltmax represent the limits of levels for a minimum input logic level of aH" and a maximum input logic level of "L". This graph shows that, along with an increase of the number N, the areas with hatchings become narrow. This means that, as was mentioned above, the larger the number (N) of the output and input/output buffer circuits which are driven simultaneously, the lower should the input voltage level VIL of logic "L" be and the higher should the input voltage level VIH of logic "H" be. Figure 1A is a partial cross-sectional view of a' first example of a semiconductor device with power lines distributed thereon, eabodying the present invention. In this figure, reference numeral 11 represents a semiconductor substrate forming a base of a semiconductor chip, and 12 represents a usual insulation film mounted on the substrate 11. On the surface of the insulation film 12, i.e., on a first layer, a V55 power line 13 is mounted. On a second layer located thereabove via a phosphosilicate glass (P5G) layer 14, a VDD power line 15 is mounted. The formation of the above layers 13 and 15 is not new, however, attention should be paid to the newly employed sub V55 power line 16 in accordance with the present invention. In this first example, the sub V55 power line 16 is mounted right above the V55 power line 13 and on the second layer on which the VDD power line 15 is also mounted. ;anerallyZ the power lines 13 and 15 are shifted in location with each other so as to prevent an electric short therebetween. Thus, the resistance of the Vss power line is substantially halved. Figure 1B is a partial cross-sectional view of a second example of the formation of power lines, being embodimentS of the present invention. The difference in arrangement from Fig. 1A is that, first, a sub V35 power line 18 is mounted on not the second layer but a third layer via a PSG layer 17. Second, a VDD power line 15' and a Vss power line 13' are mounted on the first and second layers, respectively. It is preferable to separate the different power lines, such as IS and iS', as much as possible, so as to avoid damage due to unitentional shorts therebetween. The same power lines, such as 18 and 13', can be positioned close to each other. An advantage of this second example is that the sub Vss power line 18 can be wiper than the sub Vss power line 16 of the first example. The above explanations were made with reference to partial cross sectional views. The present invention will now further be explained in detail with reference to a plan view. Figure 2 is a plan view of a semiconductor device, taken along its first layer, taking as an example the case where the device has the cross -section of Fig. IA. Figure 3 is a plan view of a semiconductor device, taken along its second layer, also taking as an example the case where the device has the cross-section of Fig. 1A. Since the second layer is superposed on the first layer, the plan views of these two layers are separated into Figs. 2 and 3 so that the first layer may also be seen. In Fig. 2, logic circuits (LOGIC) 21 are arranged in the semiconductor substrate 11 at its center (enclosed by chain-dotted lines in this figure). Peripheral circuit region 22 (corresponding to the previously mentioned input/output buffer circuits, referenced in this figure as the symbols I/O, O, or I), is arranged in the substrate at its periphery so as to enclose the logic circuit region 21. Only some of the circuits I/O (input/output), O (out), and I (input) are illustrated for simplicity. Here, the V53 power line 13 is dis tribute on and along the peripheral circuit region 22, i.e., the periphery of the semiconductor substrate 11. In this figure, the power line is distributed as a closed loop, but it is not limited to this and may be, for example, a closed loop. The Vss power line 13 supplies the power to not only the peripheral circuit region 22, but also to the logic circuit region 21 via branched power lines 23. The power of Vss is externally supplied to the substrate 11 from a pad 24. Figure 3 illustrates the arrangement of the second layer, in which a sub Vss power line 16 of the present invention is distributed in addition to the original VDD power line 15. These power lines 15 and 16 are distributed on and along the peripheral circuit region 22, i.e., the periphery of the semiconductor substrate 11. In this figure, the power lines 15 and 16 are distributed may be, for example, closed loops, but are not limited to this and, an opened loop. Further, the sub V35 power line 16 is placed almost parallel with the Vss line 13 shown in Fig. 2. Incidentally, a pad 31 is formed as one body with the pad 24 of Fig. 2, and a pad 32 is used for a connection with an external VDD power source via, for example a bonding wire (not shown). Thus, both VSS power lines 13 and 16 are constructed as a multilayer structure in the area where the peripheral circuit region 22 is positioned. This is because, first the Vss power line 13 is inherently formed in the related area (22) and, second, the reduction of the resistance of the Vss power line is required only for the related area of the peripheral circuit region 22 among all the output buffer circuits (I/O, 0) thereof. Thus, to reduce the resistance, it is not sufficient to mer- S place the sub Vss power line 16 in parallel with the original VSS power line 13. It is further necessary to electrically short these lines 13 and 16 at portions to which at least the output buffer circuits are connected. If not, the desired effect of halving the resistance of the power line cannot be achieved. In Fig. 3, each circle 33 located along the sub Vss power line 16 denotes a portion where the line 16 is electrically shorted to the VSS power line 13 lying thereunder through, for example, a through-hole. It should be understood that the other through-holes 34 are used for supplying the VDD power to the logic circuit region 21. The above mentioned matter will now be explaIned. Figure 4A is an equivalent circuit diagram of the circuit region 22, the lines 13 and 16, and the Vsn power source in a case were there are no electric shorts 33 in Fig. 3. Figure 4B is an equivalent circuit diagram of the circuit region 22, the lines 13 and 16, and the V33 power source in a case where there are electric shorts 33 in Fig. 3. When there are no electric shorts 33, (refer to Fig. 4A), a current i from the output buffer circuit (symbolized by I/O) flows to the V33 power source only through the Vss power line 13, and exhibits an equivalent resistance of R. Contrary to this, when where are electric shorts 33 between the lines 13 and 16, the current i is divided into two currents i/2 flowing through these lines. Therefore, the equivalent resistance R is reduced to R/2. In these figures, reference numeral 24(31) represents the pads in Figs. 2 and 3 connected with the Vss power source. It should be noted that while the above explanations are made regarding the power line of the Vss side as the worst case, the same applies to the power line of the VDD side, if necessary. In the worst case, the previously mentioned malfunctions may take place in the LSI circuit. Last, an example of the malfuction will be mentioned for reference. Assuming that the LSI circuit shown in Figs. 2 and 3 is fabricated as a microcomputer unit, a malfunction may take place in conjunction with an asynchronous reset signal RST ( only shown in Fig. 3), which is received at certain input buffer circuit I, which signal initializes the operation thereof. Figure 5 is a circuit diagram of an example of a prior art input buffer circuit I shown in Fig. 3. The input buffer circuit I is comprised of an input stage buffer 51 and an inverter 52. The output from the circuit I is supplied to a specified circuit of the logic circuit region 21, for example, a flip. flop FF. In both the buffer 51 and inverter 52, the transistors at the upper side are p-channel types and the transistors at the lower side are n-channel types. The buffer 51 functions as a TTL compatible circuit and determines the input logic "H" or "L" in accordance with the voltage level of the reset signal RST, i.e., whether the level is higher than 2 V or lower than 0.4 V, respectively. When the reset signal RST of logic "L" V'is supplied, the output of the buffer 51 is changed to the logic µ'H" and, therefore, the output of the inverter 52 is changed to the logic "L". This logic L" is applied to a clear terminal CL of the flip.f lop FF. Therefore, the FF is cleared and its output Q is reset to the logic "LV'. Then, the output Q changes in logic between nL" and "H" alternately in synchronizm with a clock signal CX after the reset signal RST changes to the logic "H". During a term at the logic "H" of the signal RST, the outputs of the buffer 51 and the inverter 52 maintain the logics "LH and 4,H", respectively. So long as the output of the inverter 52 maintains the logic "H", the flip.f lop FF cannot be cleared. Figure 6 depicts waveforms for explaining the operation of the circuit shown in Fig. 5. Referring to both Figs. 5 and 6, the logic change of the reset signal RST is depicted in row (1) of Fig. 6, in which a time t represents a completion of the reset operation for the flip.flop FF. Row {2) of Fig. 6 depicts logic changes of the input/output buffer circuits (I/O) and the output buffer circuits (0) in the peripheral circuit region 22. If the output logic changes take place in both the input buffer circuits (ol and the input/output buffer circuits (I/O) all at once at a time t2 , the instantaneous large current flows in the Vss power line. This large current induces a voltage drop in the VSS power line, This creates a voltage rise with respect to the ground level The The voltage rise is shown in row (3) of Fig. 6. When such a voltage rise occurs, in the Vss level, the logic tEn of the signal RST is seemingly lowered with respect to the rising Vss level. This causes a transformation of the logic "H" of the signal RST to the logic "L". Then the transformed logic "L" of the signal RST unintentionally clears the flip.flop FF. This concludes in the aforesaid malfunction. According to the present invention, since the above-mentioned voltage rise is halved in level, the erroneous logic change causing the malfunction can be prevented. The reset operation metioned above is performed by the asynchronous reset signal. This asynchronous reset operation leads to the worst case. If a synchronous reset operation is conducted, the malfunction will not occur. This is because, under such a synchronous reset mode, it is very easy to avoid coincidence of the timing of the reset with the timing of the logic change causing the aforesaid instantaneous current flow. For example, when the reset operation is preset to be effective at every rising edge of the clock signal, the logic change causing the instantaneous large current should be preset to be effective at every falling edge thereof. However, under the asynchronous reset operation mode, it is impossible to avoid coincidence of the timings. Such coincidence may frequently occur, thus producing malfunctions. As explained above in detail, according to the present invention, the deviation of the ground level in the semiconductor circuti, which is produced by the instantaneous large current flowing through the power lines, especially the Vss power line, can be suppressed. Thus, almost all malfunctions may be prevented. Particularly, the present invention is advantageous for a device having a plurality of input/output buffer cells around a basic cell array, such as a gate array LSI,

Claims: CLAMS 1. A semiconductor device comprising: a semiconductor substrate; a logic circuit region arranged in the semiconductor substrate, said logic circuit region having a plurality of logic circuits; a peripheral circuit region arranged around said logic circuit region, said peripheral circuit region having a plurality of peripheral circuits, at least one of said peripheral circuits having an output buffer circuit; first and second power lines distributed, at least, along the peripheral circuit region; and a sub power line distributed on a layer different from a layer on which said first power line distributed, in which electric shorts are formed between said first power line and said sub power line at portions under which one or more of said peripheral circuits including output buffer circuits therein are located and connected to the first power line. 2. A semiconductor device as set forth in claim 1, wherein the peripheral circuit region to be located under and connected with said electric shorts further includes an input buffer circuit composing said peripheral circuit. 3. A semiconductor device as set forth in claim 2, wherein said sub power line is electrically shorted via through-holes to said first power line. 4. A semiconductor device as set forth in claim 3, wherein said sub-power line is distributed in parallel with and right above said first power line. 5. A semiconductor device as set forth in claim 4, wherein both said first power line and said sub-power line are connected to either a first power source for supplying a first power source voltage or a second power source for supplying a second power source voltage higher than the first power source voltage. 6. A semiconductor device as set forth in claim 5, where In the first power source is connected to the first power line, the second power source is connected to the second power line, the first power line is formed on a first layer, and the sub power line and the second power line are formed on a second layer. 7. A semiconductor device as set forth in claim 5, wherein the second power line is formed on a first layer, the first power line is formed on a second layer, and the sub power line is formed on a third layer. 8. A semiconductor device as set forth in claim 7, wherein said sub power line is wide enough to cover both the first and second power lines. 9. A semiconductor device as set forth in claim I, wherein the first power line supplies a ground potential.

Inventors: HINO, YOUZI
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: H01L23
IPC codes: H01L23, H01L27, H01L21