CONTROLLABLE SWEEP GENERATOR

Abstract: A programmable sweep generator for generating a linear ramp signal of different slopes in a predetermined step sequence is disclosed.® The programmable sweep generator comprises a controllable voltage generator, a voltage-to-current converter, and integrator sections. The slopes of the ramp signal may be electronically controlled by switching the controllable voltage generator, voltage-to-­ current converter and timing capacitors in the integrator section. The use of independent buffer amplifiers, indepen­ dent control circuits, and current steering devices for each timing capacitor eliminates the need to connect a switching element in series with each timing capacitor, thereby elimi­ nating any error or non-linearity.

Description: Background of the invention The present invention relates generally to controllable sweep generators, and more particularly to a sweep generator for generating a sweep signal, the slope or sweep rate of which may be switched in predetermined steps. Sweep (or ramp) generators are widely used in electronic instrumentation, one example of which is in an oscilloscope, wherein accurate sweep signals are generated in predetermined steps to provide the timebase of a quantitative waveform measurement. Sweep generators for typical oscilloscopes generate timebase sweep signals ranging from ten nanoseconds per screen division to five seconds per screen division in 1-2-5 steps. Shown in Fig. 1 is a conventional sweep generator which comprises a controllable current source including transistor Q₁, a plurality of timing resistors R₁, R₂, ..., R n , switches S₂₁, S₂₂, ..., S 2n , and operational amplifier OP, a plurality of timing capacitors C₁, ..., C m , switched by respective switches S₁₁, ..., S 1m , a gating transistor Q₂ and a buffer amplifier A. A reference voltage V ref is applied to the non-inverting input of operational amplifier OP to maintain the emitter potential of transistor Q₁ equal to V ref regardless of the output current from the controllable current source, i.e., the collector current of transistor Q₁, depending on the selected timing resistor R₁, R₂, ..., or R n . Such output current is commonly referred to as a timing current and is utilized to charge the selected timing capacitor C₁, ..., or C m while gating transistor Q₂ remains non-conducting, thereby developing a linear ramp voltage across the timing capacitor to be made available via buffer amplifier A to output terminal OUT. The sweep rate is proportional to the timing current but inversely proportional to the capacitance of timing capacitor. Gating transistor Q₂ is turned on by applying a relatively positive voltage to the base thereof to discharge the timing capacitors C₁, ..., C m , thereby forming a short retrace portion of the ramp signal. Buffer amplifier A may include a source follower field effect transistor (FET) input stage and an emitter follower output stage for impedance conversion, thereby minimizing changes in the timing current due to leakage (or bias current), which may cause timing error. Disadvantages of the conventional sweep generator include the need for many precision timing elements (capacitors and resistors) including timing resistors in the order of ten kilohms to over ten megohms and difficulty in implementing electronic switches For example, any resistance in series with the timing capacitor would develop an undesirable voltage step when the timing current is supplied thereto. Such a voltage step is not negligible as the timing current becomes larger. In addition, in an article entitled "A time interval selector and proportional delay generator" by N. L. Roy and D. G. Becker published in The Review of Scientific Instruments, Vol. 42, No. 2, Feb 1971, pages 204-209 a ramp generator and current source is described comprising all the features of the first part of claim 1. Summary of the invention A controllable sweep generator according to the present invention is set forth in independent claim 1. Brief description of the drawings Fig. 1 is a circuit schematic of a conventional sweep generator; Fig. 2 is a simplified block diagram of a controllable sweep generator; Fig. 3 is a simplified circuit schematic of a controllable sweep generator; Fig. 4 is a circuit schematic of another controllable sweep generator; Fig. 5 is a simplified circuit schematic of still another sweep generator; Fig. 6 is a block diagram of a sweep integrator circuit according to the present invention; Fig. 7 is a circuit schematic of an integrator associated with Fig. 6; and Fig. 8 is a circuit schematic of a buffer amplifier for sweep signal output. Detailed description Referring now to Fig. 2 illustrating a simplified block diagram. The controllable sweep generator comprises three blocks: controllable voltage generator 12 to generate a plurality of output voltages V R under control of an input signal applied to input terminal 10, voltage-to-current converter 14 for converting the V R into the corresponding timing currents I T , and integrator 16 integrating the current I T to develop an output sweep voltage to be available from output terminal 18 by way of a buffer amplifier as necessary. Controllable voltage generator 12 may include a controllable current source, which may be operable under control of µP, and a current-to-voltage converter. The output voltage V R may suitable be in the range of 20 to 25 volts. Voltage-to-current converter 14 may include a plurality of resistors to generate a timing current of desired magnitude. Switching of such resistors may be performed by using electronic switches to facilitate control by a µP or any other digital control device. Integrator 16 may include a plurality of switchable timing capacitors or may be a Miller integrator. Although not shown in Fig. 2, a control signal or a sweep gate signal may be applied to integrator 16 for repetitive generation of the sweep signal by charging and discharging such timing capacitors. Shown in Fig. 3 is a circuit schematic of the controllable sweep generator. Controllable voltage generator 12 comprises in this particular circuit operational amplifier 21, current source 20 coupled to the inverting input of operational amplifier 21 and resistor 22 connected between the inverting input and the output terminals of operational amplifier 21. It is understood that the output voltage V R = I₂₀ x R₂₂, where I₂₀ and R₂₂ represent respectively the output current from current source 20 and the resistance of feedback resistor 22. The V R is therefore controllable by varying either one or both of the values of I₂₀ and R₂₂. For precise control of voltage V R , however, the current I₂₀ is normally controlled by utilizing, for example, a digital-to-analog converter (DAC) to receive a digital signal from a computer or similar control means. The output voltage V R is then forced by operational amplifier 21 across a selected one of resistors 24 a , 24 b , ..., 24 n selected by switch 26 constituting voltage to current converter 14 along with FET 25, which may be replaced by a PNP transistor. Because of very high input impedance of operational amplifier 21, such as, for example, the one including an FET input stage, the current I₂₀ flows through feedback resistor 22. Similarly, the resulting current flowing through the selected resistor 24, which is substantially equal to V R /R₂₄, flows only through the source-drain (or emitter-collector) path of transistor 25. The non-inverting input of operational amplifier 21 is maintained at a desired voltage by transistor 25 along with the gate (or base) bias network. Integrator section 16 receiving the drain output current (timing current I T ) comprises a plurality of switchable capacitors 43 a , 43 b , ..., 43 n selected by switch 17 and buffer amplifier 29, which may include an FET input stage. It is understood that the timing current I T is directly proportional to the current I₂₀ (or the voltage V R ) and inversely proportional to resistance R₂₄ (the resistance of selected resistor 24 a , 24 b , ..., 24 n ). The sweep rate (slope) of the sweep signal is directly proportional to the current I T and inversely proportional to the capacitance of the selected timing capacitor 43. The sweep rates of the resulting sweep signal may be controlled over a wide range by proper control of current source 20, and switches 26 and 17. Timing current I T may be varied, for example, from ten microamperes to five milliamperes in 1-2-5 step sequence without using very large timing resistors. Shown in Fig. 4 is a circuit schematic of another sweep generator. Controllable voltage generator section for generating the voltage V R is not included in Fig. 4 for simplicity. The voltage V R generated by any desired generator similar to the one in Fig. 3 or described hereinafter is first applied to one end of input resistor 37 by way of buffer amplifier 36. The other end of input resistor 37 is applied to the non-inverting input of operational amplifier 38 comprising transistors Q₁₀ through Q₁₄, and resistors R₁₀ through R₁₃. Transistors Q₁₀ and Q₁₁ comprise an emitter coupled transistor pair with the base of transistor Q₁₁, the inverting input, referenced to ground. Transistors Q₁₂ and Q₁₃ form a current mirror circuit. The collector of transistor Q₁₁ is coupled to the base of transistor Q₁₄, providing an emitter follower amplifier. The emitter output of transistor Q₁₄ is applied to the base of transistor 39, the collector of which is fed back to the non-inverting input of operational amplifier 38 by way of the common base transistor Q₁₈. A reference voltage provided by resistive divider comprising resistors R₁₄ and R₁₅ is applied to the base of transistor Q₁₈. The emitter of transistor 39 is returned to a negative voltage source through resistor 40. A plurality of current source transistors 41 a , , 41 n including respective programmed emitter resistors 42 a , ..., 42 n are connected in parallel with transistor 39. Connected to the collectors of transistors 41 a , ..., 41 n is a switching circuit 46 to provide a controllable timing current I T to integrator 16 through output terminal 48 under control of a logic control signal applied to control terminals T 1a , T 1b , ..., T na , T nb . The collector of transistor 41 a is coupled to the common emitter junction of emitter coupled transistor pair Q₂₃-Q₂₄. Similarly, the collector of transistor 41 n is coupled to the emitter junction of emitter coupled transistors Q₂₇-Q₂₈. Voltage swing on the bases of transistors Q₂₃, Q₂₄, Q₂₇ and Q₂₈ is determined by respective transistors Q₂₁, Q₂₂, Q₂₅ and Q₂₆, the bases of which are coupled to the base of transistor Q₁₈ by way of emitter follower transistor Q₂₀ for buffer and temperature compensation purposes. Coupled to the bases of transistors Q₂₃, Q₂₄, Q₂₇ and Q₂₈ are control terminals T 1a , T 1b , ..., T na and T nb . One collector output of each emitter coupled transistor pair Q₂₃-Q₂₄, ..., Q₂₇-Q₂₈ is grounded but the other collector outputs are coupled in common to output terminal 48. In operation, operational amplifier 38 amplifies the input signal thereto in such a manner that the entire current (V R /R₃₇) flows from collector to emitter through transistor Q₁₈ and then to the emitter of transistor 39, thereby setting the base voltage of transistor 39, 41 a , ..., 41 n substantially equal to R 40 R 37 V R . The collector current of the transistor 41 a is substantially equal to R 40 R 37 R 42a V R . Similarly, the collector current of transistor 41 n is substantially equal to R 40 R 37 R 42 n V R . This suggests that the collector current of transistor 41 a , ..., 41 n is inversely proportional to the respective emitter resistor 42 a , ..., 42 n . Such collector current is routed to output terminal 48 when a relatively high control voltage is applied to control terminals T 1b , T 2b , ..., T nb , but bypassed to ground when a relatively high control voltage is applied to the other control terminals T 1a , T 2a , ..., T na . Such selected timing current I T is supplied to integrator 16 to charge timing capacitor, thereby developing a linear ramp signal thereacross. As is understood from the foregoing description, controllable voltage V R , resistance of resistors 42 a , ...,42 n are controlled so as to provide the programmable sweep voltage. Such selection may be made by controlling the digital signal applied to control terminals T 1a , T 1b , ..., T na , T nb in addition to the input signal to control voltage generator 12. The resistance of resistor 37 may also be switched as necessary. Note that the above-described programmable current source may be used as current source 20 in Fig. 3. Fig. 6 shows a simplified block diagram of integrator circuit according to the present invention. This is particularly suited for switching one timing capacitor of a plurality of timing capacitors by electronic switching means. Applied to terminal 50 is a sweep gate pulse to control the generation of termination of the sweep signal. In this particular embodiment, three independent timing capacitors 54 a , 54 b , and 54 c and respective control circuits are used. Three reset current switch and disconnect diode circuits 52 a , 52 b , and 52 c receive the sweep gate signal applied to control terminal 50, reset current I R from reset current source 68 by way of switch 64, and the output from sweep start regulator 58. A timing current I T from current source 66 is supplied to timing capacitor 54 a , 54 b , or 54 c selectively through switch 60. The sweep voltage across each timing capacitor 54 a through 54 c is respectively coupled to output terminal 70 by way of respective buffer amplifier 56 a through 56 c and switch 62. Switches 60, 62 and 64 are intercoupled to operate simultaneously to select one of timing capacitors 52 a , 52 b and 52 c . The output voltage on output terminal 70 is applied to one input of comparator or sweep start regulator 58 which compares the quiescent output voltage with a sweep start reference level applied to the other input of such regulator 58. It is to be understood that while three timing capacitors are shown for this embodiment, the system may be expanded to include any desired number of timing capacitors. In operation, all of the switches 60, 62, and 64 are set to the upper portion "a" to select the first timing capacitor 54 a . During the sweep period of the sweep gate signal applied to control terminal 50, the timing current I T is routed into timing capacitor 54 a , thereby developing a ramp voltage thereacross. Such ramp voltage is supplied to output terminal 70 through buffer amplifier 56 a and switch 62. Similarly, the second or third timing capacitor 54 b or 54 c is chosen by setting switches 60, 62 and 64 to the middle position "b" or the lower position "c". When the sweep period is terminated, respective reset current switch and disconnect diode 52 a , 52 b or 52 c is activated to discharge the respective timing capacitor, thereby forming the retrace portion of the ramp signal. Reset current I R is always larger than timing current I T . Sweep start regulator 58 is used to establish a constant sweep start level by forming a closed loop circuit including the selected timing capacitor 54 and its associated circuits 52 and 56. This circuit arrangement is particularly useful to avoid any error or voltage step mentioned earlier due to the residual resistance or reactance of the switch connected in series with such timing capacitor. In addition, no stray capacitance of an "off" switching device is added to the timing capacitor, thereby avoiding any timing error. It should be noted that buffer amplifier 56 is directly coupled across the respective timing capacitor because of the use of independent buffer amplifier and control circuit. As is described hereinafter, optimum buffer circuit may be used as each buffer amplifier 56 a , 56 b or 56 c . The integrator block of Fig. 6 will be better understood by reference to Fig. 7 illustrating a circuit schematic of one practical embodiment. Reset current switch and disconnect diode circuit 52 comprises three emitter coupled transistor pairs Q₆₀-Q₆₁, Q₆₂-Q₆₃ and Q₆₄-Q₆₅ and three diodes D₁, D₂ and D₃. The bases of transistors Q₆₀, Q₆₂ and Q₆₄ are connected in common to control terminal 50 while the bases of transistors Q₆₁, Q₆₃ and Q₆₅ are connected to a suitable bias voltage source V bias . The emitter node of each transistor pair is connected to reset current source 68. The collectors of transistors Q₆₀, Q₆₂ and Q₆₄ are connected to a positive voltage source while the collectors of transistors Q₆₁, Q₆₃ and Q₆₅ are respectively connected to timing capacitors 54 a , 54 b and 54 c . Anodes of three diodes D₁, D₂ and D₃ are coupled in common to the output of sweep start regulator 58 while the cathodes of such diodes are coupled respectively to timing capacitors 54 a , 54 b and 54 c . Timing current source 66 is selectively coupled to timing capacitor 54 a , 54 b or 54 c by way of respective current-steering FETs Q₇₅, Q₇₆ or Q₇₇ which are under control of switching logic circuit 67. Although not shown in Fig. 7, similar switching devices and a control logic circuit are included in reset current source 68. Buffer amplifiers 56 comprise three FETs Q₇₀, Q₇₁ and Q₇₂, current source FET Q₇₃, resistors R₇₀ and R₇₁ and emitter follower output transistor Q₇₄. The gates of FETs Q₇₀, Q₇₁ and Q₇₂ are coupled to respective timing capacitors 54 a , 54 b , and 54 c . The sources of FETs Q₇₀ through Q₇₂ are connected together to the lower end of resistors R₇₀, the upper end of which is connected to the base of transistor Q₇₄. The emitter of transistor Q₇₄ is connected to sweep start regulator 58 and defines output terminal 70 from which a linear ramp signal is produced. The outputs of the three buffer amplifiers are directly coupled and no selection switch representing switch 62 in Fig. 6 is employed in this particular embodiment. In operation, assuming now that first timing capacitor 54 a is to be selected, logic control circuit 67 provides a low level only to the gate of FET Q₇₅ to steer all of timing current I T to the selected timing capacitor. Simultaneously, reset current source 68 is controlled to supply the reset current I R to the emitter node of first transistor pair Q₆₀-Q₆₁. As mentioned above, reset current I R is selected to be always larger than timing current I T . During the retrace or quiescent condition of the sweep gate signal applied to control terminal 50, the base of transistor Q₆₀ is lower than V bias , thereby making Q₆₁ conductive. Timing current I T from FET Q₇₅ and discharge current of timing capacitor 54 a flow through such transistor Q₆₁ during retrace. In the quiescent condition, timing capacitor 54 a is completely discharged, and the difference current equal to (I R -I T ) is supplied from start level regulator 58 through diode D₁, thereby completing the closed loop to maintain the sweep start level equal to the reference level (e.g, ground level) applied to sweep start regulator 58. Degeneration resistor R₇₁ helps determine the drain current of Q₇₃ operating as a current source. Resistor R₇₀ is used for proper DC offset. A linear ramp (or sweep) voltage starts from the aforementioned reference level when the sweep gate voltage at control terminal 50 goes high, thereby turning transistor Q₆₁ off and transistor Q₆₀ on, shifting reset current I R to a power supply. The selected timing capacitor 54 a is now charged by the timing current I T at the rate proportional to the I T but inversely proportional to the capacitance of such timing capacitor. As the ramp voltage develops across such timing capacitor, diode D₁ is automatically disconnected. The ramp voltage is then transmitted to output terminal 70 through FET Q₇₀, resistor R₇₀, and emitter-follower transistor Q₇₄. A reset circuit (not shown) is normally utilized to reset the sweep gate pulse when the ramp voltage reaches a predetermined level, thereby starting the retrace portion of the sweep signal. The above operation may be repeated by controlling the sweep gate signal applied to control terminal 50. It should be pointed out that a logic circuit or other mechanism (also not shown) holds the gate of FETs Q₇₁ and Q₇₂ high when timing capacitor 54 a is selected. Other timing capacitors 54 b or 54 c may be selected in the same manner to develop ramp signals of different sweep rates or slopes. FET Q₇₆ and second emitter coupled transistor pair Q₆₂-Q₆₃ are energized to select timing capacitor 54 b . FET Q₇₁ and diode D₂ constitute part of the closed loop in this instance. Similarly, FET Q₇₇ and third transistor pair Q₆₄-Q₆₅ are energized to select timing capacitor 54 c . FET Q₇₂ and diode D₃ constitute part of the closed loop in this instance. A wide range of sweep signals are generated by simply utilizing a single current source I T . The use of the independent reset current switch/disconnect diode for each timing capacitor and current steering FETs Q₇₅ through Q₇₇ is responsible for deletion of a selector switch in series with the timing capacitor from which the ramp signal is derived. This is very useful in avoiding voltage steps, spikes, etc. which cause non-linearity of the ramp signal. Although the buffer amplifiers connected to each timing capacitor are identical in this particular embodiment, different buffer amplifiers may be better suited for each sweep signal, i.e., a faster buffer amplifier for high speed. sweep signal. Fig. 8 shows a circuit schematic of such an example. Assuming that first timing capacitor 54 a is the lowest in capacitance for developing a high speed sweep signal, Darlington connected high frequency transistors Q₇₈ and Q₇₉ are used as buffer amplifier 56 a for such timing capacitor. Slight leakage current of the timing current I T may be caused because of the finite base bias current characteristic of bipolar transistors. However, such leakage or bias current may be minimized by using the Darlington connection of two high current gain transistors, increasing the timing current I T , or controlling current source 80 in proportion to the I T . Alternatively, very short channel high f T MOS FET may be substituted for the Darlington transistors. The foregoing description is made on preferred embodiments of this invention so that one having skill in the art can put the present invention into practice in any forms best suited to a particular application.

Claims: 1. A controllable sweep generator, comprising a voltage generator (12), a voltage-to-current converter (14, 66) for converting the output voltage from said voltage generator into a current for output to an integrator (16) for developing a linear ramp voltage therefrom wherein said voltage generator (12) is controllable to generate a plurality of output voltages (V R ) under the control of an input signal (10); said voltage-to-current converter (14, 66) converts said output voltages (V R ) into a plurality of timing currents (I T ) for input to said integrator (16), characterised in that said integrator includes a plurality of timing capacitors (54) each connected at one end to a reference potential source; a plurality of buffer amplifiers (56) respectively connected to the other end of said timing capacitors (54); control means (67) for selectively supplying a timing current (I T ) to one of said timing capacitors (54) and for controlling the charging and discharging of said timing capacitors (54). 2. A controllable sweep generator in accordance with claim 1, further including a reset current source (68) for selectively coupling a reset current (I R ) larger than said timing current (I T ) to the selected timing capacitor (54), and a start level regulator (58) for maintaining the start level of the sweep signal. 3. A controllable sweep generator in accordance with claim 1, wherein at least one of said buffer amplifiers uses Darlington transistors (78, 79). 4. A controllable sweep generator in accordance with claim 3, wherein a current source (80) responsive to the timing current is connected to the emitter of the output stage transistor of said Darlington transistors (78, 79). 5. A controllable sweep generator according to claim 2, wherein the output of said start level regulator (58) is connected to each of said timing capacitors (54) through a diode (D1, D2, D3). 6. A controllable sweep generator according to claim 1, wherein said control means includes a plurality of emitter coupled transistor pairs to the emitters of which said reset current source (68) is selectively coupled.

Inventors: AINSWORTH, WALTER W., METZ, ARTHUR J.
Applicants: TEKTRONIX, INC.
Application year: 1983
Main classification: H03K4
IPC codes: H04N3, H03K4