ELECTRONIC POSTAGE METER HAVING A RESET CIRCUIT

Abstract: A reset circuit for an electronic postage meter controls the operation of the reset line (104) of the meter's computing system (58). The reset circuit operates in conjunction with a protection circuit for a non-volatile memory (62). The interrelation of the reset circuit (102,124) and non-volatile memory protection circuit protects against possible loss of postage funds due to spurious data being written into the non-volatile memory (62). Circuit operation is controlled in part by voltage levels applied to the non-volatile memory. This insures that the reset to the electronic postage meter computing system is released during power-up of the meter after proper voltage levels are applied to non-volatile memory (62) and re-established during low power or power-down conditions.

Description: The present invention relates to electronic postage meters. Electronic postage meter systems have been developed, as for example, the systems disclosed in US-A-3,978,457 for Microcomputerized Electronic Postage Meter System, and in EP-A-0 019 515 for Electronic Postage Meter Having Improved Security and Fault Tolerance Features. Electronic postage meters have also been developed employing plural computing systems. Such a system is shown US-A-4,301,507 for Electronic Postage Meter Having Plural Computing Systems. The accounting circuits of electronic postage meters include non-volatile memory capability to store postage accounting information. This information usually includes the amount of postage remaining in the meter for subsequent printing and the total amount of postage printed by the meter. Other types of accounting or operating data may also be stored in the non-volatile memory. Electronic non-volatile memory function in electronic accounting circuits has replaced the function served in previous mechanical type postage meters by mechanical accounting registers. Postage meters with mechanical accounting registers are not subject to many problems encountered by electronic postage meters. Conditions cannot normally occur in mechanical type postage meters that prevent the accounting for a printing cycle or which result in the loss of data stored in the registers. In electronic postage meters conditions can occur where information stored in electronic accounting circuits can be permanently lost. Conditions such as a total power failure or fluctuation in voltage can cause the microprocessor and/or the non-volatile memory associated with the meter to operate erratically and either cause a loss of data or the storage of spurious data in the non-volatile memory. The loss of data or the storage of spurious data may result in the loss of information representing the postage funds stored in the meter. Since data of this type changes with the printing of postage and is not stored elsewhere outside the meter, there is no way to recover or reconstruct the lost information. In such a situation, a user may suffer a loss of postage funds. To minimize the likelihood of a loss of information stored in the electronic accounting circuits, efforts have been expended to insure the high reliability of electronic postage meters. Some systems for protecting the critical information stored in meters are disclosed in the above-noted patents as well as in U.S. Patent No. 4,285, 050 for Electronic Postage Meter Operating Voltage Variation Sensing System and in EP-A-75825 (U.S. Patent Application No. 306, 979 filed October 5, 1981) for Memory Protection Circuit for an Electronic Postage Meter, in the name of Pitney Bowes Inc. These systems provide protection against unpredictable circuit operation even if the microprocessor malfunctions at low voltage levels during power down, as for example, where the microprocessor turns off below a predetermined voltage level and thereafter, within a lower voltage range, turns on again and becomes capable of outputting data. An object of the present invention is to provide an electronic postage meter having a non-volatile memory means and an accounting means which operates very reliably and in which loss of data during low power conditions is very unlikely. The solution for this object is specified in the claims. The present invention provides a reset circuit which helps insure proper operation of an electronic postage meter. The reset circuit operates in conjunction with a non-volatile memory protection circuit. The combined operation of the reset circuit and the non-volatile memory protection circuit controls the reset line of an electronic postage meter computing means and a write enable terminal of the non-volatile memory. The reset circuit and the non-volatile memory protection circuit operate to insure proper function of the electronic postage meter during power-up and power-down of the meter as when the meter power switch is turned on and off. The circuits further protect the electronic postage meter from improper operation where spurious data might be written into the non-volatile memory. With use of the present invention, the reset circuit may operate in conjunction with voltages applied to the non-volatile memory, to insure that a microprocessor reset is not released, enabling a microprocessor of the postage meter to commence operation, until after the non-volatile memory voltage is at its proper level. The reset circuit can operate in a manner which insures that the reset terminal is maintained active to hold the microprocessor in the reset state while the voltage levels build so that the microprocessor will be enabled to write data into the meter's non-volatile memory only after the memory is properly powered. The reset circuit may also operate to simultaneously apply an active reset signal to the microprocessor when the necessary voltages to write into the non-volatile memory falls below a predetermined level. When a power reduction occurs causing the electronic postage meter to go into a power down routine, the reset circuit will cause the reset to go active putting the microprocessor into a known state after the completion of the power down routing when the non-volatile memory write voltage falls below a predetermined level. During a power-up condition, the reset circuit causes the reset terminal to be active until after the voltages have stabilized on the electronic postage meter non-volatile memory. The reset circuit may be adapted to simultaneously control plural reset terminals of plural computing systems. For example, the reset terminal of both an accounting module microprocessor and another microprocessor in the system, such as the microprocessor associated with the printing module, may be simultaneously controlled by the reset circuit. In EP-A-0075825, prior art according to Article 54(3)EPC, there has already been described a similar electronic postage meter arrangement with non-volatile memory means having a terminal which when energised by a voltage of a first predetermined value enables said non-volatile memory to have data written into memory locations thereof by said computer means, and which when energised by a voltage of a second predetermined value differing from said first voltage value disables said non-volatile memory from having data written into memory locations thereof by said computer means. However no provisions are made in this prior art postage meter to ensure that the computer means is enabled or disabled to output data in a definite timed relationship to the enabling and disabling of the non-volatile memory to have data written into memory locations thereof. Such a definite timed relationship is provided in the electronic postage meter disclosed in EP-A-0 019 515, however there, during a power-up routine, the computer means is enabled to output data before the non-volatile memory means is enabled to have data written into the memory locations thereof. A better understanding of the present invention may be obtained from the following detailed description thereof, when taken in conjunction with the accompanying drawings in which:- Figure 1 is an interconnection diagram of Figures 1a and 1b; and Figures 1a and 1b, when taken together, are a schematic circuit diagram, partly in block form, of an electronic postage meter reset circuit embodying the present invention. Reference is now being made to Figure 1. A postage meter 12 includes an accounting module 14 having microprocessor and non-volatile memory such as a General Instrument Corporation ER3400 type electronically alterable read only memory, a printing module 16 having microprocessor and motor control circuits; and a control module 18 having a microprocessor and control circuits. The detail of construction and operation of the system may be in accordance with the postage meter system and the mechanical apparatus shown in the above-noted US-A-4,301,507 for Electronic Postage Meter Having Plural Computing Systems and in US-A-4,287,825 for Printing Control System. Postage meter 12 includes a series of opto-interrupters 20,22,24,26 and 28. The opto-interrupters are used to sense the mechanical position of parts of the meter. For example, the opto-interrupters can be employed to sense the position of the shutter bar which is used to inhibit operation of the meter under certain circumstances, the position of the digit wheels, the home position of the print drum, the position of the bank selector for the print wheels, the position of the interposer, or any other movable mechanical component within the meter. These opto-interrupters are coupled to the printing module 16 which monitors and controls the position of the mechanical components of the meter. The printing module 16 is connected to the accounting module 14 via a serial data bus 30 and communicates by means of an ecoplex technique described in the above-noted US-A-4,301,507. Both ends of the bus are buffered by respective optics buffers, not shown, which are energized by the power supply +5 volt line to be hereafter described. Similarly, the control module 18 is connected to the accounting module 14 via a serial data bus 32 and also communicates by means of the ecoplex technique. Optics buffers, not shown, are provided to buffer the bus. It should be recognized that the particular architecture of the postage meter system is not critical to the present invention, plural or single microprocessor arrangements may each be employed. A source of operating voltage, such as (in the U.S.A.) 110 volts 60 Hertz supply, is applied across meter input terminals 34. The voltage is applied to a linear +10.8 volt power supply 36. The output from the +10.8 volt linear power supply 36 is supplied to a first +8 volt linear regulated power supply 38 and to a second +5 volt linear regulated power supply 40. The +8 volt power supply is used to power a display 42 which is operatively coupled via a bus 44 to the control module 18. The output from the power supply 40 is directly coupled to the control module 18 and is operated to energize the control module microprocessor. The AC operating voltage at terminals 34 is also applied to a silicon controlled rectifier-type, 24 volt power supply 46. The regulated output from the power supply 46 is applied to the print wheel bank stepper motor 48 and the print wheel stepper motor 50 associated with the printing module 16. The 24 volt DC power supply is coupled by an AC choke 52 to capacitor 54. The internal capacitance within the 24 volt power supply 46 provides sufficient energy storage to continue to properly energize a switching regulator 56 should an AC power failure occur at terminals 34. In such an event, the accounting module microprocessor 58 transfers information from the postage meter volatile memory (which may be internal or external to the microprocessor) via a data bus 60 to a MNOS non-volatile memory 62. The switching regulator 56, in conjunction with a transformer 68 with related circuitry, provides regulated output voltages used to energize the accounting module. A level of +5 volts is developed and applied to the accounting module microprocessor 58, to MNOS non-volatile memory 62, to the optic buffers (not shown) for the serial data bus 30 connected between the accounting and the printing modules, to the printing module 16, and to the opto-interrupters 20-28. A level of -30 volts is also developed and is similarly applied via an NPN transistor 64 to the MNOS non-volatile memory 62. The -30 volts is required in conjunction with a supply of -12 volts which is also developed and applied to the MNOS non-volatile memory 62 and the supply of +5 volts to enable the non-volatile memory to have data written into the device. The switching regulator 56 functions to selectively apply the 24 volts developed across the capacitor 54 to the junction of a diode 66 and poled transformer primary winding 68. The frequency at which the regulator 56 operates or switches is determined by a capacitor 70 which controls the operating frequency of the supply. Primary winding 68 is further coupled to ground by a capacitor 72. Diode 66 and capacitor 72 form a complete circuit in parallel with the primary winding 68. The circuit path is through a point of fixed referenced potential, here shown as ground. During quiescent operation, a level of +5 volts is developed across capacitor 72. This voltage is sensed and coupled via a series connected variable resistor 74 and a fixed resistor 76 to an input terminal on the switching regulator 56. The feedback path controls the supply to maintain a constant voltage across capacitor 72. For the component values shown, a voltage variation of approximately 10 millivolts can occur across capacitor 72. A step-up secondary winding 78 oppositely poled to the primary winding is electromagnetically coupled via a permalloy core 80 to the primary winding 68. The secondary winding 78 is connected to ground at one end and has its opposite end coupled via a diode 82 which operates in conjunction with a capacitor 84 and a current limiting resistor 86 to develop -30 volts across a zener diode 88. A tap 90 on the secondary winding is connected to a diode 92 which operates in conjunction with a capacitor 94 and a current limiting resistor 96 to develop -12 volts across a zener diode 98. Because of the filtering provided by capacitor 72 and the inductance of the primary winding 68, the noise introduced by switching transients in the primary circuit is minimized. In a like manner, the capacitors 84 and 94 and the inductance of the secondary winding 78, provide further filtering which also minimizes the noise introduced by switching transients. The operation of the power supply is described in greater detail in EP-A-0.075. 825 (US-A-4445198). A circuit is provided to insure that the MNOS non-volatile memory 62 is not energized by the -30 volts necessary for a writing operating after a predetermined voltage condition in the power down sequence has been reached. This circuit operates in conjunction with a second circuit adapted to insure a proper reset is applied in a predetermined relationship to the application and the removal of the -30 volts from the non-volatile memory. The system insures that even if data is put onto the data bus 60 by the microprocessor 58, no data will be written into the MNOS non-volatile memory 62. This is particularly important because it has been noted in the aforementioned EP-A-0075825 for Memory Protection Circuit for an Electronic Postage Meter that although the microprocessor may be designed to turn off and not output data at a determined voltage level, it has been discovered that such microprocessors may become active again even at lower voltages notwithstanding the signal applied to the microprocessor reset terminal. The -30 volts supply to non-volatile memory 62 is passed through the collector-emitter current path of the NPN transistor 64. The collector electrode of the transistor is coupled via a resistor 64 to the +5 volts developed at capacitor 72. The voltage developed at the collector electrode of transistor 100 controls the voltage applied to the base electrode of a transistor 102 whose collector electrode is connected to the reset terminal 104 of the microprocessor 58 of the accounting module 14 and to the reset terminal 106 of the microprocessor for the printing module 16. Base bias for the transistor 64 is obtained from a PNP transistor 108. The emitter electrode of the transistor 108 is connected by a 10 volt zener diode 110 to the 24 volt power supply 46. A resistor 112 provides a ground return for the base electrode of transistor 108. Resistors 114 and 116 are connected to the base electrode of transistor 64. A capacitor 118 is provided to further filter transients. The base electrode of transistor 102 is coupled to the collector electrode of transistor 64 by a resistor 120 and to the +5 volts developed at capacitor 72 by a resistor 122. A capacitor 124 is connected across the collector-emitter electrode current path of transistor 102. The collector electrode is further connected by a resistor 126 to the +5 volts developed at capacitor 72. It should be noted that although the transistor 102 is shown connected to the reset terminals 106 and 104 of the microprocessors, respectively associated with the printing module 16 and the accounting module 14, the arrangement is only by way of example. The reset system can be employed with either single microprocessor or plural microprocessor electronic postage meter systems. When the AC line voltage at terminals 34 fails, and the 24 volts output voltage of power supply 46 begins to drop and fall below a predetermined level, such as 19 volts, a low voltage detector 128 with about 2 volts of hysteresis senses the falling voltage and initiates an interrupt signal which is supplied to an interrupt or restart (RST) terminal 130 on the accounting module microprocessor 58. The interrupt signal initiates an interrupt routine e.g. as in the system disclosed in the aforementioned US-A-4,285,050 for Electronic Postage Meter Operating Voltage Variation Sensing System. The interrupt routine completes all pending accounting functions and transfers all register readings from the internal microprocessor RAM to the external non-volatile memory 62. It then goes into a wait loop which is terminated by a microprocessor reset or the return of normal voltage, indicated by a voltage greater than 21 volts at low voltage sensor 128. When the AC line voltage drops to a level such that the 10 volts zener diode 110 is no longer operating in a breakdown mode, current flow through the collector-emitter of transistor 108 ceases. As a result, transistor 64 is biased out of conduction. This causes the +5 volts which is applied via resistor 100 to the collector electrode of transistor 64 to be applied to the MNOS non-volatile memory -30 volt terminal 132. It should be noted that the -30 volts is required in conjunction with a -12 volts (which is also developed and applied to the MNOS non-volatile memory 62 -12 volts terminal 134) to have data written into the memory. Thus, rather than a negative voltage being applied to the microprocessor MNOS non-volatile memory -30 volt terminal 132, a positive voltage is applied and information cannot be written into the memory. Simultaneously with the application of the +5 volts to the MNOS non-volatile memory terminal 132, the +5 volts is likewise applied via resistors 100 and 120 and via resistor 122 to the base electrode of transistor 102. This biases transistor 102 into conduction causing capacitor 124 to quickly discharge through the collector-emitter electrode current path of transistor 102 thereby applying a reset signal to the reset terminals 104 and 106 of the accounting module microprocessor 58 and the printing module microprocessor respectively, by coupling these terminals to ground. The activation of the reset terminal places the microprocessor in a known condition. Nevertheless, the +5 volts applied to the MNOS non-volatile memory terminal 132 insures that no information can be written into the non-volatile memory 62 during the remainder of the power down cycle. This is because, as previously noted, a -30 volts must be applied to terminal 132 to enable a WRITE operation in the MNOS non-volatile memory 62. The microprocessors' reset terminals will have a reset signal applied (a ground level potential) as power decays until the voltage at the base electrode of transistor 102 falls below the level necessary to forward bias the base-emitter junction, usually approximately 7/10ths of a volt for many devices. For the various supplies and component values shown, by the time the output voltage of the +24 volt supply 46 decays to approximately +7.5 volts, the +5 volts developed at capacitor 72 will begin to drop. By this time however, the 10 volt zener diode 110 will have been turned off for a voltage change of approximately 2 1/2 volts and terminal 132 will have had a positive voltage applied to it. Thus, when the output voltage from the +24 volts supply drops to approximately +10 volts, a positive potential is applied to the MNOS non-volatile memory -30 volts write enable terminal 132, and no data can be written by microprocessor 58 into the non-volatile memory 62. This situation continues until the voltage falls below the range of uncertain operating voltage levels wherein the microprocessor 58 may operate despite a reset signal being applied to the reset terminal 104. Protection against writing into the MNOS non-volatile memory 62 is afforded by control over the conductivity of the collector-emitter electrode current path of transistor 64. During a power-up routine as the voltages begin to build, the voltage from the +24 volts power supply 46 begins to charge up its capacitors including capacitor 54 as it builds towards the 24 volt output. When the voltage builds to a sufficient level, zener diode 110 will break down and begin to conduct. This establishes a current flow through the collector-emitter electrode current path of transistor 108 which in turn biases transistor 64 into conduction. As a result, the -30 volts is coupled via resistor 120 to the base electrode of transistor 102 biasing the transistor out of conduction. Up to this point in time, however, transistor 102 is biased into conduction as the voltage builds by the +5 volts applied to its base electrode via resistors 100 and 120 and via resistor 122. This prevents a charge from building up on capacitor 124 thereby causing a solid reset signal to be applied to the reset terminals 104 and 106. When the -30 volts is applied to the MNOS non-volatile memory terminal 132, transistor 102 is biased out of conduction. This allows capacitor 124 to begin charging from the +5 volts supply through resistor 126. When the capacitor is charged to a suitable level, the reset signal is removed from the reset terminals 104 and 106 of the microprocessors, and the microprocessors begin executing instructions. It should be noted that the time delay due to charging the capacitor 124 and controlling the bias of transistor 102 from the -30 volts supply insures that the -30 volts potential is applied and has stabilized on the MNOS non-volatile memory -30 volt terminal 132 prior to the microprocessor reset terminals being released to enable the microprocessor to commence operation. Moreover, when the power begins to fall, the reset terminals 104 and 106 of the microprocessors are rendered active putting the microprocessors in the reset condition simultaneously with the removal of the -30 volts supply from the NMOS non-volatile memory terminal 132. The sequence of operation of the electronic postage meter reset circuit shown in Figures 1a and 1b is set forth in the following table. Sequence of Operations Power-Up State 24 V Supply + 5 V Supply Microprocessor Reset Low Voltage Sense Non-Volatile Memory (NVM) 1 0 - 7.5 < 5 Indeterminate Low Disabled 2 7.5 - 10 V + 5 Reset Low Disabled 3 10 - 21 V + 5 Wait Low Enabled Loop 4 21 - 24 V + 5 Read NVM Normal Enabled Then Operate Power-Down State 24 V Supply + 5 V Supply Microprocessor Reset Low Voltage Sense Non-Volatile Memory 4 24 - 19 V + 5 Operate Normal Enabled 5 19 - 10 V + 5 Write NVM Low Enabled Then Wait Loop 2 10 - 7.5 + 5 Reset Low Disabled 1 7.5 - 0 < 5 Indeterminate Low Disabled It is known and will be understood that for the purposes of the present application the term "postage meter" refers to the general class of device for the imprinting of a defined unit value for governmental or private carrier delivery of parcels, envelopes or other like application for unit value printing. Thus, although the term postage meter is utilized, it is both known and employed in the trade as a general term for devices utilized in conjunction with services other than those exclusively employed by governmental postage and tax services. For example, private, parcel and freight services purchase and employ such meters as a means to provide unit value printing and accounting for individual parcels.

Claims: An electronic postage meter comprising: input means (34) for connection to a source of operating voltage; printing means (16, 48, 50) for printing postage; accounting means (14) coupled to said printing means for accounting for postage printed by said printing means, the accounting means including computer means (58) having a reset terminal (104) for receiving a first predetermined reset terminal voltage (+5V) to enable said computer means (58) to be conditioned to output data and for receiving a second predetermined reset terminal voltage (0V) to disable said computer means from being conditioned to output data, the accounting means (14) further including non-volatile memory means (62) operatively coupled to said computer means (58) for storing accounting data when said source of operating voltage is not operating to energise said accounting means, said non-volatile memory means (62) having a terminal (132) which when energised by a first voltage of a first predetermined value (-30V) enables said non-volatile memory means to have data written into memory locations thereof by said computer means, and which when energised by a second voltage of a second predetermined value (+5V) differing from said first predetermined value disables said non-volatile memory means from having data written into memory locations thereof by said computer means (58); first voltage generating means (78, 86, 88) for generating said memory terminal voltage of said first value (-30V); second voltage generating means (68, 72) for generating said memory terminal voltage of said second value (+5V); first voltage applying means (64, 100, 108, 110) coupled to said first voltage generating means (78, ...), said second voltage generating means (68, 72) and said non-volatile memory terminal (132) for applying said voltage of said first value (-30V) to said non-volatile memory terminal (132) when said source of operating voltage is above a predetermined level and for applying said voltage of said second value (+5V) to said non-volatile memory terminal(132) when said source of operating voltage is below a predetermined level; and second voltage applying means (102,124,126) coupled to said first voltage applying means (64, ...) and to said computer reset terminal (104) for energising said reset terminal (104) during power up of the meter with said first predetermined reset terminal voltage (+5V) only after said non-volatile memory terminal (132) is energised by said voltage of a said first value (-30V). A postage meter as claimed in claim 1 wherein said second voltage applying means (102,124,126) is further adapted to selectively energise said reset terminal (104) with said second predetermined reset voltage. A postage meter as claimed in claims 1 or 2 wherein said second voltage applying means (102,124,126) is adapted to energise said reset terminal (104) with said second predetermined reset voltage when said first voltage applying means (64,100,108,110) applies said voltage of said second value (+5V) to said non-volatile memory terminal (132) such that said computer means (58) is disabled from operating to output data when said non-volatile memory means (62) has been disabled from data being written into its memory locations by said computer means (58). A postage meter according to claim 1 wherein said first and second voltage applying means comprise respective first and second three-terminal switching devices (64,102) each having a first, a second and a control terminal: the first-second terminal current path of said first device (64) being connected in series between said non-volatile memory terminal (132) and said first voltage generating means; means (114,116,108,110) being provided for sensing the voltage level of said source or operating voltage; means coupling the control terminal of said first switching device (64) to said sensing means such that said sensing means controls the conductivity of said first-second terminal current path of said first switching device (64); and the first-second terminal current path of said second three-terminal switching device (102) being coupled between said second voltage generating means (68, 72) and a point of fixed reference potential, said first terminal of said second three-terminal switching device being coupled to said computer means reset terminal (104), and said control terminal of said second three-terminal switching device (102) being coupled to said first terminal of said first three-terminal switching device (64). A postage meter as claimed in claim 4 wherein said first and said second three-terminal switching devices are transistors. A postage meter according to claim 1, wherein: data bus means (60) is provided for coupling data terminals of said computer means (58) and said non-volatile memory means (62) to enable said computer means to read data from said non-volatile memory means and to write data into said non-volatile memory means; said first voltage applying means comprises a first transistor (64) having an emitter electrode, a collector electrode and a base electrode, the collector-emitter electrode path of which is coupled between said non-volatile memory terminal (132) and said first voltage generating means (78, ...); resistor means (100) is provided for coupling said collector electrode of said first transistor (64) to said second voltage generating means (68,72); said second voltage applying means (102, ...) comprises a second transistor (102) having a collector, an emitter and a base electrode, the collector-emitter electrode path of which is coupled between said second voltage generating means (68,72) and a point of fixed reference potential; means are provided for coupling the collector electrode of said second transistor (102) to said computer means reset terminal (104); capacitor means (124) are coupled between the collector and emitter electrodes of said second transistor (102); and voltage divider means (120,122) are coupled to the base electrode of said second transistor (102) and between the collector electrode of said first transistor (64) and said second means. A postage meter as claimed in claim 6 wherein said printing means includes a microprocessor (16) for controlling the operation of said printing means, said printing means microprocessor (16) having a reset terminal (106), and means coupling said reset terminal (106) of said printing module microprocessor (16) to the collector electrode of said second transistor (102). A postage meter as claimed in claims 6 or 7 further comprising: a third transistor (108) having an emitter, a collector and a base electrode; a zener diode (110); a power supply (46) coupled to and adapted to energise said first and second voltage generating means; and the collector-emitter electrode path of said third transistor (108) being connected in series with said zener diode (110) between said power supply (46) and the base electrode of said first transistor (64). A postage meter as claimed in claim 8 wherein said computer means (58) included in said accounting means includes an interrupt terminal (130) and in that a low voltage sensor (128) is coupled between said power supply (46) and said interrupt terminal.

Inventors: ECKERT, ALTON B.
Applicants: PITNEY BOWES INC.
Application year: 1983
Main classification: G07B17
IPC codes: G07B17, G06F1