Semiconductor integrated-circuit apparatus

Abstract: An integrated circuit device comprises a substrate in which integrated circuits are formed and on which a first power supply line layer (45,V CC ) and a second power supply line layer (50,51,52,V EE ) are formed; a plurality of first internal pads (46) formed on the substrate and connected to the first power supply line layer; second internal pads (54) formed on the substrate and connected to the second power supply line layer, the number of second internal pads (54) being less than the number of first internal pads (46); a package (61) on which the substrate is mounted; and a plurality of first external pads (65) formed on the package and at the peripheral area of the substrate, the first external pads being connected to the first internal pads (46) through respective conductors. For each second internal pad (54), a second external pad (63) is formed on the package and at the peripheral area of the substrate, each second external pad being connected to a second internal pad (54) through a conductor and, also being connected to an external terminal lead. At least one third internal pad (55) is formed on the substrate and connected to the second power supply line layer. For each third internal pad (55), a third external pad (62) is formed on the package and at the peripheral area of the substrate, the third external pad being connected to the third internal pad through a conductor but having no connection to an external lead; and an electroconductive layer (64) is formed over a substantial portion of the interface between the substrate and the surface of the package, the electroconductive layer (64) extending to and being connected to the second and the third external pads (63,62), thereby removing the need for an additional external terminal lead for the third external pad (62).

Description: The present invention relates to a semi-conductor circuit and in particular to the supply voltages for such a circuit. Usually, a semi-conductor integrated circuit has two electric supply voltage systems, a high voltage side designated V cc and a low voltage side designated V EE . As the scale of the circuit becomes larger the electric power dissipation increases. Even in the case of the electric supply on the low-voltage side, the supply voltage may differ from point to point, and this difference cannot be ignored in some types of circuits. The object of the present invention is to reduce inequalities in a given supply voltage at different points of the circuit. A semiconductor integrated circuit according to the present invention comprises a semiconductor substrate in which integrated circuits are formed and on which a first power supply line layer and a second power supply line layer are formed; a plurality of first internal pads formed on the substrate and connected to the first power supply line layer; second internal pads formed on the substrate and connected to the second power supply line layer, the number of second internal pads being less than the number of first internal pads; a package on which the substrate is mounted; a plurality of first external pads formed on the package and around the peripheral area of the substrate, the first external pads being connected to the first internal pads through respective conductors; for each second internal pad, a second external pad formed on the package and at the peripheral area of the substrate, each second external pad being connected to a second internal pad through a conductor and, each of said first and second external pads, also being connected to an external terminal lead; and characterised by at least one third internal pad formed on the substrate and connected to the second power supply line layer; for each third internal pad, a third external pad formed on the package and around the peripheral area of the substrate, the third external pad being connected to the third internal pad through a conductor but having no connection to an external lead; and an electroconductive layer formed over a substantial portion of the interface between the substrate and the surface of the package, the electroconductive layer extending to and being connected to the second and the third external pads, thereby removing the need for an additional external terminal lead for the third external pad. The provision of the third internal pad or pads connected to the second power supply line layer in combination with the provision of the electroconductive layer greatly reduces voltage differences at different points in the second power supply layer. In order that the invention may be better understood, an embodiment of the invention will now be described with reference to the accompanying drawings in which:- Figure 1 is a diagram of the layout of an electric source system in a conventional LSI circuit; Figure 2 is an equivalent circuit of an ECL gate used as an internal gate of a gate array; and Figure 3 and 4 are diagrams of the layout of the electric source system according to the present invention. Figure 1 is a layout of an electric supply system of an LSI circuit as known, for example, from Review of the Electrical Communication Laboratories, Vol.26,(9/10), September-October 1978, p.1355-1366. In Fig. 1, 10 denotes an IC chip, 45 denotes a wiring pattern on the V CC side, and 50, 51, 52 denote wiring patterns on the V EE side. Wiring patterns 45, 50, 51 are formed by a first wiring layer of aluminium. A plurality of basic cells (not shown in the drawings) which have, for example, a gate circuit as shown in Fig. 2 are also formed in the IC chip 10. On the other hand , the wiring pattern 52 is formed in a transverse direction by a second wiring layer of aluminium so that it crosses the first layer and is connected to the first-layer wiring patterns 50, 51 of the V EE supply at their crossing or meeting points, as shown by dots 53 in Figure 1. The first-layer wiring pattern 45 on the V CC side is provided with six bonding pads 46 around its periphery. However, on the V EE side, only two bonding pads 54 are provided for the wiring pattern. The longitudinal wiring patterns 50, 51 on the V EE side are independent, and, as mentioned above, points thereof are connected to another wiring pattern extending in a transverse direction. However, because the longitudinal patterns 50, 51 have only the two pads 54 the electric source voltage V EE varies from point to point in the chip. This variation, which becomes more evident as the circuit scale becomes larger and the electric power dissipation increases, cannot be ignored in some types of circuits. For example, in the ECL gate shown in Fig. 2, Q₁, Q₂ are transistors for forming a current switch, Q₃ is a transistor for a constant-current source, and Q₄, Q₅ are transistors connected as emitter followers for the output stage. A base voltage V R of the transistor Q₃ for a constant current source is set with respect to the V EE side. However, if V EE is different, the constant current becomes different so that the output voltage becomes different. To compensate for this, the value of the emitter resistor may be changed. However, it is very troublesome and impractical to change the value of each emitter resistor according to the position of the gate. Figure 3 is a layout of the chip according to one embodiment of the present invention. The symbols used in Fig. 1 are used for the same portions in Fig. 3. The feature of the present invention in the embodiment shown in Fig. 3 is that pads 55 for the V EE supply are added in four corners and the end members of the wiring pattern 52 of the second layer are extended thereto. By using such a construction, six bonding pads are formed on the V EE side similar to those on the V CC side. Therefore, the internal source voltage can be equalized. However, it would be undesirable for the number of external terminals of the package to be increased by such a construction. Therefore, in the present invention, as is shown in Fig. 4, the pads 62 on the package 61 to which the pads 55 are connected via a bonding wire 60 are different from the pads 63 corresponding to the pads 54 in that the pads 62 are not connected to the external terminal. Instead pads 62, as well as pads 63, are connected to an electro-conductive layer 64 positioned in the bottom of the package 61. The layer 64 will usually be of aluminium. Alternatively, if the package 61 is formed from a multilayer ceramic, each layer has a wiring pattern, and these wiring patterns are connected via throughholes. In such a case, pads 62, 63 are also connected to the electro-conductive layer 64 via throughholes. In such a construction, the electro-conductive layer 64 is usually formed from gold, which has a lower resistivity than aluminium; or, if the layer 64 is not formed from gold the electro-conductive layer is wide and has a low resistance. It will be seen that the provision of the layer 64, to which pads 62 and 63 are connected, is equivalent to extending the pads 62 to the exterior of the package. Reference 65 indicates pads for connecting each pad 46 for the V CC supply to an external lead.

Claims: A semiconductor integrated circuit device comprising: a semiconductor substrate in which integrated circuits are formed and on which a first power supply line layer (45,V CC ) and a second power supply line layer (50,51,52,V EE ) are formed; a plurality of first internal pads (46) formed on the substrate and connected to the first power supply line layer; second internal pads (54) formed on the substrate and connected to the second power supply line layer, the number of second internal pads (54) being less than the number of first internal pads (46); a package (61) on which the substrate is mounted; a plurality of first external pads (65) formed on the package and around the peripheral area of the substrate, the first external pads being connected to the first internal pads (46) through respective conductors; for each second internal pad (54), a second external pad (63) formed on the package and at the peripheral area of the substrate, each second external pad being connected to a second internal pad (54) through a conductor and, each of said first and second external pads also being connected to an external terminal lead; and characterised by at least one third internal pad (55) formed on the substrate and connected to the second power supply line layer; for each third internal pad (55), a third external pad (62) formed on the package and around the peripheral area of the substrate, the third external pad being connected to the third interral pad through a conductor but having no connection to an external lead; and an electroconductive layer (64) formed over a substantial portion of the interface between the substrate and the surface of the package, the electroconductive layer (64) extending to and being connected to the second and the third external pads (63,62), thereby removing the need for an additional external terminal lead for the third external pad (62). An integrated circuit device according to the claim 1, wherein the substrate is of rectangular shape, and two second internal pads (54) are provided at intermediate points on opposite sides of the substrate; and in which third internal pads (55) are formed adjacent the four corners of the substrate.

Inventors: NATSUME MITSUAKI, SAITO TOSHIHARU, SUGIYAMA EIJI, NATSUME, MITSUAKI, SAITO, TOSHIHARU, SUGIYAMA, EIJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1983
Main classification: H01L27
IPC codes: H03K19, H01L27