SEMICONDUCTOR DEVICE WITH A MULTILAYER STRUCTURE

Abstract: A semiconductor device has a substrate (1, 2) provided with a mesa region (11), wherein an insulation film (6) is provided in regions other than the mesa region (11), and a polycrystalline silicon layer (10-1) and a metal silicide layer (10-2) are formed over said insulation film (6), this multilayer structure consisting of a take-out portion for at least one of the emitter (4-1), base (4-3), and collector (4-2) members of a bipolar transistor provided in the mesa region (11).

Description: SEMICONDUCTOR DEVICE Background of the Invention This invention relates to a semiconductor device, and more particularly to a semiconductor device including a bipolar transistor. The switching speed and power dissipation of a semiconductor device, which are the basic standards for indicating its performance, are determined by the value of the current in the transistor employed therein, and by the electrostatic capacitance of the elements, including parasitic elements, whose charge and discharge must be made with this current. It is desirable that the value of this capacitance is as small as possible, because the power required to operate the transistor is proportional to the capacitance for a given current. In addition, the capacitance must be reduced in order to increase the switching speed of the transistor, because the RC time constant of the transistor is proportional to the capacitance for a given sheet resistance. Some of the present inventors have developed a semiconductor device including a bipolar transistor, etc., whose power dissipation is small, which operates at a high speed, and wherein the elements occupy a small area, by isolating the active region, etc., of the semiconductor from the substrate thereof by an insulation film, thereby reducing a parasitic capacitance, and they have already filed a patent application therefor (Japanese Patent Laid Open No. 1556/1981 and US Patent Application No. 158366). Figure 1 is a section through the structure of one example of this semiconductor device. The following is a description thereof, the material of each part and the conductivity types of the semiconductor layers are prescribed (the first conductivity type is taken to be n-type and the second conductivity type to be p-type) therein so as to simplify the explanation. This also applies to the description of the present invention below, needless to say the materials and conductivity types are not limited thereto. In Figure 1, numeral 1 denotes an Si substrate of p-type conductivity, 2 a buried layer of n -type conductivity, and 3, 4 and 5 epitaxially-grown Si layers of which 3 is an n-type conductivity region, 4 a p-type conductivity region, and 5 an n+-type conductivity region. Each of these regions is formed by the doping of impurities. Numeral 6 denotes an insulation film,,7 a polycrystalline semiconductor layer, 8 an insulation film, and 9 an electrode. Numeral (I) denotes a lateral bipolar transistor wherein the electrodes of the emitter and collector regions 4 1 and 4 2 are taken out through the polycrystalline semiconductor layer 7 between the insulation films 6 and 8. Numeral (II) denotes a longitudinal bipolar transistor wherein the electrodes of base regions (an intrinsic base region 4 3 and a graft base region 4 4) are also taken out through the polycrystalline semiconductor layer 7 between the insulation films 6 and 8. The structure of the transistors shown in Figure 1 has the advantages that it enables highspeed operation because of their small parasitic capacitance, and that it also enables a reduction of the area of the elements. However, the resistance thereof is not reduced, since the take-out electrodes from the active region formed of a monocrystalline layer are constituted by the poly crystalline semiconductor layer 7. Accordingly, although the time constant, expressed as the product of the resistance and the capacitance, is reduced only by the effect of the reduction of the parasitic capacitance, the realization of high-speed operation is hindered in a circuit wherein a number of multi-emitter structures are used, since the speed of operation is determined by the time constant of the slowest emitter. This is because the time constant of each emitter is affected by the resistance of the polycrystalline semiconductor layer. Monocrystalline p-type conductivity regions 4 (4 1' 4 2 and 4 4) in contact with the poly- crystalline semiconductor layer 7 are formed by the diffusion of the p-type impurities from the polycrystalline semiconductor layer 7. That is, the p-type graft base region 4 4 is formed by diffusion from an unstable polycrystalline semiconductor region with a different diffusion constant, due to differences in the process conditions. This makes it difficult to control the depth of the graft base, and thus it has been difficult to manufacture an element with an emitter (n -type region 5) of a small area. Summary of the Invention An object of the present invention is to provide an improvement in the type of semiconductor device shown in Figure 1. That is, it is an object of this invention to provide a semiconductor device with a higher switching speed. In order to achieve this object in accordance with the semiconductor device of the present invention, an extrinsic layer in contact with an active region is provided so as to reduce the resistivity. In this invention, the extrinsic layer includes a metal layer and/or a metal silicide layer. A second object of this invention is to provide a method of producing the improved semiconductor device described above. According to the method provided by this invention, a layer selected from a metal layer and/or a metal silicide layer is disposed on an extrinsic semiconductor layer. Brief Description of the Drawings Figure 1 is a section through the structure of one example of a semiconductor device according to US Patent Application No. 158,366; Figure 2 is a section through the structure of a first embodiment of the present invention; Figures 3A to 3F are sections through the structure of the semiconductor device of Fig. 2, illustrating the sequence of the manufacture of the device; Figures 4A to 4D are sections through the structure of a second embodiment of the semiconductor device of the present invention, illustrating the sequence of the manufacture thereof; Figure 5 is a section through the structure of a third embodiment of the semiconductor device of the present invention; and Figure 6 is a section through the structure of a fourth embodiment of the semiconductor device of the present invention. Description of the Preferred Embodiments This invention will be described in detail hereunder with reference to the embodiments thereof. Embodiment 1: Figure 2 is a section through the structure of a first embodiment of the semiconductor of the present invention. In this figure, the same numbers as those used i#n Fig. 1 denote the same parts, or equivalent parts, as those in Fig. 1. In a bipolar transistor of the present invention, illustrated by a first embodiment thereof, electrodes 10 (10 1 and 10 2) taken out from monocrystalline regions (p-type regions 4 1 to 4 4) form a double-layer structure to reduce the resistance thereof. The electrodes 10 1 and 10 have a double-layer structure formed, for instance, of a polycrystalline semiconductor (a polycrystalline silicon layer) as one layer, and a metal (e.g. a refractory metal layer) or a metal silicide as the other. Electrodes 10 1 and 10 2 taken out from -l 2 base regions (4 3 and 4 4) are isolated from an emitter region (n+-type region 5) by an oxide film (insulation film 8), the base and emitter regions can also be formed by a self-alignment method. The following is a description of a method of manufacturing the semiconductor device of the present invention. Figures 3A to 3F illustrate the process of manufacturing the semiconductor device shown in Fig. 2. The main process steps thereof will be described hereunder in the order of figure number. (3A): An n -type buried layer 2 is formed in a p-type Si substrate 1 by diffusion of impurities, an n-type Si layer 11 is grown epitaxially thereon, a silicon oxide film 12, a silicon nitride film (Si3N4) 13, and another silicon oxide film 14 are formed over the whole surface in that order, and then these three layers are removed by etching except for the parts that will form the active regions of the transistors. Next, the epitaxial layer 11 is also etched, as shown in the figure, to form mesa regions. (3B): After the Si epitaxial layer 11 under the silicon oxide film 12 is side-etched by wet etching silicon oxide film 15-ts formed by the thermal oxidation. A silicon nitride film 16 and a silicon Oxide film 17 are then deposited in that order, and the oxide film 17 is etched so that it remains only in the region wherein the collector electrode of the longitudinal transistor will be formed. The nitride film 16 is then etched by reactive sputter etching so that it is left only on the sidewalls of the Si epitaxial layer 11, and in the region wherein the collector electrode will be formed. (3C): An oxide film 6 is formed by thermal oxidation, the nitride film 16 and the oxide film 15 are removed, and a p-type region 4 is formed by the thermal diffusion of impurities. (3D): A polycrystalline silicon film 18 and a film 19 of a refractory metal or a metal silicide (e.g. molybdenum silicide, tungsten silicide, palladium silicide, nickel silicide, etc.,) are deposited. When the film 19 is formed of a refractory metal, it is made into the silicide together with the polycrystalline silicon film 18, and is formed into one body therewith, by annealing later. The polycrystalline silicon film 18 is lightly doped to be p-type. Next, a photoresist film (e.g. KTFR of Kodak Company) 20 is applied, and the areas covering the mesa regions are etched so that they are slightly broader than the mesas. A coating of a photoresist (e.g. AZ135CU of Hexit Co.,Ltd. or Nicpcposit 1300 of Shipley Co. r Ltd.) 21 is then applied so that it penetrates the spaces between the mesa regions (the mesas of the Si epitaxial layer 11) and the photoresist film 20, and also covers their upper surfaces. Therefore these surfaces are flat after the coating. Next, the photoresist is etched in an 0 2 atmosphere, the etching is stopped when the metal silicide film 19 on the mesa regions is exposed. The layers of the metal silicide film 19 and the polycrystalline silicon film 18 are then removed by a plasma etching method in such a way that only the metal silicide film 19 and the polycrystalline silicon film 18 located on the top surfaces of the mesa regions are removed, so that the silicon oxide film 14 is exposed. (3E): After the removal of the photoresists, the oxide film 14 is removed, and oxidation is used to form an insulation film 8. Next the nitride film 13 is removed. A base region (p-type region 4 is formed thereafter by a method such as ion implantation. (3F): A passivation silicon nitride film 22 is deposited, a hole is made which will form the emitter region, emitter impurities are added, and thereby the emitter region (n+ region 5) is formed. After that, an electrode 9 for each region is formed. The semiconductor device of the present invention is formed by the above process. The graft base region 4 4 in the semiconductor device of the present invention can be formed very accurately, since it is not formed by the diffusion of impurities from the polycrystalline silicon film 18. In addition, high-speed operation is enabled, since electrodes taken out from an active region formed by monocrystalline layers have a two-layer structure of a polycrystalline silicon film 18 and a metal silicide film 19 which enables a reduction of the resistance. Embodiment 2: Figures 4A to 4D illustrate the process of manufacturing a second embodiment of the semiconductor device of the present invention. Figure 4D is a section through the structure of a completed semiconductor device of the present invention. Initially, the same process steps as those for the first embodiment shown in Figs. 3A, 3B and 3C are followed, the process continues from that shown in Fig. 4A. The following is a description of the process steps with reference to Figs. 4A to 4D. (it): The polycrystalline silicon film 18 is deposited and doped slightly to be p-type. Next, only the polycrystalline silicon on the mesa regions is removed in the same way as in the first embodiment, and then the polycrystalline silicon film 18 is etched by a conventional photoetching process. After that, the oxide film 14 is etched, and then the film 19 of a refractory metal such as tungsten, molybdenum, palladium, nickel, etc., is deposited. (4B): The polycrystalline silicon film 18 and the refractory metal film 19 are made to react with each other by annealing, so that a layer of metal silicide is formed only on the polycrystalline silicon film 18 and the regions around it. The annealing temperature depends upon the kind of refractory metal, the deposition method, and the annealing gas. When the refractory metal film is formed of tungsten deposited by a sputtering method and the annealing gas is hydrogen, for instance, an annealing temperature of between 6000C to 900 C is suitable. When the annealing temperature is less than 600 C, the growth rate of the metal silicide is very low, and when it is more than 9000C, the growth rate of the metal silicide layer is extremely high, which results in the formation of the metal- silicide layer even in regions some distance from the polycrystalline silicon film 18. This could cause short-circuits, via the metal silicide, between the parts of the pattern of the polycrystalline silicon film 18. In this annealing process, the annealing conditions are set so that some of the metal silicide layer also grows in the peripheral regions around the polycrystalline silicon film 18. This means that a metal silicide layer 23 is formed around the periphery of the silicon nitride film 13 on the mesa regions. (4C): The refractory metal film 19 is removed by etching (the un-reacted refractory metal film can be left as it is on the metal silicide layer 23), and a silicon oxide filni 24 is formed over the metal silicide layer 23 by a oxidation process or a deposition method. The silicon nitride film 13 is then removed by using the oxide film 24 as a mask, and the base region 4 3 is formed by a conventional ion implantation method. During this process step, the collector electrode regions of the lateral transistor region (I) and the longitudinal transistor region (II) are covered with a photoresist to prevent the implantation of ions therein. (4D): A passivation silicon nitride film 25 is deposited, and a hole is made in the emitter region in the region 4 3. The hole in the emitter region is made so that the part of the oxide film 12 not covered with the nitride film 13 is completely exposed. For this purpose, the etched edges of the nitride film 25 are formed so as to be positioned over the oxide film 24. The emitter region (n+-type region 5) is formed thereafter by ion implantation, and the silicon nitride film 25 and the oxide films 24 and 12 are etched by a conventional photoetching process to form a base contact hole 26 and a collector contact hole 27, and electrodes 9 are then formed. The process steps described above complete the semiconductor device of the second embodiment of the present invention. In this embodiment, the layers of the polycrystalline silicon film 18 for the base electrodes and the metal silicide film 23 (equivalent to 10 1 and 10 in Fig. 2) are isolated from the emitter region 5 by the oxide film 24 and the silicon nitrode film 13, and thus the base elec trodes and the emitter region can be formed so as to be self-aligning. Although the base electrodes are also isolated from the emitter region in a self-aligning manner in the first embodiment, they are isolated from each other in that embodiment by the oxide grown below the silicon nitride film 13. This oxide grown below the silicon nitride film is a called a bird beak. Its growth depends upon the oxidation conditions, the thickness of the silicon oxide film 12, the thickness of the silicon nitride film 13, etc., and it is somewhat-inferior to that in the second embodiment in terms of the control of the quantity of growth. Embodiment 3: Figure 5 is section through the structure of a third embodiment of the semiconductor device of the present invention. After the process steps followed in the same sequence as in the first embodiment as far as Fig. 3C, the polycrystalline silicon film 18 which is lightly doped to be p-type is deposited. Next, only the polycrystalline silicon on the mesa regions is removed in the same way as shown in the first embodiment, the metal silicide film 19 is deposited, and only the metal silicide on the mesa regions is removed. After that, the photoetching process, oxidation, etc., of Fig. 3 (e) are applied in the same way as in the first embodiment, the emitter region 5 is then formed, and the electrodes 9 are formed. This completes the semiconductor device shown in Fig. 5. In the present embodiment, part of the side surfaces of the monocrystalline mesa regions are in contact with the metal silicide film 19. Therefore, a lower contact resistance than that of the first embodiment can be obtained. Embodiment 4: Figure 6 is a section through the structure of a fourth embodiment of the semiconductor of the present invention. The semiconductor device of this embodiment has a higher performance than that of Figure 5. This is because an oxide film (insulation film 8) on the metal silicide is formed thickly around the n -type region 5 so that the p-type high-density region (4 4) and the n-type high-density region (5) are not in direct contact with each other. Therefore the capacitance which strongly affects the high-speed operation of the elements is reduced, while the space between the emitter and the graft base is increased, and thus high-speed elements can be manufactured with an excellent yield. The figure shows the state wherein the take-out electrode 10 constituted in two layers is made into one body by a subsequent annealing processes. As described above, the present invention enables a reduction in the sheet resistance of the electrodes, which, in turn, enables the high-speed, low-power operation of the element. The following is a concrete example of the effects thereof. In a conventional semiconductor device (shown in Fig. 1), the sheet resistance of the electrodes is about 170 fl/Ej, since polycrystalline silicon is used for base electrodes. On the other hand, the sheet resistance of the electrodes of the device of the present invention, using a metal silicide, is about 10 Q/O , that is a reduction of one order of magnitude from that of the conventional device. Accordingly, when a comparison is made between I2L elements with four collectors, for instance, prepared both by a conventional method and by the method of the present invention, the propagation delay time (tpd min) of the element of the convex tional method is 2500 ps, while that of the element according to the present invention is 500 ps. This large improvement makes it possible to manufacture a PLA (Programmable Logic Array) formed of I Ls with at least four collectors, which has been impossible so far. The effects of the present invention are not changed even when the p-type and n-type conductivities are swapped in the structure proposed by the present invention. In addition, when a reverse-operation bipolar transistor is used as the transistor (II) (numeral 5 denotes the collector and 11 the emitter in this case) in the constitution of the semiconductor device shown in Figures 2, 3F, 4D, 5 and 6, the device has the strucutre of an I 2L (Integrated Injection Logic) device.

Claims: CLAIMS: 1. A semiconductor device characterised by a semiconductor substrate (1, 2) with a mesa region of a first conductivity type; an insulation film (6) provided over the portions other than the mesa region of said substrate (1, 2); a first region (18) of a semiconductor layer of a second conductivity type which is provided over said insulation film (6) in contact with said mesa region; a second region (19, 23) of metal silicide provided over said first region (18); a third region (4) of said second conductivity type in contact with said first region (18) and provided on the mesa region of said substrate; and a fourth region of an insulation film (8) provided over a region in contact with said first (18) and/or second (19, 23) regions and with the third region (4) of said substrate. 2. A semiconductor device according to claim 1, wherein said second metal. silicide region (19, 23) is of a compound formed from said first region (18) and a metal film and formed into one body with said first region (18). 3. A semiconductor device according to claim 2, wherein the surface regions of the mesa region of said substrate have a fifth region of a semiconductor layer of said second conductivity type. 4. A semiconductor device according to claim 3, wherein the fifth region provided over the surface regions of the mesa region of said substrate has a sixth region of said first conductivity type thereon. 5. A semiconductor device comprising: a semiconductor body (1, 2) of a single crystal having a first convex portion (11) of a first conductivity type; an insulation film (6) having a first opening formed on a surface of said body (1, 2) other than said first convex portion (11); a first polycrystalline semiconductor layer (18) of a second conductivity type opposite to said first conductivity type formed on said first convex portion and on said insulation layer (6); a first metal silicide layer formed on said first polycrystalline semiconductor layer; and a first region (4) of said second conductivity type formed in said first convex portion (11) in contact with said first polycrystalline semiconductor layer (18). 6. A semiconductor device according to claim 5, further comprising a second region (5) of said first conductivity type formed in said first region and a third region (3, 11) of said first conductivity type formed in said body under said first convex portion (11), said third region (3, 11) serving as a collector region, said first region (4- 3) serving as a base region and said second region (5) serving as an emitter region to form a bipolar transistor (II). 7. A semiconductor device according to claim 6, further comprising a collector electrode (9) formed on said third region (3, 11), a base electrode (9) formed on said polycrystalline semiconductor layer (18), and an emitter electrode (9) formed on said second region (5). 8. A semiconductor device according to claim 7, wherein. said insulation film (6) has a second opening (27) at another position on said third region (2, 11), and said collector electrode (9) is formed in said second opening (27). 9. A semiconductor device according to claim 7, further comprising a high impurity concentration region (2) of said first conductivity type formed in said third region, said collector electrode (9) being formed on said high impurity concentration region (2). 10. A semiconductor device according to claim 6, wherein said first polycrystalline semiconductor layer (18) serves as an extrinsic base region. 11. A semiconductor device according to claim 5, wherein said first region (4) includes a pair of emitter and collector regions (4-1, 4-2) spaced from each other, and said first convex portion (11) between said emitter and collector regions serves as a base region, to form a lateral bipolar transistor (I). 12. A semiconductor device according to claim 5, wherein said first region (4-3) serves as a base region, a collector region (5) of said first conductivity type is formed in said base region (4-3), and an. emitter region (3, 11) of said first conductivity type is formed in said body under said first convex portion, to form an inverse bipolar transistor (II). 13. A semiconductor device according to claim 12, wherein said insulation film (6) has a second opening, a second convex portion (11) of said first conductivity type is provided in said second opening, and a pair of emitter and collector regions (4-1, 4-2) of said second conductivity type is formed in said second convex portion (11) spaced from each other, to form a lateral bipolar transistor (I). 14. A semiconductor device according to claim 13, wherein said first polycrystalline semiconductor layer (18) keeps said base region (4-3) of the inverse bipolar transistor (II) in contact with said collector region (4-2) of the lateral bipolar transistor (I), and said emitter region (2, 3) of the inverse bipolar transistor (II) extends under said second convex portion (11), to form an integrated injection logic. 15. A semiconductor device according to claim 14, wherein a second polycrystalline semiconductor layer (18) of said second conductivity type is formed in contact with said emitter region (4-1) of the lateral bipolar transistor (I) on said insulation layer, and a second metal silicide layer (19, 23) is formed on said second polycrystalline semiconductor layer (18). 16. A method of manufacturing a semiconductor device comprising: forming a semiconductor body (1, 2) of a single crystal having a first convex portion (11) of a first conductivity type; forming an insulation film (6) on a surface of said body, said insulation film including a first opening over said first convex portion (11); exposing a surface of said convex portion (11); depositing a first polycrystalline semiconductor layer (18) of a second conductivity type opposite to said first conductivity type on said first convex portion (11) and on said insulation film (6); depositing at least one layer (19) selected from a metal layer and a metal silicide layer on said first polycrystalline semiconductor layer (18); annealing said layers (18, 19) deposited on said insulation film (6); and forming a first region (4) of said second conductivity type in said first convex portion (11) in contact with said first polycrystalline semiconductor layer (18).

Inventors: MIYAZAKI, TAKAO, NAGATA, MINORU, NAKAMURA, THORU, NAKAZATO, KAZUO, OGIRIMA, MASAHIKO, SUGAKI, SHOJIRO, YAMAMOTO, NAOKI
Applicants: HITACHI, LTD.
Application year: 1983
Main classification: H01L23
IPC codes: H01L29, H01L23, H01L21