ACCESS CONTROL PROCESSING SYSTEM IN COMPUTER SYSTEM

Abstract: This invention relates to a system for processing access requests issued from plurality of access requesting units to a storage. Particularly, in such a storage system where the buffer storage BS and main storage MS are provided, access is first made to BS based on the access request and when the desired data is not found in BS, access is made to MS. When there is no request data accessed from the access requesting unit and acces is then made to MS, access to BS is carried out based on the next access request from the same access requesting unit in parallel with said access to MS.

Description: Access Control Processing System in Computer System This invention relates to an access request control system when one or more access requesting units in the computer system makes an access to a memory, in more details, to a memory comprising a high speed small capacity buffer storage (BS) and low speed large capacity main storage (MS). An access to storage has been made by the following steps that an access request information from each access requesting unit is once set to a corresponding register and when plural requests compete, any one of access request is selected in accordance with an adequate priority and BS is first accessed depending on such information. If BS has no desired data, MS is accessed. For the access to MS, a considerably long time is required as compared with an access to BS. Existingly, the access request is held in above register until MS is accessed and the unit can not issue the next access request during such waiting period. Therefore, even when the next access request data exists in BS, such data in BS can not be accessed until the preceding MS is accessed, and accordingly efficiency becomes bad. It is an object of this invention to improve above disadvantage, and in more practical, to make possible an access to BS in regard to the next access request from the same access requesting unit even while an access is requested to MS from said access requesting unit. For this purpose, in this invention, an access request information is transferred to a register for access to MS in such a stage that the MS access becomes necessary and the register for access to BS is released. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram indicating an embodiment of this invention. Fig. 2 is a detail schematic diagram of the priority determination circuit of BS shown in Fig. 1. Fig. 3 is a detail schematic diagram of the priority determination circuit of MS shown in Fig. 1. Fig. 1 is a block diagram of an embodiment of this invention. ACCO ¯ ACCn are respectively access requesting units. ACCOR t- ACCnR are respectively corresponding BS access registers. LBCR is a loop back register. Each access is selected in the BS priority determination circuit (BP) and is then accessed to BS. If there is no request operand in BS, the access request information is set to the MS access registers MSOR ¯ MSmR by means of the BSNF (BS not found) signal. Here, the MSOR ¯ MSmR may be the registers in number of m+l common to the access requesting unit or may be plural registers corresponding to each access requesting unit (one or more register may correspond to one access requesting unit). When an access is set to MSOR ¯ MSmR, the BS access register of the corresponding access requesting unit is released and becomes ready for accepting the next access. The access set to MSOR ¯ MSmR is selected again by the MS priority determination circuit and then accessed to i.#. On the other hand, ACCOR r-- ACCnR are accessed to BS in accordance with the priority considering a newly accepted access. In case MSOR ¯ MSmR are used in common by the access requesting units, if MSOR ¯ MSmR become busy, the access encountered by BSNF during the BS access is nullified until one or more MS registers becomes vacant. In case the MS register is placed in the waiting condition corresponding to each access requesting unit, it is nullified until the corresponding MS register becomes vacant. In this figure, RO ¯ R4 are registers forming the pipe line. BD is a read data register of BS. WD is a write data register of BS. MD is a read data register of MS. DO, DI are data registers. SEL is a selector. MRG is a merge circuit to be used at the time of partial write. The operations in relation to BS is already known and is not related directly to this invention. Therefore these operations are not described in this specification. Detail of the BS priority determination circuit BP is described by referring to Fig. 2 and the MS priority determination circuit MP and its control LOGIC are also described by referring to Fig. 3. Fig. 2 is a detail block diagram of the BS priority determination circuit BP. In this example, the access units comprise two CPU's (CPU0, CPU1), one unit of CHP(CHP0) and BS is composed of four banks. An access from CHPO is explained first. An access from CHPO is set to the registers CHPOV, CHPOAD, CHPOR corresponding to ACCOR in Fig. 1. CHPOV sets the effective signal of access, CHPOAD sets a part of address for checking busy condition of BS bank and CHPOR sets instruction code and address. When an access is set, contents of CHP0AD is decoded and busy check of pertinent bank is carried out. HOACPD is a signal indicating that an access already set to the port is already selected by the priority determination circuit and executed and when this signal once becomes "1", an access does not again take part in the priority determination circuit. An access for which the bank to be used is not busy and HOACPD signal is "0" takes part in the priority determination circuit. In this example, the access which takes part in the priority determination circuit includes the LB access (loop back access, mainly an access processing for data from MSU), CHP0 access, CPU0 access and CPU1 access which are described later. The priority is fixed in the sequence indicated below. LE > CHP0 > CPU0 > CPU1 Request from the loop back LB is selected first without any conditions. Request from CHP0 is selected under the condition that there is no request from LB. Request from CPU0 is selected under the condition that there is no request from LB and CHP0. Request from CPU1 is selected under the condition that there is no request from LB, CHP0, CPUO. When an access request is selected by the priority determination circuit, HOACPD is set to "1" and such request information is input to the register RO of the first stage of the pipe line. The information set to RO includes RQV indicating validity of access, OPCODE indicating operation, RQTR indicating access requesting unit and ADDRESS indicating access operand. As described later, an access request once selected is sometimes nullified during execution and in this case the HOACPD is dropped by the CHPONULL signal and thereafter it can take part again in the priority determination. Where there is no fear of possibility of nullification, -the port may be opened and therefore in such a case the set clock SCLK is given to the port register by the CHPORESET signal and HOACPD is dropped. When the set clock SCLK is given to the port register, the next access is set to the port. If there is no next request, the valid signal CHPOV remains OFF and therefore any operation does not occur. The same operations are carried out also for the CPU0, CPU1. In the figure, A is an AND gate, OR is an OR gate. An access request input to the pipe line makes an access to BS (buffer storage) with its address. When there is no request operand in BS, such access is set to MSPOR#T (MSU access port) for the access to MSU. Fig. 3 is the control circuit LOGIC to this MSPORT and priority determination circuit MP to MSU. An access set to Ro is shifted to R1. At this time, when BSNF (not found) signal is sent from BS, the setting LOGIC to MSPORT is started. In this example, two MSPORT's are used. The OPCODE is decoded and the MEMACC signal which indicates whether such access is made to MEM or not is generated. RQTR is also decoded and the CHP and CHP signal are generated. Here, when the signal sent from operation status register PPSR is "0", the CHP access is first set to MP1 and if MP1 is busy, it is set to MPO. The CHP access is first set to MP0 and if MPO is busy, it is set to MP1. If these are all busy, the NULL signal is generated for both accesses and this access is nullified. This NULL signal is ANDed with the RQV signal sent from Rl to R2, making RQV "0" and is also sent to the second acceptance port as the CHPONULL signal. Thereby the port is initialized and thereby it can take part again in priority determination. When desired data is found in BS or not found and an access request is accepted by MSPORT, the port is released by the CHPORESET signal and the next access is accepted. OPSR may be those to be set to a constant value at the time of IPL (Initial Program Loading) of computer system or to be set when an over run occurs from CHP due to the buffer condition in the channel. When OPSR is "1", the accesses from CHP are set in the sequence of MP1, MP2 as in the above case, but the access from CHP is set from MPO. If MPO is already set, the NULL signal is always generated by the NULL signal generation theory and access is nullified. This control causes MPO to be used in common by CHP access, CHP access, while MP1 is not used for CPU access but only for CHP access. The accesses set to MSPORT are selected in accordance with priority and then output to MSU. The addresses set to MSPORT is compared with the bits determined by interleave of MSU and thereby busy check of MSU is carried out. MPOV, MP1V are effective signals of MSPORT and when these are "1", MSPORT is busy. CTR0V, CTR1V are signals which are set when accesses to MSPORT are selected in accordance with priority and then sent to MSU. These indicate that access is already sent to MSU and counter COUNT is effective. When an access is set to MSPORT, busy check of MSU is carried out. It is judged as follow. Namely, when there is an access sent to MSU, the MSU bank to which an access is requested when the addresses of MSPORT are compared with the comparison circuit COMP and they match is busy. A result of busy check is OK and the effective signal of counter is "0", such access is input to the priority determination circuit. Priority is judged by the MP0HIGH signal which is inverted in synchronization with the clock. When MP0HIGH is "0", priority of access request of MP1V is high, and when it is Illir, priority of access request of MP0V high. When any access request is selected by the MSU priority determination circuit, an address of corresponding access request is selected and sent to MSU. Simultaneously, corresponding counter is started. The counter counts up in synchronization with the clock. When the counter value reaches a specified value, MPORSEL, MPlRSEL are generated by the decoder DEC, and OPCODE, RQTR, ADDRESS etc. are selected. Thereby such signals are sent to the LB port of the BS priority determination circuit (Fig. 2). The RESET signal is generated by a value of counter in such a timing that the data processing from MSU terminates, and MPOV, MP1V, CTROV, CTR1V are reset and thereby MSPORT is released. According to this invention, priority determination for BS access and that for MS access are isolated individually and the input port registers are also provided individually. Thereby each access source can issue the next BS access while MS access is being carried out. Only two Ms ports are provided for three access requesting units and they are used in common, and the particular port can also be used only for a particular access requesting unit as required. Accordingly, adequate priority can be determined in accordance with emergency of processings at the access requesting unit.

Claims: CLAIMS 1. An access control processing system in a computer system wherein a buffer storage (BS), main storage (MS) and one or more access requesting units are provided, and if there is no data-requested from said access requesting unit in said buffer storage, access is made to the main storage, characterized in that; the registers for holding the requests from respective access units for access to the buffer storage and for access to the main storage and the priority determination circuits for the buffer storage and for main storage are provided and accesses are carried out in accordance with priority determined independently. 2. An access control processing system in a computer system providing plurality of access requesting units, plurality of common registers for holding access requests from said access requesting units and a priority determination circuit which determines priority between the access requests from said access requesting units being held by said common registers, characterized in that; a setting means, which sets at least any one of said common registers as an exclusive register which holds only access requests from a particular access requesting unit, is also provided. 3. The access control processing system according to claim 1, wherein the access request holding registers for access to said main storage in such a number as less than the number of access requesting units are provided for common use by plurality of access requesting units, and a means, which receives the specified signals and controls andu one of said registers so that only the access request information sent from the specified access requesting unit is set thereto, is also provided.

Inventors: HATTORI, AKIRA C/O FUJITSU LIMITED, KOSHINO, MINORU C/O FUJITSU LIMITED, NISHIDA, HIDEHIKO C/O FUJITSU LIMITED, SHIMIZU, KAZUYUKI C/O FUJITSU LIMITED, TATEISHI, TERUTAKA C/O FUJITSU LIMITED, TSUCHIMOTO, TAKAMITSU C/O FUJITSU LIMITED
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: G06F13
IPC codes: G06F13