HETEROJUNCTION TRANSISTOR AND METHOD OF FABRICATING THE SAME

Abstract: Semiconductor device having a hetero junction in which a polycrystalline or amorphous silicon layer (7) doped with oxygen is formed over a monocrystalline silicon semicon­ ductor substrate (1) as a passivation film, and impurities are doped only into the desired portions of the layer (7), thereby forming a semiconductor layer having a desired conductivity type. The photoetching step which is heretofore required can be omitted by forming the oxygen-doped polycrystalline or amorphous silicon layer (7) and then doping impurities having the desired conductive type.

Description: DESCRIPTION SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Technical Field: This invention relates generally to a semiconductor device and more particularly, to a semiconductor device having a hetero junction whose emitter region is constituted by a material having a forbidden band width greater than that of a material forming the base region. Background Art: A transistor whose emitter region is constituted by a material having a forbidden band width greater than that of a material forming the base region so that the emitter junction forms a hetero junction is known as a "wide gap emitter hetero junction transistor". The transistor having such a structure has high emitter injection efficiency and a great current amplification ratio hFE As the combinations of materials forming an effectively operative hetero junction, a combination of Ga¯AR¯As with Ga As, a combination of Galas with Gc and a combination of single crystal silicon with polycrystalline or amorphous silicon doped with oxygen are known. Japanese Patent Publication No. 37702/1981 (corresponding to U.S.P. No. 4,062,034) discloses a semiconductor device having a hetero junction consisting of the combination of single crystal silicon with polycrystalline or amorphous silicon doped with oxygen. In this prior art device, a region having one conductivity type is selectively formed on one main surface of a single crystal silicon substrate having the other conductivity type to form a base region and a polycrystalline or amorphous silicon layer, which is doped with an impurity having a conductivity type opposite to that of the base region and with oxygen, is deposited on this main surface. The unnecessary portion(s) of this polycrystalline or amorphous silicon layer doped with the impurity and oxygen are then removed by photoetching techniques and the film is thereafter shaped in a predetermined shape to obtain an emitter having a hetero junction. A protective layer for passivation is formed after this emitter region is formed, and apertures are opened by photoetching techniques at those portions where electrodes are to be disposed. After the necessary electrodes are deposited in the ohmic contact arrangement, the semiconductor device is completed. In practically producing the semiconductor device having the structure described above and in accordance with the fabrication method described above, however, a problem is encountered durint the photoetching step in which the polycrystalline or amorphous silicon film doped with oxygen and the impurity such as P, for example, is shaped into a predetermined emitter shape. When a 1 pm-thich film is etched using an etching solution, which consists of a 1:5:20 mixture (by volume) of hydrofluoric acid, nitric acid and acetic acid and is known heretofore, and a photoresist KMER, which is commercially available from KODAK, as an etching mask, problems occur during etching that the mask peels and the film is completely lost, or the planar dimension of the emitter is reduced by 40 pm or more due to side etching. If the film is lost, the resulting device can not naturally operate as a transistor. If the emitter size is reduced by as much as 40 pm by side etching, a pellet area necessary for obtaining a desired current capacity must be increased in advance. Hence, a device having a pattern size of below 100 pm such as a high frequency transistor or a transistor inside IC can not be fabricated in practice. The semiconductor device fabricated in accordance with the fabrication method described above mostly lacks sufficient reliability and withstand voltage. Photoetching must be carried out for each wafer and is by far more time-consuming than other fabrication steps such as oxidation and diffusion (some dozens or hundreds of wafers can be processed at once). Moreover, since photoetching accounts for the major proportion of the production cost of the device,-it has been earnestly desired to somehow improve the photoetching step. Disclosure of Invention: It is an object of the present invention to provide a semiconductor device and method of fabricating the same with a reduced photoetching step. It is another object of the present invention to provide a semiconductor device having a hereto junction having high withstand voltage as well as high reliability, and a method of fabricating the semiconductor device. In the semiconductor device in accordance with the present invention, a polycrystalline or amorphous silicon layer doped with oxygen is disposed on a single silicon semiconductor substrate, and an impurity is selectively doped into only a part of this silicon layer to form a semiconductor layer having a desired conductivity type. The portion of the silicon layer, at which only oxygen is doped, functions as a passivation film. The semiconductor device in accordance with the present invention is fabricated by the steps of growing a polycrystalline or amorphous silicon layer, to which only oxygen is doped, on a semiconductor substrate, and then doping an impurity of a desired conductivity type to a part of the silicon layer to form a semiconductor layer having the desired conductivity type. The afore-mentioned hetero junction transistor can be fabricated by forming an O-doped polycrystalline or amorphous silicon layer on a semiconductor substrate, on which the portion to serve as a base region is formed in advance, and then forming a semiconductor layer, which is to serve as an emitter region, by use of an impurity having a conductivity type opposite to that of the portion to serve as the base region, on the silicon layer. In this case, the photoetching step that has been necessary conventionally for forming the emitter is no longer necessary. If an impurity having the same conductivity type as that of the base region is doped to a portion of the O-doped polycrystalline or amorphous silicon layer where a base electrode contact portion is to be formed, it becomes possible to eliminate the photoetching step for opening the window for the base electrode forming portion, in addition to the photoetching step for forming the emitter. Brief Description of Drawings: Figure 1 is an enlarged sectional view showing the semiconductor device in accordance with one embodiment of the present invention; Figure 2 is an enlarged sectional view showing the semiconductor device in accordance with another embodiment of the present invention; Figure 3 is a sectional view showing step-wise the fabrication steps of the semiconductor device in accordance with the present invention; and Figure 4 is a sectional view of the semiconductor device and useful for explaining the fabrication steps in accordance with another embodiment of the present invention. Best Mode for Carrying Out the Invention: Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Figure 1 is an enlarged sectional view showing a hetero junction transistor as an example of the semiconductor device in accordance with the present invention. In Figure 1, an n-type collector layer 13 having relatively high resistivity, an n-type collector layer 14 having relatively low resistivity and a p-type base layer 15 having relatively low resistivity are shown disposed between a pair of main surfaces 11, 12 of a single crystal silicon substrate 1. Formed on one 11 of the main surfaces of the substrate 1 is a semiconductor layer 7 which consists of an O-doped polycrystalline or amorphous silicon and having a forbidden band width greater than that of the substrate 1 and high resistivity. This layer 7 consists of a first portion 71 which is positioned close to the surface of a selected portion of the base layer 15 and is doped with an impurity such as P, and a portion 72 which consists solely of the O-doped polycrystalline or amorphous silicon. These portions 71 and 72 function as an n-type emitter and a passiavation film, respectively. An emitter electrode 3 which comes into ohmic contact with the surface of the portion 71, a base electrode 4 which penetrates through a part of the portion 72 and comes into ohmic contact with the surface of the base layer 15 and a collector electrode 5 which comes into ohmic contact with the surface of the collector layer 14 are disposed, respectively. Figure 2 is an enlarged sectional view of the semiconductor device in accordance with another embodiment of the present invention. The semiconductor device shown in Figure 2 is the hetero junction transistor in the same way as in Figure 1. An oxygen-containing polycrystalline or amorphous silicon layer 7 is deposited on a single crystal silicon substrate 1 consisting of an n-type high resistivity layer 13 an n-type low resistivity layer 14 that functions as the collectors, and a p-type relatively low resistivity layer 15 functioning as the base. P and B are doped into portions 71 and 73, respectively. The portion 71 functions as the emitter and the portion 73, as the base electrode contact portion. The other portion covers the end portion of the p-n junction between the base and collector and the portion nearby, and functions as a passivation film. Emitter and base electrodes 3 and 4 are disposed on this silicon layer. The simiconductor device in accordance with the present invention is fabricated in the following manner. Figure 3 is a sectional view useful for explaining the fabrication steps of the hetero junction transistor shown in Figure 1. First, P is diffused into an n-type single crystal silicon wafer having high resistivity to form an + form an n layer 14 and to obtain an n-on-n wafer (see Figure 3(a)). This wafer is thermally oxidized to form oxide films (SiO2 film) 16, 16'. On the other hand, an aperture is bored by photoetching at a portion of the SiO2 film on one of the main surfaces where a base region is to be formed, and B is then diffused to obtain a p base layer 15. Thereafter, the SiO2 film 16 on the wafer surface is removed, and the wafer is heated to 6600C inside a reaction furnace and is held for 50 minutes in the atmosphere of a mixed gas consisting of 25 t/min of 3 3 N2, 30 cm /min of SiH4 and 60 cm /min of N2O. Thus, an about 1 pm-thick polycrystalline or amorphous silicon film 7 having resistivity of about 1010 Ohmcm can be formed (see Figure 6(c)). This wafer is thermally oxidized in the oxygen stream to form an SiO2 film, and only a portion where the emitter is formed is photoetched to bore an aperture. P is introduced from this aperture by ion implantation. An accelerating voltage is 80 kV and an implantation quantity is about 1x1015 cm Incidentally, the oxygen doping quantity of the semiconductor layer 7 has relation with the current amplification ratio hFE of the transistor at the portion 71 and with the passivation performance at the portion 72. As a result of experiments, the inventors of this invention have found that the quantity may be within 0 to 30 atomic%. In the aspect of the passivation performance, the resistivity of the film is found increasing with an increasing O-doping quantity such as about lox107 Ohm¯cm at 0 atomic% and about 1x1011 Ohm¯cm at 30 atomic%. This means that the upper limit value of the thickness of the layer 72, which is necessary to keep a leakage current below a predetermined value, can be increased and hence, the freedom for design can be improved. When the doping quantity approaches 67 atomic% (SiO2), however, the film becomes a dielectric and the disadvantages develop in that the field mitigation effect disappears in the substrate 1 and the field in the substrate 1 is easily affected by external influences such as the humidity of the atmosphere in which the device is placed. The reason why the portion 71 functions satisfactorily as the emitter even when the O-doping quantity is zero is found, as a result of analysis by infrared absorption and electron ray diffraction, that the band gap becomes greater than the single crystal Si because the silicon film contains the amorphous phase. On the other hand, the greater the P-doping quantity at the portion 71 of the semiconductor layer 7, the better. However, its lower limit value is determined by the condition in which the layer 71 serves as the emitter of electrons and in which the voltage drop in the layer when a current flows through the transistor is sufficiently small. Hence, the doping quantity is preferably at least 4x1019 atmos/ 3 cm Next, the wafer is heat-treated at a temperature of from 900 to l,1000C and P is extended, spread and activated throughout the direction of thickness of the film 7. If the time of this activating heat treatment is too long in this activating treatment, P will come into the p-type layer 15 of the single crystal silicon substrate 1 and forms an n-type inversion layer inside the single crystal silicon substrate. When the thickness of the inversion layer exceeds the length of diffusion of electrons, the semiconductor device is no longer a hereto junction semiconductor device. The upper limit of the heattreating time is determined in view of this point. The lower limit is the longer of the time at which the activation ratio of P reaches a saturation value and the time at which the P concentration on the interface of the hetero junction becomes sufficiently high. A desired result can be obtained by carrying out the heat-treatment for several minutes to some dozens of minutes under the film-forming conditions described above. Next, an aperture is bored by photoetching at a portion of the film 7 where the base electrode is to be bonded, and Cr-Au is vacuum-deposited as an emitter-base electrode. In the transistor of this embodiment, the p base layer 15 is 18 pm thick, the acceptor dose quantity is about 2x1014 cm , the n-type collector layer 13 has resistivity of 90 Ohm#cm, a thickness is 90 um and hFE is 100 to 200. When the forming conditions of the base and the collector are the same, this becomes about 10 times that of the conventional homo junction transistor. The breakdown voltage between the collector and the emitter is about 400 V and the leakage current is up to 10 8 A. Figure 4 is a sectional view useful for explaining the fabrication steps of the hetero junction transistor shown in Figure 2, and shows the case where the base electrode contanct portion is disposed on the semiconductor layer 7. The procedures up to the doping step of P to a desired portion of the semiconductor layer 7 shown in Figure 3(c) so as to form the emitter portion are exactly the same as those of the fabrication process described above. Thereafter, the wafer surface is again oxidized (Figure 4(a)) and an aperture is bored at a predetermined portion of the oxide film 16 which is to serve as a base electrode contact portion. B 15 -2 is implanted in a dose of about 10 cm 2 forming a B-doped polycrystalline or amorphous silicon layer 73 having low resistivity (Figure 4(b)). After the activating treatment of P and B is effected at 900 to l,1000C, an electrode material (Cr-Au) is vacuumdeposited to form emitter, base and collector electrodes 3, 4 and 5 having predetermined shapes, respectively. Hydrogen treatment is then carried out at 4500C to complete the transistor of the embodiment shown in Figure 2. The transistor thus completed has hFE of about 120 and this is about 5 times that of the conventional transistor (homo junction transistor) in which the base and collector layers are the same. The polycrystalline or amorphous silicon film 7 in the semiconductor device of the present invention may consist of two layers of an O-doped layer and a layer not doped with 0. In this case, electrode metals such as AQ, AQ-Si and the like that have been used generally for transistors can be used as the electrode material. In this case, the emitter film has a two-layered structure, too, but in accordance with the conventional fabrication process, a problem different from the problems described already occurs in the photoetching step of the emitter film. In other words, the layer not doped with 0 has a by far higher etching speed than the O-doped layer when an ordinary etching solution is used and consequently, only this layer is remarkably side-etched. Accordingly, delicate etching of the emitter becomes difficult. In accordance with the structure of the present invention, however, etching of the emitter is not necessary and such a problem does not occur. In forming the emitter region by doping P, P may be doped by a heretofore known diffusion technique of P instead of ion implantation. In such a case, P can be doped without using an ion implantation equipment. Activation in the activating treatment can also be made by radiating the laser light 2 having an energy of 1 to 5 J/cm2 for 10 to 100 ns. In such a case, there can be obtained the advantages that the activating treatment can be carried out within an extremely short period of time and when the energy of the laser light is optimized, P in the film 7 is hardly diffused into the single crystal layer, the excellent hereto junction can be formed and an extremely high P activation ratio can be obtained. In accordance with the fabrication process of the present invention, a hetero junction having high reliability, high withstand voltage passivation and high injection efficiency can be obtained with a reduced number of photoetching steps and hence, the present invention greatly contributes to practical semiconductor devices.

Claims: WHAT IS CLAIMED IS: 1. In a semiconductor device consisting of a single crystal silicon substrate and an O-doped polycrystalline or amorphous silicon layer formed on one main surface of said silicon substrate, the improvement wherein said O-doped polycrystalline or amorphous silicon layer contains an impurity having a desired conductivity type at its desired portion, and exhibits said desired conductivity type. 2; The semiconductor device as defined in claim 1 wherein said single crystal silicon substrate consists of a first layer of one conductivity type adjacent to one of the main surfaces of said substrate and a second layer of another conductivity type extending adjacent to said one main surface into said first layer and forming a first p-n junction, whose end portion is exposed to said one main surface, between said first layer, and the portion of said O-doped polycrystalline or amorphous silicon layer containing said impurity exhibits one conductivity type and forms a second p-n junction between said second layer. 3. The semiconductor device as defined in claim 2 wherein said O-doped polycrystalline or amorphous silicon layer contains an impurity of another conductivity type at its portion and exhibits said another conductivity type, and said portion having said another conductivity type is formed adjacent to said second layer of said single crystal silicon substrate. 4. A process for fabricating a semiconductor device comprising the steps of: disposing a region having one conductivity type at a part of a single crystal silicon substrate having another conductivity type to form a p-n junction so that the end portion of said junction is exposed to one main surface of said silicon substrate; forming an O-doped polycrystalline or amorphous silicon layer on said one main surface of said single crystal silicon substrate; and doping an impurity of another conductivity type to the portion of said O-doped polycrystalline or amorphous silicon layer which is positioned above the region of said single crystal silicon substrate having one conductivity type, to form a region exhibiting another conductivity type and forming a p-n junction between the region of said single crystal silicon substrate having one conductivity type. 5. The process for fabricating a semiconductor device as defined in claim 4 which further includes the step of doping an impurity having one conductivity type to the portion of said O-doped polycrystalline or amorphous silicon layer which is positioned above the region of said single crystal silicon substrate having one conductivity type, in order to form a region exhibiting the same conductivity type as that of the region of said single crystal silicon substrate having one conductivity type.

Inventors: TANAKA, TOMOYUKI, YAMADA, KOICHIRO, YASUDA, YASUMICHI
Applicants: HITACHI, LTD.
Application year: 1983
Main classification: H01L29
IPC codes: H01L21, H01L29