TEXT COMPARATOR

Abstract: Prior Art contextural comparison systems require the loading of a portion of information (known as the "data base") into a working memory of the system from a mass memory storage for scanning by a computer. The entire process is rather slow. In the present invention, the information from the mass storage device (11a) to be compared is input byte-wise into decoder (12) wherein it is immediately decoded, producing a unique signal corresponding to each individual byte. Decoded data memory (13) is made up of a plurality of shift registers, each shift register receiving an individual one of such unique signals, with the information stored in the plurality of registers forming the data base to be compared. The comparison is performed in logical operator (14), with the results thereof being transmitted to CPU (15). Comparing the received information after it is shifted through the decoded data memory (13) results in faster operation of the system.

Description: TEXT COMPARATOR BACKGROUND OF THE INVENTION Related Applications This application is a continuation-in-part of U.S. Patent application . Serial No. 06/342,620 filed January 25, 1982. Field of the Invention This invention relates to a structure and method for searching computer data bases in order to locate and retrieve textual information. Description of the Prior Art Prior art text comparators for searching a computer data base are known. Structures for carrying out such techniques (such structures are herein called "textual comparison systems") are used, for example, by Lockheed Dialog Information Retrieval Service, the United States Government "Flite" service, "Lexis", and others. Such prior art textual comparison systems are softwar oriented in that a portion of the information stored in the computer (called a "data base") must be loaded into the computer working memory from a mass memory storage device (typically a magnetic disk) . The portion of the data base within the working memory of the computer is scanned by the computer, as controlled by software in- structions, in order to determine if any portion of the data base stored in the computer working memory matches the desired text. Typically the textual material com- prising the data base is stored by using a set of standard O H data base characters such as the well-known and commonly 2 used American National Standard Code for Information 3 Interchange ("ASCII"). The ASCII characters and their 4 binary and hexidecimal representations are shown in Table 1 Thus, such prior art software-oriented text comparators ° are rather slow in that the computer must control the 7 transfer of sequential portions of the data base from a 8 large storage media, such as a disk, to the computer 9 memory, and the computer must then utilize an iterative process in order to determine whether the desired text is contained within that portion of the data base which has been transferred to the computer memory. Because the computer itself is performing the search, such prior art searching techniques are rather slow, and consequently expensive due to the- large amount of computer time required 6 to perform a search. Another prior art comparator system is described in United States Patent No. 4,152,762 issued May 1, 1979 to Bird et al. Bird et al describe a method and structure for text comparison which is rather complex and requires each desired textual word or phrase to be stored in octal format in one of a plurality of "key memories". In addi¬ tion, the Bird structure requires the use of additional memories, including a "pointer memory" and a "hash memory", 6 as well as a wide variety of other subcircuits. Thus, the Bird structure is rather complex. SUMMARY The present invention attacks the problem of text comparison for the purpose of retrieving textual infor- mation from a large data base system from a different point of view. in accordance with one embodiment of this invention, the information stored in a mass memory unit, such as a magnetic disk, is input to a text comparison sub-circuit * . Each byte of information received from the disk- is input to a decoder and is immediately decoded, and a signal corresponding to the unique character correspondi to that byte is generated. The system is capable of handling up to P different characters, where P is a select positive integer. Corresponding to the pth character (where p is an integer given by l≤p≤P) and contained within the t decoded data memory is a pth shift register uniquely arranged to receive the signal from the decoder representing the pth character. The decoded data memory contains a plurality of shift registers, one shift register for each one of the pluralit of P symbols forming the data base stored in the storage device. A first signal (e.g. a binary zero) is applied to the input lead of the shift register associated with the decoded character, and a second signal (e.g. a binary one) is applied to the input leads of all shift registers associated with each other character. A clock signal is applied to each shift register of the decoded data memory, thus shifting the data on the input lead of each shift register into the least significant bit of the shift register, and shifting each bit previously stored in a shift register to the next most significant bit position within the shift register. In this manner, the decoded data memory will provide signals on the output leads of each shift register indicative of the most recently receiv character, as well as each of the preceding (K-l) characte (i.e. a "character string" comprising K characters) receiv from the mass memory unit and decoded, where K is the number of bits contained in each shift register of the decoded data memory. Thus, each bit stored within a shift register will be a binary one except for the binary zero bits stored within a shift register corresponding to the location within the K bit character string of a character corresponding to the shift register. Of importance, only a single shift register within the decoded data memory will store a binary zero bit corresponding to each of the OMPI 1 K positions within the K bit character string. By examinin 2 the bits stored within each shift register of the decoded 3 data memory, the characters comprising the K bit character 4 string, and their relative position within the character 5 string is determined. 6 The output leads of the shift registers are connected ° to the input leads of a number of logical gates, such as AND gates and NOR gates, in order to provide an output signal indicating that a desired textual phrase has been 1 located on the mass storage device. 2 3 in addition, word counters, paragraph counters, and - other devices are employed as desired to provide special text comparison functions. The text comparison sub-circuit 6 the decoded data memory, and the logical gates of this 7 invention are capable of operating at very high speeds, 8 equal to the data output speed of the mass memory unit, 9 thus providing a very high speed textual comparison operation. A second embodiment of a text comparator constructed in accordance with this invention receives data stored in a mass storage device. This embodiment includes word logic, delimiter logic, set logic, set combination logic, 6 proximity logic, and programming logic. The delimiter logic serves to monitor the characters transferred from 8 mass storage device and provides discrete signals depicting whether the character being transferred is a predefined delimiter character. The word logic serves to store data regarding predefined words (i.e., strings of characters) which are to be located and provides output signals indi- eating when such predefined words have been located. The set logic receives the delimiter signals and word signals and provides output signals when selected words are located 6 in the same sentence, same paragraph, etc., as desired. 7 The set combination logic serves to combine the signals 8 1 from the set logic in order to generate output signals in 2 response to more complex search strategies then can be 3 easily detected by the set logic. The proximity logic 4 provides output signals indicating when predefined words 5 detected by word logic 112, or predefined set of words, as 6 detected by set logic 114, or a combination of this infor- 7 mation, occurs within a predefined proximity. For example ° proximity logic 117 will determine if a first selected word occurs within N (where N is a selected integer) words of a second preselected word. The programming logic 1 serves to receive search strategy instructions from the 2 user and in response thereto provide the proper timing, 3 addressing, and data signals to the word logic, delimiter - logic, set logic, set combination logic, and proximity 5 logic to cause to be stored within these elements the 6 information required to perform the desired search strateg 7 8 BRIEF DESCRIPTION OF THE DRAWINGS 9 0 Figure 1 is a block diagram of a textual comparison 1 system constructed in accordance with this invention; 2 3 Figure 2 is a diagram of a decoder means utilized in 4 accordance with this invention; 5 ° Figures. 3a and 3b are diagrams of the decoded data 7 memory constructed in accordance with this invention; 8 9 Figure 4 is a diagram of one shift register of the decoded data memory of Figure 3; Figures 5a through 5e are diagrams of specific e bodi- ments of the logical operator section of this invention; Figure 6a is a diagram of one embodiment of a word counter of this invention; Figure 6b is a diagram of one embodiment of a sentenc counter of this invention; Figure 6c is a diagram of one embodiment of a para- graph counter of this invention; Figures 7a and 7b are diagrams of another embodiment of the logical operator section of this invention; Fig- 8 is a block diagram of a textual comparator construction in accordance with a second embodiment of this invention; Fig. 9 is a diagram depicting the relationship betwee Figs. 9a, 9b and 9c which form a schematic diagram of the delimiter logic 113 shown in Fig. 8; Fig- 10 is a diagram depicting the relationship between Figs. lOa-lOd which in turn form a schematic diagram of the set logic 114 depicted in Fig. 8; Fig. 11 is a diagram which depicts the relationship between Figs. 11a and lib which in turn form a schematic diagram of the set combination logic 115 depicted in Fig. 8; Fig. 12 is a diagram depicting the relationship between Figs. 12a-12d which in turn form a schematic diagram of the word logic 112 shown in Fig. 8; and Fig. 13 is a diagram depicting the relationship between Figs- 13a-13c which in turn form a schematic diagram of the proximity logic 117 shown in Fig. 8. DETAILED DESCRIPTION FIRST EMBODIMENT System Overview Figure 1 shows a block diagram of a text comparator constructed in accordance with the first embodiment of this invention. Mass storage device 11 comprises a devic suitable for the storage of a large quantity of data. OMP Such data is typically called a "data base". The data base might be, for example, textual material such as United States patents, judicial decisions from various courts, or other information. Mass storage device 11 typically comprises a magnetic disk, as is well known in the computer arts, and the data base stored within mass storage device 11 is typically stored in ASCII format, although this invention can be utilized in conjunction with data bases stored in other than ASCII format (for example, EBCDIC). Data stored in mass storage device 11 is transferred via bus 11a to decoder 12. Typically, bus 11a comprises a plurality of electrical leads, in order that a plurality of bits forming a single byte of information may be trans- ferred simultaneously from mass storage device 11 to decoder 12. The simultaneous transfer of a plurality of bits forming a single byte is often referred to as "paralle data output". Decoder 12 receives each byte transferred from mass storage device 11, and decodes that byte into one of a plurality of unique decoded data signals. Each such decoded data signal represents a unique one of the charac- ters which form the data base stored in mass storage device 11. For example, such characters typically comprise the numbers zero through nine, twenty-six capital letters, twenty-six lower case letters, and a variety of punctu- ation and special symbols such as asterisk, period, comma, question mark, space, and the like. Inasmuch as ASCII is • one widely used method of coding such characters into a plurality of bytes, this specification will refer to ASCII coding in order to explain the operation of one embodiment of this invention. However, it is to be understood that this invention is equally useful in systems wherein coding schemes other than ASCII is utilized. A cross reference table listing each character and its ASCII equivalent is given in Table 1. The output from decoder 12 is connected via bus 12a to decoded data memory 13. Because ASCII comprises a plurality of 96 characters, bus 12a in the preferred embodiment comprises a plurality of 96 leads, one such lead being associated with a unique one of the ASCII characters. However, it should be understood that as many leads as required can be used depending on the number of characters to be decoded and in general bus 12a comprises a plurality of M leads, where M is a selected positive integer representing the number of characters-to be decode Decoded data memory 13 stores the decoded data provid by decoder 12 for a sequence of K characters stored in mass storage device 11 where K is a positive integer which is fixed by the particular design of the decoded data memory 13. Typically K will be either eight or sixteen, although K may be any positive integer. Decoded memory 13 comprises a plurality of 96 shift registers, one shift register for each ASCII character. K is equal to the number of bits which are stored within each shift register. The data (i.e., a logical one or a logical zero) contained in each of the K bits of the 96 shift registers of decoded data memory 13 indicates which ASCII characters form each character of the K byte character string ending in the most recently decoded character. A output bus 13a, containing a number of leads equal -to K96 (K96 equals K multiplied by 96), connects each of the K96 output leads of the 96 shift registers of decoded data memory 13 to logical operator section 14. Logical operator section 14 comprises one or more logical gates which perform a logical operation on the data stored in the shift registers of decoded data memory 13. This logical operation provides an output signal indicating when a desired textual phrase, string of characters, or sets of strings of characters, has been located within the data base stored in mass storage device 11. This output ( OMPI signal from logical operator section 14 is applied via bus 14a to central processing unit (CPU) 15. Thus, central processing unit 15 is made aware that a desired textual phrase has been located in mass storage device 11. CPU 15 then follows its set of programmed instructions, and utilizes the desired textual phrase which has been located in the data base. Typically, CPU 15 stores the address location of the beginning of the desired textual phrase which has been located in the data base, stores the record number of the record (i.e., patent number, etc.) in which the desired textual phrase has been found, or performs other desired tasks in response to the location and identi- fication of the desired textual phrase within the data base. It is to be understood that, once the desired textual phrase has been located within the data base stored in mass storage device 11, and the CPU signalled by logical operator section 14, the operation of CPU 15 is generally the same as the operation of central processing units in systems utilizing prior art text comparison techniques. Decoder 12 Referring to, Figure 2, the detailed operation of decoder 12 will now be explained. The embodiment of decoder 12 shown in Figure 2 is designed for use with systems utilizing ASCII coding. For systems utilizing other than ASCII coding, the specific design of decoder 12 differs from that shown in Figure 2, but is easily provided by one of ordinary skill in the art, in light of the teachings of this specification. In ASCII format, as shown in Table 1, each character comprises eight binary digits (bits) or two hexidecimal digits. Input bus 11a comprises eight leads, thus providing to decoder 12 in a parallel output format the 8 bits forming a single ASCII character stored in mass storage device 11 (Figure 1). Input bus 11a also comprises an additional lead 99, which provides a valid data signal (VDA) which, when high (logica "1") indicates that valid data is available on bus 11a from mass storage device 11. The four least significant bits (LSB) of the ASCII btye received from bus 11a are applied to four bit buffer B-l, thus providing on leads D Q through D 3 buffered signals representing the four least significant bits of the ASCII byte. Similarly, the four most significant bits (MSB) of the ASCII byte received on bus 11a are applied to four bit buffer B-2, thus providing on leads D-7 through D-4 buffered signals representing the four most significant bits of the ASCII byte. Buffers B-l and B-2 may comprise, for example, a 74125 device, such as manufactured and sold by Texas Instruments. The buffered four least significant bits (on leads D Q through D 3 ) are applied as input signals to demultiplexers 105-2 through 105-7 and the buffered four most significant bits (on leads D-7 through D-4) are applied as input signals to demultiplexer 103. Demultiplexers 103 and 105-2 through 105-7 are four bit to sixteen bit demulti- plexers such as the 74LS154 manufactured and sold by Texas Instruments. Thus, each demultiplexer 103 and 105-2 through 105-7 provides a one of sixteen bit demultiplexing function, although only six of the sixteen output signals from demultiplexer 103 (on leads R 2 through R-) are used because, as previously mentioned, ASCII comprises 96 characters, and these 96 characters are uniquely defined by the output leads of six separate four-to-sixteen bit demultiplexers 105-2 through 105-7, as will be more fully described below. Accordingly, as shown in Table 1, the four most significant bits of an ASCII byte range from a binary 0001 (a decimal 1) to a binary 0111 (a decimal 7). The output signal on each output lead of demulti- plexers 103 and 105-2 through 105-7 is normally high (logical one). Each demultiplexer has as many output leads (16) as there are different binary input signals (16) which can be applied to its four input leads. Each OMP output lead corresponds uniquely to one possible input signal to the demultiplexer. However, when a four bit input signal (the four most significant bits on leads D-4 through D-7 connected to demultiplexer 103, or the four least significant bits on leads D Q through D 3 applied to demultiplexers 105-2 through 105-7) is input to a demulti- plexer, and that demultiplexer is enabled (to be more fully described below), a logical zero is placed on the output lead corresponding to the input signal applied to the demultiplexer. For example, if a four bit binary input signal 0101 is applied to a demultiplexer, and that demultiplexer is enabled, the output lead 5 (corresponding to a binary 0101) of the demultiplexer will be low, and all other output leads of the demultiplexer will be high. All output leads of a disabled demultiplexer are high. Demultiplexers 103 and 105-2 through 105-7 are enabled by the application of a low signal to their respective enable terminals. This occurs only when valid data is present on bus 11a from the mass storage device. As previously described, a logical one on valid data lead 99 indicates that valid data is present on bus 11a. This logical one signal is inverted ,by inverter 101a, and a logical zero VDA signal is applied to NOR gate 102 and NOR gates 104-2 through 104-7. Although NOR gates 102 and. 104-2 through 104-7 are shown external to demultiplexers 103 and 105-2 through 105-7, these NOR gates are an integra part of the 74LS154 devices. The output lead of NOR gate 102 is connected to the enable input lead of demultiplexer 103, and the output leads of NOR gates 104-2 through 104-7 are connected to the enable input leads of demultiplexers 105-2 through 105-7, respectively. Thus, with a low VDA signal on lead 99, indicating that valid data is not present on input bus 11a, the VDA signal from the output lead of inverter 101a will be high, thus causing the output signal from NOR gates 102 (having its other input lead connected to ground) to be low, thus disabling 1 demultiplexer 103. With demultiplexer 103 disabled, leads 2 R_ through R_ will all be high; thus disabling de ulti- 3 plexers 105-2 through 105-7. 4 5 On the other hand, with a logical high on VDA lead ° 99, indicating that valid data is present on input bus 9, the VDA signal will be low. Because one input lead of NOR gate 102 is connected to ground (logical zero) and the 9 other input lead of NOR gate 102 is connected to VDA, a 0 low VDA signal causes the output signal from NOR gate 102 1 to go high, thus enabling demultiplexer 103. Demulti- - plexer 103 then demultiplexes the four most significant bits, thus providing a logical low on the unique output lead R„ through R„ corresponding to the value of the four most significant bits (D 4 through D-). Output leads R 2 through R_ of demultiplexer 103 are connected to one input 7 lead of NOR gates 104-2 through 104-7, respectively, with 8 the other input lead of NOR gates 104-2 through 104-7 being connected to VDA. With a logical low VDA signal applied to one lead of NOR gates 104-2 through 104-7 and a logical low signal corresponding to the demultiplexed most significant bits on a unique one of leads R 2 through R~ applied to the other lead of one of the NOR gates 104-2 through 104-7, a high signal will be generated on the output lead of the NOR gate 104-2 through 104-7 correspond¬ ing to the value of the most significant bits. Thus, upon receipt of valid data (high VDA signal) a selected one of demultiplexers 105-2 through 105-7 will be enabled, and all other demultiplexers 105-2 through 105-7 will be disabled by the logical high signal on the remaining leads R 2 through Rg. For example, with a high VDA signal, indicating receipt of valid data, and the four most signifi cant bits equal to 0010, demultiplexer 103 is enabled and a low signal generated on lead R 2 , with leads R 3 through R 7 remaining high. Demultiplexer 105-2 is enabled by the low VDA signal and the low signal on lead R 2 - Demulti- plexers 105-3 through 105-7 remain disabled by the high level signals on leads R 3 through R„, respectively. OMPI The output signals on each output lead of the disable demultiplexers 105-2 through 105-7 will be high, as previ- ously described. The signals on the output leads of the enabled one of demultiplexers 105-2 through 105-7 will be high, except for the single output lead which corresponds to the decoded least significant bits on leads D Q through D 3 connected to the input leads of demultiplexers 105-2 through 105-7. In this manner, upon the receipt of valid data on bus 11a, a single low signal is generated on a single output lead of demultiplexers 105-2 through 105-7. The lead which contains that low signal corresponds to the character represented by the 8-bit ASCII byte received on bus 11a. For example, with a high VDA signal and an eight bit byte equal to 01101101 received on bus 11a, demulti- plexer 103 will be enabled, as previously described, and the four most significant bits (0110) demultiplexed by demultiplexer 103_, thereby generating a logical low signal on output le ' ad R g . This will enable demultiplexer 105-6, which in turn demultiplexes the four least significant bits (1101), thereby generating the signals on a logical low on output lead 6D of demultiplexer 105-6, with all other output leads of demultiplexer 105-6 remaining high. Output lead 6D corresponds to the ASCII character m, represented by 01101101. A high signal is present on leads R_, R 3 , R., R 5 and R 7 , thus disabling demultiplexers 104-2, 104-3, 104-4, 104-5, and 104-7, thereby providing high signals on output leads 20 through 5F and 10 through 7F. For convenience, the output leads from demultiplexers 105-2 through 105-7 are numbered with two digits. The first digit indicates which of the six demultiplexers 105-2 through 105-7 is connected to the lead, and the second digit indicates the lead number (represented in hexidecimal as 0 through F) . Utilizing this notation, the first digit also represents the four most significant bits of the data word received on bus 11a, and the second digit also represents the four least significant bits of the data word received on bus 11a. Inverters 101a through lOlj provide a time delayed VDA' signal. By applying the valid data signal (VDA) on lead 99 to the input lead of inverter 101a, a time delayed valid data signal (VDA' ) is generated by inverter 101j on node 101. The VDA » - signal is delayed from the VDA signal by approximately 100 nanoseconds. The VDA 1 signal is used to enable the decoded data memory 13 (Figure 1) to receive data from output leads 20 through 7F of decoder 12, but provides a time delay sufficient to allow the proper operation of decoder 12 prior to the receipt of decoded data by decoded " data memory 13. Each inverter 101a through 101j may comprise, for example, one of the six inverters comprising a 7404 Hex inverter, such as is manufactured and sold by Texas Instruments- Decoded Data Memory 13 Referring to Figures 3a and 3b, the operation of decoded data memory 13 will now be explained. Upon the receipt of a high VDA' signal (corresponding to valid data on input bus 11a of decoder 12) on node 101 of decoded data memory .13, buffer 201 provides high clock signals CLK-2 through CLK-7. Buffer 201 may comprise, for example, a 74365 device manufactured and sold by Signetics. Decoded data memory 13 comprises a plurality of shift registers such as shift register SR2J2T. For purposes of clarity, the plurality of 96 shift registers are not indi¬ vidually labelled; only shift register SR20 is so labelled. However, the array of shift registers of decoded data memory 13 of Figures 3a and 3b are arranged in a matrix comprising six rows (row 2 through row 7) and sixteen columns (column 0 through column F) . Thus, shift register SB20 is the shift register located at the intersection of r ow 2 and column 0. In a similar manner, the shift registe located at the intersection of row n and column m will be referred to as shift register SRnm in this specification. OMPI Each shift register SRn (where n and m are positive integers given by l≤n≤N and l≤m≤M) is connected to a unique one nm of leads 20 through 7F which corresponds to that shift register. Thus, shift register SR20 is con- nected to lead 20 and shift register SRnm is connected to lead nm. Leads 20, nm and NM in turn are connected to the decoder 12 of Figure 2. In this fashion, each shift register of the decoded data memory 13 is connected to a unique output lead of decoder 12 (Figure 2), thereby causing each shift register of decoded data memory 13 to correspond to a unique one of the 96 ASCII characters. For convenience, the ASCII character associated with each shift register is indicated above the shift register. Thus, shift register SR2 , connected to lead 20, corres- ponds to a blank (S) which " is coded in ASCII as a hexi- decimal "20" , as shown in Table 1. In a similar manner, each of the 96 shift registers of decoded data memory 13 corresponds to a unique ASCII character. As previously mentioned, each shift register SRnm is capable of storing K bits, thus allowing decoded data memory 13 to store K decoded characters and their relative position within the string of K characters. Clock signals CLK-2 through CLK-7 are connected to each shift register within row 2 through row 7, respectivel Upon the receipt of a high VDA' signal, CLK-2 through CLK-7 go high- The low to high transition of clock signals CLK-2 through CLK-7 enables all shift registers of rows 2 through 7, respectively, of decoded data memory 13. Enabling each shift register causes the signal on the signal lead connected to that shift register to be stored in the least significant bit of the shift register, and all other data previously stored shifted to the next most significant bit. Thus, for example, if a logical zero is present on signal lead 20, and a high VDA' signal is received, CLK-2 will go high, thus causing the logical zero on lead 20 to be stored in the least significant bit of shift register SR20. All other data previously stored in shift register SR20 will be shifted to the next most significant bit, with the previously stored most signi- ficant bit being lost. The plurality of shift registers comprising decoded data memory 13 may comprise, for example, eight bit serial in, parallel out shift registers, such as 74164 devices manufactured and sold by Signetics. Alternatively, each shift register SR2j2f through SR7F may comprise a plurality of 74164 devices serially connected in order to increase the number of bits which are stored within each of the 96 shift registers forming decoded memory 13. of importance, only a single logical zero will be present on signal leads 20-1F at any time. Thus, the unique one of the 96 shift registers which correspond to the most recently decoded byte from mass storage device 11 will store a least significant bit equal to a logical zero, while all other shift registers will store a least significant bit equal to a logical one- Thus, for example, if a blank was the most recently decoded ASCII character, decoded data memory 13 will indicate this fact by the presence of a logical zero as the least significant bit of shift register 20, with all other least significant bits being equal to a logical one. In a similar fasion, the previously decoded character will be indicated by the presence of a logical zero as the next to least signifi¬ cant bit stored in the shift register corresponding to the previously decoded character. Thus, if an "1" was the previously decoded character, the next to least signifi- cant bit stored within shift register SR21 (corresponding to the exclamation point) will be a logical zero, and the next to least significant bit stored within all other shift registers will be a logical one. In this manner, each of the most recently decoded K characters are indi- cated by the location of logical zeros within the shift register of decoded data memory 13, where K is the number of bits stored in each shift register. An example of the ability of decoded data memory 13 to store a character string which is decoded by decoder 12 (Figure 1) will now be given. Initially all bits containe within each of the 96 shift registers of decoded data memory 13, comprise logical ones. This may be accomplishe for example, by providing a low VDA signal, thus disabling demultiplexers 105-2 through 105-7 (Figure 2), and thereby providing logical one signals on leads 20 through 7F, and providing a series of low to high transitions on termina 101, thus shifting a series of K logical one signals into each K bit shift register (SR2J? through SR7F) of decoded data memory 13. These low to high transitions on terminal 101 are easily provided with well known circuitry (not shown) . if the word "Work" is to be decoded by decoder 12, the 8 bits corresponding to the hexadecimal ASCII code 57 for a "W" will be output from mass storage device 11 to input bus 11a of decoder 12. A valid data signal (high VDA) will also be made available on bus 11a. Demulti- plexer 103 will be enabled, and a logical low signal generated on lead R 5 corresponding to the most significant bits of the ASCII code for W. The logical low on lead R 5 , and the low VDA signal will enable demultiplexer 105-5. Demultiplexer 105-5 then demultiplexes the least signifi- cant bits, and provides a logical low on output lead 57. All remaining output leads of demultiplexers 105-2 through 105-7 remain high at this time. The output signals on demultiplexers 105-2 through 105-7 are then (after the time delay provided by inverters 101a through 101j ), shifted into the least significant bit positions of their cor- responding shift registers of decoded data memory 13 (Figure 3). Thus, the least significant bit of shift register SR57 will store a logical zero, and the least significant bits of all remaining shift registers will store a logical one. The shift register SR57 will store the bits 1110, and all other shift registers will store the bits 1111, if shift registers SR20 through SR7F compris four bit shift registers. The letter "o" (hexadecimal 6F) is then output from mass storage device 11 to decoder 12 (Figure 2). De ulti- plexer 103 decodes the most significant bits and provides a logical low signal on output lead R fi . The low signal on lead R g , together with the low VDA signal, enables demulti- plexer 105-6- Demultiplexer 105-6 then decodes the least significant bits, and provides a logical low signal on output lead 6F. All signals on all remaining output leads of demultiplexers 105-2 through 105-7 are logical ones at this time- The signals on the output leads of demulti- plexers 105-2 through 105-7 are then shifted into the least significant bit of their associated shift registers of decoded data memory 13 (Figure 3). At this time, shift register SR6F corresponding to the character "o" will store the bits 1110, indicating that a "o" has been the most recently decoded character. Similarly, shift regiser SR57 will store the bits 1101, indicating that the characte --w" was the previously decoded character. All others shift registers of decoded data memory 13 will store the bits 1111 indicating that their associated characters are not one of the last four characters decoded. The character "r" (hexadecimal 72) is now output from mass storage device 11 to decoder 12 (Figure 2). Demulti- plexer 103 decodes the most significant bits of the character "r", and provides a logical zero signal on output lead R ? . Demultiplexer 105-7 is thus enabled, and provides a logical zero signal on output lead 72, with the signals on all other output leads 20 through 7F being 1 logical ones. The signals on the output leads of demulti- plexers 105-2 through 105-7 are then shifted into decoder 3 data memory 13 (Figure 3). Shift register SR72 will store 4 the bits 1110, shift register SR6F will store the bits 5 1101, shift register SR57 will store the bits 1011, and ° all remaining shift registers will store the bit 1111, 7 indicating that the character string "Wor" has been decode 8 The ASCII character "k" (hexadecimal 6B) is then output from mass storage device 11 to decoder 12 (Figure 2) Demultiplexer 103 decodes the most significant bits of the ASCII character, thus providing a logical zero signal on lead R g . The logical zero signal on lead R fi enables de- multiplexer 105-6. Demultiplexer 105-6 demultiplexes the least significant bits of the ASCII character, thereby providing a logical zero signal on output lead 6B, with logical ones being present on all other output leads 20 through 7F. The data on the output leads of demultiplexer 105-2 through 105-7 is then shifted into decoder data memory 13 (Figure 3a). At this time, ' shift register SR6B will store the bits 1110, shift register SR72 will store the bits 1101, shift register 6F will store the bits 1011, and shift register SR57 will store the bits 0111, indi¬ cating that the character string "Work" has been decoded. //// //// //// //// //// //// //// //// . //// //// //// //// TABLE 1 ASCII ASC ASCII Code ASCII Cod - Code (Hexi¬ Code (He Character (Binary) decimal) Character (Binary) dec blank 00100000 20 P 01010000 1 00100001 21 Q 01010001 !! 00100010 22 R 01010010 # 00100011 23 S " 01010011 $ 0O100100 24 T 01010100 X 00100101 25 U 01010101 ' & 00100110 26 V 01010110 t 00100111 27 W 01010111 ( 00101000 28 X 01011000 ) 00101001 29 Y 01011001 -V 00101010 2A Z 01011010 + 00101011 2B [ 01011011 5 00101100 2C \ 01011100 - 00101101 2D ] 01011101 . 00101110 2E —1 or Λ 01011110 / 00101111 2F — 01011111 0 00110000 30 01100000 1 001100Q1 31 a 01100001 2 00110010 32 b 01100010 3 00110 11 33 c 01100011 4 00110100 34 d 01100100 5 00110101 35 e 01100101 6 00110110 - 36 f 01100110 7 00110111 37 g 01100111 8 00111000 38 h 01101000 9 00111001 39 i 01101001 : 00111010 3A j 01101010 > 00111011 3B k 01101011 < 00111100 3C 1 01101100 = 00111101 3D m 01101101 > 00111110 3E n 01101110 ? 00111111 3F o 01101111 έ 01000000 40 P 01110000 A 01000001 41 <L 01110001 B 01000010 42 r 01110010 C 01000011 43 s 01110011 D 01000100 44 t 01110100 E 01000101 45 u 01110101 F 01000110 46 V 01110110 G 01000111 47 w 01110111 H 01001000 48 X 01111000 I 01001001 49 y 01111001 J 01001010 4A z 01111010 K 01001011 4B { 01111011 L 01001100 4C 1 01111100 M 01001101 4D } 01111101 01001110 4E ~ 01111110 0 01001111 4F DEL 01111111 1 A detailed view of the output leads of the shift 2 registers of decoded data memory 13 is shown in Figure 4. 3 Shift register SRnm, corresponding to the shift register ^ at the intersection of row n and column m, has a plurality * of K output leads for examining the K bits stored within ° shift register SRnm. Thus, the least significant bit 7 stored within shift register SRnm is available on lead R . . . . ° nml, the next to the least significant bit is available on 9 lead nm2, and the most significant bit is available on ° lead nmK. 1 Logical Operator Section 14 3 Logical operator section 14 comprises one or more - logical gates which may be hard wired to decoded data memory 13, or alternatively programmably connected under computer control, as described later. One embodiment of logical operator section .14 (Figure 1) is shown in Figure 5a. Here, NOR gate 761a is connected so as to provide a logical one signal on output lead 762a when the character string "Work" has been located ' in mass storage device 11 (Figure 1). When the character string "Work" has been received, the fourth least significant bit of shift registe SR57 (as provided on lead 574), the third least significant bit of shift register SR6F (as provided on lead 6F3), the second least significant bit of shift register SR72 (as provided on lead 722), and the least significant bit of shift register SR6B (as provided on lead 6B1), will all be equal to logical zeros. Thus, upon receipt of the characte string "Work", the output signal on lead 762a of NOR gate 761 (having its input leads connected to leads 574, 6F3, 722 and 6B1) will be a logical one, in contrast to the logical low signal present on lead 762a at all other times. Because the character string "Work" will be detected by NOR gate 761a upon decoding of the first four letters of the word "Working" as well as for the word "Work", when seeking to locate a character string equivalent to the word "Work", and not any variations thereof, the logical operator section 14 (Figure 1) is programmed to locate the character string "Workb" (where b is a blank character). This is depicted in Figure 5b, where NOR gate 761b requires the fifth least significant bit of shift register SR57 (on lead 575), the fourth least significant bit of shift register SR6F (on lead 6F4), the third least significant bit of shift register SR72 (on lead'723), the second ' least significant bit of shift register SR6B (on lead 6B2), and the least significant bit of shift register SR20 (on lead 20 " V) to all be logical zeros in order for the signal on lead 762a to be a logical one, indicating receipt of the character string "WorkS"- By the appropriate connection of additional gates, logical operator section 14 may perform other search functions. For example, if it is desired to locate within mass storage device 11 all occurrences of either the word "Workb" or "workb", the circuit of Figure 5c will serve as logical operator section 14- Here, the input leads of AND gate 760 are connected to leads 575 (from shift register 57 corresponding to the capital letter "W") and 775 (from shift register 77 corresponding to the lower case letter "w"). Thus, a logical low on either lead 575 or lead 775 will provide a logical low signal on lead 760-1, which in turn is connected to an input lead of NOR gate 761C. The remaining input leads of NOR gate 761C are connected to leads 6F4, 723, 6B2, and 101, as in the embodiment of Figure 5b. In this manner, a logical high output signal is provided on lead 762C when either of the desired words "Workb" or "workb" are located. In many data base systems, additional symbols are used to indicated the end of a word (EOW), the end of a sentence (EOS), the end of a paragraph (EOP), and the end of a document (EOD). These additional symbols may comprise OMPI WTPO 1 eight bit bytes which do not form one of the 96 ASCII characters (i.e. comprise 00 through 07 or 80 " through 8F). 3 Alternatively, these additional symbols may comprise one " or more ASCII characters. For example, the end of sentenc -> signal (EOS) may comprise a period followed by two blanks. ° Additional shift registers are utilized to serve as word counters, sentence counters, and paragraph counters. 8 An example of a word counter, which indicates which word within a sentence is being decoded, is shown in Figure 6a. Shift register SR-EOW may comprise a 74164 8-bit serial-in, parallel-out shift register, as has been previously described for the shift registers of decoded " data memory 13. Alternatively, a plurality of 8-bit shift registers may be connected serially, thus providing shift register SR-EOW which is capable of storing greater than 8 bits. As shown in Figure 6a, shift register SR-EOW is provided a clock signal by the end of word (EOW) signal. Thus, shift register SR-EOW is clocked upon receipt of an EOW signal, thereby shifting data on input lead 876a into shift register SR-EOW and shifting data stored in the shift register to the next most significant bit. . Input lead 876a is connected to the output lead of SR flip flop ggg (which may comprise a 74LS279 device manufactured by Signetics- On receipt of a high EOS signal, indicating the end of a sentence, a logical low EOS signal is generate by inverter 998 (e.g. a 7404 device) and applied to the clear input lead of shift register SR-EOW, thus clearing shift register SR-EOW (i.e. shift register SR-EOW stores all zeroes when clear). This low EOS signal also causes flip flop 999 to provide a high output signal on lead 876a. Upon the receipt a high EOW signal, indicating the end of a word, the high output signal on lead 876a is clocked into the least significant bit of shift register SR-EOW. Also, upon receipt of a high EOW signal, inverter 997 provides a low R signal to reset flip flop 999, thus causing flip flop 999 to provide a low output signal. OMPI This low output signal is input to shift register SR-EOW by the operation of subsequent EOW signals applied to the clock input lead of shift register SR-EOW, thereby shifting the low Q signal on the output lead of flip flop 999 into the least significant bit of shift register SR-EOW, and shifting the data stored in each bit of shift register SR-EOW to the next significant bit- Thus, signal initially stored within the least significant bit of shift register SR-EOW in response to a high EOS signal is.shifted to the ' left (i.e. the next most significant bit) upon receipt of each EOW signal. In this manner, the signal on leads EOW-1 through EOW-j, where j is the number of bits stored within shift register SR-EOW, indicate which word within the sentence is being decoded. Thus, for example, if a logical one is present on lead EOW-1, the first word in the sentence is being decoded. Similarly, where a logical one is present on lead EOW-2, the second word of the sentence is being decoded- Of importance, only a single logical one will be present on leads EOW-1 through EOW-j. This is accomplished by applying a high signal to the "clear" input lead of shift register SR-EOW upon receipt of a high EOS signal, thus resetting all bits stored in shift register SR-EOW to logical zeros immediately prior to the storage of a logical one in the least significant bit of shift register SR-EOW when a high EOS signal is applied to input lead 876. A sentence counter is shown in Figure 6b. The sentenc counter, comprising shift register SR-EOS having output leads EOS-1 through ΞOS-j, operates in a similar manner as the word counter of * Figure 6a. However, RS flip flop 989 has its input lead connected to the EOP signal, thereby clearing shift register SR-EOS and setting flip flop 989 high upon receipt of each EOP signal. Upon the receipt of a high EOS signal, shift register SR-EOS is clocked in a similar manner as SR-EOW (Figure 6a), thereby storing a logical one in the least significant bit of shift register \. 1 SR-EOS upon receipt of the first sentence of each paragrap 2 and clocking this logical one to the next significant bit upon receipt of each sentence. Thus, the presence of a " logical one on a unique one of leads of EOS-1 through -> EOS-j indicates which sentence in a paragraph is being ° decoded. 7 A paragraph counter is shown in Figure 6c. The paragraph counter, comprising shift register SR-EOP having output leads EOP-1 through EOP-j , operates in a similar 1 manner as the word counter of Figure 6a and the sentence 2 counter of Figure 6b. However, the EOP signal provides a 3 clock signal to the paragraph counter SR-EOP. The input 4 lead 876c of the paragraph counter is connected to the 5 output lead of RS flip flop 979, which, is set by the EOD 6 signal. The clear input lead is activated upon receipt of 7 a high EOD signal. In this manner, the logical one appear 8 ing on a unique one of output leads EOP-1 through EOP-j 9 indicates which paragraph within the document is being 0 decoded. 1 2 Utilizing the word counter, sentence counter, para¬ 3 graph counter, and decoded data memory 13, complex full- ^" text searching may be accomplished. For example, if it is 5 desired to locate a document stored within mass storage 6 device 11 in which the word "Workb" appears in the third 7 word of the fourth sentence of the second paragraph, the 8 circuit of Figure 5d is used. The circuit of Figure 5d comprises AND gate 901 having one input lead connected to output lead 762b of the circuit of Figure 5b. Thus, a logical high signal will be input to AND gate 901 on lead 762b when the character string "Workb" is decoded. Simi- larly, a logical high signal will be input to AND gate 901 when the third least significant bit of the word counter is a logical one, indicating that the third word is being decoded. This high signal will be available on lead EOW-3. In a similar manner, when the fourth sentence of the paragraph is being decoded, a logical high will be applied at an input signal to AND gate 901 on lead EOS-4, and when the second paragraph of a document .is being decoded, a high input signal will be applied to AND gate ' 901 on lead EOP-2. Thus, a logical high signal will be present on output lead 901-1 only when the word "Workb" is decoded as the third word of the fourth sentence of the second paragraph of a document. i accordance with this invention, full text searching is accomplished to locate documents in which a plurality of desired words within the same sentence. For example, one embodiment of a logical operator section 14 which may be utilized to locate text which includes the word "batb" and "ballb" in the same sentence is shown in Figure 5e. NOR gate 976 has its input leads connected to leads 624, 613 ; -741 and 2)31 of decoded data memory 13, thus providing a logical high output signal on lead 976-1 when the word "batb" has been decoded. Similarly, NOR gate 977 has its input leads connected to leads 625, 614, 6C3, 6C2 and 20X of decoded data memory 13, thus providing a logical high on output lead 977-1 when the word "ballb" is decoded. Lead 976-1 is connected to the S input of SR flip-flop 978, thus providing a logical high on the , output lead 978-1 when the word "batb" has been decoded. Similarly, lead 977-1 is connected to the S input lead of SR flip-flop 979, thus providing a high signal on the 2 output lead 979-1 when the word "ballb" has been decoded- Flip-flops 978 and 979 are reset by a low EOS signal, which is applied to the R input leads of the flip-flops. Thus, at the end of each sentence, flip-flops 978 and 979 are reset (Q, and 2 reset to logical zero), thus indicating that the words "batb" and "ballb" have not been decoded within the next sentence. The output leads 978-1 and 979-1 from the flip-flops are connected to the input of AND gate 980, thus providing a logical high on output lead 980-1 when the words "batb" and "ballb" have been decoded within the same sentence (i.e. Q-, output lead of flip flop 978 and Q 2 output lead of flip flop 979 both high). By utilizing the end of paragraph (EOP) or the end of document (EOD) signal in place of the end of sentence (EOS) signal in the logica operator section depicted in Figure 5e, documents may be located in which the words "batb" and. "ballb" are located within the same paragraph, or document, respectively. It is often desired to find the location within the data base where a first desired word appears within a selected number of words of a second desired word. For example, it may be desirable to locate instances where the word "ball" appears within four words of the word "bat", in order to locate portions of the data base referring to baseball, while not locating portions of the data base referring to any other type of ball (e.g. golf ball, etc.) and any other type of bat (e.g. flying mammals). One embodiment of logical operator section 14 which may ac- complish this task of locating portions of the data base wherein the word "bat" appears within four words of the word "ball" is shown in . the schematic diagrams of Figures 7a and 7b. Logical operator section 14 of Figure 7a includes NOR gate 976 and NOR gate 977, which are connected in the same manner as NOR gates 976 and 977, respectively, of Figure 5e. Accordingly, a high output signal from NOR gate 976 indicates that the word "batb" has just been located. Similarly, a low output signal from NOR gate 977 indicates that the word "ballb" has just been located. Inverters 831 and 832 invert the output signal from NOR gates 976 and 977, respectively. Thus, upon detection of the word "batb", the output signal from inverter 831 is low, thus setting SR flip flop 833 to have a high Q output signal. Similarly, upon detection of the word "ballb", the output signal from inverter 832 is low, thus setting SR flip flop 834 such that its Q output signal is high. The Q output signals from SR flip flops 833 and 834 are clocked into the least significant bit of shift registers 834 and 836, respectively, upon receipt of a low EOW signal which is applied to the clock input leads of shift registers 835 and 836. SR flip flops 833 and 834 are required in order to preserve the signal indicating that the desired words have been decoded, until the receipt of the EOW signal which clocks that data into shift registers 835 and 836, respectively. If SR flip flops 833 and 834 were not used, the signal indicating that the desired words had been detected would be lost prior to being clocked into shift registers 835 and 836, respectively. Of importance, when the EOW signal comprises a blank character (which appears at the end of every word) , and the desired word being detected includes the blank character and the end of the word (e.g. "batb" and "ballb") shift registers 833 and 834 (and thus inverters- 831 and 832) are not required, because the EOW signal appears simultaneously with the high output signal from either NOR gate 976.or NOR gate 977 indicating that the desired word has been decoded. Upon detection of the word "batb" and receipt of the EOW signal, a logical one is clocked into the least signi- ficant bit of shift register 835- After the data from flip flops 833 and 834 have been clocked into shift regi- sters 835 and 836, respectively, upon the receipt of an EOW signal, a low signal is applied to terminal 841 which is connected to the reset (R) input leads of flip flops 833 and 834, thus resetting the Q output signals of flip flops 833 and 834 low. This reset signal applied to terminal 841 may comprise, for example, a signai EOW' , which is derived from but delayed by approximately 75 microseconds from the EOW signal, thus resetting flip flops 833 and 834 after the data appearing on their Q output leads have been clocked into shift registers 835 and 836, respectively, upon receipt of a low EOW signal. At the beginning of a search, a logical low signal is OMPI 1 applied in a well known manner to node 840a which is 2 connected to the reset (R) input leads of shift registers 3 835 and 836, thus resetting each bit within shift registers ^ 835 and 836 to logical zeros. Upon each subsequent EOW ^ signal, the data in shift registers 835 and 836 is shifted ° to the next most significant bit, with output data from SR 7 flip flops 833 and 834 being input to the least significant 8 bits of shift registers 835 and 836, respectively. Ac- cordingly, the signals appearing on output leads Tl through 0 Tj of shift register 835 indicate which one or ones of the 1 previous j words decoded was equal to "batb", and the 2 signals on the output leads PI through Pj of shift register 3 836 indicates which one of the previous j words decoded was equal to "ballb". In this example, it is desired to 5 locate occurrences of the word "batS" within four words of 6 the word "ballb". Accordingly, the four least significant 7 output leads of shift registers 835 and 836 are connected 8 to the input leads of NOR-gate 837 and 838, respectively. 9 Thus, NOR gate 837 generates a low output signal when the 0 word "batb" is one of the four most recently decoded 1 words, and similarly, NOR gate 838 provides a low output 2 signal when the word "ballb" has been one of the four most recently decoded words- The output leads of NOR gates 837 ^ and 838 are connected to the input leads of NOR gate 839, 5 thus providing a high output signal from NOR gate 839 which is available on node 840 when both the words "batb" 7 and "ballb" have been decoded within four words of each 8 other. The shift registers 835 and 836 are reset in a number of desired ways. First, as previously described, on beginning a search, shift registers 835 and 836 are cleared. Shift registers 835 and 836 are also cleared upon receipt of a high output signal from NOR gate 839, thus indicating that the desired words have been decoded within four words of each other. This reset procedure is designed to prevent erroneous multiple high signals on the output lead of NOR OMPI gate 839 under certain circumstances when the desired words have been decoded. For example, if the desired words are adjacent to each other, and shift registers 834 and 836 are not reset upon their first detection, NOR gate 839 will provide a high output signal when the desired words are the two most recently decoded words, the second and third most recently decoded words, and the third and fourth most recently decoded words, thus providing three signals for the same occurrence of the two desired words. Thus, by resetting shift registers 835 and 836 upon receipt of a high output signal from NOR gate 839, such erroneous multiple signals will be prevented. Finally, shift regi- sters 835 and 836 may, if desired, be reset upon receipt of an EOS signal, thus requiring the desired words to appea in the same sentence. Alternatively, shift registers 835 and 836 may be reset by the EOP signal or the EOD signal, thus requiring the desired words to be located within the same paragraph, or the same document, respectively. Figure 7b shows NOR gate 870 having its input leads connected to the .EOS signal, the output signal from NOR gate 839 appearing on terminal 840, and a signal labelled as "begin search", which is high when a search is to begin- Accordingly, NOR gate 870 will provide a low output signal which is connected to terminate 840a of Figure 7a to reset shift registers 835 and 836 at the beginning of each- search, at the end of each sentence, and upon detection of the desired words and their desired relationship by receipt of a high signal on terminal 840. Those of ordinary skill in the art, in light of the teachings of this invention, are also able to construct a logical operation section 14 may also be constructed which will detect the occurrence of a first desired word within a fixed number of sentences of a second desired word. Logical operator section 14 of Figure 7a may be used for this purpose with but a few modifications. For example, OMPI shift registers 835 and 836 will, in this instance, receiv their clock signals from the EOS signal, and flip flops 833 and 834 will be reset by a delayed EOS' signal applied to terminal 841- Furthermore, the NAND gate 870 of Figure 7b will receive as its input signals the EOP signal in place of the EOS signal, if it is desired that the two words appear within the same paragraph. Alternatively, the EOS signal applied to NOR gate 870 of Figure 7b is replaced by the EOD signal, when it is desired that the two desired words appear in the same document. Furthermore, it is to be understood that the decoder 12 and decoded data memory 13 (Figure 1) can be used with logical operator section 14 other than those specific embodiments provided in this specification. Similarly, the logical operator section 14 need not be used with the specific embodiments of decoder 12 and decoded data memory 13 provided in this specification. τ n e logical operator section 14 (Figure 1) can compris hardwired logical gates which serve to search for desired character strings. Alternatively, logical operator section 14 may comprise a large number of logical gates, including AND gates, OR gates, NOR gates, flip-flops, and the like, which may be programmably connected in order to provide the desired character search, in order to be highly flexible in performing searches. The use of cross- point switch arrays, and particularly such arrays imple- mented as integrated circuits, will be useful in the construction of logical operator section 14. One such 256 by 256 cross-point switching array is described in an article entitled "Cross-Point Array IC Handles 256 Voice and Data Channels", written by Lloyd Reaume and appearing i Electronics Magazine, October 6, 1981, pages 133-135. such a cross-point switch array is useful for connecting the plurality of output leads from the shift registers of decoded data memory 13 contained within bus 13a, the EOW, EOS, EOP, and EOD signals, as well as providing inter- connections between the logical gates of logical operators section 14. Utilizing a suitable computer program, the operation of such cross-point switch arrays within logical operators section 14 may be accomplished as a result of simple commands describing the desired search. The compute is programmed to receive the commands and operate the cross-point switch array in such a manner as to provide proper connection between the leads within bus 13a, the EOW, EOS, EOP and EOD leads, and the logical gates within logical operator section 14. As previously described, upon the decoding of the desired character string, logical operator section 14 generates a signal on bus 14a, which is connected to central processing unit (CPU) 15 (Figure 1). CPU 15 then operates as programmed, for example, to store the document number containing the desired character string, print the sentence containing the desired character string, and the like. SECOND EMBODIMENT System Overview second embodiment of a text comparator constructed in accordance with this invention is depicted in the block diagram of Fig. 8- Text comparator 80 includes mass storage device 111 which, as previously described in conjunction with the first embodiment of this invention, stores a large amount of textual data, often referred to as the "data base." Data stored in mass storage device in is transferred via bus Ilia and made available to word logic 112, delimiter logic 113, set logic 114, set combi- nation logic 115, proximity logic 117, and programming logic 116, as is fully described below. Delimiter logic 113 serves to monitor the characters transferred from mass storage device 111 on bus Ilia and provides discrete ( OMP V ~ VJP 1 signals depicting whether the character being transferred 2 is a predefined delimiter character. Such delimiter 3 characters include, for example, special characters or groups of characters denoting the end of a word (EOW), end ^ of a paragraph (EOP), end of a sentence (EOS), end of a ° document (EOD), end of a chapter (EOC), and the end of a 7 title (EOT). The delimiter signals provided by delimiter " logic " 113 are required in order to allow the text comparat 80 to determine, for example, when two specified words 10 occur within the same sentence or within the same paragrap 11 as is fully described below. \ 12 13 Word logic 112 serves to store data regarding pre- 1 defined words (i.e., strings of characters) which are to 15 be located within the text stored in mass storage device 16 111. Word logic 112 then provides output word signals on 17 bus 112a indicating when such predefined words have been 18 located in the character string being transferred from 1 mass storage device 111 via bus Ilia. These word signals 20 are transferred via bus 112a to set logic 114 and proximity 2i logic 117. 22 23 Set logic 114 receives the delimiter signals from 24 delimiter logic 113 via bus 113a and word signals from 25 word logic 112 via bus 112a and determines when selected 26 words are located in the same sentence, same paragraph, 27 etc., as desired, and provides output signals on bus 114a 28 indicating when predefined words or strings of characters 29 have been so located. 30 31 The output signals from set logic 114 are applied to 32 set combination logic 115, which serves to combine the 33 signals from set logic 114 in order to generate output 34 signals on output bus 115a indicating when the textual 3 355 information transferred from mass storage device 111 on 36 bus Ilia .meets the desired search strategy selected by the 37 user. Proximity logic 117 receives input signals from buses Ilia, 112a, 113a, and 114a and combines this information in order to provide output signals indicating when pre- defined words detected by word logic 112, or predefined set of words, as detected by set logic 114, or a combina- tion of this information, occurs within a predefined proximity. For example, proximity logic 117 will determine if a first selected word occurs within N (where N is a selected integer) words of a second preselected word. Programming logic 116 serves -to- receive search strateg instructions from the user and in response thereto provide the proper timing, addressing, and data signals via bus Ilia to word logic 112/ delimiter logic .113, set logic 114, set combination logic 115, and proximity logic 117 to cause to be stored within these elements the information required to perform the desired search strategy. While for ease and understanding word logic 112, delimiter logic 113, set logic 114, set combination logic 115, and proximity logic 117 will now be described in separate subsections of this specification, it is to be understood that each of these elements is, if required, programmed by programming logic 116 prior to the execution of a user defined textual search strategy. Delimiter Logic 113 Fig. 9 depicts the relationship between Figs. 9a through 9c which in turn form a schematic diagram of one embodiment of delimiter logic 113. Delimiter logic 113 provides on its output leads 9-6a, 9-7a, 9-8a, 9-10a, 9-12a, and 9-14a, delimiter signals indicating, for example the end of a word, end of a paragraph, end of a document, etc. These output leads 9-6a, 9-7a, 9-8a, 9-10a, 9-12a and 9-14a form bus 113a of Fig. 8. In many textual data base, the end of a word (EOW) is indicated by a non-blank character followed by a blank. This is preferred over the technique used by some textual data bases where the end of-a word is indicated simply by a blank character, because at the end of a sentence and at the end of a paragraph numerous blanks may occur in sequenc providing a corresponding plurality of undesired end of word signals. Similarly, an end of a sentence is often indicated by a period followed by two blanks, and an end of paragraph is indicated by a period followed by three blanks. The portion of the delimiter logic 113 shown in Fig. 9a serves to detect the occurrence of a blank, a non-blank character, and a period, and also combines these three characters in order to provide EOW, EOS and EOP signals on output leads 9-6a through 9-8a, respectively. The eight bit data word comprising bits DO through D7 is latched into latch 9-1 upon receipt of a clock signal (CLK) which is provided by mass storage device 111 on bus Ilia to indicate that a valid data word is present on bus 111a- Latch 9-1 comprises, for example, a 74373 device manufac- tured by National Semiconductor Corporation (hereinafter referred to as "National"). Latch 9-1 serves to store data received on bus Ilia and provide this data to the remainder of delimiter logic 113 until the next data word has been set onto bus Ilia. Thus latch 9-1 provides bits DO through D7 on leads 9-la through 9-lh. Each bit DO through D7 is uniquely applied to one input lead of exclu¬ sive OR gates 9-2al through 9-2a8, and are also uniquely applied to one input lead of exclusive OR gates 9-2bl through 9-2b8. The remaining input leads of exclusive OR gates 9-2al through 9-2a8 are connected either to a logical zero signal (typically zero volts) or a logical one signal (typically 5 volts) in order to program exclusive OR gates 9-2al through 9-2a8 so as to detect when a blank character is transmitted on bus Ilia. Similarly, the remaining input leads of exclusive OR gates 9-2bl through 9-2b8 are connected either to a logical zero signal or a logical one signal in order to program exclusive OR gates 9-2bl throug 9-2b8 so as to detect when a period is transmitted on bus Ilia. Referring to table 1, it is seen that in ASCII, a blank is a hexadecimal 20 (binary 00100000). Accordingly, the program ' leads of exclusive OR gates 9-2al through 9-2a8 (i.e., those leads not connected to data bits DO through D7 provided by leads 9-la through 9-lh, respectivel are programmed to the binary signal corresponding to the inverse of the binary signal representing a blank- Thus f the program leads of exclusive OR gates 9-2al through 9-2a8 are programmed to binary 11011111, respectively. In this manner, when a blank signal is transmitted on bus Ilia and stored in latch 9-1, the DO through D7 signals applied to each exclusive OR gate 9-2al through 9-2a8 are opposite the program signal applied to these exclusive OR gates, and each exclusive OR gate 9-2al through 9-2a8 provides a logical one output signal on its output lead. The output signals from exclusive OR gates 9-2al through 9-2a8 are applied to the input leads of NAND gate 9-3a. Thus, when a blank character is transmitted on bus Ilia, each input signal to NAND gate 9-3a is a logical one, and the blank output signal from NAND gate 9-3a is a logical zero, indicating that a blank character has been transmitted. Conversely, when a nonblank character is transmitted on bus Ilia and stored in latch 9-1, at least one exclusive OR gate 9-2al through 9-2a8 receives a data signal DO through D7 which is identical to the programming signal applied to that exclusive OR gate, and the output signal from that exclusive OR gate is a logical zero. Thus, the blank output signal from NAND gate 9-31 is a logical one, indicating that a nonblank character has been transmitted- ^JRE OMPI The output signal from NAND gate 9-3a is applied to the D input lead of D type flip-flop 9-4a. The Q output lead of flip-flop 9-4a is connected to the D input lead of D-type flip-flop 9-4b, whose Q output lead is in turn connected to the D input lead of D-type flip-flop 9-4c. Flip-flops 9-5a through 9-5d thereby providing signals indicating whether each of the last three characters transmitted was a blank or a nonblank character. D-type flip-flops- 9-4a through 9-4c comprise, for example, one flip-flop of a 74175 quad D-type flip-flop manufactured by National. Flip flops 9-4a through 9-4c each receive their clock signals from the Valid Data signal provided by mass storage device ill (Fig. 8) indicating that valid data is available on bus Ilia. "" "" Again referring to table 1, it is seen that in ASCII, a period is a hexadecimal 2Ξ (binary 00101110). Accordingl the program " leads of exclusive OR gates 9-2bl through 9-2b8 (i.e., those leads not connected to data bits DO through D7 provided by leads 9-la through 9-lh, respectivel are programmed to the binary signal corresponding to the inverse of the binary signal representing a period. Thus, the program leads of exclusive OR gates 9-2bl through 9-2b8 are programmed to binary 11010001, respectively. In this manner, when a period signal is transmitted on bus Ilia and stored in latch 9-1, the DO through D7 signals applied to each exclusive OR gate 9-2bl through 9-2b8 are opposite the program signal applied to these exclusive OR gates, and each exclusive OR gate 9-2bl through 9-2b8 provides a logical one output signal on its output lead. The output signals from exclusive OR gates 9-2bl through 9-2b8 are applied to the input leads of NAND gate 9-3b. Thus, when a blank character is transmitted on bus ilia, each input signal to NAND gate 9-3b is a logical one, and the 7 output signal from NAND gate 9-3b is a logical zero, indicating that the period has been transmitted. Conversely, when a nonperiod character is transmitted on bus Ilia and stored in latch 9-1, at least one exclusive OR gate 9-2bl through 9-2b8 receives a data signal DO through D7 which is identical to the programming signal applied to that exclusive OR gate, and the output signal from that exclusive OR gate is a logical zero. Thus, the 7 output signal from NAND gate 9-3b is a logical one, indicating that a non-period character has been transmitted The output signal from NAND gate 9-3b is applied to the D input lead of D type flip-flop 9-5a. The Q output lead of flip-flop 9-5a is connected to the D input lead of D-type flip-flop 9-5b, whose Q output lead is in turn connected to the D input lead of D-type flip-flop 9-5c ' , whose output lead is in turn connected to the D input lead of D-type flip-flop 9-5d, flip-flopts 9-5a through 9-5d, D-type flip-flops 9-5a through 9-5d comprise, for example, one flip-flop of a 74175 quad D-type flip-flop manufactured by National. Flip-flops 9-5a through 9-5d, each receive their clock signals from the Valid Data signal provided by mass storage device 111 (Fig. 8) indicat ing that valid data is available on bus Ilia. Because the end of a word is indicated by a nonblank character followed by a blank character, one input lead of NAND gate 9-6 is connected to the output lead of flip-flo 9-4b and one input lead of NAND gate 9-6 is connected to the Q ouput lead of flip-flop 9-4a. Thus, when the charac- ter most recently transmitted on bus Ilia is a blank, the output signal from flip flop 9-4a is a logical one. Similarly, when the preceding character transmitted on bus ilia is a nonblank character, the ζ) output signal from flip-flop 9-4b is a logical one. With both input leads of NAND gate 9-6 receiving logical one signals, the EOW output signal generated by NAND gate 9-6 and available on output lead 9-6a is a logical zero, indicating that the end of a- word has been detected. At all other times, OMPI either the Q output lead of flip flop 9-4a will provide a logical zero signal (indicating that the character most recently transmitted on bus Ilia is a nonblank character) or the output lead from flip flop 9-4b will provide a logical zero signal, indicating that the previously receiv character was not a nonblank character, or both, thereby causing NAND gate 9-6 to generate a logical one EOW signal. Similarly, because the end of a sentence is indicated by a period followed by two blanks, NAND gate 9-7, which generates a EOS signal on its output lead 9-7a, has one of its three input leads connected to each of the Q output leads of flip-flops 9-4a, 9-4b, and 9-5c. In this manner, when the two most recently received characters are blanks, flip-flops 9-4a and 9-4b provide logical one output signals, and when the character preceding these two blank characters is a period, flip-flop 9-5c provides a logical one Q output signal, thereby causing NAND gate 9-7 to generate a logical zero EOS signal on output lead 9-7a. • - • In a similar " manner, the end of a paragrah is indi- cated by a period followed by three blanks. Thus, NAND gate 9-8 has one of its input leads connected to each of the output leads of flip-flops 9-4a, 9-4b, 9-4c, and 9-5d. In this manner, when the three most recently receive characters are all blanks, flip flops 9-4a through 9-4c will provide logical one output signals to three input leads of NAND" 'gate 9-8. When the character preceding these three blanks is a period, flip flop 9-5d will provide a logical , one' Q output signal to the remaining input lead of NAND gate 9-8, thereby causing NAND gate 9-8 to generate a logical zero EOP signal on output lead 9-8a. Conversely, when the four characters most recently transmitted on bus Ilia are not a period followed by three blanks, at least one Q output signal from flip-flops 9-4a, 9-4b, 9-4c, and 9-5b will be a logical zero, thereby causing NAND gate 9-8 to generate a logical one EOP signal on output lead 9-8a indicating th^t the end of a paragraph has not been detecte Because the EOW, EOS and EOP signals are rather universally indicated by a non-blank character followed by a blank, a period followed by two blanks, and by a period followed by three blanks, respectively, it is preferable to utilize arrays of exclusive OR gates 9-2a and 9-2b, each exclusive OR gate having a programming lead hard wired to a logical zero or logical one potential, in order to detect the end of a word, end of a sentence, and end of a paragraph. However, the- EOD, EOC, and EOT signals oftentimes stored within mass memory device 111 utilizing a variety of special characters, depending on the database used. For example, one system might store an EOD signal in mass memory device 111 as a hexadecimal FF, while another system might store an EOD signal in mass storage device 111 as a hexadecimal FA. Accordingly, it is desir- able to provide delimiter logic 113 with the ability to be programmed in a manner that will allow delimiter logic 113 to detect the presence of the EOD, EOC and EOT signals, regardless of how those_ signals are stored in the mass storage device 111 of the particular system being used. The remainder of the delimiter logic 113 shown in Fig. 9 is capable of being programmed to detect any three desired characters stored within mass storage device 111. In this embodiment, these three characters detected by the circuit of Fig. 9 are the characters which are used to indicate the end of a document (EOD), the end of a chapter (EOC) and the end of a title (EOT). The programming of delimiter logic 113 occurs prior to the transfer of data from mass storage device 111 to bus Ilia for comparison. Prior to such transfer, programming logic 116 (Fig. 8) provides signals on bus Ilia which serves to pre-program delimiter logic 113 as to the characters stored in mass storage device 111 which .serve as the EOD, EOC and EOT delimiters. For example, programming logic 116 will first cause latch 9-9 (which comprises, for example a 74374 device manufactured by National) to store the inverse of the binary signal corresponding to the EOD delimiter character stored in mass storage device ill. Thus, for example, if the EOD delimiter characters stored in mass storage device 111 is a hexadecimal FF (binary 11111111) its inverse (binary 00000000) is stored in latch 9-9. This storage is performed by programming logic 116 providi on bus Ilia data bits DO through D7 equal to 00000000 and a suitable clock signal CLK to cause this data to be stored in latch 9-1. Programming logic 116 also provides an address signal of- 000 on address leads A0 through A2, respectively, of bus Ilia. The address signal 000 is applied to the address input leads of decoder 9-18 (which comprises, for example, a 74138 manufactured by National). Programming logic 116 also provides appropriate chip enable signals El through E3 to decoder 9-18, thereby enabling decoder 9-18. In response to these input signals, decoder 9-18 provides a positive going clock signal CLK 9-0 which is applied to latch 9-9. This positive going clock signal CLK 9-0 causes the data present on leads 9-la through 9-lh (i.e., the data stored in latch 9-1 by pro¬ gramming logic 116) to be stored within latch 9-9. This data is stored in latch 9-9 until programming logic 116 stores another eight bit word in latch 9-9. Generally, because a given data base will not change the delimiter character such as EOD, this data need be loaded into latch 9-9 only once upon installation of the equipment. However, in order to insure reliable operation of the delimiter logic 113, it may be desirable to periodically reload latch 9-9 with a binary 00000000 in order to insure that the proper data is stored in latch 9-9 despite any incipient failures which would cause the data stored within latch 9-9 to deviate from its intended value. During the operation of the text comparator, character data is transferred from mass storage device 111 (Fig. 8) OMPI to bus Ilia and, in addition to being compared by exclusive OR gate arrays 9-2a and 9-2b, is simultaneously compared with the data stored in latch 9-9 by exclusive OR gate array 9-2c to determine whether an EOD character has been transmitted on. bus Ilia. Thus, when an EOD character (hex FF) is transmitted on bus Ilia, a logical one signal will be applied to one input lead of each exclusive OR gate 9-2cl through 9-2c8 of exclusive OR gate array 9-2c. The data stored within latch 9-9 is continuously applied to the other input leads of exclusive OR gates 9-2cl through 9-2c8. Thus, when an EOD character is transmitted on bus Ilia, the data signals DO through D7 applied to one input lead of exclusive OR gates 9-2cl through 9-2c8 will be the inverse of the data which is applied by latch 9-9 to the other input lead of exclusive OR gates 9-2cl through 9-2c8, thereby causing each exclusive OR gate 9-2cl through 9-2c8 to provide a logical one signal on its output lead. These output signals are in turn applied to the input leads of NAND gate 9-10, thus causing NAND gate 9-10 to provide a logical zero EOD signal on output lead 9-10a, indicating that an EOD character is present on bus Ilia. Conversely, if a character other than an EOD character is transferred on bus Ilia, at least one exclusive OR gate 9-2cl through 9-2c8 receives a data signal DO through D7 which is identical to the data which that exclusive OR gate receives from latch 9-9, and the output signal from that exclusive OR gate is a logical zero, thus causing the EOD signal from NAND gate 9-10 to be a logical one, indi- eating that an EOD character has not been transferred on bus Ilia. in a similar manner, latch 9-11, exclusive OR array 9-2d, and NAND gate 9-12 provide an EOC signal on terminal 9-12a which indicates whether an end of chapter (EOC) character has been transferred on bus Ilia. Thus, for example, if an EOC character is hexadecimal FE (binary 11111110), prior to the textual comparison process, pro- gramming logic 116 provides a data signal D7 through DO equal to 00000001, and causes this signal to be stored in latch 9-11 by providing an A2 through A0 address signal of 001 which, together with appropriate enabling signals El through E3, in turn is applied to decoder 9-18, which in turn provides a positive going CLK 9-1 signal which is applied to latch 9-11. In this manner, when textual data is transferred from mass storage device 111 (Fig. 8) to bus Ilia, each textual character is compared by exclusive OR gate array 9-2d with the data stored in latch 9-11, and an EOC signal is made available on output terminal 9-12a indicating whether an EOC character, has been transmitted on bus Ilia. In a similar maner, latch 9-13, exclusive OR array 9-2e, and NAND gate 9-14 provide an EOT signal on terminal 9-14a which indicates whether an end of chapter (EOT) character has been transferred on bus Ilia. Thus, for example, if an EOT character is hexadecimal FD (binary lllllioi), prior to the textual comparison process, pro- gramming logic 116 provides a data signal D7 through DO equal to 00000010, and causes this signal to be stored in latch 9-13 by providing an A2 through A0 address signal of 010 which, together with appropriate enabling signals El through E3, in turn is applied to decoder 9-18, which in turn provides a positive going CLK 9-2 signal which is applied to latch 9-13. In this manner, when textual data is transferred from mass storage device 111 (Fig. 8) to bus Ilia, each textual character is compared by exclusive OR gate array 9-2e and and EOT signal is made available on output terminal 9-14a indicating whether an EOT character has been transmitted on bus Ilia. Naturally, for data base systems which utilize special characters to indicate EOW, EOS, and EOP, circuitry anal- ogous to latch 9-9, exclusive OR gate array 9-2c, and NAND gate 9-10 may be used in a similar manner as these circuit OMPI elements are used to detect an EOD character. Furthermore, the programming leads of exclusive OR gate arrays 9-2a and 9-2b need not be hard wired to logical zero or logical one signals, but rather could be wired to output signals available from a memory device, if desired. Still further, one or more of latches 9-9, 9-11, and 9-13 can be replaced by hard wiring the programming input leads of exclusive OR gate arrays 9-2c, 9-2d, and 9-2e, respectively, to appro- priate logical zero and logical one signals, although, as previously described, by utilizing latches 9-9, 9-11, and 9-13, the delimiter logic 113 of Fig. 9 can be utilized with any data base, regardless of the specific character which that data base uses as an EOD, EOC, and EOT character Word Logic 112 Referring to Fig- 12, the operation of word logic 112 will now be described. Fig. 12 depicts a portion of word logic 112 which is capable of detecting a predefined string of up to eight characters. Although not shown in Fig. 12, word logic 112 includes a latch (such as a 74373 device manufactured by National) provided between mass storage device 111 (Fig. 8) and bus Ilia, in order to store data output from mass storage device 111 and provide this data to the remainder of word logic 112 until the next data word has been made available by mass storage device 111. Naturally, other embodiments of this invention will become readily apparent to those of ordinary skill in the art in light of the teachings of this specification which will allow character strings of more than (or, if desired, less than eight characters to be detected. It is also to be understood that word logic 112 typically com- prises a plurality of the type of circuits shown in Fig. 12, in order that a plurality of character strings may be detected simultaneously. Thus, for example, in this embodiment word logic 112 contains a plurality of sixteen circuits of the type shown in Fig. 12, and thus a plurality of sixteen separate character strings, each character St _OM string comprising as many as eight characters, may be detected simultaneously as character data is transferred from mass storage device 111 on bus Ilia. Since each such circuit contained within word logic 112 is identical, the description of one such circuit as shown in Fig. 12 will fully describe the operation of word logic 112. By way of example, assume that it is desired to locate each occurrence of the word "knife" within the character data stored in mass storage device 111 (Figure 8) . Because this embodiment of word logic 112 is capable of detecting up to sixteen character strings simulaneously "knife" will be referred to as word 0 or W0 * to distinguish from other words being detected. First, the circuit of Fig. 12 is programmed in order to be able to detect each occurrence of the word "knife." To do this, programming logic 116 (Fig. 8) sequentially stores within each charact latch 17-0 through 17-7 a binary signal corresponding to the inverse of the binary signal representing each letter of the word "knife." Thus, programming logic 116 provides on bus Ilia address signals A4 through A0 of 0000, togethe with suitable enabling signals (not shown) to enable decoder 16. These address signals are applied to decoder i5 which comprises, for example, a 74154- manufactured by National. In response to this 0000 address signal, decode 16 provides a positive going chip enable 0 (CEO) signal, which is applied to character latch 17-0, thus causing the data bits D7 through DO provided on bus Ilia by programmin logic 116 to be stored in latch 17-0. Because the letter » " is depicted in ASCII as a binary 01101011, programming logic 116 provides a DO through D7 signal on bus Ilia of 10010100, which is stored in character latch 17-0. Next, programming logic 116 provides an address signal A4 through A0 of 0001, which, together with suitable enabling signals, cause decoder 116 to provide a positive going CE1 signal which is applied to character latch 17-1, & OMPI _ thus causing character latch 17-1 to store the D7 through DO signal provided by programming logic 116. At this time, programming logic 116 provides a D7 through DO signal of 10010001, the inverse of the binary signal " 01101110 which denotes the letter "n" in ASCII. In a similar manner, programming logic 116 sequentially gener- ates address signals which, together with suitable enabling signals, cause decoder 16 to provide positive going CE2 through CE7 signals, thereby causing data words provided by programming logic 116 to be stored in character latches 17-2 through 17-7, respectively- Since the selected word is "knife", the data which is stored in character latch 17-2 is a binary 10010110, corresponding to the inverse of the binary representation of the ASCII letter "i". The data stored within character latch 17-3 is a binary 1001100 (the inverse of the letter "f"), and the data stored within character latch 1.7-4 is a binary 10011010 (the inverse of the letter "e"). Because the word "knife" contains only five letters, it is unimportant what is stored in character latches 17-5 through 17-7, as the presence or absence of the characters detected by character latches 17-5 through 17-7 and their associated components will be masked by NAND-gates 22-5 through 22-7, respectivel in order to have no effect on the WORD0 output signal provided on output lead 112a-0. Output lead 112a-j?0 comprises one of the sixteen leads (leads 112a-l through 112a-15 not shown) forming bus 112a. Leads 112a-0 through 112a-15 provide word signals WOR 0 (W/J) through WORD15 (W15), respectively. The masking of unneeded characters is provided as follows. After loading the required data into latches 17-0 through 17—7, programming logic 116 sets onto bus Ilia an eight bit data word which defines which characters are to be masked by NAND gates 22-0 through 22-7. This eight bit mask word is stored in latch 20 (which may - comprise, for example, a 74374 manufactured by National) upon receipt of a clock signal provided by decoder 21 in response to the CE8 signal from decoder 16, whic is gener- ated in response to appropriate signals from ' programming logic 116. Decoder 21 comprises, for example, a 74138 manufactured by National. Because "knife" contains only five characters, the eight bit mask provided by programmin logic 116 and stored in latch 20 is a binary 00011111, indicating that the three characters detected by character latches 17-5 through 17-7 and their associated components are to be masked. After the programming of the character latches 17-0 through 17-7 and the masking latch 20 of the WORD circuit of Fig. 12, the character latches and masking latches of the WORD1 through WORD15 circuits are programmed in a similar manner in order to allow these WORD1 through WORD15 circuits to detect additional words simultaneously with the WORDj? circuit detecting occurrences of the word "knife". Mass storage device 111 then transfers its contents on a character-by-character basis to bus Ilia. Each data bit D7 through DO of each character transferred onto bus Ilia is applied to one input lead of a plurality of eight exclusive OR gates, each such exclusive OR gate being associated with one character latch 17-0 through 17-7. Thus, the DO bit is applied to one input lead of exclusive OR gate 18-0a associated with character latch 17-0, one input lead of exclusive OR gate 18-la associated with character latch 17-1,... and one input lead of exclusive OR gate 18-7a associated with character latch 17-7. The remaining input lead of each exclusive OR gate receives the appropriate bit from its associated character latch 17-0 through 17-7. Thus, exclusive OR gate 18-0a receives the DO signal from bus Ilia and the least significant bit stored in character latch 17-0. Similarly, exclusive OR gate 18-0b receives the DI signal from bus Ilia, and the second least significant bit stored in character latch 17-0, etc. Because character latch 17-0 stores the binary inverse of the first character "k" to be detected, when the chracter "k ,r is set onto bus Ilia, each exclusive OR gate 18-0a through 18 -Oh receives complementary input signals (i.e., one input signal is high, and the other input signals is low), and thus the output signal from each exclusive OR gate 18-0a through 18-0h is a logical one, which are in turn applied to the input leads of NAND gate 19-0, thus providing a logical zero k output signal from NAND gate 19-0. Conversely, if a character other than a "k" is set onto bus Ilia, at least one exclusive OR gate 18-0a through 18-0h receives identical signals on its input leads i.e. either both logical zero or both logical one), and thus that exclusive OR gate generates a logical zero output signal which causes NAND gate 19-0 to provide a logical one k output signal, indicating that the characte u k lf has not been detected. In a similar manner, the remaining character latches 17-1 through 17-4, and their associated exclusive OR gates and NAND gates, provide logical zero n, ϊ, f and e signals on the output lead of NAND gates 19-1 through 19-4 when the characters "n", "i", "f", and "e", respectively, are detected- At all other times, the signals on the output lead of NAND gates 19-1 through 19-4 are logical one. The output signals from NAND gates 19-0 through 19-7 are applied to one input lead of masking NAND gates 22-0 through 22-7, respectively- Masking NAND gates 22-0 through 22-7 mask the detected character signals provided by NAND gates 19-0 through 19-7 in accordance with the masking word stored within masking latch 20. The least significant bit stored in masking latch 20 is applied to the other input lead of NAND gate 22-0, the second least significant bit stored within that masking latch 20 is applied to the other input lead of NAND gate 22-1, etc., and the most significant bit stored in masking latch 20 is applied to the other input lead of NAND gate 22-7. Becaus the three most significant bits stored in masking latch 20 are zeroes, and these logical zeroes are applied to one input lead of NAND gates 22-5 through 22-7, NAND gates 22-5 through 22-7 always provide logical one signals on their output leads. Thus, even though the output signals from NAND gates 19-5 through 19-7 are applied to one input lead of NAND gates 22-5 through 22-7, respectively, these signals from NAND gates 19-5 through 19-7 have no effect on the output signals provided by NAND gates 19-5 through 19-7. Conversely, because the five least significant bits stored in masking latch 20 are logical ones, the output signals provided by NAND gates 22-0 through 22-4 will be the inverse of the signals provided by NAND gates 19-0 through 19-4, respectively. Thus, when the character "k" is set onto bus Ilia, NAND gate 19-0 provides a logical zero k signal to one input lead of NAND gate 22-0, which in turn provides a logical one k output signal. In a similar manner, when the letter "n" is set onto bus Ilia, NAND gate 22-1 provides a logical one n output signal; when the character "i" is set onto bus Ilia, NAND gate 22-2 generates a logical one i output signal; when the character "f" is set onto bus Ilia, NAND gate 22-4 generate a logical one f output signal; and when the character "e" i s set onto bus Ilia, NAND gate 22-5 generates a logical one e output signal. As previously described, NAND gates 22-5 through 22-7, corresponding to the detection of characters which are not of interest when searching for the character string "knife", always provide logical one output signals. The output signals from NAND gates 22-0 through 22-7 are applied to the input leads of shift registers 23-0 through 23-7, respectively. Shift register 23-0 is an eight bit shift register, shift register 23-1 is a seven bit shift register, shift register 23-2 is a six bit shift OMPI register, etc., and shift register 23-7 is a one bit shift register. Shift registers 23-0 through 23-7 are formed, for example, by the appropriate connection of a plurality of 74174 hex D-type flip flops manufactured by National. Shift registers 23-0 through 23-7 each receive a clock signal on input lead 23-7a which is provided by mass storage device 111 (Fig. 8) on bus Ilia, indicating that a valid data character is present on bus Ilia. The signals provided by NAND gates 22-0 through 22-7 are received by shift registers 23-0 through 23-7, and the content of each shift register 23-0 through 23-7 is shifted to the next most significant bit within that shift register upon receipt of each clock signal on lead 23-7a. In this manner, the output signals as provided by shift registers 23-0 through 23-7 depict the positional relationship of the detected characters. In order to provide a logical zero WORD0 signal indicating when the word "knife" is detected, and provide " a logical one WORD0 signal when the word "knife" is not detected, shift registers 23-0 through 23-7 are used. In this example, the character string "knifeαπα" is to be detected, where each "[-."indicates a "don't care" character. o detect the character string "knifeαππ", the most recentl detected character must be a "don't care" character, the second most recently detected character must also be a "don't care" character, the third most recently detected character must be a "don't care" character, the fourth most recently detected character must be the letter "e", the fifth most recently detected character must be a "f", the sixth most recently detected character must be an "i", the seventh most recently detected character must be an "n", and the eighth most recently detected character must be a "k". Accordingly, since the character "k" must be the eighth most recently detected character, the output signal from NAND gate 22-0, indicating when the character "k" has been detected, is applied to 8 bit shift register ^JRE OMPI 23-0. Similarly, since the letter "n" must be the seventh most recently detected character, the output signal from NAND gate 22-1, which indicates when the letter "n" has been detected, is applied to the input lead of seven bit shift register 23-1, etc. When the proper sequence of characters have been detected which spell "knifeαππ" the output signal from each shift register 23-0 through 23-7 is a logical one, which in turn is applied to the input leads of NAND gate 23-8, thus causing NAND gate 23-8 to provide a logical zero WORDj? signal on output lead 112a-0, thus indicating that "knife" has been detected. At all other times, at least one output signal from shift registe 23-0 through 23-7 is a logical zero, thus causing NAND gate 23-8 to provide a logical one o ^ signal on output lead 112a-0, thus indicating that "knife" has not been detected- It is apparent to those of ordinary skill in the art in light of the teachings of this specification that, if desired, word logic 112 can be programmed such that pro- gramming latches 17-0 through 17-7 and their associated components detect the character string "ππαknife", rather than "knifeαπα" as described above. In this event, the masking word stored in masking latch 20 will be 11111000, indicating that the three characters detected by character latches 17-0 through 17-3 and their associated components are to be masked by NAND gates 22-0 through 22-3, respec¬ tively. In this embodiment, where the "don't care" charac¬ ters precede the characters to be detected, the WORD0 signa goes low upon receipt of the last character in the characte string being detected, rather than j characters later, wher j is the number of "don't care" characters in the character string being detected (i.e., j=3 for "ππαknifes" ) . It is also apparent to those of ordinary skill in the art in light of the teachings of this specification that, if desired, word logic 112 can be programmed such that the OMPI programming latches 17-0 through 17-7 and their associated components detect the character string "efinkπππ". In this event, the masking words stored in masking latch 20 will be 00000111, indicating that the three characters detected by character latches 17-5 through 17-7 and their associated components are to be masked by NAND gates 22-5 through 22-7, respectively. In this event, however, shift register 23-0 is a one bit shift register, shift register 23-1 is a two bit shift register, shift register 23-2 is a three bit shift register, etc-, and shift register 23-7 is an eight bit shift register. it is also apparent to one of ordinary skill in the ar in light of the teachings of this specification that, if desired, word logic 112 can be programmed such that program latches 17-0 through 17-7 and their associated components detect the characters string "πππefink" . In this event, th masking word stored in masking latch 20 will be 11100000, indicating that the characters detected by character latche 17-0 through 17-2 and their associated components are to be masked by NAND gates 22-0 through 22-2, respectively. In this event, shift register 23-0 is a one bit shift register etc., and shift register 23-7 is an eight bit shift registe if it is desired to detect the occurrence of either upper case or lower case letters, the sixth least signifi- cant bit received from mass storage device 111 is held high and the word latches 17-0 through 17-6 are loaded with data to cause the detection of upper case letters forming the desired word. Alternatively, the sixth least significant bit received from mass storage device 111 is held low, and the word latches 17-0 through 17-6 are loaded with data to cause the detection of lower case letters forming the desired word. In either event, both upper and lower case letters will be detected by latches 17-0 through 17-6 and their associated components, as the sixth least significant bit, which distinguishes between upper and lower case, is effectively masked. In another embodiment of this inven- tion, the output signal from the sixth least significant exclusive nor gates 18-0b, 18-lb, . . . 16-6b, are held high, thereby effectively masking the sixth least signifi- cant bit and thus providing output signals when either upper or lower case letters are detected. Set Logic 114 Figs. 10a through lOd form a schematic diagram of set logic 114. Although not shown in Figure 10, set logic 114 includes a latch (such as a 74373 device manufactured by National) provided between mass storage device 111 (Figure 8) and bus 11a, in order to store data output from mass storage device 111 and provide this data to the remainder of set logic 114 until the next data word has been made available by mass storage device 111. Set logic 114 serves to determine when a set of selected words are detected within the same sentence, paragraph, document, etc., as defined by the user's search strategy. For example, that portion of set logic 114 shown in Fig. 10a detects when a predefined set of words 0 through 3 (i.e., a user defined set of W0 through W3 signals generated by word logic 112 (shown in Figs. 8 and 12) are detected within the same sentence or paragraph, etc. As previously described, the W0 through W3 signals are provided by word decode logic 112 (Fig- 12). Set logic 114 as shown in Fig. 12 is capable of receiving sixteen word signals (i.e., WO through W15, although it is apparent to one of ordinary skill in the art in light of the teachings of this specification that set logic 114 can be constructed to operate on any desired number of words which are each detected, for example, by a unique one of an equal number of circuits as shown in Fig'. 12 which form word logic 112. Furthermore, as will now be fully described, set logic 114 is capable of forming a plurality of sets, each set being generated by a plurality of four words. It is readily apparent to one of ordinary skill in the art in light of OMP 1 the teachings of this specification that set logic 114 can be constructed in order to form any desired number of 3 sets, each set being generated in response to any desired number of words. Because the embodiment of set logic 114 -> depicted in Fig- 10 is formed of four substantially identi- cal subcircuits (one such subcircuit being substantially 7 shown in each of Figs. 10a through lOd), the following 8 " description of the operation of the subcircuit of Fig. 10a 9 is sufficient to describe the operation of the entire set 0 logic 114 depicted in Fig. 10a through lOd. 1 2 Referring to Fig- 10a, leads 9-la through 9-lh are 3 connected to bus Ilia to receive the data signals DO 4 through D7, respectively. The delimiter signals (EOT, . EOC, EOD, EOP, EOS, and EOW) are received from delimiter 6 logic 113 (Figs- 8 and 9) on bus 113a. The W0 through W3 7 signals are received from appropriate portions of w.ord 8 logic 112 (Figs. 8 and 12) and applied to the SET 3 input 9 leads of SR latches 10-7a through 10-7d, respectively. Latches 10-7a through 10-7d serve to store data indicating when words 0 through 3, respectively, have been detected 2 by word logic 112- SR latches 10-7a through 10-7d each 3 comprise, for example, one of the four latches contained within a DM74279 device manufactured by National. 6 Multiplexer 10-3 selects the appropriate delimiter signal or ground, as will be fully described later) and, 8 in response thereto, provides a RESETA signal which is applied to the RESET (R) input leads of latches 10-7a through 10-7d, causing latches 10-7a through 10-7d to be reset to store logical zeros when the RESETA signal is a logical zero. Multiplexer 10-3 comprises, for example, a 74151 device manufactured by National. Latch 10-1 stores information provided by programming logic 116 (Fig. 8) on bus Ilia during the programming of the text comparator prior to executing a textual search strategy. Latch 10-1 comprises, for example, a 74373 device manufactured by National. Latch 10-8 (for example a 74374 device) serves to store masking information which is provided by programming logic 116 (Fig. 8) to latch 10-8 via bus Ilia during the programming of the text comparator of this invention prior to the execution of a user-defined textual comparison search strategy. Logical AND circuitry 10-36 combines the wT) through W3 signals in a logical AND and a logical NAND fashion and provides the SET1AND (S2AND) and the SET2AND (S1AND) signals on leads 10-14a and 10-16a, respectively. Similarly, the logical OR circuitry 10-37 combines the W0 through W3 signals in a logical OR and a logical NOR fashion and provides the SET10R (SIOR) and the SET10R (SIOR) signals on leads 10-13a and 10-15a, respectively. Logical AND circuitry 10-36 and logical OR circuitry 10-37, when masked by the masking data stored in masking latch 10-8, provide output signals which indicate whether the word 0 through 3 have been detected between two occur- rences of the signal selected by decoder 10-3, thereby providing output signals indicating whether words 0 throug 3 have been detected in the same sentence, for example. in order to program set logic 114, programming logic ιi6 (Fig. 8) first sets onto the DO through D7 data lines of bus Ilia the information which is to be stored in latch 10-1. Programming logic 116 then provides the appropriate A0 through A2 and El through E3 signals, thereby causing multiplexer 9-18 (Fig. 9a) to generate a positive going CLKlO-1 signal, which is applied to latch 10-1, thereby causing the DO through D7 data on bus Ilia to be stored within latch 10-1. The three least significant bits stored in latch 10-1 are applied to the address input leads of multiplexer 10-3, and similarly the next three least significant bits stored in latch 10-1 are applied to the address input leads of multiplexer 10-4. The three address signals applied to multiplexer 10-3 define which delimiter signal (or ground, if the input lead of multi- plexer 10-3 which is connected to ground, as shown, is OMPI , WnI xPiOs.) selected by multiplexer 10-4 in response to the address signals provided thereto by latch 10-1) are to generate the RESETA signal on the output lead of multiplexer 10-3. Ground is selected by multiplexor 10-3 in order to generat a RESETA signal when desired to reset the contents of flip-flops 10-7a through 10-7d, for example on power-up of the set logic 114. Next, programming logic 116 (Fig. 8) sets onto the " DO through D7 data leads of bus Ilia the masking data which is to be stored in masking latch 10-8. Programming logic 116 then sets onto bus Ilia the A0 through A2 and the El through E3 signals which cause demultiplexer 9-18 (Fig. 9a) to generate a positive going CLK10-2 signal, which in turn is applied to latch 10-8, thereby causing the data on leads DO through D7 of bus Ilia to be stored in latch 10-8- If required by the user defined search strategy, programming logic 116 then repeats these steps in order to program the remaining latches 10-2, 10-9, 10-10, and 10-11 of set logic 114. Assume, for example, that it is desired to locate within the textual information stored in mass storage device 111 all instances where the word "knife" (WORDO) occurs within the same sentence as the word "blood" (WORD1). Programming logic 116 programs word logic 112 as previously described, to cause WORDO to be the word "knife" and WORD1 to be the word "blood", thus causing a low W0 signal and a low WΪ signal to be generated upon detection of the words "knife" and "blood", respectively. Because it is desired to locate these two words only within the same sentence, the latches 10-7a through 10-7d must be reset upon receipt of the EOS delimiter signal. Accordingl programming logic 116 stores within latch 10-1 three least significant bits which, when applied to the address input leads of multiplexer 10-3, cause multiplexer 10-3 to select the EOS signal applied via bus 113a to generate the RESETA signal. Furthermore, because only WORDO and WORD1 are of interest in this particular search, programming 1 logic 116 causes to be stored in masking latch 10-8 an 2 eight bit mask which will cause the W2 and W3 signals to 3 have no effect on the output signals generated by the 4 logical AND logic circuitry 10-36. 5 6 Because in this example the words "knife" and "blood" 7 are to be combined a logical AND operation, the output signals from logical OR circuitry 10-37 are not used, and 9 thus the value of the four most significant bits stored in 10 masking latch 10-8 is unimportant. However, in order to 11 cause logical AND circuitry 10-36 to provide S1AND and SIAND output signals generated by the logical operation 13 S1AND = (Wl5 AND WΪ) the four least significant bits (D4 14 through DO) provided by programming logic 116 and stored 15 in latch 10-8 must be equal to 1100, respectively. In 16 this manner, the least significant bit stored in masking 17 latch 10-8 is a logical zero, which is applied to one 18 input lead of NOR gate 10-12h. With a logical zero signal 19 applied to one input lead of NOR gate 10-12h, the other 20 input lead of NOR gate 10-12h, which is connected to the O 2 1 output lead of flip flop 10-7a, controls the output signal 22 from NOR gate 10-12h. Similarly, with the second least 23 significant bit being a logical zero, which is applied to 24 one input lead of NOR gate 10-12g, the other input lead of 25 NOR gate 10-12g, which is connected to the output lead 26 of flip flop 10-7b, causes NOR gate 10-12g to generate its 27 output signal in response to the Wl signal stored in flip 28 flop 10-7b. Because the third and fourth least significan 29 bits stored in masking latch 10-8 are logical ones and are 30 each applied to one input lead of NOR gates 10-12f and 31 10-12e, respectively, NOR gates 10-12e and 10-12f always 32 provide logical zero output signals, indicating that the 33 w2 and W3 signals stores in latches 10-7c and 10-7d, 34 respectively (and thus WORD2 and WORD3) are unimportant 35. and form no part of the logical operation performed by 36 logical AND circuitry 10-36. 37 38 The output signals from NOR gates 10-12e through 10-12h are applied to the input leads of NOR gate 10-14. Because the output signals from NOR gates 10-12e and lθ-12f are always a logical zero, they will have no effect on the output signal generated by NOR gate 10-14. However, only when the output signals generated by NOR gates 10-12g and 10-12h are logical zeros, indicating that logical ones are stored in both shift registers 10-7a and 10-7b (i.e., logical zero WO and Wl signals have been received and thus logical one WO and Wl signals stored in flip flops 10-7a and 10-7b, respectively, since the last RESETA signal) will the S1AND output signal from NOR gate 10-14 be a logical one, indicating that the words "knife" and "blood" have both been located in a single sentence. As previously described, the RESETA signal is, in this example, generated by multiplexer 10-3 in response to the EOS signal. Accordingly, the data stored in latche 10-7a and 10-7d is reset to logical zeros in response to a logical zero RESETA signal. If after a logical zero RESETA signal the word "knife" is detected,, a logical zero o signal is applied to the 3 input lead of flip-flop 10-7a, thus causing a logical one to be stored in flip flop 10-7a. This generates a logical one Q output signal from flip-flop 10-7a which is applied to one input lead of NOR gate 10-12h, thus causing NOR gate 10-12a to generate a logical zero output signal- However, because the word "blood" (WORDl) has not been detected, a logical zero is still stored in shift register 10-7b, and shift register 10-7b provides a logical zero Q output signal which is applied to one input lead of NOR gate 10-12g. This, together with the logical zero input signal applied to its other input lead from latch 10-8, causes NOR gate 10-12g to provide a logical one output signal, thus causing NOR gate 10-14 to generate a logical zero SET1AND output signal, indicating that the words "knife" and "blood" have not both detected in the same sentence. If an EOS signal is now generated prior to the detection of the word "blood multiplexer 10-3 generates a logical zero RESETA signal and the shift registers 10-7a through 10-7d are reset to store logical zeros, thereby preventing an erroneous output signal from logical AND circuitry 10-36 should the word "blood" be detected in a subsequent sentence which does not also contain the word "knife". In a similar manner, if the search strategy requires the location of all occurrences of either the word "knife" or "blood" in the same sentence, the logical OR circuitry 10-37 is utilized. In this event, the four most significa masking bits stored in masking latch 10-8 by programming logic 116 are 0011. With the most significant bit from masking latch 10-8 being applied to one input lead of NAND gate 10-12a, NAND gate 10-12a always generates a logical one output signal, and thus the W3 signal stored in shift register 10-7d has no effect on the output signals generat by OR logic circuitry 10-37. Similarly, because the second most signficant masking bit stored in masking latch 10-8 is applied to one input lead of NAND gate 10-12b, NAND gate 10-12b always generates a logical one output signal, and thus the W2 signal stored in shift register io-7c has no effect on the output signal generated by logical OR circuitry 10-37. The third and fourth most significant masking bits stored in masking latch 10-8 are logical ones, and are applied to one input lead of NAND gates 10-12c and 10-12d, respectively. These logical one signals cause the output signals from NAND gates 10-12c and 10-12d to be generated in response to the W0 and Wl signals stored in flip-flops 10-7a and 10-7b, respectively, and applied to the other input lead of NAND gates 10-12d and 10-12c, respectively. If the word "knife" is detected, a logical zero WO signal is generated by word logic 112, and thus a logical one W0 signal is stored in flip-flop l0-7a. This logical one W0 signal causes NAND gate 10-12d to generate a logical zero output signal which causes NAND gate 10-13 to generate a logical one SIOR signal on output lead 10-13a (and causes inverter 10-5 to generate a logica zero SIOR signal on output lead 10-15a), thus indicating that the word "knife" has been detected. Similarly, if the word "blood" is detected, a logical zero WΪ signal is generated by word logic 112 and thus a logical one Wl signal is stored in flip flop 10-7b. This logical one Wl signal causes NAND gate 10-12c to generate a logical zero output signal, which in turn causes NAND gate 10-13 to generate a logical one SIOR signal on output lead 10-13a (and causes inverter 10-15 to generate a logical zero SIOR signal on output lead 10-15a), thus indicating that the word "blood" has been detected. If neither the word "knife" or the word "blood" is detected, flip flops 10-7a through 10-7d will each store a logical zero signal, NAND gates 10-12a through 10-12d each generate logical one output signals, NAND gate 10-13 generates a logical zero SIOR signal, and inverter 10-15 generates a logical one SIOR signal), thus indicating that neither "knife" or "blood" has been detected. . Set Combination Logic 115 set combination logic 115 serves to combine the set signals provided by set logic 114 (Figure 10) in accordanc with a user defined search strategy. Although not shown in Figure 11, set combination logic 115 includes a latch (such as a 74373 device manufactured by National) provided between mass storage device 111 (Fig. 8) and bus Ilia, in order to store data output from mass storage device 111 and provide this data to the remainder of set combination logic 115 until the next data word has been made available by mass storage device 111. Set combination logic 115 includes latches 11-2 and 11-3 (which comprise, for exampl 74374 devices manufactured by National) which store set combination words- provided by programming logic 116 in response to the user defined search strategy. Latches 11- and 11-3 store this information in response to the CLK11-6 and CLK11-7 signals, respectively, generated by decoder 9-17 (Fig. 9), as previously described). Set combination logic 115 also includes RS flip-flops 11-la through 11-lh which comprise, for example, 74279 devices manufactured by National. Shift registers 11-la through 11-lh store the SOOR, SIAND through S3OR, S3AND signals provided by set logic 114 (Figure 10). Flip-flops 11-la through 11-lh are reset by reset signal 11a provided by programming logic ' 116 (Fig. 8) when a search strategy is begun. Latch 11-2 stores the masking word provided by pro- gramming logic 116, in order to cause NAND gates ll-2a ' through ll-2h and their associated components to combine the set signals stored in flip flops 11-la through 11-lh in a logical OR function. For example, if it is desired to combine the SOOR and SOAND signals, programming logic 116 (Figure 8) causes latch 11-2 to store D7 through DO signals of 00000011, where the logical ones indicate which set signals are to be combined in the logical OR function. Thus, latch 11-2 provides logical zero signals to one input lead of NAND gates ll-2a through ll-2f, thereby causing the output signals from these NAND gates 11-2a through ll-2f to be logical ones. Latch 11-2 also provide logical one signals to one input lead of NAND gates ll-2g and ll-2h. The other input leads of NAND gates ll-2g and ll-2h are connected to the Q output leads of flip flops 11-la and 11-lb, respectively. Prior to the SOOR and SOAND signals going low, the output signals from flip-flo 11-la and 11-lb are logical zero, thus causing the output signals from ll-2g and ll-2h to be logical ones. This causes the output signal from NAND gate 11-3 to be logical zero, and the output signal from inverter 11-4 to be logical one. Thus, only when a logical zero SOOR signal or SOAND signal has been generated by set logic 114 (Fig. ιo), will the Q output signal from flip-flops 11-la or 11-lb be a logical one, thereby causing the output signal from NAND gates ll-2g and ll-2h to be a logical zero. With one input signal to NAND gate 11-3 a logical zero, the output signal from NAND gate 11-3 is a logical one, indicating that the logical OR combination of the set signals defined by the masking word stored in latch 11-2 has been met. This logical one signal from NAND gate 11-3 causes the output signal from inverter 11-4 be a logical zero, thereby causing the output signal from NAND gate 11-9 to be a logical one. in a similar manner, latch 11-3 stores a masking word provided by programming logic 116 in order to combine ; .the set signals applied to flip flops 11-la through 11-lh to be combined in a logical AND fashion. Thus, if it is desired to combine the SOOR signal with the SOAND signal in a logical AND function, latch 11-3 is programmed by programming logic 116 (Fig. 8) to store D7 through DO signals 11111100. With logical ones applied to one input lead of NOR gates ll-5a through ll-5f, the output signals from these NOR gates are logical zeroes. With logical zero signals applied by latch 11-3 to one input lead of NOR gates ll-5g and ll-5h, the output signals from NOR gates ll-5g and ll-5h will be logical zero only when both the SOOR and SOAND signals have been logical zero, thus causing logical one Q signals to be provided by both flip-flops 11-la and 11-lb, respectively. With the output signal from both NOR gates ll-5g or ll-5h logical zeros, the output signal from NOR gates 11-7 is logical one, and the output signal from NAND gate 11-8 is a logical zero, indicating that both SOOR and SOAND has been low. This causes the output signal from NAND gate 11-9 to be a logical zero. Thus, a logical zero on the output lead of NAND gate 11-9 indicates that either the logical OR function provided by latch 11-2 and its associated components or the logical AND function provided by latch 11-3 and its associated components, has been met. This logical zero output signal from NAND gate 11-9 is available on lead 115a-l to provide OMPI an interrupt signal to a central processing unit (CPU, not shown) if desired. This interrupt signal can be inverted by an inverter (not shown) if desired. This logical zero output signal from NAND gate 11-9 also provides a clock signal to latch 11-10 and which comprises, for example a 743734 device manufactured by National), thus causing the Q output signals from flip flops 11-la through 11-lh to be stored in latch 11-10. Terminal 11-lOa receives an output enable signal from the central processing unit, thereby causing the bits stored in latch 11-10 which indicate the status of the set signals received and stored within \ flip-flops 11-la through 11-lh, to be set onto bus Ilia for use by the central processing unit, if desired. Proximity Logic 117 Referring to Figure 13, the operation of proximity logic 117 will now be described- Proximity logic 117 includes a latch (such as a 74374 device manufactured by National) provided between mass storage device 111 (Figure 8) and bus Ilia, in order to store data output from mass storage device 111 and provide this data to the remainder of proximity logic 117 until the next data word has been made available by mass storage device Ilia. Proximity logic 117 serves to detect when a first selected word (detected by word logic 112 of Fig. 12) or set (detected by set logic 114 of Fig. 10) is located within a specific distance or proximity of a second selected word or set. For example, proximity logic 117 can be programmed to detect when a first word "knife" (detected by word logic 112 as, for example, word zero) is located within n words of a second selected word "blood" (detected by word logic 112 as, for example, word four), wherein n is a selected integer ranging from -7 to 7. Naturally, it is apparent to those of ordinary skill in the art in light of the teachings of this specification that alternative embodi- ments of proximity logic 117 can be constructed which will allow selection from a greater number of words or sets, and where the range of proximities can be any desired numbe including numbers greater than 7. Furthermore, proximity logic 117 allows detection of words or sets within a plural ity of n delimiter characters. Thus, proximity logic 117 i capable, for example, of detecting when a first selected word or set is located within n sentences, paragraphs, documents, etc., of a second selected word or set. The operation of the embodiment of proximity logic 117 shown in Figure 13 is as follows. Proximity logic 117 includes latches 13-2 and 13-5 which are programmed by.pro- gramming logic 116 to store address bits which in turn are applied to decoders 13-3 and 13-4, respectively, which cause decoders 13-3 and 13-4 to select which delimiter signal will provide clock signals CLK 13-1 and CLK 13-2, respectively. Latches 13-2 and 13-5 comprise, for example, 74374 devices manufactured by National- Latch 13-2 is pro- grammed by programming logic 116 setting onto bus Ilia the desired word to be stored, and appropriate address signals which cause decoder 16 (Figure 12) to generate a CE9 signal Latch 13-5 is then programmed by programming logic 116 setting onto bus Ilia the desired bits to be stored within latch 13-5, and appropriate address signals A3 through AO t cause decoder 16 to generate a CE11 signal. Latch CE10 (also a 74374 device) is then programmed in a similar manne to provide address signals to decoders 13-8 and 13-9, which in turn each select one of a plurality of word and set signals for use by proximity logic 117, as will be more fully understood with reference to the following discussion The data stored within latch 13-2 also provides three address bits to decoder 13-6, which causes decoder 13-6 to select the appropriate word or set signal to be applied to the input lead of shift register 13-11. In a similar fashion, latch 13-10, which is programmed by programming logic 116 when accessed by a CE10 signal generated by decoder 16 (Figure 12), provides address signals to decoder 13-8 and 13-9 which selects the appropriate set and word OMPI signals for input to shift registers 13-15 and 13-17. Two bits from latch 13-2 and one bit from latch 13-10 serve as address input signals to decoder 13-7, thereby selecting the appropriate word and set signals for input to shift register 13-13. Latches 13-2, 13-5, and 13-10 comprise, for example, 74374 devices manufactured by National. Decoders 13-3, 13-4, 13-6, 13-7, 13-8, and 13-9 comprise, for example 74151 devices manufactured by National. The operation of shift register 13-11, latch 13-12, and their related components is identical to the operation of shift register 13-13 and latch 13-14, shift register 13-15 and latch 13-16, and shift register 13-17 and latch 13-18, and their related components, and thus only the operation of shift register 13-11 and latch 13-12 and their associated components will be described here. Shift registers 13-11, 13-13, 13-15 and 13-17 comprise, for example 74164 serial in-parallel out shift registers manufactured by National. Latches 13-12, 13-14, 13-16, and 13-18 comprise, for example, 74374 devices manufacture by National. Latch 13-12 is programmed by programming logic 116 in response to a CE12 signal generated by decode 16 (Figure 12) in response to the appropriate A3 through AO signals provided by programming logic 116. Latch 13-12 stores an eight bit proximity word which defines the desired proximity of the words or sets being searched. Shift register 13-11 stores signals representing the relative position of the set or word selected by decoder i5 . The bits stored in latch 13-12 indicate which posi- tions within shift register 13-11 are of interest in the search strategy. For example, if it is desired to find word zero within two words of word seven (i.e., "undirected proximity), programming logic 116 programs latch 13-2 to cause decoder 13-6 to select the W0 signal, and decoder 13-7 to select the w7 signal. Furthermore, programming logic 116 programs latch 13-12 to store 00000111, and latch 13-14 to store 00000111. Programming logic 116 programs latch 13-2 to cause decoder 13-3 to select the 2θ"w signal as the CLK13-1 signal, thus causing the WO and W7 signals selected by decoders 13-6 and 13-7, respectively to be shifted into shift registers 13-11 and 13-13, respec- tively, on each EOW signal. With the four most significant bits of latch 13-12 logical zeroes, NAND gates 13-19a through 13-19e are disabled, thereby providing logical one output signals regardless of the contents of the five most significant bits of shift register 13-?11. However, because.the three least significant; bits- stored i -latch 13-?12-: re logical " ones, the output signals, from -NAND. gates .13-19f, through •- 13-19h are the logical inverse of the three least signifi- cant bits of shift register.13-11. . Thus,- if a logical one is stored, in any of the three least significant bits of shift register 13-11, the output signal from the associated NAND gate 13-19f through 13-19h is a logical zero, thus - causing NAND gate 13-23 to generate a logical one output signal. Thus, when both word zero and word seven appear within the last three words decoded (i.e., word zero is within two words of word 7), the output signal from NAND gates 13-23 and 13-24 are both logical ones, and thus the output signal from NAND gate 13-27a is a logical zero, indicating that word zero and word seven have been located within two words of each other. In a similar manner, NAND gates 13-27b through 13-27h provide output signals based on the appropriate logical combinations of the output signals from NAND gates 13-23 through 13-26. Latch 13-5 also provides three address signals to decoder 13-28 (which comprises, for example, a 74151 device as manufactured by National) which in turn selects the output signals from one of NAND gates 13-27a through 13-27h to provide an interrupt signal on terminal 13-50. This interrupt signal is used to indicate to a central processing unit (not shown) that the text comparato of this invention has detected the occurrence of the desired words or sets of words defined by the search strategy, as defined by the output signal from the NAND gate 13-27a through 13-27h which has been selected by decoder 13-28. in one embodiment of this invention, proximity logic 117 also includes latch 13-29, which comprises, for exampl a 74374 device as manufactured by National. Latch 13-29 stores the output signals provided by NAND gates 13-27a through 13-27h, and thereby allows the central processing unit (not shown) to determine the value of the signals provided by NAND gates 13-27a through 13-27h at any desire time. In one embodiment of this invention, one eight bit word representing the output signals from NAND gates 13-27a through 13-27h is stored in latch 13-29, and is made available to a central processing unit (not shown) on bus Ilia. Proximity logic 117 is also capable of detecting a so-called "directed" proximity of words or sets of words. In this event, the eight bit proximity word stored in latches 13-12, 13-14, 13-16, and 13-18 will contain only a single logical one bit, thereby causing proximity logic ιi7 to provide an output signal indicating when a first word or set is located within a precise proximity of a second selected word or set. Thus, for example, proximity logic 117 can be programmed to detect the occurrence of word zero in a location which is exactly n words after the occurrence of word seven, for example, where n is an integer ranging from -7 to +7. Thus, if it is desired to locate the occurrence of word 0 which is precisely four words after word 7, decoder 13-6 selects word 0, decoder 13-7 selects word 7, latch 13-12 stores 00000001, latch 13-13 stores 00010000, and decoder 13-28 selects the output signal from NAND gate 13-27a, thus providing an interrupt signal on output lead 13-50 when word 0 is located exactly four words after word 7. V_ O MP Alternatively, if it is desired to locate the occur- rence of word 0 which is precisely four words before word 7, decoder 13-6 selected word 0, decoder 13-7 selects word 7, latch 13-12 stores 00010000, latch 13-13 stores 00000001 and decoder 13-28 selects the output signal from NAND gate 13-27a, thus providing an interrupt signal on output lead 13-50 when word 0 is located exactly four words before word 7. Furthermore, if it is desired to locate the occurrence of word 0 which is. within four,words before,word.7 r (i;.e., -; word 0 is the first, second, third.or fourth. ord before word 7), decoder 13-6 selects word 0, decoder 13-7 selects word 7, latch 13-12 stores 0011110, latch 13-13 stores 00000001, and decoder 13 ÷ 28 selects the output signal from NAND gate 13-27a, thus providing an interrupt signal on output lead 13-50 when word 0 is located within four words before word T. it is also understood to one of ordinary skill in the art in light of the teachings of this specification, that proximity logic 117 can be constructed to detect the occurrence of greater combinations of words and sets, merely by expanding the number of latches, decoders, and shift registers, and logic gates 13-27a through 13-27h, in order to detect more complex search strategies. : .-. - . . . .- While this specification has explained the operation of this invention in conjunction with several specific embodiments, it is to be understood that this specifi- cation is not to operate as a limitation on the scope of the invention. Many other embodiments of this invention will become apparent to those skilled in the art in light of the teachings of this invention.

Claims: I CLAIM: 1. A textual comparison system for locating desired character strings within textual material comprising: ' ' means for receiving stored textual characters; means for decoding said stored textual character thereby providing decoded characters;' means for storing said decoded characters and information as to the relative positioning of said decoded characters; means for comparing said decoded characters and said information as to the relative positioning of said decoded characters, whereby the presence of desired character strings is determined; and means for providing a signal indicating that a desired character string has been located. 2. Structure as in claim 1 wherein said means for decoding said stored textual characters comprises a plural of N output leads, where N is an integer equal to the number of unique textual characters which are to be decode and each of said N output leads provides a signal when a unique one of said textual characters associated with said output lead has been decoded. 3. Structure as in claim 1 wherein said means for storing said decoded characters and information as to the relative positioning of said decoded characters comprises a plurality of N shift registers, where N is an integer equal to the number of unique textual characters which are to be decoded, and where each of said plurality of N shift registers is associated with a unique one of said N textual characters. OMPI 4- Structure as in claim 2 wherein said means for storing said decoded characters and information as to the relative positioning of said decoded characters comprises a plurality of N shift registers, where N is an integer equal to the number of unique textual characters which are to be decoded, and where each of said plurality of N shift registers is associated with a unique one of said N textua characters. 5. Structure as in claim 4 wherein each said shift registers receives as an input data signal the signal oh the output lead of said decoder means associated with the unique textual character associated with said shift regist 6. Structure as in claim 5 wherein each said shift register is clocked once upon the decoding of each charact which is decoded by said decoder means. 7. Structure as in claim 6 wherein each said shift register is ' capable of storing a. plurality of K bits, where K is a positive integer, and the data stored within said N shift registers indicates which textual characters have been decoded and the relative position of said textua characters within said textual material. 8. Structure as in claims 1, 2, 3, 4, 5, 6 or 7 wherein said textual characters are stored' in ASCII and N s equal to 96. 9. Structure as in Claim 7 wherein said means for comparing comprises a plurality of logical gates, each said logical gate corresponding to one character string to be decoded and wherein each said logical gate comprises: a plurality of K input leads corresponding to an equal plurality of K characters comprising a desired character string, said input lead corresponding to OMPI 1 the kth character (where kth is an integer given by 2 l≤/≤K) from the end of said desired character string 3 being connected to the kth least significant bit of 4 said shift register associated with said kth characte 5 " 6 10. Structure as in Claim 9 wherein said signal on 7 each of said output leads of said decoder means is a 8 logical zero only when said character associated with said 9 output lead has been decoded. 10 11. = 11- structure as in Claim 10 wherein said logical 12 gate comprises a NOR gate and the output signal from said 13 NOR gate is a logical one when said desired character 4 string has been located. 15 6 12. Structure as in Claim 9 which further includes a 7 plurality of J (where J is a positive integer less than or 8 equal to K) latches for storing information as to whether 9 an associated- one of J character strings has been located. 0 1 ' ' 13. Structure as in Claim 12 which further includes 2 a logical gate having input leads connected to the output 3 leads of said latches, thereby providing an output signal 4 indicating whether all of said J character strings have 5 been located. 6 7 14. Structure as in Claim 13 wherein said- latches 8 are reset at the beginning of each document, thereby 9 causing said logical gate to provide an output signal 0 indicating whether all of said J character strings have 1 been located within the same document. 2 3 15. Structure as in Claim 13 wherein said latches 4 are reset at the beginning of each paragraph, thereby 5 causing said logical gate to provide an output signal 6 indicating whether all of said J character strings have 7 been located within the same paragraph. 8 OMPI __ 16. Structure as in Claim 13 wherein said latches are reset at the beginning of each sentence, thereby causing said logical gate to provide an output signal indicating whether all of said J character strings have been located within the same sentence. 17. In a textual comparison system, a word counter comprising a word counter shift register which is clocked upon receipt of a signal indicating the end of a word, wherein a first signal clears said shift register and provides a first' input signal to said word counter shift register, and wherein input signals to said word counter shift register other than said first input signal are opposite said first input signal, whereby the location of said first input signal within said word counter shift register indicates the number of words decoded since the receipt of said first signal. 18. Structure as in Claim 17 wherein said first signal is an end-of-sentence signal and the location of said first input signal within said word counter shift register indicates the number of words decoded in the present sentence being decoded. 19. Structure as in Claim 17 wherein said first signal is an end-of-paragraph signal and the location of said first input signal within said word counter shift register indicates the number of words decoded in the present paragraph being decoded. 20. Structure as in Claim 17 wherein said first signal is an end-of-document signal and the location of said first input signal within said word counter shift register indicates the number of words decoded in the present document being decoded. 21. In a textual comparison system, a sentence counter comprising a sentence counter shift register whic is clocked upon receipt of a signal indicating the end of a sentence, wherein a first signal clears said shift register and provides a first input signal to said senten counter shift register, and wherein input signals to said sentence counter shift register other than said first input signal are opposite said first input signal, whereby the location of said first input signal within said word counter shift register indicates the number of sentences decoded since the receipt of said first signal- 22. Structure as in Claim 21 wherein said first signal is an end-of-paragraph signal and the location of said first input signal within said sentence counter shift register indicates the number of sentences decoded in the present paragraph being decoded. 23. Structure as in Claim 21 wherein said first signal is an end-of-document signal and the location of said first input signal within said sentence counter shift register indicates the number of sentences decoded in the present document being decoded. 24. In a textual comparison system, a paragraph. counter comprising a paragraph counter shift register which is clocked upon receipt of a signal indicating the end of a paragraph, wherein a first signal clears said shift register and provides a first input signal to said paragraph counter shift register, and wherein input signal to said paragraph counter shift register other than said first input signal are opposite said first input signal, whereby the location of said first input signal within said paragraph counter shift register indicates the number of paragraphs decoded since the receipt of said first signal. OMPI 25. Structure as in Claim 24 wherein said first signal is an end-of-paragraph signal and the location of said first input signal within said paragraph counter shift register indicates the number of paragraphs decoded in the present paragraph being decoded. 26. - A textual comparison system for locating within textual material the occurrence of a first desired character string within a selected number of K (where K is a positive integer) words of a second desired character string comprisin first means for locating within textual material the presence of said first desired character string, said first means for locating providing a first signal indicating whether said first desired character string has been located; second means for locating within textual material - the presence of said second desired character string, said second means for locating providing a second signal indicating whether said second desired character has been located; a first shift register which receives as an input signal said first signal; a second shift register which receives as an input signal said second signal; means for clocking said first shift and second shift registers at the end of each word within said textual material; a first logical gate having a plurality of K input leads connected to the K least significant output leads of said first shift register, and wherein said first logical gate provides a first output OMPI signal indicating whether said first desired characte string is located within the previous K words; a second logical gate having a plurality of K input leads connected to the K least significant output leads of said second shift register, and wherein said second iόgical gate provides a second output signal ' indicating whether said second desired character string is located within the previous K words; and .-. a third logical gate receiving as input signals said first and said second output signals, thereby providing a third output signal indicating whether said first desired character string is located within K words of said second desired character string. 27. Structure as in Claim 26 wherein said first and second shift registers are reset at the end of each docume whereby said third logical gate provides a signal indi- eating whether said first desired character string is located, within K words of said second desired character string within the same document. 28. Structure as in Claim 26 wherein said first and second shift registers are reset at the end of each para- graph whereby said third logical gate provides a signal indicating whether said first desired character string is located within K words of said second desired character string within the same paragraph. 29. Structure as in Claim 26 wherein said first and second shift registers are reset at the end of each sentenc whereby said third logical gate provides a signal indi- eating whether said first desired character string is located within K ' words of said second desired character string within the same sentence. O 30. A textual comparison system for locating within textual material the occurrence of a first desired characte string within a selected number of K (where K is a positive integer) sentences of a second desired character string comprising: •= • first means for locating within textual material the presence of said first desired character string, said first means for locating providing a first signal indicating whether said first desired character string has been located; second means for locating within textual material the presence of said second desired character string, said second means for locating providing a second signal indicating whether said second desired characte has been located; a first shift register which receives as an input signal said first signal; a second shift register which receives as an input signal said second signal; means for clocking said first shift and second shift registers at the end of each sentence within said textual material; a first logical gate having a plurality of K input leads connected to the K least significant output leads of said first ' shift register, and wherein said first logical gate provides a first output signal indicating whether said first desired character string is located within the previous K sentences; a second logical gate having a plurality of K input leads connected to the K least significant OMPI output leads of said second shift register, and wherein said second logical gate provides a second output signal indicating whether said second desired character string is located within the previous K sentences; and : ; a third logical gate receiving as input signals said first and said second output signals, thereby providing a third output signal indicating whether said first desired character ' string is located within K sentences of said second desired character string. 31. Structure as in Claim 30 wherein said first and second shift registers are reset at the end of each docume whereby said third logical gate provides a signal indi- eating whether said first desired character string is located within K sentences of said second desired characte string within the same document. 32. Structure as in Claim 30 wherein said first and second shift registers are reset at the end of each para- graph whereby said third logical gate provides a signal indicating whether said first desired character string is located within K sentences of said second desired characte string within the same paragraph. 33.. A textual comparison system for locating within textual material the occurrence of a first desired characte string within a selected number of K (where K is a positive integer) paragraphs of a second desired character string comprising: first means for locating within textual material the presence of said first desired character string, said first means for locating providing a first signal indi- eating whether said first desired character string has been located; OM second means for locating within textual material the presence of said second desired character string, said second means for locating providing a second signal indicating whether said second desired characte has been located; a first shift register which receives as an. input signal said first signal; a second shift register • which receives as an input signal said second signal; means for clocking said first shift and second shift registers at the end of each paragraph within said textual material; a first logical gate having a plurality of K input leads connected to the K least significant output leads of said first shift register, and wherei said first logical gate provides a first output signal indicating whether said first desired characte string is located within the previous K paragraphs; a second logical gate having a plurality of K input leads connected to the K least significant output leads of said second shift register, and wherein said second logical gate provides a second output signal indicating whether said second desired character string is located within the previous K paragraphs; and a third logical gate receiving as input signals said first and said second output signals, thereby providing a third output signal indicating whether said first desired character string is located within K paragraphs of said second desired character string. 34. Structure as in Claim 33 wherein said first and second shift registers are reset at the end of each docume whereby said third logical gate provides a signal indi- eating whether said first desired character string is located within K paragraphs of said second desired charact string within the same document. * . i . 35. The structure as in claim 1 wherein said means for decoding includes means for being programmed to detect only those characters forming a part of said character string. 36. The structure as in claim 35 wherein said means for decoding comprises a plurality of programmable latches for storing information defining the character string to be detected, means for comparing each received character with the information stored in said plurality of programma latches, and means for providing an output signal indicati when the characters being received form the desired charac string. 37. In a textural comparison system, a structure for detecting the presence of a delimiter character, comprisin means for receiving stored characters, means for receiving a signal defining a delimite signal being detected; means for storing said signal defining a delimit signal being detected; means for comparing said signal defining a delmiter signal being detected with a received character; and means for providing an output signal when said received character matches the delimiter signal being detected. 38. Structure as in claim 37 wherein said means for storing comprises: means for storing a plurality of textual charac- ters; means for providing a plurality of character output signals each uniquely associated with one of said plurality of textual character; and means for comparing the relative positions of said plurality of character output signals, thereby providing an output signal when said relative positio of said plurality of character output signals defines the delimiter signal being detected. 39. Structure as in claim 37 wherein said delimiter signal is selected from the group of delimiter signals consisting of END of WORD, END of SENTENCE, END of PARAGRA END of CHAPTER, END of TITLE, and END of DOCUMENT. 40. Structure as in claim 38 wherein an END of WORD delimiter is defined by the presence of a nonblank charact followed by a blank- . . 41- Structure as in claim 38 wherein an END of SENTENCE delimiter is defined by the presence of a period followed by two blanks. 42. Structure as in claim 38 wherein an END of PARA¬ GRAPH delimiter is defined by the presence of * a period followed by three blanks. 43. In a textual comparison system, set logic for combining a plurality of word signals indicating predefine words have been located between pairs of a predefined delimiter signal, comprising: means for receiving a plurality of word signals, means for storing said plurality of word signals; means for receiving a plurality of delimiter signals; means for storing information defining which of said plurality of delimiter signals is said predefined delimiter signal; means for resetting said means for storing said plurality of word signals in response to said prede- fined delimiter signal; means for combining in a logical operation said word signals stored within said means for storing said plurality of word signals and providing a SET output signal; and means for masking selected output signals from said means for storing said plurality of word signals so as to cause these signals to have no effect on said SET output signal. 44. In a textual comparison system, set combination logic for combining a plurality of set signals indicating when desired sets of characters have been detected, comprisin means for receiving a plurality of set signals; means for storing said plurality of set signals; means for combining said set signals in a logical operation and providing a SET combination output signal; means for masking selected ones of said plurality of set signals, thereby causing said selected ones of said plurality of set signals from having no effect on said SET combination logic output signal. 45. In a textual comparison system, proximity logic for detecting when a first selected word or set of words is located within a selected proximity of N delimiter characters from a second selected word or set of words, comprising: means for receiving a plurality of signals indicating when selected words or sets of words have been detected; - o - means for selecting from said plurality of signals a first selected signal and a second selected signal; means for receiving a delimiter signal; means for storing the relative positions of said first and second selected signals and providing relative position signals; - means for storing masking information; means for combining signals indicating the relative position of said first and second selected signals; means for masking selected ones of said relative position signals in response to said masking informa¬ tion; and means for providing an output signal when said first and second selected word is located within the desired proximity. 46. Structure as in Claim 45 wherein said proximity logic further comprises: -.,- means for receiving a plurality of types of delimiter signals; and means for storing information indicating which of. said plurality of types of delimiter signals is of interest.

Inventors: SKINNER JR JAMES T, SKINNER, JR., JAMES, T.
Applicants: SKINNER JR JAMES T, SKINNER, JR., JAMES, T.
Application year: 1983
Main classification: G06F7
IPC codes: G06F13, G06F17