A MIS INTEGRATED CIRCUIT DEVICE PROTECTED FROM STATIC CHARGE

Abstract: An IC circuit is protected from static charge break down by a protection circuit, which has a diffusion region (22) and a conductive pattern (25). The diffusion region works as a clamp diode and as a series resistor. The conductive pattern connects the clamp diode to the input line (27) of the IC. The conductive pattern has an elongated form. It separates the input line from the contact point (24) of the clamp diode which is severely heated during leakage of static charge through the diode. The conductive pattern is made from a high melting point metal or metal silicide to prevent it melting. A polysilicon layer (28) may be sandwiched be­ tween the conductive pattern and the substrate (21) to prevent migration of atoms from the conductive pattern to the substrate.

Description: A MIS INTEGRATED CIRCUIT DEVICE PROTECTED FROM STATIC CHARGE The present invention relates to MIS (Metal Insulator Semiconductor) type integrated circuits (ICs) protected from damage caused by static charge. It involves a protection circuit placed between an input terminal and the IC circuit, to decrease the susceptibility of the IC to static charge break down. Static charge break down is a problem affecting ICs during handling, especially MIS type ICs. As a result, some ICs which have been passed by testing nevertheless malfunction when mounted on a printed circuit board. The problem of static charge break down is to some extent inherent for an MIS IC because, in general, an input terminal of the MIS IC will be connected to a gate electrode of a MIS transistor. The gate electrode is insulated by a gate oxide layer, whose electric insulation factor is very high, so the gate is apt to be charged to a high voltage by static charge. The break down voltage (gradient) of gate oxide is about 7 x 106 V/cm. The thickness of gate oxide layer, in recent MIS ICs, especially for large scale integrated circuits (iso), is as little as 300 to 1000 A0 This means that a voltage from static charge of about 20 to 70 V is sufficient to break down the insulating gate oxide layer, so destroying the MIS transistor. In order to avoid this problem, a MIS IC is usually provided with a protection circuit whose equivalent circuit is shown in Fig.l. A clamp diode Di has a break down voltage less than that of the gate, namely about 15 to 60 V, and so breaks down more easily than the gate when static charge is present. The static charge thus leaks through the diode to the substrate, and the gate oxide layer is protected from break down. When static charge is given a conducting path, a surge of voltage results. The series resistor R , and inner capacitance Cgf which comprises the gate capacitance and stray capacitance of the wiring circuit, make up a delay circuit, which limits the surge of voltage presented to the IC, until the static charge has leaked to the substrate. In the above mentioned protection circuit, the clamp diode and the series resistance are usually fabricated by a diffusion process. The junction between the diffused region and the substrate works as a clamp diode, and the inner resisEance of the diffused region works as a series resistor. As the required resistance of ICs against static charge increases, it becomes apparent that such a protection circuit has some weaknesses. Fig. 2 shows schematically the structure of a formerly used static charge protection circuit. In the Figure, (a) is a plan view and (b) is a cross sectional view, sectioned substantially along the chained line A-A' in (a). 1 is a semiconductor substrate, 2 is a diffusion region, 3 is an isolation layer, 4 is a contact window for wiring, and 5 is an input line made of aluminium. In such a protecting circuit, when a surge voltage is introduced to the input line 5, the junction break down current of the diffusion region 2, which works as a clamp diode, concentrates mainly at the point where the input line 5 is connected to the region 2. So, the temperature of the portion designated H in Fig. 2(b) becomes very high. Consequently, in a structure in which the aluminium input line is connected directly to the diffusion region, as shown in Fig.2, a portion of the aluminium line close to the contact point B melts causing a disconnection. In some cases the melted aluminium penetrates deep into the diffusion region 2, damaging the junction and causing a short circuit of the input line 5 to the substrate. It should be noted that usually a voltage surge is induced by rapid change of current, but in the present context a surge occurs by break down of or touching to the accumulated charge. The impulsive effect is the same in both cases for an IC. The term surge should be understood to have this broader meaning hereinafter. Trial proposals have been made for overcoming this problem. Fig. 3 shows one example. The Figure shows parts of a protection circuit corresponding to parts shown in Fig.2. 1 is a semiconductor substrate, 2 is a diffusion region, and 3 is an insulation layer. Again, (a) and (b) in the Figure are a plan view and a cross sectional view, respectively. As can be seen in the Figure, the contact window 4 is filled with conductive polycrystalline silicon (polysilicon) 6. The input line 5 is connected to the diffusion region 2 via the polysilicon 6. In the Figure another insulation layer 3' is shown. This layer is an oxidized layer of polysilicon produced in the process of fabricating the contact 6. The input line 5 is contacted to the polysilicon 6 through a contact window 4' opened in the insulation layer 3'. The structure of Fig.3 is intended to prevent the melting of the contact portion by inserting polysilicon, which has a high melting point, in the contact window. However, this step is found insufficient to prevent melting, because contact is still made at the small portion H in the Figure, which reaches a high temperature. Moreover, there is the drawback that the process of fabrication is made more complicated. Another trial proposal was to make contact with the diffusion region via a pattern of polysilicon 7 as shown in Fig. 4. This Figure shows corresponding parts to those in Figs. 2 and 3. In the Figure , 1, 2 and 3 designate a substrate, diffusion region and insulation layers respectively. As can be seen in the Figure , an elongated pattern 7 of conductive polysilicon is fabricated on the surface of insulation layer 3. One end of the pattern 7 is contacted to the diffusion layer 2 through a contact window 4 opened in the insulation layer 3. The input line 5 is contacted to the polysilicon pattern 7 at the other end of the pattern, through a contact window 4' opened on the other insulation layer 3', which again is an oxidised layer of polysilicon. It was expected that, since the input line 5 is now separated from the contact portion of diffusion region 2, the heat generated at the contact portion would not affect the input line 5. But it was found that the polysilicon pattern 7 is heated by the current running through it, causing melting down of the input line. The explanation for this is that the conductivity of polysilicon is not very high and moreover it is covered by the silicon dioxide layer 3', which is a heat insulator. So, the polysilicon pattern 7 is raised to a very high temperature, causing the melting down of both the polysilicon pattern and the aluminium input line. This problem may be avoided by making the polysilicon pattern large (wide and long), but it is not practical to do so, because this increases the stray capacitance of the input line, and decreases the packing density of devices possible to achieve on the IC. According to the present invention there is provided a MIS IC device provided with a static charge protection circuit connected to an input terminal thereof, said protection circuit comprising a diffusion region and a conductive pattern, of high melting point material, via which the diffusion region is connected to the input terminal. An embodiment of the present invention can provide a protection circuit for static charge break down, and increase the resistance of an MIS IC against static charge break down. This can be achieved by providing a protection circuit including a diffusion region which works as a clamp diode and as a series resistor, in which the input line of the circuit makes contact with the diffusion region via an elongated contact pattern made of conducting material with a high melting point. Reference is made, by way of example, to the accompanying drawings in which: Fig.l shows an equivalent circuit of a static charge protection circuit; Fig.2 shows schematically in plan and cross-section the construction of a previously proposed circuit for static charge protection; Fig.3 shows schematically an example of a proposed improvement to the static charge protection circuit of Fig. 2; Fig.4 shows schematically a further proposed improvement to the static charge protection circuit of Fig.2; Fig.5 shows schematically a static charge protection circuit embodying the present invention; and Fig.6 shows schematically another static charge protection circuit embodying the present invention. .In each of-Figs. 2 to 6, (a) is a plan view and (b) is a corresponding cross sectional view taken in the direction of the arrows substantially along the chained line A-A' in the plan view. In the following description a substrate, 11 in Fig.5, 21 in Fig.6, is assumed to have p-type conductivity as an example. In fact, the substrate may be of any conductivity type. If an n-type conductivity substrate is used, the following processes should use materials with opposite type conductivity to that stated. Also, the material of the substrate may be any kind of semiconductor, but in the following explanation it is assumed to be silicon. In Fig. 5, 12 is a diffusion region whose conductivity type is opposite to that of the substrate; that is n-type in this example. It provides a clamp diode and works also as a series resistor. 13 is a first insulation layer which is composed of silicon dioxide (six2) fabricated on the substrate 11. 14 and 14' designate first and second contact windows respectively opened in the first insulation layer 13 and a second insulation layer 16. 15 is a conductive pattern preferably made of molybdenum silicide (MoSi2). 16 is a second insulation layer, composed of PSG , for example. 17 is an input line made of aluminium. Manufacturing a device of the above configuration requires only conventional fabrication processes. For instance, the diffusion region 12 is fabricated by a diffusion process, the first and second isolation (insulation)-layers 13 and 16 may be fabricated by chemical vapour deposition or oxidation, contact windows 14 and 14' are opened by photo-lithography, and the conductive pattern 15 can be fabricated by sputtering and photo-lithography, and so on. As can be seen by comparison with the foregoing Figures, this embodiment of a protection circuit according to the present invention is formed with a diffusion layer 12, one end of which is connected to the conductive pattern 15, which is made of molybdenum silicide, a high melting point material, via a first contact windowl4 in the first insulation layer 13. Generally the thickness of this molybdenum silicide conductive pattern 15 is a few thousand A . The shape of the conductive pattern may be varied according to the layout of the entire pattern on the IC. For instance, its width w may be 2 to 10 pm and its length 1 may be 10 to 500 P m. The aluminium input line 17 is fabricated on the surface of the second insulation layer 16, which covers the conductive pattern 15. It contacts the other end of the conductive pattern 15, via a second contact window 14' opened on the second insulation layer 16. It will be clear that the second contact window 14' is placed apart from the contact point H of conductive pattern 15 and diffusion region 12, where the most of the heat is generated by the break down current. In practice, another insulation layer covers the entire surface of the device to protect the surface of the IC. Concerning the material of the conductive pattern 15, high melting point metals such as tungsten, molybdenum and so on, or silicides of metals such as platinum, tungsten, molybdenum, titanium and so on are recommended. It is desirable for the sheet resistivity (sheet resistance) of the conductive pattern to be less than a few n per square For the fabrication of the conductive pattern, any conventional technique for semiconductor manufacturing may be applied. For example spattering, or co-spattering (cooperative spattering) may be used for fabricating a conductive layer of molybdenum, tungsten and so on. Any kind of photo-lithographical technology may be used for patterning. Fig. 6 shows another embodiment of the present invention. Comparing Fig.6 to Fig.5, it is provided with a polycrystalline silicon layer 28 fabricated under a conductive pattern 25. On the substrate 21, is fabricated a diffusion region 22, providing a clamp diode and a series resistor. The surface of the substrate is coated with a first insulation layer 23. The diffusion region 22 is connected to the conductive pattern 25 at a contact window 24, via an under layer 28. The under layer 28 is made of phosphor(us) or arsenic doped conductive polysilicon. The thickness of the under layer 28 can range from approximately a few hundreds A to a few thousands A . The sheet resistance of the under layer is a few tens of fl per square. The under layer 28 is sandwiched between the first insulation layer 23 and the conductive pattern 25. The conductive pattern 25, the second insulation layer 26 and input line 27 are the same as in Fig.5. The input line 27 contacts the conductive pattern 25 through a second contact window 24' opened on the second insulation layer 26. The configuration of Fig. 6 has an advantage over that of Fig.5, although it requires some additional processing to fabricate the polysilicon layer 28. The type of device shown in Fig.5 sometimes suffers from migration of the metals used for the conductive pattern. For example, molybdenum atoms may migrate into the substrate and cause the break down of the clamp diode. The sandwiched polysilicon layer 28 prevents such problems. A sandwiched polysilicon layer in the type of device shown in Fig.4 , suffers from overheating. But in this case, polysilicon under-layer 28 is covered by a conductor (that is, the conductive pattern 25) such that the electrical conductivity is good compared to Fig.4, and the polysilicon does not melt. The longer the conductive pattern can be made, the better. Of course this is limited by the design of the IC circuit. By elongating the pattern, thermal conduction is increased, and temperature is reduced so that migration of metal or melting of polysilicon is further reduced. For the fabrication of the polysilicon under-layer 28, a conventional semiconductor process such as chemical vapour deposition, sputtering and photo-lithography and so on, can be applied. As has been described above, an embodiment of a static charge protection circuit according to the present invention has a structure such that the contact point of the input line to the protection circuit is placed apart from the contact point of the clamp diode at which the greatest heating occurs during static charge breakdown of the clamp diode. The melting down of the input line or the contact point are hence prevented. In one embodiment described, the migration of metals at the contact point is also prevented. Static charge break down can be simulated by a condenser discharge. An IC which has no protection circuit has been found to fail due to the discharge of a 300 pF capacitor charged up to a few tens of volts. An IC incorporating a previously proposed protection circuit has been found to withstand up to 300 volts. But an IC which is protected by a circuit in accordance with the present invention, is able to withstand more than twice that voltage. Recently, increasingly high resistance of ICs to static charge break down is becoming required. Therefore the effect of the present invention is apparent.

Claims: CLAIMS 1. A MIS IC device provided with a static charge protection circuit connected to an input terminal thereof, said protection circuit comprising a diffusion region and a conductive pattern, of high melting point material, via which the diffusion region is connected to the input terminal. 2. A MIS IC device as claimed-in claim 1, wherein the protection circuit further comprises a conductive polysilicon under-layer beneath said conductive pattern. 3. A MIS IC device as claimed in claim 2, in which the resistivity of said conductive polysilicon under-layer is less than a few tens Q per square. 4. A MIS IC device as claimed in claim 2 or 3, in which the thickness of said conductive polysilicon under-layer is less than a few thousands A . 5. A MIS IC device as claimed in claim 4, in which the thickness of said polysilicon layer is from a few 0 hundreds to a few thousands A 6. A MIS IC device as claimed in any preceding claim, in which the high melting point material is of high melting point metal. 7. A MIS IC device as claimed in claim 6, in which the high melting point metal includes at least one of tungsten and molybdenum. 8. A MIS IC device as claimed in any one of claims 1 to 5, in which the highumelting point material includes at least one of molybdenum silicide, platinum silicide, tungsten silicide and titanium silicide. 9. A MIS IC device as claimed in any preceding claim, in which the sheet resistivity of the said high melting point material is less than a few Q per square. 10. A MIS IC device as claimed in any preceding claim, in which one end of said conductive pattern is connected to said diffusion layer through a contact window or hole fabricated in a first insulation layer which separates said conductive pattern from said diffusion region, and the other end of said conductive pattern is connected to the said input terminal of the device through a contact window or hole fabricated in a second insulation layer which separates said conductive pattern from said input terminal. 11. A MIS IC device as claimed in claim 10, in which said conductive pattern has an elongated form and at least the whole length of said conductive pattern, said diffusion layer and said input terminal are not fabricated one upon another. 12. A MIS IC device as claimed in claim 10 or 11, in which said first insulation layer and said second insulation layer are made of silicon dioxide. 13. A MIS IC device as claimed in any preceding claim, being a silicon MIS IC.

Inventors: TAKEMAE, YOSHIHIRO C/O FUJITSU LIMITED
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: H01L27
IPC codes: H01L27, H01L21, H01L23, H01L29