A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE MASTER SLICE TECHNIQUE

Abstract: A method of manufacturing a semiconductor device using the master slice technique includes the formation of both an N-channel MIS field effect transistor Tn2 and a P-channel MIS field effect transistor Tp2 in a final output stage of the device. Then during the customising step an output wire LI is connected to the drain of only one of the N-channel MIS field effect transistor Tn2 and the P-channel MIS field effect transistor Tp2 to form an inte­ grated circuit of an N-channel open-drain output type or a P-channel open-drain type. This enables the output type to be chosen to suit the particular circuit prepared by the customising step using only simple proces­ sing and very quickly.

Description: A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE MASTER SLICE TECHNIQUE The present invention relates to a method for manufacturing a semiconductor device and to a semiconductor device so manufactured and more particularly, to a method for manufacturing a metal-insulator-semiconductor (MIS) type integrated circuit device (IC) having general purpose output stages. A MIS IC such as a microcomputer includes a number of logic circuits. Some of the logic circuits have output circuits. In each output circuit, the final output-stage transistor is designed to be an N-channel open-drain output type, i.e. a type in which current flows out from an output pad, when the microcomputer is used to drive a cathode ray tube (CRT) display, for example to provide a positive voltage of, for example, 12V. Alternatively the final output stage transistor may be a P-channel open drain output type, i.e. a type in which current flows into an output pad, for example, when a microcomputer is used to drive a fluorescent display tube to provide a negative voltage of, for example - 40V. Conventionally the final output-stage transistor is manufactured to be one or the other in accordance with user requirements. This causes problems in having to choose the type of output transistor as of one or other type and naturally limits the applications of each device. If it is required to be able to select which output type is required, the manufacture of the semiconductor device is complicated because it is necessary to change masks for forming diffusion regions in the final output-stage transistor depending on the type of transistor required to be formed. Diffusion is one of the earlier manufacturing steps, and thus it is impossible for a manufacturer to proceed with the later manufacturing steps in advance of an order for a particular device if the user wishes td have the flexibility of choosing the type of output. This prevents the fast customisation of the MIS IC after receipt of an order. According to this invention a method of manufacturing a semiconductor device by the master slice technique in which at least one semiconductor device is formed including a final output stage having a MIS field - effect transistor with a gate, a source and a drain, and in which in a customising step, wiring is connected to the output stage is characterised in that both a P-channel MIS field effect transistor and an N-channel MIS field effect transistor are provided in the final output stage, and in that the customising step includes forming wiring to connect only one of the P-channel or N-channel output transistors to the remainder of the circuits of the device and to the output terminals thereby to form an integrated circuit of either the open-drain P- or N-channel output type. Embodiments of the method and devices in accordance with this invention will now be described with reference to the accompanying drawings; in which: Figure 1A is a circuit diagram of a first embodiment of an output-stage circuit of a master slice before the wiring process; Figure 1B is a circuit diagram of the outputstage circuit after a wiring process to form a P-channel open-drain output; Figure 1C is a circuit diagram of the output-stage circuit after a wiring process to form an N-channel open-drain output; Figures 2A to 2C are plans illustrating the manufacturing steps of the circuit shown in Figure 1B; Figure 3 is a cross section taken along the line III-III' shown in Figure 2C; Figure 4A is a circuit diagram of a second embodiment of an output-stage circuit of a master slice before an electrode window process; ; Figure 4B is a circuit diagram of the output-stage circuit after an electrode-window process to form a P-channel open-drain output; Figure 4C is a circuit diagram of the output-stage circuit after an electrode window process to form an N-channel open-drain output; Figures 5A to 5C are plans illustrating the manufacturing steps of the circuit shown in Figure 413; Figure 6 is a cross section taken along the line VI-VI' shown in Figure 5C; Figure 7A is a plan of a third embodiment of an output-stage circuit having transistors with a high tolerance voltage; Figure 7B is a cross-section taken along the line VIIB-VIIB' shown in Figure 7A; Figure 7C is a cross section taken along the line VIIC-VIIC' shown in Figure 7A; ; Figure 8A is a plan of a fourth embodiment of an output stage circuit having transistors with different tolerance voltages; Figure 8B is a cross section taken along the line VIIIB-VIIIB' shown in Figure 8A; Figure 8C is a cross section taken along the lien VIIIC-VIIIC' shown in Figure 8C; Figure 9A is a plan of a fifth embodiment illustrating an output stage circuit having transistors with a high tolerance voltage; Figure 9B is a cross section taken along the IXB-IXB' shown in Figure 9A; Figure 9C is a cross-section taken along the line IXC-IXC' shown in Figure 9A; Figure l0A is a plan of a sixth embodiment of an output-stage circuit having transistors with different tolerance voltages; Figure lOB is a cross section taken along the line XB-XB' shown in Figure l0A; and, Figure lOC is a cross section taken along the line XC-XC' shown in Figure l0A. In the method for manufacturing MIS or metal-oxide -semiconductor (MOS) IC's according to the present invention, both an N-channel MOS field effect transistor and a P-channel MOS field effect transistor are arranged in the final output stage of each of a plurality of output circuits integrated in the IC. Before customization, the IC manufactured according to the present invention includes transistors for constructing logic circuits, transistors for constructing output circuits, and two types of MOS field effect transistors with different conductivities in the final output stages. These transistors themselves are manufactured by conventional techniques. After forming these-transistors, the IC is covered by an insulating film. During customization to specific user designs, each output stage is formed as a P-channel open-drain output type or an N-channel open-drain output type by appropriately wiring an output pad to the desired P-channel or N-channel MOS field effect transistors. This method enables reduction ot the time needed by a manufacturer to form a desired IC after receiving a user order. According to a first embodiment of the present invention, the desired P-channel open-drain output type or N-channel open-drain output type is formed in the final output stage of a MOS IC by a wiring master slice method. "Wiring master slice method" means a master slice process using wiring patterns for customization. Figures lA through lC are circuit diagrams of an output-stage circuit illustrating the manufacturing steps according to the first embodiment. Among the figures, Fig. lA shows the output-stage circuit before the wiring master slice process. In Fig. lA, there are formed, on a substrate of an IC to be processed, a first P-channel MOS field effect transistor Tpl and a first N-channel MOS field effect transistor T as semi nl conductor elements for constructing an output circuit of, for example, an output inverter, and a second P-channel MOS field effect transistor T and a second N-channel MOS field effect transistor Tn2 as elements of a final output stage, In the figure, reference notations G represent gates, GLl and GL2 gate electrodes; S p P-type sources; 5n N-type sources; Dpl and Dp2 P-type drains; Dnl and D#2 N-type drains; Vcc power supplies or power supply lines; and E the ground. Dash lines represent wirings to be formed in the later manufacturing steps. Figure lB shows the output-stage circuit of Fig. 1A after the wiring master slice process to form a P-channel open-drain output type. In Fig 1B, the drain Dp2 of the second P-channel MOS field effect transistor T is connected to an output pad P by a wire Ll. This wiring is carried out by a master slice method. During the wiring master slice procedure, the power supply line VCC t the wirings for connecting the power supply line VCC and the sources 5p of the transistors Tpl and Tp2 a wiring line LG for connecting the drains Dpl and Dnl to the gate electrode GL2 , and wirings for connecting the sources 5n and the ground E are simultaneously formed with the wire Ll. Figure lC shows the output-stage circuit of Fig. lA after the wiring master slice process to form an N -channel open-drain output type. In Fig. lC, the drain Dn2 of the second N-channel MOS transistor Tn2 is connected to the output pad P by a wire L2. This wiring is also carried out by a master slice method. During the master slice procedure, the other wirings are also simultaneously made in the same way as in the devide of Fig. 113. Figures 2A through 2C are plan views illustrating the manufacturing steps of the final stage of the circuit of Fig. 113. Figure 2A shows the IC substrate corresponding to the final stage of the circuit of Fig. lA before customization to a P-channel open-drain output type or N-channel open-drain output type. In Fig. 2A, reference numeral 1 represents a P-type semiconductor substrate; 2 an N-type well; 3 an insulating film and covering the surface of the IC; Tp2 the second P-channel MOS field effect transistor; Tn2 the second N-channel MOS field effect transistor; GL2 the gate electrode; Sp the P-type source region; Sn the N-type source region; D the P-type drain region; and p2 Dn2 the N-type drain region. According to the first embodiment, when a user orders a P-channel open-drain output type, electrode -contact windows such as N1 , N2 , N3 , and N4 shown in Fig. 2B are formed, by a conventional photolithography technique, on the source and drain regions of all of the transistors, including transistors not shown in Fig. 2B. Then, a wiring-material layer such as an aluminum (Al) layer is formed on the substrate. After this, a wire -forming mask having the output wiring pattern appropriate for the user's needs, in this case an output wiring pattern for providing a P-channel open-drain output type, is used for patterning of the aluminum layer by means of a conventional photolithography technique. Thus, as illustrated in Fig. 2C, the output wiring L1 having the output pad P and source wirings L are formed on the insulating film 3. The output wiring L1 is in contact via the electrode-contact window N3 with the drain region Dp2 of the final-stage P-channel MOS field effect transistor T During this patterning procedure, the other aluminum wirings, such as those for constructing logic circuits or those for constructing output circuits, are simultaneously formed by a conventional master slice method. It should be noted that, in Figs. 2A through 2C, a well contact region for providing a potential to the N-type well and substrate contact region for providing a potential to the substrate 1 are not shown for the sake of simplicity. Figure 3 is a cross-sectional view, taken along line III-III' of Fig. 2C, which represents the final output stage after the above-mentioned wiring process. In Fig. 3, reference numeral 1 represents the P-type semiconductor substrate; 2 the N-type well; 3 the insulating film between layers; 4 a field oxidation film; 5 N+ -type channel cut regions; 6 P+ -type channel cut regions; 14 thin oxidation films; Tp2 the P-channel MOS field effect transistor; Tn2 the N-channel MOS field effect transistor; Dp2 the P-type drain region; Dn2 the N-type drain region; N3 and N4 electrode-contact#windows; and L1 the output wiring. After the formation of the above-mentioned wirings, the IC is covered by a surface-protecting film such as phospho-silicate glass (PSG). According to a second embodiment of the present invention, the desired P-channel open-drain output type or N-channel open-drain output type is formed in the final output stage of a MOS IC by an electrode-window master slice method. "Electrode-window master slice method" means a master slice process forming desired electrode windows. Figures 4A through 4C are diagrams of an output -stage circuit illustrating the manufacturing steps according to the second embodiment of the present invention. Among the figures, Fig. 4A shows the output -stage circuit before the electrode-window master slice process. The structure of the circuit of Fig. 4A is similar to the structure of the circuit of Fig. lA. In Fig. 4A, reference notations are similar to those in Fig. lA, that is, T and T pl Ia, that is, Tpl and nl represent a first P-channel MOS field effect transistor and a first N-channel MOS field effect transistor, respectively, for forming an output inverter; Tp2 and Tn2 a second P-channel MOS field effect transistor and a second N-channel MOS field effect transistor, respectively, for forming a final output stage; G gates; GLl and GL2 gate electrodes; P-type sources; Sn N-type sources; Dpl and D#2 P-type drains; Dnl and Dn2 N-type drains; VCC power supplies or power supply lines; and E the ground. Dash lines represent wirings to be formed in the later manufacturing steps. Figure 4B shows the output-stage circuit of Fig. 4A after the electrode-window master slice process to form a P-channel open-drain output type. In Fig. 4B, an electrode-contact window N p is formed on the drain Dp2 of the P-channel MOS field effect transistor T No electrode-contact window is formed on the drain D of the N-channel MOS field effect transistor T The drain Dp2 of the P-channel MOS field effect transistor Tp2 is connected via the electrod-contact window N to p2 p an output wiring Lo which is connected to an output pad P. The drain Dn2 of the N-channel MOS field effect transistor Tn2 is not connected to the output wiring L Thus, a P-channel open-drain output type is formed. Figure 4C shows the output-stage circut of Fig. 4A after the electrode-window master slice process to form an N-channel open-drain type. In Fig. 4C, an electrode -contact window Nn is formed on the drain Dn2 of the N-channel MOS field effect transistor T No electrode -contact window is formed on the drain Dp2 of the P-channel MOS field effect transistor T The drain p2 D of the N-channel MOS field effect transistor Tn2 is p2 connected via the electrode-contact window Nn to the output wiring L0 , which is connected to the output pad P. The drain Dp2 of the P-channel MOS field effect transistor T is not connected to the output wiring LoZ p2 Thus, an N-channel open-drain output type is formed. In Fig. 4B or 4C, the power supply line VCC , the wirings for connecting the power supply line Vcc and the sources S of the transistors Tpl and Tp2 , a wiring line LG for connecting the drains Dpl and Dnl to the gate electrode GL2 , wirings for connectig the sources and the ground E are simultaneously formed with the formation of the above-mentioned output wiring Lo during the electrode-window master slice procedure. Figures 5A through 5C are plan views illustrating the manufacturing steps of the final stage of the circuit of Fig. 4B. Figure 5A shows the IC substrate corresponding to the final stage of the circuit of Fig. 4A before customization to a P-channel open-drain output type or N-channel open-drain output type. In Fig. 5A, reference numeral 1 represents the P-type semiconductor substrate; 2 the N-type well; 3 the insulating film covering the surface of the IC; Tp.2 the second P-channel MOS transistor; GL2 the gate electrode; the P-type source region; 5n the N-type source region; D the P-channel drain region; and Dun2the p2 N-type drain region. According to the second embodiment, when a user orders, for example, a P-channel open-drain output type, the electrode-contact window N p for connecting the drain Dp2 of the P-channel MOS field effect transistor Tp2 to the output wiring Lo is formed only on the drain Dp2 of the P-channel MOS field effect transistor T in the final output stage, as illustrated in Fig. 5B, an electrode-window forming mask having the pattern to form the electrode-contact window appropriate for the users needs, in this case, the pattern for providing an electrode-contact window on the drain D of the P p2 -channel MOS field effect transistor Tp2 No electrode -contact window is formed on the drain D of the N-channel MOS field effect transistor Tn2 During the procedure of forming the electrode-contact window N p electrode-contact windows Nl and N2 , corresponding to the sources 5p and Sn of the transistors Tp2 and Ts2 in the final output stage, and other electrode-contact windows, corresponding to sources and drains of transistors for constructing output circuits and logic circuits on a region not illustrated in Fig. 5B, are, simultaneously formed. Then, a wiring material layer such as an aluminum (Al) layer is formed on the substrate. Patterning is carried out by means of a conventional photolithography technique to form source wirings L and the output wiring Lo as illustrated in Fig. 5C. The output wiring Lo has at its end the output pad P and extends on the upper portions of the drains Dp2 and Dn2 of the P-channel MOS field effect transistor Tp2 and the N-channel MOS field effect transistor Tn2 as illustrated in Fig. 5C. Thus, the drain D of the P-channel MOS field effect p2 transistor Tp2 is connected via the electrode-contact window N to the output wiring Lo , resulting in the p desired P-channel open-drain output type. During the patterning procedure, the other aluminum wirings, such as those for constructing logic circuits or those for constructing output circuits, are simultaneously formed. It should be noted that, in Figs. 5A through 5C, a well contact region for providing a potential to the N-type well and a substrate contact region for providing a potential to the substrate 1 are not shown for the sake of simplicity. Figure 6 is a cross-sectional view taken along line VI-VI' of Fig. 5C and represents the final output stage after the above-mentioned wiring process. In Fig. 6, reference numeral 1 represents the P-type semiconductor substrate; 2 the N-type well;' 3 the insulating film, 4 a field oxidation film; 5 N -type channel cut regions; 6 P+-type channel cut regions; 14 thin oxidation films; T the P-channel MOS field effect transistor; Tn2 the p2 N-channel MOS field effect transistor; Dp2 the P-type drain region; Dn2 the N-type drain region; and Lo the output wiring. After the formation of the above-mentioned wirings, the IC is covered by a surface-protecting film such as PSG. Figure 7A is a plan view of an output-stage circuit after a wiring master slice process, according to a third embodiment of the present invention; Fig. 7B is a cross-sectional view taken along line VIIB-VIIB' of Fig. 7A; and Fig. 7C is a cross-sectional view taken along line VIIC-VIIC' of Fig. 7A. In these figures, an N-channel MOS field effect transistor T and a P-channel MOS field effect transistor T H in the final output stage are made to have a high tolerance voltage. Figure 8A is a plan view of an output-stage circuit after a wiring master slice process, according to a fourth embodiment of the present invention; Fig. 8B is a cross-sectional view taken along line VIIIB-VIIIB' of Fig. 8A; and Fig. 8C is a cross-sectional view taken along line VIIIC-VIIIC' of Fig. 8A. In these figures, a P-channel MOS field effect transistor Tp2 H and an N-channel MOS field effect transistor Tn2 are given different tolerance voltages. That is, the P-channel MOS field effect transistor T has a high tolerance voltage, and the N-chamlel MOS field effect transistor Tn2 has a normal tolerance voltage. Of course, the P -channel MOS field effect transistor may alternatively be given a normal tolerance voltage, and the N-channel MOS transistor may alternatively be given a high tolerance voltage. Figure 9A is a plan view of an output-stage circuit after an electrode-window master slice process, according to a fifth embodiment of the present invention; Fig. 9B is a cross-sectional view taken along line IXB-IXB' of Fig. 9A; and Fig. 9C is a cross-sectional view taken along line IXC-IXC' of Fig. 9A. In these figures, an N-channel MOS field effect transistor Tn2-H and a P-channel MOS field effect transistor Tp2 H in the final p2-I{ output stage are given a high tolerance voltage. Figure l0A is a plan view illustrating an output -stage circuit after an electrode-window master slice process, according to a sixth embodiment of the present invention; Fig. 1013 is a cross-sectional view taken along line XB-XB' of Fig. l0A; and Fig. lOC is a cross -sectional view taken along line XC-XC' of Fig. l0A. In these figures, a P-channel MOS field effect transistor T H and an N-channel MOS field effect transistor Tn2 p2-H are given different tolerance voltages. That is, the P-channel MOS field effect transistor T has a high p2 tolerance voltage, and the N-channel MOS field effect transistor Tn2 has a normal tolerance voltage. Of course, the P-channel MOS field effect transistor may alternatively be given a normal tolerance voltage, and the N-channel MOS field effect transistor may alternatively be given a high tolerance voltage. Referring to Figs. 7A through 7C, 8A through 8C, 9A through 9C, and l0Athrough l0C, reference numeral 1 represents a P-type semiconductor substrate; 2 an N-type well; 3 an insulating film; 4 a field oxidation film; 5 N+-type channel cut regions; 6 P -type channel cut regions; 7 a P+ -type source region; 8 a P+ -type drain region; 9 a-P--type drain region having a low impurity concentration; 10 an N -type source region; 11 an N -type drain region; 12 an N -type drain region; 13 a gate oxidation film; 14 a thin oxidation film; T H the P-channel MOS field effect transistor having a high tolerance voltage; Tn2 H the N-channel MOS field effect transistor having a high tolerance voltage; Tn2 the N-channel MOS field effect transistor having the normal tolerance voltage; GL2 a gate electrode; Ni , N2 r N3 N4 , and N p the electrode-contact windows; L the source wirings; and L1 the output wiring. The output-stage circuit of a P-channel open-drain output type with a high tolerance voltage P-channel MOS field effect transistor, as illustrated in Figs. 7A through 7C, Figs. 8A through 8C, Figs. 9A through 9C, or Figs. l0A through l0C, is effectively used to drive a minus-voltage driven unit such as a fluorescent display. Also, the output-stage circuit of an N-channel open-drain output type with a high tolerance voltage N-channel MOS field effect transistor is effectively used to drive a plus-voltage driven unit such as a CRT display tube. Each of the illustrated embodiments shows a single output-stage circuit. In practice, however, there are a number of output-stage circuits in a MIS IC such as a microcomputer. All of the output-stage circuits in the MIC IC may be formed by any one or more of the foregoing embodiments. Alternatively, a selected part of the output-stage circuits may be formed by any one or more of the foregoing embodiments, and remaining output-stage circuits may be formed in a conventional way. That is, each of the remaining output-stage circuits may be manufactured to be a fixed N-channel or even a push-pull open-drain type or P-channel open-drain type. From the foregoing description, it will be apparent that, according to the present invention, a MIS IC having a desired output type, i.e., a MIC IC having an N-channel open-drain output type or a P-channel open -drain output type, can be formed simultaneously with the formation of wirings by means of a wiring master slice process or with the formation of electrode-contact windows by means of a electrode-window master slice process. Accordingly, a MIS IC having the output type desired by the user can be provided without increasing the manufacturing steps a short time after the user orders the manufacture of the MIS IC. As a result, according to the invention, a semiconductor device before wiring can conveniently be applied to general purposes, i.e., it is easy to form an N-channel MIS field effect transistor or a P-channel MIS field effect transistor in the final output stage.

Claims: CLAIMS 1. A method of manufacturing a semiconductor device by the master slice technique in which at least one semiconductor device is formed including a final output stage having a MIS field effect transistor with a gate, a source and a drain, and in which, in a customising step, iring is connected to the output stage characterised in that both a P-channel MIS field effect transistor and an N-channel MIS field effect transistor are provided in the final output stage, and in that the customising step includes forming wiring to connect only one of the Pchannel or Ni.channel output transistors to the remainder of the circuits of the device and to the output terminals thereby to form an integrated circuit of either the open-drain P- or N-channel output type. 2. A method of manufacturing a semiconductor device comprising the steps of: forming an N-channel MIS field effect transistor and a P-channel MIS field effect transistor in a final output stage of a semiconductor device, each of the N-channel and P-channel transistors comprising a gate, a source and a drain; and forming an output wiring connected to a selected one of the drains of the N-channel MIS field effect transistor or the P-channel MIS field effect transistor, thereby forming an integrated circuit of an N-channel open-drain output type or a P-channel open-drain output type. 3. A method according to claim 1 or 2, further comprising forming electrode-contact windows on the upper portions of the drains of the P-channel MIS field effect transistor and the N-channel MIS field effect transistor and in which the formation of the output wiring comprises the step of forming the output wiring in a pattern extending to only a selected one of the electrode-contact windows so that the wiring is only connected to the selected one of the N-channel MIS field effect transistor or the P-channel MIS field effect transistor via the selected electrode-contact window. 4. A method according to claim I or 2, further comprising forming an electrode-contact window on the upper portion of the drain of a selected one of the P-channel MIS field effect transistor or the N-channel MIS field effect transistor, and in which the formation of the output wiring comprises the step of forming the output wiring in a pattern extending onto the upper portions of the drains of both of the P-channel MIS field effect transistor and the N-channel MIS field effect transistor so that the output wiring is connected to the selected one of the drains via the electrode-contact window. 5. A method according to any one of the preceding claims, in which the N-channel MIS field effect transistor and the P-channel MIS field effect transistors are formed with their drains having different tolerance voltages. 6. A method according to any one of the preceding claims, wherein the drains of at least one of the Nchannel and the P-channel MIS field effect transistors are formed to have a high tolerance voltage in comparison with the tolerance voltage of the drains of other MIS field effect transistors integrated in the semiconductor device. 7. A semiconductor device comprising: an N-channel MIS field effect transistor (Tn2) and a P-channel MIS field effect transistor (Tp2) formed in a final output stage of the semiconductor device, each of the N-channel (Tn2) and P-channel (Tp2) transistors comprising a gate (G), a source (Sp or Sn) and a drain (Dp2 or Dn2); and, an output wiring (Ll, L2) connected to a selected one of the drains (Dn2, Dp2) of the N-channel MIS field effect transistor or the P-channel MIS field effect transistor (Tn2 or Tp2), whereby an integrated circuit of an N-channel open-drain output type or a P-channel open-drain output type is formed in the semiconductor device. 8. A semiconductor device according to claim 7, further comprising electrode-contact windows (N3, N4) on the upper portions of the drains (Dp2, Dn2) of both the P-channel MIS field effect transistor (Tp2), the output wiring (Ll) having a pattern extending on a selected one of the electrode-contact windows (N3, N4) so as to be connected to the drain (Dp2, Dn2) of the selected one of the N-channel or P-channel MIS field effect transistors via the selected electrodecontact window. 9. A semiconductor device according to claim 7, further comprising an electrode-contact window (N3 or N4) on the upper portion of a selected one of the drains (Dp2, Dn2) of either of the P-channel MIS field effect transistor (Tp2) or the N-channel MIS field effect transistor {Tn2), the output wiring having a pattern extending onto the upper portions of the drains (Dp2 and Dn2) of both of the P-channel and N-channel MIS field effect transistors (Tp2, Tn2) so that the output wire (Ll) is connected to the one selected drain via the electrode-contact window (N3 or N4). 10. A semiconductor device according to any one of claims 7, 8 or 9, wherein the drains (Dn2, Dp2) of the N-channel MIS field effect transistor (Tn2) and the P-channel MIS field effect transistor (Tp2) have different tolerance voltages. 11. A semiconductor device according to any one of claims 7, 8, 9 or 10, in which at least one of the drains (Dn2, Dp2) of the N-channel MIS field effect transistor (Tn2) and the P-channel MIS field effect transistor (Tp2) has a high tolerance voltage in comparison with the tolerance voltage of the drains of other MIS field effect transistors integrated in the semiconductor device.

Inventors: SHIRATO, TAKEHIDE, WADA, KENSAKU, YUASA, KOUICHI
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: H01L23
IPC codes: H01L29, H01L21, H01L23, H01L27