THYRISTOR WITH TURN-OFF CAPABILITY

Abstract: A thyristor employs MOS structure for transporting holes from its P base region to its cathode, so as to facilitate turn-off of the device. The MOS structure includes an insulating layer and a gate electrode. The insulating layer adjoins the N⁺ emitter region of the device as well as a portion of the cathode adjoining the N⁺ emitter region. The gate electrode is situated adjacent to the N⁺ emitter region and to such portion of the cathode, but is spaced from the N⁺ emitter region and such portion of the cathode by the insulating layer.

Description: THYRISTOR WITH TURN-OFF CAPABILITY Cross-References to Related Applications The present invention is related to the following U.S.Patent applications, commonly assigned to the instant assignee: Serial No. 391,620, filed June 24, 1982, by V.A.K. Temple (the inventor herein); Serial No. 345,290, filed February 3, 1982 by V.A.K. Temple (the inventor herein); and Serial No.(Docket RD-14,244), filed contemporaneously herewith, by V.A.K. Temple (the inventor herein). The entirety of the disclosures of each of the foregoing applications is hereby incorporated by reference. Background of the Invention The present invention relates to a thyristor, and, more particularly, to a thyristor incorporating metal-oxidesemiconductor ('MOS") structure for facilitating turn-off of the thyristor. Thyristors are four-region(e.g., P-N-P-N) semiconductor devices that are well-known and typically comprise a (or highly-doped P-type) emitter region, an N (lightly doped N-type) base region, a P (or P-type, of a reference doping level) base region and an N+ emitter region, along with an anode connected to the P+ emitter region and a cathode connected to the N emitter region. A thyristor is "turned-on" when it provides a high conductance between its anode and cathode, and is "turned-off" when it provides a non-conducting path between such electrodes. The above-referenced application Serial No.391,620 described and claims such a thyristor, which further includes MOS structure for facilitating turn-off of the thyristor. The MOS structure is effective to create an inversion channel in the N+ emitter region that completes a distributed current path from the P base region of the device to a further region of the device, which is ohmically connected to the cathode. The inversion channel is conductive to holes, and hole current that flows therein from the P base region to the cathode (via the further P region) facilitates turn-off of the thyristor. The inclusion of the further P+ region in the thyristor necessitates the critical alignment of a photolithographic mask in forming such region. It,therefore, would be desirable to provide a thyristor having MOS structure for transporting holes from its P base region to its cathode which does not require such further P region in a hole current path extending from the P base region to the cathode. As is known in the art, a thyristor complementary in structure to that described above can be fabricated by substituting P-type material for N-type material, and vice-versa. Objects of the Invention Accordingly, it is an object of my invention to provide a thyristor having MOS structure for transporting in a distributed current path, majority carriers from an inner base region of the device to a main current-carrying electrode of the device, wherein the thyristor does not require a further distinct semiconductor region in such distributed current path. Further objects and advantages of my invention will become apparent from a reading of the remainder of this specification. In accordance with the illustrated embodiment of my invention, I provide a thyristor having a P+ emitter region, an N base region, a P base region, and an N+ emitter region. An anode adjoins the P+ emitter region, and a cathode adjoins the N+ emitter region. An MOS structure is included for transporting holes from the P base region to the cathode. The MOS structure includes an insulating layer and a gate electrode. The insulating layer adjoins the N+ emitter region and a portion of the cathode which adjoins the N emitter region. The gate to both + electrode is situated adjacent/the N emitter region and such portion of the cathode, but is spaced from the N+ emitter region and such portion of the cathode by the insulating layer. The thryristor does not require a further P+ complete The thyristor does notrequire a further P region to/a hole current path extending from the P base region to the cathode. The thyristor may conveniently be referred to as a metal-oxide-semiconductor turn-off thyristor ("MOSTOT1,). Brief Description of the Drawing While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which I regard as my invention, it is believed that the invention will be better understood from the following description, when considered in conjunction with the sole drawing FIGURE, schematically illustrating a cross-section of a portion of a MOSTOT which incorporates my invention. Description of the Preferred Embodiments There is illustrated in FIGURE 1 a cross-section of a portion of a MOSTOT 10 incorporating my invention. Such illustrated portion of MOSTOT 10 includes a cell or repeated structure 12, which is typically round or rectangular as viewed are from above the device. Many cells identical to cell 12/typically included in HOSTOT 10. MOSTOT 10 includes a body 14 of semiconductor material, preferably silicon. In the illustrated embodiment, body 14 includes a P+ emitter region 16, an N base region 18, a P base region 20, and an N+ emitter region 22, as well as further N+ emitter regions, such as regions 24 and 26, for further cells. MOSTOT 10 has a doping profile, taken vertically through regions 16, 18, 20, and 22, which is selected to yield good thyristor performance. By way of example, a suitable doping profile for MOSTOT 10 is illustrated in FIGURE 2(a) of S.M. Sze, Physics of Semiconductor Devices, New York: Wiley-Interscience (1969) at page 322. Cell 12 includes MOS structure 30 for transporting holes from P base region 20 to cathode 28, so as to facilitate turn-off of MOSTOT 10. MOS structure 30 comprises a gate electrode 31, an insulating layer 32 having component layers 34, 36, and 38, and portion 40 of N emitter region 22, which is in the vicinity of gate electrode 31. Gate electrode 31 preferably comprises a conductive refractory material such as highly-doped polysilicon ormolybdenum silicide, known conductive equivalents to metal. Component insulating layers 34 and 36 preferably each comprise an oxide of semiconductor material, while component layer 38 preferably comprises silicon nitride, a known dielectric equivalent of oxide, to facilitate the fabrication of MOSTOT 10, as discussed below. As will be understood by those skilled in the art, biasing of gate electrode 30 with a negative voltage above a threshold magnitude results in portion 40 of N+ emitter region 22 becoming "inverted'1, or more populated by holes than electrons, so as to become conductive to holes. The inversion channel thus formed in N emitter portion 40 constitutes part of a distributed current path 42, which extends from the interior of P base region 20 to cathode 28, via the inversion channel in N+ emitter portion 40. If, through biasing of gate electrode 31, the electric field induced in further portion 48 of N+ emitter region 22 is sufficiently strong, then such further portion 48 becomes inverted and, together with the inversion channel in portion 40, completes distributed current path 42 from P base region 20 to cathode 28. However, in a typical embodiment of MOSTOT 10, the electric field in portion 48 is not strong enough to invert portion 48. Rather, the electric field in portion 48 is only sufficient to deplete portion 48 of mobile electrons, but not to cause portion 48 to become more populated by holes than electrons. Such depleted condition of portion 48 will be understood by those skilled in the art as depletion region punch-through in portion 48 from portion 40 to cathode 28. Various measures can be taken for ensuring the attainment of such punch-through of the depletion region in N+ emitter portion 48, and, if desired, the extension of the inversion channel in N+ emitter region 22 from portion 40 into portion 48. First, the thickness of insulating layer 34 between gate electrode 31 and cathode 28 can be minimized, provided that the dielectric function of layer 34 is not impaired. Similarly, the thickness of insulating layers 36 and 38 can be minimized, provided that the dielectric function of these layers is not impaired. Further, the magnitude of the biasing voltage on gate electrode 31 can be maximized, provided that the dielectric function of insulating layer 32, which surrounds gate electrode 31, is not impaired. Additionally, the dopant concentration of portion 48 can be limited so as to decrease the level of biasing voltage on gate electrode 31 at which portion 48 becomes depleted of electrons. A preferred dopant concentration for portion 48 is below about 1017 impurity atoms per cubic centimeter, although it could suitably be as high as about 1018 impurity atoms per cubic centimeter in some embodiments of MOSTOT 10. Limiting the dopant concentration of N+ emitter portion 48 to attain the foregoing purpose is likely to result in the portion of junction 50 between portion 48 and cathode 28 constituting a Schottky barrier rectifying contact for electrons. To insure proper functioning of MNSTOT 10, at least part of junction 50, between N+ emitter region 22 and cathode 28, must form an ohmic contact. This requires that at least some portion of N+ emitter region 22 adjoining cathode 28 at junction 50 have a dopant concentration in excess of about 1017 impurity atoms per cubic centimeter, and, preferably, above about 1019 impurity atoms per cubic centimeter, due to a localized N+ diffusion in region 22, for example. Junction 50 must not constitute a Schottky barrier rectifying contact for holes; otherwise, distributed current path 42 would not be complete. Accordingly, cathode 28 must comprise a conductive material with a low work function, such as aluminum or titanium. Conversely, if a complementary MOSTOT 10 were fabricated, in which N-type material were used instead of P-type material, and vice-versa,and its corresponding bypass current path were conductive to electrons rather than holes, its cathode would need to comprise a conductive material with a high work function, such as gold or platinum, so as to avoid a Schottky rectifying barrier to electrons. Cell 12 of MOSTOT 10 can be turned off when distributed current path 42 has a resistance sufficiently low to prevent P-N junction 44, between P base region 20 and N+ emitter region 22, from becoming forward biased, owing to hole current flow in current path 42, by more than about one-half of the energy bandgap voltage of the semiconductor material forming P-N junction 44 (i.e., about 1.0 volt in silicon). If the resistance of current path 42 exceeds such a value, cell 12 cannot turn-off, at least without commutation (i.e., by reversal of the anode 46-to-cathode 28 voltage of MOSTOT 10). the lat#er -off of cell 12 is markedly faster than by commutation alone. In order for the entire MOSTOT 10 to turn-off, each of its cells must turn-off. In fabricating MOSTOT 10, P+ emitter region 16, N base region 18, and P base region 20 are suitably fabricated using conventional techniques for making thyristors. The MOS structure for transporting holes from P base region 20 to cathode 28, which includes gate electrode 31 and insulating layer 32, is suitably fabricated in the following, exemplary manner. Silicon nitride layer 38, oxide layer 36, and gate electrode layer 31 are sequentially formed across the entire upper surface of the illustrated portion of semiconductor body 142, preferably by low pressure chemical deposition. Gate electrode 31 and oxide layer 36 are then photolithographically patterned to remove undesired portions thereof, leaving intact the illustrated portions of gate electrode 31 and oxide layer 36. Oxide layer 34 is then formed on gate electrode 31, preferably by thermal growth. Oxide layer 34,at least where it is thermally grown,does not grow on silicon nitride layer 38,even though the lower portions thereof appear to do so in the schematic drawings. Next,silicon nitride layer 38 is selectively removed,as by etching,so as to leave intact only the illustrated portions thereof. Layer 38 could alternatively be i:plemented by a material other than silicon nitride which likewise resists oxidation and can be removed without removing oxide The presence of these characteristics in layer 38 facilitates the fabrication of MOSTOT 10 by minimizing the per of photolithographic masking steps required. Gate electrode 31, along with insulating layer 32, is then used as a mask for forming N+ emitter regions 22, 24 and 26 in the upper portion of semiconductor body 14, preferably by diffusion, with the remainder of the illustrated portion of the upper surface of body 14 being unmasked or exposed. While carrying out such N+ diffusions, the thermal growth of oxide on the exposed portions of the upper surface of semiconductor body 14 should be minimized, in order that such oxide can be removed without reducing the thickness of oxide layer 34 to such an extent that the dielectric capability thereof is impaired. The foregoing describes a thyristor having MOS structure for transporting, in a distributed current path, majority carriers from inner base region of the device to a main current-carrying electrode of the device, wherein the thyristor does not require a further region in such distributed c'rrent path. While no specific means for turning on the thyristor has been described herein, attention is directed to the above-referenced application Serial No. 391,620, which contains a discussion of suitable means and techniques for on a turning/thyristor such as the present thyristor. While the invention has been described with respect to specific embodiments, many modifications and substitutions will occur to those skilled in the art. For example, as described in the above-referenced application Serial No. 391,620, complementary MOS structure for removing majority carriers from an inner base region of the device could additionally be fabricated on the lower surface of the thyristor described herein. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and substitutions as fall within the true spirit and scope of the invention.

Claims: TEYRISTOR WITH TURNOFF CAPABILITY CylIMS 1. In a thyristor including a body of semiconductor material having first, second, third, and fourth regions successively joined together and arranged in alternate conductivity types, and first and second electrodes respectively adjoining said first and fourth regions, improved MOS means for transporting majority carriers from said third region to said second electrode, said improved MOS means including: (a) an insulating layer adjoining said fourth region, and a portion of said second electrode adjoining said fourth region; and (b) a gate electrode situated adjacent said fourth region and said portion of said second electrode, but spaced from said fourth region and said portion of said second electrode by said insulating layer. 2. The invention according to claim 1 wherein said insulating layer comprises silicon nitride adjoining said fourth region. 3. The invention according to claim 2 wherein said insulating layer additionally comprises a thermally-grown oxide of said gate electrode. 4. The invention according to claim 1 wherein the dopant concentration of the portion of said fourth region in the vicinity of said portion of said second electrode is below about 1018 impurity atoms per cubic centimeter. 5. The invention according to claim 1 wherein the dopant concentration of the portion of said fourth region in the vicinity of said portion of said second electrode is below about 1017 impurity atoms per cubic centimeter. 6. The invention according to claim 1 wherein said first and third regions comprise P-type semiconductor material and said second and fourth regions comprise N-type semiconductor material. 7. The invention according to claim 6 wherein said semiconductor body comprises silicon. 8. The invention according to claim 1 wherein said first, second, third, and fourth regions each comprises a layer parallel to a major surface of said semiconductor body. 9. The invention according to claim 1 wherein said gate electrode is situated adjacent a terminated portion of the junction between said third and fourth regions, but is spaced therefrom by said insulating layer. 10. The invention according to claim 1 wherein said gate electrode comprises a conductive refractory material. 11. The invention according to claim 1 wherein said gate electrode comprises highly-doped polysilicon.

Inventors: TEMPLE, VICTOR ALBERT KEITH
Applicants: GENERAL ELECTRIC COMPANY
Application year: 1983
Main classification: H01L29
IPC codes: H01L29