DIAGNOSTIC SYSTEM IN A DATA PROCESSOR

Abstract: In a logical unit provided with a plurality of internal registers (12 to 15; 20), an internal memory (11-1, 11-2; 21) and a combinational circuit (16), such as an arithmetic unit, at least one (13 or 14; 20) of the plurality of internal registers is arranged to be scanned in and out. During diagnosis, when executing an instruction which makes reference to the internal memory (11-1, 11-2; 21), the register than can be scanned in and scanned out is used in place of the internal memory 11-1, 11-2; 21) for diagnosing the combinational circuit (16).

Description: DIAGNOSTIC SYSTEM The present invention relates to a diagnostic system for a data processor constructed so that during its normal operation the output of a memory is input directly to a combinational circuit, such as an arithmetic unit or the like, and the output of the combinational circuit is input directly to the memory. Fig.1 is a block diagram showing the principles of a conventional logical unit. Reference numerals 1-A to 1-C indicate gates; 2 designates a memory; 3 identifies a register; SDi denotes scan-in data; SDo represents scanout data ; X shows input data to the gate 1-A; and Y refers to output data from the gate 1-C. Incidentally, the gates 1-A to 1-C are not mere gates but are combinational circuits, such as arithmetic circuits or the like. The combinational circuit is diagnosed by checking its input and output data. The output data from the gate 1-A is input directly to the memory 2 and the input data to the gate l-B is data read out directly from the memory 2. In general, however, a scan function for the memory 2 is not provided; therefore, in the arrangement of Fig. 1, the gates 1-A and 1-B cannot be diagnosed individually. Fig. 2 is a block diagram showing the principles of anther conventional logical unit which is provided with a trite data register 4 and a read data register 5 in action to the arrangement of Fig. 1. In the case of di--gnosing the gate 1-A, the input data X is provided tl-reto and its output is set in the write data register 4, after which data of the write data register 4 is read out therefrom by a serial scan operation. In the case of diagnosing the gate 1-B, data is written by a serial scan operation into the read data register 5 and its output data is input to the gate 1-B, the output data of which is set in the register 3. Then the data of the register 3 is read out therefrom by the serial scan operation. In this way, the gates 1-A and 1-B can be diagnosed. The write data register 4 and the read data register 5 are used during the diagnosis only and during normal operation, for speeding up the operation of the logical unit, they are by-passed so that the output data of the gate 1-A is input directly to the memory 2 and the read data of the memory 2 is input directly to the gate 1-B. Since the provision of the registers which are used Jolely for diagnosis lncreaseu the amount of hardware used, it has been proposed to employ existing registers as the aforesaid read and write data registers 4 and 5. By the way, in the case where a desired test pattern is set in an instruction register, the diagnostic ratio lowers unless an operation by the test pattern is not performed normally. In the absence of a scan function for a memory, even if an instruction for reference to the memory, for instance, an instruction for adding data of first and second memories and storing the added data in the first memory , (MEM 1)#(MEM 1) + (MEM 2), is provided in an instruction register, the diagnostic results cannot be taken out to the outside. Therefore, when an instruction of the memory reference format is given, no diagnosis is possible. Accordingly, a high proportion of the memory reference instruction is a serious obstacle to diagnosis. Briefly stated, the diagnostic system of the present invention is provided with a plurality of internal registers, an internal memory and a combinational circuit, such as an arithmetic unit, and at least one of the internal registers is arranged so that it can be scanned in and scanned out. When referring to the internal memory during diagnosis, the internal register that can be scanned in and scanned out is used in place of the internal memory. The present invention thus pertains to a diagnostic system which diagnoses a circuit referring to a memory through using an internal register. The present invention provides a diagnostic system which permits a diagnosis of a combinational circuit through using an internal register when a memory reference instruction is given during diagnosis. Reference is made, by way of example, to the accompanying drawings, in which: Figs. 1 and 2 are block diagrams showing the principles of conventional logical units, as mentioned above; Fig. 3 is a block diagram illustrating an embodiment of the present invention; Fig.4 is a block diagram illustrating the principal part of the embodiment of the present invention; Fig. 5 is a flowchart of a diagnostic operation of the embodiment of the present invention ; and Fig.6 is a timing chart of the diagnostic operation. Fig.3 illustrates in block form an embodiment of the present invention. Reference numerals 11-1 and 11-2 indicate internal memories; 12 designates a program counter; 13 identifies a flag register; 14 denotes a data register; 15 represents an instruction register ; 16 shows an arithmetic unit; SDi refers to scan-in data; and SDo signifies scan-out data. Incidentally, the arithmetic unit 16 corresponds to the gate 1-A or 1-B in Figs. 1 and 2. The registers 12, 13 and 14 which are internal registers are interconnected by a scan chain. In this case, it is also possible to arrange only one internal register so that it can be scanned in and scanned out. During normal operation the content of the program counter 12 is provided as an address signal to an external storage (not shown). From the external storage is provided on a Z bus data read out in accordance with the address signal. When the data on the Z bus is an instruction word, it is set in the instruction register 15, whereas, when the data is operand data, it is set in the data register 14. In the case where an instruction decoded by the instruction register 15 is (MEM 1) + (MEM 1) + (DR), that is, an arithmeti# instruction that adds the contents of the memory 11-1 and the data register 14 and sets the added data in the memory 11-1, the contents of the memory 11-1 and the data register 14 are input into the arithmetic unit 16 via X and Y buses, respectively. The arithmetic results of the arithmetic unit 16 are written in the memory 11-1 via the Z bus. Further, each bit of the flag register 13 is set according to the arithmetic results. A description will be given of the case where the internal registers used in place of the internal memories during diagnosis are the flag register 13 and the data register 14. Select signals and write enable signals for the flag register 13, the data register 14 and the memories 11-1 and 11-2 are expressed by the following expressions: For the memories: MSL = MSL'¯T MWE = MWE'-TM For the registers: RSL = RSL + TM.MSL' RWE = RWE + TM.MWE' where MSL is a memory select signal, MSL' an original memory select signal, TM a test mode signal, MWE a memory write enable signal, MWE' an original memory write enable signal, RSL a register select signal, and RWE a register write enable signal. During diagnosis TM = 11111 and request signals to the memories are all inhibited but instead request signals to the flag register 13 and the data register 14 which are used an substitutes for the memories are valid. During diagnosis a test pattern is set by a scan operation for each register. In the event that an arithemetic instruction, (b1EM 1) c (MEM 1) + (MEM 2), is set in the instruction register 15 for making a diagnosis of the arithmetic unit 16, a system clock is generated in the state of TM = for several cycles after the scan-in operation, executing the arithmetic instruction. At this time, since TM = "1", the contents of the flag register 13 and the data register 14 are input via the X and Y buses to the arithmetic unit 16 and the arithmetic results are set in the flag register 13. After execution of the arithmetic instruction, the scan operation is performed again and the arithmetic results set in the flag register 13 are output as the scan-out data SDo to the outside, by which the arithmetic unit 16 can be diagnosed. Fig. 4 is a block diagram illustrating the principal part of the embodiment of the present invention. Reference numeral 20 indicates a register (corresponding to the flag register 13 or data register 14 in Fig. 3); 21 design ates a memory (corresponding to the memory 11-1 or 11-2 in Fig. 3); 22 and 23 identify OR circuits; 24 to 29 denote AND circuits; and Ao to An, Bo to Bn, C0 to C and Do to D represent gate n 0 n groups, respectively. As the gates Bo to B and Do to Dn, n 0 tristate gates are used for preventing a bus fight on the X and Y buses. Input data from the Z bus (see Fig. 3) to the register 20 is controlled by the gates Ao to An and output data from the register 20 to the X or Y bus (see Fig. 3) is controlled by the gates Bo to B . A control signal xl for the gates Ao n to A is made valid when the register write enable signal or n the memory write enable signal in a test mode becomes valid. A control signal X2 for the gates Bo to B is made valid n when the register select signal or the memory select signal in the test mode becomes valid. Input data to the memory 21 is gated by the gates C0 to Cn and output data from the memory 21 is gated by the gates Do to D . A control signal X3 for the n gates C0 to C is made valid by the memory write enable n signal except in the test mode. A control signal X4 for the gates Do to D is made valid when the memory select n signal except in the test mode becomes valid. When the system is in its normal operative state, the test mode signal is a "0", so that only the register write enable signal and the register select signal become valid for the register 20. And, if the scan mode signal happens to be a "0", the system clock is applied to the register 20 and when the register write enable signal is applied, the input data is set in the register 20. When the scan mode signal happens to be a "1", the scan clock is provided to the register 20 and the scan-in data SDi is scanned in the register 20 and, at the same time, the scan-out data SDo is output therefrom. For the memory 21, too, the memory write enable signal and the memory select signal become valid. Consequently, the register 20 and the memory 21 are able to perform normal operation. When the test mode signal is made a "1" to put the system in the diagnostic state, the memory write enable signal becomes the control signal X1 for the gates Ao to An, whereas the memory select signal becomes the control signal X2 for the gates Bo to B . Since the AND circuits 26 and 27 are n closed, the control signals X3 and X4 for the gates C0 to Cn and Do to D both go to "Os" and the memory 21 is separated n by the gates C0 to Cn and Do to Dn In consequence, when a memory write instruction is executed, write data is set in the register 20 and when a memory read instruction is executed, the content of the register 20 is output. Fig. 5 is a flowchart of the diagnostic operation, showing steps (1) to (4). (1) The system is put in a diagnostic mode of operation. in this case, the test mode signal is made a "1". (2) A test pattern is set by the scan operation. At this time, the test mode signal and the scan mode signal both go to "ls". (3) The system clock is generated to execute arithmetic processing. At this time, the test mode signal goes to a "1" and the scan mode signal goes to a "o". (4) The diagnostic results are butput by the scan operation. At this time, the test mode signal goes to a "1" and the scan mode signal goes to a "1". Fig. 6 is a timing chart of the diagnostic operation. A device to be diagnosed assumes the following four states according to the test mode signal TM and the scan mode signal SM. (a) SM-TM This is a state of neither the scan operation nor the diagnostic operation. The normal operation takes place. (b) SM-TM This is a state in which the scan operation is performed under the normal operative condition. In this state, the status of a register or a flip-flop in the device can be taken out to the outside, or they can be set to a desired state. (c) SM.TM This is the diagnostic state of the device. At this tie, the interior of the device is arranged for diagnosis. In the case where a tri-state bus exists in the device, a control circuit for preventing a bus fight during diagnosis and the diagnostic function for the memory in the device become valid under this condition. (d) SM.TM The scan in/scan out is performed under the diagnostic condition. That is, a test pattern for diagnosis is set and the diagnostic results are taken out. In Fig. 6, when the test mode signal TM goes to the "1" state, the system is put in the diagnostic state and when the scan mode signal SM goes to the' "1" state, the scan clock is provided to the register 20 to scan in a test pattern. Next, when the scan mode signal goes to the "0" state, the system clock is applied to the register 20 and when the memory select signal is applied, the content of the register 20 is output via the gates Bo to B n into a combinational circuit, such as an arithmetic unit. When the memory write enable signal is applied, input data (the output data from the combinational circuit, such as an arithmetic unit) is set in the register 20 via the gates Ao to An The period during which the scan mode signal remains at the "0" level is the period for execution of one instruction and when the scan mode signal goes to the "1" level again, the scan clock is provided to the register 20, scanning out its content. This scan-out data SDo is taken out to the outside for diagnosing the combinational circuit, such as an arithmetic unit. As has been described in the foregoing, according to the present invention, there is no need of providing on the input and output sides of a memory registers which are used for diagnosis only, and a combinational circuit, such as an arithmetic unit, which refers to an internal memory can be diagnosed through utilization of internal registers. It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of the present invention.

Claims: CLAIMS 1. A diagnostic system comprising a plurality of internal registers (12 to 15; 20), an internal memory (11-1, 11-2; 21) for storing various data, and a combinational circuit (16), wherein at least one (13 or 14; 20) of the plurality of internal registers is arranged to be scanned in and out; and during diagnosis said one register (13 or 14;20) is used in place of said internal memory l or 11-2;21) when executing an instruction referring to said internal memory (1In1 or 11-2; 21). 2. A system as claimed in claim 1, wherein the said internal memory (21) has input and output gate groups (C to C Do to Dn) such that during diagnosis the internal inernory (21) will neither accept data for writing therein in response to a memory write enable signal nor read out data therefrom in response to a memory select signal, and wherein the said one register (20) has input and output gate groups ( to An, B to B#) such that 0 during diagnosis the register (20) will accept data for writing therein in response to a memory write enable signal, and will read out data therefrom in response to a memory select signal. 3. A sstem as claimed in claim 1 or 2, wherein the internal registers (12 to 15) are a program counter (12), a flag register (13), a data register (14) and an instruction register (15) of a data processor or logical unit. 4. A system as claimed in claim 3, wherein the combinational circuit (16) is an arithmetic unit of data processor or logical unit.

Inventors: IFUKU, TETSUHIKO C/O FUJITSU LTD. PATENT DPT., INAMASU, SEIICHI C/O FUJITSU LTD. PATENT DPT., SHIOYA, KATSUHIKO C/O FUJITSU LTD. PATENT DPT.
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: G06F11
IPC codes: G06F11