SCANNING ELECTRON-BEAM EXPOSURE SYSTEM

Abstract: In a scanning electron-beam exposure system for expos­ ing a desired rectangular area which is larger than a predetermined maximum rectangle, the desired rectangular area is divided into a plurality of areas. Two sets of such divided areas are shifted two-dimensionally from each other. The one set of divided areas are exposed with half of a predetermined electron-beam dose and the other set of divided areas are also exposed with half of the predeter­ mined dose. This serves to reduce undesirable effects at boundaries between scanned areas.

Description: SCANNING ELECTRO-BEA EXPOSURE SYSTEM The present invention relates to a scanning electron-beam exposure system. In recent years, in semiconductor manufacturing technology, lithography carried out by means of electron beams instead of by means of light has been made possible. Electron-beam lithography is suitable for manufacturing a fine structure. Particularly, in a scanning-type electron-beam exposure system, a pattern is formed directly by using design data. For example, a pattern on a wafer can be exposed without using a mask, and, therefore, the step of manufacturing such a mask is unnecessary. In addition, the number of errors or detects in a pattern is reduced and the flexibility of a pattern is high. Electron-beam lithography can also be applied to the manufacture of a reticle or a photomask. Furthermore, in a scanning-type electron-beam exposure system, in order to improve the throughput, rectangular beam exposure is used, as is a variable rectangular-beam exposure system in which the shape of a beam is variable in view of the flexibility of generating patterns. In the above-mentioned variable rectangular-beam exposure system, even if the shape of a beam is changed, the size thereof has a maximum limit. If this maximum limit is defined as a maximum rectangle, there is no problem in a case where a depicted rectangular pattern is smaller than the maximum rectangle. However, in a case where a depicted rectangular pattern is larger than the maximum rectangle, a plurality of exposure-scanning operations are necessary. In the prior art, when such a large rectangular pattern is depicted, the pattern is divided into a plurality of maximum rectangles exposed by a predetermined exposure dose. Thus, such depicted maximum rectangles are combined into a pattern. In the above-mentioned prior art, however, there is a problem in that the border of each exposed pattern deviates. Such a deviation is due to various factors. One factor is that heat generated by electron-beam exposure accumulates in a resist so that the sensibility of the resist becomes high. Another factor is the problem of beam alignment, or the lifetime of a gun filament. Particularly, the deviation of a border causes harmful effects in the formation of resistance patterns of an analog integrated circuit in a photomask or a wafer. It is desirable to provide a scanning electron-beam exposure system for exposing by an electron bean a desired rectangular area which is larger than a predetermined area, in which system the desired rectangular area is divided into a plurality of areas to be exposed and deviation of the border of the divided areas is prevented. In an embodiment of the present invention, there are prepared two kinds of divided areas two-dimensionally shifted from each other. First, one kind of divided areas are exposed by half of a predetermined electron-beam exposure dose and then the other kind of divided areas are exposed by half of the predetermined electron-beam exposure dose. Since the two different kinds of areas are superposed on each other, deviation of the border of each area is prevented. The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawinqs, by way of example only, wherein: Figs. 1A and 1B are diagrams of a rectangular area divided into a plurality of areas in accordance 'J.j tti prcsrii invention; Fig. 2 is a block diagram illustrating an embodiment of the scanning electron-beam exposure system according to the present invention; Fig. 3 is a circuit diagram of the pattern generator 203A of Fig. 2; and Fig. 4 is a circuit diagram of the pattern generator 203B of Fig. 2. A rectangular pattern stored in a data memory (shown in Fig. 2 but not in Fig. 1) is determined by terminal coordinate information (XO , Y0) and size (X1 , Y1). Here, if the maximum rectangle of an electron bean is defined as S x S, as is illustrated in Fig. 1A, the rectangular pattern is divided into patterns 0 through 6 arranged in the X direction of the coordinates (X0 t Y0), patterns 7 through 13 arranged in the X direction of the coordinates (X0 , YO + S), and patterns 14 through 20 arranged in the X direction of the coordinates -(X0 , V + 2S). In this case, the patterns 6, 13, and 20 are 0 smaller than the maximum rectangle, and the other patterns are the same as the maximum rectangle. On the other hand, as is illustrated in Fig. 1B, the rectangular pattern is divided into patterns 0' through 6' arranged in the X direction of the coordinates (X0 , Y0), patterns 7' through 13' arranged in the X direction of the coordinates (X0 , YO + S/2), and patterns 14' through 20' arranged in the X direction of the coordinates (X0 , YO + 3/2S). In this case, the patterns 0' through 6' are smaller than the maximum rectangle, and the other patterns are the same as the maximum rectangle. That is, the divided patterns illustrated in Fig. 1B are shifted by S/2 in the X direction and by S/2 in the Y direction as compared with the divided patterns illustrated in Fiq. 1A. 1 n an embodiment of the invention, such twg3 too kinds of divided patterns are prepared. first, the patterns 0 through 20, respectively, of Fig. 1A are exposed by half of a predetermined electron-beam dose. Mext, the patterns 0' through 20', respectively, of Fig. ln are exposed by half of the predetermined electron-heam dose. That is, an exposure operation is performed so as to superpose the exposed patterns of Fig. 1A on the exposed patterns of Fig. 1B. As a result, deviation of the border of each of the patterns 0 through 20 and the patterns 0' through 20' is prevented In Fig. 2, which illustrates an embodiment of the present invention, reference numeral 21 indicates a central processing unit (CPU), and reference numeral 202 indicates a data memory for storing rectangular patterns such as the rectangular pattern illustrated in Fig. 1A or Fig. 1B. That is, in this case, the data memory 202 stores terminal coordinate information (Xo , Y0) and size information (X1 , Y1Refernce numerals 203A and 203B indicate pattern generators. For example, the pattern generator 203A generates terminal coordinate information (x0 , y0) and size information (SX X Sy) as parameters corresponding to each divided pattern illustrated in Fig. 1A to a driver circuit 204. Similarly, the pattern generator 203B generates parameters x0 , y0 , SX , and corresponding to each divided pattern illustrated in Fig. 1B to the driver circuit 204. The driver circuit 204 drives a main deflection lens 205 and a slit deflection lens 206 to determine the beam positions x0 and y0 and the beam size Sx and SY A stage-driver control circuit 207 is used for moving a stage of the electron-beam exposure system. The operation of the pattern generator 203A is initiated by a start signal ST1 of the CPU 201 and proceeds with the pulses of a system clock signal CKl. N-sMen exposure of the divided patterns illustrated in piq. IA is completed, the pattern generator 203F generates an exposure end signal ED1 which is transmitted to the CPU 201. Next, the CPU 201 generates a start signal C;T2 to initiate operation of the pattern generator 203B which proceeds with the pulses of a system clock signal CR2. When exposure of the divided patterns illustrated in Fig. 1B is completed, the pattern generator 203B generates an exposure end signal ED2 which is transmitted to the CPU 201. As a result, exposure of the rectangular patterns illustrated in Figs. 1A and 1B is completed. Therefore, the CPU 201 proceeds to expose the next rectangular pattern stored in the data memory 202. The pattern generators 203A and 203B of Fig. 2 are now explained in more detail. In Fig. 3, which illustrates the pattern generator 203A of Fig. 2, a register 301 and an adder 302 are provided in order to generate X-direction coordinate information x0 of a terminal point of a divided pattern, and a register 303 and an adder 304 are provided in order to generate Y-direction coordinate information y0 of a terminal point of a divided pattern. In addition, a register 305, a subtracter 306, a comparator 307, and a selector 308 are provided in order to generate size information S in the X-direction of a divided pattern, x and a register 309, a subtracter 310, a comparator 311, and a selector 312 are provided in order to generate size information S in the Y-direction of a divided pattern. y The operation of the circuit of Fig. 3 is explained with reference to Fig. 1A. First, the CPU 201 generates a start signal Sml, and parameters XO , Yo , X1 , and Y1 are supplied from the data memory 202 to the registers 301, 303, 305, and 309, respectively. Here, the comparator 307 compares X1 with the maximum size S. As a result, since X1 > S, the selector 308 selects the lower input S thereof and, accordingly, Sx = S. In addition, the comparator 311 compares Y1 with the maximum size S. As a result, since > S, the selector 312 selects the lower input S thereof and, accordingly, Sv = S That is, pattern 0 of the parameters (XO, YO, SX, SY) is (XO, YO, S, S). Next, after the driver circuit 204 exposes the pattern 0 with a predetermined dose, the CPU 201 generates a pulse of the system clock signal CK1. As a result, the pattern generator 203A performs an operation for generating the pattern 1 of the parameters shown in Fig. 1A. That is, the value of the register 301 is changed by the adder 302 from XO to XO + S. In addition, the value of the register 305 is changed by the subtracter 306 from Y1 to Y1 - S. In this case, the outputs of the comparators 307 and 311 remain unchanged. Therefore, S =S x S = S. y That is, the pattern 1 of the parameters (x0 , yO , SX , , Sy) is (XO + S, Y0 , S, S). Similarly, the pattern generator 203A performs an operation for generating the pattern 6 of the parameters (x0 , y0 , S , S ) shown in Fig. 1A so that the pattern 6 x of the parameters is (X0 + 6S, Y0 , X1 - 65, S). In this case, X1 - 6S < S. Therefore, the output of the comparator 307 changes so that the selector 308 selects the upper input thereof and the X-direction scanning end signal EX becomes logic "1". In this state, when the next pulse of the system clock signal CKl is generated, a signal EX' becomes logic nlU so that X0 is again stored in the register 301 and the value of the register 303 is changed from Y0 to Y0 + S. In addition, X1 is again stored in the register 305 and the value of the register 309 is changed from Y1 to Y1 - S. In this case, since V - S < S, the selectors 308 and 312 select the lower inputs thereof. Therefore, the pattern 7 of the parameters (x0 , yO , Sx , Sar) is (XO, YO + S, S, S). Finally, the pattern generator 203A performs an operation for generating the pattern 20 of the parameters (x0 , y0 , 5x , Sy ) shorn in Fig. 1.S so that the pattern 20 Or the parameters is (Di + 6S, YO + 2S, X1 - 65, 1 2S). In this case, S1 6 65 5 and Y1 - 2S S. Therefore, the outputs of the comparators 307 and 311 are both loqic "1". As a result, an end signal ED1 is transmitted to the CPU 201, thereby completing the exposure operation. In Fig. 4, which illustrates the pattern generator 203B of Fig. 2, selectors 401 through 404 are added to the elements of Fig. 3. That is, the selectors 401 and 402 are provided so that the first change amount of each of the parameters x0 and y0 is set as S/2, not as S, and the selectors 403 and 404 are provided so that the first comparison reference value of each of the comparators 307 and 311 is set as S/2, not as S. The operation of the circuit of Fig. 4 is explained with reference to Fig. 1B. First, the CPU 201 generates a start signal ST2, and parameters Xo , YO Y X1 , and Y1 are supplied from the data memory 202 to the registers 301, 303, 305, and 309, respectively. Simultaneously, the selectors 401 through 404 select S/2. Therefore, the comparator 307 compares X1 with S. As a result, since X1 > 5/2, the selector 308 selects the lower input 5/2 thereof and, accordingly, 5x = S/2. In addition, the comparator 311 compares Y1 with S/2. As a result, since Y1 > 5/2, the selector 312 selects the lower input S/2 thereof and, accordingly, Sy = S/2. That is, the pattern O' of the parameters (x0 , y0 SX t SY) is (X0 0 Y0 S/2, S/2). Next, after the driver circuit 204 exposes the pattern 0' with a predetermined electron-beam dose, the CPU 201 generates a pulse of the system clock CK2. As a result, the pattern generator 203B performs, an operation for generating the pattern 1' of the parameters shown in Fig. 1. That is, the value of the register 301 is changed by the adder 302 from X0 to XO + S/2. In addition, the value of the register 395 is changed by the subtracter 30s rom il to Y1 2 S/2. In this case, the outputs of the consarators 307 and 311 remain unchanged. However, the selector 403 selects the value S. Therefore, -S x N, That is, the pattern 1' of the parameters (x0 , yO , Sy) is (X0 + S, Y0 , S, S/2). Thus, the pattern generator 203B performs an operation for generating the pattern 6' of the parameters (x0 , YO , S , S ) shown in Fig. 1B so that the pattern x y 6' of the parameters is (X0 + 11/2S, YO , X1 - 11/2S, S). In this case, X1 - 11/2S < S. Therefore, the output of the comparator 307 changes so that the selector 308 selects the upper input thereof and the X-direction scanning end signal EX becomes logic n 1 n . In this state, when the next pulse of the system clock signal CK2 is generated, a signal EX' becomes logic "1" so that X0 is again stored in the register 301 and the value of the register 303 is changed from Y0 to Y0 + S/2. In addition, X1 is again stored in the register 305 and the value of the register 309 is changed from Y1 to Y1 - S/2. In this. case, since vl - S/2 < S, the selectors 308 and 312 select the lower inputs S/2 thereof. Therefore, the pattern 7' of the parameters (x0 , yg SX , Sy) is (X0 , YO + S, S/2, S). Finally, the pattern generator 203B performs an operation for generating the pattern 20' of the parameters (x0 , YO , SX , SY ) shown in Fig. 1B so that the pattern 20' of the parameters is (X0 + 11/2S, yo + 3/25, X1 - ll/2S, Y1 - 3/2S). In this case, X1 - 11/2S < S and yl - 3/2S < S. there fore, the outputs of the comparators 307 and 311 are both logic "1". As a result, an end signal ED2 is transmitted to the CPU 201, thereby completing the exposure operation. In the above-mentioned embodiment, the shift quantities ir the X- and Y-direction between the two kinds of divided patterns are both S,. Ilowever, it should be noted that such shift quantities can be other values only when both the X-direction and the Y-direction are shifted. As was explained above, @ an embodiment of the present invention, deviation of the border of patterns can be protected against.

Claims: CLAIMS 1. A scanning electron-beam exposure system for exposing by an electron beam a desired rectangular area, said desired rectangular area being larger than a prede termined area, comprising: means (202) for generating coordinate information (X0 , Y0) and size information (X1 , Y1) regarding said rectangular area; a first area-dividing means (203A) for dividing said desired rectangular area into a first group of areas to sequentially generate coordinate information (x0 , y0) and size information (SX B Sy) \ regarding each of said first group of rectangular areas, each of said first group of rectangular areas being smaller than said predetermined rectangular area (S x S); ; a second area-dividing means (203B) for dividing said desired rectangular area into a second group of rectangular areas to sequentially generate coordinate information (x0 , y0) and size information (S , S ) regarding each of said second group of rectangular areas, each of said second group of rectangular areas being smaller than said predetermined rectangular area, said first and second groups of rectangular areas being shifted two-dimensionally from each other; and an exposing means (204, 205, 206) for exposing by said electron beam said desired rectangular area, dependent upon said coordinate information and size information regarding each of said first and second groups of rectangular areas. 2. A system as set forth in claim 1, wherein said exposing means exposes said first group of rectangular areas with half of a predetermined electron-bean dose and ::noses said second group of rectanqular areas it half oç said predetermined electron-beam dosc.

Inventors: KAWASHIMA, KENICHI, NAKAGAWA, KENJI, OSADA, TOSHIHIKO
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: H01J37
IPC codes: H01J37, H01L21