SCHOTTKY SHUNT INTEGRATED INJECTION LOGIC CIRCUIT

Abstract: An improved integrated injection logic structure utilizes a current mirror in conjunction with each switching transistor (M₁, M₂) of the integrated injection logic circuit of this invention by connecting one of a plurality of collectors (O₀, P₀) of the switching transistor to the base of said switching transistor. In this manner, the current flowing through conducting switching transistors is limited by the current mirror. This limited current flow through conducting switch­ ing transistors, as well as the use of voltage pull up means (D₁, D₂) connected to the collectors of the switching transis­ tors prevents the saturation of conducting switching transis­ tors. This results in an increase in the voltage on the collectors of conducting switching transistors and a decrease in the voltage swing between a logical one and a logical zero, thereby substantially increasing the speed of the integrated injection logic circuit of this invention as compared to prior art integrated injection logic circuits. The voltage pull up means connected to the collectors of the switching transis­ tors may comprise resistors or preferably forward biased Schottky diodes connected between a voltage source (V dd ) and the collectors of the switching transistors. This invention is also suitable for use in MOS circuits.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to integrated circuit structures and specifically to an integrated injection logic circuit utilizing Schottky diodes to limit the signal swing for logic voltages, thus preventing saturation of the transistors forming the integrated injection logic circuit and thereby resulting in an integrated injection logic circuit having increased switching speeds over prior art circuits. Description of the Prior Art Circuits and structures utilizing integrated injection logic (I2L) are well known in the prior art. I2L structures are particularly suited for the formation of logic gates of a type wherein each gate comprises a pair of merged complementary transistors. In such a gate, a PNP injector transistor is typically used as a current source for supplying current to the base of an NPN switching transistor. The NPN transistor often has multiple collectors which may be used to drive a plurality of other logic elements. Integrated injection logic circuits are compact, operate at very low voltages, and can be fabricated easily and inexpensively utilizing relatively few masking steps. Integrated injection logic circuits and structures have been described in various patents and technical articles. See, for example, an article by H. H. Burger and S. K. Weidman entitled "Merged Transistor Logic (MTL) a Low-Cost Bipolar Logic Concept" and an article by K. Hart and A. Slob entitled "Integrated Injection Logic: A New Approach to LSI", both in the Journal of Solid-State Circuits, Volume SC-7, No. 5, October 1972 at pages 340-346 and pages 346-351, respectively; U.S. patent number 4,286,177 issued August 25, 1981 to Hart and Slob; see also the article by H. H. Berger and S. K. Wiedmann, The Bipolar Oxide Breakthrough", Parts 1 and 2, Electronics, September 4, 1975, pages 89-95 and October 2, 1975, pages 99-103, respectively; and the article by T. Poorter entitled "Electrical Parameters, Static and Dynamic Response of I2L", IEEE Journal of Solid-State Circuits, Vol. SC-12, No. 5, October 1977, pages 440-449; and U. S. Patent No. 3,993,513 entitled ',Combined Method for Fabricating Oxide Isolated Bipolar Transistors and Complementary Oxide Isolated Lateral Bipolar Transistors and the Resulting Structures", assigned to Fairchild Camera and Instrument Corporation, the assignee of this application. A multiple collector structure for bipolar transistors is described in U.S. Patent No. 4,084,174 entitled "Graduated Multiple Collector Structure for Inverted Vertical Bipolar Transistors" of Crippen, Ringarh and Verhofstadt, and also assigned to Fairchild Camera and Instrument Corporation. Each of these articles and patents is hereby incorporated by reference. Figure 1 shows a schematic diagram of a portion of a typical prior art integrated injection logic circuit. PNP Injector transistor T1 serves as a current source, providing current to the base of NPN switching transistor M1. The emitter of transistor T1 is connected to a positive voltage source VEE, the base of injector transistor T1 is connected to ground (veg), and the collector of transistor T1 is connected to input terminal 11, which is used for receiving an input signal Vin. The collector of transistor T1 is also connected to the base of switching transistor Ml. The emitter of transistor M1 is connected to ground (VG & , and transistor M1 contains a plurality of collectors 00 through 03. Each collector 0o through 03 of transistor Ml may be connected to an input lead of another integrated injection logic gate, or may be left floating. For purposes of this specification, collectors Oo through 02 are shown floating, and only collector O3 of transistor M1 is shown connected to a subsequent integrated injection logic gate. PNP injector transistor T2 and NPN switching transistor M2 comprise the second integrated injection logic gate of the circuit of Figure 1. The emitter of PNP transistor T2 is connected to a voltage source VEE and the base of transistor T2 is connected to ground VGG The collector of transistor T2 is connected to collector 03 of. transistor M1, thus receiving as an input signal the output signal provided by collector 03 of transistor M1. The collector of transistor T2 is also connected to the base of switching transistor M2. The emitter of NPN switching transistor M2 is connected to ground. The collectors P0 through P3 of transistor E provide a plurality of open collector outputs for connection to further logic gates or other circuitry if desired. The operation of the prior art integrated injection logic circuit of Figure 1 is as follows. A positive voltage VEE is applied to the emitter of transistor T1. The base of transistor T1 and the emitter of transistor M are connected to ground. The emitter-base junction of transistor T1 is forward biased, thus turning. transistor T1 on. Thus, transistor T1 supplies current from its emitter connected to VEE to its collector connected to the base of switching transistor M1. In actual operation, terminal 11 will not be floating but rather will receive a signal Vin which will be either a logical one (effectively an open circuit, resulting in a high voltage on node N1, typically 0.7 volts,) or logical zero (effectively a short circuit, thus sinking the current made available at node N1 by the collector of injector transistor T1, resulting in a low voltage on node N1, typically 0.1 volts) With a logical one applied to terminal 11, current is not drawn from the collector of T to terminal 11. Thus the injector current made available by the collector of injector transistor T1 is applied to the base and to the base-emitter junction of NPN transistor M1, thereby turning on transistor M1. Thus, transistor M conducts when a logical one is applied to input terminal 11. On the other hand, with a logical zero applied to input terminal 11, current will be drawn from the collector of injector transistor T1 to terminal 11, thus depriving transistor M1 of substantially all of the current supplied by injector transistor T1. With the injector current from the collector of transistor T1 sunk by the logical zero applied to input terminal 11, no current is available to forward bias the base-emitter junction of NPN transistor M11 thereby causing transistor M1 to remain off. Thus, transistor M1 does not conduct when a logical zero is applied to input terminal 11. PNP injector transistor T2 operates in a manner similar to injector transistor T1. A positive voltage VEE is applied to the emitter of transistor T2 and its base is connected to ground (veg). Thus, the emitter-base junction of transistor T2 is forward biased thus turning transistor T2 on. With transistor M1 conducting (logical one on input terminal 11), the current available from the collector of injector transistor T2 is sunk through collector O3 of transistor M1 to ground (logical zero on node N2), thus depriving transistor N2 of base current, thereby maintaining transistor N2 off. On the other hand, with transistor M1 off (logical zero on input terminal 11), injector current supplied by transistor T2 is not sunk by collector O3 of transistor M1, but rather provides the base current to transistor M2. This base current flows from the base to the emitter of transistor M2, thus turning transistor M2 on. In this manner, the circuit of Figure 1 allows a single input signal Vin to generate a plurality of output signals to be applied to various gates and circuits as desired. For example, input signal Vin provides four inverted signals on open collectors 0o through 03 which are applied to other circuits as desired. Furthermore, the inverted input signal available on collector O3 of transistor M1 is used to generate four non-inverted open collector signals on collectors P0 through P3 of transistor M2. The fact that switching transistors M1 and g each are shown with a plurality of four collectors serves as an example only, and it is not be interpreted that the switching transistors utilized in accordance with this invention must contain four collectors. In fact, a greater or lesser number of collectors may be utilized in accordance with well known semiconductor principles. However, as the number of collectors is increased, the capacitance of the device increases, thereby decreasing the switching speed of the circuit. Furthermore, it is well known that a plurality of input signals may be connected to nodes N1 and N2 of Figure 1, thus providing for wired NAND logical operations on a plurality of input signals. For example, if a plurality of input terminals (not shown) are connected to node N1 as is input terminal 11 of Figure 1, the signal on each input terminal connected to node N1 must be a logical one to turn transistor M1 on, thus grounding (logical zero) output leads 0o through 03 of transistor Mt. Conversely, a single logical zero on any input terminal connected to node N1 will sink the injector current provided by transistor T, thus causing transistor M1 to turn off and provide a logical one on output leads 0o through 03 of transistor M1. Thus the additional input leads connected to node N1 perform a wired NAND logic function. One limitation of the prior art integrated injection logic circuits, such as the one shown in Figure 1, is that upon the creation of a high voltage (typically 0.7 volts) on input terminal 11 (i.e. when a logical one applied to input terminal 11), transistor M7 turns on, thus decreasing the voltage on node N2 to- Vsl, where V51 is the collectoremitter voltage of transistor M1 when M1 is saturated. Similarly, with a low voltage (typically around 0.1 volts) applied to input terminal 11, transistor M1 turns off, and the voltage on node N2 is approximately VEE - V52, where V52 is equal to the emitter-collector voltage of transistor T2 when transistor T2 is conducting. For typical I2L circuits, VEE = 0.8 volts, V51 = 0.1 volts, and VS2 = 0.1 volts. Thus, the voltage on node 2 ranges from Thigh of approximately 0.7 volts (logical zero on input terminal 11, transistor M1 non-conducting) to Vlow of approximately 0.1 volts (logical one on input terminal 11, transistor M conducting). Thus, node N2 experiences a rather large voltage swing (0.6 volts) between its logical zero and logical one states. This results in the prior art integrated injection logic circuit of Figure 1 being slow due to the time required to increase the charge on the capacitances of nodes N1 and N2 so as to change the voltages on these nodes from 0.1 volts to 0.7 volts when nodes N1 and N2 change from logical zero to logical one and the time required to decrease the charge on the capacitances of nodes N1 and N2 so as to change the voltages on these nodes from 0.7 -volts to 0.1 volts when nodes N1 and N2 change from logical one to logical zero. Furthermore, the prior art I2L circuits such as the circuit of Figure 1 cause the switching transistors (M1 and M2 of Figure 1) to saturate when turned on, thus requiring a relatively large period of time to turn off and on as compared to transistors which are not operated in saturation. The I2L circuit of Figure 1 has been modified to provide prior art I2L circuits with increased speed. For example, an article entitled "ISL, A Fast and Dense Low Power Logic, Made in a Standard Schottky Process" written by Lohstroh, IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 3, June 1979, pages 585-590 describes integrated injection logic circuits utilizing Schottky diodes, and is hereby incorporated by reference. In Lohstroh's Figure 1, a plurality of Schottky diodes are connected in series with a single collector in order to drive a plurality of outputs. These Schottky diodes serve to reduce the voltage swing between high and low output signals as compared with the prior art I2L circuit of Figure 1. This arrangement does not prevent saturation of the switching transistor, and the output voltage swing between high and low states is temperature dependent and influenced by DC voltage offsets between sequential stages of logic. The circuit of Lohstroh's Figure 2 adds an additional Schottky diode to prevent saturation of the switching transistor. However, Lohstroh admits that this arrangement is not producible in a standard process, because two types of Schottky diodes are needed with different Schottky barrier heights. Furthermore, the circuit of Lohstroh's Figure 2 is temperature dependent and adversely influenced by DC voltage offsets between consecutive logic stages. The ciruit of Lohstroh's Figure 3 provides a different technique to prevent saturation of the switching transistor. However, this circuit is also temperature dependent and adversely affected by the DC voltage offsets between consecutive logic stages. An article by Peltier entitled "A New Approach to Bipolar LSI: C3L", 1975 IEEE International Solid-State Circuits Conference, Friday, February 14, 1975, pages 168-169 describes yet another prior art integrated injection logic circuit, and is hereby incorporated by reference. Peltier's structure utilizes a plurality of Schottky diodes connected in series with a single collector to provide a plurality of outputs. Peltier utilizes a Schottky transistor as the switching transistor in order to provide a saturation voltage which is not as low as the saturation voltage of NPN switching transistors, as well as to minimize charge storage within the switching transistor. The Peltier circuit is also temperature dependent, and adversely affected by DC offset voltages between consecutive logic stages. SUMMARY This invention overcomes several disadvantages of prior art integrated injection logic circuits by providing an integrated injection logic circuit in which the switching transistors are prevented from saturating during conduction and in which the voltage swing between high and low states is limited to approximately 0.1 volts. A current mirror, wherein maximum current flow through a collector is controlled by the current flow through an associated reference collector, is utilized in conjunction with each switching transistor of the integrated injection logic circuit of this invention by connecting one of a plurality of the collectors of each switching transistor to its base. In this manner, the current flowing through conducting switching transistors is limited by the current mirror. This limited current flow through conducting switching transistors, as well as the use of voltage pull up means connected to the bases of the switching transistors, prevents the saturation of the conducting switching transistors. This results in an increase in the voltage on the collectors of conducting switching tran-' sistors corresponding to a logical zero, and thus a decrease in the voltage swing between a logical one and a logical zero, thereby substantially increasing the speed of the integrated injection logic circuit of this invention as compared to prior art integrated injection logic circuits. The voltage pull up means connected to the bases of the injector transistors may comprise resistors or, preferably, forward biased Schottky diodes connected between a voltage source and the bases of The switching transistors. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a prior art integrated injection logic circuit; Figure 2 is a schematic diagram of an integrated injection logic circuit constructed in accordance with this invention; Figure 3 is a graphical representation of the relationships between the voltage and current characteristics of one output collector of a switching transistor such as M1 or M2 of the integrated injection logic circuit of Figure 2; Figure 4 is a schematic diagram of a circuit for providing a voltage Vdd to the Schottky diodes utilized in the circuit of Figure 2; and Figure 5 is a schematic diagram of a circuit constructed in accordance with this invention which utilizes metal-oxide-silicon transistors. DETAILED DESCRIPTION Figure 2 shows an integrated injection logic circuit constructed in accordance with this invention. Transistors T1 and T2 are shown as means for providing current to nodes N1 and N2 respectively, although other current sources (such as a resistor or a diode connected to a voltage source) may be utilized. Schottky diodes D1 and D2 are connected between terminal 13 and nodes N1 and N21 respectively. The collector 0o of transistor M1 is con nected to the base of transistor M1, and the collector P0 of transistor M2 is connected to the base of transistor M2. Collectors Oo and P0 form current mirrors which serve to limit the current floW through collectors 0l through 03 and P1 through P3, as is more fully described below. It is believed that PN diodes may not be used in place of Schottky diodes D1 and D2 due to excessive minority carrier charge storage within the EN diode during forward bias, resulting in the rather slow switching speeds of PN diodes. As a feature of this invention, a current mirror is formed by connecting one of the plurality of collectors of each switching transistor to its base (Fig. 2). For example, collector Oo of switching transistor M1 is connected to the base of M1. Similarly, the collector Po of switching transistor M2 is connected to the base of transistor M2. Due to the high current gain or Beta of switching transistor M1 (typically approximately 10-20), substantially all of the injector current supplied by injector transistor T1 flows to the collector O0 of transistor M1 when a logical one (i.e. open circuit) is applied to input terminal 11. The current through collector 0o in turn flows to the emitter of transistor M1 which is grounded. This connection between the base of transistor M1 and collector 0o provides a relatively constant collector current lo through collector 00. Collector current lo is determined by the magnitude of VEE (typically 0.8 volts), and the electrical characteristics of transistors T1 and M1. For a circuit fabricated with transistors of 0.5 microns by 0.5 microns per collector, preferably collector current lo is set at approximately 25 microamps in order to achieve a gate speed, with a fan out of four, of approximately 50 picoseconds. The base current, the base-emitter voltage of transistor M1 and the collector area determine the collector current of each of collectors 0o through 03 of transistor M1. Because The base current and baseemitter voltage are the same with respect to each collector 00 through 03 of transistor M1, the following equation defines the collector currents: Ia/Io = Aa/AO where Ia = the collector current of collector a' where a is an integer ranging from 1 to 3; Io = the collector current of collector O; Aa = the collector area of collector a; and Ao = the collector area of collector 0o Preferably the areas of collectors Cl through 03 are constructed to be twice the area of collector 00. In this manner, the collector current capable of being sunk by each of collectors Ci through 0¯3 is equal to 2Io. In fact, the collector current Io of collector 0o is equal to slightly less than the current supplied by the collector of injector transistor T21 because a small portion l/(l+ss) of the current supplied by injector transistor T2 forms the base current of transistor M2. Here ss is the ratio of collector current to base current of transistor T2. However, this difference is negligible and for the purposes of this specification it will be assumed that all the injector current supplied by the injector transistors T1 and T2 form the collector current of the current mirrors (collectors CC and P0). Thus, while injector transistor T2 supplies a current Io to node N2 to turn transistor M2 on, transistor M1 (when on) sinks a current 2Io from node N2, thus causing transistor M2 to turn off. Of this current 2Io sunk by transistor M1, half (Io) is provided by injector transistor T2 and half (iso) is provided by Schottky diode D2. Thus Schottky diode D2 conducts, thus causing the voltage VN2 On node N2 to equal Vdd (node 13) minus Vsk, (the voltage drop across a forward biased Schottky diode which is approximately 0.6 volts). Terminal 13 is connected to a positive voltage supply Vdd, and serves to provide current to Schottky diodes D1 and D2 connected to nodes N1 and N2 respectively. Schottky diodes D1 and D2 limit the low voltage on nodes N1 and N2 by supplying current in addition to the current made available by injector transistors T1 and T2. Thus, when node N2 is low the voltage on node N2 is equal to Vlowt where Vlow is equal to the voltage Vdd applied to terminal 13 minus the forward biased voltage drop Vsk of Schottky diode D2. Thus, for example, utilizing Schottky diode D2, the lower voltage limit of node N2 is raised from Vsl, the collector-emitter saturation voltage of transistor M1 (as previously described in conjunction with the prior art integrated injection logic circuit of Figure 1), to Vlow In this manner, the voltage swing between a logical one and a logical zero at nodes N1 and N2 is substantially reduced as compared with prior art 12L circuits. The reduced voltage swing between the two logic levels used in a binary logic circuit results in increased switching speed over prior art integrated injection logic circuits. Additional Schottky diodes are connected between Vd¯ (terminal 13) and all other bases which are used as input terminals of all other switching transistors (e.g. bases to which collectors Cl and O, of transistor M1 and collectors P1 and P2 of transistor M2 are connected) although these additional switching transistors and Schottky diodes are not shown in Figure 2. Collector 0o and P0 are not used as output terminals because they are used to form the current mirrors, as previously described. Thus, transistors E and E of the circuit of Figure 2 have a fan out of three. Node N1 is connected to VIN, which is typically made available on a switching transistor collector (not shown). Thus, Schottky diode D1 serves to prevent saturation of the switching transistor (not shown) providing VIN connected to node N1. In the I2L circuit constructed in accordance with this invention having a fan in of four, the'voltage V1 is approximately 0.6 volts, and the voltage Vhigh is approximately 0.7 volts. Thus, the voltage swing of nodes N1 and N2 between a logical one and a logical zero is approximately 0.1 volt, as compared with the voltage swing of approximately 0.6 volts of the integrated injection logic circuit of Figure 1. For circuits constructed in accordance with this invention having fan ins less than four, it is advantegeous to use a voltage swing between logical states of as little as 0.05 volts (for a fan in of one) to further reduce power and increase speed. Conversely, for circuits constructed in accordance with this invention having fan outs greater than four, it is advantageous to use a voltage swing between logical states which is greater than 0.1 volts to provide increased noise immunity. However, this increase in voltage swing need not be great - for a fan out of eight, a voltage swing of 0.12 volts provides adequate noise immunity. In one embodiment of this invention, Schottky diodes D1 and D2 are connected through terminal 13 to VEE (that is Vdd is replaced by VEE), the positive voltage supplied to the emitters of injector transistors T1 and T2. The connection of terminal 13 to VEE provides an integrated injection logic circuit in accordance with this invention having increased switching speed over the prior art integrated injection logic circuits. However, connecting Schottky diodes D1 and D2 (terminal 13) to VEE results in a circuit whose characteristics exhibit an undesirable change over operating temperature. For example, as the operating temperature of the device increases, the voltage swing between a logical zero and a logical one decreases. For a sufficiently low voltage swing between logic states, the circuit ceases to function. Furthermore, as the operating temperature of the device decreases, the voltage swing between a logical zero and a logical one increases7 thus -decreasing the speed of the device. In order to eliminate The undesirable temperature characteristics which result when terminal 13 is connected to VEE, a second embodiment of this invention connects terminal 13 to a second positive voltage source other than VEE. For example, many integrated injection logic circuits derive their power from a voltage Vcc of approximately S volts. From this 5 volt Vcc supply suitable circuitry is utilized to generate various bias voltages, such as 5 volts for transistor-transistor logic (TTL) or approximately 0.8 volts for integrated injection logic (I2L). This is typically how VEE is generated on a semiconductor chip, thus allowing the entire chip to be supplied by a single supply voltage Vcc. In the same manner, a voltage Vdd may be generated from Vcc and applied to terminal 13 to drive Schottky diodes D1 and D2. The voltage of Vdd is typically (at room temperature) approximately 1.0 to 1.2 volts although any voltage capable of providing current to Schottky diodes D1 and D2 sufficient to make the voltage swing on nodes N1 and N2 approximately 0.1 volts between a logical high and a logical low is sufficient. When the semiconductor device contains a plurality of integrated injection logic gates, each gate will have with it an associated Schottky diode connected to Vdd. Figure 4 is the schematic diagram of a circuit which is used to provide voltage Vdd on terminal 13, which corresponds with terminal 13 of Figure 2. Biasing circuit 100 comprises PNP injector transistor 81 having its base connected to ground (VGG), its emitter connected to a positive voltage source VEE, and its collector connected to the base of NPN transistor 80. NPN transistor 80 is identical to the switching transistors M1 and M2 of Figure 2 in order that the electrical characteristics of transistor 80 closely match the electrical characteristics of transistors M1 and M2. Similarly, PNP injection transistor 81 is identical PNP injection transistors T1 and T2 of Figure 2. PNP injection transistor 81 provides base drive to NPN transistor 80, thus forward biasing the base-emitter junction of NPN transistor 80, thereby turning on transistor 80. The emitter of transistor 80 is connected to ground (VGG). Thus at 250C the voltage VREF on the base of transistor 80 is equal to approximately 0.7 volts, the voltage drop across a forward biased PN junction. The collector 80-0 of transistor 80 is connected to the base of transistor 80. Because transistors 81 and T1 and transistors 80 and M1 are well matched, as previously described, a collector current flows through collector 80-0 which is equal to The collector current 1o flowing through The collector Cl forming the current mirror of transistor M1 (Figure 2). Because the area of collector 80-1 is twice the area of collector 80-0, collector 80-1 will sink 2Io, as previously described for the current mirror formed by collector 00 of transistor M1. Voltage regulator 78 receives Vsupply as an input voltage to-be-regulated, and provides a regulated output voltage Vdd in response to a feedback signal on lead 103 from comparator 79. Output terminal 13 of voltage regulator 78 is connected to the Schottky diodes D1 and D2 of Figure 2, as well as to the anodes of 100 Schottky diodes S2 5100 connected in parallel as shown in Figure 4. The use of 100 Schottky diodes S1 through S100 is a simple and inexpensive technique for providing a voltage Vdd which results in a voltage swing on the collectors of the switching transistors (e.g. transistors M1 and M2 of Figure 2) of approximately 0.1 volt between a logical high (0.7 volts) and a logical low (0.6 volts), as is more fully explained below. The cathodes of Schottky diodes S1 S2 S100 are connected to collector 80-1 of tran- sistor 80. Because collector 80-1 of transistor 80 sinks 2Io, as previously described, a current equal to 21o is drawn from voltage regulator 78 through Schottky diodes S1, S2..... S100, through collector 80-1 to ground. The input lead 101 of voltage comparator 79 is connected to the cathodes of Schottky diodes S1, S2.... S100' and the input lead 102 of comparator 79 is connected to the base of transistor 80 (0.7 volts). The output lead 103 from voltage comparator 79 is connected to voltage regulator 78, thereby providing a feedback signal to voltage regulator 78 which in turn controls the voltage Vdd on terminal 13. When the voltage Vx on The cathodes of Schottky diodes S11 S, 5100 exactly equals the voltage on the base of transistor 80 (0.7 volts), the signal on output lead 103 from comparator 79 is effectively equal to zero, and thus, the voltage Vdd remains constant. If The voltage Vx is greater than the voltage VREF on the base of switching transistor 80, a feedback signal is applied from lead 103 of comparator 79 to regulator 78, thus causing regulator 78 to decrease the voltage Vdd. On the other hand, if voltage Vx is less than voltage VREF, a signal will be applied from lead 103 of comparator 79 to regulator 78 causing regulator 78 to increase the voltage Vdd In this manner, the voltage Vx is regulated to be substantially equal to The voltage (0.7 volts). The current/voltage relationship. of a PN junction is defined as: I = 1x [ exp(qV/kT)-l ] (1) where I = the current through the PN junction; Ix = the thermal current of charge carriers through the PN junction in either direction at zero bias; q p the charge of an electron (1.60 x 10-19 coulomb); V = the voltage across the PN junction; k = Boltzmann's constant (1.38x10 23 Joules/0K); T = temperature, in K. Thus, the voltage Vdd is defined in the following equation: 2Io/100 = Ix[exp(q(Vdd-vx)/kT)-l] (2) where 2Io/100 = the current flow through each Schottky diode S1, S2....S100; and Vx = the voltage on the cathodes of Schottky diodes S1, S2..... S100, which is regulated to equal 0.7 volts. Similarly, the voltage/current relationship of a single Schottky diode (e.g. D2 of Figure 2) connected between Vdd and a collector of a switching transistor, when the switching transistor is turned on is defined as: Io = Ix [exp(q(Vdd-Vlow)/kT)-1] (3) where 1o = the current through the Schottky diode D2 which is sunk by the collector of the switching transistor; and Vlow = the (logical zero) voltage on node N2 when switching transistor M1 is con ducting. From equations (2) and (3): [exp(q(Vdd-Vlow)/kT-1] = 50[exp(q(vdd-Vx)/kT)-1] (4) OR Vlow = 0.7 -(kT/q)¯n 49 (5) Vlow = 0.6 volts at 250C (6) Thus, the voltage Vlow on the collectors of injector transistors T1 and T2 (Fig. 2) when transistors M1 and M2 are conducting is equal to 0.6 volts, as compared with the low voltage of 0.1 volt in prior art I2L circuits. The switching transistors M1 and M2 of the I2L circuit constructed in accordance with this invention do not saturate, and the voltage swing at room temperature between a logical one and a logical zero is reduced from 0.6 volts in conventional prior art I2L circuits to 0.1 volt in the present invention. Furthermore, as seen from equation (5), the voltage swing between a logical one and a logical zero is equal to V -V low = (#/#)±n 49 (7) within the range of circuit operating temperatures. In this manner, circuit operating margins are preserved over temperature. In the embodiment of this invention shown in Figure 2, close regulation of currents is achieved by basic 12L techniques and by the use of current mirrors. Shunt pull-up diodes D1 and D2 limit the voltage swing between logical states, with the voltage swing being determined, as shown in equation (7), by the ratio of switching transistor collector current when the switching transistor is conducting to switching transistor collector current when the switching transistor is not conducting. The relation between the switching transistor currents when conducting and when not conducting therefore set circuit margins. For example, the ratio of the maximum switching transistor M1 collector current Io3MAX (approximately 2Io) to the switching current of switching transistor M1 (iso) is equal to approximately 21o/1o=2 and is the margin by which switching transistor M1 is held on and the voltage on node N2 is held low. Similarly, the ratio of the switching current Io of switching transistor M1 to the minimum current drawn from node N2 through collector 03 by outputs connected to node N, is The margin by which switching transistor M1 is held off and the voltage on node N2 held high. For the circuit of Figure 2, the ratio of switching current Io to minimum current drawn from collector 03 through node N2 when switching transistor M1 is off is equal to Io/[(Fin)(.02)(2Io)] where Fin is equal to the fan in, and (.02)(2I) represents the current through collector 03 through each input lead connected to node N2 when node N1 is at logical zero and switching transistor M1 is turned substantially off. This current (0.2)(2Io) when switching transistor M1 is turned off is described more fully below. Thus, this ratio is equal to 1/0.12 or approximately 8.3 when a fan in of 3 is used. In other words, these margins, expressed in terms of currents, are (2Io-Io) = 10 and (Io-0.12Io)=.88Io, respectively, for the high and low states of The voltage on node N2. The temperature behavior of equation (7.) exactly corresponds to the temperature behavior not-only of. Thermal (Johnson) noise voltage but also of the dynamic impedances of the connected junctions, thus tending to preserve noise margins over temperature. Figure 3 is a graphical representation of the current 103 through collector O3 of transistor M1 for various voltages appearing on node N2.. In addition, the "static" components of the collector current 103 are shown. For example, Ip shows the callector.current which flows through collector O3 in the prior art integrated injection logic circuit of Figure 1. The current Ip is limited essentially to the collector current of injection transistor T2. The line Ischottky shows the contribution to the collector current flowing through collector O3 of The embodiment of this invention shown in Figure 3 due to the presence of Schottky diode D2. The total current due to each of these two components is shown in the line labelled Itotal It is This current, 1total' which flows through collector O3 up to the limit of 21o (approximately 2IpmaX) as discussed previously. ,1 The currents shown in Figure 3 are called "static" currents because they do not include currents which flow in order to change the charge stored in the capacitances of the circuit due to charging voltage levels during switching. For the purposes of this specification, it is to be understood that the currents represented in Figure 3 are these so-called "static" currents. As can be seen by the graphical representatation of Figure 3, at higfl voltages (i.e. a logical one) on node N2, the total collector current 1total is formed primarily by the contribution due to the presence of prior art integrated injection logic circuit components. However, with a logical one on node N2, the current 1total is somewhat greater as compared with prior art I2L circuits because the switching transistor M1 (Fig. 2) is not turned completely off when node N1 is at a logical zero. A logical zero on node N1 corresponds to approximately 0.6 volts, as compared with a logical zero of approximately 0.1 volt in prior art I2L circuits. However, with a logical zero (0.6 volts) on the base of switching transistor M1, the collector current 1p is equal to only approximately two percent (2%) of the maximum collector current Isat (i.e. with a logical one equal to C. 7 volts connected to the base of switching transistor M1) per output lead connected to node N2. For example, if two output leads are connected to node N2 (from two separate logic gate outputs in a "wired NAND" configuration,' previously described), sufficient base current to node N2 is provided by the logical zero (0.6 volts) state of the two driving gates to cause a pull-down current at node N2 which is equal to approximately four percent (4%) of the maximum collector current 1sat which flows when transistor M1 is saturated. However, this small current which flows when the driving gates are "off" does not adversely affect circuit operation. When the voltage on node N1 is increased from the low state to the high state, collector current 103 of transistor M1 increases, thus causing voltage Vn2 on node N2 to decrease. As the voltage V. on node N2 decreases, additional shunt current is supplied by Schottky diode D2, thus increasing the total collector current Itotal as compared with the saturated current 1sat of collector O3 of transistor M1 which would flow in the circuit of Figure 1. In this manner, Schottky diode D2 supplies current which is otherwise unavailable in a prior art integrated injection logic circuit, thus preventing the voltage Vn2 on node N2 from decreasing to Vsl, the collector-emitter voltage of transistor M1 when transistor.N1 is saturated. This increases the voltage on node N2 when node N2 is low level (logical zero) as compared with prior art I2L circuits. Due to the decrease in the voltage swing between logical one and logical zero, the change of charge stored in the capacitance associated with node N2 due to switching between a logical zero and a logical one is also decreased thereby providing increased switching speeds of the integrated injection logic circuit of this invention as compared with the switching speeds of prior art integrated injection logic circuits. As shown in Figure 3, the use of Schottky diodes in accordance with this invention limits the low level voltage excursion of voltage Vn2 on node N2. In prior art integrated injection logic circuits, when transistor M1 of Figure 1 turns on, current equal to 15at flows from node N2 through the collector O3, thus resulting in a voltage Vs1 equal to approximately 0.1 volt on node N2 where V is the saturation voltage of the collector-emitter voltage of M1 Of importance, when Schottky diodes are utilized in accordance with this invention as in Figure 2, the low level (logical zero) voltage on node N2 is limited (as shown in Figure 3) to Vlow = Vdd-Vsk' where V low is the voltage associated with a logical zero; Vdd is the voltage applied to Schottky diodes via terminal 13; and Vsk is the forward bias voltage drop across Schottky diode D2 with a current lo flowing through Schottky diode D2, as previously described. Thus, as previously described, the low level (logical zero) voltage V on node N2 is equal to approximately 0.6 volts. The.high level (logical one) voltage Thigh on node N2 is equal to VEE-Vs2, because in a similar manner as previously discussed with regard to the prior art circuit of Figure I, node N2 is not pulled down by the non-conducting transistor M1. Thus, with VEE=0.8 volts and VS2=0,1 volts, a logical one on node N2 is equal to approximately 0.7 volts. The voltage swing on node N2 between a logical high and a logical low is equal to Vhigh minus V low = A V which is approximately equal to 0.1 volts. In comparison, prior art integrated injection logic circuits provide a voltage swing on node N2 equal to thigh minus VVS1 which is approximately equal to 0.6 volts.. The integrated injection logic circuit of this invention utilizing bipolar transistors consumes more power than prior art integrated injection logic circuits. The current consumption of an integrated injection logic circuit constructed in accordance with this invention is approximately twice as great as the current consumption of a prior art integrated injection logic gate utilizing approximately the same injector current supplied by the PNP injector transistor having its emitter connected to VEE. The additional current consumption is due to the presence of one Schottky diode per gate. Utilizing small geometry, such as 0.5 micron line widths, integrated injection logic circuits may be constructed in accordance with this invention having switching speeds of approximately 50 to 100 picoseconds, while utilizing a fan-out of four, with an injector current of approximately 25 to 50 microamps per gate. A circuit constructed in accordance with this invention, utilizing metal-oxide-silicon (MOS) transistors, is shown in Figure 5. Input terminals 301, 302, 303, and 304 receive input signals Ioi Il, 12 and I3, respectively. Terminals 0o through 03 and P0 through P3 serve as open source output terminals which may be connected (as is terminal 03) to other circuitry, as desired. A resistive voltage divider comprising resistors 306 and 307 is connected between terminal 305 connected to a voltage Vdd, and ground such that a fraction of the voltage Vdd (denoted as Vhigh) is applied to input node 310. The voltage Vhigh established by the voltage divider ccmprising resistors 306 and 307 provides the high level logic signal (arbitrarily defined as a logical "one") on input node 310. With logical ones applied to input terminals 301 through 304, the signal on node 310 is a logical one. On the other hand, if any signals Io through I3 applied to input terminals 301 through 304 is a logical zero (low voltage), input node 310 is pulled down to that low voltage. In a manner similar to the circuit of Figure 2, Schottky diode 309 connected between terminal 308 and input node 310 limits the voltage on node 310 corresponding to a logical zero. Input terminal 308 is connected to a voltage supply Vsch which is utilized to power the Schottky diodes of the circuit. The voltage on input node 310 is connected to the gates of MOS switching transistors 311-0 through 311-3, thus providing open source outputs o0 through 03, respectively. Each output terminal Oo through 03 may be connected to input nodes of additional logic gates,- as desired. Furthermore, the number of switching transistors associated with each logic gate need not be four as shown in Figure 5, but may be any desired number consistent with good MOS semiconductor design practice. Preferably the voltage Vlow corresponding to a logical zero is set to approximately 0.9 volts (corresponding to a Vsch of approximately 1.4 volts, and the voltage Vhighl corresponding to a logical one, is set to approximately 1.2 volts by Vdd and resistors 306 and 307. This results in a voltage swing between a logical dne and a logical zero of approximately 0.3 volts. This voltage swing is less than prior art MOS logic circuits designed for low voltage swings in which the logical one state is typically 1.5 volts and the logical zero state is typically 0 volts. As stated previously with respect to the logic circuit of Figure 2 which is constructed in accordance with the invention utilizing bipolar transistors, the reduced signal swing between the logical one and She logical zero will result in increased speed due to the reduced amount of time required to change The charge stored in the node capacitances of this circuit. Furthermore, the speedpower product of the circuit constructed in accordance with this invention utilizing MOS devices is less than the speed-power product of a comparable MOS logic circuit of the prior art. An improved version of the circuit Figure 5 substitutes for resistor 307 an additional Schottky diode having its anode connected to input node 310 and its cathode connected to a second Schottky reference voltage, VsCh2* Similarly, resistor 407 is replaced by a Schottky diode having its anode connected to node 410 and its cathode connected to the reference voltage Vsch2. In this manner, the additional Schottky diodes establish the voltage Vhigh corresponding to a logical one equal to VsCh2 plus one forward biased Schottky diode voltage drop. For a typical value of Vsch2=0.7 volts, and a forward biased Schottky diode voltage is equal to 0.5 volts, is equal to 1.2 volts. The bias voltages Vsch (connected to Schottky diodes 309 and 409) and v (connected to the Schottky diodes replacing resistors 307 and 407 of Figure 5) can be set and controlled over a wide temperature range by the technique embodied in Figure 4, previously described in conjunction with the circuit constructed in accordance with this invention utilizing bipolar transistors. While several embodiments of this invention have been disclosed in this specification, these embodiments are not limitations of the scope of this invention. Other embodiments will become apparent to those skilled in the art in light of this specification.

Claims: CLAIMS 1. An integrated injection logic circuit comprising: means (Tl) for providing an injection current; a switching transistor (Ml) connected to said means for providing an injection current, said switching transistor having an input node (N1) and an output node (03) characterized by comprising: means for preventing the saturation of said switching transistor, wherein said means for preventing comprises a voltage pull up means (Vdd, D1) connected to said input node of said switching transistor. 2. Circuit as in Claim 1 characterized in that said pull up means comprises a diode (D1) connected between a voltage source (Vdd) and said input node (N1). 3. Circuit as in Claim 1 characterized by further comprising means for limiting the current through said switching transistor. 4. Circuit as in Claim 3 characterized in that said switching transistor comprises a plurality of output nodes (00, 01, 02, 03) and said means for limiting comprises a current mirror including one of said output nodes. 5. Circuit as in Claim 1 characterized in that said switching transistor comprises a bipolar transistor (M1) having a base, an emitter and a plurality of collectors; and said pull up means comprises a plurality of conductive devices, one said conductive device (D1) connected to said base. 6. Circuit as in Claim 5 characterized in that said switching transistor further comprises an additional collector connected to said base, thereby forming a current mirror limiting the current flow through each of said plurality of collectors. 7. Circuit as in Claim 6 characterized in that the low and high voltage on said plurality of collectors are equal to approximately 0.6 volts and 0.7 volts respectively. 8. Circuit as in Claim 1 characterized in that said pull up means comprises a resistor in parallel with a diode connected between a first voltage source and said input node of said switching transistor and a resistor connected between a second voltage source and said input node. 9. Circuit as in Claim 1 characterized in that said pull up means comprises a resistor in parallel with a diode connected between a first voltage source and said input node of said switching transistor and a diode connected between a second voltage source and said input node. 10. Circuit as in Claims 2, 8 or 9 characterized in that said diodes are Schottky diodes.

Inventors: EARLY, JAMES M.
Applicants: FAIRCHILD SEMICONDUCTOR CORPORATION
Application year: 1983
Main classification: H01L27
IPC codes: H01L21, H01L27, H03K19, H01L29