SEMICONDUCTOR DEVICES INCLUDING LATERAL-TYPE TRANSISTORS

Abstract: A semiconductor device comprises at least one lateral-­ type PNP transistor (31) having a collector region (31c), an emitter region (31e), a base region (31b), and partially extended emitter wiring (37) covering the base region, to protect against channel leakage. The collector and emitter regions directly contact an isolation region (41), but the base region contacts the isolation region via a projection (42), preferably formed integrally with the isolation region. The partially extended emitter wiring may also extend over the projection, which possibility can serve to accommodate manufacturing tolerances that would otherwise reduce the degree of integration that could be achieved reliably.

Description: SEMICONDUCTOR DEVICES ,INCLUDING LATERAL-TYPE TRANSISTORS. The present invention relates to semiconductor devices including lateral-type transistors. As is well known, lateral-type transistors are transistors in which both an emitter and a collector are arranged on the same surface layer of the semiconductor substrate. This type of transistor is used, for example, as a load element in the memory cells of some memory circuits. Thus, lateral-type PNP transistors (herein after, "PNP transistor") have a construction similar to that of conventional P-channel MOS transistors; the N-type base region of PNP transistors resembles the channel in P-channel MOS transistors. Such PNP transistors may suffer from so-called channel leakage. Channel leakage is caused by conduction between the emitter and collector of a PNP transistor that arises when negative (-) charges (usually called "contamination") are injected into an insulation layer formed on the base region. It should be understood that this problem of channel leakage is already well known. In order to avoid channel leakage, it has been proposed to mount above the base region, an electrode to which positive (+) voltage is applied, such that said negative charges are attracted toward the upper side of said insulation layer. The above-mentioned positive electrode may easily be formed above the base region when the IC is not densely packaged. However, with the recent increase in IC packaging densities, the smallness of the area that is generally available for mounting the positive electrodes may make it difficult to ensure that these positive electrodes are able to achieve their intended function of preventing channel leakage. In the prior art, if the widths of the individual electrodes are made as small as possible, such as to attain higher IC packaging densities, a problem arises in that the smaller the width, the more likely that the insulation layers are not completely covered by the respective positive electrodes. Thus, even though a positive electrode is actually present here in each PNP transistor, if the bases of the transistors are not fully covered, the PNP transistors may still exhibit channel leakage. An embodiment of the present invention can be made to provide a lateral-type PNP transistor having a P-type collector region, a P-type emitter region, and an N-type base region, all of which contact an isolation region, the isolation region projecting partially into just said base region. Reference will now be made, by way of example, to the accompanying drawings, wherein: Fig. 1 is a circuit diagram of one example of circuitry to which the present invention may be applied; Fig. 2 is a cross-sectional view of a lateraltype PNP transistor, illustrating the problem of channel leakage inherent therein; Fig. 3 is a plan view of a conventional lateraltype PNP transistor with an identical cross-section to that of the transistor shown in Fig. 2; Fig. 4 is a plan view showing an embodiment of a semiconductor device according to the present invention; Fig, 5 is a plan view of a semiconductor device identical with that of Fig. 4, except for the use of wiring of a different size; Fig. 6 is a plan view of one example of an application based on the embodiment of Fig. 4; and Fig. 7 is a plan view of a different example of an application based on the embodiment of Fig. 4. Figure 1 is a circuit diagram of one example of conventional circuitry to which the present invention can be applied. More specifically, Fig. 1 shows a typical memory cell in a memory circuit. As is widely known, memory cells (MC) are arranged in a matrix at each of the intersecting points between pairs of bit lines BL and word lines. The memory cell in Fig. 1 is typical of those in static-type memory circuits. Each of said word lines consists of a positive (+) side word line W+ and negative (-) 'side word line W . The word line W is connected to a constant current source I, and passes a hold current i therethrough. In Fig. 1, particular attention should be paid to transistors Q1 and Q2 t each of which is a load element of the memory cell MC. Previously, the load element was usually a load resistor. However, to reduce the hold current i, the trend of late has been to use a load transistor as the load element. Each of these load transistors Q1 and Q2 corresponds to the above lateral-type PNP transistor, in which the above-mentioned problem of channel leakage occurs. Figure 2 is a cross-sectional view of a lateral-type PNP transistor which illustrates the problem of channel leakage inherent therein (Fig. 2 is similar to the view taken along line 2-2 in Fig. 3 mentioned hereinafter). In Fig. 2, the reference numeral 21 represents a semiconductor substrate composed of, for example, an epitaxial layer 22 and an N-type layer 23. The reference numeral 24 represents an isolation region for electrically separating adjacent circuit elements from each other. In the N-type layer 23, particularly where a base region B is formed therein, an emitter E and a collector C are formed, respectively, as P-type regions 25 and 26 by a diffusion process whereby both emitter E and collector C are arranged on the same surface layer. As seen from Fig. 2, an insulation layer 27 is formed on the surface of the semiconductor substrate 21; it should be recognized that, during the process for forming this insulation layer 27, negative charges are sometimes injected thereinto. If the negative charges thus injected are located above the base region B, since, as previously mentioned, the PNP transistors also behave as P-channel MOS transistors, the path between the emitter E and the collector C becomes conductive, resulting in channel leakage. In order to avoid such channel leakage, an electrode having a positive voltage is usually mounted above the base region B, such as to attract the negative charges to the upper side of insulation layer 27 (see dashed lines). In this case, it is economically preferable to fabricate this positive electrode integral with an emitter wiring 28. This is because, in conventional PNP transistors, the emitter always receives a positive voltage. The emitter wiring 28 is thus distributed such that it covers not only the emitter region E, but also the base region B, as shown in Fig. 2. Figure 3 is a plan view of a conventional lateral -type PNP transistor having a cross-section similar to that of the transistor shown in Fig. 2. It should be noted that Fig. 3 exemplifies an arrangement where two PNP transistors (corresponding to Q1 and Q2 of Fig. 1) face each other across an isolation region, sandwiched therebetween, such as to conform with the circuit arrangement of Fig. 1. In Fig. 3, reference numeral 31 represents a first lateral-type PNP transistor that faces a second lateral-type PNP transistor 32 across an isolation region 33 sandwiched therebetween. In PNP transistor 31, the reference characters 31c, 31b and 31e are respectively a collector region, a base region, and an emitter region thereof, while reference symbols C1 and E1 , enclosed by square lines, represent a collector contact and an emitter contact, respectively. Similarly, in PNP transistor 32, reference characters 32c, 32b and 32e respectively represent a collector region, a base region, and an emitter region, while reference symbols C2 and E2 , enclosed by square lines, represent a collector contact and an emitter contact, respectively. Reference numerals 35 and 36 represent collector wirings, while reference numerals 37 and 38 represent emitter wirings. In Fig. 3 and on, hatched lines and dotted areas are used, not for the usual purpose of representing regions in cross- section, but to help the viewer distinguish between the different components. Of these wirings, embodiments of the invention particularly concern portions 37Q and 38g , i.e., the above -mentioned positive electrodes for preventing channel leakage that extend from respective emitter wirings 37 and 38 to completely cover respective base regions 31b and 32b Self-alignment is generally well known as a means for achieving high IC packing densities. The arrangement illustrated in Fig. 2 was also created with the aid of self-alignment. Here, the diffusion areas for forming collector regions 31c and 32C and emitter regions 31e and 32 are self-aligned by isolation region 33. With e self-alignment, the pattern densities in the IC can be considerably increased. However, recent demand for higher pattern densities has grown very strong, as a result of which an attempt is often made to set the width W of the isolation region 33 smaller than usual. This inevitably results, however, in bringing emitter wirings 37 and 38 closer to each other, increasing the likelihood of an electric short therebetween. To avoid the possibility of such an electric short occurring, width D of the margin for each wiring must be minimized. One alternative is to not have electrodes 37 and 38 e e e completely cover base regions 31b and 31c t thus creating portions not covered the electrodes. However, this construction is likely to result again in channel leakage. It should be noted that, although the above problem was explained for an example in which two PNP transistors 31 and 32 were used, identical problems will similarly arise in cases where three or more PNP transistors with the isolation regions located therebetween are provided, or when a single PNP transistor is provided. An embodiment of the present invention can provide a semiconductor device in which the width W of the isolation region is reduced for higher pattern densities and channel leakage prevented from occurring therein by a very simple means. Figure 4 is a plan view showing an embodiment of a semiconductor device according to the present invention. In Fig. 4, members are represented by the same reference numerals or characters as the corresponding members in Fig. 3; these numerals and characters are used to represent like members in the later figures as well. The only difference between the embodiments shown in Figs. 3 and 4 lies in an isolation region 41. The width w of this isolation layer 41 is narrower than the width W of the isolation region in Fig. 3. The smaller width w is intended to-allow higher pattern densities. However, the smaller the width of the isolation region, the closer the emitter wirings 37 and 38 approach to each other. In the worst case, these emitter wirings may become electrically shorted on account of a variance in wiring size during manufacturing. To avoid such shorting, the width of each emitter wiring must be made as small as possible, such as to reduce the width D of margin of the wirings (see Fig. 3) to essentially zero. However, if the width D is reduced to essentially zero, portions not covered by the extended emitter wirings 37g and 38g may be formed above the base regions due to variances in wiring dimensions arising during manufacturing, causing the base regions to be left at least partially uncovered. If such uncovered portions exist, channel leakage will tend to occur. In Fig. 4, the width of isolation region 41 is widened somewhat at the portion facing each of the base regions by providing projections 42 and 43 of the isolation region 41, said projections extending from the body of isolation region 41 into respective base regions 31b and 32b. Thus, even if base regions 31b and 32 are manufactured with considerably small widths due to variances in the manufacturing process, they remain completely covered by respective extended emitter wirings 37g and 38g , which can prevent channel leakage from occurring. Figure 5 is a plan view of a semiconductor device identical with that of Fig. 4, except that it is manufactured with wiring of a different size. In the embodiment shown in Fig. 5, wirings 31e , 32e 37g t32e and 38g are manufactured at the minimum limit in a predetermined range in allowable design size, this limit corresponding to the worst possible case of wiring size variance during the manufacturing process. Here, the side of emitter wiring 31e provided with electrode 37g is located far from one side of the body of isolation region 41. In Fig. 5, this also applies to the sides of wirings 32e and 38g with respect to the other side of region 41. In this worst case, referring to PNP transistor 31 as a representative example, the base region 31b can still be completely covered by electrode 37g because one side of base region 31b is located apart from one side of the body of isolation region 41 facing thereto. The space thus formed between the facing sides of regions 31b and 41 are filled with said projections 42 having the same composition as region 41 such that the self-alignment method described above remains applicable to recessed base region 31b. Figure 6 is a plan view of one example of an application based on the embodiment of Fig. 4. In this example, three or more identical PNP transistors are fabricated according to the present invention. However, for the sake of simplicity, only three PNP transistors are shown in Fig. 6. The third PNP transistor is represented as a whole by reference numeral 62. Reference numerals 53 and 63 represent the projections constituting a feature of the present invention. Members C3 , B3 and E3 are identical to members C1 , C2 , B1 , B2 , and E1 , E2. The members represented by reference characters 62C , 68g , 62e x and 66 are identical respectively to members 32 , 38g , 32e t and 36 shown in Figs. 4 and 5. Figure 7 is a plan view of another example of an application based on the embodiment of Fig. 4. In this example, the PNP transistor 31 does not face another PNP transistor, but rather conductor lead 71, with isolation region 41 sandwiched therebetween. In the embodiment shown in Fig. 7, it is also true that the width D (Fig. 3) of margin in the wiring should be reduced to substantially zero. This results in the formation of an uncovered portion above the base region 3 4 in the absence of projection 42. As explained above, embodiments of the present invention, can provide a simple means for attaining high IC packaging densities while protecting against channel leakage.

Claims: CLAIMS 1. A semiconductor device comprising at least one lateral-type PNP transistor having a P-type collector region, a P-type emitter region, an N-type base region, and an emitter wiring partially extended such as to entirely cover said base region, said collector and emitter regions being formed such as to directly contact said isolation region adjacent thereto, but said base region being formed such as to contact said isolation region via a projection extending partially therefrom, said partially extended emitter wiring being disposed above said projection. 2. A semiconductor device as set forth in claim 1, wherein said projection and said isolation region are integral with each other. 3. A semiconductor device as set forth in claiml or 2, wherein self-alignment is established between said isolation region and said emitter and collector regions and also between said base region and said projection. 4. A semiconductor device as set forth in claim 1, 2 or 3, wherein said projection is formed with a predetermined width between the body of said isolation region and said base region, which width is about equal to the value corresponding to the minimum limit in a predetermined range in allowable design size for said partially extended emitter wiring. 5. A semiconductor device comprising a semiconductor layer in which is formed a lateral-type transistor, having at a main surface of the semiconductor layer a collector region and a base region and an emitter region, and an isolation region for insulating the transistor from other portions of the device; the said collector region, base region and emitter region having respective peripheral boundary portions which extend adjacent to respective successive portions of one lateral boundary of the isolation region; and there being an electrical connection layer which is connected to and overlies one of the said collector and emitter regions and extends additionally over the said base region so as to overlie that region substantially completely; characterised in that the said peripheral boundary portion of the base region is displaced, in relation to the said peripheral boundary portions of the collector and emitter regions, in the direction away from the said isolation region.

Inventors: ISOGAI, HIDEAKI, ONO, CHIKAI
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: H01L29
IPC codes: H01L29, H01L27, G11C11, H01L21