SELECTIVELY OPERABLE ELECTRICAL CONNECTION CIRCUIT

Abstract: A circuit for selectively connecting an input line to an output line is suitable for selectively passing a relatively high voltage, such as a write or erase voltage for a non-volatile memory, without incurring threshold losses. In response to a +5V ENABLE signal a first capacitive node (NODE 1) controls a transistor (46) to pass a charging voltage from an input line (31) to charge a second capacitive node (NODE 2) which is coupled to the first capacitive node (NODE 1) by a transistor (51) effective as a diode. Out-of-phase clock pulses (0 &cir& /1, 0 &cir& /2), coupled to respective capacitors (34, 33) then provide a charge pumping effect to raise the potential on the first capacitive node (NODE 1) to a level such that a transistor (41) coupled thereto passes the voltage on the input line (31) to the output line (HVOUT) without threshold losses. A negative voltage blocking circuit (27) including a depletion mode transistor (49) which is controllable to enhancement mode operation and a further charge pumping circuit, blocks undesired negative input voltages. When the circuit is disabled, the clock pulses (0 &cir& /1, 0 &cir& /2) are decoupled by decoupling circuits (24, 26).

Description: SELECTIVELY OPERABLE ELECTRICAL CONNECTION CIRCUIT Technical Field This invention relates to electrical circuits of the kind for selectively connecting an input line to an output line, including coupling means adapted to couple an input voltage on said input line to said out¬ put line in response to a first voltage on a first capacitive node, when said first voltage exceeds said input voltage. An electrical circuit of the kind specified has a particular application for coupling write and erase voltages to a non-volatile memory array when inte¬ grated on a common chip with the array. Background Art A circuit of the kind specified is known from published British patent application No. 2,094,086 which discloses a non-volatile memory system. Thus, from Fig. 4 of said British patent application, there is known a boosted voltage distributing circuit which is selectively operable to supply a boosted voltage to an associated row line of the non-volatile memory array when the row line is selected. In the known circuit, an oscillator controlled pumping means raises the volt¬ age on a node coupled to the gate of a transistor having its source/drain path connected between the boosted voltage source and the row line associated with the cir¬ cuit. The known circuit has been found in practice to have the disadvantage of providing insufficient margin as to the output voltage when leakage currents, dis¬ tributed capacitance, supply voltage extremes, fabrica¬ tion tolerances and temperature extremes are taken into account concurrently. Disclosure of the Invention It is an object of the present invention to provide a circuit of the kind specified wherein the aforementioned disadvantage is alleviated. Therefore, according to the present invention, there is provided a circuit of the kind specified, characterized by charge transfer means adapted to trans¬ fer charge from said input line to a second capacitive node, when said first voltage exceeds a second voltage on said second capacitive node; and charge pump means adapted to cyclically transfer charge unidirectionally from said second capacitive node to said first capaci¬ tive node. In accordance with the field of application mentioned hereinabove, a circuit according to the inven¬ tion is particularly suited for applying write and erase voltages to a non-volatile memory array when inte¬ grated on a common chip with the array. Since such write and erase voltages are generally of a relatively high magnitude in comparison with the relatively low operating power supply voltages utilized, the circuit described in the preferred embodiment may conveniently be referred to as a high voltage pass circuit. Thus, a preferred embodiment of the invention, utilized in con¬ junction with a non-volatile memory array, provides an integrated circuit suitably configured to pass relatively high voltages from an input line to an output line, or selectively block high voltages presented to either the input or output line, in response to a single low voltage enable signal. In the particular arrangement of field effect transistors (FETs) utilized, the circuit draws a limited, transient current from the power supply pro¬ viding the high voltage, while passing the high voltage from input to output with no threshold voltage losses. In one embodiment, the circuit utilizes relatively con¬ ventional n-channel FETs, operates from a nominal 5 volt power supply, and is suitably arranged to pass in excess of 20 volts in the context of a write and erase control for a non-volatile memory array. In the composite embodiment of the preferred high voltage pass circuit, a pump circuit and a high voltage drive circuit are supplemented with a negative voltage protection circuit, a multiplicity of decoupling circuits, and a pair of negative voltage blocking cir¬ cuits to perform the described operations. The featured pump circuit is synchronously driven by a two-phase clock, Charge is drawn from the high voltage power supply, through a gating FET, to increase the voltage on a first node having distributed capacitance. Thereafter, the pumping action of the two-phase clock increases the voltage on the first node and transfers charge unidirec- tionally through a natural threshold FET to a second capacitive node. The second node provides enabling voltage to both the high voltage drive circuit and the aforementioned gating FET. In this way, the circuit takes the form of a closed loop arrangement, in which the movement of charge is initiated by the enable signal, and sustained and elevated thereafter by the pumping action of the two-phase clock. The path by which the enable line initiates pumping also serves to disable the high voltage pass circuit when the enable signal is at a low level . As was noted above, the composite high voltage pass circuit includes various forms of negative voltage protection. The featured negative voltage blocking cir¬ cuit at the high voltage input line of the high voltage pass circuit incorporates a series connected FET which is appropriately disabled by a depletion FET when the voltage on the high voltage input line is negative. Threshold voltage losses through the negative voltage blocking circuit during the pass operation are avoided by elevating the voltage on the gate electrode of the series connected FET. The higher voltage is generated by pumping a capacitively loaded node with the clock signal and regulating the charge flow with body effect in the depletion FET. The second negative voltage blocking circuit, at the output side of the high voltage pass circuit, is comprised of a pair of FETs which short the gate and drain electrodes of the FET in the high voltage drive circuit. The FET in the high voltage drive circuit controls the actual passage of high voltage from the input line to the output line. During negative voltage on the output line of the high voltage pass circuit, the path to the enable line is disconnected by the negative voltage protection circuit. In one " form, it is comprised of a series FET which is selectively biased with a negative voltage on the gate electrode. As embodied, the high voltage pass circuit also includes a group of decoupling circuits. These circuits selectively decouple the clock inputs of the high voltage pass circuit from the two-phase clock to remove the capacitive loads of the high voltage pass circuit when it is disabled. Upon considering the exem- plary non-volatile memory array application, it will be appreciated that the multiplicity of high voltage pass circuits would otherwise impose a significant loading on the two-phase clock lines, irrespective of the number of high voltage pass circuits actually operating. An embodying decoupling circuit includes a gating FET, connected in series with the clock signal line and gated by the enable line. The enable line is itself connected through a forward biased FET. The forward biased FET bootstraps the gating FET gate voltage sufficiently to ensure that the clock signal does not sustain a thres¬ hold voltage drop in progressing to the pump or blocking circuits. Brief Description of the Drawings Embodiments of the invention will now be described by way of example with reference to the accom¬ panying drawings, in which: Fig. 1 is a schematic block diagram of a write and erase control for a nonvolatile memory array. Fig. 2 is a schematic diagram of a high volt¬ age pass circuit embodying the features of the present invention. Fig. 3 is a schematic block diagram depicting the functional sections forming the circuit in Fig . 2. Fig. 4 is a schematic diagram representing a simplified functional equivalent of the pump and high voltage drive circuits from Figs. 2 and 3. Fig. 5 presents exemplary waveforms for the voltage signals on various nodes and lines of the high voltage pass circuit in Fig. 2. Best Mode for Carrying Out the Invention To understand the benefits of the present high voltage pass circuit, and to gain some appreciation for its range of applications, the ensuing description will begin with a brief presentation of the context within which the present high voltage pass circuit can be utilized. In this respect, attention is directed to write and erase control system 1 for a nonvolatile memory array as generally shown in Fig. 1 of the draw¬ ings. The nominal voltages suitable to perform the write and erase operations appear in Table I. TABLE I Page Memory Memory Substrate Erase Erase Write Operation Gate Lines Epi (HVW) (HVS) Enable Enable Enable Block erase 0 volts (all +20 volts +22 volts +5 volts 0 volts 0 volts pages) Page erase +20 volts +20 volts +22 volts +5 volts +5 volts 0 volts (pages not to be erased) 0 volts (page to be erased) Write +20 volts -2.5 volts +5 less V 0 volts 0 volts +5 volts (page to be written) 0 volts (pages not The illustrated control system is utilized to block erase, page erase (groups of 16 bytes), or write a nonvolatile (NV) memory array configured with silicon- nitride-oxide-semiconductor (SNOS) type devices. In the preferred configuration, the array is fabricated to be part of a single integrated circuit chip which includes substantially all the circuitry necessary to erase, write and read data in the memory array. It should be recognized that the description of the system in Fig. 1 is relatively abbreviated, in that SNOS memory arrays and conventionally associated high voltage supply pump, decode, oscillator, and distributor circuitry is rela¬ tively common knowledge, whereas the high voltage pass circuit of the present form is not. It is noteworthy with reference to Fig. 1, that configurations of the high voltage pass circuit appear repeatedly in the control system, and as such can contribute significantly to the area consumed if the design is not efficiently implemented at the device level. A brief description of the operations performed by exemplified memory array control system 1 follows . Referring to Fig. 1, oscillator enable circuit 2 generates a signal to initiate the operation of two- phase oscillator clock circuit 3 when a signal appears on write enable line 4 or erase enable line 6. The output signals from two-phase oscillator circuit 3, clock signals <b and •£-, are supplied to high voltage supply pump circuit 7, erase distributor 17, and high voltage pass circuits 8, 9 and 15. Clock signals •£ and -i- are also coupled to the multiplicity of high voltage pass circuits corresponding to the memory gate pages, including high voltage pass circuits 11-14, on two-line buss 16. The relatively high level of the DC voltage generated in high voltage supply pump circuit 7 is connected to the HVIN terminals of high voltage pass circuits 8 and 9. The output of high voltage pass OMPI .. ■ IPO circuit 8, from the HVOUT terminal on line VW, is dis¬ tributed to the HVIN terminals of high voltage pass circuits 11-14. Output line 18 from high voltage pass circuit 9 is coupled through erase distributor circuit 17 to the pair of lines HVS and HVW, which are respec¬ tively the electrical connections of the chip substrate and of the memory epitaxial layer. The third output line from erase distributor 17 is connected to the HVIN terminal of high voltage pass circuit 15. Erase dis- tributor 17 merely replicates the ' HVOUT signal as it appears on line 18, while decoupling the output lines from each other. The erasure of selected pages within the NV memory array is performed by selectively transmitting the erase voltage on line VW to designated memory gate electrodes of the NV SNOS devices. In the present embodiment, the devices have been organized into groups by pages numbering #1 to #N. The addresses of the pages to be erased, or written, are entered as a binary bit code into decoder 19, which selectively enables the high voltage pass circuits corresponding to the address code. The enable signals are transmitted on enable buss 21. As is no doubt evident from the embodiment, the division of the NV memory array into N pages inherently requires N individual high voltage pass circuits. An operational description of memory array control system 1 follows. The operations defined by Table I can now be related to the corresponding functional blocks in Fig. 1. During the block erase operation, all memory gate lines connected to the HVOUT terminals of high voltage pass circuits 11-14, are held at 0 volts by -the appro¬ priate page addresses, while lines HVW and HVS are biased to +20 and +22 volts, respectively, using high voltage pass circuit 9. The elevation of the voltage from the +20 volts on line 18 to the +22 volts on line HVS is performed by a simple clocked pump circuit within erase distributor 17. The two volt margin ensures that OMPI parasitic bipolar transistors elsewhere on the chip remain disabled. During this period, a +5 volt signal is provided to erase enable line 6. The page erase operation is similar, except that the page address causes an enabling of selectively designated high voltage pass circuits from the group beginning with 11 and extending through 14. In this case, the +20 volts on line 18 from high voltage pass circuit 9 is coupled to line VW through high voltage pass circuit 15. Thereafter, the +20 volts on line VW is selectively distributed to the pages not to be erased according to the signals on enable buss 21. During this operation, both erase enable line 6 and page erase enable line 20 are at +5 volts. The write operation performed by memory array control system 1 is commenced with a +5 volt signal on write enable line 4. The write enable signal actuates high voltage pass circuit 8 to couple +20 volts from the HVOUT terminal onto line VW. Thereafter, the +20 volts is selectively connected to the memory gate line, #1 to #N, according to the page addresses on buss 21. During the write operation, lines HVS and HVW are biased by separate means to approximately +4 volts and -2.5 volts, respectively. While writing, high voltage pass circuit 9 is disabled and high voltage pass circuit 15 decouples the -2.5 volts on line HVW from line VW. Given the frequency with which the high volt¬ age pass circuit appears in the memory control system, together with the variety of signals it must be capable of handling, one begins to appreciate the capability and contribution of such a circuit. A complete configura¬ tion of the high voltage pass circuit is depicted in Fig. 2. The interconnection of the functional blocks which make up Fig. 2 are shown in Fig. 3 to aid in the • understanding of the interrelationships. One skilled in the art will undoubtedly recognize the efficiency with which the complex functions defined by the blocks OMPI in Fig. 3 are physically implemented by active semi¬ conductor devices as shown in Fig. 2. Nevertheless, it should be understood that the various configurations of the high voltage pass circuit implemented in control system 1 (Fig. 1) are composed according to their par¬ ticular circuit requirements, whereby only high voltage pass circuit 15 includes all the functional sections actually depicted in Figs. 2 and 3. By virtue of its circuit location it is subject to all the variabilities of voltage contemplated for a high voltage pass circuit. Therefore, the description which follows will utilize this arrangement over alternative, simpler configura¬ tions. The circuit in Figs. 2 and 3 will be described hereinafter in two separate stages. The first stage will involve a composite description considering the functional blocks and their interaction. The second stage will contain a description of the operations performed by the individual devices within the func- tional blocks. With regard to Fig. 3, it should be understood that the central elements to the present invention are represented by the features contained in the pump cir¬ cuit section, 22, the high voltage drive circuit sec- tion, 23, and the negative voltage blocking circuit section, 27. However, the fully complemented embodiment also includes a negative voltage blocking circuit, 28, a pair of decoupling circuits, 24 and 26, and a negative voltage protection circuit incorporated within pump circuit 22. Decoupling circuits 24 and 26 contribute by reducing the load driven by clock lines 4> and ? . Phantom block 29 in Fig. 3 depicts the presence of a decoupling circuit which, by virtue of the present configuration, was not required in the embodiment of Fig. 2. Negative voltage blocking circuits 27 and 28 prevent the passage of negative voltages between ter¬ minals HVIN and HVOUT. Negative voltage protection circuit 30 (Fig. 3) represents a functional arrangement of pump circuit 22 configured to prevent a negative voltage on terminal HVOUT from propagating through to the enable line. Though not essential to the basic invention, the latter-described supplemental circuits clearly expand the versatility of the high voltage pass circuit. Continuing at the functional block level, the description will now focus on the operation of the high voltage pass circuit in performing the functions neces- sary to write and erase a nonvolatile memory array, though the invention is not limited to that narrow scope of applications. The fundamental feature of the high voltage pass circuit 15 is the ability to pass a high voltage between terminals HVIN and HVOUT without suf- fering threshold voltage losses. To accomplish this, pump circuit 22 receives the high voltage from line 31 and uses the two-phase clock signals ό, and c>- ' to provide a further elevated voltage on line 32. Thereby, the elevated voltage compensates for threshold voltage losses otherwise introduced in sending the high voltage on line 31 through high voltage drive circuit 23. Pump circuit 22 is enabled by a +5 volt signal on the enable line. Control input line VP is maintained at +5 volts unless a negative voltage is anticipated on ter¬ minal HVOUT, in which case it is biased with -5 volts. The -5 volt signal on line VP coincides with margining type testing. Decoupling circuits 24, 26, and poten¬ tially 29 are present to substantially eliminate the capacitive load on clock lines c and d * .-, from high voltage pass circuits which are disabled. Were it not for the multiplicity of high voltage pass circuits utilized to erase and write the memory by selected page, the clock loading would likely remain within acceptable limits. Note, the passage of clock signals through the decoupling circuits occurs only when a +5 volt signal appears on the enable line. OMPI Negative voltage blocking circuit 27 inhibits the passage of any negative voltage on terminal HVIN onto line 31. When high voltage pass circuit 15 is enabled, no voltage loss is introduced between HVIN and 31 by virtue of a pump arrangement within negative voltage blocking circuit 27, which pump is driven by decoupled clock signal <j> ' . The remaining negative voltage blocking cir¬ cuit, 28, ensures that negative voltage on terminal HVOUT does not pass back through the FET in high voltage drive circuit 23, by imposing a substantial short between line 32 and terminal HVOUT when HVOUT is subject to negative voltages. At that time, line VMG is provided with a +5 volt bias signal. In general, a negative voltage appears on HVOUT only during margining type testing of the NV device memory window. The procedure is routinely performed by those skilled in the fabri¬ cation of SNOS type NV memory devices. With the functional level relationships de- fined, the ensuing description will focus on the organi¬ zation and characteristic contributions of the various active and passive devices within the circuit embodied in Fig. 2. In considering the present embodiment, it should be noted that the design shown in Fig. 2 is powered from a +5 volt supply, the V voltage. The devices have a field plate zener capability of approxi¬ mately 25 volts. The width/length ratios of the devices are shown adjacent to each in Fig. 2. In the present embodiment, capacitors 33, 34 and 36 are conventional enhancement capacitors, often characterized as enhance¬ ment FETs with commonly connected source/drain elec¬ trodes. FETs 37, 38, 39, 41, 42, 43, 44, 46, 47 and 48 are relatively conventional enhancement type devices with a threshold voltage (V τ ) of approximately 0.8 volts. FET 49 in negative voltage blocking circuit 27 is a light depletion type device, having a threshold voltage approximately -1.5 volts. FET 51 has a threshold OMPI voltage of approximately 0 volts, a configuration gen¬ erally known as a natural FET. Capacitors C . and C „ represent the effective distributed node capacitance on respective nodes #1 and #2. As a general design rule, capacitors 33 and 34 should be significantly greater (by a factor in excess of 10:1) than c Nl. and C-N . -.-2. to obtain efficient operation from pump circuit 22. Other rela¬ tionships of the individual devices within the circuits will become evident after each circuit is considered individually. The signals which are coupled to high voltage pass circuit 15 in Fig. 2 have been partially described previously. However, it is worth noting that the clock signals on lines . and φ_ are generally square waves, differing by approximately 180° in phase, ranging in voltage between 0 volts and +5 volts, and having a nominal frequency of 5-20 MHz. Operation of each high voltage pass circuit is initiated with a +5 volt signal on the enable line and terminated with a 0 volt signal on the enable line. Though line VP is, as described earlier, normally +5 volts, it is capable of being biased at other voltages during the margining tests on the memory window of SNOS type NV devices in the memory array. This use is, however, of secondary consideration and well beyond the scope of the present invention. The focus of attention will now be directed to pump circuit 22 and high voltage drive circuit 23, as a combination. A functional equivalent for the combina¬ tion is depicted in Fig. 4. The presence of a prime symbol adjacent a reference symbol indicates functional correspondence between elements in Figs. 2 and 4. The structure of the operating equivalent circuit shown in Fig. 4 presents an arrangement of capacitor 33, node #2, diode 51', resistor 51' ', node #1 and capacitor 34 between two-phase clock signals <b and cjs ' . Nodes #1 and #2 are shown to be capacitively coupled to ground potential through respective capaci- OMPI tors C and C „. Node #1 is further connected to the gate electrode of FET 41 in high voltage drive circuit 23 and to the enable line through diode 44' . Node #2 is separated from HVIN' by the path through FET 46. The operation of pump circuit 22, in terms of the equivalent circuit in Fig. 4, begins with a positive signal on the enable line. This signal turns on FET 46, which then supplies charge from HVIN' to node #2, and in succession to node #1. The clock signals are thereafter utilized to elevate the potential of node #2, and cause a further transfer of charge through diode 51' and resistor 51' ' to node #1. In closed loop fashion, the elevation of " the voltage on node #1 biases FET 46 to further charge node #2 with voltage from HVIN' . The clocking and charge transfer is repeated until node #2 reaches the amplitude of the voltage on HVIN* and node #1 is at least 5 volts greater. Thereby, the gate electrode of drive circuit FET 41 is raised sufficiently above the voltage on HVIN' to ensure that the voltage at HVOUT does not suffer a threshold voltage drop in pas¬ sing through FET 41. The sequence of events characterizing the operation of pump circuit 22 and high voltage drive circuit 23 are best understood by referring to the waveforms of the various signals as shown in Fig. 5. Considering Figs. 4 and 5 together, it is apparent that pr-ior to the 5 volt enable signal, node #1 is held to 0 volts. This is accomplished by FET 44 (Fig. 2). Fol¬ lowing the rise of the enable signal to +5 volts at time , node capacitance C-,, is charged to elevate node #1 to approximately 5 volts. By time T_, enhancement FETs 41 and 46 have become conductive, connecting the HVIN' terminal to both HVOUT and node #2. Though the volt¬ age on node #1 has generally stabilized at time T„, the voltage on node #2 continues to increase until time T_ by virtue of the charge flowing between HVIN' and capa¬ citor C _ in response to the transconductance of FET 46. OMPI During the period of time immediately after T , the voltages on nodes #1 and #2 differ by the threshold of FET 46. The pumping operation is cyclically repeated until the voltage on node #2 reaches that on terminal HVIN' . The contribution of the signal from the enable line through diode 44' should not be overlooked. It is used to precharge node #1, which precharge is necessary to first enable FET 46 and thereby initiate the transfer of charge from HVIN' to node #2. Without the enabling voltage, FET 46 would normally remain nonconductive by virtue of it being an enhancement type device. It should, however, be recognized that functional diode 44' reverts to its FET structure when the enable line is at 0 volts, and draws node #1 to the same potential. To understand the contribution of the two- phase clock signals after the enable transients pre¬ ceding time » have subsided, one should consider the equivalent circuit in Fig. 4 at times T and T g . For instance, at times T clock signals φ, and Φ 2 ' initiate their transition between their 0 and +5 volt levels. During the time interval between T. and T g , node #2 is raised in potential by the positive going transition of the φ signal through a charge sharing between rela- tively large capacitor 33 and relatively small capaci¬ tor C . To some extent, charge is also shared between capacitor 34 and capacitor C ., but to a lesser degree by virtue of the-intervening resistance 51 * ' . At the time that clock signal φ ' increases, signal φ, tran- sitions downward to 0 volts. With the downward tran¬ sition, node #1 is pulled negatively by the.charge sharing between relatively large capacitor 34 and rela¬ tively small capacitor C . This ' action draws even further charge from node #2 to node #1, by virtue of the greater voltage difference. At some point in time before T., the voltages on nodes #1 and 2 stabilize and 6 differ in magnitude by the threshold of FET 51 (Fig. 2). The time interval between T fi and T 7 encompas¬ ses the opposite transition of signals b. and -' . The rise in the signal on line χ results in a charge shar¬ ing between capacitors 34 and C . to elevate node #1 by approximately 3 volts. In contrast, node #2 is drawn down by the drop in the voltage on line φ ' . The lesser amount of the drop on node #2, recognizing the blocking action of diode 51' , is attributable to the charge supplemented through FET 46 from line HVIN' . Node #2 continues to receive charge from HVIN" through FET 46 until time T , at which point the voltage on node #1 is one threshold greater than on node #2. The cyclic operation is repeated with time Ty at the 5 MHz clock rate, until HVOUT equals HVIN' . In terms of pump efficiency based on charge sharing it is preferred that capacitor 34 be signifi¬ cantly greater in capacitance than capacitor C _ . Generally, a factor of 3 or greater is suitable; how¬ ever, a factor in excess of 10 is preferred. A similar preferential relationship is sought between capacitor 33 and capacitor C . Pump operation efficiency also dictates that capacitors 33 and 34 be substantially equal in value. Consideration of the equivalent circuit in Fig. 4 and the waveforms in Fig. 5 also show that FET 51 (Fig. 2), represented by diode 51' and resistor 51'', should be a device having a threshold voltage of approx¬ imately 0 volts and minimum effective resistance. Though these considerations are not crucial to the basic operation of the pump circuit, they do represent a preferable arrangement for practicing the invention. With an understanding of the structural and operational features which characterize pump circuit 22 and high voltage drive circuit 23, attention is now directed back to Fig. 2 for consideration of another aspect of the present invention. The focus of atten¬ tion will now be on negative voltage blocking circuit 27, used to block negative voltages appearing on OMPI v;_.o line HVIN, while passing positive voltages from line HVIN to line 31 with no voltage drop. The blocking action is performed by creating an electrical connection between the gate and source electrodes of FET 39 through depletion mode FET 49 whenever line HVIN is negative with respect to line 31. To understand the contributions obtained from FET 49, consider the device in the context of the requirements necessary for the appropriate oper- ation of negative voltage blocking circuit 27. To pass positive voltage, gate electrode 50 of FET 39, connected to node #3 , must be pumped to a voltage at least one threshold above that on HVIN. In the embodiment, the pumping is accomplished by utilizing the φ clock sig- nal, conveyed to node #3 through FET 38 and capacitor 36. If FET 49 were a conventional depletion mode device, the pumping action through capacitor 36 would be ineffective by virtue of the conductive path through FET 49 to line HVIN. Nevertheless, FET 49 must be a deple- tion mode device to provide the basic negative voltage blocking function attributed to the circuit. The ap¬ parent dichotomy of operational objectives required of FET 49 is overcome by using a very lightly doped deple¬ tion FET. In that configuration, the depletion mode of operation is retained for negative voltage blocking. However, when HVIN is at a high positive voltage, the body effect on FET 49 shifts the threshold from a slightly depleted level to a slightly enhanced level. With FET 49 in an enhancement mode, node #3 can be raised above HVIN by φ. signal pumping. In this way, the uniquely defined characteristics of FET -49 provide negative voltage blocking circuit 27 with the capability both to block negative voltages and to selectively pass positive voltages without suffering threshold losses. The presence of FET 39 in the path between HVIN and line 31 also provides a modest increment of field plate zener protection for FET 41, in the case where line 32 is at or near ground potential by virtue of a 0 volt level on the enable line while HVIN is at a maximum voltage. In that situation, the voltage on node #3 is at HVIN and the combination of threshold and body effect cause a drop of approximately 3 volts across FET 39. The added margin ensures that FET 41 does not field plate zener even with worst case voltages on HVIN. Attention is now directed to the structure and contributions of negative voltage blocking circuit 28, as it appears in the embodiment of Fig. 2. In the con- text of the embodiment, the purpose of negative voltage blocking circuit 28 is to block the negative voltage on line HVOUT from being coupled through enhancement mode FET 41 to line 31. To prevent FET 41 from conducting when HVOUT is a negative voltage, line VMG is changed from its normal 0 volt level to +5 volts. With that condition, the gate electrode of FET 41 is shorted directly to its source electrode. Though the +5 signal on VMG prevents the passage of negative voltage, not exceeding -5 volts, to <line 31, it does create a path for the negative voltage on line HVOUT, through FETs 48 and 47, to reach node #1. A negative voltage on node #1 does not itself create a problem. However, if FET 44 is conductive the negative voltage will be connected to the enable line. To avoid this, line VP is biased with -5 volts whenever negative voltage appears on HVOUT. In Fig. 3 this operation is functionally represented by negative voltage protection circuit 30. The various states for the voltages on both line VP and VMG are summarized in Table II to indicate when they occur and their effect in the circuit. Since the last condition occurs only during voltage margining tests on the NV devices in the chip, it provides a predictable means for controlling the voltage supplied to lines VP and VMG. y-^r TABLE II ENABLE LINE EFFECT ON VP VOLTAGE VMG VOLTAGE CONDITIONS NODE #1 +5 volts 0 volts Enable line at Ov, Holds node #1 to Ov. and disables pump circuit 22 +5 volts 0 volts Enable line at +5 Allows node volts and node #1 #1 to rise less than +5v. to positive voltage and enables pump circuit 22 +5 volts 0 volts Enable line at +5 Acts as volts and node #1 diode 44' greater than +5v. (Fig. 4) to block node #1 voltage from the en¬ able line -5 volts +5 volts Enable line at Blocks nega¬ 0 volts tive voltage at node #1 from the en¬ able line FET 47 in negative voltage blocking circuit 28 is present to protect FET 48 from field plate zener breakdowns. FET 47 is required because node #1 can be pumped to a level of approximately 27 volts, which magnitude exceeds the nominal breakdown of FET 48. Since such field plate zener protection circuits are generally known within the art, further description of the arrangement is unwarranted. The remaining sections of the high voltage pass circuit in Fig. 2 include decoupling circuits 24 and 26. Reference to Fig. 3 indicates that a corres¬ ponding decoupling circuit, 29, has been deleted from the present embodiment because of adequate, preexisting decoupling. Referring back to Fig. 2, circuit 24 serves to decouple negative voltage blocking circuit 27 from loading clock signal φ_ when high voltage pass circuit 15 is not operating; that is, when the signal on the enable line is at 0 volts. Decoupling circuit 26 per¬ forms the same operation with respect to clock signal Φ_ for the remaining clocked input to pump circuit 22. As noted earlier, the need for circuits such as 24, 26 and 29 are related to the number of high voltage pass circuits and the drive capability of the two-phase clocking oscillator 3 (Fig. 1). The operations of decoupling circuit 24 and 26 are substantially identical . When the enable line voltage is at 0 volts, FETs 38 and 43 disconnect lines Φ ' and Φ 2 ' from φ. ^ and Φ 2 , respectively. A change in the enable voltage from 0 to +5 volts connects 5 volts, less the threshold drops associated with FETs 37 and 42, to the gate electrodes of FETs 38 and 43. However, with the cyclic transition of clock signals on lines Φ 1 and <b the gate electrodes of FETs 38 and 43 are boot¬ strapped to a voltage of approximately 5 volts greater than the DC level conducted from the enable line. In this way, the signals on lines φ χ ' and φ 2 ' are not subjected to threshold losses in passing through FETs 38 and 43. The absence of a decoupling circuit in the line connecting φ into pump circuit 22 is attributable to the substantial lack of coupling provided through enhancement capacitor 34 when the enable line and node #1 are at approximately 0 volts. Namely, when gate electrode 52 of capacitor 34 is at 0 volts, the channel which creates enhancement capacitor 34 is absent. The same zero gate voltage situation does not exist for enhancement capacitors 33 and 36. In the case OMPI of enhancement capacitor 36, the presence of a high voltage on line HVIN is coupled to node #3 and gate electrode 53. In the case of enhancement capacitor 33, gate electrode 54 is connected to node #2. Since elec- trode 54 is isolated by FET 51 from the ground potential at node #1, it may under some conditions float with sufficient potential to form significant capacitance in enhancement capacitor 33. To avoid loading the clock lines with high voltage pass circuits which are not enabled, the present embodiment incorporates decoupling circuits, such as 24 and 26, where necessary. The preferred embodiment illustrated in Figs. 2 and 3 utilizes a two-phase clock signal to pump the high voltage pass circuit. Though a standard relative phase of 180° between the signal on line φ and that on line φ« is contemplated, a nominally different phase angle will sustain operation, but at a reduced level of pump efficiency. In this respect, it should also be noted that the general high voltage pass circuit may, under limited conditions, be pumped by a single phase clock signal. The implications of using a single clock signal will be considered briefly hereinafter. The preferred embodiment of the high voltage pass circuit is capable of raising the voltage on node #1 to approximately 27 volts when HVIN is at 20 volts. The 7 volt difference between the voltage on line 32 (Fig. 2), connected to node #1, and the voltage on line 31, the HVIN voltage, ensures that the full 20 volts appears on line HVOUT. However, if lesser voltages are acceptable at line HVOUT, for example 15 volts, then a single phase clock signal embodiment of pump circuit 22 is suitable. The nominal output voltage for a single phase pump, as measured on line 32, is in the range of 22 volts. The structure of a high voltage pass circuit with a single phase clock is similar to the two-phase embodiment shown in Fig. 2. In particular, capacitor 34 - o OuMPrI , wiFO and line φ are eliminated. With this arrangment, node #1 is not pumped directly, but rather, is always charged from node #2 through natural FET 51. OMPI

Claims: CLAIMS : 1. A circuit (15) for selectively connecting an input line (31) to an output line (HVOUT), including coupling means adapted to couple an input voltage on said input line (31) to said output line (HVOUT) in 5 response to a first voltage on a first capacitive node (NODE 1), when said first voltage exceeds said input voltage, characterized by charge transfer means adapted to transfer charge from said input line (31) to a second capacitive node (NODE 2), when said first voltage exceeds 10 a second voltage on said second capacitive node (NODE 2); and charge pump means adapted to cyclically transfer charge unidirectionally from said second capacitive node (NODE 2) to said first capacitive node (NODE 1). 2. A circuit according to claim 1, charac¬ terized by enabling means (4, 6, 20, 21) adapted to pre¬ charge said first capacitive node (NODE 1) to enable said circuit (15), and to discharge said first capacitive 5 node (NODE 2) to disable said circuit (15). 3. A circuit according to claim 2, charac¬ terized in that said charge pump means includes a first capacitive device (33) connected by a first terminal to said second capacitive node (NODE 2); clock signal means 5 including a first source of clock signals (0_) coupled to a second terminal of said first capacitive device (33); and diode means (51) connected to pass charge from said second capacitive node (NODE 2) to said first capacitive node (NODE 1) . 4. A circuit according to claim 3, character¬ ized by a second capacitive device (34) connected by a first terminal to said first capacitive node (NODE 1); and in that said clock signal means includes a second > source of clock signals (0.) coupled to a second terminal 4. ( concluded) of said second capacitive device (34) and having a clock signal phase opposite that generated by said first source of clock signals (0_). 5. A circuit according to claim 4, charac¬ terized in that said coupling means includes a field effect transistor (41), having its source/drain elec¬ trodes individually connected to said input line (31) and said output line (HVOUT) and its gate electrode con¬ nected to said first node (NODE 1); in that said charge transfer means includes an enhancement field effect transistor (46), having its source/drain electrodes individually connected to said input line (31) and said second capacitive node (NODE 2) and its gate electrode connected to said first node (NODE 1); and in that said diode means includes a natural field effect transistor (51) having its source electrode connected to said first capacitive node (NODE 1) and its gate and drain elec- trodes connected to said second capacitive node (NODE 2). 6. A circuit according to claim 3, charac¬ terized in that said first capacitive device (33) has a capacitance at least three times greater than the capacitance of either said first capacitive node (NODE 1) or said second capacitive node (NODE 2) . 7. A circuit according to claim 4, charac¬ terized in that said first and second capacitive devices (33, 34) are substantially identical in capacitance and each has a capacitance at least three times greater than the capacitance on either said first capacitive node (NODE 1) or said second capacitive node (NODE 2) . 8. A circuit according to claim 3, charac¬ terized by negative voltage blocking means (27) coupled to said input line (31), said negative voltage blocking 8. ( concluded ) means (27) including: an enhancement field effect trans- istor (39) having its source/drain electrode path con¬ nected, to said input line (31); capacitive means (36), connected by a first terminal to the gate electrode of said enhancement field effect transistor (39), said clock signal means being coupled to a second terminal of said capacitive means (36); and a depletion field effect transistor (49) having one source/drain electrode con¬ nected to said gate electrode of said' enhancement field effect transistor (39), having the other source/drain electrode and its gate electrode connected to input means, and wherein said depletion field effect transis¬ tor (49) is such that the body effect attributable to a sufficiently high voltage on said input means causes said depletion field effect transistor (49) to operate in an enhancement type mode. 9. A circuit according to claim 8, charac¬ terized in that: said clock signal means are selectively decoupled from said circuit by decoupling circuits (24, 26) which are operated in synchronism with a signal pro- vided by said enabling means (4, 6, 20, 21). 10. A circuit according to claim 9, charac¬ terized in that said enabling means (4, 6, 20, 21) is coupled to said first node (NODE 1) through the source/ drain path of a further enhancement field effect trans- istor (44) . OMPI

Inventors: DONALDSON DARREL DOUGLAS, HONNIGFORD EDWARD HERBERT, POEPPELMAN ALAN DAVID, DONALDSON, DARREL, DOUGLAS, HONNIGFORD, EDWARD, HERBERT, POEPPELMAN, ALAN, DAVID
Applicants: NCR CO, NCR CORPORATION
Application year: 1983
Main classification: G11C17
IPC codes: G11C16, G11C17, H03K17