ELECTRON BEAM-OPTICAL HYBRID LITHOGRAPHIC RESIST PROCESS

Abstract: An intra-level, hybrid electron beam/optical lithographic process. A substrate is prepared by applying an adhesion promoter which is compatible with both electron beam and optical processing. To the adhesion promoted substrate surface a layer of positive resist material is applied. A fine pattern (10) is delineated in the resist by writing with an electron beam to leave a fine pattern of unexposed resist. Large areas (12) of the resist material are optically exposed while protecting the fine pattern with an optically opaque mask. Electron beam (10) and optically exposed (12) portions are removed in a developing step to leave a fine geometry pattern of resist adherent to the substrate surface.

Description: ELECTRON BEAM/OPTICAL HYBRID LITHOGRAPHIC RESIST PROCESS BACKGROUND OF THE INVENTION This invention relates in general to a hybrid lithographic process, and more particularly to an intra-level hybrid electron beam/optical photolithography process. In the semiconductor industry photol thography techniques are widely used for patterning semiconductor substrates or for patterning thin layers of material overlying semiconductor substrates, PC boards, and the like. In the conventional photolithography process a layer of photoresist is applied and portions of the photoresist material are exposed, usually through a mask, to cause exposed and unexposed portions to have different dissolu-. tion rates in a photoresist developer. Upon applying such a developer, one of the exposed or unexposed portions is removed to leave a patterned mask layer on the underlying material. The patterned photoresist layer then may be used as an etch mask, ion implant mask, metal lift-off mask, or the like. It has been conventional for a number of years to optically expose the photoresist layer through a mask. Exposure is accomplished with actinic radiation, usually having an intensity peak in the ultra violet spectral region. As the semiconductor technology progresses, there arises a need for producing patterns having very small size or critical dimension. As the size of the photoresist patterns decreases, however, to the range of 1-2 micrometer and even further into the sub-micrometer region, it becomes impossible to resolve such small sizes with optical techniques . In view of the limitations on optical techniques, some work has been done on the use of electron beam exposure of .fl the photoresist layer. Electron beam exposure is capable of delineating fine pattern geometries, but has the disadvantage that exposure of large areas is very time consuming because the exposure is made with an electron beam of small cross sectional area. Because of the nature of resist materials, an all electron beam exposure process would, in many cases, require the time consuming exposure of large areas. Resist materials can be classified as either negative or positive resists. With negative resist, the unexposed resist portion is removed during the developing process; with positive resists, the opposite is true and only the unexposed portions remain after developing. In developing a pattern, such as a gate electrode pattern on a complex MOS IC, in which fine geometries are required but in which only a small proportion of the total surface area is to remain covered, the use of negative resists and an electron beam exposure process would be advantageous. The electron beam could provide the necessary high resolution pattern but only a small portion of the resist layer would have to be exposed. Negative electron beam resists, however, suffer from swelling effects, especially for pattern sizes less than about 1 micron. The swelling effect can result in poor replication of the desired pattern. Negative resists are, therefore, generally not acceptable for use in high resolution, fine geometry electron beam processing. To use a positive resist in this application, however, would require the time consuming exposure of a large proportion of the substrate area. The high throughput of a production process, therefore, is seemingly incompatible with the high resolution achievable with electron beam exposure. To achieve the high resolution obtainable with electron beam resist exposure and yet maintain a production capable process having high throughput, it is desirable, therefore, to combine electron beam and optical lithography ^ SSΪΪEA 0_-H in a single hybrid process. Others have disclosed the use of hybrid technology, but prior art processes have not been entirely satisfactory. In one hybrid process two layers of resist are used. One layer is electron beam exposed in a fine pattern and a first etching step is carried out using this pattern as a mask. Then a second layer of resist is applied and optically exposed to pattern the large substrate areas in a second etching step. This inter-layer hybrid process has the obvious disadvantage that a number of extra steps are required. In another disclosed process using only a single layer of resist, a positive resist has been used; but in the electron beam exposure portion of the process the resist has been electron beam overexposed to such an extent that the tone of the resist has been reversed from positive to negative. Optical processing then proceeds in a normal manner as with any positive resist. This process has the disadvantage of poor resolution, decreased resist contrast, and the need for higher, and thus longer, electron beam doses. To overcome problems inherent in such prior processes it is an object of this invention to provide an improved hybrid lithographic process combining electron beam and optical lithography. It is a further object of this invention to provide an improved hybrid lithographic process in which a positive resist material is utilized and maintains its positive tone for both electron bea and optical exposure. It is the further object of this invention to provide an improved hybrid lithographic process having fine geometry resolution and high throughput. It is a still further object of this invention to provide an improved hybrid intra-level electron beam/optical lithographic process. BRIEF SUMMARY OF THE INVENTION The foregoing and other objects and advantages of the invention are achieved through a unique intra-level hybrid process which combines electron beam and optical lithography. The substrate upon which a resist pattern is to be formed is prepared by the application of an adhesion promoter which is compatible with both electron beam and optical processing. A positive photoresist, sensitive to both electron beam and optical exposure, is applied to the substrate and subsequently exposed. The fine geometry portions of the pattern are electron beam exposed and the large areas without fine geometry features are optically exposed. The process, capable of high throughput, is completed with a resist development step to leave an adherent layer of resist having fine geometry features on the underlying substrate. BRIEF DESCRIPTION OF THE DRAWING The sole FIGURE illustrates a representative composite mask for patterning an array of fine geometry patterns in accordance with the invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS In the following, the invention will be more particularly described with respect to specific examples relating to the patterning of a resist layer and the subsequent use of that resist layer as an etch mask for patterning gate electrodes of an MOS IC. These particular embodiments of the invention are selected merely to illustrate the invention; while the invention is particularly suited to this application, it is not intended that the invention be limited to such embodiments. OMPI The FIGURE illustrates a portion of a composite mask of the gate level of an MOS integrated circuit. The pattern comprises a plurality of gate electrodes 10. In processing an MOS integrated circuit, a layer of electrode material is applied over the surface of the semiconductor substrate. That layer of electrode material must then be patterned and excess electrode material removed to leave only the electrodes. In accordance with an embodiment of the invention, this is accomplished by applying a layer of positive resist over the electrode material. To delineate the gate electrode pattern, the photoresist is exposed by writing with an electron beam around the electrodes. Electron beam writing is capable of producing high resolution patterns and can delineate, for example, a gate electrode pattern having a width of only a fraction of a micrometer. To conserve time arid to provide a high throughput, production compatible process, the electron beam exposes only the resist around the desired fine geometry electrode 10 and extending outward from the electrode to the edge of the rectangle 12. The remaining resist, requiring no fine delineation, is then optically exposed using a conventional photo mask that overlays and masks the area already electron beam exposed. The necessary photo mask for this step thus need only have a plurality of opaque rectangles which are roughly aligned with the rectangles 12. The optical exposure provides for the rapid exposure of the resist material from the remaining area and which in turn provides for the removal of unwanted gate electrode material from the larger area of the semiconductor substrate. The resist around the electron beam delineated electrodes 10 is protected from exposure during the optical exposure portion of the process by the opaque rectangles provided on the optical mask. The combined exposure, electron beam and optical, thus exposes all of the resist material in the single layer of resist except that overlying gate electrodes 10. OMP Following the hybrid exposure the resist is developed to remove the exposed resist portions. The remaining resist, overlying the ultimate gate electrodes, is then used as an etch mask and the unwanted electrode material is etched using wet chemical etching, plasma etching, reactive ion etching, or the like, as needed. In practicing the process in accordance with the invention, a resist material must be used which functions satisfactorily " for both optical and electron beam exposure. A number of commercially available resist materials are available which work in this hybrid process. One such resist is PC 129 SF, now known as Allied P 2025 made by Allied Chemical Corporation. To insure that the patterned resist material adheres to the underlying material and remains adherent through subsequent processing operations, the use of an adhesion promoter is desirable. The adhesion promoter must be compatible with a process involving both optical and electron beam exposed portions of the resist. The need for an adhesion promoter is especially great when isolated islands of unexposed positive resist material smaller than about 2-3 micrometers in width are formed. It has been found particularly advantageous to use a double adhesion promoter to insure adhesion of very narrow resist areas. In particular, it has been advantageous to use a halogenated silane promoter and then an amino silane promoter with a separate cure step for each promoter. The two promoters are compatible with each other and enhance different adhesion mechanisms present with the optically and electron beam exposed resist portions. A preferred halogenated silane is vinyltrichlorosilane (VTS). A preferred amino silane is 1,3-divinyltetramethyldisilazane although materials like hexamethyldisilazane (HMDS) can also be used. The following non-limiting examples represent best modes contemplated by the inventor for practicing the invention and serve to describe the invention further. EXAMPLE I Semiconductor wafers for fabrication of MOS integrated circuits are prepared by steps which include providing a layer of gate insulator on a semiconductor substrate and overlying the insulator layer with a layer of heavily doped polycrystall ine silicon. The polycrystall ine silicon material is to be patterned to form gate electrodes of the integrated circuit. The substrates are dehydration baked in a 200°C oven purged with dry nitrogen for two hours. After cooling to room temperature, the substrates are immediately flooded with a VTS solution comprising 2.5 cc of vinyltrichloro- silane and 50 cc of xylene. Substrates are then spun at 500 RPM for 1 second and 5000 RPM for 10 seconds. The VTS solution is then thermally cured at 90°C for 10- minutes in a nitrogren purged oven. After cooling to room temperature again, a second adhesion promoter is applied to the substrate by immediately flooding the substrate with undiluted 1 ,3-divinyltetramethyldisil azane , spinning the substrate at 500 RPM for 1 second and then 5000 RPM for 10 seconds. The second adhesion promoter is thermally cured by heating to 90°C in a nitrogen purged oven for 10 minutes. After again cooling the substrates to room temperature a 2:1 diluted resist solution comprising PC 129 SF resist and resist thinner is applied to the adhesion promoted substrates. The substrates are spun for 1 second at 500 RPM followed by 20 seconds at 4500 RPM to provide a uniform layer of resist 0.5 micrometer thick. Prior to exposure the resist coated wafers are pre-baked for 30 minutes in air at 90°C. The substrates are first electron beam exposed to del ineate " gate electrode patterns in the resist layer. The resultant width of the pattern is dependent upon electron beam dosage; very narrow gates additionally experience proximity exposure from imaging both sides of the narrow gate. Electron beam doses around the gate electrode patterns are therefore adjusted for the various sized gates being patterned. Gate electrode areas are exposed with doses ranging from about 132 yC/cm 2 for gates of about 0.5 micrometer width to about 139 μC/cm 2 for 1.0 micrometer width gates. After the electron beam exposure the substrates are aligned on a conventional optical photoresist alignment tool. The electron beam patterns are covered by an aligned opaque region during an optical exposure of about 15 seconds at 6.0 mW/cm 2 . Additionally, during this exposure, patterns greater than about 3 micrometers in dimension are also optically exposed. After the hybrid lithographic exposure, both the electron beam exposed and the optically exposed images are developed in a single development step using a conventional photoresist developer. The substrates are immersion developed in D-900 developer diluted to 2:1 with water at 21°C. D-900 is a developer supplied by Polychrome Corporation. The developing is quenched by immersion into pure water followed by spin/spray rinse with water and spin dry. After development, the resist patterned substrates are post-baked at 90°C for 30 minutes and then plasma etched in a CC1 based plasma etchant. The resist material is stripped from the substrates in oxygen plasma to leave patterned gate electrodes positioned on the gate insulator. -^3RE E XAMP LE I I Integrated circuit substrates are provided which comprise semiconductor substrate having a thin gate insulator on one surface. A multi -layered structure of gate electrode material comprising a first layer of titanium suicide, a second layer of polyi ide and a third overlying layer of plasma deposited silicon dioxide is provided on the gate insulator. Adhesion promoters and resist material are applied as in Example I. The multi-layered gate electrode structure is patterned as in Example I with the following exceptions. Because the multi-layered structure has a different atomic number Z than polycrystal1 ine silicon, the electron beam energy must be adjusted to higher values. The resist is electron beam exposed with doses ranging from about 148 μC/crπ 2 for 0.5 - micrometer gate electrode widths to about 151 μC/cm 2 for 1.5 micrometer gate widths. Additionally, in etching the multilayer structure, the plasma oxide and polyimide are first reactive ion etched before finally plasma etching the titanium suicide. EXAMPLE III Substrates are prepared and processed as in Example I except that the developer is more dilute to yield a longer, more controllable development time. The developer is D-900 diluted with water in a ratio 1:1 and the development time is correspondingly increased to 45 seconds. EXAMPLE IV Substrates are prepared and processed as in Example I except for a change in developing. The developer is D-900 diluted with water in a ratio 3:2 and the developer is allowed to puddle on the substrates for 20 seconds. Puddle development differs from immersion developing in that the substrate sees only a fixed amount of developer, namely that volume of developer held on the wafer by surface tension. The developer is flooded onto the wafer and then after 20 seconds the developer is spin/spray rinsed off with clear water followed by a spin dry in air. In each of the examples, I-IV, patterned gate electrodes are realized having minimum gate dimensions ranging from 0.5 micrometers to 1.5 micrometers. Thus it is apparent that there has been provided, in accordance with the invention, a hybrid lithography process which fully meets the advantages and objects set forth above. While the invention has been described and illus¬ trated with specific embodiments thereof it is not intended that the invention be so limited. It will be apparent to those skilled in the art after review of the foregoing that variations and modifications in the process are possible. Other substrates may be used, the resist may be used for other than an etch mask, other resists may be used and the resist may be applied in different manners and thicknesses. Depending upon the resist material used and the particular applications, exposure times and intensities will vary, and other developers can be used. Accordingly, it is intended to embrace all such modifications and variations as fall within the scope of the appended claims. -

Claims: Cl a i ms 1. A hybrid process for combining electron beam and optical lithography for forming a pattern in a resist layer on a substrate which comprises the steps of; forming a layer of positive resist overlying said substrate; electron beam exposing portions of said resist layer which are to be removed, said portions located proximate to and surrounding unexposed portions of said resist layer which form said pattern; protecting said unexposed portions from optical exposure b positioning a mask having optically opaque regions over said substrate; optically exposing portions of said resist layer not protected by said mask; and developing said resist to remove exposed portions leaving a pattern of unexposed resist overlying said substrate. 2. The process of claim 1 further comprising the step of applying an adhesion promoter to said substrate before said step of forming a layer of positive resist. 3. A hybrid process for forming a pattern in a resist layer on a substrate which comprises: applying an adhesion promoter to said substrate; forming a layer of positive resist overlying said substrate; electron beam exposing a first portion of said layer surrounding an unexposed portion of said layer; optically exposing a second portion of said layer surrounding said first poVtion; and developing said layer to remove said exposed first and second portions, leaving a pattern of said unexposed portion of said layer. 4. The process of claim 3 wherein in said step of applying an adhesion promoter said promoter is selected to be compatible with both electron beam and optical processi ng. MT 5. The process of claim 4 wherein said adhesion promoter comprises first and second promoters compatible with each other. 6. The process of claim 4 wherein said adhesion promoter comprises a halogenated silane and an amino silane. 7. The process of claim 6 wherein said halogenated silane comprises vinyltrich!orosil ane. 8. The process of claim 6 wherein said amino silane comprises 1,3-divinyltetramethyldisilazane. 9. The process of claim 3 wherein said step of electron beam exposing comprises writing around said unexposed portion with an electron beam to form said first portion adjacent to and surrounding said unexposed portion. 10. A process for etching fine geometry patterns in a material which comprises the steps of: applying a layer of positive resist to said material; electron beam exposing a first portion of said layer to delineate a region of unexposed resist; optically exposing a second portion of said layer, said first and second portions comprising an exposed portion of said layer of resist surrounding an unexposed portion of said layer of resist including a fine geometry pattern; developing said layer of resist to remove said exposed portion, said unexposed portion of said layer remaining adherent to said material; and etching said material using said unexposed portion of said layer as an etch mask.

Inventors: HELBERT JOHN N, HELBERT, JOHN, N.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1983
Main classification: G03C5
IPC codes: G03C1, G03F7, H01J37