HIGH SPEED TESTING OF COMPLEX CIRCUITS

Abstract: Improved apparatus and process for testing a variety of electronic components, such as printed circuit boards (101, figure 3), which have a large number of potential circuit paths. The apparatus of the invention is characterized by a versatile searching sequence which achieves a surprising combination of search speed and efficiency and hardware economy. Advantages embodiments of the invention enable multiple test stations (32, 34, 36, figure 1) to be connected in parallel to one set of switch cards through special "matrix boards" (90, figure 3). Multiplexing of the switch cards is accomplished by only bringing one circuit board into contact with test probes at one time. The sytem has a microprogrammed sequencer wherein signals representative of pin and board designations of switch boards are utilized in conjuction with a PROM which normally contains the next address to the currently-addressed pin and board designation.

Description: High Speed Testing of Complex Circuits BACKGROUND OF THE INVENTION Tnis invention relates to a hign-speed testing apparatus for complex printed circuit ooards. Altnough there nas been much apparatus developed for use in testing printed circuit boards, most such apparatus has been severely limited in its capability to perform actual certification of error free circuits. This problem has become even more acute as tne number of connections and components on circuit ooards has increased. Tnerefore it has remained a proolem to provide a circuit-board testing apparatus that could, using a commercially-acceptaole amount of hardware, provide a hign-speed means to certify circuit boards. Tnere is a large amount of switcning circuitry necessary to perform such testing. It has not been possible in the past for multiple test stations to share this switcning circuitry. In understanding tne achievement to be described oeiow, it snould be understood tnat both manufacturers and purchasers of circuit boards are often faced with testing hundreds or even thousands of a ooard of a single configuration and tnen proceeding to test another board, wnoily different in design, yet witn, typically, up to 10,000 or more electrical connections. Errors in testing can have very serious commercial consequences. Tnerefore, it has become necessary to undertake extraordinarily expensive testing procedures or settle OMPI upon statistical tasting tecnniques tnat will not provide error-free certification capability. One of the major objectives of the system is to test and report faults in an entire pattern of opens and 5 continuities as quickly as possible. Tne key features of the macnme tnat allow sucn a rapid test rate are: 1. Tne data stored for tne test sequence is in a raw form whicn is easily accessible, can be used quickly, and interrogated by tne system to determine if there is a 0 difference between wnat tne macnine has learned about a circuit to oe tested and wnat tne macnine is actually measuring on that circuit. 2. Tne electrical sense circuitry is localized on eacn individual switcn card and tne amplifying circuit 5 associated witn switcn cards provide one single strong signal transmitted from switcn card to tne point interface card and main CPU 200 indicates whether or not any of tne cards has sensed a continuity. 3. Tne main CPU (central processing unit - data ύ processor) programs tne sequencer and controls whicn test station is to oe used at the time, and whicn stored (learned) program is to be run at any given moment. Anotner o ect is to report results to the operator of the testing apparatus in a useful form. This involves 5 botn removing fault information whicn is redundant, for example multiple detected shorts wnich are the result of tne same physical imperfection in the circuit board under test, as well as translating tne fault information from the raw form used in test sequencing to a form more directly usaole by a tecnnician in repairing a faulty board. It is further an object to be able to service multiple test stations from one set of switch cards and sequencing control circuitry. In order for this snaring of apparatus to oe effective, the speed of the testing procedure must be especially fast. In addition to the speed requirement, it is necessary tnat multiple test stations be interconnected to the switch cards in a way tnat is DOtn compact and does not require tne additional costly circuitry. A further object is to reduce tne cost of switcn cards. As a tester capable of testing 10,000 points uses 80 switcn cards, switcn cards contribute suostantially to tne cost of sucn test apparatus. Reduction in tne complexity or tne circuitry on eacn of these cards is advantageous. SUMMARY OF THE INVENTION The basic purpose of a machine built according to tne present invention is to compare continuity/opens pattern of a circuit under test witn that of a known complex circuit, particularly a printed circuit board, and to quickly and reliably report circuit faults. Tne present circuit board tester provides for multiple test stations to snare one set of switcn cards and contol circuitry. Physically this is acco plisned by connecting the test probes at each test station in parallel with tne test probes at the other test stations. Means is further provided for controlling the lowering of boards to be tested onto tne test probes so tnat only one ooard is in contact witn test prooes at one time. Switcn cards for a 10,000 point tester provide pins to connect to 10,000 points in a compact space. Yet in order for tnree test stations to share one set of switch cards, it is necessary for tnree times as many connections to oe made to that set of switch card connectors. Tnis parallel connection of tne test stations is accomplished by the use of printed circuit matrix cards of unique design. Tnese matrix cards provides a practical mechanism for cabling from tnree test stations to converge on and.be connected to one set of switcn cards. In oroer to De aoie to test witn sufficient speed to service multiple test stations from one set of control and switcn circuitry, tasks are distributed among different pieces of hardware. A main processor provides overall control. This processor determines which test station will, test at any time as well as providing tne overall control of tne test procedure. Tne mam processor issues "stimulate and scan" commands to a sequencer; the sequencer sends tne commands to the switcn cards commanding tne closing of specific switches. A sequencer is microprogrammed to control tne basic scanning sequence with high speed. Given a stimulus point and a point from which sensing should begin, the sequencer can control tne opening and closing of switches to determine the "first hit", tne lowest logically numoered point in tne scan whicn has continuity with the stimulus point. Tne sequencer also provides the source voltage wnicn is to oe applied to tne stimulus. test point. Via a hit signal, all switch cards route sensed current back to the sequencer so tnat presence of a continuity can be rapidly determined. Switcn cards are simple in design, yet operate witn a test procedure tnat can test multiple points at one time. Control signals are provided by the sequencer to tne switcn cards tnrougn a control DUS on tne switch card backplane.- Eacn switch card can determine its position from connections wired to tne switch card backplane. Switcn cards need only be able to turn on one switch at a time, and need only oe able to respond to two types of commands: turn on tne designated switcn if your number is greater than the indicated card number; turn on the designated switcn if you number is equal to tne indicated card numoer . In tne test procedure useo, test points are sequentially used as source points; for each souce point, otner test points are scanned in searcn of continuity. Tnis searcn for tne firs continuity is done in the same order as tne points are used as source points. These resulting first continuities are then stored in a test table. Tnis testing sequence results in a test table in which continuities are linked together. This facilitates tne removal of redundancies when faults are detected. In tne test procedure used, tne searcn for continuity involves testing groups of test points at once. The test points in tnese groups are on separate switch cards. This.makes it possible to test groups of points at once (providing great speed advantage) while still maintaining a simple design for tne switch cards (providing economy and reliability). OMPI BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a perspective of a compact 3-test station embodiment of the invention, wherein each station comprises a test fixture and eacn operator nas ready visual access to a smgie CRT display apparatus. Figs. 2 and 3 togetner form a diagram illustrating the overall testing apparatus. Fig. 4 depicts a matrix card useful in connecting 3 test stations to one set of switch cards. Fig. 5A is a test table tnat records the continuity pattern depicted in Fig. 56. Fig. 6A is a test table that records tne continuity pattern depicted in Fig. 6B. Fig. 7A is a test taoie tnat records the continuity pattern depicted in Fig. 7B. Fig. 7C shows the same continuity pattern witn tne addition of a snort. Fig. 8A is a test table tnat records the continuity pattern depicted in Fig. 83. Fig. 8C snows tne same continuity pattern witn the addition of an open. Fig. 9A is a schematic of circuitry of tne point interface card (PIC) wnicn connects to a portion of the control bus of the switcn card backplane. Fig. 9B is a scne atic of circuitry on the PIC used to generate a source voltage and to sense tne presence of resulting current. Fig. 9C is a scnematic of a portion of tne circuitry on the PIC. Fig. 9D is a scnematic of circuitry on tne PIC used to indicate the number of switch cards installed the tester. Fig. 10A is a scnematic of decoding logic on the PIC. Fig. 103 is a scnematic of sequencer control circuitry on the PIC. Figs. IOC and 10D are scne atics of tne sequencers of the PIC. Fig. 11 scne atically depicts pins on switch cards; the pins that correspond to the continuity pattern of Figs. 6B, 76, and 88 are specially indicated. Fig. 12 scnematically depicts pins on switch cards; tne pins that correspond to the continuity pattern of Fig. 1C are specially indicated. Fig. 13 schematically depicts pins on switch cards; also indicated is tne scanning sequence that is used once a nit nas been detected on level 2. DETAILED DESCRIPTION Terminology The present invention is used in tne testing of tne electrical continuity of circuit boards. Tne testing involves measuring tne continuity pattern among a set of test points on the circuit ooard to be tested and comparing tnis pattern witn a rererence continuity pattern. There are two types of faults: shorts and opens. Tne oθ ective of the test is to detect tnese faults, in other words, to determine wnetner tne circuit board under test has the desired continuities (i.e. does not nave opens) and wnetner tne ooard has continuities which are not desired (i.e. snorts). Test points are locations on tne circuit board from wnicn it is desired to test continuity. The term "test points" is also often used to refer to the probes of the testing apparatus wnicn contact the test points on the circuit board. The slight difference between these two meanings is rarely significant, and the intended meaning can generally be inferred from tne context. A testing macnine utilizing tne present invention is capable of testing up to 10,000 or more test points. Continuity testing is accomplisned by the well know approach of applying an electrical potential across a possiDle circuit patn and measuring the resulting current flow. In other words, one measures the impedance between pairs of test points: if tne impedance is less tnan a tnresnoid value, tnen tnere is continuity; if the impedance is greater, then there is no continuity between tnose test points. ,vhen a pattern of metallic conductors is being tested (oare board testing), it is not necessary to determine the precise impedance of tne path; essentially, it is only necessary to differentiate between current flow and lack of current flow. Altnough the invention will be discussed in tne context of bare board testing, tne present invention is applicable to other forms of testing. For example, tne tester may be modified to provide for 4-wire testing. A tester witn 4-wire capaoility can more precisely measure impedance of a circuit patn. Tnis modification is particularly useful for loaded ooard testing, as is discussed below. Testing for continuity between two test points is accomplisned by connecting a source (or stimulus) circuit to one of tne test points and connecting a sense circuit to tne otner test point. The sense circuit also provides the source return (i.e. the ground side of the source voltage) . Two switcnes are associated with eacn test point: one to connect tne test point to the souce circuit (in wnicn case tne point is called a "source point"), and the otner to connect tne test point to tne sense circuit (in which case the point is called a "sense point"). In tne testing procedure described oelqw, although only one source switch is closed at any given time, it is often aαvantageous (speeding the testing process by reducing the number of successive switch closures necessary to fully cnaracterize a circuit ooard) to close a numoer of sense switches simultaneously. Tnese switcnes must have very low noise characteristics because of the speed of the switching operations contemplated. Typically, solid state switcnes are used. CMOS type switcnes are generally satisfactory. Otner types may be used as, for example, wnen hign voltage is used in the testing procedure. Tnese switcnes are arranged on circuit boards referred to as switch cards. A typical switch card will " include enougn switcnes to connect to 128 test points, i.e. 256 switcnes. Tnese switcnes are mounted on switch cards wnich themselves are held in switch card cages mounted on the frame of tne apparatus. Tne switcn cards are installed in card cages and by being plugged into connectors in a backplane in tne card cages. Each switch card cage holds 20 switch cards. A 10,000 point tester would thus include 4 card cages and a total of 80 switch cards. The connectors provide a pin for eacn test point to which a switcn card can connect, i.e. 128 pins per card. Tnere are additional connector pins for signals connecting to the point interface card (PIC) , wnicn will be described in more detail below. There are also connector pins that uniquely identify each position in eacn of tnese card cages; tnus, althougn the switcn cards may be identical, once plugged into tne card cages, each pair of switches on eacn switcn card is uniquely associated with one test point. In other words, tne assignment of test points is carried out by direct wiring of different slot positions within the switch card cages. If for each card one numbers tnese pins from 1 to 128, tnen all pins numbered 1 (and all associated test points) can be referred to as a "level". Thus, altnough test points can oe at arbitrary physical locations on a circuit ooard, it is often helpful to ignore the arrangement on tne circuit board and conceptualize the test points as being arranged in a rectangular grid pattern, eacn card oe g a column of test points, eacn level being a row of test points; with tnis viewpoint, eacn test point can oe referenced by its card numoer and level numoer. Anotner useful way to conceptually arrange tne test points is in one line. When discussed below, this numoering system will σe referred to a "logical numoering", and, unless otnerwise indicated, "test point numoer" will refer to tne "logical numoer" descrioed nere. As will oe described in great detail below, the testing procedure involves connecting, in sequence, eacn test point (except for tne last test point) as a source point. If the points are numoered in tne order in wnich tney are cnosen to be used as test points, then one can refer to higher numbered test points as being "above". Also, in tnis conceptual arrangement, tne "first hit" refers to the lowest numbered point for which continuity witn the selected source point is detected; "first" refers to tne numerical order, not necessarily to time. Since tne test procedure need not use a source points any of the test points on those cards which (altnougn installed in tne tester) are not wired. to tne currently installed fixture, tne logical numbering cnanges from one test fixture to anotner. Tne logical numbering depends on now many switch cards are used in tne test procedure, When a new fixture is installed at a test station of tne tester, tne operator, by use of tne video terminal, indicates now many test ponts are wired in the fixture. Tne tester can tnen divide tnis numoer by tne number of points per switcn card (and round up) to determine now many cards are actually used by tnat test fixture. "Pnysicai numoe ing" refers to numoe ing the pins in tne order tney are wired to a fixture. Wnen wiring, all pins on one switcn card are used before one uses pins on tne next card. Tnus, pnysicai numoering runs 1-128 on tne first switcn card, 129-256 on tne second switch card, and so fortn. ith 20 switch cards per cage, the first card cage would nave switcnes for test points 1-2560; tne second card cage would contain switches for points 2561- 5120; etc. Tne switcnes "know" with wnicn test point numoer tney are associated as a result of tneir position on the switch card and tne above-mentioned wiring of the switcn card backplanes in each card cage. Alenough pnysicai numoer g is used in numoermg test points wnen test fixtures are wired, it is not of mucn nelp in understanding tne testing procedure of tne present invention. As will be discussed below, there are advantages to cnoosing an order for source points (e.g. logical numbering) tnat does not correspond to the physical numoering of test points. Tne logical and pnysicai nu oers associated with any pin on any switcn card may σe computed as follows: O PI Logical Test Point = [(Total Cards used in tne Test)*(Pin # - 1)1 + Card # Pnysicai Test Point = [(Card # - l)*(Pins/Card) ] + Pin #. In tne test process, data is manipulated in terms of logical test point numbers. But logical numbers are different from tne test point numbers tnat are reported to tne operator, nerein called a physical test point. Before performing a continuity test on a circuit Doard, it is necessary to determine a reference continuity pattern against which the measured pattern of tested ooards will oe compared. Further, this pattern must oe communicated to the test apparatus. The reference pattern can be provided in tne form of a known correct circuit board; tne communication of tnis pattern to the test apparatus can be accomplished by a process called learning a board. Tne learn mode in wnicn tne tester can operate is similar to, out distinct from, the test mode. Learning involves loading a correct board onto tne test apparatus (in tne same fasnion ooards to be tested will be loaded) and running a test procedure called a learning sequence, by wnich tne test apparatus determines tne continuity pattern. This pattern is then stored in tne apparatus for use in tne determination of faults on Doards to be tested. Tnis reference continuity pattern is stored in wnat is called a test table. Because one does not generally nave access to a known good board until the tester has tested some boards, usually 2 to 6 boards of uncertain accuracy are used to completely "learn" a circuit pattern. This is accomplished by "learning" a number of boards and comparing the results, taking tnose aspects of tne continuity pattern tnat are most common among these boards as a presumption of what the correct pattern should oe. There is one register of memory reserved in the test table for each test point. Tnis register can be 2 bytes long and is maintained in the random access memory. Two oytes are used for eacn test taole entry in a system witn 10,000 test points. Thus, to fully describe a pattern of opens and snorts for 10,000 test points requires about 20K oytes of random access memory (RAM) . Tne macnine stores test information in tnis test table in raw form wnich is obtained by a test procedure conducive to tne speed of operation. However, tnis form of raw intormation is not very useful to tne operator of tne tester. Test point designations in tnis raw form are according to logical numbering. The operator of the tester relates positions of test points in tne fixture to physical numbering. Also, multiple continuity discrepancies can result from a single pnysicai fault, i.e. tnis raw information contains redundancies. Thus, tne machine must decide wnat information is useful to the operator (i.e. remove redundancies) and translate tnis from raw form to a form more useful to the operator. Overall Operation In order for a particular type of PC Board to be tested it may have a customized test head (alternatively, a universal grid fixture may be used, as described below under "Variations"). Tne test head or test fixture is a device tnat mechanically interfaces tne machine to tne board tnat is to oe learned and tested. In a typical situation, an operator may nave to test several hundred of a particular board type. The board may be being snipped from a board manufacture or it may be component- loaded. In order for a board to be tested on the macnine, it must be locked in place at one of the test stations of tne macnine. A test station is comprised of an operator control panel including a receiver assembly wnereoy tne test nead mecnanicaiiy interfaces to tne macnine. Tne ooard is placed on tne test head. Tne operator must tnen load a learned or otner test program into tn main CPU's memory from a floppy disk on which the program nas been stored in a RAM of tne CPU. This is conveniently done at the CRT unit. Each test station has memory space reserved, in wnicn it can maintain tne test tade for tne board to oe tested on tnat station. Tna operator tnen presses start at his test station. Tne main CPU tnen controls the sequencer through a point interface card wnicn controls tne switch closures on the switcn cards. Tne signals are routed from tne switch card to the test stations through tne matrix card(s) and cables. The measurement signals pass from tne test station to the test head, tnrough the test probes to the printed circuit ooard. An interlock mecnanism assures that only one test station is allowed to engage a test head to a board at a time. Tne results of tne test for a given test station are communicated througn an I/O board ( in the main CPU card cage) to the operator control panel. The operator control panel tnen removes redundant information and translates from logical test points to pnysicai test points, and prints the appropriate faults on the ticket printer using tne pnysicl test point data. A test is completed, the board under test is released from the test 5 nead on whicn it is mounted, and the main CPU goes on to service a next request from another test station on the CRT. Rererring to Figure 1, a multi-station testing apparatus comprises a frame 30 which includes three test lϋ stations 32, 34, 36. Eacn test station carries a fixture 38 into wnicn a printed circuit board may be "loaded" for testing. A cathode ray tube terminal is mounted on turntable 4ϋ for viewing from eacn of the test stations. In normal practice the test results can be displayed on 15 tne CRT or can oe printed at tne individual test stations. Figures 2 and 3 are a block diagram of electrical circuitry of tne test apparatus. Tne apparatus shown is one wnerein tnree distinct testing operations are carried ϋ out Dy tnree different test operators. Each- test operator is operating a test station wnicn nas tne capability of testing printed circuit boards witn 10,000 test points. Witnin frame 30 (Fig. 1) are four switch card cages 5 eacn having 20 slots for receivng switcn cards 100 (Fig.3). Tnese switcn cards are connected in parallel to all 3 of the test stations by use of matrix cards, which will oe descriDed in greater detail below. In a 10,000 point tester, cables bearing 10,000 conductors from eacn 0 or tne test stations all converge on and are connected to tne switcn cards. Tnis massive interconnection is efficiently and compactly accomplisned by use of the OMFI matrix cards. Otner control equipment including tne controller processing units can also be compactly carried within frame 30. Previous testers have provided only one test station for eacn set of switch cards. The present tester can oe expanded to multiple test stations and still use only one set of switch cards. The preferred way to expand to tnree test stations is to mecnanically multiplex the ooards, all tnree test stations using the same switches, and their use being mecnanicaiiy, or electrically, segregated. Tnis snared use of tne switcnes represents a suostantial economy, since a station capable of testing 10,00J test points requires 30 switcn cards, each card naving 256 switches. Tnis snaring is maoe possiole by the comoination of two aspects of tnis tester: (1) the tester operates fast enough tnat tnree stations can be serviced with one set of switcn cards; and (2) tne tester provides an arrangement by which the enormous number of conductors could all De pnysicaily connected to one set of switcn cards. Tne first aspect (speed) is made possible by use of a particularly efficient testing procedure and by the tne efficient division of tas S among several separate processors. Tne second aspect (physical connection) is made practical by tne use of matrix cards and the mecnanicai multiplexing at tne test fixtures of tne circuit boards to be tested. A testing station comprises a circuit board to be tested 101 under a test head 102 which is conveniently customized for eacn kind of printed circuit ooard to oe tested. Tne test head (or test fixture) 102 will comprise wiring that will communicate directly througn test point connections in tne test weii 104 (Fig, 3) to the matrix board 90 shown in Fig. 5. Various customized test neads can be installed into eacn of the test well. The matrix boards are an extremely compact and efficient means for routing signals between tne switcn cards 100 and tne test neads wnen tnere are multiple test stations. Eacn testing station also includes, conveniently, an operator control panel 110 and a printer. Most importantly, nowever, tne test station comprises printer/operator control microprocessor 112, suitaoly oasad on a Motorola 6809 microprocessor cnip, control circuits 116 for interfering witn the control panel and printer control means 113. In addition, each operator station has its own bank of RAM 114. In general, 128K oytes of memory is used wnen testing a 10,000 test-point circuit. Tne tasks of microprocessor 112 include: responding to tne position of operator controlled switches, receiving test information (raw data from tne testing of a circuit ooard) from tne main CPU 200, removing redundant information, translating the remaining information from "logical test-point" form to a physical test-point form (a form more useful to the operator), and controlling a printer (a printer is located at each test station) wnicn is used to provide a record of test results. In addition, tnere may also be sufficient memory in the operator control panel processor to perform furtner translation to "user language". User language is tnat used to associate information describing a position on the board in terms otner than test point numbers; it is a description more directly usable by a technician involved OMTI IB in tracking down and correcting tne pnysicai " imperfections in the circuit boards that resulted in the snorts and opens reported by tne tester. For example, "pin 6 of chip U15" instead of "test point 1295". It is important to note that the processors at eacn of the tnree stations can eacn be operating on these redundancy-removing and translating functions while the main central processing unit 200 is servicing a test sequencing operations on one of the boards under test 101. Tnus tne mam CPJ 200 need ot take time after eacn test sequence to process rne raw data resulting from tne test sequence. Instead, this data is passed to the processor at tne individual test station, preventing tne redundancy removal and translation operations from delaying tne overall operation of tne tester. Tnis is one of tne features wnicn makes multiwell snaring of one set of switch cards possible. Tne main CPU 200 (Figure 2) is a microprocessor control system. Memory 206 contains the program for controlling the testing procedure (wnicn is used for testing at all test stations) as well as memory to contain information relating to each of tne tnree test stations. An important cnaracteristic of the CPU 200 is that is comprises enough memory, two bytes or more (per point) , to define tne condition of each of the points wnicn are to be tested on each of tne tnree test fixtures. Typically, 64K of random access memory 206 will be reserved and availaole for eacn (typically tnree) of the test stations. The primary job of tne main CPU 200 is to operate the testing sequence for eacn of tne ooards under test, in a manner that will be more fully described below. Eacn test point may be considered a single wire. When only a single testing operation is associated with tne apparatus tne wire may go directly to tne test fixture. When a plurality of testing operations are associated with the apparatus the single test point conductor is routed to tne matrix board for furtnar routing to the test fixture and to tne circuit board to be tested. A "point interface card" (PIC) controls all switcn cards. It interfaces between cards and tne main computer controller unit (CPU). Tne point interface card functions to determine what test points and the condition of test points and sequence of testing as tney affect tne switch cards. One point interface card will control all 3ϋ slot positions in the switcn card cages. Tne point interfaces card controls the pattern in whicn switcnes are opened and closed in response to the main CPU. (In practice, it is usually desirable to nave a new control program for each circuit board con iguration to be subject to test. Tne control program is readily "self-learned" by a program in tne CPU's read¬ only-memory (ROM) device and RAM 206. As a general rule, aoout 2 to 10 boards can "teacn" tne ROM through PIC card 129. This general procedure is already well-known. Tne test pattern, or sequence, in wnicn tne card is tested is estaolisnad by D.C. excitation of a measurement circuit from sequencing through a single point interface card 129 wnicn is described in Figs. 9 and 10. A testing procedure, taken together witn the signai- distriouting and signal-processing apparatus described above, provides not only wnat is oeiieved to be an o imun balance between snort test time and equipment cost out to acnieve such a balance while providing the versatility to accept a large numoer of special proDlems associated with circuit board testing. Matrix Cards In order to accommodate tne great numoer of potential connections and handle them in a reasonable amount of space, a matrix printed circuit board is snown in Figure 5. The switcn card backplane has sockets on one side for tne switcn cards and has sockets on tne otner side for one edge of eacn of the matrix cards. Tnere is one matrix card per switch card, i.e. for a 10,000 point tester, there are 80 matrix cards. In tne matrix ooard of Figure 5, there are two groups or conductors 94 and 92 but only one of eacn is snown in full, tne otner of eacn Deing indicated in fragmentary form. Eacn side of an illustrated board 90 has 123 - terminals, 80 wnicn are associated directly with a set of parallel conductors 92 or 94. Conductor set 92 is insulated from conductor set 94 by insulator layer commonly used in printed circuit board manufacture. However, preselected connections are made between tne conductor sets using the conductor-lined barrels (plated- tnrougn holes) 96 (according to the estaolisned tecnniques of printed circuit board tecnnology) . Figure 5 indicates the position of the connections in the insulator layer 95. It is to be noted that there are sets of terminals 80 at top and ootto of tne board. O PI A second set of plated-tnrough noles (arranged along a diagonal perpendicular to the first diagonal of plated- tnrough holes) may also oe used. This second set of connections enables the connectors on opposite sides of tne matrix card to be in tne same orientation with respect to tne matrix card. In other words, each of the three connectors (connecting to tne tnree test stations) would nave pin 1 on the left (from tne point of view of the connector) . Tnis arrangement of connector pins enames caoles to be routed from eacn of the tnree test stations witn a minimum of twists in tne cabling. Tnis is significant oecause an enormous bundle of cabling converges on tnese matrix cards from eacn of tne stations. In practice, tnis means tnat tnree distinct circuit Doard testing operations may be serviced from three perimeters while data is fed to and from a master controller serviced from tne fourtn side of the board. Eacn pin of tne matrix ooard is associated witn two switcnes. A source switcn forms a connection with a source signal. A sense switcn forms a connection to a sense signal. Eacn pin of the matrix ooard also connects to test prooes in eacn of three test fixtures. Use or matrix cards enaoles a system to oe designed wnicn can oe initially operated witn a single test station and later easily upgraded by the addition of otner stations. Tne same switcn card cage arrangement as is used for a single station system can oe used with a multiwell system. Witn a single test station, the caoles connecting to tne test fixture can connect directly to the switch C FI ~ ~ ~ cards. Wnere matrix cards are used, a Terad ' ne backplane is used between the switch cards and the matrix cards. A Teradyne backplane has back-to-back wired edge connectors, i.e. tne edges of switch cards plug into one side and the edges of matrix cards plug into the other side. Multiplexing A feature of tne present tester is that multiple test stations share one set of switch cards and one set of control circuitry. Tnis is accomplished witnout tne addition of circuitry. Tne test.fixtures (one of tnese customized fixtures is installed in the test well at each test station) are aii connected in parallel to tne switcn cards. Also provided at eacn test station is means for keeping tne circuit Doard to be tested from contacting the test proDes until it is that station's turn to test. Special spring-loaded locating pins are used to nold the circuit ooard above the test prooes. Locating pins are commonly used to accurately position circuit ooards. Tnese are noles in, for example, two opposite corners of the circuit board; printed circuitry and holes for component leads are precisely positioned relative to tnese locating noles. The locating pins of the present tester are actually compound pins: a tnin portion of the pin is located on the top of a portion wnich is of greater diameter; the thin part of the pin is sized to penetrate a locating hole, wnile tne ooard rests against tne greater diameter portion of the pin. This entire compound locating pin is spring mounted so that tne circuit will be supported above tne test probes (without contacting the probes) , but when downward force is OMPI applied to tne circuit ooard, tne pins give, allowing tne board to lower into contact witn the test probes. Tne downward force on the circuit board is applied by a door over the test fixture. When the test of a board is completed, the force on the circuit board is released, tne springs pusn tne ooard oack up off tne test prooes, releasing electrical contact and freeing the switcn cards to be used witn one of tne other test stations. Data Representation and Scanning Test Points The overall test procedure involves sequentially using each test point (except for the last test point) as a source point, and for eacn source point "scanning" tne points apove the source point to identify a "hit". A "hit" is the detection of a continuity between tne currently selected source point and at least one sense point; the "first hit" is the identification of the lowest numoered point in tne scan wnicn exhibits continuity with the source point. "Scanning" is the process of selectively closing sense switcnes. Numerous scanning procedures are possiole. The following scanning procedure offers particular advantages: (1) a relatively small number of separate test steps (due to sensing from groups of points at a time); (2) a simple design for tne switcn cards (for example, switcn cards need not De designed to close any arbitrary combination of switches, in fact, each card need only close one sense switch at a time) , (3) redundancies can easily be readily removed from tne data whicn results from tnis procedure because the resulting list of continuities is "linked". Tne tester nas botn "test" and "learn" modes. The test mode is tnat wnicn is used to detect continuity faults in circuit boards. The learn mode is used to ouild the test table from a know correct circuit board. The Dasic scanning procedure (successively using each point as a source point and scanning to determine tne first nit for tnat point) is tne same for both test and learn modes. However, when testing, additional scanning procedures will be used when the determined first hit does not agree with that indicated in the test table. First, tne basic scanning procedure will be descπoed in tne context of "learning" a board. Then, the modifications of this oasic procedure will be descriDed in tne context of detecting faults Tne reference pattern of continuities is represented in wnat is called a test taσie. Tnis is a list of first nits, one first nit for eacn test point (except for tne last) . The "first hit for test point X" is the logical number of tne lowest numbered point above x that has continuity with point X; if there is no such point, then the value of tne first hit is set to zero, or some otner special value tnat does not correspond to tne number of any test point. The test table is stored in a sequence of memory registers: tne address of the register corresponds to the number of the source point; the contents of tne register is the numoer of first hit for tnat point. For example, if wnen point 25 is used as a "§υ^2* > GMH source point (on a correct board) tne first hit is point 87, then of the memory registers used to hold the test taole, tne 25tn memory register will contain the number 87. Even if for any source point tnere would oe hits after tne first nit, the list of first hits still fully describes the continuity pattern of the circuit board. Tnis will oe explained by the following example. Assume tnat when point 25 is used as a source point, there would be a nit at point 107 as well as at point 87. In tnis case tne numoer 87 is recorded as the first nit for point 25; tne continuity between points 25 and 107 is not directly recorded. However, wnen point 87 is used as a source point, the first hit recorded for it will be point 107. Tnus tne list snows tnat point 25 is connected to point 87, and tnat point 87 is connected to point 107; because eacn pair of points is considered to oe either connected or not connected (degrees of impedance are not at issue) , one can conclude from examination of the list tnat point 25 is connected to point 107. In carrying out a test on tne illustrative system, it will σe assumed that the test program for a single Doard calls for tne testing of 2,560 connections: In practice, of course, different testing points may be selected wnen a particular circuit board to oe tested "teacnes" tne macnine (or is otnerwise known) to not require that tne testing include certain terminals on the circuit board. In tne following discussion of tne testing procedure, it will oe assumed tnat tnere are 64 points per switcn card, rather than tne 128 points mentioned in ' the discussion above. ... OMPI The matrix of test points can oe looked at as a numoer of switch cards assembled in a row, left to right, eacn card having its test point connections along ordinates extending upwardly. This arrangement of test points is scnematically illustrated in Figs. 11-13. Using sucn a model as tne oasis for discussion, it is pointed out that the general testing process is preferably one wnerein tne stimuli (i.e. source) points are selected, one by one, along each abscissa, left to rignt with the stimuli being moved upwardly to a new line of test points and back to tne leftmost card wnen one aDscissa finished. This sequence corresponds to the logical numoering oescrioeo aoove. For eacn stimuli point, tne pattern in which test points are sampled (i.e. sensed) to see if tney receive tne stimuli is also along tne aoscissa and from Dotto to top. However, all points being "sensed" along an abscissa are tested at once (until the sensing of a hit or open may require some otner procedure) . Also, it snould be noted tnat all points wnicn nave already been utilized in the procedure as stimuli points are not utilized as sensing points. Thus for each source point, the only points which are scanned in the searcn for a hit are tnose points aoove (i.e. witn nigher logical numoers than) that source point. Basic Scanning Sequence: In descriϋing this sequence, reference will be made to a relatively small matrix of cards and pins, i.e., one having 40 cards eacn card having 64 pins on test points. Tne first pin on tne first card will be called C-.P-. , tne Q- χ -?l first pin on tne second card will oe called C P I , The C l p l source switch is closed, i.e. C * j _P* j _ is our first "stimulus point". Thus C* j _p* j _ is logical test point numoer 1. In the following discussion logical numbers are in 5 parentheses following CP nu oers. All sense switches of the same pin vaiue on all cards greater than tne stimulus card are closed. Thus, all the sense switches corresponding to C 2 P* j _ tnrougn C^P-^ are closed. If a continuity existed between tne source point and any of 0 tne points wnose sense switcnes were closed (in this case, any otner points on the first level) , a nit signal would be channeled to tne sequencer (the PIC) and the detection of the nit sent on by tne PIC to the main CPU 200. In the case of all opens, there will oe no such hit 5 signal, ϊne next step, assuming no nit, is to turn off tne sense switcnes at tne first level ano go to the next level (tne next nignest pin numoer P 2 ); all sense switcnes at the next level are turned on (as opposed to tne case of tne level on wnicn tne source point was u located, in whicn case only tnose points on higher numoered cards than tnat of the source point are turned on) . If a nit signal is again not generated, switch off ail sense switcnes, and then turn on tne sense switcnes on tne next highest pin level. Continue this procedure 5 of successively turning on rows of sense switcnes until eitner a hit is detected or until all pins of ail cards beyond the source pin nave Deen tried. If no hit is detected, "0" is stored in tne register corresponding to tnat stimulus point. After completing the scan for the first hit for pin C 1 J? 1' a scan i* 3 performed for the first hit for pin C2P ] _. This is accomplished by turning off the source switch for C* j _p* j _ and turning on tne source switcn for C 2 Pτ_. We then turn on all sense switches to the right of card #2 (i.e. cy?ι 23 cards 3-40) on the same pin level, C3P-, through Q P-J_ and cneck for a hit. If there is no hit, turn off those sense switcnes C- j P-^ through C4 Q PJ_ and turn on all sense switcnes of all cards of the next nignest pin level C- j ^ through C 40 P 2 . Continue tnis process for each stimulus point until all points nave acted as a stimulus at least once and only once. This procedure continues until all test points nave Deεn utilized as stimulus points at least once and only once. Tne order in whicn the source switcn for eacn point is turned on is C-^p*, , C 2 P-^, . . . 40 p l' c l p 2' C 2 P 2 * • * C 40 P 2 * * * C 1 P 64 * * * C 40 P 64 * (Note tnat 4 Q P54 need not actually be used as a stimulus point Decause it is known tnat there will be no hit: tnere are no points aoove it to scan as sense points.) For further illustration, wnen pin C*P 25 is the source point tne scanning sequence is as follows: all sense switcnes at level 25 on cards 8-40 are turned on (not sense switcnes on cares 1-7); if no nit, tnen turn tnose sense switches off and turn on all sense switches on the next level, e.g. pins C* ] _P 26 througn C4 Q P 26 if still no nit, tnen go to tne next higner level; etc., until a nit or until all nigner pins have been tried. Wnen a nit is detected, an additional procedure is followed in order to determine whicn test point was responsiDle for tne nit. Because points on eacn of tne switcn cards are sensed simultaneously, wnen there is a hit, it is not immediately known which test point was responsiole for tne nit (or if more tnan one point at tnat pin level was responsible for the hit, what is the numoer of tne lowest point responsiDle for the hit) . Tnus, wnen a nit is detected, all of the sense switches are turned off, and the sense switches at the pin level at wnicn tne nit occurred are turned on one at a time (starting with the pin on the lowest numbered card being OMPI scanned) until a nit is again indicated, tnus determining the first card with a hit at tnat level. Tne following example illustrates the procedure followed when a hit has been detected at pin level 6. Turn off ail sense switcnes. Turn on tne sense switcn at C-^Pg. if a nit, then C* j _Pg is tne first hit, otnerwise turn off C* j _Pg and turn on tne sense switcn for C 2 Pg• If a nit, tnen C 2 g is tne first hit, otnerwise continue trying the sense switches at that level. Note that if in tnis example tne source point had been on level 6 (i.e. tnere was a nit in tne first level tried) then C-*p 6 would not nave been tried; ratner, tne first card tried would nave been tnat one immediately to tne right of tne card on which the source point was located. Tne process of learning is continued, closing tne next source switcn etc., until all (but tne last) of the test points nas been used as a source point and the test taDle is complete, that is, to say, until the apparatus nas learned the pattern to be stored in the main CPU and P inter/Operator Control memories. Tnis procedure results in the determination of tne first nit that corresponds to each test point. This is ail tnat is required for tne learning mode. This first hit information is all that is stored in the test table, and is ail tnat is needed for representation of tne reference pattern wnen Doards are tested for continuity faults. Tnis is information is stored as a taDle of numbers: tne position of each entry in tne taole corresponds to the logical numoer of tne source point for wnicn tne OWPI content of tnat entry is the logical number of the point wnicn is the first hit. A copy of tne test taDle for eacn of the test stations is stored in memory of the main CPU. A copy of tne test table for eacn particular test station is stored in tne memory 114 of tne processor 112 in the Operator/Control Panel for that test station. For tasting possioly faulty circuity boards tnis basic procedure is used. However, whenever the first hit detected does not correspond to tne first hit as recorded in tne learned test taDle, a fault exists and additional procedures are used. A Specific Example of Learning a Board: As an example we assume tnat tnree test points connected wnen tne circuit is on a test head are C P-,, •~40 p 2' and C1P3. Tnese correspond to logical test point numoers 4, 80, and 81 respectively and correspond to pnysicai test point numoers 193, 2493, and 3 respectively. In this example Fig. 6β shows a pnysicai realization of the continuity pattern. Fig. 11 indicates wnicn pins on switch cards are connected in tne continuity pattern, and Fig. 6A shows tne test table representing tnis continuity pattern. In tnis example, logical test point numbers are shown in par ntneses after tne corresponding card and pin numoers. Tne general test sequence is tne same as described above. C-^p^ (i) stimulus switcn is closed, and pin 1 of all cards have the sense switch closed. A continuity is not detected from pin 1 to any of the sense points, all sense switcnes are opened. Then, all sense switches for pin 2 of all cards are closed. No nit is detected. Thus a zero is placed in the first location in the test table. Tnis process is repeated for all pin levels above the pin level of the source signal. A zero is stored in register 1. iΛext, C 2 p, (2) source switcn is closed. All pin 1 sense switcn switches on all cards from C β ^ (3) through C. Q -, (40) are closed. The process previously descrioed - for C- j^ -^ (l) is repeated until eitner a hit is detected or all nigher numbered sense switcnes have been tried. In tnis case no hit is detected and a thus zero is placed in register 2 in the test taole. The same process is repeated for j p-^ (3) an a zero is stored in register 3. Tne same process is tnen repeated for C^p-, (4). However, wnen pin 2 of all cards is turned on a continuity is detected and a nit signal is generated. We nave determined tnat C,P-, (4) is connected to a pin 2 of some as yet unknown switch card. We want to determine tne lowest card numoer tnat generated tne nit signal. (Several cards could have generated a hit signal.) To determine the lowest card numoer, we open all sense switcnes ano close the sense switcnes for C-,P 2 (41). There will be no hit there in this example, tnus we continue oy turning off tne sense switch at C-,P 2 (41) and closing tne sense switcn at C 2 P 2 (42). Again there will De no nit. We continue tnis polling of tne individual switch cards until a hit signal is generated. A hit signal will oe generated when tne sense switch for ^40 p 2 ( & ) is closed. At tnis point an 80 is stored in location 4 in the test table. This process is continued. No hit will be detected until C 40 P 2 (80) is used as a source point. With C 40 P 2 (80) as a source point there will be a hit detected when OMPI tne sense switcnes for pin level 3 are closed. These switcnes will then be opened and tne switcn for C_l?2 (81) will oe closed. Tnere will be a hit at C-^P (81), so polling of the individual cards ends and 81 is stored in location 30 in tne test taole. Tnis process is continued until the test table of Fig. 6A is completed There will be no further hits; all remaining entries in the test taDle will tnus be filled witn zeros. Testing — Fault Identification In tne test mode tne pattern recorded in tne table of opens and continuities is compared to the results of tne actual measurements made on tne circuits being tested. Wnen tne two agree, no information is reported to tne rinter Operator Control processor 112 and memory 114. Wnen tnere is a discrepancy between wnat has been measured and what is recorded in the table, the raw information is reported. Raw information is supplied to tne microprocessor at the operator control panel. At the operator control panel tnis raw information is culled of redundnt information and translated sucn that only useful information is reported to the operator. Tne manner in wnicn the test points are actually switched during testing in which measurments are made is not dependent on tne general test pattern that is resident in tne CPU's RAM, or tne pattern learned at tne time. These points are switched according to the same general method during eacn test, wnich follows the basic sequencing pattern described above. It is only once a discrepancy between tne measured and learned continuity <& REA O PI_ patterns has oeen identified tnat tne test sequence differs from that used in learning (and described above). Tne test apparatus is. capaole of reporting multiple faults sucn as the following: more than one short to one test point; a test point tnat snows an open as well as one or more snorts. In test mode, any additional scanning that mignt be required (beyond that of tne basic scanning procedure) and tne reporting of faults depends on comparison Detween tne numoer of tne first hit actually measured and tne numoer that tne first nit snould be as recorded in tne test taoie. (dote tnat this "reporting" of faults is not reporting to the operator; ratner, this raw fault information is passed to tne Operator/Control processor wnicn will furtner process it and remove redundancies Defore reporting it to the operator of the tester.) If tne measured number is equal to tne expected number (as indicated in the test table), then there is no fault to report from tnis hit, and no furtner scanning witn tne existing source point is required. The test procedure tnen moves on to tne next point to oe used as a source point. If tne measured numoer is less tnan the expected number, tnen a short is reported from the source point to the point responsible for tne nit. in addtion, keeping the same source point, scanning is continued in search of the next hit. Depending on how the next hit number compares (equal to, less than, greater than) with tne number stored in tne table for the existing source point, a furtner fault may or may not be reported and scanning may or may not continue yet again using the same -source point. If tne measured number is greater than tne expected numoer, then it must be further determined wnetner tne measured numoer is "lin ed" to tne expected number. It is a feature of tne scanning sequence of the present invention that points which are connected together form a linked list in tne test taole. Tnus it is easy to determine from tne test table the logical numbers of all test points to wnicn a given point should be connected. Tnis can be seen in the test table of Fig. 6A: as indicated by location 4, point 4 * is connected to point άύ i looking in location 80, we see tnat point 80 is furtner connected to point 81; thus point 4 is also connected to point 31. Tnis "lin ing" means that tne contents of one register of the taole can be used as a pointer or address to another address which has as its contents the numoer of anotner connected point. To determine whetner the measured number is linked to the expected numoer, one looks at the contents of the location pointed to by the expected number. If tnis is equal to the measured number, then the number is linked. If it is less, tnen one uses tnat numoer as a pointer an compares the number in tne location pointed to by it. Tnis process continues until a number equal to the measured number is found, in wnicn case there is a link, or a number greater than the measured number is found, in wnicn case tnere is no link. If the measured number is greater tnan the expected numoer and tne measured number is linked to the expected numoer, then tnere is no fault to report from tnis hit, and no further scanning with the existing source point is performed. " V If tne measured numoer is greater than the expected numoer and the measured numoer is not linked to tne expected numoer, tnen a snort is reported and scanning is continued for the next hit. To test a circuit to see if it has the same continuity pattern as the pattern tnat was learned, the circuit to be tested is placed on the machine and the macnine is placed in tne test mode. The macnine tests for a pattern in tne same fashion that a pattern is learned. Wnen a hit is detected for a given source point the numoer of the sense point tnat caused the nit is determined and compared to tne contents of the register tnat is associated witn tne source point. If the numoers are equal, then there is no fault to report. If the hit point is different from tne value contained in the register, it is compared to the expected value; the specific procedure followed in response to detection of a fault depends on wnetner tne hit is less than or greater tnan tnat indicated in the table. A Testing Example Showing Detection of a SHORT: Aitnougn tnere are typically 128 pins are on a given switcn card and tnere are 80 such switch cards in tne switcn array, in tne description oelow, to simplify matters, we discuss a situation wnerein tnere are 64 pins per switcn card and tnere are 40 switcn cards total. Given tne continuity pattern that should exist as shown in Fig. 7B, its the learned table in Fig. 7A, we can tnen examine now it tests a pattern that is shown in Fig. 7C and wnere the interconnected points are indicated m Fig. 12. "BU EA O PI The test sequence starts tne same as the learn mode. The source switch of pin 1 of Card one is closed, and all sense switcnes of cards of pin levels greater than the source pin are stepped through, no hit is detected so the 5 resulting value is zero. This value is compared to learned value in register 1. The two values are equal. Tnus, a.fault is not reported to the operator control panei. The same process is repeated for C p-^, C P-^, etc. However, wnen tne C4P-, source switcn is closed, and when 10 all sense switcnes at pin level 1 on cards greater than card four are closed, a nit signal is generated. In order to determine wnicn card and pin caused the hit (snort fault in this case) all sense switcnes are opened and CeP-, sense switcn is closed. Mo hit is 3.5 generated, Next Cgp*-*_ sense switcn is closed. A hit signal is generated. Tne logical test point value of tnis point is 6. This is compared to tne contents of the learned register value of logical test point 4 (see the test table in Figure 7A); register 4 contains the value 20 of 80. Six is less tnan 80, tnus a snort from test point 4 to test point 6 is reported to tne operator control panel. The main CPU directs the sequencer to continue tne scan; tne scan continues beginning with closing sense switches greater than the sense switch tnat detected tne 25 fault. There are no more hits on tnat pin level. At the next pin level all sense switches on all boards are closed. A hit is detected. Next, one sense switch on pin level 2 is closed one at a time, from C-.P 2 onward, until the board that caused the hit is determined. (See 30 Figure 12) Tne circled X indicates the test point tnat caused tne nit signal to be generated. Its logical value is 80 ( C 4g 2 ) / this value is compared to tne value in the register for logical test point 4 (tne source point); the two values are equal, and the test sequence associated with the source test point 4, is complete. The test sequence continues by using test point 5 as a source point. No hit is detected. Tne value zero is compared to tne contents of register 5 in the test table (Fig. 7A). Tne two values match, no fault is reported. Test point 6 source switcn is closed and sense switcnes at pin level 1 on all boards greater than the source ooard (board 6) are closeα. A no hit signal is generated. Ali sense switcnes are closed on pin level 2. A nit signal is generated. To find wnere it is eacn sense switch on pin level 2 is closed one at a time until a nit is detected. A hit is detected on pin 2 of board 40. This is logical test point 80. This numoer is greater than tne 0 stored in location 6. Tne 80 is not linked to tne expected value, because the expected value is 0, and nothing is linked to 0. A short is reported oetween 6 and 30 ano scanning continues. Anotner hit is detected on pin level 3 at point 81. This is also reported as a snort. Scanning continues, Dut no further nits are detected wnile using point 6 as a source point. A zero is finally reported and this is equal to the contents of register 6; tnus no furtner faults are reported for test point 6. The test process is continued for test points 7 to 79, no continuities are detected and the value in each of tne registers is equal to zero. No faults are reported. Test point 80 is found to have a nit. It is determined that test point 81 has caused the hit. The contents of register 80 is equal to 81. No fault is reported. Tne remainder of the test points act as source points, and no continuities are detected. The contents of these registers are equal to zero so no additional faults are reported. A Testing Example Showing Detection of an OPEN: Given tne continuity pattern that snould exist as snown in Fig. 83, its tne learned table in Fig. 8A, we can then examine how it tests a pattern that is snown in Fig. 8C and wnere tne interconnected points are indicated in Fig. 13. Tne test sequence is tne same as previously outlined for tne detection of a snort: Tne first pin on Card one is stimulated, i.e., the source switcn of C- . P,, is closed and all "pin 1" sense switches on all cards greater than tne source card are closed. A nit is not detected. Succeeding pin levels are also scanned, and no hit is detected. Tne resulting value is zero, tnis is compared to tne contents of register 1 (see Fig. 8A) . The two values are equal, no fault is reported. Tne same procedure is followed for C^-^ a nd C P^. T e source switcn for C 4 P 1 i s closed. The sense switcnes for all pin l's of all cards greater than tne source card are closed, no hit is detected. Next, all sense switcnes for ail cards are closed for tne next highest pin level. (all P 2 s) No hit is generated (because tnere is an open type fault at pin 80). Tnen, a l sense switcnes of tne next nignest pin level, (all P3S) are closed; a nit is generated. Closing the sense switcnes at tne P 3 level of each card, one at a time, determines that card 1 generated the hit signal, logical test point 81. Tne contents of register 4 are compared to tne logical test point value of 81. The value in the register is 80, 81 is greater than 80. An open is reported to the operator control panel from test point 4 to test point 80. Next, the contents of register 80 (the expected value) is compared to the value of 81. If the two are equal, no additional faults are reported. However, if tne two were not equal, a snort would be reported if the contents of tne expected value was greater than tne detected value. The test sequence would continue until tne detected value matched a value that was pointed to by the contents of the registers associated witn test point 4, or until all sense switcnes were closed in the usual sequence and a no hit condition was determined. Any mismatcn otner than tne no nit would oe reported as a snort to test point 4. The test sequence for card four pin 1 is complete. Tne test sequence is continued for eacn logical test point as previously outlined. All the otner points up to 79 are "no nit" tests wnose corresponding register contain zero so no fault is reported. Tne source switch for test point 80 is closed and all sense switches are sequentially closed as they would for a no hit condition. At tne end of tne sequence a no hit condition is determined. However, tne contents or register 80 is equal to 81, an open is reported from 80 to 81. No further comparison is to be done because a no nit condition exists. The source switch and sense switcn sequencing continues as previously outlined. All otner test points nave a no-hit condition. Tne contents of tne -^JRE- OMPI corresponding registers are equal to zero, so that no additional faults are reported. It is to oe understood tnat other orders of testing procedures are operable. However, it is believed that wnen a great many points are Deing tested in a given circuit, otner procedures would not present the testing data to tne operator test station data processing apparatus in sucn a way as would enable such facile removal of redundant data. Thus, relatively more data processing equipment would be required. Otner basic test sequences could be used. In particular, using tne matrix model described aoove for switcn cards and pins, a vertical ratner than norizontal sequencing system could De used; a horizontal stimuli and vertical sensing system is used; a vertical stimuli and norizontal sensing system is used. However, sucn alternative testing sequence would not minimize tne amount of circuitry required for each switch card in tne way tnat scanning a level at a time does (as opposed to card at a time) . If sensing is done 1 card at a time, tnen it is necessary to design switch cards capaole of sensing at multiple points at one time; furtner, switch cards would nave to be able to turn on all sense switches aoove a certain level (i.e. when the source point is on the same card) and not turn on the sense switches at and below that level. Sensing in groups where the groups are all pins on one level results in simpler decoding circuitry for the switch cards; this approacn keeps the decoding circuitry on all cards working all tne time, rather than sitting idle while only -l one of tne switcn cards is working; tnus each switcn card need have less decoding circuitry. Removal of Redundant Information All detected open-type faults are reported. Shorts are checked for redundancy: if there is a snort between a pair of test points, tnen other test points connected to one of the 2 test points will show snorts to all of tne test points connected to tne otner of the 2 test points. Tne duplicate entires pertaining to eacn test operation are removed at eacn the operator control panel by maintaining two "tables" in its memory. The first is a copy of tne test taole wnicn was learned. The second is a table of all non-redundant fault information tnat is reported on a given test up to tne current point in tne test. Wnen a fault is reported to the main CPU all otner faults in the fault table are used to examine the test taole. If an already reported fault is lin ed (as determined oy examination of the table of reported faults and the test taole) to the new fault, tne newly reported fault is not printed. However, if tne newly reported faults proves not to be linked to already existing faults in tne fault taole, sucn information is added to tne fault table and tne new fault is reported. The test taole is retained as long as boards of the type of the "learned" Doard are tested. The fault taDle is cleared everytime a new board is presented for test. The order in wnicn data ' is acquired in conjunction witn the way in which the data is stored in memory greatly speeds the removal of redundant information. Tne recording and printing of a fault is a two step process as each fault is recognized by the sequencer and OMPI main CPU. Tne information is sent to tne appropriate printer/operator control board (POCB) via the I/O control ooard. The "POCB" has tne same test taole as the one stored in the main CPU memory. The fault data as well as tne test taole is used to select the information that is to oe printed. This is necessary because the main CPU sequence provides complete but duplicate information. In the aoove example of testing and detection of a short, it was shown that shorts would be detected between points 4 and 6, points 6 and 80, and points 6 and 81. Tne operator/control panel processor would print the first of these (tne short between points 4 and 6). However, tne otner snorts would be found to be redundant. This is determined σecause points 6 and 80 are Doth eitner found in the taDle of already reported faults, or linked to points in tne fault taole. Likewise, points 6 and 81 are eitner Doth in the fault taDle or linked tnrougn tne test table to points in tne fault table. This is determined as follows. Point 6 already exists in tne fault taole. There would σe a entry in tne fault taole indicating a snort between points 4 and 6. Tnus tne test table is examined for links to point 4. The test taole (see Fig. 7A) shows that point 4 is linked to point 80, which is itself linked to point 81. Tnus the otner points involved in the reported snorts, points 80 and 81, are linked to already reported faults. Since ootn 6 and 80 and both 6 and 81 are either in or linked to tne fault taDle, tnese faults (6 to 80 and 6 to 81) are considered to be redundant faults, and are not printed or otnerwise reported to tne operator. Distribution of Tasks The various tasks performed by the tester are distributed among various pieces of hardware. This contributes to tne speed witn wnicn tne tester operates. Tne main CPU 200 controls the overall operation of tne tester, determining wnicn test station is actively testing at any time, controlling the scanning procedure at a nign level. In directing the testing of a board, the main CPU directs the PIC, while the PIC then directs tne switcn cards to close specific switches. An feature of this tester is the cooperaton of the CPU with the sequencer. The sequencer is microprogrammed to rapidly perform a switcning sequence. However, wnen the sequencer's capaoilities are best superceded, the CPU steps in and redirects tne sequencer. This redirection of sequencing activity takes place wnen, during the testing of a circuit Doard, a fault is detected. Tne Operator/Control Panel accepts input from tne test station operator, prints fault reports for the operator, and processes tne raw fault information into a usaoie form. There is also an additional processor whicn keeps overall statistics on tester operation. This is indicateα in Fig. 2 as the "domain processor". Switch Cards: Eacn switcn card nas means for channeling sensed signals to the PIC. By detecting this sensed current, tne PIC can determine if there has been a "hit", i.e. if OMPI tnere is continuity between tne present source point and the present sense point (or at least one of the present sense points if tne PIC has commanded xnore tnan one sense switcn be closed) . Switcn card close switcnes in response to commands received from tne PIC on a control bus in tne switcn card -backplane. Only one source switch is closed at one time. Wnen a command directing tne closing of a source switch is placed on this control bus, each switch card determines wnetner tne indicated switcn is on tnat card. More tnan one sense switcn may oe clcsed at once, altnough individual switch cards can close only one at a time. Switch card sense switcnes respond to tnree commands directing tne closing of sense switches: "greater than" command, an "equal" command, and an "all" command. Wnen the "equal" command is given, then the only sense switch closed is the sense switch on the switcn card wnose numoer equais the indicated card numoer (tne switcn on that card which is closed is the one at tne pin level indicated in tne command) . Wnen tne "greater tnan" command is given, all cards with numbers greater than tne indicated number close sense switches. Tne "all" command instructs all switcn cards to close sense switches; each switcn card closes one sense switch at tne pin level indicated in tne command. Tne "greater tnan" command is used in the basic scanning sequence to close groups of switcnes (all sense switches at the same pin level as tne source switcn. The "all" command is used to close groups of sense switches at levels higher tnan tnat on wnicn the source switch is located. The "equal" command is used after a hit has been detected to poll the switch cards to determine which is the lowest numoered card with a hit. Requiring that switcn cards only be able to ' close one switch at a time greatly simplifies the circuitry wnicn must be contained on each switcn card as compared with a tester in wnich the switch cards had to be capable of closing groups of switcnes. Furtner the savings over a system in which switcn cards must be able to close aroitrary sets of switcnes is enormous. It is a feature of tnis tester that it acnieves both tne speed that results from sensing groups of test points at a time, out also acnieves the economy resulting from reduced circuitry requirements for tne switcn cards. Point Interface Card (PIC): Tne PIC is a state macnine designed to stimulate a test point and seen a hit. Aitnougn tne main CPU controls tne overall sequencing, tne PIC controls the details. Tne PIC is capable of being given a source point board and pin and a point numoer from wnicn scanning snould oegin (generally exactly 1 greater than the source point number, except after a fault nas been detected, in wnicn case tnere may oe a searcn for additional hits) and scanning until a nit is detected. It then reports to the main CPU the board ano pin numoer of the point with the lowest logical number in the scan for which there was a hit. The main CPU compares tnis information with that in tne test table and directs the PIC to perform tne next scan. Tne sequencing apparatus (Figs. 9 & 10) has a high¬ speed sequencer utilizing a Mealey-Moore machine and nign-speed TTL (Transister transistor logic) buffers and latcner. Dipolar programmable read-only memories (PROMs) witn a propagation delay of 15 nanoseconds. Mealey- Moore macnines are known in the computing art as-tne components used therein and the technology by which said components are assembled to achieve high-speed sequencing. In general, tne sequencer is a multiple state machine wnicn goes from one state to anotner depending on what its state is at any time and what stimuli it receives. It is driven Dy a system clock, at say 0.5 or even a 1.0 MHz. Tnere are actually two similar sequencers on the PIC: a board sequencer and a pin sequencer. The board and pin sequencers are operated simultaneously. A particularly unique feature increases tne speed of the system. The sequencers are set up with a starting address (decoded to board and pin) and a PROM whicn contains current address plus 1. Tnis allows the sequencer to oe ready to clock the next address at the very next pin latch or board latcn signal. Tnis will not occur, however, if the board latch or pin latch or hit nave occurred. Either of tne aoove conditions will cause tn clocks to stop and the microprocessor to read tne address of the Board and Pin Sequencers. The sequencer are tnen preloaded and tne process continues. Tne functions performed by tne PIC are the extended addressing procedure; generating pin and board limit signals Dy sequencers; timing functions using pin and ooard clocx circuits which have various speed settings varying in, e.g., two microsecond steps. The board also contains status registers which are available to the microprocessor to be read. Also included on this board is tne DAC, whicn is programmaole, which sets up the excitation voltage used for stimulating the ooard under test. Tnis circuitry also contains tne super hit sensor circuitry. The functions that are defined above are descrioed below. Tne extended addressing is used to generate board select wnicn in turn is decoded into tne various control states used Dy tne remainder of the logic. Tne pin and ooard sequencer are loaded witn starting address from 1 to 128. The sequencer then runs until it hits a pin or board limit or until it sees a hit signal. A nit is defined as a connection between tne points enaoled σy the Doard and pin sequencers. The pin and Doard sequencer essentially work in suostantially similar ways. Looking at U23 and U24 in Fig. 10D, tne current pin address is generated at tne output side or U23 (tnese are TTL levels) and is translated into CMOS levels. Tne 75365s convert tne TTL 5-volt input into a 12-volt output. U24 is a PROM which is programmed always to contain the next address so tnat the current address is fed into its input side (AO thru A7) , and it translates the input address into tne next output address and it outputs tne D-D7 which are connected to the inputs of the latch U23. The latch is controlled oy tne pin clock or board clock in tne case of tne board operations U39 and U41. The clock signal is generated from the buffered E-Clock wnich is snown at U26. U26 need not actually oe used (it would provide a divide by two) out the alternate system, the jumper shown as a megahertz is installed and U2ό is left out. U29 and U30 form a down counter which when the count of zero is reacned, automatically reload tne starting count and continue tne clock sequence. Asssuming tnat 43 tne pin sequencer is running, tnen a pin start common will have been issued to U39 pin 1 which takes U41 out of tne present condition and allows it to repsond to the clock pulses at its input derived from U40 pin 3. These clock pulses are inverted in U42, 9 and 10 and gated with pin limit at U42 pin 13. Assuming that tne pin sequencer clock is running clock pulses at the rate specified by tne speed command at pin latcn, U29 pin 3 and also U23 pin 11 causing the LS374 latch to set up the next address previously estaolisned at tne output of U24. Tnis next address is tnen sent out to tne input points 0-7 through the 75365 Duffers and go to the input of U24 so that the next address is oeing estaolisned. The next address is simply set up by programming U24 with the desired address sequences. Wnen pin limit is reacned, (tnis happens when all 8 outputs from U24 go high) , tne output of U49 pin 8 will go low, signifying pin limit. Tne condition of pin limit causes the pin latch pulses to stop, this is done via U42, 13. The microprocessor is also signaled tnat pin limit nas occurred via U23. The system then simply waits for tne microprocessor to set up a new set of pin and/or ooard addresses, making use of the pin set and board set commands. Any time tnat a hit occurs U50 pin 8 will go high causing the two clock counters, U29 nd U30, to cease counting so tnat tne current pin and board addresses are frozen. The hit command also is sent out to the microprocessor at U23 to signal it that a short has Deen found and that tne appropriate board and pin addresses should oe read to establish whether the point is legal. G ?I - -.- The analog system excitation level is established by the digital-to-analog converter (DAC) U15 (Fig. 9B) , this is a voltage output DAC. Its output is buffered by U2 and used to drive excitation high to tne analog voltage specified as stimulus on the menu. Tne DAC is an eignt bit DAC so tne range of stimulus (the excitation-high signal) can De set over 0 to 225 steps and covers a voltage range from 0 to 10 volts. (Tne steps are conveniently aoout 40 millivolts per number input to the DAC) . Tne excitation nigh signal from tne DAC ( the stimulus signal to the test point cards) includes "super nit". Tne function of super nit is to detect those errors that might oe missed due to bus type problems wnere a multitude of snorts could appear causing loss of normal excitation voltage. Super nit works oy monitoring tne current in the excitation high signal. Any time that tne current exceeds tne amount of current tnat would flow from approximately 10 Ohm hits a comparator Ul (which is tied in parallel witn the hit line) pulis tne signal to the nit line low.wnetner or not any of the switcn cards senses a hit. Tne microprocessor does not distinguish between a nit caused by super hit or one caused oy one of the switcn cards. When a nit occurs tne pin and board sequencer clocks stop, tne microprocessor is notified and it searches out the location of the hit as it would for any hit. Two separate hit levels are provided for, one in a two-wire case and one in a four-wire case. The necessary switcning of signals is done in U14. Swl informs the microprocessor of tne numoer of boards that are currently active in the system via U9, which is read as tne Swl memory locaton. Wnen the microprocessor reads f OMP tnis address, it is given a Dinary representation of the number of switch cards in the system. The output board and pin addresses are set up in U21 and U22. which appear to the microprocessor simply as memory addresses. Wnen written to, tney-establish the two eight bit addresses for tne output board and output pin. Tne system operating modes which are two-wire, four-wire, and ALL, Equals, or Greater Tnan mode are establisned tnrough the ooard control command via U20. The appropriate memory word is simply written to the Doard control address and U20 latcnes tne values. Tne initial pin and ooard addresses are set up tnrougn the pin set and board set command respectively. A pin set is used at U27 pin 13, tne pin set is an active low signal and wnen it goes low U29 pm 3 goes low causing tne pin latcn at U23 to go low. However, tnis latcn is active on the positive edge of clock so nothing nappens at tnis point. Wnen the pin set goes low the pin write enable signal goes active causing U36 to pass the data DUSS data into the inputs to the latcn. Tne prom J24 will have Deen disaoled σy tne pin prom enaDle signal at U24 pin 15. At this point pin set returns high causing pin latcn to go high wnicn in turn causes U23 to latcn tne input data derived from the data bus as opposed to tne normal route of data wnich it gets from 024. This sets up tne initial pin addresss, a similar operation sets up tne board address at 021 and 022. Once these addresses have Deen set, a pin start at 039 pin 1 or board start 039 pin 13 causing either the pin or the ooard sequencer to function. Variations Software Masking and Universal Matrix Fixtures: A test apparatus built according to tne present invention will in general have a greater number of test prooes tnan there will be test points on any particular circuit Doard. Tne test time can oe reduced if test prooes in the test apparatus which do not connect to test points on tne circuit under test can De eliminated from the test sequence, i.e. there is no point in using these as source points. Tnis elimination of certain possible test points from tne test sequence is called software masking. In tne currently most common arrangement of this type of test apparatus, a test fixture is wired especially for eacn type of circuit board to be tested. Sucn a custom fixture is provided with test prooes corresponding to the locations of test points on the circuit ooard. Tnese test prooes are wired to as to be connected to switcn cards, filling one switch card, filling tne next, and so fortn. With tnese custom fixtures one need only indicate to the tester tne numoer of switcn cards wired to the particular test fixture in use, and tne tester will then know wnicn switcnes are connected to test points (except for some on the last card used) . An approacn different from tnis custom fixturing approach is tne use of a unversal matrix fixture. The universal test matrix is a type of fixture which has test probes positioned in a square grid pattern with a spacing of, for example, 0.01 inch. Circuit boards that are designed so tnat all test points are positioned on such a O PI grid can tnen use the same test fixture; for these boards the substantial cost of wiring a custom fixture can be eliminated. However, unlike custom wired fixtures, the test points actully used on any given circuit board will not correspond to a limited group of switcn cards. Without software masking, ali test probes in the matrix would need to be used as source points. Tne proolem witn using software masking in conjunction with a universal matrix fixture is communicating to tne software tne identifications of the test prooes actually used for each type of circuit board to oe tested. This problem can όe solved by the use of a snorting plate. 4-Wire Testing: 4-wire capaoility is more important witn the testing of loaded ooards, rather than oare ooards. Bare boards contain metallic circuit connections, but do not yet contain any electronic components. Loaded boards nave components installed on them. Distinguishing between current flow due to snorts and current flow due only to tne installed components requires more precise impedance measurement than is needed for the testing of bare boards. 4-wire testing eliminates innaccuracy in sensing due to the impedance of the semiconductor switches that are used to connect test points to source and sensing circuitry, witn "4-wire" capability, single wires still run to each of tne test points, but there are four switches for eacn test point, ratner than two: source voltage; source voltage return; sense; sense return. In a 2-wire system, source and sense circuits snare the same switcnes. Addition of a Priority Chain to the Switch Cards? Some logic can oe added to each of tne switch cards and the switcn card backplane can be modified so as to allow automatic identification of tne first card witn a hit on a given level. The modification to tne switch cares and tne backplane results in tne formation of a priority cnain for the switcn cards. Thus if a card detects a nit, tnat card can, by use of the priority cnain, determine whether it is the lowest numbered card witn a nit. Witn tnis modification, once tne level is determined during a scan, tne lowest numbered switcn card with a hit can identify itself to the PIC; this eliminates tne need for polling tne individual cards. AutoLearn: Anotner feature tnat can oe used in conjunction with the aoove-oescrioed tester is an aoility to automatically determine tne maximum sequencing speed at which a particular type of board can oe tested. Due to capacitance of tne board to De tested and tne tester itself, tnere is a settling time required between sensing from a new set of sense switcnes. To perform the autolearn function, a circuit board of the type to be tested is installed in the test fixture and a series of learn-type procedures are run on that board. These procedures are performed at various sequencing rates. Tne test taoles resulting from tests performed at low rates will be identical. However, at rates above which tne board can reliady be tested, the test tables give erratic results. By performing test runs at various rates and examining tne resulting test t ' aσles, the optimum test rate can be determined. __ C ?I Augmented PIC Capabilities: The PIC might be microcoded to make it able to perform the entire test sequence, rather than just a single scan. This can reduce the time for an overall test sequence. Additionally this shifts some processing load from the control CPU to the PIC, freeing the control CPU to spend more processing time on other tasks. Further, the PIC might be microcoded to be capable of adjusting test parameters for each individual source point; for example, some source points may have to be tested at lower rates than others. In Conclusion From the above it will be seen that we have described a circuit board tester with several advantageous features. In addition to the advantages obtained from the individual features, these features combine to make "multiwell" testing possible. A multiwell tester provides the capacity of several testers at a fraction of the cost. Matrix cards and mechanical multiplexing provide the means for economically meeting the physical and electrical constraints imposed on the designer of a multiwell tester. Matrix cards provide parallel connection of test probes from several test stations to one set. of switch cards. This enables several test stations to share a single set of test circuitry in such a way that one board can be tested at one test station while other boards are loaded and unloaded at other test stations. This parallel connection is accomplished despite the enormous bulk of cabling that must converge on and be connected to the switch cards if such parallel connection is to be achieved. In addition, means is provided for mechanically multiplexing the circuit boards to be tested so that a board at only one test station at a time is electrically connected to the common set of switch cards. This method of electrically isolating the several test stations of the tester makes multiwell testing economical; the achievement of parallel connection through the use of matrix cards makes it physically practical to connect more than one test station to a tester. The tester also utilizes particularly efficient testing procedures. The choice of testing procedures enables the tester to perform tests with sufficient speed to make practical the sharing of one set of switch cards among several test stations. In order for a multiwell tester to be useful, test speed must be sufficient that the tester is available for testing a board at each test station as soon as the board has been loaded in place of the previous board. The tester also utilizes particularly economical switch cards. Each switch card need have only a minimum amount of decoding circuitry. This is made possible by the advantageous choice of certain aspects of the testing procedure. The testing procedure also provides data in a form which is particularly well adapted for further processing. The combination of storing first hits in conjunction with the scanning of only those test points above the source point results in a linked list of electrical continuity data. What we claim is:

Claims: CLAIMS 1. A tester for testing selected test points on printed circuit boards, comprising: means for applying electrical test signals to selected test points on a circuit board and measuring the electrical response thereto, means for ordering the test points in a defined sequence, means for sequencing the application of test signals to successive test points, and means for sequencing the sensing of a signal at test points subsequent to the point at which a signal is applied until a first response signal is found. 2. A tester as claimed in claim 1 wherein said sense sequencing means is operative to sense simultaneously at groups of test points, said ordering means comprises a series of switch cards, a set of test points being associated with each switch card, and wherein each of said groups includes no more than one test point from each of said switch cards. 3. A tester as claimed in claim 1 wherein the ordering means orders test points in a matrix form, said matrix having rows and columns, and wherein ^3R£A OMPI V/UrO one switch card is associated with each column of the matrix. 4. A tester as claimed in claim 3 wherein at most one switch on each switch card is closed at any time. 5. A tester as claimed in claim 3 wherein the sense sequencing means is operative to sense simultaneously those tests points in the same row as the stimulus point which are above the stimulus point, and to sense simultaneously all test points in a row for those rows above the row with the stimulus point. 6. Apparatus for testing circuit boards at a plurality of test points, said testing apparatus comprising: a set of switches, at least 2 sets of test probes means for electrically connecting in parallel corresponding ones of the test probes from one set of test probes with corresponding ones of the test probes from another set of test probes, and further connecting these parallel connected test probes to corresponding switches of the set of switches, a contact control means associated with each set of test probes, each of said contact control means O PI being adapted to control the relative position of a circuit board to be tested and the set of test probes, so as to control electrical contact between the circuit board and the test probes, and thereby be capable of electrically isolating one of the sets of test probes from circuit boards to be tested at another set of test probes. 7. Apparatus as in claim 6 wherein said contact control means comprises: means for mounting a board for testing while maintaining said board out of contact with said probes, and means for selectively bringing said board into contact with said probes for testing. 8. Apparatus as in claim 7 wherein said means for electrically connecting in parallel comprises a set of matrix cards, each of said matrix cards comprising a printed circuit card having a set of connections at one edge connected to the set of switches, and sets of connections on at least 2 other edges, each connected to a set of test probes. 9. Apparatus as in claim 8 wherein said matrix cards have conductors on one face of the cards connecting to switches, conductors on the other face of the cards connecting to test probes, and wherein these two .sets of conductors are interconnected by plated-though holes. 10. Apparatus as in claim 9 wherein the connections from the sets of test probes to the matrix cards comprise cables terminating in connectors which attach to edges of the matrix cards, and wherein said plated-through holes are arranged along two lines which run diagonally across said conductors, whereby the resulting orientation of the connectors minimizes twists in the cables.

Inventors: DECARLO JOHN M, INGRAM GEORGE S, WATSON LEROY P, DECARLO, JOHN, M., INGRAM, GEORGE, S., WATSON, LEROY, P.
Applicants: EQUIPMENT SALES COMPANY INC, EQUIPMENT SALES COMPANY, INC.
Application year: 1983
Main classification: G06F15
IPC codes: G01R31, G06F11