VIRTUAL MEMORY ADDRESSING SYSTEM AND METHOD

Abstract: A virtual memory addresing system utilizing a paging substitution scheme, includes a processor (40) which provides a virtual address on a memory bus (44) together with a first control signal (PVT) which causes an address translator (42) to commence address translation. The virtual address is also provided to a memory interface unit (48) which causes the lower order address bits to be provided to the memory unit (50) whereby the memory addressing operation can commence. Upon completion of address translation, a second control signal (MAE) causes the translated real address to be latched into the memory interface unit (48) whereby the addressing operation of the memory unit (50) can be completed. The invention enables high speed virtual memory addressing to be achieved.

Description: VIRTUAL MEMORY ADDRESSING SYSTEM AND METHOD Technical Field This invention relates to memory addressing systems of the kind including memory means adapted to contain stored data arranged in pages, processor means adapted to provide virtual addresses, and address translation means. The invention also relates to a virtual memory addressing method. Background Art Many current medium to large scale computer systems utilize a virtual memory concept to maximize the efficiency of the single most expensive component in the processing unit, the memory storage element. Generally, for performance reasons, at least some part of the storage element is implemented using semiconductor memory chips. Currently, the most popular memory chips are the dynamic random access memories, DRAM's, since they afford high densities (up to 65,536 bits per chip), good performance and they are reasonably priced compared to other technologies. The amount of physical memory provided in an actual system will be restricted due to cost, power, packaging and/or other considerations. Virtual memory storage allows software programs to be written and executed on a system using an address space that is greater than the actual physically address¬ able memory used in the system. This is possible because additional memory (slower speed) is provided by way of disc storage, tape, cards, etc. The additional or bulk storage memory, stores pages of information which can be transferred when needed into the computer's higher speed memory to effectively increase the working size of the computer's memory. Memory management resources map sections of a user's program in groups of bytes (3 bits), often O PI vn. } referred to as pages, into the physical memory as re¬ quired. Once the page is in memory, the data on that page can be accessed provided that some element within the processor can remember the mapping function between the virtual address and the real (physical) memory address. For performance reasons, the mapping function is most frequently implemented in hardware. The time utilized to effect this mapping, or address translation operation as it is also known, can result in the total memory access time being extended by as much as half of the time it would otherwise take to access memory in a non-translation mode. In conventional hardware imple¬ mentations memory access time using address translation would be calculated by summing the amount of time it takes to convert a virtual address to a real address with the amount of time it takes to perform the actual memory operation. A memory addressing system of the kind speci¬ fied is known from U. S. Patent Specification No. 3,902,164. According to this known system an additional register is used to hold a representation of a boundary in the main store below which virtual and real addresses are equal, so that translation is not required. A comparator compares each input address with the contents of the additional register and if the input address is less than the boundary value AND gating means are acti¬ vated to transfer the input address directly to a storage address register, inhibit gating means being rendered effective to prevent the output of the address translator being entered in the storage address register. If the comparison indicates that the input address is greater or equal to the boundary address, the AND gating means and inhibit gating means are not activated and the output of the address translator is applied to the storage address * register via the non-activated inhibit gating means. If under these conditions no match is v V.E OMPI detected by the address translator, a further AND gate is effective to cause the data processing unit to address a stored virtual address segment and page table to deter¬ mine the actual location specified by the input address. Although the known system improves address translation speed the use of inhibit gating means for the output of the address translator does have the disadvan¬ tage of introducing some delay. Furthermore, the utilization of an additional register for the boundary value and a comparator has the further disadvantage of adding to the cost and complexity of the known system. Disclosure of the Invention It is an object of the present invention to provide a memory addressing system of the kind specified wherein the aforementioned disadvantages are alleviated. Therefore, according to one aspect of the present invention, there is provided a memory addressing system of the kind specified, characterized in that said memory means, said processor means and said address translation means are coupled to a memory bus and in that said memory means includes memory interface means and an addressable memory unit, whereby in operation each virtual address is supplied from said processor means to said memory bus, such that said address trans- lation means is effective to translate the virtual address to a real address, each such virtual address including a group of virtual address bits which corre¬ spond to a group of real address bits of the corresponding read address and which are supplied from said memory bus to said memory interface means such that said group of virtual address bits commence to address said memory unit. According to another aspect of the present invention, there is provided a virtual memory addressing method for addressing a memory having pages of data stored therein, including the steps of providing a virtual address and commencing translation of the vir¬ tual address into a real address, characterized by the steps of commencing access of said memory using untrans¬ lated lower order virtual address bits and completing access of said memory utilizing the translated higher order address bits. It should be understood that the present inven¬ tion is based upon the recognition that in a page substitution scheme only the first several bits of the virtual address are necessary to identify the location of a page of data within real memory. The relative position of each element in a page of data remains the same whether the address is virtual or real. Such being the case, translation is complete when that portion of the virtual address that is not identical to the real address is translated (mapped) into its corresponding real address and time savings can be had by commencing memory access before all of the real address bits are available. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a group of waveforms depicting the time required to perform a virtual memory operation in the prior art; Fig. 2 is a group of waveforms depicting the time required to perform a virtual memory operation utilizing the present invention; Fig. 3 illustrates the correspondence between a page of data in virtual address space and in real address space; Fig. 4 illustrates in block diagram form a typical virtual address system; Fig. 5 illustrates in block diagram form a typical memory arrangement for providing dynamic real memory storage; O ?Γ ' " Fig. 6 illustrates in logic block diagram form the preferred logic implementation for the present invention; and Fig. 7 illustrates a plurality of waveforms indicative of an operation cycle of the present in¬ vention. Best Mode for Carrying Out the Invention In Fig. 1 there is shown a timing diagram for a standard memory operation in a processing system utilizing virtual address translation. As the processor enters cycle 1, the virtual address is being translated bit by bit into the corresponding real address. At the start of processor cycle 2, the translated virtual address is available as a real address and the memory access cycle commences. The access cycle may be for purposes of reading or writing. The total memory opera¬ tion commences at the beginning of processor cycle 1 and terminates at the end of processor cycle 3. Referring now to Fig. 2, at the commencement of processor cycle 1, the virtual address commences the address translation process with the high order bits looked at. In the present invention, recognition of the fact that for a paging substitution scheme, the bits comprising the virtual address are, for the lower order bits, the same as for the real address. These lower order bits can be taken directly from the virtual ad¬ dress without the necessity of translation, making those bits available to the memory circuit as real address bits so that memory accessing can be commenced prior to the termination of processor cycle 1. As shown in the timing waveform entitled virtual memory operation, the relative time saving is shown as equal to approximately one-half of a normal processor cycle time. More speci¬ fically, the savings is directly related to the row address strobe, RAS, and column address strobe, CAS, timing requirements of the DRAM used in the memory implementation. Referring to Fig. 3, in a matrix diagram form, the virtual address spaces are shown containing a word of data at location 800000 (HEXADECIMAL) within a 24-bit virtual address space. The word resides in the first word of a page where a page contains 1024 bytes or 256 words (4 bytes per word) . When the page is assigned a slot within the real memory, the 1024 bytes in the page retain their same relationship to the beginning of the page independent of the physical location of the page in real memory. Therefore, the real memory address of the data word, for the illustration, is 03FC00 (HEXADECIMAL) with the least significant 10 bits remaining the same. In the preferred embodiment of the invention the memory size is a 256K byte memory, therefore, real address space would consist of 256 pages of 256 words (IK bytes) each. When a page is assigned a slot within the real memory, the 1024 bytes of data in the page retain the same relationship to the beginning of the page inde¬ pendent of the physical location of the page in real memory. Therefore, the real memory address of the data byte at virtual address 800000 is 03FC00 with the least significant 10 bits remaining 0. Likewise, the data byte at virtual address 800001 receives a real memory address of 03FC01. Referring to Fig. 4, a 32-bit processor memory bus 44 interconnects a processor element 40, an address translation element 42 and a memory interface element 48. The processor element 40 generates the virtual memory address and the address translation element 42 converts the virtual address to a real address. The memory interface element 48 generates the timing strobes required for the memory array 50 as well as the memory address inputs. Logic 80 within memory interface ele¬ ment 48 provides the signals for implementing the pre- sent invention. The logic will be described in detail on the description of Fig. 6. Data read from and/or written into the memory array 50 traverses a coupling OMPI ° path 56 to the memory interface element 48. Memory address information traverses path 52 and timing control signals traverse path 54. Referring to Fig. 5, wherein is disclosed a block diagram of the type well-known for a 65K bit DRAM (dynamic random access memory) memory (example, FUJITSU MB8264) . A 65K bit storage cell 60 is accessed by signals from column and row address decoders 66 and 62, respectively. The column and row decoders receive address signals from the address buffers 58. The addresses are time division multiplexed into the address buffers 58 with the first eight bits of a 16 bit address corresponding to a row decode and the second eight bits corresponding to a column decode. The multiplexing of the row and column address is determined by the state of the signals RAS and CAS. The signal RAS is directed to the input of a clock generator 63 and the signal CAS is directed to an input of an AND gate 65. The output of AND gate 65 is directed to the input of a clock generator 64. The row address signal is generated first and enables the column addressing signal as evidenced by the fact that the clock generator 63 provides an enabling signal to the AND gate 65. If a write opera¬ tion is desired, a write enable signal WE is applied to the write clock generator 68. Generator 68 enables the data in buffer 69. Data stored in buffer 69 is then directed to sense amps and I/O gating circuit 67 and to the memory 60. The sense amp and I/O gating circuit 67 will then write the data into the proper address location. If a normal read cycle is to occur, the sense amps and I/O gating circuit 67 will read the addressed data from the memory 60 and direct the data to an output buffer 70. The data stored in buffer 70 is directed to the D out line which is part of the coupling path 56. O P Referring to Fig. 6, the logic implementation 80 shown therein is contained within the memory inter¬ face element 48. An OR gate 82 receives as inputs the memory address enable signal MAE which indicates that a real address is present on the bus 44 and the processor virtual transfer signal PVT which indicates that a virtual address is present on the bus 44. These signals along with the clocking signal XT present in virtual systems and their derivation, for simplicity purposes, will not be discussed in detail. The output of OR gate 82 is directed as an input to an AND gate 83 which has as a gating input the system clocking signal X Q . The output of AND gate 83 acts as a clocking signal for the latching circuit 84. The latching circuit 84 is com- prised of three 8-bit latch circuits (SN74LS373) cas¬ caded to form a 22-bit latch. The inputs of each latch are a corresponding line on the 32-bit processor memory bus for 22 of the bus lines labeled PMBUS24-03. Bits 1 and 2 are not required because memory data is being accessed a word at a time. Bits 1 and 2 determine byte selection within a word. Bits 32-25 are not required because the maximum memory address is contained within 24 bits. During the time when X~ and PVT are active, the PM bus inputs are received by and passed through the latch and appear at the latch outputs. With X Q being the gating control signal, when it goes high the latch closes. The signals on bus lines 10-3 are the row address signals RAlO-03 for a 65K DRAM with the signals on bus lines 11-18 being the column addresses CA18-11. Bus lines 19-24 carry the address signals AD24-19. These address signals address the particular memory bank, of which there is only one, in the preferred em¬ bodiment (32, 65K-bit DRAMS equals 256K bytes). A 2:1 multiplexer 85 receives at its inputs the signals RA10-03 and CA18-11 and in response to a multiplexing signal ADSW determines which of the two inputs will appear at its output. The multiplexer -gTJRE O PI consists of two 4-bit 2:1 multiplexer circuits (SN74LS157). The clock signal Q Q is directed to an input of a standard 50 nsec. delay line 93 with 5 nsec. taps which delay line provides at its outputs the two delayed versions of the clocking signal X n called X ΩA and QQ . The delay is required to permit the address signal to propagate through to the memory with enough set up time to allow for the stabilization of signals. These delayed clocking signals are directed to the clocking inputs of a JK flip-flop 88 and to a D-type flip-flop 90. In addition, on the J input of flip-flop 88, the memory address enable signal MAE is applied and on the D-type flip-flop 90 the processor virtual trans¬ fer signal PVT is applied to the D input. The output signals from flip-flop 88 are; at the Q output the signal MAED and at the Q output the signal MAED. The output of flip-flop 90 is the signal PVTD taken from the Q output. An eight stage shift register 92 receives at its mode input (M) the signal MAED from flip-flop 88. In addition, the clocking signal X is directed to the clock (C) input of an 8-bit shift register 92 (SN74LS165). The output of the shift register is taken at the Q_ output terminal and is identified as the clear signal CLEAR which signal is directed to the K input of flip-flop 88. Shift register 92 has its D6 input con¬ nected to ground with its remaining inputs DO through D5, D7 and S connected to +5 volts. OR gates 95 and 96 receive the PVTD and the MAED signals as inputs to pro¬ vide the signals RAS and RAS at their outputs. The signal RAS is directed to a second 50 nsec. delay line 94, the outputs of which are taken from taps 2 and 4 to provide the delayed RAS signals ADSWEN and CASEN. The ADSWEN signal is directed to the input of an inverter 97 to provide the inverted output signal ADSW. This signal is the multiplex switching signal applied to the S inputs of the 2:1 multiplexer 85. A multiplicity of AND gates corresponding in number to the number of banks in the memory are pro¬ vided. In this particular embodiment there is only one of these AND gates, but two of which 98 and 99 are shown as representatives of the wiring of the remaining gates in a system requiring larger memory. Each of the AND gates receives as an input the signals CASEN and MAED. In addition, each AND gate receives its own respective output from the decode block 86. The decode block consists of as many gates or decoder chips to select the appropriate bank of DRAM chips. The output of each of the AND gates is the respective signal CAS1 for AND gate 1 and CAS2 for AND gate 2, etc. Referring now to the waveforms of Fig. 7 in conjunction with the logic of Fig. 6. As can be seen from the timing waveforms of Fig. 7, the processor transfers the virtual address onto the PMBUS24-03 lines during the first half cycle (designated as X_.) by acti¬ vating the processor virtual transfer (PVT) signal. Bits 01 and 02 of the address are not of present int¬ erest since they are used to select a specific byte from the full word and this is done once the word is received back in the processor. At the leading edge of the X QB clock the D flip-flop 90 clocks in the presence of the PVT signal producing the PVTD term. The PVTD signal through the OR gate 95 generates the row address strobe signal RAS. The row address bits from latch 84 had propagated through the 2:1 multiplexer circuit to gen¬ erate the RAMAD08-01 signals which are the address inputs to the DRAMs (memory) . The ADSW term is in¬ active, which permitted the RAl -03 inputs to appear on the RAMAD08-01 outputs. The signal RAS is applied to all banks of the memory circuit which latches into the memory the row address. The RAS complementary signal RAS is propagated through the second delay line 94 to generate the ADSWEN address switch enable signal and the CAS enable signal CASEN. When the ADSW signal is OMPI S ΠΌ activated (active low) , the multiplexer 85 is switched to pick up the inputs CA18-11. Following a successful address translation, the real address is transferred onto the PM Bus 24-03 lines during the next X n by the address translation element. The memory address enable signal, MAE, is activated which indicates that the address is a real memory address. The OR gate 82 and AND gate 83 again provide a clock to the latch 84. The outputs of the latch are propagated through the multi- plexer 85 to the RAMAD08-01 lines as the column address. The upper address bits AD24-19 propagate through the decoder 86 to generate the bank number select signals BANK1, BANK2, etc. At the leading edge of the X Q , clock, the MAE signal allows the JK flip-flop 88 to set so as to generate the bank number select signal. At the leading edge of the X nA clock, the MAE signal allows the flip-flop 88 to set so as to generate MAED and MAED. The signal MAED reinforces the signal RAS through the OR gate 95 since the signal PVTD will be resetting at the leading edge of X QB « With the appropriate bank number term active, the signal CASEN already active and the signal MAED now active, the gates 98 and 99 will acti¬ vate the appropriate column address strobe, CAS. The column address will be strobed into the appropriate data memory bank. At the trailing edge of the signal X π and MAED active, the shift register 92 will shift the D6 input to the Q7 output. For the timing shown, the D6 input was strapped to ground so that the output signal CLEAR would be activated. The particular strapping used is a function of the access times of the DRAMs chosen for the memory design. With CLEAR active, the MAED term will be reset at the next X ΠA clock which will cause both RAS and CAS to be deactivated. In the event that a suc- cessful address translation did not occur, then PVTD resetting would not be reinforced by the signal MAED since the signal MAE would not be generated. The OMP /fa W1P signal RAS would be deactivated without a column address strobe CAS being generated. The detailed logic design of the present invention will change if the page size or density of the DRAM changes. The only changes will be in the area of the multiplexer 85 in that the untranslated low order virtual address bits for a different page size must be matched up against the number of RAMAD bits. The last two timing signals shown in Fig. 7 depict the RAS, CAS1 relationship in conventional sys¬ tems where the RAS is not generated until the address translation is complete. By comparing these to the RAS, CAS1 of the invention it is apparent that there is a time savings. In the invention, RAS is generated while address translation is still underway. CASΪ is subse¬ quently activated when the address translation com¬ pletes. The value of the time saved will be equal to the RAS to CAS minimum delay requirement for the parti- cular DRAM employed.

Claims: CLAIMS : 1. A memory addressing system, including memory means (48, 50) adapted to contain stored data arranged in pages, processor means (40) adapted to provide virtual addresses, and address translation means (42), characterized in that said memory means (48, 50), said processor means (40) and said address translation means (42) are coupled to a memory bus (44) and in that said memory means (48, 50) includes memory interface means (48) and an addressable memory unit (50), whereby in operation each virtual address is supplied from said processor means (40) to said memory bus (44), such that said address translation means (42) is effective to translate the virtual address to a real address, each such virtual address including a group of virtual address bits which correspond to a group of real address bits of the corresponding real address and which are supplied from said memory bus (44) to said memory interface means (48) such that said group of virtual address bits commence to address said memory unit (50). 2. A memory addressing system according to claim 1, characterized in that said groups of virtual and real address bits are lower order address bits of the respective addresses. 3. A memory addressing system according to claim 2 , characterized in that said memory interface means (48) includes latching means (84) adapted to latch said group of virtual address bits in response to a first control signal (PVT) provided by said processor means (40), representing that said virtual address is provided on said memory bus (44) and logic means (86-99) adapted in response to said first control signal (PVT) to provide a first addressing control signal (RAS) to said memory unit (50) to enable said memory unit (50) to initiate an addressing operation. OMP /fa WIP 4. A memory addressing system according to claim 3, characterized in that said address translation means (42) is adapted to provide a- second control signal (MAE) representing that a translated real address is provided on said memory bus (44), and effective to cause the real address to be latched by said latching means (84), said logic means (86-99) being effective to provide a second addressing control signal (CAS) to said memory unit (50) to enable said memory unit (50) to complete said addressing operation. 5. A memory addressing system according to claim 4, characterized in that said memory interface means (48) includes multiplexer means (85) coupled to said latching means and arranged to selectively couple said lower order address bits or higher order address bits to said memory unit (50) in accordance with a third control signal (ADSW) provided in dependence on said first addressing control signal (RAS) . 6. A memory addressing system according to claim 5, characterized in that said memory unit (50) is a dynamic random access memory including address buffer means (58) adapted to supply row and column addresses in time division multiplexed manner to respective row and column decoder devices (62, 66). 7. A virtual memory addressing method for addressing a memory (50) having pages of data stored therein, including the steps of providing a virtual address and commencing translation of the virtual address into a real address, characterized by the steps of commencing access of said memory (50) using untrans¬ lated lower order virtual address bits and completing access of said memory (50) utilizing the translated higher order address bits. ( OkfPI e W1PO

Inventors: CELIO JOHN ANTHONY, CELIO, JOHN, ANTHONY
Applicants: NCR CO, NCR CORPORATION
Application year: 1983
Main classification: G06F13
IPC codes: G06F12, G11C8