SHIFT REGISTER

Abstract: A shift register (60) which can alter an effective bit length without any changes in the internal structure of the shift register (60). For that purpose, a transfer clock genera­ tor (71) which supplies a transfer clock to the shift register (60) is provided, this alters the obtained clock data of the transfer clock and the input state of the shift register. This shift register can be applied to a memory of an SPS struc­ ture or the like.

Description: DESCRIPTION TITLE OF THE INVENTION SHIFT REGISTERS TECHNICAL FIELD This invention relates to a shift register which is adapted for use with a memory of a serial-parallelserial (SPS) configuration formed of a charge transfer device (CTD) such as a CCD or the like. BACKGROUND ART Fig, 1 shows an example of a memory having an SPS configuration formed by a CCD. This memory comprises a serial shift register (input shift register) 10R, parallel shift registers (parallel transfer shift registers) OR the number of which corresponds to the effective bit length of the serial shift register and a serial shift register (output shift register) 30R. The output from the output shift register 30R is reproduced by a reproducing circuit 40 and then fed to an input/output circuit 50. A part of such output is fed back to the input shift register 10R side and rewritten therein. Since the use of the memory 10 thus.made and the bit length thereof are determined when the shift registers 10R to 30R and the peripheral circuits (drive circuit and so on) are constructed, the memory has no freedom of selecting its use and bit length. DISCLOSURE OF INVENTION Accordingly, it is an object of this invention to provide a shift register which can arbitrarily vary its effective bit length even if the shift register is kept same in bit length, namely, unless the inner construction of the shift register is changed. It is another object of this invention to provide a shift register which, when used as a memory or the like, can select its use and bit length with ease. To solve these technical problems, according to this invention, a transfer clock data is properly selected and two transfer systems for driving the shift register, namely, the electrode/bit (E/B) system and the ordinary transfer system are properly used effectively so that the effective bit length of an n-phase and m-bit shift register n-I can be varied to n 1 x m bits at maximum. n BRIEF DESCRIPTION OF DRAWINGS Fig, 1 is a systematic block diagram of a memory having an SPS configuration, Fig, 2 is a cross-sectional diagram useful for explaining a shift register formed of a CCD, Fig, 3 is a systematic block diagram showing an example of a circuit which drives the shift register, Figs. 4 to 8 are respectively diagrams useful for explaining the operation of this invention, Fig, 9 is a construction diagram showing an example of the shift register and Figs. 10 to 15 are respectively diagrams further useful for explaining the operation of this invention. BEST MODE FOR CARRYING OUT THE INVENTION Fig. 2 and the succeeding drawings show an embodiment of the shift register according to the present invention. Fig. 2 shows a case in which a CCD is used as the shift register according to the present invention. In the figure, a 6-phase transfer clock shift register is illustrated as an example. The example of Fig, 2 is a buried channel type CCD. In the figure, reference numeral 61 designates a P type substrate, 62 a buried N type diffusion layer and °1 to °6 transfer electrodes. When predetermined transfer clocks (determined by clock data which will be described later) P1 to P6 are supplied to a plurality of the transfer electrodes f1 to f6 the transfer of data is carried out. Fig. 3 is an example of a drive circuit for the shift register 60. Reference numeral 71 designates a transfer clock generator which can be controlled from the outside, This transfer clock generator 71 produces data of a clock for use with the E/B transfer and data of a clock for use with the ordinary transfer. Reference numerals 72A to 72F designate bidirectional shift registers, respectively. When the clock data is supplied to the shift register 72A, the clock data is shifted in turn by one bit each from the left-hand shift register to the right-hand shift register. On the other hand, when the clock data is supplied to the right-hand shift register 72F, the clock data is shifted in turn by one bit each from the right-hand shift register to the left-hand shift register 72A. The outputs from these shift registers are respectively supplied through clock drivers 73A to 73F to the transfer electrodes to #6 shown in Fig. 2 as their transfer clocks. The effective bit length of this shift register 60 is determined by the kinds of the clock data produced from the transfer clock generator 71 and by selecting the transfer system as either the E/B transfer or the ordinary transfer. In the case of the n-phase and m-bit (m represents the total number of the transfer electrodes) shift register 60, the effective bit length can be extended from I n-l 1 x m bits to n 1 x m bits at maximum. In the case of n n 6-phase and m-bit shift register, if the kinds of the transfer clock and the transfer system are selected properly, the effective bit length can be varied from m bits to 6 m bits. In the first, an example in which the effective 5 bit length of 56 m bits is obtained will be described. In this case, data, [ 100000 ] is used as the clock data and the E/B transfer is selected as the transfer system. Accordingly, the clock data is supplied to the right-hand shift register 72F so that time sequential transfer clocks as shown in Fig. 5 are supplied to the transfer electrodes to When a single signal charge is taken in and then transferred, the shift register is set to a mode shown in Fig. 4. A predtermined DC bias is applied to a second input gate ING2 and a latch clock which changes at each predetermined period is applied to a first input gate ING1 with the result that as shown in Fig. 4B, after the predetermined signal charge is applied from an input source INS to the input gates, the signal charge is transferred under such state that it is shifted in turn by one bit each as shown in Figs. 4C to 4E by the transfer clocks (an example of such clock data is shown in Fig. 5) supplied to the transfer electrodes f1 to Fig. 6 shows such a transfer mode in which the signal charges are accumulated in the wells beneath all the electrodes °1 to °6. Since the clock data is in the E/B transfer and shifted in turn from the right-hand side to the left-hand side of the shift register, the change of the well for the signal charge is moved from the righthand side to the left-hand side as shown in the figure. When the signal charges are accumulated in the wells beneath a plurality of electrodes as described above, the data must be shifted by one bit each by the transfer clock Therefore, in the case of 6-phase clock, the input data is so controlled that an empty charge is presented in the well having the quantity of one bit at minimum. Accordingly, in the case of 6-phase clock, the shift reigster has the capacity of 6 - 1 = 5 bits at maximum. In consequence, when the number of the transfer clock electrodes in the whole of the shift register is m bits, the whole effective bit length S becomes 6 x m bits. When the transfer system is changed from the E/B transfer to the ordinary transfer under the same transfer clock data, the clock data is supplied to the left-hand side shift register 72A of the shift register so that the transfer clocks P1 to P6, being under the state shown in Fig. 7, are sequentially supplied to the respective transfer electrodes. As a result, the well is sequentially moved left to right by the clock data (see Fig. 8). Also, since the data is allowed to be supplied to the transfer electrode °1 after 6 bits were shifted, under even 6-phase driving the data is supplied to only one phase thereof. Thus, even in the 6-phase clock, the number of the transfer bits is 1. In other words, even when the total number of the transfer electrodes is m bits, the effective bit length becomes 6 run. Accordingly, even when the same clock data is used, the effective bit length can be reduced to 1/5 by changing the transfer system from the E/B transfer system to the ordinary transfer. The shift register 72 provided in the drive circuit 70 includes a plurality of D type flip-flops 75A to 75F, and gate circuits 76A to 76F provided at the data input terminal sides thereof as shown in Fig. 9. Each of these gate circuits 76A to 76F is formed of a pair of AND gates and an OR gate. One AND gates 77A to 77F are supplied with the control data which control the shift direction of the shift register and the AND gate 77A at the first stage is supplied with the clock data which is used in the ordinary transfer. On the other hand, the other AND gates 78A to 78F are the gates used when the data is shifted from the right-hand side to the left-hand side. They are supplied with the selection data which are used for shifting the data to the right-hand side, and the AND gate 78F at the last stage is supplied with the clock data which is used in the E/B transfer. The selection data and the clock data are selected by a selecting circuit 80 which selects the shift direction as shown in the figure. The selecting circuit 80 includes a pair of AND gates and 81B which are commonly supplied with a predetermined clock data from the transfer clock generator 71. And, one AND gate 81A is supplied with the selection data, while the other AND gate 81B is supplied with the selection data through an inverter 82. Accordingly, when the high level selection data is supplied to a terminal 83, the other AND gate 81B is turned off so that only the clock data, which is passed through one AND gate 81A, is supplied through the gate circuit 76A to the D type flip-flop 75A which forms the shift register 72A at the first stage, thus the clock data being shifted in turn by one bit each from the left-hand side to the right-hand side. Meanwhile, when the selection data applied to the terminal 83 is at low level only the other AND gate 81B is operated so that at this time the clock data is supplied through the AND gate 81B and the AND gate 78F provided in the shift reigster 72F to the D type flipflop 75F with the result that the clock data is shifted in turn from the right-hand side to the left-hand side. As set forth above, by the use of the selecting circuit 80, it becomes possible to use one shift register as the bidirectional shift reigster. Reference numeral 84 designates a terminal to which a clock. pulse is supplied. By the way, the embodiment shown in Fig. 8 is the case in which the effective bit length is reduced to -6m bits. Fig. 10 and the following drawings show futher modified examples. Figs. 10 and 11 show the embodiment 2 in which the effective bit length is varied to 26 m bits. Fig. 10 is a timing chart of the transfer clocks P1 to P6 used therefor and the clock data is L100100J. At that time, the shift register is driven according to the ordinary transfer system and the mode upon transfer is shown in Fig. 11 Fig. 12 shows the case in which the effective 3 bit length is varied to Wm bits and the clock data is fl010103. Fig. 12 shows a timing chart of the transfer clocks P1 to P6 based on the clock data and Fig. 13 shows the accumulation state and the transfer state of the signal charge at this time. The shift register is driven according to the ordinary transfer at this time. Fig. 14 shows the case in which the effective 4 bit length is varied to -6m bits. In this case, the data [100100] is used as the clock data and the transfer system is selected to be the E/B transfer. Fig. 14 shows an example of the transfer clocks P1 to P6. Fig. 15 shows the accumulation state and the transfer state of the signal charge at that time. When the shift register according to this invention is used for the CCD memory shown in Fig. 1, the shift register according to this invention is used as the part of the parallel shift register shown in Fig. 1. And, when the transfer clock generator and the drive circuit are added to this parallel shift register, the effective bit length can arbitrarily be varied from bits to 5 bits from the outside. Therefore, with the 6 same shift register and without varying the peripheral circuits, the capacity of the memory can freely be varied so that it is not necessary to construct the shift register and the peripheral circuits thereof in accordance with the use. In this case, it is sufficient that the data from the input shift register 10R is supplied to the second input gate ING2 shown in Fig. 4. As set forth above, according to the present invention, by the selection of the transfer system and the selection of the clock data, the effective bit length of the n-phase and m-bit shift register can arbitrarily be varied from m bits to n-l x m bits at maximum n n without varying the inner construction of this shift register. Thus in this invention, without modifying the shift register and the peripheral circuits thereof, the effective bit length can freely be varied from the outside in accordance with the use. In consequence, the shift register of the present invention is quite useful for use as a field or frame memory having a serial-parallel-serial conversion construction as described above or the like. Of course, the shift register of this invention can be used as the single shift register satisfactorily. While in the above embodiments the 6-phase shift register was referred to as the n-phase and m-bit shift register, the number of phases is not limited. Also, when the shift register 72 is constructed as shown in Fig. 9, the provision of a plurality of gate circuits 76A to 76F and the selecting circuit 80 for the shift direction enables this shift register 72 to be used as the bidirec#tional shift register so that the construction of the shift register can be simplified greatly. While in the above the shift register of the CCD construction is referred to as the charge transfer type shift register, it is needless to say that the shift register of the present invention can be formed of the shift register which employs other charge transfer elements. Moreover, while in Fig. 3 the predetermined effective bit length can be obtained by controlling the transfer clock generator 71 from the outside, it is possible that the clock data and the selection data are stored in a ROM or the like and then selected from the outside. Furthermore, when the transfer electrodes to #6 and the outputs of the clock drivers 73A to 73F are connected together, if the connection is changed, without modifying the inner construction of the shift register, the shift register having any one of the bit lengths in the above embodiments can be formed.

Claims: CLAIM A shift register comprising an n-phase and m-bit charge transfer type shift register and a transfer clock generator for said shift register wherein a bit capacity n-l can be varied to n l x m bits at maximum by driving said shift register on the basis of a predetermined transfer clock which is generated from said transfer clock generator.

Inventors: HASHIMOTO, TAKEO, NARABU, TADAKUNI, SATO, MAKI
Applicants: SONY CORPORATION
Application year: 1983
Main classification: G11C19
IPC codes: G11C19, H01L29, G11C27, H01L21