SEMICONDUCTOR DEVICE HAVING A WELL STRUCTURE

Abstract: To the ends of avoiding an abnormal phenomenon such as latch-up attributed to a parasitic element and of enhancing the density of integration, a groove-like insulator layer (20) extending in the depthwise direction of a semiconductor body (1) is formed at a boundary part between a well region (2) and the semiconductor body (1). Owing to the insulator layer (20), conductive regions which would constitute the parasitic element are separated apart, so that the latch-up phenomenon does not arise. Therefore, the area of the well region (2) can be made small, and the density of integration can be made 1.4 times higher than in prior-art LSI circuits.

Description: Semiconductor Device having a Well Str#ucture Background of the Invention The present invention relates to a semiconductor device having a well structure, and more particularly to a semiconductor device greatly effective for application to the LSIs of a memory, a random logic, a microcomputer etc. which are formed of CMOS structures. Heretofore, CMOS (Complementary Metal Oxide Sem#conductor) circuits have been constructed of a fundamental inverter circuit shown in Figure l(a) and have had a sectional structure shown in Figure l(b). Referring to the figures, numeral 1 designates an n-type Si semiconductor substrate, numeral 2 a p-type well layer, numerals 3 and 4 p-type impurity layers, numerals 5 and 6 n-type impurity layers, and numerals 7 and 8 the gates of transistors, which are usually polycrystalline silicon layers. Shown at numeral 9 is an insulator film for isolation, such as SiC2 film. The p-channel MOS transistor is constructed of the layers 3, 4 and 7, while the n-channel MOS transistor is constructed of the layers 5, 6 and 8, and the circuit designations of the respective transistors are numerals 10 and 11 in Figure l(a). Terminals 12 and 13 are input and output terminals, respectively. In the semiconductor device having the above CMOS structure of the prior art, the circuit element is formed also in the predetermined region outside the well region 2 in correspondence with the element formed in this well region. Besides these circuit elements, an n-p-n bipolar transistor is parasitically formed of the substrate 1, well layer 2 and impurity layer 5. That is, the substrate 1 is regarded as a collector, the well layer 2 as a base, and the impurity layer 5 as an emitter. Also a lateral p-n-p bipolar transistor is parasitically formed of the impurity layer 4, substrate 1 and well layer 2. That is, the impurity layer 4 is regarded as an emitter, the substrate 1 as a base, and the well layer 2 as a collector. Also resistances of the substrate 1 and well layer 2 exist, and these elements constitute a thyristor as a whole. In this manner, when the well layer is disposed within the semiconductor substrate, a parasitic thyristor is inevitably formed. In the presence of such thyristcr, when by way of example a great noise current is injected from the output terminal 13 into the p-type well layer 2 acting as the base of the parasitic n-p-n transistor, the thyristor is subjected to positive feedback, and a great current flows across a power supply terminal (Vcc) and a ground terminal, to destroy the device in the worst case. This is the abnormal phenomenon peculiar to the COS structure having heretofore been called "latch-up' (thyristor breakdown), and has been the most serious disadvantage of the CMOS structure. In order to overcome this disadvantage, the prior art cannot help taking the following measure. The base length of the parasitic p-n-p transistor, that is, the distance between the p-type impurity layer 4 and the p-type well layer 2 is set at a long interval of at least 10 gm, or the depth of the p-type well layer 2 acting as the base length of the parasitic n-p-n transistor is deliberately rendered great, whereby the current gain of the parasitic transistor is reduced so as to prevent the positive feedback to the thyristor and to avoid the latch-up phenomenon. Any of such measures, however, results in rendering the regions of the same conductivity type more distant than is necessary or widely spreading a region not required for the operation of the essential element, and it rather hampers enhancement in the density of integration of the device. For example, in terms of the occupying area per stage of an inverter, the CMOS circuit requires an occupying area which is about 1.4 times larger than that of an NMOS circuit, under the same pattern design rules. List of Prior Arts 1) USP Nc. 4,151,610 2) USP No. 4,178,605 3) US Ser. No. 380,410 4) Japanese Laid-open Patent Application No. 54-151382 Summary of the Invention An object of the present invention is to overcome the disadvantage of the prior art inherent in the well structure as described above, and to provide a semiconductor device having a well structure which has a small occupying area and which can attain a high density of integration. The construction of the present invention for accar#lishing the object comprises a semiconductor substrate, a well region which is formed in the substrate, and an insulator layer which is made of a groove-like insulator and which is formed in the boundary part between the semiconductor substrate and the well region so as to extend deeply into the substrate. The insulator layer Is, at least, deeper than the well region and is provided along the side wall of the boundary. If necessary, it is formed so as to run on the extension of the wall in the depthwise direction. in addition, it is important for enhancement in the density of integration that the insulator layer is longer in its depthwise direction than in its widthwise direction. Owing to the above construction of the present invention, even when the well region itself forms a certain conductive region (e. g., base region) of a parasitic transistor, the base current path of the parasitic transistor detours under the bottom of the insulator layer and becomes long, so that the base current of the parasitic transistor decreases, the injection efficiency thereof lowers, and the gain thereof diminishes drastically. As a result, the latch-up is hindered. Therefore, the area of the well region can be made small, and the distance between an active element to be formed within the well region and another active element to be disposed outside the well region in correspondence with the former element is conspicuously shortened, which brings forth the effect of enhancing the density of integration. In this manner, the present invention consists in that, in a circuit having one function such as an inverter circuit, an element constituting the circuit is isolated so as not to become a parasitic element or a part thereof, and it is essentially different in the object, construction and functional effect from the so-called isolation between conventional circuits or elements which incur no parasitic element (for example, the isoplanar technique, a technique utilizing LOGOS, etc.). Since the invention will be described in detail below in conjunction with embodiments, it Will be clearly understood in order. Brief Description of the Drawings Figure l(a) is a circuit diagram of an inverter circuit which employs CMOS transistors, while Figure l(b) is a schematic sectional view of a prior-art semiconductor device which is applied to this circuit. Figure 2 is a schematic sectional view of a semiconductor device as an embodiment of the present invention in which an insulator layer is disposed at the boundary between a semiconductor substrate and a well region. Figure 3 is a schematic sectional view of a semiconductor device as another embodiment of the present invention in which the insulator layer in Figure 2 extends irore deeply than the well region within the substrate. Figure 4(a) shows another example of a circuit to which the present invention is applied, while Figure 4(b) Is a schematic sectional view thereof. Figure 5 is a schematic sectional view showing still another circuit to which the present invention is applied. Detailed Descrittion of the Preferred Embodiments Figure 2 is a schematic sectional view of a semiconductor device which is an embodiment of the present invention. In the figure, numeral 21 designates a p-type impurity layer which corresponds to the layers 3 and 4 shown in Figure 1 (hereinbelow, this figure shall be referred to), numerals 22 and 23 n-type impurity layers which correspond to the layers 5 and 6, and numeral 24 a pol#crystalline silicon layer as a gate electrode which corresponds to the layer 8. The characterizing feature of the present embodiment consists in that an insulator layer 20 is disposed at the boundary part between the Si substrate 1 and the well layer 2. The insulator layer 20 has a width not greater than 5 m, and is deeper than the p-type well layer 2. This insulator layer 20 isolates the p-channel MOS transistor 10 and the n-channel MOS transistor 11. More important is that the insulator layer 20 serves as means for hampering the latch-up in such a manner that the current path between the base region (here, the well 2) of the parasitic bipolar transistor formed of the regions 5 (or 6), 2 and 1 and the electrode region (here, the impurity layer 4) of the base region is caused to electrically detour in the depthwise direction of the substrate. As a result, the latch-up phenomenon which has been the disadvantage of the prior art does not develop, and it is permitted to intake the well region smaller. Thus, the two objects contradictory to each other, namely prevent inc the latch-up phenomenon and enhancing the density of integration have been simultaneously solved. More specifically, since the insulator layer 20 is formed deeper than the well region 2, the insulating isolation between the p-type impurity layer 4 and the p-type well layer 2 is substantially perfect. In addition, since the injection of noise current to incur the latch-up goes through the path which is, at least, deeper than the well from the surface of the substrate, equivalently the p-type impurity layer 4 and the well 2 are spaced 10 tm or more in plan. Moreover, since the planar width of the insulator layer 20 is as small as 5 em or less, the transistors can be disposed in proximity to each other, which is very advantageous for enhancing the density of integration. The groove width of the insulator layer may be shorter than the depth thereof. The groove width is usually 0.3 - 10 and preferably 1 - 5 pm to the end of enhancing the density of integration. With a groove width smaller than 1 tm, difficulties are involved in the manufacturing process. Therefore, the groove width should of course be set scrupulously. In forming the insulator layer 20, the known reactive sputter etching is resorted to by employing, e. g., Si3N4 for a mask, whereby the deep groove whose side surface is substantially vertical is formed. The groove depth as predetermined is attained by adjusting the period of time of the sputtering. Subsequently, local oxidation is performed to form a thick SiC2 film in the groove, and the Si3N4 film is removed. Thereafter, an Si N film is deposited on the whole surface again. N#ext, polycrystalline silicon is buried into the groove and has its exposed part oxidized so as to wholly turn into an SiO2 film. Thus, the insulator layer is formed. In the process for forming the insulator layer, more preferably an impurity opposite in the conductivity type to the substrate is introduced into the bottom of the groove to the end of preventing the appearance of a channel. Further, the Si3N4 film deposited on the whole surface in the latter half of the manufacturing process may well be omitted. The forming method mentioned above has exemplified the case of burying the polycrystalline silicon into the groove. As the burying material, however, a dielectric material such as SiO2 or Si3N4 or a high polymer material can also be used unobjectionably. These materials have attained equal effects. Figure 3 is a schematic sectional view of a semiconductor device which is another embodiment of the present invention. In the figure, numeral 31 indicates a heavily-doped n-type semiconductor substrate, numeral 32 a lightlydoped n-type epitaxial layer, and numeral 33 a p-type well layer. The characterizing feature of the present embodiment is that an insulator layer 30 is formed so as to reach the heavily-doped n-type semiconductor substrate 31, so the p-channel LOTOS transistor area and the n-channel MOS transistor area are perfectly isolated., With the semiconductor device of the present example, notwithstanding that the resistivity of the heavily-doped n-type semiconductor substrate 31 is as very low as 0.1 9.cm or less, the base current of the parasitic transistor is substantially cut off, and hence, the latch-up phenomenon being the disadvantage of the prior art is, in effect, hindered. Figures 4(b) and 4(a) show a partial schematic sectional view of a semiconductor device as still another embodiment of the present invention, and a diagram of a circuit employing the semiconductor device, respectively. In case of constructing a memory, e. g., static type random access memory by the use of the CMCS structure, a flip-flop formed of nN'iCS transistors and high resistance loads R as shown in Figure 4(a) has heretofore been used as a memory cell thereof. This memory cell has as small a signal amplitude as 500 mV or less, and undergoes a malfunction due to noise from a peripheral circuit of large signal amplitude. In the present example, insulator layers 41 and 42 which are deep enough to reach the heavily-doped impurity layer 31 are disposed to perfectly isolate a memory cell portion X and peripheral circuit portions Y. As a result, the inflow of noise signals from the peripheral circuits has been avoided, and a semiconductor device of high reliability having a stable memory function has been obtained. In Figure 4(b),numerals 48, 49 and 60 - 65 denote n-type hmrity layers, and numbers 43 - 47 polycrystalline silicon layers as the gates of MOS transistors. Figure 5 shows a schematic sectional view-of a semiconductor device which is yet another embodiment of the present invention. In the figure, numerals 51, 52, 54 and 55 indicate p-type impurity layers, and numeral 56 indicates an n-type impurity layer. This structure shows a vertical bipolar transistor which employs the layer 56 as its emitter E, the layers 54 and 55 as its base B and the layer 31 as its collector C. The bipolar transistor is formed in such a manner that it is isolated from another element, e. g., a p-channel MOS transistor formed of the layers 3, 4 and 7 or the layers 51, 52 and 53 by deep insulator layers 57 and 58 wrich form the characterizing feature of the present example. Thus, the bipolar transistor free from the latchup phenomenon and with a small occupying area can be fabricated, and the circuit operation performance can be enhanced. Needless to say, when an impurity layer whose conductivity type is the same as that of the p-type well 33 and which has a comparatively high impurity density is formed to be shallower than the p-type well layer 33 from the semiconductor surface in the embodiment of the figure, the base -length of the bipolar transistor becomes small to increase the parameter hFR, so that a higher operating performance can be attained. The same impurity layer as stated above may well be formed in the semiconductor surface portion of the memory cell portion in Figure 4(b). In this case, most of electrons created within the semiconductor by the impingement of e(-particles are excluded by the potential difference between the p-well layer 33 and the aforementioned impurity layer. Therefore, the probability at which data of the memory cell is destroyed becomes very low, and a memory device of high reliability can be fabricated. The embodiments have been explained as employing an insulator film such as of SiO2 for the greater part in order to isolate elements formed in an identical semiconductor surface, for example, n- and p-channel MOS transistors, bipolar transistors, j-FETs, etc Of course, even when any of them is individually formed by isolating it with narrow and deep insulator layers which characterize the present invention, the same effect is achieved. The present invention has been explained as to a CMOS structure in which a p-type well is formed in an n-type substrate. However, even when they are forded in opposite conductivity types, an effect similar to the foregoing is attained. Since such construction is merely different in the symbols of the conductivity types, the detailed description is omitted,

Claims: CLAIMS: 1. A semiconductor device having a semiconductor body (1; 32) of a first conductivity type, an impurity region (2; 33) of a second conductivity type which is disposed in a selected part of a surface region of the body, and active elements (10, 11) which are respectively disposed in the semiconductor body and the impurity region so as to correspond to each other, at least one of the active elements being an insulatedgate field effect transistor, characterized in that an insulator layer (20; 30; 41, 42; 57, 58) which is, at least, as deep as said impurity region (2; 33) is disposed at a boundary part between said semiconductor body (1; 32) and said impurity region. 2. A semiconductor device as defined in claim 1, characterized in that said semiconductor body of said first conductivity type has a double-layer structure in which a high impurity layer (31) is overlaid with a low impurity layer (32). 3. A semiconductor device as defined in claim 2, wherein said insulator layer (30; 41, 42; 57, 58) penetrates said low impurity layer (32) to reach said high impurity layer (31). 4. A semiconductor device as defined in any of claims 1 to 3, wherein said active elements (10, 11) corresponding to each other are insulated-gate field effect transistors which form a CMOS structure. 5. A semiconductor device as defined in any of claims 1 to 4, wherein one (10) of said active elements is a P-channel MOS transistor, while the other (11) is an N-channel MOS transistor. 6. A semiconductor device as defined in any of claims 1 to 5, wherein the depth of said insulator layer (20; 30; 41, 42; 57, 58) is greater than the width thereof. 7. A semiconductor device as defined in any of claims 1 to 6, wherein a high impurity layer is disposed in a bottom part of said semiconductor body (32) as well as said impurity region (33). 8. A semiconductor device as defined in any of claims 1 to 7, wherein said active elements (10, 11) disposed so as to correspond to each other constitute an inverter circuit. 9. A semiconductor device as defined in any of claims 1 to 7, wherein said active elements disposed so as to correspond to each other constitute a memory cell circuit X, Y). 10. A semiconductor device as defined in any of claims 1 to 4, wherein a lateral bipolar transistor (31, 54 ... 56) is formed in said impurity region (33).

Inventors: HASHIMOTO, NORIKAZU, HAYASHIDA, TETSUYA, MASUHARA, TOSHIAKI, MINATO, OSAMU, SASAKI, TOSHIO, TAMAKI, YOICHI, YAMAMOTO, SYUICHI
Applicants: HITACHI, LTD.
Application year: 1983
Main classification: H01L21
IPC codes: H01L27, H01L29, H01L21