AN INTERFACE FOR TRANSFORMING A TYPEWRITER INTO A PRINTER

Abstract: An interface (10) for transforming conventional character code into a pulse position code useful with time code operated typewriters. The interface receives time code (M1-M8) from the typewriter (TYP) and character code (53) from a data processing device (50) and transforms the character code into a code corresponding to the time code of the keyboard matrix (MAX). The typewriter (TYP) may then be used to operate as a printer for a data processing system (50).

Description: AN INTERFACE FOR TRANSFORMING A TYPEWRITER INTO A PRINTER BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to electronic adapters and more particularly to electronic interfaces for converting time base coded type¬ writers into printers. In further particular, this invention relates to an emulation logic arrangement which converts either serial or parallel code into time based code for operating a time base coded typewriter as a printer. In data processing systems one ofthe more expensive components is the printer. In particular, when the data processing system is conformed for word processing, print quality, appearance, and character style (font) become dominant aspects and printers heretofore developed for data processing use are quickly found inadequate. For this reason most word processing systems are sold together with a printer typically of high print quality, to maintain.the visual print character¬ istics normally expected in office use. This, however, entails elaborate mechanical features involving high cost and, more importantly, duplication of the hardware already found in the office typewriter. Furthermore, word processing is sometimes an occassional function with the typewriter still providing service in many instances. Accordingly, most offices retain the typewriter when installing word processing systems, thus duplicating the cost of the print hardware. It is the conversion of typewriters using time aperture character code into standardized code that is disclosed herein. PRIOR ART Code converters of various kind have been known in the past. None, however, convert serial or parallel code into a code configura¬ tion emulating the time based coding, as found in some commercial typewriters. To the extent known the following patents constitute the best prior art: U.S. Patents #2,838,993; #3,390,334; #3,647,962; #3,649,856; #3,725,908; #3,810,154; #3,947,708; #4,027,280; #4,258,356; #4,311,991; Great Britain Patent No. 1,386,070; West Germany Patent No. 2,850,190. None of the foregoing patents are believed to teach or suggest any of the aspects of the present invention. More importantly, most of the above patents describe a time coded typewriter mechanism and therefore provide background information rather than . teachings of an emulator. SUMMARY OF THE INVENTION The present invention provides an interface conformed in its signal arrangement on one side to communicate with a computer system having a standardized bus configuration like that known as the IEΞE-488, RS232C or Centronic Parallel bus and on the other -side to communicate with any of the pulse position office typewriters exemplified by the Triumph-Adler, Royal, Brothers and Seiko Ltd. Silver Reed Model EX55 typewriters. Thus character data in a binary code such as ASCII or EBDIX, comprehensible to the computer system, is converted to pulse position code emulating the keystroke signals of this group of typewriters. As result the high quality print mechanisms provided in these typewriters are adapted for use as a printer responsive to standardized character data normally entailed in data processing. Thus the high cost of the print mechanism is not duplicated, all the necessary conversions being accomplished through the use of inexpensive electronic devices. More specifically, the characteristic data format of standardized bus systems entail either a 7 or 8 bit wide bus, with or without additional status bits, or a single channel, bit serial bus arrangement. In each instance the seven or eight bits of character data are strobed into a latch which maintains this information until the print cycle is completed. Before storage in the latch, the eight bits of data are converted into the appropriate code by a PROM (programmable read only memory) which effectively transforms -the code. The translated code then residing in the latch is sequentially decoded for row and column coordinates, corres¬ ponding to the timing coordinates of a switching matrix operated off the typewriter keyboard, in response to a running time code sequence in the typewriter. The bit serial processing systems may further include a UART (universal asynchronous £eceiver-transmitter) chip for reforming serial code into parallel form. Both of the foregoing interface arrange¬ ments further include the necessary time delays brought into effect to accommodate the various mechanical time constants of the typewriter print mechanism. It is these delays that, furthermore, control the transfer rate of character data from the processing system. In . this manner a typewriter characterized by a sequentially interrogated keyboard matrix may be used as a printer, responsive to standardized character code. BRIEF ' DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic illustration of an inventive interface for conforming a pulse position coded typewriter into a printer; FIG. 2 is a diagram of an alternative interface circuit option useful with bit serial data processors; FIG. 3 is a perspective layout of an office system incorporating the inventive interface; FIG. 4 is yet another diagram of an alternative inventive interface for conforming standard character code into a time based code arrangement of a typewriter; and FIG. 5 is a further embodiment of an interface for converting character code into a time based typewriter code. DESCRIPTION OF THE PREFERRED EMBODIMENT As shown in FIG. 1 the typewriter TYP conformed for printing by way of the present invention, is characterized as a "daisy wheel" typewriter having a keyboard KBD deployed over a switching matrix MAX of an MXN conformation which in the case of the Triumph-Adler typewriter Models SΞ1010 or SE1030 or SE5010 and 5030 Royal typewriter, comprises a 5 column, 16 row format. Thus, as the keys K of the keyboard KBD are selected one of the matrix coordinates is closed. Typewriters of this form typically also include a processor, or at least a counter, shown herein as a central processing unit CPU, which sequentially steps through the columns and rows to find the switched coordinate. Generally the count is in binary code developed on leads M. -M of which the less significant four leads M -M_ 5 o are fed to a 1 out of 16 decoder DEC and 3 of the more significant leads, e.g. M,-M 3 , drive an 8 bit multiplexer MUX. The decoder DEC then interrogates the row leads of matrix MAX while the multiplexer MUX interrogates the columns. o\;pι__ This sequential interrogation proceeds at the switching rates of the processor CPU and is thus at such high rates as to be virtually imperceptible to the user. According to the foregoing description the typewriter TYP can thus be generally characterized as a cyclic serial count, binary coded character identification typewriter; a code configuration not in common usage in the data processing industry. In essence the processor CPU recognizes the character selected by the keyboard KBD according to the pulse position of a pulse PS passed by the multiplexer MUX within a continuously running count; a technique quite suitable for typewriter use but somewhat wasteful when used in data processing. To utilize the rather expensive mechanical features provided in typewriters of this kind as an output device (printer) for the various standardized data processing systems it is thus necessary to transform the standardized character code into the foregoing matrix interrogation code. Such is achieved through the use of the inventive interface 10. More specifically, interface 10 may be generally separated into two main sections, one directed to communicate with a data processing system 50, shown herein as the handshake stage 11, and the second to translate the standardized code into the serial matrix read code of the typewriter TYP, shown herein as the translator stage 12. Stage 11 may include the necessary inverters and buffers to raise the data lines of the processor data bus 51 to the appropriate signal levels achieved in a data inverter/buffer 52. The buffer 52 outputs 8 lines of data 53 both to the translator stage 12 and to an address filter 54, shown as a single AND gate, which also receives the attention AT and data valid DV from the processor as conditioned by a control buffer 55. Thus the first word on bus 51 selects the printer and verifies for attention and valid data. The output of the address filter (gate) 54, in turn, drives the set input of an RS flip-flop 56 having its Q output combined with the data valid and attention signals AT and DV at the input of yet another AND gate 57. Gate 57 then produces the print signal PR to the translator stage 12. Signal PR, concurrently, sets off a monostable multivibrator (one shot) 58 of approximately one second duration which by its negative going edge clears flip flop 56. Thus the transfer path for the successive sets of character data remains open for one second once the printer is addressed. At the same time signal PR, recycled on each data valid signal DV, sets off yet another one shot 61, of approximately .08 second duration, which through a line driver 63 inhibits the transfer of the next successive character. Thus a .082.120 second time aperture is allowed between character transfers, accommoda¬ ting the logic in the typewriter CPU to sequence through the matrix. As the foregoing time apertures are set off character data on bus 53 is passed to the translator stage 12 where it is received as an 8 bit input of a programmable read only memory (PROM) 71. A corresponding 8 bit output is then developed at the output of the PROM which is fed to an 8 bit latch 72. Latch 72 is gated to latch in the foregoing output by a signal issuing from a one shot 73 which, in turn, is set off by the print signal PR. Since a mechanical lead time is required to raise the print mechanism to upper case an approximately 20 iliseconds further one shot 74 is raised by the output of one shot 73. One shot 74 then, at its time-out sets off a print one shot 75 which sets the time aperture for the character decode sequence. The code impressed onto latch 72 is spread into two signal branches, the first comprising three bits of data fed to a binary-to-decimal decoder 81 which converts the 3 bit code combinations into one-out-of-five signal leads. These correspond to the column coordinates of the matrix MAX. The five leads then respectively connected to the inputs of five corresponding AND gates 91-95 which also receive the output of one shot 75 and the output of a one-of-sixteen data selector/multiplexer 85. Multiplexer 85, in turn, receives at its input sixteen leads from a one-of-sixteen binary to decimal decoder 86 (four time to sixteen time decoders) which is driven by the leads M 5 ~M„ originating in the typewriter processor CPU. Thus, decoder 86 sequentially steps through the sixteen bits for OMPI fy V/n-O each row according to the binary count on leads Kr.-l'lr- - On each step a sequential one of its sixteen output leads is pulled up. Depending on the code input to the data selector/multiplexer 85 one of the sixteen output leads is pulled up. Depending on the code input to the data selector/ multiplexer 85 one of the sixteen inputs is selected. This data selection, in turn, is provided by a 4 bit output from latch 72 with the remaining one bit being fed to an AND gate 79 to identify the upper case which is, furthermore, receiving one of the sixteen outputs from decoder 86. The output of gate 79, in turn, is combined at an AND gate 77 with the output of an OR gate 78 which at its input combines the signals from one shots 74 and 75. Gate 77 is then combined with gate 95 at an OR gate 98 which feeds to the data input of a seven bit binary data selector/ multiplexer 99 which receives at its data select- terminals the signals M..-M,. O PI IPO In this manner the three more significant bit positions in latch 72 select a particular AND gate 91-95 while the less significant four bits from the latch select the gating in encoder 85 of the appropriate one of the sixteen bits of output from decoder 86. Thus both the row and the column information, generated by the matrix MAX, is emulated against the time code M.-M, and . M_-M„. Accordingly, any standardized code like ASCII may be converted to this particular matrix arrangement by the appropriate conversion algorithm in PROM 71. The above transformation arrangement is particularly suited for use with parallel bus systems like that commonly known as the IEEΞ-488 bus. Bit serial bus arrangements may be similarly accommodated through the use of various serial- to-parallel conversion devices like those shown in FIG. 2. As shown in this figure a standardized single channel bus system, like that known as the RS232C bus, entails modifications to the handshake stage 11 for transforming serial data into eight bit wide parallel code. Thus the single serial data channel is shown as bus 151, corresponding to bus 51 in FIG. 1. Bus 151 is received at the input of a universal asynchronous receiver- transmitter (UART) 152 which, according to a baud rate clock 155, in a manner known in the art, converts the serial code into the 8-bit parallel data bus 53. Concurrently, one bit in the serial bit stream is brought out as the signal data valid DV which is converted to the print signal PR through an inverter 156. Within the translator stage a first pulse FP on M R resets the UART and concurrently sets off one shots 61 and 58. In this form the serial data on bus 151 is converted to the parallel bus form 53 which is applied to PROM 71. Concurrently signal PR a latches this data leaving the UART free to accept the next serial word. While the handshake stage is thus occupied the translator stage proceeds to transform the character data according to the above-described sequence. Following similar coding arrangements one may adapt a time base coded typewriter like that made by Brothers of Japan under Model No. EMI or EM2 into a printer. Such an arrangement is shown in FIG. 4. Once again, the typewriter TYP is shown operated by a switching matrix conformed in time base code on row signals M.-M, and column signals ς - g. These signals, decode the parallel character data from the data processing system 50 which appear on bus 53. Bus 53 is tied to a PROM 401 which loads into a latch 4Q2. Latch 402 then loads with three of its leads a binary-to-decimal (B/D) decoder 404 which thus raises one out of eight of its output leads corresponding to a row signal. Concurrently yet another binary to decimal decoder 405 is serially interrogated by the code on signal lines M,-M , the parallel output of decoder 404 being tied to decoder 405 by way of a resistor matrix 406. Oϊ FI A remaining group of four bits from latch 402 is fed to a 16-bit encoder 411 which, once again, is tied at its data terminals to a 16-bit decoder 412. Decoder 412 converts the code on signals M g -Mg to a one-of-sixteen code and will thus match the code in encoder 411 once in every time countdown cycle. When this match occurs a signal is applied to the input of a NAND gate 413 which, through an inverter 414 drives the I/O terminal of decoder 404 • to be passed on a lead to decoder 405 as selected by the row code from latch 402. When the lead selection, by virtue of signals M,-M 3 , matches in decoder 405 the lead selected in decoder 404 the I/O terminal of decoder 405 goes high providing the print signal. This print signal is shaped by a shaping driver circuit comprising NAND gates 421 and 422, connected in parallel and coupled to the signal DS by a capacitor 423. Thus upon a coincidence between the decoders 404 and 405 the signal developed at the output of encoder 411 is passed through as a print pulse. Encoder.411, in turn, responds in its signal to the appropriate time code on M g -Mg. Accordingly, both the M x.-M- ό and M3_-Mσ 0 time codes are satisfied in correspondence with the character code from computer 50. - JREA O PI . -s, WIPO In addition to the foregoing there may be included the necessary upper case signal on the output of latch 402 which is combined at a NOR gate 431 with a signal from a NOR gate 432. Gate 432, in turn, combines the outputs of one shots or delays 433 and 434, the output of delay 434 being also collected at the input of gate 413. Delays 433 and 434 are furthermore in -circuit with yet another one shot 435 set off by the print signal PR which, again, may be produced as result of logic filtering of the housekeeping and data bus signals. To carry out upper case the output of gate 431 is combined with an inverter 436, inverting one of the signal lines between decoder 412 and encoder 411, at the input of a NAND gate 437 which together with an inverter 438 drives a NAND gate 439. Gate 438 receives one of the signals from decoder 404 and gate 439 passes its output to one input terminal of decoder 405. OMPI In the foregoing configuration decoders 404 and 405 may be simply implemented by way of dynamic RAM chips such as the chip circuit Number 4051 sold by Texas Instruments Inc., Dallas, Texas. Similarly latch 402 may be implemented through the use of chip model Number 74C373, encoder 411 by chip model Number 74C154 binary to sixteen bit decoder, all from Texas Instruments. The remaining items are similarly standard in the art and- any manufacturer may be selected. In further alternative the circuit shown in FIG. 5 may be utilized. While having general utility this circuit is particularly suited for typewriters like the Model Silver Reed EX55 by Seiko Ltd., Tokyo, Japan, characterized by fixed (time independent) row code -*- 8 and time base coded column format code M .-M . on the keyboard switching matrix. Once again, the data processor bus 53 provides the character data to a PROM 501 which periodically strobes its output into a latch 502. Latch 502 is connected by four of its output terminals to a decoder or data selector 503 which is also connected to the •M 1 -.-M 20 time code leads. Thus according to the 'character code a particular time code lead is selected to be applied to a NOR gate 504. Gate 504 then drives the I/O terminal of a one of eight encoder 505 which is addressed by a three bit signal from latch 502. Encoder 505 then produces an equivalent of signals R,-R g which is summed with these signals at a tap 506. In addition latch 502 produces an upper case signal collected at the input of a NOR gate 509 tied by its output to one of the output bit signals of encoder 505. The other signal collected at. gate 509 originates at a NAND gate 511 which at its input collects the output of a NAND gate 512 and one of the signals in the signal group ■ M *π~ κ 20* Gate 512 in turn,- collects the outputs of two one shot or delays 515 and 516, connected in series, the output of delay 516 being also tied to the input of gate 504. The foregoing delays are connected in circuit with a delay 517 which is .set off by the signal PR. Signal PR is again generated within the hand¬ shake stage containing the data processor 50 and the associated logic. While there are many logical configurations for a data processing system common to substantially all is the architecture of a data bus which in serial or parallel form transmits data and instructions. Thus in the examples set out herein the interface logic is illustrative only, it being understood that those skilled in the art will be able to mate a specific data processing system with the code conversion examples disclosed herein. It is to be further understood that the fore¬ going bus descriptions are exemplary only. Various other standardized bus systems may be similarly interfaced including the now popular S-100/IEEE 696 bus system. In each instance, however, eight bits of data are sufficient to identify the character selection and a discussion of the various other signal leads in the bus is therefore believed unnecessary. Furthermore, I/O addressing of the printer may or may not entail address recognition. Once again, depending on the processing system, either dedicated printer I/O ports may be available or direct printer wiring may be entailed. Accordingly, the example of a single AND gate for address filtering in FIG. 1 is illustrative only, it being the intent to disclose a conversion technique for transforming conventional code into a time based matrix code particular to this type of a keyboard. O PI J One may, furthermore, refer to the Repair Manual SE1010, SE5010 published by the Triumph-Adler Aktiengesellschaft, Further Strasse 212, D 8500 Nuruberg 80, West Germany for any further details of this typewriter, should such be desired. The inventive interface thus adapts any office typewriter of superior quality into a printer for data processing use, thus conserving the cost normally entailed in most commercially available word processing systems. This adaptation may be carried out in a separate enclosure thus allowing for convenient post market conversion which does not modify the heat distribution or electrical loading within the typewriter. One such adaptation is shown in FIG. 3. As shown in this figure, the processor " 50 includes its own keyboard BD and a display screen DS. These are typically included in most commercial data processing systems being required for effective use. When combined with the typewriter TYP the user is given the facility to operate the typewriter in its conventional mode or as a printer, without additional input. Thus the inventive interface 10 may be left dormant or may be operating depending on the task executed in the office. Obviously, many modifications and changes may be made to the foregoing description without departing from the spirit of the invention. It is therefore intended that the scope of the invention be determined solely on the claims appended hereto.

Claims: WHAT r CLAIMED IS 1. Apparatus for conforming a typewriter for use as a printer for a data processing system, said typewriter being characterized by a keyboard provided with manually articulated keys, a switching matrix of row and column conformation having a particular row and column coordinate for each said key, switching means rendered operative by said keys for closing an electrical path for each said row and column coordinate in correspondence with said keys, sequential interrogating means for sequentially inspecting each said row and column coordinate and binary code means connected to said interrogating means for producing a binary code corresponding to said row and column coordinate, comprising: *• emulating means connected to said data processing system and to said binary code means for producing switching signals in parallel with said switching means in correspondence with said interrogating means equivalent to said row and column coordinates according to data signals from said data processing system corresponding to said keys. 2. Apparatus according to Claim 1 wherein: said emulating means includes row and column encoders for producing an individual signal corresponding to each said binary code. 3. Apparatus according to Claim 2 wherein: said data processing system includes parallel signal means for.conveying data to said emulating means. 4. Apparatus according to Claim 2 wherein: said data processing system includes serial signal means for conveying data to said emulating means. 5. Apparatus according to Claim 1 wherein: said emulating means is housed separately from said typewriter and said data processing means. OMPI 6. Apparatus for conforming a typewriter for use as a printer for a data processing system, said typewriter being characterized by a keyboard provided with manually articulated keys, a switching matrix of row and column conformation having a particular row and column coordinate for each said key, switching means rendered operative by said keys for closing an electrical path for each said row and column coordinate in correspondence with said keys, sequential interrogating means for sequentially inspecting each said row and column coordinate and binary code means connected to said interrogating means for producing a binary code corresponding to said row and column coordinate, comprising: emulating means connected to said data processing system and to said binary code means for producing switching signals in parallel with said switching means in correspondence with said interrogating means equivalent to said row and column coordinates according to data signals from said data processing system corresponding to said keys, said emulating means including a decoder receiving the sequential output signals from said interrogating means and character signals from said data processing system for producing a strobe signal upon a coincidence therebetween and an encoder for directing said strobe signal. 7. Apparatus according to Claim 6 wherein: said emulating means includes row and column encoders for producing an individual signal corresponding to each said binary code. 8. Apparatus according to Claim 7 wherein: said data processing system includes parallel signal means for conveying data to said emulating means. 9. Apparatus according to Claim 7 wherein: said data processing system includes serial signal means for conveying data to said emulating means.

Inventors: LUTES BILL N, LUTES, BILL, N.
Applicants: LUTES BILL N, LUTES, BILL, N.
Application year: 1983
Main classification: G06F3
IPC codes: B41J5, G06F3