DEVICE FOR ENCIPHERING DIGITAL SIGNALS COMPRISING ONE OR MORE DES CIRCUITS

Abstract: Circuit provided with a number of data encryption standard circuits (DES). In order to obtain a greater interac­ tion between the key bits and the data bits, at least two DES are connected in series, and a number of bits of the output of a first DES is directly supplied to the input of a second DES, which number of bits is at the same time added modulo 2, modulo 4 to the bits of an equal number of other outputs of the first DES. Even if the same key should be supplied to both DES and if, due to an operating error, the first DES should have been set to encipher and the second DES should have been set to decipher, the clear text will be prevented from appearing at the output. At the same time a good protection against so-called weak keys is obtained.

Description: Device for enciphering digital signals comprising one or more DES circuits. As Background of the invention 1. Domain of the invention The invention relates to a device for enciphering or deciphering digital signals comprising at least one data encryption standard unit (DES). The working of such DES is described in greater detail in reference D1. Encipher units are mainly utilized in data connections allowing the relatively simple interception of data traffic, as it is the case for example with microwave radio relay links, and in connections for the transmission of information the content of which may absolutely not become known. Consequently, said data encryption standard units have been amply utilized for the purpose described, in which case the data signal to be transmitted is enciphered at the transmitting end with the help of a DES by means of one of 256 different keys, whereas it is deciphered at a receiving end by means of the same key. 2. State of the art In reference D2 it has already been pointed out that the 56-bit key is too small, in the sense that the key used can be found out relative 256 ly quickly by testing out each of-the 256 keys on a data signal intercepted, and that multiple enciphering can offer a solution in this case. In reference D3 it is pointed out, however, that double enciphering does not lead to the certainty meant. This is caused inter alia by the fact that there are so-called weak keys, as described in reference D4, but it may also occur that errors are committed when setting the encipher/decipher modes of the two DES applied. In both cases it may occur that double enciphering will lead to the transmission of the original or clear text. B. Summary of the invention One of the objects of the present invention is to provide a simple device for the multiple encipherment of a data signal in a reliable and economical way, in such a manner that even the so-called weak keys can be used without running the risk of an unintentionally too quick deciphering, which might be the result of for example the testing-out process. The invention is based on the idea that the interaction between all the key bits and all the data bits can be increased considerably in a simple N and surprising way by a modulo-2 addiction, in which N = a whole number to a maximum of half the number of bits that have to be added modulo 2 each time. For this purpose the device according to the invention is N characterized by means for adding modulo 2 a number of bits, which number is smaller than or equal to half the number of bits of a signal enciphered, to a number of other bits of a signal enciphered, and to supply the signal thus formed to the same DES or to another DES. In this way it is attained that, even if a DES is incorrectly set, the chance that during an enciphering process the clear text will be transmitted is considerably reduced. Moreover, it is out of the question that the key applied can be found by means of testing out by modern computers in a time shorter than some days. C. Brief description of the drawing The invention will now be further elucidated with the aid of the drawing in which is represented by Fig. 1 a connecting diagram of a data encryption standard (DES) Fig. 2 a known series circuit of two DES units Fig. 3 a block diagram of a series circuit according to the invention of two DES-units Fig. 4 a preferred embodiment of the circuit according to Fig. 3 Fig. 5 a variant of the circuit according to Fig. 3 Fig. 6 a truth table of the circuits 19 and 20 of Fig. 5 Fig. 7a an elaborate series circuit of two DES-units with interaction per byte with b a time diagram Fig. 8 a block diagram of a circuit with four DES-units Fig. 9 a block diagram of a circuit with four DES-units according to the invention Fig. 10a an elaborate diagram of a circuit according to the invention with four DES-units with interaction per block of eight bytes with b a circuit diagram Fig. 11 a block diagram of a circuit according to the invention provided with a microprocessor. D. References 1. FIPS PUB 46 of January 15, 1977. Publisher: US Dept. of Commerce/National Bureau of Standards. 2. Diffie, W. et al: Exhaustive cryptanalysis of the NBS data encryption standard. Journal: Computer; June 1977; pp. 74-84. 3. Merkle, R.C. et al: On the security of Multiple Encryption. Journal: Communications of the ACM July 1981; Volume 24; no. 7 pp. 465-467. 4. D.W. Davies: Data security in networks. Sixth data communications symposium at Asilomar Cal. USA November 26, 1979. Publisher: IEEE New York NY USA. E. Description of the embodiments Fig. 1 shows a connecting diagram of a DES in which a data signal of eight bytes each having eight bits can be supplied to an octuple input 1. Every time a reading-in command is supplied to an input 2 one byte of the signal to be enciphered is read in at the input 1, and one byte of a key is read in at an octuple input 3. The enciphering or deciphering process takes place after the reading in of the eight bytes at the inputs 1 and 3. A control signal at an input 4 determines whethersthe DES enciphers or deciphers. Every time a command is given at an input 6, one byte of the eight bytes enciphered is supplied via an octuple output 5. The working of a DES is generally known and is further described in reference DI. An improvement of the circuit according to Fig. 1 is formed by the circuit according to Fig. 2, which is already known and in which two DES units 7 and 8 are connected in series (see reference D3). The improvement according to the present invention is indicated in the block diagram according to Fig. 3, in which at the octuple input 1 of the DES unit 7 a block of eight bytes is read in in the way as described above. The bytes enciphered are supplied one by one to four-wire outputs 9 and 10, after which the signals of the output 9 are added modulo 2 to the signals of the output 10 by means of 1, 2, 3 or 4 EXOR-gates 11 before being supplied to the DES unit 8 via an input 12. The same key as supplied to the input 3 of the DES unit 7 or another key can be supplied to the input 3 of the DES unit 8. Fig. 4 shows an example of the connections between the two DES units 7 and 8. It is self-evident that every other suitable wiring sequence will suffice. A corresponding circuit is utilized for the decipherment at the receiving end. Fig. 5 shows an embodiment for a modulo-4 addition. The signals of the conductors 13 and 14 are added modulo 4 to those of the conductors 15 and 16 via the modulo-4 adders 19 and 20, respectively. The truth table for these adders is shown by Fig. 6. A modulo-8 addition can be realized in the same ways as described above. N Each of the embodiments described relates to a modulo-2 addition within one byte. A more complex variant is shown by Fig. 7, in which Fig. 7a represents a circuit for the modulo-2 addition of the bits of two bytes. Because of the fact that the bytes are read from the DES 7 on a time division basis, an intermediate store 21 is used. Fig. 7b shows the appurtenant circuit diagram for the various functions. A first byte is read out via the octuple output of the DES 7 and'supplied via an octuple switch S1 in position b to the intermediate store 21 and read in by the energization of an input 22. At the same time a readingout input 23 is energized, so that the byte will be supplied to the DES 8 via an octuple switch S2 in position b. After this the switches and S2 are switched to positions a, a second byte is added to the DES 8 via the octuple EXOR-gate 9, and the first byte registered in the intermediate store 21 is added modulo 2 to said DES 8. In the same way the third byte is added modulo 2 to the fourth byte, the fifth byte to the sixth byte and so forth. It is self-evident that here too modulo 4 and 8 additions and every combination of bytes are feasible. The effect of each of the circuits described above is that the number of key combinations will be increased, and owing to the interaction caused by the EXOR-gates, they each offer a considerably better protection against weak keys and control errors than could be obtained by using the devices known so far. A more complex way of combining DES units is shown by Fig. 8, in which the series chains of Dex units 25 and 26 on the one hand and those of DES units 27 and 28 on the other hand are connected in parallel. Via an input 24 one or more bytes are alternately supplied to each of the two chains. After the enciphering process the bytes enciphered are alternately led from each of the chains to an output 29 in the same rhythm. Various keys k can be supplied to the DES units 25, 26, 27 and 28. An improvement will be attained by the embodiment according to Fig. 9, where interaction takes place between the cipher texts of 25 and 27 by making use of interaction, as described before, by means of EXOR-gates 30 and 31. Here too the byte - by - byte encipherment can take place in the same way as described with the help of Fig. 7: this is represented by the more detailed diagram of Fig. 10a with the appurtenant time diagram of Fig. 10b. Here stores 32 and 33 serve again for registering a byte, and the octuple EXOR-gates 34 and 35 serve for the modulo-2 addition. It is obvious that the embodiments described above can be combined in an almost unlimited way without getting outside the scope of the present invention. All the solutions mentioned have the advantage that by concatenating standard DES units and EXOR functions a considerably better protection against the testing out of the key possibilities of the signal to be transmitted will be obtained. Fig. 11 shows a circuit connected with a microprocessor 36. A signal to be enciphered, which is supplied to an I/O unit 37, is led byte by byte into a DES 38 by the microprocessor 36. At the same time the microprocessor 36 reads a first key from a store 39. After the first encipher N ing process the signal enciphered is added modulo 2N by the micro- processor 36 in the way as described above. The signal thus formed is supplied again to the DES 38 and enciphered once more by means of the same key or by means of another key, which is also registered in the store 39. The store 39 comprises a read-only-memory part (ROM), in which the procedure and the various processes are stored, as well as a read/ write part (e.g. nAN) for storing the results of the various processes.

Claims: F. Claims 1. Device for enciphering or deciphering digital signals comprising at least one data encryption standard unit (DES), characterized by means for adding modulo 2N a number of bits, which number is smaller than or equal to half the number of bits of a signal enciphered, to a number of other bits of a signal enciphered, and to supply the signal thus formed to the same DES or to another DES, 2. Device in accordance with claim 1, characterized in that, a first part of the number of bits of a signal enciphered by a first DES is N added modulo 2N to another part and the signal thus formed is supplied to a second DES. 3. Device in accordance with claim 1, characterized by four DES, which are connected in parallel in two series branches of each two DES, a first part of the number of bits of a signal enciphered by a first DES in a first series branch of said two series branches being added modulo 2N to a first part of the number of bits of a signal enciphered by a first DES in the second series branch, and another part of the bits of a signal enciphered by the first DES of the second series branch being added modulo 2N to another part of the bits of a signal enciphered by the first DES of the first series branch.

Inventors: OBERMAN, MAARTEN ROELOF
Applicants: STAAT DER NEDERLANDEN (STAATSBEDRIJF DER POSTERIJEN, TELEGRAFIE EN TELEFONIE)
Application year: 1983
Main classification: H04L9
IPC codes: H04L9, G09C1