SEMICONDUCTOR MEMORY DEVICE

Abstract: A static type semiconductor memory device comprises a boosting circuit (11) for boosting a power source voltage (V cc ), a switch circuit (12) which selects the power source voltage (V cc ) in an operation mode while selecting a boosted voltage (V ccx ) from the boosting circuit (11) in a wait mode, and a static semiconductor memory cell (13) which receives the voltage selected by the switch circuit (12), as a power source voltage (V ccs ).

Description: Semiconductor memory device This invention relates to a static type semiconductor memory device. Fig. 1 shows a circuit diagram of a general semiconductor memory device. In the figure, reference numerals 1 and 2 respectively designate MOS (metal oxide semiconductor) transistors constituting a flipflop 7; numerals 3 and 4 indicate MOS transistors serving as transfer gates; and numerals 5 and 6 are high resistance elements as loads. Vcc denotes a power source voltage and Vss a reference voltage, which is ground in this instance. BL and bh denote bit lines (data input/output lines), respectively, and WL indicates a word line. The memory cell thus arranged employs a commercial power source of approximately 100 V for supplying the power source voltage Vcc in an operation mode, i.e. a read mode or a write mode. The memory cell is supplied with a voltage which is formed by dropping the commerical power source voltage to about 5 V via a transformer. For merely holding the stored data, i.e., wait mode, the power source voltage Vcc is switched from the commerical power source to a battery of approximately 2.5 V. This is called a battery back-up system and is widely used for data-holding in this field. In the static type semiconductor memory device, a specific data error, called a soft error, has recently become a focus of concern. This phenomenon arises from alpha particles emitted from radioactive impurities contained in the material of the package or the memory chip, for example, U and Th. When the alpha particles enter the memory chip, electron-hole pairs are generated and a current from these pairs flows into data-storing nodes, resulting in destruction of data stored in those nodes. The soft error problem has always been thought to be inherent only in dynamic type semiconductor memory devices, CCDs (charge coupled devices), and the like. However, recent research on soft errors shows that static type semiconductor memory devices also suffer from this undesirable phenomenon. The soft error observed in the static type semiconductor memory device will be described referring to Fig. 1. When the alpha particles enter a memory chip, and the electron-hole pairs are generated in the memory chip, a current due to the electron-hole pairs flows through the memory cell to pull down the potential on a high potential node of the flip-flop 7 (either of the output nodes N1 or N2 of the MOS transistors 1 and 2), thereby destroying the logical state "1" or "0" of the flip-flop 7. In this way, the stored data is destroyed, i.e., a soft error occurs. The nodes N1 and N2 of the flip-flop 7 are connected to the power source voltage Vcc through the high resistance loads 5 and 6. Therefore, when the electrons instantaneously flow into the high potential node as the result of alpha particle irradiation, the high potential node is equivalent to a floating state. The capacitance on the nodes of the static type semiconductor memory device is smaller than that of the dynamic type semiconductor memory device. Therefore, the soft error problem in the static type semiconductor memory device is more serious than in the dynamic type semiconductor memory device. The applied voltage, when the semiconductor memory device is backed up by the battery in a wait mode, is generally about 2.5 V. The quantity of charges stored in the data storing node is reduced by half, as compared with that when the semiconductor memory device is in an operation mode with an applied voltage of approximately 5 V. Therefore, the semiconductor memory device is more sensitive to the alpha particles when it is in the battery back-up mode. This implies that the sensitivity of the static type semiconductor memory device to alpha particles is greatly determined by the sensitivity of the semiconductor memory device when it is in a battery back-up mode. Consequently, in order to solve the soft error problem, it is necessary to render the semiconduc tor memory device more insensitiv & to alpha particles when it is in a battery back-up mode. Accordingly, an object of the present invention is to provide a static type semiconductor memory device which is substantially free from soft errors, with a considerably lessened sensitivity to alpha particles, particularly in a battery back-up mode. According to the invention, there is provided a static type semiconductor memory device comprising means for boosting a power source voltage, and a static memory cell for receiving the output voltage from said boosting circuit as a power source voltage. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a circuit diagram of a conventional static type semiconductor memory cell; Fig. 2 shows a practical arrangement of an embodiment of a semiconductor memory device according to this invention; Fig. 3 shows an arrangement of a boosting circuit incorporated into the semiconductor memory device of Fig. 2; Fig. 4 shows a circuit diagram of a switch circuit incorporated into the semiconductor memory device of Fig. 2; Fig. 5 shows an arrangement of a power source circuit of the boosting circuit shown in Fig. 3; and Fig. 6 shows an arrangement of another embodiment of a semiconductor memory device according to this invention. Referring to Fig. 2, there is shown an embodiment of a static type semiconductor memory device according to this invention. In the figure, reference numeral 11 designates a boosting circuit which receives the power source voltage Vcc and boosts it to an output voltage Vccx; numeral 12 indicates a switch circuit which receives the output voltage Vccx from the boosting circuit 11 and the power source voltage Vcc and selects one of those voltages; and numeral 13 is a static type semiconductor memory device which receives the selected power source voltage VCCS from the switch circuit 12 as a power source voltage. The boosting circuit 11 boosts the power source voltage Vcc of 2.5 V, for example, to a voltage of 4 V, for example. This circuit will be described in detail later with reference to Fig. 3. The switch circuit 12 is comprised of two input terminals 14 and 15 and a select contact 16, as schematically illustrated in Fig. 2. The details of this circuit will be given later referring to Fig. 4. The input terminal 14 receives the output voltage Vccx from the boosting circuit 11 and the input terminal 15 receives the power source voltage Vcc. The select contact 16, selectively coupled to the input terminals 14 and 15, selects either the output voltage Vccx or the power source voltage Vcc. The select contact 16, constituting a power source terminal of the switch circuit 12, is connected to a power source terminal TS. The output voltage Vccx or Vcc selected by the switch circuit 12 is applied as a power source voltage Vccs to the semiconductor memory cell 13. The semiconductor memory cell 13 is composed of a pair of enhancement type N-channel MOS transistors 18 and 19, enhancement type N-channel MOS transistors 20 and 21 as transfer gates, and high resistance elements 22 and 23 as loads. The gate of the MOS transistor 18 is connected to the drain of the MOS transistor 19. The gate of the MOS transistor 19 is connected to the drain of the MOS transistor 18. The sources of both the MOS transistors 18 and 19 are connected to the reference voltage Vss, which is ground in this instance. The drain of the MOS transistor 18 is connected to the power source terminal TS via the load 22; The drain of the MOS transistor 19 is likewise connected to the power source terminal TS via the load 23. A MOS transistor 20 as a transfer gate is inserted between the drain of the MOS transistor 18 and the bit line BL. Inserted between the drain of the MOS transistor 19 and the bit line BL is a MOS transistor 21 as a transfer gate. The gates of the MOS transistors 20 and 21 are both connected to the word line WL. In the memory cell with such an arrangement, the drains of the MOS transistors 18 and 19 provide data-storing nodes N18 and N19, respectively. In the write mode, the word line WL is selected, i.e., it is logical "1". Then, the gates of the MOS transistors 20 and 21 are opened, so that the data of logical "1"- or logical "0" is written from the bit line BL or BL to the node N18 or N19, through the transfer gate MOS tran sistor 20 or 21. The operation of the semiconductor memory device thus constructed will now be described. In the operation mode, the commerical power source is used for the power source of this semiconductor memory device. A 5 V voltage formed by dropping the commerical power source voltage is used for the power source voltage Vcc. The 5 V voltage is applied to the power source terminal of the boosting circuit 11 and the input terminal 15 of the switch circuit 12. In an operation mode, the select contact 16 of the switch circuit 12 is connected to the input terminal 15, and the power source voltage Vcc is thereby selected. Then, the power source voltage Vcc of approximately 5 V is directly applied as the power source voltage Vccs to the power source terminal TS of the semiconductor memory cell 13. In this condition, the word line WL is selected, that is, it has a logical state of owl". As a result, data of logical "1" and "0" or logical "O" and "1" are respectively written into or read out from the nodes N18 and N19 through the bit lines BL and BL and the transfer gate MOS transistors 20 and 21. In the wait mode, the power source is switched from the commerical power source to the battery, so that the battery supplies a voltage of approximately 2.5 V as the power source voltage Vcc. Then, the select contact 16 of the switch circuit 12 is connected to the input terminal 14 to select the output voltage Vccx from the boosting circuit 11. The result is that the output voltage Vccx from the boosting circuit 11 is applied as the power source voltage Vccs to the power source terminal Ts of the semiconductor memory cell 13. As described above, the boosting circuit 11 is used to boost the power source voltage Vcc from approximately 2.5 V to approximately 4 V. This will be discussed in more detail later. Thus, the boosted output voltage Vccx of approximately 4 V is applied to the power source terminal TS of the semiconductor memory cell 13 as the power source voltage Vcc. The rate of soft error occurrence was measured using the conventional memory cell as shown in Fig. 1. In this measurement, alpha particles are radiated onto the memory chip while the semiconductor memory device is in a wait mode. The measured results showed that when the power source voltage Vcc of approximately 4 V was applied, the rate of soft error occurrence was considerably reduced, as compared with the case where the power source voltage Vcc was approximately 2.5 V. These results also showed that the sensitivity of the semiconductor memory device of this embodiment when the approximately 4 V, for example, in the wait mode, was reduced to at least one-tenth that of the conventional semiconductor memory device. Fig. 3 shows an example of the practical arrangement of the boosting circuit 11 in the semiconductor memory device of Fig. 2. Reference numeral 31 denotes a ring oscillator containing an odd number of inverters cascade-connected in a ring fashion (not shown). The power source voltage Vcc is applied to the ring oscillator 31. The ring oscillator 31 produces an output signal of the voltage Vcc and frequency f. The output terminal of the ring oscillator 31 is connected to one electrode of a capacitor C. The capacitor C receives at this electrode the output voltage of the frequency f. The other electrode of the capacitor C is connected to the source of an enhancement type N-channel MOS transistor 32 whose drain is connected to the power source voltage Vcc. The drain and gate of the MOS transistor 32 are interconnected. The drain of an N-channel MOS transistor of enhancement type is connected to the source of the MOS transistor 32. The source of the MOS transistor 33 serves as an output terminal from which the boosted output voltage Vccx is taken out. The gate of the MOS transistor 33 is connected to the drain thereof. A stray capacitance Cp is present between the source interjunction of the MOS transistor 32 with the MOS transistors 33 and the ground. In the boosting circuit thus arranged, the output voltage V is independent of the frequency f and is given as Vccx Vcc 2VT + C + Cp If the capacitance of the capacitor C is much larger than that of the stray capacitance Cp, equation (1) is rewritten as Vccx = 2(VCC - VT) (2) where V designates the threshold voltage VT of the MOS transistors 32 and 33. By designing the circuit of Fig. 3 in a manner such that equation (2) holds, the output voltage Vccx obtained is 4 V when the power source voltage Vcc = 2.5 V and the threshold voltage VT = 0.5 V. When V = 3 V and V = 0.5 V, the output voltage Vccx is 5 V. Fig. 4 shows a practical arrangement of the switch circuit 12. An N-channel depletion type MOS transistor 41 and an N-channel enhancement type MOS transistor 42 make up a first inverter 43. An N-channel depletion type MOS transistor 44 and an N-channel enhancement type MOS transistor 45 form a second inverter 46. The drain of the MOS transistor 41 is connected to the power source voltage Vcc and its source is connected to the drain of the MOS transistor 42. The gate of the MOS transistor 41 is connected to its source. The power source voltage Vcc is applied to the gate of the MOS transistor 42. The source of the MOS transistor 42 is connected to the reference voltage Vss ( V). The drain of the MOS transistor 44 is connected to the power source voltage Vcc and its source is connected to the drain of the MOS transistor 45. The gate of the MOS transistor 44 is coupled with the source thereof. The source of the MOS transistor 45 is connected to the reference voltage Vss. The gate of the MOS transistor 45 is connected to an output node N43 of the inverter 43, i.e. the interjunction between the MOS transistors 41 and 42. The source of a P-channel enhancement type MOS transistor 47 is connected to the power source voltage Vcc and its drain is connected to the drain of a P-channel enhancement type MOS transistor 48. The source of the MOS transistor 48 is applied with the output voltage Vccx from the boosting circuit 11. The junction between the MOS transistors 47 and 48 forms an output node N49 of the switch circuit 12, through which the power source voltage Vcc or Vccx selected by the switch circuit 12 is taken out as the power source voltage VcCs. The gate of the MOS transistor 47 is connected to the output node N43 of the first inverter 43. The gate of the MOS transistor 48 is connected to the output node N46 of the second inverter 46, i.e., the junction between the MOS transistors 44 and 45. The operation of the switch circuit 12 with such an arrangement will now be described. Assume now that the threshold voltage VT of the MOS transistor 42 is approximately 3 V, and the threshold voltages VT of the MOS transistors 45, 47 and 48 is approximately 0.5 V, -0.5 V and -0.5 V, respectively. In an operation mode, the applied power source voltage Vcc is 5 V. In this case, the MOS transistor 42 is turned on and the potential at the node N43 is O V. The MOS transistor 45 is turned off and the node N46 has a potential of 5 V. Further, the MOS transistor 47 is turned on and the MOS transistor is turned off. As a result, the switch circuit 12 produces the power source voltage VCC of approximately 5 V as the power source voltage Vccs through the MOS transistor 47. In the data hold mode, when the power source voltage Vcc is approximately 2.5 V, the node N43 is at 2.5 V since the MOS transistor 42 is off. Then, the MOS transistor 45 is on and the node N46 is at O V. Further, the MOS transistor 47 is off and the MOS transistor 48 is on. Consequently, the switch circuit 12 produces the power source voltage VCCS via the MOS transistor 48. In this case, the power source voltage Vccs is the output voltage Vccx of, for example, 4 V, from the boosting circuit 11. The voltages at the nodes N43, N46 and N49 against V are indicated below. Table 1 EMI10.1 <tb> VCC <SEP> <SEP> | <SEP> <SEP> N43 <SEP> | <SEP> <SEP> N46 <SEP> | <SEP> <SEP> N49 <SEP> (Vccs) <SEP> <tb> 5V <SEP> <SEP> OV <SEP> 5V <SEP> <SEP> Sv <SEP> <tb> 2.5 <SEP> V <SEP> 2.5 <SEP> V <SEP> O <SEP> V <SEP> 4 <SEP> V <tb> Turning now to Fig. 5, there is shown an example of the power source circuit used in the boosting circuit shown in Fig. 3. In this circuit arrangement, the ring oscillator 31 is coupled with the output voltage Vccp of a power source circuit 50, while in the Fig. 3 arrangement, the ring oscillator 31 is directly coupled with the power source Vcc. The circuit arrangement of Fig. 5 shows the boosting circuit 11 to operate only in the battery back-up mode. In Fig. 5, MOS transistors 51 and 54 are of N-channel and depletion type, and MOS transistors 52, 55 and 58 are N-channel and enhancement type. A MOS transistor 57 is of P-channel and enhancement type. The MOS transistors 5,1 and 52 make up an E/D (enhancement/depletion) inverter 53. The MOS transistors 54 and 55 likewise make up another E/D inverter 56. The MOS transistors 57 and 58 form a CMOS (complementary metal oxide semiconductor) inverter 59. The MOS transistor 51 is connected at the drain to the power source voltage VCC and at the source to the drain of the MOS transistor 52. The gate of the MOS transistor 51 is connected to its source. The MOS transistor 52 is connected at the source to the reference voltage Vss ( V), and at the gate to the power source voltage V The junction between the MOS transistors 51 and 52 provides an output node N53 of the inverter 53. The MOS transistor 54 is connected at the drain to the power source voltage Vcc and at the source to the drain of the MOS transistor 55. The gate of the MOS transistor 54 is connected to its source. The source of the MOS transistor 55 is connected to the reference voltage V55 and the gate thereof is connected to the output node N53 of the inverter 53. The junction between the MOS transistors 54 and 55 provides an output node N56 of the inverter 56. The MOS transistor 57 is connected at the source to the power source voltage Vcc and at the drain to the drain of the MOS transistor 58. The source of the MOS transistor 58 is coupled with the reference voltage V The gates of the MOS transistors 57 and 58 are both connected to the output node N56 of the MOS transistor 56. The junction between the MOS transistors 57 and 58 provides an output node N59 of the inverter 59, and also provides an output terminal of the power source circuit 50. The operation of the power source circuit 50 will now be described. It is assumed that the threshold voltage VT of the MOS transistor 52 is approximately 3 V, and that the threshold voltage VT of the MOS transistors 55 and 58 is approximately 0.5 V, and that of the MOS transistor 57 is -0.5 U. If the supplied power source voltage VCC is 5 V, the MOS transistor 52 is turned on and a potential at the node N53 is O V. Then, the MOS transistor 55 is turned off and a potential at the node N56 is 5 V. Accordingly, the MOS transistor 57 is turned off and the MOS transistor 58 is turned on. As a result, at the output node N59 the output power source voltage Vccp becomes the reference voltage Vss, and this reference voltage V55 is applied to the ring oscillator 31 as the power source voltage to the boosting circuit 11. Specifically, when the power source voltage Vcc is 5 V, O V is applied to the ring oscillator 31. The ring oscillator 31, and hence, the boosting circuit 11 will not operate. Then, the power supply system of the semiconductor memory device is switched to the battery back-up system. In this mode, the MOS transistor 52 is turned off and the node 53 has a potential of 2.5 V. The result is that the MOS transistor 55 is on and the node N56 is O V. In turn, the MOS transistor 57 is turned on and the MOS transistor 58 is turned off. In this condition, the output power source voltage Vccp is the power source voltage Vcc which is then applied to the ring oscillator 31. Thereby, the boosting circuit 11 is driven to operate. The output voltage Vccxr for example, 4 V, of the switch circuit 12 is applied to the memory cell. The voltages, which are applied to#the key points when the power source circuit 50 is operating as mentioned above, are listed below. Table 2 EMI12.1 <tb> <SEP> VCC <SEP> | <SEP> <SEP> N53 <SEP> N56 <SEP> N59 <SEP> (VCCP) <SEP> <tb> 5V <SEP> <SEP> OV <SEP> 5V <SEP> <SEP> OV <SEP> <tb> 2.5 <SEP> V <SEP> 2.5 <SEP> V <SEP> O <SEP> V <SEP> 2.5 <SEP> V <tb> When the power source circuit as mentioned above is used for the ring oscillator 31, the voltage applied to the ring oscillator 31 is 0 V when the power source voltage Vcc is 5 V. The result is that the ring oscillator 31, and hence the boosting circuit 11, does not operate. Thus, power saving is achieved. Fig. 6 shows another embodiment of a semiconductor memory device according to this invention. In this embodiment, the switch circuit 12, which is used in the embodiment of Fig. 3, is omitted. Further, the output voltage Vccx of the boosting circuit 11 is directly con nected to the #! power source terminal Ts of the memory cell 13. The remaining portion is the same as that of the Fig. 3 embodiment. No further explanation will be given and like reference numerals will be applied to like or equivalent portions. In this embodiment, the output voltage Vccx boosted by the boosting circuit 11 is always applied to the memory cell 13. When the power source voltage Vcc is 5 V in an operation mode, the output voltage YCcx, for example, 9 V, which is obtained by the boosting circuit 11 (VcCx = 2(Vcc - V ) = 9 V), is applied to the semiconductor memory cell 13. When the semiconductor memory device is battery-driven with the V of 2.5 V in the wait mode, the V of about 4 V boosted by the boosting circuit 11 is applied to the memory cell 13. Therefore, this embodiment can prevent the soft error in the same way as the Fig. 3 embodiment does. In the Fig. 6 embodiment, the output voltage Vccx of the boosting circuit 11 is applied as the power source voltage to the semiconductor memory cell 13. Accordingly, this embodiment does not need the power source circuit 50 as shown in Fig. 5 which supplies the 0 V output voltage in an operation mode. It should be understood that this invention is not limited to the above-mentioned embodiments. For example, the boosting circuit and the switch circuit may be replaced with any other circuits if these have the same functions as the former. As seen from the foregoing description, the boosting circuit used in this invention sufficiently boosts the low voltage source when the semiconductor memory device is backed up by the battery in a wait mode. The boosted power source is applied to the memory cell in the wait mode. Therefore, the data storage in this mode is highly reliable. Further, the semiconductor memory device of the invention is improved in its resistance to alpha particles and is thus substantially free from the soft error problem.

Claims: Claims: 1. A static type semiconductor memory device characterized by comprising: means (11) for boosting a power source voltage (Vcc); and a static memory cell (13) for receiving the boosted output voltage (VCCX) from said boosting means (11) as a power source voltage (VCCS). 2. A static type semiconductor memory device according to claim 1, characterized by further comprising switch means (12) provided between said boosting means (11) and said memory cell (13) and coupled with the power source voltage (vac) and the boosted output voltage (VcCx), said switch means (12) selecting the boosted output voltage (VCCX) in a wait mode while selecting the power source voltage (VCC) in an operation mode, the selected voltage being applied as the power source voltage (VACS) to said memory cell (13). 3. A static type semiconductor memory device according to claim 2, characterized by further comprising power source means (50) for said boosting means (11), wherein said power source means (50) stops the supply of an output power source voltage (VCcpJ and renders said boosting means (11) inoperative when said memory cell (13) is in an operation mode, while allowing the supply of the output power source voltage (VCCP) thereby operating said boosting means (11) in a wait mode. 4. A static type semiconductor memory device according to claim 1, characterized in that said memory cell (13) includes first and second MOS transistors (18, 19) in which the drain and gate of one of said MOS transistors are respectively coupled with the gate and drain of the other transistor, a first load element (22) which is connected at one end to the drain of said first transistor (18) and at the other end to the power source voltage (VcCs), and a second load element (23) which is connected at one end to the drain of said second MOS transistor (19) and at the other end to the power source voltage (VCCB). 5. A static type semiconductor memory device according to claim 4, characterized in that said first and second load elements (22, 23) are resistors. 6. A static type semiconductor memory device according to claim 2, characterized in that said memory cell (13) includes first and second MOS transistors (18, 19) in which the drain and gate of one of said MOS transistors are respectively connected to the gate and drain of the other MOS transistor, a first load element (22) which is connected at one end to the drain of said first MOS transistor. (18), and at the other end to the power source voltage (VcCs), and a second load element (23) which is connected at one end to the drain of said second MOS transistor (19) and at the other end to the power source voltage (vCcs). 7. A static type semiconductor memory device according to claim 2, characterized in that said first and second load'elements (22, 23) are resistors.

Inventors: FURUYAMA, TOHRU
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1983
Main classification: G11C5
IPC codes: G11C11, G11C5