SEMICONDUCTOR DEVICE WITH A PASSIVATED JUNCTION

Abstract: In a semiconductor device the perimeter of a base-­ emitter junction (J f ) at a surface is protected by a film of silicon nitride (11), preferably formed by a direct nitridation process. A base contact electrode (8) is made of highly doped polysilicon, the surface of which is thermally oxidised to form a silicon dioxide layer (9) which terminates on the silicon nitride film (11) and which separates the base contact electrode (8) from an emitter contact electrode (10). Such a device can be fabricated in a self-alignment fashion using only one lithographic mask to form base and emitter regions and corresponding contacts.

Description: A SEMICONDUCTOR DEVICE The present invention relates to a semiconductor device. figure 1 is a schematic cross-sectional view of an Iso planar self-aligned transistor as previously fabricated. An Iso planar transistor is an oxide isolated planar transistor which has a buried layer for connecting the collector operationally to the collector electrode on the surface of the device, or to other circuit elements (not shown). Figure 1 shows only significant parts of the self-aligned transistor structure. In Figure 1, 1 is a p type silicon substrate, 2 is a n type buried layer, 3 is a collector region made of a n type epitaxial layer grown on the buried layer. 4 is a field oxide layer, 5 is a p (highly doped with p type conductivity impurities) type base contact region, 6 is a p type active base region, 7 is a n (highly doped with n type conductivity impurities) type emitter region, 8 is a p type base electrode made of polysilicon (polycrystal silicon), 9 is a thermal oxide layer of polysilicon, and 10 is an emitter electrode. As can be seen in Figure 1, the periphery of the base-emitter junction, indicated by Jf, is terminated at the edge of thermal oxide layer 9, which separates the emitter electrode 10 from the polysilicon base contact 8. A thermal oxide layer of polysilicon is porous, and its surface state is unstable compared to that of a chemically deposited oxide layer or of a silicon nitride film. Hence a slight leakage current or a degradation of break down voltage between the emitter and the base inevitably occurs for the self aligned transistor of Figure 1. There are also problems of production yield and device reliability. Similar problems can arise in other types of transistor, affecting stability. According to one aspect of the present invention there is provided a semiconductor device, comprising an active base region, an emitter region formed in the active base region, to provide a base-emitter junction having a perimeter at a surface in the device, characterised by a silicon nitride film formed on the surface to cover the perimeter of the base-emitter junction. According to another aspect of the present invention there is provided a method of fabricating a semiconductor device having an emitter electrode separated from a base contact electrode, of polycrystal silicon, by a thermally oxidised silicon polycrystal layer ; the method comprising the following steps: : a) coating a surface of a first conductivity type region of the device with a first silicon nitride film; b) forming, in turn, on the surface of the first silicon nitride film a first silicon dioxide film and a second nitride film; c) patterning the second silicon nitride film to expose a part of the first silicon dioxide film; d) etching off the exposed part of the first silicon dioxide film, to thereby expose part of the first silicon nitride film, at the same time side etching the first silicon dioxide film beneath the patterned second silicon nitride film; e) etching off the exposed part of first silicon nitride film which is not beneath the patterned second silicon nitride film; ; f) providing a highly doped silicon polycrystal layer of a second conductivity type on the surface of the patterned second silicon nitride film and on surface parts of the said device region that are exposed in step g) etching off the remainder of the first silicon dioxide film, at the same time liftinq off the patterned second silicon nitride film and the part of the silicon polycrystal layer thereon; h) providing by thermal oxidation a silicon dioxide layer on the surface of the remaining part of the silicon polycrystal layer and terminating on the first silicon nitride film, at the same time diffusing impurities from the silicon polycrystal layer into the said device region of the first conductivity type, to provide a base contact region of the second conductivity type; ; i) selectively implanting impurities of the second conductivity type, by ion implantation, through the first silicon nitride film, into said device region using as a mask the silicon polycrystal layer having the thermal oxidised silicon dioxide layer thereon; j) selectively etching off the first silicon nitride film where exposed by the silicon polycrystal layer having the thermally oxidised silicon dioxide layer thereon; k) selectively implanting impurities of the first conductivity type by ion implantation into the zone of the said device region where impurities of the second conductivity type were implanted in step i) using as 2 mask the silicon polycrystal layer having the thermal oxidised silicon dioxide layer thereon; and 1) annealing the ion implanted impurities of first and second conductivity types, by heat treatment, to form an active base region of the second conductivity type and an emitter region of the first conductivity type. An embodiment of one aspect of the present invention can provide a semiconductor device the performance of which is stable and the production yield of which is high. An embodiment of another aspect of the present invention can provide a method of fabricating such a device. Embodiments of the present invention are applicable to bipolar transistors, and are particularly effective for self-aligned planar transistors, base contact electrodes of which are made from silicon polycrystal material. A transistor fabricated in accordance with an embodiment of the present invention has a self aligned base electrode, base contact area, active base region and an emitter region. It offers improvement as regards the passivation of the base-emitter junction, at its periphery at the surface of a substrate of the transistor. Embodiments of the present invention are applicable to semiconductor devices which use any type of isolation technique, such as conventional, Iso planar or LOCOS (Local Oxidation of Silicon) isolation for example. Embodiments of the present invention are particularly applicable for stabilising the performance of self-aligned transistors. A self-aligned transistor is a transistor whose emitter or base is fabricated using a self-alignment technique. For example, the base and emitter (in many cases the contact electrodes for the base and emitter also) are fabricated using a single lithographic mask. It is necessary neither to use a specific mask for each of electrode nor, therefore, to align such masks precisely one with respect to another. It is relatively easy to fabricate a very fine or small transistor using a self-alignment technique, and fabrication costs are relatively reduced. Reference is made, by way of example, to the accompanying drawings, in which: Figure 1 is a schematic cross-sectional view of main parts of a self-aligned transistor as previously fabricated, Figure 2 is a schematic cross-sectional view of main parts of a transistor embodying the present invention, and Figure 3(a) to (i) are schematic cross-sectional views illustrating stages in a method of fabricating a transistor in accordance with an embodiment of the present invention. In Figure 2, which shows a transistor embodying the present invention, parts like or corresponding to parts in Figure 1 are designated by the same reference numerals. As compared with Figure 1, the transistor of Figure 2 is provided with a silicon nitride film 11, covering the periphery of base-emitter junction Jf. The silicon nitride film is dense and stable as compared with thermally oxidised polycrystal silicon. Moreover a silicon nitride film, chemically deposited from pure material, does not contain the dopant (impurity) which is contained in the base contact electrode material (polycrystal silicon). The state of the surface covered by silicon nitride film is inherently more stable than the state of that surface (not covered by silicon nitride film) in the transistor of Figure 1, and improvements are afforded in respect of the leakage current and the break down voltage between base and emitter. The transistor of Figure 2 is an iso-planar self-aligned bipolar transistor. Concerning self-alignment attention is directed to, for example, U.S.Pat. No. 4,157,269 issued to T.H.Ning, H. N.Yu on June 5, 1979; and IEEE vol.ED-28, No.9. 1981, PP.1010- 1013 by T.H.Ning et al. In the transistor of Figure 2, the silicon nitride film 11 covers and protects the periphery of the base-emitter junction Jf from the porous silicon dioxide layer 9 of polycrystal silicon material (polysilicon) at the surface of substrate. In more detail, the transistor of Figure 2 is fabricated with a n type collector region 3, which is made of a n type epitaxial layer, separated from neighboring regions (not shown) by a field oxide layer 4. In the upper part of the collector region 3, a p type base contact area 5, the depth of which is about 4000- to 5000 A , a p type active base region 6, the thickness of which is about 3000 A , and a n+ type emitter region 7, the depth of which is about 2000 A , are formed using conventional self-alignment techniques. A thin silicon nitride (Si 3N4) film 11, the thickness of which is 100 to 200 AO for example, is fabricated so as to cover the perimeter of base-emitter junction Jf formed between the p type active base region 6 and the n type emitter region 7. Silicon dioxide layer 9 of thermally oxidised polycrystal silicon material (polysilicon) terminates on the film 11. This layer 9 is formed at the surface of polysilicon layer 8, which latter layer is highly doped with p type conductivity impurity to form a base contact 8. The ' silicon dioxide layer 9 separates emitter electrode 10, which is formed of aluminium for example, on the surface of the n emitter region 7, from the above-mentioned polysilicon base electrode 8. In Figure 2, 1 and 2 are a p type silicon substrate and a n type buried layer respectively. Figure 2 shows only main parts of the transistor for the sake of simplicity. A collector contact, for example, is not shown in the Figure. Such a contact would be fabricated in a proper position outside of Figure 1 by conventional Iso planar technology. It should be also added that although Figure 2 and the explanation thereof refer to the use of a p type substrate as an example, substrates of a different conductivity type can be used provided that the dopants and materials of base and emitter are altered to afford conductivity types opposite to those mentioned in the above explanation. This applies also to the explanation given below concerning Figures 3(a) to (i). A method of fabricating a transistor in accordance with an embodiment of the present invention will now be explained with reference to Figure 3(a) to (i). In this case, as in an ordinary process for fabricating an Iso -planar transistor, a p type silicon substrate 1 is used, as shown in Figure 3(a). On the substrate 1, a n type buried layer 2 and n type epitaxial layer 3' are formed in order, respectively by diffusion and epitaxial growth. The epitaxial layer 3' is separated from neighboring such layers (not shown) by a field oxide layer 4. Sometimes a n collector contact region is fabricated in the separation region (the field oxide layer region in Figure 3(a)) in order to operationally connect the buried layer 2 to a collector contact fabricated on the surface of device. However, details of such an arrangement are omitted from the Figures for the sake of simplicity. The substrate is then treated in ammonia gas (HNO3) at a pressure of about 0.1 to 10 Torr and a temperature of about 1050 0C for about 100 to 200 minutes, under the application of high frequency power at about 13.56 MHz. This treatment is called a direct nitridation process. More details of such a process are disclosed in "Semiconductor Technologies" (pp. 69 to 81) by T. Ito, published by Ohm & North Holland, 1982. By this treatment, a thin silicon nitride film 11, the thickness of which is 100 to 200 A , is formed on the exposed silicon surface (the exposed surface of layer 31) as shown in Figure 3(b). This direct nitrided silicon 11 is called hereinafter a first silicon nitride film. Next, by conventional chemical vapour deposition, a first silicon dioxide (SiO2) layer 12, the thickness of which is about 3000 to 5000 A0 , and a second silicon nitride film 13, the thickness of which is about 300 to 1000 A , are deposited in order on the substrate, as shown in Figure 3(b). Next, as shown in Figure 3(b), by conventional photo-lithography, a predetermined resist pattern 14 is formed on the second silicon nitride film 13, at a place corresponding to a location where an emitter region is to be formed. It should be noted that the lithographic mask used for patterning the above-mentioned resist pattern 14 is the only mask necessary for the following processes. That is, the emitter and base regions of the transistor, their contact areas and contact electrodes, are all fabricated without need for further masks. Thus, mutual mask alignment is unnecessary , -the processes are self aligned. The second silicon nitride film 13, outside the resist pattern 14, is etched off by conventional reactive ion etching. By this process the first silicon dioxide film, outside the pattern 14, is exposed. This step is not specifically shown in the Figures. Then. making use of the thus patterned second silicon nitride film 13' as a mask, the exposed first silicon dioxide film is selectively etched off by wet eching as shown in Figure 3(c). For this etching, a process which causes side etching is preferable. To this end, wet etching for example by hydrofluoric acid (HF) is applicable. The above-mentioned etching process results in the first silicon dioxide film, where covered by the second silicon nitride film pattern 13', being side etched. The side-etched first silicon dioxide film can be seen at 12 in Figure 3(c). The width or extent of the side etching 16 (that is, the depth to which the first silicon dioxide film is laterally etched inwardly of second silicon nitride film 13' is approximately 3000 to 5000 A . By making further use of the resist pattern 14 on the second silicon nitride film or pattern 13' as a mask (in Figure 3 (c) the resist pattern 14 is omitted to avoid confusion), those parts of the first silicon nitride film 11 which are exposed (e.g. uncovered and unshadowed by the second silicon nitride pattern 13') are selectively etched off by reactive ion etching. Reactive ion etching is highly directive, and does not cause side etching to any substantial extent. Thus, the etched first silicon nitride film 11' is patterned by the etching to take a form corresponding in substance to that of the second silicon nitride pattern 13'. Then, the resist pattern 14 on the second silicon nitride pattern 13' is removed. This is shown in Figure 3(c). In the following process a region designated by the reference numeral 15 in Figure 3(c) becomes an active base region, and the first silicon nitride film or pattern 11' becomes a film which covers the surface of the base region. A polysilicon layer 8', the thickness of which is for for example 3000 to 5000 A is deposited as shown in Figure 3(d). By this deposition the second silicon nitride pattern 13' and areas outside that pattern (that is, the surface of epitaxial buried layer 3' outside the first silicon nitride pattern 11' , and the surface of the field oxide layer 4) are covered by polysilicon as shown in Figure 3(d). For depositing the polysilicon, it is desirable to use a process which does not result in lateral deposition (i.e. which does not result in deposition in areas of the deposition surface which are shadowed by an overlying layer) in order to prevent the over etched portion of the first silicon dioxide film 12 from being buried, as shown in the Figure 3(d). For this purpose a process for spattering or evaporating polysilicon material is for example applicable. Next, a high dose (about 1015 atm/cm2 ) of boron ions (B+) or ions of boron difluoride (BF+) are implanted in the polysilicon layer 8' by ion implantation, changing the polysilicon layer 8' to highly doped polysilicon. Next, the first silicon dioxide film 12 remaining between the two silicon nitride patterns 11' and 13' is removed by wet etching using, for example, hydrofluoric acid HF. By this etching process, the second silicon nitride pattern 13' and polysilicon 8' over the first silicon dioxide film 12 are lifted off. Thus, as shown in Figure 3(e), the first silicon nitride pattern 11' is exposed in an opening in highly doped polysilicon layer 8'. In a next process the substrate is heated in an oxide atmosphere (it may be dry or wet oxygen) at a temperature of approximately 10000 C. The surface of the polysilicon layer 8' is oxidized selectively to form a thermal oxide layer 9 of about 3000 to 5000 A thickness. At the same time the dopant implanted in polysilicon layer 8' (that is boron) is diffused into n type epitaxial buried layer 3' to form a p type base contact area 5, whose thickness is about 4000 to 5000 A as shown in Figure 3(f). Sometimes this type of diffusion is called as solid-to-solid diffusion. Next, boron is implanted through the first silicon nitride film 11 into the n type epitaxial layer 3', at 30 40 KeV to a dose of about 1014 atm/cmê . In this ion implantation process the thermal silicon dioxide layer 9 is used as a mask. The boron is implanted selectively into the n type epitaxial layer. In Figure 3(f) a hatched zone 6' indicates the region into which boron is implanted. Next, the first silicon nitride film 11', which is exposed in the region restricted by the thermal oxide layer 9, is selectively etched off, by reactive ion etching or by wet etching with heated phosphoric acid (H3PO4) for example. By this process, the first silicon nitride film 11' is left in place at the periphery of base contact area 5, as shown in Figure 3(g), terminating the silicon dioxide layer 9. Arsenic ions (As+), at a dose of about 1015 to 1016 atm/cm2 , are implanted into the upper region 7' of the boron implanted region 6', as shown in Figure 3(g). After the implantation, the substrate is annealed as usual for an ion implantation process. By this annealing, the implanted impurities (that is boron and arsenic) are redistributed. By the difference of the depth of the distribution, and the difference of the diffusion constant, of each dopant, a p type active base region 6, of which the depth is about 3000 A for example, and a n type emitter region 7, of which the 0 depth is about 2000 A , are provided. Also by this annealing each dopant is diffused so that the active base region 6 extends to contact the base contact area 5. The emitter region also extends to beneath the first silicon nitride film 11, as shown in Figure 3(h). Thus the base-emitter junction is protected under the silicon nitride film 11. Finally as shown in Figure 3 (i), an emitter contact electrode 10, made of silicon aluminium alloy for example, is fabricated on the emitter surface. The base contact electrode is provided by the highly doped silicon layer 8'. The base and emitter electrodes are separated from each other by the silicon dioxide layer 9. Though it is not. shown in the Figures and not explained in the above disclosure, a collector electrode and wirings therefor are fabricated each in proper position by conventional means, and a passivation film provided on the surface of the device. As can be seen from the above explanation, for fabrication of base, emitter , and their contact electrodes only the mask used for patterning the resist pattern 14 in Figure 3(b) is employed. No other mask is necessary. The electrodes are thus all self aligned. The method described with reference to Figure 3 is convenient for fabricating fine patterns for ICs, it gives a high manufacturing yield, and the base-emitter junction of a transistor is protected by silicon nitride film to stabilise performance and offer a high breakdown voltage. As can be seen in the above explanation relating to a self-aligned transistor embodying the present invention, the periphery of the base-emitter junction of the transistor is covered and protected by a silicon nitride film. Preferably, that film is deposited by a direct nitridation process. Such a direct nitrided silicon film contains substantially no impurities, so its surface state is stable. It is dense as compared to silicon dioxide film. Moreover, it is an excellent isolation film, being waterproof and chemically stable. Therefore, the present invention can provide a high quality and highly reliable self aligned transistor as compared with a self-aligned transistor as previously fabricated with a structure in which the periphery of base-emitter junction is covered by an oxide layer of porous polysilicon. It will be clear that embodiments of the present invention can be applied not only to Iso planar structure transistors but also to LOCOS isolation transistors and conventional diffusion isolated transistors. It can be applied to both npn and pnp type transistors. An embodiment of an aspect of the present invention provides a semiconductor device which comprises: a) -base contact area; b) active base region connected to said base contact area; c) emitter fabricated in said active base region; d) base contact electrode made of polycrystal silicon, fabricated on said base contact area; and e) silicon nitride film covering the periphery of base-emitter junction on the surface of substrate; said base and said emitter are isolated each other by surface oxidised layer of said of said polycrystal silicon base contact, and said oxide layer being terminated on said silicon nitride film.

Claims: CLAIMS 1. A semiconductor device, comprising an active base region (6), an emitter region (7) formed in the active base region (6), to provide a base-emitter junction (Jf) having a perimeter at a surface in the device, characterised by a silicon nitride film (11,11') formed on the surface to cover the perimeter of the base-emitter junction (Jf). 2. A device as claimed in claim 1, having a base contact area (5) connected to the active base region (6), a base contact electrode (8), of polycrystal silicon, formed on the base contact area, and an dioxide layer (9) formed by surface oxidation of the base contact electrode (8), for isolating the base contact electrode (8) from an emitter electrode (10), the oxide layer (9) terminating on the silicon nitride film (11,11'). 3. A device as claimed in claim 2, wherein the emitter region (7) is exposed at the said surface, surrounded by the nitride film (11,11') covering the perimeter of the base-emitter junction (Jf) , and the emitter electrode (10) contacts the emitter region (7) where exposed within the nitride film (11,11'). 4. A device as claimed in claim 3, wherein the base contact electrode (8) contacts the base contact area (5) outside the nitride film (11,11'). 5. A device as claimed in any preceding claim, in which the base contact area (5) is a self aligned base contact area. 6. A device as claimed in any preceding claim, in which the active base region (6) is a self aligned active base region. 7. A semiconductor device as claimed in claim 1, in which the emitter region (7) is a self aligned emitter region. 8. A device as claimed in any preceding claim, being a self aligned transistor. 9. A device as claimed in any preceding claims, being a silicon transistor. 10. A device as claimed in claim 9, wherein the nitride film (11,11') is formed by direct nitridation. 11. x method of fabricating a semiconductor device having an emitter electrode (10) separated from a base contact electrode (8), of polycrystal silicon, by a thermally oxidised silicon polycrystal layer (9); the method comprising the following steps: a) coating a surface of a first conductivity type region of the device with a first silicon nitride film (11); b) forming, in turn, on the surface of the first silicon nitride film (11), a first silicon dioxide film (12) and a second silicon nitride film (13); c) patterning the second silicon nitride film (13) to expose a part of the first silicon dioxide film (12); ; d} etching off the exposed part of the first silicon dioxide film (12), to thereby expose part of the first silicon nitride film (11), at the same time side etching the first silicon dioxide film beneath the patterned second silicon nitride film (13'); e) etching off the exposed part of first silicon nitride film which is not beneath the patterned second silicon nitride film (13'); f) providing a highly doped silicon polycrystal layer (8') of a second conductivity type on the surface of the patterned second silicon nitride film (13') and on surface parts of the said device region that are exposed in step e); etching off the remainder of the first silicon dioxide film, at the same time lifting off the patterned second silicon nitride film (13') and the part of the silicon polycrystal layer (8') thereon; ; h) providing by thermal oxidation a silicon dioxide layer (9) on the surface of the remaining part of the silicon polycrystal layer (8') and terminating on the first silicon nitride film (11'), at the same time diffusing impurities from the silicon polycrystal layer (8') into the said device region of the first conductivity type, to provide a base contact region (5) of the second conductivity type; i) selectively implanting impurities of the second conductivity type, by ion implantation, through the first silicon nitride Xile (1#'), into the said device region using as a mask the silicon polycrystal layer (8') having the thermal oxidized silicon dioxide layer (9) thereon; ; j) selectively etching off the first silicon nitride film (11') where exposed by the silicon polycrystal layer (8') having the thermally oxidised silicon dioxide layer (9) thereon; k) selectively implanting impurities of the first conductivity type by ion implantation into the zone of the said device region where impurities of the second conductivity type were implanted in step i) , using as a mask the silicon polycrystal layer (8') having the thermal oxidised silicon dioxide layer (9) thereon; and 1) annealing the ion implanted impurities of first and second conductivity types, by heat treatment, to form an active base region (6) of the second conductivity type and an emitter re#gion (7) of the first conductivity type. 12. A method as claimed in claim 11, wherein step a) is accomplished by a direct nitridation process. 13. A method as claimed in claim 11 or 12, wherein step b) is accomplished by chemical vapor deposition. 14. A method as claimed in. claim 11,12 or 13, wherein step f) is accomplished by evaporation or sputtering of polycrystal silicon. 15. A method as claimed in claim 11, 12, 13, or 14 in which the base contact region (5) is provided in step h) by a solid to solid diffusion process. 16. A method as claimed in any preceding claim, wherein the said device region is of silicon.

Inventors: GOTO, HIROSHI C/O FUJITSU LIMITED
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: H01L23
IPC codes: H01L29, H01L21, H01L23