MIS TRANSISTOR HAVING A DEPOSITED AND BURIED ISOLATION AND METHOD FOR MANUFACTURING THE SAME

Abstract: A MIS transistor having a deposited and buried isolation is disclosed. An element forming region (12) having a source region, drain region and channel region is formed in a semiconductor substrate (10). An insulating film (16) is deposited on and buried within the semiconductor substrate, in such a way as to surround the element forming region. A gate electrode (20) is formed on the channel region, through a gate insulating film (18). The gate electrode exists only on the element forming region, and the edge portion (44) in the direction of the channel width of the gate electrode is substantially aligned with the edge (46) of the element forming region.

Description: MIS transistor having a deposited and buried isolation and method for manufacturing the same This invention relates to a MIS transistor having a deposited and buried isolation, and a method for manufacturing the same. Japanese Patent Disclosure (KOKAI) No. 57-170547 discloses a MIS transistor having a deposited and buried isolation. As shown in Fig. 1, such a MIS transistor comprises: a semiconductor substrate 10 with an element forming region 12 formed therein; an insulating film 16 for isolating a device which is deposited and buried in a recessed portion 14 surrounding said device forming region 12; a gate insulating film 18; and a gate electrode 20. The gate electrode 20 is located on the insulating film 16 for isolating a device and has a gate fringe portion. In the case wherein the MIS transistor is miniaturized, for example; when the gate width becomes 1.0 pm or less, the inverse narrow channel effect indicated by curve a of Fig. 2 occurs. Due to this occurrence, a phenomenon wherein there is a reduced threshold voltage Vt may be observed, so that,the threshold voltage Vt cannot be suitably controlled. \ Furthermore, the existence of the gate fringe por f. tion will also interfere with an increase in the inte gration density of the device. In view of the above, U.S##. No. 4,160,987 and Japanese Patent Publication No. 57-1145 disclose FETs with nonoverlapping gates. However, the device isolation insulating film 14 of U.S.P. No. 4,160,987 is different from the present invention, since it is formed by thermal oxidization. When the device isolation insulating film 14 is formed by thermal oxidization, a bird's beak 22, such as that shown in Fig. 3, is formed. Thus, the narrow channel effect shown by the curve ss of Fig. 2 occurs. The present invention is intended to eliminate the inverse narrow channel effect, as indicated by the curve a of Fig. 2. One object of the present invention is to provide a MIS transistor in which no fluctuation of the threshold voltage occurs as a result of a decrease in the gate width. Another object of this invention is to provide a method of manufacturing a MIS transistor in which no fluctuation of the threshold voltage occurs as a result of a decrease in the gate width. These and other objects have been attained by the MIS transistor having a deposited and buried isolation, which comprises a semiconductor substrate, an element forming region formed on the semiconductor substrate, said element forming region having a source region, drain region and channel region, an insulating film deposited on and buried within the semiconductor substrate, to surround the element forming region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, said gate electrode existing only on the element forming region, the edge portion in the direction of the channel width of the gate electrode being substantially aligned with the edge of the element forming region. With a construction such as that mentioned above, the concentration of the electric fields at the corners of the element forming region is eliminated, so that the inverse narrow channel effect can be prevented. Therefore, the change in the threshold voltage Vt which results from a gate width can be eliminated. In addition, since no gate electrode exists in an element isolating region, the area of the gate electrode is reduced, causing the stray capacitance to be reduced. The reduction of the stray capacitance allows the switching time to be shortened, thereby enabling a high-speed operation. Furthermore, it is possible to prevent the formation of a weak inversion layer in the semiconductor substrate under the element isolation film. Thus, the cause of the leak current can be eliminated. Moreover, according to the present invention, since no gate electrode exists on the element isolating region, there is no need for a gap to prevent the contact between the gate electrodes of the adjacent transistors. As a result, the limitation given to the pattern design by the gate electrode is eliminated, which allows the device to be highly integrated. A method for manufacturing a MIS transistor having a deposited and buried isolation according to the present invention comprises the steps of: (1) forming a first insulating film on a semiconductor substrate; (2) forming a first conductive layer on said first insulating film; (3) sequentially etching the first conductive layer, first insulating film and semiconductor substrate to form a first conductive layer pattern, a first insulating film pattern and a recessed portion in the semiconductor substrate, respectively, thereby forming an element forming region; (4) forming a second insulating film on at least the recessed portion, by the CVD method; (5) forming a third insulating film on the second insulating film and the element forming region, thereby making the surface flat; ; (6) sequentially etching the third insulating film and the second insulating film, to expose the first conductive layer pattern, thereby forming an insulating film for isolating elements, this step being executed under conditions wherein the etching rates of the second and third insulating films are almost equal; and (7) etching the first conductive layer pattern and the first insulating film pattern to form a gate electrode and a gate insulating film, and further forming source and drain regions. If a MIS transistor is formed as described above, the gate electrode can be self-aligned with the element forming region. Therefore, even when no gate fringe is provided, the gate electrode can be completely bridged between the source and drain. Other objects and advantages may be understood from the following description, taken in conjunction with the accompanying drawings, in which: Fig. I is a cross-sectional view of a conventional MIS transistor; Fig. 2 is a diagram showing the relationship between a gate width and a threshold voltage in a conventional MIS transistor; Fig. 3 is a cross-sectional view of a conventional MIS transistor having an insulating film for isolating elements which is formed by thermal oxidization; Fig. 4 is a plan view of a MIS transistor according to the present invention; Fig. 5 is a cross-sectional view taken along line V-V of Fig. 4; Fig. 6 is a cross-sectional view taken along line VI-VI of Fig. 4; Fig. 7 is a cross-sectional view showing a modification of a MIS transistor of the present invention; ; Fig. 8 is a circuit diagram of a dynamic memory using a MIS transistor of the present invention; Fig. 9 is a diagram showing the relationship between a drain current ID and a gate voltage VG of the dynamic memory of Fig. 8; Figs. 10A to 10K and Figs. 11A to 11K are crosssectional views which are used to describe an embodiment of a method for manufacturing a MIS transistor according to the present invention; Figs. 12A to 12E are cross-sectional views which are used to describe another embodiment of a method of manufacturing a MIS transistor according to the present invention; and Figs. 13A to 13G are cross-sectional views used to describe yet another embodiment of a method of manufacturing a MIS transistor according to the present invention. An embodiment of a MIS transistor according to the present invention may be described as follows, with reference to Figs. 4 to 6. A P-type semiconductor substrate 10 comprises an element forming region 12 and a recessed portion 14 surrounding the element forming region 12. The recessed portion 14 is formed by etching the semiconductor substrate 10. A CVD SiO2 film 16 as an element isolation film is deposited in the recessed portion 14. Since the element isolation film is not formed by the thermally oxidization, no bird's beak will occur. N+ -type source and drain regions 24 and 26 are formed in the element forming region 12. The P-type semiconductor substrate 10 sandwiched by the source and drain regions 24, 26 becomes a channel region 28. A gate insulating film 18 is formed on the channel region 28, with a gate electrode 20 being formed on the gate insulating film 18. The source region 24 is connected to a wiring configuration 32, via a contact hole 30, and the drain region 26 is connected to another wiring configuration 36, via another contact hole 34. The gate electrode 20 is connected to a wiring configuration 40 via a contact 38. This wiring configuration 40 and the source and drain regions 24, 26 are electrically insulated by an sio2 insulating film 42. As may be seen from Figs. 4 and 5, the gate electrode 20 exists only on the element forming region 12. An edge portion 44 in the direction of a channel width of the gate electrode is substantially aligned with an edge portion 46 of the element forming region. With a construction such as that described above, the concentration of electric fields at the edge portion 46 of the element forming region 12 is eliminated, so that an inverse narrow channel effect will not appear. Therefore, a threshold voltage Vt will not fluctuate in dependence upon a gate width. Let us now assume that a dynamic memory, such as that shown in Fig. 8, is constituted by using a MIS transistor 0 and a capacitor C. Thus, when the memory size is reduced and the channel width attains a size not larger than 1 , an inverse narrow channel effect occurs, in the case of a conventional MIS transistor, so that a VG-ID characteristic such as that shown by the curve y of Fig. 9 is obtained. In Fig. 9, reference character VG denotes a voltage to be applied to the gate of the MIS transistor, and ID represents a drain current flowing through the MIS transistor. The curve 6 of Fig. 9 indicates the VG-ID characteristic when no inverse narrow channel effect occurs. As may be seen from these curves, when the inverse narrow channel effect occurs, the drain current increases and the charge hold time of the dynamic memory is shortened. Therefore, the off characteristic will deteriorate. According to the present invention, it is possible to prevent the above-mentioned charge hold time from deteriorating. If the slope 6 of the wall surface 46 in the direction of the channel width of the element forming region 12 coincides with the slope 0 of the wall surface 44 in the direction of the channel width of the gate electrode 20, the inverse narrow channel effect can be effectively eliminated. Preferably, the above-mentioned slope 6 should not be smaller than 450 and not larger than 900, as shown in Fig. 7. A considerable inverse narrow channel effect occurs when the channel width is not larger than 1.0 p. Therefore, when the present invention is applied to a device whose channel width is not larger than 1.0 u , a considerable benefit to be derived will consist of the elimination of such an inverse narrow channel effect. A first embodiment of a method of manufacturing a MIS transistor according to the present invention may be described with reference to Figs. 10A to 10K and Figs. llA to 11K. Figs. 10A to 10K correspond to a cross-sectional view in the direction of line V-V of Fig. 4, and Figs. llA to 11K correspond to a crosssectional view in the direction of line VI-VI of Fig. 4. As shown in Figs. 10A and llA, a P-type silicon substrate 10 is prepared whose crystal plane is (1, 0, 0) and which has a specific resistance of 5 to 50 Qcm. After the impurities for adjustment of the threshold voltage Vt are introduced in this silicon substrate 10, an oxide film 102 is formed over the whole surface on the substrate 10, and a polysilicon film 104 is further deposited on the oxide film 102. Next, as shown in Figs. 10B and llB, a resist film is formed over the whole surface and this resist film is patterend to form a resist film pattern 106. The polysilicon film 104, oxide film 102 and silicon substrate 10 are etched, by using the resist film pattern 106 as a mask, thereby forming a polysilicon pattern 108, an oxide film pattern 110, the element forming region 12 and the recessed portion 14. Next, an Sio2 film 112 is deposited over the entire surface by the plasma CVD method. Thereafter, the SiO2 film 112 is etched by, e.g., an ammonium fluoride solution. Since the etching rate on the stepped portion of the SiO2 film 112 is one digit larger than the etching rate on the flat portion of the SiO2 film 112, as shown in Figs. 10C and llC, the SiO2 film 112 is separated into an Sic2 film 114 in the recessed portion and an SiO2 film 116 on the element forming region 12. Thereafter the SiO2 film 116 is removed by the lift-off method. That is, the resist film pattern 106 is removed by a mixed solution of, e.g., sulfuric acid and hydrogen peroxide, and the SiO2 film 116 is also removed in the same manner (Figs. 10D and llD). Next, as shown in Figs. 10E and llE, an Sino2 film 118 is deposited over the entire surface by the CVD method, thereby completely burying a V-shaped groove 120 by the SiO2 film 118. A resist film 122 having a fluidity is further formed on it, thereby making the surface flat. Then, reactive ion etching, for example, is carried out over the entire surface. This reactive ion etching is executed under condition wherein the etching rates of the resist film 122 and SiO2 film 118 are equal, being determined by suitably selecting the thermal treatment time of the resist film 122. Reactive ion etching is performed until the polysilicon pattern 108 is exposed (Figs. 10F and llF), so that the element isolation film 16 may be formed. Next, a silicon nitride film is formed over the entire surface and is patterned, thereby forming a silicon nitride film pattern 124. The polysilicon pattern 108 and oxide film pattern 110 are etched by using the silicon nitiride film pattern 124 as a mask, to form the gate electrode 20 and the gate insulating film 18. N-type impurities are introduced, to form the source and drain regions 24, 26 as well as the channel region 28 (Figs. 10G and llG). Then, as shown in Figs. 10H and llH, an SiO2 film 126 is deposited over the entire surface by the CVD method. The SiO2 film 126 at the stepped portion is removed by slightly etching the whole surface using hydrogen fluoride HF, so that it is separated into an SiO2 film 128 on the element isolation film 16, an SiO2 film 130 on the silicon nitiride film pattern 124, and an SiO2 film 132 on the source and drain regions. Next, the silicon nitride film pattern 124 is etched, thereby removing the SiO2 film 130 (Figs. 10J and llJ). Then, the entire surface is mildly etched by hydrogen fluoride and At is deposited and patterned, to form the gate wiring 40. Additionally, the source and drain wirings 32, 36 to be connected to the source and drain regions 24 and 26 are also formed (not shown). An At film may be used in place of the resist film pattern 106, to form the element forming region 12. Furthermore, it is also possible to employ various other methods which is disclosed in Japanese Patent Disclosure (KOKAI) No. 57-170547. A second embodiment of the method of manufacutring a MIS transistor according to the present invention may be described with reference to Figs. 12A to l2E. As shown in Fig. 12A, after impurities for adjustment of the threshold voltage Vt are introduced to the Ptype silicon substrate 10, an oxide film 102 is formed over the entire surface of the substrate 10, and a polysilicon film 104 is further deposited on the oxide film 102. A resist film is formed on the polysilicon film 104, being patterned in such a way as to form a mask. The polysilicon film 104, oxide film 102 and silicon substrate 10 are etched by using the above-mentioned mask, thereby forming the polysilicon pattern 108, oxide film pattern 110, element forming region 12, and recessed portion 14. Next, after removing the above-mentioned resist mask, the SiO2 film 112 is deposited over the entire surface by the plasma CVD method (Fig. 12B). Thereafter, a resist film is deposited over the entire surface, as shown in Fig. 12C, and is patterned in such a way as to remove only the resist film on the element forming region 12, thereby forming a resist film pattern 140. Furthermore, as shown in Fig. 12D, another resist film 142 is formed over the entire surface, thereby making the surface flat. The resist film pattern 140 and the resist film 142 consist of PMMA (polymethyl methacrylate) and OFPR (a trade name of the Tokyo Ooka Co., Ltd). A proper mixing ratio of the above two chemical components allows the etching rates of the resist films to coincide with the etching rate of the CVD-SiO2 film 112. As shown in Fig. 12E, reactive dry etching may then be carried out under conditions wherein the etching rates of the SiO2 film 112, resist film pattern 140 and resist film 142 are equal, thereby exposing the polysilicon pattern 108. In this way, the element isolation film 16 is formed. Since the subsequent steps are similar to those which have already been mentioned with reference to the first embodiment, a detailed description thereof is omitted. A third embodiment of a method of manufacturing a MIS transistor according to the present invention may be described with reference to Figs. 13A to 13G. As shown in Fig. 13A, after the impurities for adjustment of the threshold voltage Vt are introduced to the P-type silicon substrate 10, the oxide film 102 is formed over the entire surface of the substrate 10, and the polysilicon film 104 is further deposited on the oxide film 102. A resist film is formed on the polysilicon film 104 and is patterned in such a way as to form a mask. The polysilicon film 104, oxide film 102 and silicon substrate 10 are etched by using the abovementioned mask, to form the polysilicon pattern 108, oxide film pattern 110, element forming region 12 and recessed portion 14 (Fig. 13B). After the abovementioned resist mask was removed, the SiO2 film 112 is deposited over the entire surface by the plasma CVD method (Fig. 13C). Thereafter, as shown in Fig. 13D, a resist film is deposited over the entire surface and only the resist film on the element forming region 12 is removed, to form a resist film pattern 150. By using the resist film pattern 150 as a mask, the SiO2 film 112 on the element forming region 12 is selectively removed (Fig. 13E). After removing the resist film pattern 150, as shown in Fig. 13F, an SiO2 film 152 is formed over the entire surface by the CVD method and a resist film 154 is further formed thereon, thereby making the surface flat. Next, as shown in Fig. 13G, reactive dry etching is performed under conditions wherein the etching rates of the Sino2 films 112, 152 and the resist film 154 are equal, thereby exposing the polysilicon pattern 108. Thus, the element isolation film 16 is formed. Since the subsequent steps are similar to those which have already been mentioned with respect to the first embodiment; a detailed description thereof is omitted. The present invention is not limited to the abovedescribed embodiments. For example, the above-mentioned gate electrode material is not limited to a polysilicon, but may be a metal such as At, or an alloy such as Mo-Si. In addition, just as the above-mentioned insulating film for isolating elements is not limited to a CVD-SiO2 film; similarly, the gate insulating film is not limited to a thermally oxidized film. Moreover, many other modifications and variations are possible, without departing from the spirit and intended scope of the invention.

Claims: Claims: 1. A MIS transistor having a deposited and buried isolation, comprising a semiconductor substrate (10), an element forming region (12) formed on said semiconductor substrate, said element forming region having a source region (24), drain region (26) and channel region (28), an insulating film (16) deposited on and buried within said semiconductor substrate in such a way as to surround said element forming region, a gate insulating film (18) formed on said channel region, and a gate electrode (20) formed on said gate insulating film, characterized in that said gate electrode (20) exists only on said element forming region (12), and in that the edge portion (44) in the direction of the channel width of the gate electrode is substantially aligned with the edge (46) of said element forming region. 2. A MIS transistor according to claim 1, characterized in that the level of the upper surface of said insulating film (16) is aligned with the level of the upper surface of said gate electrode (20). 3. A MIS transistor according to claim 1, characterized in that the wall surface (44) in the direction of the channel width of said element forming region and the wall surface (46) in the direction of the channel width of said gate electrode have slopes (e) which are in the same direction. 4. A MIS transistor according to claim 3, characterized in that said slope (o) is not smaller than 450 and is not larger than 900. 5. A MIS transistor according to claim 1, characterized in that said insulating film (16) is a CVD SiO2 film. 6. A method for manufacturing a MIS transistor having a deposited and buried isolation, comprising the steps of (a) etching a semiconductor substrate (10) and forming a recessed portion (14) in said semiconductor substrate, thereby forming an element forming region (12) in the semiconductor substrate, (b) depositing an insulating material on said recessed portion, by the CVD method, thereby forming an insulating film (16) for isolating elements, (c) forming a gate insulating film (18) and a gate electrode (20) on said element forming region, while forming source and drain regions (24, 26) within said element forming region, and (d) forming wiring configurations (32, 36, 38) to be connected to said gate electrode, source and drain regions, characterized in that said step (a) comprises the steps of forming a first insulating film (102) on said semiconductor substrate (10), forming a first conductive layer (104) on said first insulating film, and sequentially etching said first conductive layer, said first insulating film and said semiconductor substrate, to form a first conductive layer pattern (108), a first insulating film pattern (110) and the recessed portion (14) in said semiconductor substrate, respectively, thereby forming the element forming region (12), in that said step (b) comprises the steps of forming a second insulating film (112, 118) on at least said recessed portion, by the CVD method, forming a third insulating film (118, 122, 142, 152, 154) on said second insulating film and said element forming region, thereby making the surface flat, and sequentially etching said third insulating film and said second insulating film, to expose said first conductive layer pattern (108), thereby forming the insulating film (16) for isolating an element, this step being executed under conditions wherein the etching rates of said second and third insulating films are almost equal, and in that said step (c) comprises the step of etching said first conductive layer pattern and said first insulating film pattern, to form the gate electrode (20) and gate insulating film (18), thereby forming the source and drain regions (24, 26). 7. A method according to claim 6, characterized in that said second insulating film is formed of SiO2. 8. A method according to claim 6, characterized in that said step of forming the second insulating film comprises the sub-steps of: forming the second insulating film (112) over the entire surface, by the CVD method; etching said second insulating film around the element forming region, thereby separating the second insulating film (116) on the element forming region from the second insulating film (114) in the recessed portion; and eliminating the second insulating film (116) on the element forming region, by the lift-off method, thereby exposing said first conductive layer pattern (108). 9. A method according to claim 8, characterized in that said step of forming the third insulating film comprises the sub-steps of: forming a fourth insulating film (118) over the entire surface, by the CVD method; and providing a resist layer (122) on said fourth insulating film, thereby making the surface flat. 10. A method according to claim 6, characterized in that said step of forming the second insulating film comprises the sub-steps of: forming the second insulating film (112) over the entire surface, by the CVD method; forming a mask (150) on said second insulating film on the recessed portion; eliminating the second insulating film (112) around said element forming region and on said first conductive layer pattern; and eliminating said mask (150). 11. A method according to claim 10, characterized in that said step of forming the third insulating film comprises the sub-steps of: forming a fourth insulating film (152) over the entire surface, by the CVD mthod; and providing a resist layer (154) on said fourth insulating film, thereby making the surface flat. 12. A method according to claim 6, characterized in that said step of forming the second insulating film comprises the sub-step of: forming the second insulating film (112) over the entire surface, by the CVD method. 13. A method according to claim 12, characterized in that said step of forming the third insulating film comprises the sub-steps of: providing a first resist layer (140) on said second insulating film on the recessed portion; and forming the second resist layer (142) over the entire surface, thereby making the surface flat.

Inventors: HORIGUCHI, FUMIO
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1983
Main classification: H01L21
IPC codes: H01L29, H01L21