CMOS INTEGRATED CIRCUIT WITH GUARD BANDS FOR LATCH-UP PROTECTION

Abstract: Latch-up in bulk CMOS integrated circuits, caused by a parasitic pnp and npn transistors, is prevented by use of p-plus (42) and n-plus (44) guard bands which are juxtapositioned and connected to a common power supply (Vdd).

Description: Description CMOS Integrated Circuit with Guard. Bands For Latch-Up Protection Technical Field This invention relates to CMOS integrated ' circuits, and in particular, to bulk CMOS integrated circuits having an improved guard band arrangement to prevent latch-up. • * Background Art Latch-up is a potentially serious problem in the operation of CMOS integrated circuits. Latch-up is caused by the formation of parasitic bipolar transistors which are byproducts of both p-channel and n-channel devices. The susceptibility of a CMOS integrated circuit chip to latch-up is a function of the starting material, the processing procedure, and the circuit and chip design techniques. More particularly, adjacent pMOS and nMOS devices form parasitic npn and pnp devices. Together this constitutes a four layer pnpn path which results in an operation like a silicon controlled rectifier (SCR). Injected minority carrier current may accidently trigger the structure. After triggering, the structure can be turned off only by turning off the power. This triggering can occur when the injected current causes a voltage transient in the circuit that is either above the circuit power supply or below ground. It is well known that the problem of latch-up is reduced in a CMOS circuit by forcing the product of the parasitic npn and pnp transistor betas to less than one, and by shunting the parasitic resistances with lower resistivity structures. Various process modifica¬ tions to accomplish this are described in an article entitled "Latch-Up Prevention in Bulk P- ell CMOS Circuits" by Jim Lipman, VLSI Design, May-June 1982, page 30. Additionally, various design techniques are used to minimize the latch-up problem for bulk CMOS circuits. These are also described in the article referred to above. One. esign approach is the use of guard bands or rings. These are p-plus diffusions in the substrate surrounding pMOS transistors, and n-plus diffusion in the p-well surrounding nMOS transistors. The p-plus guard band is tied to ground, and the n-plus is tied to the supply voltage, Vdd. The guard bands reduce the parasitic bipolar transistor beta product by collecting injected minority carriers, and by increasing the distance between adjacent nMOS and pMOS devices. In order to collect a significant fraction of the injected minority carriers, the width of these guard bands typically must be in the same order of magnitude as the p-well diffusion depth of the nMOS devices. Typically this is about 8 microns. In addition, the spacing between the guard bands surround¬ ing adjacent nMOS and pMOS devices must be the same magnitude, i.e. , 8 microns, in order to prevent Zener breakdown between the guard bands. This can occur because the n-plus guard bands are at the positive supply voltage and the p-plus diffusion guard bands are at ground. As a result of the space between adjacent guard bands valuable space is wasted on the silicon chip substrate resulting in lower yields and greater costs. Disclosure of Invention It is therefore an object of the invention to provide improved means to prevent latch-up in CMOS circuits. Another object of the invention is to provide improved guard band arrangement to prevent latch-up in bulk CMOS circuits resulting in smaller and more densely packed chip devices. In accordance with the present invention, the p-plus and the n-plus diffusion guard rings are fabri¬ cated so that they are juxtapositioned with no space between them. To prevent the possibility of Zener breakdown, both the p-plus diffusion guard bands as well as the n-plus diffusion guard bands are maintained at the positive supply voltage, Vdd. With this configuration, the guard bands continue to function effectively to collect a signifi¬ cant amount of injected minority carriers. But because there is no spacing between the adjacent p-plus diffu- sion and n-plus diffusion guard ' bands, valuable sub¬ strate area is saved. Further, this improvement requires no additional fabrication steps over the existing guard band design. Brief Description of the Drawings Figure 1 is a cross-sectional view of a part of a CMOS integrated circuit having conventionally arranged guard band structures. Figure 2 is a schematic diagram of the parasitic bipolar transistors formed in the CMOS integrated circuit of Figure 1. Figure 3 is a cross-sectional diagram of a CMOS circuit having guard bands in accordance with the present invention. OMPI Figure 4 is a schematic diagram of the parasitic bipolar transistors formed in the CMOS circuit of Figure 3. Best Mode for Carrying Out the Invention Figure 1 shows a cross-sectional view of a part of a bulk CMOS integrated circuit 10. The indivi¬ dual devices are formed in n-type substrate 12. Depicted in Figure 1 is a p-channel MOS (pMOS) transis¬ tor 14 and an n-channel MOS (nMOS) device 16. The pMOS 14 includes a p-plus diffusion forming the source 17, gate 18 and another p-plus diffusion area 20 forming the drain. Connected to source 17 is the positive voltage supply Vdd. The voltage supply Vdd is also connected through an n-plus diffused region 21 to substrate 12. The nMOS transistor 16 is formed within a p-well 22 as is well known to those skilled in the art. In addition to gate 28, an n-plus diffusion region 24 constitutes the source, and another n-plus diffusion region 26 constitutes the drain. The p-well region 22 is connected through a p-plus diffusion region 30 to ground. Similarly, the source 24 is connected to ground. Figure 2 is a schematic representation of the parasitic bipolar devices which are formed in the CMOS circuit of Figure 1. Parasitic pnp transistor 32 is a lateral device whose emitter is formed by the source 17 of pMOS 18, whose base is formed by the n-plus region 21 and the n substrate 12, and its collector is formed by the p-well 22 and the p-plus region 30 of nMOS 16. A second parasitic device, npn trasistor 34 is also inherently created in the CMOS configuration 10. Its emitter is formed by the source 24 of nMOS 16. The p-plus region 30 and p-well 22 form its base, and its collector is formed by the n substrate 12 and by the n-plus region 21. Normally parasitic transistors 32 and 34 are biased off. However, lateral current flow in the substrate 12 and the p-well 22 can establish potential differences which turn on these parasitic transistors. The substrate resistance, Rsub, and the resistance of the p-well, Rp-well, are shown schematically in Figures 1 and 2. To sustain the latch-up state, three condi¬ tions must be met: (1) sufficient lateral current must be present to forward bias the emitter-base junction of the parasitic transistors 32 and 34; (2) the transistor current gain product, beta npn x beta pnp, must exceed the minimum necessary for regeneration; and (3) the bias supply must be capable of sourcing a current g 3 reater than the holding 3 current. When betanpn x beta is less than 1 , latch-up is impossible under all conditions. To reduce the parasitic bipolar transistor beta product, guard rings are used to surround the pMOS and nMOS devices. In Figure 1 a p-plus diffusion guard band 36 surrounds the pMOS 14 and a n-plus diffusion guard band 38 surrounds the nMOS 16. The p-plus guard band 36 is connected to ground. The n-plus guard band 38 is connected to the positive voltage supply Vdd. In order to collect a significant fraction of the injected minority carriers, the width of guard rings 36 and 38 must be of the same order of magnitude as the depth of the p-well diffusion 22, or about 8 microns. Addition¬ ally, the space 40 between the adjacent guard rings 36 and 38 must be of approximately the same dimensions as the depth of the guard rings. This is to prevent Zener breakdown between the guard rings. OMPI In Figure 2 the p-plus guard rings 36 is shown as line 36' and the n-plus guard ring 38 is shown as line 38'. As can be seen, the guard band 36 acts as a collector for minority carriers shunting the Rp-well; and guard well 38 acts as a collector of minority carriers to shunt Rsub. As explained, this has the effect of reducing the product of the npn and pnp betas. Figure 3 is a cross-sectional view of a bulk CMOS circuit 10' in accordance with the present invention. Common reference numerals are used in Figure 3 which are found in Figure 1. Unlike Figure 1 , the p-plus diffusion guard band 42 and the n-plus diffusion guard band 44 are located adjacent to each other. The space 40 in Figure 1 is eliminated. To prevent Zener breakdown both the guard bands 42 and 44 are connected to the positive power supply Vdd. The resulting change to the schematic diagram of the parasitic bipolar transistors is shown-in Figure 4. The n-plus guard band 44 is shown as line 44' and, as in Figure 2, acts to collect minority carriers in a parallel path around Rsub. P-plus guard band 42 is represented by line 42' in Figure 4, connected between the collector of pnp 32 and Vdd. By eliminating the space 40 between the guard rings valuable area of the substrate 12 is preserved. This has the effect of increasing yields and of lowering the overall cost of the chip. While the particular embodiment of CMOS described here utilizes a p-well, the invention is equally applicable to an n-well arrangement. Also, in the embodiment described the ' n-plus diffusion guard bands are shown located outside of the p-well. It is also possible for the guard bands to be located within the p-wells or n-wells.

Claims: Claims 1. A CMOS integrated circuit comprising: n-type guard bands surrounding nMOS devices; p-type guard bands surrounding pMOS devices and positioned adjacent said n-type guard bands; and both n-type and p-type guard • • bands biased with the same polarity voltage. 2. A CMOS integrated circuit as in Claim 1 wherein the nMOS devices are formed in p-wells. 3. A CMOS integrated circuit as in Claim 2 wherein the n-type guard bands are located outside of the p-wells. 4. A CMOS integrated circuit as in Claim 2 wherein the n-type guard bands are located within the p-wells. 5. A CMOS integrated circuit as in Claim 1 wherein the pMOS devices are formed in n-wells. 6. A CMOS integrated circuit as in Claim 5 wherein the p-type guard bands are located outside of the n-wells. 7. A CMOS integrated circuit as in Claim 5 wherein the p-type guard bands " are located within the n-wells. OMPI 8. In a bulk CMOS integrated circuit having guard bands of p-plus diffusions surrounding pMOS transistors and n-plus diffusions surrounding nMOS transistors, wherein the improvement comprises juxtapo- sitioning the respective p-plus and n-plus guard bands and connecting both to a common power supply. 9. A method of preventing latch-up in bulk CMOS integrated circuits caused by parasitic pnp and npn transistors comprising juxtapositioning p-plus and n-plus guard bands and connecting both to a common voltage. OMPI

Inventors: ALLEN PATRICK CHARLES, DENHAM PAUL, ALLEN, PATRICK, CHARLES, DENHAM, PAUL
Applicants: SEMI PROCESSES INC, SEMI PROCESSES, INC.
Application year: 1983
Main classification: H01L27
IPC codes: H01L27, H01L29