SWITCHED CAPACITOR CIRCUIT

Abstract: In a switched capacitor circuit, in order to eliminate leakage of a power supply noise component to a signal line through an input capacitance of an opera­ tion amplifier, a power supply noise component having the same phase as that of an input signal is applied to the gate of a transistor of a gain stage, thereby stabilizing the operating point. In order to eliminate leakage of the power supply noise component to the signal line through a parasitic capacitance of an analog switch, a dummy switch is used to detect a signal corresponding to the leakage component of the power supply noise component to the signal line, and an inverted signal having the opposite phase to that of the signal corres­ ponding to the leakage component is applied to a substrate of the analog switch, thereby cancelling the actual leakage component.

Description: The present invention relates to a switched capacitor circuit applicable to various types of analog circuit such as a high precision low-pass filter, an A/D converter and a D/A converter and, more particularly, to a switched capacitor circuit which comprises a MOS integrated circuit. A switched capacitor circuit basically comprises: an operational amplifier; a sampling circuit having two analog switches which are alternately turned on/off in accordance with sampling clocks; and a capacitor which is alternately connected to a signal input and an inverting input of the operational amplifier in accordance with the on/off operation of the analog switches so as to transfer charge corresponding to an input voltage by charging/discharging; and an integrating capacitor connected between an output of the operational amplifier and the inverting input thereof so as to integrate an input signal. When the switched capacitor circuit of the type described above comprises a CMOS device, parasitic capacitances are present in the gate-source path and the gate-drain path of an input transistor of the operational amplifier. When power supply voltages (V DD , V SS ) applied to the operational amplifier vary, the source or drain voltage of the input transistor varies, so that charge flows through the parasitic capacitance (i.e., an input capacitance of the operational amplifier) to an imaginary ground point of the inverting input of the operational amplifier. This charge is then integrated by the integrating capacitor. A change in power supply voltage (i.e., power supply noise) is transmitted by the input capacitance of the operational amplifier to a signal line of the switched capacitor circuit, thereby degrading the signal-to-noise (S/N) ratio. In other words, a power supply rejection ratio (PSRR) is degraded. Leakage of power supply noise by the input capacitance to the signal line is a first cause of degradation of the electrical characteristics of the switched capacitor circuit. The two analog switches comprise a PMOS and an NMOS, respectively. Parasitic capacitances are present in the gate-source path and the gate-drain path of the PMOS, the path between the source of the PMOS and an N-substrate, and the path between the drain thereof and the N-substrate. Similarly, parasitic capacitances are present in the gate-source path and the gate-drain path of the NMOS, the path between the source thereof and a P-well region, and the path between the drain thereof and the P-well region. A clock of a power supply voltage is applied to the gates of the NMOS and PMOS so as to turn on/off the corresponding analog switches. When this power supply voltage varies, charge flows to the imaginary ground point of the operational amplifier through the parasitic capacitances. This charge is integrated by the integrating capacitive element. This is a second cause of degradation of the power supply rejection ratio of the switched capacitor circuit. Since the parasitic capacitance is present in any other device as well as the MOS device, the same problem occurs even if the switched capacitor circuit comprises any device other than the MOS device. Power supply noise components include the following noise components. First, noise occurs in a power supply itself: in particular, a 100-kHz clock leaks in a switching regulator. Second, the power supply voltage varies in accordance with the operation of logic circuits on a single chip. Third, noise occurs as crosstalk from peripheral logic LSIs. These noise components are generated in a wide frequency bandwidth. For example, when a PCM-CODEC LSI is used, many power supply noise components are present since a compact built-in power source is used and lk-gate logic circuits are integrated on a single chip. Furthermore, since an analog signal is sampled with a switching frequency, a high-frequency component which is higher than the switching frequency causes aliasing to fall below the switching frequency. For this reason, the high-frequency component is superposed on a signal in a signal range which corresponds to an actual noise range. As described above, the power supply noise components are present in a wide frequency bandwidth. Furthermore, the power supply noise components leak to the signal line through the parasitic capacitances. As a result, a high-performance switched capacitor circuit cannot be obtained. In order to eliminate the first cause of degradation of the switched capacitor circuit, a method is proposed for forming an on-chip circuit for regulating the negative power supply voltage (Harlan Ohara et al., "A Precision Low-Power PCM Channel Filter with On Chip Power Supply Regulation", IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 6, December 1980, PP. 1005 - 1013). According to this method, since a power supply circuit is regulated, a large-sized transistor is required and high power is required to regulate the power supply voltage in a wide frequency range. Furthermore, since the voltage regulator is arranged between the power supply and the amplifier, the signal magnitude is slightly decreased, resulting in inconvenience. In order to eliminate the second cause of degradation of the switched capacitor circuit, a method is proposed wherein a P-well layer is formed between a MOS switch and a substrate and the P-well layer is biased by a regulated voltage (Douglas G. Marsh et al., "A Single-Chip CMOS PCM Codec With Filters", IEEE Journal of Solid-State Circuits, vol. SC-16, n° 4, August 1981, pp. 308-315). This method has advantages in having a compact circuit architecture and low power dissipation. However, this method can only be applied for an NMOS transistor, so the signal magnitude is limited as compared with the case of a CMOS. Furthermore, since this method disables elimination of the power supply noise components transmitted through the input capacitance of the operational amplifier and the gate capacitance of the switch, a great improvement in the power supply rejection ratio cannot be expected. Besides, US-A-4 308 468 discloses a dual-FET sample and hold circuit and EP-A-0 036 246 discloses a semiconductor memory device with substrate voltage biasing, both disclosing means for cancelling coupling noise appearing on a node by application of a voltage of reverse phase relative to the noise to the node through a capacitor. SUMMARY OF THE INVENTION : It is, therefore, an object of the present invention to provide a switched capacitor circuit having a novel means for preventing degradation of an S/N ratio which is caused by a change in power supply voltage (i.e., by leakage of power supply noise components to a signal line through various parisitic capacitances). The first and second causes of degradation of the power supply rejection ratio in the switched capacitor circuit are thus to be eliminated. The features of the switched capacitor circuit of the invention are defined in claim 1. According to the present invention, the operating point of a gain stage of the operational amplifier of the switched capacitor circuit is stabilized irrespective of a change in power supply voltage. For this purpose, the switched capacitor circuit comprises an operating point stabilizing bias circuit wherein a power supply variation component is applied to the gate of a drive MOS transistor of a gain stage such that the power supply variation component has the same phase as a variation component included in the power supply voltage applied to the source thereof so as to keep the gate-source voltage thereof constant irrespective of a change in power supply voltage. It should be noted that one of the current regulator and the operating point stabilizing bias circuit may be used to improve the S/N ratio. However, when both these circuits are used in the switched capacitor circuit, a further improvement can be obtained. According to the present invention, in order to eliminate the second cause of degradation wherein the power supply noise components leak to the signal line through the parasitic capacitances between the path between the drain of the MOS transistor and the substrate or between the source thereof and the substrate, the switched capacitor circuit may comprise a substrate bias circuit with a dummy switch which has the same arrangement as the analog switch and has the same parasitic capacitance thereas. The dummy switch detects a voltage corresponding to a leak component in the analog switch which is subject to a change in power supply voltage. A voltage of the opposite-phase to that detected by the dummy switch is applied to the substrate of the MOS transistor of the analog switch, thereby cancelling the leak component in the analog switch. According to an embodiment of the present invention, the switched capacitor circuit comprises an operating point stabilizing bias circuit, and a substrate bias circuit so as to improve a power supply rejection ratio (a ratio for rejecting a power supply voltage variation transmission to the signal line). It should be noted that one or two of the bias circuits may be selectively used for a desired application of the switched capacitor circuit so as to obtain a power supply rejection ratio which is sufficiently high in practice, although all of the bias circuits are used in the switched capacitor circuit for a maximum effect. For example, when a small number of analog switches is used, the substrate bias circuit may be omitted. In a high-performance, low-cost switched capacitor circuit which has a high power supply rejection ratio according to the present invention, a high S/N ratio can be guaranteed even if a power supply voltage is supplied from a switching regulator which has many pulsive noise components. The switched capacitor circuit has an advantage in that an expensive, high-performance power source need not be used. Furthermore, when the switched capacitor circuit and the logic circuit are formed on a single chip, a pulsive noise component appearing in the logic circuit through a common power supply wiring layer and the common substrate may not leak in the switched capacitor circuit, thereby readily realizing a high-performance large scale integrated circuit and hence resulting in convenience. Furthermore, according to the present invention, since an integrated circuit which includes the switched capacitor circuit and which processes an analog signal can be formed on a single printed circuit board together with an integrated circuit which has logic circuits, and a single power supply can be used, a simple, low-cost, compact circuit can be arranged. BRIEF DESCRIPTION OF THE DRAWINGS : Fig. 1 is a block diagram showing the basic circuit configuration of a conventional switched capacitor circuit; Fig. 2 is a circuit diagram showing an example of a conventional operational amplifier used for the circuit shown in Fig. 1; Fig. 3A is a sectional view showing the structure of a CMOS device, and Figs. 3B and 3C show parasitic capacitances of the CMOS device shown in Fig. 3A; Fig. 4 is a graph for explaining the drain-source current I ds as a function of the drain-source voltage V ds ; Fig. 5 is a circuit diagram showing an example of a conventional analog switch used for the switched capacitor circuit shown in Fig. 1; Fig. 6 is a circuit diagram showing a switch control circuit of the switched capacitor circuit shown in Fig. 1; Fig. 7 is a circuit diagram showing a CMOS operational amplifier used for a switched capacitor circuit of the present invention; Fig. 8 is a circuit diagram showing a current regulation bias circuit of the operational amplifier shown in Fig. 7; Fig. 9 is a circuit diagram of a reference voltage generator for generating a reference voltage V REF supplied to the current regulation bias circuit shown in Fig. 8; Fig. 10 is a circuit diagram showing a modification of a differential stage of the operational amplifier shown in Fig. 7; Figs. 11A and 11B are circuit diagrams respectively showing V DD noise detectors for the operational amplifier shown in Fig. 7; Fig. 12 is a block diagram of a noise phase correction circuit for correcting noise of a drive transistor of a gain stage of the operational amplifier shown in Fig. 7; Figs. 13A and 13B are circuit diagrams showing a switched capacitor circuit according to an embodiment of the present invention, where Fig. 13A shows a basic circuit arrangement thereof, and Fig. 13B shows the substrate bias circuit thereof; Fig. 14 is a circuit diagram of a high impedance circuit used for a substrate bias circuit shown in Fig. 13B; Fig. 15 is a circuit diagram of a noise detector amplifier used for the substrate bias circuit shown in Fig. 13B; Fig. 16 is a circuit diagram of a level shifter having a source follower, the level shifter being used for the substrate bias circuit; Fig. 17 shows a substrate bias circuit having two level shifters; Fig. 18 is a circuit diagram of another CMOS operational amplifier of a switched capacitor circuit, the CMOS operational amplifier being operated by a single power supply; Fig. 19 is a circuit diagram of a switched capacitor circuit according to another embodiment of the present invention; and Figs. 20A and 20B are circuit diagrams of a switched capacitor circuit which eliminates a correction switch according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS : In order to best understand the present invention, causes of degradation of a power supply rejection ratio (PSRR) in a conventional switched capacitor IC (to be improved upon by the present invention) will be described. Fig. 1 shows a basic circuit arrangement of a conventional switched capacitor circuit. Referring to Fig. 1, an integrating capacitor 4 is connected between an output 2 of an operational amplifier 1 and one inverting input 3 thereof. One end of a sampling capacitor 5 is connected to one end of each of analog switches 6 and 7. The other end of the sampling capacitor 5 is connected to one end of each of analog switches 8 and 9. The other end of the analog switch 6 is connected to a signal input 10, and the other end of the analog switch 8 is connected to the inverting input 3 of the operational amplifier 1. The other end of each of the analog switches 7 and 9 is grounded. Control inputs of the analog switches 6, 7, 8 and 9 are connected to outputs of a switch control circuit 11 which produces switch control signals  1N ,  1P ,  2N and  2P , respectively. The ON/OFF operations of the analog switches 6, 7, 8 and 9 are controlled by these switch control signals, respectively. When the analog switches 6 and 9 are ON and the analog switches 7 and 8 are OFF, the capacitor 5 is charged by an input voltage V in from the signal input 10. When the analog switches 6 and 9 are OFF and the analog switches 7 and 8 are ON, the charge on the sampling capacitor 5 is integrated by the integrating capacitor 4. An integration time constant is C₁/(C₂·f CLK ) where C₁ is the capacitance of the integrating capacitor 4, C₂ is the capacitance of the sampling capacitor 5, and f CLK is the repetition frequency of the ON/OFF operation of the analog switch (the clock frequency of the switch control circuit 11). The integration time constant is determined by the ratio C₁/C₂ of the capacitance of the integrating capacitor 4 to that of the sampling capacitor 5, and the clock frequency f CLK . Therefore, a large time constant can be obtained with a small capacitance. According to the switched capacitor circuit, a capacitive element formed on a substrate of an IC and having a small capacitance can be used as a time constant element; an integrator or a filter having a large time constant can be formed into an integrated circuit, thereby obtaining a compact circuit. Therefore, the switched capacitor circuit has been widely used as the time constant circuit of an IC. However, when the switched capacitor circuit is formed on a single IC chip, a noise component which is included in a power supply leaks to a signal line, resulting in inconvenience. The leakage of the power supply noise component to the signal line is evaluated by a power supply rejection ratio. The degradation of the power supply rejection ratio in the conventional switched capacitor IC arises from the following two causes. The first cause results from the fact that charge is transferred to the inverting input 3 through an input capacitance of the inverting input 3 by a node voltage of the operational amplifier which changes in accordance with a power supply voltage variation. Fig. 2 shows an example of a conventional CMOS operational amplifier. In the case of integrating a switched capacitor circuit, a MOS manufacturing process is utilized since the capacitive element structure of the switched capacitor circuit resembles that of the MOS transistor, the manufacturing process may not become complex, and an input impedance of the amplifier can be greatly increased. Among these advantages, the switching and amplification characteristics allow an application of the CMOS manufacturing process. The CMOS operational amplifier shown in Fig. 2 comprises: a differential stage which comprises transistors 21 to 25; a gain stage which comprises transistors 26 and 27; a frequency compensation buffer which comprises transistors 28 and 29; a bias circuit which comprises transistors 30 to 32; and a frequency compensation capacitor 40. Fig. 3A shows a section of the CMOS device structure. A capacitance C gd between a gate G and a drain D of the MOS transistor, a parasitic capacitance C gs between the gate G and a source S, a parasitic capacitance C db between the drain D and a substrate B, and a parasitic capacitance C sb between the source S and the substrate B are generated as shown in Fig. 3B. As may be apparent from the structure of the P-channel MOS transistor as shown in Fig. 3A, although the substrate is commonly used for the respective transistors, the N-channel MOS transistor is formed in a P-element isolation diffusion layer (to be referred to as a P-well layer hereinafter), thereby isolating the P-channel MOS transistor from the N-channel MOS transistor. Fig. 4 shows voltage-current characteristics of the MOS transistor. As may be apparent from Fig. 4, the MOS transistor has a constant current in a saturation region with respect to the drain-source voltage V ds . In the operational amplifier shown in Fig. 2, when the power supply voltage V DD or V SS is changed, the operating current in each gain-stage is changed. The operating current in each gain-stage is determined in proportion to a ratio of a channel width to a channel length of each of the transistors 25, 27, 29 and 32, and to a current of the bias circuit. The bias circuit serves to divide the power supply voltage to apply the gate-source voltage V gs across the gate and source of each of the MOS transistors 30, 31 and 32 so as to determine the operating current of each of the transistors. When the power supply voltage is changed, the current flowing through the bias circuit is changed, and hence the operating current of each gain-stage is changed. When the operating current of the differential stage is changed, the gate-source voltage V gs of each of the transistors 23 and 24 is changed since it is operated in the saturation region. In other words, a voltage V A2 at a node 33 is changed. Similarly, voltages V A1 and V A3 at nodes 34 and 35, respectively, are changed. A negative feedback voltage is applied from an output 36 of the operational amplifier to its input 37, and a change in an output voltage V out at the output 36 can be limited by a gain between the input and output of the operational amplifier. However, the voltage V A1 at the node 34 and the voltage V A2 at the node 33 may not be controlled by the negative feedback voltage. As a result, charge is transferred to the input 37 through the capacitance C gs between the gate and source of the transistor 23 and the capacitance C gd between the gate and drain thereof. This charge is integrated by the capacitor 4 (Fig. 1) in the switched capacitor circuit, so that a change in the output voltage V out occurs. In general, a MOS transistor has a current noise component greater than that of a bipolar transistor or the like. In order to decrease the current noise component, the gate areas of the transistors 23 and 24 are usually increased. For this reason, the capacitances C gs and C gd of the transistor 23 are considerably large. Therefore, when a CMOS operational amplifier is used in a switched capacitor circuit, it is a very serious problem as to how the power supply rejection ratio of the CMOS operational amplifier may be increased. The second cause results from the fact that a power supply voltage variation is directly transmitted to an input of the operational amplifier through a parasitic capacitance of the MOS transistor constituting the analog switch, and this variation component is integrated by the integrating capacitor. Fig. 5 shows a CMOS analog switch. The CMOS analog switch comprises a P-channel MOS transistor 41 and an N-channel MOS transistor 42. An input 45 and an output 46 are connected and disconnected by applying the switch control signals  1N and  1P to gates 43 and 44, respectively, of the P- and N-channel MOS transistors 41 and 42. The substrate of the P-channel MOS transistor 41 is connected to a power supply voltage V DD , and the substrate of the N-channel MOS transistor 42 is connected to a power supply voltage V SS , which are not illustrated in Fig. 5. The switch control signals  1N ,  1P ,  2N and  2P are generated by a switch control circuit shown in Fig. 6. The switch control circuit comprises an inverter 50, overlap prevention circuits 51 and 52, and inverters 53, 54, 55 and 56 each of which comprises a pair of CMOS transistors. The switch control signals  1N ,  1P ,  2N and  2P correspond to either of the power supply voltages V DD and V SS , and are applied to the gates of the analog switches, which are then turned on/off. The parasitic capacitances C db and C sb of the P-channel MOS transistor are directly coupled to the power supply voltage V DD . The parasitic capacitances C db and C sb of the N-channel MOS transistor are directly coupled to the power supply voltage V SS . The parasitic capacitances C gs and C gd of the P- and N-channel MOS transistors are directly coupled to one of the power sources V DD and V SS . Referring again to Fig. 1, when the analog switch 8 is OFF, the power supply voltage variation component is supplied to the inverting input 3 of the operational amplifier through the parasitic capacitance of the analog switch 8. However, when the analog switch 8 is ON, the variation component is supplied to the inverting input 3 through the parasitic capacitances of the analog switches 8 and 9. The variation component is then integrated by the capacitor 4. The second cause is a minor one as compared with the first cause. However, in the case of implementing a high-order filter or the like, the second cause is still a problem since the number of analog switches is increased. Preferred embodiments of the present invention will be described with reference to the accompany drawings. Fig. 7 is a CMOS operational amplifier used for a switched capacitor circuit according to an embodiment of the present invention. The CMOS operational amplifier comprises: a differential stage consisting of MOS transistors 61 to 65; a gain stage consisting of MOS transistors 66 and 67; a frequency compensation buffer consisting of MOS transistors 68 and 69; a frequency compensation capacitor 85; an output stage consisting of MOS transistors 70 to 72; a V DD noise detector 73 for detecting a power supply voltage variation; and a current regulation bias circuit 74. The transistors 70 to 72 of the output stage serve to decrease an output impedance and to widen the bandwidth the gain stage. Basically, the output stage may be omitted. The current regulation bias circuit 74 serves to keep constant the gate-source voltages of the MOS transistor 65 for determining the operating current of the differential stage, the MOS transistor 67 of the gain stage, and the MOS transistor 71 of the output stage. Fig. 8 shows a detailed arrangement of the current regulation bias circuit. This circuit comprises MOS transistors 90 to 93 which are operated in the saturation region. The reference voltage V REF from an input 75 applied to the gate of the MOS transistor 91 is stable with respect to the ground potential irrespective of variations in the power supply voltages V DD and V SS . The gate-source voltage V gs of the MOS transistor 91 is kept constant, so that the currents flowing through the MOS transistors 90 and 91 are kept constant irrespective of variations in the power supply voltage V DD . When the power supply voltage V DD is changed, the drain voltage of the MOS transistor 91 is changed together with the power supply voltage V DD so as to keep the gate-source voltage V gs of the MOS transistor 90 constant. Therefore, a voltage V BIN corresponding to a variation in the power supply voltage appears at an output 79 of the regulation bias circuit 74. The sources and gates of the MOS transistors 90 and 92 are commonly connected so as to form a current mirror circuit. Therefore, a constant current flows through the MOS transistor 92 irrespective of the variation in the power supply voltage V DD . The gate-source voltage V gs of the MOS transistor 92 is kept constant in accordance with the constant current characteristic of the MOS transistor 92. A voltage V BIAS at an output 78 of the regulation bias circuit 74 is changed together with the power supply voltage V SS . Therefore, the MOS transistor 65 (Fig. 7) and the MOS transistor 93 (Fig. 8), the MOS transistor 67 (Fig. 7) and the MOS transistor 93 (Fig. 8), and the MOS transistor 71 (Fig. 7) and the MOS transistor 93 (Fig. 8), whose gates are biased by the voltage V BIAS , form current mirror circuits, respectively. The gate-source voltages V gs of the MOS transistors 65, 67 and 71 are kept constant irrespective of variations in the power supply voltages V DD and V SS . As a result, the operating current in each gain-stage can be kept constant. The reference voltage V REF can be obtained by applying a stable voltage externally of an IC or by arranging a known bandgap V REF circuit which is formed on the IC chip. Fig. 9 is another example of a reference voltage generator for supplying the reference voltage V REF to the input 75 of the current regulation bias circuit. The reference voltage generator is simply arranged wherein a low-pass filter comprising a resistor 97 and a capacitor 98 eliminates an AC component of the power supply noise component and a filtered voltage is produced as the reference voltage V REF . In the CMOS operational amplifier shown in Fig. 7, when the operating current of each gain-stage is kept constant, the node voltage of the operational amplifier is stabilized in accordance with the constant current characteristic of the MOS transistor. In the differential stage consisting of the MOS transistors 61 to 65, when a substrate voltage effect of the N-channel MOS transistors 63 and 64 is great, the threshold voltages of the MOS transistors 63 and 64 are changed together with the substrate-source voltage V SB if the P-well is electrically connected to the power supply voltage V SS . Even if the operating current is kept constant, a voltage V B2 (which is supposed to be V SB ) at the node between the sources of the MOS transistors 63 and 64 is changed. In this case, when the P-well of the MOS transistors 63 and 64 is connected to the node at the voltage V B2 , the voltage V SB is kept constant and the substrate voltage effect is eliminated. Meanwhile, the voltage V gs of the MOS transistor 61 is kept constant irrespective of variations in the power supply voltage V DD , and a drain voltage V B1 thereof changes in phase with the power supply voltage V DD . The gate capacitance of the MOS transistor 63 operating in the saturation region is almost completely distributed in the gate-source path, so that only a small amount of a variation component of the node voltage V B1 leaks to an inverting input 82. Such a leaked component can be neglected. In order to completely eliminate a leaked component through the gate-drain capacitance C gd of the MOS transistor 63, two P-channel MOS transistors 61A and 62A are added as shown in Fig. 10. By utilizing the fact that the voltage V gs of the P-channel transistor 61A does not change if the operating current thereof is kept constant, a voltage V B1 , at the node between the drains of the MOS transistors 61A and 63 can be stabilized. When the operating current of each gain-stage is kept constant, the power supply voltage variation component may not be substantially transmitted to the signal line. However, since the power supply rejection ratio caused by a change in the threshold voltage of the second gain stage may not be degraded by negative feedback, the feedback signal at the high frequency range is decreased, thus degrading the power supply rejection ratio. The V DD noise detector 73 serves to stabilize the operating point of the gain-stage. By utilizing a frequency compensation capacitor 85, the gate voltage of the transistor 66 for driving the gain stage is changed to have the same phase as the variation component of the voltage at the source of the transistor 66 together with the variation in the power supply voltage V DD . As a result, the voltage V gs of the transistor 66 is kept constant. In order to generate, at the node between the drain and a source of the MOS transistors 68 and 69, a voltage V B4 having the same waveform as that of the V DD variation component, a voltage having a phase opposite to that of the variation component of the power supply voltage V DD is applied by the V DD noise detector 73 to the gate of the MOS transistor 68. Figs. 11A and 11B show two different V DD noise detectors. In the V DD noise detector shown in Fig. 11A, a bias voltage to be applied to a MOS transistor 103 is produced by MOS transistors 101 and 102. An AC variation component of the power supply voltage V DD is applied by a resistor 104 and a capacitor 105 to the gate of the MOS transistor 103, thereby obtaining, at an output 106, a voltage V BOUT having a phase opposite to that of the variation component of the power supply voltage V DD . A transconductance (gm) of a MOS transistor 107 is designed to be smaller than that of the MOS transistor 103. Fig. 11B shows a V DD noise detector which has the same arrangement as that shown in Fig. 11A, except that the resistor 104 is replaced with a MOS circuit since the time constant which is determined by the resistor 104 and the capacitor 105 is so great as to require a large area on the IC chip. A bias voltage to be applied to a MOS transistor 103 is produced by MOS transistors 101 and 110. A voltage V gs of a MOS transistor 114 is then biased by MOS transistors 111, 112 and 113 to be a voltage slightly higher than its threshold voltage. As a result, a high ON resistance of the MOS transistor 114 is used for a resistance to determine the time constant. A negative amplifier which comprises the MOS transistors 103 and 107 is used in each of the V DD noise detectors shown in Figs. 11A and 11B, so that a phase delay occurs in a high frequency range. In order to correct such a phase delay, a phase delay circuit of a resistor 117 and a capacitor 118 may be inserted between the source of the transistor 66 (Fig. 7) of the gain stage and the power supply voltage V DD , as shown in Fig. 12. Since the time constant which is determined by the resistor 117 and the capacitor 118 is very small, it is easy to build the resistor and the capacitor into the IC chip. By utilizing the regulated operational amplifier of the type described above, the power supply rejection ratio (PSRR) of the switched capacitor circuit is greatly improved. In the operational amplifier shown in Fig. 7, the operating current of each stage is determined by the N-channel MOS transistor. However, as may be apparent from the operation characteristics of the CMOSFETs, a P-channel MOS transistor may be used to obtain the same effect. Figs. 13A and 13B show a switched capacitor circuit which includes the CMOS operational amplifier described above according to the embodiment of the present invention. Fig. 13A shows the main part of the switched capacitor circuit; and Fig. 13B shows a substrate bias circuit for applying a voltage to the P-well of the N-channel MOS transistor which constitutes the analog switch. More particularly, Figs. 13A and 13B show circuit arrangements for eliminating the second cause of degradation of the power supply rejection ratio. Each of analog switches 121, 122, 123 and 124 is arranged to have the CMOS operational amplifier configuration shown in Fig. 2 and one additional input P-well which is connected to the P-well of the N-channel MOS transistor of each of the analog switches 121, 122, 123 and 124. The analog switches 121, 122, 123 and 124 correspond to the analog switches 6, 7, 8 and 9 shown in Fig. 1, respectively. A sampling capacitor 128 and an integrating capacitor 129 in Fig. 13A correspond to the sampling capacitor 5 and the integrating capacitor 4 in Fig. 1, respectively. An operational amplifier 120 corresponds to the operational amplifier shown in Fig. 7. The substrate bias circuit has the following arrangement and function. A dummy switch 140 which is the same as the analog switch used in the switched capacitor circuit is prepared to detect a power supply noise component. The detected power supply noise component is amplified by a noise detector amplifier 141 so as to generate a voltage V Pwell for eliminating the power supply noise component leaked to the signal line through the analog switch of the switched capacitor circuit. Then the voltage V Pwell is applied to the input P-well of each analog switch, thereby eliminating the second cause of degradation of the power supply rejection ratio. A switch control circuit 132 may comprise a conventional switch control circuit. Without changing any electrical characteristic of the switched capacitor circuit, the power supply rejection ratio can thus be improved. The leakage of the variation component of the power supply voltage from the analog switch, which results in the second cause, is detected and amplified by the noise detector amplifier 141. The dummy switch 140 has the same arrangement as the analog switch used in the switched capacitor circuit. The dummy switch 140 receives a DC voltage from a high impedance circuit 143. It should be noted that this DC voltage corresponds to substantially the ground potential. This is because the capacitances C gs , C gd , C sb and C db of the MOS transistor have dependency on the input-output voltage characteristics. When the DC voltage is grounded, the dummy switch 140 transmits the power supply variation component in the same manner as in the switch of the switched capacitor circuit. A level shifter 142 converts the DC component to the voltage V Pwell (ranging between about V SS to about V SS +1). This is because an output voltage V SE from the switch noise detector amplifier 141 is grounded by DC feedback. The AC component of the power supply variation which is detected and amplified is subjected to AC coupled feed back through the P-well region of the N-channel MOS transistor of the dummy switch 140 and through the capacitances C db and C sb . As a result, the voltage V Pwell is obtained at an output 144 to have a waveform such as to cancel the power supply variation component. In the switched capacitor circuit, the charging/discharging condition of the capacitor connected to an inverting input 134 of the operational amplifier 120 is changed in accordance with the ON/OFF condition of the analog switches. When the dummy switch 140 comprises two bistable switches each having ON and OFF states (i.e., a switch of MOS transistors 147 and 148 and a switch of MOS transistors 145 and 146), and a correction switch 127 is added to the switched capacitor circuit as shown in Fig. 13A, the dummy switch 140 provides a circuit symmetry to the correction switch 127, thereby eliminating the power supply variation. However, if the dummy switch 140 comprises two normally-ON switches and the correction switch 127 is omitted, only a small part of the power supply variation is remains non-eliminated. The correction switch 127 is turned on/off in the opposite manner to the analog switch 123. This is to assure that the parasitic capacitances of the dummy switch remains the same as that of the main switch due to changes in the gate capacitance in accordance with the ON/OFF states of the switches. Fig. 14 shows another arrangement of the high impedance circuit 143 shown in Fig. 13B. As shown in Fig. 13B, a high impedance circuit can be realized by a high resistance R E . However, in order to decrease the area occupied by the high impedance circuit, a high impedance circuit as shown in Fig. 14 is very effective. This high impedance circuit utilizes a high output impedance of the differential amplifier. The high impedance circuit comprises: a bias circuit consisting of MOS transistors 151 to 153; a differential amplifier consisting of MOS transistors 154 to 159; an attenuator for stabilizing the circuit by decreasing only a gain of a DC feedback loop of MOS transistors 160 to 162; and a bias circuit consisting of MOS transistors 163 and 164 so as to apply a bias voltage to the transistors 160 to 162. By the circuit arrangement which comprises the MOS transistors 152 to 155, the operating current of the differential amplifier is decreased, thereby obtaining a high output impedance. Fig. 15 shows a noise detector amplifier which comprises a single differential stage of MOS transistors 171 to 175. Fig. 16 shows a level shifter which comprises MOS transistors 181 and 182, utilizing the source follower. The output voltage V Pwell from the level shifter 142 shown in Fig. 13B is commonly supplied to the P-well of the dummy switch 140 and to the P-well of the analog switch for the switched capacitor circuit. In this case, the switch control signal is supplied from the latter switch to the P-well since the level shifter has a finite output impedance. When the switch control signal is supplied to the P-well of the dummy switch 140, the power supply variation component may not be completely eliminated. In order to completely eliminate it, two level shifters 142 and 142′ may be used to isolate the P-well, as shown in Fig. 17. Fig. 18 shows a case in which an operational amplifier of a switched capacitor circuit is operated when the positive and negative power supply voltages V DD and V SS are not used, but only the positive power supply voltage V DD is used, and the ground potential is defined as a voltage V DD /2. If the voltage V DD /2 is stabilized only with respect to the power supply voltage V DD , the voltage V DD /2 must be controlled to keep the operating current constant with respect to the variation in the power supply voltage V DD . For this purpose, a bias circuit 190 which is obtained by eliminating the MOS transistors 92 and 93 from the bias circuit (Fig. 8) biases P-channel MOS transistors 193 to 196 so as to only regulate the operating current of each stage. Fig. 19 shows a switched capacitor circuit, which has a capacitor array different from that shown in Fig. 13, according to a second embodiment of the present invention. In this embodiment, two analog switches 211 and 212 are used to charge the sampling capacitor 128, and to discharge the capacitor 128, and then to charge the integrating capacitor 129 by the charge discharged from the capacitor 128. A substrate bias circuit and a switch control circuit are not illustrated in Fig. 19. A correction switch 213 has the same arrangement as that shown in Fig. 13 and has the same effect. Figs. 20A and 20B show a switched capacitor circuit which eliminates a correction switch, according to still another embodiment of the present invention. Fig. 20A shows the switched capacitor circuit which is obtained by omitting the correction switch from the switched capacitor circuit shown in Fig. 13A; and Fig. 20B is a substrate bias circuit therefor. A dummy switch 220 of the substrate bias circuit is turned on/off in accordance with the switch control signal. For this reason, the correction switch can be eliminated. The substrate bias circuit using the dummy switch 220 can be applied to a circuit which uses only one switched capacitor circuit, as well as to a circuit which comprises a plurality of switched capacitor circuits but is operated in accordance with a single timing signal. The switched capacitor circuit of a high power supply rejection ratio can be obtained by: an operational amplifier for preventing the power supply voltage variation from leaking to the signal line by keeping the operating current constant using the reference voltage V REF which is independent of the power supply variation; and a substrate bias circuit for cancelling the power supply voltage variation leaked from the parasitic capacitance of the switch through the path between the substrate and the source (or drain) or the path between the gate and source (or drain) of the MOS transistor of the switch. The switched capacitor circuit having a high power supply rejection ratio according to the present invention can be manufactured at low cost, a high S/N ratio can be guaranteed even if a power supply voltage from the switching regulator power supply has many noise components, thereby eliminating an expensive, high-performance power supply and resulting in convenience. Furthermore, according to the present invention, in the case of forming the switched capacitor circuit and the logic circuit on the same substrate, the pulsive noise component from the logic circuit may not leak to the switched capacitor circuit through the common power supply wiring layer and the substrate. Therefore, a high-performance large scale integrated circuit can be readily realized. Furthermore, according to the present invention, the integrated circuit which includes the switched capacitor circuit so as to process an analog signal can be formed on the same chip together with the logic circuits, and the same power supply can be used, so that an economical, compact circuit can be manufactured.

Claims: A switched capacitor circuit having : an integrating capacitor (4), an operational amplifier (1) having a differential stage (61, 62, 63, 64, 65), a gain stage (66, 67) for amplifying a single -ended output signal from said differential stage, and a frequency compensation buffer (68, 69), said operational amplifier having an output end (2) and an inverting input end (3) between which said integrating capacitor (4) is connected, a sampling circuit having an analog switch (6, 7, 8, 9) and a sampling capacitor (5) connected between a signal input end (10) and said inverting input end (3) of said operational amplifier (1), and a switch control circuit (11) for controlling said analog switch (6, 7, 8, 9), characterized in that : a) it comprises an operating point stabilizing circuit (73) for detecting a variation component of the power supply voltage, for supplying the detected variation component having the same phase as a phase of the power supply voltage (V DD ) to said gain stage (66, 67) of said operational amplifier and for stabilizing an operation point of said gain stage, b) said frequency compensation buffer comprises first (68) and second (69) transistors connected in series between the power supply voltage (V DD ) and ground (V SS ), c) said gain stage comprises a third transistor (66) and a constant current source (67) connected in series between the power supply voltage (V DD ) and ground (V SS ), d) a frequency compensation capacitor (85) is connected between the common node (VB4) of the first (68) and second (69) transistors and the gate of the third transistor (66), e) the operating point stabilizing circuit includes means (101-105 in Figure 11A or 101-114 in Figure 11B) for adding the detected voltage variation component to a bias voltage applied to the gate of the first transistor (68), whereby the voltage variation component is applied to the gate of the third transistor (66) through the frequency compensation buffer and the frequency compensation capacitor (85). A circuit according to claim 1, wherein said means of said operating point stabilizing bias circuit comprise : a voltage variation component detector having a series circuit of a high resistive element (104) and a capacitive element (105, 114), said high resistive element having one end connected to a voltage source which is free from the influence of the variation in the power supply voltage, and said capacitive element having one end connected to the power supply voltage (V DD ). A circuit according to claim 1, characterized in that it further comprises : a substrate bias circuit (140, 141, 142, 143, 144) for detecting a leakage component of the variation in the power supply voltage which is transmitted to a signal line through a parasitic capacitance of a transistor of said analog switch, for producing an inverted voltage (V PWell ) having a phase opposite to a phase of the leakage component, for applying the inverted voltage to a substrate of said analog switch, and for cancelling the leakage component. A circuit according to claim 3, having said analog switch comprises a P-channel MOS transistor and an N-channel MOS transistor, which is isolated from a substrate of said P-channel MOS transistor by a P-type element isolation diffusion layer (P-well) ; and said substrate bias circuit comprises : a dummy switch (140) which has the same arrangement as said analog switch, a detector amplifier (141) for detecting the leakage component of the variation in the power supply voltage which appears at an output end of said dummy switch (140) through a parasitic capacitance of said dummy switch ; a level shifter for converting a DC level of an output signal from said (147) detector amplifier (141) to a level of a P-well voltage required for a switching operation of said analog switch ; a feedback circuit for AC coupled feed back of an output signal from said level shifter (142) to said P-type element isolation diffusion layer of said dummy switch ; and a connector circuit for applying the inverted voltage to said P-type element isolation diffusion layer of said analog switch, the inverted voltage being obtained at an output end (146) of said level shifter (142).

Inventors: IWATA, ATSUSHI, UCHIMURA, KUNIHARU
Applicants: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1983
Main classification: G11C27
IPC codes: G11C27, H03H19