Semiconductor device with spare memory cells

Abstract: A semiconductor memory device includes a plurality of bit memory sections (BMS-1 to BMS-n), a plurality of column select circuits (14-1 to 14-n) for selecting columns of each of the bit memory sections, and one spare memory section (SMS-1, SMS-2). The spare memory section (SMS-1, SMS-2; SMS-11 to SMS-1n) has spare memory cells of one column. The first switching circuits (20-1 to 20-n) are coupled with the column select circuits. A second switching circuit is coupled with the spare memory section (SMS-1, SMS-2). The semi­ conductor memory device further includes a control circuit (16-1, 16-2) programmable to operate in response to a specific address. When receiving the specific address, the control circuit turns off the selected one of the first switching circuits (20-1 to 20-n) and turns on the second switching circuit.

Description: The present invention relates to a semiconductor device with spare memory cells. With the increase in the memory capacity of recent semiconductor memory devices, there is an increasing probability that semiconductor memories will be fabricated containing defective memory cells, although the number may be very small. Technology has been studied and developed which enables the semiconductor memory devices containing defective memory cells to operate as if they didn't contain defective ones. The technology is based on the following idea. Spare memory cells, together with ordinary memory cells, are formed on a chip. When a defective memory cell is selected, a spare memory cell is selected in place of the defective one using a spare memory cell select circuit having already stored the address of the detective memory cell. The spare memory cell select circuit contains nonvolatile memory cells such as fusible elements for programming the address of the defective memory cell. In this type of the memory device, spare memory cells are arranged together with a semiconductor memory having a plurality of memory cells (MC-11 to MC-MN) arranged in a matrix. Two ways of arranging the spare memory cells may be considered; the spare memory cells SMC-01 to SMC-ON are arranged on the same row, as shown in Fig. 1, and the spare memory cells SMC-10 to SMC-MO are arranged on the same column, as shown in Fig. 2. In the memory devices shown in Figs. 1 and 2, the memory cells MC-11 to MC-MN are selected by a column select circuit 2 and a row select circuit 4 in a well known manner. The spare memory cells SMC-01 to SMC-ON shown in Fig. 1 are selected by a spare memory cell select circuit 6. The spare memory cells SMC-10 to SMC-MO shown in Fig. 2 are selected by a spare memory cell select circuit 8. In the memory device of Fig. 1 or 2, if the memory cell MC-11, for example, is defective, the spare memory cells SMC-01 to SMC-ON or spare memory cells SMC-10 to SMC-MO are used in place of the memory cells MC-11 to MC-1N or memory cells MC-11 to MC-M1. More specifically, when the memory cell MC-11 is selected in the memory device of Fig. 1, the spare memory cell select circuit 6 responds to a control signal from an external control circuit (not shown) and supplies a row select signal to the spare memory cells SMC-01 to SMC-ON, while at the same time supplying an inhibit signal to the row select circuit 4. As a result, the row select signal from the row select circuit 4 is made ineffective. In the memory device shown in Fig. 2, the spare memory cell select circuit 8 receives a control signal from the external control circuit. Responding to the control signal, the select circuit 8 supplies a column select signal to the spare memory cells SMC-10 to SMC-MO and makes the select signal from the column select circuit 2 ineffective. An ordinary semiconductor memory device with which a plurality of bits are simultaneously read out and written is provided with a plurality of bit memory sections BMS-1 to BMS-i and BMS-(i+1) to BMS-n, as shown in Fig. 3. Each of the memory sections has memory cells MC of M × N. The bit memory sections BMS-1 to BMS-n are provided with column select circuits 10-1 to 10-n for selecting columns of the bit memory sections. A row select circuit 12 for selecting rows of the bit memory sections BMS-1 to BMS-n is connected between the bit memory sections BMS-i and BMS-(i+1). The semiconductor memory device shown in Fig. 3 is further provided with a spare memory section SBMS containing spare memory cells of M × N. The row memory cells of the spare memory section SBMS are selected by the row select circuit 12. The column memory cells in the spare memory section SBMS are selected by a column select circuit 10S. Suppose now that, in the manufacturing stage of the semiconductor memory device, it is detected that one of the bit memory sections BMS-1 to BMS-n, for example, the bit memory section BMS-i includes at least one defective memory cell. In such a case, the column select circuit 10-i, for example, is substantially disconnected from a data line (not shown) to make the column select circuit 10-i ineffective in its column select function. At the same time, the column select circuit 10S is so designed as to have the same address as that of the column select circuit 10-i. Thus, the spare bit memory section SBMS is ready for use in place of the bit memory section BMS-i. With the provision of the bit memory section SBMS, even if defective memory cells are contained in the bit memory section BMS-i in the manufacturing stage, the semiconductor memory device may be operated as if it has no defective memory cells. For designing the semiconductor memory device shown in Fig. 3 so as to have a memory capacity of 8 K words × 8 bits = 64 K bits , a great number of spare memory cells, about 8 K cells, are required. When two or more of the bit memory sections BMS-1 to BMS-n contain defective memory cells, the single spare bit-memory section is insufficient to simultaneously compensate for the defective memory cells of the two or more bit-memory sections. Thus, even if the semiconductor memory device having spare memory cells of 8 K is fabricated, the semiconductor memory device is treated as a defective memory device when defective memory cells are contained in a plurality of bit memory sections, thereby providing a poor production yield. Prior art document EP-A-0 030 245 discloses a semiconductor memory device comprising main memory cells and a redundancy memory array which is incorporated with said main memory cells and contains therein a corrected memory cell corresponding to a defective memory cell contained in said main memory cells. An addressing means specifies memory arrays containing desired memory cell, in accordance with an address information. A detector detects whether or not said address information specifies said defective memory cell. A switch unit selects either one of the systems of said main memory cells and said redundancy memory array, in accordance with a resultant determination of said detector, so as to read true data, via a data bus, from a data output buffer circuit or to write true data, via said data bus, from a data input buffer circuit. The data bus is comprised of a main data bus, cooperating with said main memory cells, a redundancy data bus, cooperating with said redundancy memory array, and a common bus. The switch unit is connected between said main data bus and said redundancy data bus, and either one of these data buses is selectively connected, via said common bus, to the data output buffer circuit or the data input buffer circuit. The addressing means can specify both memory arrays of said main memory cells and said redundancy memory array, simultaneously, and the switch unit is activated parallely with the operation of the addressing means. What should be noted in that in this prior art semiconductor memory device a spare memory cell column is provided for each bit memory section. Prior art document "IBM Journal of Research and Development", Vol. 24, No. 3, May 1980, pages 291 to 298, discloses a two-bit chip with two redundant bit lines which have each an any-for-any replacement capability over the entire bit dimension. These two redundant bit lines have unique data latches for avoiding multiple bit switches for steering capability to any data latch. The redundant bit lines are connected to data pads and for compensating for defective bit memory sections. However, only data pass devices are used to switch the data pass between the redundant data latches and data pads #1 and #2. It is an object of the present invention to provide a semiconductor memory device which can effectively compensate for defective memory cells using a small number of spare memory cells. According to the present invention, there is provided a semiconductor memory device having the features as defined in claim 1. According to the invention with such an arrangement, even if at least one of memory cells on the same column are defective, spare memory cells are used in place of these memory cells on the same row. Accordingly, a semiconductor memory device containing defective memory cells may be operated in a proper manner, and the semiconductor memory device may be compensated using a small number of spare memory cells. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1 and 2 show arrangements of conventional semiconductor memory devices capable of compensating for defective memory cells, using spare memory cells; Fig. 3 shows an arrangement of a semiconductor memory device with a plurality of bit memory sections and one spare memory section; Fig. 4 shows an arrangement of a semiconductor memory device with a plurality of bit memory sections and two columns of spare memory cells according to an embodiment of the invention; Fig. 5 shows a detailed arrangement of a control circuit shown in Fig. 4; and Fig. 6 shows a detailed arrangement of each of switching circuits shown in Figs. 4 and 5. Referring to Fig. 4, there is shown an arrangement of a semiconductor memory device with spare memory cells according to an embodiment of the present invention. The semiconductor memory device, like that of Fig. 3, is provided with bit memory sections BMS-1 to BMS-i and BMS-(i+1) to BMS-n each having memory cells MC of M × N, and a row select circuit 12 coupled between the bit memory sections BMS-i and BMS-(i+1) to commonly select rows in the bit memory sections BMS-1 to BMS-n. The bit memory sections BMS-1 to BMS-i and BMS-(i+1) to BMS-n are coupled with column select circuits 14-1 to 14-i and 14-(i+1) to 14-n, respectively. The semiconductor memory device is further provided with two spare memory sections SMS-1 and SMS-2 whose rows are selected by the row select circuit 12, and control circuits 16-1 and 16-2 (to be described later) respectively connected with the spare memory sections SMS-1 and SMS-2. The spare memory sections SMS-1 and SMS-2 each include M spare memory cells SMC arranged on the same column. The column select circuits 14-1 to 14-n are respectively connected to n pair of data lines (not shown) of an input/output circuit 18 through respective switching circuits 20-1 to 20-n. Turning now to Fig. 5, there is shown a detailed circuit of the control circuit 16-1 shown in Fig. 14. The arrangement and operation of the control circuit 16-2 is substantially the same as those of the control circuit 16-1. Hence no description of it will be given. The control circuit 16-1 includes a power-on detector circuit 30 for generating a signal which is low in level immediately after the power is turned on and is high after a given time, spare signal generating circuits 32S and 32-1 to 32-i for generating a low or high level signal in response to an output signal from the power-on detector circuit 30, an address designating circuit 34, and a switching control circuit 38 for generating switching control signals in response to the output signals from the spare signal generating circuits 32S and 32-1 to 32-i and the address designating circuit 34. The spare signal generating circuits 32S and 32-1 to 32-i have the same circuit arrangements, respectively. The spare signal generating circuit 32S will be described as a typical example. The spare signal generating circuit 32S is comprised of a CMOS inverter 40S for inverting the output signal from the power-on detector circuit 30, a fuse element 42S coupled between one end of the current path of MOS transistors forming the CMOS inverter 40S and ground, and a flip-flop circuit 44S for generating an output signal with a level according to an output signal from the CMOS inverter 40S. The fuse elements of the spare signal generating circuits 32S and 32-1 to 32-i may be formed of a polycrystalline silicon layer, for example, and burned out when it is irradiated with a laser beam. The fuse element of one of the spare signal generating circuits 32S and 32-1 to 32-i corresponding to that one of the bit memory sections BMS-1 to BMS-i which contains a defective memory cell, is burned out. When a defective memory cell is contained in the bit-memory section BMS-1, for example, the fuse element of the spare signal generating circuits 32-1 and the fuse element 42S of the spare signal generating circuit 32S are burned out. The address designating circuit 34 is comprised of a MOS transistor 50 connected at the source to a power source terminal VD and operating as a load elements, a switching MOS transistor 51 grounded at the source and connected at the gate to the output terminal of the spare signal generating circuit 32S through an inverter, n-channel MOS transistors 52 to 55 whose current paths are connected in series between the MOS transistors 50 and 51, n-channel MOS transistors 56 to 59 whose current paths are connected in series between the MOS transistors 50 and 51, fuse elements 60 to 65 for respectively connecting the sources of the MOS transistors 52 to 54 and 56 to 58 to the drains of the MOS transistors 53 to 55 and 57 to 59, and fuse elements 66 and 67 for coupling the sources of the MOS transistors 55 and 59 to the drain of the MOS transistor 51. The drains of the MOS transistors 52 to 55 are coupled with the drains of the MOS transistors 56 to 59, respectively. The gates of the MOS transistors 56 to 59 are applied with column address signals A1 and A4 used for selecting columns in the bit memory sections, via inverters. The column address signals A1 to A4 are directly supplied to the gates of the MOS transistors 56 to 59. The fuse elements 60 to 67 are selectively burned out so that the address designating circuit 34 forms an address designating circuit for designating a column containing a defective memory cell. The switching control circuit 38 is comprised of an NOR gate 38S and OR gates 38-1 to 38-i whose first input terminals are respectively coupled with the spare signal generating circuits 32S and 32-1 to 32-i and whose second input terminals are connected to the output terminal of the address designating circuit 34. The output signals CS and C1 to Ci from the NOR gate 38S and OR gates 38-1 to 38-i are applied directly and through respective inverters to the switching circuit 36. The switching circuit 36, as shown in Fig. 6, is comprised of P-channel MOS transistors TP1, TP2, TP11 to TP1i and TP21 to TP2i, and N-channel MOS transistors TN1, TN2, TN11 to TNi and TN21 to TN2i. The MOS transistors TP1 and TN1 are coupled with a pair of bit lines of the spare memory cell section SMCS-1. The MOS transistors TN2 and TP2 are coupled in parallel with the MOS transistors TP1 and TN1, respectively. The current paths of the MOS transistors TN11 to TN1i are each connected at one end to one of the paired bit lines of the spare memory cell section SMCS-1 through the MOS transistors TP1 and TN2 and are connected at the other ends to data lines 70-1 to 70-i of the I/O circuit 18, respectively. The MOS transistors TP11 and TP1i are connected in parallel with the MOS transistors TN11 to TN1i, respectively. The current paths of the MOS transistors TP21 to TP2i are each connected at one end to the other of the paired bit lines of the spare memory cell section SMCS-1 through the MOS transistors TN1 and TP2 and are connected at the other ends to data lines 72-1 to 72-i of the I/O circuit 18, respectively. The MOS transistors TN21 to TN2i are coupled in parallel with the MOS transistors TP21 to TP2i, respectively. The switching circuits 20-1 to 20-i shown in Fig. 4 are each comprised of two sets of parallel circuits of p- and n-channel MOS transistors. For example, the switching circuit 20-1 is comprised of p- and n-channel MOS transistors TP31 and TN31 whose current paths are connected in parallel to each other and are each connected at one end to the data line 70-1, and p- and n-channel MOS transistors TP41 and TN41 whose current paths are connected in parallel to each other and are each connected at one end to the data line 72-1. The switching circuit 20-i is comprised of p- and n-channel MOS transistors TP3i and TN3i whose current paths are connected in parallel to each other and are each connected at one end to the data line 70-i, and p- and n-channel MOS transistors TP4i and TN4i whose current paths are connected in parallel with each other and are each connected at one end to the data line 72-i. The other ends of the current paths of the MOS transistors TP31 and TN31 are connected, through p- and n-channel MOS transistors TP511 and TN511 coupled in parallel with each other, to one of the paired bit lines of a corresponding one of N columns in the bit memory section BMS-1. The other ends of the MOS transistors TP41 and TN41 are coupled, through the p- and n-channel MOS transistors TP611 and TN611 coupled in parallel with each other, to the other of the paired bit lines in the same column. The other ends of the current paths of the MOS transistors TP3i and TN3i are connected, through the p- and n-channel MOS transistors TP5iN and TN5iN coupled in parallel with each other, to one of the paired bit lines of a corresponding one of N columns in the bit memory section BMS-i. The other ends of the current paths of the MOS transistors TP4i and TN4i are coupled, through the p- and n-channel MOS transistors TP6iN and TN6iN connected in parallel with each other, to the other of the paired bit lines in the same column of the bit memory section BMS-i. The MOS transistors TP511, TN511, TP611 and TN611 constitute one of N decoding switches whose conduction states are controlled by decoding circuit (not shown) in the column select circuit 14-1. The MOS transistors TP5iN, TN5iN, TP6iN and TN6iN constitute one of N decoding switches whose conduction states are controlled by a decoding circuit (not shown) in the column selection circuit 14-i. The gates of the MOS transistors TP11, TP21, TN31 and TN41 are connected to receive a control signal from the OR gate 38-1. The gates of the MOS transistors TN11, TN21, TP31 and TP41 are connected to receive a control signal C1 . The gates of the MOS transistors TP1i, TP2i, TN3i and TN4i are connected to receive a control signal Ci from the NOR gate 38-i, and the gates of the MOS transistors TN1i, TN2i, TP3i and TP4i are connected to receive a control signal Ci . When all the switching circuits 20-1 to 20-i are in ON state, the MOS transistors TP11 to TP1i, TP21 to TP2i, TN11 to TN1i and TN21 to TN2i are all kept nonconductive. When at least one of the switching circuits 20-1 to 20-i is in OFF-state, the corresponding ones of the MOS transistors TP11 to TP1i, TP21 to TP2i, TN11 to TN1i and TN21 to TN2i are rendered conductive and the MOS transistors TP1 and TP2 are coupled with one of the data lines 70-1 to 70-i and one of the data lines 72-1 to 72-i, respectively. The gates of the MOS transistors TN1 and TN2 are coupled to receive a control signal CS from the NOR gate 38S and the gates of the MOS transistors TP1 and TP2 are connected to receive a control signal CS . The operation of the semiconductor memory device shown in Figs. 4 to 6 will be described. Assume now that at least one defective memory cell is detected in memory cells on a first column of the bit memory section BMS-1. In this case, the fuse element 42S in the spare signal generating circuit 32S and the fuse element (not shown) in the spare signal generating circuit 32-1 are burned out and at the same time the fuse elements 63 to 65 and 67 in the address designating circuit 34 are burned out. As a result, the address designating circuit 34 has an address (0000) for designating the first column in the bit memory section. Under this condition, when the power source is ON, the power-on detector circuit 30 generates a low level signal for a preset period of time. In reponse to the low level signal from the power-on detector circuit 30, the spare signal generating circuits 32S and 32-1 to 32-i produce low level signals. Then, when the output signal from the power-on detector circuit 30 goes high, the spare signal generating circuits other than the circuit 32-1 generate high level signals. Since the fuse element of the spare signal generating circuit 32-1 is burned out, the output terminal of the inverter (not shown) of the spare signal generating circuit 32-1 is in a floating state. Therefore, the output state of the flip-flop circuit (not shown) of the spare signal generating circuit 32-1 is kept unchanged, and the output signal from the spare signal generating circuit 32-1 is kept at a low level. The low output signal from the spare signal generating circuit 32S is applied, through the inverter, to the gate of the switching MOS transistor 51 in the address designating circuit 34, thereby rendering the switching MOS transistor 51 conductive. When the output signal of the address designating circuit 34 is high, the control signals C1 to Ci from the OR gates 38-1 to 38-i are high, and the MOS transistors TP11 to TP1i, TP21 to TP2i, TN11 to TN1i and TN21 to TN2i are all rendered nonconductive. When a column address signal (0000) is applied to the address specifying circuit 34 and the circuit 34 generates a low level signal, the OR gate 38-1 produces a low level control signal C1. As a result, the MOS transistors TP31, TP41, TN31 and TN41 are rendered nonconductive and the MOS transistors TP11, TP21, TN11 and TN21 are rendered conductive. Also in this case, the NOR gate 38S generates a high level control signal CS and the MOS transistors TP1, TP2, TN1 and TN2 are rendered conductive. Accordingly, the spare memory section SMS-1 is actively coupled with the data lines 70-1 and 72-1. In this case, by the column select signal from the column decoder (not shown) of the column select circuit 14-1, the MOS transistors TP511, TP611, TN511 and TN611 are rendered conductive. At this time, however, the switching circuit 20-1 is kept turned OFF. Therefore, the bit memory section BMS-1 is separated from the data lines 70-1 and 72-1. When no defective memory cell is contained in the bit memory sections BMS-1 to BMS-i, no fuse elements in the spare signal generating circuits 32S and 32-1 to 32-i and the address designating circuit 34 are burned out. Accordingly, in this case, the address designating circuit 34 generates a high level signal for any address signals, the NOR gate 38S produces a low level control signal CS, and the OR gates 38-1 to 38-i produce high level control signals C1 to Ci. Therefore, the MOS transistors TP1, TP2, TN1, TN2, TP11 to TP1i, TP21 to TP2i, TN11 to TN1i and TN21 to TN2i are all kept nonconductive, while the MOS transistors TP31 to TP3i, TP41 to TP4i, TN31 to TN3i and TN41 to TN4i are all kept conductive. When at least one of the memory cells arranged on a column in the bit memory sections BMS-1 to BMS-i is defective, the fuse element 42S of the spare signal generating circuit 32S and, the fuse element of one of the spare signal generating circuits 32-1 to 32-i corresponding to one of the bit memory sections BMS-1 to BMS-i containing the defective memory cell, are burned out, and the fuse elements 61 to 67 of the address designating circuit 34 are selectively burned out so as to have an address to designate the column containing the defective memory cell. As a result, the defective memory cell and the memory cells on the column containing the defective memory cell may be replaced by the spare memory section SMS-1. In the above description, a defective memory cell is contained in the bit memory sections BMS-1 to BMS-i. If the defective memory cell is contained in the bit memory sections BMS-(i+1) to BMS-n, the control circuit 16-2 operates like the control circuit 16-1. The spare memory section SMS-2 is used in place of the defective memory cell and the memory cells arranged on the same column as that bearing the defective memory cell.

Claims: A semiconductor memory device comprising: a plurality of bit-memory sections (BMS-1 to BMS-N), each bit-memory section having a plurality of memory cells arranged on a plurality of memory columns; a plurality of column select circuits (14-1 to 14-n), each column select circuit being coupled with said bit-memory sections; a plurality of spare bit-memory sections (SMS-1, SMS-2), each spare bit-memory section having spare memory cells of one column; control means (16-1, 16-2) being programmable to turn on switching means (36, 38) in response to column signal generated by burn-out of a fuse and specifying the column including a defect memory cell; and address designating circuit (34) for designating an address of the column; characterized in that: said switching means (36, 36) is coupled with said spare bit-memory sections (SMS-1, SMS-2), and a further switching means (20-1 to 20-n) is provided to disconnect one or more defective bit-memory sections; said control means (16-1, 16-2) is programmable to turn off said further switching means (20-1 to 20-n) so as to disconnect one or more defective bit-memory sections (SMS-1, SMS-2), and at the same time, to turn on said switching means (36, 38) in response to said column signal for selecting columns of said spare bit-memory sections (SMS-1, SMS-2), so that one or more defective bit-memory sections are replaced with the spare bit-memory sections (SMS-1, SMS-2), when defective memory cells occur in a bit-memory section; and said control means (16-1, 16-2) includes a plurality of logic circuits (38-1 to 38-i) whose output terminals are each connected to a corresponding one of said further switching means (20-1 to 20-n), a plurality of spare signal generating circuits (32-1 to 32-i) programmable by laid column signals to generate one of two signals having different logic levels, said spare signal generating circuits (32-1 to 32-i) being respectively coupled at the output terminals with first input terminals of said logic circuits (38-1 to 38-i), and an address designating circuit (34) programmable to have a specific address designating a defective bit-memory section; said address designating circuit (34) having an output terminal connected to second input terminals of said logic circuits (38-1 to 38-i), so that said one address designating circuit (34) can only contribute to the replacement of the defective memory column. A semiconductor memory device according to claim 1, wherein said address designating circuit (34) is formed of resistive means (50) and a plurality of parallel circuits serially connected to each other and to said resistive means (50) and each having a pair of series circuits each formed of a switching element (52 to 59) and a nonvolatile memory element (60 to 67), said specified address being allotted to said address designating circuit (34) by selectively setting said nonvolatile memory elements (60 to 67), into non-conductive states, whereby said control means (16-1, 16-2) produces a control signal, when receiving said specified address, to turn off one of said further switching means (20-1 to 20-n) and turn off said switching means (36, 38). A semiconductor memory device according to claim 2, wherein when all of a plurality of fusible elements (60 to 67) are kept alive, said control means (16-1, 16-2) produces a control signal to turn on all of said further switching means (20-1 to 20-n) and turn off said switching means (36, 38). A semiconductor memory device according to claim 1, wherein each of said spare signal generating circuits (32-1 to 32-i) includes an inverter formed of CMOS transistors, a fusible element connected in series with a current path of said CMOS transistors, and a flip-flop circuit having an input terminal connected to an output terminal of said inverter and an output terminal connected to one of said logic circuits (38-1 to 38-i). A semiconductor memory device according to claim 2, wherein said nonvolatile memory element (60 to 67) is formed of a fusible element which is burned out in its non-conductive state. A semiconductor memory device according to claim 2, wherein when all the nonvolatile memory elements (60 to 67) are kept in the conductive state, said control means (16-1, 16-2) produces a control signal to turn on all of said further switching means (20-1 to 20-i) and turn off said switching means (36, 38).

Inventors: OCHII KIYOFUMI, OCHII, KIYOFUMI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1983
Main classification: G06F11
IPC codes: G06F12, G11C17, G11C11, G11C29