OHMIC CONTACT FOR N-TYPE GaAs

Abstract: An improved multi-layer contact for N-type GaAs comprising discrete layers of germanium (21, 22), gold (23, 24), and nickel (25, 26).

Description: OHMIC CONTACT FOR N-TYPE GaAs Background This invention relates to semiconductor devices and, in particular, to ohmic contact metallization for N-type gallium-arsenide (GaAs) devices. In the past, and currently, the contact metallization to N-type GaAs comprises gold-germanium and nickel layers wherein the gold-germanium layer is formed by evaporation from a common melt, or pellets or by co-evaporation. The resulting alloy typically comprises 88% gold-12% germanium by weight. A nickel layer is then deposited and, occasionally, a gold layer is deposited atop the nickel layer. The resulting structure, while providing an ohmic contact, exhibits inconsistent contact resistance, which affects device saturation characteristics. Further, in tests performed on field effect transistor (FET) devices, it has been found that device saturation current changes during processing. The change is not uniform, however. Wafers processed together in a lot do not exhibit the same amount of change. In devices of the prior art, the appearance of the surface of the contact region varies from an overall rough texture to a light texture with lumps, which are believed due to non-uniform alloying of the gold and germanium. The surface texture can cause contact problems, e.g. when a lump is near a step. If such must be accounted for in design rules, it raises the lower limit in fine line geometries. In view of the foregoing, it is therefore an object of the present invention to provide an improved contact for N-type GaAs devices. Another object of the present invention is to consistently provide a lower resistance contact for GaAs devices than has been attainable in the prior art. A further object of the present invention is to minimize or eliminate variations in GaAs device characteristics due to contact metallization. Another object of the present invention is to provide a contact having improved morphology for GaAs devices. Summary The foregoing objects are achieved in the present invention wherein a multi-layer contact metallization comprises, as separately deposited layers, germanium, gold, nickel and, optionally, a second gold layer. A more complete understanding of the present invention can be obtained by considering the following detailed description in conjunction with the accompanying drawings, in which: FIGURE 1 illustrates a GaAs FET in accordance with the prior art. FIGURE 2 illustrates a GaAs FET in accordance with a preferred embodiment of the present invention. Detailed Description FIGURE 1 illustrates what is know in the art as a dual gate HESFET (metal semiconductor field effect transistor) having source and drain contacts in accordance with the prior art. Specifically, MESFET 10 comprises a substrate 11 which may, for example, comprise semi-insulating gallium arsenide. Overlying substrate 11 is N-type conductivity gallium arsenide layer 12 which forms the active layer of the MESFET. Overlying separated portions of layer 12 are ohmic contact metallizations 13 and 14 which form the source and drain of the FET. As known in the prior art, these contact metallizations comprise an alloy of gold and germanium, typically 88% gold and 12% germanium by weight. Between source and drain contacts 13 and 14 are gate . contacts 15 and 16. Gate contacts 15 and 16 typically comprise a titanium, platinum, and gold metal system. Overlying source and drain contacts 13 and 14 are contact metal layers 17 and 18, respectively. The contact metal layer is typically 40 n . thick and comprises nickel. The gold-germanium ohmic contact layer is typically 120 nm. thick. FIGURE 2 illustrates a dual gate MESFET having source drain contacts formed in accordance with the present invention. Specifically, semi-insulating substrate 11 has N-type conductivity gallium arsenide layer 12 formed thereon. Instead of a mixture or alloy of gold and germanium, a layer of germanium is deposited in predeter¬ mined, spaced apart regions to form source and drain contacts 21 and 22. The germanium layer is from 45 to 75 nm. thick and is preferably approximately 60 nm. thick. Overlying germanium layers 21 and 22 are gold layers 23 and 24, respectively, which may be from 100 to 160 nm. thick and are preferably approximately 120 nm. thick. Overlying gold layers 23 and 24 are nickel layers 25 and 26 respectively. These nickel layers may be from 30 to 50 nm. thick and are preferably appro imately 40 nm. thick. Devices in accordance with the present invention can be made by conventional processing steps. Specifically, the germanium, gold, and nickel layers are deposited over a patterned layer of positive photoresist which has been deposited on N-type conductivity layer 12. The photoresist is removed in a conventional lift-off technique to pattern the germanium, gold, and nickel layers. The wafer is then subjected to an alloy step in which the germanium and gold layers are brought to a temperature above their 356°C eutectic temperature, forming an alloy therebetween. For example, the wafer is transported through an oven having a maximum temperature of approximately 470° at a rate such that the wafer temperature is brought to approximately 360 o for a short time, e.g. 10 seconds. The entire alloy step typically takes about two and one-half minutes. Thereafter, the gate contact metallization is applied, also using the lift-off technique, preferably the gate contact metal, e.g. titanium-platinum-gold, is also applied to the source drain metallizations to provide contact areas thereon. The wafer is then passivated and diced to form separate devices, which may be either discrete transistors or integrated circuits. In operation, the germanium increases surface doping concentration, thereby decreasing the barrier height to form an ohmic contact with the gold, which provides a low contact resistance. The nickel serves to improve morphology and wetting characteristics to the surface of the source and drain contacts. It is believed that the nickel layer also prevents deformation of the germanium and gold layers during the eutectic melt. Devices built in accordance with the present invention exhibit as little as one tenth the contact resistance of prior art devices. For any given material, the contact resistance is consistently lower with the contact of the present invention. In addition, the surface morphology of the source and drain contacts is markedly smoother than those of the prior art. This is believed to be due to the more uniform alloying of the gold and germanium. In prior art devices, despite the presence of the nickel layer, the surface morphology of the contacts is characteristically rough. There is thus provided by the present invention an improved contact metallization for N-type conductivity gallium arsenide regions. Device characteristics are improved and made consistent, and contact resistance is reduced. In addition, contacts in accordance with the present invention have improved thermal stability as compared to prior art contacts. Having thus described the invention it will be apparent to those of skill in the art that modifications can be made within the spirit and scope of the present invention. For example, an N + conductivity region is sometimes formed over the N-type conductivity region. A comparison of devices made in accordance with the present invention, and including an N + layer beneath the contact metallization, with devices having contacts in accordance with the prior art, the least favorable comparison showed < contact resistance for devices in accordance with the present invention as 75% of the contact resistance of devices having contacts built in accordance with the prior art. If desired, a gold-germanium layer can be included between the germanium and gold layers. While described with respect to a dual gate MESFET, it is understood that the contact metallization of the present invention can be used for any device having a gallium arsenide N-type conductivity region to which contact is made. " VΛ P

Claims: Claims 1. In a semiconductor device having at least one GaAs N-type conductivity region, an ohmic contact to said region comprising? a layer consisting essentially of germanium in contact with and overlying at least a portion of said region; and a layer consisting essentially of gold overlying said germanium layer. 2. The device as set forth in claim 1 and further comprising a layer consisting essentially of nickel overlying said gold layer. 3. The device as set forth in claim 2 and further comprising a gold layer overlying said nickel layer. 4. The device as set forth in claim 1 wherein said germanium layer is 45 to 75 nm. thick and wherein said gold layer is 100 to 160 nm. thick. 5. The device as set forth in claim 3 wherein said germanium layer is approximately 60 nm. thick and said gold layer is approximately 120 nm. thick. 6. The device as set forth in claim 5 wherein said region comprises germanium diffused from said germanium layer. 7. The device as set forth in claim 2 wherein said nickel layer is 30 to 50 nm. thick. 8. The device as set forth in claim 7 wherein said nickel is approximately 40 nm. thick.

Inventors: FRARY JAMES M, FRARY, JAMES, M.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1983
Main classification: H01L23
IPC codes: H01L21, H01L23, H01L29