SEMICONDUCTOR MEMORY DEVICE HAVING TUNNEL DIODES

Abstract: A semiconductor memory device has at least one memo­ ry cell (MC11 to MCMN) which includes first and second tunnel diodes (TD1 and TD2) connected in series in a forward-bias di­ rection between first and second power source terminals (VD and VS). The first and second power source terminals (VD and VS) are held at constant potentials. A switching MOS transis­ tor (TR1) is connected at one end to a connection point be­ tween the first and second tunnel diodes (TD1 and TD2). The potential at the connection point between the first and second tunnel diodes (TD1 and TD2) is determined by the potential at the other end of the switching MOS transistor (TR1).

Description: This invention relates to a semiconductor memory device having tunnel diodes. Two types of random-access memories (RAMs) are known, i.e., a dynamic RAM and a static RAM. A dynamic RAM has a plurality of memory cells each formed of one MOS transistor and one capacitor. A static RAM has a plurality of memory cells each formed of six MOS transistors or four MOS transistors and two resistors. The dynamic RAM needs to undergo a data refreshing operation in order to preserve the data stored therein. The static RAM cannot be made with a high packing density because each of its memory cells includes many elements. Prior art document "Electronics", vol. 33, no. 22, 28th May 1960, pages 75-84, discloses a circuit arrangement in which two tunnel diodes (Esaki diodes) are connected in series in forward direction for digital work between positive and negative voltage terminals, the connection point between the two tunnel diodes being connected to a signal input/output line. Further prior art document K.N.Chang: "Parametric and tunnel diodes", 1964, pages 169-171, Eaglewood Cliffs, N.J., USA, describes a similar memory circuit in which also two tunnel diodes are connected in series in forward direction between two d.c. voltage sources connected also in series. The connection point of the two tunnel diodes is supplied with an input current, and the connection point of the two d.c. sources is connected to earth. An object of the present invention is to provide a semiconductor memory device which need not undergo data refreshing operation and which can be formed of a small number of elements. The present invention provides a memory cell having first and second tunnel diodes connected in series in a forward-bias direction between first and second power source terminals, the potential at a connection point between the tunnel diodes being set at one of a first and second current trough potential as defined in the preamble of Claim 1, thereby to store data in the memory cell, said memory device being characterized as defined in the characterizing portion of Cl.1. Briefly, a switching means is connected at one end to the connection point between said first and second tunnel diodes, and a bit line is connected to the other end of the switching means, a word line is connected to the switching means for supplying a signal to control the switching means, and the potential at the connection point between the first and second tunnel diodes is set to the predetermined level through the bit line. The switching means is closed to set the potential on the data line at a predetermined level, thereby writing data into the memory cell. The data is held by a current which flows through the first and second tunnel diodes. A data refreshing operation is thus unnecessary. Since each memory cell is comprised of two tunnel diodes and one switching means, the semiconductor memory device of the invention can be constituted by a small number of elements. The stored data is read out by sensing the potential at the connection point comparing it with a reference potential provided by a dummy cell including third and fourth tunnel diodes similarly connected but generating an intermediate potential at their connection, and amplifying it by means of a sense amplifier. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a semiconductor memory device embodying the present invention; Fig. 2 illustrates the voltage-current characteristics of two tunnel diodes used in the memory device shown in Fig. 1; Fig. 3 shows a sense amplifier circuit used in the memory device shown in Fig. 1. Fig. 1 shows a memory device embodying the present invention. The memory device includes memory cells MC11 to MCMP which are arranged in a matrix array and other memory cells MC1(Pß1) to MCMN which are also arranged in a matrix array. The device further includes bit lines BL01 to BL0M each connected to those memory cells MC11 to MCMP which are arranged in the same row, bit lines BL11 to BL1M each connected to those memory cells MC1(P+1) to MCMN which are arranged in the same row, and word lines WL1 to WLN each connected to those memory cells MC11 to MCMN which are arranged in the same column. The memory device further includes a sense amplifier circuit SAC which is connected to the bit lines BL01 to BL0M and also to the bit lines BL11 to BL1M. The device has dummy cells DC01 to DC0M connected to the bit lines BL01 to BL0M, respectively and other dummy cells DC11 to DC1M connected to the bit lines BL11 to BL1M, respectively. The dummy cells DC01 to DC0M are connected to a word line DWL0, and the dummy cells DC11 to DC1M to a word line DWL1. The memory cells MC11 to MCMP, memory cells MC1(P+1) to MCMN, dummy cells DC01 to DC0M and dummy cells DC11 to DC1M are each formed of a switching MOS transistor and two tunnel diodes (or Esaki diodes). The MOS transistor has its gate connected to the word line and its current path connected at one end to the bit line. The two tunnel diodes are connected in series in a forward-bias direction between power source terminals VD and VS. A connection point between the tunnel diodes is coupled to the other end of the current path of the switching MOS transistor. Suppose the word line WL1 is made active and the switching MOS transistor TR1 of the memory cell MC11 is turned on. The potential on the bit line BL01 then changes. The currents flowing through the tunnel diodes TD1 and TD2 of the memory cell MC11 vary as shown in Fig. 2. Specifically, the current flowing through the diode TD2 changes as indicated by a solid-line curve and the current flowing through the diode TD1 changes as represented by a broken-line curve. As will be clearly understood from Fig. 2, current flows through the switching MOS transistor TR1 except for the points A1, A2 and A3 (hereinafter referred to as "current stable points") where the same current flows through the tunnel diodes TD1 and TD2. When the transistor TR1 is turned off while the current is flowing through the transistor TR1, the potential at the connection point between the diodes TD1 and TD2 changes to a value corresponding to one of the current stable points A1, A2 and A3. If the potential on the bit line BL01 is set at, for example, about VSS level while the transistor TR1 is on, and the transistor TR1 is thereafter turned off, the potential at the connection point between the diodes TD1 and TD2 will be held at a potential VA1 which corresponds to the current stable point A1. If the potential on the bit line BL01 is set at about VDD level while the transistor TR1 is on and the transistor TR1 is thereafter turned off, the potential at the connection point between the diodes TD1 and TD2 will be held at a potential VA2 which corresponds to the current stable point A2. The potential at the connection point between the two tunnel diodes of any memory cell other than the cell MC11 can be selectively set at the potential VA1 or VA2 in a similar manner. In this case, it is preferable that the points A1 and A2 be set at or near the minimal points of the V - I characteristic curves of the tunnel diodes TD1 and TD2, respectively so that minimum currents will flow at the current stable points A1 and A2. Moreover, the potential at a connection point between the two tunnel diodes of, for example, the dummy cell DC11 can be set at a potential level VA3 which corresponds to the current stable point A3. This is achieved by setting the potential on the bit line BL11 substantially equal to the potential level VA3, e.g. (VDD+VSS)/2 by means of the sense amplifier circuit SAC while the word line DWL1 is kept active, and then rendering the word line DWL1 inactive. As shown in Fig. 3, the circuit SAC includes sense amplifiers SA1 to SAM, switching MOS transistors each connected between a data line DL0 and a corresponding one of bit lines BL01 to BL0M, and other switching MOS transistors each connected between a data line DL1 and a corresponding one of bit lines BL11 to BL1M. Both data lines DL0 and DL1 are connected to an external circuit (not shown). The potential on the bit line BL11 can thus be set at (VDD+VSS)/2 when the external circuit sets the potential on the data line DL0 at (VDD+VSS)/2 and one of the switching MOS transistors connected to the bit line BL11 is turned on, and consequently a potential at the connection point between the two tunnel diodes of the dummy cell can be set at the potential VA3. To read data from, for example, the memory cell MC11, the word lines WL1 and DWL1 are made active. The potential on the bit line BL01 is then set at the potential level VA1 or VA2 according to the data stored in the memory cell MC11. At the same time, the potential on the bit line BL11 is set at the potential level VA3. The sense amplifier circuit SAC senses the difference between the potentials on the bit lines BL01 and BL11, thus reading the data from the memory cell MC11. In order to reduce the power consumption of each dummy cell, it is preferable to write data of potential level VA3 into the dummy cell immediately before the data reading cycle and to write data of potential level VA1 or VA2 into the dummy cell after the data reading cycle. In the memory device shown in Fig. 1, each of the memory cells is comprised of one MOS transistor and two tunnel diodes. Each memory cell can store the data without being subjected to a data refreshing operation. The memory device can therefore be made with a high packing density.

Claims: A semiconductor memory device having at least one memory cell (MC11 to MCMN) including first and second tunnel diodes (TD1 and TD2) connected in series in a forward-bias direction between first and second power source terminals (VD and VS), the potential at a connection point between said tunnel diodes (TD1 and TD2) being set at one of a first current trough (A1) potential (VA1) of said first tunnel diode (TD1) and a second current trough (A2) potential (VA2) of said second tunnel diode (TD2), thereby holding data in the memory cell, characterized in that: said memory cell (MC11 to MCMN) further includes, a switching means (TR1) connected at one end to the connection point between said first and second tunnel diodes (TD1 and TD2) and at the other end to a bit line (BL01 to BL0M and BL11 to BL1M), said switching means (TR1) being ON/OFF controlled in accordance with the potential of a word line (WL1 to WLN), a reference potential generating means having at least a dummy cell (DC01 to DC0M and DC11 to DC1M) including third and fourth tunnel diodes connected in series in a forward-bias direction between said first and second power source terminals (VD and VS), for generating an intermediate potential (A3) at the connection between said third and fourth tunnel diodes set substantially in the middle between a first current trough (A1) potential of said third tunnel diode and a second current trough (A2) potential of said fourth tunnel diode, and a sense amplifier (SAC) for comparing and amplifying a potential read out from said memory cell (MC11 to MCMN) and the intermediate potential (A3) output from said dummy cell (DC01 to DC0M and DC11 to DC1M) of said reference potential generating means; the potential of said bit line (BL01 to BL0M and BL11 to BL1M) is set at one of a level (VSS) near said first current trough (A1) potential of said first tunnel diode and a level (VDD) near said second current trough (A2) potential of said second tunnel diode while said switching means (TR1) is maintained to be ON by making said word line (WL1 to WLN) active and while said first and second power source terminals (VD and VS) are held at substantially constant potentials, thereby setting the potential at the connection point between said first and second tunnel diodes (TD1 and TD2) at one of said first current trough (A1) potential and said second current trough (A2) potential so as to store data; and said switching means (TR1) is turned on by making said word line active while said first and second power source terminals (VD and VS) are held at said substantially constant potentials, and the potential at the connection point between said first and second tunnel diode (TD1 and TD2) is read out to said bit line (BL01 to BL0M and BL11 to BL1M), so as to be compared with said intermediate potential (A3) generated by said reference potential generating means and to be amplified by means of said sense amplifier (SAC), thereby reading out the stored data. A semiconductor memory device according to claim 1, characterized in that said switching means (TR1) is a MOS transistor.

Inventors: MATSUKAWA, NAOHIRO
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1983
Main classification: G11C11
IPC codes: G11C11