A DC-DC CONVERTER FOR CONVERTING AN UNSTABILIZED DC-VOLTAGE TO THREE STABILIZED DC-VOLTAGES

Abstract: A DC-DC converter converts an incoming unstabilized D.C. voltage to three stabilized output D.C. voltages. The converter contains two chopper stages (1, 2) with associated transformers, rectifiers (3, 4, 17a, 17b) and smoothing filters (5, 6, 18). The two chopper stages give a first and a second pulse-formed output voltage (Ua and Ub), which are regulated by shifting the leading edge of the pulses in the first output voltage (Ua), while the second output voltage (Ub) is regulated by shifting the trailing edge of the pulses. Two output voltages (U1, U2) are obtained after rectifying and smoothing. The third output voltage is obtained by connecting in parallel the outputs of two full-wave rectifiers (17a, 17b) which are magnetically coupled to the outputs of the two chopper steps, and by connecting a smoothing filter (18) to the common output of both full-wave rectifiers. Regulation of the third output voltage (U3) is obtained by varying the phase position ( phi ) between the first and the second chopper output voltage (Ua, Ub).

Description: A DC-DC CONVERTER FOR CONVERTING AN UNSTABILIZED DC-VOLTAGE TO THREE STABILIZED DC-VOLTAGES TECHNICAL HELD The present invention relates to a D.C. converter in accordance with the preamble to claim 1, for converting an uπstabilized incoming D.C. voltage to three stabilized output D.C. voltages with the employment of two chopper circuits. Such a converter is used as the power source for the current supply to electronic equipment, especially airborn such equipment where there is a demand for low weight and volume. BACKGROUND ART In power units with a high power output which is to be distributed to several loads, it is known in the art to utilize a DC -AC converter and to provide the converter with a transformer having a plurality of secondary windings, recti¬ fiers and series regulators being connected to the secondary windings, as in the US patent 4.024.451, for example. Series regulation of the output voltages results in relatively high losses, and thereby lower efficiency, as well as power capacity being limited. To avoid this, three separate converters must be used for higher powers, which of course increases the-weight of the power unit. DISCLOSURE OF INVENTION The object of the present invention is to provide a D.C. converter of the kind mentioned in the introduction, which has as few component parts as is possible with respect to the number of obtained output voltages. In accordance with the invention, there are employed two chopper stages with associated transformers, rectifiers and smoothing filters, to provide three independent D.C. voltage outputs with output power of the same order of magnitude. After rectifying and smoothing, the two chopper stages give a first and a second output voltage which is regulated by shifting the leading edge of the pulses in the first pulse-formed output voltage, while the second output voltage is regulated by shifting the trailing edge of the pulses in the second OMPI- pulse-formed output voltage. A third output voltage is obtained by connecting the first and the second pulse-formed output voltages in parallel after rectifying and before smoothing. This output voltage can be kept constant and dependent on the other two output voltages, providing that both the first and 5 the second output voltages work with overlapping in the respective controlled edge. Regulation of the third output voltage is obtained by varying the phase position between the first and the second chopper output voltage. The converter is accordingly distinguished by the disclosures in the following claim 1. BRIEF DESCRIPTION OF DRAWINGS The invention will now be described in detail with reference to the appended 10 drawings, where figure 1 is a block diagram of a DC-DC converter in accordance with the invention, figure 2 more closely illustrates the transformer stage, together with rectifier and smoothing filter incorporated in the converter according to figure 1; 15 figure 3 is a time chart. BEST MODES OF CARRYING OUT THE INVENTION The incoming unstabilized D.C. voltage is denoted by Udc in the block diagram according to figure 1. The inventive converter contains two chopper stages 1 and 2, which are fed with the D.C. voltage Udc and conventionally convert this voltage to a square-wave pulse train with a given frequency f n . For this purpose 20 the chopper circuit 1 is controlled by a clock circuit 15, which sends control pulses with the frequency f Q to the chopper stage 1 via a pulse width modulator 11 and a logic circuit 13. After rectifying in a half-wave rectifier 3, a pulse-formed output voltage Uol (illustrated in figure 3) is obtained, and the output D.C. voltage U, is obtained after smoothing in a lowpass filter 5. The 25 voltage U, is compared with a reference voltage Url in a comparison circuit 7, and the difference voltage is taken via an amplifier 9 to the control input of the pulse width modulator 11, for varying the pulse width of the control pulses to the chopper step 1, in response to the magnitude of the difference signal from the comparator 7. In this arrangement the pulse width is varied with the aid of • '- the logic 13 by varying the leading flank of the control pulses, while the trailing _ O PI . . flank position is fixed. The frequency f is constant the whole time, and determined by the clock circuit 15. Control pulses are sent to the chopper stage 2 in a similar manner from the clock circuit 15 via a phase shifter 16, a pulse width modulator 12 and a logical circuit 14. After the pulse-formed output voltage from the chopper step 2 has been rectified in a full-wave rectifier 4, a pulsing D.C. voltage U Q2 - ~ obtained, which is smoothed in a lowpass filter 6 to give an output D.C. voltage U 2 - This is compared with a reference voltage U 2 in a comparator 8, and the difference voltage thus obtained is supplied to the pulse width modulator 12 via an amplifier 10. The control pulses to the chopper step 2 are pulse width regulated with the aid of the pulse width regulator 12 and the logical circuit 14, so that the trailing edge is varied in response to the value of the difference voltage from the comparator 8, as will be seen from the time chart in figure 3, where the indicating arrows denote, for the respective chopper step, which flank of the obtained output voltage L , , U Q2 is varied in the pulse width regulation process. A given phase shift < between the puylse-formed output voltages Up-, and U n2 is furthermore obtained with the aid of a phase shifting circuit 16. The two pulse-formed output voltages from the chopper stages 1 and 2 each feed a half -wave rectifier 17a and 17b. The two D.C. voltages are connected in parallel, and together form the voltage U Q ,, which is smoothed in a following lowpass filter 18 so that the output voltage U, is obtained. A comparison circuit 19 is connected to the output of the smoothing filter for comparing the output voltage U, with a reference voltage U ,, a difference voltage being obtained across the output of the comparison circuit, the output being connect- ed to an amplifier 20. The output of the amplifier 20 is connected to a control input of the phase-shifting circuit 16 for phase-shifting, in response to the magnitude of the amplified difference signal, the clock pulses which are supplied to the phase-shifting circuit 16 from the clock circuit 15. As will be seen from figure 3, the pulse width of the rectified output voltage U Q , will be varied by varying the phase angle f in response to the difference signal from the comparison circuit 19. The mean value of the output voltage Ug^ may thus be varied and regulation of the third output voltage U- j from the DC-DC converter is obtained. This regulation of the output voltage U-i does- not affect the regulation of the two other output voltages U j^ and U 2 » slnce °~-y the trailing OMPI and the leading edges of both rectified output voltages U Q1 , U Q2 are varied, which does not affect the output voltage U Q ,. A condition is, however, that the phase relationship of U Q , and U Q2 is such that both these voltages overlap each other at the respective controlled edge. The following applies for the output voltages U-, , U 2 and U, in the case where the lowpass filters 5,6,18 are formed as LC-filters: u U l - T • U ol u U 2 -& T • U o2 where the time intervals tp, and tp 2 are varied with the aid of shifting the respective trailing and leading edges of the voltage pulses during each period. The logic circuits 13 and 14 may possibly be implemented such that the trailing or leading edge of only one pulse is varied, or that the variation is performed only during definite periods, e g so that the trailing (or the leading) edge for each fourth pulse is varied. The time interval t -, is varied by the phase angle between the pulses in the output voltages U Q , and U Q2 being varied. Figure 2 more closely illustrates the transformer stage in the two chopper stages 1 and 2, as well as the connection to the following rectifiers. The blocks la and 2a are included in the respective chopper stage, and symbolize the conventional circuits performing the switching of the incoming D.C. voltage Udc, for obtaining the pulse-formed primary voltages U and U. (according to figure 3) across the respective primary winding. The rectifiers 3 and 4 are constructed as half -wave rectifiers of a kind known per se, each containing two secondary winding parts s, , s 2 and s,, s., respectively, with associated diodes Dl, D2 and D3, D4. The rectifiers 17a and 17b are each built up from two full-wave rectifiers connected in parallel, of which one contains the secondary winding parts s,-, s * . and diodes D5, D6 while the others contain the secondary winding parts s 7 , ~Q ~ n< - diodes D7, D8. The connection in parallel of the full -wave rectifiers 17a, 17b to the chopper stages 1 and 2, respectvely, results in that the chopper steps 1 and 2 share the load current to the commonly supplied output voltage U 3 . The three output voltages U^ u 2 and U 3 , as well as O PI IPO the loads, can be dimensioned independant from each other and may be expanded to an optical number of output voltages. Three independent D.C. outputs are obtained with the proposed DC-DC converter. The three D.C. voltages over these outputs can be regulated independant of each other with the aid of only two chopper stages and two transformers together with the associated control circuits.

Claims: CLAIMS 1 A DC-DC converter for converting an incoming unstabilized D.C. voltage (Udc) to at least three stabilized output D.C. voltages (U,, U 2 , U,) and containing a) a first chopper stage (1) with associated rectifier-filter combination (3,5) for forming a first output voltage (U,), and having a feed-back loop (7,9,11,13) containing a first pulse width modulator (11) for regulating the pulse width in response to comparison between the first output voltage and a reference voltage (U rl ), b) a second chopper stage (2) with an associated rectifier-filter combination (4,6) for forming a second output voltage (U 2 ) and having a second feed-back loop (8,10,12,14) containing a second pulse width modulator (12) for regulating the pulse width in response to comparison between the second output voltage (U 2 ) and a second reference voltage (U 2 ), there being c) a clock circuit (15) arranged for controlling the first and the second pulse width modulator (11,12), characterized in that logical circuits (13,14) are connected to the respective pulse width itiodulators (11,12), said circuits being adapted for controlling the first and the second chopper step (1,2) so that the leading edge of the output voltage (Ua) of the first chopper stage and trailing edge of the output voltage (Ub) of the second chopper stage are varied for said regulation of the pulse width, and such that these overlap each other at the respective control edge, in that both pulse width modulated output voltages from the first and the second chopper circuit (1,2) are connected in parallel to a third rectifier-filter combination (17a,17b,18) the output voltage of which forms the third output voltage (U,) of the converter, and in that a phase shifting circuit (16) is connected between the clock circuit (15) and the second pulse width modulator (12) for varying the phase position between the output voltages from the first and the second chopper stage (1,2) and thereby the third output voltage (U,) in response to a comparison between this output voltage and a third reference voltage (U r3 ). 2 A converter as claimed in claim 1, characterized in that the third rectifier- filter combination comprises a first and a second rectifier (17a, 17b) and a lowpass filter (18), the respective rectifier input being magnetically w'H-O coupled to the respective output of the first and second chopper stage (1,2), and in that the outputs of the rectifiers are commonly connected to the input of the lowpass filter (18). 3 Converter as claimed in claim 2, characterized in that both rectifiers are full-wave rectifiers.

Inventors: NILSSON STEN VALTER, NILSSON, STEN, VALTER
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET L M ERICSSON
Application year: 1983
Main classification: H02M3
IPC codes: H02M3