LIMITER WITH DYNAMIC HYSTERESIS

Abstract: Limiter circuit (13) with dynamic hysteresis for providing improved distortion immunity at the circuit output is response to an input signal. The limiter circuit (13) includes a positive (15) and negative peak detector (17). Two weighted averages are taken of the positive and negative peaks, preferably by means of a voltage divider network (18). The first input to a comparator circuit receives the input signal to the limiter circuit (13). Different voltages from the voltage divider network (18) are applied to the second input of the comparator circuit (21) so as to create a dynamic hysteresis effect in the comparator circuit (21). The different voltages are chosen in response to the output voltage from the comparator circuit (21) by means of an analog switch (19). The comparator circuit (21) includes a fixed hysteresis voltage for stabilizing the limiter circuit (13) at low level voltage input signals.

Description: LIMITER WITH DYNAMIC HYSTERESIS Background of the Invention The invention relates to limiter circuits or zero- crossing detectors which transform an analog input waveform into a binary digital waveform which is suitable for interface to a signal processor, such as a microprocessor. More particularly, the invention relates to a limiter circuit with dynamic hysteresis which provides a clean limited output signal that has a wide input dynamic range and quick response to changes in DC level of the input waveform. Text book circuits for limiters (see Burr-Brown "Operational Amplifiers" pages 358-364) solved the problem of glitches caused by noise or harmonic distortion at signal transition points by adding positive feedback or hysteresis to the ' comparator stage of the limiter. A "glitch" is defined by the IEEE Standard Dictionary of Electrical and Electronics Terms (1972) as a perturbation of the pulse waveform of relatively short duration and of uncertain origin. For specific applications a hysteresis level of a certain percentage of the input peak to peak swing voltage is usally found to be optimal. Currently, limiter circuits have hysteresis loops that are at a fixed level. As the input voltage level goes up or down the percentage of hysteresis with respect to the input voltage level OMPI changes so that the improvement provided by the hysteresis is effective only over a narrow range of input voltage levels. Accordingly, there is a need for a limiter circuit which solves the problem of glitches at the limiter output during signal transitions without being limited to operation over a narrow range of input voltage levels. It is an object of the invention is to provide a limiter circuit with a hysteresis level that is a fixed percentage of the limiter input voltage level. It is also an object of the invention to provide a limiter circuit with a hysteresis level that is effective over a wide range of input voltage levels. Summary of the Invention The invention is a limiter circuit with dynamic hysteresis for providing improved distortion immunity at the circuit output in response to an input signal. The limiter circuit includes a positive and negative peak detector. Two weighted averages are taken of the positive and negative peaks, preferably in a voltage divider network. The first input to a comparator circuit receives the input signal to the limiter circuit. Different voltages from the voltage divider network are applied to the second input of the comparator circuit so as to create a dynamic hysteresis effect in the comparator circuit. The different voltages are chosen in response to the output voltage from the comparator circuit by means of an analog switch. The comparator circuit includes a fixed hysteresis voltage for stabilizing the limiter circuit at low level voltage input signals. Brief Description of the Drawings Figure 1 is a systems block diagram of the intended systems use of the improved limiter circuit. Figure 2 is a functional block diagram of the limiter circuit with dynamic hysteresis according to the invention. Figures 3A-C are waveforms associated with the limiter with dynamic hysteresis shown in Figure 2. Figure 4 is a schematic component diagram of the limiter circuit according to the invention. Detailed Description of the Preferred Embodiment Figure 1 shows the application for which the limiter circuit of the invention is intended. The circuit is part of a tone detector signal processing chain. Tone detection is done by passing input signals through an analog band limiting filter _[__. an & then into a limiter circuit _1_3_. The purpose of the limiter circuit J_3_ is to transform the analog input waveform into a binary digital waveform suitable for interface to the digital microprocessor _1_£-» The output of the limiter J_3_ is applied to an input port of a general purpose microcomputer, which further processes the signal and makes a decision about presence or absence of the expected tone. Since often the algorithm used by the microcomputer requires precise measurements be made of the time interval between consecutive edges of the waveform at the limiter output, it is very important that the limiter output signal be without glitches or double transitions. Distortion of the signal at a transition point may be caused by 1) harmonic distortion of the input signal caused by channel non-linearity or 2) local noise from such sources as the power supply or switching transistors. The band-pass filter 11 is a broad band OMTI filter. For frequencies at the lower end of the band, their second or possibly even third harmonics may fall within the filter's bandpass. Local noise, as illustrated in Figure 1 , can be added to the signal at a point following the filter _π_. Therefore the input to the limiter _1_3_ can be subjected to distortions in the signal that potentially can cause transition distortions at the limiter output. The limiter J3_ solves the transition distortion problem by developing a bias reference signal that is a fixed proportion of the input signal level. This bias signal is used in addition to positive feedback to keep the percentage of hysteresis constant over a 50db dynamic range. In addition, the limiter circuit J_3 can inherently track DC level changes and adapt to them automatically. Figure 2 shows a functional block diagram of the limiter circuit JL3 in Figure 1. Positive and negative peak detectors, _1_5_ and J_7 respectively, are responsive to an analog input signal A from the band limit filter J _ in Figure 1. The outputs B_ and £ of the peak detectors are input to a weighted average circuit 18. Signals _ and E_ are outputs of the weighted average circuit JJ3. The relative weight given voltages _B and £ is different for each of the outputs _D and E_ of the weighted average circuit V8 ^ . The weighted average output voltages D_ and J3 are applied to an analog switch J^ in Figure 2. The output of analog switch J_9_ is a signal _F which is applied to the negative input of comparator 21. Positive input of comparator 2_ is the input signal A. The output signal from comparator 2_ is the square wave output of the limiter J_3 in Figure 1. The signal £ is input to analog switch J3_ to provide a control signal for proper operation of the analog switch. OMPI Figures 3A-C show the waveform for the various input output signals associated with Figure 2. Figure 3A shows the input and output waveforms associated with the positive peak detector J_5 and the negative peak detector V7. ' Waveform A in Figure 3A varies in amplitude over time. The waveform ]3 represents the positive peak detection output from positive peak detector 15. Correspondingly, waveform £ represents the negative peak- to-peak detection of waveform A occurring in negative peak detector _T7. Figure 3B shows the input waveforms to comparator 2Λ_. Waveform is the output from analog switch J_9_. Waveform _F provides the input signal to the negative input of comparator 2_1_. The amplitude of waveform J? in Figure 3B is direcfcly related to the peak amplitude of the input signal A and the peak detection signals 13 and £. The dynamic hysteresis can be seen in Figure 3B at the crossing points of waveforms A and F_. When waveform A is in a positive portion of its cycle the analog switch Jj9 is closed onto signal E_ from the weighted average circuit J^. As the amplitude of signal A decreases it falls below the amplitude of signal JE. Since the analog switch j_9. during this time is closed onto signal E_ then signal F_ is identical to signal E_. When signal A falls below signal _F the comparator output λ_ reverses polarity and thus causes the analog switch J_9_ to open the signal E_ input and close the signal E> input. This causes a sudden shift in signal as shown in Figure 3B. As the input signal A moves along on its negative cycle it needs to go some additional portion over one- half of its cycle in order to reach a crossing point with signal _F which causes the comparator 2J_ to reverse polarity again. As can be seen in Figure 3B the additional portion over one-half cycle that the input signal A must travel before it crosses signal is dependent upon the magnitude of the input signal A. It is in this sense that the hysteresis of the limiter is dynamic. Figure 4 shows a detailed component schematic of the limiter with dynamic hysteresis according to the invention. A positive peak detector J_5 is composed of a operational amplifier 2 _, a diode DJ_ and a capacitor C1. The negative peak detector J_ is composed of a operation¬ al amplifier ^5, a diode D2, and a capacitor C2. The value of capacitors £J_ and £2 are related to the frequency at the limiter input since the discharge time of the capacitors needs to be considerably longer than the frequency period of the input signal. A resistive series connected network R2_ and R3_ compose the weighted average circuit _1_8. The outputs of the two peak detectors are connected at the two ends of the series connected resistive network R_1_, R2 and R3. Two voltages within this resistive network are chosen as inputs to the analog switch _1_9. The first voltage is taken between RJ_ and R , while the second voltage is taken between R2_ and R3_. The resistive ladder R1_, R_2 and R3_ serve a dual purpose. They provide a discharge path for capacitors C1 and £2 so that if the input signal is removed capacitors C1 and £2_ will tend to discharge toward the average of their two previous values. More importantly though, the resistive ladder R1_, R2 and R generate the two referenced voltages inputed to the analog switch 19. V D = V C + [V B - V c ] [R2 + R3] V E = V C + [V B - V C ] [R3] [R1 + R2 + R3] -gJ E O P For representative values R1 = R3 = 3900 ohms R2 = 390 ohms V D = V C + [γ B ~ v cl * 52 * 4% conversely VE = v c + [V B - V c ] * 47.6% Note that V D (voltage D in Fig. 4) is 2.4% higher than the midpoint between V c (voltage C in Fig. 4) and Vg (voltage B in Fig. 4) while V E (voltage E in Fig. 4) is 2.4% lower than the midpoint. These two voltages (V D and V E ) are used to establish a.4.8% total hysteresis for the voltage comparator _2K For a rough estimate, the hysteresis of the limiter can be determined by the equation; % HYSTERESIS = R2 - n n R1+R3 X 10 ° Resistors _R and RJ5 provide a small additional amount of hysteresis by way of positive feedback for comparator 21. The positive feedback provides fixed hysteresis. This prevents the hysteresis from going to zero when the input signal level goes below the minimum desired dynamic range limit. The fixed hysteresis ensures the limiter will be stable at low input conditions since the fixed hysteresis voltage becomes a increasingly larger percentage of the input voltage as the input voltage decreases in magnitude to a point outside the 50 db dynamic range of the limiter. As explained in connection with Figure 3A-C the hysteresis voltage jF is generated by alternately selecting voltage E> or JE depending on the state of the comparator output G. Capacitor £3_ ensures that the voltage transition between V D and V E occurs without switching transcients. Analog switch J_9 can comprise a pair of transmission gates 20A and 20B as shown in Fig. 4. But the analog switch JJ9 is preferably a MC14053B chip. The analog switch is used as a single pole double toggle switch. The output of comparator 2_ provides the control input for the transmission gates 19A and 19B. 5 When the output of comparator 2 Λ_ is high then the transmission gate 19B connects the negative peak detector voltage _E output to the negative input of comparator 21. A high input to the control input of transmission gate 19A holds the gate in a off condition. Accordingly, if ' 10 the output of the comparator 2_ is low than the output _ of positive peak detector J passes through transmission gate 19A and into the negative input of comparator 21. The amount of shift in the threshold voltage at the negative input of comparator 2 _, caused by the switching 15 between voltage D_ and _E, is a percentage fraction of the input signal A. In summary, the invention is a limiter with dynamic hysteresis created by alternatively comparing a reference signal against voltage levels proportional to the 20 positive and negative peaks of the reference signal.

Claims: Claims 1. A method for creating a limiter circuit with dynamic hysteresis characterized by the steps of: 1) detecting the positive and negative peaks of an input waveform, 2) taking at least two weighted averages of said positive and negative peaks, 3) alternately choosing one of said weighted averages, 4) comparing said input waveform with said chosen weighted average, 5) generating a first output signal if the chosen weighted average is greater than the input waveform and generating a second output signal if the chosen weighted average is less than the input waveform. 2. A method for creating a limiter circuit with dynamic hysteresis according to claim 1 further characterized by the additional step of: 5) choosing one of said weighted averages in response to the generated output signals. O PI 3. A limiter circuit with dynamic hysteresis for providing improved distortion immunity at the circuit output in response to a input signal, the limiter characterized by: detecting means 17 for detecting the positive and negative peaks of said input signal, means 18 for taking a plurality of weighted averages of said positive and negative peaks, comparator means 21 having a first input responsive to said input signal, means 19 for alternately choosing at least one of said plurality of weighted averages and applying said at least one weighted average to a second input of said comparator means to create a dynamic hysteresis effect. 4. A limiter circuit according to claim 3 further characterized in that said means 19 for alternately choosing at least one of said plurality of weighted averages is responsive to the output from said comparator means. 5. A limiter circuit according to claim 3 or 4 further characterized in that said means 19 for alternately choosing at least one of said plurality of weighted averages is an analog switch. 6. A limiter circuit according to claim 3 further characterized in that said means 18 for taking a plurality of weighted averages is a voltage divider network. 7. A limiter circuit according to claim 3 further characterized in that said comparator means 21 includes a fixed hysteresis voltage for stabilizing said limiter circuit output at low level voltage input signals. 8. A limiter circuit with dynamic hysteresis for providing improved distortion immunity at the circuit output in response to a input signal, the limiter characterized by, means 15, 17 responsive to said input signal with a plurality of outputs proportional to said input signal, switch means 19 for alternately choosing one of said plurality of outputs, comparator means 21 responsive to said input signal and said switch means 19, feedback means R5 responsive to said comparator means 21 to control said switch means 19.

Inventors: DOLIKIAN ARMAN VAHE, DOLIKIAN, ARMAN, VAHE
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1983
Main classification: H03K5
IPC codes: H03K5