SEMICONDUCTOR MEMORY AND METHOD FOR FABRICATING THE SAME

Abstract: In a semiconductor memory a capacitor (1) is formed by utilizing a groove (17) formed in a semiconductor substrate (10). The sidewalls of the groove are covered by an insulat­ ing layer consisting of a first (18) and a second (19) insulat­ ing film. The interior of the groove is filled with conductive material. An area occupied by each memory cell can be made very small and a distance between the memory cells can also be made very small, accordingly, high denisty integra­ tion is facilitated.

Description: The present invention relates to a semiconductor memory and a method for fabricating the same, and more particularly to a semiconductor memory and a method for fabricating the same, which can increase a memory capacity without increasing a required space. Since a 1k-bit dynamic random access memory (hereinafter referred to as a dRAM) was marketed at the beginning of 1970, a MOS dynamic memory which is one of semiconductor IC memories has been scaled up four times in the memory capacity in every approximately three years. A package for accommodating the memory chip primarily uses a 16-pin dual in-line package (DIP) and a cavity size for accommodating the chip is limited. Thus, the size of the memory chip has been increased 1.4 times at most even when the integration density has increased four times. Accordingly, a memory cell area per bit has been significantly reduced as the integration density has been increased. It has been reduced by a factor of three for the increase of the integration density by a factor of four. Since a capacitance C of the semiconductor memory is represented by C = εA/t (where ε is a dielectric constant of an insulation film, A is an area of a capacitor electrode and t is a thickness of the insulation film between the capacitor electrodes), if the area A is reduced by a factor of three, the capacitance C is also reduced by a factor of three provided that ε and t are kept constant. A signal quantity S derived from a memory capacitor is proportional to a charge quantity Q which is the product of the capacitance C and a voltage V. Thus, if A is reduced, Q is reduced proportionally and the signal quantity S is also reduced accordingly. A signal to noise ratio S/N decreases as S decreases. This will raise a big problem in circuit operation. Accordingly, the decrease of A is usually compensated by the decrease of t. Thus, as the integration density is increased to 4kb, 16kb and 64kb, a thickness of a typical SiO₂ film is reduced to 100 nm, 75 nm and 50 nm. On the other hand, it has been recently found that a charge of approximately 200 fc (femtocoulomb) at maximum is created in a Si substrate by an a particle radiated from a radioactive heavy metal (U, Th, etc.) contained in the package and it causes a noise. Accordingly, it is difficult from a standpoint of stable operation to reduce the signal quantity Q below approximately 200 fc. Accordingly, it has been practiced to further reduce the thickness of the insulation film. As a result, another problem of dielectric breakdown of the insulation film has been raised. An electric field for causing dielectric breakdown in the SiO₂ film which is commonly used as the insulation film of the capacitor is 10⁷ V/cm at maximum. Thus, an SiO₂ film having a thickness of 10 nm is essentially permanently broken or degraded by an application of a voltage of 10 volts. For a long term reliability, it is important to operate the memory at a voltage which is as smaller than the maximum breakdown voltage as possible. Fig. 1 shows a configuration of a one-transistor dynamic memory cell which uses an insulated gate field effect transistor (hereinafter referred to as a MOS transistor). It comprises a capacitor 1 for storing a charge and a switching MOS transistor 2, a drain of the switching MOS transistor 2 is connected to a bit line 3 and a gate thereof is connected to a word line 4. In operation, a signal charge stored in the capacitor 1 is read out by the switching transistor 2. An actual large-scale integration memory is constructed in a memory array by one of the following two major methods. Fig. 2 shows what is called an open bit line configuration in which bit lines 31 and 32 are arranged on opposite sides of a sense amplifier 5 which differentially senses signals. Only one bit line 31 electrically crosses a word line 41, and the sense amplifier 5 senses a difference between the signals on the bit lines 31 and 32. Fig. 3 shows what is called a folded bit line configuration in which two bit lines 31 and 32 connected to a sense amplifier 5 are arranged in parallel and a word line 41 crosses to two bit lines 31 and 32. Preferred embodiments of the present invention to be described later are primarily inplemented in the folded bit line configuration although they may be implemented in the open bit line configuration. In Figs. 2 and 3, one of major performance indices of the memory array is C S /C D , where C D is a capacitance of a parasitic capacitance 6 of the bit line 32 and C S is a capacitance of a capacitor 1-2 of the memory cell. The S/N ratio of the memory array directly corresponds to C S /C D . It is thus important to increase the capacitance of the memory cell and reduce the parasitic capacitance C D of the bit line in order to raise the S/N ratio. Fig. 4 shows a plan structure of a memory cell of the folded bit line configuration, and Fig. 5 shows a sectional structure thereof taken along a line V-V in Fig. 4. As seen from Figs. 4 and 5, since a capacitor is formed at a portion in an active region 7 (shown in a dumbbell shape) encircled by a thick field oxidization film 11 of more than 100 nm thick, the active region 7 is covered by a plate 8. However, the plate 8 is selectively removed (shown at 80 in Fig. 4) at an area at which the switching transistor is formed and at an area of a contact hole 9 through which a bit line 3 is connected to a drain (or source) 15 on a Si substrate. Word lines 4 are deposited on the area 80 and the switching transistor 2 is formed there. In some open bit line memories, the switching transistor 2 has no heavily doped region 15 adjacent to the storage capacitor. The term "transistor" will also include such versions. The semiconductor memory described above is manufactured in the following manner. For the sake of explanation, the transistor is of n-channel type. If a p-channel type is used, the conductivity types of the Si substrate and the diffusion layer are reversed to those in the n-channel type. A field SiO₂ layer 11 of approximately 100 - 1000 nm thick is selectively formed on a p-type Si substrate 10 having a resistivity of approximately 10 Ω-cm by a so-called LOCOS technique which uses Si₃N₄ as an anti-oxidization mask. Then, a gate oxide film 12 of 10 - 100 nm thick is formed on the Si substrate 10 by thermal oxidization. Then, the plate 8 typically formed of poly-Si doped with phosphorus P or arsenic As is selectively deposited and a surface of the poly-Si plate 8 is oxidized to form a first interlayer oxide film 13. Then, the word lines 4 typically formed of poly-Si, Mo silicide or a refractory metal (Mo or W) are deposited and phosphorus P or arsenic As ions are implanted. Thus, n⁺ diffusion regions 15 are formed at areas on which the plate 8 and the word lines 4 are not deposited, to form a source and a drain of the switching MOS transistor 2. Then, a phospho-silicate glass (PSG) 14 is deposited to a thickness of 500 - 1000 nm by a so-called CVD method which contains phosphorus and the contact hole 9 is formed at the area at which the bit line 3 typically formed of an Al electrode is to be connected to the diffusion layer 15. Then, the bit line 3 is selectively deposited thereon. In the memory cell thus fabricated, the area 16 of the memory capacitor 1 naturally decreases as the size of the memory cell itself decreases. Thus, unless the thickness of the gate oxide film 12 is reduced, the capacitance C S is reduced as described above and it raises a big problem in the memory operation. In order to resolve the above problem, it is known to form a narrow groove in the silicon substrate and to form a memory capacitor on the surface of the groove (JP-A-51-130178 and WO-A-81/03241, in view of which the first part of claim 1 has been worded). Since the proposed memory utilizes the side walls and the bottom surface of the groove as electrode surfaces of the capacitor, it can increase the electrode area much more than the memory shown in Figs. 4 and 5 without increasing the plan area. However, in order to further increase the integration density of the semiconductor IC, the area occupied by the memory cell must be further reduced. It is an object of the invention to provide a semiconductor memory including a capacitor having an insulating film with increased dielectric breakdown voltage, and thus a memory having a large capacitance, yet a small occupation area. This object is met by the semiconductor memory defined in claim 1. The invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Figures 1 to 3, referred to above, show configurations of semiconductor memories each having a field effect transistor and a capacitor, Figures 4 and 5, also referred to above, show a plan view and a sectional view of a main portion of a prior-art semiconductor memory, Figures 6 to 11 illustrate steps in manufacturing a semiconductor memory according to one embodiment of the invention, and Figures 12 to 16 illustrate steps of a method for manufacturing a semiconductor memory in accordance with another embodiment of the invention. Embodiment 1 Referring to Fig. 6, a field SiO₂ film 11 of 500 - 1000 nm thick is selectively formed on a p-type Si substrate 10 of about 10 Ω-cm by the LOCOS, method. The field SiO₂ film may alternatively be formed by first forming a SiO₂ film on an entire surface of the Si substrate and then removing unnecessary areas by photo-etching as shown in Fig. 7. As shown in Fig. 9, after a thin SiO₂ film 111 has been formed on the surface of the Si substrate 10, an etching groove 17 is formed at a predetermined area on the Si substrate 10 by a parallel plate plasma etching which uses a photoresist as a mask and gas primarily consisting of CF₄, SF₆ or CCl₄ or mixture of them and H as a reaction gas. When a conventional photoresist film is used as the plasma etching mask, the mask may be etched. Therefore, SiO₂, Si₃N₄ and CVD SiO₂ films are deposited, in this order, on the Si substrate 10 and the resulting composite film is used as the mask, and the Si substrate 10 is dry-etched to form the groove 17. The Si₃N₄ film serves to prevent the field SiO₂ film 11 from being etched when the CVD SiO₂ film as the mask is finally removed. Accordingly, a film of any other material which meets the requirements may be used. The CVD SiO₂/Si₃N₄/SiO₂ composite film is used only as a mask which is finally removed and does not finally remain on the Si substrate 10. Therefore, a mask of any other material which meets the requirement may be used. Alternatively, where it is possible to selectively etch a desired area on the Si substrate 10 by a fine beam, the etching groove 17 can be formed without the mask. When the dry etching such as plasma etching or sputter etching is used, electrical or crystalline contamination or defect may be produced in the Si substrate 10. Accordingly, it is desirable to remove the contamination or defect by wet etching which uses mixed solution of NH₄OH and H₂O₂ or HF and HNO₃, etc. after the groove 17 has been dry-etched. The depth of the etching groove 17 formed is not limited in principle, but it is practical that the depth D M is approximately 0.5 W M - 5 W M , where W M is the width of the groove 17. As shown in Fig. 9, an impurity is introduced by a self-alignment method to the side walls and the bottom of the groove 17, using the SiO₂ film 111 or the CVD SiO₂/Si₃N₄/SiO₂ composite film which was used as, the mask to form the groove 17, as a diffusion mask, by a well-known method such as boron thermal diffusion using BN, to form a P⁺-type diffusion layer 28. The impurity may be introduced by the ion implantation. While ions go straight by the ion implantation, the ions can be implanted to the side walls of the groove 17 by implanting the ions obliquely or utilizing the sputtering by the ion implantation. In addition to the P⁺ diffusion layer 28, an n⁺ diffusion layer may be formed inside the P⁺ diffusion layer 28. An insulation film of a capacitor is next formed. The insulation film may be of any material, in principle, so long as it has a high breakdown voltage and is stable. For example, SiO₂ or Si₃N₄ formed by thermal nitrization or CVD, or Ta₂O₅, TiO₂ or Nb₂O₅ formed by CVD or reactive sputtering may be used. The capacitor insulation film may be a single layer or a multi-layer. In the present embodiment, a composite film of SiO₂ and Si₃N₄ is used. After the SiO₂ film 111 or the CVD SiO₂/Si₃N₄/SiO₂ composite film used as the mask to form the diffusion layer 28 has been removed, a SiO₂ film 18 of 5 - 20 nm thick is formed by a thermal oxidation at a temperature of 900 - 1200°C as shown in Fig. 10. Then, a capacitor Si₃N₄ film 19 of 5 - 20 nm thick is deposited by the CVD method at 650 - 850°C. The thicknesses of those films are selected depending on desired capacitance per unit area and breakdown voltage and hence they may depart from the ranges described above. The CVD Si₃N₄ film usually has a very large internal stress of up to 1 x 10¹⁰ dyn/cm². Thus, if it is directly deposited on the Si substrate 10, defects may be created, resulting in the deterioration of the characteristic. In order to avoid such a problem, it is effective to form a SiO₂ film under the Si₃N₄ film. When the Si substrate 10 is directly nitrized to form the Si₃N₄ film, such a problem does not occur and a fine film having a high breakdown voltage is formed. However, a reaction rate is very slow and a reaction time of more than one hour is required to form a film of more than 10 nm thick. A film thickness increase rate rapidly decreases after the film thickness has exceeded 10 nm. Accordingly, it is difficult to form a thick Si₃N₄ film by direct nitrization. The surface of the Si₃N₄ film 19 may be oxidized to the thickness of 2 - 5 nm in order to improve the breakdown property. As shown in Fig. 11, the plate 8 which is represented by poly-Si is deposited on the entire surface. When the poly-Si is deposited by CVD, it enters into the groove 17 and is deposited thereon. Thus, the thickness of the poly-Si film 8 deposited on the side walls of the groove 17 is substantially equal to the thickness of the poly-Si film 8 deposited on the bottom of the groove 17. Then, phosphorous is thermally diffused into the poly-Si film 8 by using PO Cl₃ gas. When W M > 2T S1 (where W M is the width of the etching groove 17 and T S1 is the thickness of the poly-Si film 8), a groove (having a groove width of 2T S2 ) remains as shown in Fig. 11. This groove is to be filled because it adversely affects to an insulation film deposited on the upper surface thereof and the deposition of the word line 4. In the present embodiment, poly-Si is deposited to the thickness of T S2 as shown in Fig. 11 and then it is removed by the thickness of T S2 by the well-known plasma etching method using CF₄ or SF₆ gas so that the poly-Si film 82 is left embedded in the groove as shown in Fig. 11. As a result, the upper surface is flattened. If the groove is filled by one step of deposition of poly-Si, a second step of deposition is not necessary. Since the plate 8 is also used as a wiring element, an appropriate thickness thereof is in the order of 100 - 500 nm. If the groove is not filled by the first step of deposition, the poly-Si is deposited in the second step to fill the groove. If the poly-Si is directly deposited on the poly-Si film 8 in the second step and then it is etched, the end point of the etching is not clear because the boundary is fused. Thus, the surface of the poly-Si film 8 is thermally oxidized to the depth of 5 - 30 nm to form a SiO₂ film. In this case, when the second poly-Si film has been entirely etched, the SiO₂ film on the surface of the first poly-Si film 8 is exposed. Since the etching rate of the plasma etching for the poly-Si is more than ten times as high as that for the SiO₂, the first poly-Si layer 8 is protected by the SiO₂ film and is not etched even if the SiO₂ film is slightly overetched. As seen from Fig. 11, according to the present embodiment, the capacitor which has the poly-Si plate 8, and the composite insulation film of the SiO₂ film 18 and the Si₃N₄ film 19, and is encircled by the P⁺ diffusion layer 28 is formed in the groove 17 formed in the substrate 10. It will be apparent that the P type substrate may be substituted by a P type well in an n type or insulative substrate. Embodiment 2 The thick SiO₂ film 11 and the thin SiO₂ film 111 are formed on the P-type Si substrate 10 by the method shown in Fig. 6 or 7, and then an n-type impurity such as As or P is ion-implanted by using a photo-resist film 30 as a mask to form a planar electrode layer 29, as shown in Fig. 12. After the photo-resist mask 30 has been-removed the groove 17 is formed by using the SiO₂ film 111 as a mask in the same manner as the Embodiment 1, as shown in Fig. 13. As shown in Fig. 14, boron is diffused by the well-known impurity diffusion method to form a p⁺-type diffusion layer 23, and phosphorus or As is diffused to form an n⁺-type diffusion layer 24 which serves as a capacitor electrode. Then, the insulation films 18 and 19, the poly-Si plate 8, the poly-Si film 82 and the insulation film 13 are formed in the same manner as the Embodiment 1. Thus, as shown in Fig. 15, the capacitor which is encircled by the p⁺-type diffusion layer 23 and has the n⁺-type capacitor electrode 24 is formed in the groove 17 formed in the substrate 10. The surface of the plate 8 is oxidized to form a first interlayer oxide film 13 of 100 - 400 nm. The Si₃N₄ film 19 is not substantially oxidized in this step. Then, exposed areas of the Si₃N₄ film 19 and the SiO₂ film 18 are etched by using the first interlayer oxide film 13 as a mask, and a gate oxide film 12 of 10 - 50 nm thick is formed by the oxidation by dry oxygen containing 1 - 5% of HCl, at 800 - 1150°C. Then, a gate (word line 4) of single or composite layer of poly-Si and/or silicide (such as Mo₂Si), or a refractory metal such as W or Mo is selectively deposited on a selected area. Then, as shown in Fig. 16, As or phosphorus is ion-implanted at an acceleration energy of 60 - 120 KeV to form n⁺ source/drain regions 15 at the area not covered by the plate 8 and the gate 4. One of the n⁺ source/drain regions 15 formed is connected to an n⁺ planar electrode 29 as shown in Fig. 16. A second interlayer insulation film 14 of CVD SiO₂ containing 4 - 10 mol% of phosphorus is deposited to a thickness of 300 - 1000 nm and it is heat-treated at 900 - 1000°C. Then, electrode connection holes 9 reaching to the n⁺-type source/drain region 15, the gate 4 and the plate 8 are formed and Al electrodes 30 are selectively deposited (only the bit line 3 is shown). Thus, a one-transistor dynamic memory having the side walls of the etching groove 17 as a portion of the capacitor is formed. Since the capacitor of the memory cell shown in the present embodiment is formed between the capacitor electrode 24 and the plate 8, the potential of the plate 8 may be fixed, for example to ground level. By grounding the plate 8, a noise can be reduced. This is advantageous to the memory operation. Since the groove 17 is encircled by the p⁺-type layer 23, the width of the depletion layer extending from the side wall of the groove 17 is reduced. As a result, a leakage current between the adjacent memory cells is reduced and the distance between the adjacent cells is also reduced. This is very advantageous to the high integration density of the memory cell.

Claims: A semiconductor memory which is formed in a semiconductor substrate comprising: capacitors (1) for storing information, insulated-gate field effect transistors (2) for reading out the signal, charges stored in said capacitors, word lines (41, 42) for applying signals to the gate electrodes (4) of the insulated-gate field effect transistors (2), and data lines (3, 31, 32) for reading out the information stored in said capacitors (1), wherein each capacitor (1) includes an electrode (24) formed at the side walls of a recess (17) provided in the substrate, wherein the side walls of each recess (17) are covered by an insulating layer (18, 19) and a layer of conductive material (8) is formed over said insulating layer to form a capacitor plate (82) separated from said side walls of the recess (17) by said insulating layer (18, 19), wherein one of the source and drain electrodes of each transistor (2) is connected to one of said electrodes (24, 82) of the capacitor (1) and the other is connected to one of said data lines (3, 31, 32), and wherein the gate electrode (4) of each transistor (2) is connected to one of said word lines (41, 42), characterized in that the insulating layer is a multilayer having at least a first insulating film (18) and a second insulating film (19). The semiconductor memory of claim 1, wherein the first insulating film (18) is comprised of SiO₂ and the second insulating film (19) is comprised of Si₃N₄. The semiconductor memory of claim 1 or claim 2, wherein said capacitor plate (82) is made chiefly of doped polysilicon. A method for fabricating the semiconductor memory of any of claims 1 to 3, comprising the steps of: a) forming an insulation film (11, 111) on a semiconductor substrate (10), b) forming a groove (17) at a selected area of said substrate (10) through said insulation film (11, 111), and c) depositing a multilayer insulation film (18, 19) and a conductive film (8) in stack on the surface of said groove (17). The method of claim 4, wherein said conductive film (8) is chiefly made of polysilicon. The method of claim 4 or 5, wherein an impurity having a conductivity type opposite to that of said substrate (10) is introduced into the surface area (29) of said substrate (10) prior to the formation of said insulation film (18, 19) in said step (c).

Inventors: KAWAMOTO, YOSHIFUMI, KURE, TOKUO, SUNAMI, HIDEO
Applicants: HITACHI, LTD.
Application year: 1983
Main classification: H01L27
IPC codes: G11C11, H01L21, H01L27, H01L29