METHOD AND ARRANGEMENT FOR RENDERING ENCIPHERED INFORMATION REPRODUCIBLE

Abstract: After the enciphering of a clear text, arbitrary control characters will occur which are not printable, such as, for ex­ ample, "return movement of carriage" and "new line". The method of rendering the whole enciphered text printable ob­ viates this disadvantage in accordance with the invention by subjecting all the enciphered characters to an additional pro­ cessing step. This processing step consists in that the charac­ ters of an enciphered text consisting of, for example, 5-bit characters, are subdivided into 4-bit words. The 4-bit words are then extended to a new 5-bit word in a manner such that it is ensured that printable characters are obtained.

Description: "Method and arrangement for rendering enciphered information reproduciblen The invention relates to a method and an arrangement for rendering enciphered information reproducible, which information consists of a series of characters of m bits each. Characters of five and eight bits, respectively, are utilized, for example, in the generally known telex code (CCITT No. 2) and in the CCITT-ISO code No. 5. These codes comprise characters which represent letters, digits and control symbols. Control symbols are, for example, the character "carriage return" and the character "new line". When clear text is enciphered, arbitrary control characters may be present in the enciphered text (the cryptogram). If the cryptogram is transmitted and is then deciphered, these control characters are converted into the original clear text. However, a problem arises if the cryptdgram is recorded, for example, by means of a line printer. The line printer will then respond to these control characters arbitrarily present in the enciphered text, as a resultof which the lay-out of the cryptogram is disturbed. The German Patent 2553897 proposes to solve this problem by transmitting non-enciphered each character representing a control character, and by preventing other characters being reproduced as control characters due to the enciphering. The invention has for its object to provide an alternative solution by which in a simple manner and with a minimum effort control characters are prevented from occurring in the cryptogram to be reproduced. According to the invention, the method of reproducing enciphered information of the above type is therefore characterized in that the method comprises the following steps: 1. blocks of n characters each are formed in the series of characters, which blocks therefore comprise n x m bits; 2. a block is subdivided into m groups of n bits each; 3. a storage device is addressed successively at the address given by each of the m groups and the contents representations of reproducible characters of m bits each - of each of the addressed locations are read out; 4. a series of said representations of reproducible characters is supplied to an output of the storage device for application to a reproducing device. The invention has the advantage that existing enciphering equipment can be extended very readily - i.e. without a change in the equipment itself - with a reproducing device!. In a preferred embodiment, the method of reproducing enciphered information according to the invention is constructed so that m = 5 and n = 4, that the 5 bits of each character of a block of four such characters are subdivided into a first part of 4 bits and a second part of I bit, so that the first parts of each character constitute respective groups and the second parts of the four characters together constitute a further group. It is favourable when the first part is constituted by the four most significant bits and the second part is constituted by the least significant bit. According to the invention, an arrangement for rendering enciphered. infdrmation reproducible, which information consists of a series of characters of m bits each, is characterized in that the arrangement comprises: a first storage device, which comprises n locations for storing a block of n characters; a register, of which an input is connected to an output of the first storage device, and a first address counter for cyclically passing through n counter positions, which address counter is connected to an address decoder of the first storage device, whereby at least one bit of the character present in the addressed storage location in each counter position is destructively read out and supplied to the register in that the arrangement further comprises a second address counter with m counter positions which is connected to a second address decoder of the first storage device and to the said register for successively addressing when the m counter positions are cyclically passed through, the respective storage locations of the first storage device and the said register, in that the arrangement further comprises a read-only memory which is provided with an address decoder which is connected to a further output of the first storage device and to an output of the register for addressing those storage locations in the read-only memory whose address corresponds to the contents of the storage locations of the first storage device and the register, and in that the read-only memory has an output to which the contents of the addressed storage locations of the read-only memory are successively supplied. Embodiments of the invention and its advantages will now be described in greater detail with reference to the drawings. In the drawings: Fig. la shows an embodiment of an arrangement for carrying out the method according to the invention; Fig. ib is a schematic representation of the contents of storage or register locations as used in the arrangement shown in Fig. la; Fig. 2 shows a table stating the occurring bit combinations and the characters associated therewith in the CCITT code No. 2, and Fig. 3 shows a flow chart of a further embodiment of the method according to the invention. Information in enciphered form is present on a transmission line 10 of the arrangement shown in Fig. la. The information consists of a series of characters, each character consisting of m bits. If, for example, the information is coded according to the CCITT code No. 2, a character consists of 5 bits. If the CCITT code No. 5 is used, a character consists of 8 bits. It will be assumed in the further description that m = 5, although the invention is not limited thereto. The characters represent in addition to digit, letter and punctuation symbols, control symbols, such as "carriage return" and "new line". The enciphered information on the transmission line is obtained by enciphering a clear text, which means that a character in the clear text is reproduced as a (quasi) arbitrary different character and that this different character is substituted for the original character. The enciphered information therefore comprises control symbols distributed over the cryptotext. The enciphered information is transmitted to the addressed location and is deciphered there in order to obtain the original clear text. In cases in which it is desired to record the text of an enciphered text, the problem arises that the control symbols occurring in the enciphered message are interpreted as such by the device by means of which this text is recorded. Due to the arbitrary occurrence of characters representing control symbols, the lay-out of the text of the enciphered text (the cryptogram) will be entirely disturbed. This is avoided by means of the arrangement shown in Fig. la, which is connected between a source of enciphered information and a device, for example, a line printer, which records the cryptogram. The characters comprising m in the example chosen 5, bits are grouped in blocks of n characters. The n characters of-one block are read into the n storage locations of a storage device 12, which is connected through an input 11 to the transmission line ;0. Each storage location can accommodate at least m (5) bits. With the given choice m = 5, it is advantageous to choose n = 4. This is for inter alia the following reason. The English alphabet in principle comprises 26 printable characters (in other languages, this number may be larger or smaller). If a group of p printable characters is chosen, on the condition that 2 is a power of 2 (i.e. 2n), for the English alphabet 2 will be at most 16, to which corresponds a value of n = 4. The storage device 12 is addressed through the address decoder 13 by means of a modulo-n counter 14 (therefore in the example chosen a moduto-4 counter). A register 16 is connected to an output 15 of the storage device 12. The register 16 can comprise at least n (4) bits. When the successive storage locations of the storage device 12 are successively addressed, each time one bit (the least significant bit, for example) of the character present at the relevant storage location is transmitted to the register 16 and is erased in the storage device 12. If the bits of one block of 4 characters of 5 bits ea di are enumerated as b1, b2, b3...b19, b20, after one complete cycle of the modulo-4 counter 14 the storage device 12 will comprise the bits b1-b4, b6-bgs b 11-b14 and b16-b19 and the -register 16 will comprise the bits b5, b10, b15 and b20, according to the configuration shown in Fig. 1b. The arrangement further comprises another counter 17, for example, a modulo-m counter. This counter is connected through an address decoder 18 to the storage device 12 and through an address decoder 19 to the register 16. If the modulo-m counter 17 passes through m (5) values the n (4) storage locations of the storage device 12 and the only location in the register 16 are successively addressed. A word consisting of 4 bits is present at each of these locations. These words are utilized as an address for a read-only memory. A further output of the storage device 12 and an output of the register 16 are connected for this purpose to the address decoder 21 of the read-only memory 20. The contents of the read-only memory are represented in the table of Fig. 2. The first column of the table indicates the list of possible addresses in decimal representation, whilst the second column indicates the contents of the storage location associated with a given address and the third column indicates which character in the CCITT code No. 2 corresponds to the bit combinations in the second column. Thus, for example, the word of 4 bits (the extreme left-hand bit is the least significant bit and the extreme right-hand bit is the most significant bit), 1011, i.e. the number, 13, is the address at which is stored a 5-bit word, 11010, which represents a character (J), which is printable, and therefore does not represent a control symbol. Thus, a flow of 5-bit characters becomes available at the output 22 of the read-only memory 20, which flow is free from undesired control symbols. An advantage cfthe invention is that without influencing the enciphering equipment, a method is provided which permits of recording the enciphered information in a suitable manner. This advantage becomes particularly manifest in cases in which existing cryptographic equipment is to be provided with these means. As has been already stated, the method according to theinv tion can also be used for other values of n and m. For example, in a system in which the CCITT code No. 5 is used, a character will consist of 8 bits (m = 8). By forming blocks consisting of 5 characters (n = 5) it is possible with the use of 3 registers of 5 bits each to address a read-only memory which will comprise 32 possible printable characters of 8 bits. An embodiment comprising a read-only memory, which is suitable both for printing characters in the CCITT code No. 2 and for printing characters in the code No. 5, is obtained if blocks consisting of 4 characters are formed. With the use of 4 registers of 4 bits each, a read-only memory can then be addressed, which also comprises 16 printable characters of 8 bits. Fig. 3 shows a flow chart of a further embodiment of the method according to the invention. The following explanatory texts relate to the inscriptions of the geometric figures explaining the functions and the states of the method of rendering enciphered information reproducible. It should be noted that such a time sequence of functions and associated states of the method of rendering enciphered information reproducible can be realized in universal sequential programmable logic circuits, such as commercially available microprocessors with associated storage and peripheral equipment. EMI7.1 <tb> Ruferreece <SEP> Inscription <SEP> Description <tb> <SEP> 23 <SEP> STRT <SEP> Start; <tb> <SEP> 24 <SEP> i: <SEP> = <SEP> 0; <SEP> the <SEP> parameters <SEP> i <SEP> and <SEP> i <SEP> <SEP> are <SEP> given <tb> <SEP> j: <SEP> = <SEP> <SEP> O; <SEP> a <SEP> value <SEP> 0. <SEP> The <SEP> values <SEP> of <SEP> the <tb> <SEP> RD <SEP> (n,m) <SEP> parameters <SEP> m <SEP> and <SEP> n <SEP> are <SEP> read <SEP> in; <tb> <SEP> 25 <SEP> i: <SEP> = <SEP> i+1 <SEP> the <SEP> parameter <SEP> i <SEP> is <SEP> incremented <tb> <SEP> by <SEP> one; <tb> <SEP> 26 <SEP> i > <SEP> n? <SEP> the <SEP> instantaneous <SEP> value <SEP> of <SEP> i <tb> <SEP> is <SEP> compared <SEP> with <SEP> the <SEP> value <SEP> of <tb> <SEP> n <SEP> reading <SEP> if <SEP> i <SEP> is <SEP> smaller <SEP> than <SEP> or <tb> <SEP> equal <SEP> to <SEP> n, <SEP> the <SEP> next <SEP> step <SEP> in <SEP> the <tb> <SEP> method <SEP> is <SEP> the <SEP> processing <SEP> step <tb> <SEP> represented <SEP> by <SEP> the <SEP> geometric <tb> <SEP> figure <SEP> 27. <SEP> In <SEP> case <SEP> i > <SEP> n, <SEP> the <SEP> next <tb> <SEP> step <SEP> is <SEP> that <SEP> represented <SEP> by <SEP> the <tb> <SEP> geometric <SEP> figure <SEP> 99; <SEP> <tb> <SEP> 27 <SEP> RD <SEP> (by) <SEP> <SEP> the <SEP> ith <SEP> <SEP> character <SEP> of <SEP> m <SEP> bits, <SEP> Bi, <SEP> <tb> <SEP> of <SEP> a <SEP> block <SEP> of <SEP> n <SEP> x <SEP> m <SEP> bits <SEP> is <SEP> read <tb> <SEP> in; <tb> <SEP> 28 <SEP> ti: : <SEP> = <SEP> LSB(Bi) <SEP> the <SEP> parameter <SEP> t. <SEP> is <SEP> given <SEP> the <SEP> value <tb> <SEP> of <SEP> the <SEP> least <SEP> significant <SEP> bit <SEP> of <tb> <SEP> the <SEP> ith <SEP> group <SEP> of <SEP> m <SEP> bits, <SEP> B <tb> <SEP> the <SEP> next <SEP> step <SEP> is <SEP> that <SEP> represented <tb> <SEP> by <SEP> the <SEP> geometric <SEP> figure <SEP> 25; <tb> <SEP> 29 <SEP> j: <SEP> = <SEP> j+1 <SEP> the <SEP> parameter <SEP> i <SEP> <SEP> is <SEP> incremented <tb> <SEP> by <SEP> one; <tb> EMI8.1 <tb> 30 <SEP> j <SEP> < <SEP> m? <SEP> the <SEP> instantaneous <SEP> value <SEP> of <SEP> i <SEP> <tb> <SEP> is <SEP> compared <SEP> with <SEP> the <SEP> value <SEP> of <SEP> m <tb> <SEP> read <SEP> in. <SEP> If <SEP> i <SEP> is <SEP> smaller <SEP> than <SEP> m, <tb> <SEP> the <SEP> next <SEP> step <SEP> in <SEP> the <SEP> method <SEP> is <tb> <SEP> the <SEP> processing <SEP> step <SEP> represented <tb> <SEP> by <SEP> the <SEP> geometric <SEP> figure <SEP> 31. <tb> <SEP> In <SEP> case <SEP> j <SEP> = <SEP> m, <SEP> the <SEP> next <SEP> step <SEP> is <tb> <SEP> that <SEP> represented <SEP> by <SEP> the <SEP> geometric <tb> <SEP> figure <SEP> 32; <tb> 31 <SEP> Aj <SEP> : : <SEP> = <SEP> MSB <SEP> (Bj) <SEP> the <SEP> jth <SEP> group <SEP> of <SEP> n <SEP> bits, <SEP> A <SEP> <tb> <SEP> is <SEP> constituted <SEP> by <SEP> the <SEP> n <SEP> most <SEP> <tb> <SEP> significant <SEP> bits <SEP> of <SEP> the <SEP> correspond <tb> <SEP> ing <SEP> character <SEP> B.; <tb> <SEP> th <SEP> J <tb> 32 <SEP> Am: <SEP> = <SEP> T <SEP> the <SEP> m <SEP> group <SEP> of <SEP> n <SEP> bits, <SEP> A <SEP> , <tb> <SEP> m <SEP> is <SEP> <SEP> constituted <SEP> by <SEP> the <SEP> n <SEP> least <tb> <SEP> significant <SEP> bits <SEP> t. <SEP> <SEP> (i <SEP> = <SEP> 1,9.. <SEP> <SEP> .n) <tb> <SEP> obtained <SEP> as <SEP> a <SEP> resit <SEP> of <SEP> the <tb> <SEP> processing <SEP> step <SEP> represented <SEP> by <SEP> the <tb> <SEP> geometric <SEP> figure <SEP> 28; <tb> 33 <SEP> Rj: <SEP> = <SEP> C(Aj) <SEP> at <SEP> the <SEP> address <SEP> A <SEP> of <SEP> a <SEP> storage <tb> <SEP> device, <SEP> the <SEP> contents <SEP> Rj <SEP> of <SEP> the <tb> <SEP> associated <SEP> storage <SEP> location <SEP> are <tb> <SEP> read <SEP> out. <SEP> R. <SEP> is <SEP> the <SEP> printable <tb> <SEP> character <SEP> of <SEP> m <SEP> bits; <tb> 34 <SEP> j <SEP> > <SEP> m? <SEP> if <SEP> i <SEP> <SEP> is <SEP> smaller <SEP> than <SEP> or <SEP> equal <SEP> to <tb> <SEP> m, <SEP> the <SEP> next <SEP> step <SEP> is <SEP> the <SEP> processing <tb> <SEP> step <SEP> represented <SEP> by <SEP> the <SEP> geometric <tb> <SEP> figure <SEP> 29. <SEP> If <SEP> i <SEP> is <SEP> larger <SEP> than <tb> <SEP> m, <SEP> the <SEP> whole <SEP> method <SEP> is <SEP> carried <tb> <SEP> out <SEP> again <SEP> for <SEP> a <SEP> next <SEP> block <SEP> of <tb> <SEP> n <SEP> x <SEP> m <SEP> bits; <tb> 35 <SEP> STP <SEP> Stop. <tb>

Claims: 1. A method of rendering enciphered information reproducible, which information consists of a series of characters of m bits each, characterized in that the method comprises the following steps: 1. blocks of n characters each are formed in the series of characters, which blocks therefore comprise n x m bits; 2. a block is subdivided into m groups of n bits each; 3. a storage device is addressed successively at the address given by teach of the m groups and the contents - representations of reproducible characters of m bits each - of each of the addressed locations are read out; 4. a series of said representations of reproducible characters is supplied to an output of the storage device for application to a reproducing device. 2. A method as claimed in Claim 1, characterized in that m = 5 and n = 4, in that the 5 bits of each character of a block of four such characters are subdivided into a first part of 4 bits and a second part of 1 bit, and in that the first parts of each character constitute respective groups and the second parts of the four characters together constitute a further group. 3. A method as claimed in Claim 2, characterized in that the first part is constituted by the four most significant bits and the second part is constituted by the least significant bit. 4. An arrangement for rendering enciphered information reproducible, which information consists of a series of characters of m bits each, characterized in that the arrangement comprises a first storage device, which comprises n locations for storing a block of n characters; a register, of which an input is connected to an output of the first storage device, and a first address counter for cyclically passing through n counter positions, which address counter is connected to an address decoder of the first storage device, wherebv at least one bit of the character present in the addressed storage location in each counter position is destructively read out and supplied to the register, in that the arrangement further comprises a second address counter with m counter positions which is connected to a second address decoder of the first storage device and to the said register for successively addressing when the m counter positions are cyclically passed through, the respective storage locations of the first storage device and the said register, in that the arrangement further comprises a read-only memory which is provided with an address decoder which is connected to a further output of the first storage device and to an output of the register for addressing storage storage locations in the read-only memory whose address corresponds to the contents of the storage locations of the first storage device and the register, and in that the read-only memory has an output to which the contents of the addressed storage locations of the read-only memory are successively supplied.

Inventors: VAN DEN ENDE, ANTONIUS CORNELIS JOHANNES
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1983
Main classification: H04L9
IPC codes: H04L9