FIELD EFFECT TRANSISTOR AND PROCESS FOR FABRICATING IT

Abstract: A field effect transistor (FET) comprises a source (8), a drain (9), and a control gate (6) on a compound semiconductor (e. g. GaAs) substrate (1). The FET has an ion-implanted channel layer (4) in the substrate adjacent the top surtace thereof, below the control gate. The concentration of ions (i. e. the carrier concentra­ tion) in the channel layer has an maximum value at the top surface and decreases monotonically from that surface towards the inside thereof. This is achieved by ion implantation for the channel layer through an insulating layer (2) on the substrate. The insulating layer is preferably an A1N layer, since such a layer has no adverse effects on the GaAs substrate during ion implantation and during subsequent heat treatment, and so allows higher uniformity of the threshold voltages of the FETs. FETs formed by this throug-implantation process have a high transconductance.

Description: FIELD EFFECT TRANSISTOR AND PROCESS FOR FABRICATING IT This invention relates to a field effect transistor (FET) and to a process for fabricating the transistor,and more particularly to a compound semiconductor FET with a high transconductance,and a process for fabricating it. Gallium arsenide (GaAs) integrated circuits (IC's) show promise as high speed devices for telecommunications and computers, as an alternative to silicon (Si) large scale integrated circuits (LSI's) and are, therefore, under vigorous investigation. For example, recently GaAs LSI's such as a 16x16-bit multiplier and a lk-bit static random access memory have been successfully fabricated. In order to improve the output-current-drive capability and the degree of integration of the GaAs LSI's, it is necessary to decrease the size of an element of a GaAs LSI, and to increase the transconductance gm of a GaAs FET. The gm of an FET is expressed by the following formula: EMI1.1 wherein C is the dielectric constant of the GaAs, p the carrier mobility, Wg the gate width, d the effective channel layer thickness, Lg the gate length, Vg, the voltage applied between the gate and source electrodes, and Vth the threshold voltage. The gm per unit gate width with a fixed Vth can be increased by shortening Lg, increasing p , or reducing d, at a constant E . The common way to decrease the device size and the gate capacitance is to shorten the gate length. Although most conventional semiconductors are of silicon, compound semiconductors such as GaAs are now under investigation, since they have a larger V than that of silicon. The present invention is directed at reducing d, i.e. reducing the effective channel layer thickness. Recently, the channel layer of an FET of a compound semiconductor LSI, such as a GaAs LSI, has in general, been formed by an ion implantation technique. The depth distribution of the concentration of implanted ions in the channel layer becomes approximately the Gaussian distribution given in the Lindhard, Scharf, and Schiott theory, and the effective channel layer thickness d can be considered to be approximately EMI2.1 wherein R is the mean projected range and a the p standard deviation of the projected range. When the kinds of the material of the compound semiconductor substrate to be ion-implanted and the ions which should be implanted into the substrate are given, the decrease in the ion implanting energy causes a decrease in both Rp and a, reducing the effective channel layer thickness d. The decrease in the ion implanting energy is, however, limited by the capability of the ion implantation apparatus along with the increasing sputtering effects and causes problems such as decreases in the controllability and in the uniformity of the ion implantation and a decrease in the carrier mobility. Further, conventional ion implantation techniques and the subsequent heat treatment for activating the ions result in problems such as the dispersion of the threshold voltage. Ion implantation into a bare compound semiconductor substrate may enhance dissociation of the components and oxidation at the surface of the substrate. Ion implantation through an insulating layer into a compound semiconductor substrate causes the incorporation of the element atoms of the insulating layer into the compound semiconductor substrate, which may have an adverse effect on the compound semiconductor. Heat treatment after ion implantation to activate the implanted ions may cause strains in the substrate due to the difference in the heat expansion coefficients of the substrate and surface protective layers. These result in defects and nonuniform carrier distribution of a channel layer formed in the compound semiconductor substrate, causing nonuniform distribution of the threshold voltages of the FET's across a wafer. Decreasing the standard deviation of the threshold voltage is necessary in order to increase the degree of integration of the LSI's. One of the inventors of the present invention has already proposed the use of an aluminum nitride (AIN) layer as a protective film for both the ion -implantation and the subsequent heat treatment. In the proposed method, the ions are implanted through the aluminum nitride layer. However, the trend is to use a thinner aluminum nitride layer as a protective film for the ion implantation and, therefore, threshold voltages may vary at different portions of a wafer. The deviation of the threshold voltages of FET's, tvth , is an important problem in fabricating GaAs LSI's. At present, when lk-bit LSI's are fabricated, AVth is allowed up to approximately 60mV, which can be attained by the prior art,though the yield of the LSI's is low. However, when 4k to 64k-bit LSI's are to be fabricated, AVth should be decreased, for example in the range of approximately 50 to 20 mV, which cannot be attained by the prior art as mentioned above. It is therefore an object of the present invention to provide a compound semiconductor FET having an improved transconductance. Another object of the present invention is to improve the ion implantation and the following heat treatment, so as to provide a process for fabricating FET's having an improved uniformity of the threshold voltages. According to one aspect of the invention, a field effect transistor (FET) comprising a source, a drain, and a control gate in and on a compound semiconductor substrate is characterised in that the FET has an ionimplanted channel layer in the compound semiconductor substrate adjacent a surface thereof, below the control gate, the concentration of ions in the channel layer having a maximum value at said surface and monotonically decreasing from said surface towards the inside thereof. According to another aspect of the invention, a process for fabricating an FET comprising a source, a drain, and a control gate in and on a compound semiconductor substrate is characterised by the steps of forming an insulating layer on a surface of the compound semiconductor substrate; ion implanting through the insulating layer into a layer in the compound semiconductor substrate adjacent said surface; and heat treating the ion-implanted compound semiconductor substrate to form a channel layer adjacent said surface thereof by activating the ions; wherein the conditions of the formation of the insulating layer, ion implantation, and heat treatment are controlled so that the concentration of ions in the channel layer has a maximum value at said surface and monotonically decreases from said surface towards the inside of the channel layer. By use of such a process, an FET can be achieved with an excellent channel layer thinner than that obtainable in the conventional process. In a process of fabricating an FET according to the present invention, it is preferable to use an AlN layer as an insulating layer on a GaAs substrate through which ion implantation is performed into the substrate. This AIN layer can prevent adverse effects in the ion implantation and in the heat treatment on the channel layer, as the A1N is the same III-V group compound as GaAs and therefore recoil Implantation is not a serious problem, and has a co efficient of linear expansion approximately equal to that of the GaAs which is effective for minimising the thermal stress from the cap to the crystal. FET's fabricated by using an A1N layer have a small standard deviation of the threshold voltages, improving the throughput of the products, particularly when the degree of integration is increased. Further, it is preferable to cover the A1N layer used for through-ion-implantation with another insulating layer sueh as A1N, or SiO2,Si3N4,A1203, or the like, before performing the heat treatment for activation,when the thickness of the A1N layer for through-ion-implantation becomes thinner in order to increase the transconductance of the FET. This is because a too-thin A1N layer will lose much of its property as an excellent surface protective layer during the heat treatment for ion activation. It has been found that another insulating layer may, however, be formed of a material other than AlN,such as SiO2 or Si3N4. Embodiments of the invention will now be described,by way of example,with reference to the drawings, in which Figs.1 to 7 are sectional views showing stages in the fabrication of an FET, Fig.8 is a graph of carrier concentration against depth; and Fig.9 is a graph of the standard deviation of the threshold voltage against threshold voltage. Figs.1 to 7 illustrate a process for fabricating an FET according to the present invention. In this example, semiconductor devices were fabricated each involving 100 GaAs depletion mode Schottky type FET's. Only one such FET is illustrated in the figures. Referring to Fig.1, on a semi-insulating GaAs single crystal substrate 1 containing approximately 0.8wt ppm chromium, a first AlN layer 2 is deposited to a thickness of approximately 55nm by a reactive sputtering technique. This first AlN layer 2 is preferably of a thickness that will not necessitate high energy ion implantation, which will result in a large deviation of the projected range, enlarging the effective channel layer thickness, and, therefore, decreasing the effect of improving the transconductance. The thickness of the first AlN layer 2 is generally in the range below 100 nm, preferably less, in this embodiment it is 55nm. In Fig. 2, a mask 3, e.g., silicon dioxide, 800 nm thick is placed covering the first A1N layer 2 and is selectively etched to open a window where a channel layer 4 is to be formed. Silicon ions are implanted at an acceleration energy of 59 keV and a dosage of 4 x 1012 cm 2 by using the mask 3, and through the first A1N layer 2 in the window into the channel layer 4 in the substrate 1. The acceleration energy and dosage were selected to obtain a distribution of ions in the channel layer 4 after heat treatment, with the maximum concentration at the top surface of the substrate 1, i.e., at the interface of the substrate 1 and the first AlN layer 2, when the first AIN layer 2 has a thickness of 55 nm. The acceleration energy and dosage depend on the kind and the thickness of the insulating layer and on the desired threshold voltages. In Fig. 3, the mask 3 is removed and a second AlN layer 5 approximately 80 nm thick is then deposited onto the first AIN layer 2, by a reactive sputtering technique. The implanted silicon ions are then activated by heat treatment at a temperature of approximately 8000C for a period of approximately 20 minutes. The characteristics of the thus ion-implanted GaAs substrate and the FET's fabricated therefrom will be described below in more detail. Conventional processes may be used after the heat treatment, one of which is described below as an example. In Fig. 4, the first and second AIN layers 2 and 5 are removed. A metal layer of, e.g., tungsten silicide (W5Si3), one of the materials that keep their Schottky contact with the GaAs substrate 1 even after a high temperature heat treatment to activate the implanted ions, is deposited over the entire surface to a thickness of approximately 500 nm, and is then patterned to form a control gate 6. A silicon dioxide layer 7 approximately 500 nm is then deposited and patterned to open a window corresponding to the source and drain regions 8 and 9. This silicon dioxide layer 7 is a mask for the following ion implantation and may be replaced by the before -mentioned silicon dioxide mask 3. Ion implantation of the silicon ions is performed at 175 keV and 1.7 x 1013 -2 cm cm2.In this ion implantation, the control gate 6 and the silicon dioxide layer 7 act as masks, and silicon ions are implanted to form a source region 8 and a drain region 9. In Fig. 5, the silicon dioxide layer 7 is removed and another silicon dioxide layer 10 approximately 150 nm is deposited over the entire surface, as a protective layer for the heat treatment. Preferably, this protective layer may be of A1N. Heat treatment is effected at approximately 8000C for approximately 10 minutes, + + resulting in an n -type source 8 and an n -type drain 9. In Fig. 6, the silicon dioxide layer 10 is removed. Gold germanium/gold layers are deposited by vapor evaporation, patterned by a lift-off technique, and alloyed at 4500C for 2 minutes to form a source electrode 12 and a drain electrode 13, thus completing the FET. Selectively, in the above-described example, a further A1N layer 14 may be used for a protective layer through which ion implantation is performed, as shown in Fig. 7. The FET's fabricated by the above-described process had transconductances of 270 mS/mm at a threshold voltage of 0.02 V and 300 mS/mm at a threshold voltage of -0.04 V, with a gate length of 1 vm. These transconductances are approximately 1.6 times those of FET's which have a Gaussian carrier concentration distribution. The standard deviation of the threshold voltages of the FET's according to the present invention was 44 meV when measured at about 100 points on the entire surface of a 2 inch-diameter wafer. Figure 8 is a graph showing the silicon ion concentration, i.e., carrier concentration in the direction of the depth of the channel layer. The solid line in the figure is obtained by the above-described process, and shows the maximum concentration at depth = 0, i.e., at the top surface of the channel layer, and monotonously decreases as the depth increases. The dotted line in the figure is obtained by ion# implantation without passivating the A1N layer and has the same threshold voltage as that of the FET of the solid line. The difference in the maximum concentrations of these two cases is needed to obtain the same threshold voltage. As seen from the graph, the depth of the channel layer can be thinner in an FET according to the present invention than in a conventional FET. This thinner depth of the channel layer improves the transconductance of the FET. In the present invention, low dispersion of the threshold voltages of the FET's also results from the through ion-implantation and heat treatment of a GaAs substrate covered by an AIN layer and another insulating layer thereon. Figure 9 illustrates the standard deviation of the threshold voltage in relation to the threshold voltage determined on the basis of long gate FET's fabricated by a process according to the present invention and by a conventional process. The said line represents an FET according to the present invention, and the dotted line an FET obtained by a conventional process. The graph in Fig. 9 clearly shows that the standard deviation of the threshold voltage in an FET according to the present invention is approximately one-third to one-half that of conventional FET's. For example, a threshold voltage of 0.5 V is obtained with the standard deviation of the threshold voltage of 16 mV. This is a result of using the process comprising the steps of forming an APN layer on a GaAs substrate, selectively ion implanting to form a channel layer, depositing another insulating layer on the A1N layer, and heat treating for activation, and allows the fabrication of LSI's of a higher degree of integration of 64k-bit or above. In this regard, it should be noted that although an A1N layer was used as the other insulating layer in the before-described example, it has been confirmed that another insulating layer such as SiO2 or Si3N4 may give the same effect. An FET according to the present invention preferably has a maximum concentration of silicon ions at the top 17 -3 surface of the channel layer of from 1 x 10 cm to 4 x 1018 cm 3. In the fabrication of an FET according tothe present invention, ion implantation of silicon through an A1N layer 20 to 100 nm thick, preferably 55 nm thick may be performed at 20 to 100 keV, preferably 59 keV and 1 x 1012to 4 x 1013 cm , and heat treatment for activating the silicon ions may be effected at 700 - 10000C, preferably 8500C for 1 to 300 minutes, preferably 20 minutes.

Claims: CLAIMS 1. A field effect transistor (FET) comprising a source (8), a drain (9), and a control gate (6) in and on a compound semiconductor substrate (1), characterised in that the FET has an ion-implanted channel layer (4) in the compound semiconductor substrate adjacent a surface thereof, below the control gate, the concentration of ions in the channel layer having an maximum value at said surface and monotonically decreasing from said surface towards the inside thereof. 2. An FET according to Claim 1, characterised in that the compound semiconductor substrate (1) is of gallium arsenide. 3. An FET according to Claim 1 or Claim 2, characterised in that the channel layer (4) is silicon ion-implanted. 4. An FET according to any preceding claim, characterised by a maximum concentration of silicon ions, 1x1017cm#3 to 4.0 x 1018cm at atthe top surface of the channel layer (4). 5. An FET according to any preceding claim, characterised in that the control gate (6) is of tungsten silicide. 6. An FET according to any preceding claim, characterised in that edges of the source (8) and drain (9) align with opposite edges of the control gate (6), respectively. 7. An FET according to any preceding claim, characterised in that the FET has a transconductance of 270 mS/mm to 300 mS/mm with a control gate (6) of lpm length. 8. A process for fabricating an FET comprising a source (8), a drain (9), and a control gate (6) in and on a compound semiconductor substrate (1), characterised by the steps of forming an insulating layer (2) on a surface of the compound semiconductor substrate; ion implanting through the insulating layer into a layer in the compound semiconductor substrate adjacent said surface; and heat treating the ion-implanted compound semiconductor substrate to form a channel layer (4) adjacent said surface thereof by activating the ions; wherein the conditions of the formation of the insulating layer, ion implantation, and heat treatment are controlled so that the concentration of ions in the channel layer (4) has a maximum value at said surface and monotonically decreases from said surface towards the inside of the channel layer. 9. A process according to Claim 8, characterised in that the compound semiconductor substrate (1) is of gallium arsenide. 10. A process according to Claim 9, characterised in that, in the step of ion implantation, silicon ions are implanted. 11. A process according to Claim 10, characterised in that, in the step of forming the insulating layer (2), an aluminium nitride layer is formed on the gallium arsenide substrate (1). 12. A process according to Claim 11, characterised in that, after the step of ion implantation and before the step of heat treatment, a second insulating layer (5) is deposited on to the aluminium nitride layer (2). 13. A process according to Claim 12, characterised in that said second insulating layer (5) is an aluminium nitride layer. 14. A process according to any one of Claims 8 to 12, characterised in that in the step of forming the insulating layer, an aluminium nitride layer (2) 50 to 200nm thick is formed; in the step of ion implantation, silicon 17 ions are implanted at 20 to 100 keV and 1x10 to 4x1018cm 2; and in the step of heat treatment, the temperature is held at 700 0C to 1000 0C for 1 to 300 minutes. 15. A process according to Claim 14, characterised in that in the step of forming the insulating layer (2), an aluminium nitride layer 55nm thick is formed; in the step of ion implantation, silicon ions are implanted at 59 keV and 4 x 1012cm 2; and in the step of heat treatment, the temperature is held at 8500C for 20 minutes. 16. A process according to Claim 14, characterised in that in the step of forming the insulating layer (2), an aluminium nitride layer 30nm thick is formed; in the step of ion implantation, silicon ions are implanted at 32 keV and 6 x 1012cm and in the step of heat treatment, the temperature is held at 8500C for 20 minutes. 17. A process according to any one of Claims 12 to 16, characterised in that said second insulating layer (5) is of SiO2, Si3N4, or A12O3.

Inventors: KAWATA, HARUO, NISHI, HIDETOSHI, ONODERA, HIROYUKI, YOKOYAMA, NAOKI
Applicants: FUJITSU LIMITED
Application year: 1983
Main classification: H01L29
IPC codes: H01L29, H01L21