DATA SYNCHRONIZATION

Abstract: The data synchronizer overcomes problems with mismatched recording and analysing equipment and can be used for multiple channel recording. By preliminary analysis a reference point is located on the record signal and used as a means to trigger the data processor. Each channel of the recorder is then played into the data processor using the data synchronizer to provide the triggering signal for the data processor. Each channel is thus able to be analysed on the same time reference. The Data Synchronizer (DS) decodes the recorded three level digital signal during playback and provides an output synchronizing pulse to externally trigger the computer system. This pulse occurs at the same instant relative to the data recorded each time the tape is played back, regardless of the playback speed.

Description: DATA SYNCHRONIZATION This invention relates to the synchronization of data for analysis wherein the data has been recorded on a number of channels. Where recording equipment and data analysis equip¬ ment is mismatched as with a multi-channel tape recording unit providing data to a single or dual channel input comput¬ er an effective means of comparing input signals occurring at the same time on different channels is difficult. To match the equipment by having the same number of input channels on the computer as output channels on the recorder can be expensive. Further where the events to be recorded are a scientific or engineering kind and occur randomly at large intervals of time a sophisticated means of time identifica¬ tion is needed to identify the signals on different channels coming from the same source. For example in monitoring explosions with multiple channel recording equipment and subsequently analyzing all data on all channels needs an accurate means of locating corresponding signals on each "' channel. To this end the present invention provides a data synchronizer which generates a record signal having a con¬ stant pulse and an interval pulse at a predetermined mul- tiple of constant pulses, to a recording unit and includes means to produce a triggering signal at a predetermined time interval from said record signal. The recording and analysing system of this invention comprises a recording unit having a plurality of recording channels and a data analyser having a fewer number of input channels and a data synchronizer which includes means to generate a record signal onto one channel of said recording unit during recording and means to produce a triggering signal from said record signal during play back of the record signal and said triggering signal being capable of activating analysis by said data analyser of information recorded on the plurality of channels of said recording unit. A preferred embodiment of this invention will now be described. A block diagram of the recording system is shown in Figure 1. The Data Synchronizer (DS) provides a three level digital signal for recording having voltage levels -IV, OV and IV. The frequency of this signal, f. , is set from a signal generator (S.G.) and is determined from the desired delay resolution and the ecording characteristics of the tape recorder (T.R.). This signal requires one data channel and may be recorded using direct or FM techniques. A block diagram of the playback system is shown in Figure 2. The Data Synchronizer (DS) decodes the recorded three level digital signal during playback and provides an output synchronizing pulse to externally trigger at the computer system (C.S.). This pulse occurs at the same instant relative to the data recorded each time the tape is played back, regardless of the playback speed. The synchronizing pulse may be delayed time-wise in steps ofΔt', given by: A , Tape recording speed 1 Tape playback speed 2f. The required delay is easily determined by using the HOLD facility of the Data Synchronizer (DS). The location of the output synchronizing pulse on the tape is determined by a pre-analysis of the tape to determine a convenient reference point prior to the occurrence of a signal to be analysed. The pulse is TTL compatible and allows for easy interfacing with TTL compatible circuits, and for positive and negative edge triggering. A depiction of the power circuit is shown in figure 3 and the data processor block diagram is shown in figure OMPI 4 while a timing diagram for the record mode is shown in figure 5, and a timing diagram for the playback mode is shown in figure 6. These drawings of this preferred embodi¬ ment will be described with reference to the two operational modes of record and playback. Typical parameter values for this application were as follows: Tape recording speed = 95.25 mm/s N = 1024 T = 12.8 s Tape playback speed = 95.25 mm/s 12.5 ms Record Mode The required switch positions are as follows: SW 1 ON SW 3 COUNT SW 4 RECORD • SW.5 OUT SW 18: desired SEQUENCE LENGTH, N Other switches: any position A signal generator is used to feed a square wave of frequency f. and voltage levels 0, IV into the record input connector Jl. The unity gain buffer 3A presents this input signal to comparator 4B. The output from 4B is inverted and converted to TTL levels by transistor Ql. The Q output of the latch 6B follows its data input D, and drives the binary counter 7 which gives 4- 2, 4-4, 4-8 and 4-16 outputs. The 4-16 output drives the binary counter 8 which gives 4-32, 4-64, 4-128 and 4-256 outputs. The 4-256 output drives the binary counter 9 which gives 4-512, 4-1024, 4-2048 and -4-4096 outputs. All of these outputs from the three binary counters and the output from latch 6B are inverted by buffers 10A to 10F, 11A to 11F and 15B. These buffered outputs drive indicators 12 to 114 which show the state of the counters. OMPI S-o Switches SW 5 to SW 17 determine which signals are fed into the NAND gates 12A, 12B, 13A and 13B. These NAND gates and the inverters 14A to 14D are equivalent to a 13-input AND gate, whose nett effect is to produce a pulse at the output of 14D once every time T, as determined by switch SW 18. This output is subtracted from the output of Ql, by amplifier 3B, and the resulting signal is made available for recording at connector J2. Every time 14D pulses, monostable 5B is triggered and lights up indicator 116 for about 0.25 seconds via buffer 15C. Playback Mode The required switch positions are as follows: SW 1: ON SW 2: closed (INHIBIT) resets counters unless SW 3 is closed (HOLD) open (ENABLE) allows counting to commence when negative pulse appears at Jl SW 3: open (COUNT) allows counting closed (HOLD) stops counting and holds counted value SW 4: contacts 6A (PLAYBACK) SW 5 - SW 17: . desired DELAY SW 18: > N The recorded synchronising waveform is played back into connector Jl. This is a three level digital signal with voltage levels - IV, OV and IV. The unity gain buffer 3A presents this signal to comparator 4A, which produces a positive pulse output every time a negative pulse occurs at Jl. This happens at intervals of time T' . The output from 4A is inverted and converted to TTL levels by transistor Q2, which controls the triggering of monostable 5A. The latch 6A is triggered by negative going edges and hence produces an output pulse every time the leading edge of a negative pulse appears at Jl. The monostable may be inhibited by switch SW 2 (when closed), OMPI r Λr- IPO . which consequently controls which negative pulse at Jl produces a monostable pulse. This pulse is high for about 70 seconds, which after being inverted by buffer 1-5A enables the binary counters 7, 8 and 9 to count. This counting mode is indicated by indicator 116. Enabling the latch 6A during a monostable pulse ensures that the binary counters are not reset, which would otherwise happen at the end of the pulse.. Because switch SW 3 enables latches 6A and 6B, at any instant it may be used to stop the counting and indicate the count value, by means of indicators 12 to 114. Hence during the preliminary playback, SW 3 is closed and put into HOLD at the required instant and then SW 5 to SW 17 are placed in the ON position if the corresponding indic- ators are lit. This playback may be done at a slow speed to make the process easier. Desirable small changes in the delay may be determined experimentally.. Switch SW 2 is opened and put into ENABLE anytime between the negative pulse at Jl which is required to start the counting, and the previous negative pulse. Closing of SW 2 and putting it into INHIBIT immediately resets the binary counters, provided that SW 3 is in the open (COUNT) position. The reset of the circuit operates as described under RECORD MODE, which produces an output pulse at connec¬ tor J3 after the desired delay as determined by switches SW 5 to SW 17. Using this technique, two data channels are stored in the digital computer system, and then the process is repeated to store the third data channel, thus maintaining time fidelity between the signals. Obviously this technique can be extended to include all unused channels of the tape recorder. ' ό i - - OMPI _ * IPO ,

Claims: THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS: 1. A data synchronizer which generates a record signal having a constant pulse and an interval pulse at a prede¬ termined multiple of constant pulses, to a recording unit and includes means to produce a triggering signal at a predetermined time interval from said record signal. 2. A recording and analysing system which comprises a recording unit having a plurality of recording channels and a data analyser having a fewer number of input channels and a data synchronizer which includes means to generate a record signal onto one channel of said recording unit during recording and means to produce a triggering signal from said record signal during play back of the record signal and said triggering signal being capable of activating analysis by said data analyser of information recorded on the plurality of channels of said recording unit. OMfl

Inventors: DICKENS JOHN D, DICKENS, JOHN, D.
Applicants: COMMW OF AUSTRALIA, THE COMMONWEALTH OF AUSTRALIA
Application year: 1983
Main classification: G11B27
IPC codes: G01V1, G11B5, G11B20, G11B27