SWITCHING CIRCUIT

Abstract: A circuit which achieves an improved speed/power product when switching capacitive loads. A high capacitance first node (A) is connected directly to pull-down means (7, 8) and is connected to pull-up means (2) through the channel of a depletion transistor (1). The gate of the depletion transistor (11) is controlled by a signal produced by inverting the voltage at a second node (8) formed by the junction of the depletion transistor (1) and the pull-up means (2). An output signal is taken from the second node (B). The depletion transistor (1) thus acts to isolate the first node capacitance (C p ) during pull-up. This results in an improved speed/power product when switching logic levels on the high capacitance node (A).

Description: Switching circuit. The input node of semiconductor logic circuits, particularly circuits which provide large numbers of separate input signal connections, is usually characterized by a high parasitic capacitance. This capacitance must, necessarily, be charged or discharged to effect switching of the circuit. If the power dissipation of the means used to charge or-discharge the node is held constant, the operating speed of the circuit is directly proportional to the node capacitance. Input node capacitance thus limits the speed/power product of prior art switching circuits. It is, therefore, an object of this invention to increase the speed/power product of switching circuits by isolating a capacitance during switching. In accordance with the invention the input node capacitance of a switching circuit is connected to its pull-up means through the channel of a depletion device. An output signal is derived from the voltage at a second node formed by the connection of the channel and the pull-up means. The gate of the depletion device is driven by the inverse of the signal at the second node. Positive feedback is thus provided to turn off the depletion device and isolate the parasitic capacitance during switching. The speed/power product of the circuit is thereby increased. The present invention will now be described by way of example with reference to the single figure of the accompanying drawing, which figure is a schematic circuit diagram of a decoder/driver circuit which incorporates an electric circuit made in accordance with the invention. Referring to the illustrated decoder/driver circuit, a pair of logical input signals m and n are applied, respectively, to the gates of enhancement transistors 7 and 8. The source terminals of transistors 7 and 8 are connected to an input node A which is characterized by a large parasitic capacitance C to ground. The drain p terminals of transistors 7 and 8 are connected directly to ground. Transistors 7 and 8 thus function to pull-down input node A toward ground potential whenever a HIGH logic level is applied to input m or input n. The gate and drain connections of depletion transistors 2 and 3 are respectively interconnected so that each of the devices functions as a current source. The source terminals of depletion transistors 2 and 3 are connected to a voltage supply V. The gate and drain of transistor 2 is connected to one end of the channel of a depletion transistor 1 at node B. The opposite end of the channel of depletion transistor 1 is connected to input node A. Transistor 2 thus functions to pull-up node A toward potential V whenever there is donduction through the channel of depletion transistor 1. Node B is connected to the gate of an enhancement transistor 5. The drain of transistor 5 is connected to ground. The source of transistor 5 is connected through depletion transistor 3, which is connected as a current source, to the potential source V. The connection between the source of transistor 5 and the drain of transistor 3 is designated node C. Transistor 5 thus functions to invert the signal on node B at node C. The inverted signal at node C is fedback to the gate of depletion transistor 1. A depletion transistor 4 and an enhancement transistor 6 are connected in series between the potential V and ground. The signal from node B is applied to the gate of transistor 4 and the signal from node Cis applied to the gate of transistor 6. The connecti#on between the drain of transistor 4 and the source of transistor 6 is designated node D. Transistors 4 and 6 thus function as a high power driver having an output at node D which corresponds to the signal at node B. When input m or n is HIGH, node A is kept LOW by conduction through transistor 7 or 8. Node C is HIGH; the resistance of depletion device 1 is therefore in its lowest state and the potential at node B is close to the potential at node A. When input m and input n go LOW, node A starts to charge and its potential rises towards the supply potential V. A voltage drop across the channel of trans is tor 1 makes node B slightly closer to potential V than node A. This potential rise is relatively slow since the large parasitic capacitance C (as well as the smaller p capacitance at node B) must be charged through the resistance of transistor 2. As node B reaches the switching point of transistor 5, node C starts to drop in potential. This cuases the channel resistance of device 1 to increase and results in node B rising toward potential V at a faster rate than node A. This positive feedback causes node C to fall at a faster rate and the resistance of device 1 to increase at a faster rate until the difference between the potential on node C and the potential on node A is less than or equal to the depletion threshold of device 1. At that point the channel resistance of device 1 is infinite. Node A is then clamped at a potential lower than the supply potential V; therefore when inputs m or n again go HIGH node A will discharge more quickly than if it had been charged to the full supply potential. Node A is effectively isolated from node B and the rise time at node Bis determined by the currentflow- ing through transistor 2 to charge the small parasitic capacitance on node B. The rise time at node D will directly track the rise time at node B. Node C is close to ground potential at this time. When input m or input n goes HIGH, transistor 7 or 8 starts to conduct. Node A discharges toward ground potential without hinderance from current through transistor 2 until the potential on node A is a depletion threshold below the potential on node C. At that point node B starts to drop in potential causing node C to rise in potential. This decreases the resistance of the channel of transistor 1 and creates positive feedback which causes node B to fall toward node A faster and further increases the potential on node C. Nodes A and B finally reach a potential close to ground and node C reaches full supply potential to pro duce the lowest possible resistance in the channel of device 1. The present invention allows isolation of parasitic capacitance at a node without requiring external clock signals to effect switching. The circuit is thus ideally suited for use in static memory applications.

Claims: 1. An electronic circuit for switching the potential at a high capacitance node from a first potential state to a second inverse, potential state; comprising pull-down means for switchably connecting the high capacitance node to a first potential; pull-up means for connecting a second node to a second potential, the second node being having a smaller capacitance than the high capacitance node; a depletion device having a channel which functionally connects the high capacitance node to the second node and a gate electrode which controls conduction through the channel; and means for inverting the potential state at the second node and for applying said inverted potential to the gate electrode of the depletion device. 2. In an electronic logic switching circuit of the type comprising: means for pulling-down the potential of a first node toward a low potential in response to the logical state of one or a combination of. several input signals; means for pulling-up the potential of the first node toward a high potential; and means which produce a logical output signal which is a function of the potential at the first node; the improvement comprising: a depletion device including a conduction channel which is connected between the first node and the means for pulling-up and a gate which controls conduction through the channel; and inverter means for inverting the potential at a second node formed by the connection between the depletion device and the means for pulling-up and for applying said inverted potential to the gate of the depletion device. 3. A circuit of claim 1 or 2, wherein the input node has a high parasitic capacitance. 4. The circuit of claim 1 or 2, wherein the pulldown means are enhancement mode transistors. 5. The circuit of claim 1 or 2, wherein the pullup means is a depletion mode transistor. 6. The circuit of claim 1 or 2, wherein the means for inverting is an enhancement mode transistor having a drain connected to ground, a source connected to the supply potential through a resistance; and a gate connected to the second node. 7. A decoder/driver circuit comprising: at least two input enhancement transistors, each having a drain connected to ground potential terminal, a gate connected for receipt of an input logical signal, and a source; a depletion device having a gate and a channel, a first end of the channel being connected to the sources of the input transistors; first pull-up means connected between a second end of the channel of the depletion device and a supply potential terminal; an inverting enhancement transistor having a drain connected to the ground potential terminal, a gate connected to the second end of the channel of the depletion device, and a source connected to the gate of the depletion device; second pull-up means connected between the source of the inverting transistor and the supply potential terminal; ; a driver enhancement transistor having a drain connected to the ground potential terminal, a source connected for transmission of an output signal, and a gate connected to the source of the inverting transistor; and a drive depletion transistor having a drain connected to the source of the driver enhancement transistor; a source connected to the supply potential terminal, and a gate connected to the second end of the channel of the depletion device. 8. The circuit of claim 7, wherein the first and second pull-up means comprise depletion transistor current sources.

Inventors: PUAR, DEEPRAJ SINGH
Applicants: NORTH AMERICAN PHILIPS CORPORATION
Application year: 1982
Main classification: H03K17
IPC codes: H03K17, H03K19, G11C7, G11C8, H02M1