A METHOD OF FABRICATING A MOS TRANSISTOR ON A SUBSTRATE

Abstract: The invention relates to fabrication techniques for the construction of MOS transistors to provide source/drain regions (20, 22) which are self-aligned and non-overlapping with respect to their gate electrode (16). The non-over-lapping feature is provided by defining a gate electrode (16) over a substrate (10), forming an implant mask of dielectic (18), for example, on the sides of the gate electrode (16), and implanting a source/drain region (20, 22) such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode (16) and the implanted regions (20, 22). The source/drain region (20, 22) is then heat driven until its side edge is substantially aligned with the edge of the gate electrode (16). Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.

Description: A method of fabricating a MOS transistor on a substrate This invention relates to a method of fabricating a MOS transistor on a substrate. It is particularly directed to improved processing techniques for fabricating MOS (metal oxide semiconductor) trans is tors in a large scale integrated circuit. A MOS transistor generally includes source/ drain regions in a substrate, and a gate electrode formed above the substrate between the source/drain regions and separated from the substrate by a relatively thin dlelectric. The relative alignment of the gate with its source/ drain regions is an important factor which influences the performance of the transistor. Conventional fabrication techniques usually cause edges of the source/drain#regions to be initially substantially vertically aligned with the edges of their gate. In subsequent heat treatment steps, however, the source/drain regions diffuse laterally. This results in the edges of the gate overlapping the source/drain regions. Consequently, undesired gate-drain overlap and Miller capacitances are created and the operating speed of the transistor is reduced. In an attempt to avoid the foregoing problem, it has been proposed to establish a photoresist or dielectric layer on top of the gate such that the gate can be undercut to provide a photoresist or dielectric area which overhangs the edges of the gate. This overhang defines a source/drain implant area which laterally separates the source/drain implants from the nearby edges of the gate. However, the amount of the undercut is difficult to control. Consequently, alignment between the gate and the source/drain regions fluctuates substantially. A related problem concerns the contacts for the source/drain regions. Except by imposing tight tolerances on the manner in which the contacts are patterned, it has been difficult to provide well aligned source/drain contacts which are well isolated from the gate electrode. For the foregoing-reasons, conventional fabrication techniques are not perfectly satisfactory for the construction of high speed, very large scale integrated circuitry, particularly where high packing density is a paramount concern. It is a general object of the invention to provide an improved fabrication technique for MOS transistors. It is a more specific object of the invention to provide a fabrication technique which results in MOS transistors having a well controlled and substantially reduced Miller capacitance and higher operating speeds. It is a further object of the invention to provide a fabrication technique whereby source/drain contacts are more easily self-aligned with respect to their gate electrode. According to the invention there is provided a method of fabricating on a substrate a MOS transistor having a gate electrode and -at least one source/drain electrode, comprising forming a gate electrode insulated from the substrate, forming an implant mask of, a controlled width on the sides of the gate electrode, implanting at least one source/drain region in the substrate such that the implant mask shields an underlying portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and a side edge of the implanted region, and heat driving the implanted source/ drain region until its side edge is substantially aligned with the previously separated side edge of the gate electrode whereby no substantial gap or overlap exists between the source/drain region and the gate electrode. Some ways of carrying out the invention are described in detail below, by way of example, with reference to the accompanying drawings, in which: Figures 1 to 4 illustrate the sequential construction of an exemplary MOS transistor fabricated in accordance with the invention wherein differential dielectric growth rate is employed, Figure 5 is a simplified top view of the transistor which is fabricated as shown in Figures 1 to 4, Figures 6 to 8 illustrate the construction of an exemplary MOS transistor employing an alternative method not requiring differential dielectric growth rate, Figures 9 and 10 illustrate how a MOS transistor is alternatively constructed with an implant mask comprising dielectric remnants, Figure 11 illustrates a variation on the method shown in Figures 9 and 10, Figures 12 and 13 illustrate how a MOS transistor is fabricated with an implant mask comprising photoresist remnants, and Figure 14 shows a variation on the method depicted in Figures 12 and 13. In the following description, a method is described for controlling the alignment of the source/ drain regions of a typical MOS transistor with its polysilicon gate electrode, and for forming self-aligned source/drain contacts. Thereafter, alternate techniques are described for achieving the same result in applications where polysilicon or other gate materials are used, and which provide control over various other aspects of fabrication. As described more specifically below, the self-aligned source/drain regions are formed even into bare silicon, if desired, while simultaneously providing an isolating layer of dielectric, for example, on the gate of the transistor. The way in which an exemplary MOS transistor is constructed with self-aligned source/drains to provide a reduced Miller capacitance and self-aligned contacts will now be described with reference to Figures 1 to 4. These figures illustrate the various stages of transistor construction which are effected by various steps in the method of fabrication. Referring first to Figure 1, there is shown a substrate 10 and field oxide regions 12 and 13 which are formed in a conventional manner, such as by local oxidation. Between these field oxide regions, an MOS transistor is fabricated by first forming a gate oxide 14 in the usual manner. Next, a polysilicon layer, designated Poly and doped to a sheet resistance of about 20 ohms per square, is defined and etched using photoresist patterning techniques. This leaves a Poly gate electrode 16 disposed above the transistorls intended channel. A dielectric layer 18, of oxide, for example, is then established on the top and sides of the gate electrode 16 and over the substrate adjacent the gate electrode such that the oxide layer on the top and sides of the gate electrode is relatively thick compared to the oxide layer adjacent the gate electrode over the intended source/drain regions. This is preferably accomplished by steam oxidation at 8500 C until about 500 nanometers of the oxide 18 are provided over the top (dimension A)of the gate electrode. This step of differentially growing the oxide provides a substantially similar oxide thickness on the side (dimension B) of the gate electrode and a relatively thin oxide layer (dimension C) over the intended source/drain regions. This thickness of the oxide layer at C will typically be about 170 nanometers because the oxide grows faster over the top and sides of the doped gate electrode. Irrespective of the specific dimensions of the oxide layer 18 and the way in which it is formed, the thickness of the oxide on the sides of the gate electrode (dimension B) is chosen so that later implanted sources and drains will be closely aligned with the vertical edges of the gate electrode 16 at the conclusion 6f transistor fabrication without any substantial gap or overlap between the source/drain regions and the gate electrode. That is, the oxide on the sides of the gate electrode acts as an implant mask to shield underlying portions of the substrate from implantation. Having established the oxide layer 18, source/ drain regions are implanted with arsenic or phosphorus, for example, to a depth which may be about 0.3 micron at 15 a dose of about 6 x 10 ions per square centimeter. Because of the masking effect provided by the oxide on the sides of the gate electrode 16, the source/drain regions 20 and 22 are not implanted adjacent the vertical edges of the gate electrode. Rather, a gap is provided between the gate electrode 16 and the source/drain regions to allow for subsequent diffusion of the source/drain regions. In some applications, it is desirable to increase the thickness (dimension A) of the layer 18 in order to provide improved isolation. Also, it may be desirable to independetly control or reduce the thickness C such as to implant the source/drain regions through a thinner oxide or no oxide at all. In these cases, an anisotropic etch, such as the plasma etch described below, may be used to remove or thin the oxide layers which overlie the source/drain regions. By using an anisotropic etch, the sidewall oxides (dimension B) are not substantially thinned, wherefore the gap between the gate electrode and the implanted source/drain regions is about 500 nanometers. However, it may be desirable to modify the anisotropy of the etch to controllably thin the oxide on the sidewall of the gate electrode to provide a smaller gap, 300 nanometers for example, where subsequent heat treatments are known to provide less lateral diffusion of the source/drain regions. After the source/drain regions have been implanted, standard processing occurs, including heat treating the structure. During such heat treatment, the implanted source/drain regions are driven deeper (to about 0.7 micron, for example) and driven laterally into substantial alignment with the vertical edges of the gate electrode (Figure 2). Good alignment is achieved by establishing the thickness of the oxide layer 18 on the sides of the gate electrode so that the known heat treatments which follow cause the edges of the source/drain regions to be driven laterally by a distance which is substantially equal to dimension B. After the heat treatment, an intermediate oxide layer 24 is deposited to a depth of about 500 nanometers, for example. As shown in Figure 2, this intermediate oxide layer preferably covers the entire structure, including the field oxide regions 12 and 13. Contact regions for the gate electrode and the source/drain regions are established by patterndefining a photoresist layer at 26, 28 and 30. As shown, a contact region is thus formed between photoresists 26 and 28. This contact region overlaps the field oxide region 12 and the Poly gate electrode. A similar overlap is created in the area between photoresists 28 and 30. Next, the oxide layers 18 and 24 are removed from the contact areas so that the substrate is exposed above the source/drain regions, preferably by using a plasma etch. The field oxide not masked by photoresist is also laid bare, and the unmasked oxide layer 18 which overlies the Poly gate may be thinned. Such a plasma etch may, for example, be carried out in a reactive plasma etcher capable of anisotropic etching. A parallel plate reactor with close spacing (about 2 centimeters) between the plates is effective using 50% CHF3 and 50% C F at a total pressure of about 700 millitorrs and a power of about 2000 watts. At this point, it should be understood that the dielectric layers 18 and 24 may be made of either similar materials or different materials. It may be desired to use different materials to provide an etch stop which avoids thinning dielectric 18 over the gate electrode. For example, the dielectric 18 may be nitride and the dielectric 24 may be silicon dioxide. In that case, differential oxide growth cannot be utilized but one of the alternate methods described below may be used. Where the dielectrics 18 and 24 are of a similar material such as silicon dioxide, a thin layer of another dielectric such as a nitride may be deposited on the dielectric 18 prior toaforming the dielectric 24. This also prevents etching from removing the dielectric 18 while the dielectric 24 is being removed. In any case, a dielectric layer 18 will remain on the Poly gate 16 to facilitate the formation of self-aligned contacts or interconnects for the source/drain regions. The directional etching described above provides the structure shown in Figure 3 wherein an intermediate oxide layer 24a and a photoresist 26 are left over the illustrated portion of the field oxide 12. The illustrated portion of the field oxide 13 is covered by an intermediate oxide layer 24c and photoresist 30, and the central portion of the remaining oxide layer is covered by an intermediate oxide layer 24b and photoresist 28. Referring now to Figure 4, the photoresists are removed in a conventional manner and an interconnect contacting layer 32, 34, such as aluminum or polysilicon, is provided so that the interconnect 32 overlies the source/drain region 20 and overlaps both the Poly gate and the field oxide 12. Likewise, the interconnect 34 overlies the source/drain region 22 and overlaps both the Poly gate and the field oxide region 13. These interconnect patterns may be used to electrically contact the source/drain and gate regions in the usual manner. Several advantages flow from the fabrication technique described above. Chief among these is the lack of undesired overlap between the finally processed source/ drain regions and the Poly 9ate. Consequently, the transistor has reduced Miller capacitance and, therefore, operates faster. In addition, the width of the Poly gate is substantially equal to the transistor's electrical channel length. This allows transistors with longer channel characteristics to be fabricted with smaller physical dimensions. Another significant advantage of this fabrication technique is that the source/drain contacts can be self-aligning This result is obtained because this technique allows etching to the substrate over the source/drain regions while the oxide layer 18 protects the Poly gate. Even if the photoresist 28 is misaligned with respect to the gate 16, the oxide 18 prevents shorts to the gate when the interconnects 32, 34 are provided for the source/drain regions. The manner in which the interconnects are provided also contributes substantially to a reduction in transistor size. As shown in the simplified top view depicted in Figure 5, the interconnect patterns 32 and 34 overlap the Poly 16 while covering the active areas designated by the shaded regions 36 and 38. Typically, the Poly and the active areas are about 2 microns wide, and an overlap of about 5 microns (dimension D) exists between the interconnect patterns and the Poly. Consequently, the size (dimension E) of the transistor is reduced to about 7 microns or less. Several alternatives are available for practicing the present fabrication technique. For example, the use of the intermediate oxide layer 24 may be eliminated and contact areas may be defined by a non selective etch. The resulting structure would be substantially as shown in Figure 4, except that the intermediate oxide would not be present. This technique is useful in forming self-aligned buried contacts. In addition, a nitrogen implant may be used -' prior to forming the oxide layer 18 (Figure 1) to reduce the rate of oxidation over the source/drain regions while not affecting the rate of oxidation on Poly. During this nitrogen implantation, the gate electrode is protected from the implant by a photoresist layer. Source/ drain implants may then be done after the oxide layer 18 is formed, and source/drain drive-in can be tailored to prevent overlap between the Poly gate electrode and the source/drain regions. The method described with reference to Figures 1-4 utilizes the differential growth rate of dielectric over the gate electrode and over the source/drain regions to provide self-aligned, non-overlapping source/drain regions. There are circumstances, however, where such differential rate of dielectric growth is difficult or impractical to obtain, such as when the gate electrode is made of a silicide or some other materials. In these cases, and in other situations where it is not desired to employ differential oxide growth, an alternative technique may be used to provide the structure shown in Figure 1 for fabricating properly aligned source/ drain regions. One such alternative is depicted in Figures 6-8. In these and the remaining figures, materials and structure which correspond to the materials and structure of Figures 1-4 have corresponding reference numerals followed by an alpha character. Referring to Figure 6, field oxide regions 12a and 13a and a dielectric layer 14a are established in any conventional manner. Then a layer of gate electrode material such as silicide, polysilicon, or other suitable material is formed over the dielectric 14a. Over the gate material 40, a dielectric 42 is formed of silicon dioxide or nitride, for example. If an oxide is selected, it may be either deposited or grown, but growing is preferred for better oxide integrity. Using conventional patterning techniques, portions of the layers 40 and 42 are selectively removed to provide the structure depicted in Figure 7. As shown, a gate electrode 40 is covered on its top by the dielectric 42 Referring to Figure 8, another dielectric 44 such as silicon dioxide is established over the dielectrics 42 and 14a and the field oxide regions. Consequently, this provides a composite dielectric having a thickness E over the gate electrode 40, a thickness F on the sidewalls of the gate electrode, and a thickness G over the intended source/drain regions. The thickness of the dielectric 44 on the sides of the gate electrode (dimension F) acts as an implant mask and is chosen so that later implanted sources and drains will be closely aligned with the vertical edges of the gate electrode 40 at the conclusion of transistor fabrication without any substantial gap or overlap between the source/drain regions and the gate electrode. The structure shown in Figure 8 may then be dry etched, as by the previously described plasma etch, to thin or even remove the dielectric 44 where it overlies the dielectric 42 and the intended source/drain regions 20a and 22a. This will essentially result in the structure shown in Figure 1. Implantation of the source/drain regions, and the subsequent processing and heat treatment described with reference to Figures 1-4 is then effected. The source/drain regions 20a and 22a will, of course, diffuse such that their edges are driven into substantial vertical alignment with the corresponding vertical edges of the gate electrode 40. Self-aligned interconnects for the source/drain regions are also provided by this alternate method, Another method of forming properly aligned source/drain regions may be used when it is desired to dope a polysilicon gate at the same time the source/drains are doped. This alternate method includes establishing a dielectric 14b (Figure 9) over the substrate and defining a polysilicon gate 16b over the dielectric 14b. Another dielectric 46, such as silicon dioxide, is then deposited (or grown) over the entire structure. Then the dielectric 46 isanisotropically etched, as by the previously described plasma etch, to expose the bare silicon substrate and the top of the gate electrode 16b as shown in Figure 10. Because of this unidirectional etch, remnants 46a and 46b of the dielectric are left on the sides of the gate electrode to mask the implantation of the source/ drain regions 20b and 22b. The gate electrode 16b may now be doped at the same time that the source/drain regions are implanted. Comparing Figures 1 and 10, it can be seen that similar structures are provided except that the gate 16b (Figure 10) is not covered by dielectric. Subsequent fabrication steps are similar to those described previously for heat driving the source/drain regions into alignment with the vertical edges of the gate electrode 16b, and for establishing the self-sligned contacts. It is sometimes preferred to leave a thin layer of oxide over the source/drain regions 20b and 22b during implantation. This variant is shown in Figure 11 in which an oxide layer 48, having a thickness typically less than 100 nanometers, is grown or deposited over the gate 16b, over the remanants 46a and 46b (not shown separately in Figure 11), and over the substrate. Source/drain regions 20b and 22b may then be implanted through the oxide layer 48 while the gate electrode 16b is simultaneously doped. The remnants on the sides of the gate electrode, as shown in Figure 10, may be:formed of material other than dielectric. One such material is photoresist, and it may be utilized as described in connection with Figures 12 and 13. Referring first to Figure 12, a dielectric 14c is established over the substrate 10c in the usual manner, and a gate electrode 16c of polysilicon, for example, is defined over the intended channel of the transistor. A layer of photoresist material 50 is then conformally established in a conventional manner over the entire structure. This results in a layer of photoresist having a depth H over the intended source/drain regions and over the gate electrode 16c. A greater depth I of photoresist occurs in the areas adjacent the sides of the gate electrode. The photoresist is then exposed and developed conventionally or anisotropically etched so as to remove a thickness H of it. Because of the greater depth of the photoresist at the areas adjacent the gate electrode, photoresist remnants or fillets 50a and 50b (Figure 13) remain on the sides of the gate electrode. These fillets serve, of course, to mask the source/drain implantation as described in the Other examples. The source/drain regions 20c and 22c may now be implanted. Because the gate electrode 16 is uncovered, this implantation also dopes the gate electrode. After the structure shown in Figure 13 has been obtained, the photoresist fillets 50a and 50b are stripped conventionally. Then an oxide layer 52 (Figure 14) may be established over the entire structure. Preferably, about 50 nanometers of the oxide 52 are grown thermally and the remainder is deposited. Next, the previously described processing occurs, including the heat treatment which drives the source/drain regions 20c and 22c into the depicted non-overlapping alignment with the vertical edges of the gate electrode 16c. When it is not desired to dope the gate electrode during source/drain implant, a layer of oxide may be deposited over the gate material prior to the application of the photoresist, such as shown in Figure 6. Processing then continues as described in connection with Figures 6 and 7 to develop an oxide layer over the defined gate electrode. The photoresist may then be applied and selectively removed as previously described, with the result that an oxide layer 54 (Figure 12) separates the photoresist from the top of the gate electrode. This oxide layer prevents the gate material from being doped during source/drain implantation. Although various methods have been described for fabricating an MOS device, all such methods provide an implant mask which ensures that the source/drain regions are properly aligned with the gate electrode at the conclusion of fabrication. In addition, the implant mask serves to isolate the gate electrode, particularly its edges, from interconnects so that the patterns which define the interconnects need not be held to tight tolerances. It will be obvious to those skilled in the art that many alterations and modifications may be made to the described method without departing from the invention By way of example only, the sequence in which some of the steps are practiced may be altered to suit a particular application or processing environment. Many other such changes will be obvious to those skilled in the art. Accordingly, it is intended that all such modifications and alterations be considered as within the spirit and scope of the invention as defined by the appended claims.

Claims: Claims: 1. A method of fabricating on a substrate a MOS transistor having a gate electrode and at least one source/drain electrode, comprising forming a gate electrode (16) insulated from the substrate (10), forming an implant mask (18) of a controlled width on the sides of the gate electrode (16), implanting at least one source/drain region (20, 22) in the substrate (10) such that the implant mask (18) shields an underlying portion of the substrate (10) from implantation to provide a gap between a side edge of the gate electrode (16) and a side edge of the implanted region (20, 22), and heat driving the implanted source/drain region (20, 22) until its side edge is substantially aligned with the previously separated side edge of the gate electrode (16), whereby no substantial gap or overlap exists between the source/drain region and the gate electrode. 2. A method as claimed in Claim 1, wherein said implant mask is formed by establishing a dielectric (18) on the top and sides of the gate electrode (16) and over the substrate (10) adJacent the gate electrode such that the dielectric (18) on the top and sides of the gate electrode (16) is relatively thick compared to the dielectric over the substrate, whereby source/drain implantation is masked by the relatively thick dielectric (B) on the sides of the gate electrode. 3. A method as claimed in Claim 2, wherein said dielectric (18) comprises an oxide which is grown at a differential rate to provide a relatively thin oxide layer over the substrate and a relatively thicker oxide on the top and sides of the gate electrode (16). 4. A method as claimed in Claim 3, wherein the oxide is grown in steam at a temperature of about 8500C. 5. A method as claimed in Claim 3, wherein the source/ drain region (20, 22) is implanted through the relatively thin oxide layer over the substrate. 6. A method as claimed in Claim 2, including anisotropically etching the dielectric (18) prior to implanting the source/drain region (20, 22) so as to remove dielectric over the intended source/drain region and yet maintain masking dielectric (B) on the sides of the gate electrode (16). 7. A method as claimed in any one of Claims 1 to 6, including forming an intermediate dielectric (24) over the gate electrode (16) and over the source/drain region (20, 22), patterning a contact area over the source/drain region (20, 22) so that the contact area overlies the source/drain region and overlaps the implant mask on the gate electrode (16), etching the contact area down to the substrate (10) while leaving the implant mask (18) on the sides and top of the gate electrode (16), and providing a conductive material¯ (32, 34) in the etched contact area to provide a contact for the source/drain region (20, 22) whereby a self-aligned contact is formed such that the gate electrode (16) is prohibited by the implant mask (18) from being shorted in the event the patterned contact area is misaligned. 8. A method as claimed in Claim 1, wherein the implant mask is formed by forming a first dielectric (42) on the top of the gate electrode (40), forming a second dielectric (44) over the first dielectric (42), over the sides of the gate electrode, and over the intended source/drain region (20a, 22a), and etching the second dielectric (44) where it overlies the intended drain/source region, whereby the second dielectric formed on the sides of the gate electrode (40) comprises the implant mask and the source/drain regions may be implanted at the etched portion of the second dielectric (44). 9. A method as claimed in Claim 1, wherein the implant mask is formed by forming a dielectric (46) over the gate electrode (16b) and over the intended source/drain region (20b, 22b), and anisotropically etching the dielectric (46) at the top of the gate electrode (16b) and the intended source/drain region so as to leave dielectric remnants (46a, 46b) on the sides of the gate electrode (16b). 10. A method as claimed in Claim 9, wherein the source/ drain region (20b, 22b) is implanted while the top of the gate electrode (16b) is substantially free of dielectric for doping the gate electrode (16b) during source/drain implantation. 11. A method as claimed in Claim 9 or Claim 10, wherein a relatively thin oxide (48) is foxed over the gate elec ¯trode (16b), the dielectric remnants (46a, 46b) and the intended source/drain region (20b, 22b) prior to implantation. 12. A method as claimed in Claim 1, wherein said implant mask comprises photoresist remnants (50a, 50b). 13. A method as claimed in Claim 12, -wherein said photoresist remnants are established by placing a conforming layer of photoresist (50) over the gate electrode (16c) and over the intended source/drain region (20c, 22c) such that a greater depth (I) of photoresist occurs adjacent the edges of the gate electrode (16c) than over the top of the gate electrode and over other areas of the intended source/drain region, and removing photoresist from the top of the gate electrode and from the source/drain region so as to leave photoresist remnants (50a, 50b) on the sides of the gate electrode (16c). 14. A method as claimed in Claim 13, including forming an oxide layer over the gate electrode prior to the application of the photore#sist to prevent doping of the gate electrode during source/drain implant. 15. A method as claimed in Claim 1, of fabricating on a substrate a MOS transistor having a gate electrode and a pair of source/drain regions, comprising forming a relatively thin gate insulator (14) over the substrate (10) and over the intended source/drain regions (20, 22), defining a polysilicon gate electrode (16) over the gate insulator (14) between the intended source/drain regions (20, 22), establishing a dielectric layer (18) over the gate electrode (16) and the gate insulator (14) such that the dielectric (18) is relatively thick at least over the sides of the gate electrode (16) and relatively thinner over the intended source/drain regions (20, 22), implanting the source/drain regions (20, 22) such that they are laterally offset from the substrate area below the gate electrode (16) by the thickness of the dielectric layer (18) on the sides of the gate electrode (16), heat driving the source/drain regions (20, 22) laterally until their edges are substantially vertically aligned with the sides of the gate electrode (16), etching contact areas so as to lay bare the substrate (10) holding the source/drain regions (20, 22) and yet maintaining the dielectric (18) on the sides of the gate electrode (16), and forming conductive contacts (32, 34) in the etched areas, whereby the source/drain regions (20, 22) are properly aligned with the gate electrode (16) and the metal contacts (32, 34) are aligned with the source/drain regions (20, 22) without shorting the gate electrode (16).

Inventors: ADAMS, JAMES R., DERBENWICK, GARY F., GNADINGER, ALFRED P., HANSON, MATTHEW V., RYDEN, WILLIAM D.
Applicants: INMOS CORPORATION
Application year: 1982
Main classification: H01L21
IPC codes: H01L29, H01L21