HIGH FREQUENCY COMMUNICATIONS

Abstract: A slow speed hf communications modem employs frequency and time diversity to overcome transmission problems due to noise, multipath etc. A digitally encoded signal is transmitted consecutively on five complementary 2-tone channels distributed within the hf band. A unique start-of-message (SOM) signal is generated (9) to precede a message transmission and an end-of-message signal (EOM) follows the message. The SOM signal is detected (18) to produce an accurate timing pulse (20) which initiates a clock in the receiver modem 3 arranged to sample each channel tone at times appropriate to receiving message signals. The noise in each channel tone is also sampled before (pre-data bit) and after (post-data bit) a signal data bit and the measured pre- and post-data bits are combined to assign a weighting factor to the associated message data bits. By providing SOM and EOM signals the modem is able to operate unattended.

Description: HIGH FREQUENCY COMMUNICATIONS The invention relates to radio communication within the high frequency band of kO Q Kz to 2.7 KHz and in particular to modems for transmitting and receiving radio frequency signals. High frequency (HF) communication performance can be degraded by three principle causes. Firstly propagation conditions can vary according to the time and frequency of transmission and also according to the geographical locations of the transmitter and receiver. Secondly, frequency selective fading and interεymbol interference can occur across the HF band because of ionospheric induced variations in multipath propagation. This arises as a result of ionospheric reflec¬ tion by means of which high frequency transmission beyond the line-of- sight is achieved. More than one ionospheric reflective mode can exist and this causes multipath reception. Severe distortion can be observed on the transmitted data and in-band noise or interference which would normally be disregarded becomes the predominant factor during periods of signal fading. These conditions can only be completely avoided by frequency changing but this is usually impracti¬ cable. Undesirable effects of multipath propagation can be counter¬ acted by employing appropriate signal processing before and after transmission. This is normally done using measurement of signal (spectral) spreading. The third cause of loss of performance is interference. Most of this encountered in the KF band is narrow band interference and can be avoided by changing the transmitting frequency. This is done by changing to an alternative channel frequency although where in-band frequency agility of the signalling tones can be used channel changing is not necessary. Wideband interference will always be a nuisance since it can only be avoided by frequency changing to a clear channel. When the wideband interference is impulsive, however, it can be avoided by adopting time dispersive coding into the tra_t_sr.itted signal format. h? object of the present invention is to provide high frequency system which employs both frequency diversity and time diversity in order to counteract the adverse reception problems encountered in HF comruπications. The invention provides a di itial communications transmitter including message enclcding means and means for transmitting each bit of an encoded message as a series of sequential signals on mutually differing frequency channels. In another form the invention provides a receiver for receiving a digital communications message wherein each data bit of a message is transmitted as a series of sequential signals on mutually differing frequency channels, the receiver comprising a plurality of detectors each responsive to a respective frequency channel, means for scanning the detector outputs sequentially to identify individual signals and means to assign to each signal thus<_etecteda weighting factor reflecting error probability and means to combine the /earihed signals to reconstruct the communications message. Advantageously each channel is two-tone, the first tone carrying the message and the second tone simultaneously carrying the complement of the message signal. By this arrangement the transmitter transmits only one tone or frequency at a time during transmission of a message and the transmission is at a fixed rate. Ey consecutively transmitting the sequential signals the power output from the transmitter can be kept constant. Preferably the transmitter includes circuit means to generate a uniquely coded Start-of-Message (SOM) signal and the receiver includes circuit means responsive to a received SOM signal to give an accurate timing signal for the scanning of the received signal. In an advantageous form the SOM signal is a 28 digit Barker-encoded signal. In order to scan the detector outputs the receiver includes ,_ clock which, on receiving the SOM timing signal, generates bit timing pulses so that each tone detector output can be sampled at appropriate time intervals for the data bits. In the preferred arrangement for assigning weighting 5 functions to the detected data bits, clock timing signals are used to sample the noise signal in each tone detector output during time intervals before and after the data bit time intervals, each time interval thus sampled being labelled in dependence on whether the noise signal is above or below a predetermined threshold level. The samples thus obtained are hereinafter tεππea 0 the pre-data bit and the post-data bit (check bits). In one embodiment the pre-data and post-data bits are combined and the weighting factor given to a data bit is zero if the combined pre-data and post-data bits include a noise signal. Using this arrangement the detected data bits from all the tone detectors with a non-zero weighting factor are combined using a simple majority, hereinafter called majority voting, to determine the best estimate for the information data bit. This method can, however, result in a good or uncorrupted detected data bit in one tone channel being ignored because one (or both) of the associated check bits is corrupt. In a second embodiment the weighting factor is derived from the square of the number of tones which are 0 not corrupted by noise, as determined by the pre-data and post-data bit sampling, the detected data bit at each tone being multiplied by the weighting factor and the sum of the products compared to a pre-determined threshold such that an estimate of the information data bit is only accepted when the ihnesbold level is exceeded. In a modification of the above best estimate method which ^> assigns a weighting factor by looking at the pre-data and post-data bits for a single information data bit, use can be made of the temporal variationintile observed noise content by using check bits from a number of successive data bits to derive a weighting factor to be applied to the oldest data bit considered. After analysing all the receiver channels when the confidence in a received data bit is below a preselected threshold an error symbol can be inserted in the received message. In one advantageous form the transmitter includes circuit means to generate a coded End-of-Mesεa.ge (EQ. ) signal and the receiver includes a detector responsive to the EOM signal so as to return the receiver to a standby condition. By this means automatic handling of received messages is facilitated. G PI ~ h Advantageously the invention provides a high frequency modem including a transmitter and a receiver. During transmission of a message the receiving circuitry can be connected to the transmitter output to check for transmission errors. The invention also provides a method of high frequency communication involving the successive steps of: 1. digitally encoding a message; 2. transmil±ing each digit consecutively as a signal in a frequency channel distributed within the high frequency band; 3. detecting the transmitted signals; 4-. scanning each frequency channel to detect noise, 5. assigning to each detected frequency signal a probability of error depending on the noise; and 6. combining the signals from each channel to reconstruct the transmitted message. The invention will now be described by way of example only with reference to the accompanying drawings of which: Figure 1 is a block diagram representation of a high frequency transmitter/receiver according to the invention; Figure 2 is a graph showing the locations in the HF band of the five 2-tone channels used by the transmitter/receiver; Figure 3 is a representation of a message format used by the transmitter/receiver; Figure k shows a single tone detection circuit in the receive modem of the transmitter/receiver; Figure 5 illustrates the timing sequences adopted in the mode of Figure h; ^υ_-_-A O PI Figure 6 illustrates graphically the processing of received signal; Figure shows a further part of the modem circuit used to obtain a best estimate from the five 2-tone channels; and Figure 8 is an alterrative circuit arrangement to that shown in Figure k. Figure 1 shows a schematic block diagram of the high frequency communication system which includes a keyboard 1 for message generation and control, a transmission modem 2 for translation of messages into a transmission forma , a receive modem 3 or decoding received messages and a visual display for presentation of received messages and assistance in preparation of messages for transmission. The keyboard 1 consisting of data keye 5 an control keys 6 is connected to a central processing unit (CPU)7 which controls the management of the complete system. A message for transmission is routed through the CPU 7 to a transmission message store 8. Also connected to the CPU 7 is an End-of- Message/Start-of-Hessage (EQK SOM) generator 9» when transmission is required the CPU 7 initiates an SOM signal from the SOM generator 9 ε_nd this is connected through a first pole 10 of a 2-pole switch 11 controlled by the CPU 7 to the transmission modem 2. The output from the transmission modem 2 is coupled by means of a centre-tapped trans¬ former 12 to transmission lines 13 * The output from the transmission message store 8 is connected to a secondpole 1 of the switch 11. TheCFU 7 controls the transmission of a message in such a way that the switch 11 firstconnects first pole 10to the transmissionmodem 2 for anSOM signal, seoar pole connected to the transmission modem 2 so that themessage stored in the transmission message store 8 can be transferred to the transmission modem 2 and then finally the transmission modem 2 is reconnected to first pole 10 of the switch 11 for an EOM signal. Onreception ofa transmittedmessage the received signal in the receive lines 15 is coupledbymeansof acentre-tapped transformer 16 througha first pole 17A of 2-poie switch 17 to the input ofan ΕΩH/S0 detector l8anda_5r__t input 19 of the receive modem >. The EOK/SQM detector l8 responds to a received SOM signal by producing a timing signal at its output 20 which is connected to a second input 21 of the receive modem 3« The timing signal prompts the receive modem 3 into readiness to accept a message and synchronises the operation of the receive modem 3 to allow O PI processing of the message to be done as will be described below. The processed message from the receive mode 3 is connected to a receive message store 22 through a 2-pole switch 23 for storage and also to the VDU display h. When an appropriate control key is depressed the contents of the receive message store 22 may be read out via translb_-ner 2k and lines 25 to a local copy output socket at 75 bauds. In a preferred arrangement the commαnications system has anQf~_--_-S facility and in this mode the CPU 7 is programmed to automaticaϋy clear the VDU display and to transmit an SOM sequence. The keyboard 1 is then connected ON-LINE to the radio transmission lines 13 and the VDU display . In this mode, adequatebufferstorage (not shown) must be providedbetween thekeyboard 1and the transmit modem 2 to compensateforthe data rate differential which will exist between them. The transmitted message is displayed on the VDU display k until an EOM has been transmitted, at which time the display is erased and the communications system is reverted to a standby condition in which a received message will be automatically stored in the receive message store 22 and displayed on the VDU display h. When used in the normal transmit mode the receive lines 15 are automatically cross-connected to the transnis- C-lrnlines13viathe secondpole 17B of the switch 17 to provide an on-line εc_£ check acility. Inthis modethe receive signalis decodedbythe receive mode 3a byaltering theconnection of the2-pole switch23the receive signalis disconnectedfrom the receivemessagestore 22 andthe VDUdisplay ^ an 'is connected to one input 26Ato atransmissioncomparatorcircuit 26. The transmitted signal is connected to a second input 26B to the transmission comparator circuit 26. ' An error alarm lamp (not shown)is connected to the transmission comparator circuit 26 so as to indicate any transmitted bit errors which are detected. Figures 2 and 3 show a diagrammatic representation of the signal format adopted by the transmit mode 2 for transmission of messages. Each data bit of a message is transmitted consecutively on five 2-tone amplitude shift keyed (ASK) modulated channels 27-31 comprising a total of 10 frequencies fl - flO distributed through the HF band from too Hz to2 * 7fcE-.. The information transmission rate of the transmission modem2 is at 10 bits/sec and with each channel arranged to produce a dedicated Mark (M) 3 or Space (S) tone 33 a frequencies f2 and fl respectively in the first channel 27 for example where the S signal is thecctπplement of the M signal, the transmission rate of each 2-tone channel 27 - 1 will be 50 ands and only one signal tone will be activated at any one time. As seen in Figure 3 a- transmitted message begins with a unique SOM signal which is transmitted during the times 3^ - 3^ on the respective channels 27 - 31- The SOM signal is a 28 bit Barker encoded signal used for frame synchronisation to ensure correct channel and bit synchronisation in a modem receiving the signal. In the receive modem the SOM signal is detected using matched filter detectors on every M and S detector output to ensure that synchronisation will be achieved even when only one signal frequency is operational. The time interval 39thus represents the total SOM frame synchronisation time. With a 50 baud data rate the SCM signal should provide a timing aquiεition of better than - 10 milliεecε. After transmission of the SOM signal a coded data preamble kQ is transmitted. The data preamble is shown in Figure 3 to consist of an S tone followed by two M tones with each S and M tone being transmitted consecutively in each cf the five channels 27 to 1 * At the 50 baud transmission rate of the modem each pulse kl is 20 milliεecε long and the time for each information bit k-2 is 100 milliεecs. The data preamble is transmitted to provide a stabilising period for the receive modem after frame synchronisation and before receiving a transmitted message. This is important where the receive modem includes signal threshold, timing and detector circuits whose circuit constants are determined by the received signal. A fixed preamble pattern such as that shown in Figure 3 is used for this purpose because the constants of these circuits can then be appropriately set at the relevant times in the preamble. At the end of each message an End-of-Message (EOM) signal is transmitted during the time interval k > on each of the consecutive 2-tone channels 27 to 31 by depressing an EOM key. In a convenient form the EOM signal can be the reverse of the SOM signal εo that a single EOM/SOM generator 9 can be used (Figure 1). The EOM message h3 " εisip-ifies message handling and control during reception and makes it possible for the modem to operate automatically in the receive mode and makes possible some degree of unattended operation. In the receive modem a matched filter is provided for each tone and this produces an output signal when the uniquely coded SOM signal is received. Each of the 10 tones fl to flO then produces an output signal on receiving the SOM signal. O Once channel and bit synchronisation is completed the channel signals are deπuLtiplexed and each 2-tone channel is threshold detected. The individual data bits thus detected are tested and labelled with a status condition dependent on the level cf inter- ference or noise present. Figure k shows one circuit arrangement for processing the received signal with the circuitry for only one tone fl shown for simplicity. The input kk to the receive modem 3 is connected via a centre tapped transformer ? to. an amplifier kβ having anAutomic GainControl (AGC) loop 'j> such that the modem can operatewith a nominalinput levelof 0 dB m in the frequency band of ^00 Hz to 2.7 kHz. Theoutput _ from theamplifier kβis connectedto arespe; tiveband-pass filter kj in eachsingle tone circuit. Theoutput from the filter ^9 is connected to a tone detector 0 connected in a circuit 1including an AGC-connected amplifier 52. Connected to the circuit 51 s achannel timingsignal S.. whichprovides a gatingsignalpulse corresponding in duration to the time during which information is transmitted on the first channel 27. Channel timing signals SIand alsoS2 to S5 for the other transmissionchannels 28 to 31are producedbyareceive clock (not shown) accordingto the format shown inFigure 5- Eachchannel timingpulse is kOmillisecs longand isrepeated every200millisecs. The channel timing pulses SIto S5are therefore consecutive intime withSI repeatedly followingS5- Also shown is the output 5-*-from anSI clockwhich periodically producesa groupof three pulseε 52-.- 5k_ f which the first pulse52__occurs immediately before an SI pulεe, the second pulse 53 n .occurs during an SI pulse and the third pulse 5^«_°ccurε just after an SI pulse. The channel timing pulseε SI applied to an input 53 of the AGC circuit 51 such that the AGC operates preferentially during the SI time intervals when the first tone fl signal data is present. A typical signal Sd from the output of the tone detector 0 is shown as a voltage-time graph 5^ in Figure 6. The graph shows random noise fluctuations 53 about a mean Λ noise level 5 with a signal 57 present having an amplitude Vs. The signal Sd is applied to the input 58 of a circuit 59 which subtractsthe mean noise level ^6 from the Sd signal $k. The signal Sd is applied to the non-inverting input 60 of a difference amplifier 6l. Sd is also connected to the inverting input 62 of the difference amplifier 61 via a switch 63 and a resistor 6 , The switch 63 has applied to it a timing signal SI, the complement of SI,such that it is closed whenever O PI there is no signal 31 and is open when a signal pulse SI is present. Thus when there is no signal SI the signal Sd applied to the inverting input 62 of the difference amplifier 61 charges an earthed capacitor 6 such that the voltage on the inverting input 62 corresponds to the voltage level 56 of the mean noise level. When a timing signal SI is present the switch 63 opens and any signal data present in the signal Sd is applied to the non-inverting input 60 of the difference amplifier 61. The output Sn from the difference amplifier 61 is a signal 66a, shown in Figure 6, in which the mean noise level is zero. The signalSn is applied via a connection 66 to a frame synchronising circuit. The frame synchronising circuit is a matched filter circuit which is arranged to detect the SOM signal 39 and, on detection, to produce an accurate frame sync output signal which is used to initiate clocktϊ__ώιg sequences in the receive modem. The signal Sn is also applied to the input of an assessor thre old circuit 67 which amplifies the signalSn whenit exceeds a threshold 67 (Figure 6) equal to -J V , where-V is the peak signal above the meannoise level. The signal Sn is connected to the non-inverting input 68 of a second • difference amplifier 69 and also to the inverting input 70 of the amplifier 69 via a voltage dividing resistor network 71, 72 and a switch 73« Resistors 71 a d 7 are connected in series between earth and the output of the difference amplifier 61 and their interconnection point 7k is connected to the switch 73« By making the resistance valves equal, the signal applied through the switch 73 to the inverting input 70 of the difference amplifier 69 is Sn/2. A capacitor 73is connected between, earth and the inverting input 70 and the switch 73 has the SI timing signal applied such that it is closed only during the SI intervaLs thus Λ when a signal of peak amplitude V iε present in the signal Snoutputof S Λ the amplifier 61 capacitor 73 charges up to a voltage of V / and the amplifier 69 acts as threshold amplifier, amplifying signals in excess of V /2. The output from the amplifier 69appears asa date signal 76 ε (Figure 6) inwhich the random noise fluctuations 55 are absent. The data signal 76is iεused asan input 77 to abit timingcircuit tokeep the cbamel timingsignals correctlysynchronised and is also connected to a threes ^e shift register 78. The purpose of the three stage shift register 78 is to sample the threshold detected signal at the times SI when data bits should be present and also to sample the signal during small time intervals immediately before and immediately after the SI times. If there iε no corruption of the input signal then these additional samples, hereinafter termed the pre-data bit and the post-data bit should have no signal present. In terms of digital logic the data bit may show either a logical "1" or a logical "0" and when there is no corruption of reception the pre-data and post-data bits should be a logical "O". Since no data is transmitted immediately before or after the data bit on any one tone the confidence in a detected data bit can be labelled by observation of the pre-data and post-data bits with two logical "0"s representing status good. Clock shift pulses for the shift register 78 are provided by the SI clock through connections 79 to each stage 8θ-δ2 of the register 8. The timing of the SI clock pulses 2 - k (Figure!?) iε so arranged that the output from the amplifier 69 is first sampled at the time determined by pulse 52 prior to the SI channel timing interval where the sample should thereforebe a "O 1 *. Timing pulse 53 during the SI interval then samples the data signal and will therefore give a data "l" or a data "0". Timing pulse k occurring after the SI intervalthen . samples the output from amplifier 69 after the data signal interval. Thus after the SI clock pulse k the shift register 78 will be filled with the pre-data bit in stage 82, the data bit in stage 8l and the post data bit in stage 8θ. The data signal is taken from the output 83 ofthe second stage 8l of the shift register 78. In the absence of noise or interference signals the pre-data bit in stage 82 and the post-data bit in stage 80 will both be "0". The outputs 8t and δ5___c_a t___serespective stages are provided as inputs to a "Ϊ.AND" gate. The output 86 from the "NAND" gate can then be used to qualify the status of the data bit with a "1" representing a good data bit and a "0" resulting from a "1" in either the pre or post-data bit (or both) representing a possibly ccc ~ _ ~ data bit. If during a transmission of a tone high levels of interference or noise are present in the same signalling bandwidth the pre- and post- data bits will probably be corrupted by the same extent as the data bit. Each channel Fl to F10 is processed in the same way and therefore there are produced ten data outputs together with status conditions which can be processed by a best estimate decoder. Figure 7 shows how the channel signals are combined for analysis by a best estimate decoder. The data output 83 from the fl tone detector (SI) is connected to the input 87 of an 8ϋ millisec delay 88 and thence OMPI to a best estimate decoder 89. The complementary output Ml from the first channel at the second tone frequency f2 is also connected to the input 9 of a second 80 millisec delay 91 before connection to the decoder 89. In a similar manner each M and S tone of the other four channels is connected to the decoder 89 via an appropriate delay such that all ten signals arrive simultaneously at the decoder. The second channel signals M2 and S2 are therefore delayed by 60 millisec, the third channel signals M3 and S3 by kQ millisec, the fourth channel signals MA- and Sk by 20 millisec and the fifth channel signals M5 and S are directly connected to the decoder 8 . In addition to these ten tone signals ten respective statue signals, as for example the outpu 86 from the Fl tone are also connected to the decoder 89. The beste__tir_ate decoder 89 is programmed with an algorithm whereby on receiving an information data bit on each of the five 2-tone channels only those tones are used which pass the pre- and post-data bit status check. A simple majority vote is then taken of the data bits to assign a "1" or a "0" to that information data bit. With these criteria for interpre¬ tation of a received signal the best estimate data is provided as an output from the decoder 89 and is connected to a character store 93- The character store is able to store all the data bits corresponding to a message character i.e. possibly five bits. If there should be no reliable data bit as indicated by all tones having at least one pre- or post-data bit "1" then an error signal at an error output 9^ from the decoder 89 causes an error symbol to be placed in the character stare 93 via an input 95 and actuates an error indicator adjacent to the VDU display hof the transmitter/receiver via a connection 96. ^-he outputfrom the character store 93 is connected to the receive message store 22. Tne received character from the character store 93 - a -i be connected as shown in the Figure 1 arrangement via a switch 23 to a comparator 26 where it is compared with the transmitted character when the system iε uεed in the transmit mode. Start and stop bits can be added to a transmitted message before and after each character so as to provide a means for error rate detection to give a further indication of the quality of the received message, to provide a means to indicate a false synchronisation and also to provide a means to indicate a circuit failure. A start/stop detector circuit 9 is connected to the data output 92 from the decoder 89. The start andstop 12 signals detected thereby are compared with signals produced by master clock circuits 98. If the detected start or stop signals are out of synchronisation with themaster clocka signal is producedat an output 99 connected to afalse synchroniεationalarm and the transmitter/receiver is automaticallyreturned toa standbymode. Thestart/stopbitsare re¬ generatedby a connection 99 from thestart/stopdetector 97 to theC-isr™.cter store 93inorderto preventloss ofcharacter synchronisation during subsequenthandling of the receivedmessage whichmight be caused by ~ -_- ~~ τi___ ofthese elements. Thetiming ofthemasterclock circuitsis controlled by a rame synchronisationsignal toinput 100 anda clockcorrection signal to input 101 frombit timingcircuits connectedto the outputs from the tone amplifiers 69in eachsignal tone detector circuit. An alternative circuit arrangement to that shown in Figure k for analysing the pre- and post-data bit time intervals in the signaloutjmts from each tone detector 50 is shown in Figure 8 where like reference numerals are used to indicate like integers. The output signal k from the tone detector 5 is connected to the input 58 ofadifference amplifier circuit which subtracts the mean noise from the signal. As in the figure k arrangement the mean noise level signal iε derived using the SI timing signal to charge the capacitor 65 connected to the inverting input 62of the difference amplifier 61. The output signal k which includes the data bit 37 in the SI time interval superimposed on the noise level signal 33 Is applied directly to the non-inverting input 60 of the difference amplifier 6l. The output εignal 66a from the difference amplifier 61 iε applied to an assessor threshold circuit 102 which iε a modification of the circuit 67 shown in Figure k. The signal 66a is applied to the non-inverting input 68 of the difference amplifier_2jp_5and a voltage of VS1 equal to half the peak voltage in signal66ais applied to the inverting input 70 of the amplifier. The amplifier 103 therefore A responds only when the voltage of the εignal 66a exceeds -5 VS1. As before the voltage dividing resistors 71 and 72 connected to the output of the amplifier 61 apply half the signal voltage to the capacitor 75 during the SI time interval when the switch 73 i- B closed. In this arrangement however the voltage developed across the capacitor 73 isnot applied directly to the inverting input 70 of the amplifier I03. The capacitor 75 voltage is connected to the inverting input 70 via a εwitch 10*. only when a εignal is applied frcra the output 105 of an "AND"gate106 13 which is produced only when a data "1" is accompanied by a status εig_al "1" indicating that the data bit is unlikely to be corrupted. When the switch 10A is closed the voltage across capacitor 75 is applied across a second capacitor 107 connected to the inverting input 70 of the amplifier 103. The timing is arranged such that the capacitor 107holds this voltage εignal (equal to VSl) until a subsequent data "1" and status "1" occur. The output signal from the amplifier 103 is connected to the inputs 108 - 110 of three similar integrate and dump filters. Input switches 111 - 113 opening respectively at times S5 immediately before the SI data bit time interval, SI and S2 immediately after the SI time interval ensure that the pre-data bit, the data bit and the post-data bit are coupled to the respective non-inverting inputs of difference amplifiers YLk - 116. During the time that the appropriate switch 111 - 113 is closed the εignal iε applied to the non-inverting input of the amplifier by an integrating PC combination 117, ll8. Subsequent to the sampling of the input signal in the three consecutive time intervals S5 } SI and S2 the capacitors llδ are short-circuited at time Sk by switches ll8a dumping their charges to earth. The outputs from the pre-data bit amplifier 11** and the post-data bit amplifier 116 are connected to a "NOR" gate 119 to give a logical "1" if a "0" ispresent at the outputs of both amplifiers. The output from the "NOR" gate 119 provides the signal at the status output 86 and also is coupled to the "AND" gate 106 together with the data output 83 from amplifier 115• A third input 120 is provided into the "AND" gate 106 and the timing signal S3 is applied to this input so that the switch 10^ in the assessor reference threshold circuit 102 is connected only at time S3 when a data "1" and a status "1" are present. The performance of the simple decoding algoritha described aboveis tobe cccrparedwith amajceityvoting ~ l ~~ > ~ ± _ _ s plicα to allthereceiveddata bits, irrespective of the polarity of any pre-or post-data bits. In this latter majority vote decoder the ten data bits corresponding tocrε information bit are summed. If the number of binary "1" data bits is greater than five the output bit is made a binary "1" and if the number of binary "1" data bite iβ less than five then the output bit is made a binary "0". When the number of narv 1ε and Oε is equal (ie five) the output bit can be made either 1 or 0 by a random selection provi V. distribution of 1s and Os in the original message. The measured performance of the sample pre- nd post-data bit decoding algorithm is slightly worse than that for the Majority Vote Decoder because the number of data bits used for decoding will at times be far less than ten. An error in a pre or post data check bit will remove its associated data bit whether or not it is in error. When errors are statistically independent such that an error in a pre-or post-data bit is uncorrβlated with an error in a data bit then the decoder performance is degraded relative to the majority vote decoder. When, however, there is a statistical dependence between data bite and their associated pre-and/or post-data check bite then the performance of the pre-, post- data bit decoder will be better than that of the majority vote decoder. The invention described thus far has adopted a simple algorithm for interpretation of a detected signal by accepting only data whose ~ ZG- a post-data bite are not corrupted by noise or interference. An alternative approach to improve signal aqtiisition in a noisy environmeit is to apply a statistical weight to each data point, the weight taking into account the number of tones which register a particular data bit. Considering a data processor arrangement as shown in Figure 7. every 100 millisecs during a message transmission one data bit and one statue bit will be provided as an input froa each tone detector into the decoder89- The pre-data bit and post-data bit are added to produce, a status number or status bit such that a '*0 M is produced when there is no error in the pre- or post-data bit i.e. status good, a "1" is produced if one bit (pre- or post-) is in error and a "2" is produced if both bits are in error. These nuaberε can then be incorporated into an algorithm to compute a weighting for each data bit and thence a best estimate. A one second tranche of data is analysed by providing a 10-stage shift register at the input of each tone and status bit in the decoder 89. This tranch will thus include ten data bits and status bits successively received by each of the ten tone detectors at times t_. to t- . A recursive algorithm has been chosen to compute a statistical weight Wf to be applied to the data bit at time t=t % for each of the ten tones F. bit for tone F at time t then the statistical _>_.--_A CMPI 11 and 10 t=1 J A data vector D, is assigned to each data bit according to thef__J_ov.__g In the H channels where a data 1 represents an in ormation 1: D t^ M ^ = +1 for data 1 = -1 for data 0 and In the complementary S channels where a data 0 represents an information 1: = +1 for data 0 F Each data vector D is then multiplied by the appropriate statd-rtical F weight W, and the products sumnsed to give: Z 10 D. = CD t * F=1 The sign of the resulting number is used to give an estimate of the information data bit. A total of + 1000 will result from a "1" information data bit in the M tone of each channel with no data corruption i.e. each status bit being a "0 M and a total of - 1000 will result under the βaπe transmission conditions if the information data bit is a "0". Confidence in the estimate of the information data bit will therefore be 100^ if the products total is + 1000 or - 1000 and will reduce to zero for a products total of zero. It is then necessary by trial in a noisy environment while retaining acceptable reception to assign a πiniaua threshold for the modulus of this product sum such that the decoder will accept an estimate above this threshold and reject an estimate below it. Thus in the former case a best estimate data bit is produced at the data output 92 and in the latter case there is an error signal produced at the error output ^» TITUTE SHEET The discontinuity in the weighting function is introduced to improve the performance of the aodera when operating with in-band inter erers. Thus when the number of pre- or post-data check bits in one tone band J is equal to 10 or more then the statistical weight W7 iβ set to zero and that channel is ignored. Analytically it has been shown that with a statistically randoπ bit error rate (EER) applied to all ten tone channels the aodem has a performance only m___>gin__-lly worse than a 10 - channel majority voting decoder but slightly better than the simple pre-/post-data bit decoder. When the _____ is random ( 0?ø to a number ( • ClO) of the tone channels the performance is considerably better than the other two decoders while with 5-^ BER to nine channels the performance of the decoder almost matches that of a single channel response under ideal conditions. Thus by applying the recursive decoding algorithm to the detected signals and pre-/poεt-data check bits the modem has demonstrated the ability to obtain the optiraum detectable output even when the input to the receiving tone channels is severely corrupted by noise. By adopting time and frequency diversity in the modem a further advantage results in that the aa-cLmum transmission power is available at each tone transmitted thereby assuring greater range and greater noise rejection capability than systems which employ simultaneous transmission of two or more tones. A set of unique supervisory signals is preferably provided which will be usable during either the on-line or normal working modes. Any one of the supervisory signals could then be called up at any time using pre-declared code words. The supervisory signal could, for example, instruct the receiving modem that the message transmission is to be-repeated five times (say). When thus operated in the normal transmission mode the transmission can be automatically sent from the transmission message store to the appropriate number of times and the receive modem can interpret the supervisory signal to prepare for the repeated message. When repeated messages are received they can be stored and compared and further assessments made on the received characters to further reduce the possibility of error. ' - - » - - - - - - Cl.iPI

Claims: AMENDED CLAMS [received by the International Bureau on 25 June 1982 (25.06.82) original claim 1 cancelled; claims 2 to 13 unchanged] 1 . (Cancelled) 2. A digital communications receiver for receiving a di«i '-lly encoded message '.'.'herein each data bit of the encoded message is transmitted as a series of sequential signals in differing frequency channels, characterised in that the receiver comprises a plurality of detectcrs (i + 9) each responsive to a respective frequency channel, means for scanning each detector output sequentially to identify individual signals (S1-S5), means (7°) to assign to each εignal thus detected a weighting factor reflecting error probability and means (89) to combine the weighted signals from the differing channels to reconstruct the message. 5. A digital communications apparatus comprising a transmitter and receiver wherein the transmitter includes message encoding means and means for transmitting each bit of the encoded message characterised in that the transmitter includes means for transmitting each bit as a series of sequential signals in different frequency channels (27-3 distributed in the hf frequency band, and the receiver comprises a plurality of detectors (49) each responsive to a respective frequency channel, means for scanning each detector output sequentially to identify individual signals (S1-S5), means (78) to assign to each signal thus detected a weighting factor reflecting error probability and means (89) to combine the weighted signals from the differing channels to reconstruct the message. 4« A digital communications apparatus according to claim 5 character¬ ised in that each channel is two-tone with the first tone (52) carrying the message signal and the second tone (55) simultaneously carrying the complement of the message signal. 5. Signal digital communications apparatus according to cl irπ 4 chπracterised in that each receiver- chf-nπel further includes ε detector responsive to the respective second tone. 6. A digital communications apparatus according to claim 5 char_.ctεr- iεed in th__t the transmi ter includes circuit π.eanε (9) to generate a - - uniquely coded Start-of-Message (SOM) signal and the receiver includes circuit means (18) responsive to a received SOM signal to give an accurate timing εignal (20) for scanning of the received signals. 7- A digital communications apparatus according to claim 6 characterised in that the receiver includes a clock which, on receiving the SOM timing signal, generates bit timing pulses (S1-S5) at the same bit intervals as the received signals, so that the output from each tone detector can be sampled during appropriate time intervals for message bits. 8. A digital communications apparatus according to claim 7 characterised in that the output from each tone detector (k$) is sampled in the bit interval before (pre-data) and in the bit interval after (post-data) the appropriate message bit time interval, each sample taken during a message bit time interval being labelled in dependence upon whether the noise determined by the pre-data (82) and post-data (8θ) sampling is above or below a pre-determined threshold level. 9. A digital communications apparatus according to claim 8 character¬ ised in that the outputs (83) from the tone detectors sampled during the time intervals appropriate to a single message bit are combined using only the channel tones having no detectable noise in the pre-data (82) and post-data (8θ) bit intervals and majority voting is adopted to deterine the message bit.. 10. A digital communications apparatus according to claim 8 characterised in that all the channel tones (87. 90) sampled during the time intervals appropriate to a single message bit are combined adopting majority voting (89) to determine the message bit, a weighting function is derived from the square of the number of channel tones which have no detectable noise in the pre-data and post-data bit intervals, and the weighting factor compared to a pre-determined threshold to determine acceptance of the message bit. 11. A digital communicationsapparatus according to claim 8 characterised in that the pre-data (82) and post-data (8θ) bits for each channel tone are' combined to give a first status bit (86) for a first associated message bit, the status bits for a number of successive message bits are combined with the first status bit to provide a weighting factor for the first message bit and the weighted message bits for each tone are combined. f O PI 12. A digital communications apparatus accordingly to claim H character¬ ised in that each received tone message bit and associated status bitfor each tone are connected to the inputs of a delay circuit (88, S _ )ax ~ - ~~~~ ed such that the message bits and status bits for each channel tone are simultaneously connected to separate shift registers, the status bits from each stage of a status bit shift register being combined to give the weighting factor for the first message bit in the associated message bit register. 13. A digital communications apparatus according to any one of claims 3 to 12 characterised in that the transmitter includes means (9) to generate a uniquely coded End-of- essage (EOM) signal and the receiver- includes detector means (18) responsive to an EOM signal so as to return the receiver to a standby condition. STATEMENT UNDER ARTICLE 19 The invention differs from the prior art in that each received bit, transmitted successively at a number of differing frequencies is assigned an error probabilitywithout the need for transmission of error bits. The thus weighted outputs from the differing frequency channels are then combined in making the decision whether a data "1" or a data "0" is present. In preferred arrangements by suitable weighting and channel combination there has been found a considerable enhancement of the ability to communicate with minimum error in very noisy u.f. environments. 1- •-/-'! -0

Inventors: WILKINSON ROBERT GRAHAM
Applicants: UNITED KINGDOM GOVERNMENT, WILKINSON ROBERT GRAHAM
Application year: 1982
Main classification: H04L1
IPC codes: H04B1, H04L1, H04L27