GATE TURN-OFF THYRISTOR

Abstract: A gate turn-off thyristor is disclosed, which comprises semiconductor substrate (1) in which a cathode emitter layer (5), a first base layer (4), a second base layer (3), and an anode emitter layer (2) are formed in this order such that pn junctions are made between respective adjacent ones of the layers. The cathode emitter layer (5) are divided into portions each of which is exposed at one of the main surfaces of the semiconductor substrate (1), the anode emitter layer (2) is exposed to the other main surface thereof, each of the separated cathode emitter layer portions (5) is made in low resistance contact with an anode electrode (7) and the second base layer (3) has a thickness W nB [µm] determined by the condition: W nB ≧ 3.817 × 10⁻¹·V BO - 2.550 × 10⁻⁴·V BO ² + 1.133 × 10⁻⁷·V BO ³ - 2.000 × 10⁻¹¹·V BO ⁴ or W nB ≧ 3.200 × 10⁻¹·V BO where V BO [V] is a breakover voltage.

Description: GATE TURN-OFF THYRISTOR This invention relates to gate turn-off thyristors and particularly to the junction structure of a gate turn-off thyristor (hereinafter, referred to as the GTO thyristor). The thyristor consisting of 4 layers of pnpn has an advantage that it can control a large electric power as compared with the transistor consisting of three layers of pnp or npn, but has also a defect that it cannot be restored from the on-state to the off-state by only a gate signal. Thus, a junction structure has been devised of the cathode emitter layer where the cathode electrode is provided, the first base layer which is adjacent the cathode emitter layer and at which the control electrode is provided, and the second layer which is adjacent the first base layer and at which the control electrode is not provided, so that the GTO thyristor has been realized which can be turned off by only the gate signal. More specifically, the width of the cathode emitter layer is reduced and surrounded by the control electrode, the lateral resistance of the second base layer beneeth the cathode emitter layer is reduced to permit the gate signal to reach the center of the cathode emitter layer, and in the on-condition, the amount of carriers accumulated on the second base layer is reduced so that the gate current necessary for turning off or the amount of charge drawn through the gate can be decreased. To decrease the amount of accumulated charges, a life time killer such as gold is doped (as disclosed in the Japanese Patent Publication No. 31876/1972), or the anode emitter layer and the second base layer are connected to the anode electrode in ohmic contact, i.e., the so-called anode emitter shorting structure (the Japanese Patent Publication No. 10143/1980) is used. When the GTO thyristor is used for a main switching element in a power converter such as an inverter, there is no problem upon normal operation, but current is extreamly increased upon occurence of shorted load, shorted thyristor-arm or like because the GTO thyristor has no current limitting action. As a result, the current to be cut off in the GTO thyristor becomes very large, and cutting off the current exceeding the limit will fail to turn off the GTO thyristor, resulting in the permanent break-down of the thyristor. Therefore, in the prior art, a snubber circuit having a diode, a resistor and a capacitor is connected in parallel with the GTO thyristor, thereby preventing the GTO thyristor from failing to be turned off. This results in not only a complicated circuit arrangement but also a large size. Accordingly, it is an object of this invention to provide a GTO thyristor which requires substantially no snubber circuit, and can be used in a simple and small-sized circuit. It is another object of this invention to provide a GTO thyristor which requires substantially no snubber circuit and has a satisfactory switching characteristic. The feature of this invention is that the thickness, WnB of the second base layer constituting the GTO thyristor is designed to satisfy the condition expressed as a function of the breakover voltage VBO as follows: WnB # 3.817 x 10-1.VBO - 2;550 x 10-4.vBO2 + 1.133 x 10 7.VBo - 2.000 x 10 .VBO preferably, WnB 2 3.200 x 10 VBO nB This invention will become more readily understood from the following exemplary description taken with the accompanying drawings, in which: : Fig. 1 is a graph showing the safety operation region upon turn-off switching of the GTO thyristor; Fig. 2 is a graph showing a characteristic required for the GTO thyristor; Fig. 3 is a connection diagram of a conven tional snubber circuit; Fig. 4 is a graph for the design of the GTO thyristor according this invention; Fig. 5 is a cross-section of a unit GTO thyristor of the GTO thyristor according to this invention; Fig. 6 is a plan of the anode side showing one embodiment of this invention; Fig. 7 is a cross-section of a unit GTO thyristor used in another embodiment of this invention; and Fig. 8 is a cross-section of a unit GTO thyristor used in still another embodiment of this invention. The inventors, after detailed examinaslon of the turn-off breakdown phenomenon in the GTO thyristor has found that unless the locus of the instantaneous value of each of the anode-cathode voltage and anode current upon turn-off switching of the GTO thyristor exceeds a limit line, the turn-off operation is successfuly performed. In Fig. 1, each of the curves 1 and 2 shows, as an envelope, the locus of instantaneous values of different anode voltages and currents of a GTO thyristor which were obtained when the GTO thyristor could be turned off. The curves 1 and 2 shows the envelope obtained with respect to two different GTO thyristors. Within each envelope, the GTO thyristor can operate with safety. Namely, the curves 1 and 2 are the limit lines within which the respective GTO thyristors can be turned off. As shown in Fig. 1, the anode voltage is substantially constant in the region in which the anode current is large, but tails in a skirt in the region in which the anode current is small. The constant voltage (V1 and V2 in Fig. 1) before the tail of skirt is called as a forward sustain voltage here. The forward sustain voltage VDRM (SUS) never exceeds the forward blocking voltage or breakover voltage VBO In order to make the GTO thyristor operative in itself, or with substantially no snubber circuit, it is necessary that the forward sustain voltage VDRM(SUS) be about 67% or above of the breakover voltage VBO Therefore, the GTO thyristor needs to have the relation between the breakover voltage VBO and the forward sustain voltage as shown in the shaded area in Fig. 2. When the breakover voltage VBO is, for example, 600 V, the forward sustain voltage VDRM(SUS) must be 400 to 600 V. The greatest problem what the conventional GTO thyristor has is its very low forward sustain voltage as compared with the forward blocking voltage or breakover voltage. For example, when the breakover voltage of a GTO thyristor is 600 V, the forward sustain voltage is only 150 to 200 V. Thus, since the conventional GTO thyristor itself does not satisfy the above condition, for example, a snubber circuit constituted by a diode D5, a resistor R5 and a capacitor C5 is connected in parallel with a GTO thyristor To as shown in Fig. 3 to cause the voltage current locus upon turn-off to follow the curve 3 in Fig. 1. In order to achieve the above objects, the inventors have examined in detail the GTO thyristor exhibiting the curves 1 and 2 in Fig. 1 and as a result found that the forward sustain voltage depends on the thickness of the second base layer constituting the GTO thyristor. In Fig. 4, the curve 100 shows the relation between the WnB and WBO of a normal GTO thyristor with a snubber circuit. The curve 200 shows the relation between the thickness WnB of the second base layer 3 and the breakover voltage VBO with substantially no snubber circuit, as given by WnB = 3.817 x 10 1.VBO - 2.550 x 10 V302 -7 3 -11 4 + 1.133 x 10 V30 - 2.000 x 10 eVBo .. (1) The thickness WnB of the second base layer is the distance from the pn junction formed between the anode emitter layer and the second base layer to the pn junction formed between the second base layer and the first base layer, measured along the direction from the anode electrode toward the cathode electrode. The curve 300 shows the relation between the WnB and WBO with no snubber circuit as given by WnB = 3.200 x 10 1-VBO (2) where WnB is expressed in um and VBO in volt. In other words, the curves 200 and 300 have been obtained by experiments and computation from the relation between the thickness WnB of the second base layer such that the forward substain voltage VDRM(SUS) is brought within the shaded area in Fig. 2 with respect to the breakover voltage VBO. The WnB of the GTO thyristor according to this invention satisfies at least the condition given by WnB # 3.817 x 10-1.VBO - 2.550 x 10-4.VBO2 + 1.133 x 10-7.VBO3 30 - 2.000 x 10-11.VBO4 (3) More preferably, WnB # 3.200 x 10 V30 (4) and no snubber circuit shown in Fig. 3 is necessary in this invention. The snubber circuit considered to be substantially unnecessary has a capacitor of capacitance Cs satisfying the following condition and a resistor of a resistance Rs determined by the capacitance Cs : EMI7.1 where VDRM is the forward sustain voltage and i is the current upon turn-off switching. That is such a snubber circuit has practically negligible capacitance Cs as it is used by the user. With such a particular value of capacitance, the relation between the forward sustain voltage VDRM (SUS) and the breakover voltage VBO is kept within the shaded area in Fig. 2, and the forward sustain voltage increases, so that the GTO thyristor can operate with good switching characteristic under substantially no provision of snubber circuit. An embodiment of this invention will hereinafter be described with reference to Figs. 5 and 6. Fig. 5 shows the cross-section of a unit GTO element constituting an anode emitter shorted GTO thyristor, and Fig. 6 is a plan of the anode electrode side of the GTO thyristor. This kind of GTO thyristor has in a semiconductor substrate 1 of P-type conductivity, an anode emitter (PE) layer 2, a second base (nub) layer 3 of n type conductivity, a first base (pub) layer 4 of P-type conductivity, and a cathode emitter (nE) layer 5 of n-type conductivity. The anode emitter layer 2 is shorted to an anode electrode made in low-resistance contact with the lower side main surface of the substrate 1 through anodeemitter shorting (n+) layers 6 and 60 (which are part of the second base layer 3) of n-type conductivity which has a high-impurity concentration and exposed at the lower side main surface. The first base layer 4 and cathode emitter layer 5 are made in low-resistance contact with the control electrode 8 and cathode electrode 9, respectively. The cathode emitter layer 5 has the so-called planer junction structure in which the pn junction end is exposed at the upper side main surface of the semiconductor substrate 1. The anode emitter layer 2 is at a position to which the exposed pn junction end of the cathode emitter layer 5 is vertically projected toward the anode electrode 7, and the anode emitter shorting layer 6 is at a position to which the center portion of the cathode emitter layer 5 is vertically projected toward the anode electrode 7. The anode emitter layer 2 may be extended over the region to which the whole of the cathode emitter layer 5 is vertically projected toward the anode electrode 7. The actual GTO thyristor has a plurality of unit GTO elements one of which is shown in Fig. 5, provided in the semiconductor substrate 1 with common first base--layers 4 and second base layers 3. In other words, when viewing the whole of the semiconductor substrate 1, the cathode emitter layers 5 appear to be in a plurality of separated strips, each being surrounded by control electrodes 8. The current capacity of the GTO thyristor can be determined by the number of these unit GTO elements. In Fig. 5, the thickness WnB of the second base layer 3 is determined by the special relationship with the brakover voltage VBO of the GTO thyristor as shown by Eqs. (3) and (4). Figs. 7 and 8 show second and third embodiments of the unit GTO thyristor according to this invention, in which like parts corresponding to those of Figs. 5 and 6 are identified by the same reference numerals. Fig. 7 shows the case of not taking the anode emitter layer 2 shorting structure but instead doping gold to short the life time for achieving turn-off performance. Fig. 8 shows the case of also doping gold and taking a structure that when the breakover voltage is 1500 V or above, the voltage drop between the anode electrode 7 and cathode electrode 9 can be prevented from abnormally increasing in the on-state. Hence, an n-type conductivity base region (nub+) 31 is provided between the second base layer 3 and the anode emitter layer 2, and has a higher impurity concentration than that of the second base layer 3. Thus, this invention can be applied to not only the anode emitter shorting structure but also anode emitter non shorting structure and in this case a lifetime killer may be doped. If each unit GTO thyristor is made according to this invention, the GTO thyristor comprising any number of such unit GTO elements can be operated properly. While in the embodiment of Fig. 6 the cathode emitter layers are provided in separated parallel strips on a square-shaped semiconductor substrate 1 to be in parallel with the sides of the substrate, the cathode emitter layers may be of any shape. For example, on a circular semiconductor substrate, there can be radially arranged the strip-shaped cathode emitter layers or in a multiradial way, or there can be concentrically arranged concentric annular-shaped or arc-shaped cathode emitter layers. Moreover, the control electrodes are not necessary to be provided at the same level on the upper main surface at which the cathode emitter layer is exposed. For example, grooves may be provided in the first base layer around each cathode emitter layer, the control electrode being formed in the bottoms of the grooves to be in low-resistance contact therewith and to surround each cathode emitter layer. In this case, the pn junction formed by the cathode emitter layer and the first base layer may take the so-called mesa-type structure in which they are exposed at the groove. The embodiments will be further described in more detail. An n-type silicon wafer having specific resistance of 30 n¯cm is prepared and a GTO thyristor as shown in Figs. 5 and 6 is produced. Although five cathode emitter layers are shown in Fig. 6, this GTO thyristor has actually 8 cathode emitter layers. The thickness of the anode emitter layer 2 is 57 Vm, that of the anode emitter shorting (n+) layer 6, 60 is 75 pm, that of the second base layer 3 is 270 pm, that of the first base layer 4 is 40 pm, and that of the cathode emitter layer 5 is 17 pm. The width and length of the layer 5 are 300 pm and 5.8 mm, respectively. The breakover voltage V30 of this GTO thyristor is 900 V, and the forward sustain voltage VDRM (SUS) is 600 V. This thyristor conducting with a current of 300 A can be turned off with a gate current of 75 A under the substantially snubber-less condition. In this connection, the conventional GTO thyristor of the same structure with a second base layer 3 having a thickness of about 130 pm requires a snubber circuit having a capacitor of 0.22 pF and a resistor of about 220 Q in order that when a current of 200 A is caused to flow in the thyristor, it can be turned off with a gate current of 50 A. According to this invention, the forward sustain voltage is large and the capacitance of snubber circuit to be usually connected in parallel with a GTO thyristor can be made very small, and therefore a circuit with GTO thyristor can be arranged to simple and smallsized.

Claims: WHAT IS CLAIMED IS: 1. A gate turn-off thyristor comprising: (a) a semiconductor substrate (1) in which a cathode emitter layer (5), a first base layer (4), a second base layer (3) and an anode emitter layer (2) are formed in this other, adjacent ones of said layers having different conductivity from each other to form pn junctions therebetween; (b) said cathode emitter layer (5) being divided into cathode emitter layer portions each of which is exposed at one of main surfaces of said semiconductor substrate (1); (c) said anode emitter layer (2) being exposed at the other main surface of said semiconductor substrate (1); (d) each of said separated cathode emitter layer portions (5) being made in low resistive contact with a cathode electrode (9); ; (e) said first base layer (4) being made in low resistive contact with a control electrode (8) formed-to surround each of said separated cathode emitter layer portions (5); (f) said anode emitter layer (2) being made in low resistive contact with an anode electrode (7); and (g) said second base layer (3) having a thickness WnB [ #m ] determined by the following condition: WnB > 3.817 x 10 V30 -2.550 x 10 V302 + 1.133 x 10 7 V303 - 2.000 x 10 11 4 where VBO EV ] is a breakover voltage given when the anode electrode (7) and cathode electrode (9) are supplied with a positive and a negative bias voltage, respectively. 2. A gate turn-off thyristor according to Claim I, wherein said anode emitter layer (2) is shorted by said second base layer (3) and said anode electrode (7). 3. A gate turn-off thyristor according to Claim 1, wherein said second base layer (3) has a base region of the same conductivity and a higher impurity concentration on the anode emitter layer (2) side. 4. A gate turn-off thyristor comprising: (a) a semiconductor substrate (1) in which a cathode emitter layer (5), a first base layer (4), a second base layer (3) and an anode emitter layer (2) are formed in this order, adjacent ones of said layers having different conductivity from each other to form pn junctions therebetween; (b) said cathode emitter layers (5) being divided into cathode emitter layer portions each of which is exposed at one of main surfaces of said semiconductor substrate (1); (c) said anode emitter layer (2) being exposed at the other main surface of said semiconductor substrate (1); (d) each of said separated cathode emitter layer portions (5) being made in low resistive contact with a cathode electrode (9); ; (e) said first base layer (4) being made in low resistive contact with a control electrode (8) formed to surround each of said separated cathode emitter layer portions (5); (f) said anode emitter layer (2) being made in low resistive contact with an anode electrode (7); and (g) said second base layer (3) having a thickness WnB [ #m ] determined by the following condition: WnB 2 3.200 x 10 V30 where VBO [V] is a breakover voltage given when the anode electrode (7) and cathode electrode (9) are supplied with a positive and a negative bias voltage, respectively. 5. A gate turn-off thyristor according to Claim 4, wherein said anode emitter layer (2) is shorted by said second base layer (3) and said anode electrode (7). 6. A gate turn-off thyristor according to Claim 4, wherein said second base layer (3) has a base region of the same conductivity and a higher impurity concentration on the anode emitter layer (2) side.

Inventors: FUKUI, HIROSHI, KIMURA, SHIN, NAGANO, TAKAHIRO, OIKAWA, SABURO, YATSUO, TSUTOMU
Applicants: HITACHI, LTD.
Application year: 1982
Main classification: H01L29
IPC codes: H01L29