SEMICONDUCTOR DEVICE HAVING CONDUCTOR LINES CONNECTING THE ELEMENTS

Abstract: In a semiconductor device of an integrated circuit having a groove isolation structure (10), an electrostatic separating structure (21) similar to the groove isolation structure is formed under the conductor lines (5) connecting the ele­ ments and in a portion of the semiconductor body (7) other than that necessary for the elements. The electrostatic separating structure (21) comprises a V-shaped or U-shaped insulating layer (22), a filled-in nonconductive material (e.g. polycrystalline silicon) (23), and a relatively thick insulating layer (24), so that the stray capacity of the conductor lines (5) can be reduced.

Description: SEMICONDUCTOR D#V1CE¯AND METHOD' F'OR' ITS' #1ANUFACTURE The present invention relates to a semiconductor device and, more particularly, to an integrated circuit (IC) having a groove isolation structure wherein a groove is formed in the semiconductor body and an insulating layer is formed on the surface of the groove. Recently, attempts have been made to increase the number of elements of large-scale integrated circuits (e.g. the number of memory cellS. of a semiconductor memory IC) and, simultaneously, to increase the IC operating speed. An increased number of elements of an IC, however, means an increased number of conductor lines connecting the elements, which results in increased .stray capacity of the conductor lines. Therefore, although the operating speed of active elements can be increased, the increased stray capacity of the condactor lines substantially impedes the increase of the IC oRera-t;Qg speed. In acc.ordance.with one aspect of the present invention; a semiconductor device has elements formed in a semiconductor body and conductor lines connecting the elements and is characterized in that the semiconductor device is provided with an electrostatic separating structure which comprises a filler within a groove formed under the conductor lines and in a portion of the semiconductor body. With this device the stray capacity of conductor lines of the semiconductor device, such as an It; is reduced. Also,the IC operating speed is increased. The groove of the electrostatic separating structure is formed in a portion of the semiconductor body other than that necessary for the elements. In accordance with a second aspect of the present invention, a -method of manufacturing a semiconductor device comprises forming groove isolation structures in a semiconductor body; forming an electrostatic separating structure in the semiconductor body in accordance with a desired conductor line pattern; and forming semiconductor elements in and conductor lines on the semiconductor body. Preferably, the electrostatic separating structure is formed at the same time as the formation of the groove isolation structures. Preferably, the cross-sectional shape of the electrostatic s,eparating structure is the same as or similar to that of the groove isolation structures. Some examples of devices in accordance with the present invention will now be described and contrasted with a prior art device with reference to the accompanying drawings, in which: Figure 1 is a partial circuit diagram of a semiconductor memory IC; Figure 2 is a partially schematic sectional view of a conventional semiconductor device; Figure 3 is a partially schematic sectional view of one example of a semiconductor device according to the present invention; Figure 4 is a partially schematic sectional iriew of a second example of a semiconductor device according to the present invention; and Figure 5 is a partially schematic sectional view of a third example of a semiconductor device according to the present invention. A prior art semiconductor memory IC comprises decoder circuits 1 and driver circuits 2, as illustrated in Figure 1, and conductor lines 3 which meander on the insulating layer formed on the semiconductor body to connect the decoder circuits 1 and the driver circuits 2. The total length of the conductor line 3 is very long, so the stray capacity of the conductor lines may become large. If a part of the semiconductor memory IC (Figure 1.) is made of a bipolar transistor 4 and a conductor line 5, as illustrated in Figure 2, the conductor line 5 is arranged on an insulating layer 6 formed on the semiconductor body 7 comprising a semiconductor substrate (e.g. a silicon wafer) 8 and an epitaxial layer 9. The bipolar transistor 4 is formed in a portion of the epitaxial layer 9 which is surrounded with a groove isolation structure 10. The groove isolation structure 10 comprises an insulating layer 11 on the surface of a groove (in this case, a V#groove) formed in the semiconductor body, a filled-in polycrystalline silicon material 12, and a relatively thick insulating layer 13. Such a groove isolation structure is referred to as a AVID" structure or "lOP" structure. The bipolar transistor 4 comprises a collector contact region 14, a base region 15, an emitter region 16, a collector electrode 17, a base electrode 18, and an emitter electrode 19. A buried layer 20 is formed between the substrate 8 and the epitaxial layer 9. Generally, the insulating layer 6 under the conductor line 5 is made of silicon dioxide and has a thickness of approximately 400 nm. Such conductor lines generate a large stray capacity which prevents an increased IC operating speed. The stray capacity of the conductor lines is very dependent on the thickness of the insulating layer formed between the conductor lines and the semiconductor body. The thicker the insulating layer, the smaller the stray capacity. Accordingly, to reduce the stray capacity of the conductor line 5 in case of Fig. 2, persons skilled in the art may think of making the insulating layer 6 thicker. However, in a case where the thick insulating layer 6 is formed, an aluminum conductor line formed by a vacuum evaporation process may break at a step of an electrode contact hole formed by selectively etching the thick insulating layer. The formation of the thick insulating layer of silicon dioxide involves a heating proess at a high temperature for a relatively long period. At this time, the semiconductor crystal is stressed by heating, so that crystal defects may occur. Furthermore, simultaneously the polycrystalline silicon material 12 filled in the V-groove is further oxidized to make alarger bird#s#beakr, so that such bird's beak hinders the fine pattern formation, i.e. prevents the density of an IC from increasing. Moreover, taking such bird's beak into consideration, the base region 15 must be enlarged, whereby the junction capacity between base and collector is increased. Such increase of the junction capacity is one of causes of delay of the IC operating speed. Figure 3 illustrates a portion of a semiconductor device, i.e., a bipolar transistor 4 and a conductor line 5 of an IC, according to the present invention. The bipolar transistor 4, semiconductor body 7, and groove isolation structure 10 are the same as those illustrated in Fig. 2. The bipolar transistor 4 comprises a collector contact region 14, a base region IS, an emitter region 16, a collector electrode 17j -#t¯ b#se- electrode 18, and an emitter electrode 19. The semiconductor body 7 comprises a semiconductor substrate (e.g., a silicon wafer) 8, an epitaxial layer 9 of single crystalline silicon, and a buried layer 20. The groove isolation structure (in this case "VIP" structure) comprises a V-shaped insulating layer 11, a filled-in polycrystalline silicon material 12, and a relatively thick insulating layer 13 Which surrounds the bipolar transistor 4 and extends into the semiconductor substrate 8 through the epitaxial layer 9 so as to isolate it from other elements (e.g., bipolar transistors) of the IC, as illustrated in Fig. 3. In order to reduce the stray capacity of the conductor line 5, an electrostatic separating structure 21 is formed under the conductor line. The electrostatic separating structure 21 comprises a V -shaped insulating layer 22, a filled-in polycrystalline silicon material 23, and a relatively thick insulating layer 24. The V-groove for the separating structure 21 is formed under the conductor line 5 and in a portion of the semiconductor body 7 other than that necessary for the bipolar transistor 4 and other elements. In this case, the sectional shape of the electrostatic separating structure 21 is the same as that of the groove isolation structure 10. Both structure 10 and 21 are simultaneously formed. After the formation of the epitaxial layer 9 of silicon on the semiconductor substrate 8, the epitaxial layer 9 is thermally oxidized to-form an insulating layer 6 of silicon dioxide. A silicon nitride layer (not shown) is formed on the insulating layer 6 by a chemical yqpWr deposition method. The silicon nitride layer and the insulating layer 6 are selectively removed by a photoetching method to expose portions of the surface of the epitaxial layer 9. Then, the exposed portions of the epitaxial layer 9 are anisotropically etched by a solution of potassium hydroxide and isopropyl alcohol to form V-grooves for the isolation structure 10 and the electrostatic separating structure 21, respectively. The bottoms of the V-grooves penetrate into the semiconductor substrate 8. The V-shaped insulating layers 22 and 11 of silicon dioxide are formed on the surface of the V-grooves by thermally oxidizing the exposed portions of the epitaxial layer 9 and the semiconductor #ubstrate 8 in the V-grooves. A polycrystalline silicon layer is formed on the exposed surfaces of the silicon nitride layer and the insulating layers 22 and 11 so as to fill the V-grooves by a chemical vapor deposition method. The polycrystalline silicon layer is polished to leave portions 23 and 12 of the polycrystalline silicon within the V-grooves. Then, the remaining polycrystalline silicon portions 23 and 12 are thermally oxidized to form the relatively thick insulating layers 24 and 13 of silicon dioxide. This completes the above -mentioned electrostatic separating structure 2 and groove isolation structure 10. Next, the silicon nitride layer is removed. The base region 15, the collector contact region 14, and the emitter region 16 of the bipolar transistor 4 are formed in accordance with a conventional process. A conductor layer of, e.g., aluminum is formed on the exposed surface and then is selectively removed by a photoetching method to form the collector electrode 17, the base electrode 18, the emitter electrode 19, and-the conductor line 5 arranged on the electrostatic separating structure 21. Since the relatively thick insulating layer 24 has a thickness of, e.g., approxi mately 1 iim (micrometer) and the V-shaped insulating layer 22 has a thickness of, e.g., approximately 500 nm, the stray capacity of the conductor line 5 of Fig. 3 is much smaller than that of the conductor line 5 of Fig. 2. It is possible to form the electrostatic separating structure according to tne present invention under all conductor lines and in a portion of the semiconductor body other than that necessary for elements. This allows the stray capacity of the conductor lines of the IC to be substantially reduced. Therefore, the IC operating speed can be increased over that of the case of a conventional IC. A-portion of-a semiconductor device (e.g., a bipolar transistor#IC) according to another embodiment of the present invention is illustrated in Fig. 4. In this case, a bipolar transistor 4 and an additional bipolar #transistor 25 are formed in a portion of an epitaxial layer 9 isolated by a groove isolation structure 10. The bipolar transistor 4, groove isolation structure 10, and semiconductor body 7 comprising the epitaxial layer 9 are the same as those illustrated in Figs. 2 and 3. The additional bipolar transistor 25 comprises a base region 26, an emitter region 27, a base electrode 28, an emitter electrode 29, the collector contact region 14, and the collector electrode 17. Namely, the additional transistor 25 utilizes the collector of the bipolar transistor 4. A conductor line 30, one of many conductor lines of the IC and traversing the isolated portion, is formed as illustrated in Fig. 4. An electrostatic separating- struct-ure 31 is formed under the conductor line 30 and between the bipolar transistor 4 and the additional bipolar transistor 25. The electrostatic separating structure 31 comprises a V-shaped insulating layer 32 which does not penetrate into the semiconductor substrate 8, a filled-in polycrystalline silicon material 33, and a relatively thick insulating layer 34. It is possible to easily form such an electrostatic separating structure 31 at the same time as the formation of the groove isolation structure 10. When a V-groove for the electrostatic separating structure 31 is formed, it is suitable to determine the depth of the V-groove by controlling the width of the exposed surface area of the epitaxial layer 9 to be etched. Since the above-mentioned electrostatic separating structure 31 exists under the con ductor line 30, the stray capacity of the conductor line 30 can be substantially reduced as compared with the case where there is no electrostatic separating structure 31. It is possible to form the electrostatic separating structure according to the present invention in a ULgroove type shape, as in Fig. 5, instead of the above-mentioned V-groove type shape, as in#Figs. 3 and 4. In this case, the electrostatic separating structure 35 under the conductor line 5 comprises a U-shaped insulating layer 36 extending into the semiconductor substrate 8 through the epitaxial layer 9, a filled-in polycrystalline silicon material 37, and a relatively thick insulating layer 38. A groove isolation structure 39 for-the bipolar transistor 4, the same as that in Figs. 2, 3, and 4, comprises a U-shaped insulating layer 40, a filled-in polycrystalline silicon material 41, and a relatively thick insulating layer 42. Namely, the isolation structure 39 has the same shape as that of the separating structure 35. Both structures 35 and 39 can be -simultaneously formed in accordance with the above-mentioned method, except that dry-etching for the U-groove is used instead of the anisotropical wet-etching for the V-groove. For example, an ion beam of argon or carbon fluoride is accelerated with a voltage of from 100 V to 10 kV and vertically bombards the exposed surface of the epitaxial layer 9 not masked by the insulating layer 6 and the silicon nitride layer (not shown), so that the exposed portion of the epitaxial layer 9 and the semiconductor substrate 8 is vertically etched to form the U-groove. The stray capacity of the conductor line 5 can be substantially reduced by the formation of the U-groove electrostatic separating struc ture 35. It will be obvious that the present invention is not restricted to the above-mentioned embodiments, and that many variations are possible for a person skilled in the art without departing from the scope of the present invention. For example, it is possible to use a nonconductive material (preferably, an insulating material) such as silicon dioxide and polyimide, instead of the polycrystalline silicon material filled in the groove. In the case where the groove is filled with silicon dioxide or polyimide, a conductor line can be formed directly on the filled-in material. It is also possible to form a metal-oxide-semiconductor field effect transistor instead of the bipolar transistor.

Claims: CLAMS 1. A semiconductor device having elements (4) formed in a semiconductor body (7) and conductor lines (5, 30) connecting the elements, characterized in that the semiconductor device is provided with an electrostatic separating structure (21,31, 35) which comprises a filler (22, 23; 32, 33; 36, 37) within a groove formed under the conductor lines (5, 30) and in a portion of the semiconducts; body (7). 2. A semiconductor device having a plurality of elements (4) formed in a semiconductor body (7) interconnected by conductor lines (5, 30), each element (4) or group of elements being surrounded by a groove isolation structure (10), characterized in that an electrostatic separating structure (21, 31, 35) is provided, the structure comprising an insulating filler within a groove formed along and under each conductor (5, 30) and in the semiconductor body (7). 3. A semiconductor device according to claim 1 or claim 2, characterized in that the semiconductor body t7) comprises a semiconductor substrate t8) and an epitaxial layer t9) grown on the substrate C8),and in that the grooves extend into the epitaxial layer (9). 4. A semiconductor device according to claim 2, characterized in that the grooves extend into the semiconductor substrate (8) through the epitaxial layer (9). 5. A semiconductor device accord to any of the preceding claims, characterized in that the groove is a V-groove or a U-groove. 6. A semiconductor device according to any of the preceding claims, characterized in that the filler comprises an insulating layer (22, 32, 36) formed on the surface of the groove, and a nonconductive material filling the groove. 7. A semiconductor device according to claim 6, characterized in that the insulating layer (22, 32, 36) is silicon dioxide and in that the nonconductive material comprises a polycrystalline silicon portion (23, 33,. 37) and a silicon dioxide layer (24, 34, 38) formed on the polycrystalline silicon portion. 8. A method of manufacturing a semiconductor device, the method comprising forming groove isolation structures (10) in a semiconductor body (7); forming an electrostatic separating structure (21, 31, 35) in the semiconductor body t7) in accordance with a desired conductor line pattern; and forming semiconductor elements (4) in and conductor lines (5, 30) on the semiconductor body (7). 9. A method according to claim 8, wherein the groove isolation structures (10) and the electrostatic separating structure (21, 31, 35) are formed at the same time. 10. A method according to claim 8 or claim 9, wherein grooves of the groove isolation structures (10) and the electrostatic separating structure (21, 31, 35) are formed by etching the semiconductor body (7).

Inventors: KIMOTO, MASAYOSHI, MAFUNE, YASUHIKO, SUGO, YASUHISA
Applicants: FUJITSU LIMITED
Application year: 1982
Main classification: H01L21
IPC codes: H01L23, H01L21