INTEGRATED LOGIC CIRCUIT HAVING AN INTERFACE TRANSISTOR

Abstract: In an integrated logic circuit having an inverter transis­ tor with a signal input connected to its control electrode and one or more signal outputs each coupled via a diode to one of its main electrodes an interface or translation transistor is added. Preferably an ISL clamped NPN transistor and a PNP interface transistor are merged together in a single semiconductive isolated island. The two transistors are laterally separated from each other along a semiconductive surface of the island, which also includes one or more metallic elements forming individual Schottky barrier con­ tact diodes with the semiconductive surface. The PNP tran­ sistor provides translation between an ISL logic gate and a TTL logic gate. One of the Schottky diodes may be used in combination with the NPN transistor as an active pull down for an output transistor of the TTL logic gate.

Description: "Integrated logic circuit having an interface transistor". The invention relates to an integrated logic circuit having a signal input formed by a control electrode of a transistor and having one or more outputs each coupled via a diode to a first main electrode of the transistor, the signal input ccoprising#py means, the integrated circuit comprising a semiconductor body having a major surface and plural surface regions of a first conductivity type adjoining said major surface, said plural surface regions being situated on a common substrate region of a second conductivity type opposite to the first conductivity type, each of said surface regions being surrounded at the major surface by an isolation zone by means of which the surface regions are isolated electrically from each other at least during operation, a first of said surface regions of the first conductivity type serving as the first main electrode of the transistor, said control electrode of the transistor being a surface zone of the second conductivity type situated in said first surface region and a second main electrode of the trans is tor adjoining the major surface and being separated from the control electrode by a rectifying junction, the first surface region at the major surface adjoining one or more conductive tracks each forming with the first main electrode a rectifying junction which serves as the said diode, and in which in the first surface region and spaced from the said surface zone of the second conductivity type a further surface zone of the second conductivity type is present. Such integrated logic circuit is known from German Patent Appli- cation P 30 13471.5. Particularly the example described with reference to figures 7 and 8 of this German Patent application shows a static induction transistor which is merged with an ##S current source transistor. The control electrode of the static induction transistor simultaneously forms the drain region of the current source transistor. Spaced therefrom is the further surface zone which forms the source region of the current source transistor. The source and drain regions define a channel region therebetween which channel region extends below an insulated gate electrode which is provided at the major surface of the semiconductor body. Other examples of integrated logic circuits having current source means connected to the control electrode of an inverter trans is tor, which control electrode forms the signal input and the signal outputs each being coupled via a diode to the first main electrode of the inverter transistors are Schottky Transistor Logic (STL) and Integrated Schottky Logic (ISL). Schottky Transistor Logic is described in, for example, IEEE ISSCC, febr. 1975, Digest of Technical Papers, pp.173-173. Integrated Schottky Logic (ISL) is a relatively new form of logic useful in large scale integrated circuits. ¯ ISL was first described in IEEE Journal of Solid State Circuits, Volume SC-14, No.3, June 1979 in a paper authored by Jan Lohstroh, entitled, "ISL, a Fast and Dense Lower Power Logic, Made in a Standard Schottky Process". ISL provides a good compromise between low power Schottky TTL (LSTm) and integrated injection logic (1%). It satisfies a demand for a circuit that consumes less power and takes up less chip area than LSITL and reguires a faster speed than I2L. An ISL gate in its simplest form comprises a current source, a normally operated collector down NPN transistor with a merged PNP clamp, and one or more output Schottky diodes. The PNP clamp, which may consist of the combination of a lateral PNP and a vertical PNP transistor sharing the collector and base regions of the NPN transistor, operates to prevent the NPN transistor from going too deeply into saturation, thereby reducing the saturation delay. The integrated logic circuits of the kind described have a relatively small logic voltage swing and a correspondingly low signal voltage level. Furthermore these logic circuits usually are operated at low current levels. In connection herewith it often is desirable to translate these signal levels to particularly, the more commonly used Tm signal levels. The present invention has for one of its objects to provide a compact integrated circuit arranged within a single island region, that will translate from the relatively low signal level to a substantially larger signal level without too much loading of the inverter transistor. Although the IEEE article referred to above states that it is possible to combine ISL with other forms of logic, such as ECL, 1%, and Tm on the same chip, it does not describe any way of translating between ISL and Tm. The obvious way to translate between an ISL gate and a Tm gate is to simply add two additional ISL gates between the input ISL gate and the TTL gate. However, the two additional ISL gates, each in its own isolated island, occupies too much space and undesirably introduces additional time delay. Interface circuits are well known for other forms of logic. In 2 Japanese Kokai No. 53-57723, an I L to Tm interface circuit uses a PNP transistor coupled to the output of the collector up NPN I L transistor. European Patent application 0009083 discloses a CML to Tm interface circuit, and German Patent application 3.024#273 discloses an ECL to Tm interface circuit. According to the invention an integrated logic circuit of the kind described in the preamble is characterized in that said further surface zone serves as an extra signal output of the logic circuit and forms the emitter of a further transistor, the base and collector of said further transistor being formed by the first surface region and the com- mon substrate region, respectively. This integrated logic circuit has a compact structure with an extra output transistor integrated in a single comnon island region and providing an emitter follower output which effectively translate to larger signal levels and simultaneously permits the logic gate to perform normal logic operation such that other outputs of usual structure can be connected to adjacent logic gate circuits of an integrated logic network. In a preferred form of the integrated logic circuit according to the invention, the transistor is an ISL clamped NPN transistor and the further transistor is a PNP translation transistor. Preferably the PNP translation transistor is coupled to a Tm inverter circuit which is present in one or more separate isolated islands of the integrated circuit. One of the conventional outputs of the logic gate circuits may be used to provide an active puildown function for one of the output transistors of the Tm inverter circuit. The advantages of this active pulldown function are a reduction in the number of camponents, increased speed, and higher output breakdown voltage. These advantages will be discussed more fully in the specific description of the preferred embodiments. BRIEF DESCRIPTION OF THE DRMINGS Figure 1 is a diagrammatic plan view of a part of an integrated circuit layout shaving the ISL to Tm translator according to the invention. Figure 2 is a sectional view taken along line 2 - 2 of Figure 1. Figure 3 is an equivalent circuit representation of the ISL to Tm translator of Figures 1 and 2. Figure 4 is a logic diagram showing translation between ISL and Tm circuitry without using the present invention. Figure 5 is a logic diagram showing translation between ISL and Tm circuitry according to the invention. Figure 6 is a schematic circuit representation of the logic diagram of Figure 6. Figure 7 is a schematic circuit showing a modification of Figure 6 in which an ISL Schottky diode is used as an active pulldown for one of the output Tm transistors. DESCRIPTION OF THE PREFERRED E#BC#IMEN#S Reference is now made to Figures 1 and 2 which show a greatly enlarged portion of an integrated circuit incorporating the translator according to the invention. This example is an ISL to Tm translator. vreviQDv A p-type substrate 1, such as silicon, is provided with an n-type epitaxial layer 12. A peripheral isolation means 14 laterally surrounds a separate portion of the epitaxial layer 12 and extends in depth to the substrat;recrion/ substrai##Hi0ithin the confines of the isolation means 14 there is formed a single isolated island or tub 15 that contains the ISL to Tm translation circuit. The isolation means 14 may be produced by forming a p-type diffusion within the epitaxial layer 12, thereby surrounding the isolated island 15 with a pn semiconductive junction. Alternatively, the isolation means 14 may be constituted wholly or partly by a dielectric material such as silicon dioxide that is formed by local oxidation of the n-type silicon epitaxial layer 12, which is the process known by the acronym WOOS. Other dielectric material such as silicon nitride, may also be used for the isolation means14. A heavily doped n-type buried layer 16 is provided at the interface of the substrate region 10 and epitaxial layer 12 where the pn junction is formed. The buried layer 16 stops considerably short of the isolation means 14 on all four sides thereof, and extends in depth partly into the epitaxial layer 12 and partly into the substrate region 10. The buried layer 16 may be produced by conventional processing means, as by implanting an n-type dopant into the substrate region 10 prior to epitaxial deposition of the layer 14, after which, during formation of the epitaxial layer 14, the n-type dopant will diffuse vertically upward into the epitaxial layer 12 and vertically downward into the substrate region 10. An NPN ISL transistor Q1 is provided at one extreme end of the isolated island 15 and a PNP translation transistor Q2 is provided at the other end of the isolated island 15. The ISL transistor Q1 is formed by a p-type base region 18 formed in the epitaxial layer 12, which functions as the collector, and a heavily doped n-type emitter region 20 formed in the base region 18. In a structure wherein the isolation region 14 is produced by a p-type region to form PN junction isolation, preferably a p-type region 22 surrounds the base region 18 on three sides thereof in the form of a U-shaped collar. The p-type peripheral or collar region 22 is spaced close to the base region 18 and merges with the isolation region 14. The emitter region 20 is offset from the center of the base region 18 in a direction away from the p-type collar region 22. Metallic ohmic contacts 24, 25, and 26 extending through openings in a silicon dioxide layer 27 are provided on the surfaces of the emitter region 20, collar region 22, and base region 18, respectively. The buried layer 16 lies under the emitter region 20 but does not underlie the portion of the base region 18 that is free of the emitter region 20. The end of the buried layer 16 lies approximately beneath the center of the base region 18, so that the part of the epitaxial collector region 12 and the part of the substrate region 10 underlying the p-type collar region 22 and also underlying approximately one half of the base region 18 are free of the buried layer 16. While the NPN transistor Q1 has emitter, base, and collector regions 20, 18, and 12 respectively, it is shunted by a two part PNP clamping transistor having a vertical part and a lateral part. The vertical part of the PNP clamping transistor has region 18 as the emitter, epitaxial region 12 as the base, and the substrate region 10 as the collector. The lateral part of the PNP clamping transistor has the region 18 as the emitter, epitaxial region 12 as the base, and the p-type collar region 22 as the collector. The p-type collar region 22 enchances the effect of the parasitic lateral PNP transistor already present in a junction isolated structure by decreasing the base width, thereby increasing the beta with attendant increase in switching speed of the ISL trans is tor Q1. The two part PNP clamping transistor limits the extent to which the NPN transistor Q1 goes into deep saturation and thereby reduces the saturation delay. A more detailed discussion of this effect and the advantages of the ISL logic form is found in the Lohstroh paper referred to above. In a structure wherein the isolation region 14 comprises a dielectric material, the p-type collar region 22 is omitted. In that case, the PNP clamping transistor comprises only the vertical part, and there is no lateral part present. Alternatively, with dielectric isolation, clamping action for the NPN transistor Q1 may be provided by a merged inversely operated NPN clamping transistor. Such a structure is described in the Lohstroh article referred to above. Accordingly, the term "ISL clamped NPN transistor" is intended to be generic to all of the aforementioned ways of clamping the NPN transistor Q1, whether they incorporate dielec isolation,: tric isolation or junctior.,M7hether they employ a single clamp or dual clamp of the PNP type or NPN type. The remainder of the ISL structure comprises one or more Schottky junction diodes D1 and D2 formed in the collector region of the ISL transistor Q1, which in this case, is the epitaxial layer 12. The Schottky diodes D1 and D2 lie centrally within the isolated island 15 directly above the buried layer 16. The Schottky diodes are constituted by two metallic contacts 28 and 30 provided on the surface of the epitaxial layer 12 and are each made of such metal as to form a Schottky barrier junction with the n-type epitaxial material. A suitable metal for the Schottky contacts is a platinunmickel alloy containing 60% platinum and 40% nickel, with a Schottky barrier height of about 0.78eV. At the opposite end of the isolated island 15 from the ISL transistor Q1 there is located the PNP translation transistor Q2. The emitter of the PNP transistor Q2 is constituted by a p-type region 32 formed in the epitaxial layer 12 over a region of the epitaxial layer-to-substrate junction that is free of the buried layer 16. The base of the PNP transistor Q2 is constituted by the epitaxial layer 12. To provide a base contact region for the PNP transistor Q2 and a collector contact region for the NPN transistor Q1,a heavily doped n-type region 34 is formed in the epitaxial layer 12 directly over the buried layer 16. A heavily doped n-type plug 35 connects the contact region 34 with the buried layer 16 through a low resistance path. The collector of the PNP transistor Q2 is formed by the substrate region 12. Thus, the PNP transistor Q2 is vertically arranged within the isolated island 15. An ohmic metallic contact 36 is provided on the surface of the base contact region 34, and another ohmic metallic contact 38 is provided on the surface of the emitter region 32. The substrate region 10 has a connection at 40 for connecting a reference voltage such as ground. In a structure having junction isolation, the p-type emitter region 32 may be surrounded on three sides thereof by a p-type peripheral or collar region 41 to enhance the lateral PNP transistor action that appears in shunt with the PNP translation transistor Q2. The lateral transistor has the p-type region 32 as emitter, the epitaxial layer 12 as base, and the isolation region 14 as collector. ¯ The'The p-type collar re- gion 41 will narrow the base width of the lateral transistor, thereby increasing the beta with attendant increase in switching speed of the translation transistor Q2. The impurity doping concentration for an exemplary structure are such as to provide the following resistivities: two ohzcentimeters for the substrate region 10, 0.3 ohm-centimeter for the epitaxial layer 12, 200 ohms per square for the base diffusion (regions 18, 32, 22, 41), and two ohms per square for the emitter and N+ diffusion (regions 20, 34, 35). An equivalent circuit diagram of the ISL to Tm translator structure is shown in Figure 3. In Figure 3, the ISL transistor Q1 is shown to consist of an NPN transistor having a PNP clamping transistor QC sharing cornmon electrodes therewith, the PNP clamping transistor QC having both the lateral and the vertical components, or only a single component, as discussed above. An input terminal B is shown connected to the base of transistor Q1. Also shown connected to the base of transistor Q1 is a current source 42, which may be either a PNP transistor or a resistor coupled to a positive voltage supply. The current source 42 can be located in a separate isolated island. A terminal F is shown at the collector of transistor Q1. The collector is coupled through the two Schottky diodes D1 and D2 to output terminals D and E respectively, and is coupled directly to the input base of the PNP translation transistor Q2. The emitter of the PNP transistor Q2 has an output at a terminal C. A logic diagram of a circuit incorporating ISL input and to output is shown in Figure 4. An input at terminal B is fed to a conventional ISL gate Y having three outputs at terminals C, D, and E. A signal at output terminal D is fed to an ISL gate X3 and a signal at output terminal E is fed to an ISL gate X4. At output terminal C it is desired to translate to a Tm output terminal G. Accordingly, it is necessary to provide two more ISL gates X1 and X2 before the signal can be applied to a TTL inverter A and obtain an output at terminal G. If gate Y is to perform a logic function at the same time that the output buffer A is being driven, then gates X1 and X2 are necessary as buffers to avoid overloading gate Y. The two ISL gates X1 and X2 shown in Figure 4 can be eliminated by incorporating within the ISL gate Y the PNP translation transistor Q2 of Figures 1 through 3. The translation transistor Q2 provides the same buffering effect as the two gates X1 and X2. This improved circuit is illustrated in Figure 5 where the ISL gate Y of Figure 3 is replaced by ISL gate Z which incorporates the PNP translation transistor Q2. The ISL gate output at terminal C is applied directly to the Tm gate A without any intervening gates. Referring now to Figure 6, there is shown a detailed schematic diagram of the improved logic shown in Figure 5. An input signal at terminal B is coupled to the base input of the ISL gate comprising trans is tor Q1 shunted by the PNP clamping transistor QC. A current source includes a resistor 44 connected between the base of the transistor Q1 and a source of positive DC potential VBB, such as 1.50 volts, and preferably a resistor 46 connected between the collector of transistor Q1 and the VBB supply. The emitter of transistor Q1 and the collector of the clamping transistor QC are returned to canaron reference potential, or ground. A Schottky output diode D1 has its cathode connected to the collector of the transistor Q1 and its anode coupled to the input of another ISL gate similar to the first one and comprising NPN transistor Q11 and PNP clamping transistor QC1. Similarly, the second output diode D2 is coupled to a third ISL gate comprising NPN transistor Q12 and PNP clamping trans is tor QC2. The collector of the NPN transistor Q1 is coupled to the base of the PNP translation transistor Q2. The emitter of transistor Q2 is connected through a resistor 48 to a positive supply Vcc, such as 5 volts, and is also connected to the base of a Schottky clamped NPN input transistor Q3. The collector is returned to ground. The collector of the transistor Q3 is coupled through a resistor 50 to positive supply VCC and to the base of a Schottky clamped transistor Q5. The emitter of transistor Q3 is connected to the anode of a Schottky diode D3 and to the base of a Schottky clamped NPN output transistor Q4. A resistor 52 is connected between the cathode of the diode D3 and ground. The emitter of transistor Q5 is connected through a resistor 54 to ground and is also connected to the base of an NPN transistor Q6. The collectors of transistors Q5 and Q6 are connected to positive supply Vcc. The emitter of transistor Q6 and the collector of transistor Q4 are connected together to an output terminal G. The emitter of output trans is tor Q4 is connected to ground. In the operation of the circuit of Figure 6, a HIGH logic input signal at terminal B will produce a Low logic signal on the collector of transistor Q1. The Low signal on the cathodes of diodes D1 and D2 cause the latter to conduct a LOW signal to the two ISL gates comprising transistors Qi 1 and Q12 respectively. The same LOW logic signal on the collector of transistor Q1 is coupled to translation transistor Q2, which is an emitter follower and conducts the LOW logic signal to its emitter at terminal C. The Tm circuit comprising transistors Q3, Q4, Q5, and Q6 functions as an inverter so that when a Low signal is applied to the base of input transistor Q3, transistor Q3 turns OFF, transistor Q4 turns OFF, transistor Q5 turns ON, transistor Q6 turns ON, and the signal at output terminal G is HIGH. Conversely, when a LOW logic signal is applied to the input terminal B of the ISL gate, transistor Q1 turns OFF, placing a HIGH signal on the base of transistor Q2. Transistor Q2 goes OFF and terminal C goes HIGH. A HIGH signal on the base of Tm input transistor Q3 causes the latter to turn on, causing transistor Q4 to turn ON and transistor Q5 to turn OFF, and transistor Q6 to turn off, causing the signal on output terminal G to go LOW. The HIGH signal at terminal C is clamped to the sum of the emitter-base voltages of the conductive transistors Q3 and Q4, which is low enough to keep transistor Q2 in the OFF-condition. The series connection of the emitter-base diodes of the input transistor Q3 and the output transistor Q4 is connected in parallel to the emittercollector current path of the further transistor Q2. With a HIGH signal on the base of transistor Q2 the voltage at terminal C should not be allowed to raise till about one VBE above VBB in order that transistor Q2 will be OFF. The advantages of employing a single translation transistor Q2 between the first ISL gate and the Tm circuit is readily apparent. The PNP transistor Q2 may be incorporated in the same isolated island with the ISL transistor Q1, thereby conserving space. Furthermore, the PNP translation transistor Q2 replaces two additional ISL gates thereby further reducing space and also shortening the time delay. A further improvement may be effected by utilizing one of the Schottky diodes of the ISL circuit to perform a pulldown function for the output transistor Q4 of the Tm circuit. This improvement is illustrated in Figure 7, wherein the Schottky diode D3 and resistor 52 are eliminated from the base circuit of output transistor Q4. Instead, one of the Schottky diodes, such as D1, present in the collector region of the ISL transistor Q1, has its anode connected directly to the base of output transistor Q4 in common with the emitter of transistor Q3. As a result, when a HIGH logic signal is applied to input terminal B turning transistor Q1 ON, diode D1 is also turned ON, placing the base of output transistor Q4 at a voltage above ground equal only to the internal voltage drop of transistor Q1 plus the forward voltage drop of diode D1, both of which are very small. The low voltage applied to the base of transistor Q4 holds it OFF. In this active pull down the low internal voltage drop of an ISL clamped transistor as compared to a Schottky clamped transistor is a major advantage. The active pull down formed by transistor Q1 and diode D1 holds the base of the output transistor Q4 OFF through the low forward resistance of Schottky diode Dl. A true collector-base breakdown is seen at point G, instead of a collector emitter breakdown when a transistor or resistor is used as a pull down. Another advantage is that when transistor Q4 is turned ON diode D1 is reversed biased and the entire emitter current of transistor Q3 goes to transistor Q4 instead of splitting between transistor Q4 and diode D3, as it would in the circuit of Figure 6. The active pull down afforded by diode D1 and transistor Q1 provides yet another advantage in assuring that transistor Q4 turns off before transistor Q5 and Q6 turn on, thereby eliminating current spikes that would occur if transistors Q5 and Q6 and Q4 were on at the same time. In the examples described the conductivity types may be interchanged. Such modified examples may be operated with similar voltages but of opposite polarity. Although silicon is preferred, semiconductor materials other than silicon may be used also, for instance AIII-BV compounds. In the Schottky diodes other materials like PtSi or Al may be used. Moreover, other conventional isolation technologies may be used such as air-isolation, V-grooves or grooves filled with insulating and/or semiconductive material.

Claims: 1. An integrated logic circuit having a signal input formed by a control electrode of a transistor and having one or more outputs each coupled via a diode to a first main electrode of the transistor, the signal input comprising current supply means, the integrated circuit comprising a semiconductor body having a major surface and plural surface regions of a first conductivity type adjoining said major surface, said plural surface regions being situated on a common substrate region of a second conductivity type opposite to the first conductivity type, each of the said surface regions being surrounded at the major surface by an isolation zone by means of which the surface regions. are isolated electrically from each other at least during operation, a first of said surface regions of the first conductivity type serving as the first main electrode of the transistor, said control electrode of the transistor being a surface zone of the second conductivity type situated in said first surface region and a second main electrode of the transistor adjoining the major surface and being separated from the control electrode by a rectifying junction, the first surface region at the major surface adjoining one or more conductor tracks each forming with the first main electrode a rectifying junction which serves as the said diode and in whichRhe first surface region and spaced from the said surface zone of the second conductivity type, a further surface zone of the second conductivity type is present, characterized in that said further surface zone serves as an extra output of the logic circuit and forms the emitter of a further transistor, the base and the collector of said further transistor being formed by the first surface region and the ccomon substrate region, respectively. 2. An integrated logic circuit as claimed in Claim 1, characterized in that said diode comprises a Schottky barrier junction. 3. An integrated logic circuit as claimed in Claim 1 or Claim 2, characterized in that the output of said further transistor is coupled to the base of an input transistor of an inverter circuit which further com- prises an output transistor across which an output signal of the inverter circuit may be taken. 4. An integrated logic circuit as claimed in Claims 2 and 3, charac terized in that one of said one or more outputs is coupled to the base of said output transistor of the inverter circuit 5. An integrated logic circuit as claimed in Claim 3, characterized in that the input and the output transistor of the inverter circuit have a Schottky barrier junction between their base and collector connections. 6. An integrated logic circuit as claimed in Claim 3, 4 or 5, characterized in that the inverter circuit is operated at Tm supply and signal levels. 7. An integrated circuit as claimed in any of the preceding Claims, characterized in that at least one of said one or more outputs is coupled to the base input of the transistor of a similar logic circuit. 8. An integrated logic circuit as claimed in any of Claims 1 to 7, characterized in that said transistor of said integrated logic circuit is clamped by at least a vertical complementary transistor part sharing cc? mon regions with said transistor. 9. An integrated logic circuit as claimed in Claim 8, characterized in that said transistor is clamped by a lateral complementary transistor part and a vertical complementary transistor part, both of saB parts sharing common regions with said transistor. 10. An integrated logic circuit as claimed in one or more of the preceding claims, characterized in that said first of said surface regions of the first conductivity type is separate portion of an epitaxial layer of the first conductivity and comprises a more highly doped region of the first conductivity type situated between said control electrode surface zone of the second conductivity type and said further surface zone of the second conductivity type, a buried layer of the first conductivity type being present at and in the vicinity of the interface between said epitaxial layer portion and said common substrate region, said buried layer extending at one end beneath the lateral extent of said second main electrode of said transistor but stopping short of one lateral extremity of said control electrode surface zone and extending beneath said more highly doped region but stopping short of said further surface zone of the second conductivity type. 11. An integrated logic circuit as claimed in Claim 10, characterized in that said separate epitaxial layer portion is laterally surrounded by an isolation wall extending from said major surface to said common substrate region. 12. An integrated logic circuit as claimed in Claim 11, characte rized in that said isolation wall is made of semiconductive material of the second conductivity type. 13. An integrated logic circuit as claimed in Claim 11, characterized in that said isolation wall comprises dielectric material. 14. An integrated logic circuit as claimed in Claim 12, characterized in that a peripheral region of the second conductivity type is present which surrounds said control electrode surface zone on at least three sides thereof remote from said more highly doped region of the first conductivity type, said peripheral region being contiguous with a surface portion of said isolation wall. 15. An integrated logic circuit as claimed in Claim 12 or Claim 14, characterized in that said further surface zone is surrounded on at least three sides thereof remote from said more highly doped region of the first conductivity type by a peripheral region of the second conductivity type which is contiguous with a surface portion of said isolation wall. 16. An integrated logic circuit as claimed in one or more of the preceding claims, characterized in that said first main electrode of the transistor is connected to a first supply connection through a resistor and that the emitter of said further transistor is coupled to a second supply connection, clamping means being present for limiting the operating voltages at the emitter of the further transistor to be smaller than the sum of a forward pn-junction voltage and the supply voltage to be applied to said first supply connection. 17. An integrated logic circuit as claimed in Claims 3 and 16, characterized in that the series connection of the emitter-base diodes of the input and the output transistor of the inverter circuit is connected in parallel to the emitter-collector current path of the further transistor. 18. An integrated logic circuit as claimed in Claim 16 or Claim 17, characterized in that the first supply connection is to be connected to a supply source providing a supply voltage of about 1,5 Volt and that the second supply connection is to be connected to a supply source providing a supply voltage of about 5 Volts.

Inventors: BELLAVANCE, JOSEPH THOMAS
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1982
Main classification: H01L27
IPC codes: H03K19, H01L21, H01L27