PROTECTION AGAINST ERRONEOUS SIGNAL GENERATION IN SEMICONDUCTOR DEVICES

Abstract: A semiconductor device comprises first and second groups of signal lines arranged at different positions adja­ cent to a surface of a semiconductor substrate (4) and an electrostatic shield layer (6) for the semiconductor substrate, the shield layer being formed under at least one (3,3′) of said groups of the signal lines, whereby the semiconductor substrate can effectively be shielded from the signal lines.

Description: PROTECTION AGAINST ERRONEOUS SIGNAL GENERATION IN SEMICONDUCTOR DEVICES The present invention relates to protection against erroneous signal generation in semiconductor devices. An erroneous signal may be produced, for example, in a semiconductor memory device, as a result of a potential change on input signal lines being transferred to bit lines of the device. In, for example, a dynamic semiconductor memory dev ice comprising a 64K bits random access memory (RAM), each sense amplifier should nowadays be able to detect the small potential difference of about 100 mV generated between pairs of bit lines. This has been necessitated by the decrease in individual cell capacities accompanying higher degrees of integration. Such a high-sensitivity sense amplifier, however, may be rather susceptible to error operations due to noise. This is especially possible when the potentials of the input signals, for example address signals, are changed at the same time as sense amplifiers operate, or just before the operation of the sense amplifiers. This change can influence the potentials of the bit lines through parasitic electrostatic capacitances, as hereinafter described in more detail, causing error operations of the sense amplifiers. It is desirable to provide protection against such potential fluctuation at signal lines of a semiconductor device, and in particular at bit lines of a semiconductor memory device, due to parasitic capacitances, and so to protect against error operations of a sense amplifier in such a dynamic semiconductor memory device. An embodiment of the present invention can be constructed in the form of a semiconductor device comprising a semiconductor substrate, a first group of signal lines, and a second group of signal lines. The first group and second group are arranged on different positions on the semiconductor substrate. The device further comprises an electrostatic shield layer for the semiconductor substrate, formed under at least one of the first and second groups of signal lines. Reference will now be made, by way of example, to the accompanying drawings,-wherein: Figure 1 is a schematic plan view of a conventional dynamic semiconductor memory device; Figure 2 is a cross-sectional view, to an enlarged scale, taken along line II-II' of Figure 1; Figure 3 is a cross-sectional view illustrating part of a dynamic semiconductor memory device according to a first embodiment of the present invention; and Figure 4 is a cross-sectional view illustrating a part of a dynamic semiconductor memory device according to a second embodiment of the present invention. Figure 1 shows a general structure of a conventional dynamic semiconductor memory device, A dynamic semiconductor memory chip CH includes in its central portion a plurality of sense amplifiers SA1, SA2, ..., Say, ..., and SA, To the right and left of each sense amplifier extend a pair of bit lines BL and BL respectively. For the purpose of simplicity, only one pair of bit lines is illustrated. The bit lines BL and BL are connected to memory cells (not shown) arranged in memory cell arrays 1 and 1'. Reference numerals 2 and 2' represent peripheral circuits of, for example, decoders or buffer amplifiers. Reference numerals 3 and 3' are input signal lines connected to input terminals Aov A1, A2, A3, A4 and A5. The input terminals Ao through A5 receive input signals of, for example, address input signals or data. All of the above elements and lines are formed on a semiconductor substrate 4. The bit lines BL and BL are diffusion layers formed at the surface of the semiconductor substrate 4 or wiring layers of, for example, polysilicon formed on the semiconductor substrate through an insulating layer (not shown). Therefore, in both cases, an electrostatic capacitance is formed between each bit line BL or BL and the semiconductor substrate 4. When the bit lines BL and BL are formed by diffusion layers, the electrostatic capacitance is greater than that when the bit lines BL and BL are formed by polysilicon or aluminum.. The input signal lines 3 and 3' are wiring layers of, for example, aluminum formed on the substrate 4 through an insulating layer (not shown in Figure 1). Therefore, an electrostatic capacitance is also formed between each input signal line and the semiconductor substrate 4. The above-mentioned capacitance may cause a problem, as hereinafter described with reference to Figure 2, showing an expanded cross-section taken along line II-II' of Figure 1. In Figure 2, the bit lines BL and BL are formed as diffusion layers at the surface of the semiconductor substrate 4. The input signal lines 3 and 3' extend in an insulating layer 5 formed on the semiconductor substrate 4. An equivalent circuit, showing the electrical relationship among the bit lines BL and BL, the semiconductor substrate 4, and the input signal lines 3 and 3', is also illustrated in Fig. 2. As mentioned before, between each input signal line 3 and the semiconductor substrate 4, there is an electrostatic capacitance CO , C1 , or C2. Also, an electrostatic capacitance C3 , C4 , or C5 is formed between each input signal line 3' and the semiconductor substrate 4. Further, between the bit lines BL and BL and the semiconductor substrate 4, there are electrostatic capacitances C6 and C7 , respectively. Since the semiconductor substrate 4 has a resistance, a resistance R is illustrated between the capacitances C6 and C7. No through N7 in the semiconductor substrate 4 are nodes connected to these capacitances CO through C7 , respectively. Due to the presence of these capacitances, the potential of the semiconductor substrate is influenced by the potential of the input signal lines 3 and 3'. In other words, if the potentials of the input signal lines 3 and 3' are changed by changing the address signals or data applied to the input terminals Ao through A5 , the potentials at the nodes No through N5 in the semiconductor substrate 4 are also changed. If the potentials of both groups of the input signal lines 3 and 3' are changed simultaneously in the same direction, i.e., from a high (H) level to a low (L) level or from a low (L) level to a high (H) level, and if the number of the input signal lines 3 is the same as the number of the input signal lines 3', no problem will occur. When one group of the input signal lines 3 changes simultaneously from the L level to the H level and the other group of the input signal lines 3' changes simultaneously from the H level to the L level, however the worst case will occur. In this worst case, the potentials at the nodes No , and , andN2 are simultaneoulsy boosted, and the potentials at the nodes N3 , N4 , and N5 are simultaneously lowered. Since the node N6 is relatively close to the nodes No through N2 , the potential at the node N6 is also boosted. Also, since the node N7 is relatively close to the nodes N3 through N5 , the potential at the node N7 is also lowered. Due to the presence of the capacitance C6 , the potential of the bit line BL is boosted. Also, due to the presence of the capacitance C7 , the potential of the bit line BL is lowered. Since the nodes #6 and N7 are separated by the resistance R, the potentials of the nodes w6 and N7 can not be equilibrated for a definite period due to the presence of the resistance R. Thus, the maximum potential difference is produced between the bit lines BL and BL. Assume that the actual data stored in a memory cell is one for increasing the potential of the bit line BL over the potential of the bit line BL. In this condition, if a reading operation is effected with respect to the above memory cell simultaneously with the change of the potentials, due to the capacitances, of the bit lines BL and BL, the capacitances CO through C7 may conversely make the potential of the bit line BL higher than the potential of the bit line BL, causing the sense amplifier SA. to detect erroneous data. A similar discussion applies to the case when the input signal lines 3 simultaneously change from the H level to the L level and the input signal lines 3' simultaneously change from the L level to the H level. The signals to be applied to the input signal lines can take any value. That is, it is not predetermined what type of signals they are, i.e., what combination of the H levels and L levels they are. Depending on the combination of the input signals, it is possible that the potential difference between the bit lines BL and BL due to the capacitances CO through C7 will become sufficiently large to cause an error reading of the sense amplifier SAi. Embodiments of the present invention will now De de scribed with reference to Figs. 3 and 4. Figure 3 is a cross-scction of a part of a dynamic semiconductor memory device according to a first embodiment of the invention. In the figure, the input signal lines 3 or 3', the semiconductor substrate 4, and the insulating layer 5 are the same as those in Fig. 2. The difference between Figs. 2 and 3 is that, in Fig. 3, a diffusion layer 6 of a conductivity type opposite to that of the semiconductor substrate 4 is formed at the surface of the semiconductor substrate 4 and under the input signal lines 3 or 3'. The diffusion layer 6 is connected to the ground. Alternatively, the diffusion layer 6 may be connected to a power supply (not shown). The diffusion layer 6 may be formed under one group of the input signal lines 3 or 3' or under both groups of the input signal lines 3 and 3'. Figure 4 illustrates another embodiment of the present invention. In Fig. 4, instead of the diffusion layer 6 in Fig. 3, a wiring layer 7, made of a good conductor such as polysilicon, aluminum, molybdenum (Mo), or molybdenum -silicide (MoSi2) is formed in the insulating layer 5 and under the input signal lines 3 or 3'. The wiring layer 7 is also connected to the ground or to a power supply. The tiring layer 7 may also be formed under one group of the input signal lines 3 or 3', or under both groups of the input signal lines 3 and 3'. The diffusion layer 6 in Fig. 3 and the wiring layer 7 in Fig. 4 act as electrostatic shield layers, respectively, of the input signal lines 3 and/or 3' for the semiconductor substrate 4. Accordingly, changes of the potentials at the input signal lines 3 and 3' by external input signals have no effect on the potential of the semiconductor substrate 4. 2nerefore, little or no potential difference is produced between the bit lines BL and BL in response to the potential change of the input signal lines 3 and 3'. Thus, error reading by the sense amplifier in the dynamic semiconductor memory device can be protected against. The present invention is not restricted to the above -described dynamic semiconductor memory device Many other modifications and changes are possible without departing from the spirit of the present invention. For example, a shielding layer such as layers 6 and 7 is also effective in other static semiconductor memory devices, code converters (CODEC), and many other semiconductor devices. Further, instead of forming the shielding layer under the input signal lines and on the semiconductor substrate, the shielding layer may be formed under the bit lines and on or at the surface of the semiconductor substrate, in an embodiment of the invention.

Claims: CLAIMS: 1. A semiconductor device comprising a semiconductor substrate and first and second groups of signal lines extending over the substrate, the lines of said first group being spaced apart from the lines of the said second group over the substrate,characterised by an electrostatic shield layer (6) interposed between one of said first and second groups of signal lines (3) and the said substrate (4). 2. A semiconductor device as claimed in claim 1, wherein said electrostatic shield layer has a means for electrostatically shielding said signal lines from said semiconductor substrate. 3. A device as claimed in claim 1, wherein the said electrostatic shield layer is connected to a constant-voltage reference terminal of the device. 4. A semiconductor device as claimed in claim 1, 2 or 3, wherein said electrostatic shield layer is a diffusion layer of opposite conductivity type to the said semiconductor substrate, which diffusion layer is formed at the surface of said semiconductor substrate. 5. A semiconductor device as claimed in claim 1, 2 or 3, wherein said electrostatic shield layer is a wiring layer formed on said semiconductor substrate, said wiring layer being formed of material of good electrical conductivity. 6. A semiconductor device as claimed in any preceding claim, wherein said semiconductor device is a dynamic semiconductor memory device in which said first group is a group of input signal lines, for receiving address signals or data, and the said second group is a group of bit lines.

Inventors: NAKANO, MASAO, NAKANO, TOMIO
Applicants: FUJITSU LIMITED
Application year: 1982
Main classification: H01L23
IPC codes: H01L27, H01L23