SEMICONDUCTOR DEVICE COMPRISING A METALLIC CONDUCTOR

Abstract: A material having metallic conduction (hereinafter referred to as a "metallic material" is heteroepitaxially grown in the laminar form on an insulating substrate (11) by molecular beam epitaxy. The resulting metallic material layer (12) is shaped in a desired pattern, whenever necessary. At least a semiconductor layer (13) is heteroepitaxially grown on the metallic material layer (12) and a semiconductor device is fabricated using the semiconductor layer (13). In this case, the metallic material layer (12) is used as one of the electrodes of the semiconductor device.

Description: TITLE OF THE INVENTION: SEMICONDUCTOR DEVICE BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a semiconductor device formed by heteroepitaxially growing a metallic conduction material on an insulating substrate. In forming vertical semiconductor devices such as diodes, bipolar transistors, FETs (Field Effect Transistors) and the like, one of the electrodes of each device is inevitably interposed between a semiconductor and a substrate. The present invention provides a method of solving the difficulty in wiring when semiconductor devices having the vertical structure are formed on the same substrate, and can be applied to all the integrated circuits of the vertical devices. Description of the Prior Art SOS (Silicon-On-Sapphire) has been known conventio nally as a technique of heteroepitaxially growing a semiconductor film on an insulating substrate and forming a semiconductor device in the film. In SOS, however, the device is limited to the lateral type because no metallic film is interposed between Si and sapphire. Since the lateral type semiconductor device uses photolithography (or electron lithography) to determine the shape and size of the active region, a device length of 0.5 pm is believed a practical limit. Accordingly, the performance that can be expected of such a relatively large device is naturally limited as typified by the switching time of at least 50 ps in the case of-Si, for example. In the lateral devices of GaAs, an HEMT (High Electron Mobility Transistor) skilfully employing the heterostructure has been known but the limit of the switching time is believed to be 30 ps at room temperature because machining below 0.5 pm is extremely difficult. The idea of interposing a metallic film between a semiconductor film and an insulating substrate to form an electrode has been known in the past, but such an idea is limited to those devices which are fabricated inside polycrystalline semiconductor films superposed on a polycrystalline metal layer and are limited to those generally r#eferred to as "TFTs" (thin film transistors). These devices involve the drawbacks resulting from the polycrystalline film that the switching speed is low, the leakage current is great and the period of time for the recombination of the minority carriers is short. Incidentally, the above-mentioned soss and TFTs are disclosed in the following literatures: (1) Proc. IEEE, 52, p. 1487 ('64), C.W. Mueller et al, "Grown-film silicon transistors on sapphire", (2) Proc. IEEE, 52, p. 1479 ('64), P.K. Weimer et al, "Integrated circuits incorporating thin-film active and passive elements". Typical examples of the heterostructures grown by molecular beam epitaxy of silicon and metal silicide are disclosed in the following literatures: (3) Appl. Phys. Lett., 37, p643 ('80), J.C. Bean and J,M. Poate "Silicon/metal silicide heterostructures grown by molecular beam epitaxy", (4) Appl. Phys. Lett., 23, p201 ('73), "Molecular beam epitaxy of alternating metal-semiconductor films". SUMMARY OF THE INVENTION A metallic material having metallic conduction (hereinafter referred to as the "metallic material") is heteroepitaxially grown in the laminar form on an insulating substrate and the metallic material layer is shaped in a desired pattern, whenever necessary. At least a semiconductor layer is heteroepitaxially grown on this metallic material layer and a semiconductor device is fabricated using this semiconductor layer. The gist of the present invention resides in that the metallic material layer is used as one of the electrodes of the semiconductor device. Molecular beam epitaxy is used for the heteroepitaxial growth. Typical examples of the insulating substrate include sapphire, spinel and high resistivity GaAs crystal. Typical examples of the metallic material include metals such as AB and silicides of transition metals. Though the design value of the thickness of the metallic material layer varies with the material used, the layer is generally from about 20 nm to about 3 pm thick. The thickness which makes possible electric wiring is used as the lower limit while the upper limit is decided by factors other than the electric conductivity. Even if the layer is verv thick, much advantage can not be obtained. Si, GaAs or GaAxAs that is used for semiconductor devices in general is also used as the semiconductor layer. Since the metallic material is hereteroepitaxially grown on the insulating substrate, followed by the heteroepitaxial growth of at least the. semiconductor layer further on the metallic material layer, matching of the mutal lattice constants should naturally be considered. If Si is used as the semiconductor material, therefore, it is advisable to use sapphire or spinel for the insulating substrate and silicide of a transistion metal for the metallic material layer. Definite examples of the silicides of transistions metals will be illustrated in the later appearing examples. When GaAs or GaA#As is used as the semiconductor material, a high resistivity GaAs crystal and AA can be suitably used for the insulating substrate and the metallic layer, respectively. It is naturally possible to interpose a so called "buffer layer" between the metallic material layer and the semiconductor layer having active region in order to improve their lattice matching. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a perspective view showing a Schottky gate FET to which the present invention is applied; Figures 2a through 2e are sectional views, each showing stepwise the frabrication step of the transistor shown in Figure 1; Figure 3 is a perspective view showing a junction FET to which the present invention is applied; Figure 4 is a sectional view of an integrated diode; Figure 5 is a sectional view of a bipolar transistor; Figure 6 is a sectional view of a switching device; Figure 7 is a sectional view of a vertical type junction FET; and Figure 8 is a sectional view of a lateral type junction FET. DESCRIPTION OF THE PREFERRED EMBODIMENTS A variety of semiconductor devices can be naturally fabricated using the semiconductor material described already. Examples of the semiconductor devices are as follows: o bipolar transistor including a pnp (or npn) or pinp (or nipn) structure in the semiconductor material; o diode including a pin or pnin (or npin) structure in the semiconductor material; o switching device having a pnpn structure; o static induction transistor (SIT); o junction field effect transistor (J-FET); o Schottky barrier gate - SIT, o permeable base transistor (PBT). Various other semiconductor devices can also be fabricated. In addition to the high speed performance resulting from the small wiring capacity, the semiconductor device in accordance with the present invention can improve by far the performance over the lateral devices because the active region is determined by the thickness of the semiconductor film formed by heteroepitaxial growth. Example 1 This example uses sapphire as the insulating substrate. Figure 1 is a perspective view of a vertical Schottky gate FET and Figures 2a through 2e are sectional views, showing stepwise the fabrication process of the FET. As shown in Figure 2a, sapphire is used as the insulating substrate 11 and Si and Ni are simultaneously vacuum-evaporated for expitaxial growth in a thickness of 20 nm in such a ratio that an intermetallic compound 12 of NiSi2 is formed. The vacuum in this case is generally 1,33 x 10 7 Pa (at least 1,33 x 10 6 Pa). The temperature of the substrate is from about 5500C to about 8009C and the growing speed is about 0.1 This. The layer 12 is then shaped photolithographically in the customary manner so that discrete devices can be electrically cut off. Silicon and antimony are then vacuum-evaporated simultaneously and an n-type Si layer 13 having a carrier concentration of 1x1018 cm 3 is heteroepitaxially grown in a thickness of 10 nm. The n-type Si layer 13 is made into a predetermined shape. At the substrate temperature ranging from 500 to 7000C, an extremely small trace amount of Sb is doped and an Si vacuum-evaporation layer 14 having relatively high resistivity is heteroepitaxially grown in a thickness of 50 nm. Its carrier concentration is selected in the range of 1014 Z n < 3x1016 cm . The Si layers 13 and 14 are photo-etched in predetermined patterns so as to partially expose the layer 12. An NiSi2 film 17 is grown further thereon in a thickness of 20 nm and is made into a lattice having a width of 1 yin and a gap of 1 # by photolithography (Fig. 2c;refer to Figure 1 for the lattice portion of the layer 17). Next, polycrystalline At layers 15, 18 are vacuumevaporated and made photolithocraphically in predetermined shapes so as to transversely connect the lattices. The same Si having relatively high resistivity as the layer 14 is heteroepitaxially grown (14': in a thickness of 50 nm so as to define a structure so that Si encompasses the aforementioned lattice (see Figure 2d). The same Si:Sb film 19 as the layer 13 is grown heteroepitaxially over the entire surface of the structure in a thickness of 20 nm, such as depicted in Figure 1. An aperture reaching the aluminum film 15 is bored in the layers 19 and 14' by photolithography and A0 thus exposed and an external electrode are wire-bonded. An electrode 20 is simultaneously disposed (16). Thus, the vertical Schottky gate FET having the structure shown in Figure 1 is obtained. The regions 13 and 19 correspond to means for injecting and sucking the carriers such as the source and drain in ordinary FETs and the electrode 17 corresponds to carrier control means such as the gate of the ordinary FET. Reference numerals 15 and 18 represent extension electrodes. Since the length of the active area is as short as 100 nm in the structure of this example, it is confirmed that switching is effected within a period as short as 1/5 to 1/10 of the switching time of the ordinary lateral devices. Example 2 This example uses GaAs as the insulating substrate. Figure 3 is a perspective view of a J-FET. As shown in Figure 3, Cr-doped GaAs (10 KQcm) 21 is used as the insulating substrate and Ak is formed thereon by molecular beam epitaxy at a vacuum of at least 1.33 x 10 Pa, providing a heteroepitaxial fill. 22. This At layer is photo-etched in a suitable shape by a customary method so as to obtain a lower electrode. A slightly Si-doped n-type GaAs film 24 is heteroepitaxially grown on the AQ film in a thickness of 50 nm by vacuum-evaporating Ga, As and Si from individual sources. Next, Be-doped p-type GaAs is similarly grown heteroepitaxially. Only the p-type GasAs is made into the lattice form by photolithography in the same way as in Example 1 (221). Next, an n-type GaAs film 24'is superposed in a thickness of 50 nm in the same way as the layer 24. An aperture reaching the p-type GaAs 221 is bored in a region 40 of the layer 24'by photo-etching. An aperture reaching the layer 22 is likewise bored in a region 41 of the layers 24 and 24' by photo-etching. After an aluminum vacuum-evaporation film is superposed in a thickness of 1 Fm over the entire surface, electrodes 27, 27' from AQ and the p-type GaAs are formed by photolithography. Reference numerals 16 and 20 represent electrode wires, respectively. According to the process described above, there can be obtained a vertical J-FET. Example 3 This example illustrates an example of the vertical diode SC. Figure 4 is a sectional view of the device. CoSi2 32 is heteroepitaxially grown in a thickness of 30 nm on a spinel substrate 31 at a substrate temperature of 600 to 6500C and photo-etching is then carried out to obtain a desired pattern. A 100 nm 17 -3 thick n-type Si 33 doped with As of 2xl0l7 cm is heteroepitaxially grown on the pattern. Next, Ga and Si are simultaneously vaccum-evaporated at the substrate temperature of 500 to 7000C and a p-type Si film 34 is heteroepitaxially grown in a thickness of 100 nm, thereby forming a p-n junction. Next, portions other than the portion at which the diode is electrically isolated are covered with Si N by a plasma CVD process and selective oxidation is effected at 1,200 C, forming an Sio, layer 36. In this case, the lower electrode 32 is not oxidized and keeps metallic conduction. An aperture reaching the CoSi2 layer 32 is bored in the necessary region (e.g. region 38) of the resulting SiO2 by photolithography and AQ (37) deposited on SiO2 by vacuum evaporation is connected to the layer 32. After photoetching in a predetermined wiring pattern is effected, a vertical diode IC in which a plurality of diodes are integrated can be obtained. In the example shown in Figure 4, the regions A and B from the diodes, respectively. As the metals forming the heteroepitaxial structure in the semiconductor, the foregoing embodiments use versus GaAs and NiSi2, and CoSi2 versus Si, but it is also possible to use verious combinations such as listed below: For Si: AXSi (where A is a member selected fron the group consisting of Ti, Zr, Hf, Cr, Mo W, V, Nb, Ta, Mn, Fe, Co, Ni, Pt, Pd, Rh and Ir and x is 0.5, 1, 1.5, 2, 2.5 and 3, for example). Example 4 The gist of the invention resides in that a laminar material having metallic conduction is heteroepitaxially grown on an insulating substrate, is shaped in a desired pattern, whenever necessary, and is further grown heteroepitaxially to fabricate a semiconductor layer in which a semiconductor device is to be fabricated, and the metallic material is used as one of the electrodes of the device. Various semiconductor devices can be naturally formed thereon. The foregoing embodiments are not limitative. For example, a bipolar transistor, a diode and a switching device can be formed by forming the semiconductor in the pnp (or npn) or pinp ior nipn) structure, in the pin or pnin (or npin) structure and in the pnpn structure, respectively, and the metallic material can be used as one of the electrodes. Figures 5 through 8 show examples of these other semiconductor devices. Figure 5 is a sectional view of a typical bipolar transistor. A metallic material layer 12 consisting of NiSi2 is heteroepitaxially grown on a sapphire substrate 11 by molecular beam epitaxy and a bipolar transistor is formed on the layer thus grown. Reference numerals 41 represents a highly doped n-type Si layer; 42 is an n-type Si layer (about 500 nm thick); 43 is a p-type Si layer (about 50 nm thick); 44 is an n-type Si layer (about 200 nm thick); and 45, 46 and 47 are A1 layers. The layers 12, 41, 42, 43 and 44 are heteroepitaxially grown by molecular beam epitaxy in the same way as in the foregoing embodiments. The highly doped n-type Si layer 41 is a layer for the contact with the electrode in the same way as in the ordinary semiconductor device; the layer 42 is a collector, the layer 43 is a base and the layer 44 is an emitter. Figure 6 is a sectional view showing an example of a switching device having the pnpn structure. A metallic material layer 12 consisting of NiSi2 is heteroepitaxially grown on-a sapphire substrate 11 by molecular beam epitaxy and a switching device is formed thereon. Reference numeral 48 represents a highly doped p-type Si layer for the contact with the metallic material layer 12. Reference numeral 49 represents a p-type Si layer (1 pm thick); 50 is an n-type Si layer (0.5 pm thick); 51 is a p-type Si layer (0.5 um thick); 52 is an n-type Si layer (1 um thick); and 53 is a highly doped n-type Si layer for the contact with an electrode 55. These layers are formed by heteroepitaxial growth by molecular beam epitaxy. Reference numerals 55 and 54 represent electrodes consisting of an AQ vacuum-evaporation film. Figure 7 is a sectional view showing an example of a vertical type junction field effect transistor. A semiconductor film having a pi (or ni) structure is formed and a donor (or acceptor) is selectively introduced into the i layer by ion implantation or vapor/solid phase diffusion to obtain a desired pattern. Alternatively, the i layer is selectively etched and an n (or p) layer is selectively grown on the etched portion to obtain a desired pattern. A gate electrode is thus formed. On the resulting gate electrode, an ip (or in) layer is then grown epitaxially to form a J-FET (junction field effect transistor). The metallic material is used as one of the electrodes of this FET. An NiSi2 layer 12 is heteroepitaxially grown on a sapphire substrate 11 and the junction field effect transistor is formed on the layer in this embodiment. A comb-like gate 58 consisting of p-type Si is buried in n-type Si layers 57, 59. Though not shown in the sectional view of Figure 7, the gates 58 are connected to one another at one of their ends and form the comblike shape as a whole. The layers 56 and 60 are layers for establishing contact with the electrodes and are highly doped n-type Si layers. Reference numerals 61 and 62 are source (or drain) and drain (or source) electrodes. Figure 8 is a sectional view showing an example of a lateral type junction field effect transistor. In the same way as in the foregoing embodiments, the metallic material 12 consisting of NiSi2 is heteroepitaxially grown on the sapphire substrate 11 and the junction field effect transistor is formed on the layer 12. Reference numeral 63 represents a p-type Si layer; 64 is a lowly doped n-type Si layer; 65 is a poly-sJlicon layer for the gate; 66 and 67 are highly doped n-type Si layers;- and-68, 69, 70 and 71 are aluminum electrodes, respectively. The layers 63, 64, 66 and 67 are heteroepitaxially grown by molecular beam epitaxy as described already. The electrode 68 is the gate and a voltage is applied across the electrodes 68 and 71. Reference numerals 69 and 70 represent source (or drain) and drain (or source). In fabricating the semiconductor devices illustrated in the foregoing embodiments, the following structures can be naturally employed, whenever necessary. (1) The semiconductor layer grown on the metallic material layer is partially removed and a metallic layer of the same or different kind is laminated at a predetermined position of the metallic layer in a thickness necessary and sufficient for bonding so as to connect an external electrode. (2) A through-hole is bored at a predetermined posi tion on the semiconductor layer and an insulating film is deposited on the upper surface of the semiconductor layer and on the side surface of the through-hole so that the metallic material layer can be easily connected to the external electrode by a wiring connected to the metallic material layer and disposed on. the insulating film. (3) In forming one semiconductor device and another on the same substrate, either the semiconductor layer is nesa -etched or a portion to be electrically isolated is selectively oxidized or nitrided in order to electrically cut off one device from another. (4) A metal is deposited at a predetermined position on the semiconductor layer so as to use it as a pad for the bonding connection with an external electrode. Alternatively, an insulating film is deposited on the semiconductor and the film at a predetermined position is removed. A plurality of semiconductor devices on the same substrate are connected to one another by conductor wirings that are brought into contact with the removed portion and are shaped in a desired pattern.

Claims: CLAIMS: 1. A semiconductor device including at least a material layer (12) having metallic conduction and heteroepitaxially grown on an insulating substrate (11) and at least one semiconductor region heteroepitaxially grown on said material layer (12), wherein an active region is formed using said semiconductor region and said material layer (12) having metallic conduction is used as one of the electrodes of said semiconductor device. 2. The semiconductor device of claim 1, wherein said insulating substrate (11) consists of sapphire or spinel, said material layer (12) having metallic conduction consists of a silicide of transition metals and said semiconductor region (13) is a layer consisting of silicon. 3. The semiconductor device of claim 1, wherein said material layer (22) having metallic conduction consists of A# and said semiconductor region (221) consists of GaAs or GaAQAs. 4. The semiconductor device of any one of claims 1 to 3, wherein said semiconductor region (42.. .44) has at least a pnp (or npn) or pinp (or nipn) structure and forms a bipolar transistor. 5. The semiconductor device of any oneof claims 1 to 3 wherein said semiconductor region has at least a pin or pnin (or npin) structure and forms a diode. 6. The semiconductor device of any one of claims 1 to 3 wherein said semiconductor region (49.. .52) has at least a pnpn structure and forms a switching device. 7. The semiconductor device of any one of claims 1 to 3 wherein at least a static induction transistor is formed in said semiconductor region. 8. The semiconductor device of any one of claims 1 to 3 wherein at least a junction field effect transistor is formed in said semiconductor region (57...59; 64, 65). 9. The semiconductor device of any one of claims 1 to 3 wherein at least a permeable base transistor is formed in said semiconductor region.

Inventors: MURAYAMA, YOSHIMASA, NAKAGAWA, KIYOKAZU, SHIRAKI, YASUHIRO
Applicants: HITACHI, LTD.
Application year: 1982
Main classification: H01L21
IPC codes: H01L21, H01L29