ELECTRIC SIGNAL COMPRESSING APPARATUS

Abstract: Apparatus for compressing an electrical input signal so as to accommodate a large dynamic range of the signal without loss of information represented by the signal, the apparatus comprising first, second and third (12, 14, 16) storage means for receiving the input signal; a gate (18) coupled between the second and third storage means so as to selectively inhibit the transfer of the signal from the second storage means to the third storage means; means (24, 23) coupling the third storage means to a receiving device; and means, including the gate (18), for enabling substantially all of the signal to be received by the receiving device for low levels of the signal, and for enabling only a portion of the signal to be received by the receiving device for other than low levels of the signal.

Description: The present invention relates to apparatus for compressing an electric input signal, e.g. from an infrared device so as to accommodate a large dynamic range of the signal which is to be transferred to a receiving device such as a charge coupled device (CCD). The application of infrared detectors to imaging is growing steadily. As advanced infrared systems are being developed, the requirement for greater sensitivity and resolution is desired for many applications. System performance parameters relating to these requirements always depend on the signal to noise ratio of the many individual detectors comprising the focal plane. The use of multielement focal planes of small closely packed detectors, made possible by the use of charge coupled devices, has helped reduce the noise in such systems, while allowing use of a large number of detectors, and, therefore, better satisfy the sensitivity and resolution requirements. The coupling circuit between the detectors and the CCDs must transform the signal information from the detectors into charges in the CCD shift registers with minimum degradation of the signal-to-noise ratio of the system. The input circuit must tailor the signal so that the CCD charge capacity is not exceeded when the signal, including the background signal, varies over the system dynamic range. In addition, the CCD must be protected from excess charge from signals beyond the system dynamic range, because excess charge injected into the CCD from one detector input will mix with charge from other inputs, thereby causing so-called image blooming and loss of information. The gain of such input circuits must be uniform so that every CCD channel has the desired maximum signal capability without saturating the CCD. Some focal plane applications require the capability of handling a very large dynamic range, and, therefore, a very large range of signal or input current to the CCDs. For example, in some applications, the background seen by the detector varies over a range of up to 10,000 to 1. In addition, the input circuit must handle this large range of inputs while maintaining a low noise figure. An ac detector/CCD coupling approach has previously been used in an attempt to handle this dynamic range, however, it has been found that this approach is strongly susceptible to CCD input nonuniformities and CCD input low frequency noise. Further, such approach has no radiometric capability. A technique for handling moderate dynamic range, sometimes referred to as the Charge Equilibrium (CE) circuit, provides charge buffering by use of charge reduction or low gain. This technique reduces noise by use of a standard charge splitting circuit. For further information on these techniques, see the articles entitled "IR/CCD Hybrid Focal Planes" by R Broudy et al, published in The Proceedings of the Society of Photo-optical Instrumentation Engineers (SPiE), Volume 132, 1978, and "Multiplexed Intrinsic Detector Arrays With Signal Processing (MIDASP)" by M Gurnee et al, published in The Proceedings of the Society of Photo-optical Instrumentation Engineers (SPiE), Volume 217, 1980. According to the present invention, there is provided a charge buffer circuits compressing an electrical charge input signal so as to accommodate a large dynamic range of the signal without loss of information represented by the signal, said circuit comprising first, second and third storage means (12, 14, 16) including first, second and third potential wells formed in a semiconductor substrate by voltage levels applied to bias each one of said storage means, said first potential well receiving the input signal, said first and second potential wells being adjacent to one another and having respective depths so as to allow signal current flow from said first potential well to said second potential well, said second and third potential wells being separated by a first gate (18) so as to selectively inhibit the signal current flow from the second potential well to the third potential well, and said third potential well being coupled to a receiving device, said first gate being enabled in a first operation mode of the circuit to allow signal current flow through the first and second potential wells into the third potential well,and said first gate being disabled in a second operation mode of the circuit during signal charge transfer from said third potential well to said receiving device, said circuit further comprising reset means (20, 22) coupled to the second potential well, said reset means resetting in a third operation mode of the circuit portions of the signal charge remaining in the first and second potential wells when the first gate is disabled, said charge input-signal being compressed by maintaining the gain of the circuit so as to be dependent on the magnitude of the input signal in that at a relatively low input signal level all of the signal charge is stored in the third potential well in the first operation mode and transferred to the receiving device in the second operation mode, in that at a relatively medium input signal level the signal charge is stored in the second and third potential wells in the first operation mode so that only the portion of the signal charge stored in the third potential well is transferred to the receiving device in the second operation mode and the portion remaining in the second potential well is reset in the third operation mode, the gain of the circuit thus being substantially equal to the magnitude of the signal portion stored in the third potential well divided by the sum of the magnitudes of those signal portions stored in both the second and third potential wells, and in that at a relatively high input signal level the signal charge is stored in the first, second and third potential wells in the first operation mode so that only the portion of the signal charge stored in the third potential well is transferred to the receiving device in the second operation mode and the portions remaining in the first and second potential wells are reset in the third operation mode, the gain of the circuit thus being proportional to the magnitude of that portion of the signal charge stored in the third potential well divided by the sum of the magnitudes of those signal portions stored in the first, second and third potential wells. An embodiment of the invention will now be described by way of example only, with reference to the accompanying drawings, in which:- Figure 1 illustrates diagrammatically the configuration of an input circuit signal compression apparatus according to the present invention; Figure 2 illustrates the potentials applied to the various gates and the charge storage capacity of the various wells of the input circuit; and Figure 3 illustrates the input compression characteristics of the input circuit. Referring to Figure 1, the detector apparatus includes a detector (not shown) which provides an input current to an input circuit via source 10 and gate 11. The input circuit includes three potential wells 12, 14 and 16. These wells are used to store minority charge carriers along the surface of a semiconductor just below insulated conductive regions which are biased with respect to the underlying crystal by an applied potential of a few volts (see Figure 2). The greater the potential applied, then the deeper the well is, and more charge can be stored in the deeper wells. The input circuit of the present apparatus utilizes, for example, three different potentials, VS1, VS2 and VS3. The potential VS1 is applied to well 12, VS2 applied to well 14, and VS3 applied to well 16. The potential VS1, is lower in magnitude than VS2, which in turn is lower than VS3. However, the potential VS3 could be lower than potential VS2. Gate 11 is utilized to enable input current from the detector to flow into well 12 at a controlled rate determined by the system. In addition to gate 11, gate 18 is utilized to transfer charge into well 16 and isolate it there in accordance with system timing. Gate 20 is enabled at the appropriate time to reset, i.e., empty, the contents of wells 12 and 14 by use of a reset voltage 22. Gate 24 is enabled when the charge in well 16 is to be transferred to the charge coupled device CCD (not shown). This transfer to the CCD may be directly from gate 24 or may, in the alternative as shown, be made through well 26 and gate 28. As described hereinafter, it will be seen that for low input currents, the input circuit of the present apparatus will have approximately unity gain, whereas, for mid-range and high input currents, the gain will be reduced. The input/output gain curve shown in Figure 3 illustrates a typical gain of the circuit of Figure 1. Three different gain slopes can be seen in Figure 3 for various input currents I. The output voltage V o (to the CCD) is shown on the vertical axis. By use of different gains, the input current is "compressed" with the fixed gain or compression curve of Figure 3 before injection of the charge into the CCD, which may take the form of a well-known CCD shift register. The operation of the input circuit, the configuration of which, and surface potentials for which, are shown in Figures 1 and 2, which Figures are aligned as indicated by the dotted lines, shall now be discussed. At low background or signal level, the input current flows through wells 12 and 14 into well 16. Gate 11 is enabled continuously to allow such current flow, whereas gate 18 is enabled to allow current to flow into well 16. At low input current, all of the charge will be found stored in well 16 when gate 18 is disabled. At this time, the charge in well 16 will be transferred to the CCD (assuming that well 26 and gate 28 are not used). For large, but intermediate, input currents, well 16 will be filled above the level of potential VS2 such that charge is stored in both wells 16 and 14. Gate 18 is then disabled and the charge in well 16 is transferred to the CCD. The charge in well 14 is removed by resetting well 14 by the use of potential 22 when gate 20 is enabled. The incremental gain under these intermediate input conditions is given by the capacitance of well 16 divided by the sum of the capacitance of wells 14 and 16, or gain equals W3/(W3 + W2). At high background and/or signal conditions, wells 16 and 14 are filled above potential VS2 and, therefore, charge is stored in the combination of wells 16, 14 and 12. When gate 18 is disabled, the charge stored in well 16 is transferred to the CCD. Following such transfer, the charge stored in wells 12 and 14 is reset by use of gate 20 and potential 22. The incremental gain under these high input conditions is given by the capacitance of well 16 divided by the sum of the capacitance of wells 16, 14 and 12, or gain equals W3/(W1 + W2 + W3). It can be seen that the relative potentials on each storage well and the number of wells can be optimized for a specific application. That is, there may be more than three wells for any particular application. Further, a single large well with a potential variation, i.e, a continuous storage depth variation, along it can be formed, for example, by use of a resistive drop in a polysilicon gate, thereby providing a smooth compression characteristic. It can also be seen that a so-called accumulator well 26 may be used. The accumulative well 26, coupled between gate 24 and gate 28, provides additional storage between the detector and the CCD. Accumulator well 26 is deeper than the other wells and may be used to collect and accumulate the charge received from well 16 for several input sample periods until such time as gate 28 is enabled to transfer the total charge in well 26 to the CCD. The accumulator well is utilized where unusually high input currents are encountered, thereby enabling the operation of wells 12, 14 and 16, as hereinbefore described, without encountering an overload condition which may cause a loss of information.

Claims: Charge buffer circuit compressing an electrical charge input signal so as to accommodate a large dynamic range of the signal without loss of information represented by the signal, said circuit comprising first, second and third storage means (12, 14, 16) including first, second and third potential wells formed in a semiconductor substrate by voltage levels applied to bias each one of said storage means, said first potential well receiving the input signal, said first and second potential wells being adjacent to one another and having respective depths so as to allow signal current flow from said first potential well to said second potential well, said second and third potential wells being separated by a first gate (18) so as to selectively inhibit the signal current flow from the second potential well to the third potential well, and said third potential well being coupled to a receiving device, said first gate being enabled in a first operation mode of the circuit to allow signal current flow through the first and second potential wells into the third potential well,and said first gate being disabled in a second operation mode of the circuit during signal charge transfer from said third potential well to said receiving device, said circuit further comprising reset means (20, 22) coupled to the second potential well, said reset means resetting in a third operation mode of the circuit portions of the signal charge remaining in the first and second potential wells when the first gate is disabled, said charge input signal being compressed by maintaining the gain of the circuit so as to be dependent on the magnitude of the input signal in that at a relatively low input signal level all of the signal charge is stored in the third potential well in the first operation mode and transferred to the receiving device in the second operation mode, in that at a relatively medium input signal level the signal charge is stored in the second and third potential wells in the first operation mode so that only the portion of the signal charge stored in the third potential well is transferred to the receiving device in the second operation mode and the portion remaining in the second potential well is reset in the third operation mode, the gain of the circuit thus being substantially equal to the magnitude of the signal portion stored in the third potential well divided by the sum of the magnitudes of those signal portions stored in both the second and third potential wells, and in that at a relatively high input signal level the signal charge is stored in the first, second and third potential wells in the first operation mode so that only the portion of the signal charge stored in the third potential well is transferred to the receiving device in the second operation mode and the portions remaining in the first and second potential wells are reset in the third operation mode, the gain of the circuit thus being proportional to the magnitude of that portion of the signal charge stored in the third potential well divided by the sum of the magnitudes of those signal portions stored in the first, second and third potential wells. Circuit according to Claim 1, characterised in that said reset means (20, 22) includes a second gate (20) coupled to a signal drain means (22). Circuit according to Claim 1 or 2 characterised in that the input signal is received from an infrared detector and the receiving device is a charge coupled device. Circuit according to any preceding Claim, characterised by including an accumulator storage means (26) successively accumulating a predetermined number of portions of the input signal transferred from the third storage means (16) prior to receipt thereof by the receiving device. Circuit according to Claim 4 characterised in that the storage capacity of the accumulator storage means (26) is greater that the storage capacity of the third storage means (16). Circuit according to any preceding Claim, characterised in that the storage capacity of the third storage means (16) is less than the storage capacity of the second storage means (14). Circuit according to any preceding Claim characterised in that the first, second and third storage means (12, 14, 16) are, except for the first mentioned gate 18, contiguous with each other to collectively form one storage means having a continuous storage depth variation so that the magnitude of the signal capable of being stored increases continuously in and through each of the storage means.

Inventors: DRIES, MICHAEL F., GURNEE, MARK N.
Applicants: HONEYWELL INC.
Application year: 1982
Main classification: H01L27
IPC codes: G11C27, H01L21, H01L29, H01L27