SEED CONTROL APPARATUS WITH A MICROPROCESSOR

Abstract: The seed control apparatus contains photoelectric seed-detectors, devices for measuring the distance covered, display and operating organs, data and control busses, buffer memories, a power supply unit, as well as a microprocessor system consisting of the microprocessor, program and data memories and the interface circuit inserted between the data bus and the detecting organs. In addition of the performance of the usual functions the microprocessor is programmed for counting operations. Between the microprocessor system and the detecting organs a programmable parallel input/output interface circuit interfacing the outputs of the detecting organs to the data bus of the microprocessor, as well as a signal level interface circuit each for the single detectors are inserted.

Description: Seed control apparatus with a microprocessor Technical f e d. The invention relates to an apparatus with a micro¬ processor for tiie control of seeders. T e apparatus contains photoelectric seed detectors, a device for measuring the path covered, display and operating organs, data and control busses, buffers, a power supply unit as well as a microprocessor system con¬ sisting of the interface circuits being inserted between the detector organs and the data bus. Background art Several solutions have "oeen developed for the control of seeding machines during operation, some of them are described in the publication "Heavy-duty seeding machines" CKarangozό L. and al., Agricultural Publishing House, Budapest, 1980. pages 154-161.). ' with these equipments fall through of the seeds is controlled by photocells or' by the aid of photo¬ electric means, while the electric pulses generated in this way are forwarded to a central unit. Recently seed control apparatus based on microprocessor BSTET TΈ ZHZEΎ control are available, e.g. the type H 216 of Hessel CG.FR). The "" aim of the known solutions has been to promote the precise performance of seeding techno¬ logies at the rows and stocks, simultaneously to enable seeding work at night. To fulfil the task set, the seed control apparatus has to deliver a series of information to the operator in course of the seed¬ ing process. In case of a failure, e.g. the clogging of the seed-pipe, the number of the seeds being less or more, than the ' prescribed quantity, the serial number of the defective furrow splitter, the effec¬ tive number of stocks and stock distance, in case of. a multiple failure the number of the defective furrow splitters are to be signalled visually and/or acoustically. In course of normal operation, the following informa¬ tions are needed by all means: the number of the seeds sown for each furrow splitter since starting the process, the effectively covered distance and the average number of seeds pro-hectare. In addition to these, the seed control apparatuses must be compatible with several types of seeding machines, .e. they could be adapted to different furrow splitter numbers and diverse diameters of the land wheels. In general, the seed control apparatuses are meeting the requirements enumerated above in such a manner that the parameters qualifying the performance of seeding technologies are controlled by counting the pulses coming from the photoelectric seed detectors and the signal transmitters measuring the distance covered, and in case of failures the occurence, the place and extent are signalled visually and/or acoustically. In the knovm apparatuses the usual SI f iO U __> components, i.e. the programmable counter circuits recommended by the manufacturers of the microprocessor are used for performing the counting functions. These counter circuits - contained in a house. - comprise one to three relatively high speed counter stages of 8 to 16 bits. Since with a seed control apparatus the pulses of a plurality of signal sources Cdetec¬ tors) are to be counted, the known solutions working with the usual components require a lot of circuit elements resulting in a voluminous apparatus. If in addition to this the electric characteristics of the signal sources are not even /uP-compa ible, due to the high number of the required interface circuits a further increase in the number of elements is to be reckoned with. When a task cannot be solved with a counter of usual capacity, i.e. 16 bits, further supplementary circuits are needed. It goes without saying that increase in volume and numbers of elements disadvantageously in¬ fluences investment costs and operational safety. Disclosure of invention The aim of the invention is to eliminate the above mentioned drawbacks and to develop a seed control apparatus which is able to realize the required func¬ tions with less components, accordingly with a lower cost expenditure with the simultaneous increase of operational safety. In accordance with the invention, the microprocessor is programmed in addition to the usual functions for counting operations, furtheron between the micro- processor system and the dececting organs a progra - able parallel inpu /output interface circuit for interfacing the output of the detecting organs to the microprocessor as well as for each of the detecting organs a signal level interface unit are inserted. A preferred embodiment of the invention contains signal level interface units which are formed as pulse shaping units, With a further preferred embodiment of the invention monostable lip-flops are applied as signal- level interfaces or pulse shaping units respectively. Brief Description of Drawings The invention will be described in details by means of a preferred embodiment, by the aid of the enclosed drawings, wherein: .Figure 1 is a block diagram showing a traditional counter interface inserted between the detectors and the microprocessor system, Figure 2 is a block diagram showing the interface circuit according to the invention, Figure 3 the time diagram of the pulse train output of a detector, Figure 4 is a block diagram showing the seed control apparatus containing the interface circuit according to the invention, Figure 5 shows schematically the connections between the seed control apparatus with the micro¬ processor according to the invention -and the seedin Όg machine. Best Llode of Carrying out the Invention The traditional counter interface circuit demonstrat- ted in figure 1 is processing, e . ' g * in case of a corn seeder with " eighteen furrow splitters, the output signals of the signal transmitters - not shown here - of eighteen seed detectors for the microprocessor system and contains 18 + 2 interface elements 1, 18 precounters 2 and 6 + 1 programmable counter inter¬ faces 3 comprising three 16-bit counter stages. The price of the totally seγeιι programmable counter inter¬ faces 3 represents a considerable proportion of the investment costs of the apparatus. At the same tine, the capacity of these expensive circuits, at least as regards to the counter frequency, is far not utilized, since the frequency of the output p bes of the seed detectors are generally of the order of magnitude of lo 100 Hz. Counting of the signals of a relatively low frequency can be solved far cheaper by using the data-memory of the microprocessor combined with a software—promoted cyclical sampling, if an information-receiving interface circuit accord- ing to the invention is applied which requires ele¬ ments in a minimal number and minimal volume, the block diagram of which is illustrated in Figure 2. V/ith this arrangement the output signals of the signal transmitters of the detectors - not illustrat- ed here - arrive via twenty-four signal level inter¬ face units 4 to the inputs of the programmable parallel interface circuit 5 » i.e. to the input/out¬ put pins thereof. This latter circuit alone is able to interface twenty-four input signals to the data bus 6 leading to the microprocessor not illustrated here. The microprocessor informs said interface circuit 5 via the control bus 7 which input 8 out of the twenty-four inputs should be enabled in a given moment. .Taeτi compared to the traditional solu- tion according to Figure 1, it becomes obvious that • y*- -.-. considerably less components are needed, in particular, when considering that the twenty-four signal level interface units 4 can be assembled of two inverters each, consequently, merely twelve IC Ce.g. of type CD 4011) containing≤>ur IT TD-gates or eight IC contain¬ ing inverters Ce.g. of typeCD 4009) are required. Accordingly, by using the circuit shown in Figure 2, one programmable interface IC 3 Ce.g. HϊTΞL 8255) enables the input of sixteen to twenty-four signals. In case, when the detectors are delivering too narrow pulses, it seems to be expedient to design the signal level interface units 4 so that they should be sui¬ table for pulse shaping when operated e.g. in a mono- stable mode of operation. In order to ensure that all the pulses, arriving from a detecting organs be counted, the time constant t m of the onostable circuit, i.e. the increased pulse width should surpass the original pulse width t., J but should be shorter, than the half of the period of repetition T, at the same time, the periodical time of sampling T should be shorter, ' than t . These correlations are shown in Figure 3 . wherein T - the minimal periodical time of the signal to be processed, t .= the original width of the signalling pulse, J t •= the period of the signal, increased by the mono- flop circuit, T m = periodical time of sampling. The instruction execution time being characteristic for the microprocessor, the number of the signal transmitters and detectors, the magnitude, number OMPI SUBSTITUTE SHE CT " and time requirement of the task set for the micro¬ processor are restricting the period of s-ampling to be obtained by interrupts and thus the highest fre¬ quency of the signal to be received. One of the embodiments of the seed control apparatus containing the interface circuit according to the invention is based on a microprocessor and the belong¬ ing program and data memories fitting into the system, together with the programmable parallel interfaces with the programmable 22 + 24 lines, the display and operating organs. The block diagram of the apparatus is shown in Figure 4, while Figure 5 illustrates the connection thereof with the seeder. As mentioned above, Figure 4 shows the block diagram of the seed control apparatus 9« As shown, the signals coming from the seed detectors Cnot illustrated here) arrive at the signal level interface unit 4 » the in- puts 8 of which are connected. to the programmable parallel interface circuit 5. The interface unit 21 for the output measuring the rotation of the land wheel, as well as the interface unit 22 detecting the elevated position of the seeding machine are also connected to the interface circuit 5. The interface circuit 5 is connected to the micro- ^ processor 10 via the data bus 6 and the control bus 7, the microprocessor contains the program memory 11 and the data memory 12. The address bus 13 forwards the addresses required for the operation of the -program memory 11 and the data memory 12, respecti¬ vely. The parallel interface 14 is also connected to the SUBSTITUTE SHfr'iT f OMPI microprocessor 10, via the busses mentioned above, and displays 15 and the operating organs 16 are connected thereto. At last, Figure 5 shows the block diagram of the completely assembled seeding machine system. The seed control apparatus 9 itself is arranged on the trailer 17 and it is connected via the collecting cable 18, the connecting cable 19 and the connectors 20 to the interf cecircuits 5 belonging to the single groups of furrow splitters; the interface circuits are further¬ more connected to the signal level interface units 4 of the seed detectors C∑Lot illustrated here), to the interface units 21 measuring the distance covered and the matching units 22 sensing the elevated position. The apparatus according to the invention solves in an economical manner the processing of the pulse train of a frequency of max. 50 Hs, arriving from the seed detectors of the seeder with eighteen furrow splitters and of further six informations, it performs the shift of the eighteen decimal counters each with six charac¬ ters and two characters, respectively, simultaneously delivering various informations requiring relatively complicated arithmetic routines. Sum irizing the advantageous features of the appara¬ tus according to the invention it can be stated that in comparison with the known solutions, by usin oon- siderably less components, with a decreased volume •and reduced costs higher operational safety could be obtained. In addition to these advantages, the embodi¬ ment herein described yields a surplus service, in so far as not only clogging of the seeding-pipe, but also the percentage of the deviation from the prescribed distance are signalled. . -^ EAT^ OMPI IP0

Claims: C L A I S " - 1. Seed control apparatus with a microprocessor con¬ taining photoelectric seed detectors, devices for measuring the path covered, display and operating organs, buffer memories, a power supply unit, as well as a microprocessor system consisting of the microprocessor, the program and data memories, furtheron of the interface circuit being connect- ed between the detecting organs and the data bus, c h a r a c t e r i z e d in that in addition to the usual functions the microprocessor C ) is programmed for couting operations too, furtheron hety/een the microprocessor system and the detect- ing organs a programmable parallel input/output interface circuit C5) interfacing the outputs of the detecting organs to the data bus C6) of the microprocessor C ) and for each detector a signal level interface unit C4) are inserted. 2. Seed control apparatus as claimed in claim 1, c h a r a c t e r i z e d in that the signal level interface units C4) are formed as pulse shaper units. 3. Seed control apparatus as claimed in claim 2, c h a r a c t e r i z e d in that said signal level interface resp. pulse shaper units are mono- stable circuits. SUBSTITUTE SKEΞT

Inventors: BALINT SANDOR, NAGY LASZLO, VEROK ANTAL, BALINT, SANDOR, NAGY, LASZLO, VEROK, ANTAL
Applicants: MEZOEGAZ TERMELOESZOEVET, "OKTOBER 6" MEZOEGAZDASAGI TERMELOESZOEVETKEZET
Application year: 1982
Main classification: G06F15
IPC codes: A01C7, G06F19