A SEMICONDUCTOR DEVICE

Abstract: A semiconductor memory having a structure where­ in each of data lines (D₀) intersecting word lines (W i ) is divided into a plurality of sub lines in its length­ wise direction, memory cells (MC) are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines (I/O) are arranged in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements (SW), and the switching elements are connected to a decoder (Y) through control lines (YC) and are selec­ tively driven by control signals ( y ) generated from the decoder.

Description: The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory device which has a high packaging density and which is advantageous for attaining a fast operation as well as a high S/N (signal-to-noise) ratio. In semiconductor memory devices, as the packaging density is increased in order to increase its storage capacity, the capacity of a charge storage portion in each memory cell decreases. In addition, the area of the memory array on a memory chip increases, and the capacitance of a data line, and the length thereof, both increase. Accordingly, it becomes increasingly difficult to attain the features of both fast operation and high S/N ratio. In order to obtain a large-capacity memory of fast operation and high S/N ratio, various arrangements have been proposed. An example will be described in connection with a MOS dynamic memory which is constructed of memory cells each including one transistor and one capacitor. In the example shown in Figure 1 of the accompanying drawings, two memory arrays MA1 and MA2 are arranged on both the sides of a Y decoder Y DEC and have sense amplifiers SA arranged on the outer sides thereof. When a memory cell MC connected to a data line D O is selected by an X decoder X DEC, a dummy cell DC connected to a data line D₀ adjoining the data line D O is selected, the difference between the potentials of the data lines D O and D₀ as based on the difference of the capacitances of both the cells is amplified by the sense amplifier SA, and reading is effected through common input/output lines I/O and I/O . In this manner the pair of data lines which are differentially read out are arranged adjacent to one another, to form the so-called folded data line arrangement. Therefore, the example has the merit that noise attributed to the electrical unbalance of the data lines is negligible. However, when the area of the memory array becomes large as a result of an increase in the storage capacity, the capacitance of the data line increases, so that the read-out voltage decreases. When, in this regard, the data line is shortened by increasing the number of divided memory arrays into, e.g. four memory arrays or eight memory arrays, it is possible to increase the read-out voltage and to raise the writing speed. Since, however, one Y decoder needs to be provided for every two memory arrays and one set of common input/output lines are one sense amplifier needs to be provided for every memory array, these peripheral circuits necessitate a large area being provided which is disadvantageous. A semiconductor memory is disclosed in United States Specification No. 4,056,811. It specifically relates to random access memories. The memory cells in a row are divided into sub-rows and an access transistor is used to selectively isolate or connect the output terminals of each sub-row of the memory cells to the row line. The capacitive loading of the output signal from the memory cells is reduced when the data stored therein is recalled. Each row of memory cells is divided into contiguous sub-rows, and a sub-row data conductor is associated with each sub-row of memory cells. Memory cells in the same column are connected to a common word line. Access devices are provided, each of which is connected to the corresponding sub-row conductor, so that all access devices in the same row can be controlled by a single line. The access devices in the same row connect the sublines to a common row conductor. Thus, when the data stored in a memory cell has to be recalled, which cell is in a particular sub-row, the access devices belonging to the other sub-row remain turned off, so that only the output terminals of the memory cells in said particular sub-row are connected to the common row line. For a memory array of a given size, the advantage of dividing each row of memory cells into sub-rows rather than decreasing the number of memory cells per row and increasing the number of rows in the array, is that the former requires less semiconductor surfaces area per stored bit than does the latter. Because each row line requires a separate sense amplifier, and row line decoder, while each column line requires only a column line decoder, a configuration which has a decreased number of memory cells per row and an increased number of rows would require more area for the support circuitry. Another semiconductor memory device is disclosed in US-A-436559 and DE-A-2919166. The memory device comprises a plurality of pairs of digit lines, a plurality of sense amplifiers, each having a pair of input terminals, a plurality of pairs of gating means and a plurality of memory cells. In this construction, respective pairs of input terminals of the sense amplifier are operatively coupled through respective pairs of gating means to respective pairs of digit lines, whereby a load chapcitance of a digit line is reduced in order to increase the detection sensitivity and thus provide high speed operation. The present invention seeks to provide a semiconductor memory having large storage capacity without a substantial increase in the area needed for the peripheral circuits, and which is capable of fast writing and fast reading and which exhibits a high S/N ratio and a high reliability. According to the present invention there is provided: a memory device including: (a) a plurality of sub-arrays (MA, MA', - -) each having a plurality of word lines (W), a plurality of data lines (D) which extend in a direction intersecting with said plurality of word lines and a plurality of memory cells (MC); each said memory cell (MC) being located at the point of intersection between a word line (W) and one of a pair (D₀₀,;D₀₀; D₀₀', D₀₀' - -) of said data lines, and includes a capacitor (Cs) for storing a signal, and a transistor (Q) to connecct the capacitor (Cs) to a corresponding data line (D), the data lines being formed in a folded data line structure to be coupled to said memory cells (MC); and the pairs of data lines being provided with differential signals, respectively arranged in proximity to each other in parallel and connected to respective differential amplifiers (SA), each differential amplifier being arranged in common to two pairs of data lines and located between the corresponding memory sub-arrays; (b) a plurality of common lines (I/O(0), I/O(1), - -) each of the common lines being arranged in common with at least two pairs of corresponding data lines (D) two of said plurality of common lines corresponding to said pairs of data lines forming a pair of common lines (I/O, I/O(0),....); (c) a plurality of means (SW, GC, GC') for connecting said two pairs of corresponding data lines (D) to said common lines; (d) a plurality of control lines (YC) each of which controls at least a corresponding one of said connecting means (SW) to control the connection of said data lines to said common lines; (e) a first decoder for selecting at least one of said plurality of word lines (W); and (f) a second decoder for controlling the selection of rows of pairs of data lines by the control lines (YC); wherein: (i) each of the common lines (I/O(0), I/O(1), ...) is located between the corresponding memory sub-arrays; (ii) each of said connecting means (SW, GC, GC') connects two pairs of corresponding data lines to a corresponding common line, each connecting means (SW,GC, GC') comprising means provided in common for two pairs of corresponding divided data lines belonging to different sub-arrays for selectively connecting one pair of both pairs of data lines to a corresponding common line; (iii) at least four of said sub-arrays (MA, MA', - -) are arranged on one side of said second decoder, and are arranged in the direction of said control lines (YC), said first and second decoder being arranged along two mutually perpendicular sides of said combination of at least four of said sub arrays; (iv) there is driver means comprised with said second decoders for driving the control lines (YC); (v) said connecting means (SW) comprises a first switching means (GC, GC') for selecting one pair of the corresponding pairs of data lines for correction to the differential amplifier based on an applied first signal on a first control line, and a second switching means (SW), for connecting a pair of data lines selected by said first switching means to a corresponding common line based on a signal on a corresponding control line; (vi) each said differential amplifier (SA) includes means for differentially amplifying two signals on two the selected pair of said data lines which two data lines are selected by two respectively corresponding first switching means (GC, GC') wherein two of said first switching means coupled to two of said four data lines are supplied in common with said first signal, with said two of said first switching means coupled to the other two of said four data lines being supplied in common with a signal complementary to said first signal when either two or said four data lines are selected; and (vii) said memory device further comprises a plurality of precharge circuits (PC, Fig. 5) for pre-charging said two pairs of data lines. In accordance with such constructions, the sub lines onto which the data of the memory cells are once read out can have their capacitances reduced owing to the division in the lengthwise direction, so that a reading operation of high speed and high gain is permitted. In addition, even when the number of divisions is increased one decoder for addressing in the digit direction (Y decoder) suffices, so that substantially no increase in the area occupied by the peripheral circuits results. In accordance with this construction, either the control lines or the common input/output lines need to be laid in the same direction as that of the divided data lines and across the memory array. However, since such wiring can be provided in a multi-level fashion by forming it as a layer different from that of the data lines (sub lines), the area occupied by the memory array is not substantially increased. The present invention will now be described in greater detail by way of example with reference to the remaining figures of the accompanying drawings, wherein:- Figure 2 is a circuit diagram illustrating the structure of a memory array which is common to several embodiments of the present invention; Figure 3 is a detailed circuit diagram of a first preferred form of memory array in a semiconductor memory; Figures 4A, 4B and 4C are a plan view, an equivalent circuit diagram and a sectional view of a memory cell of the memory array shown in Figure 3; Figure 5 is a circuit diagram showing a part of the memory array shown in Figure 3 in greater detail; Figure 6 is a waveform diagram illustrating the operation showing operations in the circuit shown in Figure 5; Figures 7 and 8 are respectively a circuit diagram showing a part of the circuit shown in Figure 5 in greater detail and a waveform diagram illustrating the operation thereof; Figure 9 is a plan view of a chip for the memory array shown in Figure 3; Figure 10 is a plan view showing another chip; and Figures 11 to 24 are circuit diagrams and waveform diagrams showing other embodiments and illustrating the operation thereof. Figure 2 conceptually shows a structure which is common to several embodiments of the present invention. In a memory wherein word lines W and data lines D ij are arranged into a matrix to form a memory array, each data line is divided into, e.g. D₀₀, D₀₁, D₀₂ and D₀₃ as shown in the figure. In parts of the respective divided data lines, there are arranged switches SW₀₀, SW₀₁, SW₀₂ and SW₀₃ which are controlled by an output control signal YC₀ provided from a circuit block 20 including a Y decoder and a Y driver. Data are exchanged through these switches between the respective data lines and common input/output lines I/O(0), I/O(1), I/0(2) and I/O(3) which are common to other divided data lines (for example D₁₀). As a result, data are written into or read out from memory cells MC by a read/write controller 30. With such a construction, the data lines are divided, so that a read-out signal of high output voltage is obtained from the memory cell MC to the data line D₀₀ at high speed by a word selection voltage which is delivered to the selected word line W from a circuit block 10 including an X decoder and a word driver. Moreover, with this construction, no substantial increase in the chip area resulting from the division occurs. The reason is that the circuit block 20 does not have to be duplicated for each divided memory array, so that it is sufficient to provide only one circuit block 20 common to the sub data lines. In the construction shown in Figure 2, when lines YC are formed by a manufacturing step different from that of the lines D ij , multi-level wiring becomes possible, and hence, the area of the memory array does not increase. By way of example, it is considered that the word lines W are formed of polycrystalline Si or a metal such as Mo, that the principal parts of the data lines are formed of a first layer of Al, and that the control lines YC are formed of a second layer of Al. It is also considered to form the word lines W out of a first layer of Al, the principal parts of the data lines D ij out of a polycrystalline Si or diffused layer, and the control lines YC out of a second layer of Al. Figure 3 shows a preferred form of memory array as applied to a semiconductor memory having a folded data line arrangement. A data line forming each row is divided into, e.g. D OO , D OO ', D₀₁ and D₀₁'. The pair of data lines D₀₀ and D₀₀ are connected to a sense amplifier SA through a switching circuit GC. The pair of data lines D₀₀' and D₀₀' are connected to the sense amplifier SA through a switching circuit GC'. Accordingly, the sense amplifier SA is arranged in common to the data pair lines D ij , D ij and the other data pair lines D ij ', D ij ' . A single control line YC₀ is arranged in correspondence with data lines D₀₀, D₀₀', D₀₁, D₀₁' ...aligned in one row and data lines D₀₀ , D₀₀' , D₀₁ , D₀₁' ... paired therewith. Control lines YC₃, YC₄, YC₇ etc. are respectively arranged in correspondence with other data pair lines. Word lines (only one word line W i being illustrated in Figure 3) intersecting the data lines are selectively driven by a circuit block 10 which includes an X decoder and a word driver. Only one of the switching circuits GC and GC' is driven by a control signal Ø GC or Ø GC ' from the circuit block 10. The information of only one of the memory cells connected with the data lines D₀₀, D₀₀', D₀₀ and D₀₀' is transmitted to one end of the sense amplifier SA. The information of a dummy cell, not shown, is transmitted to the other end of the sense amplifier SA. Signals are similarly transmitted to other sense amplifiers, and each sense amplifier differentially amplifies the transmitted signals. All outputs from the sense amplifiers arrayed in the first column are associated with a common input/output line I/O(0). Among these sense amplifiers, only one selected by the circuit block 20 through any of the control lines YC₀, YC₃, YC₄, YC₇ etc. has its output applied to the common input/output line I/O(0) and then transmitted to a read/write controller 30. Likewise, the outputs of the sense amplifiers arrayed in the other columns are transmitted to selected common input/output lines I/O(1) etc. The read/write controller 30 is controlled by an address signal A and a write/read control signal WE, and provides a data output D out corresponding to the potential of the desired one of the common input/output lines. A writing operation is similarly performed in such a way that a data input D i supplied from outside the chip is applied to the selected common input/output line and then to the selected memory cell. Referring now to Figures 4A, 4B and 4C as seen from the equivalent circuit diagram of Figure 4B, the plan view of Figure 4A shows only the portion of two memory cells which are respectively connected to the paired data lines D₀ and D₀ . The part enclosed with a dot-and-dash line indicates a first layer of polycrystalline silicon POLY I to which a supply voltage V CC is applied. In the part POLY I, hatched areas are parts which are formed on a silicon diode layer thinner than in the other part, and storage capacitances C S are formed by the hatched parts and a silicon substrate. The word lines W O and W₁ are formed of a second layer of polycrystalline silicon, and parts of them form the gates of MOS transistors. These layers are overlaid with a phosphosilicate glass layer PSG, on which the data lines D₀ and D₀ indicated by broken lines and formed of a first layer of aluminium are formed. A contact area CH is provided for the connection between the aluminium layer and an n⁺-type diffused layer in the silicon substrate. The first layer of aluminium is overlaid with an inter-layer insulating film, on which the control line YC made of a second layer of aluminium is formed. As shown in Figure 4A, the control line YC which is laid between the pair of data lines D₀ and D₀ should desirably be arranged in the middle of these data lines. The reason is that when the control line YC is located nearer to either data line, the data lines D₀ and D₀ come to have unequal capacitances with respect to the control line YC, which gives rise to the generation of noise in the differential reading of signals on the data lines D₀ and D₀ . Figure 5 shows the sense amplifier SA in greater detail and the proximate circuits which have been omitted from Figure 3. The data lines D₀ and D₀ are connected to nodes CD O and CD O through the switching circuit GC. The data lines D₀' and D₀' are also connected to the nodes CD₀ and CD₀ through the switching circuit GC'. The nodes CD₀ and CD₀ have a precharging circuit PC, the dummy cell DC and a switching circuit SW connected thereto in addition to the sense amplifier SA. The operation of the above embodiment will be described in greater detail with reference to the waveforms shown in Figure 6. First, all of the nodes (D₀, D₀ , CD₀, CD₀ , D₀', D₀' etc.) are precharged to a high potential by a precharge signal Ø p , whereupon the word line W is selected by a word pulse Ø W provided from the X decoder. Then, all the memory cells connected to the word line are selected. By way of example, a minute signal voltage which is determined by the storage capacitance C S of the memory cell MC and the capacitance of the data line D₀ is delievered to this data line D₀ corresponding to the memory cell MC. At the same time, a reference voltage is delivered from the dummy cell DC to the node CD₀ by turning "on" a pulse Ø DW . Before the word line is selected, the switching circuit GC' connected to the data line to which the memory cell to be selected does not belong is turned "off" in such a way that a control signal Ø GC ' is brought from the high level at the precharging into a low level. In contrast, the switching circuit GC remains "on". Accordingly, signal voltages corresponding to an information from the memory cell MC appear at D₀ and CD₀, and the reference voltage from the dummy cell DC appears at D₀ and CD₀ . Since the capacitance of the dummy cell DC is selected to be one half that of the storage capacitance C S of the memory cell MC, the reference voltage is set to be intermediate between the read-out voltages which appear at D₀ and CD₀ in correspondence with the information "1" and "0" of the memory cell MC. At the input terminals of the sense amplifier SA, therefore, minute fluctuating voltages corresponding to the information "1" and "0" appear at all times. Thereafter, the sense amplifier SA is operated by a start pulse Ø a so as to amplify the differential voltages. Thereafter, a control signal Ø y is delivered to the control line YC selected by the Y decoder Y DEC, and the amplified differential voltages are differentially applied onto the pair of common input/output lines I/O and I/O via the switch SW. Important features of the above described circuit arrangement are:- (a) that the common input/output lines are located between the memory arrays MA and MA' not on one side of each memory array, so the reading and writing operations can be performed fast, and (b) that since the precharging circuit PC and the dummy cell DC are made common to the two memory arrays MA and MA' the required area decreases accordingly. Of course, these circuits can be arranged for the respective memory arrays MA and MA' as in the prior art without being made common. In Figure 6, the supply voltage V CC = 5 volts by way of example, and the signals Ø P , Ø GC and Ø GC ' are set at 7.5 volts in order to apply a sufficiently high voltage so that the data lines D₀ and D₀ may be precharged with equal voltages. The signals Ø W and Ø DW are set at 7.5 volts in order to make the read-out voltage from the memory cell high by boosting the word line to 7.5 volts with a capacitor. The signal Ø y is set at 7.5 volts in order to raise the mutual conductances g m of the MOS transistors within the switching circuit SW so that the signals may be delivered from the nodes CD₀ to CD₀ to the common input/output lines I/O and I/O at high speed. That portion in the circuit block 20 which produces the control signal Ø y boosted to 7.5 volts with respect to the supply voltage V CC of 5 volts is illustrated in Figure 7, whilst waveforms in various parts of the portion are shown in Figure 8. When the Y decoder Y DEC precharged to the supply voltage V CC by the signal Ø P has been selected, decoding MOS transistors remain in the "off" states, and a node N remains at the high level, so that a MOS transistor Q D holds the "on" state. Under this condition, a pulse Ø y ' indicative of the timing of the generation of the control signal Ø y is provided and applied to the control line YC through the MOS transistor Q D . A boosting signal Ø B is subsequently applied through a capacitance C B , whereby the voltage of the control line YC is boosted to produce a waveform as shown by the signal Ø y . MOS transistors Q₁ and Q₂ constitute a circuit which keeps the control line YC connected to earth potential with a low impedance when this control line is non-selected, in order to prevent the potential of the non-selected control line from rising due to any unnecessary coupled voltage. Referring now to Figure 9, the chip is in the shape of an elongated rectangle so that it may be readily received in a standard DIP (Dual In-Line Package). The direction of the divided data lines D₀₀, D₀₀' etc. agrees with the lengthwise direction of the chip. The circuit block 10 including the X decoder is arranged centrally of the chip, and on both the sides thereof, the memory arrays MA₀, MA₀', MA₁, MA₁' etc. divided by the division of the data lines are arranged in alignment. The circuit blocks 20 including the Y decoders are each arranged on one side of the alignment of the memory arrays. The control circuits 31 and 32 are arranged in the remaining parts. The control lines YC are laid from the circuit blocks 20 including the Y decoders, so as to extend across the memory cells. In the case where the spacing between the adjacent control lines has room as in embodiments to be described later, different wiring lines from the control circuits 31 and 32 can be formed of the same layer as that of the control lines YC as illustrated in Figure 10. Referring now to a modified embodiment shown in Figure 11, it should be noted from what has been said previously that the control line YC is preferably arranged in the middle of the data lines D₀ and D₀ in order to avoid the difference of the capacitances of these data lines. In this regard, however, the control line YC and the data lines D₀, D₀ are formed of different layers. Therefore, the misregistration of masks involved in manufacturing steps incurs unequal capacitances of the lines D₀ and D₀ , which form a noise source. As shown in Figure 11, therefore, the control lines YC are formed so as to intersect over the middle parts of the divided data lines D₀ etc. According to such a construction, even when the mask misregistration has occurred in the manufacturing steps, both the data lines D₀ and D₀ can have equal capacitances of (C₀+C₁). It is possible to realize various other structures in which even in the presence of the mask misregistration, no difference occurs between the capacitances of the paired data lines as described above. Figure 12 shows an example in which the data line D₀ and D₀ intersect each other in their middle parts. In any of the foregoing embodiments, one control line is arranged in correspondence with the paired data lines. In order to reduce the number of control lines, a construction in which one control line is arranged for two pairs of data lines is also realisable. Figure 13 shows the general circuit arrangement of such an embodiment, whilst Figure 14 shows an embodiment in the case where the switching circuits GC and GC' as shown in Figure 3 are jointly used. Figure 15 shows an embodiment in which the portion of the switching circuit SW in the embodiment shown in Figure 5 is modified. The modified switching circuit SW' is controlled by the control line YC and a control line IOC extending from the X decoder 10. Since only the switching circuit SW' existing at the intersection point of the selected lines X and Y turns "on", outputs can be selectively delivered to the lines I/O(O), I/O(1) etc. in Figure 3. This signifies that the lines I/O(O), I/O(1) etc. can be decoded in advance. Therefore, a simplified circuit can be adopted for the read/write controller 30. Figure 16 shows an example in which, by expanding the idea of the embodiment shown in Figure 15, the control line YC is arranged in correspondence with two pairs of data lines, not each pair of data lines. Thus, the number of wired control lines YC becomes half, that is, the wiring pitch is twice as great as the previous embodiments, so that the manufacture is facilitated. In operation, the switching circuit SW₀ or SW₁ turns "on" only when the signal from the control line IOC(O) or IOC(1) and the signal from the control line YC have coincided. However the embodiment shown in Figure 16, differs from the embodiment shown in Figure 15 in that the signal of the control line IOC(O) or IOC(1) includes an information of a Y-system address signal besides that of an X-system address signal. That is, when the pair of the data lines D₀ and D₀ is selected, the line IOC(O) is selected by the X(Y) decoder 10', and when the pair of the data lines D₁ and D₁ is selected, the line IOC(1) is selected (usually a signal "1" is provided). Needless to say, the above referred to X- and Y-system address signals simply signify X and Y in the arrangement of two-dimensional points in a plane, and they should be discriminated from the logic addresses of the memory. Whilst the control line YC is arranged in correspondence with the two pairs of data lines, it is needless to say that each control line YC can be arranged in correspondence with any desired number of pairs of data lines. Figure 17 shows another embodiment in which the wiring pitch of the lines YC is enlarged, for example, twice as great as in the case of Figure 16. Two sets of I/O lines are provided, and the lines I/O-O and I/O-O are connected to the lines CD o and CD₀ and the lines I/O-1 and I/O-1 to the lines CD₁ and CD₁ by a switching circuit SW'', respectively, so as to exchange signals with the exterior. The two sets of I/O lines have either selected and connected with the line D i or D out by the read/write controller 30 shown in Figure 2. Alternatively, it is possible to provide a plurality of lines D i or D out and to directly connect the I/O lines therewith without performing the selecting operation. With the present embodiment, as in the embodiment of Figure 16, the wiring pitch of the control lines YC can be enlarged thus facilitating the manufacture. Whilst the embodiments thus far described are based on the structure of Figure 3, it is obvious that the X and Y decoders can be arranged in proximity as shown in Figure 18. In the embodiment shown in Figure 5, the Y decoder 20 is replaced with an X and Y decoder 20'. The X and Y decoder 20' carries out the operation (A) of an X decoder and the operation (B) of a Y decoder in divided time zones. The coincidence between a pulse Ø xy and a pulse Ø x or Ø y is taken by a gate circuit WD or Yd so as to form the output of the word line W or the control line YC. The gate circuits WD and YD are similar in arrangement to the circuit shown in Figure 7. Therefore, they are not described in detail. In Figure 18, the circuit block 10 shown in the right-hand part of the drawing does not include the function of the Y decoder. This is based on the assumption that the number of decoders required for driving the control lines YC is within the number of decoders located in the left-hand part of the drawing, and the same function as that of the left decoders is sometimes given to the right decoders 10. In the case where the juxtaposition of the gate circuits WD and YD is difficult in relation to the occupying area, the gate circuit YD can be designed in a manner to be distributed among a plurality of decoder portions. Whereas the above described embodiments are directed to the memory of the folded data line arrangement, an embodiment shown in Figure 20 is directed to a memory of the open data line arrangement. Also in this embodiment each data line is divided into a plurality of sub lines in the lengthwise direction. This arrangement is different from the embodiment shown in Figure 3 in that the paired data lines D₀ and D₀ are arranged rectilinearly. In the embodiment of Figure 3, polycrystalline silicon being a wiring material of comparatively high resistivity is used for the word lines and the word line delay time therefore poses a problem, so that in order to make the time as short as possible, the word lines are divided to arrange the circuit block 10, including the X decoder and driver, in the central position of the divided lines as illustrated in Figure 3. In contrast, in the embodiment shown in Figure 20, she word lines are formed of Al exhibiting a low resistivity, so that the word lines need not be divided and that the circuit block 10 is arranged at one end. Thus, one driver may be located on one side, and hence, the area of the circuit block 10 can be made small. Figure 21 shows an embodiment which is applied to a MOS static memory. When compared with the embodiments of the MOS dynamic memory shown in detail in Figure 5, the embodiment of Figure 21 differs in the structure of the memory cell MC and also differs in that the auxiliary circuits such as the sense amplifiers are not required for the respective pairs of data lines. The paired data lines D o , D₀ , the common input/output lines I/O, I/O , the control line YC, the switching circuit GC, etc. may be constructed similarly to those shown in Figure 5, and are not described in detail. Figure 22 shows the construction of an embodiment in which the sense of the common input/output line common to a plurality of divided data lines is different from that shown in the previous embodiments. That is, the common input/output line I/O(O) which is common to the divided data lines D₀₀, D₀₁, D₀₂ and D₀₃ is arranged in parallel with these data lines. Figure 23 illustrates an embodiment to which the structure of Figure 22 is applied. A sense amplifier SA₁ of a first stage is connected to the paired divided data lines D₀₀ and D₀₀ . Sense amplifiers of the first stage are respectively connected to the other paired divided data lines. Paired common input/output lines I/O(O) and I/O(O) are arranged in correspondence with the data lines forming a row, and are connected to a sense amplifier SA₂ of a second stage. Paired common input/output lines I/O(1) and I/O(1) and similarly arranged in correspondence with data lines of another row, and are connected to a sense amplifier of the second stage. Outputs from the sense amplifiers of the first stage arrayed in a first column are connected to the respectively corresponding common input/output lines through switches which are controlled by a control line YC₀ located in a direction intersecting the common input/output lines. Outputs from the sense amplifiers arrayed in the other columns are similarly connected to the corresponding common input/output lines through switches which are respectively controlled by control lines YC₁, YC₂ and YC₃. These control lines are selectively driven by the circuit block 20 including the Y decoder. The selection in the digit direction is performed on the output side of the sense amplifiers of the second stage by the Y decoder. Also in this embodiment, the information of the memory cell MC is once read out onto the divided data line, and it is amplified by the sense amplifier of the first stage and then delivered to the common input/output line. Therefore, even when the charge storage capacity of the memory cell is small, the information can be read out with a sufficient margin. Since the selective drive of the control lines YC₀, YC₁, YC₂ and YC₃ serves to effect the selection in the word direction, it may well be performed by the circuit block 10 including the X decoder. Figure 24 shows another embodiment to which the construction of Figure 22 is applied. The difference between the embodiment shown in this Figure from the embodiment shown in Figure 23 is that the paired common input/output lines I/O(O) and I/O(O) are arranged in common to two pairs of data line columns. Also control lines for controlling the switching circuits pair as IOC₀ and IOC₁, or IOC₂ and IOC₃, and by driving either, one of the two pairs of data line columns is selected. Also the sense amplifiers SA₁ of the first stage is arranged in common to the data line pair D₀₀, D₀₀ and the data line pair D₀₁, D₀₁ , either of which is selected by the switching circuit which is controlled by control signals Ø GC and Ø GC ' from the circuit block 10 including the X decoder.

Claims: A semiconductor memory device including: (a) a plurality of sub-arrays (MA, MA', - -) each having a plurality of word lines (W), a plurality of data lines (D) which extend in a direction intersecting with said plurality of word lines and a plurality of memory cells (MC); each said memory cell (MC) being located at the point of intersection between a word line (W) and one of a pair ( D₀₀ ,;D₀₀; D₀₀', D₀₀ ' - -) of said data lines, and includes a capacitor (Cs) for storing a signal, and a transistor (Q) to connect the capacitor (Cs) to a corresponding data line (D), the data lines being formed in a folded data line structure to be coupled to said memory cells (MC); and the pairs of data lines being provided with differential signals, respectively arranged in proximity to each other in parallel and connected to respective differential amplifiers (SA), each differential amplifier being arranged in common to two pairs of data lines and located between the corresponding memory sub-arrays; (b) a plurality of common lines (I/O(0), I/O(1), - -) each of the common lines being arranged in common with at least two pairs of corresponding data lines (D) two of said plurality of common lines corresponding to said pairs of data lines forming a pair of common lines (I/O(0) I/O (1),....); (c) a plurality of means (SW, GC, GC') for connecting said two pairs of corresponding data lines (D) to said common lines; (d) a plurality of control lines (YC) each of which controls at least a corresponding one of said connecting means (SW) to control the connection of said data lines to said common lines; (e) a first decoder (10) for selecting at least one of said plurality of word lines (W); and (f) a second decoder (20) for controlling the selection of rows of pairs of data lines by the control lines (YC); characterised in that: (i) each of the common lines (I/O(0), I/O(1), ...) is located between the corresponding memory sub-arrays; (ii) each of said connecting means (SW, GC, GC') connects two pairs of corresponding data lines to a corresponding common line, each connecting means (SW,GC, GC') comprising means provided in common for two pairs of corresponding divided data lines belonging to different sub-arrays for selectively connecting one pair of both pairs of data lines to a corresponding common line; (iii) at least four of said sub-arrays (MA, MA', - -) are arranged on one side of said second decoder (20), and are arranged in the direction of said control lines (YC), said first and second decoders (10,20) being arranged along two mutually perpendicular sides of said combination of at least four of said sub-arrays; (iv) there is driver means comprised with said second decoders (20) for driving the control lines (YC); (v) said connecting means (SW) comprises a first switching means (GC, GC') for selecting one pair of the corresponding pairs of data lines for connection to the differential amplifier based on an applied first signal (Ø GC ) on a first control line, and a second switching means (SW), for connecting a pair of data lines selected by said first switching means to a corresponding common line based on a signal (Ø Y ) on a corresponding control line (YC); (vi) each said differential amplifier (SA) includes means for differentially amplifying two signals on the selected pair of said data lines which two data lines are selected by two respectively corresponding first switching means (GC, GC') wherein two of said first switching means coupled to two of said four data lines are supplied in common with said first signal, with said two of said first switching means coupled to the other two of said four data lines being supplied in common with, a signal complementary to said first signal when either two of said four data lines are selected; and (vii) said memory device further comprises a plurality of precharge circuits (PC, Fig. 5) for pre-charging said two pairs of data lines. A memory device according to claim 1 wherein said plurality of control lines (YC) are arranged in parallel with said plurality of pairs of data lines. A memory device according to claim 2, wherein principle parts of said plurality of control lines (YC) are formed of a layer different from that of principal parts of said data lines. A memory device according to claim 1, wherein said data lines and said control lines (YC) are both formed of aluminium. A memory device according to claim 2, wherein said control lines (YC) intersect said data lines over the middle parts of said data lines. A memory device according to claim 1, wherein said second decoder (20) comprises a pull-down circuit (Q₁,Q₂) for holding non-selected control lines at a low impedance potential. A memory device according to claim 1 further comprising a plurality of dummy cells (DC) each provided in common for two data lines for providing a reference voltage to one of said two data lines which is selected by said first switching means (GC, GC'), one of said first switching means being coupled to one of said two data lines and is supplied with said first signal, and one of said first switching means being coupled to the other of said two data lines and is supplied with a complementary signal to said first signal. A memory device according to claim 1, wherein a plurality of sub-arrays (MA) constituted by said word line (WL), data lines (D) and memory cells (MC) are formed on one chip, and each of said plurality of control lines (YC) is arranged through at least one of said sub-arrays. A memory device according to any one of the preceding claims wherein said second decoder (20) comprises a pull down circuit (Q₁,Q₂) for holding non-selected control lines at a predetermined low impedance potential. A semiconductor memory according to any one of the preceding claims, in which the majority of said control lines (YC) are arranged in a layer different from that of said data lines. A semiconductor memory according to any one of the preceding claims wherein said pair of said data lines are arranged in such a manner as to be substantially parallel and to cross one another in at least one portion. A semiconductor memory according to any one of the preceding claims wherein said second decoder (20) has driver means for respectively driving the selected lines. A semiconductor memory according to any one of the preceding claims wherein two of said data lines together constitute a pair of folded bit structure and said common signal lines are also arranged in pairs. A semiconductor memory according to any one of the preceding claims, wherein said second decoder (20) has means (Q₁, Q₂) acting to fix the non-selected control lines to a non-selection potential. A semiconductor memory according to any one of the preceding claims, wherein means for generating a reference voltage is provided for each of said data lines. A semiconductor memory according to any one of the preceding claims wherein the plurality of precharge circuits (PC,Fig.5) are each provided in common for said two pairs of data lines. A semiconductor memory according to any one of the preceding claims wherein said plurality of data lines and plurality of common lines are arranged parallel to each other. A semiconductor memory according to any one of the claims 1 to 16 wherein said plurality of data lines and plurality of common lines are arranged perpendicular to each other. A semiconductor memory according to any one of the preceding claims wherein said plurality of control lines (YC) are arranged parallel to the direction of the long side of the chip (31). A semiconductor memory according to any one of the preceding claims wherein said plurality of control lines (YC) are arranged in the middle of said pair of plurality of data lines.

Inventors: HORI, RYOICHI, ITOH, KIYOO
Applicants: HITACHI, LTD.
Application year: 1982
Main classification: G11C5
IPC codes: H01L27, H01L21, G11C11, G11C5