CHIP ALIGNMENT METHOD

Abstract: Relative displacement between a chip formed on a semiconductor wafer and a means for exposing the same is carried out. An alignment mark is provided for every chip at a position near the chip. The alignment mark ofthe next chip to be exposed is read while the prior chip is being exposed. The relative displacement between the semiconductor wafer and the means for exposing the same is carried out in response to the deviation between the alignment mark of the next chip and that of the prior chip, so that the next chip is aligned at a predetermined postion.

Description: CHIP ALIGNMENT METHOD The present invention relates to a chip alignment method, more particularly to a chip alignment method which can be suitably applied to a microprojection-type exposing apparatus. The conventional chip alignment method used in a microprojection-type exposing apparatus is as follows. Prior to chip alignment, a pair of alignment marks provided in advance on the wafer, upon which the chip is to be formed, is read out by a microscope. The position determined by these alignment marks is used as the "origin" for positioning of the chips. These marks allow a precise relationship to be maintained between the origin and the means for exposing the wafer. The distance between the origin and the chip is known in advance. Moving the XY stage, upon which the wafer is mounted, under the control of a laser interferometer enables the chip to be positioned precisely with respect to the exposure means. in this method, however, mechanical accuracy, xY orthogonality, heat expansion, and warp of the wafer combine to affect alignment accuracy, whereby reduced accuracy cannot be avoided. Also, since alignment accuracy is maintained independent of the operation of the exposure means, much time is required for alignment. The time required for alignment hinders the increase of the processing capacity of the exposure apparatus. To increase alignment accuracy, even, more time is required for alignment. This further impedes improvement of said processing capacity. An object of the present invention is to provide a chip alignment method which can eliminate the above -mentioned drawbacks. Another object of the present invention is to provide a chip alignment method which can decrease the time of the al igranent. A further object of the invention is to provide a chip alignment method which can improve the processing capacity of micro-projection type exposing apparatus. The objects of the present invention can be achieved by an alignment method for sequentially aligning each of a plurality of chips formed on a wafer to a predetermined position with respect to a means for exposing said plurality of chips comprising the steps of: providing an alignment mark for each of said plurality of chips on said wafer, reading the alignment mark provided for one of siad plurality of chips and detecting an amount of displacement of said wafer while a chip which is exposed prior to said one of said plurality of chips is exposed by said means, moving said wafer according to said amount of displacement; thereby said one of said plurality of chips is aligned to the predetermined position. Further features and advantages of the present invention will be apparent from the ensuing description with reference to the accompanying drawings to which, however, the scope of the invention is in no way limited. BRIEF DESCRIPTION OF THE DRAWING Figure 1 illustrates the construction of the apparatus to which the chip alignment method according to the present invention is used; Fig. 2 illustrates an enlarged view of the chips shown in Fig 1; Fig. 3 illustrates an enlarged view of the wafer shown in Fig. 1; Fig. 4 illustrates a detailed construction of the photo receiver shown in 1; Fig. 5 illustrates a block diagram which shows the operation of the apparatus shown in Fig. 1; and Figs. 6A and 6B illustrate plan views of the relation between the chips and the alignment marks for the chips. In Fig. 1, which shows the construction of the apparatus, XY stage 1 mounts a wafer 2 thereon. Alignment marks 3 are placed on the wafer 2, upon which chips 21 are also formed. Reference numeral 4 denotes a wafer alignment scope, S a contraction lens, 6 a reticle, 7 a condenser lens, and 8 mercury lamp, as s m lar to conventonal apparatuses. The characteristic feature of the present invention is to provide an optical system which includes a light source 9, a half-mirror 10, mirrors 11, 12a, 12b, 13, a half-mirror 14, and photo-receivers 15a and l5b. An alignment mark 20a or 20b (Fig. 2) is provided for each chip 21. Each chip is formed on wafer 2 mounted on the XY stage (Fig. 3). According to the present invention, the alignment marks 20a, 20b are provided near each chip, for example, on a slicing line, prior to the alignment process. The number of the alignment marks is not limited. Referring to Fig. 1, light emitted from the light source is split into two portions by half-mirrors 10 and 12. The split light is projected, via through holes 6a, 6b provided on the reticle 6 and via the contraction lens 5, on to the alignment marks 20a and 20b (see also Fig. 2). The light reflect from the alignment marks 20a, 20b pass through lenses 12a, 12b and then 13, 14, respectively, to produce images in the photo-receivers 15a, 15b as shown in Fig. 4. The photo-receivers 15a, 15b show the relation between the images of the alignment marks and photo-receiver elements a to d and a' to d'. The four element diode (SGD-444-4) produced by EG & G Co. of the U.S. can, for example, be used as the photo-receiver shown in Fig. 4. Referring to Fig. 5, the outputs of the photo-receivers 15a and 15b are converted into digital values by the analog-to-digital (A/D) converters 22a to 22d and 23a to 23d. The converted digital values are supplied to a computer 24. In the computer 24r compensation values x and y are calculated by the following equations: x = asb+a'+b-(c+d+c'+d') y = a+d+a'+d'-(b+c+b'+c') The calculated compensation values x, y are supplied to X (Y) stage controller 25. x (Y) stage controller 25 is also supplied with the output of an interferometer 17 (Fig. 5), which reads, a pair of plane mirrors 16a and 16b (Fig. 1). The compensation values calculated in the computer 24 and the reference values stored in the computer 24 are supplied to a calculator 31. The calculator 31 calculates the total displacement values and supplies said values to a switch control circuit 32. The switch control circuit 32 distributes the output of the clock pulse generator 33 so as to form the time-velocity (voltage) curve at the output of an up-down counter 34. The time-velocity curve is formed by a velocity increasing portion I, constant velocity portion II, and a velocity decreasing portion III, III t . In Fig. 5, the velocity decreasing portion III denotes a reference voltage curve and the velocity decreasing portion III' denotes the actually shifted voltage curve which should be compensated for. The output of the up-down counter 34 is converted to an analog value by a digital-to-analog (D/A) converter 35. The output of the D/A converter 35 is further converted to a frequency by the voltage- to- -'requency (V/F) converter 36. The output of the V/F converter 36 is compared with the output of the interferometer 17. The deviation of the frequency is calculated by the deviation counter 37. The output of the deviation counter 37 is converted to an analog value by a D/A converter 38. The output of the D/A converter 35 is compared with the output of the DIA converter 38. The positional information of the motor and the error compornent is applied via an error amplifier 41 and a power amplifier 43 to the motor 44. Next, the chip alignment method according to the present invention will be explained. The wafer 2 is mounted on the XY stage 1 and is aligned by the wafer alignment scope 4. Next, interferometer 17 is actuated. The first chip on the wafer 2 is positioned under the exposure means. At this time, the detecting system gives positional information of the alignment mark of the first chip. This positional information is used in the x (Y) stage controller 25 to position the first chip with respect to alignment mark 20a. After the first chip is properly positioned, the exposure means is actuated and the first chip is exposed. A relatively long time required for this exposure. The region where this exposure is carried out includes the alignment mark 20b of the next chip to be exposed. Therefore, while the first chip is being exposed, the detecting system reads the alignment mark 20b of the next chip to be exposed. This positional information is supplied to computer 24. Computer 24 checks for deviation relating to the positional information read from the alignment mark 20b. When no deviation exists, XY stage 1 is next displaced by a one chip unit, without compensation by the stage controller 25, in response to an output signal of interferometer 17. #hen deviation does exist, this deviation is taken into consideration as the compensation amount in stage controller 25. In such case, xY stage 1 is next displaced by a one chip unit plus or minus the compensation amount. For example, in Fig. 6A or 6B, if the alignment mark deviates as shown by the dotted line, the compensation amount is subtracted from the one chip unit displacement. Figure 6A shows a correctly positioned chip 21a currently being exposed and an incorrectly positioned chip 21b to be exposed next, chip 21b is at the position 21lob. Therefore, the displacement amounts x, y of XY stage 1 should be: x = Q + dx y = dyl Figure 6B shows an incorrectly positional chip 21a currently being exposed and a correctly positioned chip 21b to be exposed next Chip 21a is at the position 21fa. Therefore, the displacement amounts x, y of XY stage 1 should be: x = t + dx2 y = dy2 Thus, the compensation amount for the next chip to be exposed is determined during the previous chip and is. reflected in the displacement distance of XY stage 1 for said next chip to be exposed. Therefore, no time is necessary for chip alignment, whereby the processing capacity of the exposing apparatus can be improved. Further, alignment compensation is carried out for every chip, so that alignment error does not accumulate. Thus, no time is necessary for improving alignment accuracy. Therefore, the processing capacity of the exposing apparatus also can be improved on this point. The above-mentioned compensation of alignment error for each chip improves alignment accuracy. When the exposure of the chip reaches the end of the line by doing above-mentioned compensation process, the first chip of the next line should be aligned by the alignment mark provided for the first chip of the next line. The XY stage 1 is thereby displaced to move said first chip of the next line directly under the exposure means by a compensated amount, thereby allowing the above-mentioned process to be repeated for all chips on the wafer. While the above-mentioned explanation was made for the case where the detecting system for the alignment marks is provided as part of the exposing system, it should be understood that the detecting system can be separate. As clear from the above-mentioned explanation, in accordance with the present invention, the following effects can be obtained: (1) No time is necessary for chip alignment at all. (2) The processing capacity of the exposing system can be improved. (3) Alignment accuracy can be improved.

Claims: CLAIMS 1. A chip alignment method for sequentially aligning each of a plurality of chips formed on a wafer to a predetermined position with respect to a means for exposing said plurality of chips, comprising the steps of: providing an alignment mark for each of said plurality of chips on said wafer, reading the alignment mark provided for one of said plurality of chips and detecting an amount of displacement of said wafer while a chip which is exposed prior to said one of said plurality of chips is exposed by said neans, and moving siad wafer according to said amount of displacement; thereby said one of said plurality of chips is aligned -to the predetermined position; 2. A chip alignment method according to claim 1, wherein said plurality of chips comprises a first chip and a second chip which is exposed next to said first chip, and the alignment mark provided for said second chip is read while said first chip is exposed.

Inventors: IIJIMA, NOBUO, ONO, YOSHINOBU, WATANABE, YOSHIO
Applicants: FUJITSU LIMITED
Application year: 1982
Main classification: G01B11
IPC codes: H01L21, G03F9