TABLE LOOK-UP OF NON-LINEAR FUNCTIONS USING REDUCED-SIZED ROM

Abstract: A digital memory (10) which contains digital data words representative of a desired symmetrical transfer characteristic of a digital signal processor. Digital signals which are to be processed are applied to the address inputs of the memory (10), producing output signals in conformance with the desired transfer characteristic. Advantage is taken of the symmetrical nature of the response characteristic to minimize the size of the memory. Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory (10), and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit. In a preferred embodiment of the invention, the memory (10) is a random access memory, with stored data values being altered in response to a user control to change the transfer characteristic of the processor.

Description: TABLE LOOK-UP OF NON-LINEAR FUNCTIONS USING REDUCED-SIZED ROM The present invention relates to digital calculation using a digital memory, such as a read-only memory (ROM) for table look-up of non-linear functions of variables and, more particularly, to the reduction of the size of the memory required for given number of places of resolution in the looked-up function. An example of such digital calculation occurs in the calculation of the angular coordinate in a scan conversion from Cartesian to polar coordinates, as may be done for addressing television graphic display memory organized to be addressed in polar coordinates. The Cartesian coordinates x and y are directed from left to right and from top to bottom of screen, respectively, in the left-hand coordinate system customarily employed by- television engineers; and it is convenient to choose the origin at the center of screen supposing the display memory is to cover the entire television screen. In any case, for the purposes of convenient scan conversion, the • origins of the Cartesian-coordinate and polar-coord ' inate systems should preferably coincide at a point in image space. Radial polar coordinate r is measured outward from this point, and angular polar coordinate 9 is measured turning about this point counterclockwise from positive half of x axis, in keeping with the use of left-hand coordinates. The angular coordinate θ could be looked up from ROM responsive to x and y. Supposing the display to comprise 512 lines with 512 picture elements (or "pixels", for short) per line, then a quadrant of 9 could be looked up from ROM using eight bits of x and eight bits of y as input. About fourteen bits of output are required to define 9 with the resolution found b experiment to be required for extracting graphic images from display memory addressed in polar coordinates. The nine most significant bits of this angular coordinate are xiseά together with eight bits of radial coordinate as input to a ROM storing u a graphic image that fills the display screen, and five next most significant bits of this angular coordinate are used in two-dimensional interpolation betv/een video samples from spatially adjacent locations in the ROM to avoid visible discontinuities in edges of the graphic image as it appears on the display screen. About sixty-four ROM's of the conventional size with eleven-bit inputs and eight- bit outputs would be required for such direct lcok-up of 9. The angular coordinate 9 could be calculated by first dividing y and x and then using a ROM to look up tan ~ ^-(y/x). Several division . calculations must be carried on simultaneously to supply results at pixel scan rate unless one divides using ROM, which would require a ROM the size of that to look up directly from x and y. The size of the ROM required to look up tan~l(y/x) has to be large enough to define y/x with enough bits to resolve the difference between 1/255 and 1/254 at one end of its range and between 254 and 255 at the other end of its range. This must require " in excess of nine bits of input to memory, eight bits being required to define possible y values divided by x of unity and another bit to define their reciprocals, which values y/x would define the boundaries of quadrant defined by the lines x=255 and y=255 with the same resolution as pixels are defined on the display screen. Additional resolution in input, to arc tangent taole look-up ROM is certainly required to avoid spatial quantization effects at edges of the graphic image displayed on screen because some of the values of y/x will fall between those associated with those points on the boundary lines x=255, y=255. Substantial still further resolution in input to arc tangent table look-up ROM is required because the non-linearity of the arc tangent function with respect to its argument is very marked as the argument beccr.es large. Manyfold increase in y/x causes only gradual increase in tan-1(y/x) . so excessive capability to resolve in this region reduces the number of bits available in v/x to resolve its arc tangent when (y/x) is small, and the number of bits of (y/x) to resolve -θ adequately throughout c the range of y/x must be increased. The inventors have found that substantially less ROM is required if one looks up 9 in ROM responsive to log2 (y/x) input as the tan ~ - * -{ nti-log [log2 (y/x) ]) . This is because 9 is more linear respective to log29 (y/x) -. Q than to y/x, so that adequate resolution in 9 can be obtained through the full range of log y/x with fewer bits than through the full range of y/x. More generally, if one has to look up a monotonically non-linear function of a variable from ROM, - j _5 the number of bits required in the ROM input to adequately resolve the function across its whole range can be reduced if the variable is expressed in logarithmic terms. Where the monotonically non-linear function gro * .-7S ■progressively more rapidly as the variable increases, then 2 Q the more common form of logarithm, which increases as argument increases, is used. Where the monotonically non-linear function grows progressively less rapidly as the variable increases a form of logarithm which decreases as argument increases (e.g. , as originally described by 2 Napier) can be used. This approach is particularly useful where the variable used as input to the RGM is the result of a calculation more easily carried forward in the logarithmic domain than in the linear domain. Digital division, such Q as that of y by x, is an example of such calculation. This can be done by subtracting the logarithm of x as obtained by table look-up from ROM from the logarithm of y as obtained by table look-up from ROM, which table look-ups can be performed sequentially from the same ROM. 5 Or this can be done by adding the logarithm of as obtained by table look-up from a ROM responsive to y input and the logarithm of 1/x as obtained by table look-up from a ROM responsive to x input. Types of calculation, besides digital division, thar are more easily carried forward in the logarithmic domain than in the arithmetic include digital multiplication, certain power-taking and root-taking processes, and combinations of these operations. A general aspect of the invention concerns the looking up of a non-linear function of a first variable from ROM not being done directly using the first variable as input to the ROM. Rather, responsive to said first variable, a second variable is generated (either from ROM or by calculation) to be applied to the ROM. This second variable is dependent from said first variable in such a way that responsive to change in the first variable the rate of change of said second variable approximates the rate of change in said non-linear function of said first variable. Fewer bits of resolution in the ROM input are required, using the second variable rather than the first variable as input, in order to describe the non-linear function with no more than a given level of quantization error. That is, while fewer points in the function are stored in ROM, their spacing in terms of first variable is better insofar as the magnitude of possible quantizing error arising from sampling with so few points. So then, too, where interpolation betv/een ROM outputs is used to allow reduction of the number of points in the function to be stored in ROM, linear interpolation between ROM outputs in terms of second variable input is more accurate than would be linear interpolation in terms of the fixst variable. In accordance with -a further aspect of the present invention, a digital memory is provided which contains digital data words representative of the desired transfer characteristic of the signal processor. Digital signals which are to be processed are applied to the address inputs of the memory, producing cutpur signals in conformance with the desired transfer characteristic. Advantage is taken of the symmetrical nature of the transfer characteristic to reduce the size of the emorv. Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory, and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit. In the Drawings: FIGURE 1 is a block diagram of a television display system for displaying an image taken from memory and rotated through a programmable angle in which apparatus the invention finds use; FIGURE 2 is a sketch useful in understanding the forms taken by the Cartesian coordinates ^ describing the rotatable image prior to its rotation; FIGURE 3 is a block diagram of scan generator and scan converter circuitry used for addressing a memory storing information organized according to polar coordinates, which scan converter embodies the invention; FIGURE 4 is a schematic diagram of a digital signal processor constructed in accordance with the principles of the present invention; FIGURES 5 and 6 are -data tables used to explain the embodiments of FIGURES 3 and 4; FIGURE 7 is a block diagram of a modification that can be made to the FIGURE 3 scan converter; and FIGURE 8 is a block diagram of a memory system useful in connection with the FIGURE 1 apparatus. In FIGURE 1 display memory 10 stores information read out at video rates to the inpμt of digital-to-analog converter (DAC) 11 to be converted to video for application to a video amplifier 12, the output of which drives the electron gun of a cathode ray tube (CRT) 13. CRT .13 has a screen 14 raster-scanned by the electron beam emanating from its electron gun. The raster-scanning is -ypically accomplished using horizontal and vertical deflection coils 15 and 16 supplying sawtooth currents from horizontal and vertical sweep generators 17 and 18, respectively. It is customary to use resonant circuits including the deflection coils in these generators and to synchronize the sweeps with horizontal and vertical synchronizing pulses supplied by timing control circuitry 19. Circuitry 19 generally includes frequency-dividing circuitry for generating these synchronizing pulses at rates subharmonic to master clock signals provided from a master clock 20, which customarily comprises a crystal oscillator which operates at the pixel scan rate or a multiple thereof. Memory 10 is addressed during its readout by the integral portions of radial and angular coordinates R and θ, respectively, supplied as output from a scan converter 21 responsive to x and y coordinates supplied to it as input from a scan generator 22. Scan generator 22 generates a sub-raster — i.e., a raster scanning of x and y addresses which may or may not be co-extensive- with the raster scanning of the display screen by electron beam. These x and y coordinates are generated by scan generator 22 at pixel scan rate during each line scan of CRT 13 screen 14 in the trace direction, as timed from timing control circuitry 19. Scan converter 21 is programmable as to the degree of rotation (expressed as angle φ) of the image to be read out of display memory 10. This angle φ is added to the angular ψ coordinates descriptive of unrotated image to obtain the angular 9 coordinates descriptive of rotated graphic image. That is, in the system being described tan-l(y/x) defines Ψ , rather than , with 9 being defined as equalling ψ plus the angle φ by which the image is rotated betv/een memory 10 and its display on screen 14 of CRT 13. The angle φ may, for example, be calculated by a microprocessor 23, responsive to data received or interchanged with display control circuitry 24. The display control circuitry 24 might, for example, comprise the gyroscopic compass, synchros and synchro-to-digital converters in a horizontal situation indicator svstem for aircraft cock it use. MicroDrocesscr 23 may also use radial coordinate r output from scan converter 21 in its calculations where concentric images are to be rotated in differing degrees. FIGURE 2 is useful in understanding how to define the x and y coordinates of electron beam trace position to implement scan conversion. Point 30 is the arbitrarily chosen center of rotation for the image to be retrieved from memory 10. This center of rotation 30 is the center of a dashed-line circle 31 of arbitrary radius within the perimeter of which the image will always repose, whether rotated or not. It is convenient to choose this radius to be 2 n' pixels, where n is an integer. Circle 31 is inscribed in a square 32 with sides 32a, 32b, 32c, and 32d which defines that portion of the raster-scan to be transformed from x, y coordinates to the r, 9 coordinates used for addressing memory 10. The scan conversion calculations are considerably simplified by choosing the center of rotation 30 as the origin for the x, y coordinate system. However, the point at which it is best. to begin to carry forward the scan conversion process is the first point to be scanned in square 32—i.e. the upper left-hand corner 33, presuming the use of conventional CRT raster-scan with the relatively slow line-by-line scan from top to bottom in the trace direction and with the relatively fast pixel-by- pixel scan from left to right in the trace direction. This facilitates the changing of the rotation of the graphic image taken from memory 10 as it is presented on display screen 14 of CRT 13 without introducing disruption in the image as displayed. The rotation of the image as a Gestalt becomes possible simply by adding a different angle φ of programmable rotation to the angular coordinate developed by scan converter 21, performing this addition during times between successive raster scannings of the portion of image space occupied by the graphic image stored in memory 10. It is desirable to avoid insofar as possible straightforward digital multiplication in the scan conversion process, and the alternative of us some accumulation process processing at pixel-by-pixel rate in conversion of x and at line-by-line rate (where the display is not interlaced) in conversion of y may occur to the digital system designer. Beginning scan conversion at other than the x, y origin poses a problem of how to establish the initial conditions for accumulation. In part, this problem arises in as much as the origin is the only point that is scan- converted without being affected by the angle φ through which the image is rotated. Another aspect of the problem is that the origin in both coordinate systems is remote from point 33, so at least one of its coordinates tends to have nearly maximum value. Usually accumulation processes are carried forward from zero, however, so that the large numbers are gradually accumulated, this tending towards simplifying the arithmetic to a single addition or so. FIGURE * 3 shows a particular sub-raster scan generator 40 for generating x and y scan coordinates. The rest of the apparatus in the figure is a scan converter for converting these Cartesian coordinates to polar form for addressing memory 10 addressed in polar coordinates. E.g. , memory 10 is addressed by column using the integral portions (int 9) of the angular coordinate (9) and by row using the integral portions (int r) of the radial coordinate (r) . It is convenient to have the scan generator generate x and y coordinates in two's complement form. The y coordinate of scan is generated using an n-bit counter 41 and a set-reset flip-flop 42; their combined outputs provide the y coordinate in two's complement form, its most significant bit being provided by the Q output of flip-flop 42 and its less significant bits by counter 41 output. The output of counter 41 is reset to "ZERO" and the Q output of flip-flop 42 is set to "ONE" by a SLOW-PRR INITIALIZATION pulse generated in timing control circuitry 10 at the time when the raster- scanning of the display screen brings the electron beam trace to position 33 (described in connection with FIGURE 2). ("PRR" is the abbreviation for "pulse repetition rate.") The count in counter 41 is incremented by a LINE-SCAN-RATE CLOCK pulse furnished to it by timing control circuitry 19 following each time the electron beam trace crosses side 32d of square 32 in FIGURE 2, and occurring before the trace crosses side 32b on the ensuing line of display screen raster-scan. When the electron beam scan has crossed side 32d of square 32 on the electron-beam-trace scan line just prior to that, which sweeps through center of rotation 30, the n-bit counter 41 will have counted 2 n scan lines and have reached full count of 2 n -l . The next LINE-SCAN-RATE CLOCK pulse input will cause the counter 41 output to change from n parallel bits each .i_.ei.ng a ONE to n parallel bits each being a ZERO and to reset flip-flop 42. When being reset, flip-flop 42 toggles -from a ONE to a ZERO at ' its Q output; and its Q output remains a "ZERO" for the remainder of the scanning of square 32. The x coordinate of scan is generated using a n-bit counter 43 and a set-reset flip-flop 44; their combined outputs provide the x coordinate in two's complement form, its most significant•bit being provided by the Q output of flip-flop 44 and its less significant bits, by counter 43 output. The output of counter 43 is reset to a ZERO and the Q output of flip-flop 44 is set to a ONE by a FAST-PRR INITIALIZATION pulse generated by timing control circuitry 19 at the time when the raster- scanning of the display screen brings the electron beam to any point on side 32b of square _32 (described in connection with FIGURE 2) . The count in counter 43 is incremented at video rate by a PIXΞL-SCAN-RATΞ CLOCK pulse furnished from timing control circuitry 19. Khen • the electron beam has reached a distance from side 32b one pixel shorter than that center of rotation 30 is from side 32b, the n bit counter 43 will have counted 2 n pixels and have reached full count of 2 n -l. The next PIXΞL-SCAN- RATE CLOCK pulse input will cause the counter 43 output to change from n parallel bits each being a ONE to n parallel bits each being a ZERO and to set flip flop 44 with its overflow bit. The Q output from flip flop 44 toggles from a ONE to a ZERO and remains a ZERO for the remainder of the scan to side 32d of square 32. The types of circuitry that can be used in timing control circuitry 19 for generating the LINE-SCAN- RATΞ CLOCK, SLOW-PRR INITIALIZATION, PIXΞL-SCAN-RATE CLOCK and FAST-PRR INITIALIZATION pulses are familiar to the video system designer. The PIXEL-SCAN-RATE CLOCK and LINE-SCAN- ATE CLOCK pulses are normally generated by frequency-dividing counters v/hich count MASTER CLOCK pulses—although it is possible (particularly in systems with monochromatic display) that the master clock 20 supplies output pulses at pixel scan rate, which may be applied without frequency division to counter 43 as input for counting. The SLOW-PRR INITIALIZATION pulse may be generated using a counter to count e.lectron-beam-trace scan lines since field retrace and then using a digital comparator to compare the output of that counter to a programmed line count for obtaining indications of when the edge 32a of square 32 has-been reached by the electron beam trace; and the FAST PRR INITIALIZATION pulse may be generated using a counter to count pixels since line retrace and then using a digital comparator to compare the output of that counter to a programmed pixel count for obtaining indications of when the edge 32b of square 32 has been reached by the electron beam trace. These counters are normally extant in the frequency divider circuitry used in the generation of horizontal and vertical synchronizing pulses for the horizontal and vertical sweep generator 17, 18. In the special case where the perimeters of the display screen and of square 32 coincide, the SLOW-PRR and FAST-PRR INITIALIZATION pulses may be provided by the vertical and horizontal synchronization pulses, respectively, with the PIXΞL-SCΛN- RATE and LINE-SCAN RATE CLOCK pulses being supplied as gated clocks, with clock pulses furnished only during trace and not during 5 retrace. In this special case the counters used in the scan generator may also be employed in the counting used in frequency division of the master clock pulse repetition rate to control the timing of horizontal and vertical synchronization pulses for sweep generators 17 and 18. ,ø In other cases, where the square 32 is entirely within the confines of the screen, gated clocks may be used where clock pulses are provided only so long as the electron beam trace is within square 32. Allowing square ■ 32 to be only partially on screen will require measures to 15 prevent the portion of the display that is supposed to be off-screen — i.e., beyond an edge of the screen — from appearing on screen extending from the opposite edge of screen. This blanking is most straightforwardly carried out by selectively enabling the reading of memory 10 0 depending on whether the evenness or oddness of the counts in counters 41 and 43 correspond or do not correspond to those of counts from the frequency-dividing counters in timing control circuitry 19, which are used to time horizontal and vertical synchronization pulses. While 5 field interlace is not normally used in digitally generated graphic video displays, where it is used, the LINE-SCAN- RATE CLOCK to counter 41 can comprise 'pulse doublets, each doublet occurring once per line scan interval to cause counter 41 to increment by two each time it counts 0 rather than by one. Provision is then also made to apply an additional LINE-SCAN-RATE CLOCK pulse to counter 41 every other interval between field scans, to compensate for the one less line in alternate fields. Circuitry 50 converts the x and y coordinates to 5 the radial coordinate r of the polar coordinates used for addressing memory 10 supposing it to be of a type addressed in polar coordinates. The following formula is a conventional basic conversion formula used in circuitry 50. By a process that will be explained presently x 2+y2 is accumulated in a (2n÷l) -bit register 51 to provide an 2 r input to a read-only memory (ROM) 52. ROM 52 stores a square-root look-up table and responds to r" to provide the radial coordinate r. The accumulation of x 2 and y2 is based on the following specific expression of the binomial theorem, where z is the general expression for either variable, x or y. (z+1) 2 = z 2 +2z÷l (2) From this one can by the rules of ordinary algebra develop the following relationships. (x+1) 2 +y 2 = (x 2 +y 2 )÷(2x÷l) (3) x 2 +(y+l) 2 = (x 2 +y 2 )+(2y+l) (4) • The initial contents of r 2=x2+y2 register 51 should be twice 2 n or 2 (2n+I - ) - that is, the sum of x 2 and y 2 associated with point 33. This is arranged by resetting the (2n+l)-bit register 51 output responsive to the SLOW-PRR INITIALIZATION pulse to all ZERO'S, which represents an overflow count of 2 ( 2nτl) . Thereaf er, the two's complement output of ' register 51 is clocked out and added to the two's complemeni output of a multiplexer 53 responsive to each REGISTER CLOCK pulse provided from the output of an OR. ate 55 responsive to either a LINE-SCAN-RATE or PIXEL-SCAN-RATE CLOCK received at one of the inputs of gate 55; and the two's complement result is used to update the contents of register 51. Multiplexer 53 is arranged to select as its output, during times the register 51 is to be clocked with a REGISTER CLOCK pulse derived from a PIXEL-SCAN-RATΞ CLOCK pulse, its input corresponding to a (2x+l) term. This term comprises n more significant bits each * corresponding to the Q output bit of flip-flop 44, n less significant bits corresponding to the n-bit output of counter 43, and a least significant bit which is invariably a ONE. Multiplexex 53 is arranged to select as its output, during times the register 51 is to be clocked with a REGISTER CLOCK pulse derived from a LINE-SCAN-RATE CLOCK pulse, its input corresponding to a (2y+l) term. This term comprises n more significant bits each corresponding to the Q output bit of flip flop 42, n less significant bits corresponding to the n-bit output of counter 41, and a least significant bit which is invariably a ONE. The n more significant bits of these two's complement terms being all ZERO'S is indicative of their being positive. In such instances the n less significant bits correspond to the 2x portion of (2x+l) and to the 2y portion of (2y+l) ; and the least ' significant bits being ONE's add unity to 2x and 2y. The n more significant bits in these two' s complement terms being all ONE's, on the other hand, is indicative of their being negative. In such instances the remaining bits correspond to the complement of (2x+l) and to the complement of (2y+l) —i.e. those terms subtracted from 2 n . In the case where the perimeters of square 32 and the display coincide, the multiplexer 53 is controlled by pulses generated during horizontal retrace. Absent the pulses, counter 43 output is selected by multiplexer 53 as its output, otherwise counter 41 output is selected as its output. In other cases the multiplexer 53 can be controlled by the output of a flip-flop, set by alternate overflow bits from counter 43 to direct multiplexer 53 to select counter 41 output as its output, and reset by delayed LINE-SCAN-RATE CLOCK pulse to direct multiplexer 53 to select counter 43 output as its output. Circuitry 60 converts the x and y coordinates to an unrotated image angular coordinate ψ to which a programmable angle Φ of image rotation is added to generate the rotated-image angular coordinate 9 of the polar coordinates used for addressing memory 10, continuing to suppose it to be of a type addressed in polar coordinates. The most significant bit of ψ indicative of the half-plane the sample point of the unrotated image lies in is available directly from polarity-bit flip-flop 42 of scan generator 40. The second most significant bit of ψ, which together with the most significant bit of ψ indicates the quadrant in which φ lies, is generated at the output of an exclusive OR gate 68 to which the outputs of flip flops 42 and 44 of scan generator 40 are applied. The less significant bits of φ are, in essence, to be generated as the arc tangent of |y|/jx| . The quotient of |y|/|x| requires registers of extreme length to maintain sufficient accuracy in defining angles close to multiples of ιr/2, including zero and τr/2, inasmuch as |yj/|xj changes rapidly except around odd multiples of TΓ/4. A comparison of the range of [y|/|x[ values can be achieved, and division can be facilitated, by carrying forward the division " process using logarithms. To generate a good approximation for larger values of |y|, the two's complement, with most significant bit (MSB) suppressed, y output o counter 41 is applied as first inputs to a first battery 61 of exclusive OR gates each receiving the Q output of flip flop 42 (MSB) as their second inputs. The outputs of the battery 61 of exclusive OR gates is the approximation to |y| in ordinary binary numbers. The output from second battery 62 of exclusive OR gates provides a good approximation " for larger values of jx| analogously, in response to inputs taken from the output of counter 43 and the Q output (MSB) of flip-flop 44. Where memory 10 stores information at locations with r coordinates close to the origin r=o, the Q outputs of flip-flops 42 and 44 can be added to the outputs of batteries 61 and 62 of exclusive OR gates to obtain |y[ and |x[ exactly. A ROM 63 responds to the n-parallel-bit output of battery 61 of exclusive OR gates to supply its logarithm to the base two, and a ROM 64 responds to the n-parallel-bit output of battery 62 of exclusive OR gates to supply the logarithm to the base two of its reciprocal. These logarithms are summed in adder 65 to develop the logarithm of [y|/|x|, applied as input to a ROM 66 . ROM 66 supplies the arc tangent of the antilogarithm of its input to generate ψ= tan~l( {y[/[ | ) or its complement, depending on the display quadrant. A battery 69 of exclusive-OR gates responds to the quadrant indication from exclusive-OR gate 68 applied to their first inputs and to ROM 66 output applied to their second inputs to provide the polar • coordinate ψ of the unrotated image, φ is summed in adder 67 with the angle φ through which the image is to be rotated. This addition generates 9, the polar coordinate the integral portion of which is to be used in addressing memory 10, supposing its storage locations to contain the display image information in polar-coordinate organization. The use of the batteries of exclusive OR gates 61 and 62, which encode the x and y signals of counters 41 and 43 in accordance with the values of the most significant bits of the x and y signals provided by flip-flops 42 and 43, and the use of the battery of exclusive OR gates 69, which decode the output signals of cascaded ROMS 63, 64 and 66, provide a reduction i the sizes of the ROMS. • The arrangement of FIGURE 4 illustrates the principles of this reduction in memory size. In FIGURE 4, eight-bit input signals, corresponding to the x or y signal of FIGURE 3, are encoded by -exclusive OR gates 81 through 87, which correspond to battery of exclusive OR gates 61 or.62. A digital memory 80, corresponding to cascaded ROMS 63, 64 and 66 , is addressed by exclusive OR gates 81 through 87 to produce output signals which are decoded by exclusive OR gates 91 through 97. The exclusive OR gates 91 through 97 correspond to the battery of exclusive OR gates 69 of FIGURE 3. In the arrangement of FIGURE 4, the seven lower order bits 2 through 2 and (LS3) the least significant bit of an eiσht-bit input sicnal are applied to the ! respective inputs of the seven exclusive-OR gates 87 through 81. The MSB of the input signal is applied to second inputs of each of the seven exclusive-OR gates 87 through 81. The outputs of exclusive-OR gates 87 through 81 are coupled to the seven address inputs a fi -a n of a digital memory 80. The seven outputs b ( .-b r) of the memory 80 are coupled to respective inputs of exclusive-OR gates 97 through 91. The MSB of the input signal is applied to second inputs of exclusive-OR gates 97 through 91. The seven lower order output bits 2 6 through 21 and LSB of a processed output signal are produced at the outputs of exclusive-OR gates 97 through 91. In this embodiment, it may be necessary to delay the MSB between the input and the output of the system, to equalize the memory access time delay encountered by the lesser significant bits. The operation of the embodiment of FIGURE 4 is exemplified by the tables of FIGURES 5 and 6. These tables illustrate the principles of the processor of the present invention in terms of four-bit signals, which are equally applicable to the arrangements of FIGURES 3 and 4. In FIGURE 5, the table with the heading "Binary Data In" shows the binary words and their decimal equivalen for the dynamic range of a four-bit input signal. The dynamic range extends from a minimum value of 0000, decimal 0, to a maximum value of 1111, or decimal 15. The range is seen to exclude sixteen levels. The dashe box shown in the center table of FIGURE 5, labelled "Memory Address", contains the data stored in the memory for a linear, unity transfer characteristic. The memory contains eight addressable memory locations, indicated as L0 through L7. Three bits are stored at each address location. For a linear unity transfer characteristic, the digital data stored -in each memory location is the same as the digital address for that location; for example, when memory location L5 is addressed by the digital address word 101, the digital word produced by the memory is 101. For a unity transformation, the processed output signal values are the same as the input signal values. For instance, assume that the input signal to the processor has a value of 0101, or decimal 5. The MSB, 0, is exclusive-ORed with the lesser significant bits 1, 0, and 1, to produce the address for the memory. The exclusive— ORing of an MSB of 0 does not change the value of the address bits, which are 101. These address bits select location L5 of the memory, which produces output bits 101. These output bits are exclusive-ORed with the MS3 of 0 to produce the lesser significant bits of the output signal, in this example, 101. The MSB is passed directed to the output, forming the complete output word of 0101. Now assume that the input signal to the processor has a value in the upper half of the dynamic range, including decimal values 8-15. If the input signal has a value of 1101, which is decimal 13, for example, the MSB of 1 is exclusive-ORed with the lesser order bits 101. This exclusive-ORing produces an address of 010 for the memory, which addresses memory location L2. The data word stored in location L2, 010, is produced at the output of the memory. The 010 bits are exclusive-ORed with the MSB of 1 to produce the three_lower order bits of the output signal, in this case 101. The MSB is passed directly to the output, forming the complete output word of 1101. FIGURE 5 illustrates that the arrangements of FIGURES 3 and 4 will process an input signal over its full dynamic range for a symmetrical transfer characteristic with a memory having a capacity of 2N-1 (N-l) . For the example of FIGURE 5, N is equal to- four, and 2 N ~ 1 (N-l) is therefore equal to 8 (3)=24, as shown by the twenty-four bits enclosed in the dashed box. In FIGURE 4, where N=8 for eight-bit input and output signals, 2 N (N-l) is equal to 896, which is an improvement of required data storage as compared with the 2048 bits of memory required for eight-bit words without encoding and decoding. FIGURE 6 shows data tables similar to those of FIGURE 5, in that four-bit input signals are transformed into four-bit output signals with unity gain. The tables 5 of FIGURE 6 differ from those of FIGURE 5 because the input signals and the RAM data are in two's complement notation, as are x and y of FIGURE 3. The "Data In" table of FIGURE 6 comprises ascending positive and descending negative values from a median zero value. ,0 The two' s complement notation is advantageous in many cases because the location of zero at the center of the number system tends to minimize register over-anά under¬ flows as signals are combined and processed. For two's complement signals, data words corresponding to positive - j _5 signal values are stored in the memory as outlined by the dashed block. Negative decimal value words in -the lower half of the number system are converted by the exclusive-OR gates at the input and converted again at the output of the memory to make use of the stored data words over the 20 full signal range, as was the case for the upper half of the binary number range of FIGURE 5. It may be seen that the sequence of memory addressing illustrated in the "Memory Location" column of FIGURE 5 progresses in the sequence L0, L1...L6, L7 for 2 decimal input signal values of 0 through 7, then progresses in the reverse sequence, L7, L6...L1, L0 for decimal input signal values of 8 through 15. By inverting the MSB which is applied to the exclusive-OR gates in FIGURE 4, as indicated by broken line inverters 88 and 98, the sequence 0 of memory location addressing can be changed to L7, L6 ... LI, L0, L0, LI ... L6, L7 which is the same as the memory location sequence shown in the "Memory Location" column of FIGURE 6. The option of inverting the MSB at the inputs of the exclusive-OR gates permits the memory 80 to be 35 addressed in a complementary sequence over the dynamic range of the applied input signal. The same principle is applicable to the address and data tables of FIGURE 6. It is also possible to invert the transfer characteristic of the processor through selective inversion of the z-iSB which is ap lied to either the input or out ut exclusive-OR gates, while operating on the same data table stored in the memory. If the MSB is inverted from the input word to the output word, and if the MSB is applied to either the input exclusive-OR gates 81-87 or the output exclusive-OR gates 91-97 in inverted form, the result will be an inversion of the transfer response characteristic of the processor. This feature is applicable to use of the processor with either binary or offset two's complement signal forms. ROM's 63 and 64 of FIGURE 3 have * been constructed using two component ROM's of the conventional size with eleven-bit inputs and eight-bit outputs, responding to the nine bits of x and y respectively to provide sixteen- bit logarithms. ROM 66 has been constructed using four component ROM's of this size to respond to the twelve most significant bits of adder 65 output to provide 9 with sixteen bits resolution. So eight component ROM's of this size in addition to simple adder 65, suffice for calculation θ with sixteen-bi-t resolution, rather than sixty four ROM's of this size being needed as would be the case with table look-up of 9 directly from x and y. FIGURE 7 shows how ROM 66 of FIGURE 3 can be replaced by a ROM 71 which stores 0_<ψ_<(π/4) rather than 0_<ψ_<(.τr-/2) taking advantage of the following relationship for 0 p_ (τ. /2 ) . -1 tan [<V2)-ψ] = = [tan (ψ) ] This havles the number of inputs to the ROM for arc tangent look-up. Digital comparator 72 compares the n-parallel-bit output from battery 61 of exclusive OR gates to the n- parallel-bit output from battery 62 of exclusive OR gates to develop an output that is a ZERO for the former smaller than the later and is otherwise a ONE. This output and the output of exclusive OR gate 68 are applied as inputs to a further exclusive OR gate 78. The output of gate 78 is used as the third most significant bit of φ and so reduces by one the number of bits stored at each location in ROM 71 to preserve the accuracy provided by ROM 66. The output of comparator 72 also is applied as 5 control signal to multiplexors 73 and 74 and as first input to each of a battery 75 of exclusive OR gates . These exclusive OR gates receive as second inputs respective bits of the output from ROM 71, reproducing those bits as their outputs when their first inputs are Q ZERO and complementing those bits as their outputs when their first inputs are ONE. The output of comparator 72 being a ZERO directs multiplexors 73 and 74 to apply the outputs of batteries 61 and 62 of exclusive OR gates to ROM's 63' and 64', respectively; and battery 75 of 5 exclusive OR gates passes the ROM 71 output without complementing to furnish the less significant bits of ψ. The output of comparator 72 being a ONE directs multiplexors 73 and 74 to apply the outputs of batteries 61 and 62 of exclusive OR gates to ROM's 64' and 63', respectively; 0 and battery 75 of exclusive OR gates complements the ROM 71 output in its output to furnish the less significant bits of ψ. Variations of the circuit of FIGURES 3 or 7 are possible wherein ROM 64 or 64' is replaced by a ROM supplying the logarithm of y rather than the logarithm of its reciprocal, and wherein adder 65 is replaced by a subtractor circuit for linearly combining the output of ROM 63 or 63' with that of the ROM responsive to y. Still further variations are possible where the x and y outputs 0 of multiplexors 73 or 74 are alternately used as inpu€s to the same ROM used as a logarithm look-up table, with a subtractor combining the alternately supplied ROM outputs to develop input for the ROM 66 or 71 used to look up the arc tangent of the antilogarithm of (log 2 y - lcg 2 x) . The r and 9 coordinates generated by the scan - conversion techniques described above each comprise an "integral" portion or "modulus" - i.e., the more signficant bits of that coordinate which are used to address the memory - and a "fractional" portion or "residue" - i.e., the less significant bits of that coordinate which are not used to address the memory. While the residues frac r and frac 9 of these coordinates could be simply disregarded, it has 5 been found that using them to govern a two-dimensional interpolation between each four closely-grouped adjacent locations in memory can practically eradicate spatial quantization effects in the raster-scanned display. These undesirable effects, such as "staircasing" of slant lines, - JQ tend to arise because the sampled points of the stored image do not conformally map the centers of the display pixels. The two-dimensional linear interpolation can be done by successively polling each of the four adjacent 1 locations in memory for each pixel scanned in the display raster. Or the memory may be quadruplicated with the image shifted one coordinate step in one direction or the other or both in the three supplementary memories, with the four memories being read in parallel and their outputs 0 summed for each pixel scanned in the display raster. The first of these alternatives involves high video rates of operation. The second of these alternatives requires a four times increase in memory size. It was observed that this increase in memory size is just to store replicated 5 data with shifted addresses, which led to a search for a way to retrieve the four pieces of information for the two-dimensional linear interpolation in parallel from a memory not increased in size. FIGURE 8 shows the result of ' that search. 0 Memory 1-0 is subdivided into four portions 10a, 10b, 10c, and lOd. These portions are read out in parallel via a multiplexer 100 to simultaneously supply four bits of information in parallel to the two-dimensional linear interpolation circuitry 90. The least significant bits o: 5 the integral portions int r and int 9 of r and 9 control the multiplexer which accesses the memories depending on whether odd or even column address is at the left in the square arrangement of four adjacent locations in memory under consideration and on whether an odd or even row address is uppermost in the arrangement. For certain square arrangements such as those where the least 5 significant bits of int r and of int 9 are both a ZERO the submemories are addressed similarly in r and 9. For squares of four adjacent memory locations displaced one row? downward, the lowermost row should be at a row address one higher-than the uppermost row. This is ■ j o taken care of by row-addressing submemories 10a and 10b with the output of adder 181, which adds the least significant bit of the integral portion of the r coordinate to the more signficant bits of the integral portion of the r coordinate used directly to row-address submemories 10c 15 and lOd. For squares ' of four adjacent memory locations displaced one column to the right the rightmost column should be at a column address one higher than the leftmost column. This ' is taken care of by column-addressing 20 submemories 10a and 10c with the output of adder 182, which adds the least significant bit of the integral portion of the θ coordinate to the most significant bits of the integral portion of the 9 coordinate used directly to column-address submemories 10b and lOd. 2 As each pixel is raster-scanned the four adjacent locations in memory addressed at that time supply upper left, upper right, lower left, and lower right information for two-dimensional linear interpolation in interpolator circuitry 90. This interpolation can be 30 carried out as shown in FIGURE 8, for example. The lower- left point trace intensity information is subtracted from the lower-right trace intensity information in combining circuit 1 1; the difference is multiplied in digital multiplier 192 by the fractional residue of the 35 appropriate coordinate and added back to the lower-left trace intensity information in combining circuit 193 to obtain a first intermediate interpolation result. The upper-right and upper-left trace-intensity information are combined analogously to the lower-right and lower-left trace-intensity information using combining circuit digital multiplexer 195, and combining circuitry 96, to supply a second intermediate interpolation result from the output of combining circuit 196. This second inter¬ mediate interpolation result is subtracted from the first in combining circuit 97; and the resulting difference is multiplied in digital multiplier 98 by the residue of the other coordinate and added back to the second intermediate interpolation result in combining circuit 199 to obtain the final interpolation result supplied as input to digital-to-analog converter 11. One skilled in the art of digital system design and armed with the foregoing disclosure will be enabled to design many other embodiments of the invention -specified in the broader of the claims which follow this specification, and the scope of the invention defined by these claims should be accordingly broadly construed. For example, where there is no desire to carry forward calculations in the logarithmic domain prior to table look-up of a monotonically non-linear function of a first variable from ROM, it may be desirable to develop a second, dependent variable for addressing the ROM by calculation, as a root or power of the first variable. Or, as a r further example, the second variable may be log 2 ' of the first variable, where k is a constant. As a still further example, certain non-monotonically non-linear functions of a first variable may be taken as output from ROM responsive to second variable input , which second variable is a polynominal expression of powers of the first variable.

Claims: WHAT IS CLAIMED IS: 1. In a digital signal processing system, including a source of digital input signals of N-bit words, each having an Nth most significant bit, and (N-l) lesser significant bits, a digital signal translation circuit comprising: a digital memory having an address input and a data output at which M-bit output signals are produced, for storing a table of digital signals; encoding means, coupled between said source of digital input signals and said address input of said digital memory, for combining respective ones of said lesser significant bits with said most significant bit; and decoding means, having an input coupled to said data output of said digital memory, for combining respective ones of said M output bits of said memory with said most significant bit to produce processed output signals. 2. The arrangement of Claim 1, wherein said encoding means comprises a plurality of exclusive- OR gates, each having a first input responsive to said Nth bit of said digital input signals, a second input responsive to a bit of said digital input signals other than said Nth bit, and an output coupled to said address input of said digital memory; and said decoding means comprises a plurality of exclusive-OR gates, each having a first input coupled to the output of said digital memory, a second input coupled to receive said Nth bit of said digital input signals, and an output at which a bit of said processed output signals is produced. 3. The arrangement of Claim 2, wherein the number of exclusive-OR gates of said encoding means is equal to (N-l) , the number of exclusive-OR gates of said decoding means is equal to (N-l) , and the size of said digital memory is equal to 2^-1 (N-l) . 4. The arrangement of Claims 1, 2 or 3, further comprising means for combining said most significant bit of said digital input signals, with said processed output signals of said decoding means to produce translated output signals of N-bit words. 5. Apparatus for calculating the square of the radial coordinate of polar coordinate raster scan, said apparatus characterized by: means for supplying . temporally-parallel streams of x and y orthogonal Cartesian coordinates descriptive of raster scan, the y coordinates enumerating scan lines in each field of raster scan by zero and by negative and positive numbers, and the x coordinates enumerating picture elements in each scan line by zero and by negative and positive numbers, zero x and y coordinates specifying the point in the raster scan with zero radial coordinate; an output register for storing the square of the radial coordinate of polar coordinate raster scan as it is calculated; means for initializing the contents of said output register to the square of the radial coordinate of the initial point of said raster scan; means responsive to each change in x coordinate for doubling that change; means for thereupon performing a signed addition of * the doubled change, unity and the contents of said output register to update the contents of said output register; means responsive to each change in y coordinate for doubling that change; and means for thereupon performing a signed addition of the doubled change, unity, and the contents of said output register to update the contents of said output register. 6. Apparatus as set forth in Claim 5 characterized by being in combination with a read-only memory having an input to which at least a portion of said square of the radial coordinate is applied and having an output for providing a function of that radial coordinate. 7. Apparatus for calculating the radial coordinate of polar coordinate raster scan, said apparatus characterized by comprising in addition to the apparatus set forth in Claim 5 the following: a read-only memory responding to at least a portion of the contents of said output register for supplying from storage said radial coordinate as output signal. 8. Phantom raster generating apparatus comprising means for generating a description of raster scan in angular coordinates and in coordinates orthogonal to said angular coordinates, such as radial coordinates, including means for transforming a description of unrotated raster scan in Cartesian coordinates to a description of unrotated raster scan in angular and orthogonal coordinates; image memory means responsive during each of its read cycles to the modular or integral portions of said angular and of said orthogonal coordinates applied thereto as memory addressing for supplying data concerning successive ones of first points located at said modular or integral portions of said angular and radial coordinates, second points located at said modular or integral portion of one of said angular and orthogonal coordinates altered by unity in a given sense and at said modular or integral portion of the other of said angular and orthogonal coordinates, third points located at said modular or integral portion of said other of said angular and orthogonal coordinates altered by unity in said given sense and said modular or integral portion of said one of said angular and orthogonal coordinates, and fourth points located at said modular or integral portions of said angular and orthogonal coordinates (Claim 8, cont'd) each altered by unity in said given sense; and means for providing a two-dimensional interpolation among said data, characterized in that said means for providing a two-dimensional interpolation among said data comprises: means for performing a first linear interpolation, accordin to residual or fractional portions of said one of said annular and orthogonal coordinates, between data concerning successive pairs of first and second points to obtain a stream of first intermediate interpolation results; means for performing a second linear interpolation according to residual or fractional portions of said one of said angular and orthogonal coordinates, between data concerning successive pairs of third and fourth points to obtain a stream of second intermediate interpolation results; and means for performing a third linear interpolation between concurrently provided first and second intermediate interpolation results according to residual or fractional portions of said other of said angular and orthogonal coordinates to obtain a stream of successive video signal samples. 9. Phantom raster generating apparatus as set forth in Claim 8 characterized in that said means for generating a description of raster scan in angular and orthogonal coordinates includes, in addition to means for transforming a description of unrotated raster scan in Cartesian coordinates to a description of unrotated raster scan in angular and orthogonal coordinates, means for linearly combining a programmable offset to said angular coordinates. 10. Phantom raster generating apparatus as set forth in Claim 8 characterized in that said means for generating a description of raster scan in angular and orthogonal coordinates includes, in addition to means for transforming a description of unrotated raster scan in Cartesian coordinates to a description of unrotated raster (Claim 10, cont'd) scan in angular and orthogonal coordinates, means for linearly combining offsets with said angular coordinates as a function of said orthogonal coordinates. 11. Phantom raster generating appartus comprising image memory means responsive during each of its read cycles to the modular or integral portions of angular coordinates and at coordinates, such as radial coordinates, orthogonal to said angular coordinates, applied thereto as memory addressing, for supplying said data concerning successive ones of first points located at said modular or integral portions of said angular and radial coordinates, second points located at said modular or integral portion of one of said angular and. orthogonal coordinates altered by unity in a given sense and at said modular or integral portion of the other of said angular and orthogonal coordinates, third points located at said modular or integral portion of said other of said angular and orthogonal coordinates altered by unity in said given sense and said modular or integral portion of said one of said angular and orthogonal coordinates, and fourth points located at said modular or integral portions of said angular and orthogonal coordinates each altered by unity in said given sense; and means responsive to the residual or fractional portions of said angular and orthogonal coordinates for performing a two-dimensional interpolation between each successively supplied set of first, second, third, and fourth points to obtain successive samples of a video signal descriptive of an image stored in said image memory means, said phantom raster -genrating apparatus characterized in a generator for the angular coordinates for addressing said image memory means which includes means for generating a description of raster scan in angular coordinates and in coordinates orthogonal to said angular coordinates, such as radial coordinates, and means selectively combining an offset with said angular coordinates for generating the angular coordinates for application to said image eiory means. 12. Apparatus for generating a relatively high- amplitude-resolution video signal descriptive of an edge transition in a graphic image to appear on a display screen, which screen is to be raster scanned during the writing of the display in accordance with the scanning line-by-line of one coordinate in a system of orthogonal, Cartesian spatial coordinates and scanning pixel-by-pixel of the other coordinate, and which edge transition portion of the graphic image is defined by single bit or at least relatively low amplitude resolution samples at points defined by integral portions of another system of orthogonal spatial coordinates, said apparatus characterized by means for generating in said other system of spatial coordinates a stream of pairs of first and second coordinates describing a rotated phantom raster scan — i.e., at least a portion of the raster scanning of display screen as transformed to said other system of coordinates — and having respective integral and fractional values; means for specifying without replication the low-amplitude-resolution samples of said graphic image at points in said other system of spatial coordinates specified by integral portions of said first and second coordinates; means responsive to the integral values of each pair of first and second coordinates for selecting the low-amplitude-resolution samples concerning four points in said other system of spatial coordinates defining the corners of a spatial region, the location of the first point in said other system of spatial coordinates specified by the integral values of said first and second coordinates, the location of the second point specified by the integral value of said first coordinate as modified by unity and by the integral value of said second coordinate, the location of the third point specified by the integral value of said first coordinate and by the integral value of said second coordinate as modified by unity, and the location of the fourth point specified by the integral values of said first and second coordinates each as modified by unity; and means for generating, (Claim 12, cont'd) responsive to each set of four low-amplitude-resolution samples thus selected, a successive sample of said high- amplitude-resolution signal essentially equal to a weighted summation of those selected. four low-amplitude-resolution samples, the sample concerning the first point weighted in proportion to the product, of the complements of the fractional portions of said first and second coordinates, the sample concerning the second point weighted in proportion to the product of the fractional portion of said first coordinate times the complement of the fractional portion of said second coordinate, the sample concerning the third point weighted in proportion to the product of the complement, of the fractional portion of said first coordinate times fractional portion of said second coordinate, and the sample concerning the fourth point weighted in proportion to the product of the fractional portions of said first and second coordinates. 13. Apparatus for looking up tabulated values of a non-linear function of a first variable, which function is other than simply the anti-logarithm of said first variable and exhibits a non-linearity that is monotonic or nearly so throughout the range of said variable, said apparatus characterized by: a first read only memory with a plurality of storage locations for storing respective ones of said tabulated values, each storage location addressable by a binary number which is a logarithm of said variable, said logarithm being such as to reduce the number of bits required in the binary numbers for given ' resolution in the definition of said function; and means for generating binary numbers for addressing said first read only memory which are logarithms of said first variable. 14. Apparatus as set forth in Claim 13, characterized by said means for generating numbers for addressing said first read-only memory comprising means for performing the steps of an arithmetic calculation carried out in the logarithmic domain up to the step of taking the antilogarithm to find the arithmetic result. 15. Apparatus as set forth in Claim 13, characterized by said means for generating numbers for addressing said first read-only memory comprising: means for performing the steps of a division carried out in the logarithmic domain up to the step of taking the antilogarithm to find the quotient. 16. A combination as set forth in Claim 13, characterized in that said means for generating numbers • for addressing said first read-only memory includes: means .fo .generating binary numbers descriptive of a second variable; means for generating binary numbers descriptive of a third variable; a second read-only memory addressable by said binary numbers descriptive of a second variable to provide respective binary numbers proportional to their logarithms; a third read-only memory addressable by said binary nu bres, desriptive of a third variable to provide respective binary numbers proportional to their logarithms; means for linearly combining the binary numbers provided by said second and third read-only memories to provide the addressing for said first read only memory. 17. The combination characterized by means for supplying successive pairs of binary numbers respectively descriptive of first and second variables, each binary number having an integral portion and at least some of them having respective non-integral portions; a memory having storage locations for storing single-bit-binary-number digital samples of a two-dimensional function of said first and second variables; means responsive to integral (Claim 17 , cont ' d) portions of each successive pair of binary numbers respectively descriptive of said first and second variables for extracting from said memory digital samples of said two-dimensional function at first storage location coordinates equal to those integral portions, at second storage location coordinates respectively equal to the integral portion of the first variable incremented by unity and to the integral portion of the second variable, at third storage location coordinates respectively equal to the integral portion of the first variable and to the integral portion of the second variable incremented by unity, and at fourth storage location coordinates respectively equal to the integral portion of said first variable incremented by unity and to the integral portion of said second variable as incremented by unity; means for obtaining a first intermediate interpolation result by linearly interpolating between the digital samples at said first coordinates and at said second coordinates in accordance with the fractional portion of said first variable, which means includes means for selecting zero as said first intermediate interpolation result ' responsive to the digital samples at said first coordinates and at said second coordinates both being ZΞROs, means for selecting unity as said first intermediate interpolation result responsive to the digital samples at said first coordinates and at said second coordinates both being ONEs, means for selecting the fractional portion of said first variable as said first intermediate interpolation result responsive to the digital samples at said first coordinates 'and at said second coordinates being respectively a ZERO and a ONE, and means for generating the complement of the fractional portion of said first variable as said first intermediate interpolation result responsive to the digital samples at said first coordinates and said second coordinates being respectively a ONE and a ZERO ; means for obtaining a second intermediate interpolation result by linearly interpolating between the digital samples at said third coordinates and at said fourth (Claim 17, cont'd) coordinates in accordance with the fractional portion of said first variable, which means includes means for selecting zero as said second intermediate interpolation result responsive to the digital samples at said third coordinates and air said fourth coordinates both being ZEROs, means for selecting unity as said second intermediate interpolation result responsive to the digital samples at said third coordinates and at said fourth coordinates both being ONEs, means for selecting the fractional portion of said first variable as said second- intermediate interpolation result responsive to the digital samples at said third coordinates and at said fourth coordinates being respectively a ZERO and a ONE, and means for generating the complement of the fractional portion of said first variable as said second intermediate interpolation result responsive to the digital samples at said third coordinates and at said fourth coordinates being respectively a ONE and a ZERO; and means for obtaining a final interpolation result, which is the interpolated value of said two-dimensional function, by linearly interpolating between the said first and said second intermediate interpolation results in accordance with the fractional portion of said second sample.

Inventors: ACAMPORA ALFONSE, LEWIS HENRY GARTON JR, REITMEIER GLENN ARTHUR, SMITH TERRANCE RAYMOND, STROLLE CHRISTOPHER HUGH
Applicants: RCA CORP
Application year: 1982
Main classification: H04N5
IPC codes: G06F1, G06T3, G09G5, G11C7, G11C8, H04N9