MULTICELLULAR THYRISTOR

Abstract: A four-region semiconductor device (that is, a p-n-p-n or n-p-n-p device) including at least one further region uti­ lizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the de­ vice is provided with a turn-off capability. The device re­ quires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the de­ vice.

Description: Cross-Reference to Related Application This application is a continuation-in-part of copending U.S.Patent application Serial No. 331,049, filed December 16, 1981, the entirety of which is hereby incorporated by reference. Background of the Invention The present invention relates to a four-region semiconductor device (that is, a p-n-p-n or n-p-n-p device) including at least one further region, and, more particularly, to a ¯four-region device having the capability of turning off upon application of a voltage signal to a control gate thereof. Four-region semiconductor devices per se are well known in the art, and-include, for example, thyristors or SCRs. Many techniques exist for turning on a thyristor; however, fewer techniques exist for turning off a thyristor. One technique for turning off a thyristor is implemented in a gate turn-off thyristor(GTO). A GTO is a four-region device which has a control gate connected to one of the inner regions thereof, for example, the P-base region. With the connection made to the P-base region, a positive bias voltage of sufficient magnitude, applied to the GTO's control gate, serves to turn the GTO on. A negative bias voltage of sufficient magnitude applied to the GTO's control gate serves to turn off the GTO. As will be appreciated by those skilled in the art, a turn-off current of significant magnitude must be supplied to a GTO's control gate to implement turn-off thereof. Since the energy requirement for the GTO control gate during turn-off is proportional to the turn-off current required thereby, this energy requirement is significant, or high. A further deficiency of a GTO arises in a practical implementation thereof wherein the GTO has its control gate and cathode interdigitated to optimize its turn-off gain (that is, the ratio of turn-off control gate current to the device current). The deficiency is that the device area underneath the control gate does not substantially contribute to carrying device current. Consequently, such a GTO fails to utilize a high percentage of its semiconductor body for carrying current through the device. Another deficiency of a GTO is that its speed of turnoff is limited by carrier recombination in the inner region of the device which is not connected to its control gate, after the p-n junction between the two inner regions of the device becomes reverse.biased. Objects of the Invention Accordingly, it is an object of the present invention to provide a four-region semiconductor device including at least one further region and having a turn-off capability, which device has a low energy requirement for its tun-off control gate and which device, further, utilizes a high percentage of its semiconductor body for carrying current through the device. Another object is to provide a four-region semiconductor device including at least one further region and having a turnoff capability, which device is not subject to the entire delay of carrier recombination in either of its inner regions during turn-off, thereby achieving high-speed turn-off. Summary of the Invention In carrying out the objects of the invention, there is provided a semiconductor device comprising a body of semiconductor material, a first electrode, a second electrode, and a third electrode spaced from the body by a first insulative layer. The body comprises first, second, third, and fourth regions, successively joined together in the foregoing order. The first region is separated from the third and fourth regions by the second region, and the fourth region is separated from first and second regions by the third region. The first and third regions are of one conductivity type, and the second and fourth regions are of the opposite conductivity type. The semiconductor body further comprises a fifth region adjoining the fourth region, separated from the first, second, and third regions by the fourth region, and which is of the one conductivity type. The first electrode is electrically connected to the first region. The second electrode is electrically connected to the fourth and fifth regions. The third electrode overlies an area of the fourth region, but is spaced therefrom by the first insulative layer. The third electrode, the first insulative layer, and the fourth region are so constructed and arranged that a first inversion channel within the fourth region, and connecting together the third and fifth regions is induced beneath the third electrode upon application to the third electrode of a first bias voltage having predetermined polarity and magnitude. The semiconductor device may conveniently be referred to as a metal-o#ide-semiconductor turn-off thyristor("MOSTOT"). The term "metal" in "metal-oxide semiconductor connotes, as is knotim in the art, metal or other highly conductive material, such as highly doped polysiliconand the term "oxide" connotes an oxide of semiconductor material or another insulating layer. Brief Description of the Drawing Figures The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself, however, both as to organization and method of operation, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawing figures in which: : FIGURE 1 is a schematic, cross-sectional view of a portion of a MOSTOT incorporating one embodiment of the present invention; FIGURE 2 is a composite graph of various parameters of the MOSTOT of Figure 1 versus the resistance of a bypass current path of such device; FIGURE 3 is an electrical circuit representation of a portion of the MOSTOT shown in Figure 1; FIGURE 4 is a schematic, cross-sectional view of a portion of a MOSTOT incorporating a further embodiment of the present invention; FIGURE 5 is an electrical circuit representation of a portion of the MOSTOT shown in Figure 4; FIGURE 6 is a schematic, cross-sectional view of a portion of a MOSTOT incorporating a still further embodiment of the present invention; FIGURE 7 is an electrical circuit representation of a portion of the MOSTOT shown in Figure 6; ; FIGURE 8 is a schematic, cross-sectional view of a portion of a MOSTOT incorporating a modification of the embodiment shown in Figure 6; and FIGURE 9 is a schematic, cross-sectional view, in perspective, illustrating various aspects of a preferred implementation of the present invention. Detailed Description of the Invention Figure 1 shows a portion of a MOSTOT 10. The left-hand side of the device 10, as shown, comprises half of a cell the other side of which is preferably symmetrical with the shown half,¯ and the right-hand side of the MOSTOT 10. as shown, comprises a portion of a further cell which advantageously is configured substantially the same as the former cell. Accordingly, only the left-hand cell is described in detail here. The MOSTOT 10 includes a semiconductor body 11, which comprises first, second, third, and fourth regions, 12, 13, 14 and 15, respectively, successively joined together in the foregoing order. The first region 12 is separated from the third and fourth regions 14 and 15 by the second region 13; and the fourth region 15 is separated from the first and second regions 12 and 13 by the third region 14. The junction between the first and second regions 12 and 13 defines a first junction 17; the junction between the second and third regions 13 and 14 defines a second junction 18; and the junction between the third and fourth regions 14 and 15 defines a third junction 19. The first and third regions 12 and 14 are both of one conductivity type, P-type here; and the second and fourth regions 13 and 15 are both of the opposite conductivity type, N-type here. In the particular MOSTOT shown, the regions 12-15 comprise, respectively, a P+ emitter region, an N base region, a P base region, and an emitter region (having portions N1+ and N2, as discussed below). The first region 12 preferably has a maximum doping concentration in excess of about 1018 impurity atoms per cubic centimeter; the second region 13 preferably has a maximum doping concentration below about 1016 impurity atoms per cubic centimeter;the third region 14 preferably has a maximum doping concentration below about 1017 impurity atoms per cubic centimeter; and the 1 portion of the fourth region 15 preferably has a maximum dqglg concentration in excess of about 1018 impurity atoms per cubic centimeter. It is desirable that the foregoing doping concentrations be selected to provide good thyristor action in the MOSTOT 10, and, accordingly, specific quantitative values of such doping concentrations will be apparent to those skilled in the art. The semiconductor body 11 further comprises a fifth region 21 which adjoins the fourth region 15 and is separated from the first through third regions 12-14 by the fourth region 15. The fifth region 21 is of the one conductivity type, P-type here, and preferably has a doping concentration in excess of about 1018 impurity atoms per cubic centimeter to attain good electrical contact to an electrode 25, discussed below. The junction between the fourth and fifth regions 15 and 21 defines a fourth junction 22. The third and fourth junctions 19 and 22 each have respective terminated portions at the exterior of the semiconductor body 11, such terminated portions being at the upper surface of the body 11 in the particular embodiment shown. A first electrode 24 is electrically connected to the first region 12, and functions as an anode in the MOSTOT 10. A second electrode 25 is electrically connected to both the fourth and fifth regions 15 and 21, and functions as a cathode in the device 10. A third electrode 27 is spaced from the body 11 by an insulative layer 30. The third electrode 27 functions as a turn-off control gate in the MOSTOT 10. The third electrode 27"overlies" an area of the semiconductor body 11 extending at a minimum from a location proximate the aforesaid terminated portion of the third junction 19, such as at dashed line 28, to a location proximate the aforesaid terminated portion of the fourth junction 22, such as at dashed line 29. While the third electrode 27 preferably overlaps the exposed portions of the third and fourth junctions 19 and 22, as shown, a small amount of underlap is tolerable. What is crucial is that, in accordance with the invention, the third electrode 17, the insulative layer 30, and the fourth region 15 are so constructed and arranged that an inversion channel 31, as delineated by a dashed line within the fourth region 15 and which connects together the third and fifth regions 14 and 21, is formed beneath the third electrode 27 by applying a bias voltage thereto which has a polarity and a magnitude suitable to attract minority carriers of the fourth region 15 into the channel 31. The overlapping of the third electrode 27 over the exposed portions of the third and fourth junctions 19 and 22 serves to enhance such attraction of minority carriers of the fourth region 15 into the channel 31, and helps to ensure a path of low resistance to "bypass" carriers, or carriers having a same electrical sign as such minority carriers. The electrical resistance to such bypass carriers (holes, here) of the channel 31 (hereinafter, simply "resistance") varies according to the magnitude of the aforesaid bias voltage in a manner which will be apparent to those skilled in the art. To implement the instant embodiment of the invention, with the inversion channel 31 present due to the application to the third electrode 27 of the aforesaid bias voltage, the maximum electrical resistance presented to bypass carriers along a distributed, bypass carrier current path 32, extending from the interior of the third region 14, through the channel 31, and through the fifth region 21, to the second electrode 25, constitutes a value selected to limit forward biasing of the third junction 19 as a result of bypass carrier current flow in the current path 32 to no more than about one-half of the energy bandgap voltage of the semiconductor material forming the third junction 19 (hereinafter, simply "energy bandgap voltage"). This enables the MOSTOT 10 to turn off, as will be more apparent from the discussion of device turn-off below. -- The distributed bypass carrier current path 32, which exists during device turn-off is to be distinguished from the hole and electron current paths which exist in the device in the on-state. Such on-state current paths are generally oriented straight up and down across the various junctions 17, 18, and 19, as viewed in Figure 1. To facilitate the attainment of the proper value for the resistance of the distributed, bypass carrier current path 32, the fourth region 15 preferably has an N2 portion, as shown in Figure 1, in which the first channel 31 is situated 17 and which has a maximum doping concentration below about 1017 impurity atoms per cubic centimeter in the area occupied by the channel 31. This facilitates the creation of the inversion channel 31 upon the application to the third electrode 27 of the aforesaid bias voltage. Such doping of the N2 portion in the fourth region 15 can be achieved by, first, providing an N+ diffusion for the entire fourth region 15 through a first diffusion window, and, second, providing a carefully selected P lateral diffusion for the fifth region 21 through a second diffusion window located within the first diffusion window, thereby forming the N2 portion having a lower doping concentration than the original N diffusion. Alternatively, the fourth region 15 can be formed by one diffusion for the N1 portion, and another diffusion for the N2 portion, which overlaps the diffusion for the N1+ portion after which the fifth region 21 can be diffused into the fourth region 15 through a diffusion window located within the same diffusion window used for diffusing the N2 portion. Additionally, to facilitate the attainment of the proper value for the resistance of the distributed, bypass carrier current path 32, the following design considerations should be taken into account. Reducing the overall length of the current path 32 by reducing the horizontal dimension of the fourth region 15 as viewed in Figure 1 will desirably decrease the resistance of the current path 32. Further, the length of the channel 31 (that is, the dimension in the direction of current flow) can be minimized, and the width of the channel 31 (that is, the dimension normal to the direction of current flow) can be maximized, both of which desirably decrease the resistance of the current path 32. In connection with maximizing the width of the channel 31, the configuration of the fourth region 15 of the MOSTOT 10 as viewed from above (which defines the cell configuration) preferably is square or round, as opposed to being elongated, whereby the channel width per area of each cell is maximized. Still further, the doping of the third and fifth regions 14 and 21 to high concentrations desirably decreases the resistance of the current path 32; however, the third region 14 should not be too highly doped lest the forward drop of the MOSTOT 10 becomes undesirably excessive. In general, the lower the resistance of the bypass carrier current path 32, the greater the amount of device current that can be turned off. In a worst case analysis, the MOSTOT 10 could turn off a maximum amount of current equalling one-half of the energy bandgap voltage divided by the resistance of the current path 32. Such a worst case analysis assumes the following: (1) that all hole current passing upward in the MOSTOT 10 through the second junction 18 as viewed in Figure 1 is constrained to flow in the distributed current path 32; (2) that the total device current passing across the second junction 18 consists solely of hole current; and (3) that the maximum voltage across the third junction 19 must be reduced all the way to one-half of the energy bandgap voltage before device turn-off can occur. A computed example of a one-dimensional model of a particular implementation of the MOSTOT 10 of Figure 1 indicates, however, that the MOSTOT 10 can turn off considerably more current than in the foregoing, worst case. Such computed example has provided the data illustrated in the composite graph of Figure 2, wherein various device parameters are plotted against the resistance of the bypass carrier current path 32. When such resistance has been reduced to about 10 milliohms, the MOSTOT-10 turns off, and all the curves shown fall to zero. As can be appreciated from Figure 2, the hole current through the current path 32 ("Hole Current through Inversion Channel") comprises but a fraction of the hole current at the second junction 18. Additionally, it can be seen that the hole current in the current path 32 comprises only about 40 per cent of the total device current. Further, it can be seen that the maximum voltage across the third junction 19 only needs to be reduced to about 0.814 volts in order for turn-off of the MOSTOT 10 to occur, as compared with one-half of the energy bandgap voltage, which is about 0.6 volts for silicon. It is believed that the foregoing computed example represents more typical design assumptions than does the worst case, discussed above. Accordingly, a typical MOSTOT 10 of Figure l can turn off considerably more current than the worst case analysis suggests. The operation of the MOSTOT 10 can be understood with reference to Figure 3, which shows an electrical circuit representation of one of the cells of the MOSTOT 10 of Figure 1. In Figure 3, the electrodes 24, 25 and 27 correspond to the like numbered electrodes in Figure 1. The first, second, and third regions 12, 13, and 14 of Figure 1 are represented in Figure 3 by a bipolar 35, while the second, third and fourth regions 13, 14 and 15 are represented by a bipolar transistor 36. The transistors 35 and 36 are coupled to each other in back-to-back fashion. The inversion channel 31 of Figure 1, along with the P fifth region 21 at one end thereof and with the P base third region 14 at the other end thereof, is represented as a metal-oxide semiconductor field effect transistor ("MOSFET") 37 in Figure-3. When the MOSTOT 10 10 is in a turned on condition, device current flows from the anode electrode 24 to the cathode electrode 25, and the transistors 35 and 36 operate in a regenerative mode; that is, the collector current for one transistor drives the base of the other transistor, and vice-versa, thereby maintaining the MOSTOT 10 turned on. The hole current path from the collector of the transistor 35 to the base of the transistor 36 is indicated by the current arrow 39. Upon application of the aforesaid bias voltage (which is negative, here) to the gate electrode 27, the MOSFET 37 draws away or "steals" hole current from the hole current path 39, and directs the diverted current through the path indicated by the current arrow 40 (this is the analog of the bypass current path 32 ot Figure 1), to the cathode electrode 25. When the bias voltage on the gate electrode 27 reaches a sufficient magnitude, the resistance through the MOSFET 37 will be sufficiently lowered to a value that reduces the base-to-emitter voltage of the transistor 36 below about one-half of the energy bandgap voltage of the semiconductor material forming its base-to-emitter junction. This causes the transistor 36 to turn off, which, in turn, causes the transistor 35 to turn off, thereby turning off the cell of the MOSTOT 10 of Figure l, which is represented in Figure 3. For the entire MOSTOT 10 to turn off, however, it is necessary that all the cells in the MOSTOT 10 turn-off. In order to achieve turn-off of the MOSTOT 10, the third electrode, or turn-off control gate 27, needs to be biased with a bias voltage and charged to a value proportional to the capacitance between the third electrode 27 and the semiconductor body 11. Because the energy requirement for the turn-off control gate 27 is proportional to the product of the square of such bias voltage and the value of such capacitance, and because the values of both of such voltage and capacitance 2 are low (for example, 10 volts and 1000 picofarads-cm2, respectively), it can be appreciated that the energy requirement of the turn-off control gate 27 is likewise low. When the MOSTOT 10 is operating in a turned on condition, the region 33 between the vertical walls of the adjacent N+ emitter regions 15 and 34 is a region of reduced electron injection from the N+ emitter regions 15 and 34; accordingly, current flow from the anode to the cathode of the MOSTOT 10 is reduced in the region 33 compared with the remainder of the illustrated portion of the semiconductor body 11. However, because the region 33 is typically much smaller than the remainder of the semiconductor body 11, and because current spreading of electrons occurs as they flow downward to the anode 24, the MOSTOT 10 achieves utilization of a high percentage of the semiconductor body 11 for carrying current therethrough. The deleterious effect of the region 33 becomes reduced as the dimension between the anode 24 and the cathode 25 becomes larger. Turning now to Figure 4, a portion of a MOSTOT 45 incorporating a second embodiment of the invention is shown, and comprises two half cells in the same manner as the device 10 of Figure 1. The MOSTOT 45 has first through fourth regions 47, 48, 49 and 50, respectively, which are suitably doped to the same concentrations as the first through fourth regions 12, 13, 14 and 15, respectively, of the MOSTOT 10 of Figure 1. The anode and cathode electrodes 52 and 53 of the device 45 correspond to the anode and cathode electrodes 24 and 25 of the MOSTOT 10. In the MOSTOT 45, carriers, electrons here, are diverted to the anode electrode 52 through a distributed, bypass carrier current path 55, which is the complement of the bypass carrier current path 32 of the MOSTOT 10. The current path 55 includes an inversion channel 57 within the first region 47, which is the complement of the inversion channel 31 of the MOSTOT 10. The inversion channel 57 is created by application of a bias voltage, positive here, to a turn-off control gate 58 which is separated from the semiconductor body 59 by an insulative layer 60. The bypass carrier current path 55 further includes a fifth region 61, which is the complement of the fifth region 21 of the MOSTOT 10. The gate electrode 58 and insulative layer 60 correspond to the gate electrode 27 and insulative layer 30 of the device 10. Additionally, the first region 47 preferably has a P1 portion and a P2 portion, preferably having a lower doping concentration than the P1+ portion, corresponding to the preferred relative doping concentrations of the N1+ and N2 portions, respectively, of the fourth region 15 of the MOSTOT 10 discussed above. Accordingly, an understanding of the MOSTOT 45 will be apparent to those skilled in the art, based upon the above description of the MOSTOT. 10, along with the foregoing comments noting complementarities and correspondences between theMOSTOT 10 and 45. A further understanding of the MOSTOT 45 can be had from considering its operation with reference to Figure 5, which shows an electrical circuit representation of one of the cells of the MOSTOT 45 of Figure 4. In Figure 5, the electrodes 52, 53J 58 correspond-to the like numbered electrodes in Figure 4. The first through fourth regions 47-50 are represented in Figure 5 by coupled, back-to-back bipolar transistors 62 and 64, in the same manner as the transistors 34 and 35 of Figure 3 represent the first through fourth regions 12-15 of the MOSTOT 10. The inversion channel 57 of Figure 4, along with the N+ fifth region 61 at one end thereof and with the N base region 48 at the other end thereof, is represented as a MOSFET 65 in Figure 5. When the MOSTOT 45 is in a turnedon condition, the device current flows from the anode electrode 52 to the cathode electrode 53, and the transistors 62 and 65 operate in a regenerative mode; that is, the collector current of one transistor drives the base of the other transistor, and vice-versa, thereby maintaining the MOSTOT 45 turned on. The electron current path from the collector of the transistor 64 to the base of the transistor 62 is indicated by current arrow 67. Upon application of the aforesaid bias voltage (which is positive, here) to the gate electrode 58, the MOSFET 65 draws away or "steals" electron current from the current path 67 and directs the diverted electron current through the path indicated by current arrow 68, to the anode electrode 52. When the bias voltage on the gate 58 reaches a sufficient magnitude, the ¯resistance of the MOSFET 65 will be sufficiently reduced to such a value that the base-to-emitter voltage of the transistor 62 is reduced to below about one-half of the energy bandgap voltage thereof. This causes the transistor 62 to turn-off, which in turn, causes the transistor 64 to turn-off, thereby turning off the cell of the MOSTOT 45 of Figure 4 which is represented by the circuit of Figure 5. For the entire MOSTOT 45 to turn-off, however, it is necessary that all the cells in the MOSTOT 45 turn off. As is the case with the embodiment shown in Figure 1, the embodiment of Figure 4 attains the objects of a low energy requirement for the turn-off gate control electrode 58, and of utilization of a high percentage of the semiconductor body 59 thereof for carrying current. Turning to Figure 6, a portion of a MOSTOT 70 incorporating a third embodiment of the present invention is shown, and comprises two half cells in the same manner as the MOSTOT 10 of Figure 1. The MOSTOT 70 incorporates features of both the MOSTOT 10 of Figure 1 and the MOSTOT 45 of Figure 4. Specifically, the portion of the MOSTOT 70 above second junction 71 suitably is substantially identical to the portion of the MOSTOT 10 above the second junction 18 thereof; and the portion of the MOSTOT 70 below the second junction 71 suitably is substantially identical to the portion of the MOSTOT 45 below second junction 72 thereof. Accordingly, an understanding of the MOSTOT 70 can be had by consideration of the above discussions of the MOSTOTs 10 and 45 in light of the foregoing comments. The portion of the MOSTOT 70 shown thus has two turnoff control gates, gate A and gate B, which provides faster device turn-off, as will become apparent from the discussion below. A further understanding of the MOSTOT 70, including details of operation, can be had by reference to Figure 7, which shows an electrical representation of one of the cells of the MOSTOT 70 shown of Figure 6. In Figure 7, the gate A, gate B, anode and cathode electrodes correspond to the like designated electrodes of Figure 6. The four regions of the MOSTOT 75 of Figure 6, designated P1 + emitter, N base, P base, and N1 emitter, are represented in Figure 7 by bipolar transistors 72 and 74, in the same manner as the transistor 34 and 35 of Figure 3 represent the first through fourth regions 12-15 of the MOSTOT 10. An upper MOSFET 75 is associated with the upper inversion channel 77 of Figure 6, and a lower MOSFET 78 is associated with the lower inversion channel 80 of Figure 6. From the previous descriptions of the MOSTOTs 10 and 45, it can be appreciated.that a negative bias voltage having a sufficient magnitude applied to gate A will divert sufficient hole current 81 away from the P base hole current 82 so as to reduce the base-to-emitter voltage of the transistor 80 below about one-half of the energy bandgap voltage thereof, thereby inducing turn-off of the transistor 74. This, in turn, causes the transistor 72 to turn off; however, the turn-off of this transistor 72 is slowed by carrier recombination in the Nbase region of the MOSTOT 70 after the second junction 71 becomes reverse biased during the process of device turn-off. In accordance with the instant embodiment of the present invention, the delay due to carrier recombination in the N base region of the MOSTOT 70 is largely avoided by diverting sufficient electron current 85 away from the N base electron current 84 and channeling the diverted electron current 85 to the anode electrode through the MOSFET 78, thereby turning off the transistor 72. The MOSFET 78 is activated to accomplish this result through application to the gate B of a bias voltage, positive here, of sufficient magnitude so as to reduce the base-to-emitter voltage of the transistor 72 below about one-half of the energy bandgap voltage thereof. Accordingly, the instant embodiment of the invention attains the object of high-speed turn-off by not being subject to the entire delay of carrier recombination in its inner region, the N base region here, after the second junction 71, or p-n junction between the two inner regions, P base and N base, of the 240STDT70, becomes reverse biased. In practising the foregoing described third embodiment of the invention, illustrated by way of example in Figure 6, the density of cells (which determines cell size or, alternatively, the number of cells when, for instance, some cells are deleted) of the MOSTOT 70 above the second junction 71 need not be the same as the density of cells below this junction. Further, in order to achieve the fastest device turn-off, the aggregate hole current passing through all the inversion channels under gate A, such as the inversion channel 77, should be approximately equal to the aggregate electron current passing through all the inversion channels under gate B, such as the inversion channel 80, whereby the lower and upper bipolar transistor portions of the MOSTOT 70, represented by transistors 72 and 74 in Figure 7, respectively, turn off at approximately the same rate. This may require different cell densities above and below the second junction 71 in the MOSTOT 70, and, for example, where the semiconductor body 87 of the MOSTOT 70 comprises silicon, the cell density above the second junction 71 should be greater than the cell density below this junction. This is because in silicon the resistance to hole current is greater than the resistance to electron current; thus, the cell density above the second junction 71, pertaining to bypass carrier current consisting of holes (not illustrated), should be relatively high, thereby shortening the path of such bypass carrier current (not illustrated) and limiting the resistance of such path to a desired value. The MOSTOT 70 additionally attains the objects of the previous MOSTOTs 10 and 45, namely, the objects of a low energy requirement for its turn-off control gates, (both gate A and gate B), and of the utilization of a high percentage of ts semiconductor body 87 for carrying current. Turning to Figure 8, a portion of a tSOSTOT 90 illustrating a modification of the MOSTOT 70 of Figure 6 is shown. The difference between the MOSTOTs 70 and 90 is that in the MOSTOT 70, first and fourth regions 91 and 92, respectively, are horizontally aligned with each other as viewed in Figure 6, whereas in the device 90, first and fourth regions 94 and 95, respectively, are horizontally offset from each other as viewed in Figure 8. The MOSTOT 70 of Figure 6 has the advantage of maximizing current-carrying capacity. This is because the areas of reduced carrier injection 97 and 98, adjacent to the first and fourth regions 91 and 92, (and thus, adjacent to the upper and lower inversion channels 77 and 80) are horizontally aligned with each other, thereby minimizing the influence of these regions in decreasing the current carrying capacity of the MOSTOT 70. On the other hand, the MOSTOT 90 of Figure 8 maximizes turn-off speed. This is because the upper inversion channels, such as channel 100, which are horizontally offset from the lower inversion channels, such as channel 101, are provided with a large flow of hole current originating from the first layer 94; and the lower inversion channels, such as channel 101, are provided with a large flow of electron current originating from the fourth layer 95. With the foregoing inversion channels receiving large hole and electron currents, respectively, the lower and upper transistor P rLons of the MOSTOT 90, represented by the transistors 72 and , in Figure 7, respectively, are orced to turn off especially rapidly. The thicker the MOSTOTs 70 and 90 are, however, the less pronounced are the foregoing differences between them. In making the MOSTOTs described herein, the first through third regions, as these terms are used above, are preferably fabricated using conventional techniques for making thyristors. This is due to the fact that the first and second junctions, as these terms are used above, comprise the main voltage blocking junctions of the respective MOSTOTs, at least where the first through fourth regions are doped to the various concentrations described herein, and also because thyristor technology comprehends the effectiveness of these junctions for voltage blocking purposes. Further, unlike the situation in MOS technology, carrier lifetime should be long, especially in the second region, so as to provide low forward voltage,as is known in the art. The turn-off gates fifth and their associated insulative layers, as well as the/region, as these terms are used above, are suitably fabricated using conventional techniques for making field-effect transistors ("FET's"). The fourth region, as this term is used above, is suitably fabricated using either thyristor or FET technology. Various aspects of a preferred implementation of the invention are illustrated in Figure 9, showing a portion of a MOSTOT 110. The semiconductor body of the MOSTOT 110 comprises a silicon wafer, with first through fourth regions 112-115, respectively, each comprising a layer substantially aligned with a major surface of the wafer. An / a 117 of the MOSTOT 110 corresponds to the right-hand si the MOSTOT 10 as shown in Figure 1. The shape of a cell in the DIOSTOT 110 is square, and each cell is so constructed and arranged that approximately the same amount of device current is turned off by each. Turn-off gate electrode 118 comprises polysilicon, either P-type or N-type, which is doped to a very high concentration to increase its conductivity and to enable all cells with which the electrode 118 is associated to turn off at approximately the same time. The gate electrode 118 has a substantially rectangular cross-section, and an insulative layer 120 forms a sleeve around the bottom, top, and sides thereof. The insulative layer 120 comprises an oxide of the semiconductor body of the MOSTOT 110, deposited nitride, or a combination thereof. Cathode electrode 121 is disposed over the entire upper surface of the portion of the 110 shown, and is insulated from the gate electrode 118 by the insulative layer 120. In area 122 of the MOSTOT 110, a cathodeemitter short is illustrated. The cathode electrode 121 is disposed over the semiconductor body in the area 122, the gate electrode 118 advantageously not being present in this area because it does not interact with the semiconductor body in this area. The cathode electrode 121 is connected to, and, thus, electrically shorts together portions of the N+ emitter region 115 and the P base region 114, thereby reducing the sensitivity of the MOSTOT 110 to spurious turn-on due to noise or thermal currents in its semiconductor body. The P regions within the area 122, unlike the P+ region within the fourth layer 123 of the area 117, do not perform any electrical function, but may conveniently be disposed there to simplify device manufacture. Cathode-emitter shorts preferably are occasionally but regularly interspersed amongst the cells in the MOSTOT 110 incorporating elements of the present invention,such as the cell in the area 117. This obviates the need for maintaining a bias voltage on the turn-off control gate 118 to keep the MOSTOT 110 in a turned-off condition. Ajiternatively, or in addition to the foregoing use of cathode-emitter shorts,anodeemitter shorts, such as the electrical short implemented in area 124 by anode electrode 125 connecting together the P+ emitter region 112 and N base region 113, preferably are occasionally but regularly interspersed amongst the cells in the MOSTOT 110 incorporating elements of the present invention,such as the cell in the area 117. Anode-emitter shorts, similar to cathode-emitter shorts, reduce the sensitivity of the MOSTOT 110 to spurios turn-on due to noise or thermal currents in its semiconductor body. Anode-emitter shorts also serve to speed up MOSTOT 110 with an anode-emitter short is what is known in the art as an asymmetric device, because it cannot block reverse voltage. Anode-emitter shorts per se, as well as cathode-emitter shorts per se,are known in the art. While no specific gate means for turning on the various MOSTOTs described herein have been illustrated,it will be apparent to those skilled in the art that these MOSTOTs may suitably be turned on by any conventional gate means,such as by a turn-on gate electrode connected to either the second or third regions, as these terms are used above,for turning on any of the MOSTOTs described herein. Additionally,these MOSTOTs can be turned on with an MOS turn-on gate,such as described in D.Kahng, editor, Silicon Integrated Circuits - Part B, Academic Press,l981, at pages 265-267. A further suitable technique of turning on the MOSTOTs comprises optical light turn-on. Moreover, the invention renders practical turn-on of the MOSTOTs by noise or thermal current (or a combination thereof) in their semiconductor bodies, which heretofore has been characterized,for example, as "Non Gated Undesirable Thyristor Triggering", the title of Chapter 6 of A.Blicher, Thyristor Physics, Springler-Verlag(l976). Such turn-on requires that a MOSTOT not include cathode-emitter or anode-emitter shorts, such as described above, whereby the sensitivity of the MOSTOT to turn-on by noise or thermal current (or a combination thereof) is rendered high,and the MOSTOT will turn-on in a suitable environment, as will be apparent to those skilled in the art. Turn-off of the MOSTOT can then be enabled through use of the turn-off control gates described herein. A MOSTOT in accordance with an alternative embodiment of the invention is structurally similar to any of the abovedescribed devices; however, its distributed, bypass carrier current path (or paths) is designed with a resistance to bypass carriers that is too high to permit turn-off of the device solely by means of biasing the gate (or gates) of the device. Such device must be commutated off in similar manner as with a conventional thyristor; that is, the polarity of its anode-tocathode voltage must be reversed so that the device turns off. However, such MOSTOT can turn off much more rapidly than a conventional thyristor. In addition, the design considerations discussed above that are useful in reducing the resistance of a distributed, bypass carrier current path can be relaxed. For example, the device can have a cell size which is larger than in the previously-described MOSTOTs, and, as such, could be fabricated with a higher yield. While only certain preferred features of the invention have been shown by way of illustration, many modifications and changes will occur to those skilled in the art. For example, each of the second regions of the MOSTOTs described herein, which are shown as N type, could be modified to have the portion thereof which is in contact with the respective first region doped to a concentration substantially higher than the concentration of the remainder of the second region, whereby the MOSTOT would become what is known in the art as an asymmetric device. As such it can be made thinner and still block the same forward voltage, provided that the resistance of the remainder of the second region is suitably increased. Such thinner devices are notably faster and have lower forward drops than do devices which lack the more highly doped portion in the second region. Since the foregoing asymmetric device cannot block reverse voltage, it preferably also incorporates anode-emitter shorts which similarly make the device asymmetric. Further, while the MOSTOTs described herein have been illustrated as formed by a planar diffusion process,other processes, involving the etching of a groove into a device semiconductor body, can just as well be used. Such a groove can have various shapes, depending upon whether a preferential etch or isentropic etch is used, and upon what the crystallogrphic orientation of the MOSTOT's semiconductor body is. Those skilled in the art will appreciate the range of possible groove shapes. By way of example, a common groove shape is that of a "V", as further described in D.Kahng, editor, Silicon Integrated Circuits - Part B, Academic Press, 1981, at pages 209-210. The invention does not depend upon the various regions of the described MOSTOTs having any particular configurations; therefore, other configurations of these regions can be utilized whereby, for example, a planar MOSTOT can be made having all of its p-n junctions terminating at a common MOSTOT surface which is planar. Further, referring to Figure 1, by way of example, the invention does not require the fourth region 15 to have any particular shape; therefore, the first region 15 could be elongated, or round, by way of example. Likewise, referring to Figure 4, by way of example, the present invention does not require the first region 47 to have any particular shape; therefore, it could be elongated or round, by way of example. Still further, the invention applies to complementary devices, wherein P-type regions are used in place of the N-type regions described herein, and vice-versa. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims: Claims 1. A semiconductor device characterized by a) a body (11; 87) of semiconductor material including first, second, third and fourth regions (12 to 15; 91, 92; 94, 95; 112 to 115, 123) successively joined together in the foregoing order; said first region (12; 91; 94; 112) being separated from said third and fourth regions by said second region (13: 113); and-said fourth region (15; 92; 95; 115, 123) being separated from said first and second regions by said third region (14; 114); said first and third regions being of one conductively type; and said second and fourth regions being of the opposite conductivity type: said body further including a fifth region (21) adjoining said fourth region, being separated from said first, second and third regions by said fourth region, and being of said one conductivity type; b) a first electrode (24; 125) electrically connected to said first region; c) a second electrode (25; 121) electrically connected to said fourth and fifth regions; d) a third electrode (27; A; 118) overlying an area of said fourth region; and insulative layer (30; 120) spacing said third electrode from said body: said third electrode, said insulative layer and said fourth region being so constructed and arranged that an inversion channel (31; 77; 100) within said fourth region and connecting together eaid third and fifth regions is included beneath :aid third electrode upon application of a bias voltaqe of predeterminded polarity and magnitude to said third electrode. 2. The device according to claim 1 characterized by a distributed bypass carrier current path (32) in the semiconductor body (11; 87), said current path extending from the interior of said third region (14, 114) through said inversion channel (31; 77: 100) and through said fifth region (21) to said second electrode (25; 12), the resistance of said current path being too high to permit turn-off of the device solely by application of said bias voltage to said third electrode (27; A; 118). 3. The device according to claim 1 or 2 characterized in that said semiconductor body (87) further includes a sixth region adjoining said first region (91; 94), being separated from said second , third, fourth and fifth regions by said first region, and being of said opposite conductivity type; in that said first electrode is additionally electrically connected to said sixth region; in that a fourth electrode (B) is included and overlies an area of said first region; and in that a second insulative layer is included and spaces said fourth electrode from said first region: said frtirth electrode, said second insulative layer, and said first region being so constructed and arranged that a second inversion channel (80; 101) within said first region and connecting together said second and sixth regions is included beneath said fourth electrode upon application of a second bias voltage of predetermined polarity and magni tude to said fourth electrode (Fig. 6; Fig. 8). 4. The device according to claim 3 characterized by a distributed emitter bypass current path in the semiconductor body (87), said current path extending from the inte riser of said second region through said second inversion channel (80; 101) and through said sixth region to said first electrode, the resistance of said current path being too high to permit turn-off of the device solely by application of said second bias voltage to said fourth electrode (B). 5. The device according to claim 3 or 4 characterized in that said first and second inversion channels (77; 80) are substantially horizontally aligned with each other where a major surface of a wafer constituting said semiconductor body (87) defines a horizontal plane. (Fig. 6) 6. The device according to claim 3 or 4 characterized in that said first and second inversion channels (100, 101) are substantially horizontally offset from each other where a major surface of a wafer constituting said semiconductor body defines a horizontal plane. (Fig. 8) 7. The device according to one of the preceding claims 3 to 6, characterized in that said third and fourth electrodes (A, B), said first and second insulative layers, and said first and fourth regions (91, 92; 94, 95) are so constructed and arranged that during device turn-off the aggregate current passing through all inversion channels under said third electrode (A) is approximacely equal to the aggregate current passing through all inversion channels under said fourth electrode (B). 8. A semiconductor device characterized by a) a body (59) of semiconductor material including first, second, third and fourth regions (47 to 50) successively joined together in the foregoing order; said first region (47) being separated from said third and fourth regions by said second region (48), and said fourth region (50) being separated from said first and second regions by said third region (49); said first and third regions being of one conductivity type; and said second and fourth regions being of the opposite conductivity type; said body further including a fifth region (61) adjoining said first region, being separated from said second, third and fourth regions by said first region and being of said opposite conductivity type; b) a first electrode (52) electrically connected to said first and fifth regions; c) a second electrode (53) electrically connected to said fourth region; d) a third electrode (58) overlying a portion of saifi first region; and e) an insulative layer (60) spacing said cirri jrrlelectrode from said body; said third electrode, said insulative layer, and said first region being so constructed and arranged that an inversion channel (57) within said first region and connecting together said second and fifth regions is induced beneath said third electrode upon application of a bias voltage of predetermined polarity and magnitude to said third electrode. (Fig. 4) 9. The device according to claim 8, characterized by a distributed bypass carrier current path (55) in the semiconductor body (59), said current path extending from the interior of said second region (48) through said inversiOn channel (57) and through said fifth region (61) to said first electrode (52) the resistance of said current path being too high to permit turn-off of the device solely by application of said bias voltage to said third electrode (58). 10. The device according to one of the preceding claims to 9, characterized in that at least a first portion of said first region (12; 47; 91; 94; 112) has a maximum doping 18 concentration in excess of about 10 impurity atoms per cubic centimeter; at least the part of said second region (13; 48; 113) which is adjacent to said third region (14; 49; 114) has a maxi 16 mum doping concentration below about 1016 impurity atoms per cubic centimeter; said third region (14; 49; 114) has a maximum doping con 1017 centration below about 1017 impurity atoms per cubic cen- timeter; and at least a first portion of said fourth region (15; 50; 92; 95; 115; 123) has a maximum doping concentration in 18 excess of about 10 impurity atoms per cubic centimeter 11. The device according to claim 10, characterized in that said fifth region (21; 61) and/or said sixth region has a maximum doping concentration in excess of about 1018 impurity atoms per cubic centimeter. 12. The device according to claim 10 or 1l characterized in that said inversion channel containing first and/ or fourth region (15; 47; 91; 92; 94; 95; 115; 123) comprises a second portion containing said inversion channel (31; 57; 77; 80;100 101), said second portion having a maXimum doping concentration below about 1017 impurity atoms per cubic centimeter in the area occupied by said inversion channel. 13. The device according to one of the preceding claims 1 to 12, characterized in that said semiconductor body (11; 59; 87) comprises a wafer and said first, second, third and fourth regions (12 to 15; 47 to 50; 91, 92; 94, 95; 112 to 115, 123) each comprises a respective layer substantially parallel to a major surface of said wafer. 14. The device according to one of the preceding claims 1 to 13, characterized in that said semiconductor body (11; 59; 87) comprises silicon. 15. The device according to one of the preceding claims 1 to 14, characterized in that said one conductivity type is P-type and said opposite conductivity type is N-type. 16. The device according to one of the preceding claims 1 to 15, characterized in that said third electrode (27; 58; A; 118) and/or fourth electrode (B) comprises polysilicon. 17. The device according to claim 16, characterized in that said first and/or second insulative layer (120) forms a sleeve around said third or fourth electrode (118), respectively. (Fig. 9) 18. The device according to one of the preceding claims 1 to 17, characterized in that said first and second electrodes (24, 25; 52, 53) are free of electrical connection to said second and third regions (13, 14; 48, 49), respectively, whereby the device can be turned on by noise or thermal current or a combination thereof. 19. The device according to one of the preceding claims 1 to 17, characterized in that said first electrode (125) and/or second electrode (121) includes an electrical connection to said second region (113) or said third region (114), respectively, whereby the sensitivity of the device to turn-on by noise or thermal current or a combination thereof is. reduced. (Fig. 9)

Inventors: TEMPLE, VICTOR ALBERT KEITH
Applicants: GENERAL ELECTRIC COMPANY
Application year: 1982
Main classification: H01L29
IPC codes: H01L29