SEMICONDUCTOR DEVICE

Abstract: Disclosed is a semiconductor body (118), comprising a semiconductor substrate (101) of a first conductivity type, a first semiconductor layer (105) of the first conductivity type formed on the substrate (101), a second semiconductor layer (115) of a second conductivity type, and a first semiconductor region (114) of the second conductivity type formed between the surface of the first semiconductor layer (105) and the sub­ strate (101). The lmpurity concentration of the first semicon­ ductor region (14) is equal to or lower than that of the second semiconductor layer (115).

Description: Semiconductor body This invention relates to an improved semiconductor body comprising both high breakdown voltage bipolar transistors and high speed semiconductor elements. In the field of semiconductor integrated circuit, it is a matter of serious concern to develop a technique which permits producing a semiconductor body in which are formed both high breakdown voltage bipolar transistors and high speed semiconductor elements. However, to form such bipolar devices is contradictory to the formation of such semiconductor elements, rendering it difficult to develop the technique mentioned above. Fig. 1 shows the construction of a prior art semiconductor body used for producing a semiconductor integrated circuit. As seen from the drawing, an n -type epitaxial layer 2 is formed on a p -type semiconductor substrate 1. Also, n+-type buried layers 31 and 32 are selectively formed at the interface between the substrate 1 and the epitaxial layer 2. Further, a recess 4 is formed by etching in the surface region of the epitaxial layer 2 facing the n -type buried layer 3#, whith the result that the distance between the epitaxial layer surface and the buried layer is smaller in an epitaxial layer region 21 above the buried layer 31 than in an epitaxial layer region 22 above the buried layer 32. In a semiconductor body of this construction, high speed semiconductor elements is formed in the epitaxial layer region 21, with high breakdown voltage semiconductor elements formed in the epitaxial layer region 22, so as to form a semiconductor integrated circuit. In the prior art of Fig. 1, however, the presence of the recess 4 renders it difficult to achieve fine processings in forming desired semiconductor elements in the epitaxial layer. Fig. 2 shows the construction of another prior art semiconductor body used for forming a semiconductor integrated circuit. In the prior art of Fig. 2, an n -type first epitaxial layer 12 is formed on a p -type semiconductor substrate 11. Also, n -type first buried layers 131 and 132 are selectively formed at the interface between the substrate 11 and the first epitaxial layer 12. The first buried layer 131 may be omitted in some cases. Further, an n -type second epitaxial layer 14 is formed on the first epitaxial layer 12. As seen from from the drawing, an n -type second buried layer 15 is formed at the interface between the first and second epitaxial layers 12 and 14 in a manner to face the first buried layer 131. In a semiconductor body of this construction, high speed semiconductor elements is formed in the second epitaxial layer 14 above the second buried layer 15, with high breakdown voltage semiconductor elements formed above the first buried layer 132 in a manner to extend through the first and second epitaxial layers 12 and 14. In the prior art of Fig. 2, however, it is necessary to form by means of impurity diffusion a p+ -type isolation region (or a dielectric film like an oxide film acting as an isolation region) extending through the first and second epitaxial layers 12, 14 to reach the substrate 11. What should be noted is that the epitaxial layer consisting of the layers 12 and 14 is so thick that it is necessary to apply a heat treatment at a high temperature for a long time for forming the p+-type isolation region mention above. The heat treatment mentioned causes a severe impurity diffusion from the buried layers 131, 132 and 15, namely, the buried layers are expanded, rendering it very difficult to control as desired the distance between the surface of the second epitaxial layer 14 and the buried layers 15 or 132. It follows that the highspeed and high breakdown voltage semiconductor elements formed between the second epitaxial layer surface and the buried layer 15 and between the second epitaxial layer surface and the buried layer 132, respectively fail to perform satisfactory characteristics. It may be certainly possible to ensure a sufficient distance between the epitaxial layer surface and the buried layer by increasing the thickness -of the epitaxial layer. In this case, however, the p -type isolation region must be made deeper, leading to a severer heat treatment for forming the isolation region and, thus, to a greater expansion of the buried layer. In other words, the above-noted problem can not be solved by increasing the thickness of the epitaxial layer. Incidentally, the prior art shown in Fig. 1 also gives rise to the above-noted problem inherent in the prior art of Fig. 2. An object of this invention is to provide a semiconductor body with a smooth surface in which are formed both high breakdown voltage bipolar elements and high speed semiconductor elements performing satisfactory characteristics. According to this invention, there is provided a semiconductor body, comprising a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the substrate, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, and at least one first semiconductor region of the second conductivity type formed between the surface of the first semiconductor layer and the substrate and having an impurity concentration equal to or lower than that of the second semiconductor layer. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:. Fig. 1 is a cross sectional view showing partly a prior art semiconductor body used for forming a semiconductor integrated circuit; Fig. 2 is a cross sectional view showing partly another prior art semiconductor body used for forming a semiconductor integrated circuit; Figs. 3A to 31 are cross sectional views collectively showing how to produce a semiconductor integrated circuit by using the semiconductor body according to one embodiment of this invention; Figs. 4A to 41 are cross sectional views collectively showing how to produce a semiconductor integrated circuit by using the semiconductor body according to another embodiment of this invention; and Fig. 5 is a cross sectional view showing another means for forming the n -type impurity region and the + p -type impurity region in the manufacture of the integrated circuit shown in Figs. 4A to 41. This invention provides a semiconductor body comprising a first semiconductor layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, and a first semiconductor region of the second conductivity type formed between the surface of the first semiconductor layer and the substrate. Thn impurity concentration of the first semiconductor region is equal to or lower than that of the second semiconductor layer. It should be noted that the major element region of a high breakdown voltage bipolar transistor is formed within the first semiconductor region mentioned above. Also, it suffices to provide an isolation region of the first conductivity type in a manner to extend through the second semiconductor layer alone of the second conductivity type. Thus, the semiconductor body of the present invention permits markedly moderating the heat treating conditions, i.e., impurity diffusing conditions, for forming the isolation region, compared with the prior art shown in Fig. 2. The moderate heat treatment permits suppressing the impurity diffusion from the buried layers of high impurity concentration formed at the interface between the substrate and the first semiconductor layer and between the first and second semiconductor layers, rendering it possible to form both high breakdown voltage bipolar transistors and high speed semiconductor elements performing satisfactory characteristics. To be brief, the breakdown voltage of the bipolar transistor is determined by the thickness of the first semiconductor layer. On the other hand, the thickness of the second semiconductor layer serves to determine the operating speed of the semiconductor elements formed together with the bipolar transistor mentioned above. Also, the moderate heat treatment mentioned previously produces an additional effect. Specifically, the lateral diffusion of impurity is suppressed in the step of forming the isolation region. In other words, the side diffusion of the isolation region can be suppressed, rendering it possible to increase the degree of integration of the produced semiconductor device. Further, the upper surface of the semiconductor body, i.e., the surface of the second semiconductor layer, is not provided with a recess but is smooth. Thus, it is possible to apply fine pattern processings to the semiconductor body. In addition, it is possible to prevent the breakage of the interconnection mounted to the semiconductor body. As described above, the semiconductor body of this invention permits producing a semiconductor device comprising bipolar transistors of high breakdown voltage and semiconductor elements operable at high speed. Of course, the produced semiconductor device is high- in integration degree and in reliability. Example 1 Figs. 3A to 31 collectively show how to produce a semiconductor integrated circuit by utilizing the semiconductor body according to one embodiment of this invention. In Example 1, the integrated circuit comprises an npn bipolar transistor of high breakdown voltage, an npn bipolar transistor operable at high speed, and an integrated injection logic device operable at high speed. Specifically, Fig. 3A shows that an oxide film 102 is formed by thermal oxidation on the main surface of a p -type silicon substrate 101 having a resistivity of 1 to 20 Qocm. The oxide film 102 is selectively etched away so as to provide an opening 103, followed by diffusing in a hot furnace an n-type impurity -such as antimony or arsenic into the silicon substrate 101 thorugh the opening 103 so as to form an n+-type diffusion layer 104 having a sheet resistivity of 5 to 50 Q/2. Then, the remaining oxide film 102 is removed, followed by forming a p -type epitaxial layer 105 having a thickness of 3 ym or more on the surface of the substrate 101 as shown in Fig. 3B. The epitaxial layer 105 has a resistivity of 1 Qcm or more. Also, the heat in the epitaxial growth step causes the impurity contained in the diffusion layer 104 to be diffused into the epitaxial layer 105 so as to form selectively an n+ -type first buried layer 106 around the interface between the substrate 101 and the epitaxial layer 105. Further, an oxide film 107 about 1,000 A thick is formed by thermal oxidation on the entire surface of the epitaxial layer 105 as shown in Fig. 3C, followed by forming a photoresist film 108 on the entire surface of the oxide film 107. The photoresist film 108 thus formed is selectively removed by photolithography so as to provide a window 109 above the buried layer 106. Under this condition, an n-type impurity of large diffusion coefficient, e.g., phosphorus, is introduced through the window 109 into the epitaxial layer 105 by ion implantation under an acceleration energy of 160 to 220 KeV and a dose of 1 to 30 x loll cm¯2 so as to form selectively a phosphorus ion injection layer 110. After the ion implantation, the photoresist film 108 is removed, followed by forming a SiO2 film 111 about 1 pm thick on the thermal oxide film 107 as shown in Fig. 3D. The oxide film 111, which is formed by chemical vapor deposition, is annealed for 10 to 30 minutes at 900 to 1,1000C, followed by selectively etching the oxide film consisting of 107 and 111 so as to provide deffusion windows 1121, 1122 and 1123. It should be noted that the window 1121 is positioned to face the buried layer 106 at least partially. On the other hand, the windows 1122 and 1123 are sufficiently apart from the buried layer 106. Then, an n-type impurity, e.g., antimony or arsenic, is diffused in a hot furnace into the p -type epitaxial layer 105 through the diffusion windows 1121 to 1123 so as to form an n+ -type diffusion layer 1131 having a sheet resistivity of 5 to 50 Q/D and large n+-type diffusion layers 1132 and 1133. In this thermal diffusion step, the phosphous ion injection layer 110 (see Fig. 3C) is converted into an n -type impurity region 114. After After formation of the n -type diffusion layers 1131 to 1133, the oxide films 111 and 107 are completely removed, followed by forming an n -type epitaxial layer 115 having a resistivity of 0.1 to 50 Q*cm and a thickness of 1 Um or more on the p -ype epitaxial layer 105 as shown in Fig. 3E. It should be noted that the heat in this epitaxial growth step causes the impurity contained in the n -type diffusion layers 1131, 1132 and 1133 to be diffused into the n -type epitaxial layer 115 so as to form n -type buried layers 116, 117 and 1172 around the interface between the p -type epitaxial layer 105 and the n -type epitaxial layer 115 and, thus, to prepare a desired semiconductor body 118. Incidentally, the buried layer 116 is connected to the first buried layer 106 formed in advance as apparent from Fig. 3E. On the other hand, the buried layers 1171 and 1172 act as second buried layers. Then, a p-type impurity, e.g., boron, is selectively diffused into the n -type epitaxial layer 11-5 of the + semiconductor body 118 so as to form p -type isolation regions 119 as shown in Fig. 3F. It should be noted that the isolation regions 119 extend across the n -type epitaxial layer 115 to reach the p -type epitaxial layer 105 so as to electrically divide the n -type epitaxial layer 115 into regions 1151, 1152 and 115 After formation of the isolation regions, an n-type impurity, e.g., phosphorus, arsenic or a mixture there of is selectively diffused into the divided regions 115 to 1153 so as to form n+-type deep layers 120, 121 and 122 122 connected to the n -type buried layers 116, 1171 and 1172, respectively. As seen from the drawing, the + divided region 1153 is surrounded by the n -region consisting of the second buried layer 1172 and the deep layer 122. Further, a p-type impurity, e.g., boron, is selectively introduced by ion implantation into the divided region 1151 followed by diffusing the implanted ions so as to form a deep p-type base region 123 having a sheet resistivity of 120 to 250 Q/2 within the divided region 1151. Then, a p-type injector 124 and a p-type external base region 125 each extending to reach the n+-type second buried layer 1172 are formed within the divided region 1153 by means of ion implantation, followed by diffusion. The injector 124 and the external base region 125 are substantially equal in sheet resistivity to the base region 123. Similarly, an annular p-type external base region 126 having a sheet resistivity of 120 to 200 Q/D is formed within the divided region 1152 by means of ion plantation, followed by diffusion. As seen from Fig. 3G, the external base region 126 is shallower than the base region 123 formed in advance within the divided region 1151. Then, a p -type internal base region 127 having a sheet resistivity of 300 to 1,000 Q/O is formed in the region surrounded by the annular external base region 126 by means of ion implantation, followed by diffusion. Further, p -type internal base regions 128 each having a sheet resistivity of 1 to 3 kQ/C are formed in the regions surrounded by the external base regions 125 by means of ion implantation, followed by diffusion. The insulation film 129 formed on the entire surface as seen from Fig. 3H is selectively etched away so as to provide openings 1301 to 1306, followed by forming on the entire surface a polycrystalline silicon (polysilicon) film 131 doped with an n-type impurity such as phosphorus, arsenic or both phosphorus and arsenic. Then, the polysilicon film 131 is heated so as to allow the n-type impurity contained in the polysilicon film 131 to be diffused through the openings 1301 to 130 into the semiconductor region so as to form an n -type emitter region 132 within the base region 123 of the divided region 1151, to form an n -type enlarged region 133 in the surface region of the n+-type deep layer 120 of the divided region 1151, to form an n+-type emitter region 134 within the p -type internal base region 127 of the divided region 1152, to form an n+-type enlarged region 135 in the surface region of the n -type deep layer 121, and to form n+-type collector regions 1361 and 1362 within the p -type internal base regions 128 of the divided region 1153. In the next step, the polysilicon film 131 is selectively etched away so as to allow the openings 1301 to 1306 alone to be filled with the remaining polysilicon film. Then, a second insulation film 129' such as a CVD-SiO2 film or a PSG film is formed on the entire surface followed by selectively removing the second insulation film 129' and the first and second insulation films 129 and 129' so as to provide contact holes 137 to 13712. Finally, a metal film, e.g., AQ, AQ-Si or A#-Si-Cu film, is formed on the entire surface by vacuum vapor deposition, followed by patterning the metal film so as to form the interconnections mounted to the semiconductor regions, as shown In Fig. 31. As seen from the drawing, the interconnections thus formed include an emitter electrode 138 connected via the polysilicon film 131 and the contact hole 1371 to the n -type emitter region 132 formed in the divided region 115 ; a base electrode 139 connected via the contact hole 1372 to the p+-type external base region 123; a collector electrode 140 connected via the polysilicon film 131 and the contact hole 1373 to the n -type region 133 communicating with the first buried layer 106; an emitter electrode 141 connected via the polysilicon film 131 and the contact hole 1375 to the n+-type emitter region 134 formed in the divided region 1152; a base electrode 142 connected via the contact hole 1376 to the p-type external base region 126; a collector electrode 143 connected via the polysilicon film 131 and the contact hole 1377 to the n+-type region 135 communicating with the second buried layer 1171; an electrode 144 acting as a ground lead and connected via the contact hole 1374 to the p -type isolation region 119 serving to electrically isolate the divided regions 1151 and 1152; an electrode 145 acting as a ground lead and connected via the contact hole 1378 to the n+ -type deep layer 122 formed in the divided region 1153; electrodes 1461 and 1462 acting as output leads and connected via the polysilicon film 131 and the contact holes 1379 and 13710 to the n+-type collector regions 1361 and 1362, respectively; an electrode 147 acting as an input lead and connected via the contact hole 13711 to the p-type external base region 125; and an injector electrode 148 connected via the contact hole 13712 to the p-type injector 124. In the semiconductor integrated circuit thus produced, an npn bipolar transistor 149 of high breakdown voltage, an npn bipolar transistor 150 operable at high speed, and an I2L (Integrated Injection Logic) circuit 151 are formed in the divided regions 1151, 1152 and 1153, respectively, as apparent from Fig. 31. To reiterate, the semiconductor body 118 used for producing the semiconductor integrated circuit comprises a p -type semiconductor substrate 101, a p -type first semiconductor layer (epitaxial layer) 105 formed on the substrate 101, an n -type second semiconductor layer (epitaxial layer) 115 formed on the layer 105, and an n -type first semiconductor region (n -type in purity region) 114 formed between the surface of the p -type epitaxial layer 105 and the substrate 101, as seen from Figs. 3E and 31. The impurity concentration of the region 114 is equal to or lower than that of the epitaxial layer 115. What should be noted is that the major portion of the npn bipolar transistor 149 of high breakdown voltage is located in the n -type epitaxial layer 115 and the n -type inpurity region 114. This facilitates formation of the p+ -type isolation region 119 (i.e., seventh semiconductor region) serving to electrically separate the npn bipolar transistor 149 from the npn bipolar transistor 150 operable at high speed and the I2L circuit 151 operable at high speed. Specifically, it suffices for the isolation region 119 to extend across the n -type epitaxial layer 115 alone, rendering it possible to shorten markedly the thermal diffusion treatment for forming the isolation region 119, compared with the prior art semiconductor body shown in Fig. 2. Thus, it is possible to suppress the impurity diffusion from the buried layers 106, 1171 and 1172, (i.e., second semiconductor region, third semiconductor regions) namely, the buried layers can be prevented from expansion in the step of forming the isolation region 119. It follows that it is possible to control as desired the characteristics of the bipolar transistors 149, 150 and the I2L circuit 151. The shortened heat treatment mentioned above also permits suppressing the lateral impurity diffusion so as to prevent the isolation region 119 from being expanded. As a result, it is possible to produce a semiconductor integrated circuit high in integration degree. An additional effect to be noted is that the semiconductor body 118 has a smooth surface, rendering it possible to apply fine pattern processings for forming fine semiconductor regions like base regions, emitter + regions, etc. It should also be noted that the n -type diffusion layer 116 (i.e., sixth semiconductor layer) connected to the n -type first buried layer 106 is formed in the step of forming the n+-type second buried layers 1171. and 1172 as seen from Figs. 3D and 3E. In other words, the diffusion layer 116 extends upward to enter the uppermost semiconductor layer, i.e., n -type epitaxial layer 115. Thus, in order to enable the n+-type deep layer 120 to be connected to the diffusion layer 116, the n -type layer 120 need not be as deep as the thickness of the epitaxial layer 115. The small depth of the n -type layer 120 permits markedly shortening the thermal diffusion time for forming the layer 120 and, thus, produces effects similar to those described previously in conjunction with the isolation region 119. Example 2 Figs. 4A to 41 collectively show how to produce a semiconductor integrated circuit comprising an npn bipolar transistor of high breakdown voltage, an npn bipolar transistor operable at high speed, and an I2L circuit operable at high speed, by utilizing the semiconductor body according to another embodiment of this invention. Specifically, Fig. 4A shows that an oxide film 102 is formed by thermal oxidation on the main surface of a p -type silicon substrate 101 having a resistivity of 1 to 25 n¯cm, followed by selectively etching the oxide film 102 so as to provide openings 1031 to 1033. Then, an n-type impurity such as antimony or arsenic is selectively diffused within a hot furnace through the openings 1031 to 1033 into the substrate 101 so as to form n -type diffusion layers 1041 to 1043 having a sheet resistivity of 5 to 50 Q/D. After -formation of these diffusion layers, the remaining oxide film 102 is removed, followed by forming on the substrate surface a p -type epitaxial layer 105 having a thickness of 3 pm or more and a resistivity of 1 Qcm or more as shown in Fig. 4B. It should be noted that the heat in the epitaxial growth step causes the impurity contained in the diffusion layers 1041 to 1043 to be diffused into the epitaxial layer 105 so as to form n -type first buried layers 1061 to 1063 around the interface between the substrate 101 and the epitaxial layer 105. Then, a thermal oxide film 107 having a thickness of about 1,000 is formed on the entire surface of the epitaxial layer 105, followed by forming a photoresist film 108 on the oxide film 107 as shown in Fig. 4C. The photoresist film 108 thus formed is selectively removed by photolithography so as to provide a window 109 facing the first buried layer 1061, followed by introducing an n-type impurity, e.g., phosphorus, through the window 109 into the epitaxial layer 105 by ion implantation under an acceleration energy of 160 to 220 KeV and a dose of 1 to 30 x 1011 cm 2 so as to form a phosphorus ion injection layer 110. In the next step, the photoresist film 108 is removed, followed by forming again a photoresist film 108' as shown in Fig. 4D. The photoresist film 108' thus formed is selectively removed by photolithography so as to provide windows 109'1 to 109'4, followed by selectively introducing boron, i.e., p-type impurity, into the epitaxial layer 105 through the windows 109'1 to 109'4 by ion implanation under an acceleration energy of 200 XeV and a dose of 1 to 100 x 1014 cm -ê so as to form boron ion injection layers 1521 to 1524 positioned to surround the first buried layers 1061 and 1063. After formation of the boron ion injection layers 1521 to 1524, the photoresist film 108' is removed, followed by forming a SiO2 film 111 having a thickness of about 1 pm on the thermal oxide film 107 by chemical vapor deposition (CVD), as shown in Fig. 4E. Then, the oxide films 107 and 111 is selectively removed so as to provide a diffusion window 1121 partially facing the n+-type first buried layer 1061 and diffusion windows 1122 and 1123 facing the n -type first buried layers 1062 and 1063, respectively. Further, an n-type impurity, e.g., antimony or arsenic, is selectively diffused through the diffusion windows 1121 to 1123 into the epitaxial layer 105 in a hot furnace so as to form n -type diffusion layers 1131, 1132 and-1133 each having a sheet resistivity of 5 to 50 Q/a. As seen from Fig. 4F, the diffusion layer 1131 extends to reach the buried layer 1061. Likewise, the diffusion layers 1132 and 1133 extend to reach the buried layers 1062 and 1063i respectively. In this thermal diffusion process, the impurity contained in the phosphorus ion injection layer 110 is diffused so as to convert the layer 110 into an n -type impurity region 114 (see Fig. 4F). Also, the impurity contained in the boron ion injection layers 1521 to 1524 is diffused so as to convert the layers 1521 to 1524 into p+ -type impurity regions 1531 to 1534. Then, the remaining oxide films 111 and 107 are entirely removed, followed by forming on the p -type epitaxial layer 105 an n -type epitaxial layer 115 having a resistivity of 0.1 to 50 Q-cm and a thickness of 1 pm or more as seen from Fig. 4G. It should be noted that the heat in the epitaxial growth Etep causes the impurity contained in the n+-type diffusion layers 1131 to 1133 to be diffused into the n -type epitaxial .layer 115 so as to form an n+-type diffusion layer 116. Also formed are n -type second buried layers 1171 and 1172 connected to the first buried layers 1062 and 1063, respectively. Further, the impurity contained in the p -type impurity regions 1531 to 1534 is diffused into the n -type epitaxial layer 115 in the epitaxial growth step as seen from Fig. 4G so as to provide a desired semiconductor body 118'. In the next step, a p-type impurity, e.g., boron, is selectively diffused into the n -type epitaxial layer 115 of the semiconductor body 118' so as to form p+-type + isolation regions 119 connected to the p -type impurity regions 1531 to 1534 formed previously as seen from Fig. 4H. Naturally, the isolation regions 119 thus formed serve to electrically divide the epitaxial layer 115 into regions 1151, 1152 and 1153. # Then, an n-type impurity, e.g., phosphorus, arsenic or mixture of phosphorus and arsenic, is selectively diffused into the divided regions 1151 to 1153 so as to form n+-type deep layers 120, 121 and 122. As seen from the drawing, the layer 120 is connected to the n+ -type first buried layer 1061 via the diffusion region 116. Likewise, the layers 121 and 122 are connected to the n -type first buried layers 1062 and 1063 via the second buried layers 117 and 1172, respectively. As seen from the drawing, the deep layer 122 is formed in a manner to surround the divided region 115 Finally, a semiconductor integrated circuit comprising an npn bipolar transistor 149 of high breakdown voltage, an npn bipolar transistor 150 operable at high speed, and an I2L circuit 151 operable at high speed formed in the divided regions 1151, 1152 and 1153, respectively as shown in Fig. 41 is produced as in Example 1. Naturally, it is possible to control as desired the breakdown voltage of the transistor 149 and the high operation speed characteristic of the transistor 150 and the I2L circuit 151 in the semiconductor integrated circuit of Example 2 as in Example 1. In the circuit of Example 1 shown in Fig. 31, the n -type epitaxial layer 115 is electrically divided by the p+-type isolation regions 119. In this case, lateral parasitic transistors are formed by adjacent divided regions 1151 to 1153 and the p -type epitaxial layer 105 below the n -type epitaxial layer 115. Particularly, the parasitic transistors formed between the divided regions 1151 and 1152 and between two adjacent transistors (not shown) of high breakdown voltage exhibit a considerably large value of current amplification factor. In the circuit of Example 2 shown in Fig. 41, however, the p -type impurity regions 1531 to 1534 (i.e., fifth semiconductor regions) connected to the p+-type isolation regions 119 extend across the p -type epitaxial layer 105, rendering it possible to suppress the formation of lateral parasitic transistors in question. As a result, the semiconductor integrated circuit is enabled to exhibit an improved reliablility. Also, the p -type impurity regions 1531 to 1534 extend into the n -type epitaxial layer 115 as apparent from the drawing, leading to a shortened heat treatment for forming the + p -type isolation regions 119. As mentioned previously, the shortened heat treatment permits controlling as desired the characteristics of the produced semiconductor integrated circuit. + It should also be noted that the n -type first buried layers 1062 and 1063 (i.e., fourth semiconductor regions) serve to decrease the sheet resistivity of the n+-type second buried layers 1171 and 1172 connected to the layers 1062 and 1063 trespectively. Thus, it is possible to decrease, for example, the collector resistance of the transistor 150 formed above the n+ -type first buried layer 1062, enabling the transistor 150 to operate at a higher speed. In the Examples shown in the drawings, the n -type impurity region 114 formed within the p -type epitaxial layer 105 is larger (or smaller) in width than the n+-type first buried layer 106 (or 1061) positioned below the region 114. However, it is possible to make the width of the region 114 equal to or smaller (or larger) than that of the buried layer 106 (or 1061) depending on the desired transistor characteristic, etc. of the integrated circuit. Also, the n+-type diffusion region 116 connected to the buried layer 106 (or 1061) is formed within the n -type impurity region 114 in the Examples shown in the drawings. However, it is not absolutely necessary to form the diffusion region 116 within the region 114; it suffices for the diffusion region 116 to contact the n -type impurity region 114 at least partially. In the Examples shown in the drawings, the isolation region 119 is formed of a p+-type diffusion layer. But, it is also possible to use a dielectric material for forming the isolation region 119. Of course, it sufficies for the dielectric material layer, i.e., isolation region, to extend across the n -type epitaxial layer 115, or to contact the p+-type impurity regions (1531 to 1534), rendering it possible to shorten the heat treatment for forming the isolation region and, thus, to suppress the impurity diffusion from the n -type buried layer 1171, etc. Thus, the isolation region 119, even if formed of a dielectric material, permits producing the particular effects described previously in conjunction with Examples 1 and 2. The use of a dielectric material is particularly effective for producing a semiconductor device comprising both a transistor operable at high speed and a transistor of high breakdown voltage because of reducing the prasitic capacitance. In the Examples shown in the drawings, the p-type base region 123 of the bipolar transistor 149 of high breakdown voltage is not in contact with the n -type impurity region 114. But, the base region 123 may be allowed to contact the n -type impurity region 114-. Also, the base region 123 may be allowed to consist of a shallow internal base region low in impurity concentration and a deep external base region high in impurity concentration. In the Examples shown in the drawings, the base regions of the transistors are formed separately from each other. However, it is possible to form a common base region depending on the desired transistor characteristics. For example, it is possible to make the external base region of the high breakdown voltage transistor common with the external base region of the I 2L circuit. It is also possible to make the internal base region of the high breakdown voltage transistor common with the internal base region of the high speed transistor. The use of a common base region permits simplifying the manufacturing process of the semiconductor integrated circuit. Example 1 described previously, ion implantation technique is employed for forming the n -type impurity region 114. But, it is also possible to employ impurity diffusion technique in place of ion implantation technique. In this case, a glass film doped with a low concentration of an n-type impurity, e.g., phosphosilicate glass (PSG) film or arsenic-added glass (AsSG) film, is formed on the SiO2 film 111 provided with a diffusion window. The PSG or AsSG film thus formed is used as the diffusion source for diffusing phosphorus or arsenic into the p -type epitaxial layer 105 so as to form the n -type impurity region 114. In Example 2, ion implantation technique is employed for forming the n -type impurity region 114 and the p -type impurity regions 1531 to 153 Of course, the ion implantation technique may be replaced by impurity diffusion technique in Example 2, too, as seen from Fig. 5. Specifically, the thermal oxide film 107 having a thickness of about 3,000 formed on the p -type epitaxial layer 105 is selectively removed to provide the diffusion windows 1541, 1543 to 1545, followed by forming a boron-addedglass (BSG) film 155 on the entire surface. Then, the BSG film 155 is selectively removed from the diffusion window 1542, followed by forming a PSG film 156 on the entire surface. Naturally, the BSG film 155 and the PSG film 156 thus formed are used as the diffusion sources for forming in the p -type epitaxial layer 105 the n -type impurity region 114 and the p+-type impurity regions 1531 to 1534 in a single or more heating step. Further, ion implantation technique is employed for forming the base regions of the transistors in the Examples shown in the drawings. But, the ion implantation technique may be replaced by thermal diffusion technique which utilizes an insulation film doped with a p-type impurity, e.g., BSG film, as the diffusion source. It should also be noted that the resistivity of the base region described previously in conjunction with Examples 1 and 2 may be changed freely depending on the desired operation characteristics of the resultant transistors. Naturally, the conductivity type of the semiconductor regions may be reversed, i.e., the p-type and n-type regions may be changed into n-type and p-type regions, respectively, in the Examples shown in the drawings. Even if the conductivity type is reversed, the resultant semiconductor device produces effects similar to those described previously. Further, a logic circuit such as an emitter coupled logic (ECL) circuit may be formed in place of the high speed npn bipolar transistor and the I2L circuit formed in the Examples shown in the drawings. It is also possible to form uni-junction transistors like MOS-FETs together with the npn bipolar transistor of high breakdown voltage. As described above in detail, the semiconductor body of this invention permits producing a semiconductor integrated circuit comprising, for example, a bipolar transistor of high breakdown voltage, a bipolar transistor operable at high speed, and an I2L circuit operable at high speed. Of course, the integrated circuit mentioned is-high in integration density and in reliablility.

Claims: Claims: 1. A semiconductor body (118), comprising a semiconductor substrate (101) of a first conductivity type; a first semiconductor layer (105) of the first conductivity type formed on the substrate (101); a second semiconductor layer (115) of a second conductivity type formed on the first semiconductor layer (105); and a first semiconductor region (114) of the second conductivity type formed between the surface of the first semiconductor layer (105) and the substrate (101), the impurity concentration in the region (114) being equal to or lower than that in the second semiconductor layer (115). 2. The semiconductor body (118) according to claim 1, wherein a second semiconductor region (106 or 1061) of the second conductivity type high in impurity concentration is buried around the interface between the substrate (101) and the first semiconductor layer (105). 3. The semiconductor body (118) according to claim 1 or 2, wherein at least one third semiconductor region (1171, 1172) of the second conductivity type, which is high in impurity concentration, is formed around the interface between the first semiconductor layer (105) and the second semiconductor layer (115). 4. The semiconductor body (118) according to claim 3, wherein fourth semiconductor regions (1062, 1063) of the second conductivity type high in impurity concentration are buried below the third semiconductor regions (1171, 1172) around the interface between the substrate (101) and the first semiconductor layer (105). 5. The semiconductor body (118) according to claim 4, wherein the fourth semiconductor regions (1062, 1063) are directly connected to the third semiconductor regions (1171, 1172), respectively. 6. The semiconductor body (118') according to claim 1 or 2, wherein fifth semiconductor regions (1531, 1532) of the first conductivity type high in inpurity concentration are selectively formed across the first semiconductor layer (105) between two adjacent first semiconductor regions (114) or in a manner to surround the first semiconductor regions (114). 7. The semiconductor body (118') according to claim 3, 4 or 5, wherein a fifth semiconductor region (1532 to 1534) of the first conductivity type high in impurity concentration is formed across the first semiconductor layer (105) between the third semiconductor regions (1171, 1172) or in a manner to surround the third semiconductor regions (1171, 1172). 8. The semiconductor body (118') according to claim 3, 4, 5 or 7, wherein fifth semiconductor regions (1531, 1532) of the first conductivity type high in impurity concentration is formed across the first semiconductor layer (105) in a manner to surround the first semiconductor regions (114). 9. The semiconductor body (118, 118') according to claim 2, 3, 4, 5, 6, 7 or 8, wherein a sixth semiconductor region (116) of the second conductivity type high in impurity concentration is formed within the first semiconductor region (114) or around the interface between the first semiconductor region (114) and the first semiconductor layer (105), one end of said sixth semiconductor region (116) being in contact with the second semiconductor region (106, 1061), with the other end extending into the second semiconductor layer (115). 10. The semiconductor body (118, 118') according to claim 1, 2 or 6, wherein a seventh semiconductor region (119) of the first conductivity type high in impurity concentration is formed across the second semiconductor layer (115) in a manner to surround the first semiconductor region (114). 11. The semiconductor body (118, 118') according to claim 3, 4, 5, 7, 8 or 9, wherein seventh semiconductor regions (119) of the first conductivity type high in impurity concentration are selectively formed across the second semiconductor layer (115) between two adjacent first semiconductor regions (114), between the first semiconductor region (114) and the third semiconductor region (1171), and between the third semiconductor regions (1171, 1172). 12. The semiconductor body (118, 118') according to claim 11, wherein the seventh semiconductor regions (119) are connected to the fifth semiconductor regions (1531 to 1534). 13. The semiconductor body (118, 118') according to claim 10, 11 or 12, wherein the second semiconductor layer (115) is electrically divided by the seventh semiconductor regions (119) so as to form an island region (1151) connected to the first semiconductor region (114), a bipolar element (149) of high breakdown voltage being formed within said island region (1151), and another island regions (1152, 1153) within which are formed at least one kind of ordinary semiconductor elements (150, 151). 14. The semiconductor body (118, 118') according to claim 1, 2 or 6, wherein a dielectric film is selectively formed across the second semiconductor layer (115) in a manner to surround the first semiconductor region (114). 15. The semiconductor body (118, 118') according to claim 3, 4, 5, 7, 8 or 9, wherein a dielectric film is selectively formed across the second semiconductor layer (115) between two adjacent first semiconductor regions (114), between the first semiconductor region (114) and the third semiconductor region (1171), and between the third semiconductor regions (1171, 1172). 16. The semiconductor body (118, 118') according to claim 15, wherein the second semiconductor layer (115) is electrically divided by the dielectric film so as to form an island region connected to the first semiconductor region (114), a bipolar element of high breakdown voltage being formed within said island region, and another island regions within which are formed at least one kind of ordinary semiconductor elements. 17. The semiconductor body (118, 118') according to claim 13 or 16, wherein the ordinary semicondcutor element is an integrated injection logic circuit (151) consisting of a lateral pnp transistor comprising a carrier injection mechanism portion as the emitter region, and a vertical npn transistor comprising the base and collector regions of the pnp transistor as the emitter and base regions, respectively. 18. The semiconductor body (118, 118') according to claim 13 or 16, wherein the ordinary semiconductor elements comprise an integrated injection logic circuit (151) and a vertical npn transistor (150) operable at high speed (e.g. ECL).

Inventors: IWASAKI, HIROSHI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1982
Main classification: H01L27
IPC codes: H01L29, H01L21, H01L27