IMPROVED MOTOR SPEED CONTROL SYSTEM

Abstract: An improved motor speed control system for high speed, high resolution motor control applications such as centrifuges. A proportional or proportional plus integral motor control system is provided with improved circuitry which uses digital phase lock techniques to generate a speed difference signal that accurately reflects the difference between the actual and desired speed of the motor. This speed difference signal is used to adjust the speed of the motor until the actual and desired speeds become approximately equal to one another. An error integrating network may then be enabled to eliminate any remaining difference between actual and desired speed, thereby assuring a negligible speed error.

Description: - 1 - IMPROVED MOTOR SPEED CONTROL SYSTEM Background of the Invention In precision speed control systems, such as those used in centrifuges, both a wide range of speeds 5 and high speed resolution are desirable. A centrifuge may, for example, have to operate over a speed range of many thousands of rpm and yet be able to attain and remain at a speed within of only a few rpm of the desired value. One approach to meeting these control 10 requirements has involved the use of phase locked loop type control systems. In such systems a digital refer¬ ence signal that is indicative of the desired speed is compared in phase with a digital actual speed signal produced by the motor tachometer to generate a phase 15 difference signal. The latter signal is then used to change the motor speed as necessary to drive the tach¬ ometer signal into frequency and phase match with the reference signal. While phase locked loop type control systems 20 are adequate for many applications, they suffer from two serious problems. The first of these is that the actual and desired speed signals must have frequencies which are quite close to one another before the circuit can achieve a stable locked condition. This is because 25 the high gain used in the phase comparators of phase locked loop control systems, coupled with the time lag associated with the inertia of the motor, give rise to oscillations when the motor attempts to approach the desired speed from too far away. Accordingly, speed 30 control systems that utilize phase locked loop tech- " niques require circuits which are able to bring the motor speed within the stable capture range of the phase locked loop and then surrender control thereto. This necessarily . greatly complicates the control 35 circuitry. OMPI - 1 - IMPROVED MOTOR SPEED CONTROL SYSTEM Background of the Invention In precision speed control systems, such as those used in centrifuges, both a wide range of speeds and high speed resolution are desirable. A centrifuge may, for example, have to operate over a speed range of many thousands of rpm and yet be able to attain and remain at a speed within of only a few rpm of the desired value. One approach to meeting these control requirements has involved the use of phase locked loop type control systems. In such systems a digital refer¬ ence signal that is indicative of the desired speed is compared in phase with a digital actual speed signal produced by the motor tachometer to generate a phase difference signal. The latter signal is then used to change the motor speed as necessary to drive the tach¬ ometer signal into frequency and phase match with the reference signal. While phase locked loop type control systems are ade.quate for many applications, they suffer from two serious problems. The first of these is that the actual and desired speed signals must have frequencies which are quite close to one another before the circuit can achieve a stable locked condition. This is because the high gain used in the phase comparators of phase locked loop control systems, coupled with the time lag associated with the inertia of the motor, give rise to oscillations when the motor attempts to approach the desired speed from too far away. Accordingly, speed control systems that utilize phase locked loop tech¬ niques require circuits which are able to bring the motor speed within the stable capture range of the phase locked loop and then surrender control thereto. This necessarily . greatly complicates the control circuitry. indicative of the desired motor speed and a digital feedback signal indicative of the actual motor speed. The resulting signal is applied, in analog form, to a summing amplifier which in turn provides a speed con- trol signal to the motor drive circuitry. When the difference between the actual and desired speeds is large, the summing amplifier operates in a saturated or output voltage limited mode to pro¬ vide ' to the motor drive circuitry a speed control signal that rapidly accelerates (or decelerates) the motor. As the difference between the actual and de¬ sired speeds becomes sufficiently small, the summing amplifier comes out of saturation i.e., the summing amplifier reverts to operation in a linear mode, and causes the motor to accelerate more slowly towards the desired final value. Finally, as the difference be¬ tween the actual and desired speeds approaches zero, the output of the summing amplifier will approach a final, steady state value dependent upon the desired motor speed. In applications in which the circuitry of the invention must attain a precisely defined final speed, there may be applied to the summing amplifier an addi¬ tional input signal produced by an integrating circuit which integrates the phase and frequency difference between the actual and desired speed signals. This integrating circuit will accumulate even small differ¬ ences between the actual and desired speed signals to produce a signal that is sufficiently large to elimi- nate any residual, steady state errors in the speed control signal. In this manner, the speed of the motor is forced to assume a " precise value corresponding to that called for by the reference signal. The improved speed difference detector net- work of the present invention comprises a subsystem that includes a digital phase comparator circuit, a VCO O PI — •*- and a low pass filter circuit, each of which is of the type frequently used in phase locked loop circuits. In this subsystem one input of the phase comparator is supplied with a signal produced by digitally combining the output signal of the VCO and the reference signal, the remaining comparator input being supplied with the actual speed signal. One beneficial effect of this arrangement is that it causes the phase locked loop subsystem to produce a signal that is related to the frequency difference between the signals applied there¬ to rather than a signal that is related to the phase difference between those signals. This, in turn, al¬ lows the avoidance of the capture and stability prob¬ lems that resulted from the high gain of the phase comparator which was used in phase locked loop type motor control systems. (A similar result will occur if the connections of the reference and actual speed signals are interchanged. ) As a result, in spite of the fact that digital phase locked loop techniques are used to combine the desired and actual speed signals, the overall control system operates as a true propor¬ tional-type feedback system. Preferably, the desired speed difference sig¬ nal is an analog voltage that is derived from the ana- log input voltage of the VCO. This allows the speed difference detector network of the invention to inter¬ face directly with a summing amplifier in which there may be added to the speed difference signal a correc¬ tion signal such as, for example, a signal produced by an error integrating network which is responsive to the phase and frequency difference between the desired and actual speed signals. Such a correction signal may be desirable to eliminate the steady state error that is inherent in all proportional-type feedback systems. Thus, a motor control system utilizing the circuitry of the present invention has both many of the advantages of digital circuitry, such as freedom from drift, and critical component values, and many of the advantages of analog circuitry, such as easily combinable signal values. These and other features of the present in¬ vention will be described in connection with the ac¬ companying drawing. Description of the Drawings The single drawing is a combined block- schematic diagram of the preferred embodiment of the present invention. Description of the Preferred Embodiment Referring to the drawing, there is- shown an a-c motor 12 having an output shaft 15 for driving a load (not shown) such as a centrifuge or other rotating machine. Operating power is supplied to motor 12 through power leads 17 which connect motor 12 to the output of a variable speed a-c motor drive unit 16. ' The speed at which drive unit 16 drives motor 12 is dependent upon the magnitude of an analog speed control signal .which is applied to drive 16 through an input line 18. As will be explained more fully presently, drive 16 is conventional and need not be of a highly linear or drift-free type. This is because the feed- back provided by the control system of the invention will automatically compensate for any drift or non- linearity in drive 16. Accordingly, the internal structure of drive unit 16 will not be described herein. Associated with motor 12 is a feedback signal generating circuit, here shown as a tachometer 20, which may be mounted on the housing of motor 12, as shown, or in any other suitable manner, and which provides on an output lead 22 a feedback or actual speed signal that is. indicative of the rotational speed of shaft 15. Tachometer 20 is preferably of the type which provides a digital or two-state output signal the frequency (more precisely the repetition rate) of which is directly proportional to motor speed. The duty cycle of this signal is unimportant since the the digital portion of the circuitry of the invention is responsive only to the positive-going edges of the digital signals applied thereto. Also associated with motor 12 is a reference signal generating circuit 24. The latter circuit, which may be of any of a number of well known types, serves to generate on conductor 25 a digital signal the frequency of which is related to the desired speed of motor 12. Circuit. 24 may, for example, comprise an oscillator the frequency of which may be controlled by a manually adjustable potentiometer, thumbwheel switches or an output port of a suitable mini or micro¬ computer. Because the manner in which the reference signal is generated is conventional and forms no part of the present invention, the internal structure there- of will not be described herein. To the end that the actual speed signal from tachometer 20 may be combined with the reference signal from generating circuit 24 to generate a speed differ¬ ence signal suitable for use in controlling motor 12, there is provided the electronic speed control cir¬ cuitry shown in the remainder of the drawing. Broadly speaking, the latter circuitry comprises a main speed control loop including a speed difference detector network 30 and a summing amplifier 35. Also included in the speed control circuitry, although its presence is not essential to the present invention, is a secon¬ dary control loop that includes a digital phase com¬ parator 40, a level shifting network 45, and an inte¬ grating network 50. As will be explained in detail later, the main speed control loop allows the speed of motor 12 to be adjusted over a wide range of speeds, -gτ B.EA O PI without regard to the magnitude of the difference between the initial and desired final speeds. The secondary speed control loop may be (and in the pre¬ ferred embodiment is) provided to reduce or eliminate any steady state speed error in the main speed control loop, thereby assuring that the system provides a precisely specified speed. In the illustrated embodiment summing ampli¬ fier 35 includes an operational amplifier 80 which operates from ±12 volt power supplies (not shown) and which has a non-inverting (+) input that is connected to the mid-point of those power supplies, a point which also serves as the system ground. These connections allow amplifier 80 to provide output voltages which can vary symmetrically with respect to the system ground. Summing amplifier 35 also includes input resistors 76, 77 and 78, through which respective input signals may be applied for summation by amplifier 80, a feedback resistor 82, and a feedback capacitor 84. The latter are preferably chosen to have values such that ampli¬ fier 35 has a low pass filtering characteristic. Because the operation of summing amplifiers is well known, summing amplifier 35 will not be described in detail herein. In the present embodiment, speed difference detector 30 includes a phase locked loop integrated circuit or chip 60 which may be of the type manufac¬ tured under the designation CD4046 by R.C.A. and under similar designations by a number of other manufac- turers, a digital feedback network here shown as an exclusive-OR gate 62, a low pass filter network made up of a resistor 66, a resistor 67 and a capacitor 68, a capacitor 70 and a resistor 72, all of which will be described presently. For the sake of easy cross refer- ence, the leads of chip 60 are labeled with numbers which are the same as the pin numbers used by the -B- manufacturer thereof. Speed difference detector cir¬ cuit 30 also includes an additional exclusive-OR gate 64, which is associated with a biasing feature which will be described later. The power leads of chip 60 (not shown) are connected between ground and the +12 volt power supply. Speed difference detector circuit 30 is most easily understood as a closed-loop subsystem that util¬ izes phase-locked loop circuitry the characteristics of which have been modified.by the addition of a digital signal combining element (such as 62) so that it pro¬ vides frequency rather than phase difference informa¬ tion to the overall system of which it is a part. This frequency or, equivalently, speed difference informa- tion is then used in the main speed control loop of an overall speed control system of the proportional type to control the speed of motor 12. One important advan¬ tage of this arrangement is that the overall speed control system is not subject to the previously de- scribed problems with phase-locked loop type control systems, Another important advantage of this arrange¬ ment is that, unlike previously known proportional type speed control systems, the desired speed difference signal is generated using digital techniques which eliminate problems such as thermal drift and the use of precision components and elaborate calibration pro¬ cedures. Thus, the motor control system of. the in¬ vention has both the flexibility of proportional type speed control systems and the advantages of phase- locked loop type speed control systems. Shown within the outline of integrated cir¬ cuit 60 is a block diagram of those of the circuit net¬ works included therein that are used in practicing the present invention. These networks include a phase comparator or detector 60a, a voltage controlled oscil¬ lator (VCO) 60b, and a source follower network 60c. Phase comparator 60a serves to receive the digital signals on input pins 3 and 14 and to generate on output pin 13 a tri-state digital signal dependent upon the phase angle between the signals on pins 3 and 14. These three states include a zero volt state, a +12 volt state and an open circuit state. Phase comparator 60a has associated therewith the Roman numeral II, the latter being a type number used by the manufacturer to distinguish phase comparator 60a from another selec- table phase comparator (identified by the Roman numeral I) which is present on the same chip. The type I phase comparator is not used in practicing the present inven¬ tion because of its tendency to lock onto harmonics of the VCO frequency. Detailed information concerning the internal structure and operation of phase comparator 60a is hereby expressly incorporated herein by refer¬ ence from pages 488-492 of an R.C.A. publication en¬ titled "RCA COS/MOS Integrated Circuits", published in 1978. VCO 60b serves to receive (at pin 9) the output voltage of phase comparator 60a, after the lat¬ ter has been filtered by low pass filter 66-68, and to generate (at pin 4) a digital signal the frequency of which is proportional to the voltage at pin 9. To this end, resistors 66 and 67 and capacitor 68 of the low pass filter network are connected between pins 9 and 13 and the circuit ground in the manner suggested by the manufacturer, resistor 67 serving to introduce a phase lead into the internal feedback path within network 30. The rate at which the VCO output frequency changes with changes in its input voltage is fixed by capacitor 70 and resistor 72, which are connected to pins 6, 7 and 11 in the manner suggested by the manufacturer. It will be understood that resistor 72 and capacitor 70 should provide a rate of change of frequency with voltage that is reasonable in view of the range of speeds over which motor 12 is to operate. Source follower network 60c receives the fil¬ tered d-c voltage which low pass filter 66-68 applies to input pin 9 and applies to output pin 10 a voltage that is equal thereto. The advantage of using source follower 60c is that it allows pin 10 to supply an out¬ put current of a usable magnitude without loading and therefore affecting the operation of low pass filter 66-68. Because both the frequency of the digital sig¬ nal on output pin 4 and the magnitude of the analog d-c voltage at output pin 10 are fixed by the output vol¬ tage of low pass filter 66-68, it will be seen that the signal at output pin 10 of chip 60 conveys the same information as the digital signal on output pin 4 thereof. In the illustrated embodiment speed differ¬ ence detector 30 uses the above-described phase locked loop circuitry to generate frequency rather than phase difference information about the desired and actual speed signals. This occurs because a digital signal combining element, here shown as an exclusive-OR gate 62, is connected between output pin 4 (the output of VCO 60b) and input pin 3 (one input of phase comparator 60a). As a result of this connection, pin 3 of chip 60 is connected to receive a signal produced by digitally combining or adding the reference signal and the output signal of VCO 60b, while the actual speed signal from tachometer 20 is applied to pin 14. Since the phase locked loop circuitry will change its VCO output fre¬ quency as necessary to make the frequency of the sig¬ nals at the two inputs of its phase detector equal to one another, i.e., to make F VCQ + F BEF = TACH , the frequency of the VCO output signal will equal F TACH ~ F RE tϊιe des ^ red frequency difference signal. Since, as previously explained, the same frequency difference OMPI information is available in analog form at output pin 10, it will be seen that circuit 30 provides frequency difference information having a digital underpinning. The significance of the above frequency difference information is that, since the frequencies of the reference and actual speed signals bear a one to one relationship to desired and actual motor speeds, the frequency difference therebetween is a direct indication of the difference between the actual and desired speed of the motor, i.e., the speed error of the system. As a result, speed difference detector 30 is usable as a part of the.overall proportional type speed control system shown in the drawing. Assume, for example, that motor 12 is operating under steady state conditions. Under these conditions, the frequency of the actual speed signal will be approximately equal to the frequency of the reference signal, causing the speed difference signal on pin 10 of circuit 60 to have a relatively small value. This speed difference signal is supplied to motor drive 16 through input resistor 76 of summing amplifier 35. Leaving aside, for present purposes, the effect of the other signals which are applied to summing amplifier 35 through input resistors 77 and 78, amplifier 35 serves as an inverting ampli- fier which provides to motor drive 16 an analog speed control signal that is proportional to the speed dif¬ ference signal received at pin 10. As is the case with all proportional type speed control systems, the above speed control signal deviates from its ideal, zero value by the amount necessary to supply the required load power and compen¬ sate for system losses such as friction. Since the non-zero speed control signal from summing amplifier 35 requires a non-zero speed difference signal at pin 10, the actual speed signal will not have exactly the same frequency as the reference signal. The amount by which the speed difference signal on pin 10 differs from its ideal zero value is known as the steady state error of the system. Naturally, the higher the gain of speed difference detector 30 and/or summing amplifier 35, the smaller this steady state error will be. The manner in ' which this steady state error may be substantially eli¬ minated will be described later in connection with the secondary speed control loop including networks 40, 45 and 50. If the above-described conditions are changed by, for example, doubling the frequency of the refer¬ ence signal, the speed difference signal at pin 10 will increase substantially. For such relatively large changes in the speed difference signal, the output vol- tage of summing amplifier 35 will be quickly driven to a limiting (saturation) value corresponding to one of the power supply voltages, in this case +12 volts. In this saturated condition, motor drive 16 will be pro¬ vided with a high, substantially constant d-c signal which will cause it to accelerate motor 12 toward its new final value. This acceleration will persist until the frequency of the actual speed signal on conductor 22 approaches sufficiently close to that of the refer¬ ence signal on conductor 25 that the speed difference signal becomes small enough to allow amplifier 80 to come out of saturation. The latter condition is accom¬ panied by a slowing of the acceleration of motor 12, which slowing continues as the frequency of the actual speed signal approaches closer and closer to the fre- quency of the reference signal. Finally, as the fre¬ quency of the actual speed signal becomes approximately equal to that of the reference signal, a new steady state condition is attained at a new value of steady state speed error. As will be explained later in connection with the frequency offset signal, a similar sequence of events (except for a sign reversal), will be understood to occur when a change in the reference signal requires a deceleration of motor 12. Thus, it will be seen that all changes in the speed of motor 10 occur in orderly manner, without the capture and lock- ing problems which are known to be associated with phase locked loop type speed control systems. While the foregoing description involves the application of the actual speed signal to pin 14 of circuit 60 (through an exclusive-OR gate 64 which will be discussed later), and the application of the refer¬ ence signal to exclusive-OR gate 62, a similar signal will appear at pin 10 if the connections of these signals are interchanged. More particularly, the just mentioned interchange of connections will produce a speed difference signal that has the same magnitude as that described above, but with a reversed polarity. Accordingly, interchanging the connections of the reference and actual speed signals may require that the speed difference signal be applied to the non-inverting rather than the inverting input of operational ampli¬ fier 80, or that an additional, inverting operational amplifier be connected between pin 10 and amplifier 0. Thus, it is important only that one input of phase comparator 60a is supplied with one of the reference and actual speed signals, while the remaining input of phase comparator 60a is supplied with a signal produced by combining the output signal of VCO 60b with the other of those signals- In the event that it is desirable to reduce or eliminate the above-described steady state speed error, this may be accomplished by using the illus¬ trated secondary speed control loop including phase comparator 40, level shifting network 45, and integrat¬ ing network 50. Also associated with the secondary speed control loop is a relay 88 and a relay control circuit 90 which together serve to enable integrating OMPI network 50 only when the speed of motor 12 is close to its steady state value. Generally speaking, the secon¬ dary speed control loop utilizes the phase and fre¬ quency difference between the reference and actual speed signals to generate a . correction signal which, when added to the speed difference signal from detector network 30, results in a signal which allows the speed error of the system to be driven even closer to its ideal, zero value. Stated differently, the use of the secondary speed control loop with an integrating net¬ work effectively converts the illustrated control system to a proportional-plus-integral type control system, and thereby eliminates steady state errors. The operation of the secondary speed control loop will now be described. Phase comparator 40 is preferably of the same type as phase comparator 60a of speed difference detector 30. Phase comparator . 40 may, for example, be a part of a second phase locked loop integrated circuit of the type described above in which only the phase comparator portion thereof is used. Because,the inputs of phase comparator 40 are connected to receive the reference and actual speed signals, the voltage at the output thereof will be dependent upon the phase and frequency difference between those sig- nals. In order that the tri-state (zero volt, +12 volt, open circuit) digital signal produced by phase comparator 40 may be converted to a tri-state (-6 volt, +6 volt, zero volt) signal suitable for application to integrating network 50, there is provided a level shifter network 45 which includes resistors 92, 93 and 94. These resistors are connected in the illustrated manner between the previously mentioned +12 and -12 volt power supplies. Phase comparator 40 cooperates with level shifting network 45 to supply integrating network 50 with a digital signal that includes a suc¬ cession of +6 and -6 volt pulses, separated by zero volt intervals. When the reference frequency is great¬ er than the tachometer frequency, the average value of this digital signal has a first polarity and a magni¬ tude that is dependent upon the magnitude of the dif¬ ference between those frequencies. When the reference frequency is less than the tachometer frequency, the average value of this digital signal has the opposite polarity and a magnitude that is again dependent upon the magnitude of the difference between those frequen¬ cies. As a result, it will be seen that integrating network 50 is provided with a digital correction signal having a magnitude and sign that is dependent upon the magnitude and sign of the speed error of the system. This, in turn, allows integrating network 50 to accumu¬ late the effect of the steady state speed error of the main control loop and to use the same to provide an analog correction signal which, when added to the output of the main speed control loop in summing ampli¬ fier 35, forces the actual speed of motor 12 to become substantially equal to that called for by the reference signal. In view of their just-described function, it will be apparent that phase comparator 40 and level shifting network 45 may be replaced by an additional speed difference detector of the type described in connection with network 30 above. If the latter re¬ placement is made, it may also be necessary to use biasing circuitry of the type which will be described later in connection with gate 64 and resistor 78. In the illustrated embodiment integrating network 50 includes an operational amplifier 95, having an input resistor 96, a feedback capacitor 97, and a resistor 98 through which capacitor 97 may be dis- charged when a contact 99 of relay 88 is closed by relay control network 90. Except for resistor 98 and O PI contact 99, integrating network 50 is of a conventional design and serves to produce an output voltage that is proportional to the integral of its input voltage. As a result, integrating network 50 converts the above- described digital correction signal into an analog correction signal which is suitable for application to summing amplifier 35. In view of its conventional design (except as noted), integrating network 50 will not be described in detail herein. While integrating network 50 is beneficial in eliminating the small steady .state error of the main speed control loop, it can lengthen the time required for the motor speed to reach a new steady state value after a large change in desired speed. This is because the large phase and frequency differences that are associated with large changes in desired speed will quickly cause the output voltage of amplifier 95 to be driven to its limiting value. Since this output vol¬ tage can only be driven from its limiting value by integrating a digital correction signal of the opposite polarity, the integrating network causes the circuit to overshoot, undershoot and generally exhibit undesirable dynamic response characteristics. In order to eliminate these undesirable ten- dencies, integrating network 50 is provided with switch contact 99 which, with resistor 98, serves to maintain integrating capacitor 97 in a discharged condition until the actual motor speed is relatively closed to the desired motor speed. Once the latter condition exists, integrating network 50 is effectively enabled by relay control network 90 which opens short circuit¬ ing contact 99 and thereby allows capacitor 97 to begin charging. Integrating network 50 then operates in the previously described conventional manner to eliminate the steady state speed error of the main speed control loop. ^ T&EAl OMPI To the end that the state of contact 99 may be controlled so as to automatically accomplish the above-described result, contact 99 may be the normally open contact of a relay 88 which is in turn controlled by relay control network 90. The latter network is preferably arranged so that relay 88 closes switch con¬ tact 99 whenever the output voltage of summing ampli¬ fier 35 is more than a predetermined number of volts positive or negative from zero. In this manner, when the output voltage of amplifier 35 is sufficiently close to its final value to indicate that the motor is operating at approximately the desired speed, network 90 deenergizes relay 88. This, in turn, opens contact 99 and enables the previously described integrating action. Since relay control network 90 may comprise a window comparator circuit of a type that is well known to those skilled in the art, the internal structure thereof will not be described in detail herein. Because the zero to +12 volt power supply connections of phase locked loop circuit 60 prevent the output voltage thereof from assuming negative values, circuit 60 cannot deal effectively with negative speed difference values. In order to eliminate this problem, it is desirable to in effect bias phase locked loop circuit 60 so that it has a positive non-zero output voltage when the actual and desired motor speeds are equal to one another. Through the use of this bias, phase locked loop circuit 60 may be made to respond symmetrically to both positive and negative speed errors. To the end that the above-mentioned biasing may be accomplished, a digital frequency offset signal produced by a suitable oscillator (not shown) may be combined with the actual speed signal on conductor 22, in an exclusive-OR gate 64, before being applied to input pin 14 of phase locked loop circuit 60. This causes pin 14 of circuit 60 to be supplied with a digi¬ tal signal having a frequency equal to the sum of the actual speed signal and the frequency offset signal. This, in turn, forces circuit 60 to match the reference signal frequency with the last mentioned summation signal rather than with the actual speed signal. As a result, the speed difference signal on pin 10 will have a non-zero value when the actual and desired speeds are equal to one another. Stated differently, the speed difference signal on pin 10 will be approximately equal to zero only when a predetermined frequency difference exists between the reference and actual speed signals. For general purpose applications a frequency offset signal having a frequency corresponding roughly to the mid point of the VCO frequency range will be. suitable. While the above-described biasing improves the performance of phase locked loop circuit 60, it will introduce a sizable error in the speed control signal unless it is compensated for. One manner in which this compensation may be accomplished is the application of an analog bias cancelling signal to a further input of summing amplifier 35, through resistor 78. The effect of this cancelling signal is to sub¬ tract off, in summing amplifier 35, the component of its total input current that is attributable to the above-mentioned frequency offset signal. In this manner, the effect of the frequency offset signal is confined to detector 30, where its effects are benefi¬ cial, and is prevented from reaching motor drive 16 where its effects could be detrimental. It will be understood that the introduction of the frequency offset signal at exclusive-OR gate 64 has no effect on the previously mentioned interchangeability of the connections of the reference and actual speed signals. In view of the foregoing, it will be seen that the speed control system contemplated by the present invention includes at least a main speed con¬ trol loop having an improved speed difference detector network. This speed difference detector comprises a phase locked loop circuit. As a result, there is imparted to the main speed control loop the accuracy and self-adjusting properties of digital phase locked loop circuitry without also imparting thereto the capture and locking problems that are associated with phase locked loop type control systems. The speed control system of the invention preferably also in¬ cludes a secondary speed control loop which is capable of eliminating any steady state errors in the main speed control loop. As a result, the speed control system of the invention cannot only be adjusted over a wide range of speeds, but can also settle, within great precision, to the desired value in that range.

Claims: -__:u- 1. A motor speed control system of the type having a first signal generator for generating a digital feedback signal indicative of the actual speed of a motor, a second signal generator for generating a digital reference signal indicative of the desired speed of the motor, a phase comparator having first and second inputs and an output, a voltage controlled oscillator having an input and an output, and a connection between the output of the phase comparator and the input of the voltage controlled oscillator, characterized by: (a) digital circuit means for combining the signal at the output of the voltage controlled oscil¬ lator with one of the feedback and reference signals, said digital circuit means having ah output connected to one input of the phase comparator, (b) means for connecting the remaining input of the phase comparator to receive the other of the feedback and reference signals, (c) whereby the signal at the input of the voltage, controlled oscillator comprises a speed difference signal that varies in accordance with the difference between the actual and desired speed of the motor. 2. The control system of claim 1 in which the digital circuit means is an exclusive-OR gate. 3. The control system of claim 1 further includ¬ ing a third signal generator for generating a digital frequency offset signal, second digital circuit means for combining the digital frequency offset signal with the signal to be applied to said remaining input of the phase comparator, and means for connecting the second digital circuit means between the third signal generator and said remaining input of the phase OMPI comparator, whereby a bias is introduced into the speed difference signal. 4. The control system of claim 3 further including a summing amplifier having a first input connected to receive the speed difference signal and a second input connected to receive a d-c bias voltage sufficient to cancel said bias. 5. The control system of claim 1 further including a summing amplifier, means for generating an analog correction signal the magnitude and sign of which varies in accordance with the integral of the phase and frequency difference between the feedback and reference signals, and means for applying said speed difference and correction signals to the summing amplifier. 6. The control system of claim 5 further including switching means for disabling the correction signal generating means when the magnitude of the speed difference signal exceeds a predetermined value. 7. A motor speed control system of the type having a first signal generator for generating a digital feedback signal indicative of the actual speed of a motor, a second signal generator for generating a digital reference signal indicative of the desired speed of the motor, a phase locked loop integrated circuit having first and second phase comparator inputs, a phase comparator output, a voltage controlled oscillator input and a voltage controlled oscillator output and a low pass filter connected between the phase comparator output and the voltage controlled oscillator input, characterized by: (a) digital circuit means for combining the signal at the output of the voltage controlled oscillator with one of the feedback and reference signals, said digital circuit means having an output connected to one of the phase comparator inputs, (b) means for connecting the other phase comparator input to receive the other of the feedback and reference signals, (c) whereby the signal at the voltage controlled oscillator input comprises a speed difference signal that varies in accordance with the difference between the actual and desired speed of the motor. 8. The control system of claim 7 in which the , digital circuit means is an exclusive-OR gate. 9. The control system of ci im 7 further including a third signal generator for generating a digital bias signal, second digital circuit means for combining the digital bias signal with the signal to be applied to said other phase comparator input, and means for connecting the second digital circuit means to said other phase comparator input, whereby a bias is introduced into the speed difference signal. 10. The control system of claim 9 further including a summing amplifier having first input connected to receive the speed difference signal and a second input connected to receive a d-c bias voltage sufficient to cancel the effect of the digital bias signal. 11. The control system of claim 7 further including a summing amplifier, means for generating an analog correction signal the magnitude and sign of which varies in accordance with the integral of the phase and frequency difference between the feedback and reference signals, and means for applying said speed difference and correction signals to the summing amplifier. 12. The control system of claim 11 further including switching means for disabling the correction signal generating means when the magnitude of the speed difference signal exceeds a predetermined value. 13. A speed difference detector network for generating a speed difference signal that varies in accordance with the difference between a digital feedback signal indicative of the actual speed of a motor and a digital reference signal indicative of the desired speed of that motor, characterized by: (a) a digital phase comparator having first and second inputs and an output, (b) a voltage controlled oscillator having an input for receiving an analog input voltage and an output for supplying a digital output voltage, (c) a low pass filter connected between the output of the phase comparator and the input of the voltage controlled oscillator, (d) means for applying one of the feedback and reference signals to one input of the phase comparator, (e) combining means for digitally combining the digital output voltage of the voltage controlled oscillator with the other of the feedback and reference signals, (f) means for connecting said combining means to the other input of the phase comparator, and O H -2*4- (g) means for connecting the input of the voltage controlled oscillator to the output of the speed difference detector network. 14. The speed difference detector network of claim 13 in which the combining means comprises means for digitally adding the signals applied thereto. 15. The speed difference detector network of claim 13 in which the phase comparator and voltage controlled oscillator comprise parts of a phase locked loop integrated circuit.

Inventors: FRANKLIN ROBERT C, PARKES CHRISTOPHER W, FRANKLIN, ROBERT, C., PARKES, CHRISTOPHER, W.
Applicants: BECKMAN INSTRUMENTS INC, BECKMAN INSTRUMENTS, INC.
Application year: 1982
Main classification: G05D13
IPC codes: H02P23