DYNAMIC RANDOM ACCESS MEMORY DEVICE

Abstract: A dynamic random access memory device comprises one-transistor, one-capacitor-type memory cells (C₀₀ ∼ C 127,127 ) in rows and columns and dummy cells (DC₂₀′ ∼ DC 2,127 , DC₂₀″ ∼ DC 2,127 ″, DC₂₀‴ ∼ DC 2,127 ‴) in rows. The capacitors (C d ) of the dummy cells are charged to a high power supply potential (V CC ) by one or more charging tran­ sistors (Q A , Q A ′) clocked by a reset clock signal (⊘ R ). The capacitors (C d ) of the dummy cells are discharged to a low power supply potential (V SS ) by one or more transistors (Q B , Q B ′) clocked by an operation clock signal (⊘ WL ) having a potential lower than the high power supply potential (V CC ).

Description: DYNAMIC RANDOM ACCESS MEMORY DEVICE The present invention relates to a semiconductor device, more particularly, to a dynamic random access memory (RAM) device comprising one-transistor, one-capacitor-type memory cells. In a MOS dynamic RAM device, one-transistor, one -capacitor-type memory cells have been put to practical use, and, in addition, such memory cells are often used since they are advantageous in respect to integration density. In this type of memory cells, each cell comprises a capacitor and a transistor which serves as a switching element for charging and discharging the capacitor. Therefore, the presence or absence of charges in the capacitor represents data 11111 or "0". The memory cells are arranged at intersections between word lines and bit lines. In addition, dummy cells are arranged at intersections between dummy word lines and bit lines. In the prior art, these dummy cells are similar in construction to the one-transistor, one-capacitor-type memory cells in that they comprise a capacitor, a transistor, and an additional transistor for resetting the capacitor. However, in recent years, dummy cells comprising only one capacitor have been developed (See: IEEE Journal of Solid-State Circuits, vol. SC-15, No. 2, pp. 184-189, Apr. 1980). A dynamic RAM including such one-capacitor dummy cells is advantageous in respect to integration density and reduces the load of the operation clock generator. In a dynamic RAM device including the above-mentioned one-capacitor-type dummy cells, a discharging transistor and a charging transistor are provided in series between two power supplies (VCC t Vss), and their connection node is connected to a dummy word line connected to the dummy cells. The control of this device is carried out as follows. First, the dummy word line is discharged by the discharging transistor clocked by a reset clock generator. In this state, the dummy word line is at level Vss. Then, the dummy word line is charged by the charging transistor clocked by an operation clock generator so that the potential of the dummy word line is pushed up to the power supply voltage (VCc). In the above-mentioned dynamic RAM device, however, in order to push up the potential of the dummy word line, the operation clock generator must generate a potential higher than Vcc + Vth , where Vth is the threshold voltage value of the charging transistor. As a result, the operation clock generator has to incorporate a charge-pumping circuit or a bootstrap circuit for generating such a higher potential, Therefore, the operation clock generator becomes complex, and, accordingly, the operation speed of the operation clock generator, that is, the access speed of the device, becomes low. It is, therefore, a principal object of the present invention to provide a dynamic RAM device comprising one -transistor, one-capacitor-type memory cells in which the access speed is high. It is another object of the present invention to provide a dynamic RAM device comprising one-transistor, one-capacitor-type memory cells in which correct data can be read out even if the fluctuation of a power supply voltage is generated. According to the present invention, there is provided a dynamic RAM device; first;Jand second power supplies, the potential of the first-po68-r supply being lower than that of the second power supply; a first clock generator for generating a first clock signal having a potential higher than that of the second power supply and a second clock signal having a potential lower than or equal to the potential of the second power supply;a second clock generator for generating a third clock signal having a potential higher than the potential'of the second power supply alternately with the first and second clock signals; a plurality of word lines selectively driven by the first clock signal; a plurality of pairs of bit lines precharged by the second power supply in response to by the third clock signal; a plurality of sense amplifiers, each sense amplifier being arranged between one pair of the pairs of bit lines, for sensing the difference in potential between the pairs of bit lines; a plurality of one-transistor, one-capacitor -type memory cells in rows and columns, each memory cell being connected to one of the word lines and to one of the bit lines; a plurality of dummy cells, each dummy cell comprising a capacitor and a connection node, the capacitor having an electrode connected to one of the bit lines and another electrode connected to one of the connection nodes; at least one charging means, each means being connected to each of the connection nodes of the dummy cells respectively and driven by the third clock generator, for charging the capacitor of each of the dummy cells; and at least one discharging means, each means being connected to each of the connection nodes of the dummy cells respectively and driven by the second clock signal, for discharging the capacitor of each of the dummy cells. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below contrasting the present invention with the prior art and referring to the accompanying drawings, wherein: Figure 1 is a block circuit diagram illustrating a prior art dynamic RAM device; Fig. 2 is a partial circuit diagram of the circuit of Fig. 1; Fig. 3 is a circuit diagram illustrating another prior art dynamic RAM device; Figs. 4A and 4B are timing diagrams of the signals appearing in the circuit of Fig. 3; Fig. 5 is a circuit diagram illustrating a first embodiment of the dynamic RAM device according to the present invention; Figs. 6A and 6B are timing diagrams of the signals appearing in the circuit of Fig. 5; Fig. 7 is a circuit diagram illustrating a second embodiment of the dynamic RAM device according to the present invention; ; Figs. 8A and 8B are also timing diagrams of the signals appearing in the circuit of Fig. 5; and Fig. 9 is a circuit diagram illustrating third embodiment of the dynamic RAM device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the prior art dynamic RAM devices will be explained with reference to Figs. 1, 2, 3, 4A, and 4B. In Fig. 1, for example, a 16 kbit (precisely, 16,384 bit) RAM device is illustrated. In the figure, one-transistor, one-capacitor-type memory cells C00, C01, ....., Co, 127 C63,0, C63,1, ....., C63,127, C64,0' C64,1' ....., C64,l27 I 12710 t 127,1 t and C127,127 in rows and columns are arranged at intersections between word lines WL@ r ....., WL 63 ' W164 t ....., and WL127 and bit lines BLo, BLo, BL1, BL1, ....., Bl 127, and BL 127, and sense amplifiers so, s1, ....., and s127 in a row are ---- -- arranged between bit line pairs BL0 , BLo , BL1 BL11, ......, BL@@@, and BL, @@@ Further, dummy cells Dc@@ DC 1 , , and 1,127 in a row are connected to the terminals of bit lines BLo, Bl1, ....., and BL127 and to dummy word line DWL1 while dummy cells DC20 , DC21 , ....., and DC 2, 127 in a row are connected to the terminals of bit ---- ---- --- lines BLo, BL1, ....., and BL 127 and to dummy word line DWL2. In Fig. 1, #WL is an operation clock signal for driving word lines WL0, ....., WL 63, WL 64, ....., and WL 127 and dummy word lines DWL1 and DWL2. #R is d reset clock signal for resetting capacitor QR (not shown in Fig. 1 but shown in Fig. 2) of each dummy cell and for precharging bit lines BL, t BLo t BL1 t BL1 27 and BL 127 The selection of word lines WL@, WL1, ......, and WL127 is carried out by word decoders DEC, and, simultaneously, the selection of dummy word lines D1 and DWL2 is also carried out by row decoders DEC. For example, when one of word lines WL0 0 through WL63 is selected, dummy word line DWL2 is selected while when one of word lines WL 4 through WL127 is selected, dummy word line DWL1 is selected. Such selection is carried out by transfer gates TG1 TGO ' TG63, TG , , TG127 , and TG128 which are switched on by word decoders DEC so as to transfer clock signal fWL In more detail, word decoders DEC decode row address signals A0, A0, A1, A1, ....., A5 and A5 so that one of transfer gates TG0 through TG127, that is, one of word lines WLo through WL 127 , is selected, and, in addition, row decoders DEC decode row address signal A6 or A6 so that one of transfer gates TG and TG128 , that is, one of dummy word lines DWL1 and DWL2 , is selected. In Fig. 2, which is a partial circuit diagram of the circuit of Fig. 1, word line WLO and dummy word line DWL2 of Fig. 1 are illustrated in detail while the other word lines and dummy word line DWL1 are omitted. That is, if word line WL is selected, dummy word line DWL2 on the opposite side regarding the sense amplifiers is always selected. Each of memory cells C00, C01, ......, and C0, 127 comprises capacitor Cm and transistor Qm while each of dummy cells DC20 , DC21 , , and DC2,127 comprises capacitor Cd , transistor Qd t and transistor QR. In this case, the capacity of each capacitor Cd of the dummy memory cells is set to be about half the capacity of each capacitor C of the memory cells. During the standby mode, reset m clock generator Ck2 generates reset clock signal R having a potential higher than VCC + Vth. 1 where Vth is the common threshold voltage value of the enhancement transistors. As a result, capacitors Cd of dummy cells D20 , D21 , and DC2 127 are discharged, and, simultaneously, bit lines BL2, BL@, BL@, BL@, ....., BL@@@@, and BL@@@ are precharged to potential VCC Next, during the selecting mode, operation clock generator CK1 supplies clock signal through on-state transfer gates TGo and TG128 to word line WL@ and dummy word line DWL@, which means that word line WLo 0 and dummy word line DWL2 are selected. As a result, for example, when the potential of capacitor C of m memory cell C00 is high (which corresponds to data "l't, for example), the potential of bit line BL, does not decrease while when the potential of capacitor C of memory cell C00 m is low (which corresponds to data "0"), the potential bit line BL decreases. On the other hand, in dummy cell DC20 since capacitor Cd is charged, bit line BLO decreases. In any case, since the capacity of capacitor C is different m from that of capacitor Cd , there is generated a difference in potential between bit lines BL0 and BL0. Such difference in potential is sensed, that is, enlarged, by sense amplifier Sg and then the difference is read out. In Fig. 2, however, the load of operation clock generator CK1 is dependent on not only the capacity of word line WL , the capacity of the gates of transistors Qm of memory cells C00 , C01 , , and C02, 127 , and the like, but also is dependent on the capacity of dummy word line DWL2 , the capacity of the gates of dummy cells DC20 DC@@, ....., DC@ 127, and the like. Therefore, the load of operation clock generator CK1 is large, and thereby the operation speed of the device is reduced. Figure 3 is a circuit diagram illustrating another prior art dynamic RAM device which is disclosed in Fig. 8 of the IEEE Journal of Solid-State Circuits, vol. SC-15, No. 2, pp. 184-189, Apr. 1980. In Fig. 3, word line Wflo and dummy word line DWL1 are illustrated in detail while the other word lines and dummy word line DWL2 are omitted. That is, if word line WL is selected, dummy word line DWELL on the same side regarding sense amplifiers S1', S2' and S63' is always selected. Each of dummy cells DC10', DC11' , and DC1 ,l27 comprises only one capacitor Cd I thereby remarkably reducing the area occupied by the dummy cells in the chip as compared with the dummy memory cells of Fig. 2. and QB are charging and discharging transistors, respectively, for dummy word line DWL1 , that is, for capacitors Cd Charging transistor QA is clocked by clock signal #WL of operation clock generator CK1 while discharging transistor QB is clocked by clock signal 4)R of reset clock generator CK2. Therefore, the load of operation clock generator CK1 is dependent on the capacity of charging transistor QA1 and the like in addition to the capacity of word line WLA0, the capacity of the gates of transistors Qm of memory cells C00, C01, ....., and C0, 127, and the like, thereby reducing the load of operation clock generator CR1. The operation of the circuit of Fig. 3 will now be explained with reference to Fig. 4A regarding only bit lines BL0 and Bl1 since sense amplifier S0, responds to the pair of bit lines Bl0 and Bl1. Assuming memory cell C00 stores data "1", that is, that capacitor C of memory m cell C00 is charged, during the standby mode, the reset clock signal is high (VCC + Vth + a), discharging transistor GR is turned on so that capacitors Cd of dummy cells DC10', DC1111 .. , 1 DC1112611 and DC1, 127 are discharged, and, accordingly, the potential of dummy word line DWL1 remains low (V SS = ground level). Simultaneously, bit lines BL0, Bl0, BL1, BL1, ....., Bl26, BL126 BL127, and BL127 are precharged to level VCC Next, during the selecting mode, the potential of clock signal R is changed from level VCC + Vth + a to level VSS x and, in addition, the potential of clock signal 4)WL is changed from level VSS to level VCC + Vth + a. As a result, the potential of word line WL selected by the decorder DEC is changed in common phase with the potential of clock signal #@@@ in addition, discharging transistor Q@ is turned off while charging transistor QA is turned on. As a result, the potential of the selected dummy word line DWL is changed in common phase with the potential of clock signal tWL-. Simultaneously, the bit lines assume-a floating state. In this case, since bit line BLO is connected to dummy word line DWL, by the capacitive coupling of capacitors Cd , the potential of bit line BLo is pulled up in proportion to the capacitance ratio of bit line BLo to dummy word line DWL1. That is, the potential of dummy word line DWL1 causes the potential of bit line BLo to be slightly positive relative to the potential of bit line BL1. Thus, a difference AVBL in potential is generated between bit lines BLo and BL1 , and, during the sensing mode, such difference is sensed by sense amplifier S0'. As a result, the lower-side potential of bit line Bt is decreased to V SS Similarly, assuming that memory cell C00 stores data "0", that is, that capacitor Cm of memory cell C00 is discharged, the potential of dummy word line DWL1 also causes the potential of bit line BLO to be high. However, ourrent flows from bit line BL0 into capacitor Cm of memory cell C00 , and, accordingly, the potential of bit line BL, is pulled down in proportion to the capacitance ratio of capacitor C of memory cell C00 to bit line Blo. Then, as m illustrated in Fig. 4B, the potential of bit line BL becomes slightly negative relative to the potential of bit line Bull. Thus, a difference #VBL in potential is generated between bit lines BL and BL1 , and, during the sensing mode, such difference #VBL' in potential is sensed by sense amplifier S0'. As a result, the lower-side potential of bit line BL, is decreased to Vss. In the dynamic RAM device of Fig. 3, however, in order to push up the potential of dummy word line DWL1 to level Vcc t operation clock generator CK1 must generate a Vth that is, a potential of potential higher than VCC + VCC + Vth + a, and, accordingly, Operation clock generator CK must incorporate a charge-pumping circuit or a bootstrap circuit which is not provided with a capability of driving quickly a heavy load including both dummy word line DWL1 and word line W0. . Therefore, the operation speed of row selection, that is, the access speed of the device, becomes low. Figure 5 is a circuit diagram illustrating a first embodiment of the dynamic RAM device according to the present invention. In Fig. 5 the elements which are the same as those of Fig. 3 are denoted by the same reference numerals as in Fig. 3. As the figure shows, if word line WLo 0 is selected, dummy word line DWL2 on the opposite side regarding sense amplifiers S@, S@, ....., and S127 is selected. In addition, charging transistor QA is connected to reset clock generating circuit CK2 while discharging transistor QB is connected through transfer gate TG128 to operation clock signal generating circuit Ck1 which generates clock pulses fWL and #WL' in reciprocal phase with reset pulse fR. The operation of the circuit of Fig. 5 regarding only bit lines BL, and BLo will now be explained with reference 0 to Fig. 6A. Assuming that memory cell C00 stores data "1", that is, that capacitor C of memory cell C is charged, m 00 during the standby mode, the reset clock signal 4)R is high (VCC + Vth + a), charging transistor QA is turned on so that capacitors C, of dummy cells DC@@, DC@@', ..... DC2,1261, and DC2,127' are charged, and, accordingly, the potential of dummy word line DWL remains high (VCC) 2/ ------ Simultaneously, bit lines BL, , BL, , BL1 , BL1 , ....., BL126 t BL126 t BL127 , and BL127 are precharged to level VCC Next, during the selecting mode, the potential of clock signal 4)R is changed from level VCC + Vth + a to level VSS , and, contrary to this, the potential of clock signal WL is changed from level VSS to level VCC + Vth + a. As a result, the potential of a selected word line WLo is changed in response to the potential of clock signal 4). When clock signal fWL is changed, clock generator CK1 simultaneously generates clock signal #WL' which is changed from VSS to VCC in common phase with clock signal m Thus, charging transistor QA is turned off while discharging transistor QB is turned on. As a result, the potential of dummy word line DWL2 is changed in opposite phase to the potential of clock signal 4)'. Simultaneously, the bit lines assume a floating state. In this case, since bit line BL0 is conhected to dummy word line DWL2 by the capacitive coupling of capacitors Cd, the potential of bit line Bt0 is pulled down by an amount in proportion to the capacitance ratio of dummy cell capacitor Cd to bit line Bt0. That is, the potential of dummy word line DWL1 pulls down the potential of bit line BL so that of it is slightly negative relative to the potential of bit line BL0. Thus, a difference AVBL in potential is generated between bit lines BL0 and BL0, and, during the VSS sensing mode, such difference is sensed by sense amplifier As As a result, the lower-side potential of bit line BLO is decreased to V33 Similarly, assuming that memory cell C00 stores data "0", that is, that capacitor C of memory cell C00 is in discharged, the potential of dummy word line DWL2 also pulls down the potential of bit line BL0. However, current flows from bit line BL, into capacitor C of memory cell C00 m and, accordingly, the potential of bit line BL0 is also pulled down by the capacity ratio of capacitor C of memory m cell C00 to bit line BL0. Dummy cell capacitor Cd is designed to have about a half of the capacitance of one memory cell capacitor C . Then, as illustrated in Fig. 6B, m the potential of bit line BL0 becomes slightly negative relative to the potential of bit line BLo. Thus, a difference in potential AVBLI is generated between bit lines BLO and BL0 , and, during the sensing mode, such difference in potential is sensed by sense amplifier Sg As a result, the lower-side potential of bit line BL is decreased to In the dynamic RAM device of Fig. 5, operation clock generator CX1 generates clock signals fWL having level VCC + Vth +a and fWL' having level VCC However, it should be noted that the load driven by the clock signal QWL which requires a high level VCC + Vth + a is reduced. As stated above, a clock signal having a level higher than VCC is generated by a charge-pumping circuit, bootstrap circuit, or the like which usually has only an ability to drive a small load. Therefore, if the load which requires clock signal having level higher than VCC is small, the operation speed of operation clock generator CK1 becomes high. As a result, the access speed of the device becomes high. Note that generally in a memory device, the highest priority of design is to reduce the access time. Therefore, although reset clock generator CK2 incorporates a charge -pumping circuit or a bootstrap circuit for generating a potential higher than VCC t this is not disadvantageous since the reset operation does not affect the access speed. Figure 7 is a circuit diagram illustrating a second embodiment of the dynamic RAM according to the present invention. In Fig. 7, each of dummy cells DC20"', DC2111', ....., , and DC2 127"' comprises discharging transistor QBO for discharging capacitor Cd , instead of discharging transistor QB of Fig. 5. In this case, discharging tran sistors B1 ' are smaller than discharging transistor QB of Fig. 5. However, the operation of the circuit of Fig. 7 is substantially the same as that of the circuit of Fig. 5. Note that, in this case, dummy word line DWL2, is not directly connected to capacitors C of dummy cells DC20", DC21", ....., and DC2,127". In addition, the potential at node 1 , N1, ....., or N127 of Fig. 7 corresponds to the potential of dummy word line DWL2 of Fig. 5. Figures 8A and 8B are also timing diagrams of the signals appearing in the circuit of Fig. 5 (or 7). In Figs. 8A and 8B, it is assumed that the potential of the power supply VCC fluctuates at the transition from the standby mode to the selecting mode. That is, since charging transistor 0A is relatively large, the potential of dummy word line DWL2 rapidly follows the fluctuation of the power supply potential VCC Contrary to this, since the bit lines have a large capacitance and, in addition, the precharging transistors are relatively small so as to limit current therethrough, the potential of the bit lines responds very slowly to fluctuation of the power supply voltage VCC In Fig. 8A, which corresponds to Fig. 6A, the power supply potential is decreased from VCC to VCC - AVCC In this case, the potential of bit line BLo is not as decreased as in Fig. 6A. That is, in the case of reading data "1", the difference AVBL in potential becomes small. Consequently, the sensing speed is reduced, and an erroneous read operation may result. Contrary to this, in Fig. 8B, which corresponds to Fig. 6B, the power supply potential is increased from VCC to VCC + AVCC In this case, the potential of bit line BLO is decreased greatly as compared with Fig. 6B. That is, in the case of reading data 11011, the difference AVBL' in potential also becomes small. Consequently, the sensing speed is reduced, and an erroneous read operation may result In order to avoid fluctuation of the potential of the bit lines due to fluctuation of a power supply potential, according to the present invention, capacitor Cd of the dummy cell can also be charged-by using the potential of the corresponding bit line. Figure 9 is a circuit diagram illustrating a third embodiment of the dynamic RAM device according to the present invention. In Fig. 9, each of dummy cells DC20"', DC21", , and DC2,1271,1 comprises charging transistor instead of charging transistor QA of Fig. 7. That is, charging transistor QAW of dummy cell -DC20,11 is connected between bit line BLO and node No Therefore, during the 0 standby mode, even when power supply potential VCC fluctu ates rapidly, the potential at node No t ----, or N127 of capacitors Cd remains stable since the potential at node N@, N@, ....., or N127 follows the potential of bit line BLO ' 1 tBL1 , -..., or BL127 , which potential does not fluctuate so much. Therefore, the above-mentioned unfavorable difference in potential, which reduces the sensing speed and may result in an erroneous read operation is not generated. As explained hereinbefore, the dynamic RAM device according to the present invention is advantageous, as compared with the prior art as illustrated in Fig. 3, in that the access speed is high since it is unnecessary that the operation clock generator CK1 drives a heavy load requiring a potential higher than Vcc in the selecting operation.

Claims: CLAIMS 1. A dynamic random access memory device; first and second power supplies (VSS t Vcc), the potential of said first power supply (ass) being lower than that of said second power supply (Vcc); a first clock generator (CK1) for generating a first clock signal (4)j having a potential higher than the potential of the second power supply and a second clock signal (#WL') having a potential lower than or equal to the potential of said second power supply; a second clock generator (CK2) for generating a third clock signal (4) R having a potential higher than the potential of said second power supply alternately with the first and second clock signals; ; a plurality of word lines (WLo X WL127) selectively driven by said first clock signal; a plurality of pairs of bit lines (BL0 BL0 # BL127, BL127) precharged by said second power supply in response to said third clock signal; a plurality of sense amplifiers (Sg S127), each sense amplifier being arranged between one pair of said pairs of bit lines, for sensing the difference in potential between said pairs of bit lines; a plurality of one-transistor, one-capacitor -type memory cells (C@@ # C127 127) in rows and columns, each memory cell being connected to one of said word lines and to one of said bit lines; ; a plurality of dummy cells (DC20' X DC2,1271), each dummy cell comprising a capacitor (Cd) and a connection node (N0 # N127), said capacitor having an electrode connected to one of said bit lines and another electrode connected to one of said connection nodes; at least one charging means, each charging means being-connected to each of said connection nodes of said dummy cells respectively and driven by said third clock generator, for charging said capacitor of each of said dummy cells; and at least one discharging means, each discharging means being connected to each of said connection nodes of said dummy cells respectively and driven by said second clock signal, for discharging said capacitor of each of said dummy cells. 2. A device as set forth in claim 1, wherein said discharging means comprises a transistor (QB) having a drain connected to said connection nodes of said dummy cells (DC20' "'DC2,127,), a a gate for receiving said first clock signal, and a source connected to said first power supply. 3. A device as set forth in claim 1, wherein said discharging means comprises a plurality of transistors (QB' ), each transistor being incorporated into one of said dummy cells (DC20" "' DC2,12711) and having a drain connected to one of said connection nodes of said dummy cells, a gate for receiving said second clock signal, and a source connected to said first power supply. 4. A device as set forth in claim 1, wherein said charging means comprises a transistor (Q ) having a drain connected to said second power supply, a gate for receiving said third clock signal, and a source connected to said connection nodes of said dummy cells (DC20' DC, DC2,127,). 5. A device as set forth in claim 1, wherein said discharging means comprises a plurality of transistors (QA')' each transistor being incorporated into one of said dummy cells (DC@@"' #DC2 127"') and having a drain connected to said respective bit line, a gate for receiving said third clock signal, and a source connected to one of said connection nodes of said dummy cells.

Inventors: NAKANO, MASAO, NAKANO, TOMIO, OHIRA, TSUYOSHI, TAKEMAE, YOSHIHIRO, TSUGE, NORIHISA
Applicants: FUJITSU LIMITED
Application year: 1982
Main classification: G11C11
IPC codes: G06F11, G11C11