MASTERSLICE INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME

Abstract: In a masterslice integrated circuit, a plurality of input and output logic gates and a plurality of internal logic gates are arranged in the form of an array. A custom-made wiring pattern is arranged between the input and output logic gates and the internal logic gates. At least one of the logic gates comprises a plurality of PNP transistors (Q₁₁ ∞ Q₁₅) and a plurality of output stage circuits (OS A , OS B ). In addition, by the custom-made wiring pattern, one of the output stage circuits is connected to the emitter of at least one of the PNP transistors to form one of the logic gates.

Description: MASTERSLICE INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME The present invention relates to a masterslice integrated circuit device. More particularly, it relates to a semiconductor device having a large number of input/output buffers and a logic gate array and to a method for manufacturing the same by using masterslice technology. In general, in a large-scale integrated (tSI) semiconductor circuit of complex logic, customers may request a preferred design. Therefore, when designers design logic LSI layout patterns in accordance with the customers' requirements, the design time becomes remarkably long, and, therefore, the manufacturing cost of logic LSI semiconductor circuits becomes high. Therefore, for logic LSIs, it is essential to use a standard layout pattern so as to shorten the design time and lower the manufacturing cost. Several approaches have been taken to meet this requirement. One approach is masterslice (gate array) technology in which a standard layout pattern mainly for active areas and a custom-made layout pattern mainly for interconnections are prepared and merged into mask patterns for designing masks. On the other hand, in an internal circuit of a logic LSI semiconductor device, a signal is transmitted by a small driving power and a small signal amplitude to enhance the operation speed. However, when a signal is transmitted from the internal circuit of the logic LSI semiconductor device to an external circuit outside the logic LSI semiconductor device, a large driving power is necessary. In addition, when there is a difference in the signal level between the internal circuit and the external circuit, level conversion is also necessary. For this purpose, a large number of input output buffers are provided on the perimeter of the logic tS semiconductor device. Of course, such buffers are also manufactured by using masters lice technology. In a prior art method for a semiconductor device having a large -umber of buffers, a plurality of buffer patterns are prepared as a standard layout pattern In this case, each buffer pattern has a definite number of inputs and a definite --umber of outputs. For example, each buffer pattern has three inputs and one output. Next, a custom -made layout pattern is prepared for interconnections between the internal circuit and the inputs of each buffer. In the above-mentioned prior art, however, since each buffer pattern has a definite number of inputs, the number of connection configurations between the internal circuit and the buffers is limited. It is desirable to provide a masters lice integrated circuit device having a large number of input/output buffers and to provide a method for manufacturing the sfflme by using masters lice technology in which the number of connection configurations between the internal circuit and the buffers is increased, Accord#ng to one -aspect of the present invention, there is provided a masters lice integrated circuit device including a plurality of input and cetput logic gates disposed in a peripheral region thereof, a plurality of internal logic gates disposed in a central region thereof, and a custom-made wiring pattern disposed between the logic gates to desired function, the logic gates be-ng arranged in the form of an array, at least one of the bc-c gates comprising: a plurality of PNP transistors, each of the PNP transistors having a base for receiving a first signal-and an emitter for providing a second signal corresponding to the first signal; and a plurality of ctput stage circuits which are arranged at positions so that at least one of the PNP transistors can be connected to c-e of the output stage circuits by the custom -made wiring pattern, one of the output stage circuits being connected to the emitter of at least one of the plurality of PNP transistors to form one of the logic gates. A¯ordang to a second aspect of the present invention, there is provided a method for manufacturing a masters lice integrated circuit device including a plurality of input and output logic gates disposed in a peripheral region thereof, a plurality of internal logic gates disposed in a central region thereof, and a custom-made wiring pattern disposed between the logic gates to desired function, the logic gates being arranged in the form of an array, the method comprising the steps of: forming a plurality of PNP transistors, each of the PNP transistors having a base for receiving a first signal and an emitter for providing a second signal corresponding to the first signal; forming a plurality of output stage circuits at positions so that at least one of the PNP transistors can be connected to one of the output stage circuits, each of the plurality of output stage circuits having an input and an output terminals; and electrically connecting the emitter of at least one of the plurality of PNP transistors to the input terminal of one of the plurality of output stage circuits to form one of the logic gates. Reference will now be made, by way of example to the accompanying drawings, wherein Fig. 1 is an equivalent circuit diagram illustrating a prior art masters lice integrated circuit device manufactured by using masterslice technology; Fig. 2 is a logic circuit diagram of the circuit of Fig. 1; Fig. 3 is an equivalent circuit diagram illustrating an embodiment of a masters lice integrated circuit device embodying the present invention; Figs. 4A through 4D are logic circuit diagrams of the circuit of Fig. 3; Fig. 5 is a circuit diagram in which the circuit of Fig. 1 is used as an output buffer of a logic LSI gate array; Fig. 6 is a circuit diagram in which the circuit of Fig. 3 is used as an output buffer of a logic LSI gate array; Figs. 7A and 7B are cross-sectional views illuss trating NPN and PNP transistors; and Fig. 8 is a plane view of an output buffer of Fig. 4A. In Fig. 1, GA and GB designate buffer patterns constructed as transistor-transistor logic (TTL) patterns. Each buffer pattern GA and GB comprises resistors R1 through R4, transistors Q1 through Q4 , and a diode D1 to form a three-input NAND circuit. The transistor Q1 is a multi -emitter transistor having three emitters. The transistor Q2 serves as an inverter. The transistors Q3 and Q4 form an output stage. That is, when one of the transistors Q3 and Q4 is turned on, the other is turned off. The standard layout pattern represented by the buffer patterns GA and GB is connected to an internal circuit (not shown) by a custom-made layout pattern for innerconnections. That is, inputs 11 , 12 r 16 of the buffer patterns GA and GB are connected selectively to logic gates of the internal circuit. Note that, generally, in a masterslice integrated circuit device, a plurality of such input and output buffers which are also logic gates are arranged in a peripheral region, while a plurality of such internal logic gates are arranged in a central region. In addition, both types of the logic gates are arranged in the form of an array. In the buffer pattern GA t when at least one of the inputs Ii , 12 ,and 13 is at a low potential, a current flows from the power supply VCC through the resistor R1 and the base and emitter of the transistor Q1 to the internal circuit. As a result, the transistor Q2 is turned off, and, accordingly, the transistors Q3 and Q4 are turned off anvil on, respectively, so as to cause the output OA tu be at a high potential. Contrary to this, when all the inputs Il through 13 are at a high potential, a current flows from the power supply VCC through the base and collector of the transistor Q1 to the base of the transistor Q2. As a result, the transistor Q2 is turned on, and, accordingly, the transistors Q3 and Q4 are turned off and on, respectively, so as to cause the output OA to be at a low potential. In Fig. 1, however, since the buffer pattern GA or GB has a definite number of inputs, such as three inputs, the number of connection configurations between the internal circuit and the inputs of the buffers is limited. For example, as illustrated in Fig. 2, which is a logic circuit of the buffer patterns GA and GB of Fig. 1, each of the inputs I1 through 16 is connected to one logic gate of the internal circuit (not shown). In addition, if only one logic gate of the internal circuit is connected to the buffer pattern GA by a custom-made layout pattern, only one input, such as the input Il , is used while the other inputs 12 and 13 are unused. Therefore, wasted areas are created. Further, if four logic gates of the internal circuit are connected to the buffer pattern GA by a custom-made layout pattern, another kind of transistor Q1 must be prepared and must be connected by the custom-made layout pattern to the buffer pattern GA t and this procedure becomes complex. In Fig. 3, which illustrates an embodiment of the present invention, as a standard layout pattern for buffers which are, in this case, output buffers, two kinds of patterns are prepared. That is, a plurality of input stage patterns IS1 , IS2 , ..., IS5 are regularly arranged and a plurality of output.stage patterns OS and OSB are regularly arranged. The input stage patterns are connected by a custom-made layout pattern (not shown) to the output stage patterns OSA and OSB so as to form output buffers. Each input stage pattern, such as the IS1 , comprises a PNP transistor Q11 having a base for an input Ii , an emitter for an output, and a grounded collector. On the other hand, each output stage pattern, such as the OSA , comprises NPN transistors Q2 ,Q3 , and Q4 , resistors R1 t R2 t R3 and R4 , and a diode D1. That is, the PNP transistors Qll through Q15 correspond to the transistor Q1 of Fig. 1. Note that in Fig. 1 the transistors are all of the NPN type while in Fig. 3 each input stage pattern comprises a PNP transistor and each output stage pattern comprises NPN transistors. A custom-made layout pattern is provided to selectively connect the emitters E1 through E5 of the input stage patterns to the bases B A and B B of the output stage patterns. Various configurations of the buffers GA' and GB' are realized. For example, when the emitter E1 is connected to the base B A while the emitters E2 through E5 are connected to the base B t the buffer GA' serves as an inverter while the gate GB' serves as a four-input NAND circuit, as illus traced in Fig. 4A. When the emitters E1 and E2 are connected to the base B A while the emitters E3 , E4 , and E5 are con nected to the base B t the gate GA' serves as a two-input NAND circuit while the gate GB' serves as a three-input NAND circuit, as illustrated in Fig. 4B. When the emitters E1 E2 and E3 are connected to the base BA while the emitters E4 and E5 are connected to the base BB byt the gateGA' serves as a three-input NAND circuit while the gate GB' serves as a two-input NAND circuit, as illustrated in Fig. 4C. When the emitters E1 through E4 are connected to the base B A while the emitter E5 is connected to the base BB t the gate GA serves as a two-input NAND circuit while the gate GB' serves as an inverter, as illustrated in Fig. 4D. The number of configurations of the buffers GA' and GB' is increased by increasing the number of input stage patterns or PNP tran sistors. Thus, in an embodiment of the present invention, it is possible to -increase the degree of freedom regarding the number of inputs as compared with some prior devices. In the circuit of Fig. 3, when the emitters E1 and E2 of the transistors Q11 and Q12 are connected to the base BA of the transistor Q2 of the output stage pattern OSA , a two-input NAND circuit GA' is realized, as illustrated in Fig. 4B. Therefore, when at least one of the inputs Il and 12 is at a low potential, the output OA is at a high potential. That is, when the input II is at a low potential, the transistor Q11 is turned on. As a result, most of the current flowing through the resistor R1 flows into the emitter and collector of the transistor Q11 t and, accordingly, the transistor Q2 is turned off so as to turn on the transistor Q3 and turn off the transistor Q4. Therefore, the output OA is at a high potential. On the other hand, when both of the inputs I1 and 12 are at a high potential, the transistors Q11 and Q12 are turned off so that most of the current flowing through the resistor R1 flows into the base emitter of the transistor Q2. Accordingly, the transistor Q2 is turned on so as to turn off the transistor Q3 and turn on the transistor Q4. Therefore, the output OA is at a low potential and thus NAND logic operation is performed When the input #I1 is at a low potential, the base current flowing through the emitter base of the transistor Q11 is 1/hFE of the collector current flowing through the emitter and collector of the transistor Qll Therefore, this base current is very small, which means that the driving power of the internal circuit of the NAND circuit GA' can be small. That is, the fan-out (the number of outputs) of the internal circuit can be increased. In Fig. 3, even if all the transistors Qll through Q15 are replaced by diodes, various configurations of buffers as illustrated in Figs. 4A through 4D can be obtained by a custom-made layout pattern. In this case, however, when an input or a cathode of one diode is at a low potential, the current flowing through the resistor R1 flows through the diode into the internal circuit, thereby decreasing the fan-out, or the number of outputs of the internal circuit. In Fig. 3, if Q11 through Q15 are NPN transistors formed in individual isolated regions of a semiconductor device and each NPN transistor has a collector selectively connected to the base B A or the base BB , a base for an input, and a grounded emitter, the buffers GA' and GB' serve as OR circuits, not as NAND circuits. If such individual NPN transistors are used for a NAND logic, it is necessary that the base of each transistor be connected by a connection to the resistor R1 and that the collector of each transistor be connected by a connection to the base BA. As a result, the connections become complex, and, in addition, the collector capacity can become large. Contrary to this, in embodiments of the invention, the collector of each PNP transistor is commonly grounded, and therefore the collector capacity can be kept smali In Fig. 5, the buffer pattern GA of Fig. 1 is connected to an internal logic gate IG of an internal circuit. The logic gate IG is also constructed as a TTL circuit comprising transistors Q21 and Q22 resistors R5 , R6 b R7d and R8 and a diode D2. In this case, the diode D2 and the resistor R8 form a clamp circuit for clamping the high level of the output voltage V0. In the buffer pattern GA t the threshold voltage Vth of the input Il is represented by: Vth =VBC +VBE1 +VBE2 - VBE3 where VBC is the base to collector voltage of the transistor Qli V is the base to emitter voltage of the transistor Q2; VBE2 is the base to emitter voltage of the transistor Q4; and VBE3 is the base to emitter voltage of the transistor Ql. If it is assumed that VBEl X VBE2 ¯ VBE3 VBE ¯ 0.8V and VBE3 - V BC ¯ O.lV, then Vth =tu 1.5V In addition, the low-level of the output OA equals the collector-emitter voltage V CE of the transistor Q4 , that is, about 0.1V, while the high-level of the output OA equals VCC - 2VBE , that is, about 3.5 V, when VCC = 5V. On the other hand, in the internal logic gate IG, the threshold voltage Vth is represented by Vth =VBC +VBEl- VBE2 where V BC is the base to collector voltage of the transistor Q21 t VBEl is the base to emitter voltage of the transistor Q22 , and V BE is the base to emitter voltage of the transistor Q21' If it is assumed that VBE2 - V BC ¯ 0.lV and = VBEl = VBE2 =# VBE="j0. 8V, then Vth ¯ 0.7V. In addition, the low-level of the output V0 is the collector to emitter voltage VCE (X0.1V) of the transistor Q22 while the high-level of the output V0 is clamped by the clamp circuit formed by the diode D2 and the resistor R8. In Fig. 5, in order to match the buffer pattern GA to the internal logic gate IG, the high-level of the output V0 of the gate IG should be higher than the threshold voltage Vth (X1.5V) of the buffer pattern GA. Therefore, it is desirable to enlarge the amplitude of the output Vn by cutting the clamp circuit away, which can be disadvantageous in respect to operation speed. In Fig. 6, the buffer pattern GA' of Fig. 3 is connected to the internal logic gate IG. In the buffer pattern GA' the threshold voltage Vth of the input I, is represented by: Vth =VBEl +VBE2 VBE3 where VBEl is the base to emitter voltage of the transistor Q2' VBE2 is the base to emitter voltage of the transistor Q4 , and VBE3 is the base to emitter voltage of the transistor 011 If it is assumed that VBEl = VBE2 = BE3 = BE , then Vth ¯ VBE ¯ 0.8V, which is half of the threshold voltage of the prior art. In the internal logic gate IG, the high-level of the output V0 is clamped by a series circuit of the two diodes D2 and D3 at about l.5V since the forward voltage of each diode is equal to or smaller than 0.8V. Therefore, the swing or amplitude of the output V0 is about 0.1 to 1.5V. In addition, when one of the diodes D2 and D3 is constructed as a Schottky barrier diode, the amplitude of the output V0 is about 0.1 to 1.ZV. In this case, the threshold voltage of the buffer pattern GA' is approximately an intermediate value of the amplitude of the output V0 , which voltage reasonably drives the buffer pattern GA'. In a structure embodying the present invention, there are two kinds of transistors, that is, NPN transistors and PNP transistors. Such two kinds of transistors are formed in a semiconductor device. For example, in Figs. 7A and 7B, reference numeral 71 designates a semiconductor substrate lightly doped with N-type impurities. An N -type buried layer 72 having a high concentration is formed on the substrate 71, and, in addition, an N-type epitaxial layer 73 is deposited thereon. Within the epitaxial layer 73 are formed a P+-type impurity diffusion layer 74, a P+-type impurity diffusion layer 75, an N+-type impurity diffusion layer 76, and an N -type impurity diffusion layer 77. In Fig. 7A, the layers 77, 75, and 73 are an emitter region, a base region, and a collector region, respectively, of an NPN transistor while in Fig. 7B, the layers 75 and 73 and the substrate 71 are an emitter region, a base region, and a collector region, respectively, of a PNP transistor. Note that the collector region of the PNP transistor of Fig. 7B can be commonly grounded by grounding the substrate 71. In addition, in Fig. 7B, the buried layer 72 is small; however, the buried layer 72 can be omitted. Further, in Fig. 7B, the base width is large so that the value hFE is small; however, such a small value hFE is sufficient for a buffer. In the circuit of Fig. 8, a custom-made layout pattern (innerconnections) is illustrated by the shaded portions. The circuit of Fig. 8 corresponds to that of Fig. 4A. In embodiments of the present invention, since the input stage of a buffer is constructed as single-emitter PNP transistors which are prepared without connections, the input stage of each buffer is voluntarily altered by a custom-made layout pattern and thereby the buffers canlb-e better - utilized. In addition, the input threshold voltage of each buffer can be small, and therefore suitable for a high speed LSI semiconductor circuit having a small amplitude.

Claims: CLAIMS 1. A masters lice integrated circuit device including a plurality of input and output logic gates disposed in a peripheral region thereof, a plurality of internal logic gates disposed in a central region thereof, and a desired wirirsg pattern connecting said logic gates to provide desired circuit functioN,said logic gates being arranged in the form of an array, at least one of said logic gates comprising: a plurality of PNP transistors #Qll X each of said PNP transistors having a base for receiving a first signal and an emitter for providing a second signal corresponding to said first signal; and a plurality of output stage circuits (OSA , OSB) which are arranged at positions so that at least one of said PNP transistors can be connected to one of said output stage circuits by said desired wiring pattern, one of said output stage circuits being connected to the emitter of at least one of said plurality of PNP transistors to form one of said logic gates. 2. A device as set forth in claim 1, wherein each of said output stage circuits includes: first and second power supply terminals (GND, Vac); a first NPN transistor (Q2) having a base connected to the emitter of at least one of said plurality of PNP transistors, a collector connected to said second power supply terminal, and an emitter; a second NPN transistor (Q3) having a base connected to the collector of said first NPN transitor, a collector connected to said second power supply terminal, and an emitter; and a third NPN transistor (Q4) having a base connected to the emitter of said first NPN transistor, a collector connected to the emitter of said second NPN transistor and serving as one output, and an emitter connected to said first power supply terminal. 3. A device as set forth in claim 2, wherein each of said output stage circuits further includes a diode (D1) having an anode connected to the emitter of said second NPN transistor and a cathode connected to the collector of said second NPN transistor. 4. A method for manufacturing a masterslice integrated circuit device including a plurality of input and output logic gates disposed in a peripheral region thereof, a plurality of internal logic gates disposed in a central region thereof, and a -desired wiring pattern disposed between said logic gated to provide- desired circuit funczions, said logic gates being arranged in the form of an array, said method comprising the steps of: : forming a plurality of PNP transistors, each of said PNP transistors having a base for receiving a first signal and an emitter for providing a second signal corresponding to said first signal; forming a plurality of output stage circuits at positions so that at least one of said PNP transistors can be connected to one of said output stage circuits, each of said plurality of output stage circuits having an input and an output terminals; and electrically connecting the emitter of at least one of said plurality of PNP transistors to the input terminal of one of said plurality of output stage circuits to form one of said logic gates, using the said desired wiring pattern.

Inventors: MITONO, YOSHIHARU, OMICHI, HITOSHI, TANIZAWA, TETSU
Applicants: FUJITSU LIMITED
Application year: 1982
Main classification: H01L27
IPC codes: H01L27, H03K19