METHOD FOR MANUFACTURING A MASK TYPE READ ONLY MEMORY

Abstract: A method of manufacturing a mask type read only memory having a plurality of MOS transistors is described, in which source and drain regions of certain of the M0S transistors are shorted in accordance with a requested program, after an interconnection wiring layer has been formed on the semiconductor substrate. The source and drain regions are interconnected by means of a channel (83) created by ion-implantation of a suitable impurity. The shorted MOS transistors are then covered by a protective layer (84), the contour of which indicates those MOS transistors which have been shorted.

Description: The present invention relates to Read Only Memories and particularly to a method for manufacturing a mask typ Read Only Memory and to a method of manufacturing the same in which the time for writing data into the ROM is short. A prior art mask type Read Only Memory is shown in Figures 2 to 3. A gate insulating film 12 and a gate electrode 14 are formed on a P type semiconductor substrate 10. An N⁺ region 16 is formed between gate electrodes 14 by a diffusion process. In the Read Only Memory shown in Figures 1 and 2, MOS transistors Q11, Q21 and Q31 and MOS transistors Q12, Q22 and Q32 are connected in series; load transistors are not shown. The number of gates provided in the semiconductor devices depends on the specification given by a user. For example, in order to render the MOS transistor Q22 nonoperative, the source and drain of the MOS transistor Q22 are shorted by means of an ion implanted layer 18. However, such a process of ion implantation is performed at an early stage in the wafer making process. This results in a considerable delay before a user will receive the ROMs. Proposals to cope with this problem are disclosed in United States Patent Specification No. 4,080,718. In these proposals, an impurity is introduced into the channel region by ion implantation in the final stages of the wafer making process, in order to render the MOS transistor into a depletion type. In the final stages, a PSG (phosphosilicate glass) layer is etched away and the impurity is then introduced into the semiconductor substrate by an ion-implantation process. The semiconductor device fabricated is delivered with the implanted regions kept exposed. Accordingly, its reliability is poor. In GB-A-2 017 406, a method of manufacturing a NOR-type ROM is described which may comprise the steps of selectively forming a first insulating layer for a field region and a gate insulating layer, defining the source and drain areas by etching this first insulating layer and subsequent ion implantation, performing a field oxidation to cover source and drain regions with an insulating layer, depositing a polysilicon film over the entire slice, defining gate electrodes by etching this polysilicon film, depositing a thick layer of silicon oxide to insulate the metal level from the polysilicon level and either removing this thick layer only over the gates or over the entire ROM array area. Subsequently metal contacts and interconnections are defined in the usual manner. In the next step programming is performed by using either a further protective oxide layer or a photoresist layer as an implant mask. In the case of using a photoresist layer, a protective oxide layer may be deposited on the ROM area after the programming step. Thus, either the programmed cells are left without a covering of thick protective oxide or all the ROM cells are covered in a similar manner. The present invention seeks to provide an improved mask type Read Only Memory and a method for manufacturing the same which can produce the completed semiconductor more quickly than previously. According to the invention there is provided a method of manufacturing a mask type Read Only Memory which has a plurality of MOS transistors connected in series, comprising the steps of: (a) selectively forming a first insulating layer having a thick portion and a thin portion for a field region and a gate insulating layer respectively, on a semiconductor substrate of a first conductivity type; (b) forming a polysilicon layer on said insulating layer; (c) forming gate electrodes for the MOS transistors by partially removing said polysilicon layer; (d) forming regions of a second conductivity type in the substrate, to be source and drain regions of the MOS transistors; using the gate electrodes as a mask, and so that the MOS transistors are connected in series by the second conductivity type regions formed between the gate electrodes; (e) forming a second insulating film on the semiconductor substrate in which the MOS transistors are formed; (f) forming a contact hole in the second insulating film to the second conductivity type region of some of the MOS transistors for allowing the formation of outer contact electrodes; (g) forming outer contact electrodes and bonding pads; (h) selectively removing at least part of the second insulating film and exposing the gate electrode, source and drain regions of certain of the MOS transistors; (i) connecting the source and drain regions of the certain MOS transistors by means of a channel region in accordance with a set program, by ion implantation of an impurity; (j) forming a protective film on said bonding pads, the outer electrodes, and the MOS transistors; (k) removing said protective film on the bonding pad; and (l) providing an outer-lead to the bonding pad. A preferred embodiment of the invention will now be described by way of example and with reference to the accompanying drawings, wherein: Figure 1 is a schematic plan view of a known semiconductor device; Figure 2 is an equivalent circuit of the semiconductor device shown in Figure 1; Figure 3 is a cross-sectional view taken along line I-I on Figure 1; Figure 4 is a circuit diagram of the mask type Read Only Memory of the preferred embodiment; Figure 5A is a plan view of a pattern layout illustrating the mask type Read Only Memory corresponding to the circuit of Figure 4; Figure 5B is a plan view of a pattern layout illustrating a portion of the mask type Read Only Memory cell of Figure 5A; Figure 5C is an equivalent circuit of the mask type Read Only Memory cell shown in Figure 5B; Figure 5D is a cross-sectional view taken along line II-II in Figure 5B; and Figures 6A to 6L are cross-sectional views of a semiconductor substrate schematically illustrating stages in a method of manufacturing a mask type Read Only Memory according to the preferred embodiment. An embodiment of a mask type Read Only Memory according to the preferred embodiment of the present invention and a corresponding method of fabrication will be described with reference to Figures 4, 5A to 5D and 6A to 6L of the drawings, same features being denoted by same reference signs. Referring to Figure 4, the mask type Read Only Memory consists of a plurality of NAND gate blocks 100 arranged in a row and column matrix, each of the blocks is selectable by the output signals of a page decoder 44 and select signals sel₀ to sel₃. Each of the NAND gate blocks 100 includes four NAND gate circuits 46, 47, 49 and 50, one of which is selected by transistors Q45, Q46, Q49, Q50 to which signals ROM·A, ROM· A are applied. Predetermined data is permanently written into matrix cell portions 200. The Read Only Memory has a first and second power source terminals VDD and GND, an output terminal 41, a first branch node 42 and a second branch node 43. A P-channel IGFET Q41 is connected between the first power source terminal VDD and the output terminal 41. An N-channel IGFET Q42 is connected between the output terminal 41 and the first branch node 42. An aluminium wiring electrode 45 interconnects the first branch node 42 and the second branch node 43. A first NAND gate circuit 46 and a second NAND gate circuit 47 are connected between the branch node 42 and GND. N-channel IGFETs Q43, Q44 in the first and second NAND gate circuits 46, 47 select both of the first and second NAND gate circuits 46, 47 simultaneously. N-channel IGFETs Q45, Q46 in the first and second NAND circuits 46, 47 select one of NAND circuits 46 and 47. The matrix cell portions 200 are connected to address decoder 48. A third NAND circuit 49 and a fourth NAND circuit 50 are arranged in the same manner as first and second NAND circuits 46, 47. Referring to Figures 5A to 5D, a polysilicon-gate electrode layer is formed by interposing an insulating layer 71 between the P type substrate 61 and the gate electrode layer 69, and N⁺ diffused regions 74, 76 are provided about the channel region. The diffused regions 101, 102 and 52 which constitute regions 74, 76, are formed in a numeral "8" shape (as shown in Figure 5). An insulated aluminium wiring layer 80 is provided in the centre of the "8" shape diffused region, and the aluminium layer 80 connects with the diffused regions 101, 102 at contact holes 79a, 79b. The source and drain regions 74, 76 of selected MOS transistors are connected by implanted channel regions 83. A method of manufacturing a mask type Read Only Memory will be schematically described referring to Figures 6A to 6L. A thermal oxide film 62 of 100 nm (1000A°) is formed over the entire surface of a P-type silicon substrate 61 which has been doped with boron by the thermal oxidation process. A silicon nitride layer 63 of 300 nm (3000Å) is deposited over the entire surface of the oxide film by the CVD process. Some areas of the silicon nitride layer 63 on the substrate 61 where elements are to be formed, are removed by the photoengraving process (Figure 6A). A wet oxidation process is performed in order to form a thick SiO₂ field oxide film 65 of 1 µm (Figure 6B). As shown in Figure 6C, the remaining silicon nitride masks 64 and the thermal oxide film 62 are removed by the engaraving process. The surface of the semiconductor substrate 61 is thus exposed. A first thin insulating film (SiO₂) 67 of 50 to 100 nm (500 to 1000Å) thickness which serves as a gate oxide film, is formed on the exposed surface 66 of the semiconductor substrate 61. Next, a polysilicon layer 68 of 300 to 400 nm (3000 to 4000Å) thickness is deposited over the entire surface by the CVD process (Figure 6D). The polysilicon layer 68 is subjected to a photoengraving process to form a given pattern, and thus gate electrodes 69, 70 are formed. Using the gate electrodes 69, 70 as a mask, the SiO₂ film 67 is etched away to form gate oxide films 71, 72. Next, a PSG film 73 is deposited over the entire surface by the CVD process. Subsequently, by using the gate oxide films 71, 72 as a mask, phosphorus in the PSG film 73 is diffused into the substrate 61 to form N⁺-type drain and source regions 74, 76 (Figure 6E). The PSG film 73 is then removed by etching. As shown in Figure 6F, an SiO₂ film 78 of 200 to 600 nm (2000 to 6000Å) thickness is formed on the surface as a third insulating layer, by the CVD process. Contact hole 79 for an aluminium wiring electrode 80 is formed in the SiO₂ film 78. Next, aluminium is vapour-deposited over the entire surface and is photoetched to form bonding pads 81 and wiring electrodes 80 at given locations as shown in Figure 6G. Next, a photo-resist layer 82 is formed over the surface to provide an etching mask, and the SiO₂ film 78 covering the transistors which are to be of the depletion type in accordance with the information to be stored, is etched away. By using the SiO₂ film 78 (or resist 82) as a mask, impurity divalent phosphorus ions P⁺⁺ of N type, with an energy of 160 KeV, are implanted into a channel region through gate electrodes 69 and gate oxide film 71 (and the SiO₂ 78A). An N type implanted channel region 83 connecting the source and drain of the transistor is thus formed, and the transistor is rendered a depletion type (Figure 6I). Next, as shown in Figure 6J, a protective film 84 such as a BPSG (boron-doped phospho-silicate glass) film or PSG film or silicon nitride film, of 500 to 700 nm (5000 to 7000Å) thickness is deposited over the surface by the plasma CVD method. The surface protective film 84 is formed with concave regions corresponding to the depletion type transistors which represent the stored information. Accordingly, it is possible to check the stored information from the outer configuration of the device. Next, as shown in Figure 6K, a bonding pad 81 for an outer-lead is exposed, and the chip fabricating process is completed. As shown in Figure 6L, an outer-lead 86 made from aluminium is connected to the bonding pad 81. In the described method of making a mask type Read Only Memory, the ion implantation into the channel region to form a depletion type MOS transistor to determine the memory content of the device is performed at a late stage of the process. The fabrication process steps up to the deposition of the SiO₂ film following the formation of the MOS transistors may be performed in advance before the memory contents are determined. After the memory contents are determined in accordance with a customer's requirements, a mask for the memory contents is obtained, and the ion implantation into the above-mentioned channel regions and the remaining steps of the process are performed. Accordingly the period from when the memory contents are specified by a customer until the products storing those contents are completed is considerably reduced. Further, because the protective film covering each depletion type transistor in the memory region is concave in shape the contents stored may be checked externally.

Claims: A method of manufacturing a mask type Read Only Memory comprising the steps of: I forming a plurality of MOS transistors connected in series in a semiconductor substrate of a first conductivity type by (a) selectively forming a first insulating layer having a thick portion (65) and a thin portion (67) for a field region and a gate insulating layer, respectively, on the semiconductor substrate, (b) forming a polysilicon layer (68) on said insulating layer, (c) forming gate electrodes (69, 70) for the MOS transistors by partially removing said polysilicon layer, (d) using the gate electrodes as a mask forming regions (74, 76) of a second conductivity type in the substrate to be source and drain regions of the MOS transistors, said second conductivity type regions of adjacent transistors being connected so that the MOS transistors are connected in series, and (e) forming a second insulating film (78) on the surface of the substrate in which the MOS transistors are formed; II (a) forming a contact hole (79) in the second insulating film to expose the second conductivity type region of some of the MOS transistors, (b) forming an aluminium contact electrode on the insulating film away from the transistors and which makes contact with the region of second conductivity type through said contact holes, (c) forming bonding pads (81); III (a) selectively removing at least part of the second insulating film (78) to expose the gate electrode, source and drain regions of certain of the MOS transistors, (b) connecting the source and drain regions of each of said exposed MOS transistors by means of a channel region (83) by ion implantation of an impurity of the second conductivity type; and IV forming a protective film (84) on said bonding pads, outer electrode (80) and the MOS transistors, removing the protective film (84) from the bonding pads and providing an outer lead (86) to each of the bonding pads. A method as claimed in claim 1, wherein step for forming the thick field insulating layer on the semiconductor substrate comprises the steps of: (a) forming a thermal oxide layer (62) on the semiconductor substrate (61); (b) selectively forming a silicon nitride film (65) on the thermal oxide layer; (c) forming a first thick insulating layer (65) on the semiconductor substrate by oxidizing the semiconductor substrate using the silicon nitride film as a mask; and (d) removing said silicon nitride layer and the thermal oxide layer. A method as claimed in claim 1 or claim 2, wherein the step of forming regions of a second conductivity type to the source and drain regions of the MOS transistors comprises the steps of: (a) forming gate insulating films (71, 72) in the MOS transistors by etching the thin insulating film (67) using the silicon gate (69, 70) as an etching mask; (b) forming an impurity source film (73) on the semiconductor substrate, and (c) diffusing the impurities in the impurity source film into the semiconductor substrate so as to form source and drain regions (74, 76). A method as claimed in claim 1, wherein said step for selectively removing the insulating film over the source regions and drain regions of said certain MOS transistors, includes the steps of: leaving a thin film (78A) of the second insulating film (78) on the silicon gate electrodes (69) of at least some of said certain MOS transistors.

Inventors: SHIOTARI, YOSHIHISA
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1982
Main classification: H01L21
IPC codes: H01L29, G11C17, H01L21, H01L27