DUAL POLARITY SWITCHABLE OPERATIONAL AMPLIFIER CIRCUIT

Abstract: A switchable input operational amplifier with two feed­ back resistors (R1, R2) which determine the gain of the amplifiers for each polarity of operation, is constructed such that, when operating in one polarity, the feedback resistor associated with the other polarity has no effect on the opera­ tion of the circuit.

Description: DUAL POLARITY SWITCHABLE OPERATIONAL AMPLIFIER CIRCUIT The invention relates to a dual polarity switchable input operational amplifier circuit operable in response to a signal applied to a polarity select input to provide a voltage output of either polarity for the same value input current. Such an operational amplifier is shown incorporated as part of a four-bit, dual polarity multiplying digital-to-analogue converter described in IBM Technical Disclosure Bulletin, Vol. 24, No. 5, Oct. 1981, on pages 2432 to 2434. (IBM is a registered trade mark of International Business Machines Corporation.) In this article, a four-bit multiplying digital-to-analogue converter with unidirectional current output feeds a current mirror which performs voltage level shift and current reversal. The mirror can be switched off, if required, to provide zero output irrespective of input conditions and feeds a switchable input operational amplifier which generates output voltage signals of the required gain switchable to either polarity for all digital input values. Details of the operational amplifier circuit capable of performing this required function are not disclosed in the article. One operational amplifier capable of producing an inverted or non-inverted signal output dependent on a voltage level present at the positive control input of the amplifier is described in an article 'plus or minus unity gain' Elektor (GB) Vol. 6, July/August 1980 at page 7-25. It is becoming more common in the computer industry to build circuits from a basic building block of a single chip on which a predetermined set of devices are provided. Since the number of different devices available on such a chip is limited, being dependent on the technology employed, considerable skills and ingenuity need to be exercised in order to design circuits with the desired functions using only the available devices. A basic building block, known as master slice used by IBM provides a plurality of logic devices constructed using bi-polar technology. Although analogue circuits can be built using the technology predominantly intended for the construction of logic devices, this imposes limitation and many circuits cannot be made in this way without recourse to the use of externally connected discrete components. Apart from this constraint imposed by the available technology, there is additionally considerable incentive to make the most economic use of the devices so as to put as much function on each master slice chip as possible. The IBM master slice is built using Zircon technology which is not adaptable for the construction of various high frequency devices including FETs, on the chip. One obvious problem associated with the circuit described in the Elektor article is that the switching operation depends upon an FET device and since this cannot be constructed on the master slice using Zircon technology the disclosed amplifier is quite unsuitable. Additionally, the use of an FET device in this way to control switching of the amplifier would inevitably introduce off-sets which would be translated to the output and modification with use of additional devices would be necessary. The invention as claimed overcomes this problem by a unique design of amplifier circuit which performs the desired switching function; requires only those components which can be formed on the chip using the technology of the chip without the need for external components; and is extremely economical in its use of components. Briefly, the invention achieves these advantages by providing a switchable dual input operational amplifier with two feedback resistors connected so that the amplifier operates as an inverting amplifier when one set of inputs are selected and as a non-inverting amplifier when the other set of inputs is selected, the two resistors individually determining the gain of the amplifier for each polarity, the circuit connections being such that when operating in one polarity, the resistor associated with the other polarity has no effect and vice versa. In order that the invention may be fully understood, a preferred embodiment thereof will now be described with reference to the accompanying drawings, in which: Figure 1 shows in schematic form a dual polarity operational amplifier according to the present invention; and Figure 2 shows the detailed construction of the circuit formed using the technology of the master slice chip. The circuit shown schematically in Figure 1 consists of a dual input operational amplifier 1 having two sets of differential inputs 2 and 3 each of which is selectable by an appropriate voltage applied to a switch control terminal 4. The amplifier is connected to function as an inverting amplifier in one mode of operation, and as a non-inverting amplifier when in the other mode. Thus, input current on common input terminal 5 is applied to the negative input 2.1 of one pair of input terminals, and to the positive input 3.2 of the other pair. The positive input 2.2 of said one pair of input terminals is connected to ground and a feedback resistor R2 is connected between the negative input 2.1 and the output terminal 6 of the amplifier. Selection of input pair 2 by an appropriate voltage on the switch control terminal 4, in this case an up-level TTL signal, puts the amplifier in inverting mode with the gain determined by the value of resistor R2. The negative input 3.1 of said other pair of input terminals is directly connected to the output terminal 6 and the positive input terminal is shunted to ground through resistor R1. Selection of input pair 3, in this case by a down-level TTL signal, puts the amplifier in inverting mode with the gain determined by the value of resistor R1. When in inverting mode, the voltage on the input 2.1 is at a virtual earth because of the small differential input voltage required to 2 4 produce an output from the high gain (102 < A < 104) operational amplifier. Therefore the current flowing through resistor R1 tends to zero. Accordingly, since the current flowing into the amplifier also tends to zero, all the input current I from input terminal 5 flows in through R2 generating a negative output voltage, V = - I. x R2. 0 in When in non-inverting mode, the amplifier operates in voltage follower mode with the output voltage following the voltages on input 3.2. In this case, the current flowing through resistor R2 tends to zero and, since the current in the amplifier also tends to zero, all the input current I. from input terminal 5 flows through R1 genera in ting a positive output voltage V = I. x R1. 0 in The integrated circuit realisation of this circuit is shown in Figure 2 where the same reference numerals as used in Figure 1 are used to identify corresponding items. The operational amplifier input stage consist of transistors T1 and T2 connected in a long-tailed pair configuration as the non-inverting portion, and transistors T3 and T4 similarly connected as the inverting portion. The differential inputs 2 and 3 of the amplifier are provided by the base connections to the four transistors. Thus, current input signals I. on common input terminal 5 are applied directly to the in base of transistor T1 (the positive input 3.2 of the non-inverting portion of the amplifier) and to the base of transistor T4 (the negative input 2.1 of the inverting portion). The base of transistor T2 (the negative input 3.1 of the non-inverting portion) is connected to the amplifier output terminal 6 and the base of transistor T3 (the positive input 2.2 of the inverting portion) is connected to ground. Additionally, the positive input 3.2 to transistor T1 (and the negative input 2.1 to transistor T4) is shunted to ground through resistor R1. Finally the negative input 2.1 of the transistor T4 (and the positive input 3.2 of transistor T1) is connected to the amplifier output terminal 6 via resistor R2. The emitters of the transistor T1 T2, T3 T4 combinations are connected to further transistors T5 and T6 respectively. These transistors are themselves connected in a long-tailed pair configuration to a current source provided by transistor T7 and resistor R3. Transistors T5 and T6 are operated as a switch to select one or other of the two portions of the operational amplifier input stages. The current source T7 R3 draws a current, the relative value of which is 211, so that in the absence of input current to the amplifier, a current I1 flows through each transistor T1 and T2, or T3 and T4 of the selected portion of the amplifier. Switching of the transistors T5 and T6 controlling the selection of the inverting or non-inverting portions of the amplifier, is by means of a TTL level signal applied to switch control terminal 4. This terminal 4 supplies the base of transistor T8 which has its collector/ emitter path connected in series with resistor R4 and current source T9, R5 combination. The current source defines a constant current I2, of a similar magnitude to constant current I1. A predetermined voltage V at node 7 is connected to the base of switch transistor T5. The magnitude of the voltage V varies in accordance with the magnitude of the signal applied to terminal 4, and is arranged to swing about a reference voltage Vref produced at node 8 and connected to the base of the other switch transistor T6. The reference voltage Vref is defined by an identical constant current I2 drawn through transistor T10 connected to function as a diode, and resistors R6, R7 in series with transistors T11 and T12 both of which are also connected to function as diodes. The value of ref is fixed at twice the The drop of the two diodes T11, T12 below ground potential. In operation, an up-level polarity select signal on terminal 4 causes the voltage on the base of transistor T5 to rise above Vref switching on transistor T5 and selecting the non-inverting portion of the amplifier. A down-level polarity select signal on terminal 4 causes the voltage V to fall below Vref switching on transistor T6 and selecting the inverting portion of the amplifier. To avoid saturating transistor T5, the voltage swing on its base is limited to one The above ground by transistor T13 connected as a clamping diode between the bases of transistors T5 and T6. The operation of the amplifier is as described with reference to Figure 1. Thus, in non-inverting mode, with transistors T1 and T2 conducting with the base of transistor T2 tied to the output voltage at terminal 6, the negative feedback of the link between output and base of transistor T2 causes the output voltage to equal that of the base of transistor T1. Accordingly all input current I flows through in resistor R1 giving a positive voltage I. R1 at output terminal 6. in No current flows through resistor R2, both ends of which are at the output voltage. In inverting mode, with transistors T3 and T4 conducting and with the base of transistor T3 tied to ground, the base of transistor T4 is also at ground by virtue of the negative feedback of resistor R2. Accordingly, the input current flows from ground potential through resistor R2 to output terminal 6 giving a negative voltage -I. R2 at in output terminal 6. No current flows through resistor R1 which has one end tied to ground and the other end at a virtual ground. Current through transistors T2 or T4, depending on the selected mode of operation, is applied to a current mirror combination of transistors T14, T15, T16 and T17 and resistor R8 to ground to mirror the current into the emitter/collector path of transistor T15. The arrangement is such that the nominal current I1 out of transistor T15 just meets the requirements of its current source provided by transistor T18 resistor R9 combination, defining a -zonstant current of I1. Changes in the nominal current value as a result of input current I. through in the amplifier forces current into the base of transistor T19 having resistor R10 in its emitter path which produces a corresponding voltage swing at its collector. Since the voltages involved are small, a further transistor T20 connected on a Darlington configuration is coupled to receive and further amplify the signal. The output voltage on the collector of transistor T20 is the output voltage appearing at output terminal 6.

Claims: CLAIMS: 1. A dual polarity switchable operational amplifier circuit having an input (5) and an output (6), said input being connected to two sets of amplifier inputs (2 and 3), means responsive to a polarity select signal for selecting one or other sets of ampLifier inputs (2 or 3), the circuit being operable in response to a current input (5) to provide a corresponding voltage at its output (6), the voltage being of one polarity when one set of amplifier inputs (2) is selected and of the other polarity when the other set of amplifier inputs (3) is selected, characterised in that the gain of the amplifier operating in each polarity is determined by a feedback resistor (R1 or R2) associated with that polarity, the construction and arrangement being such that the portion of the amplifier associated with the non-selected set of amplifier inputs (2 or 3) is inactive, and has a high input impedance, so that it has substantially no effect on the operation of the portion of the amplifier associated with the selected set of amplifier inputs (3 or 2). 2. A circuit as claimed in claim 1, in which the amplifier comprises a first and second transistor long-tailed pair configuration (T1, T2) and a third and fourth transistor long-tailed pair configuration (T3, T4) connected to a bistable switch (T5, T6) operable in one state to cause only the first and second transistors (T1, T2) to conduct and operable in the second state to cause only the third and fourth transistors (T3, T4) to conduct, said one set of amplifier inputs (3.2, 3.1) being the base connections to the first and second transistors (T1, T2) and said other set of amplifier inputs (2.2, 2.1) being the base connections to the third and fourth transistors (T3, T4), said circuit input (5) being directly connected to the amplifier inputs (3.2, 2.1) to the first and fourth transistors (T1, T4) and the circuit output (6) being coupled through a current to voltage converter (T14-T20, R9 - R10) to the emitter/collector paths of said second and fourth transistors (T2, T4), the amplifier input (2.2) to said third transistor (T3) being directly connected to a first reference voltage (ground), and the amplifier input (3.1) to the second transistor (T2) being directly connected to the circuit output (6), a first feedback resistor (R1) connected between the circuit input (5) and said first reference voltage (ground) and a second feedback resistor (R2) connected between the circuit input (5) and the circuit output (6), the arrangement being such that with said first and second transistors (T1, T2) conducting, said amplifier operates in non-inverting mode with its gain defined by said first feedback resistor (R1) and with said third and fourth transistors (T3, T4) conducting, said amplifier operates in inverting mode with its gain defiend by said second feedback resistor (R2). 3. A circuit as claimed in claim 2, in which said bistable switch consists of a fifth and sixth transistor long-tailed pair configuration (T5, T6), said fifth transistor (T5) being connected as the tail of said first and second transistor long-tailed pair configuration (T1, T2) and said sixth transistor (T6) being connected as the tail of said third and fourth long-tailed pair configuration (T3, T4), the alternate states of the bistable switch, wherein one transistor is conducting and the other non-conducting, being determined by the relative levels of voltages applied to the bases of the transistors (T5, T6), and the nominal current through the two transistors (T1, T2 or T3, T4) of the selected long-tailed pair configuration of the amplifier being determined by a constant current source (T7, R3) connected as the tail of the long-tailed pair configuration (T5, T6) of the bistable switch. 4. A circuit as claimed in claim 3, in which the base of the sixth transistor (T6) is connected to a predetermined reference voltage (Vref) and a switching voltage (V) derived from said polarity select signal, and having a value either above or below said reference voltage (V f) is applied to the base of said fifth transistor (T5). 5. A circuit as claimed in claim 2, in which said current-to-voltage converter comprises a current mirror circuit (T14-T17, R8) operable to mirror emitter/collector current of said second and fourth transistors (T2, T4) into a constant current source (T18, R9), the current requirements of which correspond to the nominal emitter/collector current of said second or fourth transistors when conducting, a voltage being derived therefrom proportional to variations in nominal emitter/collector current (I1) caused by an input current (liy) at said input (5) and said voltage being amplified and supplied at said output voltage (Vo) to said circuit output (6). 6. A circuit as claimed in any one of the preceding claims in which the first and second feedback resistors (R1, R2) are of identical value.

Inventors: COLE, TERENCE GEORGE, SMITH, COLIN
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1982
Main classification: H03F3
IPC codes: H03F3