CARRIER RECOVERY CIRCUIT

Abstract: A carrier-wave regeneration circuit for use in a demod­ ulator for a 2 n -phase PSK modulated signal comprises a phase-locked loop including a voltage-controlled oscillator 7 and an automatic frequency control (AFC) loop for avoid­ ing the pseudo-lock-in phenomenon. The AFC loop is com­ prised of two differentiating circuits (21, 25) two mixer circuits (22, 26), and a difference circuit (27) and forms a symmetrical structure so as to exclude undesired noise thereby carrying out a stable AFC operation.

Description: CARRIER-WAVE REGENERATION CIRCUIT The present invention relates to a carrier-wave regeneration circuit for use in a demodulator for a 2 phase (n = 1, 2, ...) phase-shift keying (PSK) modulated signal. In general, a carrier-wave regeneration circuit is provided in a demodulator of a receiver for 2n-phase PSK modulated signals. Such carrier-wave regeneration circuits are already known. For example, in a carrierwave regeneration circuit according to the multiplying system, four-phase PSK modulated signals are multiplied by four so as to obtain non-modulated signals, and after that, the non-modulated signals are divided by four so as to regenerate carrier-waves in phase synchronization with the received PSK signals. In a carrier-wave regeneration circuit according to the remodulation system, the received PSK modulated signals are again modulated (remodulated) using demodulated output signals. In a carrier-wave regeneration circuit according to the baseband processing system, the output signal of a Cost as loop is used. In the baseband processing system, since carrierwaves are regenerated directly from the received PSK modulated signals, a phase-locked loop (PLL) circuit is basically provided. This PLL circuit is preferably locked in to the frequency of the carrier waves ; however, this PLL circuit may also be locked in to pseudo-lock-in frequencies: f0 + fc/Na fg + 2fC/N, . . where f0 is the freqeuncy of the carrier waves, foe fc is a clock frequency, and N = 2n In particular, such a pseudolock-in phenomenon often occurs in the case of a smallcapacity digital communication where the ratio of the clock frequency (fc) to the carrier wave frequency (fro) is small. In order to avoid the above-mentioned pseudolock-in phenomenon, it has been known to use a highly stable voltage-controlled crystal oscillator in the PLL circuit. However, the use of such a crystal oscillator in a carrier-wave regeneration circuit is costly, and, in addition , the normal lock-in range for the carrier wave frequency is small. In order to enlarge the normal lock-in range for the carrier wave frequency, it has also been known to add a highly stable crystal oscillator and a sweep circuit to the PLL circuit. In a carrier-wave regeneration circuit using a highly stable crystal oscillator and a sweep circuit, the pseudo-lock-in phenomenon is detected by obtaining the frequency difference between the voltage-controlled oscillator of the PLL circuit and the highly stable crystal oscillator. That is, when the frequency difference is larger than a predetermined value, the sweep circuit sweeps the control voltage of the voltage-controlled oscillator so that the PLL circuit is separated from the pseudo-lock-in range and again performs the lock-in operation for the carrier waves. However, even when the PLL circuit is separated from one pseudolock-in range, the PLL circuit may be again locked in to another pseudo-lock-in range. Therefore, in order to enlarge the lock-in range for the carrier waves, the design of the sweep circuit, including the sweep frequency, and the sweep amplitude must be carefully determined. In order to enlarge the normal lock-in range for the carrier wave frequency, it has been further known to add a simple automatic frequency control (AFC) circuit to the PLL circuit. In a carrier-wave regeneration circuit using an AFC circuit, either a sine-wave signal Qr a cosine-wave signal obtained in the rLL circuit is different iated and, after that, the differentiated signal is supplied to the cosine-wave signal or the sine-wave signal to obtain the frequency difference between the received PSK modulated signal and the output signal of the voltage controlled oscillator. This frequency difference serves as a control voltage for the voltage-controlled oscillator. Therefore, even if the PLL circuit is locked in a pseudolock-in range it can be separated from that range by AFC. Thus, enlargement of the normal lock-in range for the carrier waves is economically realised. However, in this regeneration circuit, spurious signals are generated due to the asymmetry of the AFC circuit, thereby causing the normal lock-in operation to be unstable. According to the present invention, there is provided a carrier-wave regeneration circuit for use in a demodulator for a 2n-phase (n = 1, 2, ...) PSK modulated signal comprising: voltage-controlled oscillator means for generating first and second signals in phase quadrature; first and second mixing means for mixing the PSK modulated signal with the first and second signals, respectively baseband processing means for multiplying the output signals of the first and second mixing means by a factor of 2n to generate third and fourth signals in phase quadrature; first and second differentiating means for differentiating the third and fourth signals; a third mixing means for mixing the output signal of the first differentiating means with.the fourth signal; a fourth mixing means for mixing the output signal of the second differentiating means with the third signal; means for generating the difference between the output signals of the third and fourth mixing means; a first control means for supplying a first control voltage indicative of the third or fourth signal to the 'voltage-controlled oscillator means; and a second control means for supplying a second control voltage indicative of the output signal of the difference-generating means -to the voltage-controlled oscillator means. Embodiments of the present invention can provide carrier-wave regeneration circuits using AFC circuits which 'en'able a normal lock-in operation to be stable. Reference is made, by way of example, to the accompanying drawings, in which: Figure 1 is a block circuit diagram illustrating a first prior art carrier-rave regeneration circuit; Figure 2 is a block circuit diagram illustrating a second prior art carrier-wave regeneration circuit; Figure 3 is a block circuit diagram illustrating a third prior art carrier-wave regeneration circuit; Figure 4 is a block circuit diagram illustrating a carrier-wave regeneration circuit. according to one embodiment of the present invention; Figure 5 is a graph showing the relationship between a frequency difference 6ad and a control voltage VAFC provided in the circuit of Figure 4; Figure 6 is a circuit diagram of voltage-controlled oscillator 7 of th circuit of Figure 4; ; Figure 7 is a circuit diagram of baseband processing circuit 4 of the cireuit of Figure 4; Figure 8 is a block circuit diagram illustrating a carrier-wave regeneration circuit according to another embodiment of the present invention; Figure 9 is a graph for assistance in understanding the determination of threshold values V10 and V20 employed in the circuit of Figure 8; Figure 10 is a detailed circuit diagram of a determination circuit 28 and an isolated-pulse generator 29 of the circuit of Figure 8; Figures 11A, liB, 11C, 12A, 12B, and 12C are timing diagrams showing signals appearing in the circuit of Figure 10. In Figure 1,which illustrates a first prior art carrier-wave regeneration circuit, a PLL circuit is constituted by hybrid (circuit) 1, phase detectors or mixer circuits 2 and 3, Cost as loop-type baseband processing circuit 4, amplifier 5, low pass filter 6, voltage-controlled oscillator 7, and 900 phase shifter 8. A-received four phase PSK modulated input signal having frequency W. in passes through hybrid 1 to mixer circuits 2 and 3 which generate output signals cos ( G)d.t+g) and sin (G)d.t+&commat;) in phase quadrature, where COd and Q are differences in frequency and phase, respectively, between the input signal and and the output signal (GO0) of voltage-controlled oscillator 7. Baseband processing circuit 4 generates output sin4(Wd .tiG). Thus, voltage-controlled oscillator 7 is controlled by voltage sin4(#d.t+#) so as to generate carrier waves. If the PLL circuit is locked in for the carrier waves,)d= 0 and g = 0 , that is, sin4(#d.t+#) = 0. However, when enlarging the lock-in range for the carrier waves1. a pseudo-lock-in phenomenon often occurs. In this case, sin4(63d.t+0) = O butLDd k 0. In order to avoid this pseudo-lock-in phenomenon, it has been proposed to use highly stable crystal oscillator as voltage-controlled oscillator 7 , Such use, however, makes the circuit costly and the normal lock-in range small. In Figure 2, which illustrates a second prior art carrier-wave regeneration circuit, elements 11 through 16 are added to the elements of the circuit of Figure 1. Reference numeral 11 designates a highly stable crystal oscillator having frequency rv 12 a mixer circuit, 13 a counter, 14 a determination circuit, 15 a sweep circuit, and 16 a sum circuit. The difference in frequency between voltage-controlled oscillator 7 and crystal oscillator 11 is counted by counter 13. Wffien the frequency difference is larger than a predetermined value, determination circuit 14 initiates the operation of sweep circuit 15 so that the sweep voltage is added to the control voltage of voltagecontrolled oscillator 7, thereby sweeping the oscillating frequency thereof. -As a result, the PLL circuit is separated from a pseudo-lock-in range and again performs the normal lock-in operation for the carrier waves. In the circuit of Figure 2, however, even if the PLL circuit is separated from one pseudo-lock-in state , the circuit may also be locked in another pseudo-lock-in state. Therefore, in order to enlarge the normal lock-in range for the carrier w-aves, the sweep frequency, the sweep amplitude, and the like-must-be carefully designed. As- a result, it is not easy to manufacture and adjust the circuit of Figure 2. in Figure 3, which -illustrates a third prior art carrier-wave regeneration circuit, elements 21 through 24 are provided to form -an AFC loop. In Figure 3 elements 1 to 8 correspond to elements 1 to 8 of Figure 1.. However it should be noted that -in Figure 3, baseband processing circuit 4 delivers two outputs: sin4(aJd.t+G) and cos4(#d.t+#). Reference numeral 21 designates a differentiating circuit, 22 a mixer circuit, 23 a low pass filter, and 24 an amplifier. Differentiating circuit 21 generates the output d dtcos4(#d.t+#) = -4#dsin4(#d.t+#) Therefore, mixer circuit 22 generates the output - 4 dsìnê(#d.t+#) = - 2{#d-cos8(#d.t+#)} That is, frequency difference -2 d is supplied through low pass filter 23 and amplifier 24 to voltage-controlled oscillator 7 to perform AFC. Thus, voltage-controlled oscillator 7 is controlled by first control voltage VpLL due to the phase-locked loop and by second control voltage VAFC due to the AFC loop. As a result, even if the PLL circuit becomes locked in a pseudo-lock-in range, the PLL circuit is separated from the pseudo-lock-in range by AFC and is moved toward the center of the normal lock-in range for the carrier waves. In the circuit of Fig. 3, however, there is a serious problem in that the AFC is unsuitable due to the AFC circuit being asymmetrical , with the result that control voltage VAFC is relatively noisy in spite of thepresence of low pass filter 23, which eliminates the frequency component of a signal passing therethrough. Note that usually differentiating circuit 21 creates a large amount of noise. rn Figure'4 which illustrates one embodiment of the present invention, a symmetrical AFC circuit is provided so that a stable AFC operation is performed. That is, differentiating circuit 25, mixer circuit 26, and difference circuit 27 are added to the elements of Figure 3. As explained above, mixer circuits 2 and 3 generate outputs cos(cod.t+g) and sin (od.t+g) in phase quadrature which are supplied to baseband processing circuit 4, which, in turn, generates first and second outputs cos4(#d.t+#) and sin4(#d.t+#) in phase quadrature. Sine-wave component sin4(#d.t+#) is supplied to the PLL while both of the cosinewave and sine-wave components are supplied to the AFC loop. It will be appreciated that it is alternatively possible to supply the cosine-wave component to the PLL. Differentiating citcuits 21 and 25 differentiate outputs cos4(cJ.t+Q) -and sin4( W d.t+g) , respectively, of baseband processing circuit 4 and generate the following differentiating outputs: EMI8.1 = -4#dsin4(#d.t+#) EMI8.2 = 4#dcos4(#d.t+#) Mixer circuit 22 mixes the output of differentiating circuit 21 with the second output of baseband processing circuit 4 while mixer circuit 26 mixes the output of differentiating circuit 25 with the first output of baseband processing circuit 4. Therefore, the outputs of mixer circuits 22 and 26 are as follows: -4#dsinê4(#d.t+#) and 4#dcosê4(#d.t+#) . Difference circuit 27 generates the difference between the outputs of mixer circuits 22 and 26, that is, 4 aJd- The output of difference circuit 27 is supplied through low pass filter 23 and amplifier 24 to voltage controlled oscillator 7 as control voltage VAFC . Therefore, when frequency difference bOd between the received PSK input signal and the output of voltage-controlled oscillator 7 locked in a pseudo-lock-in state is detected, voltagecontrolled oscillator 7 is controlled so that frequency difference Wd becomes zero. Thus, an AFC loop is produced so as to avoid the pseudo-lock-in phenomenon. Output sin4(#d.t+#) of baseband processing circuit 4 is supplied through amplifier 5 and low pass filter 6 to voltage-controlled oscillator 7 as control voltage VpLL. If frequency difference Wd d equals zero, control voltage VPLL is a value corresponding to the difference in phase between the received PSK modulated input signal and the output of voltage-controlled oscillator 7 so that a PLL is produced. Accordingly, carrier waves are regenerated from the output of voltage-controlled oscillator 7 in synchronization with the phase of the received input signals. It should be noted that, in a PLL, if frequency difference cJd is not zero, VpLL is in general not zero either. Therefore , a PLL also serves as another AFC loop. In Figure 4, even when the outputs of differentiating circuits 21 and 25 include undesired noise, such undesired noise is excluded by difference circuit 27. In addition, the high frequency component of the output of difference circuit 27 is excluded by low pass filter 23. Thus, control voltage VAFC of Figure 4 is more stable than control voltage VAFC of Figure 3. Figure 5 is a graph showing the relationship between frequency difference 3d and control voltage VAFC of voltage-controlled oscillator 7 of Figure 4. As mentioned above, control voltage VAFC given by the output of difference circuit 27 controls voltage-controlled oscillator 7 so that frequency difference bOd d becomes zero. In Figure 6, which is a circuit diagram of voltagecontrolled oscillator 7 of Figure 4, reference numeral 71 designates an oscillating circuit , 72 a variable capacitance diode, 73 a capacitor, and 74 an inductance. The-combination of variable capacitor 72, capacitor 73, and inductance 74 determines the oscillating frequency of oscillating circuit 71. In this case, the oscillating frequency varies in response to the voltage supplied to variable capacitance diode 72, which voltage is determined by first control voltage VpLL and second control voltage VAFc. First control voltage VpLL has a polarity responsive to the positive or negative value of phase difference G while second control voltage VAFC has a positive or negative polarity responsive to frequency difference todw Two kinds of control voltages VpLL and VAFC are superposed on variable capacitance diode 72 so as to lessen both frequency difference cod and phase difference B. In Figure 7, which is a block circuit diagram of baseband processing circuit 4 of Figure 4, reference numerals 41, 42, 46 , 47, 49, 50, 54, and 55 designate absolute value circuits, 43, 45, 48, 51, 53, and 56 designate difference circuits, and 44 and 52 designate sum circuits. Here it is assumed thatoL=wd.t + Q Circuits 41, 42, and 43 are used for generating output cos 2&alpha;. That is, absolute value circuits 41 and 42 generate butptitscos2 and sin , respectively, and difference circuit 43 generates output cosê&alpha; - sin2o' = cos2 Circuits 44 through 48 are used for generating output sin 2&alpha; . That is sum circuit 44 generates-output cos &alpha; + sin , and, therefore, absolute value circuit 46 generates output (cos &alpha; + since 2 In addition, difference circuit 45 generates output cos - sin&alpha; , and, therefore absolute value circuit 47 generates output (cosoC- sin)2. Difference circuit 48 generates output (coso( + sin 2 - (cos&alpha; - since = 4cos&alpha; since = 2sin2&alpha; sin2 (after amplitude adjusting) Similarly, circuits 49 through 51, which are the same as circuits 41 and 43 are used for generating output cos4&alpha;, while circuits 52 through 56 , which are the same as circuits 44 through 48, respectively , are used for generating output sin4&alpha;. Thus, signals cosy and sin&alpha; are changed to signals cos4&alpha; and sin4&alpha; by baseband processing circuit 4 of Figure 4. In Figure 8, which illustrates another embodiment of the present invention, determination circuit 28 and isolated-pulse generator 29 are employed in place of element 24 of Figure 4. Determination circuit 28 determines whether output level V of low pass filter 23 is within a predetermined range having maximum level V10 and minimum level V20 as shown in Figure 9. Note that the curve in Figure 9 is the same as the curve of Figure 5. In Figure 9,#1 and #2 show pseudolock-in frequencies, and V10 and V20 are output yoltages of filter 23 when frequency difference #d is #1 and #2, respectively. Such values V1O and V20 are threshold values of determination circuit 28 (Figure 8). Returning to Figure 8, determination circuit 28 compares the output V of low pass filter 23 with high threshold value V10 to generate digital output V1, and, simultaneously, determination - circuit 28 compares the output of low pass filter 23 with low threshold value V20 to generate digital output V2. When isolated-pulse generator 29 detects the rising of output V1 of determination circuit 28, generator 29 generates a positive isolated pulse. On the other hand, when isolated-pulse -generator 29 detects the falling of output V2 of determination circuit 28, generator 29 generates a negative isolated pulse. Such a positive or negative isolated pulse is supplied to voltage-controlled oscillator 7 as control voltage V'AFc . This means that an AFC loop is produced so as to avoid the pseudo lock-in phenomenon. In Figure 10, which is a detailed circuit diagram of determination circuit 28 and isolated-pulse generator 29 'of Figure 8, determination circuit 28 comprises comparators 281 and 282 which compare output V of low pass-filter 23 with threshold values V10 and V20 , respectively. Isolatedpulse generator 29 comprises rising-detection circuit (differentiating circuit) 291, falling-detection circuit (differentiating circuit) 292, or OR circuit 293. The waveforms of the signals in Figure 10 are illustrated in Figures llA, llB, and llC and Figures 12A, 12R, and, 12C. When output V of low pass filter 23 becomes highe'r than threshold value Vino, as illustrated in Figure 11A, comparator circuit 281 pulls up its output V1, as illustrated in Figure 11B, so that isolated-pulse generator 29 generates positive isolated pulse P1, as illustrated in Figure llC. Similarly, when output V of low pass filter23 becomes lower than threshold value V20 , as illustrated in Figure 12A, comparator circuit 282 pulls up its output V2, as illustrated in Figure 12B2 so that isolated-pulse generator 29 generates negative isolated pulse P2, as illustrated in Figure 12C. Thus, in the second embodiment, when the output of low pass filter 23 corresponding to frequency difference Wd exceeds pseudo-lock-in frequency W1 or W2, a positive or negative isolated pulse is supplied to voltage controlled oscillator 7, thereby reducing the time period required for separating the PLL circuit from the pseudolock-in range. Note that, in this case, separating of the PLL circuit from the pseudo-lock-in range is also always carried out by a PLL. The above-mentioned embodiments are related to four-phase modulated waves; however, the present invention can be applied in the regeneration of multi--phase modulated carrier waves such as eight-phase waves, sixteen-phase waves, and the like. As explained hereinbefore, according to the present invention, since stable AFC is carried out for the regeneration of carrier waves2 a normal lock-in operation for carrier waves is carried out at a high speed. In addition, the normal -lock-in range can be enlarged. According to the present invention there is provided a carrier-wave regeneration circuit for use in a demodulator for a 2n-phase '(n=1,2,.¯.) PSK modulated signal comprising: voltage-controlled oscillator means for generating first and second signals in phase quadrature; first and second mixing means for mixing said POSE; modulated ----- - s signal with said first and second signals , respectively; baseband processing means for multiplying the output s-ignals of said first and second mixing means by a factor of 2n to generate third and fourth signals in phase quadrature; differentiating means for differentiating said third signal; a third mixing means for mixing the output signal of said differentiating means with said fourth signal; and a first control means for supplying a first control voltage indicative of a signal generated by said baseband processing means to said voltage-controlled oscillator means; and a second control means for supplying a second control voltage derived in dependence upon the output signal of the third mixing means to said voltage-controlled oscillator means; wherein the carrier-wave regeneration circuit further comprises: further differentiating means for differentiating the fourth signal; a fourth mixing means for mixing the output signal of said further differentiating means with said third signal; and means for generating the difference between the output signals -of said third and fourth mixing means; and wherein the first- control voltage is indicative of either said third or said fourth signal, and the second control voltage supplied by the second control means is indicative bf' the' output signal of said diffe::ende-generating means.

Claims: CLAIMS 1. A carrier-wave regeneration circuit,for use in a demodulator for a 2phase (n=1,2,...) PSK modulated signal, comprising: voltage-controlled oscillator means (7,8) for generating first and second signals in phase quadrature; first and second mixing means (2,3) for mixing said PSK modulated signal with said first and second signals, respectively; baseband processing means (4) for multiplying the output signals of said first and second mixing means by a factor of 2n to generate third and fourth signals in phase quadrature; first and second differentiating means (21,25) for differentiating said third and fourth signals; a third mixing means (22) for mixing the output signal of said first differentiating means with said fourth signal; ; a fourth mixing means (26) for mixing the output signal of said second differentiating means with said third signal; difference-generating means (27) for generating the difference between the output signals of said third and fourth mixing means; a first control means (5,6) for supplying a first control voltage (VpLL) indicative of said third or fourth signal to said voltage-controlled oscillator means; and a second control means (23,24; 23,28,29) for supplying a second control voltage (VAC, VAFc,) indicative of the output signal of said difference-generating means to said voltage-controlled oscillator means. 2. A circuit as set forth in claim 1, wherein said voltage-controlled oscillator means comprises: a voltage-controlled oscillator (7) for generating said first signal; and a 90 phase shifter (8) connected to ,the output of said voltage-controlled oscillator for generating said second signal. 3. A circuit as set forth in claim 1 bur 2, wherein said first control means comprises: an amplifier ('5) for receiving said third or fourth signal; and a low pass filter (6), connected to the output of said amplifier, for generating said first control voltage (VpLL). 4. A circuit as set forth in claim 1,2 or 3, wherein said second control means comprises: a low pass filter (23) for receiving the output signal of said difference-generating means; and an amplifier C24), connected to said low pass filter, for generating said second control voltage (VAFC). 5. A circuit as set forth 'in claim 1, 2 or 37wherein said second control means comprises: a low pass filter (23) for receiving the output signal of said difference-generating means a determination circuit (28) , connected to said low pass filter, for determining whether or not the output level of said low pass filter is within a predetermined range; an isolated-pulse generator (29), connected to said determination circuit, for generating an isolated pulse when the output level of said low pass filter deviates from said predetermined range, said isolated pulse serving as said second control voltage (YAFc,2. 6. A circuit as set forth in claim 5, wherein said isolated pulse has a polarity which depends upon whether the output level of said low pass filter deviates from the said predetermined range by exceeding the upper level of said predetermined range or by falling below the lower level of said predetermined range.

Inventors: HOMAN, HIROYUKI, SASAKI, SUSUMU
Applicants: FUJITSU LIMITED
Application year: 1982
Main classification: H04L27
IPC codes: H04L27