ELECTRONIC CIRCUIT

Abstract: Electronic circuit, characterized by containing at least one Schottky field effect transistor with contact elements (H, L) having different Schottky barrier heights.

Description: ec ron c c rc Fig. la and b show two versions of how the complementary field- effect transistors which are discussed below can be used to form a digital circuit, in this case an inverter. The circuit principle is ~ t, known and is usually realized with transistors of MOS.-type (metal- oxide-semiconductor). When A is high (close to the + voltage) then B is low (close to 0 or the -voltage), and conversely. It is also known that the gate electrodes G, instead of consisting of a metal contact (or of a nearly etal!ically conducting poly- silicon contact) on oxide, can consist of metal contacts directly on the semiconductor surface. The semiconductor can be silicon or GaAs, InP, InP ι_, χ As , In v Ga i. v As » ei:c * ( x an d y < • ) - The new concept is to use, in a suitable way, two different metals (or nearly metallically conducting materials), with different Schottky barrier heights (defined here as to n-type material), one high, the other low, as contacts to the semiconductor. It is known that a low barrier gives a low-resistive contact to n-type semiconductor (in contrast to a high barrier contact which conducts ^ r little), and that a high barrier gives a low-resisti e contact to p-type semiconductor (in contrast to a low .barrier contact which conducts yery little. The source- and drain-electrodes S and D in the diagrams of fig. 1 shall in principle be low-resistive contacts to the semiconductor. For an n-channel transistor, the S- and D-connections are layers of the material with low Schottky barrier, below called the "low-metal". The layers are made by evaporation, sputtering, etc. and are patterned by suitable methods, e.g. using photolithographic methods. For a p-channel transistor S and D are made of the "high-metal". The gate electrodes (one or more) for the n-channel transistor are made of the "high-metal", for the p-channel transistor of the "low-metal". Different methods of constructing the transistors will be described below. A '* 1. See fig. 2. 4 The layer A with typical thickness 0.1 - 0.5 ym consists of a suitably doped (often with ion-implantation) π-type semiconductor. t The layer B can be a layer with considerably lower conductivity (for instance be the remaining part of an epitaxial layer A + B on the insulator saphire C; alternatively B can be a differently doped, for instance high-resistive p-type, part ofthe semiconductor). ^U E_ c:π That part of the n-layer which is below ' G can in the extreme states be either depleted of free carriers (i e form a depletion layer) and then impede current flow between S and' D, or have many free carriers; the transistor then conducts because of easy current transport between S and D. Because G is made from the "high-metal", a depletion layer. ith thickness X is formed in the n-layer below, if G is connected (directly or via a resistor) to S. The current between S and D then becomes low. When a positive bias V^ is applied to G relative to S,- the depletion width decreases, and becomes smaller than the thickness of the A-layer, hence a conducting channel is formed between S and D. By choosing a "high-metal" with very high barrier, e.g. iridium with a barrier of approximately 0.9 electronvolts, X can be large at the same time as the forward current 3f Qnl to G ._ , ■' "«' qV forw. Jforw. " A T e W ■ e ~ Υr ~ becomes.small , even if V^ is a few tenths of a volt. (For a barrier height _ό of approximately 0.9 eV- the current becomes of the order of 10 -10 - 10-9 A for a transistor .with the channe - ength 1 of « 2 y and a channel width w of 300 ym, for V^ « 0.3 V). The positive supply • voltage + in fig. 1 therefore can be several tenths of a volt, without the input A loading the output B of a preceding similar cell as that of fig. 1 , too much. The p-transistor is constructed in a similar way to that shown in fig. 2, but using a p-type layer A and with the L- and H-metal-s inter¬ changed. To form the CMES-cell in fig. 1 a, the n- and p-channel transistors are formed on different ' slands" on the semiconductor whereby the islands are isolated from each other with any of several commonly used isolation methods in semiconductor technology. If silicon on saphire is used, the simple method of etching ditches down to the saphire can be used, see fig. 3. The relation between the resistivity p in the n-channel in fig. 2, and the width X is approximately given by X « ( in Ωcm, X in y ) , Here V, = φ , - ς , where Φ -. is the barrier height of the contact and ς - (p) is the distance between the conduction band and the Fermi level, see fig. 4. The corresponding relations are obtained for the p- transistor where the barrier height is ψ «• The CMES-cell in fig. 1 a uses "enhancement transistors"; to have the transistor conduct one must apply a voltage V fiS 0 of suitable polarity between G and S. The n-layer in fig. 2 is so highly doped, for instance to 10 -10 cm -4 -1 that it has a conductivity of, say 10 Ω per square. For the CMES-cell in fig. 1 b the transistors are of depletion type. That' is, in order to shut off the transistor one has to apply a voltage V GS f 0 on G. One version of this type of transistor will de described below, with reference to fig. 5. 2, As an example is shown an n-channel depletion type transistor on a silicon-on-saphire-island. v is a low-doped n-layer and n is a " highly doped n-layer. The potential profile under G for Vgς = 0 (see fig. 5 b)- shows that the depletion width B is small, and part of the n -doped layer forms a channel K with good conductivity. ' The doping is adjusted, e.g. using ion implantation, to a suitable depth profile so -4 -1 that K becomes sufficiently conducting, say 10 Ω per square, but so the effective barrier φ -- for current transport, because of tunneling effect,does not become appreciably lower than the high barrier Φ . When a negative voltage is applied to G, relative to S, then B is increased (K decreases) and the channel conductance decreases, φ ** should not be so low that considerable current is flowing to G (see above). Nor should φ' be so low that a large hole current can flow from the substrate. The p-channel depletion transistor can be constructed on the same v-wafer, but using p -doping, and the low- and high-metals are inter¬ changed compared with above. The difference in function between the L- and H-contacts becomes large because of the exponential dependence on φ, see for instance the expression for j 0rw above. For L and H one may choose materials with the lowest and highest known barriers. For L a possible choice is one of the rare earth metals Tb, Er, Yb, Y, which give approximately 0.3 - 0.4 eV barrier height. Alternatively other contact materials, for instance Mn, Hf or Al , sflicides, highly doped semiconductor films or corrducting plastics, etc., can be used. For H one may use noble metals with high barrier, for instance Ir (0.9 eV), Pt, Os, etc. Other contact materials, e.g. Ho, suicides, highly doped semiconductor layers or conducting plastics etc.. can also be used. * For passivation of the fabricated circuit one may for instance use CVD-oxide. When the contact films are deposited one can start from a semiconductor surface with a thin layer of siliconOxide on top, in which holes for the contacts are made. The contact pattern that connects the different transistors with each other and with external connections can be the L- and H-materials themselves, or another material, e.g. aluminium, or consist of a sandwich of both. To avoid reactions in solid phase between the films one may use intermediate layers which can stop diffusion, e.g. a layer of titanium. The gap between the L- and H-metals, in CMES-cells usually of the magnitude y , may be given a chemical treatment or irradiation dose so that a suitable band-bending is obtained at the surface, whereby the gap can be made small. The principles above can also be used to fabricate larger units " that can be used for power control. The electrodes marked D and S in fig. 1 can also be interchanged. S and D are identical in the schematics drawn here but a certain difference in the electrical characteristics can then be obtained. Electr i cal connections to the substrate, if any, are normally connected to S. When fabricating the transistors described- above on compound semiconductors like GaAs etc., which can give faster circuits than silicon circuits, the technology offers, beside simplicity and possibilit to achieve extremely small dimensions, also the advantage that compounds can be used which can be doped only with difficulty and where formation of pn-junctions is difficult. Suitable H-materials for GaAs can be: Au, Bi, Sb, Pt, Ag, (SN) -polymers etc; for L-materials: Ca, Hg, W etc. From the description above it is clear that the described circuit is particularly suited for fabrication of integrated circuits with high packing density, because the transistors can be fabricated with fewer process-steps than what has been possible before. One factor here is that the same material (L and H) performs complementary functions in the two transistors of a complementary circuit, thereby permitting easy and highly ' conducting interconnection patterns. The complementary switch circuit plays an increasing role in digital circuits, in memories, registers, counters etc. A simple fabrication process reduces the number of faults and hence gives increased fabrication yield. The circuit described above can, besides in digital circuits be used also in linear (analogue) circuits, microwave applications, power applications etc. • TJR£

Claims: 6 C LAI MS 1. Electronic circuit " , characterized by containing at least one Schottky field effect transistor with contact elements (H, l) having different Schottky barrier heights. 2. Circuit according to claim 1, characterized by the Schottky field effect transistors contact elements being metals, or materials with nearly metallic conductivity. 3. Circuit according to claims 1 or 2, characterized by the Schottky transistors contact elements for collector and emitter (D, S) being material with low Schottky barrier, while the contact element for the gate (G) is of a material with high Schottky barrier (n-transistor) . 4. Circuit according to claims 1 or 2, characterized by the Schottky transistors contact elements for collector and emitter (0, S) being material with high Schottky barrier, while the contact element for the gate (G) is of a material with low Schottky barrier (p-transistor)-. 5. Circuit according to any of the previous claims, characterized by containing at least two complementary Schottky field effect transistors according to claims 3 and 4 respectively. ._ 6. . Digital circuit according to ' any of the previous claims, for instance flip-flop, gate, shift register, counter etc, characterized by combinations of Schottky field effect transistors constructed according to any of the previous claims. 7. Analog circuit according to any of claims 1-5, for instance amplifier, oscillator, switches etc, characterized by combinations of Schottky field effect transistors con¬ structed according to any of claims 1-5

Inventors: BOHLIN KJELL, NORDE HERMAN, STOLT LARS, TOVE PER ARNE
Applicants: BOHLIN KJELL, NORDE HERMAN, STOLT LARS, TOVE PER ARNE
Application year: 1982
Main classification: H01L29
IPC codes: H01L27, H01L29