AN ELECTRIC CIRCUIT FOR DETECTING THE MAXIMUM VALUE OF A PLURALITY OF INPUT CURRENTS AND A SIGNAL PROCESSING CIRCUIT EMPLOYING IT.

Abstract: An electric circuit is constructed of a first current mirror circuit (14) and a second current mirror circuit (15). The first current mirror circuit has a first input transistor (Q₁), a first coupling transistor (Q₂) and an output transistor (Q₃), while the second current mirror circuit has a second input transis­ tor (Q₄), a second coupling transistor (Q₂) and the output transistor (Q₅). First and second input terminals (20, 22) are respective­ ly connected to the collectors of the first and second input transistors (Q₁, Q₄), and a common output terminal (23) is connected to the collector of the respective output transistor (Q₃, Q₅). First and second additional transistors (Q P1 , Q P4 ) are respectively connected to the first and second input transis­ tors, whereby an output current proportional to either greater value of two input currents supplied to the two input terminals (20, 21) is provided from the common output termi­ nal (23).

Description: TITLE OF THE INVENTION AN ELECTRIC CIRCUIT AND A SIGNAL PROCESSING CIRCUIT BACKGROUND OF THE INVENTION The present invention relates to an electric circuit and a signal processing circuit which employs it. More particularly, the present invention is directed toward an electric circuit for detecting the maximum value of a plurality of input currents and a signal processing circuit employing it. Figures 1 to 4 show electric circuits which were studied by the inventor prior to the present invention. The electric circuit shown in Figure 1 or Figure 2 includes a current mirror circuit 10 or 11 which is constructed of PNP transistors Q1 Q2 or Q1 Or Q)and which is well known to those in the art. A first current source 31 and a second current source 32 are connected to the input terminal 20 of the current mirror circuit 10 or 11, while a load 40 is connected to the output terminal 22 thereof. The power supply terminal 24 of the current mirror circuit 10 or 11 is supplied with a supply voltage Vcc. The inventor's study, however, has revealed that, with the composite current mirror circuit of Figure 1 or Figure 2, in a case where the device characteristics of the PNP transistors Q1 and Q2 are equal to each other, an output current which is supplied from the output terminal 22 to the load 40 becomes the sum between a current flowing through the first current source 31 and a current flowing through the second current source 32, so the maximum value of the currents cannot be detected. The composite current mirror circuit in Figure 3 includes a first current mirror circuit 12 which is constructed of PNP transistors Q1 and Q2, and a second current mirror circuit 13 which is constructed of PNP transistors Q2 and Q3. A first current source 31 is connected to the input terminal 20 of the first current mirror circuit 12, while a second current source 32 is connected to the input terminal 21 of the second current mirror circuit 13. A load 40 is connected to the common output terminal 23 of the first current mirror circuit 12 and the second current mirror circuit 13. A power supply terminal 24 is supplied with a supply voltage Vcc. The inventor's study, however, has similarly revealed that, with the composite current mirror circuit of Figure 3, in a case where the device characteristics of the PNP transistors Q1, Q2 and Q3 are equal to one another, an output current which is supplied from the output terminal 23 to the load 40 becomes half of the sum between a current flowing through the first current source 31 and a current flowing through the second current source 32, so the maximum value of the two currents cannot be detected. The composite current mirror circuit in Figure 4 includes a first current mirror circuit 14 which is constructed of discrete PNP transistors & Q3, and a second current mirror circuit 15 which is constructed of similar discrete PNP transistors Q2 - Q5. A first current source 31 is connected to the input terminal 20 of the first current mirror circuit 14, while a second current source 32 is connected to the input terminal 21 of the second current mirror circuit 15. A load 40 is connected to the common output terminal 25 of the first current mirror circuit 14 and the second current mirror circuit 15. A power supply terminal 24 is supplied with a supply voltage Vcc. The inventor's study, however, has revealed that, with the composite current mirror circuit of Figure 4, in a case where two input currents Iinl and Iin2 have a difference, an accurate current comparing operation cannot be executed. Figure 5 shows a measurement circuit for experimenting on the current comparing operation of the composite current mirror circuit of Figure 4. All the transistors Q1 ¯ Q5 are discrete PNP transistors. A fixed resistor Rll of 12 kg and a variable resistor R12 are connected in series to the first input terminal 20, a fixed resistor of ¯ 43 KR is connected to the second input terminal 21, and an ammeter 50 for measuring an output current IOUT is connected to the common output terminal 23. The first input current Iinl is varied by changing the resistance value of the variable resistor R12, whereas the second input current Iin2 becomes a constant current owing to the fixed resistor R2. Figure 6 is a graph which shows the experimental result of the composite current mirror circuit of Figure 4 obtained by the use of the measurement circuit of Figure 5. In a region A in Figure 6, the resistance of the variable resistor R12 is low, so that the first input current Iinl becomes a value greater than that of the second input current 1in2' and the output current 1OUT varies depending upon the first input current Iinl. In a region B in Figure 6, the sum between the resistances of the fixed resistor Rll and the variable resistor R12 is approximately equal to the resistance of the other fixed resistor R2, so that the first input current Iinl and the second input current Iin2 become values substantially equal to each other, and further, the output current 1OUT becomes a value substantially equal to each of the above values. In a region C in Figure 6, the first input current Iinl becomes a value smaller than that of the second input current 1in2 because of a high resistance of the variable resistor R12. In the region C of Figure 6, accordingly, it is ideal for an electric circuit for detecting the maximum value of a plurality of currents, that the output current 1OUT is unconditionally determined by the second input current Iin2 which is greater and constant. It has been revealed, nevertheless, that the composite current mirror circuit of Figure 4 has a characteristic deviating from the'ideal state, particularly in the region C in Figure 6. The inventor studied the cause of the above phenomenon, and has drawn a conclusion as described below. In the region C of Figure 6 in which linl < Iin2 is satisfied, the base-emitter voltage VBE of each of the discrete PNP transistors Q1, Q2 and Q4 in Figure 4 is obtained as follows in accordance with the greater current Iin2 EMI5.1 where K denotes Boltzmann's constant, T the absolute temperature, a the magnitude of electronic charge, and Is a saturation current in the reverse direction. Accordingly, the base-emitter junction of the transistor Ql is biased by the base-emitter voltage VBE determined by Equation (1), so that a current equal to the second input current 1in2 tends to flow through the emitter-collector path of the transistor. Since, however, the high resistance 12 is connected to the collector of the transistor Q1' the current to flow through the emitter-collector path thereof is limited to the smaller first input current I. in Thus, in the region C of Figure 6 which satisfies Iinl < 1in2' the discrete PNP transistor Q1 in Figure 4 is driven into its saturation region, and hence, the collector-base junction thereof is forward-biased. A transistor saturation current ISAT based on the saturation of the transistor 91 flows through a path illustrated in Figure 4, and is supplied to the load 40 via the common output terminal 23. Unless such transistor saturation current ISAT is supplied to the common output terminal, the output current 1OUT will be unconditionally determined by the greater and constant second input current Iin2 under the condition of Iinl < Iin2. In actuality, however, the above transistor saturation current ISAT flows in the composite current mirror circuit of Figure 4, so that the deviation from the ideal state occurs in the region C of Figure 6. Further, it has been similarly revealed that, in the region A of Figure 6 in which Iinl > Iin2 is fulfilled, the discrete PNP transistor Q4 is driven into its saturation region, resulting in a deviation from an ideal state in the region A. SUMMARY OF THE INVENTION In this manner, the present invention has been made on the basis of the results of study by the inventor as described above, and it has for its object to provide an electric circuit for detecting the maximum value of a plurality of input currents and/or a signal processing circuit employing it. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1, 2, 3 and 4 show electric circuits which were studied by the inventor prior to the present invention; Figure 5 shows a measurement circuit for experimenting on a circuit operation# in Figure 4; Figure 6 is a graph showing an experimental result obtained with the measurement circuit of Figure 5; Figure 7 shows an equivalent circuit of an electric circuit according to an embodiment of the present invention; Figure 8 is a sectional view of the essential portions of the semiconductor integrated circuit of the electric circuit according to the embodiment; Figure 9 shows an equivalent circuit of an electric circuit according to a second embodiment of the present invention; Figure 10 shows an equivalent circuit of an electric circuit according to a third embodiment of the present invention; ; Figure 11 shows an equivalent circuit of an electric circuit according to a fourth embodiment of the present invention; and Figures 12A and 12B are circuit diagrams of a signal processing circuit according to another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIFIENTS Several embodiments according to the present invention will now be described with reference to the drawings. Figure 7 shows an equivalent circuit of an electric circuit for detecting the maximum value of a plurality of input currents, according to an embodiment of the present invention. Circuit elements inside a two-dot chain line IC are formed within the sili#con chip of a monolithic semiconductor integrated circuit. Such electric circuit, that is, a composite current mirror circuit includes a first current mirror circuit 14 and a second current mirror circuit 15 which are constructed of lateral PNP transistors Ql - Q5 that are formed within the silicon chip. Terminals 20, 21, 23 and 24 are the external terminals of the semiconductor integrated circuit. A first current source 31 is connected to the input terminal 20 of the first current mirror circuit 14, a second current source 32 is connected to the input terminal 21 of the second current mirror circuit 15, a load 40 is connected to the common output terminal 23 of the first current mirror circuit 14 and the second current mirror circuit 15, and the power supply terminal 24 is fed with a supply voltage Vcc. Further, according to the present invention, parasitic PNP transistors Qpl and Qp4 as additional transistors are respectively connected to the PNP transistors Q1 and Q4 Figure 8 shows a sectional view of the essential portions of the semiconductor integrated circuit acpording to the embodiment. N -type buried layers 801 and 802 are formed in the top surface of a P-type silicon substrate 800, and N-type epitaxially grown layers 803, 804 and 805 are further formed thereon. In the N-type epitaxially grown layer 804, there are formed a plurality of P-type impurity diffused layers 806, 807, 808 and 809 and an N -type impurity diffused layer 810. In the surface of the N-type epitaxially grown layer 804, the P-type diffused layer 807 surrounds the P-type diffused layer 806 in the form of a ring, the P-type diffused layer 809 surrounds the P-type diffused layer 808 in the form of a ring, and the N+-type diffused layer 810 surrounds these P-type diffused layers 806, 807, 808 and 809. Further, an isolation region 811 is formed in the N-type epitaxially grown layer 804 by P+-type diffusion. Emitter electrodes 812 and 813 form ohmic contacts with the P-type diffused layers 806 and 808 respectively, collector electrodes 814 and 815 form ohmic contacts with the P-type diffused layers 807 and 809 respectively, and a base electrode 816 forms an ohmic contact with the N type diffused layer 810. An electrode 817 which forms an ohmic contact with the rear surface of the P-type substrate 800 is connected to an earth potential point. Thus, the lateral PNP transistor Q1 is formed of the P-type diffused layers 806, 807, N-type epitaxial layer 804 and N+-type diffused layer 810, while the lateral PNP transistor Q4 is formed of the P-type diffused layers 808, 809, N-type epitaxial layer 804 and N+-type diffused layer 810. To be specially mentioned is that the first parasitic PNP transistor Qpl as the additional transistor is formed of the P-type diffused layer 807, N-type epitaxial layer 804 and P-type substrate 800, while the second parasitic PNP transistor Qp4 as the additional transistor is formed of the P-type diffused layer 809, N-type epitaxial layer 804 and P-type substrate 800. Equivalently, the emitters of the parasitic PNP transistors Qp1 and Qp4 are respectively connected to the collectors of the lateral PNP transistors Q1 and Q4, the bases of the parasitic PNP transistors Qp1 and Qp4 are respectively connected to the bases of the lateral PNP transistors Q1 and Q4, and the collectors of the parasitic PNP transistors Q1 and Q4 are connected to the earth potential point. According to the embodiment of the present invention shown in Figures 7 and 8, the maximum value of a plurality of input currents can be detected with high precision for reasons described below. In a case where the first input current Iinl of the first current source 31 is greater than the second input current Iin2 of the second current source 32, there is the danger that the PNP transistor Q4 receiving the smaller current 1in2 will be driven into its saturation region. In this case, as illustrated in Figure 7, at the same time that the collector-base junction of the PNP transistor Q4is forward-biased, the emitter-base junction of the parasitic PNP transistor Qp4 is also forward-biased. Accordingly, the collector current of ofthe PNP transistor Q4 flows to the earth potential point via the emitter-collector path of the parasitic PNP transistor Qp4. Thus, in the case of Iinl > 1in2' it becomes possible to reduce the inflow of the transistor saturation current 1SAT of the PNP transistor Q4 to the load 40. On the contrary, in a case of Iinl < 1in2' the PNP transistor Q1 receiving the smaller current Iinl is in danger of being driven into its saturation region. In this case, as illustrated in Figure 7, at the same time that the collector-base junction of the PNP transistor Q1 is forward-biased, the emitter-base junction of the parasitic PNP transistor Qp1 is also forward-biased. Accordingly, the collector current Ill of the PNP transistor Q1 flows to the earth potential point via the emittercollector path of the parasitic PNP transistor QP1. Thus, in the case of Iinl < Iin2, it becomes possible to reduce the inflow,of the transistor saturation current ISAT of the PNP transistor Q1 to the load 40. The experimental result of the current comparing operation of the embodiment of the present invention shown in Figures 7 and 8, the result having been obtained with the measurement circuit of Figure 5, is indicated by a characteristic curve 22 in Figure 6. It has been verified that the characteristic curve #2 of Figure 6 of agrees at very high precision with an ideal current comparing operation in the case where the base-emitter voltage VBE of each of the PNP transistors Q1 - Q5 in the composite current mirror circuit of Figure 7 is 0.7 volt Figure 9 shows an equivalent circuit of an electric circuit for detecting the maximum value of a plurality of input currents, according to a second embodiment of the present invention. Circuit elements inside a two-dot chain line IC are formed within the silicon chip of a monolithic semiconductor integrated circuit. Transistors Q1 - Q5 are lateral PNP transistors, and the collectors and bases of the respective PNP transistors Q1, Q4 are connected through the base-emitter junctions of the other PNP transistors Q3, Qs. Further, parasitic PNP transistors Qp1# Qp4 are equivalently connected to the respective PNP transistors Q1 Q4 as additional transistors. In particular, the PNP transistors Q1' Q4 and the parasitic PNP transistors QP1' QP4 are constructed as shown in the sectional view of Figure 8. As regards the others, the same parts as in Figure 7 are assigned the same reference numerals and will be omitted from description. Also with such embodiment, in the case of Iinl > Iin2 or Iinl < 1in2' the parasitic PNP transistor Qp4 or QP1 turns "on" respectively, to permit reduction in the inflow of the transistor saturation current ISAT of the PNP transistor Q4 or Q1 to the load 40. Figure 10 shows an equivalent circuit of an electric circuit for detecting the maximum value of a plurality of input currents, according to a third embodiment of the present invention. Circuit elements inside a two-dot chain line IC are formed within the silicon chip of a monolithic semiconductor integrated circuit. Transistors Q1 - Q5 are lateral PNP transistors, while transistors are Q7 are vertical NPN transistors. Especially different from the embodiment of Figure 9 is that the NPN transistors %, Q7 are respectively connected to the PNP transistors Q3, Q5 and that the emitters of both the transistors Q6, Q7 are supplied with a bias voltage VB. Parasitic PNP transistors QP19 Qp4 are equivalently connected to the respective PNP transistors Q1, Q4 as additional transistors. In particular, the PNP transistors Ql, Q4 and the parasitic PNP transistors Qp#, Qp4 are constructed as shown-in the sectional view of Figure 8. Also with such embodiment, it is permitted in the case of Iinl > Iin2 or Iinl < Iin2 to reduce the inflow of the transistor saturation current ISAT to the load 40. Figure 11 shows an equivalent circuit of an electric circuit for detecting the maximum value of a plurality of input currents, according to a fourth embodiment of the present invention. Circuit elements inside a two-dot chain line IC are formed within the silicon chip of a monolithic semiconductor integrated circuit. Transistors Q1' Q2 and Q4 are lateral PNP transistors, while transistors Q3 and Q5 are vertical NPN transistors. The bases and collectors of the respective PNP transistors O1 Q4 are connected through the collector-emitter paths of the NPN transistors Q3, Q5, and the bases of both the transistors Q3, Q5 are supplied with a bias voltage VB. Parasitic PNP transistors Owpl Qp4 are equivalently connected to the respective PNP transistors Q1, Q4 as additional transistors. In particular, the PNP transistors Q1, Q4 and the parasitic PNP transistors QP1 Qp4 are constructed as shown in the sectional view of Figure 8. Also with such embodiment, it is permitted in the case of Iinl > Iin2 or Iinl < 1in2 to reduce the inflow of the transistor saturation current ISAT to the load 40. Figures 12A and 12B show circuit diagrams of a signal processing circuit according to another embodiment of the present invention. Such signal processing circuit is a CX (Compatible Expansion) type expander, and is effective for the noise reduction of a record or the audio system of an optical video disk. The principle of such signal processing circuit as a noise reduction system is reported in IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, November 1981, Volume CE-27, Number 4, pp. 626 - 630, and should be referred to. Circuit elements inside a two-dot chain line IC are formed within the silicon chip of a monolithic semiconductor integrated circuit, and the other circuit elements are constructed of discrete components. A right channel audio input signal and a left channel audio input signal, which have been compressed by a CX type compressor, are respectively supplied to No. 1 terminal and No. 2 terminal through coupling capacitors C100 and C101 and are respectively amplified by a first input amplifier 121 and a second input amplifier 122. The first input amplifier 121 is constructed of transistors Q12' resistors R1 - R14 and a phase compensation capacitor C1, while the second input amplifier 122 is constructed of transistors Q13 - Q24 resistors R15 - R28 and a phase compensation capacitor C2. The output signal of the first input amplifier 121 provided from No. 16 terminal is supplied through a coupling capacitor C102 to No. 15 terminal which is the input terminal of a first full-wave rectifier 123, while the output signal of the second input amplifier 122 provided from No. 14 terminal is supplied through a coupling capacitor C103 to No. 13 terminal which is the input terminal of a second full-wave rectifier 124. The first full-wave rectifier 123 is constructed of transistors Q25 - Q33 and Q35 -Q37 resistors R29' R53 and a phase compensation capacitor C3, thereby to provide a first full-wave rectification current at a node N1. The second full-wave rectifier 124 is constructed of transistors Q38 - Q46 and Q48 - Q50, resistors R38 - R and a phase compensation capacitor C4, thereby to provide a second full-wave rectification current at a node N2. Such full-wave rectifier is reported in detail in Japanese Laid-open Patent Application No. 52-123850, and should be referred to. A maximum current detector 125 includes a first current mirror circuit 125A which is constructed of PNP transistors Q34, Q51 and Q53, and a second current mirror circuit 125B which is constructed of PNP transistors Q47' Q51 and Q52. A load resistor R47 is connected to the common output terminal N3 of the first current mirror circuit 125A and the second current mirror circuit 125B. The PNP transistors Q34 and Q47 are respectively formed as shown by the lateral PNP transistors Q1 and Q4 in the sectional view of Figure 8. As in each of the foregoing embodiments, therefore, parasitic PNP transistors are equivalently connected to the respective PNP transistors Q34 and Q47 as additional transistors. Accordingly, in a case where the first full-wave rectification current of the node N1 is greater than the second full-wave rectification current of the node N2, or in the converse case, either of the two parasitic PNP transistors turns "on", and the inflow of the transistor saturation current 1SAT of the PNP transistor Q34 or Q47 to the load R47 can be reduced. A maximum current detection output signal having developed across the load R47 is supplied through a wiring lead L4 to the input of a peak detector 126 (the base of a transistor Q84). Such peak detector 126 is constructed of transistors Q84 - Q107, resistors R66 - 84 phase compensation capacitors C5 and C6 and a peak holding capacitor C106. A peak hold voltage is generated at No. 12 terminal. This peak hold voltage produced at No. 12 terminal is transmitted to No. ill terminal through a low output impedance buffer circuit 127 which is constructed of transistors Q108 - Q114 and resistors R85 and R86. Connected to No. 10 and No. 11 terminals is a time constant circuit 128 which is constructed of transistors Q115 and Q1169 resistors R87, R88 and R108 - R110 and capacitors C107 and C108. A rising time constant of about 30 msec is determined by the resistor R87 and the capacitor C108 while a decaying time constant of about 200 msec is determined by the resistor R88 and the capacitor C108. A first control circuit 129, which is controlled by a control switch SW connected to No. 5 terminal, is constructed of transistors Q117 - Q125 and resistors R89 - R97. When the control switch 5W has become the "on" state, the transistor Q120 of the first control circuit 129 falls into the "off" state, the transistor Q121 into the "on" state and the transistors Q124 and Q125 into the "off" states. At this time, a transistor Q130 falls into the "ont' state and a transistor Q133 into the "off" state in a switching type low output impedance buffer circuit 130 which is constructed of transistors ¯ Q134 and resistors R98, R99 and R200 - R Accordingly, the voltage of No. 10 terminal is transmitted to the input terminal of a second control circuit 131 (the base of a transistor Q135) through the transistors Q126 ¯ Q129 and resistor R203 of the buffer circuit 130. On the other hand, the second control circuit 131 is constructed of transistors Q135 - Q148' resistors R204 - R211 and a phase compensation capacitor C7. A first bias circuit 132, which is constructed of transistors Q149 ¯ Q152 and resistors R212 - R215' supplies a fixed voltage to a resistor R21l. s The capacitor C107 and resistors R108 and R109, which are connected to No. 11 terminal, constitute a high-pass filter. The output signal of the high-pass filter at the common juncture of the resistors R108 and R109 is transmitted to the base of the transistor Q148 through No. 9 terminal. Since the transistors Q145 - Q14? connected to the collector of the transistor Q148 constitute a current mirror circuit, the signal transmitted from No. 10 terminal and the signal transmitted from No. 11 terminal are added to each other at the input terminal.of the second control circuit 131 (the base of the transistor Q135). The addition signal is transmitted to the collector of the PNP transistor Q141 as well as Q142 X and is further transmitted to a third control circuit 133 through a wiring lead L6. The third control circuit 133 is constructed of transistors Q153 and Q154 and a resistor R216, and provides a control output signal from the emitter of the transistor A first variable gain amplifier 134 is constructed of transistors Q54 - Q68 and resistors R48 - R and its gain varies depending upon the collector current value of the transistor Q65. Likewise, a second variable gain amplifier 135 is constructed of transistors Q69 - Q83 and resistors R57 - R65, and its gain varies depending upon the collector current value of the transistor Q80. Thus, the first variable gain amplifier 134 variably amplifies the output signal of the first input amplifier 121 at No. 16 terminal and transmits the amplified signal. to No. 4 terminal, while the second variable gain amplifier 135 variably amplifies the output signal of the second input amplifier 122 at No. 14 terminal and transmits the amplified signal to No. 3 terminal. It is therefore possible to obtain a right channel audio output signal and a left channel audio output signal which have been expanded by the signal processing circuit functioning as the CX type expander. A second bias circuit 136 is constructed of transistors Q155 - Q160 a Zener diode ZD and resistors R217 - R223, and generates a plurality of bias voltages. A third bias circuit 137 is constructed of transistors Q161 ¯ Q 6 and resistors R224 and R225, and generates a bias voltage Vbl at the base of the transistor Q163 A buffer circuit 138, which is constructed of transistors Q164 - Q170 and resistors R226 and R227, transmits the bias voltage at the common juncture of the resistors R219 and R220 to the emitters of the transistors Q169 and Q170 with a low output impedance. A buffer circuit 139, which is constructed of transistors Q171 & 77 and resistors R228 and R229, transmits the bias voltage at the common juncture of the resistors R220 and R to the emitters of the transistors Q176 and Q177 with a low output impedance. Accordingly, in the case where the signal processing circuit operates as the CX type expander, the gain of the first variable gain amplifier 134 and that of the second variable gain amplifier 135 are simultaneously determined by either greater one of the first full-wave rectification current of the node N1 and the second full-wave rectification current of the node N2. It is therefore possible to provide a CX type expander of high precision. When the control switch 5W connected to No. 5 terminal has become the "off" state, the transistor Q120 of the first control circuit 129 falls into the "on" state, the tra#nsistor Q121 into the "off' state and the transistor Q124 and Q125 into the "on" states. Then, such signal processing circuit stops the operation as the CX type expander. The respective embodiments of the present invention described above can adopt various modified aspects of performance within the common knowledge of those skilled in the art. By way of example, it is obvious that the electric circuit according to any of the embodiments in Figures 7, 9, 10 and 11 can be utilized as the maximum current + detector 125 in Figure 12A.

Claims: What Is Claimed Is: 1. An electric circuit comprising: (a) a first current mirror circuit (14) having a first input transistor (Q1), a first coupling transistor (Q3) and an output transistor (Q2), wherein an emitter of said first input transistor (Q1) and an emitter of said output transistor (Q2) are connected, a base of said first input transistor (Q1) and a base of said output transistor (Q2) are connected, a collector and the base of said first input transistor (Q1) are connected through said first coupling transistor (Q3), a first input terminal ( o0 ) is connected to the collector of said first input transistor (Q1)' and an output terminal ( @ ) is connected to a collector of said output transistor (Q2); ; and (b) a second current mirror circuit (15) having a second input transistor (Q4), a second coupling transistor (Q5) and the output transistor (Q2), wherein an emitter of said second input transistor (Q4) and the emitter of said output transistor (Q2) are connected, a base of said second input transistor (Q4) and the base of said output transistor (Q2) are connected, a collector and the base of said second input transistor (Q4) are connected through said second coupling transistor (Q5), a second input terminal ( # ) is copnected to the collector of said second input transistor (Q4), and said second current mirror circuit (15) has an output terminal common to said output terminal of said first current mirror circuit (14); ; said first current mirror circuit (14) further having a first additional transistor ( QP1) whose emitter, base and collector are respectively connected to the collector and base of said first input transistor (Ql) and a reference potential, while said second current mirror circuit (15) further has a second additional transistor (Qp4) whose emitter, base and collector are respectively connected to the collector and base of said second input transistor (Q4) and the reference potential; ; said first input terminal (#0)) being supplied with a first input current (Iinl) and said second input terminal ( @ )¯ with a second input current ((Iin2), whereby an output current ((IoUT) proportional to either greater value of the two input currents (IinlX Iin2) is provided from said common output terminal (#). 2. An electric circuit according to Claim 1, wherein the base of said first input transistor (Q1) and the base of said second input transistor (Q4) are formed of an N-type semiconductor layer- (804) on a P-type semiconductor substrate (800), and the collector of said first input transistor (Ql) and the collector of said second input transistor (Q4) are respectively formed of a first P-type semiconductor layer (807) and a second P-type semiconductor layer (809) which are formed within said N-type semiconductor layer (804); with the result that equivalently the emitter of said first additional transistor (QP1) is formed of said first P-type semiconductor layer (807), that equivalently the emitter of said second additional transistor (Qp4) is formed of said second P-type semiconductor slayer (809), that equivalently the base of said first additional transistor (Qp1) and the base of said second additional transistor (Qp4) are formed of said N-type semiconductor layer (804), and-that equivalently the collector of said first additional transistor (up1) and the collector of said second additional transistor (up4) are formed of said P-type semiconductor substrate (800). 3. A signal processing circuit comprising: (a) a first input amplifier (121) for amplifying a first input signal; (b) a second input amplifier (122) for amplifying a second input signal; (c) a first rectifier (123) for producing a first rectified current from an A.C. output signal of said first input amplifier (121)-; (d) a second rectifier (124) for producing a second rectified current from an A.C. output signal of said second input amplifier (122); (e) a maximum current detector (125) for producing an output signal which is proportional to either greater value of the first and second rectified currents; (f) a peak detector (126) whose input terminal is connected to an output terminal of said maximum current detector (125); (g) a time constant circuit (128) whose input terminal is connected to an output terminal of said peak detector (126); ; (h) a first variable gain amplifier circuit (134) which is so constructed that its input terminal is supplied with the output signal of said first input amplifier (121), and its gain is controlled by an output signal of said time constant circuit (128), whereby a first expanded output signal is provided from its output terminal; and (i) a second variable gain amplifier circuit (135) which is so constructed that its input terminal is supplied with the output signal of said second input amplifier (122), and its gain is controlled by the output signal of said time constant circuit (128), whereby a second expanded output signal is provided from its output terminal; wherein said maximum current detector (125) comprises; ; (1) a first current mirror circuit (125A) having a first input transistor (Q34), a first coupling transistor (Q53) and an output transistor (Q51), wherein an emitter of said first input transistor (Q34) and an emitter of said output transistor (Q51) are connected, a base of said first input transistor (Q34) and a base of said output transistor (Q51) are connected, a collector and the base of said first input transistor (Q34) are connected through said first coupling transistor ( Q55), a first input terminal (N1) is connected to the collector of said first input transistor (Q34), and the output terminal (N3) is connected to a collector of said output transistor (Q51); ; and (2) a second current mirror circuit (125B) having a second input transistor (Q47), a second coupling transistor (Q52) and the output transistor (Q51), wherein an emitter of said second input transistor (Q47) and the emitter of said output transistor (Q51) are connected, a base of said second input transistor (Q47) and the base of said output transistor (Q51) are connected, a collector and the base of said second input transistor (Q47) are connected through said second coupling transistor (Q52), a second input terminal (N2) is connected to the collector of said second input transistor (Q47), and said output terminal (N3) is connected to the collector of said output transistor (Q51)i and wherein said first current mirror circuit (125A) further has a first additional transistor (up1) whose emitter, base and collector are respectively connected to the collector and base of said first input transistor (Q34) and a reference potential, while said second current mirror circuit (125B) further has a second additonal transistor (Qp4) whose emitter, base and collector are respectively connected to the collector and base of said second input transistor (Q47) and the reference potential, and said first input terminal (N1) is supplied with the first rectified current, while said second input terminal (N2) is supplied with the second rectified current. 4. A signal processing circuit according to Claim 3, wherein the base of said first input transistor (Q34) - and the base of said second input transistor (Q47) are formed of an N-type semiconductor layer (804) on a P-type semiconductor substrate (800), and the collector of said first input transistor (Q34) and the collector of said second input transistor (Q47) are respectively formed of a first P-type semiconductor layer (807) and a second P-type semiconductor layer (809) which are formed within said N-type semiconductor layer (804); with the result that equivalently the emitter of said first additional transistor (QP1? is formed of said first P-type semiconductor layer (807), that equivalently the emitter of said second additional transistor (Qp4) is formed of said second P-type semiconductor layer (809), that equivalently the base of said first additional transistor (up1) and the base of said second additional transistor (Qp4) are formed of said N-type semiconductor layer (804), and that equivalently the collector of said first additional transistor (QP1) and the collector of said second additional transistor (Qp4) are formed of said P-type semiconductor substrate (800).

Inventors: SATO, TETSUO
Applicants: HITACHI, LTD.
Application year: 1982
Main classification: H03G7
IPC codes: H03G7, H03F3, G01R19, H03G9, H03G3