MULTI-EMITTER TYPE NPN TRANSISTOR

Abstract: A multi-emitter type npn transistor comprising: an n-type collector region (24), a p-type base region (28), a plurality of n-type emitter regions (30-1, 30-2) formed in the base region (28), a collector electrode (36) which is in contact with the collector region (24), a base electrode (40) which is in contact with that portion of the base region (28) which lies between any two adjacent ones of the plurality of emitter regions (30-1, 30-2), and a plurality of emitter electrodes (38-1, 38-2) which are in contact with the plurality of emitter regions (30-1, 30-2), respectively.

Description: Multi-emitter type npn transistor The present invention relates to a multi-emitter type npn transistor. A multi-emitter type npn transistor generally has a structure as shown in Figs. 1 and 2. However, with the structure as shown in Figs. 1 and 2, there is a problem of the formation of a parasitic lateral npn transistor at a region indicated by the broken line, that is, between the two adjacent emitter regions. Describing this in further detail, a conventional npn transistor, as shown in Figs. 1 and 2, comprises a p-type substrate 2, an n-type epytaxial layer 4 formed + on the substrate 2, an n -type region 6 for collector contact formed in the epytaxial layer 4 by the diffusion of an n-type impurity, a p+-type base region 8 formed in the epytaxial layer 4 by the diffusion of a p-type impurity, emitter regions 10-1 and 10-2 formed in the base region 8 by the diffusion of an n -type impurity, a p+-type isolation region 11, an insulation film 12 having contact holes of predetermined pattern formed on the major surface of the semiconductor body of this construction, and electrodes 14, 16-1, 16-2 and 18 which are in contact with the regions 6, 10-1, 10-2 and 8 through contact holes formed in the insulation film 12. The isolation region 11 and insulation film 12 are omitted in Fig. 1 for simplification. Since the two emitter regions 10-1 and 10-2 are arranged relatively close to each other, the electrons injected to the base region 8 from one emitter region 10-1, for example, reach the other emitter region 10-2, forming a parasitic lateral npn transistor 20 having the emitter region 10-1 as an emitter, the base region 8 as a base, and the emitter region 10-2 as a collector. This parasitic lateral npn transistor affects the original function of the logic circuit formed on the epytaxial layer 4, resulting in erroneous operation of the logic circuit. The present invention has been made in consideration of this and has for its object to provide a multiemitter type npn transistor of a construction so that the formation of an undesirable parasitic lateral npn transistor may be prevented. In order to achieve this object, there is provided according to the present invention, a multi-emitter type npn transistor comprising: a collector region of n conductivity type, a base region of p conductivity type, a plurality of emitter regions of n conductivity type formed in said base region, a collector electrode which is in contact with said collector region, a base electrode which is in contact with said base region at that portion thereof which is between any two adjacent ones of said plurality of emitter regions, and a plurality of emitter electrodes which are in contact with the plurality of emitter regions, respectively. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a plan view showing the configuration of a conventional multi-emitter type npn transistor; Fig. 2 is a sectional view of the transistor viewed along the line II - II of Fig. 1 indicated by the arrows; Fig. 3 is a plan view of a multi-emitter type npn transistor according to an embodiment of the present invention; Fig. 4 is a sectional view of the transistor viewed along the line IV - IV of Fig. 3 indicated by the arrows; ; Fig. 5 is a graph showing the characteristic curves of the current amplification ss as a function of the base current IB of the conventional multi-emitter npn type transistor shown in Figs. 1 and 2 and the multi-emitter npn type transistor of the present invention shown in Figs. 3 and 4; Fig. 6 is a plan view of a multi-emitter type npn transitor according to another embodiment of the present invention; Fig. 7 is a sectional view of the transistor viewed along the line VI - VI of Fig. 6 indicated by the arrows; and Figs. 8 and 9 are plan views of multi-emitter type npn transistors according to other embodiments of the present invention. Figs. 3 and 4 show a multi-emitter type npn transistor according to an embodiment of the present invention. According to this embodiment, an n-type epytaxial layer 24 is formed on a silicon substrate 22 of p conductivity type. In the epytaxial layer 24 are + formed an n -type collector contact region 26, and a p+-type base region 28. Within the p -type base region 28 are formed two emitter regions 30-1 and 30-2. A p -type region 32 is an isolation region. The epytaxial layer 24 defines the collector region. An insulation film 34 of, for example, SiO2 (silicon dioxide) having contact holes of predetermined pattern is formed on the major surface of the semiconductor body of this configuration. Electrodes 36, 38-1, 38-2 and 40 of aluminum, for example, are formed in the n+-type collector contact region 26, the n-type emitter regions 30-1 and + 30-2, and the p+-type base region 28 through the contact holes formed in the insulation film 34. The isolation region 32 and insulation film 34 are omitted in Fig. 3 for the sake of simplification. In the npn transistor of the configuration as described above, the contact hole for contact with the base is formed at the position of the midpoint between the emitter regions 30-1 and 30-2. A base electrode 40 is formed on the p+-type base region 28 through this base region contact hole. In other words, the base electrode 40 is in contact with the part of the base region 28 which is between the two adjacent emitter regions 30-1 and 30-2. In the npn transistor of this configuration, during operation, the base electrode 40 is connected to an external power supply of positive potential to be kept at a positive potential, and the p-n junction between the p+-type base region 28 and the emitter regions 30-1 and 30-2 is biased in the forward direction. Therefore, most of the electrons injected into the base region 28 from the emitter electrode 38-1 through the emitter region 30-1 are attracted toward the interface between the base region 28 and the base electrode 40 and are recombined with the holes at this interface. As a consequence, the electrons which are injected into the base region 28 from the emitter region 30-1 are prevented from reaching the emitter region 30-2, so that the formation of the parasitic lateral npn transistor of the regions 30-1, 28 and 30-2 is prevented. This is seen from the characteristic curves of the current amplification ss as a function of the base current 1B for the conventional npn transistor shown in Figs. 1 and 2 and the npn transistor according to the present invention shown in Figs. 3 and 4. Referring to Fig. 5, curve I is the characteristic curve for the conventional npn transistor, and curve II is the characteristic curve for the npn transistor of the present invention. The ordinate and abscissa in Fig. 5 are both logarithmic scales. The distance between the emitters on the mask during the manufacture of the conventional npn transistor of the curve I was set to 40 pm, and the distance between the emitters on the mask during the manufacture of the npn transistor of the present invention of the curve II was set to 30 pm. Thus the distance between the emitters in the npn transistor according to the present invention is set smaller than the distance between the emitter regions of the conventional npn transistor. Despite this fact, as may be seen from Fig. 5, the current amplification ss of the conventional npn transistor (curve I) is 2 to 4 while the current amplification ss of the npn transistor (curve II) of the present invention is about 0.1 in the low current range and is 0.5 to 0.7 even in the high current range. In this way, it is seen that the npn transistor of the present invention shown in Fig. 4 achieves better results than the npn transistor shown in Figs. 1 and 2. Figs. 6 and 7 show another embodiment of the present invention, wherein the number of the emitter regions is increased. Since the configuration of the npn transistor of this embodiment is substantially the same except for the emitter regions and the emitter electrodes as the embodiment shown in Figs. 3 and 4, the same reference numerals denote the same parts and the description thereof will be omitted. Base region contact holes are formed at the positions of the insulation film which correspond to the emitter regions 30-1, 30-2, 30-3 and 30-4. A base electrode 42-1 is in contact with the base region portion between the emitter regions 30-1 and 30-2, base electrode 42-2 is in contact with the base region portion between the emitter regions 30-2 and 30-3. A base electrode 42-3 is in contact with the base region portion between the emitter regions 30-3 and 30-4. A base electrode 44 is in contact with the base region portion which is not sandwiched between the emitter regions (the right edge of the base region 28 shown in Figs. 6 and 7) through the contact hole. The isolation region 32 and insulation film 34 are omitted in Fig. 6. The base electrode 44 is for connection with an external power supply (not shown) at positive potential and is connected with such an external power supply during operation. On the other hand, the base electrodes 42-1, 42-2 and 42-3 are the electrodes for attracting the electrons. Although these electrodes 42-1, 42-2 and 42-3 are not directly connected to the external power supply, they are electrically connected to the external power supply through the base region 28 since the base electrode 44 is connected to the external power supply to be kept at a positive potential. Therefore, these electrodes 42-1, 42-2 and 42-3 are kept at substantially the same positive potential (potential of the external power supply) as the base electrode 44. Therefore, as in the case of the embodiment shown in Figs. 3 and 4, the electrons injected to the base region 28 from the emitter regions 30-1, 30-2 and 30-3, and 30-4 are attracted to the base electrodes 42-1, 42-2 and 42-3 and the interfaces between these base electrodes and the base region 28 so that these electrons may be recombined with the holes at these interfaces. In this manner, the electrons injected into the base region 28 are prevented from reaching the other emitter regions, so that the formation of lateral npn transistors between the adjacent emitter regions is prevented. In the embodiment shown in Figs. 6 and 7, the base electrodes 42-1, 42-2 and 42-3 are electrically connected to the base electrode 44 for connection with the external power supply through the base region 28, so that the base electrodes are kept at substantially the same potential as the base electrode 44. However, the present invention is not limited to this configuration. For example, as shown in Fig. 8, the layer defining the base electrodes 42-1, 42-2 and 42-3 is extended to form a common connection layer to which an external power supply is connected. In this case, all the base electrodes 42-1, 42-2 and 42-3 are directly connected to the external power supply. In this case, the base electrode 44 for connection with the external power supply in the embodiment shown in Figs. 6 and 7 is not necessary. Furthermore, at least one of the base electrodes 42-1, 42-2 and 42-3, for example, the base electrode 42-1 as shown in Fig. 9 may be extended and may be connected to the external power supply. In this case, as in the case of the embodiment shown in Figs. 6 and 7, the base electrodes 42-2 and 42-3 are electrically connected to the base electrode 42-1 through the base region 28, so that the base electrodes 42-2 and 42-3 are kept at substantially the same potential as the base electrode 42-1 (potential of the external power supply). In this case, the base electrode 44 for connection with the external power supply as in Figs. 6 and 7 need not be formed. In any of the embodiments described above, it is preferable to space the base electrodes sufficiently apart in order to enhance the effect of attracting the electrons. In summary, according to the present invention, in a multi-emitter type npn transistor, a base electrode is arranged at the base region portion between two adjacent emitter regions. During operation, a positive voltage is applied to the base electrode, so that the electrons injected into the base region from one emitter region may be attracted to the interface between the base electrode and the base region to be recombined with the holes at this interface. Therefore, injected electrons are prevented from reaching the other emitter region, and the formation of a parasitic lateral npn transistor may be prevented. The present invention is not limited to the particualr embodiments described above. It is to be understood that various other changes and modifications may be made within the spirit and scope of the present invention.

Claims: Claims: 1. A multi-emitter type npn transistor comprising: a collector region (24) of n conductivity type, a base region (28) of p conductivity type, a plurality of emitter regions (30-1, 30-2, 30-3, 30-4) of n conductivity type formed in said base region (28), a collector electrode (6) which is in contact with said collector region (24), and a plurality of emitter electrodes (38-1, 38-2, 38-3, 38-4) which are in contact with the plurality of emitter regions (30-1, 30-2, 30-3, 30-4), respectively, characterized in that a base electrode (40, 42-1, 42-2, 42-3) is provided which is in contact with that portion of said base region (28) which lies between any two adjacent ones of said plurality of emitter regions (30-1, 30-2, 30-3, 30-4). 2. A multi-emitter type npn transitor according to claim 1, wherein at least one of said base electrodes (40, 42-1, 42-2, 42-3) is an electrode to be connected to an external power supply. 3. A multi-emitter type npn transistor according to claim 1, wherein said base electrodes (42-1, 42-2, 42-3) are connected one to another and connected commonly to an external power supply. 4. A multi-emitter type npn transistor according to claim 1, including a further base electrode (44) which is connected to an external power supply. 5. A multi-emitter type npn transistor according to claim 2, 3 or 4, wherein said base electrode (40, 42-1, 42-2, 42-3, 42-4) connected to the external power supply is set at a positive potential.

Inventors: NAKAI, MASANORI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1982
Main classification: H01L29
IPC codes: H01L29, H01L21