D-A CONVERTER

Abstract: A D-A converter in which the time constant of an integrating circuit (4) can be reduced and a high-speed operation becomes possible. The D-A converter is advan­ tageous in that, if the amount of a ripple contained in an analog output of the converter is equal to that of the conventional converter, the time constant of the integrating circuit can be reduced with the result that the conversion speed can be improved. Separates most significant and least significant bits of digital input and treats separately. Most significant preset a down counter (2) whose output is combined with a divided clock signal (Q L ) by a gate circuit (15) to provide a signal (43). Least significant bits control a set of signals (Q₃* to Q₄*) derived from clock (Q o ) in order to pseudo-randomise ripple-producing components and to provide second signal (41). Signals (41 and 43) are combined and integrated to produce analogue output.

Description: D-A CONVERTER The present invention relates to a D-A converter for converting digital data composed of most significant M bits DN+ ---' D DN+M, and least significant N bits D1, ---, DN where M and N are positive integers respectively into an analog quantity. Such a converter may be used in a pulse width modulation system. Fig. 1 shows a converter for a conventional pulse width modulation system, and Fig. 2 illustrates operation of the modulation system. The conventional system will now be explained briefly. Referring to Fig. 1, the system comprises a frequency divider 1 having a counter incorporated therein, a programmable counter 2, a preset circuit 3, and an integrating circuit 4. In Fig. 2 is shown a reference clock signal QO, an output signal 5 of the frequency didiver 1, and an output signal 6 of the prgrammable counter 2. First, the frequency of reference clock signal QO is divided by the-frequency divider 1 to determine a period of the output signal 6, that is, an interval 22 in Fig. 2 is determined. At a time 23, a value corresponding to a digital data D1 - DN is preset in the programmable counter 2 through the preset circuit 3. The preset value in the programmable counter 2 is subtracted by the clock QO, and the output signal 6 is held in "14" level during the subtraction. If the content of the programmable counter 2 becomes 0 at time 24, the output signal 6 is made "L" level and the subtracting operation is terminated. In the next output signal period, the output signal 6 having pulse width corresponding to the digital data D1 - DN is obtained again and is passed through the integrating circuit 4, thereby an analog output corresponding to the digital data D1 - DN is obtained. In abovementioned system, however, the width 21 of "H" level of the output 6 is in a specific position within the pulse period as shown in Fig 2. Therefore, when the output pulse waveform is expanded into Fourier series, the first order term becomes large and the fundamental frequency becomes small. In order to reduce ripple components of the output of the integrating circuit 4, the time constant of the integrating circuit must be creased, resulting in that the operation speed becomes low. In view of abovementioned disadvantages, the present invention is in' tended-to-provide a D-A converter in which the time constant of the integrating circuit can be reduced and a high-speed operation becomes possible. According to the invention, there is provided a D-A converter for converting digital data composed of most significant M bits DN+1, ---, DN+ and least significant N bits D1, ---, DN where M and N are positive integers re spectively into an analog quantity, characterised by: a frequency dividing circuit having M+N frequency dividers connected in tandem, a first frequency divider of said M+N frequency dividers being adapted to receive an input clock signal ao and the remaining frequency dividers being adapted to generate output signals Q1, --- , QN, QN+1, --- and QN+M, respectively; a programmable counter of M bits for receiving the input clock signal QO; a preset circuit for receiving a signal QL which has the same period as that of said output signal QN and is at a first level during an interval corresponding to one period of said clock signal QO and at a second level during the remaining portion of its period to preset values corresponding to the most significant M bits data DN+1, --- , DN+M into said programmable counter when said output signal QL is at said frist level; a first gate circuit for being set when said output signal QL changes state from said first level to said second level and reset when the content of said programmable counter becomes a predetermined preset value; a decoder circuit for receiving said output signal QL and outputs of said frequency divider circuit to generate output signals Q Ir M+1' Q , --- and whose M+2 periods at a predetermined level do not overlap each other; a second gate circuit for receiving least significant N bits data D1, --- , DN to control said output signals of said decoder circuit; and an integrating circuit for integrating the. sum of the output signals of said first and second gate circuits. For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram of an example of a prior art D-A converter; Fig. 2 is a timing diagram illustrating the operation of Fig. 1; Fig. 3 is a block diagram of an embodiment of the present invention; and Fig. 4 is a timing diagram illustrating the operating of Fig. 3. An embodiment of the present invention will now be explained referring to Figs. 3 and 4. In Fig. 3 an integrating type D-A converter comprises a frequency dividing circuit 1 including five frequency dividers connected in tandem to produce output signals Q1' --- , Q5, a programmable counter 2 of two bits, a preset circuit 3, an integrating circuit 4, a gate circuit 15 to hold output constant during a certain time, AND circuits 31 - 33, and OR circuits 34, 35. It is assumed that a digital quantity having five bits D1, D2, D3, D4, and D5 of 1, 0, 1, 0 and 1, respectively, be inputted. First, output according to the data D4, D5 corresponding to most significant two bits will be explained. Values corresponding to D4; D5, for example, values 0, 1, 2 or 3 in decimal notation when binary digital data D4, D5 are [0.0] [1.0] [0.1] or [1.1], respectively, are preset to the programmable counter 2 through the preset circut 3 in response to preset signal QL shown in Fig. 4. Preset timing is determined by the preset signal QL in "H" level having a width corresponding to one period of clock QO per every four periods of QO (one period of QLT i.e. QL has a period equal to that of Q2)- The programmable counter 2 counts clock Q0 from trailing edge time of QLT and when the content of the counter attains a prescribed value, i. e. value 0 in this example, the counter 2 provides an output signal 42 in Fig. 3 to be sent to the gate circuit 15. An output 43 of the gate circuit 15 holds "H" level during end period from the trailing edge of present signal QL until the next leading edge of the signal 42. An output according to data D1, D2 and D3 corresponding to least significant three bits will now be explained. The reference clock Q0 is applied to the frequency dividing circuit 1 to obtain output signals Q3 - Q5 in Fig. 4 from the respective frequency dividers in the third, fourth and fifth stages. The output signals Q3 - Q5 and the signal QL are supplied to the decoder circuit 16, and output signals Q*3 Q*5 are obtained therefrom by a logic operation according to the following equations (1). 9 3 . =. Q 4 Q3 W QL (1) Q*5 = The output signals thus obtained are processed by the AND circuits 31 - 33-in-response to data bits D1 - D3, and output signals of AND circuits 31 - 33 are entered to the OR circuit 34 from which a pulse output 41 is obtained. This pulse output 41 and the aforementioned pulse output 43 are supplied to the-OR circuit 35, and output 44 of the circuit 35 is integrated by means of the integrating circuit 4. Therefore an analog output corresponding to digital data D1 - D5 is obtained. As clearly seen, the period of the output 44 is constituted from eight intervals T1 - T8 shown in Fig. 4. The difference in time duration of the "H" levels between the intervals T1 - T8 is at most one corresponding to one period of QO and so the period of the output 44 can be approximated by an interval T1, that is, 1/8 of T1 + --- +T8 = T1. When this pulse output passes through the integrating circuit 4, ripple component of analog output can be reduced. If the number of bits in the digital data is made equal to that of the pulse output 6 from the conventional D-A converter shown in Fig. 1, the interval 22 shown in Fig. 2 is equal to a sum of the intervals, T1+ --- T8, shown in Fig. 4. Therefore, abovementioned fact is clearly understood from that the output 44 in the embodiment of the invention has period of "H" level distributed without being localized to a specific position. Abovementioned matter will now be described quanti tatively. In the-conventional system shown in Fig. 1, the fundamental period component of the pulse output (component whose period is equal to the interval 22) becomes maximum when the "H" level interval 21 becomes a half of the period 22. Asswning that the digital data bits be D1 - D5, an amplitude of the output pulse 6 be VO, and the period of the clock QO be to, the fundamental period component A1 becomes A1 = 2Vo (2) # (#: ratio of circumference of circle to its diameter) Assuming that the time constant of the integrating circuit 4 -be T, and when the pulse output 6 is supplied to the integrating circuit 4, the ripple component VR1 of the output of the inte grating circuit becomes VR1 = 32 x. Voto (3) #2# Next, the embodiment of the present invention in Fig. 3 will be considered. The fundamental period component of the sum of the periods, T1+ --- +T8 (equal to 32to), of the pulse output 44 in Fig. 3 becomes maximum when data D1 is "1". Then the fundamental period component A2 becomes A2 = 0.195 x Vo (4) When the pulse output is passed through the integrating circuit .4 having the time constant T, the ripple component VR2 of the output therefrom becomes - VR2 = 3.12x -¯ (5) When the time duration of "H" level in each of the intervals T1 - T8 becomes equal, that is, D1, D2 and D3 are O, the fundamental period of the pulse output 44 becomes 4to. This component becomes maximum when the time duration of "H" level coincides with that of "L" level. Then the maximum fundamental period component A3 becomes 3 2Vo A3 W t6) Therefore, the ripple component VR3 contained in the output of the integrating circuit 4 becomes VR3 = 4 x Vot #2# (7) As clearly seen from the equations (3), (5) and (7), the ripple component contained in the output of.the integrating circuit 4 of the D-A converter of the present invention becomes 1/8 - 1/10 in comparison to the conventional D-A converter. In other words, according to the present invention, if the amount of the ripple contained in the analog output is made equal to that of the prior art converter, the time constant of the integrating circuit can be reduced, with the result that the conversion speed can be increased. Although the D-A converter is constituted for five bits composed of most significant two bits and least signifi cant three bits in the abovementioned embodiment, it is possible to constitute a D-A converter for two bits composed of the most significant one bit and least significant one bit, or more, by providing a proper number of stages (equal to the total number of bits) of the frequency dividing circuit 1 and a proper number of bits (equal to the nutter of most significant bits) of the prograninable counter 2 in Fig. 3. Although the input from the frequency dividing circuit 1 is decoded according to equation (1) in the embod- ment shown in Fig. 3, a similar effect is obtained according to other concept than equation (1), provided that the inter vals in "H" level (or "L" level) of decoded output are selected without mutual overlapping.

Claims: Claims: 1. A D-A converter for converting digital data composed of most significant M bits DN+1, --- 1 DN+M, and least significant N bits D1, --- , DN where M and N are positive integers respectively into an analog quantity, characterized by: a frequency dividing circuit (1) having M+N frequency dividers connected in tandem, a first frequency divider of said M+N frequency dividers being adapted to receive an input clock signal QO and the remaining frequency dividers being adapted to generate output signals oil , --- ' QNT AN+1, --- and QN+MT respectively; a programmable counter (2) of M bits for receiving the input clock signal Qo; a preset circuit (3) for receiving a signal QL which has the same period as that of said output signal QN and is a first level during an interval corresponding to one period of said clock signal Qo and at a second level during the remaining portion of its period to preset values corresponding to the most significant M bits data DN+1, --- , DN+M into said programmable counter when said output signal QL is at said first level; a first gate circuit (15) for being set when said output signal QL changes state from said first level to said second level and reset when the content of said programmable counter (2) becomes a predetermined preset value; a decoder circuit (16) for receiving said output signal Q1 and outputs of said frequency divider circuit (1) to generate output signals Q*M+1; Q*M+2' --- and Q*M+N whose periods at a predetermined level do not overlap each other; a second gate circuit (31 to 34) for receiving least significant N bits data D1, --- , DN to control said output signals of said decoder circuit (16); and an integrating circuit (4) for integrating the sum of the output signals of said first and second gate circuits. 2. A D-A converter claimed in Claim 1, characterized in that the decoder circuit (16) provides output signals represented by Q*M+1 = QM+1.QL Q*M+2 = QM+1.QM+2.QL Q*M+N = QM+1.QM+2 --- . --- QM+N-1.QM+N.QL

Inventors: KOBAYASHI, HIROSHI C/O MITSUBISHI DENKI K.K., TAKEBE, HIDEHARU C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1982
Main classification: H03M1
IPC codes: H03M1