ELECTRO-OPTIC ELEMENT AND METHOD OF MAKING THE SAME

Abstract: The electro-optic element comprises a semi-insulating substrate (10) having a substantially planar surface (12), a depression (13) formed in the surface and filled by a multilayered semiconductor stracture (14 to 17) so that the exposed surface of the structure is coplanar with the planar surface (12), and a region (19) having a material diffused into the structure of conductivity type opposite that of the structure to form an active part such as a diode, of the electro-optic component.

Description: ELECTRO-OPTIC ELEMENT AND METHOD OF MAKING THE SAME The present invention is directed to an electro-optic element and to the method of fabrication of the element. The invention is particularly applicable to high speed low cost fiber optic communication systems requiring a monolithic electro-optic transmitter-receiver. In the prior art there has been described the growth of N type AlGaAs, GaAs, and AlGaAs layers successively on a semi-insulating GaAs substrate for a semiconductor laser device such as shown in US Patents 4,105,955, 4,166,278 and 4,138,038. According to the invention, there is provided a solid state electro-optic element comprising a semi-insulating substrate having a substantially planar surface; a depression formed in a portion of said planar surface and filled by a semiconductor layer means so that the exposed surface of the layer means is essentially coplanar with said planar surface portion; and a region of said epitaxial layer means having a conductivity type opposite that of the layer means to form an active part of the electro-optic component. According to the invention, there is also provided a method of fabricating a solid state electro-optic element, comprising the steps fo preparing a semi-insulating substrate having a substantially planar surface; etching a depression in the planar surface of the substrate to prepare a site for an optoelectronic component; epitaxially growing over said depression a thin semiconductor deposition to substantially fill said depression; and, forming in said epitaxially grown deposition, a material of conductivity type opposite that of the deposition to provide an active portion of the optoelectronic component. An embodiment of the invention will now be described by way of example, with reference to the accompanying drawings, in which: Figure 1 describes a series of steps in the fabrication of a planar GaAs electro-optic transmitter according to the present invention. Figure 2 is a cross-section of a portion of the transmitter structure derived from the steps of Figure 1, Figure 3 is a graphical presentation of the relative emission intensity of the diode versus wavelength (A ), and Figures 4 and 5 are photomicrograph presentations of the cross-section of the transmitter structure. Referring to Figure 1 there is shown a progression of processing steps involved in the fabrication of the planarstructure GaAs electro-optic transmitter. Figure la discloses a substrate 10 of semi-insulating GaAs, with an optional GaAs:Cr doped buffer 11, and having a planar surface 12. Etched into the planar surface of the substrate is a "wide-well" or channel 13 (for example 100-500 urn wide) to prepare a site for the laser structure. By way of example, the depth of the channel may be on the order of about 2-20 urn. Then by employing VPE (vapor phase epitaxy) or LPE (liquid phase epitaxy) growth the desired n-doped AlGaAs GaAs-AlGaAs-GaAs epitaxial layers 14, 15, 16 and 17 are grown, as shown in Figure Ib, over the planar surface 12 and the well 13. The thickness of the epitaxial layers 14 to 17 are adjusted such that a subsequent chemical-mechanical polishing step produces a new planar surface 18, shown in Figure lc, where the GaAs:Cr substrate is exposed and the layers 14, 15, 16 and 17 are preserved and remain only in the channel 13. These epitaxial layers grown in the wide well will provide the laser structure. The mechanical polishing exposes the GaAs:Cr substrate over the remainder of the planar surface 18. A mask of Si3N4 over the planar surface 18 with a window over a portion of the well area provides for a selectivexsiffusion 19 of Zn into the well structure, as shown in Figure ld, in order to make the required p+, E and n regions needed for a transverse junction stripe (TJS) laser structure in the well. In one preferred embodiment the Al Ga As layers are x = 0.35 and the GaAs layer 15 was Te-doped to a carrier concentration of approximately 2 x 1018cm on a substrate of GaAs oriented < 100 > . The Zn diffusion extends down through the epitaxial layers 17, 16, 15 and 14 to provide a p-n junction in the active GaAs layer 15. Prior to MESFET fabrication by direct ion implantation the Si3N4 is removed and the surface is etched to remove surface damage. When the multiplexer and driver 20 are completed, Figure le, the final processing steps are carried out to complete the laser. For illustrative purposes a TJS DBR (distributed Bragg reflector) laser 21 is shown in Figure lf. In the process steps outlined above, all contact lithographic processes are performed on planar surfaces to eliminate the problems encountered in processing non-planar surfaces such as non-uniform photoresist spin-on and mask alignment. Further, the temperature cycling, chemical etches and mechanical stress involved in the fabrication of the MESFETs and the lasers are compatible. Still further, since all the active components are at the surface, the electronic and the optical components can be developed independently during initial stages. The planar structure provides direct access to all the active components and facilities testing and heat sinking. Figure 2 shows the details of a GaAs -n homojunction emitter in the form of a Transverse junction stripe light emitting diode or laser diode fabricated in the well. The layer 10 shows the semi-insulating substrate, then the epitaxial layers including the AlGaAs confining layer 14, the GaAs active layer 15, the AlGaAs confining layer 16 and the GaAs cap layer 17. The layers 14 to 17 as deposited are n-layers. The cross-hatched portion of Figure 2 represents the Zn diffused area, which is p doped, with the junction area being indicated by the dashed line 30. The heavy line 31 is indicative through the predominant current flow path through the diode. The junction can also be formed by the ion implantation of Be in place of the diffusion of Zn. Figure 3 is a graphical presentation of spectral characteristics and plots the relative emission intensity of the diode on the ordinate axis versus wavelength (A ), It can be seen that in this AlGaAs-GaAs device the emission curve peaks at about 9000 A . Figures 4 and 5 are photomicrographics of a crosssection of a transverse junction structure grown in an etched wide well. Figure 4 shows the "as grown" AlGaAs, GaAs structure on the substrate. Prior to the heteroepitaxial growth, wide-wells of 450 um x 10 vm were formed by chemical etching in a < 100) oriented substrate structure. Subsequently a three layer TJS structure (AlxGai#xAs = 0.35; GaAs active layer; A1xGal xAs = 0.35) was grown by liquid phase epitaxy on the entire surface as shown in Figure 4. While the active layer is shown as GaAs throughout the description, it may also be AlXlGa1¯xlAs where the xt is not equal to zero. The planar surface was then restored, as shown in Figure 5, by a chemical-mechanical polish in which the substrate is again exposed except in the well where the layered structure remains. The Zn diffusion described above can be performed either before or after restoration of the planar surface; however, it is preferable to perform the Zn diffusion with the epitaxial layers on the wafer to help protect the GaAs:Cr substrate Although the planar structure solid state electrooptic element has been described as fabricated in a GaAs system it may also be fabricated in the same way in a InP (indium phosphide) system. In this case the substrate is InP and the epitaxial layers may be the quaternary semicon ductor InGaAsP of the general composition Inl Ga P As and in which the respective values of x and z may differ from one layer to another and where 0 < x < 1 and where O < z < 1.

Claims: CLAIMS 1. Solid state electro-optic element comprising a semi insulating substrate having a substantially planar surface; a depression formed in a portion of said planar surface and filled by a semiconductor layer means so that the exposed surface of the layer means is essent ially coplanar with said planar surface portion; and a region of said epitaxial layer means having a conduc tivity type opposite that of the layer means to form an active part of the electro-optic component. 2. The element according to Claim 1, wherein the epitaxial semiconductor layer means comprises layers of AlGaAs and GaAs, and wherein the substrate is gallium arsenide. 3. The element according to Claim 1, wherein the semi conductor layers means comprises layers of Al Ga, As I. a#nd Al IGal As where xl is not equal to zero. 4. The element according to Claim 1, wherein the substrate is InP, and wherein the epitaxial semiconductor layer means includes at least one layer comprised of the general composition In1#xGaxP1 #As ## 5. The element according to any one of the preceding claims, wherein said region of opposite conductivity type is diffused down through a section of said semiconductor layer means which comprises first, second and third layers, said first and opposite conductivity type reg ions forming a p-n junction in said layers, said first and third layers acting as confining layers and said second layer being an active layer of a transverse junction stripe optoelectronic component. 6. A method of fabricating a solid state electro-optic element, comprising the steps of preparing a semi-insu lating substrate having a substantially planar surface; etching a depression in the planar surface of the sub strate to prepare a site for an optoelectronic component; epitaxially growing over said depression a thin semi conductor deposition to substantially fill said depression; and, forming in said epitaxially grown deposition, a material of conductivity type opposite that of the deposition to provide an active portion of the optoelectronic component. 7. The method according to Claim 6 and further comprising the step of fabricating hlESFETs on a different portion of said planar surface by direct ion implantation. 8. The method of Claim 6 or 7, wherein the deposition is multilayered, and including the steps of chemical-mech anical polishing said epitaxially covered planr surface to re-expose said substrate and establishing a new substantially planar surface which planar surface eff ectively includes the epitaxially grown layers in said depression; and, diffusing zinc down into a portion of said epitaxially grown layers and thereby forming a g-n junction, whereby the first and third layers are confining layers and the second layer is the active lay er of a transverse junction stripe optoelectronic component. 9. The method of Claim 6 or 7, wherein said depression is filled with thin layers of Al Ga As or Al Ga As and x 1-x Awl 1go 1As (where xl is not equal to zero) so that the surface of said epitaxial layers in said depression is substantially coplanar with said planar surface; and wherein a diode region is formed in said epitaxial thin film layers, the diode region being an active region of the optoelectronic structure. 10. The method of Claim 6, 7, 8 or 9, wherein the depression is between 2 and 20 urn deep

Inventors: KOLBAS, ROBERT M.
Applicants: HONEYWELL INC.
Application year: 1982
Main classification: H01L27
IPC codes: H01S5, H01L27, H01L31, H01L33