TERMINAL UNIT FOR AUTOMATIC METER READING SYSTEM

Abstract: The terminal unit (18) is arranged for connection to a power line (24) for receiving commands over the power line through a receiver (40). The unit includes an information processor (44) which is operable in response to an execute immediate type of command to execute a specified function immediately, and which is also operable in response to an execute hence type of command to execute a specified function at a specified future time.

Description: TERMINAL UNIT FOR AUTOMATIC METER READING SYSTEM Technical Field The present invention relates to an improved terminal unit for an automatic meter reading system. The invention is especially useful in automatic remote meter reading systems for reading and trans¬ mitting utility meter readings from the users prem¬ ises to a central location for recordation and billing. For instance, the invention is especially useful for reading and transmitting data from electric power meters, or gas meters, or water meters , which measure consumption of those commod¬ ities . Background Art The present invention represents an improve- ment upon a prior system disclosed in British patent specification 1,543 ,501,General Electric Co m p a n y ; published on 4 April 1979. In that prior system, a reading control center communicates over voice grade communication lines with a number • ^J^EACT of section control units , and through the section control units and through electric power lines to individual meter terminal units. The present in¬ vention relates particularly to improved meter terminal units for use in such a system. The. meter terminal units of the prior system were capable of receiving and immediately carrying out commands relating to load control operations and relating to the transmission of meter readings back to the section control units. However, it has been determined that it is very desirable to provide for additional command functions in such systems including the transmission of commands to meter terminal units requiring future actions by the meter terminal units at predetermined times as specified by the commands. Summary of the Invention It is a major object of the present invention to provide an improved terminal unit for an automatic meter reading system which is operable to receive and « execute an "execute hence" type of command requiring the terminal unit to carry out the command at a specified future time. The "execute hence" O , V. capability is in addition to the ability to carry out commands for immediate execution. In carrying out the invention there is pro¬ vided a terminal unit for an automatic meter reading system, said terminal unit being arranged for con¬ nection to a power line and comprising means for receiving a command over the power line , decode means responsive to the received command to effect the immediate execution of the function specified by the command in response to recognition of an address assigned to said terminal unit as specified by at least a portion of the contents of the com¬ mand; characterized by the provision that said decode means comprises an information processor including means to distinguish between an execute immediate _ command and an execute hence command and -to cause the immediate execution of a command only when that command is recognized as an execute immediate com¬ mand, and further characterized by the provision that said information processor is operable to effect the execution of the function specified by the command only at a specified future time in response to recognition of the command as an execute hence type of command in combination with recognition of an address assigned to said terminal unit as specified by an address portion of the command, said time of execution being specified by a time field portion of said command. In the accompanying drawings: FIG. 1 is a schematic block diagram of an entire system of the type incorporating the present invention. FIG. 2 is a schematic block diagram showing the major components and interconnections of the meter terminal unit of the present invention. FIG. 3 is a schematic diagram of a preferred embodiment of the information processor portion of the meter terminal unit of FIG. 2. FIG. 4 is a schematic diagram illustrating the apparatus and components which are intended to be connected to the information processor of FIG. 3 to receive decoded commands and to operate in re- sponse thereto, and to provide data to the informa- « tion processor for transmission back to the section control unit. O P FIG. 5 is a functional block diagram illus¬ trating a system combination of logical component circuits which can be employed for carrying out certain aspects of the invention. Detailed Description of the Invention Referring particularly to FIG. 1 of the draw¬ ings, there is shown a schematic diagram of a system in which the present invention is particularly use¬ f l. The system is generally designated as 10 and includes a reading control center (RCC) 12' hich 'communicates with a section control unit (SCU) 14 , over a communication link 16. The section control unit 14 communicates with a plurality of meter terminal units (MTU) 18 over a communication link 24. The communication link 24 preferably consists of an electric power distribution grid. Each meter terminal unit 18 has the capability of reading a plurality of different utility meters by taking readings from meter reading encoders 54. Each terminal unit 18 also has the capability of controlling a number of different loads 58 or alert signal devices 56. Each terminal unit also has the capability for reporting the status of a plurality of devices such as relay O PI contacts (not shown) . In the preferred embodiment, each meter terminal unit 18 has the capability for reading three meter encoders 54, controlling three external loads 58, and two alert signalling devices 56; and for reporting the status of up to six external contacts. The reading control center 12 controls the overall operation of the system. Control center 12 includes a digital computer 26 which communicates with the rest of the system through one or more com¬ munications interface units (CIU) 28. ϊhe communications interface unit 28 issues commands and receives data over the communication link 16, which is preferably a voice grade telephone circuit, through a modulator-demodulator circuit (MOD) 30. A similar modulator-demodulator, circuit 30 is provided as shown at the section control unit 14 end of the communication link 16. Preferably, the section control unit 14 is installed at a sub-station of the utility, such as the electric power utility which may be. using the system. The section control unit then communicates with all of the meter terminal units 18 for customers who are served by that sub-station. OM Commands or messages are preferably trans¬ mitted from the section control units 14 over their associated power lines 24 by means of carrier signals which are binary phase-modulated at thirty bits per second. Generally, the meter terminal units 18 can be commanded to perform any of the following functions: reading and storing meter data, perform¬ ing a reading of demand data and calculation of demand, transmitting previously stored meter or demand data, turning loads off and on, -turning customer alerts on and off, and providing the status of external con¬ tacts . The meter terminal units are individually addressable, group addressable, or block addressable. In each of the latter two cases, a number of meter terminal units are simultaneously addressed, and simultaneously respond to the commands. FIG. 2 is a simplified schematic diagram of the meter terminal unit 18 of the present invention. The meter terminal unit includes a receiver 40 which is connected to the power line 24. Signals received by the receiver 40 from the section control unit 14 OMPI of FIG. 1 over the power line 24 are transmitted on connections 46 to an information processor 44. The receiver 40 receives clock signals from the infor¬ mation processor 44 over a line 48. The information processor 44 is sometimes referred to below as a decoding device or as "decode means". Signals which are to be transmitted from the information processor 44 back to the section control unit 14 of FIG. 1 are carried through a plurality of lines 52 to a transmitter 50 which is also connected to the- power line 24. The information processor 44 transmits signals over a plurality of lines indicated at 60 to a plural¬ ity of encoders 54, alert indicator devices 56, and load control devices 58. The information processor 44 also receives signals from the encoders 54 and from a plurality of status switches 62 over a plurality of lines 64. The alert devices 56 may be signal lamps to alert the customer, for instance, " that he is operating in a peak demand period, so that he may voluntarily limit his loads to keep his* costs down. FIG. 3 is a more detailed schematic diagram of the information processor 44 of FIG. 2. The information processor preferably includes a micro¬ computer 66, which is preferably a micro-computer model 8049 which is available from Intel Corporation of Santa Clara, California, U.S.A. The micro-computer 66 incorporates a first eight bit port 68 through which signals are sent over the multiple lines 60 to the encoders 54, the alerts 56, and the loads 58, as previously described in connection with FIG. 2, and as shown and described in more detail in connection v/ith FIG. 4 below. Micro-computer 66 also includes * a second eight bit port 70 through which most of the signals are- received on the multiple connections 46 from receiver 40, as previously described in connection with FIG. 2, and through which information signals are supplied on the multiple connections 52 to the transmitter 50, as previously described in connection with FIG. 2. The connections 52 are further identified as IBTD (data) and IBTG. Connection IBTG is the gate connection. One of the inputs 46 from the receiver 40 to the micro-processor 66 is supplied to the input terminal (TO) to provide a clock strobe (RC) from O PI the receiver to the micro-processor so as to time the operation of the micro-processor in receiving data from the receiver 40 in connection with the data receiving function. The other connection labeled OBDR receives data containing commands. The micro-computer 66 also includes an in¬ ternal random access memory (RAM) 74 which is used in the course of various micro-computer operations for the storage of commands and data, as described more fully below. The micro-computer 66 also includes an eight bit bi-directional port 72, which is also sometimes referred to as a bus, and by means of which the micro-computer communicates with a number of other associated memory and multiplex units 94, 96, 100, and 104. A phase locked loop circuit 76 forms a part of the information processor circuit 44, and is arranged to operate in response to a 60 Hz input signal on connection 75 to p'rovide a square wave 60 Hz timing signal at the Tl input of the micro¬ computer 66. The phase locked loop circuit 76 also provides a timing signal on connection 48 to receiver 40 which is at a frequency of 983,040 Hz. Similarly, the phase locked loop circuit provides a timing signal to transmitter 50 on a connection 77 at a frequency of 61,440 Hz. Referring again to the ^ port 68 from the micro-processor 66, the connections 60 are carried to the relay drivers shown in FIG. 4. Thus, the connec¬ tions labeled EMSl through EMS3 of FIG. 3 are carried to the encoder relay drivers 78 of FIG. 4 so that an individual signal on any one of these three connec¬ tions will enable a corresponding one of the relay drivers 78. That corresponding relay driver will pick up an associated one of the encoder relays 80 to select one of the three meter encoders 54a, 54b, or 54c. In this " manner, the encoders are individually activated. Similarly, signals on either of lines ASl or AS2 activate one of the alert relay drivers 82 which selectively activate the alert relays 84 which selectively activate the alert indicator devices 56a or 56b. Also, the lines LSI through LS3 of the set 60 from the micrp-computer 66 in FIG. 3 activate selectively the individual load control relay drivers 88, controlling the associated individual load control relays 90 to selectively control the loads 58a, 58b, and 58c. As a result of the enablement of any one of the encoders 54a, b, or c, meter reading data is generated which must be carried back to the micro¬ computer 66. This is accomplished over lines 64, which are individually labeled ES123 and ED123, and which are carried to a multiplex unit 96 in FIG. 3. Similarly, data on the status of status contact elements 102 is carried by signal lines ST1-ST6 , which also comprise part of the connections 64, back to the multiplex unit 96 of FIG. 3. From the multi¬ plex unit 96, such data is carried to the micro¬ processor on bus 72. Data is read out of the multiplex circuit 96 through bus 72 to the micro-processor 60 in response to a read signal RD received from the micro-computer 66 and also in response to the concurrence of address control signals indicated at AD0-AD2 received from an address latch circuit 94. The control of the operation of the address latch circuit 94 is carried out by the micro-processor 66 by means of a connection to a clock input C from an output ALE of the micro¬ processor 66. By means of a connection to bus 72, data from the encoders 54 obtained through multiplex 96 is stored in an encoder data random access memory (RAM) 100. The data stored- in the random access memory 100 may be addressed for read out by the eight addresses designated ADO to AD7 which may be obtained from the address latch circuit 94. Memory 100 is further controlled by a connection to receive the read signal RD, previously referred to above, or a write signal WR, both emanating from the micro¬ processor 66. The information processor 44 also includes an address programmable read only memory (PROM) 104 which is addressable by signal bits ADO through AD4 from the address latch 94 when enabled by a signal from AND circuit 98. The AND circuit 98 is enabled upon the coincidence of a read signal RD and a memory strobe signal (MS) from the micro-computer 66. FIG. 5 is a functional block diagram illus- trating a system combination of logical component circuits which can be employed for the ^ purpose of carrying out the invention. However, in the pre¬ ferred embodiment , these components are preferably entirely embodied in the micro-computer 66 of FIG. 3. Accordingly, FIG. 5 is considered to be a functional representation of a part of the micro-computer 66. However, it will be understood that all of the elements which are represented'as discrete elements in FIG. 5 do not necessarily exist as discrete elements in the micro-computer 66, although the functions of these discreet elements of FIG. 5 are clearly performed by the micro-computer 66. The functions of the micro-computer 66 (as a part of the information processor 44) are described immediately below by reference to FIG. 5 as though the functional elements illustrated in FIG. 5 all existed as discrete elements within processor 66. Referring in detail to FIG. 5 , the command signal OBRD received on one of the connections 46 is reviewed by an address recognition discriminator 110 to determine whether or not this particular terminal unit is being addressed by the command. If the address of the present terminal unit, or a group address for the group to which this terminal unit belongs, is not recognized, then the command goes no farther than the address recognition discriminator because the command is not to be carried out by this particular terminal unit. On the other hand, if the address is recognized as destined for this particular terminal unit, the command is passed on to the command discriminator 112. The command discriminator 112 determines whether the command is an execute immediate command, or an execute hence command. If the command is an execute immediate command, it is stored in the execute immediate register 114. However, if it is an execute hence command, it is stored in the execute hence •register 116. An execute immediate command calls for immediate execution of the command. An execute hence command calls for execution of the specified command at a future time. The time for execution of the execute hence command is passed on to an execute hence time register 118. Register 118 preferably stores the execute hence time in terms of a time interval during which the system is to wait before execution of the execute hence command. This time storage is in the form of a number. The execute hence time register 118 is then provided with clock pulses from a decrement clock 120 which successively reduces the time interval number stored in the execute hence time register 118. When the register 118 is finally decremented to 0, it causes the emission of a gating signal on connection 121 to a gate 122 which gates the command through from the execute hence register 116 for actual execution. The execute hence commands and the execute immediate commands are often issued in related pairs in which the execute hence command is for one opera- tion, and the execute immediate command is for an opposite operation. For instance, in accordance with the present invention, a maximum demand measurement may be made over a measured interval of time. For such an operation, the execute hence command may command the termination of the demand measurement interval and the execute immediate command which is paired with that execute hence command may command the commencement of the demand measurement interval. In accordance with another feature of the present invention, when paired execute hence and execute immediate commands are to be dealt with, the execute hence command is first received and stored by the terminal unit in the execute hence register 116. O Later, the corresponding execute immediate command which commands the opposite operation, is received and stored in the execute immediate register 114. The commands stored in the two registers 116 and 114 are then compared in a comparison circuit 124 to see if they indeed command opposite operations. If the comparison confirms this, then the compare circuit 124 issues a gating signal at 125 to a gate circuit 126 to permit the execute immediate command to be executed from the execute immediate register 114-. Thus , in accordance with this preferred feature- of the in¬ vention , the execute immediate .command cannot be executed unless a corresponding opposite action com¬ mand is already stored in the execute hence register 116. While the above description was given in terms of storage of the execute hence command prior to reception of the execute immediate -command, that sequence is not essential. Thus, the execute im- mediate command can be stored first, but it will not be executed until an execute hence command calling for the opposite action is stored in the execute hence register 116. However, it is preferred that OMPT the execute hence command be stored first so that the execute immediate command can be executed promptly when it is received by favorable comparison in the compare circuit 124. Referring back to FIG. 3, all of the storage registers of FIG. 5 are preferably embodied within the random access memory 74 contained within the micro¬ computer 66, and the logical switching embodied in FIG. 5 is carried out by the logic circuits of micro- computer 66. Summarizing the operation of the terminal • unit of the invention, the terminal unit is arranged for connection to a power line 24, as shown in FIG. 2, and includes a receiver 40 for receiving a command over that power line. The command is typically in digital pulse form. An information processor 44, which is sometimes referred to below as a "decode means" , receives the command from the receiver over connections- 46 and responds to the received command to affect the immediate execution of the function specified by the ' command in response to. recognition of an address assigned to the terminal unit as specified by at least a portion of the contents of the command. The information processor 44 is shown in more detail in FIG. 3 as comprising a micro¬ computer 66, which is functionally illustrated, in part, in FIG. 5. The address recognition function is carried out by the address recognition dis¬ criminator ' llO of FIG. 5. It is an especially important feature of this invention however that the information processor includes means, such as the command discriminator 112 of FIG. 5, to dis- tinguish between an execute immediate command and an execute hence command, and to cause the immediate execution of a command only when that command is recognized as an execute immediate command. The information processor is further operable to affect the execution of the function specified by the command only at a specified future time in response to recognition at 112 of the command as an execute hence type of command. The future, time of execution is specified by a time field portion of the command which is stored at the execute hence time register 118. In accordance with the preferred embodiment of the invention, the time field portion of the contents of the execute hence command is in the form of a numerical value corresponding to a specified length of time, and the information processor in¬ cludes a means such as the decrement clock 120 to decrement the storage value of the time field portion stored in the execute hence time register 118 at uniform time intervals.- The processor is then operable to perform the function specified by the function portion of the command when the stored value of the time field portion stored in register 118 has been decremented to 0. As previously mentioned above, in accordance with the present invention, the execute immediate and execute hence commands may be issued in related pairs calling for opposite functions. One of the pairs of opposite functions to be -carried out by the execute hence command and the execute immediate command may consist of the "demand on" function and .the "demand off" function. In accordance with still another feature of the invention, the in¬ formation processor 44 (FIG. 3) includes a plurality of function code identifiable storage devices which may be embodied in the encoder data random access memory 100. The micro-computer 66 is operable for measuring the difference in the measure- ment data obtained at the beginning and at the end of each "demand on" interval, and for comparing that difference to the largest difference obtained during a preceding "demand on" time interval. The larger of the two compared difference values is then stored in one position of the random access memory 100. In this manner, whenever a greater demand is measμred than any demand previously measured, the new and greater demand is stored for future reference. In accordance with another aspect of the invention, the pair of execute hence and execute immediate commands may relate to respectively turn¬ ing on a load and turning off that load by control of the load control relay drivers 88 and the load control relays 90 of FIG. 4, as previously mentioned above. In accordance with another aspect of the invention , the information processor 44 , FIG . 3 , is operable to respond to a command to trans fer "ξ JREA OMPI data from the status devices 102 (FIG. 4) , or from the encoders 54 FIG. 4 to memory storage, such as the random access memory 100 (FIG. 3) , or the internal random access memory 74 (FIG. 3) , and then to transfer that data from the memory to the transmitter 50 of FIG. 2 for transmitting the measurement data over the power line 24. O

Claims: CLAIMS : 1. A terminal unit (18,FIG. 2) for an automatic meter reading system, said terminal unit being arranged for connection to a power line (24) and comprising means (40) for receiving a command over the power line, decode means (44) responsive to the received command to effect the immediate execution of the function specified by the command in response to recognition (at 110,FIG.5) of an address assigned to said terminal unit as specified by at least a portion of the contents of the command; characterized by the provision that said decode means comprises an information processor (44,FIG. 3) including means (66,FIG. 3; 112,FIG.5) to distinguish between an execute immediate command and an execute hence command and to cause the immediate execution of a command only when that command is recognized as an execute immediate command, and further characterized by the provision that said information processor (44, FIG.3) is operable to effect the execution of the * function specified by the command only at a specified future time in response to recognition Claim 1 (continued) (at 112,FIG.5) of the command as an execute hence type of command in combination with recognition (at 110) of an address assigned to said terminal unit as specified by an address portion of the command, said time of execution being specified by a time field portion (stored at 118) of said command. 2. A terminal unit as claimed in claim 1 further characterized in that said information processor (44,FIG.2; 66,FIG.3) includes means (116,FIG. 5) to store the function portion of the execute hence command, and further characterized in that the time field portion of the contents of the execute hence command contains a numerical value corresponding to a specified length of time, said information processor (44,FIG.2; 66,FIG.3) including means (74,FIG.3; 118,FIG.5) to store said time field portion and being* operable to decrement (at 120) the stored value of said time field portion at predetermined time intervals; said information processor then being operable (at 122) to perform the function specified by the stored contents (at 116) of the function portion of the command when the stored value of the time field portion (at 118) has been decremented to zero. OMPI 3. A terminal unit as claimed in claim 1 further characterized in that said information processor (44,FIG.3) is first operable to receive and store (at 74,FIG. 3; 116,FIG.5) the command containing the execute hence type of address, said processor then being operable to receive and store (at 74,FIG.3; 114,FIG.5) the execute immediate command having a function code portion and an action field portion, said last- mentioned function code portion containing a specified function to be performed which is an opposite of the function specified in the execute hence command, said processor being operable to compare (at 124,FIG.5) the functions specified in the execute immediate(atll4)and execute hence (at 116) commands and to perform (at 126) the function specified in the function code portion of the execute immediate command (at 114) only if the execute hence command containing the opposite function has- been previously received and stored (at 116) for later execution at the expiration of said specified time interval. -^ϋR 4. A terminal unit (18,FIG.2) as claimed in claim 1, claim 2 or claim 3 further characterized in the provision of means (54) for measuring demand over a predetermined interval of time, and further characterized in that the execute hence command relates to the specified function of turning off the demand function, and the execute immediate command function which is opposite in sense to the execute hence command calls for the "demand on" function. 5. A terminal unit as claimed in claim 4 further characterized in the provision of ,a plurality of function code identifiable storage means (100,FIG.3), means (66,74) for measuring the di-fference of measurement data obtained at the beginning and at the end of each "demand on" interval and for comparing that difference to the largest difference obtained during a preceding "demand on" time interval, the larger of the two compared difference values being stored in an identified one of said storage means. 6. A terminal unit as claimed in any one of claims 1, 2, or 3 further characterized in the provision of means (66 ,FIG.3; 82,84,FIG.4) for controlling a load, and further characterized in that the execute * hence command relates to the specified function of turning on the load, and the execute immediate command function which is opposite in sense to the execute hence command turns on the load. 7. A terminal unit as claimed in claim 6 further characterized in the provision of at least one alert control means (66,68,FIG.3; 82,84,FIG.4) for controlling an alert device associated therewith; and further characterized in that said processor, operates in response to a unique function code type contained in the function code portion of a received command to selectively activate an identified one of said alert control means to effect the turning on of the alert device (56a,56b,FIG.4) associated therewith; and further characterized in that said processor operates in response to still another function code type contained in the function code portion of a received command to selectively activate an identified one of said alert control means to effect the turning off of the alert device associated therewith. 8. A terminal unit as claimed in claim 6 further characterized in the provision of at least one status means (102,FIG.4) for monitoring- the status of a switch associated therewith; further characterized in the provision of a multiple position storage means (74,FIG.3) and still further characterized in that said processor (44,FIG.3)operates in response to a unique function code type contained in the function code portion 'of a received command to selectively affect the storage of a signal from said status means (102) into an identified position of said storage means (74) as an indication of switch status; and further characterized in that said processor operates to affect the trans¬ fer of said switch status signal from said storage means (74) to transmitter means (50,FIG.2) for transmitting said measurement data over said power line (24). OM

Inventors: OUELLETTE M, ROBINSON P, SCHMIDT L
Applicants: GEN ELECTRIC, GENERAL ELECTRIC CO
Application year: 1981
Main classification: H04B3
IPC codes: G01R21, G08C15, G08C19, H04B3, H04M11, H04Q9