SYNCHRONIZING CIRCUIT ADAPTABLE FOR VARIOUS TV STANDARDS

Abstract: A television sync signal generator adapted for ready conversion among various television standards includes a memory (216) in which information related to the magnitude of at least one component of a composite sync signal is stored at address locations each corresponding to at least one particular time in each recurrent television frame. A clock signal generator (212) addresses the memory (216) to sequentially read out the information so the sync signal can be reconstructed. By dividing the sync signal into four intervals which are selected by paging signals from one counter, a reduction in required memory capacity is achieved. For further reducing the number of memory addresses required, each memory address contains information relating to the instantaneous resolution or clock rate. A sample rate controller (820) is coupled to the memory for having the instantaneous clock address rate controlled in response to the contents of the memory.

Description: SYNCHRONIZING CIRCUIT ADAPTABLE FOR VARIOUS TV STANDARDS This invention relates to synchronizing arrangements for generating synchronizing and blanking signals, which arrangement is readily adaptable for various television standards. , There are four main television standards in use throughout the world; NTSC, SECAM, PAL and PAL-M. Making receivers for each one of these various standards poses no problem, since there is sufficient manufacturing volume to economically justify this specialization. _ • Studio apparatus- using sync generators, such as for example cameras, is however, a different situation. It is difficult to justify making a sync generator for just one standard due to the low volume involved. One solution is shown in U.S. Patent Number 4,169,659, which shows a sync generator that is adaptable to different_ standards. However, a cost penalty is then incurred on every unit because each unit must include portions applicable only to other standards, even though they may never be used. Further, once built, the adaptable unit cannot be readily changed to produce different pulses as may be required, e.g., a pulse occurring at the 19th horizontal line to control insertion of a vertical interval test signal when the unit was designed co produce a pulse on the 21st horizontal line. Another problem is that the circuit cannot be changed without complete redesign of hardware to generate a new standard as this may become necessary. For example, one standard that is sometimes used has 24 frames per second to match that of film, and 655 lines per frame, which standard has the same bandwidth as that of NTSC. It is therefore desirable to have a sync generator that is readily adaptable in the field among both present and future standards. It is also desirable that there be only a small cost penalty Jior this adaptability, which then is offset by the larger volume of manufacture of the adaptable circuit. In accordance with the principles of the present invention a method for generating a television synchronizing signal comprises the steps of storing at address locations information relating to the magnitude of at least one componen of a composite synchronizing signal at each of a predetermined plurality of sampling points or times in each television frame; and generating sampling signals for recurrently addressing the memory for reading the information from the memory for generating the component signal- In accordance with a further aspect of the present invention, for reducing the number of memory addresses require the generating step comprises generating -periodic sampling signals at a rate determined by information stored in the memor . IN THE DRAWINGS: FIGURE 1 is a drawing of an TSC composite video signal in the area of the vertical blanking- interval; - FIGURE 2 is a block diagram of an embodiment of the invention; FIGURE 3 is a detailed block diagram of another embodiment of the invention; FIGURE 4 is a timing diagram of vertical rate signals present in FIGURE 3; and FIGURE 5 is a timing diagram of horizontal rate signals present in FIGURE 3. FIGURES 6 and 7 are pulse timing diagrams useful in understanding the memory reduction aspect of the invention; FIGURE 8 is a simplified block diagram of the reduced memory embodiment of the invention; and FIGURE 9 is a detailed block diagram of the FIGURE 8 embodiment. FIGURE 1 illustrates an NTSC composite video signal in the region about the vertical blanking interval of one television field. Positive-going pulses 10 are the horizontal svnchronizing signals occurring before time OMPI tl near the bottom of the raster. During the next time interval tl-t2, the composite signal comprises the superposition of the vertical blanking pulse 12 and six 5 equalizing pulses 14. In the next interval t2-t3 , the composite signal comprises the superposition of the vertical blanking signal 12 and a vertical sync signal 16 serrated by negative-going equalizing pulses 18. During the next interval t3-t4, the composite signal comprises the IP superposition .' of the vertical blanking signal 12 with further equalizing pulses 14. The composite signal in interval t3-t4 is identical to that in the interval tl-t2. The composite signal during the next following interval t4-t5 comprises the sum of the vertical blanking 5 . . .. signal 12 and horizontal sync pulses 10. Interval t4-t5 has a duration established ' by the number of horizontal lines selected in accordance with the desired application within the television synchronizing standard being used. In the time following time t5 and extending until the 0 next following time tl of the beginning of the next following blanking signal, the composite signal is as described above for the time preceding time tl. The composite sync for the second NTSC, field is identical except for certain half-line time shifts. 5 FIGURE 2 illustrates in simplified block diagram form a television composite synchronizing and blanking signal generator according to the invention. In FIGURE 2 , is shown a clock signal generator 210. A counter 212 is coupled to generator 210 for counting 0 clock pulses and provides a decoded output signal on parallel output lines illustrated as a broad arrow 214. The decoded signal uniquely represents each state of the counter 212 as it counts clock pulses. A digital read-only memory (ROM) 216 is addressed by the signals on lines 214. Thus, each unique state of counter 212 addresses a single memory location in ROM 216. Each memory location of ROM 216 has sufficient bit storage capacity for the number of levels required to synthesize 0 the instantaneous amplitude of the desired waveform. With 8 bits, a signal having 256 levels can be synthesized. To synthesize the waveform of FIGURE 1, three levels are required; white, blanking and sync levels, which requires a storage capacity of 2 bits. The two bits representing the three levels are provided by ROM 216 to a D-to-A converter 218 to 10 sequentially generate at the clock rate the desired 3-level analog output signals. In the event that the sync standard being Used requires a count of clock pulses less than the maximum count of which counter 212 is capable, the counter may be reset at the proper count (representing the number of clock pulses in one field or one frame, as required) . The reset is accomplished by a pulse generated by ROM 216 and applied over a conductor or line 222 to counter 212. It should be noted that the reset information requires another one-bit section of memory in ROM 216 consequently, the data path of ROM 216 must be a minimum of 3 bits in width. Other synchronization and control signals can be provided by ROM 2.16. " For example, output 220 can provide a burst flag. . in this case, each ROM memory location must have a storage capacity of four bits, two of which are used as described to generate the composite sync and blanking signal, and one of which resets the counter as described above, and a further one of which is used to control the instantaneous value which the burst flag is to have. In a similar manner, other control signals such as horizontal and vertical drive can be provided by providing sufficient additional memory capacity. The above-described arrangement carries the information to generate television sync and blanking signals for any desired standard in the form of the programming of various memory locations . Change from one standard to another within a particular piece of equipment can be accomplished by changing the programming of ROM 216, or alternately by replacing the ROM with one appropriately programmed. An erasable programmable ROM (EPROM) can be reprogrammed by first erasing the unwanted current program,(such as one which can be erased by ultraviolet light) and using an appropriate programmer for imposing the desired program on the memory. Replacing ROM 216 can be easily accomplished if it is mounted in an integrated circuit socket. The memory capacity required for the above- described arrangement is large. The memory requirements can be reduced by exploiting the cyclically redundant nature of the components making up the composite sync and blanking signals. It will be noted that in FIGURE 1 the signal in the interval between times tl and t2 is of the same shape and has the same amplitude (on a line-to-line basis) as the signal between times t3 and t4. Consequently, the signal can be generated by recurrently addressing the same ROM memory addresses. These intervals form what is hereafter called a type 1 interval. Next is the interval between times t2 and t3 which is hereafter called a type 2 interval. The sync and blanking signals during the type 2 interval are generated by addressing another portion of the ROM. The signals present during the interval between times t4 and t5 are different in amplitude and shape than those in the aforementioned intervals. The interval t4-t5 is a type 3 interval, and the sync and blanking signals produce during a type 3 interval are generated by addressing still another portion of the ROM. The last type of interval is a type 0 interval, which occurs before time tl and after time t5, and corresponds to the main portion of the television signal during which active video is present. Yet another portion of the ROM is used to store the information relating to the amplitudes of the sync and blanking components of the composite sync signal during type 0 intervals . FIGURE 3 illustrates in block diagram form a sync generator arrangement having reduced memory as compared with the arrangement of FIGURE 2. The arrangement of FIGURE 3, designated generally as 320, accepts clock pulses at an input terminal 322 from a source (not shown) and generates at various output terminals those synchronizing and blanking signals from which a composite blanking signal is formed. The clock pulses are illustrated as 501 of FIGURE 5. Since OMPI sync generator 320 may operate with equipment which ■ processes color television signals in a sampled manner, it is desirable to use a clock signal frequency which is related to the color subcarrier frequency. Often, the clock signal is at four times the subcarrier frequency (4 X SC) . However, inexpensive present logic circuits cannot operate dependably at this frequency, so in the embodiment shown the clock signal is at a frequency of one-seventh of 4 X SC. [Other clock frequencies such as one-fifth of 4 X SC may be used.] Clock signal 501 is applied to both a horizontal counter 324 and to a. horizontal latch circuit 326 as illustrated in FIGURE 3 ' . ' Horizontal counter 324 is a synchronous seven- bit binary counter, each of the cells or stages of which is coupled by an address line to a corresponding portion of a horizontal ROM 328. Horizontal counter 324 also produces on an output conductor 330 a signal illustrated as 410 of FIGURE 4 having twice the horizontal frequency. This twice-horizontal-frequency signal is produced by dividing the frequency of clock signal 501 by an appropriate factor. Counter 324 is capable of a maximum count of 128, but is reset by a signal from an appropriate memory location in ROM 328 (by way of latch 326) at the appropriate count. For a particular embodiment of the sync generator for producing a standard NTSC sync signal, the clock frequency of clock signal 501 is 2.04545 MHZ and the corresponding count of counter 324 is 65. The twice horizontal frequency signal produced on conductor 330 by dividing 2.04545 MHz by the divisor 65 is applied to a vertical counter 332, to a divide-by 2 counter 336, and to a latch circuit 334. The counter 332 has a unique state during each half-line of a field. Vertical ROM 338 decodes the unique state of the counter 332 and for each state produces an output (outputs) from the corresponding memory location. ROM 338 must have a bit width or memory capacity at each location commensurate to the application. As in the • arrangement of FIGURE 2, one memory bit per location or address is used to generate the counter reset pulse. The reset pulse is generated when the appropriate count of counter 332 addresses the memory location of ROM 338 containing a logic 1 (for the positive-logic case) , rather than the logic 0 occurring at all other prior addresses. The reset pulse is coupled from ROM 388 at output terminal 02. Other output signals of ROM 338 are the vertical drive signal, which appears at output terminal 03, and horizontal page selection signals which appear at output terminals 00 and 01 of ROM 338. These 'various' output signals of ROM 338 are applied to corresponding -input terminals of a vertical latch circuit 334. Latch 334 acts to reclock the signals in accordance with half-line signal 410. This reclocking accommodates internal delays of counter 332 and ROM 338. In effect, the latch output signal corresponds to the ROM output signal for the preceding half-line. Vertical reset pulse 412, vertical drive pulse 414 , and the horizontal page selector signals 416 and 418 as illustrated in FIGURE 4 are generated at output terminals L2 , L3, L0 and Ll respectively, of latch 334. Each of the cells or stages of counter 332 is coupled by one of ten address lines (VAO-VA9) to a corresponding portion of vertical ROM 338. ROM 338 decodes the addresses represented by each unique state of counter 332 as it counts the twice-horizontal frequency signal applied to the counter input. Ten-stage counter 332 is capable of a maximum count of 1024, but is reset as described by the appropriately programmed ROM according to the required standard being generated. In this particular embodiment for producing standard NTSC frame of 525 lines, counter 332 counts 525 twice-horizontal frequency pulses 410 (which have a duration of one-half horizontal line) during each field. For other standards, as for example the aforementioned 655-line standard for film compatibility, or for 625-line 5 PAL or SECAM, counter 332 is reset during the appropriate count. In a similar manner, counter 332 addresses ROM 338 to provide the vertical drive signal to latch 334. Latch 334 reclocks this drive signal to provide 10 at output L3 the seven full lines duration vertical drive signal 414. Negative-going signal 414 begins between half line intervals 6 and 7 as illustrated in FIGURE 4 and ends between half line intervals 20 and 21 (not shown) for NTSC. Since this signal 414 changes 15 at one-half line intervals ' , no information from horizontal ROM 328 is required to. generate it. Consequently, vertical drive signal 414 can be derived exclusively from vertical ROM 338. This is true in the case ' of all the above-mentioned standards, the only difference ■ 20 being the occurrence of the leading and.trailing edges with respect to the zero labelled half line. The width in all of these standards is the same seven full lines at NTSC. The page signals 416 and 418 at outputs LO 25 and Ll, respectively, are used to identify which one of the types of intervals is currently being counted or generated, and this information is applied to horizontal ROM 328 at inputs H 8 and HA9 respectively. In particular, during the type 0 intervals both page signals are low. 30 During type 1 intervals page signal 416 is high, while page signal 418 is low. In the type 2 intervals, page signal 416 is low, and page signal 418 is high. Type 3 intervals have the both signals 416 and 418 high. If it is desired to provide other signals, e.g., color 35 bar gating signals or while balance cursor, then it is necessary to provide more page address lines from latch 334 to ROM 328, thus dividing each field into more intervals. However, for every new page address line, the size of ROM 328 must be doubled. 40 OMPI A problem is encountered due to the interlace structure of the NTSC frame, which requires a one-half line offset of the composite sync and blanking signals between successive fields. This is shown by signals 420 and 422 of FIGURE 4 for field one as compared to signals 424 and 426 for field two. Since the counters are based on half scan line intervals, we can provide for interlace by a free running counter (one that never gets reset) such as counter 336 operating at the line frequency. This free running clock 336 is 180° out-of-phase during the same vertical count in each of two successive fields due to the odd number of half lines per field. Using the output signal 502 shown in FIGURE 5 of clock 336 as address signal for address line HA7 for ROM 328 permits identification of which half of the selected "type of line" it is desired to be read out of memory for that one-half line interval. The two different half line intervals determined by counter 336, when taken in combination with the four types of intervals (type Q - type 3) determirsd by the page signals, result in a total of eight half line. intervals. These eight unique half-line intervals are stored in eight corresponding pages " on portions of horizontal ROM 323. ' The final address lines that remain are those that originate from the horizontal counter 324. These seven address lines HAC--HA5 sequentially access the memory locations cf ho izo al ROM 323 and ' read out the stored amplitude-of the timing signals from the pages of ROM memory addressed by the page signals in the time interval chosen by the master clock applied to input 332. These timing signals are shown in FIGURE 5 for all eight half-line intervals. In particular, they are composite sync signals 503a, 503b, 503c, and 503d during intervals type 0 to type 3 respectively, which are present at output H00 of ROM 328. Signal 503a comprises the horizontal sync signal during active video signal, 503b is the equalizing pulses. Signal 503c comprises the vertical serrations, while signal 503d is the horizontal sync during the vertical blanking interval. Composite blanking signals 504a, 504b, 504c, and 504d are present during intervals type 0 to type 3 respectively at output H01. Signal 504a is the horizontal blanking .during horizontal retrace, while signals 504b, 504c, and 504d are the blanking during the vertical blanking interval, i.e., there is blanking during the entire horizontal scan as indicated by logic "0" throughout the scan. Horizontal drive signal 505 is present during intervals type 0 to type 3 respectively at output HO2 and is the same for all interval types. A horizontal reset signal 506 is shown, which is the same for all half line intervals, and it is present at output HO3. - The occurrence of the pulse therein is under the control of ROM 328, and the address or addresses at which it occurs can be changed in accordance with the desired standard to be generated and the clock frequency which is desired. In addition, if for a given standard, a higher resolution or accuracy is desired, a higher frequency clock signal at input 322 is required. This, " in turn, requires a different place in ROM 328 in order for reset signal 506 to occur at the same time 'at the beginning of every half line. All of the above-described signals generated by ROM 328 are present at the respective ' ROM 328 outputs one cvcle cf the clock si rnal at 322 sooner than shown in FIGURE 5. They are applied to latch 326, which reclocks them in accordance with the clock signal at input 322. This is to compensate for the delays inherent in counter 324 and ROM 328. The composite sync, composite blanking, horizontal drive, and horizontal reset signals are available for any desired system application. Typically, the composite sync and composite blanking signals are coupled to a level-shifting circuit for creating the amplitude superposition necessary to form the composite sync and blanking waveform of FIGURE 1. This corresponds functionally to the D-to-A converter 218 of FIGURE 2. Counter 324 is a seven stage counter capable of 128 counts, but in the described embodiment is reset at the occurrence of the sixty-fifth count by the horizontal reset pulse 506. This occurs twice during each horizontal line. FIGURE 6 illustrates a part of the equalizing pulse interval. FIGURE 6b illustrates in expanded form one equalizing pulse 62 and FIGURE 6c illustrates 4 X SC clock pulses to the expanded scale. In the vicinity of times t60 and t70 at which transitions take place in the pulse waveform, the clock pulses must be closely spaced to prbvide sufficient resolution. This may be especially true if the pulse edges are not abrupt as shown but have a finite rise-time. For the interval between t60 and t70, however, the magnitude of pulses 62 does not change.. Also, after time t70 there is an interval of about 35yS in which the sync value is low. It can be seen that the regions around t60 and t70 requiring high resolution are relatively small, yet many memory locations must be provided for storing redundant information at high resolution everywhere else. According to the further aspect of the invention, the clock xate is changed during the generation of the sync interval as shown in FIGURE 7. As illustrated in FIGURE 7b around time t6G and t70, many clock pulses are provided for high resolution. In the broad flat areas, few clock pulses are provided. This is accomplished by using an additional bit of memory at each address, preprogrammed with a logic 1 or a logic 0 in a pattern 64 as illustrated in FIGURE 7c. Pulse pattern 64 represents the value of the additional bit at each memory location. A logic 0 is stored in the additional bits of the memory addressed by clock pulses t57 and earlier. This represents a low clock rate. The clock rate remains low until the next clock pulse occurs at time t58. When clock pulse t58 addresses the memory, the additional bit at that location has a logic 1, representing a high clock rate. The clock responds by switching to a high rate and in quick succession addresses t59, t60, tδl and t62 address locations, all of which have a logic 1 additional bit. The ' clock rate remains high after pulse t62 addresses a memory location, and t63 clock pulse occurs in quick succession. The corresponding memory location at the t63 address is a logic 0, representing ' a low clock rate. The clock returns to the low recurrence rate, and only three clock pulses occur at the low rate in the interval t63-t66. The additional bit addressed by clock pulse t66 is a logic 1, and the clock returns to the high speed mode for the duration of the high level of pulse 64. In this -way, the number of memory locations required to be addressed can be very much reduced from about 43 in the arrangement of FIGURE 6 to about 8 in FIGURE 7. FIGURE 8 illustrates a simplified block diagram of a reduced memory arrangement. FIGURE 8 is similar to FIGURE 2, except that an additional controllable counter 820 is included between clock signal generator 810 and counter/decoder 8-12. Counter 820 is of a known type in which the level of the logic signal on its control input determines the modulus by which the fixed-rate clock pulses from generator 810 are counted to produce piecewise-periodic clock signals as illustrated in conjunction with FIGURE 7. Counter 820 may include for example a fixed divide-by-16 counter and a switch controlled by the control input which takes an output from the divide-by-16 counter or directly from the fixed clock. FIGURE 9 is a detailed block diagram of a reduced memory counter-ROM ' sync generator according to the invention. In this arrangement, elements corresponding to those in FIGURE 3 have the same reference number. In FIGURE 9, a master clock generator 900 produces fixed clock pulses f which are applied to inputs of a multiplexer 902 and a divide-by-Nl counter 904. A horizontal resolution select signal taken from the additional bit in the memory and held by latch 326 is used to control the resolution as described previously on a line-to-line basis. Multiplexer 902 selects either the master clock or the"divided master clock to advance horizontal counter 324. Similarly, a vertical resolution select signal is applied from vertical latch 334 to a vertical multiplexer 906 which selects either the counted-down output of horizontal counter 324 directly or the output of 324 further divided by N2 in counter 908. The embodiment of FIGURE 2 was constructed using integrated circuits as follows: Block Quantity Component No. Manufacturer 324 .1 74LS393 Texas Instruments 332 1 CD4040 RCA Corporation 36,326,334 4 each - 74LS175 Texas Instruments 328,338 2 each 2758 Intel Other embodiments of the invention will be apparent to those skilled in the art. For example, the clock pulses may be at the 4 X SC rate or at any desired rate so long as logic of commensurate speed is used. Where gross change issynchronizing standard is contemplated, the number of stages in horizontal counter 324 and vertical counter 332 may be increased to accommodate large numbers of samples per line or large numbers of lines per field. Synchronizing and blanking signals other than those shown may be generated, as for example, pulses identifying particular lines in interval t4-t5 for identifying ancillary information. 0 - Other embodiments of reduced memory aspect of the invention will also be apparent to those skilled in the art. For example, several different levels of resolution may be used in order to minimize the memory requirements, whereupon two or more additional bits would be necessary at each memorylocation. ° Rather than dividing down from a master clock generator,several clock generators at different rates might be used. The clocks can be slaved to sync or to burst in knownmanner. The resolution can be changed in many ways,as by having high resolution during only the entire vertical blanking interval and during each 0 succeeding horizontal blanking interval.

Claims: CLAIMS : 1. A method for generating a television synchronizing signal- comprising the steps of, storing information relating- to the magnitude of at least one component of a composite synchronizing signal at each of a predetermined plurality of sampling points in each television frame; and generating sampling signals for recurrently addressing said memory means for reading said information from said memory for generating said component signal. 2. A.television synchronizing signal generator comprising: memory means for storing information relating to the magnitude of at least one component of a composite synchronizing signal at each of a predetermined plurality of sampling points in each television frame; and clock signal generating means coupled to said memory means for generating sampling signals for recurrently addressing said memory means for reading said information from said memory for generating said component signal. . .. . * 3. A television synchronizing signal generator according to Claim 2 wherein said component comprises horizontal synchronizing information. 4. A television synchronizing signal generator according to Claim 2 wherein said component comprises vertical synchronizing information. 5. A television synchronizing signal generator according to Claim 2 wherein said component comprises blanking information. 6. A television synchronizing signal generator according to Claim 2 wherein said composite synchronization signal comprises composite horizontal and vertical synchronization signals and composite blanking signal components. 7. A television synchronizing signal generator according to Claim 2 wherein said memory means comprises horizontal and vertical memories, and said generating means comprises cascaded horizontal and vertical counters coupled to said horizontal and vertical memories respectively. OMPI 8. A television synchronizing signal generator according to Claim 7 further comprising horizontal and vertical latches coupled to said horizontal and vertical memories respectively. 9. A television synchronizing signal generator according to Claim 7 wherein said horizontal and vertical memories provide reset signals to said horizontal and vertical counters respectively. 10. A television synchronizing signal generator according to Claim 7 wherein said vertical memory provides 'at Least one page address signal to said horizontal memory. • 11. A television synchronizing signal generator according to Claim 10 wherein said page address signal is two in number whereby four types of time intervals can be determined within said horizontal memory. 12. A television synchronizing signal generator according to Claim 7 further comprising a further counter coupled to between the output of said horizontal counter and said horizontal memory to determine half-line intervals. 13.-A television synchronizing signalgeneratoradapted fαrready conversionamongvarioustelevision standards comprising: memory means for storing information relating to the magnitude of at least one component of a composite synchronizing signal at each of a predetermined plurality of sampling points in each television frame; and clock signal generating means coupled to said memory means for generating periodic sampling signals for recurrently addressing said memory means for reading said information from said memory for generating said component signal. OMPI_ - 14. A television apparatus adapted for ready conversion among various television standards, comprising: memory means for storing information relating to the magnitude of at least one component of a composite synchronizing signal at each of a predetermined plurality of addresses each related to a particular sample time in each television frame; and clock signal generating means coupled to said memory means for generating piecewise-periodic _ sampling signals for recurrently addressing said memory means for reading said information from said memory for generating said component. 0 15. A television apparatus according to Claim 14 wherein said clock signal generating means comprises: periodic clock signal generating means; and controllable clock signal generating means coupled with said periodic clock signal generating means 5 and with said memory means for controlling said periodic clock signals to form said piecewise-periodic sampling signals. 0 5 0 O PI

Inventors: MARLOWE F, SMITH T
Applicants: RCA CORP
Application year: 1981
Main classification: H04N5
IPC codes: H04N5