SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device which is strong against noise such as α-ray and has an improved hold cha­ racteristic of stored data is disclosed. The device compri­ ses a pair of multi-emitter transistors structured as a flip-­ flop and is featured in that each of the pair of transistors is provided with a third emitter region (5, 5′) and the third emitter region of each of the transistors is electrically con­ nected to the collector (2, 2′) of the same transistor.

Description: SEMICONDUCTOR MEMORY DEVICE The present invention relates to a semiconductor memory device, and more particularly, to a memory call employing a flipflop circuit constructed of bipolar transistors. Owing to the development of the technique of micro-fine patterning, a memory capacity of a semiconductor memory device has been rapidly and greatly increased. In accordance with miniaturization of circuit elements such as transistors achieved by the micro-fine patterning technique, parasitic capacitances in a circuit have been remarkably reduced. Consequently, speed-up of operations and power reduction of parasitic capacitances imply that an electric charge quantity which takes part in holding of a memory state in a memory cell is reduced. Therefore, if noisy electric charge caused by > -rays should income to a memory cell externally, the storage condition of electric charge in a memory cell would be easily inverted or changed, resulting in a faulty operation of the memory cell, that is, the so-called "soft error". Especially, if d -rays generated from packagingmaterial of an integrated device or the like in a natural state should strike a semiconductor chip, then a certain quantity of electric charge would be induced there. If this should arise in a memory cell section, the memory contents would be liable to be inverted. As a result, the memory cell section is now becoming very fragile in respect to reservation of memory contents. It is therefore one object of the present invention to provide a bipolar memory cell which is free from a soft error, especially an aL-ray error and is suitable for high-density circuit integration. According to the inventive concept of the present invention, attention is paid to the fact that if an additional capacitance is associated with a collector of a bipolar transistor, then reduction of a stored voltage caused by electric charge induced by ;i-rays can be held minimum. In the present invention, as the most effective method for providing an additional capacitance, an additional emitter region is newly provided in the bipolar transistor. This additional emitter region is connected to a collector of the same-transistor. Thus, the collector-substrate capacitance, emitter-base capacitance and collector-base capacitance accompanying to this modification are jointly used for increasing the quantity of electric charge stored in the collector portion of the transistor in the memory cell, and thereby it is intended to prevent inversion of memory contents in a memory cell due to noisy electric charge caused by d -rays. When this featured bipoiar transistor is use for forming aflip-flop type memory cell, capacitances of pair of collector nodes of the flip-flop can be remarkably increased and hence hold characteristic of the memory cell can be improved. It should be noted that the above featured transistor according to the invention is also applicable to a logic transistor for an inverter circuit, a general purpose flip-flop circuit, a shift-register and so on wherein stability against noise such as O( -ray can be improved. A memory cell according to the present invention employs a pair of multi-emitter transistors each having a collector, a base, a first emitter and a second emitter, the collectors and bases of the first and second transistors being cross-coupled from each other, the first emitters of the first and second transistors being connectable to a word line, the second emitters of said first and second transistors being connectable to a pair of digit lines respectively, and characterized in that, a first semiconductor region is provided in the base of the first transistor and a second semiconductor region is provided in the base of the second transistor, the first and second semiconductor regions having the opposite conductivity to that of the bases of the transistors wherein the first semiconductor region is electrically connected to the collector of the first transistor, and the second semiconductor region is electrically connected to the collector of the second transistor. According to the present invention, there is provided a semiconductor device comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type opposite to the first conductivity type formed in the first semiconductor region, a third and a fourth separate semi conductor regions of the first conductivity type formed in the second semiconductor region, first means for electrically connecting the third region to the first region, second means for supplying the first semiconductor region with a predetermined voltage and third means for supplying the second region with a logic signal, wherein an output signal corresponding to said logic signal is derived from the fourth region. According to the present invention, there is also provided a semiconductor device comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a second and opposite conductivity type formed in the first semiconductor region, a third semiconductor region of the first conductivity type and having higher impurity concentration than that of the first semiconductor region, the third semiconductor region being formed on both a first portion of the first semiconductor region and a second portion of the second semiconductor region adjacent to - the first portion, and a fourth semiconductor region formed in the second semiconductor region, first means for supplying the third semiconductor region with a predetermined voltage, and second means for supplying the second semiconductor region with a logic signal, in which an output signal corresponding to the logic signal is derived from the fourth semiconductor region. Now, consideration will be made on how the condition where hold of memory contents in memory cells becomes difficult is brought about by irradiation of #C -rays. Normally, side faces and a bottom face of a transistor forming a memory cell is isolated from a silicon substrate which is normally of P-type conductivity by a reverse-biased depletion layer of 3 - 4 Crm in thickness formed between the transistor and the substrate. Electron-positive hole pairs produced in the depletion layer between the collector and the substrate by irradiation of OC -rays will act in the direction of reducing electric charge stored at the collector node, and especially in the case where the off-side transistor forming the flip-flop type memory cell is irradiated by -rays, the electron-positive hole pairs act in the direction of pulling down the collector potential by an amount corresponding to a predetermined electric charge quantity. If the collector potential of the off-side transistor is lowered in this way, these arises the posibility that it becomes nearly the same level as the collector potential of the on-side transistor, and hence the memory contents are inverted in the direction determined by the unbalance of the electrical parameter in the circuit elements forming the flip-flop in the memory cell. It is to be noted that although the excitation of the electron-positive hole pairs caused by passage of 3(-rays would arise not only in the above described depletion layer between the collector and the substrate but also in the depletion layers between the collector and the base and between the base and the emitter, in view of the thickness of the depletion layers it is believed that the electron-positive hole pairs produced within the depletion layer between the collector and the substrate could predominantly contribute to inversion of the memory cell contents. In any event, it is obvious that if the capacitance connected to acollector node of the memory cell transistor is made large, then stability against generation of noisy electric charge caused by CC-rays would be increased because the stored electric charge quantity in a steady state is increased. According to the present invention, in order to increase a capacitance associated with a collector, the capacitance of the collector per se is not directly increased but one emitter is additionally provided in a flip-flop transistor. The emitter has a high impurity concentration, and hence, the capacitance associated with the base-emitter junction is large as compared to its area. Moreover, owing to a minor effect, the effective capacitance value contributing to the hold of memory contents really acts as a capacitance four times as large as this capacitance of the base-emitter junction. The above -mentioned and other features and advantages of the present invention will become more apparent by reference to the following description of preferred embodiments of the present invention taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a circuit diagram of a heretofore known memory cell, Fig. 2 is a cross-section view showing a transistor structure used in the known memory cell as illustrated in Fig. 1, Fig. 3 is a circuit diagram of a memory cell according to the present invention, Fig. 4 is a plan view of a memory cell according to a first embodiment of the present invention, Fig. 5 is a cross-section view showing a transistor structure available in the memory cell of Fig. 4. Fig. 6 is a plan view of a memory cell according to a second embodiment of the present invention, and Fig. 7 is a cross-section view showing a transistor structure available in the memory cell of Fig. 6. At first, description will be made on a bipolar memory cell in the prior art with reference to Figs. 1 and 2. An equivalent circuit of a bipolar memory cell in the prior art is depicted in Fig. 1. As shown in Fig. 1, respective bases 3, 3' and collectors 2, 2' of multi-emitter transistors Q1 and Q2 each having two emitters are cross-connected at nodes N1 and N2. An emitter 7 of the transistor Ql is connected to a true date line D, while an emitter 7' of the transistor Q2 is connected to a complementary data line D. The other emitters 6 and 6 of the respective transistors Q1 and Q2 are connected in common to a word line W. A collector 2 of the transistor Q1 is connected to a voltage source V through a resistor 10 and a Schottky barrier diode (SBD) 8. Likewise a collector 2' of the other transistor Q2 is connected to the voltage source V through a resistor 10' and a SBD 8'. A detailed structure of the multi-emitter transistor Q1 in Fig. 1 is illustrated in Fig. 2. In Fig. 2, component parts corresponding to those shown in Fig. 1 are designated by like reference numerals. Of course, the transistor Q2 has exactly the same structure as the illustrated transistor Q1 The transistor illustrated in Fig. 2 includes a P-type substrate 1, an N-type collector region 2, a P-type base region 3 formed in this collector region 2, further a P+-type base ohmic contact 4 and N+-type emitters 6 and 7 both formed in the base region 3, and a collector ohmic contact 2C formed within the collector region 2, and on the collector region 2 is provided a metallic layer 8 for forming a Schottky barrier diode. Considering now a parasitic capacitance CC associated with one collector node N1, it is composed of a capacitance CCS between the collector and substrate, a capacitance CCB between the collector 2 and base 3, a capacitance CBC between the base 3' and collector 2' of the opposite side transistor Q2, a capacitance 2 CBE between the base 3 and first and second emitters 6 and 7, a capacitance CD of the Schottky barrier diode 8, and a capacitance CR between the resistor 10 and substrate. The capacitance between the base and collector is effective nearly double because of a known mirror effect, and so, assuming that CBC ¯ - CCB for the sake of simplicity, the parasitic capacitance CC can be represented as follows: CC = 4 CBC + 2 CBE + CCS + CD + CR ....... (1) The typical value of the capacitance CC is about 10 PF when the memory all is formed on an area having a width of 40 ,um and a length o#f 60 m. Now one preferred embodiment of the present invention will be explained with reference to Figs. 3 to 5. As shown in Fig. 3, according to the present invention, transistors Q1' and Q2' each having three emitters are used. A third emitter 5 of the transistor Q1' is connected to its collector 2, and a third emitter 5' of the transistor Qz' is connected to its collector 2'. The other circuit construction in Fig. 3 is similar to that shown in Fig. 1, and emitters 6 and 6' are connected in common to a word line W, while emitters 7 and 7' are respectively connected to date lines D and D. Now in the transistors Q1' and the emitters 5 and 5' connected to the collectors of the same transistors are in a reverse-biased condition with respect to the bases 3 and 3' of the same transistors, and hence current paths from the emitters 5 and 5' to the bases 3 and 3' are not present. Therefore, it is obvious that the circuit operation of the memory cell in Fig. 3 is basically identical to that of the memory cell in the prior art shown in Fig. 1. However, it is to be noted that in this case since the emitters 5 and 5' are held in a back-biased condition with respect to the bases 3 and 3', they have the functions of capacitances. Accordingly, the collectors 2 and 2' of the transistors Q1' and Q21 would be added with capacitances due to the emitters 5 and 5'. Therefore the quantities of electric charge stored at the collectors 2 and 2', respectively, in accordance with the information to be stored, would increase by the amount corresponding to the increase of capacitance due to the emitters 5 and 5', and hence the capability of holding -the memory information can be widely enhanced. With reference to Fig. 4, first layout example of the memory cell shown in Fig. 3 will be explained. In this figure, the same reference numerals are employed for portions corresponding to those in Fig. 3. A memory cell is fabricated on a P-type semiconductor area 30 having a width of 40 Clm and a length of 60 Fm. The transistor Q1' is composed of an N-type collector region 2, a P-type base region 3, and three N-type emitter regions 5, 6 and 7. P+ base contact regions 4 and 4' are formed respectively in the base regions 3 and 3'. In the collector region 2, an N+ region 2C is formed for a contact purpose. The transistor Q2' has a similar structure whose layout of the respective regions is a rotational symmetrical relation to that of the transistor Q1 The pair of digit lines D and D are made of aluminum wirings extending in a longitudinal direction. The word line W is made of an aluminum wiring extending in a lateral direction. The power voltage line (A) is realized by two separate aluminum wirings 32 and 33 extended in the lateral direction. The base contact region 4 of the transistor Q1' is connected to the third emitter 5a' and the collector contact region 5b' by a polycrystalline silicon wiring 9' which is highly doped with P-type impurity. This wiring 9 is very highly doped and hence does not form an effective PN barrier with the N+-type region 2C' so that ohmic connection therebetween is obtained. Similarly, the collector contact region 2G and the sriterregion 5' of the transistor Q1' are connected to the base contact region 4' of the transistor Q2' by a polycrystalline silicon wiring 9 which is highly doped with a P-type impurity. The resistors 10 and 10' are made of a polycrystalline silicon wirings which are slightly doped with a P-type impurity. Wirings 34 and 35 respectively for connecting the wiring 32 and the register, -and the wiring 33 and the register 10' are made of highly N-type doped polycrystalline silicon wirings. The shottcky diodes 8 and 8' are formed by platinum layers contacted to the collector regions 2 and 2' through contact holes. Then, a further detailed practical structure of the transistor Q11 will be explained with reference to Fig. 5. It is to be noted that the structure of the other transistor Q2' is also identical to the illustrated structure. In Fig. 5, component parts corresponding to those shown in Fig. 3 are designated by like reference numerals. With reference to Fig. 5, as compared to the structure shown in Fig. 2, the third emitter 5 and a conductor 9 for connecting the third emitter 5 to a collector contact region ZC are newly added. Normally, the third emitter S is formed simultaneously with emitters 6 and 7, and so, increase in manufacturing step does not occur. Here, considering the effect of the provision of the third emitter, this emitter forms a junction capacitance CBE between the base region 3 and the emitter, and in view of the circuit construction this capacitance CBE is added in parallel to the capacitance Car between the collector region 2 and the base region 3. Hence, it has an effect of increasing a capacitance by 4X CBE than Equation ( 1) above. Moreover, a capacitance per unit area is largest for the capacitance between the base and the emitter having a high impurity concentration, and hence, although the third emitter 5 is small in area, it has a large effect. It is also to be noted that the increments of capacitances < CCS and a C3C caused by the increase of the junction areas between the collector and substrate and between the base and collector, respectively, serve as increments of the capacitances associated with the collector nodes N1 and N2 of the respective transistors. Therefore they are effective for protecting the memory cell from the 0t -ray error. Thus, the resultant increase o CC of the collector node capacitance becomes 4 CC = 4 x CBE + #CCS + AC3C ¯ -........ (2) According to the above embodiment, the typical value of the total capacitance of the collector node is about 12 PF. Thus, increase of about 2 PF in the collector node capacitance can be achieved. An area of a memory cell is substantially dependent upon the areas of the collectors of the two transistors Ol' and Q2'. As a method for straightforwardly increasing a capacitance associated with a collector, it may be conceived to enlarge the area of the collector per se. However, this will straightly bring about increase of the area of the memory cell, and so, it is not favorable. According to the present invention, it is only necessary to additionally provide one emitter in each transistor, and the base region where the emitter is to be additionally provided, generally has a margin in space, so that the increase of the collector area caused by additionally providing an emitter in the base region is very small. According to the present invention, the capacitance associated with the collector can be increased by about 20% as compared to the transistor structure shown in Fig. 2. It has been proved that if the collector load capacitance is increased by about 20%, then the probability of occurrence of the soft error due to OC -rays on the like can be reduced by a factor of 1/102. A second detailed semiconductor structure of the memory cell according to another embodiment of the present invention will be explained with reference to Figs. 6 and 7. In this embodiment, a highly-doped N+ region 51 is formed on a region including a portion of the collector region 2 and a portion of the base region next to the portion of the collector region in place of the regions 5 and 2C of Fig. 4. The portion of the region 51 within the base region 3 acts as the previously mentioned third emitter 5. Also the region 51 forms an electrical connection between the collector region 2 and the third emitter region. Similarly, highlydoped N+ region 51' forms the third emitter region with its part within the base region 3' and electrically connects the third emitter and the collector region 2'. Remaing portions are similar to those Fig. 4. The structure of the transistor Q1' according to the present invention is illustrated in Fig. 7. In this transistor structure, the third emitter 5 and the collector ohmic contact 2C shown in Fig. 4 are modified into one integral N+-type region 51 to automatically short-circuit the collector region 2 and the third emitter 5 and thus omit the conductor 9 connecting the collector to the third emitter. In this preferred embodiment also, the increament #CC of the collector node capacitance Cc is represented, similarly to the above -described first embodiment, approximately by the following equation: 4 CC = x CBE +# CCS + 4 CBC Therefore, as will be apparent by comparing Fig. 6 to Fig. 2, the collector node capacitance can be most effectively increased with only a slight increase of the transistor size accompanied. As described in detail above, the present invention has the effects and advantages that by adding a large capacitance to a collector node of a flip-flop transistor in a memory cell with only a slight increase in the memory cell area as a whole, memory information in a memory cell can be reserved stably against noisy electric charge caused by Ok -rays, without increasing the manufacturing steps.

Claims: I claim: 1. A semiconductor memory device comprising a pair of digit lines; a word line; and a memory cell; said memory cell including a first and a second bipolar transistors each having a collector, a base, a first emitter, a second emitter, and a third emitter, first connection means for connecting said collector of said first transistor to said base of said second transistor, second connection means for connecting said collector of said second transistor to said base of said first transistor, third connection means for connecting the first emitters of said first and second transistors to said word line, fourth connection means for connecting the second emitter of said first transistor to one of said pair of digit lines, fifth connection means for connecting the second emitter of said second transistor to the other of said pair of digit line, sixth connection means for connecting the third emitter of said first transistor to said collector of said first transistor, and seventh connection means for connecting the third emitter of said second transistor to said collector of said second transistor. 2. The device as claimed in claim 1, further comprises a source of power voltage, first load means connected between said collector of said first transistor and said source of power voltage and second load means connected between said collector of said second transistor and said source of power voltage. 3. The device as claimed in claim 1, in which said first and second connection means include wirings made of a polycrystalline silicon. 4. A semiconductor device comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type opposite to said first conductivity type formed in said first semiconductor region, a third and a fourth separate semiconductor regions of said first conductivity type formed in said second semiconductor region, first means for electrically connecting said third region to said first region, second means for supplying said first semiconductor region with a predetermined voltage and third means for supplying said second region with a logic signal, wherein an output singal in response to said logic signal is derived from said fourth region. 5. A semiconductor device comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a second and opposite conductivity type formed in said first semiconductor region, a third semiconductor region of said first conductivity type and having higher impurity concentration than that of said first semiconductor region. said third semiconductor region being formed on both a first portion of said first semiconductor region and a second portion of said second semiconductor region adjacent to said first portion, and a fourth semiconductor region formed in said second semiconductor region, first means for supplying said third semiconductor region with a predetermined voltage, and second means for supplying said second semiconductor region with a logic signal, in which an output signal corresponding to said logic signal is derived from said fourth semiconductor region. 6. The device as claimed in claim 4 or 5, further comprising a shottcky barrier diode formed on said first semiconductor region. 7. The device as claimed in claim 4, in which said third and fourth semiconductor regions have higher impurity concentration than that of said first semiconductor region. 8. The device as claimed in claim 4 or 5, further comprising a fifth semiconductor region of said first conductivity type formed in said second semiconductor region. 9. In a memory cell employing a pair of multi-emitter transistors each having a collector, a base, a first emitter and a second emitter, said collectors and bases of said first and second transistors being cross-coupled from each other, said first emitters of said first and second transistors being connectable to a word line, said second emitters of said first and second transistors being connectable to a pair of digit lines respectively, the improvement comprising a first semiconductor region formed in said base of said first transistor, a second semiconductor region formed in said base of said second transistor, said first and second semiconductor regions having the opposite conductivity to that of the bases of said transistors, first means for electrically connecting said first semiconductor region to said collector of said first transistor, and second means for electrically connecting said second semiconductor region to said collector of said second transistor.

Inventors: SUZUKI, MASAO
Applicants: NEC CORPORATION
Application year: 1981
Main classification: G11C11
IPC codes: H01L23, H01L21, H01L29, G11C11, H01L27