IMPROVEMENTS IN OR RELATING TO SYNCHRONISING OF CLOCKS

Abstract: A time clock modem transmitter comprises a pseudo-random number generator (PNG) which produces a time-spaced sequence of pseudorandom numbers such that each number uniquely represents the time of day. A transmitter PNG (11) capable of producing a polynomial sequence longer than 24 hours is reset every 24 hours by a transmitter reference clock (4). A receiver clock modem includes a receiver PNG (26) having the same polynomial characteristics as the transmitter PNG (11). A received signal number is fed into the receiver PNG and PNG is then started. The output from the receiver PNG and the received signal are then compared to ensure correct synchronisation of the receiver clock modem. A detector is provided which is responsive to the random number representing 2400 hours such that it produces a resetting output pulse at 2400 hours to reset a receiver reference clock. Clock pulse generators 19 and 28 are provided to rapidly advance by one cycle on actuation the reference clock and PNG respectively in the transmitter and the receiver for resetting the clocks.

Description: IK ROVSI-ZKTS IN 03 -RELATING TO SYKCHRONISI G OF CLOCKS The invention relates to the standardisation of clocks as is required for example in modern communications systems. In the field of communications, particularly where net-working systems are used, there is frequently a need to acquire and then maintain over long periods of time an accurate time-signal reference to operate electronics communications equipment. Ivoάern atomic frequency standards are readily available having drift rates of 1 in 1θ '! 2 which can maintain an accurate reference over long period of time without the need for frequent checking or correcting. ϊhe difficulty experienced in standardising distant clocks is to obtain a sufficiently accurate synchronising tine-signal. Generally, current net-working systems require an accuracy of only better than 1 second as they run at relatively low baud rates and/or they have been specifically designed to operate from such timing sources. However recent developments in HF/VHF communication systems indicate that timing accuracies within the range 100 microseconds to 10 milliseconds will be necessary. The requirement for a time signal source can be met at present using a reasonably stable clock and a standard time signal transmission such as KSF, Vr./V or GBP. etc. The high speed time codes used by these services are transmitted in short burts once per minute on the minute. The trε-π-εzitteά sequence contains a simple framing preamble followed by a 100 baud data code giving GKT and the date. Although in principle a simple serial to parallel conversion is all that is required to decode the information contained in these transmitted codes in practice sophisticated error checking would be essential to discriminate against unwanted signals and to avoid erroneous decoding. BAD ORIGINAL &' o:*'π_ Errors in time code acquisition can occur because of poor propa ation or high interference levels which frequently pervade the ~ f.F radio spectrum. The accuracy with which the time code signal can be received will depend on the signal to noise ratio of the transmitted time signal, the band width of the receiver and the coding format. The object of the present invention is to provide a time code modem which adopts a special modulating technique to provide a timing accuracy which is better than has been previously possible for a given bandwidth. In one form the invention provides a transmission clock modem for transmitting time-coded signals which comprises: a transmission pseudo-random number generator (PKG) to generate a train of pseudo-random numbers; pulse generator means to produce clocking pulses for correction to the transmission FKG such that the output numbers from the trans¬ mission PNG are equi-εpaced in time; resetting means connected from the reference clock to the transmission PKG such that the transmission PNG is reset to a predetermined condition, hereinafter referred to as zero, after a preselected time interval: and means to transmit the output from the transmission PNG. P G's are well knov circuits which produce an apparently random series of encoded numbers up to a maximum number which then repeats cyclically. Thus by mailing an appropriate choice of transmission FKG, clocking pulse rate and preselected time interval the total of pseudo¬ random numbers within the train of numbers can be kept within the maximum possible number for the PKG and therefore each nuπber in the train will uniquely define the time within the preselected time interval. Preferably the resetting means comprises a transmission reference clock which produces an output resetting pulse at the end of each of the preselected time intervals. Advantageously the time interval!, is 2**+ hours. Thus after the PNG output is a number representative of 2-^000 hours the PKG is reset and the random number train starts again from zero. In order to synchronise the transmission PNG and the transmission reference clock there is provided a pulse generator which can be actuated to add to the transmission PKG a number of clocking pulses equal to the number of pseudo-random numbers which can be generated by the transmission PNG within the preselected time interval and to simultaneously advance the transmission reference clock by the preselected time interval. By thus advancing both the PNG and the transmission reference clock through one complete cycle synchronism is achieved as the PNG is reset to zero during the cycle when the clock passes 2*^00 hours, say, and the clock and the PKG then continue to the end of the cycle when the transmission reference clock will return to the correct time with synchronism maintained. The invention also provides a clock modem receiver for deriving the "time from a transmitted series of time coded signals represented by a train of pseudo-random numbers comprising: a receiver pseudo random number generator (PKG) capable of producing an output train of pseudo-random numbers identical with the transmitted train of pseudo-random numbers; a clocking pulse generator connected to the receiver PNG such that the receiver PNG is clocked at the same rate as the transmitted signal; • a detector to ' receive the transmitted train of pseudo-random numbers; a synchronising control circuit to synchronise the receiver FKG to the received train of pseudo-random numbers; and decoding means to derive the time from the output of the receiver PNG. Preferably the receiver includes a receiver reference clock, and a detector responsive to the number generated by the receiver PKG representative of the end of the preselected time interval to produce an output signal to reset the receiver reference clock. Advantageously the transmitter and receiver PNGs comprise shift registers having at least one feed-back loop. The synchronising control circuit then includes means to feed the received time-coded pseudo-random numbers signal into the receiver PNG shift register and switching means operable between a first position in which the feedback loop is disconnected while the received pseudo-random numbers signal is fed into the receiver PNG shift register, and a second position in which the received signal is disconnected from the receiver PNG shift register and the feedback loop is connected. Thus if the received signal is error free and identical to the transmitted signal, once the receiver PNG feedback loop is reconnected the receiver PNG output will be synchronised with the received pseudo-random numbers signal. It is necessary to k , receiver reference clock with reference to the receiver FKG output so as to derive the time. As in the transmitter, there is preferably provided in the receiver a receiver pulse generator which is capable of being actuated to add to the receiver PKG a number of clocking pulses equal to the number of pseudo-random numbers which can be generated in the preselected time interval and to advance the receiver reference clock by the- preselected time interval to thereby synchronise the receiver PNG and the receiver reference clock. The received signal may however include bit errors which will result in. a false time registration once the acquired signal is stored in the shift register of the receiver PNG and the FKG started. The receiver therefore preferably includes comparator means to check the synchronisation of the output from the receiver FKG and the received pseudo-random numbers. The comparator means may include an error counter to count the proportion of bit errors, a discriminator to produce an output when the proportion of bit errors exceeds a predetermined threshold and a re-synchronisation control operative on receiving an output from the discriminator to reconnect the received signal to the receiver PKG shift register. In order to speed up the synchronisation checking it is possible to provide a high speed reciiculating shift register at the input of the receiver clock modem connected such that once the receiver PNG is switched on after acquisition of.a first block of received time-coded signal bits the next block of received time-coded signal bits can be stored and rapidly circulated together with output from the receiver PKG, such that the checking can be done off-line at high speed. An independent battery -operated clock may be advantageously included in the receiver clock modem so that absolute time and relative tire may be determined by respective reference to the battery clock and the transmitter clock-derived time. The provision of a battery-operated clock also gives the receiver clock modem an independence from the mains supply so that the clock mode can be transported without less of time information. The accuracy with which the receiver clock can record the time from the received coded time signal can be improved by providing a sub-bit time resolver. This is done by cross correlating the received time signal with the receiver PKG output and determining the time delay which gives the raa-xiπui-i cross-correlation. ϊhe invention v/ill now be described by vay of example only with reference to the accompanying drawings of which: Figures 1 and 2 illustrate the time-derived polynomial; .Figure 3 is a schematic block diagram of a transmitter clock modem using the polynomial; Figure is a block diagram of a receiver clock modem for use wit the.transmitter clock modem of Figure 3; Figure 5 is a schematic block diagram of a ING synchronisation circuit for use in the receiver clock modem of Figure ■* +; • Figure 6 is a flow chart of one arrangement of a receiver FKG automatic synchronisation control circuit; Figure 7 s a schematic block diagram of a B ~ G synchronisation circuit alternative to that shown in Figure 5; Figure δ is a block diagram of a sub-bit time resolver for use with, the receiver clock modem and Figure 9 is a battery clock incorporated in the receiver clock modem. The time clock modeal comprises a transmitter clock modem which includes an internal 2- - our reference clock to provide timing pulses to uniqely time-synchronise a pseudo-random binary data signal from a transmitter pseudo-random number generator (JENG). The time-coded data signal is then transmitted for reception by a receiver clock modem which decodes the received coded signal in real time to find the time of day. If a resolution of 5 milliseconds (+ -> bit) is to be achieved the bit rate of the data signal will have to be 100 bauds. The length of a -hour polynomial or pseudo-random number sequence required to produce this time resolution v/ill therefore be 8,6*40,000 bits long and this sequence will uniquely.define a 24- our clock. Figures 1 and 2 show how the polynomial sequence can be used to represent time. The pseudo-random number sequence 1 is produced at intervals of 10 msec by means of a EΪG chosen to have a polynomial length greater than 8.64 x, 10 . HIG'ε operate cyclically having a maximum number, equal to the *^ polynomial length, of different pseudo-random numbers which can be ,rf sequentially generated before those numbers are cyclically repeated, ~~ Thus to uniquely represent the time of day the time taken to generate ϋ DC this aaxiaum number must exceed 24 hours. Once every 24 hours, at C» Q midnight for example, the FNG is then reset to zero by means of a 3j reset pulse 2 from the internal reference clock so that the sequence of pseudo-random numbers generated during a 24-hour period is repeated β each number will then uniquely represent the time of day. The ETG comprises a 25-stage shift register, wit a single modulo-two feedback network taken from the 25rd stage. This provides the required polynomial length for the HTG such that the time 3 i then uniquely specified by a particular sequence of 25 bits immediately preceeding that time. Figure 3 shows diagra matically how the transmitter clock modem operates. A 24 - hour clock 4 is driven from a 5*-∑H. reference source connected to input 5- A first output 6 from the 24-hour clock 4 is connected to a liquid-crystal display (LCD) 7 which is used to monitor the 24-hour clock time so that it can be set up using the manual load time facility 8. A I Bs reference signal is provided at a second output 9 for the purpose of assisting in setting the clock. A third output 10 from the 24-hour clock 4 is used to provide the reset pulse 2 to reset the transmitter HTG 11. the 24-hour clock 4 registers 2400 hours the detector 12 produces a reset pulse v/hich is connected to the transmitter HTG 11. A fourth output 13 from the 24-hour clock 4 is connected to a clocking input 14 of the transaitter HTG 11. The clocking rate is such that a pseudo-random data sequence at 100 bits per sec is provided at the output 15 of the transaitter ETG 11. The length of this psenάo- random sequence is 8.64 x 10 bits since the transmitter HTG is reset every 24 hours and then the sequence repeats. The transmitter HTG output 15 is connected to a Frequency Shift Keying (FSK)modulator 16 which has a 1KH reference signal applied to an input 17. The FSK modulator 16 produces a 1 KΞ z sub-carrier modulated ' signal having a deviation ratio of approximately 0.3 at the output lδ of the transmitter clock modem. Once the 24-hour clock 4 is set to the correct time the transmitter HTG 11 can be synchronised with the 24-hour clock 4 by advancing the 24-hour clock 4 and the transmitter HTG 11 at high speed through settings corresponding to a period of time equivalent to exactly 24 hours by applying to the 24-hour clock 4 and the transaitter HTG 11 a train of 8.64 x 10 pulses. A clock pulse generator 19 is connected to the drive inputs 20 and 21 of the clock and the transmitter HTG respect¬ ively and is so arranged that on depressing a HTG synchronisation button 22 a train of 8.64 x 10 pulses is generated at a frequency of 500 KHz. This synchronisation, operation therefore takes about 18 sees. BAD ORIGINAL # Figure h shows diagraamatically the configuration of a receiver clock noden which is required to acquire polynominal synchronisation wit the inconing FSK pseudo-random data and then to derive the correct tine of day. The received signal at the input 23 of the receiver clock modem is applied to a 1 KHz FSK demodulator 23. The demodulated signal is then connected to the input of a HϊG automatic synchronisation detector 25 which is connected to a receiver HTG 26. The automatic synchronisation detector 25 and the receiver HTG 6 are connected together in a feed¬ back loop such that the receiver BIG 26 is brought into synchronism '.with the incoming pseudo-random data. Since the incoming data can be. degraded by one or more bit errors it is necessary to check whether the synchronisation of the receiver HTG 26 has been done correctly. The checking procedure is described below. Once the checking procedure shows that the receiver HTG 26 has been correctly synchronised, the automatic synchronisation detector 25 produces a signal at an output 27 which initiates a high speed full cycle 2-+-hour clock rotation similar to that carried out in synchronising the transmitter clock modem. The output 27 from the automatic synchronisation detector 25 is connected to a clock pulse generator 28 which, on receiving a signal indicating synchronisation, produces a train of 8.6- x 10 clock pulses. The train of clock pulses is connected to the receiver HTG 26 and to a 2-τ-hour clock 29 v/hich is driven by a πΞa reference signal applied to an input 30- The output 3 from the receiver HϊG 26 is connected to a detector 32 v/hich produces a reset pulse for the 24-hour clock 29 whenever it detects the pseudo-random number v/hich is at the end of the EϊG sequence. The train of pulses from the clock pulse generator 28 therefore rapidly cycles the receiver HϊG 26 and the 2 z J*-hour clock 29 through the equivalent of Zh hours and when the 2*400 hour point is reached in the EG cycle the reset pulse resets the clock 29. Bot the receiver 31G 26 and the 2 -hour-clock 29 continue to run at high speed until the 2-+-hour cycle is complete when the receiver HϊG v/ill dice again be in synchronism wit the incoming polynomial and the 2*÷-hour clock v/ill then display the correct time to within + , 5 πillisecs (being bit synchronised to within + • bit). PJO. output 33 from the 2 < +-ho r clock 29 provides a 100 Ez clocking signal for the HTG 26. BAD ORIGINAL δ S nchronisation of the receiver E*G 26 wit the incoming pscudo-random da a is achieved by means of a circuit shown schematically in Figures 5 and 6. As in the transmitter clock, the HG 26 in the receiver comprises a 25-stage shift register 3-'÷ wit a single modulo-two feed- 5 back netv/ork 35 talcen from the 23-cd stage ~ G to produce the δ.β** x 10 bit maximal length polynomial sequence. The pseudo-random numbers signal froπ the output 37 of the FSK deπodulator 2*-f- enters the receiver BIG shift register 3*÷ v/hen an input selector switch 3 is connected to the "Fill" position 39 as shown. She input switch ~ τS 0 remains in the "Fill" position 39 for a sufficient tiae until at least twenty-five input data bits have entered the shift register ~~ k. The switch 38 s then connected to position kθ which closes a. feedback loop -τ-1 around the shift register k to complete the HTG circuit and simultaneously disconnects the input data signal from the shift register. She shift register h vath the connected feedback loop hi thus fo-m the receiver HTG 26 producing an isolated pseudo-random data sequence which can be compared with the input data signal to check that the synchronisation has been correctly achieved. If the fill of data into the shift register 3*÷ were free from errors the ° random data sequence from the receiver HTG 26 would be indentical with the transmitted signal. If the "Fill" of data into the shift register 3*÷ is incorrect and/or the subsequently received input -signal, is corrupted by errors then bit errors will be seen when comparing the output from the receiver HTG with the received signal. 5 These bit errors are counted by connecting the received signal to a first input k ' > of a modulo-two circuit K≥ with the output from the receiver HTG 26 connected to a second input -V. Whenever a bit error is present a signal is produced at the output of the modulo-two circuit *2. The number of bit errors is then counted by a counter 5 0 and when the bit error rate (SHE) exceeds a preselected threshold an output signal is applied to a re-cycle synchronisation control circuit 4*6 hich reverses the position of switch 3*3 to allow a nev; "Fill" of input data into the shift register 3*÷« This process is repeated as necessary until the BER indicates that an error-free "Fill" has been _5 obtained. BAD ORIGINAL If the input signal bit error rate is high during a "Fill" the proba¬ bility of correctly filling the shift register >'+ becomes very small but it is still statistically possible. When it does occur the bit errors detected between the receiver ϊNG 2δ and the input signal v/ill be high after the "Fill" because the input signal is still erroneous. iihen this happens the error rate measured betv/een these tv:o signals will correspond with the HEIR of the input data signal. If the "Fil-l" was incorrect the error rate measured between the HG sequence and the input signal vill always be -1* because both sequences are statistically uncorrelated. She error rate measured after a "Fill can therefore be used to indicate the su-ccεs≤ of the "Fill" operation. ΞϊG synchronisation can be detected because an error rate of ~ - will always bo produced if the "Fill" was incorrect and an error rate of less than ~ Vm% will be produced when the "Fill" is correct. A simple " bit error counter, is therefore all that is required to indicate if synchronisation has been accomplished between the receiver BUG 26 and the input signal. This is illustrated in the Figure 5 arrangement where the error counter k$ is coupled to a re-synchronisation control circuit *τ6. theoretically the threshold of the re-synchronisation control circuit 6 can be set to just below 50o ESS because the error rate v/ill always be ~ 0 if the 'Fill" is incorrect. However, a threshold as high as this is impracticable because a very long measure¬ ment period vill be required to ensure a neaninful reading of BΞB is taken. If this were not done an incorrect -Fill" might be accepted (as being correct) because the HSR measured could be lower than the actual figure. Shis is due to normal statistical averaging properties and is related to sampling error theory. If this happens the HiG v/ill be unsjTichronised and the time of day vill be erroneously decoded. If the error threshold is lowered, the time taken to measure the bit error BAD ORIGINAL β OV:PI rate can be reduced to a more acceptable figure without increasing the probability of a false synchronisation but the receiver HΪG 26 vill only be allowed to synchronise on input signals having error rates less than this threshold level because the re-synchronisation control circuit 46 v/ill continue to instruct a re-fill even v/hen the '-Fill" is correct as long as the input SER is above this threshold. A compromise betv;een these two extremes can be made to ensure that the receiver HΪG 26 v/ill correctly synchronise in response to an input signal v/ith a reasonably high BΞR and yet the probability of a false synchronisation occurring vill be very Email. This compromise is-illustrated in Figure 6. An error rate threshold of 80 in a block of 224 was used because this offered a working noise margin of 3&J input BEE v/ith a probability of a false synchronisation occuring only once in 10 attempts. Once the input data "Fill" into the receiver HTG 26 is complete (in this case 32 input bits) the next 22**+ input data bits (checking bits) at the input 47 of a comparator ko are compared to the simultaneous 22k output bits at the output 49 from the receiver HTG 6 * The comparator 43 also counts the number of errors detected and in circuit 50 the total is compared vith a preset number, δθ in this case. If the total is less than 80 this indicates correct synchronisation and a signal is produced at the output 27 to advance the 24-hour clock 29 and the receiver HTG 26 by one complete cycle and thereby set the clock to the correct time of day. If the total number of errors counted by the comparator 48 is greater than 80 indicating incorrect synchronisation a signal to initiate refilling of the receiver HTG 26 is produced by a circuit 51 v/hich prompts a control circuit 52 to fill the receiver HTG 26 with, the ne∑t 32 signal input bits. This procedure is then repeated until correct synchronisation is achieved. Figure 7 shov/s how the basic auto-synchronisation control circuit of Figures 5 a^-d 6 can be modified to speed up the synchronisation procedure. This is done by storing the 224 "Fill" checking bits in a high-speed recirculating shift register 53 connected between the data input from the output 37 of the FSK demodulator 24 and the receiver HTG 26. BAD ORIGINAL J> The error rate measurement taken after the "Fill" can nov/ be done off ¬ line at high speed. In this way the synchronisation check can be done well within one bit period, eg less than 10 milliseconds. If the check is satisfactory the date input and the HTG output will be in bit synchronisation and the circuit operates as before. If it is incorrect the refill and check is done again. In this way the •Fill" and synchronisation checking can be reduced from 2.56 seconds to less than 0.25 seconds. The accuracy of the receiver clock mode will always be better tha-n + 5 milliseconds because the maximum error between the receiver HTG and the input data signal can only be - bit after synchronisation. Bit synchronisation in the receiver can be improved to ensure that the time error is normally within _+ 1 millisecond provided the input signal to noise ratio is better than 0 dB in a 3 kHz bandv/idth. This is done by adjusting the phase of the receiver HTG output signal to align with the input data signal. This phasing technique could be made to operate vith far higher noise levels but to do so would require much longer averaging periods for filtering and phase locking. This is impracticable because fast initial phase locking followed by a rapid synchronisation of the HΪG is necessary if the modem is to properly operate over fading and noisy channels. Figure 8 shov/s an alternative approach v/hich vill provide sub-bit timing resolution without jeopardising speed of acquisition. This is done by croεs- correlating the input signal with the output from the receiver HΪG after completing synchronisation,. Noise and distortion on the input data signal are minimised by integrating over several seconds. Ten cross-correlation integral values are measured over a 10 millisecond range (+i it)« From this the relative delay between the input data signal and the receiver HTG signal can be found. The accuracy with v/hich this delsy can be measured v/ill depend upon the input signal to noise ratio and the integration time of the cross-correlation process. V/ith an integration time of 1 second, it can be shown that the input signal to noise ratio will have to be - 4 dB(in 3 kHz BW)or better for the timing error to be within 100 ^1 seconds for 0o of the time. BAD ORIGINAL & 6 It can be similarly shov.*n th-at, for the modem to operate down to -3 d3 carrier to noise and to still retain a timing acquisition accuracy of ICO microseconds or better the integration tine will have to be 10 seconds or more. Shis presupposes a non-dispersive input data signal is used during the measurement period. The received input from the output 57 of the FSK demodulator Zk is provided as an input into a 10-stage 10 msec analogue delay line 5k which has a 1 kHz clocking signal applied to its clock input 55- Thus the time interval between successive stages is 1msec and the total delay is 10 msec. The 10 msec delay is chosen since this is equal to the time interval between successive bits of the signal data. The cseudo random data output k9 from the receiver EIG 26 will normally be de- lεyea on the input signal by -J bit (5 msec.) This delayed output from the receiver H1G Zβ is connected in parallel to the first inputs 57-5S of ten multipliers 59-60 of v/hich only two are shown for clarity. Ten tap outputs 65- from the delay line 3k are respectively connected to the second inputs 61-62 of the multipliers. The .product outputs from the multipliers 59-69 ' are respectively applied to integrators 6 -66 with their integration times set to a least 1 sec. The outputs from the integrators 63- 6 are respectively connectεd to the taps 67-68 of a 10-stage delay line multiplexer 69 which has a 1 kHz clocking signal applied to its clock input 70. The output 71 is passed through a 100 Hz low pass filter 72 so as to form the envelope of the time-averaged cross-correlation products as indicated by the curve 73• E e output from the filter 72 is connected to a peak detector time resolver circuit k which is clocked by the 100 Ez clocking signal from the output 35 of the 24-hour dock 29. The time resolver 7 makes a measurement of the peak signal output from the filter 72 in each 10 msec period and then determines the time difference between the data clock pulses and the peak signals 75 measured from the curve 73« T-fce output 76 from the time resolver circuit 7*÷ is an analogue signal which represents the time error with within, the range - 5 msec to an accurancy of +_ 100ytisecs. Included in the receiver clock mode is a battery operated clock illustrated in Figure 9- The battery clock is a 24-hour clock 77 provided with an LCD isplay 78 powered from the mains 79 by a power BAD ORIGINAL 15 supply 8θ. The power supply 80 includes an 18 amp hour rechargeable battery which provides the battery clock with power for up to 7 days. The 24-hour clock 77 is controlled by a 5 l-Hz crystal oscillator 81 or it may be connected to an alternative reference source such as a caesium source via a- terminal 82. The time of the 24-hour clock 77 s set by means of a Load Time input 83 and a 1 Hz output reference signa is provided .at an output 84 for the purpose of checking the timing of the battery clock. Provision of a battery clock confers two advantages. Firstly, it is possible to transport the equipment with- out any external power supply requirement and secondly it can be desirable to have two independent clocks within the receiver clock modem to provide both absolute and relative time: the battery clock provides absolute time whilst the transmit clock will provide relative time. The performance of the modem will ultimately depend on the remote programming facility of the receiver code generator and in particular the ability to achieve only correct synchronisation with the input polynomial when operating in the presence of noise or interference. This is of critical importance when synchronisation of the receiver clock Prø is to be done over HF radio circuits so emphasis has been placed on protecting the PW3 from achieving incorrect synchronisation by incorporating rigorous safeguards in the synchronisation detection circuits as described. The performance of the modem can therefore be quantified in two ways. a. the time taken to achieve correct synchronisation; and b. the probability of getting a false synchronisation. The time taken to get correct synchronisation will depend on the input EΞR and the length of the receiver PNΞ shift register. The higher the ' input BEB the longer it will take to get synchronisation because the probability of getting 25 or more correct input data bits to fill the PN3 shift register becomes less likely. The time taken to become synchronised is therefore directly proportional to the number of receiver Pϊv3* •• Fills" required to guarantee having received at least one (all-correct) 25-bit "1111". BAD ORIGINAL The time talcen to acquire synchronisation of the receiver PKG 26 is directly proportional to the number of "Fills" made and as the time taken to fill the FNΞ and check synchronisation is 2.5osecs (256 bits at 100 bits/sec) the synchronisation time is 2.56 n sees where n is the number of "Fills to acquire synchronisation when adopting the basic automatic synchronisation shown in Figure 5 and 6. By setting the error threshold to 8θ bits in 224 the probability of obtaining a false synchronisation can be shown to be 1 in 10 attempts when the input signal is random noise. If the error threshold were set lower than this the protection against false synchronisation could be "improved but the probability of detecting correct synchronisation would be reduced-for erroneous input data with a higher BΞR. Similarly if the threshold level were increased, the probability of false synchronisation would be higher, but the receiver PK2 will now recognise correct synchronisation when it occurs even when the input signal bit error rate is much higher than before. A compromise . between these two situations was made based on a need to have adequate security against false synchronisation but still retaining the ability to detect synchronisation when the input data error rate is reasonably high. The invention provides a time code signal format having a narrow transmission bandwi&h and an ability to work with poor i put signal to noise ratios and yet retain good guarranteed timing accuracy. Such a system is required v/hen an HF skywave radio link is used to cope with facing, multipath and interference from other radio signals but it is also particularly useful for time encoding many other signal forms which have to be recorded before being used. The accuracy of the time clock modem can be improved firstly by introducing a sub-bit timing resolver as is shown in Figure 8. • This technique, however, requires long integration times and is unsuitable if fading or dispersion is present. Secondly, the accuracy can be improved by increasing the transmitted code bit rate. For a 1 kbi /sec code rate the maximum possible timing error can only be +_ -g- millisec. For higher rates the error is reduced proportionally. This method is only acceptable, however, when there are no restrictions limiting the transmitted bandwiifch. Although the invention has been described with reference to a simple form of PIG employing only one feedback loop in a 25-stage shift register more sophisticated PK-is could be used to > provide a higher degree of orthogonality between different parts of the HϊG polynomial sequence. The technique could be applied to a monthly or yearly pseudo-random sequence but in these cases the time to find synchronisation would be correspondingly increased 5 compared to a 24-hour polynomial. As an alternative to extending the pseudo-random number sequence the basic time interval can be extended by using time division * multiplexing of the transmitted signal so as to include additional information such as the day, month or year. Thus for example every 0 hundredth bit transmitted could convey this additional information. Since the receiver is capable of maintaining synchonis when the received signal is corrupted by noise the time division irltiplexing has no significant effect on the receiver's capability of aquiring the time signals. The receiver can then be provided with a synchronous detector to e-x-tract the additional information data bits, and after aquiring several such bits to carry out a simple majority vote to prevent noise corruption of the. information. The invention has been described with reference to FSK modulation of . 1 kHz reference frequency. FSK has the advantage that it can be sent via national radio transmitters without affecting the broad¬ casts. It is however possible to use amplitude modulation of a selected tone in a dedicated transmission. By using a single frequency, further information useful to the communications engineer can be extracted from the sub-bit time resolver. Information can be obtained on ultipath propagation by looking for the number of peaks in the output from the sub-bit time resolver. A microprocessor nay be included and the number of peaks resolved will then indicate the quality of the communications link eg if these are too many modes observed the link cannot operate successfully. Other modifications of the invention falling within the scope of the accompanying claims will be apparent to those skilled in the art. c:-:? SUBSTIT \. ;?

Claims: Claims 1. A transmission clock modem for transmitting time coded signals comprising: a transmission pseudo-random number generator (BIG) (11) to generate a train of pseudo-random numbers; a pulse generator means to produce clocking pulses (14) for connection to the transmission HTG such that the output numbers from the transmission B ' G are equi-spaced in time; resetting means (12) connected to the transmission H7G such that -fee transmission B G is reset to a predetermined condition, referred to as zero, after a preselected time interval; and means (16) to transmit the output from the transaission HTG. 2. A transmission clock modem as claimed in claim 1 wherein the re¬ setting means (12) comprises a transmission reference clock (4) which produces an output resetting signal at the end of each of the preselected time intervals. 3. A transmission clock modem as claimed in claim 2 wherein there is provided a transmitter pulse generator ' (19) which can be actuated to add to the transmission B ' G a number of clocking aises equal to the number of pseudo-random numbers which can be generated by the transmission HTG within the preselected time interval and to simultaneously advance the transmission reference clock by the preselected time interval to thereby synchronise the transmission BIG and the transmission reference clock. 4. A receiver dock modem for deriving the time within a preselected time interval from a series of time-coded signals represented by a train of pseudo-random numbers comprising: a receiver pseudo-random number generator (EG (2o) capable of producing an output train of pseudo-random numbers identical with the tranaπitted train of pseudo-random numbers; a receiver clocking pulse generator (33) connected to the receiver HTG such that the receiver HTG is clocked at the same rate as the transmitted signal; a detector (23) to receive the transmitted train of pseudo-random numbers; a synchronising control circuit (25) to synchronise the receiver HTG (26) to the received train of pseudo-random numbers; and decoding means to derive the time from the output of the receiver HTG. 5. A receiver clock modem as claimed i claim 4 wherein the decoding means includes a receiver reference clock (29) to display the derived time and a detector (32) connected to the receiver HΪG and responsive to the number generated by the receiver HTG representative of the end of the preselected time interval to produce an output signal to reset the receiver reference clock to zero. 6. A receiver clock mode as claims!in claim 5 wherein the receiver HϊG (26) comprises a shift register (3 ) having at least one feed-back loop, the synchronising control circuit including means -to feed the received time-coded pseudo-random numbers signal into the receiver HTG shift register and switching means (38) operable between a first position in which the feedback loop is discon¬ nected while the received signal is fed into the receiver HTG shift register and a second position in which the received signal is disconnected from the receiver HIG shift register and the feed-back loop is connected. 7. A receiver clock mode as claimed in claim 6 wherein there is provided a receiver pulse generator (28) which can be actuated to add to the receiver HTG (26) a number of clocking pulses equal to the number of pseudo-random numbers v/hich are transmitted within the preselected time interval and to simultaneously advance the receiver reference clock by the preselected time interval to thereby synchronise the receiver HTG and the receiver reference clock. 8. A receiver clock modem as claimed in any of claims 4 to 7 including comparator means to check the synchronisation of the output from the receiver HTG and the received pseudo-random numbers. 9. A receiver clock modem as claimed in claim 8 wherein ' the comparator means includes an error counter 4 ) to count the proportion of bit errors; a discriminator (50) to produce an output when the proportion of bit errors exceeds a predeterm¬ ined threshold; and a re-synchronising control (46) operative on receiving an output from the discriminator to reconnect the -received signal to the receiver HTG shift register. SUBSTITUTE SHEET ( --.ττ ' 10. A receiver clock modem as claimed in claim 4 including means to determine the phase difference betv/een the output signal from the receiver HTG and the received signal, said phase difference being used to correct the time derived from the synchronised output from the receiver HIG. 11. A receiver clock modem as claimed in claim 4 including a battery- operated clock (77).

Inventors: WILKINSON R
Applicants: UNITED KINGDOM GOVERNMENT, WILKINSON R
Application year: 1981
Main classification: G04G9
IPC codes: G04G7