LOGIC CIRCUIT

Abstract: Disclosed is a logic circuit integrated in an LSI, compris­ ing a first transistor (Q₂) with a Schottky barrier clamping diode, a first resistor (R₂) connected between the collector of the first transistor and a power supply line (Vcc), a second transistor (Q₃) with its base connected to the emitter of the first transistor (Q₂), and a pull-up resistor (R₄) connected between the collector of the second transistor (Q₃) and the power supply line (Vcc). In order to shorten the rise time of the output voltage, a diode (Q₅) is provided between the collectors of the first and the second transistors (Q₂, Q₃) to provide an additional path for current from the power supply line (Vcc) to the output terminal through the first resistor (R₂) and the diode (Q₅) when the second transistor (Q₃) changes from its ON state to its OFF state.

Description: LOGIC CIRCUIT The present invention relates to a logic circuit in which the rise time of the output signal is improved without significant penalty in power consumption. Before explaining the embodiments of the present invention, a conventional TTL (transistor-transistor logic) NAND circuit will first be explained with reference to Fig. 1. In Fig 1, a multiemitter npn transistor Q1 has a base connected through a resistor R1 to a power supply line Vcc, a collector connected to the base of the transistor Q1 and two emitters adapted to receive two input signals IN1 and IN2. The transistor Q1 and the resistor R1 constitute an AND circuit in which a logical product of the input signals IN1 and IN2 is obtained at the collector of the transistor Q1. The collector of the transistor Q1 is connected to the base of an npn transistor Q2 which has a collector connected through a resistor R2 to the power supply line Vcc and an emitter connected through a resistor R3 to a ground line GND. The emitter of the transistor Q2 is connected to the base of a transistor Q3 which has a collector connected through a pull-up resistor R4 to the power supply line Vcc and an emitter connected to the ground line GND. Clamping diodes Q4 are connected in series between the collector and the emitter of the transistor Q3. The clamping diodes Q4 may be replaced by a resistor. The transistor Q2 receives at its base a collector voltage from the transistor Q1 and shifts the voltage to provide the shifted voltage to the base of the transistor Q3. The transistor Q3 inverts and amplifies the voltage received at its base to provide an output voltage at its collector connected to an output terminal. The resistor R3 connected between the base of the transistor Q3 and the ground line GND acts as a pull-down circut for drawing charges at the base of the transistor Q3 when the transistor Q3 has been turned off. The resistor R3 may be replaced by another pull-down circuit, for example, an active pull-down circuit. It should be noted that the transistors Q2 and O3 are Schottky barrier transistors for preventing their excessive saturation. The operation of the circuit of Fig. 1 is well known in the art. Briefly explaining, when both of the input signals are at a high reference potential level (hereinafter referred to as an "H level"), the transistor Q1 is in a cut-off state so that a current is supplied from the power supply line Vcc through the resistor R1 to the base of the transistor Q2 to turn it on. Because the transistor Q2 is an emitter follower, the transistor Q3 is then turned on so that the output voltage of the terminal OUT becomes a low reference potential level (hereinafter referred to as an "L level"). When at least one of the input signals IN1 and IN2 is at the L level, the current flowing through the resistor R1 flows through the base and the emitter of the transistor Q1 so that no base current is supplied to the base of the transistor Q2. Thus, the transistors Q2 and Q3 are turned off. At this state, the pull-up resistor R4 pulls the potential at the output terminal to the power supply voltage Vcc. The clamping diodes Q4 determine the uppermost level of the H level. The disadvantages of the conventional circuit of Fig. 1 will now be described. During the transition from the ON state to the OFF state of the transistor Q3 , the charging of a capacitance Ct of a wiring line or an input of a next stage transistor (not shown) connected to the output terminal OUT should be effected, when the potential at the output terminal OUT rises from the L level to the H level. Therefore, the rising speed of the potential at the output terminal OUT is determined by the capacity to charge the capacitance Ct The capacitance CL may have various values depending on the circuits connected to the output terminal. The rising speed of the potential at the output terminal OUT should ideally be unaffected by the capacitance CL. One means considered to increase the capacity tor charging the capacitance CL , is to reduce the time constant derived from the pull-up resistor R4 and the capacitance CL by decreasing the value of the resistor R4. However, if the value of the resistor R4 is decreased, the current Il which flows through the resistor R4 will be increased. As current ordinarily flows through the resistor, the increased current I1 causes an increase in the power consumption. As another means to increase the capacity for charging the capacitance CL , an active circuit, for example, a Darlington circuit may be connected between the collectors of the transistors Q2 and Q3. However, such an active circuit makes it impossible to operate the logic circuit at a low voltage of, for example, 2V, such a low voltage being used in recent LSI's (large scale integrated circuits). SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a logic circuit in which the rate of rise of the output signal is improved without increasing the power consumption. significantly. Another object of the present invention is to provide a logic circuit integrated in an LSI, in which the rate of rise of the output signal of the logic circuit is improved without increasing the operating voltage. In order to achieve the above objects, there is provided, according to the present invention, a logic circuit comprising: a first transistor with a Schottkybarrier clamping diode, having a base adapted to receive an output voltage of a prestage logic gate, a collector, and an emitter for providing a voltage shifted from the output voltage of the prestage gate; a first resistor connected between the collector of the first transistor and a power supply line; a second transistor having a base connected to the emitter of the first transistor, a collector connected to an output terminal, and an emitter connected to a ground line; and a pull-up resistor connected between the collector of the second transistor and the power supply line, for pulling up the potential at the collector of the second transistor; whereby current flows from the power supply line to the output terminal along a path through the pull-up resistor; and characterized by an additional diode having an anode connected to the collector of the first transistor and a cathode connected to the collector of the second transistor, whereby an additional current path is provided for temporarily allowing current flow from the power supply line through the first resistor and the diode to the output terminal during a transition from an ON state to an OFF state of the second transistor. The foregoing objects and other features of the present invention will be more apparent from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which: Fig. 1 is a circuit diagram illustrating -a conventional logic circuit; Fig. 2 is a circuit diagram illustrating a logic circuit according to an embodiment of the present invention; Fig. 3 is a graph illustrating the relation between the output voltage and the pull-up current in the circuit of Fig. 2; and Fig. 4 is a circuit diagram illustrating a logic circuit according to another embodiment of the present invention. Fig. 2 is a circuit diagram illustrating a logic circuit according to an embodiment of the present invention. The difference between the circuit of Fig. 1 and the circuit of Fig. 2 is that, in Fig. 2, a diode Q5 is provided between the collectors of the transistors Q2 and Q3. The anode of the diode Q5 is connected to the collector of the transistor The The cathode of the diode Q5 is connected to the collector of the transistor Q3. The other portions are the same as the portions of the circuit of Fig. 1 and are designated by the same reference characters. Therefore, the constitution of the circuit of Fig. 2 is not described here. The operation of the circuit of Fig. 2 will be described with reference to Fig. 3. By providing the diode in in the polarity illustrated in Fig. 2, an additional current I2 flows from the power supply line Vcc through the resistor R2 and the diode Q5 to the output terminal OUT, during the transition from the ON state to the OFF state of the transistor Q3. Thus, because the pull-up current flowing through a node N connected to the collector of the transistor Q3 and the output terminal OUT is I1 + I2 greater than the pull-up current I1 in Fig. 1 as illustrated in Fig. 3, the rise time of the output signal from the L level to the H level is shortened in comparison with the rise time in the circuit of Fig. 1. Further, bec-ause the diode Q5 is not always turned on, the current I2 flows only temporarily. More precisely, the diode Q5 is so designed as to satisfy the expression: Vcc - VBE Q5 < V H where Vcc represents the voltage of the power supply line Vcc, VBE Q represents the forward voltage of the diode VBE , and V represents the H level potential at the output H terminal OUT determined by the diodes Q4. When the diode satisfies the above expression, the additional current 12 flows only when the output voltage rises from the L level potential VL to (Vcc - VBE Q5) After the output potential at the output terminal OUT exceeds the value Vcc - VBE Il only the pull-up circuit I1 flowing through the resistor R4 flows through the clamping diodes Q4. As a result, the rise time tpLH , which is the transient time required for the transition from the L level to the H level of the output signal, is decreased in comparison with the conventional circuit of Fig. 1, while the power consumption is substantially the same in both circuits of Figs. 1 and 2. Because the rise time t PLH is decreased, the dependency of the rise time tpLH to the capacitance CL , i.e., AtPLH /AC , in the 'S circuit of Fig. 2, is also decreased in comparison with the circuit of Fig. 1. During the fall time of the transition from the H level to the L level, the additional current 12 does not flow. This is because, when both of the input signals IN1 and IN2 are changed to the H level, the transistor Q1 is turned off so that the base potential of the transistor Q2 is increased to cause the transistor Q2 to be turned on. Accordingly, the potential at the anode of the diode Q5 is lowered to turn off the diode Q The emitter current of the transistor O2 is supplied to the base of the transistor Q3 to turn on the transistor Q3. Thus the potential at the output terminal OUT falls to the L level. Because the diode Q5 is in the cut-off state, the current flowing through the transistor Q3 is only the current I1 flowing through the pull-up resistor R4 and the current supplied from the output terminal OUT. As a result, the falling speed of the output signal is not decreased in comparison with the conventional circuit of Fig. 1. Further, it is possible to design the values of the resistors R2 and R4 to be smaller and larger, respectively, in comparison with those in the circuit of Fig. 1, while the power consumptions in both circuits are designed to be the same. By decreasing the value of the resistor R2 t the base current of the transistor Q3 is increased. Also, by increasing the value of the resistor R4 , the load of the transistor Q3 is decreased. As a result of the increased base current and the decreased load, the fall characteristic of the output signal is also improved. Although both of the transistors Q2 and Q3 are Schottky barrier transistors in the circuit of Fig. 2, the Schottky barrier clamping diode can be eliminated in the transistor Q3 when the transistor Q3 does not have a Schottky barrier clamping diode, the saturation voltage of the transistor Q3 is VBEQ3 + VCESATQ2 - VBEQ5 t where VBEQ3 represents the base-emitter voltage of the transistor Q3 , VCESATQ2 represents the saturation voltage between the collector and the emitter of the transistor Q2 , and V represents the BEQ5 forward voltage of the diode Q5. Since VBEQ is nearly equal to VBEQ , the saturation voltage of t transistor Q3 is nearly equal to VCESATQ2 This value VCESATQ2 is substantially equal to VCESATQ , which is the saturation voltage of the transistor Q3 wssen the transistor Q3 has the Schottky barrier clamping diode. Accordingly, even when the transistor Q3 does not have the Schottky barrier clamping diode, the transistor Q3 is also prevented from being excessively saturated; and the effect of the present invention, that is, the rapid fall of the output signal without increasing the power consumption by conducting the current I2 through the diode Q5 only when the output voltage rises from the L level to Vcc - VBEQ , can be obtained. If the transistor 2 does not have/Schottky barrier clamping diode, the additional current I2 will not be effectively obtained, because, in this case, the transistor Q2 is excessively saturated when its base potential is at the H level, and therefore, the rise of its collector potential is delayed even after its base potential has fallen and the transistor Q3 has begun to turn off so that the diode Q5 will not be turned on. The potential at the collector of the transistor Q2 x i.e., the anode of the diode Q5 , rises to the H level only after minority carriers on the base of the transistor Q2 have been discharged. Therefore, in order to obtain the effects of the present invention, at least the transistor Q2 should have a Schottky barrier clamping diode. Fig. 4 is a circuit diagram illustrating a logic circuit, according to another embodiment of the present invention. The difference between the circuit of Fig. 2 and Fig. 4 is that, in Fig. 4, two input-stage pnp transistors Q1 and Qlb are employed in place of the npn multiemitter transistor Q1 in Fig. 2. The emitters of the transistors Qla and Qlb are commonly connected to the base of the transistor Q2. The collectors of the transistors Qla and Qlb are grounded. The bases of the transistors la and Qlb are adapted to receive the input signals IN1 and IN2 respectively. The rest of the circuit configuration is the same as that of Fig. 2. The circuit of Fig. 4 is a NAND circuit. The effect of rapid fall of the output signal without increasing the power consumption can also be obtained by the circuit of Fig 4, as will easily be understood by those skilled in the art. From the foregoing description, it will be understood that, according to the present invention, a logic circuit can be obtained in which the rising speed of the output signal is improved without increasing the power consumption and without increasing the operating voltage. The present invention is not restricted to the illustrated embodiments, but various changes and modifications, for example, various logics are possible without departing from the spirit of the invention.

Claims: CLAIMS 1. A logic circuit comprising: a first transistor (Q2) with aESchottky barrier clamping-diode, having a base adapted two receive an output voltage of a pre-stage logic gate, a collector, and an emitter for-providing a voltage shifted from the output voltage- of the pre-stage gate; a first resistor (R2) connected-between the collector of the first transistor and a power supply line (Vcc); a second transistor (Q3) having a base connected to the emitter of the first transistor, a collector connected to an output terminal, and an emitter connected to a ground line; and a pull-up resistor (R4) connected between the collector of the second transistor and the power supply line, for pulling up the potential at the collector of the second transistor (Q3), whereby current flows from the power supply line to the output terminal along a path through the pull-up resistor (R4); and characterized by an additional diode (Q5) having an anode connected to the collector of the first transistor (Q2) and a cathode connected to the collector of the second transistor whereby an additional current path is provided for temporarily allowing current flow from the power supply line through the first resistor (R2) and the diode (Q5) to the output terminal during a transition from an ON state to an OFF state of the second transistor (Q3). 2. A logic circuit as set forth in claim 1, wherein the second transistor (Q3) comprises a Schottky barrier clamping diode. 3. A logic circuit as set forth in claim 1 or 2, wherein the additional diode (Q5) has a forward voltage VBE satisfying the expression: Vcc where Vcc represents the voltage of the power supply line; and VH represents the high reference potential at the output terminal. 4. A logic circuit as set forth in claim 3, comprising a clamping circuit connected between the output terminal and the ground line, for determining the value V N

Inventors: TANIZAWA, TETSU
Applicants: FUJITSU LIMITED
Application year: 1981
Main classification: H03K19
IPC codes: H03K19