APPARATUS FOR THE DISPLAY AND STORAGE OF TELEVISION PICTURE INFORMATION BY USING A MEMORY ACCESSIBLE FROM A COMPUTER

Abstract: An apparatus for the display and storage of television picture information by using a memory accessible from a computer in which the memory comprises dynamic RAM memory elements arranged in memory blocks being accessed in repetitive cycles. The address inputs of the memory elements are controlled by an address generator through an address modifying circuit and an address switching unit. The address modifying circuit modifies the picture addresses provided by the address generator corresponding to the internal address requirements of the memory blocks. The address switching unit is connected both to predetermined address lines of the address generator and to address lines of an interface providing connection towards the computer. The data bus of the memory is coupled to a data switching unit having outputs coupled to a parallel to series converter and to the multiplexer of the interface. The control of the data and address switching units is carried out by the least significant horizontal address bits. Owing to the specific kind of control a part of the memory blocks is always connected to the computer and an other part to the display unit, and these connections are cyclically interchanged. This control provides for the continuous refreshment of the dynamic RAM memories, and the apparatus will be in a quasi-continuous connection both with the display and the computer.

Description: - / APPARATUS FOR THE DISPLAY AND STORAGE OF TELEVISION PICTURE INFORMATION BY USING A MEMORY ACCESSIBLE FROM A COMPUTER Technical Field The invention relates to an apparatus for the display and storage of television picture information by using a memory accessible from a computer. The apparatus according to the invention can widely be used in the field of computer technics in the form of a graphic display. Background Art The wide range of applications of graphic displays might be the result of the appropriate interconnections of television monitors and computers offered by recent technical progress. There are al¬ ready a large number of computer controlled graphic displays which are commercially available. A common feature of such displays lies in that they all have a central clock that controls an address generator to provide horizontal and vertical picture and memory addresses, and the address gene¬ rator is coupled to a synchronizing unit. The. connection towards the computer is established through an interface forming part of the display, and the computer has appropriate access periods in which it can communicate with the random access memory add¬ ressed by the address generator and controlled by a memory control unit. A digital to analog converter is coupled to the data bus of the memory and the out- OMPI put of the D/A converter provides the standard video signal ' s required for a conventional standard black and white or color television monitor. In the known apparatuses of the above kind the computer access is provided during the line returning or picture returning periods.. Since the repetition period of the lines is 64 ,us, the computer accesses established during line returning periods are limited in time. If the computer has limited access time to the memory, the rate of information refreshment or the amount of information that can be read out from the memory in a unity time will be reduced. For increasing the speed of operation the storage capacity can be increased which, however, is connected with high costs. A substantial part of the prices of such apparatuses is the price of the memory elements used therein, therefore the reduction of the number of memory ' elements is of high importance<, A virtual increase in memory demand in conven¬ tional display systems is created by the circumstance that the picture dissolution' provided by the tele¬ vision technique can be covered generally by a re¬ dundant amount of storage capacity only due to in— effective memory allocation possibilities. This means that the storage capacity of the required number of memory elements is utilized in part only which is associated with decreased storage efficiency. Of the various types of random access memories the dynamic RAM memories are considered to be the most favourable when the storage capacity pro unity cost quotient is regarded. For the operation of such dynamic memories it is required that within as ' short time periods as about 2 s all addresses of the me-. mory should be accessed. With memory addresses corresponding to the vertical and horizontal scanning movement of the electron- beam of the monitor the above condition cannot be satisfied easily. The usage of certain kinds of address modification have al¬ ready been proposed in connection with the application of random access memories, however, in such cases the modified addresses have been less easy to be handled and inspected than the horizontal and vertical add¬ resses corresponding to the movement of the scanning electron beam which are visual and easy to work with. Object of the Invention The object of the invention is to provide an apparatus for the display and storage of television picture information that comprises a m-emory accessible for a computer in which the efficiency of memory utilization is better than in conventional systems, the memory . access time for the computer is substan- tially shorter than the duration of a television line, whereby the rate of information streaming to and from the computer is high i.e. the time of complete trans¬ cription of a picture is short, and which enables the usage of cost-saving dynamic RAM memories. Disclosure of Invention According to the invention an apparatus has been provided for the display and storage of television picture information by using a memory accessible for a computer which comprises a central clock generator, an address generator providing horizontal and vertical picture addresses and coupled to the address generator, a synchron unit for generating line and picture - A- syπchron signals, an interface for providing connection towards the computer, a random access me¬ mory addressed by the address generator, a memory control unit, a digital to analog converter coupled to the data bus of the memory for providing video signals, in which the improvement lies in that the memory consists of dynamic random access memory ele¬ ments having address inputs controlled through an address modifying circuit, the inputs of the address modifying circuit are coupled to the output of an address switching unit, the address switching unit comprises a first input group connected to predetermin¬ ed address lines of the address bus of the address ge¬ nerator and a second input group connected to prede- termined address lines of the interface, the data bus of the memory is connected to the input of a data switching unit comprising a first output group connect¬ ed to parallel inputs of a p_rallel-to-series converter preferably a shift register and a second output group coupled to multiplex inputs of a multiplexer, the out¬ put of the multiplexer is connected to the data line of the interface, the control inputs of the address switching unit and of the data switching unit being connected to a horizontal address line of the address bus associated with a horizontal address bit of low significance, the parallel to series converter is controlled by the address lines carrying the least significant horizontal address bits, and the digital input of the digital to analog converter is connected to the serial output of the parallel-to-sεries con¬ verter. In a preferable embodiment of the invention the data bus of the memory, the data switching unit, the parallel-to-series converter and the multiplexer OMPI as well as the busses interconnecting these units are designed to bidirectional data-transport and the series input of the parallel-to-serial converter ' is coupled to the digital output of an A/D converter. It is preferable if the following conditions are true for the address modifying circuit: = Y* Y .if Y, and 1 .- ■ X' 8 1 = X- 8 = Y- χ = v. if Y 9 = 1 • wherein the addresses X and Y represent the states of the corresponding horizontal and vertical bit lines of the address bus, and the addresses X' and Y* designate the states of the modified horizontal and vertical addresses present at the output of the add¬ ress modifying circuit. By using such modifications in the address system, the required, storage capacity will be reduced to nearly a half value. In accordance with the scanning with alternating half pictures it is preferable if each memory element of the memory is associated with a respective other memory element, and of the so obtained pairs of me¬ mory elements the first is validated by the condition Y • = 1 and the second by the condition Y - 0. The apparatus according to the invention satis¬ fies the objects, set forth hereinabove, since the me- mory is built up by dynamic RAM memory elements which are timely refreshed by the appropriate address alloc¬ ation. The memory is available for the computer in the half of its operational time, whereby the rate of information reading and writing operations are both high, and the average access time for the computer to reach the memory is typically about 1 ,us. At the same time the storage capacity is effect¬ ively utilized due to the .address ' modification carried out by the address modifying circuit. Brief Description of Drawings The invention will now be described in connect¬ ion with certain preferable embpdiments thereof, wherein reference will be made to the accompanying drawings.. In the drawing: Fig. 1 shows schematically the screen of the monitor for illustrating the horizontal and vertical dissolution, Fig. 2 is similar to Fig. 1 in which besides the vertical and horizontal margins of the picture area the most significant four address bits have also been indicated, Fig 0 3 shows schematically the memory required for covering the visible picture area. Fig, 4 is similar to Fig. 3 showing transformed memory regions, Fig c 5 shows the block diagram of the address modifying circuit implemented with a multiplexer, Fig. 6 shows the general block diagram of the invention, and Fig. 7 shows a preferable embodiment of the me¬ mory organization of the apparatus shown in Fig. 6» Modes for Carrying Out the Invention Fig. 1 shows the visible area of the screen of a television monitor. The problem to be solved lies in how this useful image area can be covered by an associated memory,, If the standard 4 : 3 picture size is to be maintained with nearly identical horizontal and vertical dissolution, then the possibility.offered OMH . * 1 U by the application of television technique will be best used if respective memory contents are associat¬ ed with each visible raster line i.e. if the vertical dissolution is equal to a raster line. During picture reversal the lines are not visible, therefore the number of visible raster lines is less than the complete number of raster lines in a picture. In case of using standard pictures ' with 625 lines, the efficiency of picture utilization will be fairly good if memory coverage is provided for e.g. 576 of the horizontal lines. Later it will be explained that the selection of that number is preferable also in view of several other aspects. With fixed 4 : 3 proportion between the horizon- tal and vertical dimensions of the picture, the hori¬ zontal dissolution will be 76S which is equal to the maximum number of vertical lines that can be display¬ ed on the screen. Indeed, with the ' selection of such number a proportion of 4 : 3 is provided, because the number of raster points in a line -is :768=12x64 and the number of raster points in a column is: 576= 9x64. If such a high dissolution is not required, then with substantially unchanged system design half as good dissolution can be obtained in both directions requiring a quarter storage capacity, in which the number of raster points in a line is: 384=12x32 and the number of raster points in a column is: 288= 9x32. In the following part of the description the invention will be described in connection with the higher dissolution. Fig. 1 shows that the 768 distinguishable horizontal states can be defined by ten binary addresses, and additional ten binary addresses are required for the definition of the 576 distinguishable vertical states. Indeed, nine add- resses would not be sufficient for determining all of the vertical states, because nine binary addresses g can define only as much as 2 = 512 states which num¬ ber is less than the required number 576. Each ele¬ mentary point of the television monitor having a me- mory coverage is defined therefore by the values of ten horizontal and ten vertical addresses. Let X , X-,,...,X a and X g designate the horizontal and Y , Y, , ..., Y Q and Y g designate the vertical addresses of respective elementary raster points, in which the less sig a nificant addresses being a Xo and Yo and the most significant ones being X q and Y q . Fig, 2 shows again the visible picture area divided now in horizontal direction 12 and in vertical direction 9 elementary regions. Each of such ele en- tary regions has a square shape and comprises 64 ras- 2 ter points in both directions i.e. altogether 64 point It follows from the binary address system that within each of such elementary regions the respective raster points are defined by the least significant six bits of the horizontal and vertical addresses, i.e. by the horizontal addresses X , X,, X 2 , X-,, X. and X 5 and by the vertical addresses Y O. Y —-, . Y-C, Y3.,, Y4„ and .Y,-. The selection of the required one of the elementary regions is provided by the most significant four address bits. In Fig. 2 the visible picture area has been illustrated in such a way that numerical address values have been labelled at the upper and left margins to define the elementary regions and the numerical add¬ ress values have been associated with the binary values of the corresponding most significant four horizontal addresses X,, X 7 , X_ and X q and vertical addresses Yg, Y 7 , Y and Yg.If such binary addresses are read out as binary numbers, the values of such numbers are equal to the numerical coordinates of the corres- ponding elementary regions. In the knowledge of the above designations re¬ ference is made to Figs. 3 and 4 illustrating the me¬ mory area required for the coverage of the visible picture area. Fig. 3 is similar to Fig. 2 and shows the elementary regions each consisting of 64 x 64 points and the numerical values of the elementary re¬ gions have also been indicated at the upper and left margins of the complete area. The numbers of the vertical numerical addresses have been preceded by the binary values of the associated most significant vertical address bit Y n . In view of the fact that existing memories have integer numbers of address ports it can be understood on the basis of Fig. 3 that with the memory coverage of a picture area with 4 : 3 size-ratio an ineffective memory utilization is obtained. Indeed, if the address- ing of the elementary regions (each defining 64 points) as units is considered, then respective four address bits are required in each directions and of the corres- ponding storage capacity defining 16 x 16 of such unity regions only 9 x 12 regions would comprise useful in¬ formation. In Fig * 3 the dashe'd line defines the half of the full storage capacity which can be addressed in the vertical direction by three bits instead of the required four bits. Fig, 4 shows such a memory area, can be addressed vertically by three bits and horizon¬ tally by four bits. Such a memory can be implemented with storage means having half capacity compared to that required for the coverage of the area shown in Fig. 3o It should be mentioned that the above re¬ ferred three vertical bits represent actually the usage of nine vertical address bits, since the full address also comprises the six less significant add¬ ress bits required for the addressing within the respective elementary regions. When FigSβ 3 and 4 are compared, it can be seen that the lowest line of the elementary regions (i.e. the last 64 lines of the visible imag-e) have been "left out" in Fig, 4. This last line of regions can be divided in three fields A, B and C each being ' associated with actual picture information requiring memory coverage. Fig.- 4 shows that the fields A, B and C can be allocated in the first three lines of the last four horizontal regions. This will be clear if we understand that the horizontal address with its four bits can define sixteen horizontal regions, of which only twelve is required for the actual exist- ing elementary regions. The remaining last four "blank" memory locations can well be used for the memory coverage of the fields A, B and C. Fig. 4 shows that with such allocation the last four locat¬ ions of the last five memory lines are left empty. These empty but actually existing memory locations can be used for special purposes not forming part of the present invention,, Between the picture area shown in Fig. 2 and the actual memory capacity shown in Fig. 4 the corres- pondeπce can be provided by the application of modifi¬ ed addresses. A basic feature of the present invent¬ ion lies in that the addressing of the elementary ras¬ ter points occurs in accordance with the ten horizon¬ tal and ten vertical addresses shown in Figs. 1 and 2 i.e. with altogether twenty addresses, and such addresses define the respective raster points when the apparatus is controlled by a computer coupled there¬ to,, Such way of addressing is pictorial i.e. it can easily be visualized and the programs made by such addresses are not complicated and can be checked easily. The actual addressing of the memory, however, occurs when the above mentioned visual addresses called also as picture addresses have been modified. The modification of the picture addresses is carried out by an address modifying circuit illustrat- ed schematically in Fig. 5. The address modifying cir¬ cuit can be implemented with a multiplexer 100 having eigth input and four output ports and comprising a selection control input SEL controlled by the vertical address bit Y q . The eight inputs receive in the arrangement of Fig. 5 the horizontal address bits X_ and X q and the vertical address bits Y fi , Y-, and Y q . The four output supplies modified horizontal addresses X* and X' and the modified vertical address bits The task - f the address modifying circuit shown in Fig. 5 is to transform the elementary fields A, B and C in the memory fields shown in Fig. 4. From the comparison of Figs. 3 and 4 it can be seen that when the value of the vertical address bit Y g is 0, the picture scanning takes place in the upper eigth lines of regions and no address modific¬ ation is reauired. When the value of the vertical address bit Y q will be "1", a modification is required. Fig. 4 shows that in the last four horizontal address regions (right hand side) of the memory the value of the first two most significant horizontal address bits X g and X g is OMPI ■ WIPO l β If during the address modification in case of Y g =l the value of the addresses X_ and X q is changed to 1, then the so obtained addresses will define the last -four horizontal regions of the memory when the electron beam scans the fields A, B and C in the niπeth line of regions. It is characteristic to the field A that during its existence the values of the horizontal address bits X R and X q are both 0. From this follows that with the above modification of the horizontal add¬ resses the field A is transformed to the field A" in Figi 4 (Y q does not address the memory). During the scanning of the field S provision should be made that the modified addresses define the field B' in Fig„ 4. In Fig, 3 it can be seen that in the field B the value of the horizontal address Xo 0 is 1. In Fig, 4, however, the modified field B* has a vertical address in which Y fi =l. The address modifying circuit of Fig. 5 satisfies this condition by provid- iπg the equation Xg = -Y ' if Y q = 1. Similarly,, when the field C is scanned by the electron beam, the modified address should define the field C, It is true for the field C that X g =l (Fig.3). In the field C* the .condition Y 7 =l should be met. The circuit of Fig, 5 provides for such conditions. The address modifying circuit does not change the least significant six horizontal and vertical addresses X Q , X χ , X 2 , 3 , X , X 5 and Y , Y ∑ , Y 2 , Y 3 , Y . t Y-. which within the respective elementary regions define memory locations associated with respective raster points. The address modification does not affect the addresses X 6 ^ -,' X- 7, and X8_ either. The modified addresses are summarized in the following table 1. The addresses marked by the comma " * " represent the modified ones. Table 1. The multiplexer 100 shown in Fig. 5, which can be implemented e.g. by the integrated circuit SN 74157 of Texas Instruments Inc., can be replaced by any other logical circuit that is capable of satis¬ fying the criteria set by. table 1. When the address modifying circuit is used, the most significant vertical address Y q is not transmitt- ed for further utilization, since the role of this address bit lies only in the appropriate control of the address modifying process. This explains why only nine¬ teen addresses should be associated with actual me¬ mory address ports of the complete number of twenty picture addresses. With the twenty picture addresses the operations and the programming remain easy to handle and visual, and the address modification spares half of the required storage capacity. .Fig» 6 shows the general block diagram of the apparatus according to the invention. The apparatus comprises a central clock generator 110 providing clock pulses with a repetition frequency.of about 15 MHz and an address generator 112 which in res¬ ponse to the clock pulses provides horizontal and vertical addresses required for addressing the me¬ mory. The output of the address generator 112 is coupled to address bus 114 which comprises the add¬ ress lines of the horizontal and vertical addresses X- X, X g and Y lf Y 2 Y g described in connect¬ ion with Figs β 1 to 4. The address generator 112 has a synchron output 116 which controls a synchron¬ izing unit ll8 β The synchronizing unit 118 gene- rates synchron pulses for a television monitor net shown in Fig * 6 and the pulses are phase-lockεd to the picture addresses and are combined with video output signals provided by the apparatus to form a standard compound video signal sequence. The address bus 114 of the address generator 112 is couoled to first inputs of n a dress switch¬ ing unit 3.20 consisting of a few number of cne-out of-two type multiplexers. The output of the address switching unit 120, depending on the logical value of the control signal coupled to its control input 122, provides the logical values of the signals lead either of its first or second inputs. The second in¬ puts of the address switching unit 120 are connect¬ ed to the address outputs of interface 124 provid- ing connection to an outer computer or terminal not shown in the drawing. It will be explained later that the display monitor and the computer alterna¬ tively get access to memory 130 of the apparatus. The way of addressing the memory 130 is identical in case of both kinds of accesses. The addresses of the displayed raster points are always determined by the condition of the address bus 114 of the address generator 112 β The memory access initiated by the outer computer is determined by the address sent from the computer via the interface 124. For the sake of distinguishing the addresses arriving from the computer and the normal picture addresses, the horizontal and vertical computer addresses will be designated as AX-,, AX~ ... AX q and AY-,, A 2 ,..AY g . The computer has access to the memory in pre¬ determined operational phases only, which is provid¬ ed by interconnecting the address access enable in¬ put 126 of the interface 124 with one of the address lines e.g. with the horizontal address line X^, of the address generator 112. The output of the address switching unit 120 is coupled through the address modifying circuit 128 to the address inputs of memory l30 o The address modifying circuit 128 is substantially indentical with that shown in Fig. 5 and it provides an appropriate address control for the memory 130 which is in accord¬ ance with the aforementioned conditions. The memory 130 is coupled to a memory control unit 132 which latter is connected both to the address generator 112 and the interface 124 and it controls the memory 130 in appropriate modes of operation (writing, read¬ ing modes). A data bus 134 is associated with the memory 130 for transmitting both output and input data and the data bus 134 is coupled to the input of a data switching unit 136. The data switching unit 120 regarding its design and control, and it has the task of alternatively switching the data bus 134 either to the computer or to the display monitor. The data switching unit 136 has a control input 138 controlled by the appropriate address line (the hori-' zontal address line X-^) of the address bus 114. In the operational mode in which the data switching unit 136 is associated with the televis-bn monitor, the unit 13.6 is directly coupled to a transition memory which can be implemented by a shift register 140 in the exemplary ambodiment, and the shift register 140 is controlled from the least significant horizontal address lines (X Q » X-i # X 2 a n< - X 3 )and it performs a parallel to serial conversion. The series output of the shift register 140 is coupled to D/A converter 142 which represents at its analog output the read out memory values in the form of an analog voltage. The apparatus shown in Fig. 6 facilitates the reading of outer video signals in the memory 130. In this case appropriate circuits (not shown in the drawing) provide that the video signals which are to be recorded arrive synchronouosly with respect to the horizontal and vertical addresses of the appara- tus. From the analog signals arriving in video in¬ put 144 an A/D converter provides digital signals coupled to the series input of the shift register 140. The writing mode is set by the computer through the interface 124 and by the memory control unit 132, and in that case data entered seriesly in the shift register 140 can be written through the data switch¬ ing unit 136 in parallel in the memory 130 receiving then a writing enable signal.*- During computer access periods the other out- put group of the data switching unit 136 acts as if it were an extension of the data bus 134. This out¬ put group consists of a plurality of parallel bit lines coupled respectively to corresponding inputs of multiplexer 148. The multiplexer 148 has a state O PI control input 150 and the logical condition of the latter selects the input which is coupled to data line 152 of the interface 124, The above described connection between the data line 152 and the data bus 134 provides for a bidirectional data-movement, whereby the computer will be capable of writing in and reading out from the memory 130. The apparatus shown in Fig. 6 can store six bits of information at each address. This means that the memory is composed of six memory units controlled in parallel, and the units coupled to the data bus 134 can transmit signals corresponding to the six bit long output information. From the six bit long information content the D/A converter 142 can produce 2 =64 steps of gradation, or if color display is used 64 different .colors can be displayed on the screen of the monitor. In the latter case a standard RGB signal should be generat¬ ed from the output signal of the D/A converter 142. The operation of the apparatus shown in Fig. 6 is as follows. With the conditions described in ccnnection with Figs. 1 to 4 during the scanning of each tele¬ vision raster line 768 raster points can be display- ed (when the higher dissolution is used). If the visible section ' of a raster line is regarded, the duration of a raster point will be about 66 ns. The period time of the clock pulses of the clock gene¬ rator 110 is about 66ns, and the address generator 112 provides the vertical and horizontal addresses from these clock pulses. The horizontal addresses are obtained by appropriate divisions of the clock pulses according to subsequent integer powers of two, and the period time of the horizontal address Xo is equal to that of the clock pulses, For the understanding of the memory address¬ ing, also the actual access times of existing me¬ mories should be regarded. In the following para- graphs the specific properties of random access dynamic memories will be described, since these pro¬ perties form conditions for the realization with regard to the design of the addressing system,, In dynamic RAM memories the storage elements are respective capacitors. The losses of such capa¬ citors should be compensated frequently at least following every period of 2 ms duration. This operat¬ ion is called as refreshment. If no refreshment occurs with a 2 ms long period, the stored information gets lost. The addressing system is designed in such a way that the first half of the addressing bits are enabled by a Row Address Strob signal, in short by a RAS signal, and the second half is enabled by a Column Address Strob signal i.e. CAS signal. It is sufficient for the refreshment that the first half of the address bits is used for either writing or read¬ ing operations within repetitive periods shorter than 2 ms. The number of address ports of dynamic RAM me¬ mories is half the number of bits required for their complete addressing. The complete addressing occurs in two consecutive moments. In the first step to¬ gether with the establishment of the RAS signal e.g. the first group of seven address bits and in the second step together with the CAS signal the second group of seven address bits have to be coupled to the address ports. The writing enable signal can be established together with the generation of the CAS signal. Without the presence of a write enable sig¬ nal, the reading mode is obtained. Following the es¬ tablishment of an address the readout data will be available after a certain delay, and in writing mode data can be read in when a corresponding delay time has elapsed since the establishment of the address. This delay time takes an essential part from the full access time of the dynamic memory and typically it is between about 150 and 300 πs. The price of dynamic memories increases rapidly with the shorten¬ ing of access time. It has been found that with the currently available integrated components the spe¬ cific memory costs for a unity stored information are at minimum if dynamic memories with 16K x 1 bit storage capacity are used, however, the usage of me¬ mories with 64K x 1 bit capacities can also be pre¬ ferable in the present invention without any sub¬ stantial change in system design or way of control. Reference is made again now to Fig, 6 and the operation will be described .in the exemplary case when the memory 130 consists of several dynamic me¬ mories with 16K x 1 bit storage capacity addressed all in parallel. For the addressing of a memory with such capacity 14 bits are required. The output of the address generator 112 pro¬ vides the horizontal addresses Xo, X,1, .,. X9-. and the vertical addresses Yo, Yl-, ... Y o y fl altog -ether twenty addresses. Each address combination represents respective elementary raster points in the visible picture area, as it has been described in connection with Figs. 1 and 2. In connection with Fig. 5 it has been describ¬ ed that of the twenty input address lines the address modifying circuit 128 pass-es through only nineteen because as many bit lines are already sufficient for the addressing of the required number 768 x 576 of raster paints. The dynamic memory elements forming the memory 130 can be addressed in the exemplary case by 14 bits. The remaining five address lines cannot be used directly for the addressing of the memory. It can be understood, if the memory 130 is composed of 2 =32 memory elements and each has a storage capa- city of 16K x 1 bit, then the remaining five bit should serve for the selection of the required me¬ mory element. Let us examine what kind of memory organiz¬ ation can provide that the reading of the memory towards the display monitor should occur synchro- nouosly with the scanning electron beam, that the memory elements should obtain refreshment within the required maximum 2 ms long periods and in the mean¬ time the computer should have a free access to all of the memory locations. For the illustration of the circuit design of the memory 130 Fig, 7 shows the units coupled direct¬ ly to the memory 130, and the groups organized by the individual memory elements have also been illust- rated. The following explanation supposes that in each raster point a single bit is stored only. Obvi¬ ously, if more information have to be stored associat¬ ed with respective raster points, this demand can be satisfied by a simple multiplication of the memory elements. Fig. 7 shows that the memory elements of the memory 130 a re grouped in two blocks 130a, 130b and each block comprises a pair of groups of memory ele¬ ments each group comprising eight elements. It follows from the principle of the standard television scanning with alternating half-pictures, that two adjacent lines which are neighbours on ' the visible picture are associated with separate half- -pictures following each other. The duration of each half-picture is 20 ms. When this is compared to the vertical addresses shown in Figs. 1 and 2 it can be seen, that the 0 values of the vertical address Yo define the first half-pictures and the 1 values thereof define the second half-pictures. Within the respective memory blocks 130a and 130b a group of eight memory elements is associated with the value and another group with Yo=1. The memory control unit 132 illustrated in Fig. 6 is organized in such a way that depending on the value of Y it enables either of the two groups. Within the respective blocks the sixteen memory elements are connected in parallel. Since the address Y has been used for the selection of the required group of memory elements, there are only four further addresses which have to be allocated, because the respective memory elements can be addressed by fourteen bits. The difference between the- respective blocks 130a and 130b lies in that the block 130a stores the information associated with the raster points hav¬ ing a horizontal address X,=l, while the other block 130b stores information for the points having hori¬ zontal addresses with X,=0. When the addressing is considered the blocks 130a and 130b can be regard¬ ed as being addressed in parallel, however, actually the address switching unit 120 and the data switch¬ ing unit 136 connect the respective blocks alter¬ natively to the television monitor or tc the inter- " ^ 22 ~~ - ~~ face 124 coupled to the computer. Fig, 7 shows that in case of X~=l the address switching unit 120 connects the address generator 112 through the address modifying circuit 128a to the address lines of the upper block 130a, In that case eight .memory elements are read out in parallel from the block 130a and the readout data are written in eight parallel locations of the shift register 140 through he data switching unit 136. . Substantially at the same time the interface 124 clocks the addresses AX-,=0 towards the computer, and the address switching unit 120 passes the address lines coming from the interface 124 through the add¬ ress modifying circuit 128b to the memory elements of the lower block 130b. The data lines of the me¬ mory elements of the block 130b are switched by the data switching unit 136 towards the multiplexer 148 also at the same time. When the value of X-, is changed to 0, then the functional roles will be interchanged i. e, the address and data lines of the upper block 130a will be switched towards the interface 124 and the lower memory block 130b will communicate with the monitor. The blocks are therefore alternatively coupl- ed either to the computer or to the monitor depend¬ ing on the state of X-, and during each of such connections an information reading or writing operat¬ ion takes place that corresponds to the passage of 8 bits of information. Obviously, the above described alternative switching of the blocks can be spared if the incivi- dual blocks comprise sixteen parallel mεmcry elements which are distinguished according to the value of Y . OMPI \YI?O In such cases, however-, the simultaneous switching and transfer of sixteen bits is required, and the handling and matching of buses with high bit-num¬ ber is not favourable regarding the costs. Remaining with the exemplary embodiment shown in Fig. 7 it can be seen that during each value of Fig, 3 respective groups of 8 bits length will be available at the parallel inputs of the shift register 140, It follows from the addressing system that each period of X-, comprises 3 full periods of X . When the shift register.140 is clocked by pulses having a frequency of 2X (with period times of approximately 66 ns), the informat¬ ion written in parallel in the shift register 14C will be shifted to D/A converter 142 (Fig. 6 ) and the monitor obtains fresh information in every 66 ns. Instead of the shift register 140 a multiplexer with eight inputs and an output can also be used if it is set by ' the addresses X O, X-1, and X.2_..0f the aforementioned remaining four address bits the control of the selection between the blocks has taken one i.e. the bit of X-,, and the still remain- ing three address bits are used for the control of the parallel to series conversion carried out by the shift register 140 or by the multiplexer not shewn in the drawing. In view of the fact that the blocks are alternatively connected towards the shift re¬ gister 140, respective blocks can be accessed from the computer side in each half-period of X_, Obviously, if the memory 130 is designed to have a larger storage capacity and more than 14 bits can be used for determining its address, then the problem of memory allocation will be less comp¬ licated, since a fewer number of address bits will have to be used for the parallel to series conversion i„e, the length of the shift register can be reduced. A substantially equivalent alternative is ob¬ tained if smaller picture dissolution is sufficient. With half as fine dissolution in both directions, the configuration shown in Fig. 7 can be modified inas¬ much, as there will be no need for the repetition of the memory elements in the'memory blocks according to the value of Yo because both half pictures will then comprise identical information and also the frequency of the clock pulses can be reduced to the half of the value used with the high dissolution. By such modific¬ ations it is sufficient ' if respective four bits are transmitted in parallel from and to the memory instead of the eight bits of the previous embodiment. With such dissolution the required full memory capacity is therefore a quarter of the value required for the higher dissolution. The continuous refreshment of the dynamic me¬ mory elements can be provided by the rational allocat¬ ion of the 14 memory address bits, It should be beared in mind that each address clocked together with the RΛS signal must occur within repetition periods shorter than 2 ms. Of the horizontal addresses the addresses o' " I' X 2 and X, are not used for the direct address- iπg . of the memory elements. The remaining addresses are changing in every line, and due to the allocation of the modified memory addresses shown in Figs, 4 and 5 in the lines associated with the vertical addresses Y g =0 not every value of the horizontal address X q is utilized and the usage of the horizontal address X p x also not preferable for the memory refreshment, since only those addresses can be used for the refreshment task that occur in shorter periods than 2 ms, A pre¬ ferable allocation of the actual memory addresses is OMPΓ V'iPO given below for memory elements of 16K x 1 bits capacity. The memory addresses established together with RAS signals are: Of these addresses the horizontal ones take every possible combination in every television line, and the slowest vertical address Y-- occurs at least in every eighth television line, i,e. having an occurr¬ ence rate of 512 .us. With such addresses the require- εnts for the refreshment of the memory are satisfied well within the maximum permitted periods of 2 milli¬ seconds. The memory addresses established together with the CAS signals are: g. X g and 4 , Υg, Yg, Y ? and Yg. Of the remaining addresses: - Y q is used for the address modifying circuit 128; - Yo is used for the validation of the q J rouos of the blocks 130a and 130b (according to the changes of the half pictures); - X , X-, and X ? are used for controlling the parallel to series conversion; and - X_ 2 is used first to control the selection between the memory blocks and on the other hand to control the alternating access to the memory either for the computer or for the display monitor. It can also be preferable, if unlike to the or¬ ganization shown in Figs. 6 and 7, the memory blocks 130a and 130b are divided in two parts, respectively, in such a way, that respective groups of four memory elements are controlled in parallel. If the switch¬ ing of the addresses and the data between the groupc is carried out by means of the occurrence cf the address X 2 , then the length of the parallel to series conversion can be reduced to two bits i * e. the shift register might comprise four locations only * In that case, however, the memory cycles of the memory groups controlled according to different values of the address X 2 should be offset in time with one cycle with respect to each other to provide sufficient time therebetween for the undisturbed access towards the comDUter. The advantaσe of such an orαanizaticπ lies in that data lines carrying four bits can ' be used instead of. the data lines of eight bits required in the organization according to Figs. 6 and 7; which in¬ volves substantial reduction of hardware costs. It will be clear from the above description that the skilled artician can devise further emboci- ments not described herein without departing from the scope and spirit of the' present invention and the invention cannot be limited to the exemplary embodiments explained for the clear understanding only.

Claims: Clai s 1, Apparatus for the display and storage of television picture information by using a memory accessible from a computer, comprising a central clock generator, an address generator coupled to the clock generator for generating horizontal and vertical picture addresses, a synchron unit connect¬ ed to the address generator and providing line and picture synchron signals, an interface providing a connection towards the computer, a random access memory addressed by the address generator, a memory control unit, a digital to analog coverter coupled to the data bus of the memory for providing video signlas, c h a r a c t e r i z e d in that the memory (l3θ) consists of dynamic random access me- mory elements having address inputs controlled through an address modifying circuit (12SJ, the in¬ puts of the address modifying circuit (128; are coupled to the output of an address switching unit (l2θ), the address switching unit (120) comprises first input group connected to predetermined add¬ ress lines of the address bus (114) of the address generator (112) and a second input group connected to predetermined address lines of the interface (124, ) , the data bus (134) of the memory (l3θ) is connect- ed to the input of a data switching unit (135) comp¬ rising a first output group connected t o parallel inputs of a parallel—to-εeries converter preferably a shift register (140) and a second output group- coupled to multiplex inputs of a multiplexer (143), the output of the multiplexer (148) is connected to the data line (152) of the interface (124)', the control inputs of the address switching u it (12C) and of the data switching unit (136) being connected to a horizontal address line of the " address bus associated with a horizontal address bit ,) of low significance, the parallel to series converter is controlled by the address lines carrying the least significant horizontal address bits (x , X-, or X 2 ) the state control inputs of the multiplexer (148) are coupled to the address lines of the interface (124) carrying the least significant horizontal address bits (AX , AX, or A 2 ) , and the digital input of the digital to analog conver¬ ter (142) is connected to the serial output of the parallel-to-series converter. 2. The apparatus as claimed in claim 1, c h a r a c t e r i z e d in that the data bus of the memory (l3θ), the data switching unit (136), ' the parallel-to-series converter and the multiplexer (152 as well as the buses interconnecting these units being designed to bidirectional data-transport, and the series input of the parallel-to-serial converter is coupled to tne digital output of an analog to di¬ gital coverter (146). 3, The apparatus as claimed in claim 1, c h a - r a c t e r i z e d in that between the in- and outputs of the address modifying circuit (128) the following logical equations are true: X 8 = X* 8 ; X g = X' 9 ; Y_= Y' 6 ; Y ? = Y' ? if Y g = 0 and. which the addresses designated by. X and Y represent the states of the corresponding horizontal and ver¬ tical bit lines of the address bus (114), the add¬ resses X' and Y* designate the states of the modi¬ fied horizontal and vertical address lines at the output of the address modifying circuit (128). O PI . .,. WIPO 4. The apparatus as claimed in any of claims 1 to 3, c h a r a c t e r i z e d in that each me¬ mory element of the memory (l3θ) is associated to a respective other emory element, and in the so obtained pairs of memory elements the first ones being validated by the Y =1 condition, while the other ones by ' the condition. 5. The apparatus as claimed in claim 4, c h a - r a c t e r i z e d in that the memory (l3&) is or¬ ganized in two blocks (130a, 130b) each of which is coupled to a respective address modifying circuit (128a, 128b), and the address switching unit (l2θ) and the data switching unit (135) comprising switching paths, for switching between the blocks. 6. The apparatus as claimed in claim 5, c h a ¬ r a c t e r i z e d in that in the ' respective blocks (130a, 130b) of the mer.ory (130) the memory elements being arranged in pairs of groups addressed in para¬ llel, and the control " of the groups being offset in time with respect to onε-anot er by a memory cycle. 7, The apparatus as claimed in claim ^ c h a ¬ r a c t e r i z e d in that the vertical dissolut¬ ion being either 576 or 238 raster points and the horizontal dissolution being either 763 or 3S4 raster points. -gJRE fr- O PI ΗPO « « -

Inventors: ENDRODI B, SZENES Z
Applicants: ENDRODI B, SZAMITASTECH KOORD, SZENES Z, SZAMITASTECHNIKAI KOORDINACIOS INTEZET
Application year: 1981
Main classification: G06F13
IPC codes: G06F13, G09G1, G09G5