SEMICONDUCTOR DEVICE USING RESISTORS EACH FORMED OF ONE OR MORE BASIC RESISTORS OF THE SAME PATTERN

Abstract: Basic resistors R₀, R₁, R₂ and R₃ of the same pattern are arranged in parallel fashion on a semiconductor substrate. A first resistor is formed between terminals T₁₂ and T₁₂′ by con­ necting basic resistors R₁ and R₂. A second resistor is formed between terminals T₂₂ and T₂₂′ by connecting basic resistors R₀ and R₃. The basic resistors R₁ and R₂ of the first resistor are dis­ posed in the middle portion of the resistor group RG. The ba­ sic resistors R₀ and R₃ of the second resistor are arranged on opposite sides of the first resistor. The basic resistors R₀ to R₃ are formed to the same pat­ tern and so, ideally, should have the same resistance. How­ ever, error resistances may arise, for example due to heat sources on the semiconductor substrate. By connecting the basic resistors in the way described the effects of error resist­ ance can be substantially cancelled.

Description: SEMICONDUCTOR DEVICE USING RESISTORS EACH FORMED OF ONE OR MORE BASIC RESISTORS OF THE SAME PATTERN. The present invention relates to a semiconductor device having a group of basic resistors and more particularly to a monolithic semiconductor device including a plurality of resistors, each of which comprises one or more basic resistors. In a monolithic semiconductor device such as an AD converter, a DA converter, an operational amplifier, etc., formed on one chip, resistors as well as active elements such as transistors are often formed by diffused layers or thin film layers. In such a device, a ratio of one resistance to another resistance is required to have as high an accuracy as possible, in order to deal with an increased number of bits. For example, in an 8-bit AD converter, an analogue signal is divided into 1/28 signals. To divide the analogue signal accurately, the ratios between the resistances included in the AD converter must be within a tolerance 8 of lower than 1/(2x28) The required accuracy increases along with the increase in the number of bits used by the semiconductor device. For the purpose of fabricating resistors on a semiconductor substrate so as to realize the desired ratios of the resistances with a high accuracy, in a conventional manner, a number of basic resistors are formed each to the same pattern, and then, a desired number of the basic resistors are combined, i.e., connected by wirings, so as to obtain the desired ratios between the resistances. Since all of the resistors have the same pattern, it is much easier to realize accurately desired resistance ratios by connecting basic resistors to provide resistances than to fabricate a resistor of a desired length for each resistance. However, in the conventional method, although each basic resistor has the same pattern, the resistances of the basic resistors are not always equal to each other. The difference between the basic resistances is the result of, for example, thermal treatment during a diffusion process or, after the diffusion process, Xis due to heat sources such as semiconductor elements loaded on the semiconductor substrate. Since the basic resistances are not always accurately equal to each other, the obtained ratios between the resistances are not always equal to the desired ratios. In most cases, there is a linearly changing temperature gradient along one direction on each chip on which the basic resistors are arranged. According to an embodiment of the present invention there is provided a semiconductor device comprising a semiconductor substrate, and a group of resistors including a plurality of basic resistors having the same pattern as one another, a predetermined number of the basic resistors being connected to form a resistor having a desired resistance value, wherein the group of resistors comprises a first resistor formed by connecting one or more of the basic resistors arranged on the middle portion of the group, and, a second resistor formed by connecting a plurality of the basic resistors arranged on both sides of the first resistor. Thus, the basic resistor or resistors of the first resistor are disposed between basic resistors of the second resistor. The basic resistors may be arranged in parallel fashion on the semiconductor substrate. An embodiment of the present invention can provide a semiconductor device having resistors, in which the accuracy of the ratios between the resistances is improved, for example by taking into account the linearly changing temperature gradient. An embodiment of the present invention can provide such a semiconductor device by which an increased number of bits can be used. Reference is made, by way of example, to the accompanying drawings, throughout which like reference characters and numerals designate the same or similar parts, and in which: Fig. lA is a plan view of a conventional semiconductor device on which patterns of resistors are connected; Fig. lB is an equivalent circuit diagram of Fig. lA; Fig. 2A is a plan view of a semiconductor device on which patterns of resistors are connected, according to an embodiment of the present invention; Fig. 2B is an equivalent circuit diagram of Fig. 2A, and; Figs. 3 to 6 are equivalent circuit diagrams of semiconductor devices, according to further embodiments of the present invention. Before describing the embodiments of the present invention, a conventional semiconductor device will first be explained. Fig. lA is a plan view of a conventional semiconductor device on which patterns of resistors are connected. Referring to Fig. lA, resistors 1, 2 and 3 having resistances Ro , R1 and R2 , respectively, are basic resistors formed on a semiconductor substrate (not shown). Each of the basic resistors 1, 2 and 3 is formed by using the same pattern and under the same fabricating process. Therefore, the resistances Ro , Rl and R of the basic R0 resistors are theoretically the same as each other and are equal to the designed value R. When two resistances having a ratio of 1 to 2 are to be fabricated, both ends of the resistor 1 are connected through aluminum wirings A110 and AIl1 , respectively, to terminals Tl and T1, , respectively, to form one resistance R on one hand, and on the other hand, another resistance 2R is formed by connecting one end of the resistor 2 to one end of the resistor 3 through an aluminum wiring AR, , and also by connecting the other ends of the resistors 2 and 3 to terminals T2' and T2 through aluminum wirings AQ2 and AZ3 , respectively. Thus a semiconductor device having two resistances with the theoretical ratio of 1 to 2 is obtained as illustrated in Fig. lA. The equivalent circuit diagram of the device of Fig. lA is illustrated in Fig. lB. If all of the resistors 1, 2 and 3 have the same resistance R, the ratio between the-resistance 1, which is the value of the resistor between the terminals Tl and Tl' , and the resistance (R1 + R2), which is the value of the resistor between the terminals T2 and T21 , is equal to the designed value which is 1 to 2. A resistor having a resistance 2R can of course be made by forming a resistor having a length twice that of the basic resistor 1. However, in this case, the accuracy of the length is deteriorated, where the term "length" represents the length of the portion functioning as a resistor. That is, it is difficult to form a resistor to have a length exactly twice that of the basic resistor because displacement of positions often occur when windows are opened to make the terminals. In contrast to this, it is much easier to form a plurality of basic resistors having the exactly same length and to actualize the resistance 2R by connecting in series two of the basic resistors, as mentioned above with respect to the conventional device. This is an advantage in the above-mentioned conventional device. However, there is still a problem in the conventional device. That is, as mentioned before, although each basic resistor has the same pattern, the resistances of the basic resistors are not always equal to each other. If the basic resistances Ro to R2 have some errors, and, for example, if these values are practically as follows: Ro R R1 = R (1 + A) R2 = R (1 + 2A), respectively, then the practical ratio of the resistance between the terminals Tl and T1, to the resistance between the terminals T2 and T2, is: EMI5.1 Therefore, the practical ratio differs from the designed ratio by 38. As has been described above, it is assumed that each resistance differs from the neighboring resistors by the error A. That is, the resistances increase or decrease along one direction under certain conditions. Such conditions are not special cases. For example, during a diffusion process for forming the resistors, semiconductor substrates, or, in other words, wafers are placed in a furnace so that they are subjected to heat treatment. In the furnace, heat is not always applied uniformly to each wafer because of various reasons. For example, supporting means for fixing the wafers in the furnace may act as a heat source to provide a linear temperature gradient on each wafer. In one chip of the semiconductor device, if there is a temperature difference during diffusion process for forming diffused type resistors, the error A of resistance value from the designed resistance will appear. Further, even when uniform resistances can be obtained in the fabricating process, such a linear temperature gradient may also be produced on each chip during operation of the semiconductor device, because semiconductor elements loaded on each chip generate heat to act as heat sources during the operation. For example, there may be a heat source such as an output transistor at the side of the resistor 3, and there may be no heat source at the side of the resistor 1. In such a case, the temperature at the side of the resistor 3 is higher than the temperature at the side of the resistor 1. Accordingly, the resistance R2 becomes higher than the resistance Ro , as will be understood when considering a temperature coefficient of a resistor in a semiconductor. The properties of IC resistors including the temperature coefficient are described in "Analysis and Design of Analog Integrated Circuits", Paul R. Gray & Robert G. Meyer, University of California, Berkeley, JOHN VJILEY & BR< SONS, copy right 1977, on page 105, Fig. 2.33. The present invention provides a semiconductor device in which resistors are suitably connected to realize the desired ratios between resistances with a high accuracy. Fig. 2A is a plan view of a semiconductor device on which patterns of resistors are connected, according to an embodiment of the present invention. Referring to Fig. 2A, basic resistors 1, 2 and 3 in a diffused type resistor group RG are fabricated in the same way as in the conventional device. Let it be assumed that the resistances Ro , ERI and R2 of the resistors 1, 2 and 3 are R, (R + A) and (R + 2A), respectively, as in the conventionaldevice of Fig. 1. According to the present invention, one end of the resistors 1 and 3 placed on opposite sides of reSist¯ group RG are connected by an aluminum wiring At10. The other end of the resistor 1 is connected through an aluminum wiring AZ11 to a terminal T20. Also, the other end of the resistor 3 is connected through an aluminum wiring AZ14 to a terminal T20'. Thus, a series connected resistance (Ro + R2) is formed between the terminals T20 and T20'. With respect to the resistor 2 placed in the middle portion of the resistor group RG, one end of the resistor Rl is connected through an aluminum wiring AZ12 to a terminal T10 and the other end is connected through an aluminum wiring AQ13 to a terminal Tlo'. Fig. 2B is an equivalent circuit diagram of Fig. 2A. The ratio of the resistance between the terminals T10 and T101 to the resistance between terminals T20 and T201 is: EMI6.1 Therefore, in this embodiment, the error A is cancelled so that the desired ratio of resistances can be obtained accurately. Figs. 3 to 6 are equivalent circuit diagrams of semiconductor devices, according to further embodiments of the present invention. In each of these devices, basic resistances Ro , Rl , ... R are arranged on the semi n conductor substrate in parallel fashion to form a diffused resistor group RG. The resitance values are assumed to be as follows: Ro R R1 = R (1 + A) R = R (1 + nA) n In the second embodiment of. the device of Fig. 3, the ratio of resistances 1:3 is nearly realized by connecting in series the resistances Ro , R2 and R3 which are placed on both sides of the resistance R1. The accurate ratio of the first resistance R1 between terminals T11 and T111 ' to the second resistance (Ro + R2 + R3) between terminals T31 and can can be calculated as follows. EMI7.1 where, A is much smaller than 1. The error is nearly equal to 2A, which is very small in comparison with the error in the conventional device. In the conventional device, for example, the resistance R3 is taken as the first resistance; and the resistance obtained by connecting the resistances Ro , R1 and R2 is taken as the second resistance. In this case, the error becomes about -6E which is much larger than the error in the second embodiment. It should be noted that, in place of taking the resistance Rl as the first resistance, the resistance R2 may be taken as the first resistance; and the resistance obtained by connecting the resistances Ro , R1 and R3 may be taken as the second resistance. In this case, the error is about -2A, resulting in the same effect as in the above-mentioned second embodiment. In general, it can not be determined at the designing stage whether the resitances increase from right to left or from left to right in the diffused resistor group RG. However, since the structure of the resistor group RG is symmetrical or almost symmetrical, as illustrated in Figs. 2A and 3, the same effect of small error is obtained regardless of the direction of the increase of the resistances. Figs. 4 to 6 illustrate semiconductor devices of further embodiments of the present invention, in which completely symmetrical connections are presented to provide desired ratios of resistances completely, regardless of the increased number of resistors. Referring to Fig. 4, the resistances R1 and R2 on the middle portion of the resistor group RG are connected in series to form the first resistance between terminals T12 and T121 , and the resistance R0tand R3 on both sides of the resistor group RG are connected in series to form the second resistance between terminals T22 and T22' , so that the ratio 1:1 is obtained between the first and second resistances. The ratio of the first resistance to the second resistance is calculated as: EMI8.1 which is exactly the same as the designed value. Referring to Fig. 5, the resistances R3 and R4 on the middle portion of the resistor group RG are connected in series to form the first resistance between terminals T13 and Tl3'; and the resistances Ro , Rl , R2 , R5 , R6 and R7 on both sides of the resistor group RG are connected in series to form the second resistance between terminals T33 and T331 , so that the exact ratio 1:3 without the error component A is obtained between the first resistance (R3 + R4) and the second resistance (Ro + Rl + R2 + R5 +R6 + R7). In Fig. 6t three resistances are formed so that the exact ratios 1:2:3 without the error component A is obtained. That is, the resistances R5 and R6 on the middle portion of the resistor group RG are connected in series to form the first resistance (R5 + R6) between terminals T14 and T14' the resistances R3, R4, R7 and R on both sides of the first resistance are connected in series to form the second resistance (R3 + R4 +R7 + R8) between terminals T24 and T24'; and, the resistances Row R1, R2, Rg, R10 and R11 on both sides of the resistor group RG are connected in series to form the third resistance (Ro+ R1 + R2 + Rg + R10 + R11) between terminals T34, T34'. As will easily be calculated, the ratio (R5 + R6): (R3 + R4 + R7 + R8):(R0 + R1 +R2 + Rg +R10 + R1l) is exactly equal to 1:2:3. From the foregoing description, it is apparent that, according to the present invention, a high accuracy can be obtained with respect to the desired ratios between resistors which are formed with the same pattern on a semiconductor substrate, even when these resistances include errors. The present invention can be applied most effectively when these errors are due to a linear change in resistance values in one direction in the group of the resistors. When there is no error in each resistance, the present invention may of course be applied without any trouble. Thus, an embodiment of this invention provides a semiconductor device of a monolithic type comprising a group of resistors having a plurality of basic resistors arranged in parallel fashion. Each basic resistance is formed by the same pattern so as to have a consistent resistance and an error resistance. The error resistance may be due to heat sources on the semiconductor substrate. In the ratio of a first resistor formed by connecting one or more of the basic resistors arranged on the middle portion of the group to a second resistor formed by connecting a plurality of basic resistors arranged on both sides of the first resistor, the component of the error resistance is substantiSly cancelled. Hence, in its broad aspect, the present invention provides a semiconductor device having a plurality of basic resistors arrayed in a group across a semiconductor substrate. When a single basic resistor is to be employed a basic resistor substantially central of the group is used. When two or more basic resistors are to be employed connected together, basic resistors substantially symmetrically positioned in the group are connected together.

Claims: CLAIMS 1. A semiconductor device comprising: a semiconductor substrate; and, a group of resistors, including a plurality of basic resistors having the same pattern as one another, a predetermined number of the basic resistors being connected to form a resistor having a desired resistance value, characterised in that the group of resistors comprises: a first resistor constituted by one of the basic resistors, or formed by connecting together more than one of the basic resistors, the or each basic resistor of the first resistor being disposed in the middle portion of the group; and a second resistor formed by connecting together basic resistors disposed to opposite sides of the first resistor. 2. A semiconductor device as claimed in claim 1, wherein the basic resistors of the said plurality are arranged in parallel fashion on the semiconductor substrate. 3. A semiconductor device as claimed in claim 1 or 2, wherein the group of resistors further comprises a third resistor formed by connecting together basic resistors disposed outside the second resistor. 4. A semiconductor device as claimed in claim 1, 2 or 3, wherein the basic resistors are diffused type resistors formed on the semiconductor substrate. 5. A semiconductor device as claimed in claim 1, 2 or 3, wherein the basic resistors are thin film resistors formed on the semiconductor substrate.

Inventors: KUDO, OSAMU, TAMADA, HARUO
Applicants: FUJITSU LIMITED
Application year: 1981
Main classification: H01L27
IPC codes: H01L29, H01L27