WAFER AND METHOD OF TESTING NETWORKS THEREON

Abstract: Substrate for an array of integrated circuit dice (10') disposed in a regular array on the monolithic wafer substrate (1). Also disposed on the wafer substrate (1) is a network (11') interconnecting various circuits (10'), with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals (12') exist in the network (11') for connection of the connections of the network with the various integrated circuits (10'). The networks are connected to a contact pad by one or more connection pads (13'), for power and for data entry, and there is provided an auxiliary lead (160, 180, 200) and contact pad (16', 18', 20') for each network for testing each network for operability, also disclosed in the testing method.

Description: WAFER AND METHOD OF -TESTING NETWORKS THEREON BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to the fabrication and testing of monolithic integrated circuit wafers. More particularly, this invention relates to the addition to state-of-the-art wafers of a new conductive test cir¬ cuit integrated on the wafer during manufacture which may be used to test the networks between the dice on the wafer so they may be tested to prove that the wafer meets quality standards. In addition, the method of testing this new wafer is disclosed. 2. Description of the Prior Art While no satisfactory method has heretofore been developed which meets the need for testing networks on wafers, there have been developed ways of testing the integrated circuit dice themselves, as may be seen from U.S. Patent No. 4,183,460, granted January 15, 1980, and the references shown therein, which disclosure is incorporated herein by reference. This patent is deemed illustrative of the state of the art. It is also well known to use testing networks on printed circuit boards on which each die, after testing and packaging, is inserted. Current state-of-the-art tests on monolithic integrated circuit wafers are performed by automatic testers which sequence across the wafer, die by die, to identify each workable die, before the wafer is scribed. If the dice is defective, a mark is made over each defective die, and it is discarded. Such commer- cially available machines include those manufactured by various corporations which manufacture the chips, or they can be obtained commercially as fully automatic wafer probe systems from Pacific Western Systems, Inc., 505 E. Evelyn, Mt. View, CA 94041 or Electro-Glas, Inc., 2901 Coronado Dr., Santa Clara, CA 95051. In addition, probe equipment can be Obtained from Kulicke Soffa Industry, Inc., 507 Prudential Rd., Horsham, PA 19044, which probe equipment interfaces with commer¬ cially available I. C. Test Equipment such as made by Fairchild, Teradyne, etc. In addition, printed circuit board testers exist which insert pin probes at a plurality of points on the printed circuit boards, which pins are sequenced to determine whether the networks, now defined by the packaged circuits placed in the board and soldered or otherwise bonded in place, have a proper connection. In this art, it is known to place small fixed resistors in a circuit so that tests being made can measure whether the circuit has a known resistance. However, it has become possible to build full scale wafers now because the yield of good dice on the wafer has increased. A number of theoretical advantages arise from what may be called wafer scale integration. In order to achieve faster switching speeds, or conversely, smaller signal propagation times, it has been recognized that the die which contains the integrated circuits could be connected on the wafer itself. This requires a network being formed on the wafer by masking or by electron beam pattern generation. This can make use of the space between dice, or the whole wafer as a network. In this latter instance, the individual die from another wafer is directly bonded to the network of the wafer containing the network. In the former case, the ultimate wafer scale integration is achieved, for the entire wafer can be utilized for its best tested function. The problem with machines constructed on wafer scale is effective testing of the circuits so constructed. It is to this- problem that the invention which I have described below is directed. SUMMARY OF THE INVENTION According to my invention, I have provided a monolithic integrated circuit wafer on which may be disposed thereon an array of integrated circuit dice and interconnection networks for interconnection of a plurality of dice to one another and to an external connection pad for the wafer. To this known device I have, in accordance with my invention, provided that the network is composed of a plurality of subnetworks, each having a terminal connection. The terminal connection is connected to an external connection test pad for the wafer. Each of the terminal connections is of measured distance to the external connection test pad and has an inherent measurable resistance. This measurable resistance is a function of the length of the connection to the external connection test pad. According to my invention, after having provided the aforesaid novel structure for a wafer network, one is able to test the network for fault by means of resistance testing of the premeasured subnetworks. Accordingly I have provided a substrate in the form of a wafer made of silicon or any other material suitable for integrated circuit-type processing. Two layers of interconnection separated by a layer of insulation are deposited and patterned on this wafer. The resolution for paterning the metal on the wafer is such that the two layers of metal provide enough routing channels to interconnect all the chips which can physically be placed on the wafer. The actual routing .is provided by a particular pattern of orthogonal lines with a special selection of cross-points connecting certain lines to each other in such a manner that all possibly desired connections among substrate bonding pads and between substrate bonding pads and the outside world can be made. I will describe herein below a representative simplified preferred embodiment, and the method of testing the wafer. Thereinafter, I will describe alternate embodiments which may be preferred in specific instances. Description of the Invention Figure 1A shows the wafer of the Prior Art. Figure IB shows an improved wafer in accordance with the preferred simple embodiment of my invention. Figure 1C shows an improved wafer in accordance with my preferred master wafer in plan view, of which layers will be shown. Figure 2 is a plan view of the layer portions of the wafer of Fig. 1C, showing pad lines; ^ Figure 3 is a plan view of the layer portion of the wafer of Figure 1C showing net lines; Figure 4 shows the layer portion of Fig. 1C for power distribution; Figure 5 shows a cell (2 in Fig. 1C) in more detail; Figure 6 shows a layer of the cell of Fig. 5 showing bonding pads in detail; Figure 7 is a further detail of Fig. 5; Figure 8 shows a cross section of Fig. 5 through a cross-over between a pad line and a net line; Figure 9 is a diagr-amatic view of an interconnection between the pads; Figure 10 is a diagram of a cell (2) of Fig. ic showing how smaller chips can be bonded in the cell position; Figure 11 is another diagram showing how to mix chips; Figure 12 shows a strip layout. Turning to the drawings in more detail, it will be seen from Figure 1A representing prior art wafers that, as previously stated, they may be formed with an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer 1. Also disposed on the wafer 1 is a network 11- intercon¬ necting various circuits 10', shown as a die, with other integrated circuits, such as die 21, disposed in the array formed on the wafer for data transfer therebetween. O PI WIPO Terminals or nodes 12' exist in the network 11' for connection of ' the connections of the network with the various integrated circuits 10'. The networks are connected via a lead to one or more contact pads 13' , for power and for data entry. My invention as shown in Figure IB departs from this Prior Art by the provision of a connection of measured distance to an auxiliary lead 160, 180, 200 and associated pad 16' , 18' , 20' for each network which is to be tested. This test lead 160 is connected to test pad 16' and to a terminal 12' of the network 11'. The test connection in the form of auxiliary leads 160, 180, 200 and their pads is formed on the wafer,as by diffusion, during the process of manufacture of the wafer and the integrated circuits disposed thereon. Preferably, the test connection is formed by a line approximately ten (10) microns in width and of the same thickness as the other lines of the network, approxi¬ mately one (1) micron in thickness. It should be here noted that since the usual wafer has a diameter of about 15 centimeters, a line across this diameter would pass a signal in a propagation time of less than one nanosecond. Since the distance between the test pad 16' and the terminal node 51 of the die position 21' of the network is a known distance for those wafers made with the same mask, the resistance of the net 11' with test connection line is also known, within an acceptable variance. For instance, a line of these dimensions, should it extend all the way across the wafer would have approximately an inherent resistance of 100 ohms, and a connection which is two thirds of the diameter would be approximately 66 ohms. In practice, the accepted parameters of any predetermined line can be measured electrically, by calculation from a test of a known wafer. Thereafter, it will be possible to test all like wafers against this standard to determine whether there is an acceptable network. Testing of the wafer, now can be accomplished with a known wafer tested, using the method which I would outline herein. Utilizing a node 51 of the die position 21' to which probe 50 point contact can be made to the network and the pad 16' as an example, the inherent resistance from node 51 to test pad 16' can be measured. The testing node 51 can be grounded at 16' by a grounding device, preferably a conductive elastomeric ring 17' which is connected to ground. It will be noted the elastomeric gasket grounds all terminal pads. If a normal 50 ohm resistance of the point against ground is to be expected and the normal 50 ohm resistance is found to be present, or within an acceptable variance, the network is proved. However, if there is a very high resistance, then an open circuit within the network is shown. If only a 20 ohm resistance is found, then it knows that there is a short to another network on the wafer. The wafer can be completely tested by utilizing existing probes which previously have been utilized to test each die on the wafer. The same point which will be probed by the probe point on the die "will be the position of the network test node 51. Each network has suitable test pads 16', 18', 20'. The elastomeric conductor ring interconnects all test pads to ground. By stepping from one die position to another, a test can be made of the entire wafer. Ox.ϊPI Now, in my preferred embodiment, as shown in Figures IB I bond dice to the network wafer as at die position 100 after the network wafer itself has been tested. This is accomplished by known bonding tech- niques (gold bump, solder ball, etc.), the type of bond being immaterial. The important point is that an already tested die is bonded to its proper position in an already tested network wafer. The resultant wafer is a hybrid circuit. Figure 1C is a plan view of a wafer 1 showing how the available area may be divided up into inner- cells 2, outer cells 3, logic line hookup areas 4, and power hookup areas 5. Figure 2 shows horizontal pad lines 6 and vertical pad lines 7 crossing a number of cells in such a way that each pad 8 can be connected to its own pad line. Outer cells are crossed by either horizontal or vertical pad lines. Inner cells are crossed by both horizontal and vertical pad lines. Figure 3 shows horizontal net lines 9 and vertical net lines 10 which cross all cells in such a way that each horizontal pad line 6 is crossed by each vertical net line 10 and each vertical pad line 7 by each horizontal net line 9. Each horizontal net line 9 is connected permanently to exactly one vertical net line 10 and to exactly one contact pad 27 in one of the hookup areas 4. Thus, all pad lines cross all nets and all nets can be externally accessed. Figure 4 shows a power grid 11 for a two rail power distribution system. Each cell is crossed by both rails three times in both the horizontal and vertical directions. The power rails are connected to a pair of contact pads 12 in each power hookup area 5. -* Figure 5 shows an inner cell with some more detail. Power grid 11, bonding pads 8, pad lines 6 & 7, and net lines 9 & 10 share the available space in such a way that only two . etal planes are needed and that no wires are found under a bonding pad. Figure 6 shows that a cell contains main bonding pads 14 and auxiliary bonding pads 15. Only main pads command their own pad lines as shown in Figure 2. An auxiliary pad is connected to a next neighbor main pad. Figure 7 shows a detail 13 as it may be found in Figure 5. The narrow lines are pad lines 6 and 7, and the wide lines are net lines 9 and 10. Cross-overs between pad lines are insulated. Cross-overs between net lines are generally also insulated except that each horizontal net line is connected through a via hole 16 at one point to a vertical net line. Cross-overs between pad lines and net lines have a via hole 17 cut into the insulator between the metal layers for a connection in between. Figure 8 shows a cross section through a cross- over between a pad line and a net line. Lower level metal 19 is generally separated from upper level metal 20 by the insulator 21 except for the via hole within the insulation where the metals are interconnected if appropriate for design. Figure 9 shows how the desired interconnection between three pads 8 is made by selecting two orthogonal net lines 9 & 10 which are permanently connected to each other by via hole 23 between the applicable pad lines 6 & 7 and the chosen net. Figure 10 shows how smaller chips 24 & 25 which require less area and a smaller number of pads OMFI y (A>7 then provided by a cell can be accommodated effi¬ ciently. Some unused pads 15 are buried under the chip. Power connections 26 are made directly to one of the power rails and not to a pad 8. Figure 11 shows how a mixture of chips which require larger, equal, and smaller areas than provided by a cell can be accommodated. The numbers within the chip symbols indicate maximum size and available logic signal pads. Figure 12 shows how the strips containing the power buses and the bonding pads are layed out. From the above, it will be seen that the draw¬ ings disclose a substrate 1 which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal 19, 20, Hius providing two principal levels of interconnection. An insulation layer 21 is placed between the metal layers and also between the lower metal layer and the substrate if the latter is con- ductive. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layer or layers, respectively. The real estate provided by the substrate 1 is divided up into special areas used for inner cells 2 outer cells 3 signal hookup areas 4 and power hookup areas 5. In one preferred embodiment, the substrate may be a disk with a diameter of 75mm, the cells may be squares with edges of 9mm, the signal hookup areas may be rectangles with sides of 4.5mm and 36mm, and the power hookup areas may fill out the remaining space at the "corners". OMFI The cells are intended to host the integrated circuit chips 24, 25 and to provide the bonding pads 8 for the signal connections between the chips and the substrate. In the preferred embodiment, the inner cells provide sixty-four signal pads each so that LSI chips with up to sixty-four leads and with a physical size of up to 8mm by 8mm can be accommodated. Chips which are substantially smaller than the possible maximum in terms of physical size and signal leads can share a cell as shown by example in Figure 10. Since bond wires cannot jump over a neighbor chip to find a substrate bonding pad, auxiliary pads 15 are provided which are connected with the main pads 14 through the substrate (Figure 6). Over-size chips which are either larger than 8mm by 8mm or which require more than sixty- four bonding pads can be stretched over 2 or more cells or any quadrants thereof. Figure 11 shows some exam¬ ples. The maximum chip size and number of available bonding pads is inscribed within the outline of a chip. it is also possible that bonding pads can be borrowed from another cell or quarter cell along the common edge between 2 cells. Since some pads will be buried under the chips, the back of the chips is insulated from these pads by suitable means as, for instance, chip bonding with non-conductive epoxy. All in all, it can be seen that the substrate can be universally used for any combination of chip sizes. Some chips, particularly dynamic MOS RAM chips, have the unique characteristic that their aspect ratio is approximately 2:1 and that the chip bonding pads are located along the 2 smaller sides of the chip. Such chips can be accommodated more economically by reduced- cells which provide bonding pad only in one direction. Such cells are shown in the preferred embodiment as outer cells. They are derived from complete cells by omitting either the horizontal or the vertical rows of bonding pads. RAM chips would be placed into an outer cell-like chip 25 shown in Figure 10 except that all vertical pad columns on the chip as well as on the substrate would have been eliminated. Power supply connections have been separated from logic signal connections because they must provide lower series resistance. Since it is not known in advance where the power inputs of a particular chip may be located, it is not possible to assign power pads on the substrate. This problem has been solved by pro- viding 2 power buses 11 along the edges and along the center lines of all cells. A chip power pad which may be located anywhere along the edge of the chip can now be connected to a power bus instead of a substrate pad with a bond 26. The power buses form a power grid over the entire substrate as shown in Figure 4. The width of a power bus may be 350^ m. If implemented with Ifl m- thick aluminum, which yields a sheet resistivity of 30mCL/E3 , the longitudinal resistance would amount to 86m∑l/mm. If the actual loads are known, the voltage drops in the power system can be computed accordingly. For a general approximation, one can work with a "power sheet" instead of a "power grid", whereby the equiva¬ lent power sheet resistivityJis derived from the actual sheet resistivityJo by multiplying it with the ratio between cell width and bus width. § If a disk with the radius R is loaded over its entire surface with a current density j, and if the periphery of the disk is held at ground potential, then the point with the highest potential is found at the center of the disk and the voltage U between the center and the periphery is found to be 4 • ζ = .257.0, / 2R = 75mm, and j = Io/(9mm) yields U = 1.12.Q.*!©. Thus, for a load of 1 amp per cell, the voltage drop from the power hookup to the center of the wafer would be approximately 1 volt. One has now to consider two -basic types of circuits: "symmetrical circuits" as, for instance, CMOS and "unsymmetrical circuits" as, for instance, NMOS. For symmetrical circuits, which have a threshold centered between the power rails, the power grid as described so far is adequate. The supply voltages at the substrate edge may be 0 and +5 volts. The threshold would then be set by a chip-internal voltage divider to approximately 2.5 volts. A chip at the center would see voltage drops of approximately 1 volt at each power rail, i.e., the power input voltages would be +1 and +4 volts. The threshold of the circuit at the center would again be halfway between the power rails, i.e., at +2.5 volts so that all circuits on the wafer could properly communicate with each other. In unsymmetrical circuits, all thresholds are referenced to one of the power rails (usually ground) and more or less independant from the other power rail. In this case, the voltage drop along the reference rail ust be relatively small. This can be accomplished by using a solid ground sheet under the two metal layers discussed above and by making via connections between the ground grid and this sheet at several points per cell. If the ground sheet is comprised of a conductive silicon wafer with an additional layer of 2 *. m-thick aluminum a sheet resistivity of lOmH/π may be accom¬ plished. Based on the same formula used above, the maximum voltage drop can be estimated to be U = 0.04∑L *io or approximately 0.04 volts for cell currents of 1 amp each. This value is acceptable for most circuits. The next problem to be solved by this inven¬ tion is to interconnect all substrate pads with . each other in any possibly desired way and also to connect any or all pads to the outside world. This is accom¬ plished by a set of pad lines 6, 7 and a set of net lines 9, 10. A pad line is permanently connected to exactly one pad 8. Thus, there are as many pad lines on the substrate as there are pads, whose number is 16*64 + 16*32 = 1,536 in the preferred embodiment. A pad line is routed either horizontally or vertically across the substrate for a certain distance. As can be seen in Figure 2, the principal wiring pattern is such that, if a horizontal set of pad lines serves n columns of pads, there must be (n -1) pad lines passing between two pads of one and the same column. Net lines are also routed either horizontally or vertically across the substrate. One horizontal net line 9 and one vertical net line 10 are permanently connected to each other, thus forming a net. Each net is connected to one contact pad 27 in one of the hookup areas 4. One preferred embodiment of the invention provides a total of 288 nets. Since the hookup areas are 36mm long, the resulting contact pitch is 0.5mm. Another preferred embodiment provides 432 nets, causing a 0.33mm pitch for the peripheral contacts 27. The combined routing pattern of pad lines and net lines is such that each pad line crosses each net exactly one time, which can be seen by combining Figure 2 and Figure 3. A number of pads can now be connected to each other by choosing a net and by making connec¬ tions at the cross-over points between this net and the respective pad lines (Figure 9). If one assumes that no more than 1,300 of the 1,536 available pads are actually used, the number of 288 nets would be adequate if the average fan-out is larger than 1,300/288 -1 = 3.5. Accordingly, 432 nets would be adequate for an average fan-out of ,at least 2. Once an adequate number of nets have been chosen, one can truly say that all thinkable pad interconnection patterns can be derived from one standard set of lines. In the preferred embodiment, the length of a pad line is 33mm, and the length of a net line is approximately 42mm (from one end to the farthest possible via) . If the sheet resistivity of the metal is 30mfl/π , the longitudinal resistivity of a 10/4 m wide pad line would be 3_θL/mm and that of a 20A* m wide net line would be 1.5/1/mm. The total resistance of a pad line amounts then to 100H and that of a net line to 63f . The longest possible interconnection from, say, a pad in the upper left corner to a net line at the far right, then down to the net line at the bottom, then to the far left side, and finally up along another pad line to another pad in the upper left corner would amount to 326X1., a large value for a line between two pads which are located close to each other. An average connection would, of course, be much better. The best connection, however, is realized by choosing a net whose junction between its horizontal and vertical net lines is as close as possible to the pads which have to be tied together. It is, therefore, part of this invention to arrange the junctions 23 between the net lines not on a simple diagonal line as indicated for the small representative number of lines in Figure 3, but rather in such a way that they are evenly distributed over the total field of inner cells. This provides a high probability that a net with a close-by junction can be found in all cases. The average connection length should thereby be reduced to about 1/5 of the raaximum or to approximately 70-1. The actual programming or firing of a cross-over between a pad line and a net line can be done by a normal via hole. The method could be called "mask programming" as the term is applied in prior art to ROM chips. The disadvantage of this method is that a new via hole mask must be prepared for each new interconnection pattern and that, therefore, a large number of different part numbers must be handled in the manufacturing process. The advantage is that, in case of large volumes per part numbers, the simple via reduces manufacturing costs over other methods and that the direct via does not introduce substantial series resistance. Pads 18 used in another context are shown in Figure 7 and Figure 8 only in those locations where they are needed for a programming function. For the convenience of processing and other considerations, however, the pad area can be extended. Particularly, all pads in a vertical column can be made as contiguous strips, running in parallel under the upper level metal lines. A net line can be tied to more than one pad line, but a pad line can only be tied to one net line. Pads, pad lines, net lines, and power buses share the available space in the two metal layers as shown in Figure 5. All pads 14, 15 are placed in the upper layer so that bonds can be made. The lower level space under the pads is not used because bonding may cause tiny cracks in the insulator which could lead to shorts with the lower layer metal. The power buses 11 are also part of the upper layer so that bonds can be made to it. An exception is the cross-over between two buses. Here, one bus dives through under the other bus. Net lines 9, 10 do not need to come to the surface except for the contact pads 27 in the contact areas 4. Horizontal net lines 9 may be placed into the lower layer as indicated in Figure 7. They dive through under the power grids and avoid the bonding pads. Vertical net lines 10 may be placed in the upper layer. At the edge of the open fields between the power grids they have to dive to the lower layer so that they can also pass the grids. Note that the required lower level space is available because no other horizontal lines run under the power grids. Horizontal pad lines 6 run in the lower level just as the horizontal net lines 9 except that a via connection must be made to the bonding pads 14, 15. Note that the pad lines do not run under the bonding pads but rather in the space between them though lines and pads are in different layers. This is accomplished by fitting the pads between the lines as sketched in Figure 2. The auxiliary pads 15 which have not been shown in Figure 2 _O PI WIrO can be connected the same way because they are topo- logically adjacent to their respective main pads 14. The vertical pad lines 7 are placed together with their pads into the upper layer but must dive together with the vertical net lines in order to pass the horizontal power buses. The auxiliary pads 15 are connected to their respective pad lines through vias. Outer cells have the same power grids but only one-half of the net and pad lines is shown in Figure 2 and 3. Their wiring pattern is a direct subset of that used for inner cells. The space of a 9mm cell may be allocated to the major areas as shown in Figure 5: 0.89mm each for the edge strips containing main bonding and two power buses, 0.9mm for the center strip containing auxiliary pads and two power buses, and 3.16mm each for the fields which contain each 8 pad line strips and 9 net line strips. The edge and center strips may be divided down further as shown in Figure 12. A net line strip which is 120 A m wide can be used either for four 20/ι -lines and four 10 * m-spaces or for six 10 ι m-lines and six 10/ /m-spaces. A pad line strip which is 260/4 m wide can be used for one 1204 m pad, seven 10 * m-lines, and seven 10 A m spaces. While I have discussed hybrid circuits in detail, the pattern discussed using auxiliary lead lines to test the network may be used when chips are formed on the wafer. It is possible using known techniques, as by electron beam pattern generation, to make both the dice and the networks on the same wafer. Here testing of the dice is tested by die to die pro¬ gression in accordance with U.S. Patent 4,183,460 of January 15, 1980. Preferably, before proceeding to the next die, the tester for the die 21' is programmed to switch to the network test mode and the individual probe at point 51' is used as a control while the pad 16' is used as ground through the elastomeric gasket 17'.

Claims: AMENDED CLAIMS (received by the Internatinal Bureau on 18 May 1982 (18.05.82)) ) 29. A substrate for intercoupling pads of one or more integrated circuit chips which, are adapted to be mounted on said substrate comprising: a support, substrate providing on the surface thereof a plurality of chip bonding positions as chip cells, each, of said cells being provided with at least a power supply bonding point, and a plurality of logic signal connection bonding points, said cells and their associated bonding points being arranged on the surface of said substrate so as to accept a variety of chip sizes permitting a plurality of chips to be bonded thereto at one or more than one cell for each chip; and conductive electrical distribution means beneath the surface of said substrate and coupled to said bonding positions for providing a power and logic distribution network for said chips. O F 30. A substrate for integrated circuits according to Claim 29 further comprising; a silicon wafer support having therein a conductive grounding member; - an insulation layer; a reticulate array of conductors on • said insulation layer; said reticulate array of conductors having a first plurality of logic net lines arranged in substantially parallel directions across said substrate; said reticulate array of conductors having a second plurality of logic net lines arranged in substan¬ tially parallel direction across said substrate and crossing said first plurality of logic net lines; said first and said second plurality of logic net lines being separated by non-conductive material between others of the same plurality of logic net lines and the other of said plurality of logic net lines; means for coupling one of said first plurality of logic net lines with one of said second plurality of logic net lines so as to thereby define an electrically conductive network across both directions of said logic net lines; said reticulate array of conductors also providing a plurality of separate pad lines traveling across said substrate, each of said plurality of separate pad lines being electrically insulated from interconnection with other of said plurality of separate pad lines, and each of said pad lines being connected to bonding pads located at the surface of said substrate; means for coupling a single pad line to a single logic net line; means for coupling net lines to logic hook-up pads located on the surface of said substrate; said power distribution network having power hook-up areas across the surface of said substrate and to power hook-up pads located at the surface of said substrate; means for interconnecting net lines into a desired logic network whereby signal bonding pads of the surface of said substrate are coupled for signal transmission therebetween through said network of logic net lines; 31. A substrate according to Claim 29 or 30 in combination with integrated circuit chips; the interconnections between pads on the substrate and the integrated . circuits being made by downbonding connection; and the integrated circuits are face up on the substrate and downbonded thereto. 32. A substrate for integrated circuits according *. * • to Claim 29 further comprising; a silicon wafer support having a conductive grounding member; an insulation layer; a reticulate array of conductors on said insulation layer, said reticulate array of conductors having a plurality of logic net lines arranged in substantially parallel directions across said substrate; said reticulate array of conductors having a second plurality of logic net lines arranged in substantially parallel direction across said substrate and crossing said first plurality of logic net lines; said first and said second plurality of logic net lines being separated by non-conductive material between others of the same plurality of logic net lines and the other of said plurality of logic net lines; means for coupling one of said first plurality of logic net lines with one of said second plurality of logic net lines as to thereby define an electrically conductive network across both directions of said logic net lines; said reticulate array of conductors also providing a plurality of separate pad lines traveling across said substrate, each of said plurality of separate pad lines being electrically insulated from interconnection with other of said plurality of separate pad lines, and each of said pad lines being coupled to bonding pads located at the surface of said substrate; means for coupling a single pad line to a single logic net line; means for coupling net lines to logic hook-up pads located on the surface of said substrate; power distribution means having power hook-up areas across the surface of said substrate and to power hook-up pads located at the surface of said substrate; means for interconnecting net lines into a desired logic network whereby signal bonding pads of the surface of said substrate are coupled for signal transmission therebetween through said network of logic net lines. 33. A substrate according to Claim 29 wherein the interconnections between pads on the substrate and the integrated circuits being adapted to be made by a down- bonding connection. 34. A substrate according to Claim 29 wherein said substrate has a plurality of modular cells on its surface adapted to receive said integrated circuits face up on. the substrate. 35. A substrate for integrated circuits according i to Claim 29 wherein: said support substrate includes a support member which is electrically conductive and suitable for integrated circuit processing during the process of manufacture of said substrate; an insulation layer on said support member; network definition means on said insulation layer; power distribution means on said insulation layer; a plurality of bonding pads at the surface of said substrate; an interconnection coupling means coupled to said power distribution means, said network definition means and to said bonding pads for defining the interconnection therebetween; said plurality of bonding pads including a first set of power .bonding pads and a second set of signal bonding pads each adapted to be coupled to corresponding pads of said integrated circuits; said interconnection coupling means including programmable coupling elements which are adapted to be programmed to define the networks which are desired for interconnection of said integrated circuits; and said interconnection coupling means providing in combination with said network definition means and said power distribution means and said bonding pads a universal interconnection matrix for a variety of standard integrated circuits. 36. A substrate according to Claim 29 adapted to interconnect contact point's of integrated circuitry, further comprising: a reticulate array of conductors included in said electrical distribution means and adapted for being intercoupled to said bonding points; and programmatically defined means within said reticulate array for interconnecting said predetermined conductors to form a desired electrically conducting network between said bonding points located on said support element. 37. A substrate for integrated circuitry according to Claim 29 wherein said support substrate has a plurality of contact pads located at the surface thereof; said electrical distribution means including a reticulate array of conductors adapted for interconnection to said contact pads; and means which have been programmatically defined for interconnecting said contact pads to said conductors for forming a desired electrically conducting network between contact pads of said support substrate. 38. A substrate for integrated circuits according to Claim 29 further including: a member of said substrate which is suitable for integrated circuit processing during the process of manufacture of said substrate; an insulation layer on said member; said conductive electrical distribution means including network definition means on said insulation layer; power distribution means on said insulation layer; a plurality of bonding pads at bonding points at the surface of said substrate; interconnection coupling means coupled to said power distribution means, said network definition means and to said bonding pads for defining the interconnection therebetween; said plurality of bonding pads including a first set of power bonding pads and a second set of signal bonding pads each adapted to be coupled to corresponding pads of said integrated circuits. 39. A substrate according to Claim 38 wherein said network definition means and said power distribution means are disposed in a reticulate array of conductors. 40. A substrate according to the preceding Claim 36 wherein said reticulate array includes a first set of conductor lines disposed in a first direction; a second set of conductors disposed in a second direction; said first set of conductor lines and said second set of conductor lines crossing one another in spaced relationship; and at least one of said first set of conductors being connected to at least one of said second conductors. 41. A substrate according to the preceding Claim 40 wherein said second set of conductors is connected to at least one other of said first set of conductors for signal transmission between the first of said first set of conductors to the second of said first set of conductors. 42. A hybrid circuit comprising, in combination the substrate according to Claim 29 and a plurality of separate and discrete integrated circuit chips each having a plurality of bonding pads for connection to an external power source and for signal interconnection, each of said chips being configured to perform a predetermined usable function and bonding means for electrically defining said signal interconnection to predetermined bonding points on said substrate. 43. A substrate according to Claim 29 adapted to provide support and universal interconnection of said chips, wherein said substrate has a silicon support member; and an interconnection matrix of conductors on said silicon support with a plurality of bonding pads on the surface of said universal interconnection substrate adapted for coupling of said chips. 44. A substrate according to Claim 43 wherein said interconnection matrix of conductors has two layers of conductors separated by an insulator and being inter¬ connected through at least one mask programmably defined via in the insulator, whereby selected conductors are interconnected to each other and to at least one of said plurality of bonding pads on said surface of said universal interconnection substrate by a said mask programmably defined via interconnection. * -> 45. A substrate for integrated circuits, comprising * ■ a substrate, a plurality of binding points on said substrate adapted to be conductively bonded to integrated circuits to be mounted on said substrate, a network of conductors formed on said substrate and having means interconnecting at predetermined crosspoints selected ones of said conductors to form a desired network configuration by the intercoupling of network conductors, interconnection means interconnecting at least some of said bonding points with corresponding individual conductors of said network of conductors whereby each of said interconnection means forms the conductive path from its bonding point to said network. 46. A substrate according to Claim 45 in combina¬ tion with a plurality of separate integrated circuit chps each having a plurality of binding pads; said substrate having contained therein on a matrix formed on a silicon layer on which are disposed passive conductors which are electrically interconnected to bonding pads located on the surface of the said universal interconnection substrate; means for electrically bonding said chips to selected pads of said substrate whereby the selected interconnection of selected separate chips permits the selected integrated circuit chips to perform their separate functions in cooperation with other chips also electrically bonded to the surface of said substrate. 47. A substrate according to Claim 45 for supporting a plurality of discrete integrated circuits, including: a support wafer; - an insulating layer on said wafer; a reticulate array of conductors on said insulating layer, said reticulate array including; a first set of conductive lines oriented in a first direction; a second set of conductive lines oriented in a second direction; said first and said second lines being insulated from one another; means for interconnecting said first and said second line at selected cross points; said first set of said second set of conductive lines including a plurality of pad lines,, each of .said pad lines being connected to a bonding pad on the surface of the reticulate array of conductors; said first and said second lines including a plurality of net lines; each of said net lines being adapted to be connected to a pad line; means for providing a connection between each pad line and one of said net lines at a single desired location; means for interconnecting net lines to other net lines; said reticulate array of conductors also including power conductor means arranged to provide power to a plurality of bonding pads. O PI 48. A substrate according to Claim 45 including: a support subs : trate element which is electrically conductive and suitable for integrated circuit processing; e an insulating layer on said substrate; a reticulate array of conductors on said insulating layer, said reticulate array including; a first set of conductive lines oriented in a first direction; a second set of conductive lines oriented in a second direction; said first set of conductive lines crossing said second set of conductive lines; means interconnecting selected ones of said first set of conductors and said second set of conductive lines at selected cross points; a plurality of binding pads at the surface of said reticulate array and adapted to provide bonding connection points to integrated circuits which are to be interconnected to said reticulate array of conductors; power conduction means arranged to be coupled with some of the said bonding pads; and coupling means coupling a single conductive line of said reticulate array to a signal bonding pad. 49. A substrate according to Claim 45 including: a support member 1 which is suitable for integrated circuit processing during the course of manufacture of said substrate; an insulating layer on said support member; network definition means on said insulating layer, including a reticulate array of conductors on said insulating layer; a plurality of binding pads at the surface of reticulate array of conductor, including a first set of signal bonding pads and a second set of power bonding pads; coupling means for defining the intercon¬ nection of said array power conduction means arranged on said support member and supplying power to said power bonding pads. 50. A substrate according to Claim 45 including: a support member which is electrically conduct¬ ive and suitable for integrated circuit processing during the process of manufacture of said substrate; an insulation layer of said support member; network definition means on said insulation layer; power distribution means on said insulation layer; a plurality of bonding pads at the surface of said substrate; including a first set of power bonding pads coupled to said power distribuiton means and a second set of signal bonding pads adapted to be coupled to corresponding pads of said integrated circuits and adapted to be coupled to said network definition means; interconnection coupling means coupled to said power distribution means and to network definition means and to said bonding pads defining the intercon- nection therebetween; and said interconnection coupling means including mask programmed coupling elements which are mask programmed to define the networks which is desired for said integrated circuits. 51. A substrate according to Claim 50 wherein said reticulate array of conductors on said substrate includes a plurality of redundant conductors, the mask programming of vias in said insulating layer deter- mining which of said redundant conductors are used in said network of conductors. 52. A substrate according to Claim 51 wherein said reticulate array of redundant conductors comprises a power distribution network. OI.2FI 53. A substrate according to Claim 51 wherein said reticulate array of redundant conductors comprises a logic distribution network. 54. A substrate according to Claim 51 wherein said reticulate array of redundant conductors comprises a logic distribution network and a power distribution network. _,_\) 55. A substrate according to Claim 51 wherein said reticulate array of redundant conductors includes a logic distribution network and a power source. 56. A substrate according to Claim 50 wherein said substrate includes a power grounding element. 57. A substrate according to Claim 45 including: a base substrate having formed thereon a plurality of conductors programmably interconnected to form a network; said base substrate having located thereon a plurality of bonding pads arranged in a modular array so as to define a plurality of surface cells of bonding pads; said surface cells being adapted to form a signal connection bond cell for an integrated circuit to be coupled thereto; said bond cell being formed of pads of one or more of said surface cells with said conductors. OMPI ' 58. A substrate according to Claim 45 including: a support member which is electrically conductive and suitable for integrated circuit processing during the process of manufacture of said substrate; an insulation layer on said support member; network definition means on said insulation layer; ) power distribution means on said insulation layer; a plurality of bonding pads at the surface of said substrat ; an interconnection coupling means coupled to said power distribution means, said network definition means and to said bonding pads for defining the interconnection therebetween; said plurality of bonding pads including a first set of power bonding pads and a second set of signal bonding pads each adapted to be coupled to corresponding pads of said integrated circuits; said interconnection coupling means including mask programmed coupling elements which are programmed to define the networks which are desired for intercon¬ nection of said integrated circuits; said network distribution means including a reticulate array of conductors coupled to said signal bonding pads. OMPI 59. A substrate according to Claim 45 including: a silicon wafer; a first . layer of patterned conductors deposited and patterned on said wafer; - a layer of insulation deposited on said wafer and mask programmed to define interconnection vias for said patterned conductors of said first layer; and a second layer of patterned conductors deposited and having via connection through said insulating layer at cross points of interconnection with said first layer of patterned conductors. 60. A substrate according to Claim 45 including: a conductive substrate; a plurality of bonding pads on the surface of said substrate and adapted to be electrically connected to corresponding bonding pads of chips to be bonded thereto; a corresponding number of pad lines intercon¬ nected; a signal network, each connected at only one point to one of said pad lines. GMFI 61. A substrate according to Claim 45 including: a substrate having a top side and a bottom side; an insulation layer deposited on said top side; an interconnection matrix formed on the surface of said insulation layer; said insulation matrix having an upper contact surface at which a plurality of bonding pads are exposed and adapted to be electrically connected to corresponding bonding pads of chips to be bonded thereto; each of said bonding pads being connected to pad lines within said interconnection matrix; said interconnection matrix having disposed therein a plurality of net conductors; each of said pad lines being connected at only one point to a net conductor such that there is only one connecti.on between a single pad line and the network of conductors; the signal conductors being connected to at least one pad line. CMFI ~ 62. A substrate according to Claim 45 including: * a substrate having a top side and a bottom side; an interconnection matrix providing an upper - contact surface having a plurality of bonding pads exposed which are adapted for electrical connection to corresponding connection points of integrated circuits which are adapted to be connected thereto; said interconnection matrix including a plurality of pad lines which of which is connected to a single bonding pad and having a plurality of net lines each of which is adapted to be electrically connected to a pad line; and ~ via means for defining a single connection between said pad line and one of said net lines whereby a pad line is the sole interconnection between its bonding pad and said one of said net lines. 63. A substrate according to Claim 62 wherein the substrate includes: an insulation layer deposited on the top side of said substrate and beneath said interconnection 5 matri . Oϊ.'-FI 64. A substrate according to Claim 45 including: ϊ a support member ' which is suitable for integrated circuit processing during the process of manufacture of said substrate; an insulation layer on said support member; network definition means on said insulation layer; power distribution means on said insulation layer; a plurality of bonding pads at the surface of said substrate; an interconnection coupling means coupled to said power distribution means, said network definition means and to said bonding pads for defining the interconnection therebetween; said plurality of bonding pads including a first set of power bonding pads and a second set of signal bonding pads each adapted to be coupled to- corresponding pads of said integrated circuits; said interconnection coupling means including coupling elements which are adapted to define the networks which are desired for interconnection of said integrated circuits; and the surface of said substrate being defined by areas of inner cells, outer cells, logic line hook-up areas and power hook-up areas. 65. According to Claim 64 wherein said power distribution means provides conductive lines for each of said inner cells and said outer cells, said conductive lines passing to said power hook-up areas - which are provided with said power bonding pads adapted to supply power to said power distribution means and thereby to provide power to said integrated circuits which are adapted to be electrically bonded to said power distribution conductive lines . 66. A substrate according to Claim 45 including: a silicon support member; a conductive grounding member; a first insulation layer; a reticulate array of conductors defining network distribution means and power distribution means; and s ' aid reticulate array of conductors providing by said power distribution means coupling elements between bonding pads located on the surface of said substrate and to integrated circuits adapted to be electrically coupled to said power distribution means, and in addition by said network distribution means providing a network for interconnection of a plurality of signal pads located on the surface of said substrate and adapted to be electrically coupled to corresponding signal pads of said integrated circuits. 67. A substrate according to Claim 45 wherein said substrate is: a universal interconnection substrate having a plurality of network configurations formed thereon and having means configuring the substrate to form a desired interconnection between bonding pads located at the surface of said substrate; and bonded to said substrate are a plurality of discrete integrated circuit chips bonded to the surface of said substrate and having bonds made to selected bonding pads of said substrate, thereby forming a hybrid circuit having said desired interconnection substrate. 68. A substrate according to Claim 45 including: a silicon wafer support member; a conductive grounding member; a first insulating layer; a conductive power distribution means; a second insulating layer; bonding pads including signal pads and power pads; pad lines and net lines; and via means providing an electrical coupling of conductive members selected from elements of said defined substrate. OMPI 70. A substrate according to Claim 45 including: i a support member : which provides electrically conductive means and is suitable for integrated circuit processing during the process of manufacture of said substrate; an insulation layer on said support member; network definition means on said insulation layer; power distribution means on said insulation layer; a plurality of bonding pads at the surface of said substrate; an interconnection coupling means coupled to said power distribution means, said network definition means and to said bonding pads for defining the inter¬ connection therebetween; said plurality of bonding pads including a first set of power bonding pads and a second set of signal bonding pads each adapted to be coupled to corresponding pads of said integrated circuits; and said interconnection coupling means including coupling via elements which define the networks which are desired to interconnection of said integrated circuits. 71. A substrate according to Claim 45, including: a silicon wafer support member; a conductive grounding member; a first insulation layer; a conductive power distribution means; a second insulation layer; a plurality of bonding pads including a first set of signal bonding pads and a second set of power bonding pads; and * network distribution means; the surface of said substrate defining a plurality of cells; said signal bonding pads being arranged about the surface of said substrate; said power bonding pads being arranged at the surface of said substrate; said conductive power distribution means being interconnected to said power bonding pads and providing contact points .which ' are adapted to be bonded to integrated circuits arranged on the surface of said substrate at power pads of said integrated circuits; said signal bonding pads being adapted to be bonded to said integrated circuits arranged on the surface of said substrate at signal bonding pads of said integrated circuits; said network distribution means including: a plurality of spaced net lines and a plurality of pad lines; each of said pad lines being connected to a single signal bonding pad; each of said pad lines being connected to a single net line; said net lines providing a coupling between pad lines and their signal bonding pads; and coupling means for defining which pad lines and net lines are intercoupled. 72. According to Claim 71 wherein said coupling means are programmatically determined during the process of manufacture of said wafer. 73. A substrate according to Claim 45 including: a base substrate having formed thereon a plurality of conductors adapted to form a network when intercoupled; said base substrate having located thereon a plurality of bonding pads arranged in a modular array so .as to define a plurality of surface cells of bonding pads; said surface cells being adapted to form a signal connection bond cell for an integrated circuit to be coupled thereto; said bond cell being formed of pads of one or more cells of said modular array; means of inter.coupling pads of one or more of a said surface cells with said conductors to thereby form a network; said means for intercoupling said conductors to thereby form said network. 74. A substrate according to Claim 73 wherein said modular array is adapted to allow bonding of a plurality of sizes of chips to the base substrate so as to permit chips of different types and sizes to be mounted on said substrat . OMPI 75. A substrate according to Claim 45 for inter- coupling pads of one or more integrated circuit chips which are adapted to be mounted on said substrate including: a support substrate; conductive electrical distribution means on said substrate including a plurality of conductors which define at least one cross point between said conductors; means on the surface of said substrate for providing bonding positions for one or more integrated circuit chips which are adapted to be mounted on said substrate, said means on the surface of said substrate including a plurality of bonding points; intercoupling means located at a cross point between conductors which thereby define the electrical interconnection between said conductors and said chips which are adapted to be coupled to said conductors by being bonded to said bonding points. 76. A substrate according to Claim 74 wherein said support substrate is a silicon substrate. 77. A substrate according to Claim 74 wherein said conductive electrical distribution means define a universal interconnection matrix of conductors. 78. A substrate according to Claim 74 wherein said conductive electrical distribution means includes a plurality of signal conductors. 79. A substrate according to Claim 74 wherein said conductive electrical distribution means includes a power distribution means. VIFO 80. A substrate according to Claim 74 wherein said conductive electrical distribution means includes a plurality of logic signal conductors and power distribution means. 81. A substrate according to Claim 74 wherein the surface is provided with a plurality of cells providing a bonding area and power supply connection points and signal connection points for chips adapted to be bonded thereto. 82. A substrate according to Claim 81 wherein a plurality of said cells which have at least some of their power supply points and their signal connection points are arranged to provide an intercouupling network for a variety of chip sizes including some of which chips require more bonding area than provided by other chips of smaller sizes. _ C ' 83. A substrate according to Claim 45 for inter- coupling bonding pads of one or more integrated circuit chips which are adapted to be mounted on said substrate including: a support element; a reticulate array of conductors on said support element each of said conductors being electrically insulated from others of said conductors except at predetermined electrically conductive cross points betweeen at least some of said conductors, said reticulate array of conductors including pad lines, net lines and power distribution lines; at least one surface area on said support element defining a chip bonding area as a cell having a power distribution supply point and a plurality of bonding pads situated at the surface of said -support element, said bonding pads being each coupled to a single corresponding pad line, and means for intercon¬ necting a single pad line with a single net line, and means for interconnecting a net line with one or more other net lines to define a logic distribution network; signal connection points for chips adapted to be bonded thereto. 84. A substrate according to Claim 83 wherein a plurality of chip handling areas are provided defining cells which have at least some of their power supply points " and their signal connection points arranged to provide an intercoupling network for a variety of chip sizes including some chips which require more bonding area than provided by other chips of smaller sizes. O:. * IFI 85. A substrate according to Claim 45 for inter- coupling bonding pads of ' one or more integrated circuit chips which are adapted to be mounted on said substrate including: a support element; a reticulate array of conductors on said support element each of said conductors being electrically insulated from others of said conductors except at predetermined electrically conductive cross points between at least some of said conductros, said reticulate array of conductors including pad lines, net lines and power distribution lines; at least one surface area on said support element defining a chip bonding area as a cell having a power distribution supply point and a plurality of bonding pads situated at the surface of said support element, said bonding pads being each coupled to a single corresponding pad line, and means for intercon¬ necting a single pad line with a single net line, and means for interconnecting a net line with one or more other net lines to define a logic distribution network; wherein there are a plurality of chip bonding area cealls on said support element; wherein said plurality of chip bonding cell areas are arranged together with their bonding pads to enable bonding of chips of different sizes to said support element utilizing bonding pads of one or more cell areas. C FI 86. A substrate according to Claim 45 wherein said substrate is adapted to provide support and intercon¬ nection of said chips, and for providing at least a power connection to an external source of energy.

Inventors: STOPPER HERBERT
Applicants: JOHNSON ROBERT ROYCE
Application year: 1981
Main classification: G01R31
IPC codes: G01R31, H01L21, H01L23, H05K1