I2L SEMICONDUCTOR DEVICE

Abstract: A semiconductor device includes a linear circuit section including a vertical npn transistor (TR4) and an I²L circuit section including a set of an injector pnp transistor (TR6) and an inverter npn transistor (TR5), these transistors being formed on the same wafer (30, 36) as for the vertical transistor (TR4). The inverter and injector transistors (TR5, TR6) are both lateral transistors.

Description: Semiconductor device This invention relates to integrated injection logic (I2L) semiconductor devices. The 12L circuit is a bipolar digital circuit realized by a semiconductor device of high integration density and low consumption power. The 12L semiconductor device has an advantage that a linear circuit section can be integrated together with an 12L circuit section on the same chip. For this reason, various 12L semiconductor circuits are extensively used for home and industrial large scale integrated circuits (LSI) for which both the linear and digital functions are required. Recently, the application field of the LSI has been further extended, and there are demands for the 12L digital circuit section to operate at higher speeds and for the linear circuit section to operate at higher voltages. Basically, the 12L circuit operates at a low voltage (about 0.7 V) and requires a thin epitaxial layer section in the substrate of a semiconductor device which constitutes this circuit. However, the emittercollector breakdown voltage of an npn transistor in the linear circuit section that is formed together with the 12L circuit section using the substrate having a thin epitaxial layer, is about 10 V. Therefore, it is impossible to obtain as high breakdown voltage as 30 to 50 V required for usual purposes. A bipolar integrated circuit that satisfies the required characteristics of both the 12L circuit section and linear circuit section is therefore complicated in manufacture and high in manufacturing cost. For example, when manufacturing a semiconductor device including a high breakdown voltage linear circuit section and a high speed I2L circuit section formed on the same chip as shown in Fig. 2, an epitaxial wafer as shown in Fig. 1 is used. This epitaxial wafer is formed by diffusing n-type impurities at a high impurity concentration into the surface region of a P'-type substrate 1 to form a burried layer 2, epitaxially growing n-type semiconductor layer 3 to a thickness tl on the substrate 1 and the burried layer 2, forming an n+-type burried layer 4 in the surface region of the epitaxial layer 3 not overlapping the burried layer 2, and forming an n-type semiconductor layer 5 to a thickness t2 on the epitaxial layer 3 and the burried layer 4. The circuit construction as shown in Fig. 2 may be fabricated using the semiconductor wafer of Fig. 1. A vertical npn transistor TR1 constituting the linear section circuit is formed in a region including the burried layer 2, and lateral npn transistor TR2 and vertical npn transistor TR3 constituting the 12L circuit section are formed in a region containing the burried layer 4. A p-type region 6 is formed in the surface region of the epitaxial layer 5, an n+-type region 7 is formed in the P-type region 6, and an n-type diffusion region 8 is formed to extend from the surface of the epitaxial layer 5 to the burried layer 2. Electrodes 10, 11 and 12 are formed in connection with the respective regions 6, 7 and 8. An n+-type diffusion region 14 is formed by diffusion to extend from the surface of the epitaxial layer 5 to the n+-type region 4. P-type regions 15 and 16 are formed in the surface regions of the epitaxial layer 5 enclosed by the diffusion region 14. These regions 15 and 16 are slightly spaced apart. An n-type region 17 is formed in the p-type region 16. Electrodes 18 to 21 are formed in connection with the respective regions 14 to 17. The linear circuit section and 12L circuit section are isolated from each other by p+-type region 22 formed to extend from the surface of the epitaxial layer 5 to the substrate 1. Fig. 3 shows the equivalent circuit of the npn transistor TR1 constituting the linear circuit shown in Fig. 2. Fig. 4 shows the equivalent circuit of the npn transistor TR2 and npn transistor TR3 constituting the 12L circuit section shown in Fig. 2. The electrode 18 shown in Fig. 2 is used as a ground terminal in the equivalent circuit of Fig. 4. Figs. 5 and 6 show models of the respective linear circuit section and I2L circuit section shown in Fig. 2. To form a linear transistor having a high breakdown voltage, it is required to set at a sufficiently large value the resistivity pl of an n-type epitaxial layer 23 which corresponds to the epitaxial layers 4 and 5 in Fig. 2, and set at a sufficiently large value the thickness t3 of that portion of the n-type epitaxial layer 23 which intervenes between the burried layer 2 serving as a collector region and the p-type region 6 serving as a base region in Fig. 2. For example, in order to set the breakdown voltage of the epitaxial layer 23 between the regions 2 and 6 to about 30 to 50 V, it is necessary to set the effective thickness t3 of the epitaxial layer 23, to 10 to 20 microns and set the resistivity pl of the epitaxial layer 23 or epitaxial layers 2 and 5 to 1 to 5 n¯cm. The response characteristic of the 12L circuit device having the construction as shown in Fig. 6 is represented by a cut-off frequency fc which is given as follows: EMI4.1 where S1 and S2 respectively denote areas of top surface portions of the collector and base of the inverter transistor, F denotes the number of collectors of the inverter transistor, t4 is the thickness of the epitaxial layer 24 between the burried layer 4 and p-type region 16, NB is the impurity concentration of the p-type region 16 serving as the base region, Dn is an electron diffusion coefficient, and N24 is the impurity concentration of the epitaxial layer 24. This equation is explained in "Trans. on Electron Devices" (IEEE, March, 1975). As is evident from the equation, in order to increase the response speed of the 12L circuit, it is required to increase the impurity concentration N24 of the epitaxial layer 24 and reduce the thickness t4. To meet the requirement, it has hitherto been a practice to form the two epitaxial layers 3 and 5 and form n+-type regions 2 and 4 respectively in the surface regions of the substrate 1 and epitaxial layer 3, as shown in Fig. 1. With this wafer, it is possible to improve the breakdown voltage characteristic of the linear transistor in the semiconductor device of Fig. 2 without substantially affecting the response characteristic of the 12L circuit section by suitably controlling the thickness and impurity concentration of the epitaxial layer 3 and also possible to improve the response characteristic of the I2L circuit section without affecting the breakdown voltage characteristic of the linear transistor by suitably controlling the thickness and impurity concentration of the epitaxial layer 5. However, the semiconductor device shown in Fig. 2 has the following drawbacks. (1) The n-type epitaxial layers 3 and 5 have to be formed in separate steps, and also the burried layers 2 and 4 have to be formed in separate steps. (2) If the epitaxial layer 5 is separately formed after the formation of the epitaxial layer 3, the quality of the epitaxial layer 3 is lowered to reduce the yield of the semiconductor wafer. (3) The formation of the epitaxial layers 3 and 5 requires many manufacture control parameters, and it is difficult to obtain a wafer of stringent ratings. Owing to these drawbacks, an LSI manufactured using the semiconductor wafer having the two epitaxial layers 3 and 5 and burried layers 2 and 4 formed in different depth positions becomes high in manufacturing cost. An object of the invention is to provide a semiconductor device, which can be obtained using a semiconductor wafer of a simple construction and nevertheless permits to obtain high response characteristic of I2L circuit section and increase the breakdown voltage of a transistor in a linear circuit section. In one form of the invention, it is contemplated to provide a semiconductor device, which comprises a linear circuit section including at least one vertical transistor and an 12L circuit section including an injector lateral transistor and an inverter lateral transistor, these transistors being formed on the same chip as the vertical transistor. Although according to the invention, it is necessary to form a thick semiconductor wafer for increasing the breakdown voltage of the vertical transistor of the linear circuit section, a desired response characteristic of the inverter transistor can be obtained without being influenced by the thickness of the wafer because this transistor is a lateral transistor, thus providing a high speed I2L circuit section. This invention can be more fully understood from the following detailed description when taken in con junction with the accompanying drawings, in which: Fig. 1 is a sectional diagram showing a prior art semiconductor wafer used to form a linear circuit section and an I2L circuit section on the same chip; Fig. 2 is a sectional view of a semiconductor device which is formed using the semiconductor wafer of Fig. 1 and in which the linear circuit section and 12L circuit section are formed on the same chip; Figs. 3 and 4 are respectively equivalent circuit diagrams of the linear circuit section and I2L circuit section of Fig. 2; Figs. 5 and 6 are views respectively showing models of the linear circuit section and I2L circuit section shown in Fig. 2; ; Fig. 7 is a sectional view showing a semiconductor wafer used for manufacturing a semiconductor device according to the invention including a linear circuit section and an 12L circuit section formed on the same chip; Fig. 8 is a sectional view showing an embodiment of the semiconductor device according to the invention; Fig. 9 is a circuit diagram showing the I2L circuit section of the semiconductor device shown in Fig. 8; Fig. 10 is a view showing a model of the I2L circuit section of the semiconductor device shown in Fig. 8; Figs. llA to llF are views for illustrating the steps of manufacturing the I2L circuit section of the semiconductor device shown in Fig. 8; and Figs. 12 and 13 are sectional views showing different embodiments of the semiconductor device according to the invention. Fig. 7 shows a sectional view of the semiconductor wafer used for manufacturing a semiconductor device embodying the invention as shown in Fig. 8 including a lin-ear circuit section of high breakdown voltage and a high speed I2L circuit section formed in a single semiconductor chip. This semiconductor wafer is obtained by diffusing n-type impurities at a high impurity concentration into mutually spaced-apart surface regions of a p--type silicon substrate 30 to form n+-type burried layers 32 and 34 and then forming an n-type layer 36 by the epitaxial growth method on the substrate 30 and the burried layers 32 and 34. The n+-type burried layer 32 forms the collector region of transistor TR4 in the linear circuit section shown in Fig. 8, while the layer 34 forms the emitter of inverter transistor TR5 in the I2L circuit section. The semiconductor wafer shown in Fig. 7 has been extensively used for manufacturing bipolar semiconductor integrated circuits. Highly advanced and sofisticated techniques are avaiable for manufacturing this semiconductor wafer, and a high quality wafer can be obtained at a low cost. In one embodiment of the invention, the thickness of the epitaxial layer 36 is set to 10 to 20 p and the resistivity thereof to 1 to 5 Q-cm for forming the transistor TR4 of high breakdown voltage in the linear circuit section. According to the invention, the response characteristic of the I2L circuit section, on the other hand, is hardly influenced by the thickness and impurity concentration of the epitaxial layer 26 as will be discussed hereinafter. The npn transistor TR4 in the linear circuit section of the semiconductor device shown in Fig. 8 has the same construction as the npn transistor TR1 in the linear circuit section of the semiconductor device shown in Fig. 2. More particularly, the base region of the transistor TR4 is constituted by a p-type region 38 formed in the surface region of the epitaxial layer 36, and the emitter region is constituted by an n+-type region 40 formed in the p-type region 38. Base and emitter electrodes 42 and 44 are coupled to the respective p- and n+-type regions 38 and 40. A collector electrode 46 is coupled to the n+-type region 32 via n+-type region 48 which extends from the surface of the epitaxial layer 36 to the n-type region 32. The I2L circuit section is formed in that portion 36-1 of the epitaxial layer 36 which is surrounded by an n+-type region 49 formed to extend from the surface of the epitaxial layer 36 to the n+-type layer 34. An injector transistor TR6 in the I2L circuit section is formed of p-type regions 50 and 52 formed in mutually spaced-apart manner in the surface region of the epitaxial layer 36. More particularly, the emitter and collector of the injector transistor TR6 are constituted by the respective p-type regions 50 and 52, and the active base is constituted by part of the epitaxial layer 36 intervening be-tween the p-type regions 50 and 52. Electrodes 54 and 56 are formed in connection with the respective p-type regions. A lateral inverter trans is tor TR5 is constituted by p--type region 58 formed to partly overlap the p-type region 52 in the surface region of epitaxial layer 36-1, n+-type region 60 formed in part of the regions 52 and 58 and n+-type region 62 formed in contact with the n+-type region 49 and having a portion which extends into the p--type region 58 to face the n+-type region with a small distance. More particularly, the emitter of the inverter transistor TR5 is constituted by the n+-type region 62, the collector is constituted by the n+-type region 60, and the base is constituted by part of the p -type region 58 intervening between the n+-type regions 60 and 62. Electrodes 64 and 66 are formed in connection with the respective n+-type regions 60 and 62. The linear circuit section and I2L circuit section are isolated from each other by p+-type region 68 formed to extend from the surface of the epitaxial layer 36 to the substrate 30. Figs. 9 and 10 show the equivalent circuit and a model of the I2L section shown in Fig. 8, respectively. The electron injection efficiency of the lateral transistor TR5 is greatly influenced by the ratio of impurity concentrations in the emitter region 62 and base region 58. In this embodiment, a sufficiently high electron injection efficiency can be obtained because it is possible to set a high impurity concentration for the emitter region 62 and a low impurity concentration for the base region 56. In addition, it is possible to further increase the current amplification factor of the inverter transistor TR5 because the regions 60 and 62 can be formed such that the effective width t5 of the base region 58, i.e., the gap between the collector 60 and emitter 62, is sufficiently small. Further, the emitter resistance may be made low by virture of the high impurity concentration of the emitter region 62. Thus, the inverter transistor TR5 is a lateral trans is tor, its response characteristic can be set without being substantially influenced by the gap t6 between the base region 34 and burried layer 34 and the impurity concentration of the epitaxial layer 36-1. While a high breakdown voltage of the linear circuit section transistor TR4 requires a large thickness and a low impurity concentration of the epitaxial layer 36, the reduction of the impurity concentration of the epitaxial layer 36 increases the electron injection efficiency of the inverter transistor TR5 and improves the response characteristic of the I2L circuit section. In general, it is undesired to cause a large current through the inverter transistor TR5, which is a lateral transistor and carries main current in the lateral direction. According to the invention, however, it is possible to obtain a desired circuit characteristic with the transistor of the above construction because the I2L circuit section can be driven with a small current of the order of 10 to several 100 pA. Figs. llA to llF are views showing the steps involved in the formation of the 12L circuit section shown in Fig. 8. As shown in Fig. llA, insulating film 70 is formed to cover the semiconductor wafer, and photoresist film 72 having a desired pattern is formed on the insulating layer 70. Boron is then selectively injected as a p-type impurity by the ion implantation method into the epitaxial layer 36 with the photoresist layer 72 as a mask to form the P--type region 58 in the epitaxial layer 36. At this time, the injection rate of the p-type inpurity boron is controlled such that the p--type region 58 may have a very low impurity concentration. Subsequently, the photoresist film 72 is removed, and the insulating film 70 is partly removed. Then, an n-type impurity is diffused into the epitaxial layer 36 to form the n+-type region 49 extending from the surface of the epitaxial layer 36 to the n+-type region 34, followed by covering the exposed surface of the epitaxial layer 36 with the insulating layer 70 as shown in Fig. llB. The n+-type region 58. This n+-type region 49 co-operates with the n+-type region 34 to isolate the n-type epitaxial layer portion 36-1 from the rest of the epitaxial layer 36. This region 49 is also used as part of the emitter of the inverter transistor TR5. A photoresist film 74 having a predetermined pattern is then formed on the insulating layer 79 as shown in Fig. llC. Impurities of p-type are subsequently injected by the ion implantation method into the epitaxial layer 36-1 with the photoresist film 74 as a mask to form the p-type regions 50 and 52. The p-type region 52 is formed such that it is electrically connected to the p--type region 58. The photoresist 74 is then removed, and a plurality of openings are formed in selected portions of the insulating layer 70. Subsequently, impurities of n-type are diffused through these openings to form the n+-type regions 60 and 62 closely spaced apart, for instance by a distance of about 1,000 as shown in Fig. llD. At this time, it is important that the facing portions of the n+-type regions 60 and 62 are both formed in the p'-type region 58. With this construction, electrons are injected at a high electron injection efficiency from the n+-type region 62 into the p--type region 58. Afterwards, electrode holes for forming the electrodes for the regions 50, 52, 60 and 62 are formed, as shown in Fig. llE. The electrodes 54, 56, 64 and 66 are then formed in connection with the respective regions 50, 52, 60 and 62. When manufacturing the semiconductor device as shown in Fig. 8, it is possible to form the n+-type region 48 in the same step as the n+-type region 49, to form the p-type region 38 in the same step as the regions 50 and 52 and to form the n+-type region 40 in the same step as the n+-type regions 60 and 62. While a preferred embodiment of the invention has been described, this invention is not limited thereto. For example, while in the above embodiment, the p--type region 58 has been spaced apart from the n+-type region, the region 58 may be formed in contact with the region 49 as shown in Fig. 12. In this case, the n+-type region 49 serves as the emitter region of the transistor TR5, and the formation of the n+-type region 62 need not be formed in the step shown in Fig. llD. Further while the n+-type regions 52 and 58, the region 60 may be formed solely in the region 58 as shown in Fig. 13. Further, it is possible to reverse the conductivity types of the semiconductor layers and regions used in the above embodiment.

Claims: Claims: 1. A semiconductor device comprising a linear circuit section including at least one vertical transistor (TR4) and an I2L circuit section including at least one set of injector transistor (TR6) and inverter transistor (TR5) which are formed on the same wafer on which said vertical transistor is formed, characterized in that said injector and inverter transistors (TR6, TR5) are each formed of a lateral transistor. 2. A semiconductor device according to claim 1, wherein said wafer includes: a semiconductor substrate (30) of one conductivity type; first and second semiconductor regions (32, 34) of opposite conductivity type formed in a surface region of said semiconductor substrate (30); and a semiconductor layer (36) of the opposite conductivity type formed on said semiconductor substrate (30) and first and second semiconductor regions (32, 34) and having a lower impurity concentration than said first and second semiconductor regions (32, 34). 3. A semiconductor device according to claim 2, wherein the vertical transistor in said linear circuit includes: a third semiconductor region (38) of said one conductivity type formed in a surface region of said semiconductor layer (36) and constituting a base region; and a fourth semiconductor region (40) of the opposite conductivity type formed in said third semiconductor region and constituting an emitter region. 4. A semiconductor device according to claim 2 or 3, wherein the lateral transistor in said I2L circuit section includes fifth and sixth semiconductor regions (50, 52) of said one conductivity type formed in a surface region of said semiconductor layer (26) to face each other. 5. A semiconductor device according to claim 4, wherein the inverter lateral transistor in said I2L circuit section includes: a seventh semiconductor region (60) of the opposite conductivity type formed in said sixth semiconductor region (50); and an eighth semiconductor region (62, 49) of the opposite conductivity type formed partly in said sixth semiconductor region (52) to face said seventh semiconductor region (60) and electrically coupled to said second semiconductor region (34). 6. A semiconductor device according to claim 5, wherein said sixth semiconductor region (52, 58) has an impurity concentration lower in its portion intervening between said seventh and eighth semiconductor regions (60, 62) than in its portion facing said fifth semiconductor region (50). 7. A semiconductor device according to claim 6, wherein said eighth semiconductor region includes a first portion facing said second semiconductor region (60) and a second portion (49) electrically coupled to said second semiconductor region (34) and extending from the surface of said semiconductor layer (36) to said second semiconductor region (34) to co-operate with said second semiconductor region (34) to surround said fifth to seventh semiconductor regions. 8. A semiconductor device according to claim 6, wherein said eighth semiconductor region (49) extends from the surface of said semiconductor layer (36) to said second semiconductor region (34) and surrounds said fifth to seventh semiconductor regions. 9. A semiconductor device according to claim 5, wherein said eighth semiconductor region includes a first portion facing said second semiconductor region (60) and a second portion (49) electrically coupled to said second semiconductor region (34) and extending from the surface of said semiconductor layer (36) to said second semiconductor region (34) to co-operate with said second semiconductor region (34) to surround said fifth to seventh semiconductor regions. 10. A semiconductor device according to claim 5, wherein said eighth semiconductor region includes a first portion facing said second semiconductor region (60) and a second portion (49) electrically coupled to said second semiconductor region (34) and extending from the surface of said semiconductor layer (36) to said second semiconductor region (34) to co-operate with said second semiconductor region (34) to surround said fifth to seventh semiconductor regions.

Inventors: IKEDA, MASASHI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1981
Main classification: H01L27
IPC codes: H03K19, H01L29, H01L21, H01L27