Metal layers for use in electronic circuit interconnection system

Abstract: A metal laminate for use in a substrate on which an elec­ tronic semiconductor component is to be mounted, the lami­ nate comprising a flat sheet material having a core layer of an iron alloy of low thermal expansion coefficient having on each primary face thereof a layer of copper, the laminate hav­ ing a sufficiently high thermal conductivity that, in use, it is capable of maintaining the component at a safe temperature during operation.

Description: The field of this invention is that of interconnection systems for semiconductor components and integrated circuit devices. The invention relates more particularly to metal layers for use in interconnecting ceramic chip-carrier types of integrated circuit devices and direct-mounted integrated circuits with wire-bonded interconnects and the like in such a way as to permit high-density mounting of the devices on a low cost substrate while avoiding the interconnection-bond integrity problems and heat-dissipation problems usually associated with interconnection of such devices. At the present time, most integrated circuit devices are provided in the form of dual-in-line packages (DIP) which are mounted and electrically interconnected on conventional glass-epoxy printed circuit (p.c.) boards and the like by having device terminals fitted onto plated-through holes in the boards, with or without the use of intermediate mounting sockets. The present invention does not exclude systems incorporating such dual-in-line packages but, with the trend toward increasingly larger numbers of pin-outs, higher speeds, and higher density of i.c. devices, it is found that much larger p.c. board areas are needed to accommodate the devices even when multilayer boards are used. Greater difficulties are encountered in trying to mount larger i.c. devices using DIP packages without damage to device terminals, and the ratio of packaging and mounting cost to i.c. device cost is becoming excessive. As a result, various different types of device packages and/or direct device attachment are being considered for facilitating interconnection at the "board" system level, commonly called the No. 2 level. For example, leadless ceramic chip-carriers and directly attached i.c. devices and the like have been proposed for permitting higher device mounting density in an interconnection system. However, because of the difference in thermal expansion properties between the ceramic i.c. packages or i.c. devices and the conventional p.c. boards, some compliant lead structure has typically been required between the terminals on the packages or i.c. devices and the circuit paths on the boards to assure suitable interconnection bond integrity. Some of the more recently proposed i.c. devices, such as tape-automated-bonded (TAB) devices have been provided with a compliant lead structure but it is then found that the heat-dissipating properties of the conventional low cost p.c. boards are still too limited for permitting any suitable degree of device mounting density. Substrates having ceramic bases and having metal conductors deposited on top of such bases have also been proposed for use for direct i.c. chip or bar attachment or for mounting of ceramic chip carriers but the use of such known ceramic substrates has been limited by cost and fabrication technology and has typically been limited in size to less than about 100 square inches (100 square inches = 0.65 m²). It would be desirable if an improved electronic interconnection system could be provided for directly attaching i.c. chip or bars or for mounting ceramic i.c. devices as well as other devices of different types in an economical and convenient manner, particularly using substrate means of substantial area greater than about 100 square inches. Such a system should be adapted to provide high device density on a low cost, large scale substrate and the substrate should have heat-dissipating and thermal expansion properties which are compatible with the devices mounted in the system. The invention provides a metal layer means for use in a single or multilayer substrate in which circuit paths, device mounting pads, lead connections, edge terminals and pin mounting holes and the like are provided in etched metal layer means, or plates, which have thin coatings of glass frit or other inorganic dielectric material or the like fused to one or both sides of the etched plate pattern. The metal layer means is as defined in claim 1. Ceramic chip-carrier types of integrated circuit devices or other i.c. devices or semiconductor components having thermal expansion characteristics generally corresponding to those of the inorganic substrate coating material are then mounted on the substrate and are electrically interconnected to circuit paths and the like on the substrate. In that way, the substrate has thermal expansion properties which are compatible with the thermal expansion properties of the ceramic chip-carrier types of i.c. devices and the like for permitting interconnection of the devices with high connection-bond integrity. In a particularly preferred application of the invention, the system incorporates a multilayer substate in which the glass-coated patterned metal plates as above described are arranged in stacked relation to each other with pin mounting holes and the like aligned in the metal layers and with the layers secured together by fusing of the glass layer coatings. Where high temperature substrate materials such as glass are used as above described (suitable for 1000°C. for example), the system is particularly well adapted to incorporate low cost hybrid circuit features and to use non-noble metals for both circuit elements and passive components directly in the substrate. The plates are provided with plated vias extending through the aligned holes and through the glass materials for electrically interconnecting the substrate layers where required. Other objects, advantages and details of the metal layer means of this invention appear in the following detailed description of preferred embodiments of the invention, the detailed description referring to the drawings in which: Fig. 1 is a diagrammatic plan view of an interconnection system incorporating a metal layer means as provided by this invention; Fig. 2 is a partial section view to enlarged scale along line 2-2 of Fig. 1; Figs. 3-6 are partial section views similar to Fig. 2 diagrammatically illustrating manufacture of the substrate used in the interconnection system of Figs. 1 and 2; Figs. 7-8 are partial section views similar to Figs. 3-6 diagrammatically illustrating manufacture of an alternative example of the substrate shown in Figs. 3-6; Figs. 9-11 are partial section views similar to Figs. 3-8 illustrating other alternative example of the substrates; (There are no figures numbered 12 to 17 in this specification) Fig. 18 is a block diagram illustrating steps in a method for making substrates employing the metal layer means of this invention; Figs. 19-21 are partial plan views to enlarged scale similar to Fig. 1 illustrating the mounting of alternate integrated circuit devices and the like in an interconnection system corresponding to that illustrated in Fig. 1; Referring to the drawings, 10 in Figs. 1 and 2 indicates a preferred embodiment of an electronic circuit interconnection system using the metal layer means of this invention which system is shown to include substrate means 12 having one or more electronic semiconductor means 14 mounted thereon, the substrate means having thermal expansion properties corresponding to those of the semiconductor means and having sufficient thermal conductivity to maintain the semiconductor means at safe temperatures during system operation. The substrate means includes metal layer means in accordance with the invention such as the metal layer 16 which, as is diagrammatically illustrated in Figs. 1 and 2, has different portions defining various different circuit paths means and the like such as are typically provided in an interconnection substrate. For example, the metal layer 16 preferably includes semiconductor device mounting pads 16.1 The metal layer also typically provides a plurality of circuit path conductors 16.2 extending between different semiconductor device locations on the substrate means, a plurality of circuit path conductors 16.3 which extend from such device locations to edge terminals 16.4 located at the edge of the substrate means, and other circuit conductors 16.5 extending from device locations to the location of substrate holes 16.6 which can mount connector pins or plated-through metal vias for connecting to other metal layer means in the substrate or the like. The metal layer means 16 also preferably includes heat-dissipating layer portions 16.7 as shown in Fig. 1,. The material of the metal layer 16 comprises an iron alloy which has thermal properties most compatible with the i.c. device or package to be used with the metal layer. Other metals such as copper, low carbon steel or the like are also needed. In a preferred embodiment, where direct i.c. mounting is contemplated or where ceramic chip carriers are to be used, the metal layer 16 preferably embodies an iron alloy material having a nominal composition by weight of about 42 percent nickel and the balance iron, such an alloy having a very low coefficient of thermal expansion of about 5.4 x 10⁻⁶ m/m/°C (about 3 x 10⁻⁶ in./in./°F). The layer 16 is formed iron alloys of low coefficient of thermal expansion having nominal compositions by weight in the range of about 36 to 50 percent nickel and the balance iron, of about 31 percent nickel, 8 percent chromium, 8 percent cobalt, and the balance iron, of about 32 percent nickel, 15 percent cobalt, 1 percent molybdenum, and the balance iron, of about 38 percent nickel, 7 percent chromium and the balance iron, of about 17 percent chromium and the balance iron, of about 16.5 percent chromium 4.5 percent aluminum, and the balance iron, of about 57 percent cobalt, 9 percent chromium and the balance iron, and of about 23 to 30 percent nickel, 17 to 30 percent cobalt, 0.6 to 0.8 percent manganese, and the balance iron. The metal layer means typically have a thickness in the range from about 0.05 to 1.5 mm (about 0.002 to 0.060 inches) to provide the substrate means with substantial heat sink properties desired. Thin copper is provided on selected outer surfaces of the metal layer means by plating or cladding or in other conventional manner for facilitating soldering of components and the like to the metal layer means described below. An inorganic base means 18 is bonded to selected portions of the metal layer means for securing the circuit path means and the like 16.1 - 16.7 in selected, spaced, electrically insulated relation to each other, the inorganic base means and the metal layer means being selected and proportioned relative to each other for providing the substrate means with selected thermal expansion and thermal conductivity properties as is further described below. Preferably, all of the metal layer portions described above as well as any other typical substrate features which are incorporated in the metal layer portions are embedded in the inorganic material of the base means 18 so that the inorganic material extends up between adjacent circuit path conductors 16.3 and the like in the metal layer means. As illustrated in Figs. 1 and 2, one side 16 a of each metal layer portion is embedded in the inorganic base means and the opposite sides 16 b of the layer portions are exposed from the embedding means. The inorganic base material 18 preferably comprises any conventional soda-lime glass material or the like which is fused to selected portions of the metal layer 16 but other inorganic materials of relatively low thermal expansion such as porcelain enamels, solder glass frits and other vitreous materials, ceramic materials, alumina or crushed mica or the like are also used. The semiconductor means 14 is of any conventional type and typically embodies portions of an inorganic material having selected relatively low thermal expansion properties and has metal conductor means which are electrically and thermally interconnected with the circuit path means and the like on the substrate means 12 as is further discussed below. For example, in the interconnection system illustrated in Figs. 1 and 2, a plurality of the circuit path means and the like 16.1-16.7 are provided in a selected pattern at a semiconductor device location such as is indicated by the broken line 16 a in Fig. 1. The semiconductor means 14 then comprises a typical ceramic chip-carrier type of integrated circuit unit. That is, the unit has a conventional integrated circuit embodied in a chip 14.1 of semiconducting silicon material as will be understood and has chip terminals 14.2 for use in conventional manner in electrically connecting the integrated circuit of the chip with other electrical circuit means as will also be understood. The chip is mounted on an inorganic ceramic chip-carrier member 14.3 in any conventional manner, usually by soldering the chip to a metallized surface of gold, copper or the like (not shown) plated or deposited on the carrier, and metal conductors 14.4 are electrically connected to the respective chip terminals and are bonded to the carrier member in any conventional way to extend to selected locations of the carrier member, usually at the edge of the underside of the carrier member as is illustrated in Fig. 2. A metallized surface (not shown) deposited at the center of the underside of the carrier member is preferably secured in heat-transfer relation to a semiconductor mounting pad 16.1, usually by soldering to a copper flashing (not shown) provided on the pad for mounting the unit in good heat-transfer relation to the substrate means, and the metal conductors are fixedly secured (by soldering or the like) in electrically and thermally conducting relation to circuit paths 16.2, 16.3 and 16.4. Typically the ceramic i.c. unit has a ceramic or metal cover 14.5 sealed over the i.c. chip. Alternatively, the semiconductor means 14 incorporated in the system of this invention comprises conventional beam-lead units, dual-in-line (DIP) units, tape-automated-bonded (TAB) units, flip-chip units, direct-mounted i.c. chips or other conventional semiconductor means. In that arrangement, the interconnection system 10 provides high density mounting but achieves low cost and reliable mounting and electrical interconnection of the electronic semiconductor means. The ceramic chip-carrier i.c. units 14 are adapted for low cost repetitive or automated manufacture to provide a compact, stable structure and, in the system 10, the units are mounted with high density, in closely spaced relation to each other. The units have fixed solder connections or the like between the units and device mounting pads on the substrate means and also have fixed and secured solder connections between the metal conductors of the ceramic chip carriers and the circuit paths on the substrate means. The units are therefore secured in close heat-transfer relation to the substrate means and form a rugged secured package with the substrate means. Substantial portions of the i.c. units are formed of inorganic ceramic or silicon materials having relatively low coefficients of thermal expansion and the substrate means 12 incorporate corresponding low-expansion metal allows and substantial portions of inorganic glass or ceramic materials or the like so that the substrate means is dimensionally stable and has thermal expansion properties substantially corresponding to those of the semiconductor means 14. Accordingly, the bonds between the metal conductors 14.4 of the chip carrier and the circuit paths 16.1 - 16.3 of the substrate means retain their integrity during extensive thermal cycling of the system 10. The iron alloy materials of the metal layer means 16 assure good fused bonding or the like of the inorganic materials 18 to the metal layer means so that the substrate means also displays a long service life during thermal cycling. In addition, the thickness of the metal layer means and the proportions of the metal layer means which are specifically or otherwise devoted to heat-sink or heat-dissipating purposes in the substrate means are selected so that sufficient heat is withdrawn from the semiconductor means and is dissipated from the system by the substrate means for assuring that the semiconductor means are maintained at safe temperatures during system operation. The substrate means 12 used in the system 10 is easily and economically fabricated as is shown in Figs. 3-6 and 18, thereby to provide a substrate means with the desirable properties as discussed above. That is, the metal plate 16 c is chemically cleaned and dimensionally stabilized using conventional techniques as is diagrammatically indicated at 20 in Fig. 18. In one such method, the sheet is degreased with a suitable solvent, is rinsed in a water spray, is etched clean in a dilute ferric chloride solution (39° Baumé), and is dimensionally stabilized by firing at 975°C. for 15 minutes in a dry hydrogen atmosphere, the atmosphere reducing or avoiding the formation of oxides on the sheet or plate. The top and bottom of the plate are coated with a conventional photoresist and are processed with conventional photolithographic techniques as diagrammatically indicated at 22 and 24 in Fig. 18 to provide a mask 21 on the sheet 16 c as is diagrammatically illustrated in Fig. 3. The masked sheet is then etched and the masking material is subsequently removed as indicated at 26 and 28 in Fig. 18, thereby to provide the sheet 16 c with an aperture 16.6 and with other partially formed substrate features as is shown in Fig. 4. Typically, the sheet is etched in a composition comprising a mixture of 46° Baumé ferric chloride and hydrochloric acid. The partially processed sheet 16 c is then coated with a glass frit 18 a which is deposited by screen printing or in other conventional ways to leave the aperture 16.6 open. The glass frit is then heated to be vitrified and fused to the plate as indicated at 30 in Fig. 18 and, as indicated at 32 and 34 in Fig. 18, an additional photoresist is provided and processed on the partially coated plate 16 c to form an additional mask 23 as illustrated in Fig. 5. The plate is then further etched as indicated at 36 in Fig. 18 and the mask is again removed to form the finished substrate 12 as illustrated in Fig. 6. It should be understood that many other processes and other etching compositions and the like can also be used in forming the substrate means. Any surfaces of the plate 16 c to which soldering is to be effected are plated with copper (not shown) in any conventional manner to facilitate such soldering, particularly where nickel-iron alloys have been used in the plate as above-described. Alternatively the original sheet 16 c can be provided with a very thin outer copper cladding (not shown) so that, when the plate has been etched and the masks 21 and 23 are removed, soldering to the paths 16.5 is easily effected. In an alternative example of the substrate as illustrated in Figs. 7 and 8, a similar substrate means 40 is used in the system, that is to say, a substrate means 38 is formed in a similar manner to substrate 12 to have similar or related substrate features such as a substrate aperture 16.6 as formed in the metal layer 16 d as shown in Fig. 7. The glass-coated sides of two substrate means 12 and 38 are then abutted; features of the two substrate means such as the apertures 16.6 are aligned as desired; and the glass coatings of the two substrate means 12 and 38 are fused together for securing the substrate means in stacked relation to each other to form the multilayer substrate means 40 as shown in Fig. 8. In that arrangement, additional semiconductor means can be mounted on the metal layer means 16 d , or the metal layer means 16 d can be electrically connected to the layer 16 c by any conventional means (not shown), or the metal layer 16 d can provide additional heat-dissipating capacity in the substrate means as may be desired. In another alternative example of the interconnection system as shown in Figs. 9-11, a substrate layer means 42 is formed with a metal layer 16 e which is first processed as described above with reference to the substrate means 12. The layer 16 e as thus processed is then further processed as indicated at 44 in Fig. 18 to provide additional glass frit means fused to the plate 16 e to cover selected portions of the second side of the plate as is indicated in Fig. 9. As indicated at 46 in Fig. 18, and as is indicated in Figs. 10, or 11, the substrate layer means 42 is then combined with a substrate means 12 or with a substrate means 12 and 38 or the like to form multilayer substrate means 48 or 50 as shown in Figs. 10 and 11. The substrate means of the above described interconnection systems are also adapted to mount and to electrically interconnect various other types of semiconductor means as is illustrated in Figs. 19-21. Thus, in the system 10 a illustrated in Fig. 19, the substrate means 12 a is provided with circuit path means 70, and a flip-chip type of i.c. unit (as diagrammatically indicated by the broken lines 72) is mounted on those circuit path means 70 in a conventional manner. Alternatively, in the system 10 b shown in Fig. 20, a chip 74 of semiconducting silicon material having an integrated circuit embodied therein is mounted directly on a device mounting pad 16.1 (not shown) on the substrate means 12 b in closely spaced relation to other circuit path means 76 provided on the substrate means 12 b . The terminals of the chip are then electrically interconnected with the circuit path means 76 by thermal compression bond means 78 as indicated in Fig. 20. Alternatively, the circuit path means 80 are provided in a substrate means 12 c as shown in Fig. 21, and a dual-in-line integrated circuit unit 82 has terminals or leads 82.1 inserted into apertures 16.6 (not shown) in the substrate means 12 c located in the circuit path means 80 as will be understood and soldered to the circuit path means for electrically connecting the dual-in-line package to the circuit path means.

Claims: A metal layer means for use in a substrate on which an electronic semiconductor component is to be mounted, the metal layer means comprising a flat sheet material having a layer of an iron alloy of low thermal expansion coefficient having on a primary face thereof a layer of copper, for facilitating soldering, the iron alloy being a member of one of the groups of alloys having the following nominal composition by weight: nickel 36 to 50%, balance iron nickel 31%, chromium 8%, cobalt 8%, balance iron nickel 32%, cobalt 15%, molybdenum 1%, balance iron nickel 38%, chromium 7%, balance iron chromium 17%, balance iron chromium 16.5%, aluminium 4.5%, balance iron cobalt 57%, chromium 9%, balance iron nickel 23 to 30%, cobalt 17 to 30%, manganese 0.6 to 0.8%, balance iron. A metal layer means as claimed in claim 1, wherein the iron alloy has a nominal composition of about 42% by weight nickel, the balance being iron.

Inventors: MANNS WILLIAM GARY, SPINELLI THOMAS S, WEIRAUCH DONALD F, MANNS, WILLIAM GARY, SPINELLI, THOMAS S., WEIRAUCH, DONALD F.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1981
Main classification: H01L23
IPC codes: H01L23, H05K1, H05K3, H01L21