RADIO RECEIVER

Abstract: A radio receiver comprises a conventional LW (long wave) receiving stage (20), a MW (medium wave) receiv­ ing stage (30), a PLL (phase-locked loop) circuit (14) and a digital N value generating circuit (54, 66-1 ∼ 66-4) and further comprises a newly introduced comparating means (52, 72), a LW/MW discriminating means (78), a first stor­ age means (73), a second storage means (67) and a sweep controlling means (62). The comparating means (52, 72) compares the digital N value and a value sup­ plied from the first storage means (73) which stores data, indicating respective border frequencies of the LW and MW bands. The second storage means (67) receives data from the first storage means (73) and controls the digital N value generating circuit (54, 66-1 ∼ 66-4). The LW/MW designating means (78) supervises whether the digital N value designates the LW band or the MW band and func­ tions to energize the LW receiving stage (20) or the MW receiving stage (30), alternatively. The sweep controlling means (62) functions to increase or decrease the digital N value by one integer progressively.

Description: RADIO RECEIVER The present invention relates to a radio receiver, and more particularly to a radio receiver which is preferably mounted in an automobile. Generally, there are two ways for conducting a channel selection, the first way is manual channel selection and the second way is automatic channel selection. The latter automatic channel selection is very convenient for conducting a channel selection in an automobile. The reason for this, is that the automobile can always receive broadcasting transmitted from a local broadcasting station which is located in the same.area where the automobile is running. Thus, the automatic channel selection is the most preferable way for receiving the corresponding broadcasting being transmitted in the area in which the automobile is running. Of course, local broadcasting can also be received through manual channel selection. In this case, it is relatively easy to realize a circuit for performing automatic channel selection, if the automobile, provided with the circuit, is restricted to run only within a particular area, in which particular area, the frequency range of the broadcasting is relatively limited, as is a MW (medium wave). Contrary to this, it is relatively difficult to realize the above mentioned circuit for performing automatic channel selection, if the automobile, provided with the circuit, runs within a particular area, for example the European Continent. In the European Continent, a LW (long wave) and also a MW are transmitted as AM (amplitude modulation) broadcasting, and further, in some areas, an FM (frequency modulation) broadcasting is also transmitted. In order to deal with such a mixture of broadcastings, during reception of the AM broadcasting, a band switching from the LW to the MW and vice versa, is usually activated by manual operation. In other words, the automatic channel selection cannot be conducted with respect to both bands of the LW and the MW, without operating the above mentioned band changer. Accordingly, if the automatic channel selection is required to be conducted with respect to the LW, the MW and also the FM, three band switching operations must be carried out, that is the LW-band, the MW-band and the FM-band. Thus, usually, the automatic channel selection is conducted in each of the LW, MW and FW bands, independently. As is apparent from the above, a radio listener would feel convenienced, if the automatic channel selection, during the reception of AM broadcasting, could be done from the LW to the MW and vice versa, without using any manual band switching operation. Also, a radio listener would feel convenienced, if he could conduct the manual channel selection from the LW to the MW and vice versa, without using a manual band switching operation. In the prior art, a mechanical tuning circuit, comprised of a variable reactance device and a variable capacitance device, is used for conducting the channel selection. However, it is difficult to conduct channel selection, by using a single mechanical tuning circuit, within the range of the LW and MW bands, with a high degree of accuracy. This is because a so-called tracking must be taken into consideration. That is, it is difficult for a radio receiver using the prior art to vary a RF (radio frequency) signal, an IF (intermediate frequency) signal and a LF (local frequency) signal simultaneously with the same linearity, along the LW and MW bands. Further, regarding the preset buttons, for selecting a desired channel, arranged on an operating panel of the radio receiver, for example, three of the five preset buttons can be allotted to channel selection buttons for selecting desired LW broadcastings and the remaining two preset buttons can be allotted to channel selection buttons for selecting desired MW broadcastings. In such an allocation, it is impossible for a radio listener to tune into one of the desired radio frequencies, at random, by using the above mentioned five preset buttons, without using a manual band switching operation. In recent years, a so-called PLL (Phase Locked Loop) frequency synthesizer has become being known and put into practical use, and thereby some advantages can be produced, which advantages cannot be produced by the above mentioned mechanical tuning circuit. In other words, a particular radio receiver can be obtained, which particular radio receiver could not be realized by using the mechanical tuning circuit. In the present invention, it is intended to realize a particular radio receiver, utilizing the PLL frequency synthesizer, which will satisfy, especially, the following technical matters. (1) The switching between the LW and MW, can be conducted without using any band switching operation and, accordingly, the two bands of the LW and the MW may substantially be treated as a single band. (2) Both the preset buttons for the LW, for example, L number of preset buttons, and the preset buttons for the MW, for example, N number of preset buttons (L + N = 5 or 7) can be set, at random, without using any band switching operation and, accordingly, it becomes easy for a radio listener to operate the operating panel of the radio receiver. (3) The automatic channel selection and also the manual channel selection can be conducted between the LW band and the MW band continuously, without using a band switching operation. It is an object of the present invention to provide a radio receiver, utilizing the PLL frequency synthesizer, which can satisfy the technical matters, mentioned in paragraphs (1), (2) and (3) above. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 depicts a graph, used for explaining the operation of a radio receiver according to the present invention; Fig. 2 is a flowchart for conducting an automatic channel selection or a manual channel selection; Fig. 3 is aflowchart for conducting a preset (digital) channel selection by using preset buttons; Fig. 4 is a block diagram of a radio receiver, according to the present invention, which is constructed by using hardware; Fig. 5 is a front view of an operating panel which is used in the radio receiver, according to the present invention, and; Fig. 6 is a detailed block diagram of the circuit shown in Fig. 4, according to the present invention. Fig. 1 depicts a graph, used for explaining the operation of a radio receiver according to the present invention. In the graph of Fig. 1, the abscissa indicates a time (t) and the ordinate indicates a frequency (f). The-symbol RLW denotes a frequency range of the LW, the lowest frequency of the HLW is represented by the symbol fLmin t for example 155 kHz, and the highest thereof is represented by the symbol for w for example 281 kHz. In this case, the frequency florin and the frequency fLmax correspond, regarding digital N values of the PLL frequency synthesizer, respectively to N = 67 and N = 81. Similarly, the symbol RMW denotes a frequency range of the MW, the lowest frequency of the RMW is represented by the symbol fMmin , for example 522 kHz, and the highest frequency thereof is represented by the symbol fMmax , for example 1602 kHz. In this case, the frequency fMmin and the frequency fMmax correspond, regarding said digital N values of the PLL frequency synthesizer, respectively to N = 108 and N = 228. When automatic channel selection or manual channel selection (semi-automatic channel selection) is conducted, a receiving frequency can be varied along a route indicated by solid line arrows such as EMI4.1 fLmin ---, by sweeping a local oscillating frequency up- wardly, thereby a desired broadcasting of all those which are being received can be selected. (Note: the above mentioned term "semi-automatic channel selection" means a selection mode in which, when a selection button is turned/ pressed ON, an automatic sweep As operated, while, when the selection button is OFF, the automatic sweep is stopped; the above symbol EMI5.1 denotes that the receiving frequency changes stepwise from the LW to the MW and vice versa). Contrary to the above, the receiving frequency can be varied along a route indicated by dotted line arrows such as fMmaxe EMI5.2 by sweeping the local oscillating frequency downwardly, thereby a desired broadcasting of all those which are being received can be selected. Especially, according to the automatic channel selection mode, every time each of the broadcastings is correctly received during the sweep of the above mentioned route, indicated by the solid line arrow or the dotted line arrow, the sweep is suddenly stopped. This automatic channel selection can be operated by means of a circuit for detecting the appearance of an intermediate frequency signal or another circuit for detecting the appearance of a broadcasting signal. However, according to the manual channel selection mode, the sweep is suddenly stopped at the moment when a radio listener stops operating the manual channel selection, regardless of an appearance of a broadcasting signal. On the other hand, according to the automatic or semi-automatic channel selection mode, a radio listener can catch a desired radio frequency signal, at will, by turning the above mentioned selection button OFF. In the prior art, when each frequency transition occurs, such as EMI5.3 EMI5.4 it is required to conduct the manual band switching operation. However, in the radio receiver according to the present invention, it is not required to conduct such a manual band switching operation. Further, in the prior art, there are five or seven preset buttons, in which some of the preset buttons are allotted to selecting the LW channels and the remaining preset buttons are allotted to selecting the MW channels. In this case, each preset button is restricted to the LW channel only or a preset button for the MW channel only, due the mechanism of the preset buttons. However, since the number of the LW stations and the number of the MW stations change in every country or area, it is not convenient for a radio listener to divide the preset buttons only into the LW and MW preset buttons. Furthermore, in the prior art, although the same preset button can be allotted to the LW or the MW alternatively, by conducting the band switching operation, such mechanism will become complicated if a preset button must also be allotted to FM besides the LW and the MW. However, the above mentioned band switching operation will be eliminated from the radio receiver, by introducing the PLL frequency synthesizer into the radio receiver and, accordingly, both the LW band and MW band can be treated substantially as a single band. Based on the above mentioned conception, the radio receiver of the present invention operates by the steps defined by flowcharts shown in Figs. 2 and 3. Fig. 2 is a flowchart for conducting an automatic channel selection or a manual channel selection. Fig. 3 is a flowchart for conducting a preset (digital) channel selection by using preset buttons. In Fig. 2, first, an automatic channel selection button is turned ON (see step &commat; Ga: AUTOMATIC CHANNEL SELECTION BUTTON IS SWITCHED ON"). In this case, the sweep is designated to shift upwardly along the solid line arrows shown in Fig. 1. Next, it is determined whether or not the digital N value designates the LW, where the digital N value is produced from a digital N value generator and applied to a PLL circuit (see step Gb: "DOES N VALUE DESIGNATE LW?"). That is, in step b h it is discriminated whether the present N value exists within the receiving frequency range of the RLW or the RMW (refer to Fig. 1). If the N value exists within the range of the RLW (see "YES"), step c starts. In step c , it is detected whether or not the N value designates the highest frequency (fLmax) of the LW (see step : Qc: "DOES N VALUE DESIGNATE f ?"). That is, it is determined whether the present Lmax N value exists at the highest frequency of the receiving frequency range of the RLW (see Fig. 1) or exists in below of this highest frequency. If the N value does not yet. reach the highest frequency (flax) (see "NO" of step the N value is increased by one step and thus the higher receiving frequency signal is selected (see step Gd: "N-y N + 1"). At this increased frequency, it is detected whether or not a radio broadcasting exists (see step Ge "DOES RADIO BROADCASTING EXIST?"). If the radio broadcasting exists (see "YES" of step c e the above mentioned circuit for detecting the intermediate frequency signal, is operated and the automatic channel selection operation is stopped (see step f Gf: "STOP AUTOMATIC CHANNEL SELECTION"). At this moment, if the received radio broadcasting is comfortable for the radio listener, the automatic channel selection mode is released (see step g : "END"). If not, he will put the automatic channel selection button ON again, and the operation will return to the first step Ga. At step , if it is determined that no radio broadcasting exists, then it is detected whether or not the present N value designates the MW (see step h : "DOES N VALUE DESIGNATE MW?"). Since the channel selection of the RLW (Fig. 1) is being conducted at present, the result of step Gh should be "NO". Therefore, the operation starts again from step the Thereafter, the increment from N to N + 1 of step will be executed repeatedly until the receiving frequency, obtained by the channel selection, reaches the highest frequency of the RLW. In step h , if it is determined that the N value now designates the MW (see "YES" of step c ), this means that since the N value reaches the highest limit of the RLW (Fig. 1), the band must be switched from the LW to the MW (see step i Q: "SWITCHING TO MW"). This switching from the LW to the MW, is carried out not by the manual band switching operation but by the automatic band switching operation which is automatically conducted by a change of the N value and also a LW/MW band switching signal. The above mentioned change of the N value is carried out, in the present stage, by setting the fMmin as a new N value (see step j G: "SET N VALUE TO fMmin"). Next, the operation returns to step again and if, in this step, MW radio broadcasting is received, the auto matic channel selection operation is stopped at step f . If the received radio broadcasting satisfies the radio listener, step g (END) takes place. If not, he will turn the automatic channel selection button ON again, and the operation will return to the first step a. Ga. Contrary to the above, in step , if MW radio broad- casting is not received, the result of step Ce) is wNOw and then step h starts. Since channel selection of the RMW (Fig. 1) is being conducted at present, the result of step should be "YES". Thereafter, step k ("NN + 1") Starts, in order to seek, step by step, a radio broadcasting having the higher receiving frequency. This digital N value is increased one by one until a comfortable radio broadcasting is received, along the following steps step step e DOES RADIO BROADCASTING SEXIST?") - > step G ("DOES N VALUE DESIGNATE fMmaX?") -- > the step k . If MW radio broadcasting is received, the result of step becomes "YES", the automatic channel selection operation is stopped at step t If the received MW radio broadcasting is satisfactory for the radio listener, the operation reaches step i (END). If not, the automatic channel selection button is turned ON again at step Since the receiving frequency exists within the range of the RMW (Fig. 1), the result of step becomes "NO", and then step Q starts (see step # : "DOES N VALUE DESIGNATE fMmaX?"). If the present N value still designates a receiving frequency existing within the range of the RMW, the result of step # is "NO". Therefore, the operation is oriented to the above mentioned step k . Thereafter, it goes through the following steps: step Ge.' step 3# step k - > step e ', and flows again until a comfortable radio broadcasting is received. The channel selection in the RMW is continued and when the receiving frequency reaches the fMmax t the result of step G becomes "YES". Thereafter, step m starts (see step m : : "SWITCHING TO LW"). This switching from the MW to the LW is also, as previously mentioned, carried out not by a manual band switching operation but by the automatic band switching operation which is automatically conducted by the change of the N value and also the LW/MW band switching signal. The above mentioned change of the N value is carried out, in the present stage, by setting the fLmin as a new N value (see step n : "SET N VALUE TO fLmin"). Thus the receiving frequency is changed again to a frequency of the RLW, and identical operations as previously mentioned, will be carried out repeatedly. The above explanation has been made by taking as an example of the case where the sweep is conducted upwardly along the solid line arrows of Fig. 1. Contrary to this, if the sweep is conducted downwardly along the dotted line arrows of Fig. 1, similar automatic channel selection as previously mentioned can be conducted by carrying out reverse sequences with respect to the above explained sequences. For example, step Gb should be changed to read as "DOES N VALUE DESIGNATE MW?", step Q should be changed to read as "DOES N VALUE DESIGNATE fMmi ?", step d should be changed to read as "N-y N -1", step ( should be changed to read as "DOES N VALUE DESIGNATE LW?", step should be changed to read as "SWITCHING TO LW", step Q should be changed to read as "SET N VALUE TO fLmax" step 0 should be changed to read as "N- > N-1", step G should be changed to read as "DOES N VALUE DESIGNATE fLmin?", step should be changed to read as "SWITCHING TO MW" and step n should be changed to read as HSET N VALUE TO In Fig. 3, which is a flowchart for conducting a preset channel selection by using preset buttons first, the preset button is switched on at step o Go. In the next step it is determined whether or not the preset button, being now turned ON, selects the LW radio broadcasting (see step : "DOES N VALUE DESIGNATE LW?"). If the preset button indicates selection of a LW radio broadcasting ("YES"), the tuning circuit of the radio receiver is switched to the LW tuning status by a command of the LW/MW band switching signal (see step q : "SWITCHING TO LW") and also the N value, designated by the preset button is set (see step 0: "SET N VALUE"). Thus, the LW band radio broadcasting can be received, which is designated by the preset button (see step s : "RECEIVING OF BROADCASTING"). Contrary to the above, in step p , if it is determined that the N value designates the MW (see "NO" of step ), ), a step starts. In step t t the operation of "SWITCHING TO MW" is carried out by the LW/MW band swtiching signal and, further, in step u , the operation" SET N VALUE" is carried out and finally the desired MW band radio broadcasting can be received at step In the flowchart of Fig. 3, the above mentioned determi nation in step , , the band switching in step q and the band switching in step t Gt, are carried out automatically in the radio receiver (explained hereinafter). The operations, conducted according to the flowcharts of Figs. 2 and 3, can be processed mainly with the aid of a micro-computer, under control of software. That is, programs are set up, in advance, according to the above mentioned steps and, thus, the radio receiver can be controlled under these programs. It is, of course, that the operations, conducted according to the flowcharts of Figs. 2 and 3, can also be performed mainly by hardware, that is, by electronic circuits. Fig. 4 is a block diagram of a radio receiver, according to the present invention, which is constructed by hardware. In this figure, the symbol ANT denotes an antenna for receiving radio broadcasting, the symbol SP denotes a speaker which transmits the radio broadcasting frequency signal as an audio signal. A block 10, connected between the antenna ANT and the speaker SP, is a conventional part of a radio receiver circuit (Note: Circuits, acting as the FM receiving part of the radio receiver, are omitted from this figure). Therefore, circuits, located outside the block 10, are newly employed according to the present invention. First, an input signal from the antenna ANT, is applied to a LW receiving stage 20 or a MW receiving stage 30. The LW receiving stage 20 and the MW receiving stage 30 are alternatively energized by a battery B, by way of a power switching circuit 51. Accordingly, when the LW receiving stage 20 is in an active status, the MW receiving stage 30 is left in an idle status, and vice versa. Either an LW intermediate frequency signal, from the LW receiving stage 20, or an MW intermediate frequency signal, from the MW receiving stage 30, is led, via an OR circuit 11, to an intermediate frequency control stage 40 and finally reaches, via an audio frequency circuit (AF) 12, the speaker SP. The LW receiving stage 20 is comprised of an LW tuningamplifying circuit (LW/RF) 21, an LW local oscillating frequency circuit (LW/LO) 22 and an LW mixing circuit (LW/MIX) 23, the circuit 23 mixes the frequency of the output signal from the circuit 21, with the frequency of the output signal from the circuit 22. The MW receiving stage 30 is comprised of an MW tuningamplifying circuit (MW/RF) 31, an MW local oscillating frequency circuit (MW/LO) 32 and an MW mixing circuit (MW/MIX) 33, the circuit 33 mixes the frequency of the output signal from the circuit 31, with the frequency of the output signal from the circuit 32. The intermediate frequency controlling stage 40 is comprised of an intermediate frequency amplifying circuit (IF) 41, which amplifies the intermediate frequency output signal from the OR circuit 11, a detecting circuit (DET) 42 which detects the intermediate frequency signal developed at the output of the circuit 41, and an intermediate frequency signal detecting circuit (IF/DET) 43, which detects the appearance of the above mentioned intermediate frequency signal. An LW local oscillating frequency signal SLL, from the circuit 22, or an MW local oscillating frequency signal SLM, from the circuit 32, is applied, via an OR gate 13, to a PLL circuit 14. The circuit 14 receives either the signal SLL or the signal SLM and also the digital N value data DN supplied as external data, thereby the so-called frequency synthesizer is formed by the PLL circuit 14. That is, the circuit 14 contains therein a crystal oscillator Xtal and produces an oscillating output signal, the frequency of which signal is determined by the N value which is designated by the data D , thereby a phase-locked loop is maintained in a stable status, which the phase lock loop is constructed along a loop, that is, a low pass filter (LPF) 15-) the local oscillating frequency circuit 22 (or 32) + the OR gate 13 - the PLL circuit 14 H the low pass filter (LPF) 15. In this case, during the stable status condition of the phase-locked loop, the following equation, fSLL = N.fr or fSLM = N.fr is obtained, where f SLL and f SLM denote respectively the frequencies of the above mentioned signals SLL and SLM, N denotes the digital N value (DN) and f denotes the frequency of a reference signal, for example 9 kHz. The frequency of 9 kHz corresponds-to a minimum separation frequency, by which frequency a plurality of radio broadcasting frequencies, existing in the ranges of the RLW and the RMW in fig. 1, can be differentiated from one another. The explanations, mentioned above, are effected only on typical and conventional parts of the radio receiver circuit in fig. 4. The circuit according to the present invention will now be explained. The major part of the circuit according to-the present invention in fig. 4 is comprised of a comparating circuit 52, a first storage circuit 53, a digital N value generating circuit 54, a channel selecting circuit 55, including a second storage circuit therein, and an operating panel 56. The operating panel 56 is provided with a plurality of operating buttons, for example, as shown in Fig. 5. Fig. 5 is a front view of an operating panel which is used in the radio reciever, according to the present invention. In Fig. 5, the symbol PB represents preset buttons which can select, for example seven channel radio broadcasts. The symbol AT represents an automatic channel selection button for starting the sweep of the automatic channel selection upwardly. The symbol AT' represents an automatic channel selection button for starting the sweep of the automatic channel selection downwardly. The symbol MT represents a manual channel selection knob. When the knob is rotated clockwise, the sweep of the manual channel selection starts upwardly, while, rotated counterclockwise, the sweep thereof starts downwardly. The symbol VD represents a knob for a volume control. It should be noted that, instead of the above mentioned knob, momentary-type push-buttons can also be utilized. For example, when a momentary-type push-button (VD) is pressed ON, the sweep of the manual channel selection may be started upwardly, and alternatively, when a momentary-type push-button (MT) is pressed ON, the sweep thereof may be started downwardly. In this case, either one of the push-buttons (VD, MT) may be cancelled, if necessary. The symbol BS represents a band switching button which performs band switching between the AM (LW, MW) and the FM. In this case, the band switching between the LW and the MW is, as previously mentioned, not required. A display panel DP indicates what band is now selected and what receiving frequency is now selected. The symbol MB represents a memory button. The memory button MB is used when respective desired radio broadcasts are initially allotted to respective preset buttons PB. Returning again to Fig. 4, when the operations, defined by the flowchart of Fig. 3, are carried out, a desired one of the preset buttons (PB) on the panel 56, is placed ON. Then, the digital N value, corres onding to this desired preset button PB, is produced from the channel selection circuit 55 and set in the digital N value generating circuit 54. The circuit 54 provides the data DN , corresponding to the N value, to the PLL circuit 14. As a result, a desired radio broadcast, designated by the corresponding preset button, can be received. On the other hand, in Fig. 4, when the operations, defined by the flowchart of Fig. 2, are carried out, first the gist of the step is conducted by the operating panel 56 and the gist of the step f? is conducted by means of an LW/MW discriminating circuit (although which the circuit is contained in the channel selection circuit 55, but is not illustrated in Fig. 4) which controls the power switching circuit 51. The gist of step (c) is conducted by leans of the circuit 52. The gist of step (d) is conducted by arans of the circuit 54. The circuit 54 receives clock signal CLK from the circuit 14 and carries out the increment operation of the N value, that is N < N + 1. The gist of step is conducted in accordance with the condition whether or not a signal SID is generated from the circuit 43. When the signal SID is applied to the circuit 54, the circuit 54 stops receiving the clock signal CLK. The gist of step (hl is conducted by means of the aforesaid LW/MW discriminating circuit, but is not shown in Fig. 4. The gist of step Q is conducted by means of said LW/MW discriminating circuit which controls the circuit 51. The gist of step 7 is conducted by transferring data from the circuit 53 to the circuit 54. The gist of step 0 is conducted by means of the circuit 54, as is also step . The gist of step is conducted by means of the circuit 52. The gist of step Gm is conducted by means of said LW/MW discriminating circuit which controls the circuit 51. The gist of step is conducted by transferring data from the curcuit 53 to the circuit 54. Fig. 6 is a detailed block diagram of the circuit shown in Fig. 4, according to the present invention. The OR gate 13, the PLL circuit 14 and the low pass filter (LPF) 15, shown in Fig. 6, are identical to those shown in Fig. 4. The OR gate 13 receives the signals SLL and SLM and also receives a local oscillating frequency signal SLF of the FM, if necessary. If the upward sweeping automatic channel selection button 64-4 (see the AT of Fig. 5) is placed ON and a corresponding one of flipflops, in a flip flop array circuit 63, is set. An output from the flip flop is applied, via a line 101, to a sweep control circuit 62. Then, an up(increment)-control signal is applied, via a line 102, to the up(increment)-control input of each 4-bit programmable up/down counters 66-1, 66-2, 66-3 and 66-4. Thereafter, these counters 66-1 through 66-4 act as an up(increment) -counter. It should be noted that the counters 66-1 through 66-4 correspond to the digital N value generating circuit 54 of Fig. 4. The N value, corresponding tithe lastly Vg.ed- receiving frequency, is set into the counters 61-1 through counter 66-4, via respective lines 103, 104, 105 and 106, where the lastly used receiving frequency has been has been-stored in a second storage circuit 67. The above mentioned -set-ting of the digital N value is carried out when a load command sg';i4l is applied from the circuit 67, via a line 107, to each of the counters. The lastly used receiving frequncy can be held as it is, because the corresponding lastly used N value', held in respective counters 66-1 through 66-4, is trat ferred, via a line 108, to the second storage circuit 67 and the circuit 67 is maintained to be active by not sto,p-ping the supply of power thereto. In order to realize this, the power from the battery +B is always supplied, via a line 109, to the circuit 67. On the other hand, the power from the battery +B is supplied to the circuit block 10 of Fig. 4 via a switch which is connected in series with the battery +B. Accordingly, the circuit block 10 can be active or non-active by controlling this switch. In this case, the second storage circuit 67 can be made of a RAM (Random Access Memory) which corresponds to circuit 55 of Fig. 4. An LW/MW discriminating circuit 78 is employed so as to detect whether the N value, held in the counters 66-1 through 66-4, designates the LW or the MW (refer to step of Fig. 2). The circuit 78 can be realized very simply, if a particular fact is taken into consideration. That is, during the LW status, the N value is within the range of 67 X 81, while, during the MW status, the N value is within the range of 108 X 228. According to this fact, during the LW status, a logic bit "0" is developed on a line 111 connecting with the counter 66-3, while, during the MW status, a logic bit "1" or "0" is developed on the same line. Accordingly, the LW and the MW can be distinguished from each other by super vising a logic bit "0" or "1" developed on the line 111, with the aid of, for example a two-input OR gate. The output bit of the counter 66-1 corresponds to a LSB (Least Significant Bit) and the output bit of the counter 66-4 corresponds to a MSB (Most Significant Bit). Whether or not the N value, held in the counters 66-1 ¯ 66-4, designates the LW or the MW, can be determined by means of the circuit 78. The determination by the circuit 78 is transferred to a first storage circuit (corresponding to circuit 53 of Fig. 4) and a power switching circuit 79 (corresponding to circuit 51 of Fig. 4). The circuit 79 distributes a power PLW to be supplied to the LW circuit group or a power PMW to be supplied to the MW circuit group alternatively in accordance with the instruction from the circuit 78. If the circuit discriminates that the LW band is now selected (refer to "YES" of step in Fig. 2), the first storage circuit 73 (corresponding to circuit 53 of Fig. 4) produces data indicating the highest frequency Lmax of the LW, and supplies the data (fLmax) to a comparating input (II) of a comparating circuit 72. The circuit 72 can be made of a so-called digital comparator. The circuit 73 can be made of a ROM (Read Only Memory), and further the circuit 78 also stores, other than the above mentioned data indicating the highest frequency Lmax of the LW, data indicating the lowest frequency fLmin of the LW, data indicating, respectively the highest and lowest frequencies fMmax and of the MW. As mentioned above, the data, indicating the highest frequency fLmax of the LW, is now.fixedly applied to the second comparating input (II) of the comparating circuit 72, and simultaneously the N value of the counters 66-1 X 66-4 is applied to the first comparating input (I) of the circuit 72. This N value is increased one by one (refer to step in Fig. 2) under the upward sweeping automatic channel selection mode, if the button AT of Fig. 5 is placed ON. The N value, defined by the counters 66-1 X 66-4 can increase one by one, because these counters receive, via a line 112, a clock signal CLK (refer to the CLK of Fig. 4) supplied from a sweep controlling circuit 62. In this case, the clock signal CLK can be produced by dividing the high frequency clock signal, given from the PLL circuit 14, into a clock signal having the frequency of, for example 9 kHz, by means of a frequency dividing circuit 61. Thus, the counters 66-1 X 66-4 can increase their N value one by one, by receiving successive clock- signals CLK (refer to step in Fig. 2). The N value, increasing successively, is applied, as N value data DN t to the PLL circuit 14 successively via a data selector 65. In this case, the N value of the counters 66-1 X 66-4 is supplied from the data selector 65 to the PLL circuit 14 synchronous with a clock signal given, via a line 113, from the frequency dividing circuit 61. This synchronization is necessarily obtained, because the clock signal, on the line 113, is produced synchronous with the clock signal on the line 112. As explained above, the LW receiving stage 20 of Fig. 4 can sweep the receiving frequency range RLW successively by means of the PLL circuit 14. During this sweep of the receiving frequency, it is detected whether or not the radio broadcasting exists (refer to step z in Fig. 2). If a radio broadcast is received, the intermediate frequency detecting signal SID is produced from the intermediate frequency detecting circuit 43 of Fig. 4 and applied, in Fig. 6, to the flip.flop array circuit 63. At the same time, the flip flop, connecting with the upward sweeping automatic channel selection button 64-4, is reset and, accordingly the sweep controlling circuit 62 is de-energized by a signal transferred on the line 101. Consequently, the counters 66-1 X 66-4 are also de-energized and left as they are. Thus, the last N value of these counters is held as it is (refer to step f in Fig. 2). As a result, the radio broadcast on the LW band, specified by the last N value, can be received. During the successive increase of the N value, by the counters 66-1 X 66-4, if no radio broadcast is received (refer to "NOw step e in Fig. 2), then step h in Fig. 2 starts. In step h , if the LW/MW discriminating circuit 78 of Fig. 6 determines that the N value of the counters 66-1 X 66-4 designates the LW band, then step c in Fig. 2 is started again. Step c is conducted mainly by the com- parating circuit 72 of Fig. 6. As previously explained, since the circuit 72 now receives, at its second comparating input (II), the highest frequency fLmax of the LW band, the N value of the counters 66-1 X 66-4, applied to the first input (I) thereof, is compared with the frequency fLmaX with respect to a large or small relationship therebetween. When the N value of the counters becomes equal to the N value designating the frequency fLmax t it is concluded that the receiving frequency reaches the highest border of the range RLW shown in Fig. 1 (refer to "YES" of step Gc in Fig. 2). At this time, the comparating circuit 72 produces a coincidence signal and applies this signal, via a line 114, to the circuit 73. Then, the circuit 73 writes data, indicating the lowest frequency fMmin of the MW stored therein, into the second storage circuit 67 via a line 115. The write operation of the data (fMmin) is achieved in accordance with an instruction given by a read/write controlling circuit 71. The data (fMmi ), written in the circuit 67, is set into the counters 66-1 X 66-4 via lines 103 ¯ 106. Accordingly, the N value of the counters 66-1 X 66-4 is changed to the N value indicating the frequency fMmin. At this time, the circuit 78 detects the occurrence of band switching from the LW to the MW, by the signal transferred on line 111, and the circuit 78 instructs the circuit 79 to supply the power PMW to be supplied to the MW receiving stage 30 of Fig. 4. At this moment, the receiving frequency exists at the starting point of the frequency range RMW in Fig. 1. On the other hand, when the comparating circuit 72 produces the above mentioned coincidence signal on the line 114, the circuit 73 applies data, indicating the highest frequency fMmax of the MW band stored therein, to the second x comparating input (II) of the circuit 72. In this case, when the receiving frequency is witin the range of the BMW in Fig. 1, the circuit 72 fixedly receives, at its second comparating input (II), the data indicating the frequency of fMmax At present, since the band switching from the LW to the MW is performed, the result of step /;7 in Fig. 2 is now "NO" and, accordingly step Q starts. The result "NO" of step G is held as it is until the N value of the counters 66-1 X 66-4 reaches the N value corresponding to the frequency of f During this time, the circuit 72 cannot still produce the aforesaid coincidence signal therefrom. Therefore, step in Fig. 2 is conducted. Since the upward sweeping automatic channel selection button 64-4 is now pressed ON, the flip flop array circuit 63 signals to the sweep controlling circuit 62 and the circuit 62 controls, so as to make the counters 66-1 "s 66-4 as the up(increment) -counter which is driven by the clock signal. ,CLK. Therefore, the N value of the counters 66-1 X 66-4 increases one by one from the N value corresponding to the frequency f (refer to step in Fig. 2). If the intermediate frequency detecting signal SID is produced from the circuit 43 of Fig. 4 and applied to the circuit 63 of Fig. 6, the corresponding flip. flop of the circuit 63 is reset. Accordingly, the sweep controlling circuit 62 is de-energized and, then the counters 66-1 X 66-4 stop counting the clock signal CLK and hold the last N value thereof as it is (refer to "YES" of step e Ge1 in Fig. 2). If the received radio broadcast is not satisfactory for a radio listener, he places the button 64-4 ON again and starts step Ga in Fig. 2 again. When the N value of the counters 66-1 X 66-4 reaches the N value indicating the frequency of fMmax t the values of the first and second comparating inputs of the comparating circuit 72 coincide with each other, and then, the coincidence signal is applied to the circuit 73 via the line 114 (refer to "YES" of step Q in Fig. 2). Thereafter, the circuit 73 writes the data, indicating the frequency of fLmin stored therein, into the circuit 67 via the line 115. Further, this N value, indicating the frequency fL in t is set into the counters 66-1 ¯ 66-4 (refer to stepnin Fig. 2). At this time, the line 111 provides the logic bit "0" and, accordingly, the power PLW to be supplied to the LW receiving stage 20 is fed from the battery +B by means of the circuits 78 and 79. As a result, the band switching from the MW to the LW is automatically achieved (refer to step in Fig. 2). Also, at this time, the circuit 73 receives the aforesaid coincidence signal via the line 114 and applies the data, indicating the frequency of flmax t to the second comparating input (II) of the comparating circuit 72, fixedly. Thus, the sweep of the frequency begins from the starting point of the range RLW in Fig. 1. In the above mentioned operational sequence, step m and take place simultaneously and also steps Q and j take place simultaneously. The above mentioned operational sequence is performed by taking as an example a case in which the upward sweeping automatic channel selection button 64-4 is pressed ON. Contrary to this, when the downward sweeping automatic channel selection mode is selected the button 64-3 should be ON. In this case, the counters 66-1 "s 66-4 are controlled to operate as a down(decrement)-counter, by a signal transferred via the line 101, the circuit 62 and the line 102. Further, when the comparating circuit 72 produces the aforesaid coincidence signal, the circuit 73 supplies data, indicating the lowest frequency of Lmin (RLW) or Mmin (BMW), to the circuit 72, at its second comparing input II, while, the circuit 73 also supplies data, indicating the highest frequency of Lmax (RLW) or fMmax (RMW), to the circuit 67. However, the remaining operations to be conducted in the downward sweeping automatic channel selection mode, are substantially the same as those explained above regarding the upward sweeping mode. When an upward sweeping semi-automatic channel selection mode is selected, a button 64-2 should be turned ON, while, when a downward sweeping semi-automatic channel selection mode is selected, a button 64-1 should be selected. In such a semi-automatic mode, when the button 64-1 or 64-2 is turned OFF, the sweep controlling circuit 62 is suddenly de -energized. At the same time, the lastly received frequency is maintained in the radio receiver circuit. The flowchart of Fig. 3 will be explained with reference to Fig. 6. At step Go in Fig. 3, one of the preset buttons 70-1 X 70-7 (corresponding to PB of Fig. 5) is turned ON. A preset-latch circuit 69 detects the ON state which has been initiated by either one of the buttons 70-1 through 70-7 and further this detection is transmitted to the second storage circuit 67 via a line 120. The circuit 67 stores N values corresponding to the respective preset buttons 70-1 X 70-7 and, accordingly one specified N value is set into the counters 66-1 X 66-4 (refer to steps and and &commat; in Fig. 3). This, the PLL circuit 14 operates based on the specified N value and a corresponding desired radio broadcast can be received. In this case, step G in Fig. 3 is conducted by means of the LW/MW discriminating circuit 78. The desired broadcasting channels are allotted, in advance, to respective preset buttons 70-1 X 70-7 by the initial write operation of data into the circuit 67. When such initial write operation is required, a memory button 68S is turned ON (corresponding to MB of Fig. 5). Then a flipvflop 68 is set by the button 68S, and the circuit 67 is changed to a write operation mode by way of the read/write controlling circuit 71. For example, the manual channel selection knob MT of Fig. 5, is operated, and when a desired radio broadcast is received, both the memory button MB 685 and one of the preset buttons 70-1 X 70-7 are turned ON simultaneously. As a result, the N value of the counters 66-1 X 66-4, corresponding to the desired radio broadcast, is written into the circuit 67 via the line 108. The reference numeral 74 represents a band selector which cooperates with switches 75 and 76. The switch 75 corresponds to the band switching button BS of Fig. 5. The status whether or not the LW or the MW is selected by the button 75 is transmitted, via the selector 74, to the LW/MW discriminating circuit 78, the first storage circuit 73 and the second.storage circuit 67. In this case, the circuits 67 and 73 are activated at their respective AM storage areas (Note: The FM mode is not mentioned in the present invention). The switch 76 is used for selecting the LW mode or non-LW mode. If it is apparently expected that the radio receiver is used in a country where no LW radio broadcasting is transmitted, the switch 76 is electrically shorted in advance in the manufacturing factory. Thereby, the LW/MW discriminating circuit 78 is restricted to select only the MW band by a signal applied from the shorted switch 76, via the selector 74 and a line 121. The reference numeral 80 represents a display panel which corresponds to DP of Fig. 5. The information to be displayed on the panel 80 is given from an operation circuit 77. The circuit 77 can convert the selected N value of the counters 66-1 ¯ 66-4 into ordinary used digit numbers, for example 155 !kHzl. In this case, since the aforesaid reference frequency for (refer to the equation fsLL = N*fr or fSLM = N4fr) varies in every country, such as 5 kHz, 9 kHz or 10 kHz, the corresponding reference frequency for of each country should be specified by the circuit 73, via a line 122. The display panel 80 is driven by the clock signal fed from the frequency dividing circuit 61. The circuits 78 and 67 are also driven by the clock signal from the circuit 61. When the flip flop array circuit 63 is operated, the preset latch circuit 69 must not be operated and vice versa. In order to satisfy such an operational limitation, lines 123 and 124 are introduced between the circuits 63 and 69. That is, either one of the operated circuits (63 or 69) can reset the other circuit (69 or 63) by a reset signal transferred through the respective line 123 or 124. The reason why such an operational limitation is required is that manual channel selection and automatic channel selection must not be performed at the same time. Further, the reset of the flip-flop 68 is achieved, via the circuit 69 and a line 125, when either one of the preset buttons 70-1 through 70-7 is turned/pressed ON. As explained above in detail, the techniedl matters, previously mentioned in paragraphs (1), (2) and (3), can be satisfied by the radio receiver according to the preset invention.

Claims: CLAIMS 1. A radio receiver comprising: a LW receiving stage including a LW tuningamplifying circuit, an LW local oscillating circuit and a LW mixing circuit for converting a LW receiving signal into a LW intermediate frequency signal; a MW receiving stage including a MW tuningamplifying circuit, a MW local oscillating circuit and a MW mixing circuit for converting a MW receiving signal into a MW intermediate frequency signal; ; an intermediate frequency controlling stage including a detecting circuit and an intermediate frequency signal detecting circuit, the detecting circuit receives either one of said LW intermediate frequency signals or MW intermediate frequency signals, produced respectively from said LW receiving stage or MW receiving stage, and driving an audio frequency circuit, the intermediate frequency signal detecting circuit operates to detect the appearance of an intermediate frequency signal; a PLL circuit receiving either a LW local oscillating signal or- a MW local oscillating signal, produced respectively from said LW receiving stage or said MW receiving stage and feeding an oscillating output signal, which is specified by an externally supplied digital N value, to said LW tuning-amplifying circuit or MW tuning-amplifying circuit via respective feed back paths; and, a digital N value generating circuit producing said digital N value, characterized in that at least the following five means are further employed in said radio receiver, that is, a comparating means for receiving, at its first comparating input, said digital N value, a first storage means for storing both the lowest frequency fLmin and the highest frequency fLmax of a LW receiving frequency range and also both the lowest frequency fMmin and the highest frequency fMmax of a MW receiving frequency range, and the first storage means applying either one of the values fLmin and fLmax or either one of the values f and fMmax to said comparating means, at its second comparating input, a LW/MW discriminating means for receiving said digital N value and discriminating whether the digital N value specifies the LW or the MW, further designating either said values fLmin and fLmax or said values fMmin and fMmax according to the result of said discriminating operation, furthermore energizing either said LW receiving stage or said MW receiving stage, a second storage means, acting as a storage means for achieving transmission of the initial set of data to said digital N value generating circuit, for receiving, from said first storage means, the other of said values fLmin and fLmax or the other of said values fMmin and which values are stored in said first storage means, but not applied to said comparating means, and a sweep controlling means for increasing or decreasing said digital N value of said digital N value generating circuit by one integer upwardly or downwardly, in the sweep controlling means, when the upward sweeping of said digital N value is to be conducted, said values Lmax and fLmin t during the LW band, and said values fMmax and fMmin t during the MW band, are supplied, from said first storage means, respectively to said com- parating means, at said second comparating input and said second storage means, the band switching operation, between the LW band and the MW band, is carried out every time a coincidence signal is produced from said comparating means, while, also in the sweep controlling means, when the downward sweeping of said digital N value is to be conducted, said values Lmin and fLmax C during the LW band, and said values fMmin and and t during the MW band, are supplied, from said first storage means, respectively to said com- parating means, at said second comparating input and said second storage means, the band switching operation, between the LW band and the MW band, is carried out every time the coincidence signal is produced from said comparating means. 2. A radio receiver as claimed in claim 1, wherein said LW/MW discriminating means is made of a transistor which is turned/switched ON or OFF by two predetermined logic bits produced from said digital N value generating circuit. 3. A radio receiver as claimed-in claim 1, wherein said LW/MW discriminating means is made of a two-input OR gate which receives two predetermined logic bits produced from said digital N value generating circuit. 4. A radio receiver as claimed in claim 1, wherein said first storage means is made of an ROM. 5. A radio receiver as claimed in claim 1, wherein said second storage means is made of an RAM. 6. A radio receiver as claimed in claim 1, wherein said digital N value generating circuit is made of a programmable up/down counter.

Inventors: ITO, TATSUO
Applicants: FUJITSU-TEN, LTD
Application year: 1981
Main classification: H03J7
IPC codes: H03J7, H03J5, H04B1, H03J1