PLASMA CHARGE TRANSFER DEVICE

Abstract: A plasma charge transfer device display system includes input driver circuits (7) coupled to respective input driver lines of a display panel (3) and phase driver circuits (8) coupled to phase driver lines for shifting trapped charge in the panel (3). A power supply (9) provides a toggle voltage V which switches alternately between +140 volts and -60 volts and which is applied to the input driver circuits (7). Control logic (4) causes the voltages on selected ones of the input driver lines to switch from -60 volts to +140 volts simultaneously with the switching of the voltage on the first one of the phase driver lines from +140 volts to zero volts; the resulting large transient voltage changes cause gas discharges. The phase driver line switches back to +140 volts before the input driver line switches back to -60 volts. Trapped charges are progressed along the device in synchronism with switching of the phase drivers (8). The device operates with relatively low absolute magnitude voltages enabling implementation by hybrid or monolithic circuits.

Description: P ASMA CHARGE TRANSFER DEVICE Technical Field This invention relates to plasma charge trans¬ fer devices of the kind including a plurality of input driver circuits coupled to respective input driver lines, a plurality of phase driver circuits coupled to phase driver lines, said input driver lines and phase driver lines being connected to electrodes in gas-filled cells, and control means coupled to said input driver circuits and to said phase driver circuits. Background Art A plasma charge transfer device of the -kind specified is known from U.S. Patent Specification No. 3,781,600. In this known device, an input driver line is switched from zero volts to an input voltage V\ which is greater than the discharge voltage V , and shortly thereafter a first phase driver line is switched from V to zero volts, V being a sustaining voltage which is less than V_ and which is insufficient to cause dis- charge unless combined with the potential due to a trapped charge. Since V. > V, a gaseous discharge is caused between the input electrode and the adjacent electrode of the first cell. This discharge, however, is extinguished in a very short period of time and a wall charge is trapped on the wall of the dielectric covering of the electrode of the first cell. Such trapped charge is then caused to progress along the device in synchronism with the switching of successive p c hase driver lines from Vs volts to zero volts. In the embodiment described in said U.S. Patent Specification, Vi. is about 200 volts, V^ zz is about 180 volts and Vs is about 160 volts. The known device has the disadvantage that the voltage needs of the driver circuits are not readily compatible with implementation by hybrid or monolithi- cally fabricated devices in view of the limited voltage rating of such devices. s^_ k ^ ~ 01,-71 Disclosure of the Invention It is an object of the present invention to provide a plasma charge transfer device of the kind specified, wherein the aforementioned disadvantage is alleviated. Therefore, according to the present invention, there is provided a plasma charge transfer device of the kind specified, characterized in that said input driver circuits are adapted to provide first and second voltages of respective first and second polarities on said input driver lines, and in that said control means is arranged: to cause said input driver circuits to provide, on said input driver lines, said second voltage at the time a first of said phase driver lines is provided with a third voltage of said first polarity; to cause the voltages on selected ones of said input driver lines to switch from said second voltage to said first voltage and simultaneously to cause the voltage on said first one of said phase driver lines to switch from said third voltage to substantially zero voltage; and to cause the voltage on said first one of said phase driver lines to switch from substantially zero voltage to said third voltage before the voltages on said selected ones of said input driver lines are switched from said first voltage to said second voltage. In summary, there is described herein a circuit for energizing a plasma charge transfer display system of the type having a multiplicity of input driver circuits, individually connected through input lines to loading electrodes within the display panel, and a group of phase driver circuits, connected through phase lines to a prescribed pattern of other electrodes within the display panel. Charge is created by ionizing the cell gas between selected input electrodes and the first of the phase electrodes, and is shifted in a controlled manner to designated locations within the display panel by selectively energizing the succession of phase elec¬ trodes. The charge creation and transfer functions are_ regulated by a control logic block, which defines the sequence for energizing the input and phase driver circuits in order to create, shift and hold luminous patterns within the display. The input driver circuits are supplied with power from a switched voltage supply which alternates abruptly and sequentially between fixed positive and negative polarity voltage sources. Switch¬ ing is synchronized by the control logic. In one form, the amplitude of the positive polarity voltage source is selected so that it is sub¬ stantially equal to the voltage required to transfer trapped charge between successive phase electrodes. In such a case, the amplitude of the negative polarity voltage is constrained by the requirement that there be sufficient transient voltage to cause cell gas ionization between selected input electrodes and their adjacent phase electrodes when one is abruptly connected to the positive polarity voltage source as the other is connec¬ ted to the negative polarity voltage source. The two sources of voltage conduct power to the multiplicity of input driver circuits through a switching means which provides at its output either one or the other of the voltages, in a repetitive, rapidly transitioning se¬ quence. The phase driver circuits are energized through a direct connection to one of the voltage sources. The control logic block generates command signals which are directed to the multiplicity of input driver and phase driver circuits. The phase driver circuits are sequentially energized to provide the display phase electrodes with pulses having an upper level equal to the positive polarity voltage and a lower level of substantially zero voltage. The input driver circuits, however, are supplied with power from a switch¬ ing voltage alternating abruptly and periodically between positive and negative voltage levels. Whenever the switched voltage is negative in polarity, a non¬ linear conductive path applies it directly to all the input lines. During the positive polarity segment of he switched voltage, the input lines receive the posi¬ tive polarity voltage pulses, but only when the corres¬ ponding input drivers are energized by command signals from the control logic. Absent such command signals the associated input lines remain at substantially zero voltage during the positive segment. The control logic synchronizes the timing of the switching means, the input driver command signals and phase driver command signals to ensure that the electrode voltage levels, polarities and transition rates are appropriate for the formation of trapped wall charge and its transfer through the display panel. In addition, the control logic, according to the teaching in the prior art, selectively energizes the input driver circuits at each timing interval to create prescribed patterns within the display panel. In the context of the embodiment, the control logic energizes the input and phase driver circuits so that input electrodes prescribed to load charges into the display are connected to the negative polarity voltage through the switching means when the first of the phase electrodes is energized with the positive polarity voltage. Thereafter, the selected input electrodes are rapidly driven to the positive voltage level by the switching means as the first phase electrode is brought abruptly to substantial¬ ly zero voltage, causing the cell gas to ionize and thereby create a wall charge on the first of the phase electrodes. At the onset of the second phase, control logic command signals energize the first phase driver circuit to provide positive polarity voltage to the first phase electrode at the same time that the second phase electrode driver circuit output is commanded from its normal positive voltage level to a substantially zero voltage. Accordingly, trapped charge adjacent the first phase electrode is transferred to a location adjacent the second phase electrode. The succeeding phase command signals used to shift, hold and erase -5- trapped charge are well understood from the teachings in the prior art. Brief Description of the Drawings Fig. 1 contains a block diagram schematically showing an embodying plasma charge transfer type display system. Fig. 2 is a schematic diagram of a switching power supply. Fig. 3 contains a schematic diagram of the phase driver circuits. Fig. 4 contains*a group of seven voltage versus time plots depicting the waveforms at various electrical nodes within the display system. Fig. 5 shows the schematic diagram of an embodying input driver circuit. Best Mode for Carrying Out the Invention The described embodiment utilizes an electronic circuit configuration particularly suited for energizing the high voltage electrodes in a d.c. input plasma charge transfer type display system, when using hybrid or monolithically fabricated devices having moderate voltage capability. More particularly, the embodiment describes the construction and interconnection of driver circuit groups, using a multiplicity of substantially identical electronic devices, operated from a dual polarity voltage source, to load, shift, hold and erase data within a shift type plasma display. The ensuing disclosure presumes that the reader is versed in the art of shift type plasma display systems as generally taught in U.S. Patents 3,781,600 and 4,051,409. These patents are particularly useful, since they provide the funda¬ mental operating characteristics of the display panel in such a way that the distinguishing features of the present invention can be discerned from the polarity and timing of electrical signals on a group of voltage versus time plots. OMPI _ In an attempt to maintain continuity with the cited art, the schematic depicted in Fig. 1 utilizes a similar format. Furthermore, within the body of this specification, like elements are designated with identi- cal reference numerals. Though the art is replete with teachings of display systems and the conceptual aspects of their control, the practical problem of actually implementing the display operations is far from rudimentary when the multitude of conflicting objectives and constraints are recognized. This is particularly true in cases of the type at hand, where the display panel contains a great multitude of data lines, while the cost and size of the driving elements is highly constrained. Undoubtedly one is aware that microcomputers are readily available to implement the control logic. Miniaturization of the driving elements is, however, limited by the voltage amplitudes required at the electrodes of the display to properly load, shift, hold and erase information within the display panel. As is recognized from the prior art noted above, transient voltages in excess of 300 volts, as well as sustained levels of a nominal 200 volts, are required to operate such plasma charge transfer systems. The normal inclination to use hybrid or monolithically fabricated driver devices, in an attempt to reduce electronic component size and power consumption, is not reconcilable with the voltage needs of the panel. Moderately priced and readily available devices of this type are normally rated at voltages nominally less than 150 volts. Therefore, those practicing in the art gen¬ erally utilize high voltage discrete components operated in conjunction with one or more single polarity power supplies. In terms of modern microelectronics, the physical size of discrete device driver circuits is tremendous, and grows in proportion to the number of data lines in the display. Though the embodying display panel depicts only seven data lines, a representative commercial display would more likely contain in excess of thirty lines. The disadvantage of using discrete driver elements is self-evident. Attention is now directed to Fig. 1 of the drawings, where one embodiment of the invention is schematically depicted in block diagram form. For purposes of contrast, deleted keep-alive driver circuit block 1 and erase driver circuit block 2, typifying the prior art, are shown in location by way of dashed lines. Display panel 3, control logic block 4' and character generator block 6 are substantially identical to the counterparts described in the latter of the above-noted U.S. patents. Any unique features attributable to these three blocks will become self-evident from the descrip¬ tion of the invention embodiment. Consequently, the focus of attention will be directed to input driver block 7, phase driver block 8, power supply block 9 and the unique interconnection with display panel 3 to obtain the voltage reduction objectives sought. First consider the structure of power supply block 9, as it is depicted in Fig. 2 of the drawings. Electrical power is provided to the block from a conven¬ tional voltage source having both +140 volts D.C. and -60 volts D.C. The supply output line designated V 0 is merely a continuation of the former D.C. voltage. The output voltage designated V rn OG is otherwise. V τ θG ' generally referred to hereinafter as the toggle voltage, takes the form of an unbalanced square wave switched abruptly between -60 volts and +140 volts at a rate defined by the synchronization command signal entering at line 11. The command signal supplied to line 11 is a periodic, square, positive-going voltage pulse generated in control logic block 4. Since the operation of the switching circuit in Fig. 2 is as a whole rudimentary, an intimate description of each element's operation is considered superfluous. It suffices to note that that circuit is fundamentally non-inverting and operates such that the absence of a positive voltage command signal on line 11 drives V TQG to the -60 volt extreme of its excursion, while the presence of the signal causes saturation of transistors 12 and 13, and accordingly, an output of +140 volts. The cyclic rate of the command signal, and V TQG derived theref-rom, defines the maximum rate at which data, in the form of trapped wall charge, can be entered into the display panel. Attention now turns to phase driver block 8, shown in Fig. 3 to contain within a single structural unit four identical, hybrid phase driver circuits. At this point it is also useful to note that the time plots of the different circuit voltages are depicted in Fig. 4. For purposes of distinguishing the various phase driver block output voltages the waveforms are designated with subscripts β A to Ώ . One input to phase driver block 8 is the +140 volt D.C. voltage V^ the others are com¬ prised of a group of command signals # to ? originating in control logic block 4. The number and relationship of the input phases are described adequately in the above-noted prior art. Therefore, it suffices to note that the embodying command and phase driver output signals are characterized by step changes in voltage which follow the ordered, repetitive sequence shown in Fig. 4. Though time coincident, the amplitudes of command signals $7, to ?-. are the inverse of the waveforms depicted in Fig. 4, namely zero when V„ to V_ are at +140 volts and some moderate positive m AagnitudeD during the time when the phase driver output voltages are at the zero level. Recalling that the contemplated device forming control logic block 4 is a microprocessor, the voltage peaks of command signals 7. to #_ will fall within the range of 5 to 15 volts. The electronic elements forming the internal circuitry of phase driver block 8 also appear in Fig. 3. An example of a commercially available device internally configured in the manner shown is the hybrid inverting driver circuit designated by part number KH6844 and manufactured by Toko, Incorporated. Recognizing that c ~ .:π - 9- the operation of the device is within the understanding of those working in the art, only the idiosyncrasies of this circuit, as they uniquely suit the needs of the display panel system, will be accentuated hereinafter. For purposes of driving the embodying display panel phase lines, it need only be noted that diode 14 in the circuit is unnecessary, in view of the positive polarity of V and the low relative magnitudes of command signals øL to j? D in comparison to V 0 . Attention is now directed to input driver block 7, schematically depicted in Fig. 5 of the drawings As clearly appears, the internal structure of each driver circuit is identical to that shown in the above- described phase driver block. However, the number of individual input driver circuits is significantly great¬ er, in that an individual driver circuit is needed for each data line in the display panel. The embodiment shows seven such lines. The command signals entering block 7, I, to I 7 , emanate from control logic block 4, and are characterized as being either zero or low posi¬ tive amplitude voltage pulses. Distinguishing from the phase driver block, the power supplied to input driver block 7, V T0G , is not a fixed D.C. level, but rather, comprises a square wave periodically switching between -60 volts and +140 volts. A time plot showing the waveform appears in Fig. 4. An analysis of the toggle voltage waveform and the electronic elements in each circuit driving an input line of the display panel reveals that the signals V to V are complex partial modulations of V T0G with command signals I, to I 7 , respectively. The actual waveforms on exemplary input lines will be described in detail during the ensuing analysis of the system opera¬ tion. Presently, for purposes of understanding the circuit in Fig. 5, it suffices to note that diode 16 and the PN junction between the base and collector leads of transistor 17 are forward biased during the period when V is negative in polarity. Functionally, this is _OMFI -10- equivalent to the phantom diode shown at reference numeral 18, providing negative supply voltage protection. In contrast to the phase driver circuit described ear¬ lier, diode 19 in the input driver circuit is a neces- sary element to prevent the effects of a negative V from propagation through the PN junction of tran¬ sistor 21 to molest the command signals I, to I.,. With an understanding of the functional blocks and their constituent circuits at hand, the succeeding inquiry will dwell on their cooperative interaction to properly actuate the display panel. The beneficial practical considerations noted previously, namely over¬ coming the inherent voltage limitations of hybrid and monolithic drivers, will become apparent. Likewise, the innate ability to delete ancillary circuits, such as keep-alive drivers 1 and erase drivers 2, will become evident. Consider now the multitude of voltage waveforms as they appear in Fig. 4, selectively representing the voltage versus time characteristics at various locations in the embodying display system of Fig. 1. As a prelude to the operational description, however, note that the plots of exemplary input driver voltages, V and V τ , transition between their positive and negativ 1e extrem5es no earlier than, and preferably after, phase voltage V ff reaches its positive extreme and V„. reaches its plots shows the slightly delayed transition embodied. The purpose for this delay is to ensure that trapped wall charge adjacent each φ. electrode in the display panel consistently transfers to a point adjacent pf_ ___ electrode, rather than return to the input electrode by way of a backfire. The deleterious effect known as backfire is described in the former of the previously noted U.S. patents. The first plot shown in Fig. 4 represents the toggle voltage, v TOG , spanning a range of -60 volts to +140 volts with respect to system ground. Immediately below are plots of two, representative input driver voltages, V_ and V_ . The remaining four waveforms plQtted in the Figure are the phase driver voltages. Since the important aspects of the invention focus on the loading segment of the panel operating sequence, the plots depict only that segment. The extension of these teachings to the shift, hold and erase segments is thought to be rudimentary in view of the cited prior art, and therefore, omitted from the plots. Commence the analysis of the display system's operation by noting the amplitudes of exemplary input nt in time immediate- l d h l se in _ 0G to its +140 volt level. With the toggle voltage at -60 volts, and the previously described path through diode 16 and transistor 17 of the input driver circuit, shown in Fig. 5, the -60 volts appears on line 1 and electrode 1 of the display panel. The state of input electrode 5 is the same. Note also-, that during this same period of time the voltage V~ applied to phase line A and elec¬ trode A of the display panel is at +140 volts. At the next point in time of concern, t Q , the toggle voltage switches abruptly from -60 volts to +140 volts. However, output voltages V τ and V τ , from 1 5 the first and fifth input driver circuits, do not follow the toggle voltage unless the appropriate zero voltage command signals, I, and I,-, are present. In the waveform depicted, command signal I, is at the zero volt level while signal I,- is at a nominal positive voltage. For contrast compare the effects at each of the input lines. First consider the characteristics and effects of the voltages applied to input electrode 1 and adjacent phase electrode A. At time t Q , the synchronization of command signals from control logic 4 drives the phase voltage V- from its previous +140 volt level to a substantially zero level, as it drives the input voltage V from its -60 volt level to a +140 volt level. The cumulative effect, however, is significantly greater since the cell gas experiences a relative transition of 340 volts between the input and phase electrodes when compared to the state prior to time t Q . This transient voltage variation is sufficient to cause cell gas ioni- zation and a trapped charge formation adjacent phase A electrode. In contrast consider the time t„ activity at input electrode 5. As shown in the plot, though V 0 undergoes an abrupt switch from +140 volts to a zero level, input voltage V is limited to a zero level rise x 5 by the control logic command signal to the input driver circuit. Consequently, the cell gas only experiences a 200 volt transition of relative voltage, an amplitude inadequate to ionize the cell gases and cause trapped charge adjacent phase A electrode in line 5. The next point in time of interest is t, . At time t, command signals are .directed to phase driver circuits A and B, increasing voltage V 0 and decreasing voltage V_ . With an understanding of the prior art at hand, one readily recognizes that the positive charge trapped adjacent phase electrode A of line 1 is trans¬ ferred to phase electrode B in line 1. At phase elec- trode A of line 5, however, there is no positive wall charge, consequently no transfer to phase electrode B in line 5. Viewing the whole of the input waveforms depic¬ ted in Fig. 4, the voltages show that line 1 is loaded with data represented by three successive bits of charge, while line 5 contains a charge bit between two non-charged bits. The 140 volt relative transition attendant the phase A voltage rise at t, is less than the magnitude necessary to ionize the gas between input electrode 1 and phase electrode A. At some point in time soon after t,, the toggle voltage is commanded by logic block 4 to revert to its -60 volt level. Accordingly, input driver volt- O PI ages V and V follow to that level. The short delay between 1time t, 5and the transition of the toggle voltage is, as was noted hereinbefore, inserted to ensure that charge trapped adjacent phase electrode A moves to phase electrode B rather than undergo a backfire to input electrode 1. Furthermore, the delayed transition of the toggle voltage significantly reduces the magnitude of the relative voltage change experienced by the cell, substantially suppressing the gas ionization associated with the input voltage transition to its -60 volt level. A salient feature of the invention can be discerned by noting the magnitudes of voltage impressed across the various devices in the input and phase driver blocks. Notwithstanding the 340 volt transient and 200 volt steady state amplitudes impressed across cell electrodes, the devices used in the circuits require a nominal operating voltage of only 140 volts. The desir¬ ability is self-evident, since this voltage is within the limits of commercially available hybrid and raonolith- ic devices. Another beneficial aspect of the invention resides in the polarity of the voltages as they are developed in Fig. 4. Note lation to V , immediately zation time. This polarity coincides with the objective that positively charge ions, and not electrons, be trapped adjacent phase A electrode, to facilitate sub¬ sequent shifting into the display panel. The invention depicted in Fig. 1 provides a number of ancillary benefits. As shown, the conventional keep-alive driver circuit, 1, is supplanted by connecting one energizing terminal of a pair of keep-alive electrodes to the toggle voltage, V T0G , and the remaining energizing terminal of the pair of keep-alive electrodes to the phase driver voltage V- . An analysis of the corres- ponding waveforms in Fig. 4 shows the presence of a periodic 200 volt transition, adequate to repeatedly ionize the gas between the keep-alive driver electrodes -14- within the display panel. Connection to phase driver line D represents merely one example of implementing the keep-alive function. Others of the phase driver lines are also viable alternatives, as long as the voltage in that phase continues to alternate during display panel operation. An example of an unacceptable keep-alive connection is a phase which is not toggled during a hold sequence in the display. Note also from Fig. 1 that the previously necessary erase driver block, 2, is readily replaced with a soft erase circuit connected to phase driver line A. As shown, to implement the soft erase circuit the display erase electrodes are connected to a common terminal for collecting charge onto capacitor 22 and slowly dissipating that charge through directional diode 23 and resistor 24. The invention as described herein presupposes the need for a nominal 340 volt transition between display electrodes to obtain consistent ionization of cell gases and reliable wall charge formation. Like¬ wise, the 140 volt phase driver amplitude corresponds to that which is reasonably necessary to reliably transfer charge during display panel operation, tempered by the voltage capabilities of commercial hybrid and monolithic devices. Common use of a single +140 volt supply in this embodiment thus dictates the -60 volt amplitude of the negative power supply. The invention as a whole, however, fully contemplates relative variations in the voltage amplitudes and polarity distributions as may be necessary to suit the particular needs and capabilities of the plasma charge transfer display panel actually utilized. G .1PI

Claims: CLAIMS : 1. A plasma charge transfer device including a plurality of input driver circuits (7) coupled to respective input driver lines, a plurality of phase driver circuits (8) coupled to phase driver lines, said input driver lines and phase driver lines being connec¬ ted to electrodes in gas-filled cells, and control means (4) coupled to said input driver circuits (7) and to said phase driver circuits (8), characterized in that said input driver circuits (7) are adapted to provide first and second voltages of respective first and second polarities on said input driver lines, and in that said control means is arranged: to cause said input driver circuits (7) to provide, on said input driver lines, said second voltage at the time a first of said phase driver lines is provided with a third voltage of said first polarity; to cause the voltages on selected ones of said input driver lines to switch from said second voltage to said first voltage and simultaneously to cause the voltage on said first one of said phase driver lines to switch from said third voltage to substantially zero voltage; and to cause the voltage on said first one of said phase driver lines to switch from substantially zero voltage to said third voltage before the voltages on said selected ones of said input driver lines are switched from said first voltage to said second voltage. 2. A plasma charge transfer device according to claim 1, characterized in that non-selected ones of said input driver lines are supplied with substantially zero voltage during the time that said first voltage is applied to selected ones of said input driver lines. 3. A plasma charge transfer device according to claim 2, characterized by power supply means (9) coupled to said control means (4) and to said input 3 . ( concluded ) driver circuits (7), said power supply means (9) being arranged to provide an output voltage sequentially switching between said first and second voltages. 4. A plasma charge transfer device according to claim 3, characterized in that said input driver circuits (9) are continuously conductive to said second polarity voltage and selectively conductive to said first polarity voltage. 5. A plasma charge transfer device according to claim 4, characterized in that the amplitude of said third voltage is sufficient to cause transfer of trapped charge between successive ones of said gas-filled cells. 6. A plasma charge ^ transfer device according to claim 5, characterized in that the sum of the absolute values for said first, second and third voltages exceeds the ionization voltage of the gas in said cells. 7. A plasma charge transfer device according to claim 6, characterized in that the absolute values of said first, second and third voltages are nominally less than 150 volts. 8. A plasma. charge transfer device according to claim 7, characterized in that said first and third voltages are equal. 9. A plasma charge transfer device according to claim 8, characterized in that said first voltage is positive, said second voltage is negative and said input driver circuits include hybrid or monolithically fabricated inverting transistorized circuits (7) having negative supply voltage protection and a negative supply voltage current path between said input driver lines and said power supply means (9). 10. A plasma charge transfer device according to claim 3, characterized by a pair of keep-alive electrodes having first and second energizing terminals, said first energizing terminal being coupled to said power supply means (9) and said second energizing ter¬ minal being coupled to one of said phase driver lines. 11. A plasma charge transfer device according to claim 3, characterized by a plurality of erase driver lines associated respectively with said input driver lines, said erase driver lines being commonly coupled to one of said phase driver lines via a soft erase circuit (22, 23, 24). OMFI s -. V ^i Λ -f P t O c-i

Inventors: CURRY JOHN LESLIE
Applicants: NCR CO, NCR CORP
Application year: 1981
Main classification: H05B41
IPC codes: G09G3, H05B41