BIPOLAR LOGIC CIRCUIT

Abstract: A bipolar logic circuit has a resistance (any of RS₁ to RS₅)) connected between one current-amplifying transistor (Q₁ or Q₂) and a following current-amplifying transistor (Q₂ or Q₃ respectively). The resistance (RS₁ to RS₅) stabilises the output waveform of the circuit. Alternative dispositions of the resistance within the circuit are allowed. A current source (IP₁) for example constituted by a resistor (R₁) is provided. Control of the current (I) delivered by the current source, and/or of the value of the resistance (RS₁ to RS₅) allows the input threshold voltage of the circuit to be selected.

Description: Bipolar Logic Circuit This invention relates to a bipolar logic circuit. A defect of previously proposed logic circuits, which involves the disturbance of an output waveform as a result of the influence of adjacent circuits and parasitic capacitance, will be explained with reference to the following drawings; Fig. 1 of the accompanying drawings is a circuit diagram of a previously proposed bipolar logic circuit, Fig. 2 is a waveform diagram showing an output waveform of the logic circuit of Fig. 1, Fig. 3A is a circuit diagram of a circuit having a large collector capacitance, and Fig. 3B illustrates a pattern arrangement corresponding to the circuit of Fig. 3A In Fig. 1, a diode D1 has a forward voltage VF of 0.4 (V) and transistors Q1 to Q3 have a VBE of 0.8V and a threshold voltage of 2.0 (V), for example. If an input voltage IN is higher than 2.0 (V), base current for the transistor is supplied from the transistor Q1, the first stage transistor, to the transistor C2 the next stage transistor, through the emitter of the transistor Q1 The transistor Q2 is turned on, whereby base current for the transistor 031 the output stage transistor, is supplied from the emitter of the transistor Q2- As a result, the transistor Q3 is turned on. At the same time, the collector potential of the transistor Q2 falls, thus turning off another transistor Q4, another output stage transistor. In consequence an output OUT of the logic circuit falls to L level. Conversely, if input voltage IN is lower than 2.0 (V) the transistors Q1' t2 and Q3 are turned off and only the transistor Q4 is turned on, whereby the output OUT rises to H level. If a logic circuit of this type is fabricated in a high speed and high packing density integrated circuit, the waveform of the output OUT is deformed in some instances, being affected by parasitic or stray capacitance or the like. In particular, it is quite possible that when the output OUT falls from H level to L level, one or more peaks PK follow as shown in Fig. 2, thus deforming the waveform of the output OUT. Fig. 2 is a representation. qf an oscilloscope waveform showing how the output OUT changes with Vcc as parameter. It also illustrates the waveform of the input IN. In the circuit of Fig. 1 the polarity of the input IN is opposite to that of the output OUT. The cause of the one or more peaks EK can be attributed to many factors. One factor is the collector capacitance of a transistor used. Nore precisely, since the first stage transistor Q1 has a large capacitance Cc, indicated in Fig. 1, an oscillation occurs in a loop A (indicated by a broken line) which feeds the output OUT back to the input terminal through the base and emitter of the transistors Q1 and Q2 and which is capable of amplifying current. In consequence, such peaks PK as are shown in Fig. 2 are generated. This undesirable phenomenon is prominent in, for example, a circuit such as is shown in Fig. 3A. In this circuit a plurality of transistors Q - n have their emitters commonly connected and their collectors commonly connected, thus constituting a logical OR gate. The bases of the transistors Q R Qn are connected to receive respective inputs INa-INn. The output of the logical OR gate is a n coupled to a gate G. If the circuit of Fig. 3A is fabricated as an integrated circuit, the integrated circuit will have a pattern such as is shown in Fig. 3B. That is, the transistors Qa-Qn will be formed in the same island L, which functions as a collector common to all the transistors Qa-Qn. Therefore it is natural that the capacitance Cc of the common collector is very large. In Fig. 3B, a collector electrode is indicated as C, E represents an emitter electrode and B designates a base electrode. semen the transistor Q1 of the circuit shown in Fig. 1 is one of the transistors Qa¯Qn shown in Fig. 3B, the collector capacitance of the transistor Q1 is large. In this event the waveform of the output OUT of the circuit of Fig. 1 has peaks PK. It will now be described more in detail why the butput OUT has such peaks PK as are shown in Fig. 2. If the transistor Q1 for amplifying current has a large collector capacitance Cc (e.g. a large parasitic capacitance), the input current supplied to the base is, as shown in Fig. 1, divided into a current I1 flowing to the embitter and current 12 flowing to the collector when the input IN rises from L level to H level. Since the collector capacitance C of the transistor Q1 is large, a time c constant C .R of the transistor Q1 is large proportionally C and the collector potential of the transistor Q1 inevitably undergoes so called undershoot operation (indicated by US in Fig. 2). In a case in which there is delay in recovering from the under-shoot operation, the base current of the transistor Q1 so flows as to charge the capacitance , As the result, the transistor Q1 will be turned off. Once the transistor Q1 is turned off, its collector potential starts rising again. In this way the collector potential falls and rises repeatedly. Consequently, a pulsating current flows through the emitter of the transistor Q1 The pulsating output current of the transistor Q1 is amplified by the transistor Q2' which generates a larger pulsating current. The output current of the transistor is then amplified by the transistor Q3, which generates a still larger pulsating current. The output current of the transistor Q3 is amplified by the transistor Q. As a result, the output OUT has a waveform similar to that of the emitter current of the transistor Q1- Obviously, it has several peaks PK. A further defect of previously proposed bipolar logic circuits will be explained with reference to Fig. 4 of the accompanying drawings, which is a circuit diagram of a TTL circuit. Usually, the input threshold voltage Vth of a TTL circuit is specified by the sum of base-emitter voltages VBE of transistors used in the circuit and/ or the forward voltage or voltages VF for a diode or diodes. No distinction is made hereinafter. In the circuit of Fig. 4, the transistors Q to Q8 determine the input threshold voltage Vth. The potential of a point R is the sum of the VBE1s of the transistors Q6 to Q8 (VBE6 to VBE8) and the input IN is at potential lower by one VBE (VBE5). Thereby, the level of output OUT is determined according to whether the input voltage is higher or lower than such input threshold voltage Vtho The threshold voltage Vth of the TTL circuit shown in Fig. 4 is expressed by the following equation. Vth = BE6 + VBE7 t VBE8 - VBE5 Therefore, the VBE1S of the transistors must be changed in order to change the threshold voltage. However, the VBE of a transistor is specified by the emitter ize and is usually selected within the range from 0.7 to Pt8V, For example, when the VBE's of the transistors are equal, Vth can be selected only within the range from 1,4 to 1.6V. In addition, it is also possible to vary the VBE's of the transistors but the range of variation pt threshold voltage is still limited and production processes must be changed. Therefore, it is undesirable to vary the VBE's of the transistors. According to the present invention there is provided a bipolar logic circuit, characterised in that a resistance is provided in the current path in the circuit which determines the input threshold voltage of the circuit. An embodiment of the Present invention can Drovide a which TTL or DTL circuit/nas stable output waveforms, and can provide for the free setting of input threshold voltage. An embodiment of the present invention can provide a bipolar logic circuit which prevents disturbance of output waveforms as a result of the influence of adjacent circuits and parasitic capacitance and which provides a stable waveform. An embodiment of the present invention can provide a bipolar logic circuit with stable output waveforms by the addition of only a simplified circuit, and can provide for free selection of threshold voltage. An embodiment of the present invention provides a bipolar logic circuit comprising a first current amplifying transistor and a second current amplifying transistor, the base of which is connected to the emitter of the first current amplifying transistor, and in which a resistor is inserted in the path between the emitter of the first current amplifying transistor and the base of the second current amplifying transistor. An embodiment of the present invention provides a bipolar logic circuit in which a current. source is connected between the resistor and the lower voltage power source. Reference is made, by way of example, to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a previously proposed bipolar logic circuit, Fig. 2 is a waveform diagram showing an output waveform of the bipolar logic circuit of Fig. 1, Fig. 3A is a circuit diagram of a circuit having a large collector capacitance, Fig. 3B illustrates a pattern arrangement corresponding to the circuit shown in Fig. 3A, Fig. 4 is a circuit diagram of a previously proposed TTL circuit, Fig. 5 is a circuit diagram of a first embodiment of the present invention, Fig. 6 is a graph illustrating the relationship between emitter current and base-emitter voltage of a transitor used in the circuit of Fig, 5, for assistance in çxpXan-atiQn of the present invention, Fig. 7 is a waveform diagram illustrating an output waveform of the circuit shown in Fig. 5, Fig. 8 is a circuit diagram of a second embodiment of- the present invention, Fig. 9 is a waveform diagram illustrating output waveforms of the circuit shown in Fig. 8, illustrating the effects provided by virtue of the present invention. Figs. 10 (a) and 10 (b) are circuit diagrams of different forms of a third embodiment of the present invention, Fig. 11 is a circuit diagram of a fourth embodiment of the present invention, Fig. 12 is a schematic circuit diagram illustrating a further embodiment of the present invention, Fig. 13 is a graphical representation of input/output transfer characteristics of the embodiment of the present invention shown in Fig. 12, Fig. 14 is a circuit diagram illustrating a form of the embodiment of the present invention shown in Fig. 12, Fig. 15 to Fig. 17 are circuit diagrams for assistance in explanation of further embodiments of the present invention, Figures marked (a) illustrate previously proposed circuits whilst Figures marked (b) illustrate generally corresponding embodiments of the present invention,and Fig. 18 and Fig. 19 are circuit diagrams illustrating respective examples of current sources which can be employed in embodiments of the present invention. The embodiments of the present invention shown in Figs. 5 to 11 illustrate bipolar logic circuits so formed as to prevent disturbance of output waveforms. Fig. 5 shows a first embodiment of the present invention. The circuit of Fig. 5 is similar to the circuit of Fig. 1, except that resistances RSl and R52 are connected in series between the emitter of a transistor Q1 and the base of a transistor Q2 and except that resistances R53, Rs4 and R55 are connected in series between the emitter of the transistor and the base of a transistor Q3. The resistances RSl - R55 are used to stabilise the output signals of the transistor Q1 and Q2' Alternatively, only one resistance may be connected between the emitter of the current amplifying transistor Q1 and the base of the next-stage transistor Q2 and/or only one resistance may be connected between the emitter of the transistor Q2 and the base of the next-stage transistor Q3. The resistances R51 - R55 are so connected as mentioned above in order to apply negative feedback on input signals to the transistors Q1, Q2 and 03. It will now be described how the resistor RS1 functions, with reference to Fig. 6. Fig. 6 illustrates the relationship between emitter current 1E and base-emitter voltage VBE of the transistor A voltage drop is created at the resistance RS1 in the opposite direction to and in response to a variation 1E of the emitter current. This voltage drop suppresses variation of the emitter current IE. When the emitter current IE changes by # IE, the base-emitter voltage VBE changes by ss VBE The resistance R51 reduces the change 4 VBE As a result, the base-emitter voltage VBE varies in the directions of arrows Y and ultimately reaches a stable point K. That is, even if the transistor Q1 generates a pulsating current, the resistance R51 reduces the peaks of the pulsating current. All the other resistances R52 - R55 perform the same function as the resistance RSl. The resistances of RSl-RsS must be determined according to the value of a current which flows in the circuit including the resistances ESl-RS5 For example, they are determined according to the impedance of the circuit including the resistances RSl-Rs5 so that the voltage VRS between the resistance RSl and the resistance R55 may lie in the range 50mV to 100 mV. If the voltage VRS is normally 60mV, variation of the voltage VBE can be fully compensated even if the variation is so large that the emitter current IE would be reduced in about 1/10. Hence the emitter current 1E can remain stable and constant. Fig. 7 shows the waveform of the output OUT which is generated in a case in which only the resistance RS1 is used and has a resistance of 110Q . The condition of input IN in Fig. 7 is similar to that illustrated in Fig. 2. In-Fig. 7 outputs OUT of different levels, with VCC as parameter, are shown. As is evident from Fig. 7, no peaks are generated after an under-shoot US has taken place. Fig. 8 illustrates a second embodiment of the present invention. In the circuit of Fig. 8 a stabilising resistor RS is connected between the emitter of transistor Q1 and the base of transistor Q2. Fig. 9 shows calculated values representing waveforms which the output OUT of the circuit may have when the stabilising resistor R5 in Fig. 8 is set to various resistance values. As will be clearly understood from Fig. 9, when the resistance of the resistor R5 is 0, (i.e. when no stabilising resistor is provided) the circuit generates an output OUT having the same waveform as the output OUT of the circuit shown in Fig. 1. It is a good assumption that this output OUT has two peaks PK1 and PK2. lwhen the resistance of the resistor R5 is 5061 or 150#, in an embodiment of the present invention, the circuit generates an output OUT which has no peaks whataPeverP Indeed the output OUT may be delayed due to the stabilislug resistor R5. This delay is negligibly small and no problem is experienced in practice if the resistance Of the resistor R5 is about 10% or less of the impendance of the whole circuit. Fig. 10 shows a third embodiment of the present invention. This third embodiment is shown in two forms in Fige 19, (a) and (b)-, respectively. The circuit of Fig. 10 (a) is a DTL circuit, and the circuit of Fig. 10 (b) is a TTL circuit. Each circuit uses two current stabilising resistors RS1 and RS'2. In each case the resistor Rfi1 is connected between the emitter of a transistor Q1 and a resistor R', and the resistor RSw2 is connected between the resistor R' and the base of a transistor Q3. It is not necessary to use both resistors R51 and Ras,2; Any one of them can serve to stabilise the output of either the DTL circuit or the TTL circuit to a sufficient degree. Fig. 11 shows a fourth embodiment of the present invention. The circuit of Fig. 11 is identical with the circuit of Fig. 5 except that a transistor Q0 is connected to receive an. input signal, in place of diode D1. In the circuit of Fig. 11 all the current stabilising resistances RSl-Rs5 need not be used. It is sufficient to use at least one current stabilising resistance The embodiments of the present invention described below utilise at least one stabilising resistance as explained above, and moreover are capable of providing for easy changing of the threshold voltage Vth of a bipolar logic circuit such as a TTL or DTL circuit. These embodiments of the present invention will be explained in detail with reference to the embodiments shown in Figs. 12 to 19. Fig. 12 illustrates an embodiment of the present invention applied to a TTL circuit similar in form to that of Fig. 4. The threshold voltage Vth of the TTL circuit of Fig. 12 can be changed over a wide range by means of a resistor R'5 which is inserted in series into the path extending from the emitter of transistor Q6 to the base of transistor Q7, called the phase splitter, and a constant current source IP which supplies a current I. In the TTL circuit of Fig. 12, a voltage VRS, generated by the resistor Rs, is included in the input threshold voltage Vth. Therefore, the input threshold voltage Vth is expressed by the following equation: Vth = VBE6 +VBE7 + VBE8 + VRS VBE5 ... (2), and VRS, = I Ras, ............... (3) A base current for transistor Q7 flows when the transistors Q8, Qg turn on, but it is sufficiently low to be ignored for values near Vth The minimum value Vth(min) of Vth which can be achieved in accordance with equation (2) can be expressed by the equation (4),which is the same as equation (1), since Vth (min) is obtained when R = 0 or I = 0. th(min) = VBE6 + VBE7 + VBE8 - PE5 .....(4) On the other hand, the maximum value Vth(max) of Vth can be set as-high as the power source voltage Vcc, but ifs properly expressed by equation (5) when a margin VtbM allowing the TTL circuit to be turned ON stably is considered. Vth(max) =Vcc - VthM ................(5) In general, it is recommended to set V thN to a value 1.6V which is the value of two stages or higher with VBE being set almost to 0.8V (VBE = 0.8V). The operation of the TTL circuit of Fig. 12 is similar to the operation of the circuit of Fig. 1. when input voltage to the transistor Q5 > Vth, the transistor Q5 turns OFF, transistors Q6 to Q8 turn ON and Qg turns OFF Thereby output OUT becomes L. On the other hand, when input voltage < Vth, the transistor Q5 turns ON, transistors Q6 to Q8 turns OFF and Q9 becomes ON. Thereby output OUT becomes H. Figure 13 illustrates input/output transfer characteristics where the operating point of the output OUT, namely the threshold voltage Vth of the input IN, becomes small, with Vth (min) of equation (4) considered as the lower limit, when the current I or resistance RS, is set small, and where the operating.point becomes large, on the other hand, with Vth(maX) of equation (5) considered as the upper limit, when the I or RS, is set large. In Fig. 12, D3 is a speed-up diode which extracts base charges from the transistor Q7, and D4 is a level shift diode for output OUT. The resistor Rs, inserted in the path extending from the emitter of the transistor Q6 to the base of transistor Q7 also plays a role, as explained above, as a stabilising resistor for the output waveform. Figure 14 is the schematic diagram indicating a modification of Fig. 12 in which the current source is realised with a very simple structure, the resistor R1 In Fig. 14, when the transistor Q5 is OFF, the transistors to to Q8 are ON, whilst'Qg is OFF. Therefore the output OUT is at L level. At this time, a voltage which is equal to the sum of the VBE's of the transistors Q7 and Q8, VBE7 +VBE8 is applied across the resistor R1 and a current I, (VBE7 + VBR8)/R7 flows through this resistorR1 Since VBE7, and VBE8 change little, the current I becomes constant and the resistor R1 operates as a constant current source. On the other hand, when the transistor Q5 is ON, the transistors Q6 to Q8 become OFF. Therefore, no voltage is applied across the resistor R1 and the reistor R1 can be ignored. hMen the current source IP1 is formed by a resistor as in Fig. 14, the input threshold voltage Vth can be set merely by providing two resistors R5, and R1 having selected resistance values. The TTL circuit of Fig. 12 can be roughly divided into an input stage including transistors Qg, Q6 and an invertor including transistors Q7 to Qg. The input stage can take various modified forms as shown in Figs. 15 to Fig. 17, and the structure of the invertor is not limited only to that shown in Fig. 12. Fig. 15(a) to Fig. 17(a) are schematic circuit diagrams of the respective previously proposed TTL or DTL circuits which differ only in their input stages, whilst Fig. 15(b) to Fig. 17(b) are schematic diagrams of respective further embodiments of the present invention corresponding in general terms to circuits of Figures 15(a) to 17(a) respectively. In Fig. 15(a), the transistor Q6 (of Fig. 12 or Fig. 4) of the input stage is replaced by a diode D5 and the forward voltage of the diode has effect. In a corresponding circuit embodying the present invention, as shown in Fig. 15(b), the resistor RS, is inserted between the cathode of diode D5 and the base of transistor Q7, whilst the resistor R1 is inserted between the base and earth GND. The threshold voltage V Vth can be set as in the case of Fig. 14 merely be selecting the values of resistor Rs, or R1. In Fig. 16(a),.the transistor Q5 of Fig. l5(a) is replaced by a diode D6, thus forming an input stage. In this case, connection of the resistors Rs, and R1 in the corresponding circuit embodying the present invention is the same as is shown in Fig. l5(b) as indicated in Fig. 16(b). Figure 17 (a) illustrates an input stage in which the diodes D5, D6 of Fig. 16(a) are replaced by one npn transistor Q1o. The diode D3 is omitted. As shown in Fg, 17(b), in the corresponding circuit embodying the present invention the resistor R5, is connected between the collector of transistor 1O and the base of transistor Q7 whilst the resistor R1 is connected between the said base and the earth GND. In each of the embodiments, a resistor Rs, is inserted between the input stage and the invertor. Since the threshold voltage Vth, as explained above, is determined by the total of the VBE's within the circuit, as viewed from the input IN, it is possible to insert a corresponding resistor in a different location, so long as the location is selected to lie within the path which determines the threshold voltage Vth In addition, the current source IP1 shown in Fig. 12 can be realised most easily as a resistor but it goes without saying that the current source can naturally be formed by any other desirable method, for example as shown in Fig. 18 and Fig. 19. Fig. 18 illustrates another embodiment of the present invention, of which the circuit is identical to that of Fig. 14 except for the structure of the current source IP2bounded by broken lines in Fig. 18. In Fig. 18, current source IP2 is formed by a diode D6 and a resistor R4, which are connected in series between power source Vcc and GND, and a transistor Q14 whose base is connected to the anode of the diode D6. The current I flowing through transistor Q11 is the same as the current ID flowing through the diode D6 in Fig 18. Therefore, the current I is expressed by the following equation. (VF is forward voltage of the diode D6) EMI19.1 The current source IP2 shown in Fig. 18 is useful in cases in which it is necessary to determine the input threshold voltage Vth correctly. Fig. 19 illustrates another possible current source structure for use in embodiments of the present invention. The current source IP3 of Fig. la is formed by a resistor R4, a resistor R5, two diodes D7 and D8 connected in series between power source Vcc and GND, and transistor Q11 whose base is connected to the anode of the diode D8. In Fig. 19, current I' flowing through the transistor Q11 is expressed by the following equation. (VBEll is the VBE of Q Vr is forward voltage of the diodes D8, Dg) EMI20.1 The current source IP3 can allow input threshold voltage Vth to be set correctly in spite of fluctuation of power source voltage Vcc. An embodiment of the present invention can provide a bipolar logic circuit which generates an output signal having a stable waveform. The more current amplifying transistors the circuit has, the more will its output waveform be deformed if no current stabilising resistance is used. In view of this fact, a bipolar logic circuit embodying the present invention is useful because its output waveform is corrected or stabilised by the provision of as few as one current stabilising resistance. Further, even if a bipolar logic circuit embodying the invention has an IC structure as generally illustrated in Fig. 3, collector capacitance CC is no longer problematical, thus allowing various pattern arrangements. Moreover, the input threshold voltage of a bipolar logic circuit embodying this invention can be changed or selected over a wide range using only a simple structure, thus improving the degree of freedom available in design. An embodiment of the present invention is uninfluenced by adjacent circuits even when it is a high density integration and high speed bipolar logic circuit, such as TTL or DTL, and disturbance of output waveforms due to parasitic capacitance is avoided, by the insertion of a resistor in the path between an emitter of a first current amplifying transistor and the base of a second amplifying transistor. Noreover, an embodiment of the present invention can provide a bipolar logic circuit of which the input threshold voltage can be selected over a wide range by applying a current to the said resistor using a current source. A bipolar logic circuit has a resistance (any of RS1 to RS5) connected between one current-amplifying transistor (Q1 or R2) and a following current amplifying transistor (Q2 or Q3, respectively). The resistance (RS1 to RS5) stabilises the output waveform of the circuit. Alternative dispositions of the resistance within the circuit are allowed, A current source (IP ) for example constituted by a resistor (R1) is provide, Control of the current (I) delivered by the current source, and/or of the Value of the resistance (RS1 to RS5) allows the input threshold voltage of the circuit to be selected.

Claims: Claims 1. A bipolar logic circuit, characterised in that a resistance is provided in the current path in the circuit which determines the input threshold voltage of the circuit. 2. A bipolar logic circuit, having an input terminal and a current-amplifying transistor, characterised in that a resistance is provided in the current path in the circuit from the input terminal to the current-amplifying transistor. 3. A bipolar logic circuit as claimed in claim 2, wherein the resistance is inserted between a transistor arranged for receiving signals from the input terminal and the said current-amplifying transistor. 4. A bipolar logic circuit as claimed in claim 2, wherein the resistance is inserted between a diode arranged for receiving signals from the input terminal and the said current-amplifying transistor. 5. A Bipolar logic circuit comprising a first current-amplifying transistor and a second current-amplifying transistor, the base of which is connected to the emitter of the first current-amplifying transistor, characterised in that a resistance is inserted in the path between the emitter of the first current-amplifying transistor and the base of the second current amplifying transistor. 6. A bipolar logic circuit comprising a diode and a current-amplifying transistor, the base of which is connected to the cathode of the diode, characterised in that a resistance is inserted in the path between the cathode of the diode and the base of the current-amplifying transistor. 7. A bipolar logic circuit as claimed in claim 6, further comprising another current-amplifying transistor, the base of which is connected to the emitter of the current amplifying transistor of claim 6. 8. A bipolar logic circuit as claimed in any preceding claim, wherein a current source is connected between the said resistance and- a power source voltage line. 9. A bipolar logic circuit as claimed in claim 8, wherein the input threshold voltage of the bipolar logic circuit is changed by changing the value of the said resistance and/or the value of the current which flows through the current source when the circuit is in use. 10. A bipolar logic circuit as claimed in claim 9, wherein the current source comprises a resistor which is connected between the said resistance and a lower power source voltage line. 11. A bipolar logic circuit as claimed in claim 9, wherein the current source comprises a transistor having its collector connected to the said resistance, its emitter connected to a lower power source voltage line, and its base connected to a higher power source voltage line via a resistor, and a diode connected between the base of the transistor of the current source and the lower power source voltage line. 12. A bipolar logic circuit as claimed in claim 9, wherein the current source comprises a transistor having its collector connected to the said resistance, its emitter connected to Åa lower power source voltage line via a resistor, and its base connected to a higher voltage power source voltage line via another resistor, and two diodes connected in series between the base of the said transistor of the current source and the lower power source voltage line.

Inventors: UENO, KOUJI
Applicants: FUJITSU LIMITED
Application year: 1981
Main classification: H03K19
IPC codes: H03K19