MULTI-MASTER PROCESSOR BUS

Abstract: Presently, the interconnection of multiple processors results in decreasing the speed of operation of the system each time a processor is added to the interconnecting bus. The present invention enables the bus to operate at least eight times faster than in the prior art. A multi-master processor bus and a method of processing data which permits multiple microprocessors (10) to communicate freely and inexpensively among themselves and various system resources (12). The bus uses a multiphase clock (16-18) and latches (32, 114) to provide time slice signals to sequentially activate each processor, one at a time in a repetitive sequence. The bus includes cables (40) and terminals (176) for each of the cables with means for interconnecting each of the modules (10, 12) in series daisy chain fashion to selected cables.

Description: Multi-Master Processor Bus Specification The present invention relates to a multi-master processor bus which permits multiple microprocessors to communicate freely and inexpensively among themselves and various system resources. The invention permits easy expansion of functionality without modification of the individual processors and thus contemplates a very large scale computer system which can be built with a number of micrqproces.sors. i The Prior Art The current state of the art technology allows only one to three processors to share a common system bus at the same time. Many of the bus structures in use today cannot even handle two processors without elaborate and expensive direct memory access (DMA) controllers, bus multiplexers and conflict resolvers. Current microprocessor system buses are extremely wasteful in exploiting bus bandwidth. When a microprocessor accesses a typical system bus, it will wait on the bus until it receives or transmits the desired data. Most microprocessors have. bus cycle time of 500 to 1000 nsec. . The actual data transfer could be accomplished within a fraction of that period. While a given processor is waiting for its data, it effectively locks out any other processors from using the bus. The Advance of the Present Invention The multi-master processor bus of the present invention allows a large number (N) of processors to share a common system bus simultaneously without conflict and requires very little or no hardware overhead and a very simple software that is embedded within each processor board. Each processor board is identical to each other in every respect, mechanically, electrically, and in firmware (if desired}. A limit of eight master processors is typically chosen as a practical guide for assembly and test, but additional processors theoretically could be added to the system. In accordance with the present invention the backplane that supports the bus is a simple standard network of wires that interconnects the various system modules. The system controller is made up of only two standard medi-mri scale integration chips (MSIs) that can be integrated within the backplane. The multi-master processor bus greatly increases the effective bandwidth of the"system bus by employing a time multiplex packet driven architecture. The architecture allows unlimited global system resources, it allows each master processor unlimited private resources and allows multiple ulti-master processor buses to be interconnected. The Present Invention More specifically, the present invention relates to * a multi- master processor bus for interconnecting a plurality of processor modules comprising a plurality of cables each having a plurality of connecting lines to a plurality of sets of processor module terminals for attachment to a plurality of processor modules. Cables are supplying at least the following purposes: interrupt request; interrupt acknowledge; address and control; time slice vector and clock; and data. Clock means provides periodic impulses and counter means is assocated with the clock to count the impulses and generate a multiphase clock. The cable connections include cables and means for OΪ.-PI t - 3 - interconnecting each of the modules in series daisy chain fashion to both the interrupt request and interrupt acknowledge cables. The invention also contemplates a method of processing data using a plurality of master processors which are provided with parallel cable connections to a bus. By the method one of the master processor is selected arbitrarily to be the master master to designate which processor shall be active, accept data or output data to other processors. Time slice signals are then provided to sequentially grant access to the bus by each of the processors one at a time in a repetitive sequence. Drawings of a Preferred TSmbodiment of the Invention A preferred embodiment of the present invention is illustrated_in the.accompanying drawings in which: _..._ • -. Fig. 1 is em overall block schematic diagram of the multi- master processor bus in the connection system, showing interconnections of a plurality of processors; Fig. 2 is a more detailed schematic block diagram showing a bus/processor interface typical of the present invention; ' •; Fig. 2A is a block diagram showing the interrupt request enable/disable portion of a processor module; Fig. 3 is a similar block diagram of a bus/resource module interface example; . _ . . . . . . ... . Fig. 4 is another block diagram showing a further bus/resource interface example, a resource module's interrupt request logic; Fig. 5 is a multi-master processor bus backplane schematic with certain block input elements illustrated; Figs. 6, 7, and 8 are each composite time scale graphs relating to various signals within a multi-master system. The system in accordance with the present invention consists of master processor modules, global resource modules, system timing controller and a backplane. A master processor module contains a processor and some combination of read only memory, read/write memory, input/output devices and some control logic. These components are for the private use of the processor. The processor module also contains an interface to the system bus. Only processor modules may access the system bus. Processor modules are also known as bus masters or master modules. A global resource module may be any combination of read only memory (ROM), read/write random access memory (RAM), input and output devices (I/O), and dedicated processor subsystems. It also contains an interface to the system bus. Global resource modules may not access the system bus unless specifically requested by a master processor. The system timing controller consists of a master clock and logic to provide an N phase system clock that is encoded into log, n bit field. This logic preferably is incorporated into the backplane bus circuit board. The backplane is a simple linear array of sockets and inter¬ connections for the system. The various system modules may be plugged into the backplane in any sequence and in any quantity as long as the master processor limit of N is not exceeded. Another feature of the multi-master processor bus system is that each system module may run asynchronously with respect to each other The system bus, however, is a synchronous bus. The multi-master processor bus is also called a "global bus". Each master processing module may be a self-sufficient computer, capable of operating even if it is not.plugged into the multi-master processor bus. Referring first to Fig. 1, a multi-master processor bus system as whole is shown schematically. In this diagram, there are a plurality of processor modules 10a, 10b, 10c, and implicitly there are other modules up to lOn. Similarly, there are shown resource modules 12a and 12n with the possibility of intermediate resource modules. The resource modules as explained above are connected to the multi-master processing bus, or global bus 40 only in response to actions or commands from a processor module 10a, 10b, 10c... . The multi-master processor bus 40 consists of a plurality of multi-wire cables. One of those cables is time slice vector and clock bus 14. Connections are made to the bus 14 from the various modules by connection lines. Processor module 10a is connected by connection 14a. Resource module 12a is connected to bus 14 by lines 14b. Processor module 10b is connected by lines 14c. Processor module 10c. is connected by lines 14d. Processor resource module 12n is connected by lines 14n. The time slice vector and " clock bus is provided at input from a counter 16 which is triggered by a 16 MEGA hertz clock 18. The output of the counter is applied to buffer 20 which also buffers the clock 18. The buffer puts a signal out on the time slice vector and clock bus 14 and thereby enables application of that pulse to each of the modules. The time slice vector pulses are effective on AND gates sequentially conditioned in the various modules. The multi-master processor bus also includes interrupt acknowledge bus 22 and the interrupt request bus 24. Tne interrupt request is applied to the input of the first processor module 10a by bus ' 24x. The signal can be generated by any of the nodules by connection buses 24a, 24b, 24c, 24d, and 24n. The Interrupt Acknowledge signal is only generated by Processor Modules. The Interrupt Request signal s usually generated by Resource Module. However, these signals are supplied to each module interface to allow any module to be put into any position on the Global Bus. For example, master processor module 10a may gain access to resource module 12a iy interconnecting interrupt request bus 24xa. A similar bus connects C:-.Ϊ? resource module 12a and processor module 10b bus 24xb. Similarly, bus 24xc connects processor module 10b and processor module 10c. Then, bus 24xd connects the next intermediate module and so forth until the next to the last module is connected lay line 24xπ to resource module 12n. The interrupt acknowledge bus 22 is connected to input bus 22x to processor module 10a which, in turn, is interconnected by bus 22xa to resource module 12a. Resource module 12a is interconnected by interrupt acknowledge bus 22xb and interrupt acknowledge bus 22xc interconnects processor module 10b and processor module 10c. Processor module 10c is connected to the next module (not shown) by interrupt acknowlege bus 22xd and the next to the last module is connected to resource module by interrupt acknowledge interconnection bus 22xn. The interrupt acknowledge signal may be supplied by any of the modules by buses 22a, 22b, 22c, 22d, and 22n. Data bus 26 and address and control bus 28 complete the essential buses, and each of them has bus connections to the module as follows: connection cables 26a and 28a to processor module 10a; cables 26b and 28b to resource module 12a; cables 26c to processor module 10b; connection cables 26d and 28d to processor module 10c; connection cables 26n and 28n to processor module 12n. The multi-master processing bus architecture shown in Fig. 1 supports a very powerful operating system that is extremely small in size and relatively simple in overall complexity. The πulti-master processor bus signals require differing numbers of lines in the global bus. The following numbers of lines are typically required for the specified signals: 23 for Address; 16 for Data; 3 for Time Slice Vector; 1 for Device Busy, 1 for Read ^ Write, 1 for upper Data Strobe; 1 for Lower Data Strobe; 1 for Reset; 1 for Global Interrupt Request; 1 Global Interrupt Daisy-Chain In; 1 for Global Interrupt Daisy-Chain Out; 1 for Master 16 MHZ Clock; 1 for Data Ready; 1 for Interrupt Vector Request; 1 of Global, interrupt Cr Acknowledge; 1 for Global IACK Daisy-Chain In; and 1 for Interrupt Acknowledge Daisy-Chain Out, making a total of 56 lines. Each master processor module 10a, 10b, 10c, lOn is self- sufficient as a computer system. Preferably, but not necessarily, each master processing module is identical to every other module. An encoder means is employed in connection with the counter 16, clock 18, and buffer 20 system to assign a given multi-processor module its time slice, and each multi-processor module and each resource module is given an individual time slice, preferably. An encoder, not shown in Fig. 1, but having connection to master cables 26 and 28. The encoder cam also be read by the system software embedded in each master processor module (MPM) to determine its status relative to each of the other master processor modules in the system. Upon system initialization, each master processor module " initializes its own system components. The system components may consist of universal asynchronous receiver transmitters (UARTs), parallel input/output devices (PIOs, etc.). At this stage, the master processor module then reads its time slice encoder to determine where in the global memory (predefined points) each successive master processor module can pass information and commands to the other master processor modules. Each master processor module then clears its own command block and global memory and sets a flag that signals other master processor modules that it is present and functioning properly. The master processor module, which was assigned a zero time slice by arbitrary choice is designated the master master processor module. The master master assumes the duties of the system supervisor and is responsible for initializing the global resource modules in the system. It also assigns other master processor modules to various tasks as needed. Each master processor module as it completes its assigned tasks enters an idle loop and checks its command block in C FI global memory for new tasks to perform. The command block is a segment of memory set up by the master master to allow communications among various master processor modules and contains commands, pointers to program and data structures, and status words needed to perform a task. The various processor modules are connected in a so-called "daisy chain" to other master processor modules. The master master, if it is the earliest master processor module in the interrupt request daisy chain 24x, 24xa, 24xb, 24xc, 24xd, ... 24xn, can be used to handle all global interrupt requests by always enabling interrupts to itself and inhibiting the interrupt request signals from propogating through the daisy chain to the other master processor modules. The - master master then performs the required system functions prior to assigning a master processing module to process the interrupt generated task. The master master is a supervisor only by default and at any time and for any reason may transfer its system responsibilities to any other master processor module. For example, it may detect an internal hardware fault and trigger the change. Each master process module may communicate with other master processor modules through a "back door" (a communication link external to the multi-master processor bus) to allow the system to recover from catastrophic faults. For example, it is possible the master master may encounter a severe fault. This ability allows the remaining master processor modules to choose a new master master and ignore the failed master master. Each master processor module should also have internal time-out capability to enable the master processor module to disengage itself from a global bus transaction in the event of a serious bus fault. Perhaps a master processor module would access a global resource module that was always busy and this condition could lock up the master processing module without time-out capability. - 9 - It will be understood that there are other ways of operating the system of the present invention and the above description is intended to be by way of example of what can be done. Fig. 2 is an example of an interface between a multi-master processor bus and a processor module designed to use a Motorola microprocessor. Referring now to Fig. 2, the structure shown is a multi- master processor bus/processor interface example. As seen in Fig. 2, processor data bus 34 is connected to the global bus 40 through a series of buffers 30a, 30b, and latches 32a and 32b used to collect data from the global bus 40 through a global data path 38 by way of input bus 36. The buffers are conventional buffers used to connect to or isolate an individual processor and the global bus. The latches are registers -used to latch " data from the global bus during those times which are the individual processor*s time slice. Internal cables connect the processor through the cable 34 to the buffers and latches and cable 36 through global data interchange connects the buffers and latches to the multi-master processor or global bus 40. In addition to the data interchange to the .system described, there is a series of buffers 42a, 42b, 42c between a common address bus 44 to the processor and an output cable 46 to the global address system. Global address contact is made through cable 48 to the multi- master processor bus 40 or global bus. Through this system the global resource is addressed and selected. Also involved is a global control which may have to do with other procedural processing factors which are handled through buffer 50 through a global control cable 52 to the multi-master processor bus. Global inquiry lines axe provided with the signal lines for input and output of the global interrupt requests, respectively, GIRQOUT 56 and GIRQIN 58. There is also a line 60 carrying the master clock MCLK for each of the processors in the system. The line 62 accesses a comparator 64 which senses the voltage applied at the input side and makes a comparison with connecting lines 68 and a dip switch 72 to ground line 70. If the processor wants to read the dip switch encoder value, data is fed out of the buffer 66 to the processor date bus 74 when released by a signal on line 76. The comparator 64 also has a line 78 outputting the voltage E t and applying it to the OR gate 80. This signal is known as the "valid time" signal and its output voltage E ou ^ is active when the time slice vector matches the dip switch encoding on the dip switch 72. When the other input terminal of OR gate 80 is enabled by a processor request to access a global resource, a processor request signal is generated. Junction point 82 provides a processor request for global resources applied to the OR gate 84 which generates a read encoding signal REN when a low active (read, not write) signal is also present. The output of gate 80 is applied to the D terminal of D type flip—flop 86 to turn it on when the clock signal is applied by the master clock to the clock terminal. The alternate outputs at terminals Q and Q to provide mirror image signals at these two terminals. Q terminal outputs a VGR (Valid Global Request) signal and is applied to OR gate 88 and AND gate 90 to generate RCLX (the signal used to latch data from the global bus) and BEN (signal used to enable processor data onto the global bus) signals respectively. A low active signal from the Q terminal coincides with a (read, not write) R W signal at OR gate 88 to generate (BEN). A signal. GRDY indicating a Global bus ready at OR gate 90 generates an output signal used to latch data from the global bus into the latches for use by the processor. Also involved in the system is a flip-flop latch system which results in a DTACK output. Global busy (G BUSY) line 92 which acts on O...PI the D type flip-flop 96 terminal D to turn the flip-flop on and generate mirror image clock signals, at outputs Q and " β- The GRDΫ line 94 applies a signal to the D terminal of flip-flop 102 producing similar clock outputs. Flip-flop 102, like 96, is operable to pass a bus transfer signal when a valid global request occurs. Both flip- flops are cleared when the processor cycle ends, signaled by falling edge of DS. Output signals also appear at AND gate 98 when enabled by W/R signal. When the flip-flop is on, a clock signal is applied through AND gate 104 if a read, not write, signal R/W is applied. If signals appear from OR gates 98 and 104, an low active output through NOR gate 100 generates a DTACK (a signal to the processor indicating signal on line 106). Global interrupt vector request GIVRQ is generated when interrupt acknowledge signal is applied to inverter amplifier 108 and to NAND gate 110 in the presence of the valid global request signal. The system of Fig. 2A is associated with the system of Fig. 2 and represents a logic circuit used by a processor to steer the global interrupt request to itself or pass it down the line of processors in connection with the activity of the global bus. The circuit is relatively simple consisting of a flip-flop 180 that is controlled by the processor to steer the global interrupt request GIRQ IN signal. Depending upon the flip-flop output activated, the OR gate 182 refuses the input and generates GIRQ OUT or the OR gate 184 generates IRQ output to the processor accepting the global interrupt. Fig. 3 is an example of the interface logic needed to build a global resource module. The module is a memory module without the ability to request global interrupts. It should be noted in this regard that each nodule responds to an 8 bit address field. The most significant 8 bits of the address is the module address. The logic involves a delay line which is used to match the bandwidth of the iR incoming request with the bandwidth of the memory devices. As in Fig. 2, access in Fig. 3 to the global bus 40 is through a global data line 38 or through a global address and control line 48/52. Global data is provided through buffers 112a and 112b or through registers 114a and 114b. Data is fed through an internal data bus line 34 from the RAM array 120. RAM array 120 is addressed through the internal address line 44. Read and write instructions are given through an internal R/W line 51, which is also connected to registers 114a and 114b. The address presented by the master processor is fed through the global bus to the global address and control lines 48/52 to the registers 116a, 116b, and 116c which store the address presented by a master processor, whichever one is selected. Key data is fed from chip 116a through the terminals B0, Bl, B2 of comparitor chip 122 which provides an output indicating that the vector is approved. At the same time, the read, not write, signal R/W is amplified and inverted by inverting amplifier 124 to a write, not read signal W/R which is appled to an OR gate 126 terminal which generates a signal in the presence of a VECTOR OK signal or a write signal to the AND gate 128. AND gate 128 provides an enabling DONE signal output to control chip 130. Global address information is also fed from the global bus line 48 to the comparison chip 118 which provides an output whenever the global address matches the fixed module address. The low active output is treated by inverting amplifier 132 and fed to the AND gate 134 which outputs to the clock terminal of another D type flip-flop 136. The AND gate 134 clocks flip-flop 136 when a masterclock signal, a module select and a not busy signal coincides. A not busy BUSY signal generated by the flip-flop 136 when it is actuated by the AND gate 134, and a voltage V χ is present at the D terminal of the D type flip-flop 136 will provide a BUSY clock signal through the Q terminal to the delay line 138 signal at flip-flop 140 clock terminal. The delay line O delays the clock application to the D type flip-flop 140, but it is ultimately applied turning to flip-flop 140 and applying the signal to gate 128 enabling that gate to operate to produce a DONE signal to chip 130. When the signal is passed through AND gate 128, it indicates that the operation is complete. A clear signal is applied to clear flip-flops 136 and 140 after the operation is complete. A RESET signal is required during system power up and is applied to flip-flop 130. A BUSY signal is applied to counter the ARRAY ENABLE of the RAM array 120 to disable the memory whenever the module is not busy. The not busy BUSY signal which normally is generated by flip-flop 136 is applied to AND gate 142 as well as gate 134. NAND gate 142 in the presence of a MODCS signal enables the global bus and other equipment to be advised that the resource module is being addressed by the system. When the process is complete, a signal applied through the operation complete line out KAND gates 144 and 146 will be possible in the presence of read, not write, signals R/W. A read signal is applied thereto also to produce the GDRDY and BUFEN outputs shown to inform the rest of the system of the resource module condition. Fig. 4 is an example of an interrupt requester module interface. This interface may exist in a global research module or in a processor module. When a module requests an interrupt, it must have the interrupt vector ready on its internal data bus 34. ' Once the interrupt vector is requested, the interrupt vector is presented through the buffers 112a and 112b through the output cables to the global data line 38 and to the master processor bus 40. Low active global vector request GIVRO signal is amplified and inverted through inverter amplifier 148 and applied to one terminal of NAND gate 150.to produce a BEN (used to enable the buffers) and to one input of NAND gate 152 which produces a low active global device ready signal GDRDY at its output. Each of these NAND gates has a low active signal indicating interrupt acknowledge I CK. The master clock provides an input to clock terminal of D type flip-flop 154 and an IRQ is input at terminal D to turn on the flip-flop. The presence of an interrupt request will produce an output at each of the Q and Q terminals of D type flip-flop 154 to one terminal of OR gates 156 and 160, respectively. A signal (low active) from OR gate 156 will clear the interrupt request flip-flop 158. Flip-flop 158 receives an edge signal from a device within the module at the clock terminal and a fixed level at the D terminal to provide an interrupt request output IRQ at the Q terminal. OR gate 156 will also transmit an IACK signal (GIACK OUT) signal in the presence of a low active signal representing a global interrupt acknowledge input GIACKIN. When an interrupt request IRQ is generated at flip-flop 158, that signal is applied through an inverting amplifier 162 to provide a low active global interrupt request signal GΣBQ. Fig. 5 represents a back-plane diagram showing some of the detail of the interconnection of the multi-master processor bus, or the "global bus" so-called, which has been shown generally in other τ3rawings as member 40. The back plane provides plug-in terminal connections for circuit cards and typically a 12 card back plane assembly will fit in a standard 19 inch equipment rack. The back plane allows 2 inches of mechanical mounting overhead. The schematic drawing of Fig. 5 represents connections for the chip side of the boards connectors. Only connections for the front side of the system or approximately a sixth of the three circuit boards, for each processor, is represented. The other termi al arrays are similar to those shown, and will be understood to have similar arrangements but with different connections. The pull-up resistors are used only for some of the control signals which are generated by open-collector gates or for generating default and non-active command signals in the advent some system boards are removed. The lines between the terminal connections OMPI represent hard wiring or cable connections. The blocks shown represents the time slice vector generator or system controller. Reset in the system is controlled through a reset switch which applies or removes a signal between a voltage divider consisting of a resistor 166 connected to a 5 volt voltage supply and capacitor 168 connected to ground which signal is applied to an inverting amplifier 164 to generate a signal representative of absence of global reset GRESET. Normally GRESET is generated out of the amplifier, however, and when the reset switch is applied, that signal is also generated. In the absence of a reset signal, the time slice vector generator, consisting of the chips 170, 172, and 174, is operative. The back plane of the multi-master processor bus or global processor bus 40 consist of three groups of circuits on each side of the board. The circuits are represented by connections between terminal points on the drawing of Fig. 5 and represent one-third of the circuits on the integrated circuit side of the board. Using this "daisy chain" effect, in some cases the boards in one column, or row, are interconnected with those in the next row so as to give a sequential transfer effect. Board connectors are located in columns or rows, indicated by 176a, 176b, 176c, 176d, 176e, through 176n. Inputs to various boards include fixed and variable voltage sources with the resistors 178 to apply a predetermined potential to the input of the first panel which is transfered directly or in succession by the activity along the various cards. Theory of Operation The present multi-master-processor bus system is based on the MC 68,000 micro-processor that has a typical bus cycle time of 500 nsec. The system timing controller divides the 500 nsec period into eight 62.5 nsec periods, one for each processor module. The time slice vector is generated by dividing a 16 MHZ clock with a three bit counter. Therefore, the counter will produce a three bit value which ranges from 0g to 7g- Each state of the counter has a period of 62.5 nsec. This cycle is repeated every 500 nsec. Each processor module will have a 3 bit switch that is continuously compared to the time slice vector. When a match occurs, the given processor module is allowed access onto the system but if it desires. This 3 bit encoder can be read by the processor and is used to allow the embedded software within the module to know if it is a master master or just a master processor. The master master would assume system responsibilities such as initialization until it decided to give up its responsibilities to another master processor. It is assumed that the other master processors will initialize their own subsystems and then quietly wait for instructions from the master master. A processor module that wants to write data into a GRM will wait until its time slice occurs; at which time, the processor will put Address and Data onto the Bus. The GRM's will compare the Address to their own and if the selected GRM is not busy, the GEM will latch the address and data from the bus and begin to process the request. If the GRM is already busy, the processor must wait until its next time slice before it can reissue its request. If a processor module wants to read data from a GRM, it puts the address onto the bus. If the GEM is not busy, the GEM will latch the Address and the current time slice vector. THE GRM will then process the request. When it has valid data ready, it will wait for the current time slice vector to equal the stored value- At that' time, the GRM will put the data onto the bus and assert the Data Ready line. The processor then latches the data and proceeds with its work. -If the GRM has been busy during the initial request, the processor will wait until it is granted access to the Bus. O - • There is no DMA on this Bus. A DMA device would be considered as a master processor and would have its own time slice. All global interrupts will be "or-tied" together as a common Interrupt Request line. This signal is then daisy-chained through all of the processor modules. Each processor may either accept or reject the request. If it accepts the request, the signal is not propagated through the chain; otherwise, the request continues through the chain. Upon accepting the request, the processor will generate an Interrupt Acknowledge that is "or-tied" with the IACK signals from the other processors. This combined signal is then daisy-chained through the interrupt requestors. The earliest requestor in the chain that has requested an interrupt will accept the IACK and the IACK is inhibited from proceeding throught he daisy-chain. During the following Bus Cycle, the accepting processor will generate a Vector Request signal during its time slice. The requesting module will then present a 16 bit vector onto the Bus and assert the data ready signal. The processor will then latch the vector from the bus. When a requesting module makes an Interrupt Request,' the module will consider itself busy and will not accept any other request until its interrupt is accepted and completed. Figs. 6, 7, and 8 are intended to illustrate global system operational sequences. Fig. 6 illustrates a write sequence which embodies the following steps: 1. A master processor module MPM internally generates a global request. (START); 2. MPM waits until its time slice occurs; 3. MPM asserts Address, Data and Control onto global bus; 4. If a Busy signal is asserted, go to line §2; -^ s Z^EA { G..-PI 5. (END ) Fig. 7 similarly represents a read sequence as follows: 1. A MPM internally generates a global request (START); 2. MPM waits until its time slice occurs; 3. Assert Address and Control onto global bus; 4. If a Busy signal is asserted, go to line #2; 5. MPM waits until its next time slice to occur; 6. If no Data Ready signal is asserted, go to line #5; 7. MPM captures Data from Global bus; 8. (END). Fig- 8 represents an interrupt sequence as follows: 1. A system module (master or resource) generates an interrupt request signal (START); 2. A MPM responds with an interrupt acknowledge signals; 3. The responding MPM then waits until its next time slice occurs. It them asserts the Interrupt vector request signal and negates the Data Stroble (DS) signal; 4. The requesting module places the interrupt Vector onto the data bus and asserts the Data Ready signal; 5. The MPM latches the vector from the global bus and negates the Interrupt Acknowledge and vector request signals; 6. (END). The systems shown in the schematic drawings are intended to be representative only. It will be clear to those skilled in the art that many variations on those shown may be employed. All such variations are intended to be within the scope and spirit of the present invention. OIΓ

Claims: AMENDED CLAIMS (received by the International Bureau on 23 December 1982 (23.12.82)) (new) !• A synchronous dat processing system comprising: a plurality of N processor modules, each processor module including a processor and interface circuitry; a global bus system connected in parallel to the interface circuitry of each of the processor modules and resource modules for providing communication among the processor modules and between the. processor modules and the resource modules; and system timing means for dividing a predetermined bus cycle time period into N equal time slices, each processor module being granted access to the global bus for a single time slice during each bus cycle time period. (new) 2. The data processing system as recited in claim 1 wherein the processor modules are each assigned a module number running sequentially from 0 to N — 1, and the time slices are each assigned a number, the numbers being assigned running sequentially from 0 to N — 1, each processor module being granted access to the global bus during the numbered time slice which corresponds to its module number. (new) 3. The data processing system as recited in claim 2 wherein: the system timing means includes a counter for generating consecutive repeating count signals from 0 to N - 1, the counter outputting the count signals onto the global bus system; and decoder circuitry within the interface circuity of each processor module for receiving the count signals and for granting access to the global bus system when a count signal corresponds to the module number of the particular processor. (new) 4 β j-e data processing system as recited in claim 2 wherein the predetermined bus cycle time period is 500 nanoseconds. (new) 5. The data processing system as recited in claims 1 or 4 wherein the global bus system comprises a time slice and clock bus, a data bus and address bus, each of said buses including a plurality of lines. (new) 6 * Th data processing system as recited in claim 2 wherein the processor modules are all of the same structure and wherein the module numbers are assigned in a completely arbitrary manner. (new) 7. The data processing system as recited in claim 1 wherein each processor module is fully self-sufficient and capable of asynchronous operation itself without regard to the global bus. (new) S. A method of operating a synchronous data processing system having a plurality of N processor modules, each of the processor modules being connected through interface circuity to a global bus system the method comprising: dividing a predetermined bus cycle time period into N equal time slices; and granting each processor module access to the global bus during a single time slice during each bus cycle time period. (n«w) 9. The method as recited in claim 6 further including the steps of: assigning a sequential number from 0 to N - 1 to each time slice; assigning a sequential module number from 0 to N - 1 to the processor modules; and granting each processor module access to the global bus when the number of the time slice corresponds with its module number. OMPI fαew) 10. The method as recited in claim 7 further including the steps of: generating count signals corresponding to the time slice number; outputting the count signals onto the global bus; and comparing the count signals to the module numbers.

Inventors: KRIS BRYAN
Applicants: KRIS BRYAN, TEXTRON INC
Application year: 1981
Main classification: G06F15
IPC codes: G06F13