PSEUDO-MICROPROGRAMMING IN MICROPROCESSOR WITH COMPRESSED CONTROL ROM AND WITH STRIP LAYOUT OF BUSSES, ALU AND REGISTERS

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/­ data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The ALU, registers and busses along with the control ROM are constructed in an interrelated layout whereby minimum space is needed on the chip. Like bits in all registers and the ALU are aligned and in a regular pattern. The busses are metal lines overlying each of the strips of ALU/register bits. Controls are polysilicon lines perpendicular to the busses and aligned with columns of the control ROM. The control ROM is an array of rows and columns of potential MOS transistors, compressed by eliminating column lines which contain no tran­ sistors. The number of bits per column is a minimum to enhance compressability producing a wide configuration (long row lines) which allows the columns for control signals to align with the part of the ALU/register strip where the signal is to be used. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instruc­ tions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-­ chip memory does not effect the off-chip main memory map. Micro­ processors are thus made more versatile and can be customized with little design effort. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions.

Description: BACKGROUND OF THE INVENTION This invention relates to a microprocessor as described in the pre-characterizing part of claim 1. A microprocessor of this type is disclosed in US-A-4,074,351, which shows a single chip "microcomputer" type device, which contains a 4-bit parallel ALU and its control and circuitry with ROM and RAM for program and data storage. Further, it relates to a method of making a logic array of rows and columns of potential cells for generating a plurality of control signals for a microprocessor. A microprocessor device is a central processing unit or CPU for a digital processor which is contained in a single semiconductor integrated circuit, usually fabricated by "MOS/LSI" technology as shown in US-A 3,757,306. This patent shows an 8-bit CPU on a chip including a parallel ALU, a register stack, an instruction register and a control decoder, all interconnected using a bidirectional parallel bus. The term microprocessor usually refers to a device which employs external memory for program and data storage, while the term microcomputer refers to such a device which has on-chip ROM and RAM for program and data storage; the terms are also used interchangeably, however. Subsequent to the time US-A-3,757,306 and US-A-4,074,351 were originally filed many improvements have been made in microprocessors and microcomputers to multiply the speed and capabilities of these devices and reduce the cost of manufacture. Generally, the trend in the semiconductor industry is toward providing more circuitry in less space, i.e., smaller chip size. As photolithographic techniques are improved the line widths and resolutions are improved, providing added density, but circuit and system improvements also contribute to the goals of increased performance with smaller chip size. Some of these improvements in microprocessors are disclosed in the following US Patents,: 3,991,305, 4,156,927, 3,934,233, 3,921,142, 3,900,722, 3,932,846, 3,939,335, 4,125,901, 4,158,432, 3,757,308, and 3,984,816. The demand for additional capabilities in microprocessor devices at lower cost continues, however, in spite of the advances which have been made in these technologies in recent years. Of course, not only the parts cost is of concern; the major concern is in lowering the cost of software and the amount of memory needed to store the programs, as well as the execution time for complex programs. Examples of some of the various microprocessor and microcomputer devices in this evolution of the technology are described in publications as well as the above-mentioned patents. In Electronics, September 25, 1972, p. 31-32, a 4-bit P-channel MOS microcomputer with on-chip ROM and RAM is shown which is similar to Patent 3,991,305. Two of the most widely used 8-bit microprocessors like that of US-A-3,757,306 are described in Electronics, April 18, 1974 at pp. 88-95 (the Motorola 6800) and pp. 95-100 (the Intel 8080). A microcomputer version of the 6800 is described in Electronics, February 2, 1978 at pp. 95-103. Likewise, a single-chip microcomputer version of the 8080 is shown in Electronics, November 25, 1976 at pp. 99-105 and a 16-bit microprocessor evolving from the 8080 is described in Electronics, February 16, 1978, pp. 99-104. Another single-chip microcomputer, the Mostek 3872, is shown in Electronics, May 11, 1978, at pp. 105,-110. A microprocessor which is particularly adapted for digital processing of real-time analog signals, the Intel 2920, is shown at Electronics, March 1, 1979, pp. 105-110. An improved version of the 6800 is disclosed in Electronics, September 17, 1979 at pp. 122-125, while a 16-bit microprocessor identified as the 68000 which evolved from the 6800 is described in Electronic Design, September 1, 1978 at pp. 100-107. Floating point arithmetic is performed in a 16-bit processor called the 8087, used as a co-processor with the 8086, as described in Electronics, May 8, 1980, pp. 114-121. EP-A-0 001 164 discloses a read-only-memory as separate entity. Although this document generally discloses a decoder and a ROM as possibly employed in a microprocessor, it does not specifically relate the described ROM to a microprocessor environment. This document further describes the elimination of conductors of either the row or column set of the ROM, where a number of stored words may end in a string of binary "1's", for example, since no short-circuit element would be required at cross points between the row and column lines, thereby enabling the corresponding word line to be shortened. However, there is no suggestion in this document of assigning the plurality of column lines into a plurality of separate groups, wherein one group is provided for each of the control lines. The publication "Programmable Logic and Microprocessors"-Tonge et al, Post Office Electric Engineering, J, Vol. 70, No. 3, October 1977, pages 136-144, London, GB, relates to the problem of reducing the area on a chip occupied by a logic array, but it fails to suggest the specific structure of assigning a plurality of column lines into a plurality of separate groups, wherein one group is provided for each of the control lines. It is the principal object of the invention to provide an improved microprocessor device. Another object is to provide improved performance or capabilities of a microprocessor or microcomputer while at the same time reducing the size (and thus cost) of the semiconductor device needed to implement the desired features. Further objects are to provide: an improved high density layout for a single chip processor along with the associated controls for these elements whereby microprogramming is facilitated; a combined and interrelated design for both a wide-word or compressed control ROM for a single-chip microprocessor. A further object is to reduce the area on the chip occupied by the control ROM as well as other instruction decode and microcode generator circuitry. SUMMARY OF THE INVENTION: The above objects are achieved by a microprocessor having the features defined in claim 1. This microprocessor contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The ALU, registers and busses along with the control ROM are constructed in an interrelated layout whereby minimum space is needed on the chip. Like bits in all registers and the ALU are aligned and in a regular pattern. The busses are metal lines overlying each of the strips of ALU/register bits. Controls are polysilicon lines perpendicular to the busses and aligned with columns of the control ROM. The control ROM is an array of rows and columns of potential MOS transistors, compressed by eliminating column lines which contain no transistors. The number of bits per column is a minimum to enhance compressability producing a wide configuration (long row lines) which allows the columns for control signals to align with the part of the ALU/register strip where the signal is to be used. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions. Although shown combined, the features may be used independently. BRIEF DESCRIPTION OF THE DRAWINGS The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein: FIGURE 1 is an electrical diagram in block form of a microprocessor system which may employ features of the invention; FIGURE 2a is a diagram of the word, byte and bit definitions of the 16-bit data word used in the system of Figure 1; FIGURE 2b is a memory map for the main memory 2 of Figure 1 and a diagram of a number of adjacent memory locations in the general memory area referred to as a "workspace"; FIGURE 2c (multiple sheets) is a mpa and list of the opcodes for the instructions executed by the microprocessor in the system of Figure 1; FIGURE 2d is a timing diagram showing voltage vs. time for the system of Figure 1; FIGURE 2e (four sheets) is a logic flow chart of the execution of instructions and handling of interrupts of the microprocessor device of Figure 1; FIGURE 3 is an electrical diagram in block form of a MOS/LSI microprocessor chip including a CPU or central processor unit employed in the microprocessor system of Figure 1 and utilizing features of the invention; FIGURE 4 is a greatly enlarged plan view of the semiconductor chip containing the microprocessor of Figure 3 showing the physical layout of the various parts of the device; FIGURE 4a is an enlarged detail view of a part of the layout of Figure 4 showing the register strip; FIGURE 5a-5g are electrical schematic diagrams of various parts of the ALU and register strip within the microprocessor of Figures 3 and 4; FIGURE 6 is a detailed electrical schematic diagram of a compressed control ROM used in the microprocessor of Figures 3 and 4. FIGURE 6a is a detailed electrical schematic diagram of a Y decode for the compressed control ROM of Figure 6 according to another embodiment; FIGURE 6b is an expanded version of a part of the control ROM of Figure 6 showing the compression feature; FIGURE 7 is a timing diagram showing conditions in the system of Figures 1 and 3 for an add operation; FIGURE 7a is a diagram of a sixteen bit instruction word for the add operation of Figure 7; DETAILED DESCRIPTION OF SPECIFIC EMBODIMENT: Microprocessor System The microprocessor device to be described herein may be of various configurations; in one embodiment the microprocessor device may be used in a system shown in generalized form in Figure 1. The system may be, for example, a single-board general purpose microcomputer, a word processing system, a computer terminal with display and typewriter keyboard, a communications switching or processing system, or any of many applications of this type. The system includes a single-chip MOS/LSI central processing unit or microprocessor 1 which will be described in detail, along with a memory 2 and input/output or I/O device 3. The microprocessor, memory and I/O communicate with one another by a 16-bit, parallel, bidirectional, multiplexed address/data bus 4, along with control lines 5. Suitable supply voltage and clock terminals are included; for example the device may employ a single +5V Vcc supply and ground or Vss, and a crystal may be connected to terminals of the device 1 to control the frequency of an on-chip oscillator which will then define the system timing. It is understood that concepts of the invention may be used in a single-chip microcomputer with on-chip memory instead of the off-chip memory 2, as well as in a microprocessor having separate address and data busses instead of the bidirectional bus 4. In general terms of course, the system of Figure 1 functions in traditional manner. The microprocessor 1 fetches an instruction by sending out an address on the bus 4 to the memory 2 then receiving the instruction via the bus 4 from the addressed location in the memory 2. The microprocessor then executes this instruction, which usually requires several machine cycles (as defined by a clock or crystal) including sending out via bus 4 addresses for the operands stored in the memory 2, and receiving this data back on bus 4, as well as writing a result into memory 2 by an address followed by data on the bus 4. The I/O devices 3 may be addressed like memory 2; this interface to external devices is accomplished using the address/data bus 4 and control lines 5 since the I/O devices 3 occupy locations in the memory address space. This is known as memory-mapped I/O. In the example to be described in detail, a 15-bit address is applied to the bus 4 from the microprocessor 1 (the 16th bit is a hardwired 0 for addressing), which will directly address 2¹⁵ or 32K words of memory. Each 16-bit word in memory includes two 8-bit bytes, so the microprocessor can address 64K bytes. The instruction set of the microprocessor 1 allows either word or byte operations. Figure 2a shows the data word and byte formats and bit definitions for the system of Figure 1 as described herein. Words are assigned even numbered addresses in memory 2. A 16-bit byte address is explicitly manipulated by all addressing modes, internally, but only the 15-bit word address is provided to the memory system 2 via bus 4, providing direct addressing of a 32K word memory space. The CPU device 1 supports several methods of increasing the amount of physical memory space which it can address, including paging, functional separation and mapping. Paging is accomplished by using a status bit on one of the control lines 5 and a 16th address bit. Functional separation is accomplished using "bus status codes" on BST lines 6 to enable separate memory spaces for instructions or data. Mapping is accomplished by using external map logic devices which are managed by mapping instructions; this may extend the physical address range to 16M bytes or 2²⁴, meaning the equivalent of a 24-bit address. The system of Figure 1 employs a memory-to-memory architecture in which the register files or working registers used by the CPU reside in the external memory 2 rather than in the microprocessor chip 1. This type of architecture allows faster response to interrupts and increased programming flexibility, compared to the traditional method of having most operands and return addresses stored in registers on the chip 1. The bulk of memory 2, particularly addresses 0080 to FFFA (all addresses are given in hexidecimal or base-16 in this description), is available for program storage or for "workspaces" as seen in Figure 2b. The first word of a workspace is addressed by a workspace pointer (always an even address) and the remaining fifteen words are addressed by the workspace pointer plus 02 up to 1E ( a 4-bit binary address). By maintaining the working register in memory 2, a context switch or interrupt can be executed with a minimum of data transfer between microprocessor 1 and memory 2 because most of the data to be saved is already in the memory 2. In addition to the parallel I/O 3, the system includes a bit-addressable input-output capability using a communications register unit or "CRU" 7 which employs one of the terminals (bit-0) of the address/data bus 4 as an input and another (bit-15) as an output, along with the lines 5 as control. Interrupts are provided by four input lines 8 which define sixteen interrupt codes, sampled by the CPU 1 when an interrupt request line (one of three interrupt controls among the lines 9) is active and compared internally with an interrupt mask. If the code on the lines 8 is equal to or higher in priority than the mask, the interrupt sequence is initiated. If the comparison fails, the processor ignores the request. Another one of the control lines 9 produces a non-maskable interrupt, wherein priority codes on lines 8 are not material. The system permits direct memory access (DMA) in which large blocks of memory words may be transferred via bus 4 between memory 2 and an I/O device 3 such as a disc memory. A "hold" command on one of the control lines 5 indicates to the processor 1 that an external controller desires to use the bus 4, so the processor enters a hold state with its terminals going to the bus 4 in a high impedence state. A definition of the function of each of the control lines 5, bus status lines 6 and interrupt controls is given in Table A. The status bits for a sixteen bit status register ST are shown in Table B where the conditions for setting each bit for instructions in the instruction set are defined. A definition of the interrupt levels is given in Table C. Of course, this specific system is merely illustrative of contemporary microprocessor or microcomputer systems in which features of the invention may be used. The CPU chip 1 of Figure 1 executes the instructions set of Fig. 2c, although it is understood that other instructions could be defined for execution in addition to or in place of the particular ones described. The instruction set of Fig. 2c is principally the same as that of a microprocessor sold by Texas Instruments under the part number TMS9900 and described in a book entitled 9900 Family Systems Design", published in 1978 by Texas Instruments Incorporated, P.O. Box 1443, M/S 6404, Houston, Texas 77001, Library of Congress Catalog No. 78-058005; such book is incorporated herein by reference. The instructions of Fig. 2c which were not executed by the TMS 9900 are: Signed Multiply and Division; long word add, subtract, shift left and shift right; Branch Indirect; Branch & Push Link; long distance; Load Status and Load Workspace Pointer; Load Map File; and multiprocessor support instructions Test, Test & Clear, and Test & Set. The source and destination addressing modes available in executing this instruction set are set forth below. Generally, the two-bit T fields Td and Ts (bits 4-5 and 10-11) define the addressing modes in instructions such as Add, Subtract, Move, Compare and the like. The 16-bit opcodes for the instructions are shown in Figure 2c which occupies three sheets. Figure 2c is arranged in descending order to show the groups(based on the left-most or most-significant "1") which are used in the entry point generator circuitry. THE CPU CHIP The processor architecture within the CPU chip 1 is shown in block diagram form in Figure 3, in chip layout form in Figure 4, and in logic diagram form in Figures 5 and 6. Generally, the processor includes an ALU or arithmetic logic unit 10 along with its associated registors, controls, data paths and related logic circuitry. This ALU is adapted for use in the system of Figure 1, but features of this CPU architecture may be used in other similar systems. The ALU 10 consists of sixteen parallel binary adder/logic states which function as the computational component of the processor. The ALU 10 receives a 16-bit "A" input 10A and a 16-bit "B" input 10B to produce a 16-bit parallel output 10C. The A input 10A of the ALU is from a 16-bit parallel A bus. The data on the A bus is active low; the indicators A , A-, or NA should be used in referring to this bus to be technically accurate, and the same is true of the other busses. The A bus may receive data from any one of several sources as will be described, with selection of inputs being made by control inputs 11. Similarly, the B input 10B is from a 16-bit parallel B bus which may receive data from any one of several sources as defined by control inputs 11. The output 10C from the ALU 10 goes to either a P bus or an E bus under control on inputs 11. The ALU performs all the arithmetic and logic functions required to execute microinstructions in the processor such as the functions of addition, subtraction, AND, OR, exclusive OR, complement, etc. as needed for the instructions of Figure 2c. The processor has a number of registers associated with the ALU 10, only three of which are accessable to the programmer. These three are a program counter or PC register, a workspace pointer or WP register, and a status register ST. Other internal registers which are used during the acquisition or execution of instructions are inaccessable to the programmer. The program counter PC is a 15-bit counter that contains the word address of the next instruction following the instruction currently executing. The fifteen stages are left-justified with the 16th bit hardwired to 0; instructions in the memory 2 are constrained to word boundries, so a single byte is not accessed, only even addresses (words) can be used. The microprocessor references this address to fetch the next instruction from memory 2 and the program counter PC increments the address when the new instruction is executing. If the current instruction in the microprocessor 1 alters the contents of the program counter PC, then a program branch occures to the location in memory 2 specified by the altered contents of the program counter. All context switching operations, such as interrupts, plus simple branch and jump instructions, affect the contents of the program counter. The program counter can be loaded from the E bus by lines EPC, or its contents applied to the B bus via lines PCB or alternatively to the P bus via lines PCP. All such transfers to or from the program counter are defined by control inputs 11, or course. Internally, the program counter PC includes binary add circuitry to add-1 to the count contained in the 15-bit register at the proper time, again under control of an input 11. The status register ST is a 16-bit register that contains the results of program comparisons, indicates program status conditions, and supplies interrupt mask level to the interrupt priority circuits. Each of the sixteen bit positions in the status register signifies a particular function or condition that exists in the microprocessor 1; these bit position assignments are shown in Table B. Some instructions use the status register ST to check for a prerequisite condition; others affect the values of the bits in the register; and others load the entire status register with a new set of parameters. Interrupts also modify the status register. Each instruction may have an effect on the status register. All sixteen bits of the status register ST may be loaded from the E bus via lines EST or loaded onto the E bus via lines STE, upon a command on the control lines 11. The processor 1 uses blocks of words in the memory 2, called workspaces, for instruction operand manipulation instead of internal hardware registers. A workspace occupies sixteen contiguous memory words as in Figure 2b, in any part of memory 2 that is not reserved for other use. The individual workspace registers may contain data or addresses, and function as operand registers, accumulators, address registers, or index registers. Some workspace registers are dedicated to take on special significance during execution of certain instructions. A large number of these 16-word workspaces may exist in the 32K words of memory 2, providing a high degree of program flexibility. To locate the workspace in memory 2, the hardware register WP or the workspace pointer is used. The workspace pointer WP is a 15-bit register (left justified with 16th or LSB hardwired to 0) that contains the memory address of the first word in the workspace of Figure 2b. The processor accesses any register in the workspace of Figure 2b by adding twice the register number to the contents of the workspace pointer and initiating a memory request for that word. The 16th bit is 0 so this is equivalent to adding two times the register number to WP. Figure 2b illustrates the relationship between the workspace pointer and its corresponding workspace in memory. The WP register is loaded onto the B bus via lines WPB, or loaded from the DI bus via lines DIWP, under command of the control lines 11. This workspace concept is particularly advantageous during operations that require a context switch, which is a change from one program to another, as in the case of a subroutine or an interrupt. Such an operation using a conventional multi-register arrangement requires that at least part of the contents of the register file be stored and reloaded, using a memory cycle to store or fetch each word. The processor 1 accomplishes this operation by changing the workspace pointer WP. A complete context switch requires only three storage cycles and three fetch cycles. exchanging the program counter PC, status register ST, and workspace pointer WP. After the switch, the workspace pointer WP contains the starting address of a new 16-word workspace (Figure 2b) in memory 2 for use in the new routine. A corresponding time savings occurs when the original context is restored. Instructions in the processor 1 that result in a context switch include: Branch and Load Workspace Pointer (BLWP), Return from Subroutine (RTWP), and an Extended Operation (XOP) instruction; device interrupts, the arithmetic overflow interrupt, illegal op-code detection trap, and others also cause a context switch by forcing the processor to trap to a service subroutine. The internal registers not accessable to the user (programmer) in the processor 1 include a memory address or MA register, a data or D register, and a K register. The D register, is connected as input to a swap bus S via parallel lines DS, and a swap bus output on lines SK may be applied to the K register, all under control of commands on the lines 11. The D register functions principally as a data output latch, and is loaded from the E bus via lines ED. The D register is applied to a DI bus by sixteen parallel lines DDI. The data path from the output 10C of the ALU to the E bus and thus to the D register via lines ED, then to the DI bus via lines DDI and to the A input of the ALU via the A bus is useful in divide routines, for example. Primarily, however, output data is loaded into the D register from the E bus, then to swap bus S via lines DS, and then to sixteen address/data buffers 12 via lines 13. Data can be transferred onto the swap bus S straight or swapped, depending upon factors like byte operations being performed; these transfers are of course under control of commands on lines 11. The address/data buffers 12 are sixteen bidirectional, tristate buffers of conventional form, each having an input/output terminal connected to one of the external bus lines 4. These buffers usually receive addresses from the P bus via lines 14, or data via lines 13, for output to the bus 4; for input to the microprocessor chip 1, program or data words are applied via lines 13 to the swap bus S, thence to the K register via lines SK. It is also possible to load the P bus from the K register via lines PK, under a command on a line 11, and thus output the K register via the P bus. The addresses to memory 2 are usually sent out from the microprocessor 1 via the P bus which is loaded by sixteen lines MAP from the MA register. The bits in this register can also be transferred to the B bus via parallel lines MAB, thus to the B input 10B of the ALU; alternatively the MA register may be loaded from the E bus via lines EMA or from the K latch via lines KMA, all as defined by control lines 11. Another internal register transparent to a user is the temporary or T register. This register receives a 16-bit parallel output 10F from the ALU 10, and applies its output to the B bus in three ways: either directly via lines TB, shifted left via path TLB or shifted right via path TRB. The T register can also receive the B input 10B to the ALU delayed by 3/4 of a clock cycle by a path BT. The T register provides an important function in multiply and divide operation as will be explained. A register also used in multiply and divide operations is referred to as the MQ shift register (for multiply/quotient). This register has the capability of right shift or left shift by commands on lines 11. The register may be loaded from the A bus or the DI bus by 16-bit parallel lines AMQ and DIMQ, or may be outputted to the E bus or the B bus via lines MQE or MQB. For bit or serial CRU operations involving the CRU 7, the "O" bit of the MQ register is loaded from the "O" A/D buffer 12 at a line CMQ; the output for this purpose is by way of the D register, in parallel, even though only one bit may be used. An instruction register IR provides the usual function of containing the current instruction, the instruction being executed during a given microcode state time (machine cycle). The instruction register IR is loaded from the DI bus via lines DIIR, or may be loaded into the E bus via lines IRE, under control of lines 11. Various fields of the instruction going to IR also can go to a A bus by 2-bit and 4-bit connections IR2 and IR4. During each cycle, however, the contents of the instruction register IR are transferred via sixteen parallel lines IR0-IR15 to entry point and microcontrol generator circuits as well as miscellaneous control circuitry. The control signs 11 are generated in a control ROM 15 which is in this case split into two halves, 15H for the high side and 15L for the low side of the ALU and registers. Since there are many controls 11 used on only part of the bits, high or low, rather than all sixteen, space is saved by splitting the control ROM 15 in this manner. Each half of the control ROM has an X array 15X and a Y-select array 15Y. Buffers 15B for each line 11 receive the select outputs from the Y array 15Y and introduce clock or other logic as may be needed to produce the controls in the lines 11. The number of microcontrol lines 11 is about 142, depending upon the instruction set to be implemented, well with in the addressing range (256) of an 8-bit address on lines 16 that go to both sides 15H and 15H. This 8-bit control ROM address is generated by entry point logic or by a microjump circuit. Microjump addresses, produced on eight lines 17 which receive output 11 from the control ROM, can generate a jump address for the next state. The microjump address on lines 17 is fed back to a logic array 18 that can also generate an entry point from inputs received from an execute entry point array 19E or a source/destination address entry point array 19A. A group detect circuit 20 receives the 16-bit instruction word from IR as well as status bits from ST and other controls and produces two inputs to the entry point arrays 19A and 19E, first a group identification and second a field. The group is determined by the left-most 1 of the opcode as seen in Figure 2c, and the field is three to four bits starting with the left-most 1. The address to the control ROM 15 on the lines 16 may also be held in an 8-bit latch 21 so the same state is re-executed as in multiply or divide instructions; to this end a 4-bit state counter SC is provided which counts state-time up to sixteen, and an overflow output of the state counter can control release of the holding latch 21. Thus, operation of the processor is controlled by instructions loaded into the IR register to generate an entry point via group detect 20 and logic arrays 18, 19A, 19E; the entry point is a starting address for the control ROM 15 entered on address lines 16. This address results in a specific set of commands on the control lines 11; some lines 11 will be active and most not. The address may also produce a jump address on lines 17 to define the control ROM address for the next state, or the next state may be another entry point, or may be the same state due to the holding hatch 21. When the last state needed for the instructions is reached, the next instruction is loaded into register IR and another entry point derived. As described below, the control ROM 15 is of the "compressed ROM" configuration, according to a feature of one embodiment of the invention. The control outputs 11 from the control ROM 15 also produce bus status codes for lines 6 by a generator circuit 22. The bus status codes of Table E are each generated in response to the specified conditions; an external device can be decoding BSTI-BST3 on the lines 6 and MEM- on one of the lines 5 determine exactly what activity is presently being implemented on the bus 4. The interrupt codes on the lines 8 and the controls 9 are applied to interrupt control circuitry 23 within the chip 1. Bits 12-15 from the status register ST are also applied to the circuitry 23 to provide the interrupt mask for comparison with an interrupt code from external. A logic flow chart defining how interrupts are handled by the processor 1 is shown in Figure 2e (four sheets). The external control lines 5 are connected to control generator circuitry 24 which responds to lines 11 from the control ROM as well as to other conditions within the chip, and to the lines 5, to produce the necessary internal controls and other external controls 5. An on-chip memory array 25 is included on the processor chip 1 to provide added functions not in the instruction set of Fig. 2c. This memory 25 contains a section 25A of ROM, for example 512 words, and a section 25B of RAM, for example sixteen words or one workspace. The ROM 25A resides at hex addresses 0800-OBFE and the RAM 25 B at hex addresses 0000-001E, but these are not within the memory map of Figure 2b; these locations are merely examples. A memory address decode circuit 25C receives a memory address on lines 25 D from the P bus and selects one word from the ROM or RAM 25A, 25B, which is input or output via data I/O circuit 25E to lines 13 on sixteen parallel lines 25F. An on-chip memory control 25G detects a specified opcode referred to as MID or macroinstruction detect (in this example either an illegal opcode or an XOP executed while bit-11 of stat register ST is set to one); the control 25G is activated to transfer execution to the on-chip memory 25. When entering this operation, a context switch saves the WP, PC and ST register contents in registers R13, R14 and R15 of the 16-word workspace in RAM 25B. The CPU then executes assembly language instructions(Fig. 2c) from the ROM 25A; during execution of these macroinstructions various microinstructions may access the external memory 2 in the usual manner using indirect antoincrement and indexed addressing modes. By providing this on-chip memory space 25 separate from the external user space (memory map of Figure 2b), new instructions can be emulated in a manner completely transparent to the programmer. These new instructions can be emulated in a manner completely transparent to the programmer. These new instructions are constructed using the Fig. 2c set plus special instructions; a customer for the processor chip 1 may specify certain added instructions to be implemented via on-chip memory 25, yet the customer can write the programs to be stored in ROM 25A to execute these instructions using the Fig. 2c instruction set. Detailed operation of the memory 25 is explained below. An important feature is that the ALU 10 and its associated registers K, D, MA, PC, WP, T, MQ, ST and IR as described above are laid out on an MOS/LSI chip in a regular strip pattern as seen in Figure 4a. Each of these registers as well as the ALU contains sixteen bits or stages which are laid out in a pattern like memory cells, the bits arranged horizontally in Figure 4 as seen; the A, B, DI, E and P busses of Figure 3 are each sixteen parallel metal strips on top of the cells of the ALU and registers (rather than beside the registers as depicted in Figure 3), and all of the dozens of control lines 11 are horizontal polysilicon lines as they are used as the control gates of four transistors in the ALU 10 and its registers. The number of control lines 11 needed for the ALU 10 is greater than for a single register such as the WP register, for example, and it is a fortunate circumstance that the space needed to lay out the ALU stages is greater than for a single register, so waste space is minimized. That is, the space needed in the control ROM 15 to generate the controls is the same as the space needed for the controlled circuitry. This layout arrangement is indeed advantagious when used with the compressed "wide-word" control ROM or decoder as will be described because it fits exactly alongside the control ROM with virtually none of the wasted space which would be used only for routing conductors in conventional construction of microprocessors. That is, all bus lines A, B, DI, E and P etc., and all control lines 11 are routed over or under functional regions or cells of the chip rather than over unused silicon, and almost all 90° turns are produced inherently at functional cells rather than in conductor routing. In the prior devices, the control ROM, the registers, the ALU, etc., were islands of circuitry connected by busses or conductors. The enlarged view of Figure 4a shows a small part of the ALU 10 and registers, illustrating the metal bus lines and the polysilicon control lines 11 for an N-channel silicon gate MOS device made generally according to U.S. Patent 4,055,444 assigned to Texas Instruments. It is significant to note that most of the connecting lines such as KDI, ED, EMA, MAB, DINP, etc. as mentioned above are not physically lines of elongated conductors at all but instead are merely metal-to-silicon contact areas along the metal bus lines of Figure 4a. That is, routing of 16-bit parallel conductors is minimized by the strip feature. THE ALU AND REGISTER CIRCUITS The detailed circuits employed in the ALU and its associated registers will be described with reference to Figures 5a-5g. These circuits fit together as seen in Figure 3. Generally, only one bit of the sixteen bits is shown in a strip. For the most part the remaining fifteen bits are the same as the one shown in detail, with some exceptions. THE ALU Referring to Figure 5e, one of the bits of the ALU 10 consists of a complex logic circuit having its A input 10A connected to the A bus and its B input 10B connected to the B bus while its output 10C is connected by transistors 10a and 10b to the E and P busses, respectively. The transistors 10a and 10b have connected to their gate control lines 11 labelled HD1ALTE and H1ALTP, respectively. Throughout this description, the convention used for labelling commands or control lines 11 is (a) clock phase such as H1 or "half 1", then (b) the source such as "AL" (for ALU), and (c) "T" or "F" for to or from, followed by (d) the destination such as "P" or "E" bus. The half and quarter clocks are shown in the timing diagram of Figure 2d. Using this convention, H1ALTP means this control 11 occurs during the H1 or half-1 clock and defines the connection from ALU to the P bus. An input to the A bus from the DI bus by line DIA and transistor 10C is controlled by an H1DITA command on a line 11, translating as "D1 to A, on H1 clock". Carry-in and carry-out for this bit are on lines Cout and Cin respectively, which are connected to adjacent stages of the ALU. The carry-out line is precharged to 1 or Vcc on Q1 by transistor 10d, then conditionally discharged after Q1 goes low by a transistor 10e. A NOR gate 10f drives the gate of the transistor 10e based upon a S1STOPG input on one of the control lines 11 (meaning stop generate, on S1), and the voltage on a node 10g. The output of gate 10f is the carry generate condition, and is made unconditionally 0 if STOPG is active. The node 10g, precharged to 1 on Q1, is connected to a node 10h by a transistor 10i which has the inverted A input on its gate. Similarly, in the carry propogate circuit a node 10j is precharged to 1 on Q1 and is connected by a transistor 10k (also receiving inverted A input) to a node 10m. The nodes 10h and 10n, precharged to 1 on Q1, are conditionally discharged by complex NAND/NOR logic circuit including transistors 10o driven by the B and B input (inverted and twice-inverted), along with transistors 10p driven by the four control lines 11 labelled H2ALU1 to H2ALU4. The four controls ALU1-ALU4 define the operation performed in the ALU as set forth in Table H. The "H3Logic" control on a line 11 is the arithmetic/logic control; when this line is high the ALU performs logic functions by unconditionally grounding the Cin line by transistors 10g, but when low Cin is applied to an input of an exclusive NOR circuit 20p, the other input being the inverted propagate signal from node 10j. The propagate signal also drives the gate of a transistor 10s in conventional manner. An important feature of the ALU 10 is the NOR gate 10f and its stop-generate control which allows the function of two's complement A to be produced with the same code as "pass A" but with H3logic = 0. This is produced by negative A and absolute value of A. A carry input to the LSB of the ALU 10 is produced by microcode controls 11. A CIFCO or "carry-in from carry-out" control applies the carry-out from the MSB of the prior state to the carry-in at the LSB for the current state. A STCIN control applies the status bit-3 to the carry-in. A CIN control produces an unconditional carry in to the LSB. The Workspace Pointer Register A detailed circuit diagram of the workspace pointer register WP is shown in the lower part of Figure 5c. This register includes two static invertor stages WPa with an input node WPb connected to the output during H2. The input node can be loaded from the DI bus by a transistor WPc having an H4WPFDI (WP from DI, on H4)command on its gate. An intermediate node WPd is connected to the B bus via an inverter WPe and a transistor WPf which has a command H1WPTB (WP to B on H1) on its gate. Fifteen bits are exactly the same, and bit sixteen is a hardwired 0 or Vss. The workspace pointer register WP is used as the B input to the ALU 10 when generating the source and destination addresses for typical instructions of Fig. 2c. In a context switch, WP is saved by writing into memory 2, and the path for this operation is the B input of the ALU 10 and the P bus. WP is loaded from off-chip by the DI bus. The Program Counter and Incrementer Also seen in Figure 5c, the program counter PC consists of a pair of static inverters PCa having an output node PCb connected to an input node PCc on Q2 by a transistor PCd. The input node PCc may be loaded from the vertical E bus by a transistor PCe having H4PCFE (PC from E, on H4) on its gate; this signal is on one of the control lines 11 running horizontally through the register matrix. The output of the program counter at an intermediate node PCf is connected to the gate of a transistor PCg, from which the program counter contents may be read out onto the vertical P or B busses by transistors PCh or PCi and lines PCP or PCB. The signals to control these transfers are H1PCTP (PC to P, on H1) and H1PCTB (PC to B, on H1) on separate horizontal control lines 11. The program counter is incremented when an H3PCINC signal appears on one of the control lines 11, turning on a transistor PCj; on H1 a transistor PCk turns on, loading the contents of this bit of the program counter onto the gate of a transistor PCm in series with a carry line PCn from the prior bit. Each bit of the carry path is precharged to 1 on Q1 by a transistor PCp. The carry-in for each bit on line PCn is connected by a NOR gate to the gate of transistor PCq; the NOR gate also has the H4PCFE signal as one input. This circuit causes a carry to be propogated if the bit is 1 and carry-in is 1; or causes the bit to go from 0 to 1 if the carry-in is 1. The LSB stage is a hardwired 0 because only the 15-bit word address is sent out on the bus 4; the 16th bit is the byte address which is not used for access. For byte operation using the odd numbered byte, the next lower even number is the address then the byte swap circuitry S is activated. Thus, the 16th bit of the address is always 0. All the other fifteen bits are identical to that shown in Figure 5c. The carry-out from the last bit is truncated as it would represent address FFFF ( in hex). The Memory Address Register: One bit of the MA register is seen in detail in the upper part of Figure 5c. This register includes a pair of standard inverters MAa and MAb in each of the sixteen bits with feedback by a transistor MAc clocked on H2. The register is loaded from the E bus via sixteen separate lines EMA and a transistor MAd in each line. The gates of the sixteen transistors MAd are driven by a signal H4MAFE (MA from E, on H4) on one of the horizontal control lines 11. Likewise, each MA register bit is loaded from the K latch by a line KMA and a transistor MAe which has H4MAFK on its gate. Output from the MA register is taken at an intermediate node between the two inverters which is connected by a transistor MAf to two output transistors MAg and MAh. An H1MATP command on one of the control lines 11 turns on the transistor MAg and connects the output to the P bus via line MAP. In H1MATB command turns on the transistor MAh and connects the output to the B bus via the line MAB. Of course, it is understood that there are sixteen of each of the input and output lines to or from the busses, as is true for the other registers. The MA register is usually loaded via P bus to the A/D buffers 12 as a basic part of most instruction sequences. It is usually loaded from the ALU output 10C via the E bus when an address is generated by adding WP + 2S, for example, which is usually done for most instructions. The Data Register : The D register or data register contains sixteen bits constructed as shown in detail in Figure 5b. This register stage consists of a pair of inverters Da and Db with a feedback path via transistor Dc clocked on H2. The input of this register is from the E bus via transistor Dd and a line ED (one of sixteen lines ED), with the transistor Dd being controlled by an H4DFE (D from E) command on one of the lines 11. One of the outputs is from an intermediate node De and a transistor Df which connects to the DI bus by a transistor Dg and one of the sixteen lines DDI. This output is controlled by an H1DTDI (D to DI) command on a control line 11 which is connected to the gates of all sixteen of the transistors Dg. The other output from the D register is by sixteen lines DS, each going to the gate of a transistor Sa in the swap circuit S. The output of this transistor inverter is connected to the swap bus Sb by a transistor Sc having a "straight" command on its gate or a transistor Sd having a "swap" command on its gate. The line 11 connected to the gates of each of the sixteen transistors Sc carries the H2DTSS (D to swap-straight) command, while the line 11 carrying the H2DTSW (D to swap-swapped) is connected to the gates of the transistors Sd. E bus connects to Vcc via Dh and Dd. The D register most often functions to receive the data output from the ALU10 via the E bus. Also, it functions as the source of an ALU operand input to the A side via the DI bus and the A bus. The D register is used mainly for data output, and also in ready and hold conditions and in divide operations, for example. The K latch : The K register of K latch contains sixteen identical stages, one of which is shown in Figure 5b. The K register uses two standard inverters Ka and Kb with feedback on H1 by a transistor Kc. The output is connected to the gate of an inverter transistor Ke which is connected to output transistors Kf and Kg. A command Q1KTP (K to P) on one of the lines 11 turns on the transistor Kf and connects the output of the K register to the P bus via line KP. A command Q1KTDI (K to DI) turns on each of the sixteen transistors Kg and connects the output to the DI bus by sixteen lines KDI. The K register is loaded from the swap bus S in either straight or swapped condition by transistors Ki and Kj. A command H3KFSS on one of the control lines 11 connects the swap bus to the input of the K register via sixteen transistors Ki while a command HeKFSW connects the swap bus to the input of K via sixteen transistors Kj for swap or byte operations. The Sap Circuit: The swap circuit S shown in Figure 5a functions to connect the 16-bit D register to, or the K register from, the A/D buffers 12 via lines 13, either stright or with the high and low bytes swapped. Addresses are usually transferred in or out via the P bus that is connected to the A/D buffers without going through the swap bus, since addresses need not be swapped in byte operations, only data. Thus, data comes in via the K register and goes out via the D register, both using the swap bus S. The Temporary Register: In Figure 5d one stage of the sixteen stages of the T register or temporary register is seen in detail. This register consists of two standard inverter stages Ta and Tb with feedback on H2 via transistor Tc. Output from the T register is from a node Td at the output of the inverters, via an inverting transistor Te to a node Tf precharged to Vcc on Q3 via transistor Tg. A H1NLDI command on one of the lines 11 controls a transistor Th in series with transistor Te. Output from the node Tf directly to the B bus is by a line TB and a transistor Ti controlled by a H1TTB (T to B) command on a horizontal line 11. To shift left, the node Tf is connected by a transistor Tj to the B bus in the next more significant bit, to the left, via line TLB. To shift right, the node Tf is connected by a transistor Tk to the B bus in the next lower significant bit, to the right, via line TRB. The transistors Tj and Tk are controlled by commands H1TSLB and H1TSRB on two of the horizontal lines 11. The T register is loaded from the B bus by a line BT and a transistor Tm clocked on Q3 along with an inverter Tn and a transistor Tp which has H1TFB on its gate. This input is delayed by 3/4 of a clock cycle. The transistor Tp at the inverter output has its output to the input node Tq to load the T register. The transistor Tr at the inverter output and a transistor Ts with H1TFB on its gate goes to node Tf as a path for replacing the B bus information on the B bus after a delay. Thus, H1TFB followed by H1TTB is a quicker path than loading T register then reading it out onto the B bus in the next cycle. The "F" output from the ALU 10 is connected to the input Tq through a transistor Tt, and to the gate of a transistor Tu. The transistor Tu is in series with a transistor Tv, and both Tu and Tv are controlled by H1TFF. The output of the transistor Tv goes to the node Tf as an output from F to the B bus, which may be either straight, left-shifted, or right-shifted. This arrangement of the T register has great advantages in divide operations. The MQ Shift Register: The MQ register consists of sixteen bits, one of which is shown in Figure 5f. This register may be shifted left or right by controls 11 and so is used in multiply and divide instructions, in CRU operations, and the like. Also, the register can be used as a general purpose working register. To this end, an input node MQa may be loaded from the E bus via transistor MQb and line EMQ by control H4MQFE, or loaded from the DI bus via transistor MQc and line DIMO by control H1MQFDI. Feedback on Q3 is provided by a transistor MQd, and the output of the first stage is connected to the input of the second during H2 by a transistor MQe. The left shift function is provided by a transistor MQf connecting the input node MQa to a node MQg in the next less significant bit of the register, this occurring when a command HD4MQSL appears on one of the lines 11. The HD4 prefix for this control means that it occurs at H4 in the next state time, or delayed one clock cycle, from the time this microcode is generated in the control ROM 15. The right shift function is produced when an HD4MQSR control occur on a line 11 turning on a transistor MQh to connect the node MQa to the input node MQa of the next more significant bit of the register. For CRU I/O operations, the first and last bits of the sixteen bits in the MQ register are used as inputs and outputs via the DI bus or other busses coupling to the bus 4. The contents of the MQ register are applied to the E, P or B busses by a circuit consisting of an inverter MQi and inverter transistor MQj connecting input node MQa (twice inverted) to output node MQk. The output node MQk is connected by transistors MQm to the B, P and E busses when H1MWTB, H1MQTP or HD1MQTE commands occur. The output of MQn of the first inverter MQp is connected to the input of the second stage by a transistor MQq on H4MQFE, when MQb is activated. The Status Register: One bit of the sixteen bit status register ST is shown in Figure 5g. This stage consists of a pair of inverters STa and STb, with feedback on Q4 by a transistor STc. An input node STd may be loaded from the E bus through a transistor STe when a command H1STFE occurs. Several other input transistors STf may set or load the input node from other sources, such as other controls 11 from the control ROM 15, etc. The output of the status register is taken at an intermediate node STg by an inverting transistor STh with a transfer transistor STi going to the E bus, under control of and HD1STTE command on a line 11. Among the controls 11 from the CROM 15 are twelve control status signals CS1 to XS12 and two set status signals SS0 and SS2. These control various transistors STf to set or conditionally set the status bits according to the instruction set of Fig. 2c and the status bit definitions of Table B. The Instruction Register : The instruction register IR is a sixteen bit register, one bit of which is shown in Figure 5g, containing two inverter stages IRa and IRb with feed-back via transistor IRc and H2. The instruction register is loaded from the DI bus at input node IRd through transistor IRc on an H4IRLD command. Also, the instruction register may be cleared by a transistor IRf connecting the input node IRd to Vcc on an H1IRCLR command. True and complement outputs from the instruction register IR are taken at nodes IRg and IRh; these outputs go to the group detect 20 as the IRO-IR15 (and IRO - IR15 ) signals, and are of course used to generate entry point addresses, etc. Coming in, bits which define the addresses of registers in the workspace are fed directly to the A inputs of the ALU for source and destination address generation, under control of commands 11 before reaching IR. Certain ones of the IR outputs and ST outputs are used in a jump detect circuit 26 (Figure 3) to detect any of the jump instructions and/or conditions are defined by the instruction set of Fig. 2c. The bits received by the jump detect circuit are: ST0-ST3, ST5, STO - ST4 , IR4-IR7, and IR4 - IR7 . The group detect 20 received all fifteen IR bits and complements and determines which of the eleven groups G0 to G10 the instruction word falls in, as defined in Figure 2c. This is based on the position of the leading "1". Then, the four bit (or in some cases three bit or two bit) field defined also in Figure 2c is used to generate the entry point address in a PLA. THE COMPRESSED CONTROL ROM: The control signals on the lines 11 which defines the operation of the processor are generated in a control ROM 15 as seen in Figure 6. According to an important feature of this processor, the control ROM is compressed so that it uses much less space on the chip than prior control decoders. The control ROM 15 generates a set of microcontrol signals on the lines 11 for each individual address applied to the eight input address lines 16; the input is split into a four-bit X address on lines 16a and a four-bit Y address on the lines 16b. For each of the 256 possible address inputs, a unique combination of outputs could be produced, but in a typical embodiment less than 256 are required because an instruction set can be implemented with fewer than 256 states. In a processor which executes the instruction set of Table D, for example, 239 addresses or microcode states are used to selectively activate 142 controls 11 (including eight microjump addresses for lines 17). Figure 6 shows only eight of the control lines 11, as examples, these being for the MAFDI, MATB, PCINC, PCTB, WPTB, ALTP, CIFCO and DITA signals. The others are similarly coded, depending upon the instruction set. The control ROM 15 is split into an X-select portion 15x and a Y-select portion 15Y. The X-select portion contains sixteen X lines 15a and a variable number of Y lines 15b, depending upon the degree of compression, as will be explained. The X address on the lines 16a selects one-of-sixteen of the lines 15a using a standard decoder 15c. Where a circle 15d appears at the intersection of an X line 15a and a Y line 15b, a transistor is formed which connects the Y line 15b to ground through a source-to-drain path. The X lines 15a are poly lines forming the transistor gates. Note that all of the Y lines 15b are populated, i.e., all have circles or transistors 15d. This is in contrast to control ROMs in prior microprocessors where a large part of the ROM is unpopulated (or if the opposite polarity logic is used, is almost totally populated). The control ROM 15 of Figure 6 is compressed by eliminating all of the Y lines 15b which do not contain a transistor 15d. The Y select portion 15Y of the control ROM of Figure 6 includes sixteen lines 15e, only one of which is selected by a one-of-sixteen Y decoder 15f. The transistors 15g, in series with the lines 15b, cause the selection of one and only one of sixteen possible Y lines 15b in each group according which line 15e is high, determined by the binary code on the four lines 16b, all other Y lines 15b in each group are isolated from the control line 11 via transistors 15g. In place of the Y select of Figure 6, a Y select as seen in Figure 6a can be used; here eight lines 15e are used; only one Y line 15b is selected by a one-of-sixteen decode arrangement responsive to the four Y address bits from line 16b and their four complements A transistor 15h is formed in shunt with Y line 15b in each place a circle is shown. The Y select of Figure 6 used more lines 15e, but fewer transistors 15g than the transistors 15h of Figure 6a. In either case, the function of the Y select 15Y is to cause only one of the several Y lines 15b in each group to be controlling, as determined by Y address 16b. The embodiment of Figure 6a employs opposite logic for the X select 15x, compared to that of Figure 6; a logic form is used in Figure 6a wherein non-selected lines have a circle or transistor 15d, so the output from a line 15b to a control 11 includes an inverting NOR gate for each group, along with a clock and an inverting buffer 15i. In Figure 6, all lines 15b are connected together as a hardwired AND in the output to a line 11 in each group with only one inverter 15i. The compressed ROM of Figure 6 employs false logic in that the line 15b goes low when the control line 11 which it drives is supposed to go high, generally. Each line 15b has a precharge transistor 15p connected to it so that on each Q4 clock the lines 15b are precharged to Vcc. An invertor 15i produces a 1 on a line 11 when its corresponding Y line 15b is 0. On Q1 of each state time the lines 15a and 15e become valid, conditionally discharging one line 15b in each group and leaving all others at Vcc or 1. The selected line, inverted, becomes a positive control on a line 11 for each group. In some cases such as the ALU control for add, as explained, the output is again inverted to facilitate ROM compression. In Figure 6b two of the groups of Figure 6 are shown without the compression feature, these two groups being the lines 15b for producing the MAFDI and MATB commands. Each group potentially contains sixteen lines 15b and sixty-four transistors 15f. By eliminating the unused lines 15b in each group (shown dotted) where no transistors 15d are present, and eliminating the Y select transistors 15f of these lines, a large saving in space and complexity is produced. For the MAFDI group only four lines 15b are needed, saving twelve Y lines and forty-eight transistors 15f. The MATB group needs only nine Y lines, saving five lines 15b and twenty transistors 15f. Each of the remaining six groups of Figure 6 requires less than sixteen lines 15b as follows: PCINC has nine lines 15b; PCTB six; WPTB nine; ALTB twelve; CIFCO one; and DITA fifteen. For these eight control lines chosen as an example for Figure 6, the total saving is sixty-three of 128 possible Y lines 15b, and 252 transistors 15f of a possible 512, or 49%. Considered another way, if a fully implemented ROM was used the X select part 15X would contain 16 x 16 x 8 = 2,048 potential transistors. The compressed ROM of Figure 6 contains 16(4 + 9 + 9 + 6 + 9 + 12 + 1 + 15) or 16 x 65 = 1040 potential transistors 15d or cross points. Again, the saving is 49%. For an instruction set used for one embodiment, 142 lines 11 are needed so a fully implemented control ROM would contain 142 x 16 x 16 = 36,252 bits. By compression, this is reduced to less than 10,000, a saving of 72%. In control ROMs for microprocessors, most of the potential ROM bit locations are coded to contain no transistor. The most common action for a given control output 11 is to be off (logic 0). For a typical 16-bit microprocessor with 142 primary control signals 11, usually less than thirty (sometimes only a few) are active during any given state. There are many reasons for this fact. For example, while several registers (MA, PC, WP, T or MQ) may go to one input (B) of the ALU, only one can go to a single input at a time and therefore the control signals for the other possible paths are inactive. Also a number of special control signals may be used in only a few states. This fact was used in prior control decoders for microprocessors by employing secondary decoders; some control signals came from a main control ROM as secondary controls that were decoded in smaller ROMs or random logic to produce primary controls. Ordinarily the primary signals were encoded where only one of several was needed for a given state. In such a scheme, control ROM is saved at the expense of more random logic outside the control ROM; this makes microprogramming more difficult since the microcode is one level removed from the final control signals, and also slows down the device since time is required to go through the decode states. The compressed control ROM of Figure 6 basically uses unencoded control outputs 11. Some controls contain logic circuits in their paths but this is a minimum compared to prior approaches. Most of the control signals are clocked by H1, Q1, etc. in standard clocked gates so that the signals are valid only during a selected time period. The depth of the control ROM is selected to enhance compressability. Assuming a totally random distribution of control signal occurances, the chance of getting a column that can be eliminated is (by a derivation of hypergeometric probability) approximately Where #S = number of states, #P = number of occurances of the control signal, and #B/C = the number of potential bits per column i.e., the number of lines 15a in Figure 6. For example, assuming a control ROM with 256 states, with a control signal that occurs then times, and sixty-four X lines, i.e. columns with bits sixty-four deep, the probability of eliminating a column is 5%. Clearly the compression technique would not be practical with this chance of reduction. This is a primary reason this ROM compression has not been previously considered. However, several methods can be used to increase the chances of eliminating columns or Y lines. One method of increasing the likelihood of compression is to directly attack the probability equation above by reducing the number B/C, the bits per column. In the example in the previous paragraph, if the bits per column (the number of X lines) is reduced from sixty-four to sixteen the probability of reduction goes from 5% to 52%. This modification is contrary to established practice because ROMs in integrated circuits are made relatively square (same number of X and Y lines) since this tends to reduce the area of the associated control circuitry for the ROM. Assuming the same number of bits in a ROM, by reducing the number of bits per column (number of X lines) the number of columns (Y lines) is correspondingly increased. However, the compressed ROM approach according to Figure 6 offsets the increase by reducing the number of columns and thus the number of bits. More columns are created (by reducing the bits per column) so that columns can be eliminated. Even with elimination of unpopulated columns, the number of columns created by reducing the bits per column is not fully absorbed so that the control ROM tends to be wide in the direction of the ROM output lines (longer X lines 15a) while getting shorter in the length of column lines 15b. The increase in the number of column lines 15b increases the number of Y select transistors 15f and at some point this increase is not offset by the reduction in the ROM array 15X due to reducing the bits per column. For a given CPU with a specified register and ALU architecture and instruction set, therefore, there will be a peak point at which the reduction due to column length or number of X lines is at an optimum. Another type of compression is accomplished by changing the addresses of states. The probability equation above assumes a random accurance of signals. By moving the X and Y addresses around (principally by analysis) more "blank" columns can be created and thus eliminated. First, for this purpose it should be noted that the column reduction is done on the basis of bits 15d which have the same Y select (same Y address). Those states which have the same Y select are said to be in the same partition. In the example shown in Figure 6, sixteen possible X addresses 0 through F (in hex) have a Y address of 0 (but some are unused) and thus are in the same partition, i.e., there are sixteen states per partition. By rearranging the state addresses the number of bit columns 15b with all zeros (and thus columns that can be eliminated) is increased. For example, ignoring DITA, a Y address of "8" is used only twice in the example shown in Figure 6, and each time it contains only two transistors on the column lines in the X array 15X, so this is a candidate for consideration. By changing the Y address to "5" instead of "8", "5" is already implemented for those output groups, and moving the transistors to the "5" column, then two more lines and four Y select transistors would be eliminated. Of course, this example would not be possible in actuality because the X position on the Y=5 column is already occupied on some other control line groups not seen in Figure 6, as well as DITA. There are some practical problems with changing state addresses, the biggest of these problems being that of generating starting addresses of micro-routines. When the starting address or entry point is generated in random logic rather than by logic arrays or ROMs, it has been found best to let the starting addresses be fixed conveniently by the random logic and then work compression around these fixed addresses. The changing of state addresses (the 8-bit addresses on the lines 16) has a closed loop effect on the micro-code, since the jump fields 17 in the micro-word outputs 11 change to jump to the changed address. While the columns which produce the jump fields 17 can be reduced by changing addresses, it is a difficult problem to optimize for. This is particularly true if the Y addresses are changed because this affects other reductions. Thus, in attempting to reduce the jump fields 17 it is best to only change X addresses, thus not affecting other reductions. Another method of compressing the control ROM is by changing the polarity of control signals. By correctly choosing the default conditions of control signals, significant control ROM column reductions can be achieved. By default condition is meant the condition of a signal on a line 11 when a transistor 15d is not coded (i.e., not present). In the example of Figure 6, as thus far described, it has been assumed that the default condition has been in inactive output on a line 11 (output a logic 0) if no transistor 15d is present; however, this is not necessarily the best default for all cases. If a command on a line 11 is active in more states than inactive it may thus be advantageous to add an invertor in the buffer 15B and then code the inverse into the control 15X. The best example of how choosing optimum defaults can work to advantage is given by the controls 11 for the ALU 10. There are eight control signals 11 for the ALU, these being ALU1, ALU2, ALU3, ALU4, STPG (stop generate, preventing carry generate), H3Logic which is 1 for logic and 0 for arithmetic, CIFCO, and CIN which affects only the first bit. If coded conventionally, the ALU circuit of Figure 5d produces the ADD function with ALU1-ALU4 at 0110, STPG at 0, H3Logic at 0, CIFCO at 0, and CIN at 0. This is the most commonly used condition in a typical instruction set, so if the two 1's in the ALU1-ALU4 controls can be eliminated the possibility of compressing the control ROM 15 can be enhanced. Thus, inverters 10i are added series with the lines 11 for the ALU2 and ALU3 signals (seen in Figure 5d). Thus, ADD is a default condition coded with no transistors in the ROM 15X, allowing a maximum of compression. In this case it becomes preferable to code a PASS of either the A or B input in the ALU as an ADD plus zero rather than use the ALU function of PASS which is coded as 0011 for pass A or as 0101 for pass B (uninverted) with H3Logic=1. Much more compression is made possible by using ADD plus zero instead of PASS in coding the ALU operation because no transistors (all zero outputs) are required for the control ROM 15. In one embodiment, the inversion of the ALU2 and ALU3 results in use of the SLU1-ALU4 control columns 15b in only twenty-four out of a possible sixty-four times, i.e., the columns have transistors 15d and are thus present in twenty-four and are absent in forty cases for a particular instruction set. Use of the control ROM compression as described herein significantly alters the overall design approach used for a microprocessor chip, because control ROM becomes very inexpensive in terms of space utilized. For example, suppose one particular instruction needs a special control signal 11 during one state of execution. Previously this would require an instruction decode signal combined with a general purpose control ROM output signal that indicates when to use. With the compressed control ROM feature, only one column 15b is added and since the columns are short this represents a more compact and thus lower cost solution than if random logic were used. Therefore even special purpose signals may be best generated in the control ROM rather than in random logic with the compression feature minimizing the cost. The ability to relegate almost all the control signals to the control ROM simplifies designing the microprocessor 1, and the same time gives a small chip area (translating to lower chip cost). One of the additional advantages to using the compressed control ROM is that controls 11 are generated by the associated column lines 15b using so little space that the lines 15b can be duplicated if controls 11 are needed in two different areas of the chip of Figure 4, rather than by generating it once and routing conductors from one place to another on the chip. That is, if a control is needed in bit-0 and bit-15 only, it may be more space-efficient to generate it on both sides by a column 15b on both sides, instead of a line 11 going all the way accross the strip. Or, if a control 11 is needed in the area of the instruction register IR at the bottom of the strip and also in the area of the swap bus S at the top of the strip, then the control can be generated in the control ROM 15 at both places, rather than running a metal or poly line from one area to the other. REGISTER-TO-REGISTER ADD OPERATION : One of the most common instructions in any processor is "add". In the processor described herein, the add instruction uses workspace addressing. The two operands are obtained from registers in the main memory 2 via bus 4 and the result is stored in a register in the memory 2. Various addressing modes may be used, including direct, indirect, automatic incrementing, or relative. The example uses register direct addressing for one operand located in the workspace, and register indirect addressing for the other operand which is in a register whose address is located in the workspace; the result is stored in the same register which is directly accessed for an operand. This instruction is referred to as "ADD" *R, R″ for programming purposes. Execution of the add instruction of the example uses parts of seven "state" times or clock cycles. The timing sequence of clocks used in the microprocessor 1 is shown in Figure 2d and includes four overlapping half-cycle clocks H1, H2, H3 and H4. The clock H4 of course occupies part of the state time after the one in question. Also, a state time contains four quarter cycle clocks Q1, Q2, Q3 and Q4. The device is built using N-channel technology, so the clocks are positive-going. Typically, the state time is 200 nsec., or the repetition rate is 5 MHZ. The clock input 0 to the chip or the crystal frequency is four times the state frequency or about 20 MHZ. The memory 2 can be accessed within a state time of the microprocessor 1, so when an address is sent out on the bus 4 during Q2 of a given state time the contents of the addressed location will appear on the bus 4 for input to the microprocessor chip 1 during Q4 or H4 in the same state time. The add instruction of the example requires five memory access operations: one to fetch the instruction, one to fetch the address of the "source" operand, two for the "source" and "destination" operands, and one to store the result in the memory 2 at the "destination" location. The instruction for the add operation of this example is fetched before the previous instruction has completed execution. This pre-fetch feature results in a significant advantage in operating speed. It will be assumed that the prior instruction was also an add operation, and that the next instruction following the one of the example is also an add operation, to illustrate the pre-fetch feature and overlap of operations. Of the seven state times partially occupied by the add operation of this example, the first two are shared with the prior instruction and the last two are shared with the following instruction execution; thus only the central three are exclusively used in this add operation. Referring now to Figure 7 a timing chart for execution of the ADD *R, R instruction is illustrated. The seven state times to be discussed are designated S1 through S7. Briefly, during S1 (which overlaps the prior add instruction) the instruction word in question is pre-fetched by sending out the address which is in the PC register onto the bus 4 to access a location in the memory 2 (ordinarily the ROM part which contains program rather than the RAM part which is used for workspaces); then the contents of this location are received back on the bus 4 and loaded in to the instruction register IR. During S2, the result of the prior operation is written into the location in the memory 2 which is in the memory address register MA; the contents of MA register are sent out on the bus 4 followed by the result of the previous add operation. Meanwhile, during S2, the contents of the WP register are added in the ALU 10 to a number derived from the instruction word pre-fetched during S1; this number is two times the source register number, or 2S. So, the address of the source register is calculated during S2 and is stored in the MA register, then during S3 this address is sent out on the bus 4 to access the source address contained in the selected register of the workspace; this source address is read from the memroy 2 and returns via bus 4 to be stored in MA and K registers in microprocessor 1. During S4 state time the address of the source operand is sent out from the K register onto bus 4 and the contents at this address in memory 2 returned via bus 4 to the K register. Also during S4 the destination address is calculated in ALU 10 by adding the contents of the WP register to two times the "D" field of the instruction word and storing the result in the MA register. Next, during S5, this calculated D address (within the workspace, thus "direct") is sent out from MA register on bus 4 while the operand in the K register is moved to the T register. Then, the contents of the addressed register in memory 2 is returned via bus 4 to be stored in the K register of the chip 1, still during S5. Now the add operation is ready to be implemented; the S operand is in the T register and the D operand is in the K register. Thus, during state S6 the add operation is executed by adding the contents of K and T and putting the result in the D register. Meanwhile, however, during S6 the instruction for the next operation is pre-fetched by sending out the address in the program counter PC (which has been incremented) onto bus 4 and receiving the contents of this address in memory 2 back via bus 4 to be loaded during S7 in the instruction register IR in chip 1. Also, during S7 state time, the result of our example add operation is written into memory 2 by first sending out the address in the MA register (which is the D or destination address calculated during S4) onto bus 4, followed by the contents of the D register, completing execution of the ADD *R, R instruction. During S7, incidentially, the source address for the next instruction is calculated in the ALU 10 adding the contents of the workspace pointer WP to two times the S field of the instruction word accessed in S6, so another add operation is already two state times into its execution sequence. Accordingly, the states S6 and S7 correspond to the states S1 and S2 of Figure 7. The instruction word for "ADD R*, R" is shown in Figure 7a. This is the sixteen bit word which is read during S1 state time in Figure 7, i.e., the contents of the location addressed by the PC register, in this example. The first 3-bit field 010 says "add". The "B" field, bit 3, defines whether this is a byte operation or a word operation; in this example it is a word operation. If B = 1, the operands are bytes and the operand addresses are byte addresses. With B = 0, the operands are words. The TD and TS fields, bits 4, 5 and 10, 11, determine the addressing mode of that operand. In the example, TS is 00 so the S field (bits 12-15) contains the register number in the workspace which has the source operand. TD is 01, meaning indirect workspace register addressing mode, so the D field (bits 6-9) contains the register number in the workspace which has the address of the distination operand in it. Considering the execution of the ADD *R, R instruction example in more detail, it will be noted that Figure 7 also shows the contents of the various registers and busses as a function of time, as well as other features. Each of register and bus operations will be examined for each microcode state time, along with the control signals produced on the lines 11 to produce these operations. In the S1 state time of Figure 7, the control line 11 for H1PCTP (see Figure 5c) is high during H1, turning on transistors PCi and placing the contents of the PC register on the P bus. Then the DEN command goes high on H1, so the P bus is loaded into the output buffers 12 and thus to the bus 4. The program counter PC is incremented during H3 time by the H3PCINC command on a line 11, turning on transistors PCj and PCm of Figure 5c, so later at S6 the next instruction in sequence will be accessed. A DEN signal comes up on H2 on a control line 11 to produce a DEN-command at H3 on one of the lines 5 to enable the memory 2 to put data on the bus 4 beginning at Q4. The instruction word fetched here is valid on the bus 4 beginning at Q4, and is loaded into the K register via lines SK by a control H3 KFSS generated every H3 except when blanked; this control turns on the sixteen transistors Ki of Figure 5b. During this state time S1 an add operation for the prior instruction occurs just as will be described for S6, directing the result to the E bus. A control SAMPI on one of the lines 11 causes the interrupt lines 8 to be sampled so that if an interrupt is present a context switch will occur. Turning now to the S2 state time of Figure 7, the instruction which is in the K register is connected to the DI bus at Q1 when the Q1KTDI command goes high and turns on the sixteen transistors Kg; this command occurs every Q1 unless blanked by a control line 11. A command 2STA at H1 causes the S field of the instruction word on the DI bus to be left-shifted and connected by four transistors Ca to bit-11 through bit-14 of the A bus as seen in Figure 5e. The contents of the workspace pointer register WP are transferred to the B bus at H1 by the H1WPTB command on a line 11 turning on the transistors WPf of Figure 5c. Thus, with WP on the B bus and 2S on the A bus, when the ALU 10 operated (at H2 and H3) an output will be produced at node 10C during H3 which is the sum (WP + 2S). A command ALTE on a line 11 occurs at delayed H1 time, meaning delayed one state time, so at H1 of the next cycle the ALU output is connected by transistors 10a to the E bus. As will be described below with reference to the S7 state, the result of the previous operation is written into memory 2 from D register which was loaded from the E bus at H4; the ALU 10 loaded the E bus at S2, H1 (the same as HD1 for S1). During the S3 state time of Figure 7, the address of the register which will contain the source address is generated by an ALU operation. In this operation the contents of the workspace pointer register WP are applied to the B bus by an H1WPTB command turning on transistors WPf and an IR2D command at H1 which applies bit-6 through bit-9 of the instruction register IR to bit-11 through bit-14 of the DI bus via the transistors IRe′ of Figure 5g. The IR2D command in effect left shifts the D field of the instruction word (see Figure 7a) by one bit to multiply by binary two, then applies it to the A input of the adder via the DI bus. The ALU 10 is in the add condition by default, none of the ALU 1-ALU 4 commands being present, and the input 10c is applied to the E bus at H1 of the next state time by the HD1ALTE command on the line 11 to the gates of transistors 10a (Figure 5d). Execution From On-Chip Memory The auxiliary on-chip memory 25 provides a method for adding new functions not in Table D and enhancing the performance of specific kernels of software, thereby increasing the total capabilities of the system of Figure 1. The memory space 25 is separate from the user space 2 of Figure 2b and is contained within the microprocessor chip 1. Assembly language program segments located in this space 25 benefit from the full performance capabilities of the processor 1 since no wait states are required for memory accesses. While executing in the on-chip memory 25, certain control capabilities are available which are not accessible by ordinary programs. The auxiliary on-chip memory 25 permits a new instruction to be emulated in a manner completely transparent to the programmer. The memory 25 consists of 512 16-bit words in ROM 25A and 16 words in RAM 25B. The ROM resides at addresses ( in hexadecimal) 0800-OBFE, and the RAM resides at addresses 0000-001E, serving as workspace storage during execution in memory 25. Whenever the processor 1 encounters an MID opcode (an illegal opcode or an XOP executed while status bit-11 is set to 1), a check is made to determine whether an attached processor is prepared to respond to the MID opcode. If not, program control is transferred to the memory 25. The memory 25 is entered via an entry point table occupying the first ten words of the ROM 25A. Each entry in the table contains the start address in ROM 25 of an emulation routing for a particular MID opcode or group of opcodes. Illegal single-word opcodes are divided into eight groups, with the entry addresses for each group as indicated in Table F. Illegal two-word opcodes are treated as a ninth group, and XOPs as a tenth, as shown in Table F. When an illegal opcode or XOP is encountered, instruction execution transfers to the ROM 25A address in the entry-point table corresponding to that opcode. A context switch occurs after the entry-point address has been read from the table. The workspace pointer is set to 0000 and the program counter is set to the entry-point address. The old WP, PC, and ST are placed in the RAM 25B at locations in the workspace corresponding to R13, R14 and R15, respectively. The PC value saved in R15 points to the word following the MID opcode. If the MID opcode is a multiple-word instruction, the saved PC points to the location following the first word of the instruction. To exit the memory 25, a context switch is invoked by executing a RTWP instruction (opcode 0380 in hex). Interrupts are checked prior to executing the next instruction. In those instances where interrupts (maskable or non-maskable), should not be checked before executing the next instruction, the exit from the memory 25 is invoked using the opcode 0381, a special form of the RTWP instruction. In either case, the WP, PC, and ST registers are updated with R13, R14 and R15 from the RAM 25B. If the memory 25 is entered upon detection of an MID opcode not supported by the memory 25, a level-2 must be executed to indicate that an attempt has been made to execute an undefined opcode. The opcode 0382 is provided to exit the memory 25 under these conditions. When this opcode is executed in memory 25, an RTWP occurs follow by a level-2 trap. The opcodes 0380, 0381 and 0382 (hex) provide the only valid means for performing an exit for memory 25. During emulation of an MID opcode 25, the emulation routine can modify the saved status register in R15 in accordance with the results of the emulated opcode. Upon return from the memory 25, the updated status is passed to the main instruction stream. If the status is not updated, it will be restored in its original form. During execution in the memory 25, several processor functions are modified to provide increased control. These are interrupts, external memory accessing, an evaluate address instruction EVAD, and conditional jump, as will now be described. All interrupts except reset are inhibited while executing from memory 25. However, pending interrupts can be detected using the conditional jumps described below. During execution from memory 25, data in external (off-chip) memory 2 is accessed using the indirect, indirect autoincrement and indexed addressing modes. Workspace registers R2, R6, R7, R8, R9, R10, R13 and R14 in the RAM 25B are used as base registers during external accesses. An external access using one of these registers is accompanied by a bus status code indicating a particular type of memory cycle, and MEM-is active low. The bus status code corresponding to the use of each register is indicated in Table G. An external access should utilize a base register whose use is accompanied by a bus status code appropriate to the type of access being performed; the programmer selects a register from Table G accordingly. Two examples illustrate use of the external access capability. First, R13 in the RAM 25B contains the user's workspace pointer. To read into register R1 in the workspace of RAM 25B the contents of register R4 in the workspace in memory 2 from the main instruction stream executing just prior to entering memory 25 (i.e. the "user's" workspace), the instruction MOV @8(R13), R1 is executed from memory 25. This instruction says move the contents of the location of address at R13 plus 2x4 =8 into R1. A WS bus status code is output during this operation (MEM-=0, BST=110). Second, to read immediate data or a symbolic address (following an MID opcode in the user's program) into R4 in RAM 25B, the instruction MOV *R14+,R1 is executed while in memory 25. This causes the user's PC in R14 in RAM 25B to be incremented by two, and an IOP bus status code is output (MEM-=0, BST=010). Using register R0, R1, R3, R4, R5, R11 and R15 as base register for indirect, indirect autoincrement or indexed addressing results in an internal access in the memory 25. During internal accesses, the MEM-, WE- and DEN- signals output from the processor 1 remain inactive high. During execution from memory 25, a NOP bus status code is output during each machine cycle except when an external access is in progress, as explained above. An EVAD (evaluate address) instruction is provided during execution from memory 25 to permit convenient calculation of effective source and destination addresses of MID opcodes. EVAD assumes that the MID opcode contains a four-bit opcode, a six bit source field and a six-bit destination field. The address calculations are based upon the original WP of the user, saved in R13 in RAM 25B. If the contents of a register in the user's workspace are fetched as part of the address calculation, a WS bus status code is output by the processor 1 while the external access takes place. The saved PC (in R14 of RAM 25B) is incremented appropriately if symbolic or indexed addressing is used. The contents of any workspace register in RAM 25B except R0 can be evaluated using EVAD. When EVAD is executed, the calculated effective source address is placed in R8 in RAM 25B, and the calculated distination address in R7. If the source or destination field specifies autoincrement mode, the address of the user's register is placed in R9 or R10, respectively. A summary of the EVAD instruction, including its effect on status bits 0 and 2, is given at the end of Table D. For EVAD instructions, if only the source field of an MID opcode is to be evaluated, the destination field should be cleared to prevent unnecessary external accesses or unintentional modification of the user's PC. For example, if the MID opcode resides in R5 in Ram 25B, the instruction sequence ANDI R5, 003F EVAD R5 is executed while in the memory 25 to calculate the effective source address. The destination field, which is all zeros, is interpreted as register direct addressing mode (and ST2 is cleared.) The TB (test bit), SBO (set bit to one) and SBZ (set bit to zero) instructions are not available during execution from memory 25. In place of these operations and using the same opcodes are conditional jump instructions used to detect pending interrupts. These instructions, allow interrupts to be tested at interruptible points in routines executed from memory 25. Instructions requiring long execution times, such as block move instructions for a minicomputer, can be emulated in a way that permits them to be interrupted and resumed after interrupt servicing. One restriction exists regarding the use of MID opcodes within interrupt service routines. An MID opcode encountered in the interrupt routine for an NMI or level-1 interrupt, or for a reset routine that does not cause complete system reinitialization, must not result in an exit from the memory 25 by means of opcode 0382, the special form of RTWP that causes a level-2 trap. The reason is that the level-2 routine can be interrupted by an NMI, by a level-1 interrupt or by reset, possibly destroying the return linkage established previously. In general, this restriction can be interpreted to mean that an MID opcode in the service routine of an interrupt of higher priority than level-2 must either be recognized by an extended instruction set processor or defined by an emulation routine in the memory 25. The last sixteen words of the ROM 25A may be reserved for self-test software used to verify ROM 25A and RAM 25B operation. MID opcode 002D, defined to be the opcode for an execute micro-diagnostics instruction in a minicomputer, is executed in the user program to invoke the self-test routine. Upon encountering this opcode, the processor 1 transfers control to the ROM 25A location (start address of the test routine) pointed to by the address contained in entry-point table location 0804, in the manner indicated in Table F. Emulation of the On-Chip Memory : In order to allow emulation of the processor 1 with an on-chip memory 25, the processor may be constructed to access an off-chip memory as if it were the ROM memory 25A. This is important for systems development or prototyping purposes. The "software" or firmware written for the ROM 25A must be checked out and de-bugged before the masks are made to produce the chips 1 in volume for a specific customer application. To this end, the control circuitry 24 responds to a special indication in the form of pulling RESET- and XIPP-low and releasing them simultaneously. This is accomplished by wiring the two together at the external pins. Referring to Figure 1a, when this emulator mode is thus entered, the ROM 25A is no longer used, and addresses 088-OBFE access an external memory 25A′ (but not within the memory map 2b). The on-chip RAM 25B is still active and is used, so addresses 0000-001E are responded to in the usual manner by the memory 25. In this mode, accesses to the ROM 25A are instead directed to the memory 25A′ off-chip, and this memory 25A′ may be either ROM, EPROM or RAM. These accesses are accompanied by active WE- and DEN- signals on the lines 5, along with a NOP or 001 code on the BST lines 6. When operating in this mode, the memory 2 is connected to receive the BST lines 6 so that it will not respond when the bus status code is NOP, which distinguishes memory 25 accesses from accesses of the user memory 2 address space of Figure 2b. This emulator mode has other advantages in addition to systems development. Parts manufactured with unusable codes in the ROM 25A, or non-functional ROM 25A, need not be discarded, but instead can be used as emulator devices. Also, small volume custom application may use the processor 1 exclusively in the emulator mode, with all the accesses to memory 25A going to the off-chip memory 25A instead. As production volume for such an appreciation rises, the firmware can then be moved on-chip to reduce the systems parts count. This has advantages for applications where the initial cost of the completely-custom internal firmware for the on-chip ROM 25A is not justified. Extended (Off-Chip) Accesses for On-Chip Memory : As described above, all accesses to the memory 25 in the normal mode are accompanied by a NOP bus status code on lines 6 to indicate that an internal cycle is in progress. The address to the memory 25 are actually output via buffers 12 and bus 4, and data from the memory 25 is likewise output. This is only to facilitate debugging and testing because the memory 2 does not respond since the WE- and DEN- outputs on lines 5 from control circuitry 24 are inactive. A useful alternative is to permit accesses to additional off-chip auxiliary memory to exapnd the memory 25, still separate from the memory map of Figure 2b. To this end, accesses to memory 25 space not within the defined addresses 0800 to OBFE and 0000-001E is responded to in a special way. When in the MID mode, i.e. accessing memory 25 as described above, an address outside the range of memory 25 will cause the control circuitry 24 to activate WE- and DEN- outputs on the lines 5; NOP (and MEM- high) still appears on the BST lines 6. When this occurs, a memory 2′ is accessed as indicated in Figure 1a. The system memory 2 is connected to the BST lines 6 so it will not respond when NOP is involved. This mode of operation has advantages in adding to the flexibility of the system. The memory 25, off-chip or on-chip, is entirely separate form the user memory space, so complex system functions (added instruction set) are implemented while leaving the user (programmer's) address space intact for simplicity. Speed-critical functions otherwise built up in software can be implemented in extended memory 2′ for increased efficiency. Part or all of the off-chip memory 2′ can be fast RAM, which will execute faster than if ROM were used because no wait states are needed; the RAM can be used for scratch storage, or loaded upon command with updated emulation software. Of course, the extend off-chip memory 2′ for memory 25 provides room for more functions than can fit on the on-chip memory alone, so more complex systems can make use of the processor 1. Indeed, attached-processor type functions can be implemented using the extended memory 2′, needed nothing other than memory components and software written in standard assembly language. As with the on-chip memory 25, the off-chip extension 2′ of the memory 25 is completely transparent to the user-programmer (all the software is generated in the systems design), and resides in address space entirely separate from the user memory 2. ADDRESSING MODES : The instructions of Fig. 2c may be used with a variety of available modes for addressing random memory data (e.g., program parameters and flags), or formatted memory data (character strings, data lists, etc.). These addressing modes are: a) Workspace Register Addressing b) Workspace Register Indirect Addressing c) Workspace Register Indirect Auto Incrementing Addressing d) Symbolic (Direct) Addressing e) Indexed Addressing f) Immediate Addressing g) Program Counter Relative Addressing h) CRU Relative Addressing The following description explains the derivation of the effective address for each addressing mode. The applicability of addressing modes to particular instructions is included in Table D along with the description of the operations performed by the instruction. The symbols following the names of the addressing modes (R, *R, #R+, @LABEL or @TABLE (R)) are the general forms used to select the addressing modes for a register R. Workspace Register Addressing, R The workspace register R contains the operand, so the workspace pointer WP plus 2R gives the address of the operand. The worksapce register addressing mode is specified by setting the two-bit T-field (TS or TD) of the instruction word equal to 00. Workspace Register Indirect Addressing, *R The workspace register R contains the address of the operand, so the workspace pointer WP plus 2R gives the address of the register R containing the address of the operand. The workspace register indirect addressing mode is specified by setting the two-bit T-field (TS or TD) in the instruction word equal to 01. Workspace Register Indirect Auto Increment Addressing, *R+ The workspace register R contains the address of the operand just as in WR indirect addressing, but after acquiring the address of the operand, the contents of workspace register R are incremented. The workspace register indirect auto increment addressing mode is specified by setting the two-bit T-field (TS or TC) in the instruction word equal to 11. Symbolic (Direct) Addressing, @LABEL For this mode, the word following the instruction contains the address of the operand. The program counter PC contains the address of the instruction and (PC)+2 is the address of the operand. The symbolic address mode is specified by setting the two-bit T-field (TS or TD) in the instruction word equal to 10 and setting the corresponding S or D field equal to 0. Indexed Addressing, @Table (R) For indexed addressing, the word following the instruction contains the base address, the workspace register R contains the index value, and the sum of the base address and the index value results in the effective address of the operand. The indexed addressing mode is specified by setting the two-bit T-field (TS or TD) of the instruction word equal to 10 and setting the corresponding S or D field not equal to 0. The value in the S or D field is the register which contains the index value. Immediate Addressing Here the word following the instruction (i.e. PC plus 2) contains the operand. No T-field is pertinent here because only immediate instructions use this mode. Program Counter Relative Addressing For this mode, the eight-bit signed displacement in the right byte (bits 8-15) of the instruction is multiplied by two and added to the updated contents of the program counter PC; the result is placed in the PC. Macro Instruction Detection (MID) Trap The acquisition and attempted execution of a macro-instruction opcode will cause the MID trap to occur before execution of the next instruction. Macro-instruction opcodes which cause the trap are listed in Table F. The MID interrupt has basically two applications. The MID opcodes can be considered to be illegal opcodes and the MID trap is then used to detect errors of this nature. The second, and primary application of the MID trap is to allow the definition of additional instructions for the processor, using the on-chip memory 25 or using software in the MID trap service routine to emulate the execution of these instructions. MID opcodes are used as the opcodes for these "macro" instructions. The benefit of this implementation of macro instructions is that the macro instructions can be implemented in the memory 25, in microcode in other processors, or in software by the service routine, and software will then be directly transportable among these processors. When instruction emulation is performed, the subroutine can modify the saved status register ST in workspace register R15 in accordance with the results of the emulated instruction. The updated status will then be passed to the main instruction stream. Otherwise, unmodified status will be restored by the return. Although the invention has been described with reference to a specific embodiment, this description is not mean to be construed in a limiting sense. Various modifications of the disclosed embodiment, as well as other embodiments of the invention, will become apparent to persons skilled in the art upon reference to the descriptionof the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention. TABLE A DEFINITION OF CONTROL LINES ALATCH Address latch. When active (high), ALATCH indicates that address information is present on the bus 4. When inactive (low), ALATCH indicates that either memory data or CRU data is present on the bus 4, or that the bus 4 is in another state, depending upon the values of the BUS STATUS bits and MEM-. (ALATCH=0 is a strobe for decoding MEM- and BST1-BST3, which will be stable when ALATCH=0.) ALATCH has a low-to-high followed by a high-to-low transition at the beginning of every bus cycle. During a HOLD state, ALATCH will remain low when the READY and WAITGEN signals indicate a wait state. MEM- Memory cycle. When low, MEM- indicates that the bus 4 is in a memory cycle, and when high, MEM-indicates that the bus 4 is in another type of cycle or state, depending upon BST1-3. MEM- assumes the high impedance state when HOLDA is active. An internal resistive pull-up maintains a high level. WE- Write enable (also inverted CRU clock). When low, WE-indicates that memory write data is available on the bus 4 (when MEM-=0); or that CRU data out is available on bit-15 of the bus 4. (CRU bus status); WE- is a three-state signal and assumes the high impedance state when HOLDA is active. An internal resistive pull-up maintains a high level. DEN- Data driver enable. When active (low), DEN- indicates that a read (memory or CRU) cycle is taking place on the bus 4 and that external devices such as in memory 2 or CRU 7 may enable 3-state drivers that output data onto the bus 4. DEN- is a 3-state signal and assumes the high impedance state when HOLDA is active. An internal pull-up maintains a high level. READY Ready: When active (high), READY indicates that memory 2 or the CRU 7 is ready to complete the present bus cycle. When not-ready is indicated, a Wait state (defined as extension of the present bus cycle by two clock cycles) is entered. At the end of each Wait state READY is examined to determine if another Wait state is to be generated or if the bus cycle is to be completed. WAITGEN Wait state generate. When active (high) at the first sample time of READY in a memory or CRU bus cycle, WAITGEN will generate the first Wait state regardless of the logic level of READY. After this first sample time, the logic level of WAITGEN is ignored and extension or completion of bus cycles is determined by READY alone. WAITGEN may be tied high to provide a simple means of generating a single Wait state, and can help minimize problems associated with propagating a Ready/Wait indication to the processor 1 in large, multi-board systems. RESET- Reset. When active (low), RESET- causes the processor 1 to set all status bits in status register ST to zero and inhibits WE-, DBIN- and MEM-. When RESET- is released, the processor 1 initiates a level zero interrupt sequence that acquires WP and PC from locations 0000 and 0002 in memory 2, sets all status register bits to zero, and starts execution. RESET- will also terminate an idle state. RESET- must be held active for a minimum of one CLKOUT cycle. RESET- is a Schmitt-trigger input. HOLD- Hold. Used as a DMA or direct memory access request. When active (low), HOLD- indicates to the processor 1 that an external controller 3 desires to use the bus 4. The processor 1 enters the Hold state following a hold signal when it has completed its present bus cycle. The processor 1 then places the bus 4 in the high impedance state (along with MEM-, ALATCH, BSTI-3, DEN-, and WE-) and responds with a HOLDA encoding on BSTI-BST3. When HOLD- is removed, the processor 1 returns to normal operation. BSTI-BST3 Bus status codes. When decoded in conjunction with MEM-, BST1-BST3 provide information about the type of bus cycle or state currently in progress (e.g., Memory, Internal ALU, HOLDA, Interrupt Acknowledge, Instruction Acquisition, and Multi-Processor Interlock). ALATCH provides the appropriate timing to strobe this decode (MEM- and BSTI-BST3 valid when ALATCH 1wo). BST1-3 assume a high impedance state when HOLDA is active. An internal resistive pull-up maintains a high level (HOLDA Bus Code). XIPP- External Instruction Processor Present. When the processer 1 fetches an illegal op-code (or an XOP), the XIPP- signal will be sampled at the end of the MID bus state. If XIPP- is true, the processor 1 will execute the trap to the Level 2 interrupt vector (XOP vector for an XOP). It will fetch the new WP and store the old WP, PC, and ST in the new workspace (registers 13, 14, and 15 respectively). At this point, the processor 1 enters the Hold state and responds with HOLDA encoding on BSTI-BST3. After completing the instruction, the external processor 3 releases XIPP (after first updating WP, PC, and ST as required by the instruction). The release of XIPP- signals the processor 1 to refetch the updated WP, PC, and ST from trap registers 13, 14, and 15 and continue normal execution. (If there is no external processor 3 present, the processor 1 completes the trap and performs the instruction in software). INTP- Interrrup Pending. The INTP- is true whenever an interrrup which is not masked or a non maskable interrupt (NMI-) is detected. This signal is not tri-state and may be used to interrupt an external instruction processor 3 which is doing a series of instructions. INTREQ- Interrupt request. When active (low), INTREQ- indicates that an external interrupt is requested. If INTREQ- is active, the processor 1 loads the data on the interrupt-code-input lines 8 (ICO-IC3) into an internal interrupt-code-storage register 23. The code is compared to the interrrupt mask bits of the status register ST. If equal or higher priority than the enabled interrupt level (interrupt code equal or less than status register bit-12 to bit-15 the interrupt sequence in initiated. If the comparison fails, the processor 1 ignores the request. INTREQ- should remain active and the processor will continue to sample lines 8 (IC0-IC3) until the program enables a sufficiently low priority to accept the request interrupt. ICO-IC3 Interrupt codes. Applied to lines 8. ICO is the MSB of the interrupt code, which is sampled when INTREQ- is active. IC3 is the LSB. When IC0-IC3 are LLLH, the highest external priority interrupt is being requested and when HHHH, the lowest priority interrupt is being requested. Interrupt levels are shown in Table C. NMI- Non Maskable Interrupt. When active (low), NMI- causes the processor 1 to execute a nonmaskable interrupt with memory address FFFC containing the trap vector (WP and PC). The NMI sequence begins after the instruction being executed is completed. NMI- will also terminate an idle state. If NMI- is active during the time RESET- is released, then the NMI- trap will occur after the RESET- function is completed. NMI- must be active for at least one clock cycle to be recognized and will only be recognized once for each high-to-low transition.

Claims: A microprocessor formed in a single semiconductor body comprising: an arithmetic logic unit (10), a plurality of separate registers (IR, K, D, MA, PC, WP, T, MQ, ST); a plurality of bus lines (A, B, DI, E, P) for selectively connecting the inputs and outputs of said arithmetic logic unit (10) and said plurality of registers, a logic array (15) for generating a plurality of control signals, said logic array (15) having a plurality of row lines (15a) and a plurality of column lines (15b) intercepting said row lines, a plurality of control lines (11) connected to said logic array (15) and providing outputs therefrom, said plurality of control lines (11) being connected to said arithmetic logic unit (10) and said plurality of registers for applying control signals from said logic array (15) thereto to connect selected ones of said bus lines (A, B, DI, E, P) to and from inputs and outputs of said arithmetic logic unit (10) and said registers, and addressing means (16) for selecting row lines (15a) and column lines (15b) of said logic array (15) to selectively activate respective ones of said plurality of control lines (11); characterized in that the plurality of column lines (15b) of said logic array (15) are divided into a plurality of separate groups with one group for each of said control lines (11), and said addressing means (16) being effective to select no more than one column line (15b) in each group for activation in response to an address, the number of column lines (15b) per group differing among the groups. A microprocessor as set forth in claim 1, further characterized in that a potential cell is provided at the intersection of each row line (15a) and each column line (15b) of said logic array (15). A microprocessor as set forth in claim 2, further characterized in that the potential cells are insulated gate field effect transistors. A microprocessor as set forth in either of claims 2 or 3, further characterized in that there is at least one cell on each column line (15b) in each group of column lines (15b) of the logic array (15). A microprocessor as set forth in any preceding claim, further characterized in that said addressing means (16) in selecting column lines (15b) activates a column line (15b) in some but not all of said groups for a given address. A microprocessor as set forth in any preceding claim, further characterized in that the maximum number of column lines (15b) in a group does not exceed N, and the given address contains C bits, where N = 2 C . A microprocessor as set forth in any of claims 2 to 4, further characterized in that the logic array (15) comprises a plurality of cell groups, each cell group including an array of potential cells with M row lines (15a) and N column lines (15b), first selector means (15c) for activating one of said M row lines (15a) as defined by an address of B bits, second selector means (15f) for selecting one of said N column lines (15b) as defined by an address of C bits, where M = 2 B , and wherein logically unneeded column lines (15b) of potential cells are physically omitted from the logic array (15), whereby N is an integer substantially less than 2 C , and the cell groups contain differing numbers N of column lines. A method of making a logic array (15) of rows and columns of potential cells for generating a plurality of control signals for a microprocessor, comprising the steps of: defining a logic array (15) by providing a plurality of row lines (15a) and a plurality of column lines (15b) intercepting said row lines (15a) at said potential cells, providing row select means (15c) for activating one row line (15a) in response to a first address, and providing column select means (15f) for activating one column line (15b) in response to a second address for selecting row lines (15a) and column lines (15b) to selectively generate respective ones of the plurality of control signals; characterized by defining a plurality of equal groups of said column lines (15b), one group for each control signal, the column lines (15b) in each group intercepting said row lines (15a) at said potential cells, activating no more than one column line (15b) in each group in response to the second address by said column select means, and physically eliminating from the logic array (15) column lines (15b) which contain no cells for a given sequence of control signals to be generated for the microprocessor, whereby each column line (15b) in every group contains at least one of said cells. A method as set forth in claim 8, further characterized by inverting said control signals to thereby increase the number of column lines (15b) containing no cells prior to physically eliminating from the logic array (15) the column lines (15b) which contain no cells. A method as set forth in either of claims 8 or 9, further characterized by populating the logic array (15) with cells using false logic to thereby increase the number of column lines (15b) containing no cells prior to physically eliminating from the logic array (15) column lines (15b) which contain no cells. A method as set forth in any of claims 8 to 10, further characterized by eliminating parts of said column select means for the column lines (15b) containing no cells. A method as set forth in any of claims 8 to 11, further characterized in that some of the groups of column lines (15b) contain unequal numbers of column lines (15b) after physically eliminating the column lines (15b) which contain no cells from the logic array (15). A method as set forth in any of claims 8 to 12, further characterized by forming an insulated gate field effect transistor at the location of each one of the potential cells for which a control signal is to be generated for a given first and second address. A method as set forth in any of claims 8 to 13, further characterized in that said addresses are selected to maximize the number of column lines (15b) containing no cells.

Inventors: GUTTAG,KARL M., LAWS,GERALD E., MCDONOUGH,KEVIN C.
Applicants: TEXAS INSTRUMENTS INCORPORATED
Application year: 1981
Main classification: G06F15
IPC codes: G06F9, G11C17, G06F15