SPEECH SYNTHESIS AID FOR THE VOCALLY HANDICAPPED

Abstract: A speech synthesis communication aid for the vocally handicapped comprises a selector panel for use with translucent overlays bearing words or symbols arranged in an 8x8 matrix array and having controls (16, 17) operable by a user to enable selection and consequent back-illumination of one or more of the matrix cells. A microcomputer (15) is programmed to respond to cell selection to organise the back-illumination and also correspondingly to address a speech synthesiser circuit (10) having a read-only memory (7) containing data adapted for generation of speech signals so that an output is provided from the speech synthesiser circuit corresponding to the selected cell. The read-only memory is a plug-in module preprogrammed with a vocabulary corresponding to the words or symbols on a respective overlay, and a plurality of such modules and overlays are provided to obtain the requisite vocabulary repertoire. The microcomputer is also programmed to enable strings of speech utterances to be assembled by selection sequentially of a plurality of matrix cells and to be verbalised by the speech synthesiser, function keys (18) being provided for user operation to utilise this facility.

Description: Speech synthesis aid for the vocally handicapped This invention concerns a speech synthesis aid for the vocally handicapped which takes advantage of recent advances in the field of electronic speech synthesis to provide a relatively low-cost portable device- exhibiting substantial flexibility of applic ¬ ation ranging from a communication aid operable by a person incapable of speech to enable speech utterances selected from a preselected range to be made, to a device useful for example as a learning aid which couples synthesised speech utterances with the playing of a simple game or the performance of simple routine operations. In recent years speech synthesiser circuits have been developed to a point where devices are available which are capable of selective operation to output signals which when applied to drive an acoustic transducer produce clear and intelligible speech. Such devices commonly employ more or less complicated micro¬ electronic circuitry including read-only-memories (ROM's) pre-programmed with data information selectively accessible by a microcontroller for outputting the requisite signals for speech generation. Such circuits . .. .. __ . 44 - 2 - have found application in electronic calculators, instruments and computer-type peripherals where a spoken word output is desired in addition to for example a visual display, and it has been proposed to incorporate speech synthesis systems into oper¬ ating routines such as for example are involved in pre-flight checking of aircraft. The present inven¬ tion is not concerned with the actual circuits and methods employed for synthesising speech, rather the invention is concerned with applications for known speech synthesis devices. Hereinafter described, in accordance with the present invention is a speech synthesis commun¬ ication aid for the vocally handicapped which employs a small microcomputer to monitor control inputs and appropriately drive a visual display and a speech synthesiser unit. The aim ±9 to provide a portable and easily used aid for persons with speech handicaps. By means of simple controls, the invention allows the user to communicate via synthesised speech, independent of natural voice function. Since a broad vodabulary is required to cover the range of application, a modular approach employing interchangeable repertoire modules and associated word-selector overlays is used, the repertoire modules being designed so that the user may plug them into the speech aid as required. Assoc¬ iated with each repertoire module is a translucent overlay sheet on which appropriate symbols or words are printed, the overlay sheet corresponding to the currently installed repertoire module being adapted to be placed over a selector panel on the speech aid. This panel is comprised of a rectangular array of lamps any one of which may be selected by the user to be illuminated under microcomputer control, the arrange- ment being such that when an overlay is placed on the OMPI selector panel, the words or symbols of the overlay are positioned to locate over the lamps in the array and may be selectively highlighted to indicate selec¬ tion of the corresponding speech output. Selector controls are provided for changing, via the micro¬ computer, the lamp or lamps currently illuminated in the selector panel. Use of these controls allows the apparent movement of an index light behind the overlay sheet,' permitting the choice of desired words or symbols printed thereon. Having selected a word or symbol, other controls may be used to cause the in¬ vention to utter a spoken equivalent to that word, or to store it. In the latter case, a string of utter¬ ances may be constructed by repeatedly selecting and storing words or symbols. When the desired assembly has been created it may be synthetically spoken by operating the appropriate control. The capabilities to repeat and extend existing utterance strings are provided. Further to basic speech-aid capabilities, the invention includes options for extra therapeutic func¬ tions. By means of external connection facilities and appropriate programming, units may be interconnected or linked to a master console. These modes are inten- ded for teaching applications. The latter mode allows a teacher to monitor and guide pupils in the style of a language laboratory. Sentence construction exercises might be conducted through such a network equipped with suitable overlay sheets and vocabulary modules. Pro- vision is made for data to flow bidirectionally between speech-aid units and the control console. In a stand¬ alone therapeutic mode, the aid may function as a game or puzzle, simple concept-ordering problems being provided in pre-programmed form associated with specific overlay sheets and vocabulary modules and the vocal - k _ output of the unit being used to guide and encourage the user. The invention enables an unlimited reper¬ toire, a simple means of utterance selection and outstanding therapeutic capabilities. A lack of restriction on repertoire size is obtained by virtue of the use of interchangeable vocabulary modules and overlay sheets. The back-illuminated selector panel with uncomplicated controls (joystick or slider, or push-buttons, for example) facilitates utterance selection. Due to its microcomputer-based design, the invention is amenable to functional expansions • including network and games modes. The invention in its various aspects, and features and advantages thereof, will become fully apparent to those possessed of appropriate skills from consideration of the following descriptions of two exemplary embodiments of the invention, the first em¬ bodiment being described in outline and the second in detail, which are illustrated in the accompanying drawings wherein:- Fig. 1 is a top plan view of the operating panel of -the irst embodiment; Fig. 2 shows the circuit diagram (in block form) of the embodiment of Fig. 1; Fig. 3 shows the circuit diagram of an input . switch sub-system of the circuit of Fig. 2; Fig. 4 shows the circuit diagram of a display sub-system of the circuit of Fig. 2; and Figs. 5 and 6 together show the basic system software flow-chart of the first embodiment; and wherei :- Fig. 7 shows a—schematic circuit diagram of a microcomputer section of the second embodiment; Fig. 8 shows a schematic circuit diagram of display and keyboard sections of the second embodiment; Fig. 9 shows a schematic circuit diagram of speech synthesis and control key sections of the second embodiment; Fig. 10 shows a schematic circuit diagram of a power supply section of the second embodiment; Fig. 11 shows input/output port allocation in i the second embodiment; and Fig. 12 shows a simplified system software flow-chart of the second embodiment. i Fig. 1 shows the front face appearance of the first described embodiment which may be comparable in size and weight with a portable cassette tape recorder. The controls include an 8 8 cell individually and selectively back-illuminated selector panel 1 with *slider controls 3 and to allow choice of the cell illuminated on the selector panel, the controls selec¬ ting columns and rows respectively. Translucent word- defining overlay sheets (not shown) are laid on panel 1. Power to the unit is switched by 2, whilst keys 5 and 6 control "speak" and "store" functions of the unit, the "speak" key being used to initiate the device output and for repetition of utterances and the "store" key being used when sequentially selected utterances are to be strung together. The device of Fig. 1 is adapted to provide readily intelligible synthesised speech from a Tele- sensory Systems Inc. TSI-S2 large scale integrated two chip synthesiser with interchangeable vocabulary ROMS embodied as plug-in modules. The device operates under microcomputer control, a device from the Intel MCS-48 single-chip microcomputer family for example being selected for this purpose. The 87^8 unit of this family might by selected, this unit. being UV erasable and re- programmable and providing IK x 8 bits of control C PI memory, 64 x 8 bits of read/write memory and 27 input/ output (I/O) lines. Such a device is capable of around one minute of speech output per vocabulary module, divided among 64 selectable utterances. In the embodiment described only the speech output mode is provided. Symbols selected by the user are uttered by the invention. Utterances may be stored to produce strings of words and may be repeated. Expansion to include the network and therapeutic puzzle modes mentioned hereinbefore is readily available by appropriate reprogra ming of the microcomputer con¬ trol memory and the addition of a simple hardware inter ace. The system may be considered as five sections, namely:- (i) a single-chip microcomputer with support components; (ii) input switches and associated bus-sharing com onents; (iii) the speech synthesiser chip set and assoc¬ iated audio-path components; (iv) decoders controlling the selector panel and system enable lines; and (v) the selector panel driver and lamp array sub-sys em. Referring to Figs. 2, 3 and 4 of the accom¬ panying drawings, an Intel 8748-8 microcomputer 15 (Fig. 2) operating with a cycle time of 4.17us is the central controlling element of the system, ports 1 and 2 of the microcomputer being used for output and mixed I/O respectively. Output port 1 provides a six bit select bus to speech synthesiser integrated circuit 10 and to display decoders 8 and 11. The speech synthe¬ siser 10 comprises for example a Telesensory Systems Inc. device no. S2. Bits 6 and 7 remaining from Port 1 OMPI are decoded to provide four system module enable lines via decoder 13• These lines are used to control the speech synthesiser 10 and the input subsystem cons¬ tituted.by selection switches 16, 17 and function keys l8. The low order four bits of Port 2 are not used to control intrinsic system functions, but are dedicated to the role of providing the top four bits of addresses to external program memory in conduction with 8 lines from address latch 19. These low order address bits are strobed from the data bus into the address latch during ALE cycles. Bits 4 to 7 of Port 2 are used to input data from the. select and function switches 16, 17 and 18. As shown in Fig. , all three switch modules share the bus and are selected onto it by pulling switch? common lines to ground via transistors 21, 23 and 26. These devices are controlled by system enable lines. The structure of the 8748 Ports 1 and 2 is such that, when configured as inputs, lines are internally pulled high by 50k resistors, thereby obviating the need for external pull-ups. The diodes 20, 22, 24 and 25 assoc¬ iated with the switches prevent the state of disabled switches from effecting valid data. Fig. 2 shows the speech synthesiser LSI, 10 interfaced to the microcomputer 15 via eight lines; the previously mentioned six-bit utterance select input, and "start" and "busy" lines. A level-shifting network is provided as shown in Fig. 2 on appropriate synthesiser 1/0 lines to allow interfacing of the TTL and PM0S logic signals. "Start" is an input and is controlled by a system enable line. "Busy" is a status output indic¬ ating synthesiser non-availability, and is monitored by a single-bit testable input, TO. Connections are also made to a vocabulary ROM 7 » housed in a plug-in module. This contains the parameters associated with the utterance set from which the synthesiser reconstructs speech. Resulting audio signals are low-pass filtered by ilter circuit 9 to remove sampling frequency components associated with digital signal processing. 5 They are then fed, after ampli ication by a small monolithic audio amplifier 12, to a loudspeaker 14. The circuit diagram of the eight by eight incandescent lamp display matric constituting the selector panel is represented in Fig. 4 which is a 10 simplified diagram showing only four element lamps and associated drivers, the full system comprising eight such row and column drivers connected to 64 incandescent lamps each with an associated diode. Lamps 30 etc. are driven by row and column PNP* tran- 15 sistor buffers 27 and 28 respectively. Eight tran- sistors make up each buffer. These devices are acti¬ vated by low- true signals derived from two 74 S138 -three-to-eight line decoders (8 and 11 in Fig. 2) controlled by bits 0 to 5 of Port 1 of microcomputer 20 15. Diodes 29 etc. are employed in the array to prevent spurious current paths through unselected lamps. 1 System expansion facilities have been provided by incorporating an address bus latch (Fig. 2, 19) and by making PSEN (program Store Enable), RD (Read), WR 25 (Write) and the data and address busses externally accessible. Memory mapped interface devices and up to 3K bytes of program memory and 190 bytes of data mem¬ ory may be added to the system via these expansion facilities. ; 30 System software is illustrated by the flow¬ chart of Figs. 5 and 6 wherein the following terminology is employed:- UTT ADDR is the synthesiser and selector panel control address; and 35 UTT PTR is a pointer to the current UTT ADDR storage location in data memory. O PI Referring to Figs. 5 and 6, the majority of CPU time is spent in an idle loop in which the selec¬ tor panel controls and function keys are scanned. Display refreshing is done in this loop, illuminating the current lamp for 20 ms per cycle. After reading the row and column selector switches, the data obtained is translated from Qrey code (produced by the slide logic switches) to an UTT ADDR. This is then compared with the UTT ADDR obtained in the last scan. A repeat flag, FO is set if a change is detected. When the "Store" key is actuated, the current UTT ADDR is stored at the UTT PTR location, the FO flag is cleared and the UTT PTR is incremented. Thus a string of utterances may be stored by alternately setting the selector panel controls and depressing the "Store" key. Actuation of the "Spea.k" key causes the FO flag to be tested. If it is set, the selector panel controls have been altered since the last speak or store operation, and a new item is assumed. Thus the UTT PTR and FO flag are reset before the selected utterance is output. If the F0 flag is not set, repeat mode is assumed and the current stored string is output, leaving the UTT PTR unchanged, ready for a repeated output if the "Speak" key is re-depressed. If the "Store" key is actuated at this point, new utterances may be added to the end of the existing string. It will be appreciated that the flow diagrams (Figs. 5 and 6) are at a high level and do not show the structure of specified operations. The function key input subroutine is edge- sensitive and includes debounce delays to avoid spurious data entries. The "speak string" subroutine outputs to both the speech synthesiser and selector panel. Data is output from an UTT ADDR buffer starting at the buffer base and ending on the last position of the UTT PTR. BUSY, generated by the speech synthesiser, is tested within the subroutine, allowing correct output timing. Functional enhancements are attainable within the IK byte on-chip program memory space. External additional program and data memory may be added to further expand functional capabilities. Having thus described, in outline, a first embodiment of the invention, a second embodiment will hereinafter be described in detail with reference to Figs. 7 to 12 of the accompanying drawings. Whilst a single-chip microcomputer controller would be employed in production versions of the speech aid hereinafter described to minimise parts cost, the described embodiment uses a Z8θ microprocessor with associated support components, this approach having been dictated by the availability to the inventors of ZδO software development tools. The embodiment hereinafter described comprises four readily identifiable sections which are illustrated in Figs. 7, to 10, namely a microcomputer controller (Fig. 7) an integrated display/keyboard (Fig. 8), a speech synthesiser unit with vocabulary ROMs and audio output components (Fig. 9) and a logic-controlled power supply (Fig. 10). Referring to Fig. 7, the microcomputer cont¬ roller is based on a Z8θ microprocessor 50, and employs a memory-mapped architecture with partially decoded linear select device addressing. Program memory con¬ sists of 2k bytes of PROM space in a single 2716 device 51 residing between hexadecimal addresses 0000 and 07FF in the system memory space. By virtue of its erasable/reprogrammable nature, the 2716 was a logical choice for program development. Read/write memory is provided in the form of two 2114 RAM chips 52 offering Ik bytes of temporary workspace mapped between hexa¬ decimal addresses 3000 and 33FF. Communication with display, keyboard, speech synthesiser and power supply control lines is furnished via two 8255A programmable peripheral interface (PPI) devices 53 each offering three eight-bit I/O ports, A, B and C. These are configured under software control to give four output and two input ports. Mapped in memory space, the PPIs have hexadecimal addresses of 5000 to 5003 and 9000 to 9003. respectively. The former device controls display rows, display columns and various enables through its three ports. The latter strobes keyboard rows and provides speech synthesiser utterance addresses through its A port, whilst its B and C ports, configured as inputs, monitor keyboard column^ and miscellaneous system status bits. System support functions (clock and reset generation and device selection) are performed by the remaining microcomputer components. A discrete crystal-controlled transistor oscillator 54 operating at 1MHz generates the system clock signal. This is buffered by a TTL schmitt inverter 55 before being fed to the microprocessor clock terminal. An inverted version of the same signal is used to synchronise, via a D type flip-flop 56, an asynchronous reset line derived from a schmitt inverter-based power-on reset circuit 57- The synchronised reset signal is fed in inverted and non-inverted forms to the reset terminals of the microprocessor 50 and PPIs 53 respectively. An array of two-input NAND gates 58 each fed by an in¬ verted version of the Z8θ MREQ. (memory request) signal together with levels derived from the top four bits of the address bus provide device enable lines. Following a system reset, the ZδO program counter commences addressing memory from hexadecimal 0000, hence address bit A „ is initially low. This bit is inverted before being routed to the PROM enable NAND gate, thereby allowing program memory access following system reset. The other device-enabling gates are fed directly by address lines A , A ^ and A _ and enable RAM and PPIs 1 and 2 respectively. As is generally the case with linear select systems, only one address selecting bit may be true at any one time, hence A „ aru A._ are considered mutually exclusive in the system software. The RAM enable signal is further gated with RD and WR (read and write) signals by gates 59 before being routed to the 21l4 chip select terminals. This prevents data bus contention during write cycles when the RAM enable signal is true before a write pulse. Reference -should be made to the Zilog Z8θ Technical Manual for a detailed description of Z8θ system timing. Referring now to Fig. 8, the display/keyboard circuit is schematically represented. Physically, this assembly comprises a set of 64 back-illuminated switches 60 (only some of which are shown) realised via membrane switch technology. This allows cells of the flexible translucent keyboard overlays, associated with particular vocabulary repertoires to be selectively high-lighted under software control. The display consists of 64 Tl incandescent lamps 6l (used because of their "white" light output) isolated against spurious back currents by series diodes 62 aiid driven by l6 bipolar transistors 63 arranged as eight row and eight column drivers, the former being configured as emitter followers while the latter operate in the saturating common emitter mode. As with the lamps 6l, only some of transistors 63 are shown in Fig. 8. Both driver sets are arranged to be enabled by high-true signals. A set of eight 4K7 resistors 64 pull up the row driver inputs which are connected to port A of PPI 1 (Fig. 7). Eight 390-Λ. resistors 6 limit drive current sourced by port B of PPI 1 to the bases of the column driver transistors 63. The keyboard may be based on a matrix of 8 8 thin silver contact strips laid down on two stable plastic films. A thin perforated non-conducting membrane separates the films which are arranged so that the conductor sets lie at right angles to each other. The perforations are aligned with the crosspoints of the conductor-carrying films so that external pressure (e.g. from a finger) causes deformation of the film through a perforation and consequential contact closure. Keyboard rows are strobed by port A of PPI 2 (Fig. 7) which, under software control, sequentially pulls row lines .low. Column lines, pulled high by 47 resistoι»s 66 are montored by port B of PPI 2. If a coincidence of row strobe and contact closure occurs, the associated column line is pulled low. Software then decodes the location of the depressed key. The speech synthesiser and control key sub¬ section is shown in Fig. . A Telesensory Systems Inc. S2B mini speech synthesis board 70 is used in the embodiment, this circuit having been modified to include a vocabulary ROM containing a "standard" set of 64 utterances mounted "off-board" as a plug-in module. ■ Different plug-in modules will contain repertoires appropriate to the diverse needs of the speech handicapped. The computer interface to the board 70 comprises six address lines SA 0-5 (to select one of 64 utterances), a "start" line ST, a ROM power down control line VR0M, and a "busy" output. The S2B requires its inputs to be pulled high via resistors and its "busy" output to be level-shi ted and buffered when interfaced to TTL circuitry. Utterance address and ROM power down signals derived from port A, PPI 2 and a "start" signal from port C, PPI 1 are buffered by a 74LS244 device ' 71 and pulled high via a 4K7 resistor package 72 before being fed to the appropriate terminals of the S2B. The "busy" signal from the synthesiser 70 is level- shifted and buffered by a discrete transistor inverter 73, then fed to port C of PPI 2 along with low true "speak" and "clear" control key lines. The analogue output AAS of the S2B is processed by an amplifier 74 and filter 75 before being routed to a loudspeaker 76. Filter characteristics are variable by means of a preset Baxandall circuit to allow intellegibility to be optimised. The basic filter response is bandpass and, with Baxandall flat, has corner frequencies at 400Hz and lKHz. Roll-on and roll-off are at approximately . 6dB per octave. Filter and amplifier are realised via 3l4θ operational amplifier chips. The output level is adjustable by a gain trimmer in the amplifier stage. A complementary emitter follower buffer 77 using germ¬ anium transistors for low base-emitter voltage drop drives the loudspeaker from the filter output. A red/green light emitting diode (LED) indicator 78, driven by a pair of TTL inverters 79 enabled by signals from port C of PPI 1 is employed to show system status. Typically green will be lit to show the normal "on" state. Red might indicate low battery conditions. In order to meet certain special functional requirements of the speech aid, the power supply (Fig. 10) incorporates several unusual features. It is required that the aid be portable and independent of external power sources, hence internal batteries are dictated. Most internal circuitry requires a +5 volt supply, hence three 2-volt Cyclon accumulators 8θ were chosen for the power source. These 2.5 Ah devices yield a series EMF of 6 volts, allowing an accompanying regulating circuit only a one volt drop. In addition it was desired that a low battery condition be signalled to the microcomputer to allow an orderly automatic shut¬ down procedure. Further, a requirement for toggle on/ off action and automatic time-out in standby mode was specified. Finally the S2B speech synthesiser requires a minus 10 volt rail which must be derived from the 6 volt power source. The requirement of low regulator dropout voltage dictated a germanium saturable series pass element 8l. This transistor is driven by the collector current of one side of a long-tailed pair 82 which operates as a comparator between a zener derived reference potential and a proportion of the output voltage. Emitter current for the long-tailed pair 82 is sunk by a resistor 83 n series with a transistor switch 84. When the transistor 84 is disabled, base current to the series pass tran¬ sistor 8l is cut off and the regulator output falls to zero. A keep-alive current is fed to the reference zener 85 under these conditions. This facilitates ord¬ erly power-up behaviour. A PNP transistor 86 with base- emitter connected via a current limiting resistor 87 across the series pass transistor 8l monitors the input- output differential voltage and produces, via a CMOS schmitt trigger gate 88 , a "battery low" logic signal which is routed to port C of PPI 2. Under powered down conditions the regulator draws less than one milliamp, and hence may be permanently connected to the six volt supply. • The base of the long-tailed pair emitter current switch transistor 84 is fed via a current limiting resistor 89 from a set/reset flip-flop 0 configured 1 T(T - using CMOS schmitt NAND gates, permanently powered from the six volt supply. Flip-flop 0 may be triggered "on" by the momentary closure of the "on/ off" key switch 91. A differentiating network 92 between the switch and gate ensures a short (10 microsecond) trigger pulse. The set/reset flip-flop 90 is triggered "off" by a high to low transition of a line from port C of PPI 1. Under conditions of low battery voltage,- a "lock-out" circuit 93 prevents the flip-flop 90 from adopting a stable "on" state. This is achieved by resetting the flip-flop 90 with a suitably delayed version of the "battery low" logic signal. Automatic power-down on low battery voltage is disabled after a few milliseconds by a delayed output from the flip-flop 90 derived by CR network 94. A ter this initial automatic power-down time "window", only a logic signal from the microcomputer can switch off the system. To this end an output (low true) is derived from the "on/off" control key 91 and routed to port C of PPI 2, thereby enabling the microcomputer to detect when the user wishes to power-down. In order to cater for the -10 volt rail requirements of the S2B, a flyback type converter is included in the power supply sub-system. A 1:1 ferrite pulse transformer 95 is driven by a transistor 96 in series with a current sensing resistor 97 from the six volt supply. Transformer primary current is monitored by the inverting input of a 3l4θ operational amplifier 98 c-onfigured as a schmitt trigger with threshold varied by feedback from the transformer secondary circuit. Two paths provide both AC positive feedback ensuring high switching efficiency, and negative DC feedback regulating the output voltage. Secondary current is rectified and smoothed to form the minus 10 volt output. Logic con- trolled on/off switching is effected by virtue of the OMP power supply to operational amplifier 98 being derived from the +5 volt rail. When this is disabled, no base current flows in the switching .transistor 96, hence no current is drawn from the six volt supply. Having thus described the construction and organization of the second embodiment, reference may now be had to Fig. 12 which is a software flowchart of the basic system function together with the following functional description of the machine operation. On power-up (depression of ON/OFF key) LED flashes red during settling time and until key is released, then lights green to indicate "ready" state. If battery voltage is initially low, power-up is inhibited by hardware. To enter an utterance or string of utterances, display areas are pressed in the order that utterances are required. As areas are pressed . they back-illuminate to " show current store contents. Pressing the . SPEAK key allows the stored utt- erance string to be verbally output in the order of entry. As each utterance is made the associated display area blanks. At the end of the string all previously selected display areas are re-illuminated. Pressing the CLEAR key during any user entry phase clears the utterance store and blanks the display. Entering an utterance already stored clears that utterance from memory and blanks the associated display area. If more than l6 utterances are entered, LED flashes red/green and further entries are ignored; control key functions continue to operate normally. If battery volts drop below the "battery low" threshold during operation and the machine is speaking, the LED displays red and the machine automatically powers-down after the current utterance is spoken. Under standby conditions, low battery voltage is indicated by red LED illumination for 5 seconds during which time all control and entry functions except ON/ OFF are locked out. At the end of the time-out period automatic power-down is invoked. If the machine is left "on" for greater than 10 minutes without any entries being made, the LED flashes green for 10 seconds to warn of incipient power-down. Any entries made during this time restore normal operation. If no entry is made, the machine powers itself down. There follows appended hereto a complete software listing in respect of the operations and external and internal control functions in respect of the embodiment abovedescribed with reference to Figs. 7 to 12 of the accompanying drawings. Whilst there have thus been described two embodiments of the invention, it will be well apprec¬ iated by those possessed of appropriate skills that many variations, alterations and modi ications, could be made without departure from the spirit and scope of the invention. The foregoing is therefore intended to be read as exemplifying the invention and not in a limitative sense. EQUATES: Addresses OΠΓD * 0056 ST TP! εou 33FFH :τop- ΠF STACK (5003) 0057 PPIIC: εnu 5003H ;PPI l CTRL REΓ; (9003) 00Ξ8 ι P 2C: εαu 9OO:JH :PPT 2 CTR Γ.FG < iOU(I) 0059 ROWDP: εαu 501)OH ;PPT l pπi A <(i/p) <suoι • UOώO COLDf: εnu 5001H ;PPT \ PORT D (OVP) (sou... 00Λ3 F-NAE-S: FΠU SOn-.'H ;veτ 1 PORT C <f)/P> <9ll<l0> 0062 UTTΛO: • εnu 900OH ;PPI 2 POFv-r A ( Q/t-1 (90U0) 00*3 ROW Y: EC-ill 9000H * (9001) ϋOA COLKY: εαu 9001H -iPPl 2 PORT B (I/P) \ (9002) 0065 MISCI: EQU 002M ;PPI 2 PORT C <I/P) Goriβtants (0080) 0069 co i: εαu 80H ;PPI l CONFIGURATION CODE (008B) 0070 COM2: εnu 3BH f PI 2 CONFIGURATION CODE <0070) . 0071 CKEY: εαu 70H ;CONTROL KEY BITS (0010) 0072 SP K: εαu 10H fSPEAK KEY CODE <0020> 0073 CLRKi εαu 20H JCLEAR KEY CODE <00-*?Q) 0074 PWRK: εαu 40H .POWER .KEY CODE (0001) 0075 BUSY: εαu 01H ;SYNTH BUSY BIT (0002) 0070 BLOW: εαu O.'H iBATTERY LOW BIT <0001) 0077 STRT: εαu 01H SYNTH START BIT (0002) 0078 POFF: • εαu 02H JPOWER OFF BIT <Q0*<*0> 0079 VROM: εαu -10H ;SYNTH ROM PWR DOWN BTT <0010) 0080 GRNL: EQU 10H JGREEN LED ENAB (0020) 0081 REDL: εαu 20H .RED LED ENAB (0030) 00R2 LEDS: εαu 30H JBOTH LEDS (0001) 0083 LBAT: εαu 01H ;STAT BIT - BATT LCiW (0013) 008**. DLCN: εαu 19D DELAY CONSTANT FOR _H-3 UNIT (000A) 008Ξ DEED: εαu • 10D flOMS DELAY (0032) 0086 PAUS: εαu 50D ;S0MS DELAY <00FA) 0087 FUSH: εαu 2500 5250MS DELAY (0064) 0088 TIMO: εαu 100O »TIME-OUT LOOP CONST (000C) 0089 SCTL: εσu 12D ;SCAN COUNTER LIM 1 (OOlθ) 0090 SCTF: εnu 20D ;SCAN COUNTER LIM 2 (0010) 0091 STRS: εαu 10H JSTORE SIZE (0007) 0092 LOOM: εαu 07H ;LOW OCTAL DTGIT MASK <003Ω) 0093 HIDM: εαu 30H .HIGH OCTAL DIGIT MASK (003C) 0091 STOP: εαu AOD fSTOP* UTTR ADDR (002F) U095 PLSE: εαu -".7D .'PLEASE* UTTR ADDR <002S) 0096 CLER: εαu 370 fCLEAR' UTTR ADDR ζOOOO) 0099 ORG oonoH :START AOOR OF C RL T.O PRCM MΛ N BODY OF SYSTEM 0000 31FF33 0106 SPATO: LD SP.STKTP i ΪHXT STACK PTR 0003 CDAB00 • 0107 CALL INSYS . INTT sγsτει-1 01)06 CDP.ntlO 0108 KSCAN: CALL κε γ so ; WATT FUR USER I/P OOUV 3U1R 0109 JR NCCTRLK 00OB CDβsni 0110 CALL CHSTO . NEW ENTRY ■ > OOUE 38IJC 0111 JR CrDεLEN- 0010 CD9C01 0112 CALL ENCNT ;EXCESS ENTRIES ? 0013 3Q0C 0113 JR C»ENLMT 0O15 71 0114 _, LD (HL)-C ;SAVE FW ENTRY 0016 23 0115 INC HL POINT TO NEXT LOC 0017 CDB901 0116 Rεois: CALL UPDIS ;UPDATE DISPLAY 001A ιs A 0li7 JR KSCAN 001C CDD001 0118 DELEN: CALL DLSTO JDELεTE ENTRY 001F 18F6 0119 JR REDIS 0021 CUε401 0120 ENLMT: CALL FLDRG JFLASH RED/GREEN 0024 18E0 0121 * JR KSCAN 0026 3E10 0122 CTRLK: LD AfSPKK 0028 Al 0123 AND C 5SPEAK EY ? 0029 2021 0124 JR N2.CLKCH 002B 110030 0125 LD DE-.STBAS ;STORE BASF ADDR oo2 1A 0126 UTTLP: LD A-(DE> ?C T ADDRESΞFD ITεM * 002F 4F 0127 LD C.A 0030 CD37Q2 0128 CALL SPEAK UTTER ADDRFF.ΞFD ITEM 0033 B7 0129 OR A .SεT ERASE FLAG 0034 CD6B02 0130 CALL DTSPL " JBLANK DTSP AREA 0037 CD6B01 0131 CALL EATCH ;cnεcκ BATTERY 003A 13 0132 INC DE 5POINT TO NEXT ITEM 003B B7 0133 OR A ;Rεsετ CARRY 003C E5 0134 PUSH HL 003D ED52 0135 SBC HL.DE ;FINISHED UTT STRING ? 0040 F22ε00 0137 JP P-UTTLP 0043 3A1730 0138 LD A,(STATE) ;GET STAT BYTE 0046 εόoi 0139 AND LP-AT ;LOW BATTERY RECORDED 0040 2ooε 0J40 JR NZ.PDOWN 004A iscε 0141 JR REDIS 004C 3E20 0142 CLKCH: LD AtCLRK 004E Al 0143 AND C JCLEAR KEY ? 004F 2007 0144 JR NZ.PDOWN 0051 210030 0145 LD HL.STBAS ;CLEAR STORE 0054 36FF 0146 LD (HL).OFFH .INHIBIT FLAG 0056 18BF 0147 JR REDIS 0058 3A1230 0148 PDOMN: LD A.(ENAST) 005B 47 0149 LD BrA 005C 0E02 0150 LD C.POFF 005E Bl 0151 OR C 0O5F 320250 0152 LD (ENABS)τ JSET OFF BIT 0062 47 0153 LD B.A 0063 79 0154 LD A.C 0064 2F nιr. C:PL OOΛ:; ΛU 0156 AND • B Oil .A 320250 . ϋir.7 LD (ENABS).A ;Vπur R nπ 006V JI-LD in5? JR UΠUN _ Q? fPI SUBROUTINES INSYS Con _ φ ipes PPIs » -sets w*» αυiesceπt ou p states . Initi al ises store loca ion--; -. Ensures speech swrvthos iser is in ouio«-;e«» t tat.e. Il l' Mtiir-ates red LED whi lst ON/OFF Key is active? l i shts 3reer- UJIHΓ- rt»l < ** a-5P<3 * No parameters passed * Register s+.3tβs not prβsprveci. 006B 3EB0 0177 INSYS: LD A.CON1 OOόD 320350 0178 LD (PPIIC).A .'CONFIGURE PPI 1 0070 3EQB 0179 LD A»C0 2 0072 320390 0190 LD (PPI20.A CONFIGURE PPI 2 007<4 320250 0132 LD (ENAE.S)--A 5 DEACTIVATE ENABLES 0079 320090 01S3 LD (UTTAD)rA ;ZERO UTT ADDR 007C 321330 018--J LD (UTTST)»A ;INIT UTT ADDR IMAGε 007F 321730 01S5 LD (STATE:).A :INIT ΞTAT r.γτε 0082 0EFF Q1S6 LD C.OFFH ♦BLANK FLAG αoa"t CD6B02 Q1Q7 CALL DISPL JCLεA DIΞP & IMAGE 00Θ7 CD5A01 01S8 CALL SCNCC ;CLEAR SCAN, CTR 00SA 210030 0189 LD HL.STBAS J OAD STORE PTR 008D 36FF 0190 LD (HL)rOFFH INHIBIT FLAG 008F 110A00 0191 LD DE-.OEED .SETTLING DELAY (10MS) 0092 CDD102 0192 CALL DELAY 0095 3E20 0193 LD A.REDL 0097 3202Ξ0 01 LD (ENAeS)fA JLIGHT RED LED IΞCI) 009E E601 0197 AND BUSY JSYNTH READY ? DYLP 00A3 E6--I 0200 AND PWRK JON/OFF KEY INACTIvε ? 00A5 28F3 0201 JR ZF DYLP 00A7 3E10 0202 LD rGRNL 00A9 320250 0203 LD (ENAE.S)--A SLIGHT GREεN L D 00AC 321230 0204 LD (ENAST).A ;UPDATE εNABLES IMAGE 0AF C9 0205 RET EYSC Scans all (i ludi g control) keys. Exi'ts with keyc-ode in C. Cnrry is set if entrw is froir- is lay panel and rf»-*-_ι--*t i * f from control keys. Battery cortdition is tested art's a scan counter is checked for overflow and incremented on each scan. Power— down routine is entered if time—ou or low battery . conditions are detected. Keycαde par.sed in C. Ca y set for disPlaπ entry, reset for control entry. AF corrupted. ♦ ooεo OS 0223 KEYSC: PUSH DE 0083 CD5A01 0226 CALL SCNCC ΪZERO SCAN CTR ooε-ό CD6B01 0227 KEYLP: :ALL BATCH .BATTERY LOW ? 00B9 3B21 0220 JR C,KYOFL 00BB CD1901 0229 •CALL SCNCT ϊCHECK & NCR SCAN CTR ooεε 3EFE 0230 LD At-OFEH JINXT ROW PATT 1111111: OOCO 0608 0231 LD EW0SH JBITS TO STROBE 00C2 320090 0232 ROWSC: LD <ROWKY> i-A 00C5 3A0190 0233 - LD- A.<COLKY) 00C8 FEFF 023-1 CP 0FFH JANY KEY ACTIVE ? 00CA 2023 0235 JR NZ»COLSC OOCC 07 * 0230 * RLCA ΪNEXT ROW PATTERN OOCO 10F3 0237 DJNZ ROWSC 0OCF 3A02 0 0238 LD Af<MISCI) Q0D2 E670 0239 AND CKEY . .CTRL KEYS ACTIVE ? 00D-1 FE70 0210 CP CKEY 00D6 2SDE 02*11 JR ZtKEYLP ααos -IF 02-12 LD C»A 00D9 B7 02*13 OR A JRESεT CARRY 00DA εi 021-1 KEYSX: POP HL .RECOVER ORIGINAL BC 00DB • M 0215 LD EirH ;κεsτoRε & OQDF 113200 02-19 YOFL: LD DE»PAUS J5DMS DELAY ooε2 066*1 0250 LD B»TIHO JLOAD TIHE-OUT 00E-1 3A0290 0251 YOFC: LD A.(MISCI) 00E7 E6-10 0252 AND PWRK ;ρowεκ « γ ACTivε ? ooε9 CAΞ800 0253 P ZtPDOWN ooεc CDD102 025*1 CALL DELAY ooεF 10F3 0255 DJNZ KYOFC 00F1 C35S00 0256 P PDOWN Q0F-1 6F 0257 COLSC: LD L»A fSΛVE COL ΪCΛLC ROW OFFSET scALε JSAV WEIGHTED ROW 00FC 110Λ00 026*1 LD 0ε»0FBD »DENOUNCE DELAY tlOM^) QtlFF 0)0102 0265 CO CHJ CALL ' DELAY 0102 :.Λ0190 n' 6 LD A-.CCOLKY) 01or, M> 0767 CP L ;KEY STILL ACrivc ? 01UΛ 2UF7 l)?60 JR Z.COUCH oion 70 0269 LD A.L JRεCπ'JE COL UIflV n/.ιjfl 0270 LD C>0OH 0308 OF 0271 COUCS: RtfCA SHIFT DO M 010C 3802 0272 JR CCOLΛD oioε 1UFΘ 0273 D.JNZ cm cs 0110 F 0271 COLAD: 10 Π.A ;CALC OIL OFFSET 011-1 81 0277 ADD H JFC.RM KCY ADDR 0115 ■ IF 0278 LD C»A Ollά 37 0279 • SCF 0117 1SC1 02311 JR KEYS* - 2% - SCNCT Tests o ri rιcrc-flι rit«i a t rep h_ιto r-oι * r>t««r in ιtιo«*n v. MSB " is πs sajr-st a constant and if «_renter» low hwt.β is e te against a second constant * If low ' fr-πte is areatpr. prosram control is trans erred to j»ouer-rioun seoiencr.. If low byte is less than second corι--.tPint» 3r*-»F*n LED is fln-_l.ed arid thr» countPr lricrp p t.f . If op w e is less than first conctsnt cαi.-nter is ιr*crι-.π*pmtc**d- Subroutine is p.ritpd aftpr iricren*»ntiri * _. Nα parameters passed * Nα registers corrupted. 0119 F5 0299 SCNCT: PUSH AF 011A C5 0300 PUSH BC 011D D5 0301 PUSH DE one E5 0302 PUSH HL 011D 211430 0303 LD HLFSCNTR ; POINT TO hse OF CTR 0120 3EDC 0304 LD A SCTL 0122 BE 0305 CP <H1_) JCNT > LIM 1 ? 0123 23 0300 INC - HL 0124 23 0307 INC HL ;POINT TO LSB OF CTR 0125 FA3 01 0308 JP M.SCNTO 0128 0603 0309 SCNCV: " LD B.03H FCNTR BYTE NO 012A 0EO1 0310 LD CFOIH JINΠR VALUE 012C 7E 0311 SCNIN: LD A»<HL) JGET BYTE 012D 81 0312 ADO AFC . ;INCR rr . .012E 77 0313 LD <HL)»A ;REPLACE IT 012F 3003 0314 JR NCFSCNEX 0131 2B 0315 DEC HL 0132 10F8 0316 DJNZ SCNIN 0134 El 0317 SCNEX: OP HL 0135 Dl 0318 POP DE • 0136 CI 0319 POP EC 0137 Fl 0320 POP AF 0138 C9 0321 RET 0139 3E14 0322 SCNTO: LD A»SCTF 013B BE 0323 CP <HL) JCNT - LTM 2 ? 013C CA58 0 0324 JP ZFPDOWN 013F 11FAO0 0325 LD DEFFLΞH JFLAΞH DELAY C250HS> 0142 3E30 0326 LD LEDS 0144 2F 0327 CPU ; INVERT LED CTRL 0146 3Λ1230 0329 LD AF<ENAST) ) A ;LEDS OFF ) A ;LED ON O PI SCNCC Clears memory-based scan counter. No parameters passed * No reaisters corrupted. 01SA • F5 0349 SCNCC: PUΓ.H AF 01SB CΞ 0350 PUSH ec 015C E5 0351 PUSH HL 01ΞD 0603 0352- LD BF03H JCNTR BYTE NO 01ΞF 211430 0353 LD HLFSCNTR 0162 AF 0354 . XOR A 0163 77 0355 SCCLP: LD <HL)FA {ZERO BYTE 0164 23 0356 INC HL 0165 10FC 0357 DJNZ SCCLP 0167 El 0358 POP HL 0168 CI 0359 OP BC 0169 Fl 0360 OP AF OlόA C9 0361 RET BATCH TPβts for battery lou condition, ϊf found* e::its uith carry set* red LED illuminated and LBAT bit set in status byte. Carry set if battery low. AF corrupted * 016B E5 0374 BATCH: PUSH HL 016C 3A0290 0375 LD AF(MISCI) 016F E602 0376 AND BLOW .BATTERY LOW ? 0171 2810 0377 JR Z*BATEX 0173 3E01 037S LD A*LBAT 0175 211730 0379 LD . HLFSTATB .'POINT TO STΛT C.YTE 0178 B6 0380 OR AF<HL) ;SET LOW BAT BIT 0179 77 0381 LD <HL)FA ! REPLACE STAT RYTE 017A 3E20 0382 LD ArREDL 017C 320250 0383 LD (ENARSI-A ;LIGHT RED LFD 017F 321230 0384 LD <ENAST)*A UPDATE ENABLES IMA(_C 0182 37 0335 SCF 0183 El 0306 BATEX: POP HL 0184 C9 0387 RET CHSTO Tests if eritry passe in C already exists in- tare. If it does* carry is set and the store location is passed in DE. Carry set if not new eritry* DE points to existing entry. AF corrupted. 0185 C5 04U0 CHSTO: PUSH EC 0186 E5 0401 PUSH' HL 0107 79 0402 LD A*C 0188 210030 0403 LD HI..STBAS ϊPOINT TO STORE RASE 0188 OtlOOO 0404 . LD ECFSTRS JSTORE SIZE 018E EDB1 0405 CPIR ϊSEARCH STORE 0190 2804 0406 JR ZFINSTO 0192 87 0407 OR A ESET CARRY 0193 El 0408 CHSTX: POP HL - 0194 CI 0409 POP EC 0195 C9 0410 RET 0196 37 0411 NSTO: SCF 0197 2B 0412 DEC Ht_ 0198 E5 0413 • PUSH HL ΪXFER LOC 0199 Dl 0414 POP DE ; 019A 18F7 0415 JR CHSTX ENCNT Checks if excess entries have been made. Carry set if excess. AF " corrupted. 019C D5 0427 ENCNT: PUSH DE 019D E5 0428 PUSH HL 019E 111000 0429 LD DEFSTRS ;STORE SIZE 01A1 210030 0430 LD HLFSTBAS . ?STORE BASE 01A4 19 0431 ADD HLFDE ;CALC STORE TOP 01A5 E5 0432 PUSH HL JXFER STORE TOP 01A6 Dl 0433 POP DE F 01A7 El 0434 POP HL ESTORE STORE PTR 01AS E5 0435 PUSH HL JSΛυε IT AΠΛJM 01A9 B7 0436 OR A JRESET CARRY 01AA IB 0437 * DEC DE CORRECT STORE TOP 01AB EB 0438 EX DE.HL 01AC 07 0439 OR A DE EXCESS ENTRY ? NCNR 01l:Λ ■ 17 0446 EHCN : sr:r Oil-/ IOKA 0447 R ENCNX I B'OTS Mi-dϋ s Hi -r.i- ' lav. from πritrv* .turp. Dior-lay is up a e tn on« * . ' location t'«»fιjrπ HL content?.. No parameters passed * No rtf-a isters corrup t «»d. 01E-9 F5 0460 UPD S: PUSH AF 01BA 05 0461 PUSH DE 0168 E5 0462 PUSH HL 01BC E5 0463 PUSH HL JXFER PTR 01ED Dl 0464 . POP DE ; • 01BE 210030 0465 LD HLFSTBAS 01C1 4E 0466 UPDAR: LD CF* HL> . ;GET ITEM 01C2 37 0467 SCF ;ADDITIVE DI5P FLAG 01C3 CD6B02 0468 CALL DISPL 01C6 23 0469 INC HL »POINT TO NEXT ITEM 01C7 B7 0470 OR A ESET CARRY 01C8 ED52 0471 SBC HLFDE ;DONE ALL ? 01CA 20F5 0472 JR NZFUPDAR 01CC El 0473 POP HL 01CD Dl 0474 POP DE DLSTO Deletes entry pointed to by DE from store and re— huf les store * Pointer in HL repositioned to account for deletion. DE carries location of entry for deletioriF HL carries current store pointe • No registers corrupted. 01D0 F5 0491 DLSTO: PUSH AF 01D1 C5 0492 PUSH BC 01D2 D5 0493 PUSH DE 01D3 E5 0494 PUSH HL 01D4 67 0495 OR A JRESET CARRY 01D5 ED52 0496 sεc HLFDE -CALC NO OF SHUFFL. S 01D7 E5 0497 PUSH HL fXFtR THEM ; ;XFER LOC ; ;POINT TO SOURCC LΠ .SHUFFLE .RECOVER PTR ;ADJUST IT 01E3 cy 0500 RET FLDRG Flashes LED altorn-->te red/ϊlreen until e ession of an*, k y is sensed * Spas, "stop please clear* before flashing LED * No parameters passed. No re≤iste s corrupted * 01E4 F5 0521 FLDRG: PUSH AF 01E5 C5 0522 PUSH BC 01E6 D5 0523 PUSH DE 01E7 11FA00 0524 LD DErFLSH JSET 250MS DELAY 01EA 0E3C 0525 LD CFSTOP "STOP* 01EC CD3702 0526 CALL SPEAK 01EF 0E2F 0527 LD CFPLΞE J*PLEASE* 01F1 CD3702 0528 CALL SPEAK 01F4 0E25 0529 LD CrCLER ;'CLEAR* 01F6 CD3702 0530 CALL SPEAK 01F9 3E20 0531 FLDLP: LD AFREDL 01FB 320250 0532 LD <ENABS> A ..LIGHT RED LED 01FE CDD102 0533 CALL DELAY- 0201 CD1FQ2 0534 CALL ANYKY ;ANY KEY ACTIVE ? 0204 380D 0535 JR CFFLDRX 0206 3E10 - 0536 LD AFGRNL 0208 320250 0537 LD <εNAE:S).A .LIGHT GREEN LED 020B CDD102 0538 CALL DELAY 020E CD1F02 0539 CALL ANYKY 0211 30E6 0540 JR NCFFLDLP 0213 3E1Q 0541 FLDRX: LD A GRNL 0215 320250 0542 LD - CENABSJFA ;LIGHT GREEN LED 0210 321230 0543 LD (ENAST)FA .UPDATE ENABLεS IMAGE 021B Dl 0544 POP DE 021C CI 0545 POP EC 021D Fl 0546 POP AF 021E C9 0547 RET ANYKY Ins p ects all key states. Exits uith carry set if ana k.ea is active . AF corrupted 021F ΛF 0559 ANYKY: XOR A 0220 320090 0560 LD ROWKYJFA STROBE KEYB ROWS 0223 3A0190 0561 LD AF<COLKY) 0226 FEFF 0562 CP OFFH εYB ENTRY ? 0228 200B 0563 JR NZF FS 022A 3A0290 0564 LD A»<MISCI) 022D EA70 0565 AND t_κεγ JCTRL KEY ENTRY ? 027F FF.70 0566 CP CKEY 0231 7002 0567 JR . NZFANYFS 0233 I:/ 0560 ΠR A JRFSET CΛF-.UY ! */ 05 9 KfTT 023:. :ι/ 0570 Λ..TF3: r:cr 0236 C9 0571 RET SPEAK Utterft item addressed bv» contents of C * Exits uithout inak.ins utterΛncr. if C contains FrH. Enter uith C cuntairiina utterance address * No reϋ-sters corrupted. 0237 F5 0584 SPE :AK: PUSH AF 0238 C5 0585 PUSH BC 0239 3EFF 0536 LD A OFFH 023C: F:9 0587 CP C ;INHIBIT ? 023C 282A 0588 JR ZFSPKEX U23E 3A1230 0589 LD AF(ENAST) 0241 0601 0590 LD BFSTRT 0243 B0 0591 OR B .SET START BIT 0244 320250 0592 LD <ENABS>FA 0247 321230 0593 LD <ENAST)FA ;UPDATE ENABLES IMAGE 024A 3E40 0594 LD A.υROM 024C Bl 0595 OR c .SET SYNTH ROM PWR BI" 024D 320090 0596 LD (UTTAD. »A ;SEND UTTR ADDR 0251 2F 0598 CPL JCOMPL START BIT 0252 47 0599 LD B.A 0253 3A1230 0600 LD AF<ENAST) 0256 AO 0601 AND B ESET START BIT 0257 320250 0602 LD (E ABS) FA 025A 321230 0603 LD (ENASTJ A 025D 3A0290 0604 SPKLP: LD A.<MISCI) 02.60 E601 0605 AND • BUSY ;STILL TALKING . 0262 20F9 0606 JR NZ SPKLP 0264 AF 0607 XOR A 0265 320090 0608 LD (UTTAO. A ;RST SYNTH RUM PUR BIT 0208 CI 0609 sPKεx: POP BC 0269 Fl 0610 POP AF 026A C9 0611 RET OISPL Displays or blanks cell addreτ.ced by utterance a«1drt*ss* pas e in C. If carry is set on entrv. th isplay is additivela up ated* as are ima*ie locations COLST and ROUST. If carrv is not sell tht* is p lay and πι *-F> locations arc subtr ct-vela updated. £r.t_priri«J thp routine with FFH in C causes '.it-condi ional blank g of tht? entire displav.. Entt-y uith C containina cell or blank flaβ and carrv" sft to additivela uρdat.->» reset to sυbtractively update. No registers corrupted. * 026E: 05 0629 DISPU: PUSH DE 026C C3 0630 PUSH - EC 026D F5 0631 PUSH AF {SAVE FLAGS 026F FEFF 0633 CP 0FFH 7BLANK FLAG ? 0271 28-4*4 063*4 JR Z BLANK 0273 ε60 0635 AND LOOM .MASK FUR LO ϋ÷IGIT 0275 CDC602 0636 CALL DECOD DECODE COL A13DR . 0278 Fl 0637 PDF- AF JREΞTΠRE FLAGS 0279 F5 0638 - PUSH AF . SAVE AGAIN 027A 300C. 0639 JR NC COLOF 027C 3A1130 06*10 LD A»,(COLST) 027F E2 06-41 OS D ;UPDATE COL 0280 321130 0-6-42 CLDIS: LD <COLST ) rA UPDATE COL IMAGE 02S3 320150 06*43 LD (COI.DP) rA JSEND TO DISP 0286 1809 06.4-4 JR ROWDC Jl'S COMPL 028B 3A1130 06-48 LD A» (COLST) 028E A2 06*49 AND D »UPDATE COL 028F ιsεF 0650 JR CLDIS ' 0291 79 0651 ROWDC: LD AFC 0292 E638 0652 AND HIDM .MASK FOR HI DIGIT 029-4 OF 0653 RRCA .SHIFT DOWN 0295 OF 065*4 RRCA 0296 OF 0655 RRCA 0297 CDC 02 0656 CALL DECOD * JDECODE ROW ADDR 029A Fl 0657 POP AF ; sτπRε FLAGS 029£: F5 0658 PUSH AF JΞAwε AGAIN 029C* 300C 0659 JR NC ROWOF 029E 3A1030 0660 LD A ( ROUST) 02A1 B2 0661 OR D .'UPDATE ROW 02A2 321030 0662 RWDIS: LD <R0W3T) FA JUPDATE ROW IMAGE 02A5 320050 0663 LD (ROWDP) A . SEND TO DISP 02A8 1809 066*4 JR DISPX 02AA 7A 0665 ROWOF: LD AFD 02AD 2F 0666 CPL f __ OA-IPI U2S8 320150 0ώ77 LD (COLDPJ-A ϋ2B£ 321030 0678 LD * <ROWST>-*A 02C1 32onso 0079 LD (ROWDP)r 02C1 1SED α_.ao JR D2SJPX 02Cό 17 oόai DECOD: LD 8.A Q2C7 lώOi 0ώ82 LD D.01H 02C9 AF 0083 XOR A OZCA B8 008-τ CDQWN: CP 8 02CB C8 OόSS RET 2 02CC 03 008-6 DEC B 02CD CB22 Qό37 . SLA D 02CF 18F9 0688 JR CDQWN . DELAY Produces elay with value appro.si.riate. ly eαual to contents of DE times milliseconds . Error about l _ at l Oπis . Eritry with DE containing reouired elay in mil liseconds. No registers corrupted. S RAM STORE LOCATIONS (3000) 0721 ORG 3000H .START OF RAM AREA 3000 (0010) 0723 sτε.Ac: DΞ 10H jENTRY STORE 3010 (ϋ00_) 072*1 ROWST: DS 01H DISP ROW THΛGΓ 3011 (0(1til) 0725 CDLS7: DS 03H ;01SP CUL 3MAGK 3012 tαuoi. 072ώ ENAS1 : OS 01H ;E ' NΛΓ:I.ES 3MACE 3013 <(1(101 > 0727 UTIST: DS 01H ;UTTR AODR IMAGE 303*9 (0003) 0728 SCNTR: DS 03H ; EY SCAN CTK- 3017 COUUl) 0729 STATf:: DS 01H ;STATUS BYTE 3018 (0000) 0733 END SPA; Errors 0 Ranse Count 0 "

Claims: CLAIMS : 1. A speech synthesis device unable by the vocally handicapped to provide a speech facility comprisin :- a housing incorporating a selector panel and associated selector controls enabling identification by a user of one or more of a plurality of available selectable ^speech, utterances, and indicator means associated Vit said panel for providing an indication of selected ones of said speech utterances; a speech synthesiser circuit in said housing and capable of outputting electrical signals transfor¬ mable into audible speech utterances in response to corresponding inputs thereto; a read only memory associated with said speech synthesiser circuit and having pre-stored therein data to enable said speech synthesiser circuit to output electrical signals representative of a predetermined limited speech vocabulary, said read only memory being a modular unit selectively connectable with and dis- connectable from said speech synthesiser circuit whereby a requisite vocabulary repertoire may be pro¬ vided by means of a plurality of such modular units; and a microcomputer interfaced with said selector panel and associated selector controls and with said speech synthesis circuit, said microcomputer being programmed such that the indentification by a user of a selected speech utterance causes the addressing of corresponding data items stored in said read only memory and the enabling of the speech synthesiser cir¬ cuit to output corresponding electrical signals for transformation into speech utterances corresponding to the user selection. 2. A speech synthesis device as claimed in claim 1 wherein said selector panel comprises a matrix array of selectable cells each having associated indicator means actuable via said micro¬ computer in response to a corresponding user selec¬ tion to illuminate a corresponding location of a translucent overlay bearing graphical representa¬ tions of selectable speech utterances corresponding to data stored in the read only memory, the arrange¬ ment being such that with a plurality of such over¬ lays and a plurality of correspondingly pre-stored read only memories the requisite vocabulary reper¬ toire may be provided. 3. A speech synthesis device as claimed fi claim 2 wherein said selector controls comprise a matrix array of manually operable switches associated with said matrix array of selectable selector panel cells. 4. A speech synthesis device as claimed in claim 3 wherein said matrix array of manually operable switches constitutes the selector panel, the said switch array comprising a plurality of row conductors mounted upon one face of a first flexible membrane, a plurality of column conductors mounted upon an opposed face of a second membrane, a spacer layer interposed between said first and second membranes and having defined therein openings whereat the row conductors traverse the column conductors whereby pressure upon said first membrane in selected areas thereof will cause a selected row conductor to contact a selected column conductor, and driver circuitry associated with said row and column conductors for causing a unique _ signal to be developed at an input port of the micro¬ computer in response to contact of a selected row con- ductor with a selected column conductor consequential to selection by the user of a corresponding cell of the array. 5. A speech synthesis device as claimed in any of the preceding claims wherein said microcomputer includes a read/write memory storage facility, and said selector controls include means enabling a user selectively to -store signals representative of a plurality of serially selected speech utterances to be vocalized in a continuous speech utterance string. 6. . A speech synthesis device as claimed in any of the preceding claims wherein said microcomputer comprises a microprocessor employing a memory-mapped architecture with partially decoded linear select device addressing. 7. A speech synthesis device as claimed in claim 6 wherein said microcomputer comprises a microprocessor, a program memory storage device configured as a prog¬ rammable read only memory (PROM) , a read/write memory storage device configured as a random access memory (RAM), and programmable peripheral interface (PPI) means configured under software control to provide communication between the microprocessor and indicator, selector panel, speech synthesiser and power control lines. 8. A speech synthesis device as claimed in claim 7 wherein the microcomputer comprises a power—on reset circuit for deriving a reset signal synchronised with system clock which is applied to resetterminals of the microprocessor and the PPI means. OMPI 9. A speech synthesis device as claimed in claim 7 or 8 wherein a RAM enable signal from the micro¬ processor is gated with ED and R signals (RD = read and WR = write) before being routed to the RAM so as to prevent data bus contention during write cycles when the RAM enable signal is true be ore a write pulse. 10. A speech synthesis device as claimed in any of claims 6 to 9 wherein said microprocessor is a Zilog Z8θ device. 11. A speech synthesis device as claimed in any of the preceding claims including a software controlled T.attery power supply system arranged to derive a "battery low" logic signal in response to a detected low battery condition, the occurrence of a said "battery low" logic signal being arranged to signal an orderly automatic shut-down procedure by the micro¬ computer. 12. A speech synthesis device as claimed in claim 11 wherein the power supply system comprises a low volt drop saturable pass element in series with the battery for providing a regulated output voltage, the said element being controlled in dependence upon a comparison between a zener-derived reference voltage and the power supply output voltage, and a further element monitors the input-output differential voltage across the said series element for providing said "battery low" logic signal. OMPI 13. A speech synthesis device as claimed in claim 12 wherein a selectively operable on-off switching device is associated with said series pass element for determining the operation thereof to determine the on- off condition of the power supply, and circuitry is provided for feeding a keep-alive current to the reference zener when the power supply is in its off condition for facilitating orderly power-up behaviour. 14. A speech synthesis device as claimed in any of the preceding claims wherein the power supply sub¬ system includes a converter circuit comprising a 1:1 ferrite pulse transformer driven by a transistor in series with a current sensing resistor from a battery supply rail, the transformer primary current being monitored by an operational amplifier configured as a schmitt trigger with threshold varied by feedback from the transformer secondary circuit via paths providing both AC positive feedback and negative DC feedback, and the secodnary current being rectified and smoothed for providing the requisite output. 15. A speech synthesis device as claimed in any of the preceding claims wherein the speech synthesiser circuit provides an analogue output which is processed by a filter and amplifier before being routed to an acoustic output transducer, and wherein filter charac¬ teristics are variable by means of a Baxandall circuit to allow the intelligibility of the speech utterances to be optimised.

Inventors: ALBES Z, JONES N, WATSON J
Applicants: ALBES Z, JONES N, WATSON J
Application year: 1981
Main classification: G10L1
IPC codes: G09B21, G10L13