LEADLESS INTEGRATED CIRCUIT PACKAGE AND CONNECTOR RECEPTACLE THEREFOR

Abstract: The invention is concerned with the problem of providing connections to leadless integrated circuit packages. A connector assembly (10) for connection to a computer backpanel (14) or the like includes a leadless integrated circuit package (16) and a connector receptacle (20) for receiving the leadless package (16). The leadless package (16) has two insulating layers (60, 62) and outwardly extending conductors (68, 72) formed on each of the two layers (60, 62). The insulating layers (60, 62) have contact coupling edges (70, 74), with the contact coupling edge (70) of one layer (60) extending outwardly of the contact coupling edge (74) of the other layer (62). Rows of contacts (40, 42) in the receptacle (20) make electrical contact with the conductors (68, 72) on the leadless package at the contact coupling edges (70, 74). The construction enables an increased number of external connections to be made to the chip (12) without a substantial increase in the surface area of the package (16). In a second embodiment, the connector assembly (10a) includes a leadless integrated circuit package (20a) having three insulating layers (60a, 62a, 92a) and outwardly extending conductors (68a, 72a, 90a) formed on each of the three layers (60a, 62a, 92a).

Description: LEADLESS INTEGRATED CIRCUIT PACKAGE AND CONNECTOR RECEPTACLE THEREFOR Technical Field This invention relates to leadless integrated circuit packages of the kind including an integrated circuit chip, and having a first plurality of substan¬ tially coplanar conductors electrically connected to said chip, and projecting in an outward direction from said chip. The invention also relates to connector receptacles for receiving leadless integrated circuit packages of the. kind specified. Background Art A leadless integrated circuit package of the kind specified is known from U.S. Patent No. 3,877,064. Leadless integrated circuit packages are commonly used for mounting integrated circuits on print¬ ed circuit boards, computer backpanels, and the like, and have significant advantages over conventional dual in-line packages (DIP's) and single in-line packages (SIP's) in the manufacture of large electronic systems, such as computers. - If, during the assembly of integrated circuits on a computer backpanel, there is discovered a defect in one of the integrated circuits, the leadless package having the defective integrated circuit is simply removed from its receptacle and replaced with a new package. There is thereby eliminated the problem of removing packages having soldered leads or pins, and the potential for bending or breaking such pins when removed. There is a practical limitation on the number of external connections that can be made to the package and chip, such limitation largely depending on the physical dimensions of the package. A leadless package typically has an insulating substrate or layer and a plurality or set of conductors on the layer extending between connector coupling edges about the periphery of the layer and a center or central location of the package where the integrated circuit chip is supported. These conductors provide electrical connections to the chip, but must be limited in number since each conductor requires a certain amount of surface area on the layer. Advances in integrated circuit technology have resulted in increased circuit densities and, in turn, increased numbers of circuit functions that can be provided on a single integrated circuit chip. How¬ ever, such increases in the number of functions often require additional external electrical connections to - % . . . the chip. It would be possible to increase the number of external connections by increasing the size or sur¬ face area of the package so that more conductors could be provided between the connector coupling edges of the insulating layer and the integrated circuit chip. In¬ creasing the size of the package, however, also increases the amount of area required for each package on a mount¬ ing member such as a printed circuit board or backpanel, and thus eliminates some of the space savings achieved by the increased circuit density of the chip itself. It will thus be appreciated that the known leadless integrated circuit package has the disadvan¬ tage that the circuit density that can be achieved utilizing such packages is unduly restricted. Disclosure of the Invention It is an object of the present invention to provide a leadless integrated circuit package of the kind specified and a connector receptacle therefor wherein the aforementioned disadvantage is alleviated. Therefore, according to the present invention, there is provided a leadless integrated circuit package of the kind specified, characterized by a second plurality of conductors electrically connected to said .._ _ - ., - ^ _ ^ chip and projecting also in an outward direction from said chip, each conductor of said second plurality of conductors being spaced from the plane of said first plurality of conductors in a direction substantially transverse to an outward direction from said chip, whereby said second plurality of conductors provide an increased number of external electrical connections to said chip without a substantial increase in the surface area of said package. According to another aspect of the invention, there is provided an assembly for providing electrical connections between an integrated circuit chip and a mounting member, characterized by a leadless integrated circuit package for supporting said integrated circuit chip, said package including: first and second insulating layers having contact coupling edges, with a contact coupling edge of- one of said first and second insulating layers spaced inwardly from a contact coupling edge of the other of said first and second insulating layers, and conductors on- each of said first and second insula¬ ting layers extending between the contact coupling edge of each of said first and second insulating layers " and the integrated circuit chip, with said conductors ex¬ posed at the contact engaging edges; and an electrical connector receptacle for receiving said leadless inte¬ grated circuit package, said receptacle including: a plurality of electrical pins for making electrical con¬ nections at said mounting member, and a contact connected to each of said pins, each of said contacts positioned so that one of said contacts is coupled with each of said conductors at the contact coupling edge of said. first insulating layer and one of said contacts is coupled with each of said conductors at the contact coupling edge of said second insulating layer. According to yet another aspect of the inven¬ tion, there is provided a connector receptacle for receiving a leadless integrated circuit package accord¬ ing to the last but one of the preceding paragraphs, characterized by a housing forming an outwardly opening chamber for receiving the package; a first, upper ledge formed within the chamber on the side walls of said housing; a second, lower ledge formed within the chamber on the side walls of said housing; first and second rows of contacts located within the chamber for making contact with conductors on the package, said first row of contacts spaced along said first ledge and said second row of contacts spaced along said second ledge; and electrical pins projecting through said housing, each of said pins electrically connected to one of the contacts in said first and second rows of contacts. Brief Description of the Drawings Embodiments of the present invention will now be described by way ,of example with reference to the accompanying drawings, in which: Fig. 1 is an exploded perspective view, with portions broken away, of a connector assembly including a leadless integrated circuit package and shown posi- tioned for being electrically connected to a computer backpanel; Fig. 2 is a transverse sectional view of the leadless integrated circuit package in the assembly of Fig. 1, taken along the line II-II of Fig. 1; Fig. 3 is a fragmentary bottom view of the leadless integrated circuit package of Fig. 2, as seen along the line III-III of Fig. 2; Fig. 4 is an enlarged fragmentary sectional view of the connector assembly of Fig. 1; and Fig. 5 is an enlarged fragmentary sectional view of a connector assembly, illustrating an alterna¬ tive embodiment. Modes for Carrying Out the Invention Turning now to the drawings, there is shown in Fig. 1 a connector assembly 10 for electrically con¬ necting an integrated circuit chip 12 to a computer backpanel 14. The integrated circuit chip 12-is sup¬ ported or mounted, as shown in phantom in Fig. 1., on the underside of a leadless integrated circuit package 16. The package 16 can be removably inserted into a connector receptacle 20 and is held in place in the receptacle 20 by a cover plate 22. The cover plate 22 is secured to the receptacle 20 by conventional means, such as the illustrated screws 24 that pass through holes 26 in the cover plate 22 and are threadedly re- ceived in aligned holes 25 at the four corners of a housing 30 of the receptacle 20. Alternatively, but not shown in the drawings, the cover plate 22 could, as conventional, be hinged to the housing 30 along one side thereof, and have a latch or clip for releasably se- curing the cover plate- 22 to the opposite side of the housing. The actual manner in which the cover plate 22 is secured to the housing 20 is unimportant for purposes of the present invention. As seen in Fig. 1, the housing 30 of the receptacle 20 has four side walls 32 and a bottom wall 34 that define an upwardly and outwardly opening chamber 36 into which the leadless package 16 is placed. The side walls 32 include, within the housing 30 and around ' the chamber 36, an upper ledge 37 and a lower ledge 38. An outer row of resilient electrical contacts 40 (only two of which are shown in Fig, 1) extend through aper¬ tures 41 into the chamber 36 at the upper ledge 37 along each of the side walls 32. Similarly, an inner row of resilient electrical contacts 42 (only two of which are shown in Fig. 1) extend through apertures 43 into the chamber 36 at the lower ledge 38 along each of the side walls 32. As can be seen in the drawings, the contacts 40 are spaced both upwardly and outwardly from the contacts 42. The contacts 40 are electrically con¬ nected to outer rows of pins 48 projecting downwardly from the bottom of housing 30, and the contacts 42 are electrically connected to inner rows of pins 50, spaced inwardly from the outer rows of pins 48 and also pro¬ jecting downwardly from the bottom of the housing 30. The pins 48 and 50 are received in apertures 54 in the backpanel 14 for making electrical connections with circuits or conductors (not shown) at the backpanel. As will be described in greater detail later, when the connector assembly 10 is fully assembled, the leadless package 16 is held firmly between the cover plate 22 and the rows of contacts 40 and 42 in the housing chamber 36. Each of the contacts 40 and 42 will provide an electrical connection between one of the pins 48 and 50 and the leadless. package 16. Referring now to Figs. 2 and 3, there is shown in greater detail the leadless integrated circuit package 16. As can be seen, the leadless package 16 is com¬ prised of an upper insulating layer 60 and a lower insulating layer 62. The lower layer 62 is open at its _ , center and defines, with the underside of the top layer 60, a central open portion or pocket 66 for receiving the integrated circuit chip 12. The integrated circuit chip 12 may be fixed, such as by adhesive, to the under¬ side of the top layer 60 at the pocket 66. A set or plurality of coplanar conductors 68 (illustrated partially in Fig. 3) extend outwardly along the underside of the upper layer 60 from the pocket 66 to contact touching or coupling edges 70 located about the periphery of the upper layer. Likewise, a set or plurality of coplanar conductors 72 (illustrated par- tially in Fig. 3) extend outwardly along the underside of the lower layer 62 from the pocket 66 to contact touching or coupling edges 74 located about the periph¬ ery of the lower layer. The conductors 68 terminate at pads 76 along the contact coupling edges 70 of the upper layer 60 and the conductors 72 terminate at pads 78 along the contact coupling edges 74 of the lower layer 62. The conductors 68 and 72 are electrically connected at the pocket 66 in a conventional fashion, such as by wires 80, to the integrated circuit chip 12. Although, for purposes of simplifying the drawings, the conductors 68 and 72 are shown in Fig. 3 as extending from generally only one side of the pocket 66 to the contact coupling edges, in actual practice the conductors will extend from each side of the pocket 66 to all four edges along the periphery of each of the layers 60 and 62. The conductors 68 and the conductors 72 lie in planes that are essentially separated by the thickness of the lower insulating layer 62. As will become ap¬ parent, the separation of the conductors 68 and the conductors 72 in a direction which is generally per¬ pendicular or transverse to the direction in which .the conductors extend outwardly permits an increase in the number of external connections to the integrated circuit chip 12, without a significant increase- in the surface area of the leadless package 16. As can be seen in Figs. 2 and 3, the upper layer 60 is larger in surface area than the lower layer 62 so that the contact coupling edges 70 of the layer 60 extend beyond and are spaced outwardly from the contact coupling edges 74 of the layer 62. The pads 76 of conductors 68 are exposed at the edges 70 so that they each couple with or touch one of the previously men¬ tioned contacts 40 in the connector receptacle 20. The pads 78 of the conductors 72 are spaced inwardly, as well as downwardly from the pads 76, so that they each couple with or touch one of the previously mentioned contacts 42 in the receptacle 20. The conductors 68 and 72 can be formed on the layers 60 and 62 using a conventional process, such as photoetching. Once the conductors 68 and 72 have been so formed, the layer 62 can be affixed to the layer 60 by, for example, a suitable adhesive or the like. As illustrated in Fig. 4, when the leadless package 16 is secured in the connector receptacle 20, with the screws 24 holding the cover plate 22 firmly at the top of housing 30 of connector receptacle 20, the leadless package 16 is urged against the contacts 40 and 42 along the ledges 37 and 38 on the side walls of housing 30. The contacts 40 and 42 will resiliently deform as needed to accommodate the package 16, with each contact in firm physical and electrical contact with one of the pads 76 and 78 on the package 16. An electrical path is thereby established between each of the pins 48 and 50 and the circuitry on the integrated circuit chip 12 * . It should be apparent from the foregoing description that the number of external electrical connections made to the integrated circuit chip 12 in the leadless " package 16 is significantly greater than the number of external electrical connections in prior leadless packages by virtue of having both the plurality of conductors 68 and the plurality of conductors 72, each plurality of conductors extending outwardly from integrated circuit chip 12 so that each conductor makes electrical contact with one of the contacts 40 and 42 in the connector receptacle 20. Since the conductors 68 on layer 60 lie in a plane that is spaced transversely from the plane in which conductors 72 on layer 62 lie, the amount of surface area that the leadless package 15 occupies is not significantly greater than the surface area of prior packages that have only one plurality or set of conductors. In Fig. 5, there is shown a connector assembly 10a illustrating an alternative embodiment of the present invention. In order to further increase the number of electrical connections made to an integrated circuit chip (not shown) that is mounted in a leadless in¬ tegrated circuit package 16a, the package 16a of the connector assembly 10a is shown as having a set of coplanar conductors 68a, a set of coplanar conductors 72a, and a set of coplanar conductors 90a. The con¬ ductors 68a each are formed on the underside of an upper insulating layer 60a, each extend outwardly from the center of layer 60a, and each terminate at a pad 76a at a contact coupling edge 70a of the layer 60a. The conductors 72a each are formed on the underside of a middle insulating layer 62a, each extend outwardly from the center of layer 62a, and each terminate at a pad 78a at a contact coupling edge 74a of the layer 62a. In the same fashion, conductors 90a are each formed on the underside of a lower insulating layer 92a, each extend outwardly from the center of layer 92a, and each ter¬ minate at a pad 94a at a contact coupling edge 96a of the layer 92a. The contact coupling edge 96a on layer 92a is spaced inwardly and downwardly of contac£ coupling edge 74a on layer 62a. . Likewise, contact coupling edge 74a on layer 62a is spaced downwardly and inwardly of contact coupling edge 70a on layer 60a. As a result, when the leadless package 16a is secured in a connector re¬ ceptacle 20a, the pads 76a, 78a and 94a make firm phy¬ sical and electrical contact with contacts 40a, 42a and 98a within the receptacle 20a. The contacts 40a, 42a and 98a are electrically connected to pins 48a, 50a and 100a, respectively, that project from the bottom of the receptacle 20a. It should be apparent, of course, that al¬ though the embodiment of Fig. 5 shows three sets of coplanar conductors extending outwardly from the in¬ tegrated circuit chip at the center of the leadless package 16a, additional sets of conductors and in¬ sulating layers could be provided to even further in¬ crease the number of external electrical connections to the integrated circuit chip. Although the presently preferred embodiments of the present invention have been described, it will be -£.R_._ understood that within the purview of this invention various changes may be made within the scope of the appended claims.

Claims: CLAIMS : 1. A leadless integrated circuit package (16) including an integrated circuit chip (12), and having a first plurality of substantially coplanar con¬ ductors (68) electrically connected to said chip (12), and projecting in an outward direction from said chip (12), characterized by a second plurality of conductors (72) electrically connected to said chip (12) and pro¬ jecting also in an outward direction from said chip (12), each conductor of said second plurality of con- ductors (72) being spaced from the plane of said first plurality of conductors (68) in a direction substan¬ tially transverse to an outward direction from said chip (12), whereby said second plurality of conductors (72) provide an increased number of external electrical con- nections to said chip without a substantial increase in the surface area of said package (16). 2. A leadless integrated circuit package (16) according to claim 1, characterized by an insulating layer (62) located between said first plural¬ ity of conductors (68) and said second plurality of conductors (72). 3. A leadless integrated circuit package ' (16) according to claim 1, characterized in that said first plurality of conductors (68) are formed on a first insulating layer (60), and wherein said second plurality of conductors (72) are formed on a second insulating layer (62) . 4. A leadless integrated circuit package (16) according to claim 3, characterized in that said package (16) is adapted for insertion into a connector recep¬ tacle (20) having a plurality of contacts (40, 42), and wherein said first plurality of conductors (68) and said 4. ( concluded ) second plurality of conductors (72) terminate at pads (76, 78) distal to said chip (12), said pads (76, 78) being adapted to couple with respective ones of said contacts (40, 42) in said connector receptacle (20). 5. A leadless integrated circuit package (16) according to claim 4, wherein said pads (76) of said first plurality of conductors (68) are spaced further from said chip (12) than said pads (78) of said second plurality of conductors (72). 6. A leadless .integrated circuit package (16) according to claim 1, characterized by: first and second insulating layers (60, 62), said first and second layers (60, 62) being in overlying relation and each having a contact coupling edge (70, 74), with the contact coupling edge (70) of one of said first and second lay¬ ers (60, 62) projecting beyond the -contact coupling edge (74) of the other of said first and second layers (60, 62); said first and second pluralities of conduc- tors (68, 72) being associated respectively with said first and second insulating layers (60, 62), each of said conductors (68, 72) extending from said chip (12) to said contact coupling edge (70, 74) of its associated layer. 7. A leadless integrated circuit package (16) according to claim 6, characterized in that said first insulating layer (60) has an edge (70) overhanging an adjacent edge (74) of- said second insulating layer (62) so that at least portions (76) of said first plurality of conductors (68) are exposed at the overhang¬ ing edge (70) of said first substrate (60). 8. A leadless integrated circuit package (16) according to claim 7, characterized by a third 8 . ( concluded ) plurality of conductors (90a) located on a third in¬ sulating layer (92a) and spaced from said first and said second plurality of conductors (68a, 72a) in a direction generally perpendicular to the direction in which said first and second conductors (68a, 72a) extend outwardly, said third plurality of conductors (90a) extending in an outward direction from said chip (12), and said second substrate (62a) having an edge (74a) overhanging an adjacent edge (96a) of said third substrate (92a) so that at least portions of said second plurality of conductors (72a) are exposed at the overhanging edge (74a) of said second substrate (62a). 9. An assembly (10) for providing electrical connections between an integrated circuit chip (12) and •a mounting member (14), characterized by a leadless integrated circuit package (16) for supporting said integrated circuit chip (12), said package (16) in¬ cluding: first and second insulating layers (60, 62) having contact coupling edges (70, 74), with a contact coupling edge (74) of one of said first and second insulating layers (60, 62) spaced inwardly from a contact coupling edge (70) of the other of said first and second insulating layers (60, 62), and conductors (68, 72) on each of said first and second insulating layers (60, 62) extending between the contact coupling edge of each of said first and second insulating layers (60, 62) and the integrated circuit chip (12), with said conductors (68, 72) exposed at the contact engaging edges (70, 74); and an electrical connector receptacle (20) for receiving said leadless integrated circuit package (16), said receptacle (20) including: a plurality of electrical pins (48, 50) for making electrical connections at said mounting member (14), and a contact (40, 42) connected to each of said pins (48, 50), each of said contacts (40, 42) positioned so that one of said contacts (40, 42) is coupled with each of said conductors (68) at the 9. (concluded) contact coupling edge (70) of said first insulating layer (60) and one of said contacts (42) is coupled with each of said conductors (72) at the contact coupling edge (74) of said second insulating layer (62). 10. A connector receptacle (20) for receiving a leadless integrated circuit package (16) according to any one of claims 1 to 8, characterized by a housing (30) forming an outwardly opening chamber (36) for receiving the package (16); a first, upper ledge (37) formed within the chamber (36) on the side walls (32) of said housin _ (30) ; a second, lower ledge (38) formed within the chamber (36) on the side walls (32) of said housing (30); first and second rows of contacts (40, 42) located within the chamber (36) for making contact with conductors (68, 72) on the package (16), said first row of contacts (40) spaced along said first ledge (37) and said second row of contacts (42) spaced along said second ledge (38); and electrical pins (48, 50) projec- ting through said housing (30), each of said pins (48, 50) electrically connected to one of the contacts in said first and second rows of contacts (40, 42).

Inventors: ZAKHARIYA R
Applicants: NCR CO, NCR CORP
Application year: 1981
Main classification: H01L23
IPC codes: H01L23, H05K7