ADDRESS EXPANDING SYSTEM

Abstract: An address expanding system comprises an instruction register (36) which is coupled to a main memory (20) and which stores an instruction read from said main memory, said instruction including a common address modification field (60) for specifying an index address modification and base address modification and a displacement; a plurality of general registers (42) which are connected through a bus to the instruction register, the contents of one of said general registers being added to a logical address in the index address modification; a plurality of base registers (52) which are coupled throuph the bus to the instruction regis­ ter, the contents of one of said base registers being added to the logical address in the base address modification; base register address generating means (76) which receives a first data from the common address modification field and which produces a second data to specify one of the base registers; and adding means (68, 74) which is coupled to said instruction register, said general registers and said base registers and which adds the contents of said general registers, said base registers and said displacement.

Description: Address expanding system This invention relates to an address expanding system of a computer. Various methods of address modification are known. Fig. 1A shows a format of instruction used in a computer TOSBAC-40 manufactured by Toshiba Corporation, Japan. Fig. 1B shows a format of instruction used in computer systems 360 and 370 manufactured by International Business Machines, Inc., U.S.A. The instruction of Fig. 1A comprises an 8-bit OP field 2 for specifying an operation code (hereinafter called "OP code"), a 4-bit R1 operation field 4 for specifying a first operand, a 4-bit X field 6 for specifying one of index registers and a 16-bit A field 8 for specifying a byte-unit address (64 KB at maximum). In this architecture, a programming can be effected in an addressing space of only 64 KB at maximum. The instruction of Fig. 1B comprises an 8-bit OP field 10 for specifying an OP code, a 4-bit R1 field 12 for specifying a first operand, a 4-bit X field 14 for specifying one of index registers, a 4-bit B field 16 for specifying one of base registers and a 12-bit D field 18 for specifying displacement (byte address) of 4 KB at maximum. In either the computer system 360 or the computer system 370, the index registers comprise 32 bits each, and the base registers comprise 24 bits each. The index modification and the base modification can be performed simultaneously. The main memory of the computer system is constituted by segments of various sizes. The start addresses of these segments are stored in the base registers. The span of the largest segment is 4 KB. (The word "span" means a memory area which can be specified by address value stored in one base register.) The maximum span being 4 KB, it is hard for a programmer to make a program. Suppose at the initial stage of programming a programmer estimates that a desired program is within a memory capacity of 4 KB, and that in the final stage of programming, however, he finds out that the program exceeds the memory capacity of 4 KB. Then, the programmer must use two segments or must change the contents of the base registers at a certain stage of programming. If the contents of the base registers are changed, the resultant program will be complexed, which is the main cause of bug. This invention was made, aiming at eliminating the above-mentioned difficulty in programming. Accordingly an object of the invention is to provide an improved address expanding system. To achieve the object, in an address expanding system of this invention having a main memory, a memory address register which is connected to said main memory through a memory bus and to a source bus and in which an address to access said main memory is latched, and a memory data register which is connected through the memory bus to said main memory and to the source bus and in which data read from said main memory or to be located in the same is latched in accordance with the address latched in said memory address register, the improvement comprises: an instruction register which is coupled to said main memory and stores an instruction read from said main memory, said instruction including a common address modification field for specifying an index address modification, a base address modification and a displacement; a plurality of general registers which are connected through a bus to the instruction register, the contents of one of said general registers being added to a logical address in the index address modification; a plurality of base registers which are coupled through the bus to the instruction register, the contents of one of said base registers being added to a logical address in the base address modification; base register address generating means which receives a first data from the common address modification field and produces a second data for specifying one of the base registers; and adding means which is coupled to said instruction register, said general registers and said base registers and which adds the contents of said general register, said base registers and said displacement. In the address expanding system of this invention, an index register specifying field for specifying index address modification is assigned in a common field of an instruction. And so is a base register specifying field for specifying base address modification. The invention has the following features: (1) The expansion of an address space can be effected. (It can be effected unlimitedly by increasing the number of bits which comprises the base registers.) (2) The maximum capacity of one segment can be broadened. (3) The software which has been used in prior art can be directly used. (4) The range of memory capacity specified by the address value stored in the index register equals to the range of memory capacity specified by an immediate address specifying field A (64 KB). (5) Subtraction can be effected, in which the address value specified in the immediate address specifying field A is subtracted from the address value specified by the contents of the index register. (6) Almost no impact effects the prior art instruction system. (7) A memory management can be effected in segment unit. Other objects and features of the invention will be apparent from the following description taken in connection with the accompanying drawings. Figs. 1A and 1B show formats of instruction used in prior art systems; Fig. 2 shows a block diagram of a data processor to which an address expanding system according to the invention is applied; Fig. 3 shows a format of instruction used in the embodiment of the present invention; Fig. 4 is a block diagram of an embodiment of the invention; and Fig. 5 is a block diagram of another embodiment of the invention. Fig. 2 is a block diagram of a data processor to which an address expanding system according to the invention is applied. As shown in Fig. 2, a main memory 20 is coupled with a memory bus (M-BUS) 22. Between the M-BUS 22 and a source bus (S-BUS) 24 is inserted a memory address register (MAR) 26. The MAR 26 stores an address of the main memory 20. Connected also between the M-BUS 22 and the S-BUS 24 is a memory data register (MDR) 28. The MDR 28 stores data read from the main memory 20 or data to be stored into the main memory 20. The MDR 28 is connected to an instruction buffer bus (IB-BUS). Further provided is an instruction buffer register (IBR) 32 which is connected between the S-BUS 24 and a destination bus (B-BUS) 34 and which is connected also to the IB-BUS 30. An instruction code is loaded from the main memory 20 into the IBR 32 through the M-BUS 22. The code is then loaded from the IBR 32 into an instruction register (IR) 36 via the IB-BUS 30. An instruction decoding unit (IDU) 38 is connected to the IB-BUS 30 for decoding the instruction loaded in the IR 36. A microprogram control unit (MCU) 40 controls the operation of a microprogram in accordance with an instruction from the IDU 38. The IR 36 and the MCU 40 are connected to each other. To the S-BUS 24 there is connected a general register file 42 which comprises 16 registers GRO to GR15. The general registers GRO to GR15 are used as arithmetic registers, data registers, or the like. In the embodiment of Fig. - 2 the general registers GRO to GR15 are used as index registers. To the general register file 42 an arithmetic and logic unit (ALU) 44 is connected. The ALU 44 is connected also to the B-BUS 34 and a quotient register 46. The ALU 44 performs various arithmetic operations and logical operations. The quotient register 46 is connected to the S-BUS 24 for temporarily storing the result of the operation performed by the ALU 44. Connected between the S-BUS 24 and the B-BUS 34 is a program status word register (PSW) 48 which stores interrupt levels or various flags such as a carry flag, a sign flag or a zero flag when a program is executed. Connected also between the S-BUS 24 and the B-BUS 34 is a program counter 50 which stores an address of the instruction to be executed next. Connected also between the S-BUS 24 and the B-BUS 34 is a base register file 52 which comprises eight registers BRO to BR7. Each of these registers BR0 to BR7 stores a base address which specifies the start address of a segment in the main memory 20. Further, between the S-BUS 24 and the B-BUS 34 there is connected a working register 54 which is used as a temporary buffer when microinstructions of the microprogram are executed. Fig. 3 shows a format of instruction used in the embodiment of Fig. 2. The instruction comprises an 8-bit operation (OP) field 56 for specifying an operation to be done, a 4-bit R1 field 58 for specifying a first operand, a 4-bit X field 60 for specifying one of the index registers (i.e. general registers GR1 to GR15 of the general register file 42) and one of the base registers BRO to BR7 for achieving index address modification and base address modification, and a 16-bit A field 62 for specifying the address (displacement) of 64 KB at maximum. Fig. 4 is a block diagram of the embodiment of the invention. In Fig. 4, like parts are designated by numerals identical with those used in Fig. 2 and are not described here in detail. From an IR 36 a 4-bit address data recorded in the X field 60 is supplied through a line 64 to the general register file 42. The contents of one of the index registers (i.e. general registers GR1 to GRIS of the file 42) are supplied through a line 66 to one input port A of a first adder 68. To the other input port B of the first adder 68 a 6-bit address data of the A field 62 is supplied. The first adder 68 accumulates the address data supplied to both input ports A and B and supplies the result of addition through a line 72 to the input port B of a second adder 74. In the meantime, the 4-bit address data of the X field 60 is supplied to a code converting logic 76 which comprises three AND gates 781, 782 and 783. To one input terminal of each AND gate a 1-bit data, for example MSB of the X field 60, is supplied through a line 80. To the other input terminals of the AND gates 781, 782 and 783 the remaining three bits of the X field 60 are supplied, respectively. The code converting logic 76 produces an ANDed output, which is supplied through a line 82 to the base register file 52, thus specifying one of the base registers BRO to BR7. The contents of one base register specified are supplied through a line 7 to the input port A of the second adder 74. The second adder 74 accumulates the address data supplied to both input ports A and B and supplies the result of addition through a line 86 to a main memory 20. The index registers correspond to the base registers specified by the contents of the X field, as shown in the following table: Table 1 EMI7.1 <tb> <SEP> X <SEP> XR <SEP> BR <tb> <SEP> 0 <SEP> 0 <tb> <SEP> 2 <SEP> 2 <SEP> 0 <SEP> <tb> <SEP> 3 <SEP> <SEP> 3 <SEP> <SEP> 0 <tb> <SEP> 4 <SEP> <SEP> 4 <SEP> <SEP> 0 <tb> <SEP> 5 <SEP> <SEP> 5 <SEP> <SEP> 0 <tb> <SEP> 6 <SEP> <SEP> 6 <SEP> <SEP> 0 <tb> <SEP> 7 <SEP> <SEP> 7 <SEP> <SEP> 0 <tb> <SEP> 8 <SEP> <SEP> 8 <SEP> <SEP> 0 <tb> <SEP> 9 <SEP> <SEP> 9 <SEP> <SEP> 1 <SEP> <tb> 10 <SEP> 10 <SEP> 2 <tb> 11 <SEP> 11 <SEP> 3 <tb> 12 <SEP> 12 <SEP> 4 <tb> 13 <SEP> 13 <SEP> 5 <tb> 14 <SEP> 14 <SEP> 6 <tb> 15 <SEP> 15 <SEP> 7 <tb> Suppose a base address is loaded in the base register BRO, said base address specifying a base of a segment to which an instruction using the base register BRO is allocated. Then, when the next instruction is fetched, the physical address for the next instruction is produced by adding the value of the base register BRO to the contents of a location counter (not shown). Therefore, when X = 0, no index modification is effected and the address of the second operand is assumed to be the address A within the segment of the program. When X = 1 to 8,, the address of the second operand is within the segment of the program, which is specified by the base register BRO, and is modified by one of the index registers XR1 to XR8 (i.e. general registers GR1 to GR8). When X = 9 to 15, the address of the second operand is within the segment specified by one of the base registers BR1 to BR7 and is modified by one of the index registers XR9 to XR15 (i.e. general registers GR9 to GR15). As shown in Fig. 4, a NOR gate 88 is connected to receive the 4-bit data of the X field 60. The NOR gate 88 produces a logic lt signal when all the four bits are of logic "0". The output signal of the NOR gate 88 is inverted by an inverter 90. Therefore, a logic "0" signal is supplied to the first adder 68 only when all the four bits in X field are of logic "0", as an ENABLE signal. The first adder 68 therefore carries out no addition and supplies the 16-bit data from the A field 62 through the output port C to the second adder 74. Thus, no index modification is effected when X field equals zero. Fig. 5 is a block diagram of another embodiment of the invention. In Fig. 5, like parts are denoted by numerals identical with those used in Fig. 4 and are not described herein detail. This embodiment uses a mapping table (MT) 92 in place of such a code converting logic as used in the embodiment of Fig. 4. The MT 92 comprises sixteen 3-bit registers. The MT 92 has such a configuration as illustrated in the following table. Table 2 EMI9.1 <tb> <SEP> X <SEP> XR <SEP> BR <tb> <SEP> 0 <SEP> <SEP> - <SEP> <SEP> M [ 0 ] <tb> <SEP> 1 <SEP> 1 <SEP> M[1] <tb> <SEP> 2 <SEP> 2 <SEP> M [ 2 ] <SEP> <tb> <SEP> 3 <SEP> 3 <SEP> M[3] <tb> <SEP> 4 <SEP> 4 <SEP> M [ 41 <tb> <SEP> 5 <SEP> 5 <SEP> M[5] <tb> <SEP> 6 <SEP> 6 <SEP> M [ 6 ] <tb> <SEP> 7 <SEP> 7 <SEP> M[7] <tb> <SEP> 8 <SEP> 8 <SEP> M [ 8 ] <tb> <SEP> 9 <SEP> 9 <SEP> M [ 9 ] <tb> 10 <SEP> 10 <SEP> M [ 101 <tb> 11 <SEP> 11 <SEP> M [ l1 ] <SEP> <tb> 12 <SEP> 12 <SEP> M [ 12 ] <tb> 13 <SEP> 13 <SEP> M[13] <tb> 14 <SEP> 14 <SEP> M[14] <tb> 15 <SEP> 15 <SEP> M [ 15 ] <tb> In this embodiment, the MT 92 is so designed as to receive the contents of the X field 60 and to output mapping address M [ xj. Therefore, when the 4-bit data from the X field 60 is supplied to the MT 92, the MT 92 converts the input data into a mapping address, which specifies one of the base registers. There is no predefined correspondence between the contents of the X field 60 and the base register address. Various correspondences between the contents of the X field 60 and the base register address can therefore be selected by the programmer. According to the address expanding system of the present invention, a greater memory capacity can be obtained while holding the compatibility with the TOSBAC-40 system. Further, the size of one segment can be enlarged from 4 KB to 64 KB. Although only two exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many other embodiments are possible without materially departing from the novelty teachings and advantages of this invention. For example, various modifications are available for the field position and the number of bits of the instruction and also the number of bits of the registers. Further, in the embodiments described above, two adders are used. However, only one adder may be used in place of the two. Still further, the addition may be effected at the ALU. Moreover, the hardware described above can be realized by microprograms. In addition, the mapping table MT 92 can be comprised of a read only memory. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the following claims.

Claims: Claims: 1. In an address expanding system having a main memory (20), a memory address register (26) which is connected to said main memory (20) through a memory bus (22) and to a source bus (24) and in which an address to access said main memory (20) is latched, and a memory data register (28) which is connected through the memory bus (22) to said main memory (20) and to the source bus (24) and in which data read from said main memory (20) or data to be loaded into the same is latched in accordance with the address latched in said memory address register (26), the improvement comprises: : an instruction register (36) which is coupled to said main memory (20) and stores an instruction read from said main memory (20), said instruction including a common address modification field (60) for specifying an index address modification and a base address modification, and a displacement (62); a plurality of general registers (42) which are connected through a bus to the instruction register, the contents of one of said general registers being added to make a memory address in the index address modification; a plurality of base registers (52) which are coupled through the bus to the instruction register, the contents of one of said base registers being added to make a memory address in the base address modification; ; base register address generating means (76) which receives a first data from the common address modification field and produces a second data for specifying one of the base registers; and adding means (68, 74) which is coupled to said instruction register, said general registers and said base registers and which adds the contents of said displacement, said general register and said base register. 2. An address expanding system according to claim 1, wherein said base register address generating means (76) comprises a plurality of gates (781, 782, 783). 3. An address expanding system according to claim 1, wherein said base register address generating means (76) comprises a mapping table consisting of a plurality of registers. 4. An address expanding system according to claim 1, wherein said base register address generating means (76) comprises a mapping table consisting of a read only memory. 5. An address expanding system according to claim 1, wherein said adding means (68, 74) comprises: a first adder (68) which is coupled to said general registers and the instruction register (36) and which adds the contents of one of said general registers and those of said displacement (62) for the index address modification; and a second adder (74) which is connected to said base registers (52) and said first adder (68) and which adds the contents of one of said base registers (52) and those of said first adder (68) for the base address modification. 6. An address expanding system according to claim 1, wherein said adding means (68, 74) comprises an arithmetic logic unit (44). 7. An address expanding system according to claim 5, further comprising address modification inhibiting means (88, 90) which is coupled to said instruction register (36) and said first adder (68) to inhibit the addition and passing the contents of said displacement (62), thus effecting only base address modification.

Inventors: YAMAZAKI, ISAMU
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1981
Main classification: G06F13
IPC codes: G06F9, G06F12