MULTIPLE DIGITAL PROCESSOR SYSTEM

Abstract: An electronic digital processor system is provided that is implemented on a single MOS/LSI semiconductor chip including a ROM 6 for storing instruction codes, a RAM 81 for storing data, an arithmetic logic unit 125 performing opera­ tions on the data under control of microinstructions or commands from control circuitry 82 which generates these commands in response to instruction codes. The multi­ processor aspect includes two independent and simul­ taneously operable register sets 148, 149, 150 and 151 for the temporary storage of data from the arithmetic and logic unit 125 and two program counters 19 and 40, two subroutine registers, 33 and 54, two page address resiger sets 21, 35 and 42,57 and two page subroutine registers 23 and 44 together with two chapter register sets 26,39 and 47,61 with chapter subaddress registers 24 and 45 for addressing the ROM 6. A single set of data paths 70 is provided which couples the dual independent and simultaneously operable register sets to the ROM 6, the RAM 81 and the arithmetic and logic unit 125 and the control circuitry 82. Each individual register set includes the capability to store several sets of data at the same time. The storage registers include a closed circuitry loop of pairs of field effect devices and pairs of clocking devices wherein the clocking devices are coupled between the field effect devices. Input and output terminals are coupled to selected field effect devices. The multiplicity of the registers allow the processing system to be operated as an integrated multiprocessor system in the presence of a single arithmetic and logic unit 125, a single RAM 81 and a single ROM 6. One application of this invention is a two player game apparatus which includes inputs for first and second player together with a display for each player and a common display for providing the game status connected to this multiprocessor system. Another application of the multiprocessor system is an electronic apparatus with a single processor dedicated to the display function. This enables one processor to perform the application algorithm of the device while another processor is totally dedicated to the updating of the display. A further applica­ tion of this invention is an electronic telephone including a keyboard input, a telephone line interface, a speech synth­ esis device with a control line and an audio line coupled to the telephone line interface. A message recorder and an audio line coupled to a telephone line interface to the dual electronic digital processor to control the device. These applications are made possible by the shared and indepen­ dent input and output interfaces provided by the multi­ processor system. In addition, the multiprocessor system includes an external memory interface to provide additional memory to supplement the internal memory on the dual processor chip.

Description: BACKGROUND Since their introduction, computers have increased in size and capability over the years. As computer capability increased, the computers were required to serve several different functions. Traditionally, when a number of users desired access to a computer, a system call "time sharing" was implemented where many different users could access the computer. However, as time progressed many more complex problems arose that required simultaneous processing capabilities. At that time, most computers were large central processing systems. This type of architecture which consisted of one central processor with a large memory bank and dedicated input/output (I/O) proved to be very burdensome when used as solutions for these increasingly complex problems. One of the first problems that arose was the need to separate the I/O section from the main CPU so that the CPU could work on a problem while the I/O could independently input or output information. In the mid to late 60's, minicomputers emerged as a new type of computer architecture. A minicomputer consisted of a CPU that was somewhat smaller than that in most of the existing large computer systems. A minicomputer contained much less memory than the larger traditional computer system. However, the introduction of the minicomputer allowed certain intelligent devices to be built. An intelligent device is one that contains its own processing capability that can operate independently from any other processing system to which it is connected. This new minicomputer architecture solves many of the complex problems, such as the independent I/O problem. At this same time, integrated circuitry was evolving. In the 1960's integrated circuitry consisted of small scale integration (SSI) which consisted of 10 to 12 gates per chip. During the late 1960's, medium scale integration was introduced which increased the gate count per chip to 100 - 1,000. Then in the 1970's, large scale integration (LSI) and very large scale integration (VLSI) was introduced pushing the gate count per chip up to as high as 50,000. As the gate count increased, ?i the capability of these chips increased proportionately. Then around the same timeframe in the 1970's, the first computer on the board systems was introduced. These systems contained a CPU and memory on the same printed circuit board. It became possible to experiment with certain computer architectures. To expand computer capability, three approaches were possible. The first was to increase word size which increases precision. For control applications, this approach does not offer many advantages. The second approach was to increase memory size. This approach became costly unless memory architectures such as cache memories were used. I For computers on a board or computers on a chip the amount of area available for memory was limited so this approach was not a complete solution. The third approach, increasing the number of CPU's, seemed to be the most practical. New architectures emerged containing centrally controlled minicomputers tied together. Two main types of architectures emerged, federated systems and distributed systems. A federated system contained many processors tied to a single or multiple data busses where one processor was the master and controlled transmission of data over the data bus or data busses. Usually in a federated system, each processor was completely and totally independent in hardware and software from the other processors. That is, each processor had its own processing unit and its own memory. The advantage of the federated system is that one processor controlled a system that allowed many processors to service many different users. However, the disadvantage was the complexity of the system control software of the federated system; that is, the software that was used to control the different processors on the data bus or data busses. The software could become quite complex and could also generate inefficiencies in that not all of the processors on line would be used to their full capability. The other alternative in computer architecture was the distributed system. This system consisted of different processing units connected via a data bus or data busses as in the federated system but control was not exercised by a single processor over the remaining processors. Rather the control either was transferred from processor to processor around the data bus loop as in a pooling protocol or each processor could access the bus as required independently of the other processors. In addition, some distributed system processors were allowed to share the same memory modules, thus allowing for one processor to communicate with another processor without actually accessing the data bus. The data busses became the key to both types of computer architecture. As a result, many different data bus protocols emerged. The most popular data bus protocol is the EIA RS-232 interface. The RS-232 interface standard provides an interface between data terminal equipment and data communication equipment using serial binary data exchange. The standard specifies electrical signal characteristics, connector pin assignments, functional interchange circuit descriptions for serial binary data exchange. Another data bus standard is the IEEE 488 which is a digital interface for programmable instrumentation. A multiplexing data bus standard is provided in MIL-STD-1553 which is a standard for bit serial transmission employing a central bus controller. As these bus protocol standards become more sophisticated, the software required to control these bus architectures becomes more complex. A reference for the evolution of distributed computer system is Distributed Micro Minicomputer Systems by Tay Witzmann, Prentiss-Hall, 1980. The invention disclosed avoids all probvlems related to the data bus structure and the data bus software by disclosing a multi processor system that can share the same semiconductor chip. The forerunner of present day microprocessor chips were the semiconductor arrays used in miniature electronic calculators, such as shown in U.S. Patent No. 3,891,921, issued June 25, 1974 to Kilby, Merryman and VanTassel, assigned to Texas Instruments. In the years since the invention of these integrated arrays for calculators, many advances in technology has resulted in great improvements in size, power, cost and functions and reliability of semiconductor chips. Earlier microprocessor systems that have a similar type of single processor structure are U. S. Patent No. 3,991,-305, issued November 9, 1976 by Caudel and Raymond assigned to Texas Instruments and U.S. Patent No. 4,064,544 issued December 20, 1977, entitled "Microcomputer with Code Conversion" by Graham F. Tubbs assigned to Texas Instruments Incorporated. These two patents disclose microprocessor structure in a single form that is similar to the present invention in a dual form. SUMMARY OF THE INVENTION In accordance with the present invention, an electronic digital multiprocessor system is provided that includes a set of dual independent and simultaneously operable registers. A processor system is implemented that includes a ROM for the storing of instruction codes, a RAM for storing data, an arithmetic and logic unit for performing operations on data under control of commands, control circuitry that generates these commands in response to the instruction codes from the ROM. The arithmetic and logic unit is controlled by a group of microinstructions generated from a certain class of instruction codes while another class of instruction codes include fields of constants. A set of data paths is provided which couples the register sets to the RAM, the ROM, the arithmetic and logic unit and the control circuitry. The register sets store data operated upon by the arithmetic and logic unit and store addresses for data in the RAM and instructions in the ROM. The control circuitry provides for the simultaneous and independent execution of instructions in both the register sets. The simultaneous operation is achieved by providing access to the ROM by one register set at the same time the second register set has access t9 arithmetic and logic unit. In a further embodiment of this invention, an electronic digital multiprocessor system is provided which includes a ROM for storing instruction codes, a RAM for storing data, an arithmetic unit for performing operations on the data according to commands, control circuitry for generating these commands in response to the instruction codes, input ports and output ports and a set of dual independent and simultaneously operable registers. The system is implemented on a single MOS/LSI semiconductor chip. The input ports are dedicated individually to each register set for the purpose of inputting data into the register sets. The output ports are provided for the displaying of data that has been processed within the system. A set of data paths is provided which couples the register sets to the ROM, to the RAM, the arithmetic and logic unit, the input ports, the output ports, and the control circuitry. In a further embodiment of the present invention, a storage register is provided that includes a closed circuit loop of pairs of field effect devices and pairs of clocking devices. The closed circuit loop is arranged such that the clocking devices separate the field effect devices. In a further embodiment of this invention, the second terminal of the second clocking device of the first clocking device pair is connected to the input of the first field effect device of the first field effect device pair. The output of the first field effect device of the first field effect device pair is connected to the first terminal of the first clocking device of the first clocking device pair. The second terminal of the first clocking device of the first clocking device pair is coupled to the input of the second field effect device of the first field effect device pair. The output of the second field effect device of the first field effect device pair is coupled to the first terminal of the first clocking device of the second clocking device pair. The second terminal of the first clocking device of the second clocking device pair is coupled to the input of the first field effect device of the second field effect device pair. The output of the first field effect device of the second field effect device pair is coupled to the first terminal of the second clocking device of the first clocking device pair. The second terminal of the second clocking device of the first clocking device pair is then coupled to the input of the second field effect of the second field effect device pair. The output of the second field effect device of the second field effect device pair is then coupled to the first terminal of the second clocking device of the second clocking device pair thus closing the loop. The alternate clocking of the clocking device pairs will cause a field effect device to update the next coupled field effect device through the active clocking device while these field effect devices are isolated from the remainder of the closed loop circuitry by the inactive clocking devices. Data may be stored in the loop by rotating the data through the field effect device pairs. It should be obvious to those skilled in the art that the number of pairs of field effect devices, likewise the number of pairs of clocking devices may be increased as long as the clocking devices and field effect devices are arranged as discussed. The number of data bits stored in the closed circuit loop is the number of pairs of field effect devices and clocking devices in the closed circuit loop. An input terminal may be included in this closed loop circuitry by coupling the input terminal between a clocking device and the input side of a field effect device. An output terminal may be included in this closed loop circuit by coupling the output terminal between the output of a field effect device and a clocking device terminal. It should also be obvious to those skilled in the art that any arrangement of input and output devices may be included in this circuit in order to perform data storage functions or demultiplexing functions. In a further embodiment of this invention, an arrangement of closed loop circuits are provided that allow the parallel storage of data. It should be obvious to those skilled in the art that any number of closed loops may be arranged in order to construct a register that would store several bits in parallel. It should also be obvious to those skilled in the art that the cross connections between the parallel closed loops would provide a cross strapping capability that includes multiplyinc and dividing by the simple shifting of data between adjacent closed loop circuits. In another embodiment of the present invention, an electronic digital processing system is provided which includes a plurality of central processing units. The processor system includes a ROM for storing instruction codes, a RAM for storing data, and an arithmetic unit for performing operations on data under control of commands from control circuitry that generate the commands in response to the instruction codes. The arithmetic unit is controlled by a group of microinstructions generated from a certain class of instruction codes while another class of instruction codes includes of fields constants used in some operations such as "compare contents of accumulator with a constant." The central processing units operate independently and simultaneously to execute instructions on data obtained form the RAM and share a single set of data paths which couples the ROM, the RAM, the arithmetic unit and the central processing units circuitry. In a further embodiment of the invention, an electronic digital processor system is provided which includes a ROM for storing instruction codes, a RAM for storing data, and an arithmetic unit for performing operations on data under control commands, control circuitry for generating commands in response to the instruction code, input means, output means and a plurality of central processing units. A system is implemented in a single MOS/LSI semiconductor chip. The central processing units execute commands which operate on the data by controlling the arithmetic unit, the RAM, the input and the output. The central processing units share a single set of data paths which couple the ROM, the RAM, the arithmetic unit, the control circuitry, the input and the output to the central processing units. In another embodiment of the present invention, a two player game apparatus is provided which includes game display, player inputs connected to a digital processor system further including two independent and separable operable central processing units sharing a single memory, an arithmetic and logic unit and control circuitry for controlling the operation of the two processing units. Using the two independent central processing units with shared memory, the game algorithm may be executed in such a manner that both players may provide inputs to the game simultaneously. One embodiment which a two player game apparatus is provided which includes first and second player inputs, first and second player displays, and a game display all connected to a single electronic digital processor system further including two independent and simultanedusly operable central processing units. The electroic digital processor system further includes a single shared memory for the storage of game data and the storage of the game program, an arithmetic and logic unit for use by both central processing units and control circuitry for the operation and control of the two central processing units. The first central processing unit includes a connection to a player input and a connection to that player's display. Likewise, the second central processing unit includes a connection to its player's input and its player's display. In addition, both central processing units can display data on a common game status display. The digital processor system further includes data paths for the transfer of data in the central processing units and between the inputs and display outputs for the central processing units. This dual processor arrangement allows for the simultaneous and independent execution of game algorithms for a simultaneous two player game operation. In a further embodiment of the present invention, an electronic apparatus is provided which includes a keyboard and a display connected to an electronic digital processor system. The electronic digital processor system further includes a memory, an arithmetic and logic unit and two simultaneously and independently operable central processing units. In addition, the digital processor system further includes an input port dedicated to one central processing unit and an output port dedicated to the first central processing uit in addition to an output port dedicated to the second central processing unit and a third output port that is common and can be used by either central processing units. The keyboard is connected to the first central processing unit input and the display is connected to the second central processing unit individual output port. The functional algorithm for the digital processor unit is executed in the first central processing unit which obtains input data from the keyboard connected to its input port. The output data for the'functional algorithm is placed in the memory common to both central processing units. The second central processing unit is dedicated to refreshing the display. The output data from the functional algorithm calculations made in the first central processing unit is obtained from the common memory by the second central processing unit in order to refresh the displays. Since both central processing units oprate in a simultaneous and independent fashion, the output data from the functional algorithm is displayed as soon as it is stored into the digital processor memory. In yet a further embodiment of this invention, an output port of the first central processing unit is connected to the keyboard in order to display data that has been input into the first central processing unit. The output port of the second central processing unit is dedicated to the second central processing unit as discussed previously. In this configuration, the keyboard display will be updated by the first central processing unit as it receives the input data and the second central processing unit will update displays as previously described. In an additional embodiment 9f this invention, the digital processor system includes three output ports: two output ports from the two central processing units and a third output port common to both central processing units. In this configuration, the output port for the first central processing unit is connected to the input keyboard and displays to the input keyboard the input data that bas been received by the first central processing unit. The output port for the second central processing unit and the common output port are connected to the display. In this configuration, the functional algorithm executed in the first central processing unit provides for the updating of the keyboard input displays, whereas the algorithm in the second central processing unit provdes the refresh data to the display as previously described. In addition, a first central processing unit may write directly into the display by outputting the data through the common output. In an even further embodiment of this invention, the electronic digital processor system is provided with three output ports: two output ports for each of the two central processing units and a common outport wherein all three output ports are connected to a single display and in addition, the output port dedicated to the first central processing units is connected to the keyboard input. The functional algorithm is executed in the first central processing unit and in addition, the first central processing unit updates the keyboard input display to acknowledge input data. The second central processing unit is dedicated to the refreshing of the display as previously discussed. However, in this configuration, a first central processing unit may output directly into the display through either the output port dedicated of the first central processing unit or through the output port common to both central processing units. In another embodiment of the present invention, an electronic telephone is provided that includes a keyboard interface, a speech synthesis device, a message recorder, and an interface to a telephone line. There is an audio connection between the telephone line interface and the message recorder and an audio and control line interface between the speech synthesis device and the telephone line interface. The speech synthesis device transmits a message to the caller upon the occurrence of an incoming call and controls the telephone line interface by answering the line upon the occurrence of an incoming call and terminating the line after a user's specified time. The message recorder records the incoming caller's telephone message through the audio connection with the telephone line interface. The invention further includes an electronic digital processor system that contains two independent and separably operable central processing units with input and output ports for each central processing unit and an output port that is addressable by both central processing units. The keyboard is connected to the input of the first central processing unit and to the output of the first central processing unit. The first central processing unit receives the telephone number input by the user through the input port and acknowledges the input of this telephone number through the first central processing output port. The input of the second central processing unit is connected to the telephone line interface to receive the occurrence of an incoming telephone call. The common output is output is connected to speech synthesis device. Upon the occurrence of an incoming telephone call, the second central processing unit will activate the speech synthesis device to answer the telephone through the control line coupled to the telephone line interface and to transmit through the audio line coupled to the telephone line interface a predetermined message to the telephone caller. The second central processing unit output port is connected to the message recorder in order to activate the message recorder to record a message from the incoming telephone caller after the speech synthesis message has been completed. At the end of a user specified time, the speech synthesis control line will disconnect the audio line in the telephone line interface. In a further embodiment of this invention, a display may be coupled to the first central processing unit output to display the telephone number that is being input through the keyboard. In addition, a repertory dialer may be coupled to the common output port and the speech synthesis device and. message recorder coupled to the second central processing unit output port. The repertory dialer would allow the user to prestore frequently used telephone numbers and to active these telephone numbers upon the telephone line intrface by addressing the stored numbers in the repertory dialer through the keyboard input. In addition, additional household sensors may be added to the invention by coupling these sensors to the second central processing unit through its input port. These household sensors would include a fire detector, a household security intrusion detector, and a detector that would be activated upon a signal from a remote control unit. Upon the occurrence of a fire by the fire detector, the fire department would be called and alerted by the speech synthesis device as to the existence of the fire and the address of the household. Upon activation of the household security intrusion sensor, the police department could be likewise notified. A remote control device could be used to active the electronic telephone in the case of a medical emergency, thus allowing the prestored number for a physician to be automatically dialed and emergency message through the speech synthesis device transmitted to the physician. In another embodiment of the present invention, an electronic digital multiprocessing system is provided which includes a ROM for the storage of commands, a REM for the storage of data, an arithmetic and logic unit, two independent and simultaneously operable central processing units, an input port for one central processing unit, an input port for the second central processing unit, an output port for the first central processing unit and an output port for the second central processing unit and an output port shared by both the first and second central processing units, control circuitry for obtaining the commands from the ROM and data from the RAM and a plurality of data paths which couple the central processing units to the ROM, the RAM, the arithmetic and logic unit, the different input ports, the different output ports and the control circuitry. The control circuitry provides for the simultaneous execution of instructions by both central processing units by causing one central processing unit to access the ROM at the same time the second central processing unit is accessing the arithmetic and logic unit. The input to output change is accomplished by specific instructions implemented in the control circutry. The two dedicated output ports are connected to the portion of the central processing units that receive data from the arithmetic and logic units. In a further embodiment of the invention, one of the inputs to the second multiprocessor includes a zero cross detection circuitry which provides an input signal to the second central processing unit when the voltage of the input to the zero cross circuitry crosses its average direct current voltage level. In another embodiment of this invention, the input to the first central processing unit includes a harmonic conversion transducer which provides a signal to the first central processing unit when the frequency of the input signal is a submultiple of the frequency of the input to the central processing unit. In still another embodiment of the present invention, an electronic digital multiprocessor system is provided which includes a set of dual independent and simultaneously operable registers, a ROM for storing instruction codes, an interface to an external memory for additonal storage of instruction codes, a RAM for storing data, an arithmetic and logic unit foriperforming operations on data according to commands from control circuitry that generates the commands in response to the instruction codes. Each of the dual registers serve to store addresses of instructions contained in the ROM and external memory and data contained in the RAM. In addition, each of the dual registers serve to store results from the arithmetic and logic unit. The external memory interface can be used to operate the multiprocessor system independent from the internal ROM. In a further embodiment of the invention, an electronic digital multiprocessor system is provided which includes a ROM for the storing of instruction codes, an external memory interface for accessing an external memory for storing of additional instruction codes, a RAM for storing data, an arithmetic and logic unit for performing operations on the data according to control circuitry which generate commands in response to the instruction codes, input ports and output ports together with a set of dual independent and simultaneously operable registers. The system is implemented on a single MOS/LSI semiconductor chip. The control circuitry is provided for the simultaneous and independent execution of commands involving both register sets. The dual register sets share a single set of data paths which connect the ROM, the interface to the external memory, the RAM, the arithmetic and logic unit, the input and the output to these register sets. The external memory can be used in either the testing or the operation of the multiprocessor system. The external memory interface can be altered to become an output port. BRIEF DESCRIPTION OF THE DRAWINGS The novel features believed characteristic of the invention are set forth in the claims. The invention itself, however, as well as other features and advantages thereof will be best understood by reference to detailed descriptions will follow when read in conjunction with the accompanying drawings, wherein: : FIGURE 1 is a block diagram of a microprocessor chip detailing the input and output; FIGURE 2a is a schematic drawing of a register; FIGURE 2b is a timing diagram for the register in FIGURE 2a; FIGURE 2c is a table diagram showing the contents of the devices in FIGURE 2a in accordance with the timing diagram in FIGURE 2b; FIGURE 2d is a schematic diagram of an additional embodiment of the register in FIGURE 2a; FIGURE 2e is a timing for the register in FIGURE 2d; FIGURE 2f is a table diagram depicting the contents of the register in FIGURE 2d in accordance with the timing diagram in FIGURE 2e; FIGURE 2g is an additional embodiment of the register in FIGURE 2a; FIGURE 2h is a schematic diagram of a combination of registers as in FIGURE 2a; FIGURE 3a and 3b are a block diagram of the digital processing system of the invention; ; FIGURE 3c is a block diagram of the branching and subroutine addressing circuitry; FIGURE 3d is a timing diagram in voltage versus time for the clocks in the system herein described; FIGURE 4a is a schematic diagram of the positive selector 119 and negative selector 120 together with the adder 125; FIGURE 4b is a timing diagram for the operation of the alder 125; FIGURE 5 is a schematic of the Y registers 148 and 149 and the accumulators 150 and 151; FIGURE 6 is a schematic diagram of the status circuitry 126 and 127 and the status latches 143 and 144; FIGURE 7 is a schematic diagram of a constant and K input logic portion of block 82; FIGURE 8a is a schematic diagram of a portion of the programmable logic array for the instruction decoder; FIGURE 8b is the remaining portion of the instruction decoder; ; FIGURE 9a is a schematic diagram of the "load X register with a constant" instruction decoder; FIGURE 9b is a schematic diagram of the call instruction decoder; FIGURE 9c is a schematic of the transfer page to chapter instruction decoder; FIGURE 9d is a schematic of the load page instruction decoder; FIGURE 9e is a schematic of a return instruction decoder; FIGURE 9f is a schematic of the branch instruction decoder; FIGURE 10 is a schematic diagram of the CPU A inputs 104 and K input multiplexer 102; FIGURE 11 is a schematic of the CPU A K input divider circuitry 97; FIGURE 12 is a schematic diagram of the CPU B inputs 155 and status bit circuitry 157; FIGURE 13 is a schematic diagram of the switch which changes the CPU B inputs to the CPU B outputs; FIGURE 14 is a schematic diagram of the K input multiplex circuitry 106; ; FIGURE 15 is a schematic diagram of the CPU A output buffers 162 and the CPU B output buffers 159; FIGURE 16 is a schematic diagram of the CPU A output programmable logic array 164; FIGURE 17 is a schematic diagram of the CPU A output circuitry 165; FIGURE 18 is a schematic diagram of the CPU A program counter 19; FIGURE 19 is a schematic diagram of the feedback circuitry included in the program counter 19; FIGURE 20 is a schematic diagram of the CPU A subroutine latches 34; FIGURE 21 is a schematic diagram of the CPU A chapter address register 26 and chapter buffer register 39; FIGURE 22 is a schematic -diagram of the CPU A chapter subroutine register 24; FIGURE 23 is a schematic diagram of the CPU A page address registers 21 and the CPU A page buffer register 35; FIGURE 24 is a schematic diagram of the CPU A page subroutine registers 23; ; FIGURE# 25 is a schematic diagram of the RAM write multiplex circuitry 89; FIGURE 26 is a schematic diagram of the RAM Y decode circuitry 79; FIGURE 27 is a schematic diagram of the CPU A and CPU B X registers 99; FIGURE 28 is a schematic diagram of the X decode circuitry 88 and a partial diagram of the RAM array 81; FIGURE 29 is a partial schematic diagram of the R register circuitry 77; FIGURE 30 is a schematic diagram of the R register output buffers for RO and R1; FIGURE 31 is a schematic diagram of the output buffer for R14 and R15; FIGURE 32 is a schematic diagram of the ROM PC decoder 8; FIGURE 33 is a schematic diagram of the ROM page decoder 10 and a partial schematic diagram of the ROM output drivers; FIGURE 34a is a partial schematic of the ROM array 6 and the ROM array drivers for the ROM output lines 11; ; FIGURE 34b is a timing diagram for the operation of the ROM array 6; FIGURE 35 is a schematic diagram of the initialization and test circuitry for the digital processor system. FIGURE 36 is a block diagram of the two player game configuration illustrating the player displays that are dedicated to individual central processing units together with a common display. FIGURE 37 is a block diagram of the two player game apparatus illustrating a two player display and common game display coupled to a common CPU output. FIGURE 38 is a block diagram of software that is executed in the two central processing units for the configuration shown in FIGURE 36. FIGURE 39 is a block diagram of the software executed in the central processing unit for the configuration shown in FIGURE 37. FIGURE 40 is a block diagram of the electronic apparatus configuration where CPU A is dedicated totally to the keyboard input and CPU B is dedicated totally to the display. FIGURE 41 is a flow chart of software in CPU A and CPU B for receiving input data and executing the algorithm while providing output data to the display. FIGURE 42 is a block diagram of the electronic apparatus where CPU A is connected to the input keyboard and CPU B is connected to the display and the common output port for the electronic digital processor system is also connected to the display. FIGURE 43 is a block diagram of the electronic apparatus where all three output ports are connected to the display port in addition to the CPU A output port being connected to the keyboard input. FIGURE 44 is a block diagram of the electronic telephone including the keyboard, processing unit speech synthesis device, message recorder and telephone line interface. FIGURE 45 is a block diagram of the electronic telephone including a keyboard processor unit, repertory dialer, message recorder, speech synthesis device and telephone line enter phase. FIGURE 46 is a block diagram of the electronic telphone including keyboard, keyboard display, speech synthesis device, message recorder and telephone line interface. FIGURE 47 is a flow chart showing a software flow for both central processing units. FIGURE 48 is a block diagram of the electronic telephone including the keyboard, the procssor unit, a keyboard display, repertory dialer, message recorder, speech synthesis device and telephone line interface. FIGURE 49 is a block diagram of the electronic telephone including the keyboard, processor unit, keyboard display, repertory dialer, message recorder, speech synthesis device, telephone line interface and household sensors. Detailed Description of Specific Embodiment Figure 1 illustrates a dual microprocessor single semiconductor integrated chip arrangement. Chip 1 contains the dual microprocessor system. The dual microprocessor will be referred as as CPU A and CPU B. Signal group 2 consist of four input lines connected to the CPU A. KA1 is the least significant bit and KA8 is the most significant bit. Signal group 3 consist of lines KB1 through KB8 which are connected to CPU B and act as either inputs or outputs. KB1 is the least significant bit. Also included is SB which is an output signal from CPU B. Signal group 4 are the 16 register discrete outputs RO R15. These discrete outputs may be set or reset by either CPU A or CPU B. Signal group 5 is eight lines used to output encoded 8 bit data from the output latch for CPU A. Signal group 251 contains the INIT 1 and INIT 2 inputs which are initialization inputs for both CPU's. These inputs will be used in conjunction with the power up sequence to increase the power up time as required by any power supply constraints. Signal group 252 contain the oscillator 1 and oscillator 2 inputs for the chip clocking circuitry. Signal group 253 contains the Vss and Vdd. Vdd is the supply voltage which is normally set at 9 volts. Vss is the reference voltage for the chip. Figure 2 illustrate the circuit arrangement that allows a register to contain bit information for both CPU A and CPU B. Figure 2a is a basic design of this circuit. Figure 2b illustrates the timing applied the circuit in Figure 2a; Figure 2c illustrates the contents of the different storage elements in Figure 2a according to the timing diagram in Figure 2b. The circuit in Figure 2a contains four MOS inverters, 255, 256, 257, and 258. For the purpose of illustrating the contents during execution, these inverters are numbered 1, 2, 3, 4, respectively. The circuit in Figure 2a also contains two sets of devices numbered 259 and 260. Devices 259 are triggered by G2 such that when t2 is low, the data is allowed to flow in a counterclockwise direction, i.e., from inverter 1 to inverter 2 and from inverter 3 to inverter 4. Likewise, devices 260 are triggered by R3 such that when \3 is low data from inverter 4 is transferred to inverter 1 and data from inverter 2 is transferred into inverter 3. This circuit also contains device 261 which is triggered by "won. When "W" is low, the device is conductive such that data from the Data In terminal is input into the inverter 1. Referring now to Figure 2b when TO, W and \2,and X3 are high, in Figure 2c we see that the contents of the four inverters in the circuit in Figure 2a are unknown. At T1 the input Al is placed at the Data In terminal and when W falls is loaded into inverter 255 as illustrated in Figure 2c labeled T1 At T2 92 falls allowing the Al input data which in inverter 255 is stored as Al to be passed to inverter 256 and is stored as Al. At T3, t3 falls and allows the contents of inverter 256 to be passed to inverter 257. Therefore, the Al in 256 is now an Al in 257. At T4 a new input, B1, is present at the Data In terminal and is passed to inverter 255 which is stored as B1. When t2 falls again at T5, the B1 in inverter 255 is passed to inverter 256 as B1 and the contents of inverter 257 which is Al is passed to inverter 258. It should be noted now at the end of T5 or the rising of 92 that the lower two inverters, 255 and 256, contain bit inputs for CPU B and the upper inverters, 257 and 258, contain inputs for CPU A. At T6 b3 falls and the contents of the inverter 258 is passed to inverter 255 and complemented and the contents of 256 is passed to inverter 257 and complemented. At T7 a new input to CPU A register, A2 is present at the Data In terminal and is loaded into the inverter 255. At T8 the contents of inverter 255 or A2 is passed to inverter 256 where it is complemented as A2. If no data was input at T7, the data in the upper two inverters would be allowed to rotate into the data in the lower two inverters and likewise for the data in the lower two inverters at T7. Therefore, this loop illustrated in Figure 2a allows for a circular storage of data for both CPU A and CPU B simultaneously. For the circuit shown in Figure 2a, data can be output on line 262 on the fall of #2. Another embodiment of this circuit arrangement in Figure 2a is illustrated in Figure 2d, together with the timing diagram Figure 2e and contents table Figure 2f. The circuit 273 contained in Figure 2d consist of data input through a device 263 triggered by W, six MOS inverters, numbered 264, 266, 268, 269, 270 and 271 and three devices, number 265, and three devices, number together with the data outline 272. Circuit 273 allows the storage of bits for three CPUs, CPU A, CPU B and CPU C. The actual data stored will rotate through the six inverters shown and in a similar fashion to the circuit in Figure 2a. Referring now to the timing diagram, Figure 2e and the contents table Figure 2f, at TO the contents of the six inverters is unknown. Then at T1, Al is placed on the Data In terminal and allowed to be loaded into inverter 264 at the fall of W. Therefore, inverter 264 contains Al. At T2, t2 falls and allows the transfer of the contents of inverter 264 to inverter 266. Therefore, inverter 266 now contains Al. At T3, 83 falls and allows the transfer of contents of inverter 266 to inverter 268. Therefore, the Al in inverter 266 is complemented and stored in as A1 in inverter 268. At T4, B1 is available at the Data In terminal and is loaded into the inverter 264 at the fall of W. Inverter 264 now stores 31. At T5, N2 falls and the inverter and information in 264 is transferred to inverter 266, i.e., B1 and 264 becomes B1 and 266. The contents of inverter 268 Al is loaded into inverter 269 as Al. At T6, M3 falls again allowing the rotation of the data as shown. At T7, C1 is now loaded as C1 into inverter 264 as previously iscussed. AT T8 t2 falls allowing the rotation of the data as shown. It should be noted now at the rise of N2 that the contents of circuit 273 is the three bits for CPU A CPU B or CPU C. Al is available for output on line 272 at the data out terminal. At T9 data is circulated as shown. At T10, A2 is input into the Data In terminal and loaded into inverter 274 at the fall of W. The contents of 264 is now A2. At Tll, the contents of 264 is loaded into 266 so now that 264 contains A2, 266 contains 269 asA2. The contents of 268, 270, Cl is loaded into inverter 269 as Cl. The contents of inverter 270, #, is loaded into inverter 271 as art It should be apparent to one skilled in the art that additional inverter pairs and clocking device pairs can be added to this circuit as shown to increase the storage capability for additional CPUs. A further embodiment of this circuit in Figure 2a is illustrated in Figure 2g. Circuit loop 274 contains basically the same elements as those contained in the circuit illustrated in Figure are However, additional input and output is terminals are provided. For inverter 276 the input is terminal 275 and output is 277. This arrangement is similar for the other inverters, 280, 284 and 287, as beshown. The input and output of data from circuit 274 can be accomplished with devices similar to device 261 in Figure 2a which are not shown in Figure 2g. The architecture in Figure 2g allows the parallel architecture illustrated in Figure 2h. This type of arrangement allows the parallel storage of data for two CPUs in a register, that is, for each bit stored in a register for the two CPUs, a loop must be provided. It should be apparent to those skilled in the art that different arrangements are possible for a circuit shown in Figure 2h, i.e., the interconnection between the loops can be varied to allow the loading of one inverter into any of the inverters in the next adjacent loop. The Digital Processor System Figure 1 illustrates an embodiment of this invention in a single semiconductor integrated chip 1. A block diagram of the system within the chip 1 of FIG. 1 is shown in FIGS. 3a and 3b. This system is a modification of the digital processor chip described in U. S. Pat. No. 3,991,305 by Edward R. Caudel and Joseph H. Raymond, Jr. assigned to Texas Instruments. The system is centered around a ROM (read-only-memory) 6 and a RAM (random-access-memory) 81. This arc-hitecture gives the user the flexibility to partition memory for each processor. In addition, each processor can share program routines contained in the ROM. The third advantage to this architecture is that the processors may communicate with each other through RAM memory since the memory RAM is common to all processors. The ROM 6 contains a large number, in this case 3072 instruction words of 8 bits per word, and is used to store the program which operates the system. The RAM 81 contains 512 self-refresh memory cells software organized as 8 files of 16 words of 4 bits per word. The number of words in the ROM or cells in the RAM depends upon the desired complexity of the digital processor functions. Numerical input data is stored in the RAM 81, along with intermediate and final results of calculations, as well''as status information or "flags," decimal point position and other working data. The RAM functions as one of the working registers of the processor system, although it is not organized in a hardware sense as separate registers as would be true if shift registers or the like were used for this purpose. The RAM is addressed by a word address on lines 80, i.e., one out of thirty-two address lines in the RAM is selected by means of a RAM Y address decode circuit 79, by an address signal on lines 85 applied from a RAM address decoder 88. For a given word address on lines 80 and address on lines 85, four specific bits are accessed and read out on RAM lines 86. Alternatively, data is written into the RAM 81 via the decoder 88 from a RAM write control circuit 89 via four lines 87. The ROM 6 produces an eight-bit instruction word on ROM output lines 11 and 70 during each instruction cycle. The instruction is selected from 24,576 bit locations in the ROM, organized into 3,072 words containing eight bits each. The ROM is portioned or divided into three chapters, each chapter containing sixteen groups or pages of sixty-four words each. A specific instruction in the ROM is addressed by a ROM word address on one of 6 lines 7, a page address on four lines 16 or 15, and chapter address on two lines 17 or 18. The ROM word address on line 7 is generated in a decoder 8. The encoded ROM word address is produced in either program counter (A) 19 or program counter (B) 40 which are multi-stage exclusive-or feedback shift registers that may be incremented after an instruction cycle, or may have an address loaded nto them via lines 20 from ROM output lines 11 for a call or branch operation. The ROM word address decoder 8 receives an encoded address on six lines 13 or 14, through lines 12. Two three-level subroutine registers (A) 33 and (B) 54 are respectively associated with the program counters (A) 19 and (B) 40 to serve as a temporary storage for the return address during call or subroutine operations. The incremented program address is stored in the registers (A) 33 or (B) 54 via lines 27 or 48 respectively when a call instruction is initiated so that this incremented address may be copied back into the program counters (A) 19 or (B) 40 via lines 28 or 49 respectively when execution of the subroutine has been completed. The subroutine registers (A) 33 and (B) 54 also receive inputs from CLA 34 and CLB 55 via lines 68, 69 and 63, 62 respectively. CLA 34 and CLB 55 are three stage latches that enable the subroutine registers (A) 33 and (B) 54 to execution of up to three levels of subroutines. Figure 3c illustrates interconnection of CLA 34 and CLB 55 with subroutine registers (A) 33 and (B) 54 to be described. The ROM page address on lines 9 is produced in a decoder 10 which receives a four-bit encoded address on lines 16 or 15 from page address registers (A) 21 or (B) 42 respectively which also have buffer registers (A) 35 and (B) 57 associated with them for branch or subroutine call (BRNCAL) purposes. Registers 21 or 42 will always contain the current four-bit page address for the ROM, and directly accesses the ROM page decoder 10. The buffer registers 35 and 57 are multifunction buffers and temporary storage registers, the contents of which can be the present ROM page addresses, or the page addresses during BRNCAL operations. The page address buffer registers 35 and 57 are loaded with a 4-bit code from the ROM word field during the load page instruction (LDP). These registers then transfer their contents to the page address registers 21 and 42 respectively upon execution of a valid branch or call instruction. The page address buffers Registers 35 and 57 receive their inputs from either the ROM 6 via lines 11 and 56 or from the page address registers 21 and 42 via lines 30 and 51 respectively. Their contents are loaded in the page address registers 21 and 42 via lines 29 and 50 respectively. Associated with the page address registers 21 and 42 are page subroutine registers 23 and 44. Each page subroutine register actually contains three levels of subroutine storage capability. The page subroutine registers 23 and 44 receive inputs from CLA 34 and CLE 55 respectively via lines 6;8, 37 and 63, 59 respectively. CLA and CLB designate the current subroutine level. The contents of the page subroutine registers 23 and 44 are loaded with the contents of the page address registers 21 and 42.respectively via lines 22 and 43 respectively during successful call instruction executions. During the execution of valid return instructions, the page address register 21 and 42 and the page buffer Registers 35 and 57 will be loaded with the contents of the page subroutine registers 23 and 44 respectively. In addition to the page address input the page decoder 10 also receives a chapter input from the chapter address registers 26 and 47 via lines 17 and 18 respectively. The chapter address registers 26 and 47 receive their contents from the chapter buffer registers 39 and 61 respectively via lines 31 and 52 respectively. The chapter buffer registers 39 and 61 receive their contents from the page buffer registers 35 and 57 respectively via lines 36 and 58 respectively or from the chapter address registers 26 and 47 via lines 32 and 53 respectively. Associated with the chapter address registers 26 and 47 are chapter subroutine registers 24 and 45 respectively. Each chapter subroutine register actually contains three levels of subroutine storage capability. The chapter subroutine registers 24 and 45 also receive inputs from the CLA 34 and CLB 55 respectively via lines 6S,38 and 63,60 respectively. Upon execution of a call instruction, chapter subroutine registers 24 and 45 will receive the contents of the chapter address registers 26 and 47 respectively via lines 25 and 46 respectively. Upon execution of a Return instruction, the contents of the chapter subroutine Registers 24 and 45 will be copied into the chapter address Registers 26 and 47 and into the chapter Buffer Registers 39 and 61. The page address may remain constant while program counters 19 or 40 are being sequenced or are branching within a page. Calling or branching to another page requires an instruction which loads a new page address into registers 35 or 57 via lines 56, i.e. the LDP instruction. The contents of the ROM 6 are then transferred via lines 11, 70, and 75 into the instruction decoder 82 via lines 72, 73, and 74. The instruction decoder 82 decodes the instructions and produces control signals which activate the selected components of the microprocessor system. Example instructions are represented by the instruction mnemonics 92 and 93. Numerical data and other information is operated upon in the system by a binary adder 125 which is a bit-parallel adder having a precharged carry circuit. The inputs to the adder 125 are determined by "P" and "N" input selectors, 119 and 120 which receive four-bit parallel inputs from several sources and select from these what inputs are applied to the adder on P and N input lines 123 and 124. First, the memory read or recall lines 86 from the RAM 81 provide one of the alternatives for both P and N inputs. Four registers receive the adder output 130, these being the "RAM Y" registers (A) 148 and (B) 149 and accumulators (A) 150 and (B) 151. The two "RAM Y" registers 148 and 149 have output lines 146 and 147 respectively that input into Register Rotator 145 which selects one of the two to be transmitted on lines 107 into the P input selector 119. The N selector 120 elso receives the accumulator outputs 152 and 153 which are rotated via Register Rotator 154 on lines 114 to the input lines 112. The complement of the accumulator outputs 152 and 153 are received by the N selector 120 via lines 103 through inverter 113. Thus, the P adder input 123 is selected from the following sources: data memory or RAM 81 on lines 86 and 109, RAM Y registers (A) 148 or (B) 149 via lines 146 or 147 and 107, constant or keyboard or "bit" information from CKB logic on lines 91 and 108. The N adder input 124 is selected from the following: the output from the accumulator (A) 150 or (B) 151 via lines 152 and 153 through 114, the complement of the accumulator output via lines 103 and inverter 113, the CKB output on lines 111, and the memory output on lines 110. The output from the adder 125 through lines 130 is applied to either the RAM Y (A) 148 or (B) 149 via lines 141 and the accumulators (A) 150 or (B) 151 via lines 142 through select circuitry 140. All of the operations of the adder 125 and its input selectors 119 and 120, etc., are controlled by the instruction decoder 82. The instruction decoder is responsive to instruction words on line 71 from ROM 6. The four bits of the accumulator (A) 150 output are also applied to Output A Register 162 for the output signals via lines 161, and the output of the Output Register (A) 162 is applied via lines 163 to an output Programmable Logic Array 164 which merely encodes a five-bit segment identification to a user specified one-of-eight representation on eight lines 165. The four bits of the accumulator (B) 151 output are applied to Output Register (B) 159 via lines 160 for output via lines 156 into the output lines 155. The fifth bit of the Output Register (B) 159 is the status which is output to the Ss pad via line 158. The Register 77 is a random access register where all bits are separately, independently, and mutually exclusively addressed. When one of the bits in the Register 77 is addressed from the decoder 79, either a "1" or "0" may be entered into the address cell of the Register 77 under control of the SETR or RSTR instructions on line 76 from the current instruction word, as determined by the output of the decoder 79 in the output arrangement. This bit will remain in the defined state until again specifically addressed and changed; meanwhile any or all of the other bits may be addressed and set or reset in any order. It is possible to have any combination of Register 77 bits set or reset, providing 216 or 65,536 code combination (for a sixteen-digit output) on the output lines 78. Ordinarily, however, a routine is used whereby the sixteen stages of the Register 77 are addressed in descending order, MSD to LSD repetitively, to provide ascan cycle. During power-up or hardware-clear, all the bits of the Register 77 are unconditionally set to two". Similar to the Register 77, the other output via register 162 is static in that the contents once entered will remain until intentionally altered. The register 162 functions as an output buffer, remaining latched while the accumulator (A) 150 is being manipulated. The data sources for the Y register (A) 148 and (B) 149 are the following: a four-bit constant stored in the ROM 6 as part of an instruction word; a four bit constant input to instruction decoder 82 from either input keyboard A or B via line 90; the accumulators 150 and 151 transferred to the Y registers (A) 148 and (B) 149. Status logic registers 126 and 127 provide the function of examining the AU MSB carry output C3, or 2 compare COMP output from the adder 125 on lines 128 and 129, and producing a status generate signal on lines 138 and 139 and 2 delayed status on lines 166 and 122 that is selected by multiplexer 121 which is sent via line 75. BRNCAL via line 172 is input to CALL/BR logic 67 which in turn produces a signal to indicate address copying between program counters (A) 19 or (B) 40 and the subroutine registers (A) 33 or (s) 54, for example. Thus, the status registers 126 and 127 always function to set up the validity for a BRNCAL branch. The status generate signal 128 and 129 provide inputs to the status latches 143 and 144 via lines 139 and 138 respectively. These status latches in turn input a bit into the two output registers 162 and 159 via lines 167 and 168 respectively. A control circuit 89 determines what and when data is written into or stored in the RAM 81 via lines 87. This RAM write control 89 receives inputs from either the accumulators via lines 96 or the CKB logic via lines 95, and this circuit produces an output on lines 87 which go to the RAM 81. Selection of what is written into the RAN is made by the instruction word. Constants or keyboard information, from CKB lines 95, as well as the adder output via the accumulator, may be written into the RAM, via the write control 89, and further the CKB lines 95 can be used to control the setting and resetting of bits in the RAM, via the write control 89. The RAM page address location into which data is written -is determined by three bits of the instruction word on lines 101 as applied via lines 94 to a RAM file address register 88 and thus to lines 85. The RAM Y address in the decoder is of course selected by the contents of RAM Y registers (A) 148 and (B) 149 via lines 83, and X register 99 via lines 84. The two four keyboard inputs 2 and 3 appear internal to the chip 1 on lines 104 and 155. The multiplexer 106 determines which of the four inputs 104 or 155 will be input via lines 90 to the K-input of the control logic 82. The A inputs K1A, K2A, K4A, and K8A are input to th multiplexer 106 through lines 105, 116, 117, and 118. R8A is input to a divider 97 through line 115 and user defined switch 102 through line 115. Divider 97 also outputs 1 bit into user defined switch 102 via line 98. Divider 97 is used as a divide down counter. The B inputs K1B, K2B, K4B, and K8B are input to the multiplexer 106 through lines 131, 132, 133, and 134 respectively. K8B is input through a user defined switch 135 via line 136 which places K8B directly on the input line 134 or inputs the K8B pad signal through zero detect circuitry 299. Four bit inputs are shown, although some systems may need only three inputs. It is seen that a keyboard input may be applied via CKB logic 82, lines 91 and the adder 125 to the accumulators (A) and (B) 150 and 151. BRANCH and Subroutine Call Fig. 3c is an illustration of the program counter, the page address register, page buffer register, chapter address register, chapter buffer register and the three levels of the program subroutine register, page subroutine register and chapter subroutine register. The architecture in Fig. 3c is repeated for both the A and B sets of registers in Fig. 3a and 3b. If the status line 75 is "1" and the next instruction is a branch signified by line 169 being a "1", then the controller 179 via line 171 causes the page address register 21 to be loaded with contents of the page buffer Register 35 via lines 29. The page buffer Register 35 may be previously loaded with the branch page address by use of the LDP instruction if the branch is a long branch. A long branch is defined as a branch that requires a page and/or chapter address change. If the branch is to generate a change in chapter and page, the chapter buffer register 39 must be loaded by use of the TPC instruction via line 172 in addition to the LDP instruction loading the page address. The LDP instruction is executed which cause four bits of page address to be loaded from the ROM 6 over lines 11 and 56 into the page buffer Register 35. If the chapter address is to be changed, then the execution of the TPC instruction will cause the least significant two bits of the address in the page buffer register 35 to be loaded via lines 36 into the chapter buffer register 39. When the actual branch instruction is executed, line 169 is a "1" and if the status 75 is "1" then line 171 is activated which causes the copying of page address over lines 29 and copying of the chapter address over lines 31. For a call to be executed, the call line 170 and status line 75 must be both "1". When these conditions occur, CL1 34-1 is set to "1" via line 65 to signify that the first subroutine level is in use. Line 171 is set to "1" which causes the present incremented address of the program counter 19 to be stored in the first subroutine Register 33-1 via line 27; the subroutine address is then placed in the program counter 19 from the ROM 6 via lines 11 and 20. If a return is executed then CL1 34-1 is reset to 0 via line 65 and the incremented address now stored in the first subroutine Register 33-1 is moved into the program counter 19 via line 28. If the first subroutine, register loaded, i.e. the processor is executing instructions in the first subroutine level and another subroutine call instruction is encountered then CL2 34-2 is set to 1 via line 65 and the incremented address of program counter 19 is loaded'into the second subroutine Register 33-2 via line 27. The new subroutine address is then loaded into the program counter from ROM 6 via lines 11 and 20. If a third call instruction is encountered, then CL3 34-3 is set in a similar manner and the incremented address in the program counter 19 is stored in the third subroutine Register 33-3 via line 27. If a fourth call instruction is encountered, it is treated as a branch and the integrity of the three subroutine registers is maintained. A long call, defined as a call to a subroutine located off the current page address, and/or chapter address is also possible. If the call is also off the current chapter the following sequence occurs. The subroutine chapter is first loaded into the page buffer register 35 from ROM 6 via lines 11 and 56 upon execution of the LDP instruction. The chapter buffer register 39 is next loaded from the page buffer register 39 via line 36 upon execution of the TPC instruction. The subroutine page is loaded into the page buffer 35 from the ROM 6 via lines 11 and 56 upon executing the LDP instruction. When the call instruction is executed, CL1, 34-1 is set to 1 via line 65. Line 171 and 69-1 cause the incremental address in the program counter 19 to be stored in the first subroutine Register 33-1 via line 27. The page address is in page address Register 21 is to be stored in the first page subroutine Register 23-1 via line 22, the chapter address in the chapter address Register 26 is to be stored in the first chapter subroutine Register 24-1 via line 25. The subroutine address is loaded into program counter 19 from the ROM 6 via lines 11 and 20. The subroutine page is loaded in the page address Register 21 from the page buffer Register 35 via line 29. The subroutine chapter is loaded in the chapter address Register 26 from the chapter buffer Register 39 via line 31. If addition long call instructions are executed,, each call must be preceeded by LDP and TPC instructions, if required, CL2 34-2 will be set to signify loading of the second subroutine level and the CL3 34-3 will be set to signify the loading of the third subroutine level. The remaining program counter subroutine Registers 33-2 and 33-3, together with the page subroutine Registers 23-2 and 23-3 and chapter subroutine Registers 24-2 and 24-3 are loaded in a similar manner as before. When a return instruction is executed, the highest level CL latch that is "1" is set to "0" via line 65 and the corresponding program counter subroutine Register 33 contents is loaded into the program counter 19 via line 28, the contents of the corresponding page subroutine Register 23 is loaded into the page address Register 21 via line 22 and into the page buffer Register 35 via line 30. The contents of the corresponding chapter subroutine Register 24 is loaded into the chapter address Register 26 via line 25 and into the chapter buffer Register 39 via line 32. Each successive return instruction is executed in the same way. After all CL latches 33 are set to "0", any further encountered return instructions will be treated as a No-op. SYSTEM TIMING Figure 3d illustrates the system timing for the microprocessor system in Figure 3a and 3b. These processors will operate synchronously with the external oscillator but will operate in phases that are skewed with each other. The timing for this architecture may be viewed as two macroinstruction per machine cycle where each macroinstruction generates its own unique set of microinstructions. All of the timing signals of through #6 are derivations of the oscillator which input into the circuitry for the system. B1 is down for two complete oscillator cycles and up for four. t2 is down for two and up for four, offset from Q1 by one complete oscillator cycle. E3 is up for three and down for three. h is down for one, up for two. 95 is offset from W4 by one complete oscillator cycle and is down for one, up for two. Likewise, \6 is offset from b5 by one complete cycle and is down for one and up for two. B1 and 82 are used for memory fetching in the ROM 6 for both CPU A and CPU B, for instance,#during the first cycle that t1 is low, this period is used to fetch the instruction for CPU A. Likewise during the first low period for N2, this time period is used to fetch the first instruction for CPU B and then during the down part of #2, the CPU A instruction word is executed. It will be noted that the execution of the CPU A instruction occurs at the same time that the CPU B instruction is being fetched. Likewise when \1 goes low, the CPU B instruction is then executed and the next instruction for the CPU A is then fetched. This allows the processor to use both the ROM and the arithmetic unit at the same time 1) for executing the instructions and 2) for fetching the instructions. Therefore, the processor system is used efficiently since the ROM does not have to await the execution of the instruction and the logic to execute the instruction such as the arithmetic unit does not have to wait for the fetching of the instruction from the ROM. \3 is used for multiplexing data through the circuitry. Normally when 93 is down, inputs to CPU A are input into the circuitry. Likewise when N3 is high, the inputs for CPU B are placed on input lines. #4, 5 and 6 are used to precharge, conditionally discharge and examine the ratioless circuitry and clock all dual purpose logic (RAM, AU). The timing for the arithmetic unit 125 and the ROM 6 are discussed in the descriptions of these sections. The Adder Input Select As shown in Figure 4A the adder input selects 119 and 120 include for each bit of the adder two sets of complex gate arrangements 120-1, 119-1, etc, each consisting of complex OR/NAND gates 200 and 201, respectively. Gate 201 receives five inputs from the instruction decoder 82, referred to as 15N, CKN, MTN, ATN, and NATN, which determine which of the data input lines will be activated. ATN activates gates 120 for inputting the output from the accumulator 150 or 151. NATN is the control line for inputting of the complement of the accumulators 150 or 151. MTN is the control line for the input from the RAM 81, MEM. CKN is the control line for the constant input, CKB, received from the constant and K input logic 82. Selector 119 is shown with these control inputs and three data inputs 202 for complex gate 200. MTP is the control signal for the input from RAM 81, MEM. CKP is the control line for the input from the constant and K-input logic 82. YTP is the control line for the input of the Y Register 148 or 149. The Adder As shown in detail in FIGURE 4A, the binary adder 125 consist of a set of four parallel adder stages 125-1, 125-2, 125-4 and 125-8; all four of these stages are basically the same. Considering the MSB stage 125-8, each adder stage consist of a first complex gate 204 and a second complex gate 205 and a carry input 207 and a carry output 206. The complex gate 204 receives two inputs, 120-8 and 119-8 from the input selectors 120 and 119 when clocked in during B5 and produces an output on line 130-8 which is the or equivalence function of the inputs on 119-8 and 120-8. A carry output is produced on the line 206 by first precharging a line 206 to a "0" or Vdd on E5, then conditionally discharging when E5#goes to Vss, depending on the output of a gate 211. When both inputs 119-8 and 120-8 are", one of the generate conditions for generating a carry is satisfied so the output of gate 211 causes a device 209 to be conductive after 5 goes high, discharging line 206 to Vss or "1". A carry signal is produced on line 206 if both inputs 119-8 and 120-8 are "1", or if either of these is "1" and "carry in" or line 207 is "1", or if both inputs 119-8 and 120-8 are "1" and carry-in on line 207 is "1"; for all other situations, the line 206 remains at "0" or Vdd after N5 ends. A signal on line 207 "carry-in" comes from the previous stage 125-4 which in turn comes from the preceeding stage and the preceeding before that. The carry-in signal is also produced by the instruction decoder 82. The carry-out line 206 is sent to the two status circuits 126 or 127. The adder 125 provides a "compare" function wherein a compare output is produced on line 210. It also goes to the status circuits 126 and 127. The line 210 is charged by E5 to Vdd by any of the two devices 212 which are conductive then conditionally discharged on < Zr by any of the device 212 turned on by the outputs 214 of the complex gates 204. Conditional discharge occurs if line 214 goes to Vdd which occurs if the inputs to the complex gate 204 at 119-8 and 120-8 are not the same. Where all of the inputs 120-8 are the same as the inputs 119-8, line 210 will be "0", otherwise "1". Outputs from the adder stage 125-1, 125-2, 125-4 and 125-8 are produced are lines 130 of which line 130-8 and is the output of complex gate 205. The complex gates 205 receive inputs from line 214 and "carry-in" for that bit on line 206 The complex gate 205 produces a "equivalence" function of the ouputs on line 214 and carry-in. During 5. these outputs 130 are not valid, because the carry circuit is being precharged. Carry is not valid so the outputs 130 are not valid, until after size ends. The adder output 130 is an input to the arithmetic unit select 140 shown in Figure 5. Figure 4b illustrates the timing for the arithmetic logic unit for CPU A. The operation of the logic unit for CPU B is identical as that for CPU A except where t2 is low in CPU A, 81 is low in CPU B. The operation of the arithmetic logic unit for CPU A starts and is completed during the time that B1 is high. The microcontrols are precharged during the fall of 6, 701, for initialization. At this same time, 05 is used to time the precharging of the carry and compare logic, 702. When #6 is high, #2 and 4 fall, the C8 and NE microcontrols sample the carry out line 206 and compare lie 210 as shown in 706. At the fall of t2 703, the status generated is coupled into the status circuits and into the status latch A. This operation is timed by the down portion of #2. Also at the rise of t6 704, during this same time slot, the microcontrols are validated and the arithmetic operations are begun. The next time slot is defined by the fall of b5, 705, and the rise of 84. During the fall of #5, the adder is isolated from the data multiplexer and the carry and compare circuits are evaluated. The results are written into the working registers or into the RAM 81. During the low time of 95, 705, the status is generated and the operation of the arithmetic is complete. The Accumulator and RAM Y Reaister Figure 5 shows the four sections of the arithmetic unit select 140 and accumulator 150 and 151 and Y Register 148 and 149. The arithmetic unit select circuitry is shown in Sections 140-1, 140-2, 140-4, and 140-8 where the actual circuitry contained within the section is illustrated in 140-8 and is similar in the other sections 140-1, -etc. In section 140-8 the output from the arithmetic unit on line 130-8 is selectively directed to either the Y Register or the accumulator by devices 215 and 216. Device 215 receives a signal AUTOA from gate 218. Device 216 receives this signal AUTOY from gate 217. Both gates 217 and 218 receive their signals AUTOY and AUTOA from the instruction decoder 82 together with a such that for either AUTOA or AUTOY to be -Vdd b5 must be -Vss; thus the accumulator 150 and 151 or Y Register 148 and 149 can only be loaded during 5. RAM Y Register 148 and 149 are actually one circuit containing a single loop 219 of four inverters. Data for CPUA and data for CPU B are contained in loop 219. When device 216 conducts, then the data from the adder 125 is conducted by a line 130 into register 148 inverter 221. The operation of the RAM register Y loop 219 is similar to that which is illustrated in Figure 2A. On the occurrence of 86, the inverted data in 222 is transferred torthe inverter 222. On the occurrence of #4, the data in 221 is inverted and stored in inverter 223 in the upper part of the loop in 149-8. In actuality, the contents of 149-8 and 148-8 can be either the contents of the CPU A or the CPUB data, depending on the clock cycle timing. The operation of the accumulators 150 and 151 is similar in that there exist a four inverter loop 220 which receives the data from the adder 125 and first loads it into an inverter 224 and on the occurrence of B6 that data is transferred to inverter 225. The ouput of the RAM Y Register 148 or 149 is taken from inverter 223 on line 228 or from inverter 221 on line 227. Likewise, the output of the accumulator 150 and 151 is taken from inverter 224 on line 229 or from inverter 231 on line 230. Status Circuitry Figure 6 illustrates the status circuitry. Complex gate 232 receives four inputs; 210 which is the compare line from the arithmetic unit 125, NE which is the not-equal control line from the instruction decoder 82, line 206 which is the carry output from the adder 125 and C8 which is the carry control line from the instruction decoder 82. If the compare line is to be sent to the status NE is set high and thus line 210 is transmitted through to line 239. If the carry bit is to be sent through, then C8 is high and line 206 is transmitted to 239. Status circuitry 127 receives the signal from 239 through a NOR gate 240 clocked in by both #1 and X2, likewise status circuitry 126 receives its input from line 239 through NOR gate 241 which is clocked in by 2 and then #1. There is a single output from these two circuitries 126 and 127 that is clocked by i3 and is known as a status line "ST". Both gates 240 and 241 receives inputs from the initialization circuitry. The status latches 143 and 144 are set from line 239 through gates 233 and 234 and devices 237 and 238. When the status latch for CPU A is to be set, the instruction line set status "ST" is high and when t1 is high gate 234 activates device 237 which allows the information on line 239 to be transmitted to the status latch 143. Likewise when the "ST" line is high and the G2 line is high, gate 233 activates device 238 and the information on 239 is transferred to the status latch 144. Status latch 143 is refreshed by t2 and status latch 144 is refreshed by 81. The output of the status latch is line 235 and the output of the status latch 144 is the output 236. Control Keyboard Bit Logic The CKB logic portion of the instruction decoder block 82 is shown in Figure 7 and it consists of four complex identical gates 240-1, 240-2, 240-4 and 240-8 which produce a CKB 1 to CKB 8 outputs on lines 91. The CKB outputs 91 are applied to the adder input selectors 119 and 120 and to the RAM WRITE control 89 as explained. Each of the four complex gates 242-1 - 242-8 contain three separate gating arrangements 245, 244 and 243, each of which will produce a CKB output under certain conditions, dependent upon the current instruction words on line 72. The gating arrangement 243 receives RO, Rl, and R7 into an AND gate. R4 replaces R7 for complex gate 242-1, R5 for 242-2, and R6 for 242-4. The purpose of this gating arrangement is to place R4, R5, R6 and R7 onto CKB 1 through CKB 8 respectively, when the instruction code Olxxxxxx is executed. The gating arrangement 244 receives RO, R1, R2, R3 and R4 from lines 40 and K8 from the input keyboard multiplexer 106. The purpose of this arrangement is to output the keyboard inputs from lines 90 onto lines 91 *ien the instruction word 00001XXX is encountered. The gating arrangment 245 functions in setting and resetting bits -in the RAM 81, and receive RO, R1, R2 and R3 from lines 72 and input to an AND gate, so this part will be responsive to an instruction word 0011xxxx while the remaining part of the gate is responsive to R6 or R6 or R7 or 2 so that only one of the four gates 242-1 to 242-8 will Produce a CKB output of "ln. This serves to select one of the four bits for a bit operation. The overall function of the CKB logic 242 is thus three-fold. First, a fourobit constant appearing in the R5 to R8 field on the instr.-#ction code may be applied to the lines 91. Second, the Keyboard or external inputs on lines 90 may be applied to Xtines 91. Third, one of the four lines 72 may be selected for addressing one of four bits of a digit in the RAM 81. All of these functions are under control of the current instruction words on line 71. The °nstruction Decoder Fiarn#es#8a and 8b illustrate the instruction decoder portion of block 82 which contain both the fixed instruction and instruction PLA. Referring to Figure 8a, limes 73 are input into the instruction decoder 82 and consist of the 8 lines from ROM 6 in true and complement form These lines are transformed into lines 250. The actuation of the selected line in 250 is valid at N6 due to device 248. A pattern of gates 247 are shown which are thin oxide areas represented by circles connected to the P dif±-usion lines 250 and to the interleaved P diffused linus Vss not shown and thus form MOS transistors at each circle. Each line 249 therefore functions to produce a Vss or "1" output if any line 250 which crosses it has a circcle or a gate over it and is activated by Vdd; otherwise each line 249 will be at Vdd during the period 26¯ :When the instruction bus 73 (data and its complement) is active and in the case where in one of the gates such as gate 247 turns on in the macroinstruction section of the PLA, a particular line of the macroinstruction lines 250 will remain at logic zero or charged at Vdd and the respective macroinstruction will be executed. In most cases, at least one gate such as gate 247 will turn on thus providing a discharge path for most of the macroinstruction lines 250 and these lines will be at a logic "1". One of the macroinstruction lines 250 will remain charged and the respective macroinstruction will be executed. Figure 8b illustrates another portion of the instruction decoder which produces 7 instructions. SUIT. RBIT and RSTR are all activated when the respective lines 73 from ROM 6 are activated and when 5#is high. TODA is low when 92 is high. TODB is low when 1 is high. IOC is low when this high. The JAM line 712 is used in a testing mode to input instructions on the instruction line 71 via 73 from the output pads 165. This enables the user to execute instructions from a separate memory. The OUTROM line is also used in a testing node to download the contents of ROM 6 to the Output Pads 165. This enables the user to examine the contents of ROM 6. The remaining instructions are produced by logic that is illustrated in Figure 9. LDX is produced by being high and an instruction 00101XXX as illustrated in 9a. The call instruction is generated by llxxxxxx instruction as shown in Figure 9b. The inhibit line is also introduced to restrict the call signal from being activated during a system test. Figure 9c illustrates the TPC instruction which is activated on an instruction of 00061011 and no inhibit instruction as previously mentioned. LDP is generated by 0001 and no inhibit as shown in Figure 9d. Figure 9e illustrates the generation of the return signal. The return signal is the complement of the return bar and is generated by a 1111000 without an inhibit. The BRNCAL signal is generated by the logic illustrated in Figure 9f whereby a l0xxxxxx instruction with the status line high and the inhibit line high. The inhibit line is use'd during the testing modes to prevent the branching, calling of subroutines, or returning from subroutines during the downloading of ROM 6 as previously discussed. INPUT Referring to Figure 3a, the CPU A keyboard inputs 104 and CPU B keyboard inputs 155 provide the input data for the multiprocessor. Figure 10 is an expanded view of CPU A A keyboard logic 104. CPU A keyboard logic consists of four similar input blocks, 104-1, 104-2, 104-4 and 104-8. Referring now to block 104-1, the CPU A keyboard input least significant bit KAl is input on pad 291-1 and enters block 104-1 which contains a Schmitt trigger 305 for squaring the wave form of the input signal and the associated circuitry 306 to provide the data on line 118. Likewise, input pads 291-2, 291-4 and 291-8 provide input data onto lines 117, 116 and 115, respectively. Line 115 enters a switch 102 and also provides information on line 100. Switch 102 is user programmable and allows the user to either input data directly from pad 291-8 or to use divider 97 by sending information obtained on pad 291-8 to the divider via line 100 and receiving the output from the divider via line 98 input into the switch 102 as shown. Line 105 is the output of this switch and provides this input information to the multiprocessor unit. Referring now to Figure 11, the divider 97 is shown. The input to the divider is provided by line 100 which is referred to earlier and originates from input pad 291-8. The output divider is a simple divider circuit made up of flip-flops 291, 292, 294, 295 and 296. This divider provides the divide by 2, divide by 10 or divide by 20 signal over the output line 98. Also provided is an input line 289 which resets divider 97 to 0 during initialization and bypasses divider 97 during tests. Referring now to Figure 12, the CPU B keyboard input 155 is shown together with the status bit output block. CPU B keyboard inputs are shown in Figure 12 as four component blocks, 155-1, 155-2, 155-4 and 155-8. Blocks 155-1, and 155-2 and 155-4 are similar as shown in 155-. Block 155-4 receives an input signal from the keyboard input pad 308-4 and transmits that input signal through a Schmitt trigger 309 onto line 133. A special design feature of this multiprocessor allows the keyboard inputs to CPU B to also be used as outputs. The determination of whether the pads 308-1 to 308-8 are input or output are made under program control using instructions TDO and IOC. TDO forces the input/output blocks 155-1 to 155-8 into an output mode such that output data can be provided on pads 308-1 to 308-8. Under the output conditions, blocks 155-1 to 155-8 receive the output information over lines 156 as shown in Figure 3a. Referring back to Figure 12, lines 156-1, 156-2, 156-4 and 156-8 are illustrated as inputs into blocks 155-1 to 155-8, respectively. Referring now to block 155-4, this input signal from the CPU output register 159 (as shown in Figure 3a) is input into a gate 310 via line 156-4 together with the control line 297-4 which originates from a switch illustrated in Figure 13. This signal switches the block 155-4 into the output mode when it is high allowing line 156-4 to output the bit information through pad 308-4. Block 155-4 also receives an input 300-4 which is the initialization signal and zeros the contents of this block. Block 155-8 includes another option available to the user. That option is a zero cross detection circuitry contained in block 299. The user has the option to either select the input directly from the pad 308-8 or the input from this zero cross detection circuitry. This' zero cross detection capability allows the user to make the 60 Hz power signal a basis for system timing. The user choses either option by programming switch 135 to either select the input from pad 308-8 or to zero cross circuitry detection 299. Whichever signal is selected is then transmitted through Schmitt trigger 311 to line 134. The remaining circuitry in block 155-8 is as explained in block 155-4. Block 157 serves two purposes. The first purpose under normal conditions is that it provides status latch information from Output Register 159. This information is provided over line 158 and is gated with line 298 in gate 312. Line 298 contains the output command from the switching circuitry shown in Figure 13. During test mode if line 316 is active, then 1 will be output on the SB pad 307. If line 315 is active which implies in turn that line 316 is inactive, then the status (ST) will be output on SB pad 307. During test mode, either lines 316 or line 315 will remove line 158 containing CPU B status information and substitute line 314 which contains status of both CPU A and CPU B during test. Line 313 is an initialization line that zeros the contents of block 157 during initialization. Figure 13 illustrates the switch used to change the keyboard input logic 155 to output logic for CPU B. This circuitry receives an input signal on lie 320 which, is activated when the TDO instruction is executed. This signal will force the switch to force the keyboard circuitry 155 into an output mode. The circuitry in Figure 13 also receives input 321 which is a signal that becomes active when the IOC instruction is executed. This instruction causes the circuitry to toggle from either input to output or output to input. The output of this switch is transmitted on line 297. Line 323 is also provided for initialization which will force the circuitry into the input mode. Figure 14 illustrates the multiplex circuitry 106 shown in Figure 3a. This circuitry receives lines 118, 117, 116 and 105 from the CPU A keyboard input circuitry 104 as discussed earlier and lines 131, 132, 133 and 134 from the CPU B keyboard input 155. The timing signal 03 selects the inputs from the CPU A keyboard input circuitry 104 when 53 is low and when h3 is high, the inverter 319 selects the inputs from CPU B circuitry 155. The selected lines are output via lines 90-1, 90-2, 90-4 and 90-8. OUTPUT Figure 15 illustrates the two output registers, 162 and 159. Output register 162 contains the outputs for CPU A and output register 159 contains the outputs for CPU B. Included are buffers for the status latch data for both CPU A and CPU B. The buffer for CPU A 162 can be divided into five parts labeled 162-1, 162-2, 162-4, 162-8 and 162-S. Sections 162-1 - 162-8 are dedicated to the outputting of the accumulator via lines 326 which in the CPU A mode corresponds to line 161 in Figure 3a. Section 162-S transmits the status latch data of CPU A. In Section 162-1 the accumulator bit is input from the line group 326 through a clocking device 335. Device 335 is active when the TDO instruction is executed in CPU A. This line is then clocked into gate 336 when line 327 equals "1". Line 327 becomes active when CPU2A is initialized thus zeroing out the output buffer 162; The accumulator data input is clocked in through device 337 when 1 becomes active and the output is upper line of pair line 163-1. The remaining four sections of 162 ork in a similar manner. Section 162-2 transmits the second accumulator line over line pair 163-2. Section 162-4 transmits the fourth accumulator line over line pair 163-4. Section 162-8 transmits the eighth line from the accumulator over line pair 163-S. Section 162-S then transmits the status latch data of CPU A over line pair 334. Adjacent to block 162 in Figure 15 is block 159 which contains the output buffer for CPU B. The output buffer for CPU B 159 can be divided into five sections. The first section 159-1 is typical of all five and receives an input from the accumulator. Section 159-1 receives input from the first accumulator line in the group lines 326 which is transmitted through device 338 when the TDO instruction is executed in CPU B. This data is further gated through device 339 when 2 is low. Gate 325 is connected to this accumulator line and a line 328 which becomes active when ths CPU B is initialized. When gate 325 becomes inactive, the CPU B outputs are zeroed. The operations of the other five sections of ths output buffer 159 are similar. In particular section 159-S outputs the CPU B status latch data obtained from line 331 to line 333 in a manner similar to the output of the accumulator information in 159-1. Lines 156-1 to 156-8 are then output to CPU B keyboard blocks 155-1 to 155-8, respectively. The status latch data output on line 333 is transmitted to status pad SB 157. Figure 16 illustrates the output programmable logic array 164. The output programmable logic array is a 32 term segment device which will be programmed by the user and provide the 8 outputs on lines 341 when R2 is low on line 340. Line 342 is provided to disconnect the output PLA during the test mode which downloads the ROM contents to the output pads 165 and also during the random logic test which converts output pads 165 to the random logic input. Figure 17 illustrates 2 of the 8 CPU A output ports 165. Output pads 165-7 receives three input sig#nals, 341-7, 344 and 343. All three inputs are coupled to gate 347 which allows the signal on line 341-7 to be output when the system is not under test per line 344 or the system is not under initialization per line 343. When line 343 is active under initialization, it also zeros the output via device 350. The output pads 165 have a special function during test. Under one test, they are used as output ports to download the ROM 6. In one mode of the second test, they are used to load instructions over the instruction bus. When the first part of the second test is performed, line 344 becomes active thus blocking any output to section 165-7 through gate 347 as previously mentioned and allows for the inputting of information from pad 346 via line 349 into line 348 to line 341-7 as controlled by device 351. All other sections in 165 operate in a similar manner. During the second phase of this second test the output pads 165 are returned to the output mode. PROGRAM COUNTER Figure 18 illustrates program counter 19 as illustrated in Figure 3b. The program counter 19 is identical to program counter 40 except that program counter 19 contains the program counter for CPU A and program counter 40 contains the the program counter for CPU B. In addition, the 41 signal for program counter 19 is b2 for program counter 40. Otherwise the internal architecture is the same. Therefore, only program counter 19 will be illustrated and discussed. Figure 18 also illustrates subroutine register 33 and its relationship with program counter 19. It should be noticed that subroutine 33 is divided up into three sections, 33-1, 33-2 and 33-3; 33-1 contains a RAM cell 376 for storage of the program counter during the execution of a subroutine. Sections 33-2 and 33-3 have similar architectures. It should also be noted that both the program counter and the subroutine register are divided into six vertical sections representing the six bits of information output from the program counter 19. Only the left-most section for both the program counter and the subroutine register are shown since the remaining sections are similar. The program counter 19 has four basic modes of operation - normal, branch, subroutine and initialization. In the normal mode, the program counter receives signal 358 which allows the information contained in inverter 369 to be input into inverter 368 by device 370. The bit information contained in -368 is then output on line 355 which is the output for the program counter 19. The information on line 355 goes to both the ROM Y decoder during & (#2for CPU B) and the feedback circuitry shown in Figure 19 in order to access the next instruction. Under normal operations, the instruction counter outputs illustrated as PCA0 through PCA5 which are fed through the feedback circuitry illustrated in Figure 19 in order to provide the next instruction address by line 359. Upon the occurrence of & , the information on 359 is then loaded into gate 369 and at the occurrence of the next 2 clock, the line 358 is activated allowing device 370 to pass the data in from device 369 to 368. It should be noted that this is a feedback register and does not count in the normal binary fashion, i.e.,00,01,l0,l1 etc. Rather, it is a pseudo random program counter which shifts a 1 through the shift register and then shifts a 0 and so forth. The sequential count for the shift register is 00,0,001,011,111, etc. Therefore, as long as the program counter is in normal operation, the feedback register will provide the additional bit to the program counter to increment the address. The next mode that the program counter operates in is the branch mode. Upon the occurrence of the branch mode, a signal on line 357 activates device 371 which allows the new branch address contained in the instruction from the ROM to be input into the program counter or more specifically into inverter 368. The ROM loaded program address then appears on the program counter lines PCA0 through PCA5. Therefore, upon the activation of 1 the information contained on line 359 will be the new branch address plus 1, resulting from being transmitted through the feedback circuitry. This new address is then stored in inverter 369 and upon to normal operation, the activation of line 358 will cause the new program address to be loaded into inverter 368. Therefore the execution of a branch instruction will cause the new address to be loaded directly from the ROM and from that point on, under normal operations, the program counter will be incremented from the new address. The next mode of operation is on the execution of a call instruction where the program counter must store its incremented address into one of the subroutine registers in 33. When a call is executed, line 357 becomes active upon b2 and allows the address from the ROM to be loaded into the program counter via line 356 and the remainder of lines 375. At the same time, the old address plus 1 which was contained in inverter 369 is loaded into the subroutine register 33-1 through device 373 which has been activated by line 362 which becomes low when the call instruction is executed. This allows this bit of information to be stored in the RAM cell 376. This RAM cell is identical to the one in U.S. Patent No. 3,958,818, assigned to Texas Instruments which is -hereby incorporated by reference. Concurrent with the old address being destroyed, the old address incremented is stored in the RAM and the new address is stored. The execution continues at the new subroutine address and this address is fed through the feedback circuitry as in a normal operation. When a return statement is encountered and executed, the old address incremented then stored in cell 376 is then loaded into inverter 369 through gate 372 which is activated by the return signal on line 361. On the execution of the next 2, line 358 activates device 370 and the incremented old address is then loaded into inverter 368. The determination of which RAM cell, 33-1, 33-2 or 33-3, is to contain the old program address is determined by lines 364, 365 and 366 which are output from the subroutine latches 34 to be discussed later. These three lines represent the three levels of subroutine capability available. A "1" in either 364, 365 or 366 will determine which of the RAM cells will contain and store the old incremented program address. The remaining mode of operation for the program counter is the initialization mode. During initialization line 363 becomes active thus allowing device 374 to ground the contents of inverter 368. Initialization is required to take such time as to allow inverter 369 to be initialized. This is accomplished through the feedback circuitry operation on line PCA0 through PCAS and the occurrence of 1 which in turn loads the incremented initialization address into inverter 369. Referring now to Figure 19, the feedback circuitry is made up of a set of complex gates 377, 378, 379 and 380. These gates function to feed the output of the program counter and provide the incremented signal on line 359 as previously discussed. 'ATOCS Figure 20 illustrates the subroutine latches 34 for CPU A. The subroutine latches 55 for CPU B are similar. Thus only subroutine latches 34 will be illustrated and discussed. Subroutine latches 34 contain three levels of subroutines. The highest subroutine level occupied is signified by this circuitry through lines 364, 365 or 366 outputting a "0" whereas the others output a "1". In other words, if level 1 is occupied, 364 will output a "0" and lines 365 and 366 will be "l". If level 3 is occupied, then lines 364 and 365 will be "1" and line 366 will be 11011. Upon initialization devices 382, 383 and 384 are activated from the initialize signal on line 363 thus grounding inverters 385, 387 and 389 causing the outputs of the subroutine latches 364, 365 and 366 to be #l",. Line 379 becomes active when a valid call has been executed. A valid call is defined as a call instruction occurring. and when the status line is high. When line 379 becomes active, device 395, 394 and 397 are activated. At that time, a "0" is loaded into inverter 385. The output of inverters 385 and circuits CL1A is then passed through device 398 upon the occurrence of < 4 and through gate 391 when > 2 goes low (when C1 goes low for CPU B) onto line 364 which cause the first level of subroutine registers to be addressed. The incremented program counter address is now copied into the subroutine Register 33. CLlA is a shift register latch known as a mster/slave register latch. The contents of inverter 385 is transferred into inverter 386 upon the occurrence of X5. The contents of 386 is the complement of the contents of 385. Upon the occurrence of & , the contents of 386 is then stored in 385 again. Upon the occurrence of another valid call, line 379 becomes low again activating device 395 Gate 381 becomes a ii1n because the output of inverter 386, 388 and 390 are not all "1". When level 1 is occupied, the contents of 386 is "0" and thus the activation of device 395 will cause a "1" to be stored in inverter 387. At this time 2 "0" is then stored in inverter 385. Therefore, the output of CL2A becomes a "1" and is transmitted through device 399 upon the occurrence of 4 and through gate 392 when 82 drops and line 365 goes low. Upon the occurrence of a third valid call line, 379 becomes low again thus activating device 397 which loads a "1" into inverter 389 and "O"s inveter 387, thus the "1" travels to the third level causing line 366 to be "1" in order to load the third subroutine RAMs in the subroutine register 33. If an additional call is executed, the circuitry will not change and the program counter will branch to the new call address. When a return statment is encountered, as in this case with all three levels occupied, line 378 becomes high, activating gate, 40i allowing the contents of inverter 389 to be grounded. Therefore, the output on line 366 will become non. Likewise when another return is executed, device 402 becomes active thus zeroing the contents of inverter 387 and causing line 365 to return to "on. A third return will cause line 378 to become low and device 396 to become active which zeros inverter 385 and thus the three latches will return to their original state. Additional returns will be treated as "No Opsn. CHAPTER ADDRESS REGISTER AND CHAPTER BUFFER REGISTER Figure 21 illustrates the chapter register 26 and chapter buffer register 39 shown in Figure 3b. Chapter register 26 and chapter buffer register 39 are dedicated to CPU A. Chapter buffer register 61 and chapter register 47 are dedicated to CPU B and are identical to the CPU A chapter registers. Referring now to Figure 21, the chapter register and chapter buffer register are shown in sections. The chapter buffer register is shown as 39-2 and 39-1 in the upper part of the drawing. Each section in the chapter buffer register is responsible for 1 bit of information to be transferred to the chapter register. Each' section is identical to the other, so therefore, only 39-1 will be discussed. Likewise in the bottom part of the drawing, the chapter register consists of two sections, 26-1 and 26-2, which are identical and therefore only 26-1 will be discussed. In 26-1 the actual storage of bit information in the chapter register is contained in inverters 425 and 426 which operate in a master/slave register latch similar to that discussed earlier. During normal operations, a signal from line 417 which corresponds to b2 (51 in CPU B) recirculates the data from inverter 425 into inverter 426. This is done through device 409 which is active when line 417 is low. The data is refreshed back into inverter 425 upon the occurrence of b 2 (i#Z in CPU B) causing the device 428 to-pass the information from inverter 426 to inverter 425. The output of the contents of the chapter register is available on line 424 which is the contents of the inverter 426. Likewise, for chapter register section 26-2, the output is on line 421. During normal operation the chapter address in inverter 426 is simply refreshed with inverter 425 and remains constant. During a branch operation, the new address must be loaded from the chapter buffer 39-1. The information in the chapter buffer register is contained in inverter 430. Inverter 429 is refreshed by inverter 430 during 1 (u2 for CPU B)' by device 431. During a branch operation, line 416 goes low thus activating device 408 allowing the address contained in inverter 430 to be loaded into inverter 426. The address that is originally loaded into the chapter buffer inverter 430 originates from line 402 which is the output of the page buffer. The transfer occurs when device 404 is active upon the execution of a TPC instruction, transfer of page buffer to chapter buffer instruction, thus activating line 433. The data-from line 402 is then refreshed again when u 2 for CPU B) activates device 431. When a branch occurs and the information in inverter 430 is transferred into the chapter address register and inverter 426. Line 415 becomes low during t2 1 for CPU B) of the branch operation; therefore, the information transferred from the page address buffer register into the chapter buffer register is inverted at first into inverter 429 and then inverted in inverter 430. Upon execution of a branchh instruction the contents of inverter 430 is loaded through device 408 during 52 into inverter 426 of the chapter address register. During a long subroutine call execution, the subroutine chapter must be loaded prior to the execution of the call instruction with the TPC instruction. This will cause, the subroutine chapter to be loaded into the chapter buffer inverters 429 and 430 as previously discussed. Upon the execution of the call instruction then, the address is the chapter address register inverter 426. During the call mode the chapter is loaded into the subroutine RAM via line 423 through device 411 which becomes active during the execution of the call instruction, thus line 419 is a "0" during #5 contained within the low time of 2. At the same time, line 416 is low thus device 408 passes the chapter subroutine address from inverter 430 into the chapter address register inverter 426. During the return mode the chapter address register is loaded with the contents of the chapter subroutine register via line 423 through inverter 412 and device 410 which becomes active when line 418 goes low as the result of the execution of the return instruction. This occurs during W2 (t1 for CPU B). The original address is thus loaded into chapter address register inverter 425 to be circulated into the chapter address inverter 426. In addition, the contents of the chapter subroutine register is loaded into the chapter buffer register through device 407 which becomes active during ithe execution of the return instruction. During initialization, the chapter buffer register 39 is set to "0" by activating line 420 which causes device 406 to input a nln into chapter buffer register inverter 429, thus causing a "0" to be loaded in the chapter buffer register inverter 430. The chapter buffer register data becomes "0". At the same time, line 420 causes device 427 to become active thus grounding chapter address register inverter 426 thus the output on line 424 will be "0". Lastly during a test phase, the contents of the chapter address register inverter 425 can be loaded from line 413 when device 403 becomes active. This allows the address to be loaded from the keyboard inputs during a ROM test. CHAPTER SUBROUTINE REGISTER Figure 22 illustrates chapter subroutine register 24 shown in Figure 3b and similar to chapter subroutine register 45. This chapter subroutine register is divided into two sections, 24-1 and 24-2. Each section of the chapter subroutine register is further divided into the three levels of subroutine. For section 24-1, the division of three levels become 24-1-1, 24-1-2 and 24-1-3. Each level is identical to the first level as section 24-1 is identical to 24-2. Therefore, only section 24-1, level 1 will be discussed, i.e., 24-1-1. The subroutine contains a RAM structure 442 and is similar to the RAM cell structure previously discussed. This RAM receives its input on line 423 from the chapter address register 425 previously discussed. This RAM cell is allowed to be loaded with this bit information when line 364 becomes low. Line 364 originates from the subroutine latch 34 as previously discussed. The RAM cell is recycled and the Write to cell time is# and Read from cell is Z4 upon lines 436 and 437 as shown. Likewise the RAM cell in 24-1-2 may be loaded when line 365 is low from the subroutine latch and section 24-1-3 may be loaded when line 366 is low. Only one of these lines, 364, 365 or 366, will be a "0" during a subroutine call as discussed previously. PAGE ADDRESS REGISTER AND PAGE BUFFER REGISTER Figure 23 illustrates the page address register 21 and page buffer register 35 as shown in Figure 3b and similar to page address Register 42 and page buffer Register 47. The page address register 21 can be divided into four sections, 21-1, 21-2, 21-3 and 21-4, representing the four bits of information contained in the page address register. Each section is identical and therefore only section 21-1 will be discussed. Likewise the page buffer register 35 can be divided into four sections, 35-1, 35-2, 35-3 and 35-4. Buffer registers 35-1 and 35-2 are identical. Buffer registers 35-3 and 35-4 differ from 35-1 and 35-2 in that the first two sections transfer their bit information into the chapter buffer register as previously discussed. Other than this small difference, these four sections are identical. Therefore, only 35-1 will be explained. In normal operation, line 417 becomes low and j(2 1 in CPU B) goes low, thus activating device 452. Device 452 is connected to inverter 455 and inverter 454 which# is connected to another device, 456. These four elements make up master/slave latch a as previously discussed. The actual contents of the page address register for this section is contained in inverter 454 and is updated from inverter 455. Therefore, when device 452 becomes active, inverter 455 updates inverter 454. During the occurrence of 8/1 2 in CPU B), device 456 then takes the information from inverter 454 and updates inverter 455. As long as the CPU A is in normal operation, the circular refreshing cycle will continue. For the proper execution of a long branch instruction, the address of the new branch page must have been loaded into the page buffer register 35. The load page instruction lowers line 433 which activates device 445 to input the information on line 464 into the page address inverter pair 446 and 447. The information contained in 447 is always updated with the contents of inverter 446 and inverter 446 is updated with the information in inverter 447 when Z1 is low (#2 in CPU B), thus activating line 462 which activates device 449. When the branch address is loaded, it remains in the page buffer register 35. The branch command is executed which activates line 416 and device 451. This in turn allows the information on the page buffer register inverter 447 to be loaded through device 451 into the page address register inverter 454. During the execution of a call subroutine instruction, the address of the subroutine page must have been loaded into the page buffer register 35 prior to the execution of the long call instruction. This is accomplished by the load page into buffer instruction, LDP, which activates line 433, thus activating device 445 allowing the forthcoming subroutine address to be loaded over 464 into the page buffer register inverter 446. Upon loading the new subroutine address into the page buffer register inverter 446, the page buffer register inverter 447 is updated from page buffer register inverter 446 and the cycle is refreshed through device 449 when ZI (Z2' for CPU B) on line 462 goes low. Upon the execution of the call instruction, line 416 becomes low thus activating device 451. Therefore, the new subroutine address contained in page buffer register inverter 447 is loaded into page address register inverter 454 through device 451. During R5 within 82 (El for CPU B), 419 goes low causing device 458 to be activated allowing the page address contained in inverter 455 to be loaded into the page address subroutine RAMs via line 460. The new page address loaded into inverter 454 of a page address register which is later output on line 461 to the ROM 6. Upon the execution of a return statement, the contents of the subroutine page RAM is Loaded back via line 460 into the page address register 21 and page buffer register 35. When the return instruction is executed, line 418 becomes low, activating device 457. Therefore, the address contained within the subroutine RAM is transmitted through inverter 459 and device 457 back into the page address register inverter 455 and through device 452 into inverter 454. The page address is loaded into the page buffer register inverter 446 through device 450 which is active during the return instruction execution that covers line 415. During initialization, the CPU A page address register state becomes 0000. The CPU A page buffer register contents becomes 0000. The CPU B page address buffer becomes 1111 and the CPU B page buffer register becomes 1111. During a test mode, the page address can be loaded via the keyboard. In particular, line 432 is low during the test mode, activating device 465 thus allowing the keyboard information contained on line 463 to be input into the page address register inverter 455. Therefore, the ROM can be read out through the ROM lines by specifying the page address using the keyboard. Lastly, the page buffer register section 35-1 and 35-2 can be loaded into the chapter buffer register39 via line 414 and 402 as discussed previously. PAGE SUBROUTINE REGISTERS Figure 24 illustrates the page subroutine register 23 shown in Figure 3b similar to page subroutine Register 44 for CPU B. The page subroutine register can be divided into four sections, 23-1, 23-2, 23-3, and 23-4, which contain the four address bits. All sections in the page subroutine register are similar therefore only section 23-1 will be discussed. Each section is in turn comprised of three subroutine levels. Since all three levels 23-1 through 23-3 are similar, only the first level, 23-1 will be discussed. Each level of each section is basically made up of a RAM cell 467 similar to the RAM previously discussed. The input to the cell and output from the cell pass over line 460 into the page address register 21. The determination of which cell contains the address to be loaded when a new address is to be loaded into the page subroutine register 23 is determined by the subroutine latch 34 which activates one of the three lines, 369, 365, and 367. When the line is activated the RAM cells in that level are activated and are allowed to receive and store the address from the page address register. Likewise when this line is low, the RAN can load the stored address into the page address register over the same line 460. For example, if the first level of subroutine is to be activated, line 369 will become low. Therefore when the subroutine call is executed and the address in the page address register is to be stored in the page subroutine register 23, the address for section 23-1 will be loaded via line 460 into RAM cell 461 since line 369 from the subroutine latch will be low. Likewise, when a return statement is executed and line 369 is low from the subroutine latch, the contents of RAM cell 467 will be loaded back into the page address register 21 via line 460. The RAM cell is read when is low and is written into when as is low. ^ Q2 for CPU B) is provided. to activate device 468 to discharge the RAM bit lines. THE RAM WRITE MULTIPLEXER Figure 25 illustrates the WRITE multiplexer 89 as shown in Figure 3a. The RAM multiplexer 89 can be divided into four separate sections, each section providing a line of information to RAM 81 on a set of lines 87. Likewise each section receives two inputs, one from the accumulator on line 96 and the other from the constant and keyboard logic on lines 95. Each section also receives one of four control signals on lines 475, 476, 477 and 478. Since all sections are identical, only section 89-1 will be explained. When the output of the accumulator 150 or 151 is to be stored in memory, the contents of the accumulator 150 or 151 is placed in section 89-1 of the WRITE multiplexer 89 onto line 96-1. A store command activates line 476 which in turn activates device 479 allowing the information contained on line 96-1 to be output onto line 87-1. Likewise when the contents of the constant keyboard logic is desired to be written into memory, the contents is placed on line 95-1 and upon execution of the CKBM microinstruction, which is the load constant into memory microinstruction, line 475 is activated which in turn activates device 484 allowing the contents of line 95-1 to be transmitted over line 87-1. For the set bit operations, line 477 and 478 are used. For set bit, line 477 is low and 478 is high. Line 477 then activates device 482 which inputs a Vss or "1" onto line 87-1 provided that the CKB 1 data coming into the cell is a "1' which will, in turn, be inverted to a non. The "0" turns on device 481 providing a complete path to ground from line 87-1. Additionally, it should be noted that only one bit may be set, i.e., 4 CKBI is nin then CKB 2, CKB and CKE b will be "0". When the reset bit is executed, line 477 becomes high and line 478 goes low. Device 485 is turned on from line 478 and device 480 is turned on by CKB 1 providing a path from line 87-1 to Vdd, resetting the bit to "0". Likewise only one bit may be reset per instruction. THE RAM Y DECODER Figure 26 illustrates the RAM Y decoder 79 as shown in Figure 3a. The RAM Y decoder receives four of the RAM Y register outputs, 83-1, 83-2, 83-4 and 83-8. Line 84 originates from the X register whereas lines 83-1 to 83-8 originate from the Y register 148 or 149. These lines are input into the RAM Y decoder 79 and becomes the data and its complement and are input into RAM 81. The RAM Y decoder can be divided into 16 sections, 79-1 to 79-16; each section is identical except for the gate code therefore only section 79-1 will be explained. The output from section 79-1 are two lines, 80-1 and 80-2. The output of the RAM Y decoder 79 consists of lines cof 80-1 to 80-32. Each of the inputs line 84 and lines 83-1 to 83-8 are coupled to the RAM Y decoder 79 through a true line and an inverter. In the case of the line 84, the input is on line 490 and line 491 through inverter 483. The actual decoding of the five main input lines is done with transistor devices, such as 481 and 482, by placing these devices in a position to be controlled by either the true line or the complement line in some specified combination. During \4 line 495 is active low and thus devices 496 and 497 pass their charge to ground. However, the address previously loaded into the circuitry 488 and 489 remain. At W5 devices 480 become active thus allowing the Vdd to pass through the selected devices similar to 481 or 482, depending on which of the lines 84 or 83-1 to 83-8 are active. Then during t6 from device 487 the addresses contained in the circuitry 488 and 489 are transmitted over line 80-1 and 82-2, respectively, to RAM 81. The output of the initial stage of RAM Y decoder 79-1 then are lines 493 and 494 which are input to two devices 485 and 486 which are gated-load amplifiers. A gated load amplifier is a device which will only transmit a valid signal to its output when the load is energized. Inverters 485 and 486 are used to transmit the address data from lines 493 and 494 into a circuitry 488 and 489. Circuit 489 is a mirror image or 488. Circuitry 488 and 489 retain the data transferred by lines 493 and 494 during the next decode phase consisting of Q4 and Mix5. RAM X CIRCUITRY Figure 27 illustrates the X register 99 as shown in Figure 3a. The X register contains three rotating registers as previously discussed in Figure 2. The X registers are loaded via lines 500 to 502 when 499 becomes active thus activating devices 513 allowing the lines to input into the rotating register. Since the operation of all three rotating registers are basically the-same, only the rotating register outputting line 84 will be discussed. The register 760 receives its input on line 500 which is input into inverter 505 through device 513 as previously discussed. When a4 occurs, the information in inverter 505 is transferred into inverter 506 through device 512. When S6 occurs, device 510 becomes active and the information in inverter 506 is then transferred to 507. This circular transfer of information continues as previously discussed for rotating registers. The output to line 84 is then maintained in inverter 508. For lines 94-1 and 94-2 the information is maintained on inverters 514 and 515, respectively. It should be noted that the register circuits on lines 501 and 502 differ from the above in that the output lines 94-1 and 94- are coupled to inverters 514 and 515. It also should be noted as previously discussed that line 84 goes to the RAM Y decoder whereas lines 94-1 and 94-2 go to the X decoder. Figure 28 illustrates the X decoder 88 and a section of the RAM 81. The X decoder consists of two lines, 94-1 and 94-2 entering the decoder and the two inverters, 520 and 521, coupled with these lines in order to generate the data and its complement such that the lines output are 85-1, 85-2, 85-3 and 85-4. This two to four decoding allows the lines such as 523, 524, 525 and 526 to act as a selector into the RAM 81 to select the bit lines to be accessed. When the bit lines are selected, the RAM outputs on lines 516, 517, 518, and 519 as shown. RAM The RAM 81, illustrated in Figure 28, consists of elements such as 522 which have been disclosed in U.S. Patent No. 3,919,181, assigned to Texas Instruments in an array 16 elements by 32 elements. The timing for the RAM involves #4, B5, and #6. During 86 the RAM bit lines are discharged. During 84, the following cycle, the RAM is read. 85 is the Write cycle where the RAM is conditionally discharged according to whether a "C" or a "1" is to be stored from lines 516 to 519. R REGISTERS Figure 29 illustrates the R register 77 with RAM 81 and input lines through the RAM 81. Register 77 consists of 16 sections. All of these sections are similar to the sections shown in 77-0. Therefore, only section 77-0 will be discussed. The register receives the data from line 537 which is termed the reset/set bus. This bus is activated by either device 534 or 533. When the set register command is executed, the line 527 goes low causing device 533 to become active, thus grounding the line 537. In a similar fashion, when the reset register instruction is executed line 528 goes low causing device 534 to become active and Vdd is coupled into the RS bus line 537. Device 535 is activated by line 536 which is 2 RAM discharge line. When the RAM is discharged 536 goes low activating device 535 thus discharging the RS bus line 537. Register section 77-0 inputs the RS bus along with the two address lines, 80-1 and 80-2. The RAM register is addressed by the Y decoder in such a manner that two address lines determine which register is to receive the bit information from the RS bus line 537. Due to the nature of the Y decoding circuitry, lines 80-1 and 80-2 will contain either a 11 or 10 or a 01: If the lines are 11, then that R register is not selected to receive the bit information from the RS bus line 537. However, if lines 80-1 and 80-2 are 10 or 01 then the circuitry 532 which is a wired OR couples the latch circuitry 531 to receive the input RS bus 537 that is clocked in at 85. Using this scheme only ope of the register sections in 77 may be loaded at any one time with the RS bus line 537 with the Y decoder 79. RAM REGISTER OUTPUT Figure 30 illustrates to RO output buffer and R1 output buffer. Register output buffers, RO to R13 are similar to that illustrated in RO. Therefore only the RO circuitry will be discussed. The register buffers for R14 and R15 are different since they are used in initialization and testing and will be discussed later. Referring to Figure 30, the circuitry for the buffer consists of two inputs, 78-0 and line 303. Line 78-0 is the input from the RAM register 77-0. Line 303 is an initialization line. When the data is transmitted over line 78-0, it is input through an inverter 548 and activates device 549 causing the output voltage to go to ground, thus deactivating device 550 and causing a voltage of Vdd to appear through line 547 onto output pad 546 for RO. During initialization, line 303 becomes active causing device 545 to become active. In addition line 544 and input line 78-0, coupled through inverter 548, are input into NAND gate 543 and into device 551 potentially passing Vdd which causes device 550 to become active thus line 547 will go to ground instead of Vdd. Therefore the register path 546 will be initialized to a n 0 Figure 31 illustrates the circuitry for the register buffers for R14 and R15. R15 is identical to R14 so only the circuitry associated with R14 will be explained. The circuitry in R14 is similar to the circuitry in RO in that the input for the register is coupled to line 78-14 and into an inverter 552 to activate device 553. This, in turn, causes device 555 to be inactive allowing the line 542 potential to be Vdd. Therefore Vdd appears on line 542 register pad 541 causing a #on to be output. If the register data is "1", then line 78-14 will couple a "1" into inverter 552 which will couple a "1" into device 553 causing the device 553 to be inactive. Therefore, Vdd will activate device 555 thus grounding line 542 and coupling a "1" into register pad 541. In addition to this circuitry, R14 contains line 302 which is an input line from pad R14. This input pad is used during tests. During initialization, R14 will be initialized by line 303 which is then coupled into gate 539 via line 538 along with the data. If the data is "1", then the line 556 will be "0" and the output of the NAND gate will be a "1". If, however, the data is "1" and the line 303 is "1", the output of the NAND gate will be a "0" thus activating device 554. The line 303 will activate device 540 thus causing the gate of device 555 to go to ground inactivating device 555 and coupling a non through line 542 onto the register pad 541. ROM Y DECODER Figure 32 illustrates the ROM Y decoder 8 as shown in Figure 3b. The ROM Y decoder receives 6 inputs lines 12 and outputs 64 lines 7 to the ROM array 6. In Figure 32 the input lines are numbered 12-0 to 12-5 and represent the 6 bits of the multiplexed program counter, either for CPU A or CPU B. Each of these lines is input to a section similar to Section 561. The line in 561 12-0 is divided into true and complement line as shown. The output of 561 is similar to line 573 and 574 for line 12-5. The function of the ROM Y decoder is to take the 6 inputs and decode them into 1 of the 64 lines 7 for the ROM array. Line 573 is coupled to the device 568 of the gate circuitry 570. Line 574 is coupled to device 569 of circuitry 570. Line 571 and 572 are outputs from the circuitry 570 and couple through devices 564 and 565 respectively to the circuitry including capacitors 562 and 566 and devices 563 and 567. In the ROM Y decoder, there are 64 capacitors similar to 562. However, in this figure only four are shown. These capacitors are termed "BOOT STRAP" capacitors and provide the charge for the gate which will drive the Y address into the ROM 6. During 04, line 558 becomes active, thus providing charge to the BOOT STRAP capacitors. During 05 all but one of the 64 capacitors will be selectively discharged. This is accomplished by use of the true and complement lines 573 and 574 for all the addresses 12-0 through 12-5. When 04 is inactive and ground, active lines such as 573 would provide a path to ground through device 568 for capacitor 562 since 06 via line 559 will be active and thus device 564 will allow the passage of the charge from capacitor 562 through any path to ground. If, however, line 573 was inactive, then line 574 would become active thus activating device 569 and thus discharging capacitor 566 through device 565. Therefore, since either line 573 or 574 will be active during the period of 5, 32 of the 64 capacitors will immediately be discharged. Circuit 570 is repeated for 64 rows even though only 2 rows are shown. All rows will connect to lines such as 571 and 572. To discharge the remaining 31 capacitors, a path to ground is provided through one of the remaining 5 decode devices. In other words, the 4 devices within circutiry 570 will combine with either of the devices such as 568 or 569 depending on which line is not active to provide a path to precharge both capacitors across the row of lines 571 or 572. For the one capacitor that will remain charged, none of the devices in that row will provide a path to ground. This particular row is, of course, determined by the address on lines 12-0 to 12-5. Therefore at the end of #5, only 1 of the BOOT STRAP capacitors will remain charged. Then at #6 line 560 will become active thus activating one of the devices such as 563 to drive the line charged by the BOOT STRAP capacitor into the ROM array 6. Therefore, the 1 of the 64 lines determined by the multiplexed program counter address is selected. ROM PAGE DECODER Figure 33 illustrates the ROM page decoder 10 as shown in Figure 3b. The ROM page decoder consists of 6 sections shown as'596 through 601. Sections 596 and 597 are the same, but are different from the other four sections, 598 through 601. Section 596 is shown as consisting of two BOOT STRAP capacitors 590 and 591. These BOOT STRAP capacitors provide extra charge for driving the devices in the ROM. This is required for the ROM X0 line 9-0 and the ROM X1 line 9-1 as will be shown. In Section 596, line 9-0 is divided into a true and complement line, the true being 593 and the complement line coupling through inverter 592; therefore, either the true or the complement line will be active for a selected address. The selected address will charge either capacitor 590 or 591 when the 4 line is inactive, allowing for a fast charge on line 607 or 608 when# iR is active. Sections 598 through 601 are similar and therefore only 601 is shown. Section 601 is coupled to an input ROM 5 via line 9-5 or line 604 which is coupled through device 603 to produce line 605 and line 606 which has been coupled again through another inverter 602. The inverter 603 is provided for driving purposes. The lines ROM XO through ROM X5 are the page and chapter address of the instructions to be accessed. ROM SENSE AMPLIFIER Figure 33 partially illustrates the ROM sense amplifier 710 which drives the ROM output lines 11. Figure 33 shows the ROM sense amplifier 710 in Sections 710-0 to 710-6. Section 710 is also illustrated in Figure 34a. Section 710-0 is unique from the other sections 710-1 to 710-7. As shown the ROM output in Section 710-0 is coupled through two inverters, 589, provided for driving purposes. Device 588 and device 587 are used during the testing sequence to zero all the outputs from the ROM. Lines 11 contain inverted ROM data. Device 588 traps the ROM data when S6 is low. Device 587 zeros the output of the section when the random memory test is being conducted. Line 592 grounds this one input 750 during the initialization forcing a "0" on line 11-0 which will become a n1n on the RQ line of the instruction bus. During normal operations, the ROM which is precharged during h4 will be read in Q6 therefore device 588 will become active allowing data to flow from the ROM through inverter 589 into inverter 590 onto line 11-0. Referring now to Figure 34a, section 710-7 is illustrated. As mentioned earlier, Section 710-7 is identical to Sections 710-1 through Section 710-6. In Section 710-7 the ROM is output through inverter 581 through device 582 which become active during #6 and through inverter 584 onto line 11-7. Device 583 is provided to zero the ROM complement output during the test sequences as discussed earlier. ROM Figure 34a also illustrates the Read Only Memory (ROM) array 6. The ROM is precharged during #4, and read during 6. The charge is provided by devices 622 which are connected to Vdd and provide power to the ROM via lines 616. During #4, line 620 becomes active thus allowing the bit lines within the ROM to be charged through device 621. A typical device in the ROM is device 613. In the ROM the cells containing devices such as 613, when addressed, will provide a discharge, where there is to be no discharge at that address, no device such as device 613 will be provided. The address lines of the page decoder shown as 580 are shown for 1 of the 8 sections of ROM 6. All other 7 sections of the ROM are similar. In the section shown, the X lines are divided into 3 sections, 577, 578 and 579, which represent the 3 chapters that may be addressed by the page decoder 10. During BX power is provided to the address lines 580 such that the address devices will selectively provide paths to ground to discharge the selected ROM cells. The lines in 580 consists of pairs of true and complement of the X address as previously discussed. The top four lines , OX, 1X and 1X select the first two major sections of the ROM address and are coupled to the several transistor devices as shown. When one line is active, the other line will be inactive; thus, one device such as 614 when active will provide a path to ground thus discharging the selected ROM bit line cell. These two sets of lines UX, OX, 1X and 1X provide the discharging of the ROM bit lines. Lines 2X, 2X through 5X and 5X provide the addressing of the cells for the specified ROM output line. For example, if line CX is active, then line OX will be inactive, therefore device 614 and device 615 will be inactive. Device 614 will provide a ground path for bit line 753 and ROM bit 613. This path will continue through device 754 to ground 611. Figure 34b illustrates the timing of the Read Only Memory (ROM). The fall of 81 initiates the selection of the ROM instruction for CPU A. Specifically the address for the ROM location is selected and driven for the ROM X most significant bits for b4 and E5 as shown in interval 711. Also during the fall time for 'Q4, 713, the bit paths and the Y decode circuitry is precharged. During the same time the address lines for the X lines of the Read Only Memory least significant bits are discharged. At the rise of #, 714, the boot strap capacitors in the Y decoding circuitry are discharged and the address lines for the.ROM X least significant bits are driven, 714. At the fall of the b6, 715, the ROM Y address lines are driven-and the ROM word is sampled in the sense amplifier. At the fall of #2, 712, the fetching cycle for CPU A ends and the fetching cycle for the CPU B begins, repeating the > 4, 5 and 6 sequences for CPU B. INITIALIZATION CIRCUITRY Figure 35 illustrates the initialization circuitry for the multiprocessor system. When power is first applied, circuitry .654 is activated which transmits a signal, PUCA, or the power up for the CPU A when t3 goes low. This signal is output from inverter 693 and is input into complex gate 653. Likewise when g goes high, device 69x is activated and the power up signal for the CPU B is transmitted from inverter 694 into complex gate 686. Complex gate 655 also receives inputs from the initialization A pad 650 and the initialization B pad 651 together with inputs from inverter 693 in order to set the valid condition for test. Upon power up the output of gate 653 zeros the registers R14 and R15 which are also used in test modes. The INyTR signal originating from gates 655 is used to alter registers R14 and R15 from output to input and enable the test modes. The INITP signal output from complex gate 653 is used to initialize the register for pads RO to R13. The power up procedure initializes both CPUs and starts the CPUs according to the system timing diagram in Figure 3d. After power up, if only one CPU is to be initialized only one INIT pad should receive a low to high transaction signal. In other words, if the user desires to initialize CPU A but allows CPU B to continue running, then CPU A would be initialized setting pad 650 to a logical "ln. The same is true for initializing CPU B in that pad 651 would receive the logical "1" signal. The initialization of one CPU and not the other CPU or the initialization of the CPUs together with some testing mode specified with R15 and R14 would result in the output of gate 653 being a "0" but the initialization of both CPU A and CPU B would result in an output from gate 655 which would allow inputs from the two registers, R14 and R15, to be input into gates 669 and 668, respectively. The devices 681 and 682 clock in the initialization signals into the CPUs at the proper time. Device 681 receives a signal when t4 occurs during '63. Device 682 is activated when #4 occurs and t occurs receiving that signal through inverter 667. Gates 687 and 683 receive the initialization signal from the CPU A pad 650 and CPU B pad 651, respectively, together with indication of the initialization inhibit during test from gate 680. The output of gate 686 is the initialization signal for CPU B. The output of gate 689 is the initialization signal for CPU A. The initialization circuitry in conjunction with R14 and R15 initiates the test conditions for the multiprocessor system. Three tests are provided: the ROM test, the random logic input test, and the random logic output test. To specify a test, the user inputs a combination of "lns or 10ns into R14 and R15 as inputs. As discussed earlier during one of the initialization modes, R14 and R15 become input buffers rather than their normal function as output buffers. To begin the ROM test, a "1" is input into R14 and a no n is input to R15 and both initialization pads 650 and 651 must receive "l"s. During the ROM test, the contents of the ROM 6 are transmitted over the instruction bus and output to the user through the output buffers 165. To accomplish this, the instruction PLA as shown in Figure 8b receives the output ROM signal which inputs the ROM data onto the CPU A output bus which is in turn routed into--the output buffers 165. During the execution of the ROM test, an inhibit signal must be generated to inhibit the execution of any branch or call instructions. This is accomplished in the initialization circuitry through gates 696 and 695. The "1" from the register R14 is input into gate 669 together with a signal test initialization and the output of gate 669 is input into gate 684 together with the non that is input into Register 15 to define the ROM test. The output of gate 684 signifies the ROM test to be performed. This is then input into gate 695 together with the signal that the initialization circuitry is not in power up. The output then of gate 695 is input into gate 696 together with the clocking to produce the inhibit signal. This test enables the user to step through all the instructions contained on the ROM in this multiprocessor system. To execute the random logic input test, both pads 650 and 651 must receive "l"s and pads R14 and R15 must receive nuns. The random logic input test allows the microprocessor system to be executed with instructions from outside of the immediate system by allowing the output buffer pads 165 to be used as inputs for execution of these instructions from some outside source. The instructions are executed as those instructions would normally be executed if contained in the ROM 6. The "1" in pad 15 and the lllfl in the pad 14 are input into the initialization circuitry through gates 668 and 669, respectively. These generate signals which are then input into gate 685 to produce a jam signal. The jam signal is used to switch the 0 - output buffers 165 into an input mode and to drive the instruction bus 71 from the 0 output buffers 165. It is also used to switch the circuitry for the status output pad 157 to output the status for both CPU A and CPU B. This capability is quite unique in that it allows the user to test the microprocessor system with an externally defined sequence of instructions. External memory access is initiated by synchronizing the external memory system with phase clocks cai through \6) of the multiprocessor system. The RA input 104 and KB input 155 are used as the instruction input. KA input 104 and KB input 155 must be multiplexed to allow the CPU A input and CPU B input functions to be accomplished during the same macroinstruction cycles. It should be obvious to one skilled in the art that this is accomplished by adding transfer gates to the KA input 104 and KB input 155 circuitry which connects the KA input 104 and KB input 155 circuitry to the instruction bus 71. These transfer gates are controlled by the external memory clocks and a synchronizing input signal to allow the inputs to the instruction bus to be multiplexed with the inputs to CPU A and CPU B. In addition to the synchronizing input signal and the phase clocks, the external memory system must also include a program counter and page register with associated controls. The output test 2 from the initialization circuitry also serves to remove the ROM from the instruction bus and thus preventing any of the instructions from the ROM to be transmitted on the instruction bus. If the user inputs a "0" and "1" on pads 14 and 15, respectively, and a "1" into the two initialization pads 650 and 651, then the random logic output test will be specified. The object of the random logic output test is to allow an output through the CPU A 0-output buffers 165 while the CPU is executing instructions that have been input on those same set of lines. This is accomplished by first performing the random logic input test and inputting an instruction into the CPU for execution and then forcing the CPU into an output mode with an output instruction and then changing the initialization and test circuitry to perform the random logic output test, allowing the output buffers 165 to transmit the results of the instructions that had been previously executed with the random logic input test. The non and "1" input into R14 and R15 are entered into the initialization circuitry through gates 669 and 668', respectively. Gate 668 affects the TEST 2 signal which disables the JAM signal in order to allow the O-output buffers 165 to be used as inputs. During the execution of the random logic test, both input and output, the 86 time slot is used as the dead time allowing the toggling between the random logic input test and the random logic output test. Figure 36 illustrates the configuration of a two player game apparatus including a player one input shown as the player one keyboard 800, a player two input shown as player two keyboard 801, three displays, 802, 803 and 804, all connected to the electronic digital processor system microprocessor chip 1. The input from the player one keyboard 800 to the microprocessor unit 1 is shown as the signal group 2 which corresponds to the signal group for the central processing unit A in Figure 1. Likewise, the input for central processing unit B is shown as 3, corresponding to the central processing unit B inputs in Figure 1. It should also be noted that the same signal lines provide output to the player two display 804, further including the SB line as described previously. The outputs for the central processing unit A is shown as signal group 5 and is coupled to the player 1 display 802. The R outputs or register outputs are shown as signal group 4 and is coupled to the common game display, 803'. In this configuration each central processing unit is dedicated to the update of the display -on the player keyboard and also an individual player display showing to the player that player's individual status. In addition, both central processing units provide the output to the game display 803. In this configuration it is intended that each player is allowed to see that player's individual player status and the common display. Therefore, player 1 should not be able to view the player 2 display 804. Since both central processing units access the same read-only memory and the same random-access memory, both central processing units can execute the game algorithm from the same read-only memory while storing the individual player's data in the RAM that is partitioned for that central processing unit. This arrangement allows for the simultaneous and independent execution of the same game algorithm by two different players. While the execution of these algorithms are independent, these algorithms are permitted to output to a common game display 803. It is this common game display 803 that informs the players of the game status, or in other words, the status of the algorithms of both central processing units. Figure 38 illustrates the two game algorithms. The algorithms for CPU A includes a set of instructions to scan the player 1 keyboard and thus input data from the player 1 keyboard. While this embodiment illustrates the player 1 input as a keyboard, it should be obvious to one skilled in the art that other forms of inputs beside a keyboard may be used. The inputs from the player 1 keyboard are then placed in memory for the execution of the algorithm which is the next block in sequence. As a result of the execution of this algorithm, the output data is updated. A third block provides for the updating of the displays with this algorithm output. In this particular embodiment, only the player 1 display is updated by the execution of the algorithm in the CPU A. Finally, a timer is updated. The timer is optional and provided to signal the exploration of time for a player or to shut down the game apparatus when not in use. The algorithm for CPU B includes a scan of the player to input keyboard. Next, the data that is input is placed into memory for the execution of the player 2 algorithm. The output of this algorithm is then provided to the individual player display as in the CPU A configuration. In addition, CPU B is to provide data provided by CPU A and CPU B to the common game display. This is accomplished by taking data from the CPU A portion of RAM and data from the CPU B portion of RAM and outputting that data to the R register as shown in Figure 3A block 77 onto the signal lines 4 as shown in Figure 36 to the common display 803. As illustrated in Figure 38, the execution of the CPU A algorithm and the CPU B algorthim are continuous and simultaneous. While both central processing units may use this same algorithms contained in the ROM 6 in Figure 3B, these two central processing units are independent in that they are storing data in their individual partitioned locations in the RAM 81 as shown in Figure 3A. The time division for the execution of these algorithms is shown in Figure 38 as time slots, T1 through T4. Figure 37 illustrates another configuration of the two player game apparatus. Like the configuration in Figure 36, the configuration of Figure 37 includes a player 1 keyboard 805 connected to CPU A; a player 2 keyboard 806 connected to CPU B; and 3 games displays, 807, 808 and 809. The difference in the Figure 37 configuration is that all three displays are output from the register outputs over the signal lines 4. The output for the individual CPUs are used only to update what displays exist on the player keyboards. This configuration would be appropriate when the individual player displays are fairly simple, such as a small number of discrete LED lights together with a fairly simple game display. The software for the configuration in Figure 37 is shown in block diagram form in Figure 39. Note that Figure 39 is similar to Figure 38. For CPU A the first block describes software that is used to scan the player 1 keyboard for input data. This data is placed in the RAM for execution of the player 1 algorithm as specified in the second block. The third block describes the software that is used to take the algorithm output data from the RAM and display that data on the player 1 display. Likewise, the last block takes data from the RAM and displays the data on the common display through the register outputs as previously discussed. Likewise, for CPU B the first block consists of reading the player inputs; the second block consists of the execution of the player algorithm using input data stored in the RAM and outputting data from the algorithm to the RAM; updating the player 2 display from the output data contained in the RAM and updating the common display. Like the software in Figure 38, the software in Figure 39 is executed simultaneously and independently as shown by the timing nomenclature T1 through T4. It should be obvious to one skilled in the art that the configurations for the player outputs may be modified using the capabilityof the electronic digital processor system 1 in figure 37, that is, an individual CPU output may feed 1, 2, 3, or more displays, depending upon the complexity involved. Of course, the same is true for the register output. In addition the unique feature of this apparatus provides for the simultaneous and independent execution of game algorithms. However, the execution of the game algorithms may be made nonsimultaneous and non independent by the appropriate program contained within the read-only-memory. FUNCTIONAL APPARATUS CONFIGURATION An application of the multiprocessor system is illustrated in Figure 40. Specifically, this application involves the reading of input data from an input source 1805, updating the input source display to acknowledge receiving the input data, executing an algorithm and displaying the results. In this application, the display apparatus 1806 requires frequent refresh updates as with a liquid crystal display. Figure 40 illustrates the interface of the input apparatus 1805, the display apparatus 1806 to the multiprocessor device 1. CPU A is dedicated to scanning the input for input data, updating the input device 1805 to acknowledge the reception of input data, and the execution of the algorithm contained in the read-only memory ROM and storing the results of the algorithm in RAM. CPU B is dedicated to updating the display apparatus 806 with the output of the algorithm which has been placed into the RAM by CPU A. CPU B simply reads the same RAM locations as written into by CPU A and uses this information to update the display through the CPU B output. Note in this configuration, the register output or common output for the multiprocessor system is not utilized. Figure 41 illustrates the software configurations for both CPU A and CPU B. In CPU A the first block input data contains software that scans the input apparatus 1805 for input data and acknowledges the input through the CPU A output register. The next block execute algorithm contains the actual algorithm to be executed using the data obtained from the input apparatus. The block for the CPU B algorithm is simply the software to display output data and continuously refreshes the display 1806. As previously discussed in Figure 40, the output data is provided in the RAM that is accessed by the CPU B software and this data is output to the display. Figure 41 illustrate that CPU A and CPU B software are executed simultaneously. Stringent requirements of the display apparatus upon the microprocessor chip are-easily met by this configuration which dedicates a CPU to the display. Other embodiments of this invention are possible and should be apparent to those skilled in the art. Two such further embodiments are illustrated in Figures 42 and 43. In Figure 42, the display apparatus 1807 receives inputs from both the CPU B output register and the common register output. As discussed previously, the common register output, R output, is an output device that is addressable by both CPU A and CPU BW In the configuration illustrated in Figure 42, CPU A can be totally dedicated to receiving inputs from input apparatus 1805, acknowledging the inputs through the CPU A output, and executing the algorithm. CPU A may also provide outputs to the displays 1807 through the R output register output. The CPU B software may still be totally dedicated in providing output data to the display apparatus. CPU B may output this data either through the CPU B output or through the register output as can CPU A. In Figure 43 the display apparatus 1808 is connected to both the CPU A output, CPU B output, together with the register output or R output. In addition, CPU A output is connected to the input apparatus 1805 as before. In this configuration, the CPU A software would scan the input apparatus for input data, acknowledge the input data through the CPU A output and be able to provide data to the display through either the CPU A output or through the R output. The CPU'B software would remain dedicated through the display and provide data through the CPU B output or through the R output interfaces. It should be noted that the differences between the three configurations is the amount of software in CPU A that is dedicated to outputting data to the display; therefore, display apparatus with stringent requirements for refreshing would be easily interfaced to the disclosed multiprocessor system that can completely dedicate one CPU for display computational support from a second CPU. It should be noted that in both Figures 42 and 43 the display 1807 can consist of a dot matrix liquid crystal display device connected to circuit devices that drive the liquid crystal display, such as the HLCD0538 and HLCD0539 produced by Hughes. To interface with these devices, the R outputs on lines 4 would be used to output data and the CPU outputs on lines 3 and 5 would be used to output control signals. ELECTRONIC TELEPHONE CONFIGURATION A configuration using the multiprocessor system is illustrated in Figure 44. This application is the electronic telephone. The multiprocessor system 1 is shown connected to a keyboard device 2806 through the CPU A input channel marked 2. The keyboard device 2806 is a keyboard device containing the digits 0 - 9 plus (*) and (t) as in a normal telephone touch-tone pad. The keyboard is interfaced to the CPU such that it will input each number individually through the CPU A input port. In addition, the CPU A output is connected to keyboard 2806 through lines 5. This allows the numbers input into the CPU A to be acknowledged through the CPU A output port. Traditionally, this has been done by sounding and tone, but this could also be done in another appropriate manner such as turning on selected lamps. The multiprocessor system is also connected to the telephone line interface device 2809 via line 3a to CPU B. The telephone line interface device simply provides the interface to the existing telephone line and allows the processor to answer the telephone by activating the audio line and activating the speech synthesis device 2807 which is also connected to the multiprocessor system. Through the same control lines, the multiprocessor system can also deactivate the audio line and effectively "hang up" at the conclusion of the call. the multiprocessor system 1 is also connected to a speech synthesis 2807 through'the register output by lines 4. The speech synthesis device is a device similar to that disclosed in U.S. Patents 4,209,836 that have predetermined words stored for electronic reproduction when the device is activated. The function of this device is to tell the caller that the party that he/she has called is not available, and to please leave a recorded message, or if certain additional sensors to be discussed later are connected, to give the party at the other end of the telephone line certain specific messages. The speech synthesis device in the configuration of Figure 44 controls the telephone line interface via line 2811 and also provides an audio input to the telephone line interface via the same line. The audio line is for transmitting the message from the speech synthesis device to the caller. The control line is to enable and disable the audio line of the telephone interface. Also connected to the multiprocessor system 1 is a message recorder 2808 connected to the CPU B output port via line 3b. The message recorder is a standard type tape recorder that is activated by the multiprocessor system to record messages from the caller. This is accomplished by activating the message recorder via lines 3b and then allowing the audio portion to be input via line 2810 from the telephone line interface. At a certain predescribed time, determined by the user, the message recorder will be turned off by CPU B and in addition the telephone line interface audio line will be disconnected via line 2811. This configuration allows the user to program the multiprocessor system 1 to store frequently used telephone numbers by placing these numbers into the keyboard for storage in the multiprocessor memory RAM. In addition, the user may use the keyboard to activate the message recorder to playback messages that have been recorded. The user may additionally use the keyboard to program the electronic telephone speech synthesis device to playback certain messages when the telephone is being answered. Lastly, the user may program the electronic telephone through the keyboard 2806 to allow incoming calls to come through or in other words, not to answer the phone, allowing the user to answer the phone. Referring to Figure 45, an electronic telephone is shown which includes the repertory dialer 2812. As before, the multiprocessor system 1 is connected to the keyboard 2806 via the CPU A input lines 2 and via the CPU A output line 5. CPU B is connected to a telephone line interface 2815 through the CPU B input line 3a. The CPU B output port is connected to a message recorder 2813 and a speech synthesis device 2814 via lines 3b. The multiprocessor system register outputs, R output, are connected to the repertory dialer 2812. The repertory dialer is connected to the telephone line interface via lines 2818 which include both audio and control lines. The speech synthesis device is also connected to the telephone line 2815 via line 2816 for an audio transmission. The message recorder is connected to the telephone line interface 2815 via line 2817 for audio reception. This configuration in Figure 45 functions in a manner similar to that of the configuration in Figure 44. However, in this configuration the repertory dialer provides the dial tones for the telephone line interface 2815. The repertory dialer also has the capability to store external from the multiprocessor system 1 a number of frequently called telephone numbers. Therefore, the user may store some number in the multiprocessor system 1 memory RAM or telephone numbers in the repertory dialer memory 2812. When an incoming call is detected via CPU B, the control line 2818 is activated through the register output through line 4 and the repertory dialer 2812 to activate the audio portion of the telephone lines. At this time the speech synthesis device 2814 is activated by the CPU B output through line 3b. To output the predetermined speech synthesis message over lines 2816 into the telephone line interface 2815 to alert the caller that they are to leave a telephone message. After the speech synthesis device message has been transmitted to the caller, the message recorder 2813 is activated by CPU B through the CPU B output via line 3b in order to allow the caller to record the message over the audio line 2817 into the message recorder 2813. At the end of the user prescribed time, the message recorder 2813 is inactivated by the CPU B output port through line 3b. At the same time, a multiprocessor system deactivates the telephone audio line via the control line 2818 from the R output through line 4 and the repertory dialer 2812. Keyboard input 2806 operates as in the configuration in Figure 44. The electronic telephone configuration in Figure 46 is similar to that in Figure 44 with the exception of an additional keyboard input display 2819 connected to the CPU A output via line 5. The keyboard input display 2819 can be either a light-emitting diode display or a liquid crystal display and functions to display the numbers that have been input through the keyboard input. In addition, this display may display the numbers that have been stored into the multiprocessor system 1 RAM. The remaining operation of this configuration is similar to that configuration described in Figure 44. The electronic telephone configuration shown in Figure 47 is similar to the electronic telephone configuration in Figure 45 with the exception of the additional input display 2819 connected to the CPU A output via line 5. As previously discussed, the keyboard input display 2819 provides the user with a visual read out of the telephone numbers that have been input through the keyboard 2806 into CPU A via line 2. As before, display 2819 could be either a light-emitting diode display or a liquid crystal display. While in this configuration, the display 2819 could display numbers that have been stored in the multiprocessor system 1 RAM, the display 2819 would be unable to store numbers that have been stored in the repertory dialer 2812. With this exception, the configuration shown in Figure 47 would function effectively the same as the configuration in Figure 45. The electronic telephone configuration shown in Figure 48 is similar to the electronic telephone configuration in Figure 47 with the addition of household sensors 2820 that are input into the CPU B via line 3a. The household sensors 2820 may consist of a fire detection device, a security intrusion device or a device that is activated by some remote control. Each device would have an individual input into CPU B. The device input would active a specific function within the electronic telephone. For instance, if the fire detector, or smoke detector was to become active, CPU B would receive signals from lines 3a from the sensor 2820 and would activate the repertory dialer 2812 through the register outputs via line 4 to dial the fire department or alternatively, the fire department number would be stored in the multiprocessor 1 RAM and would be computer controlled dialed through the repertory dialer 2812 via the register outputs through line 4. The audio tone from the repertory dialer would be the touch tone sounds representing the fire department telephone number as is conventionally done in touch tone telephones. The repertory dialer would activate the audio portion of the telephone line via line 2818 through the telephone interface 2812. After this has been accomplished, the speech synthesis device 2814 would be activated by the CPU B via the CPU output and'line 3b to repeat a message listing the fire situation and the address of the user in order that the fire equipment may be dispatched. This message would be repeated several times, determined by the user's program. In a similar manner, the security intrusion device would input a signal into CPU B when activated causing the repertory dialer to ial the police department and a message to the police department would be produced by the speech synthesis device 2814. Additionally, a sensor that would be activated by remote control device would be included in the household sensor 2820. Upon activation of this remote control device, the CPU B would active the repertory dialer to dial the number of a physician and the speech synthesis device 2814 would repeat a message alerting the physician to a medical emergency at the user's address. All these functions would be made possible by the electronic telephone configuration illustrated in Figure 48. Figure 49 illustrates a flow chart of the software that would be contained in both CPU A and CPU B. While this flowchart is abbreviated, it should be obvious to one skilled in the art what the contents of each of the blocks in the flowchart would be. The CPU A software would simply monitor the keyboard input and upon receiving an input determine whether the repertory dialer is to be activated and would display the number that was input onto the display. As previously discussed, if the repertory dialer was activated and contained a number not stored in the computer multiprocessor system memory, then the display would not display the number that was actually being called. However, if the number had been stored in the multiprocessor system RAM, then the number would be displayed' to the user. CPU B software monitors the telephone line interface and controls the speech synthesis device and message recorder. If an incoming call is detected, then the speech synthesis device control line would be activated to enable the audio portion of the telephone line as previously discussed. The software would then activate the message recorder at the end of the speech synthesis message. At the end of the user's specified time, the recorder would be unactivated, and the telephone audio line would be inactivated via software control. If there was no incoming call, then CPU B would scan the household sensors. If a household sensor was active the CPU B would actuate the particular repertory dialer telephone number specified in the user program to be activated upon the reception of an active signal from that selected sensor and furthermore activate the specific speech synthesis message called for in the program. If none of the household sensors were found to be active, then the program would continue to loop monitoring for incoming calls or activation of any household sensors. TABLE I TABLE OF MICRO INSTRUCTIONS. STO ACC to MEM; applied to the write control 89, the four-bit output from the accumulator 150 or 5 191 is applied by the write logic 89 and line 87 where it is written into the current addressed word location in the RAM; CKM CKB to MEM; the four bits on CKB output lines are applied via write logic 89 and lines 87 where it is written into the currently addressed word location in the RAM; CKP CKB to +AU; the four bits on CKB output lines 108 are applied to the positive input 123 of the adder 125 by input selector 119. YTP Y to +AU; the four bits on the output 83 of the Y Register 148 and 149 are applied to the positive input 123 of the adder 125 via input 107 and P input selector 119. MTP .MEM to +AU; the four bits at the memory output lines 109 are applied to the positive input 123 of the adder 125 by the output selector 119. ATN ACC to -AU; the contents of the accumulator 150 or 151 are applied via lines 114 and 112 to the negative input 124 of the adder 125. NATN ACC to -AU; the complement of the accumulator 150 or 151 is applied via lines 114 and 113 to the negative input 124 of the adder 125. MTN MEM to -AU; the four bits of the then-current word and page address in the RAM 81 appearing on the memory output lines 110 are applied to the negative input of the adder 125 by the negative input selector 120. 1STN 15 (-1) to -AU; a constant 15 or hex F is applied to the negative input 124 of the adder 125; this is used in subtraction by two's complement addition, or in compare operations. CKN CKB to -AU; the four bits on the CKB output lines ill are applied to the negative input 124 of the adder 125 by the input selector 120. NE COMP to STATUS; the compare output COMP if the adder 125 is applied by line 128 or 129 to the status circuit 127 or 126. C8 CARRY 8 to STATUS; the carry output from the MSB of the adder 125 is applied via line 128 or 129 to the status circuit 126 or 127. CIN Carry In to AU; the carry input CIN on the line is allowed to be applied to the carry circuit of the LSB of the adder. AUTA AU to ACC; the output of the adder 125 on the four lines 130 is applied to the input of the accumulator register 150 or 151. AUTY AU to Y; the output of the adder 125 on the four lines 130 is applied to the input of the Y address register 148 or 149. STSL Status to status latch 143 or 144 upon execution of the YNEA instruction. If the Y register 148 or 149 is not equal to the accumulator 150 or 151, the status latch 143 or 144 is set to logic "1". If the result is equal, the status latch 143 or 144 is set to logic non. TABLE II THE INSTRUCTION SET CALL: llXXXXXX Conditional on status; if status line 75 is a logic "0", then the call instruction is not performed. If the status is "1", the machine goes into the call mode. The contents of the program counter 19 or 40 are stored in the subroutine registers 33 or 54. The page adress ine the page address register 21 or 42 is stored in page subroutine register 23 or 44, respectively. The contents of the page buffer register 35 or 57 is then loaded into the page address register 21 or 42. The chapter address in register 26 or 47 is stored in the chapter subroutine register 24 or 45 and the chapter buffer register 39 or 61 provides the new chapter address. The contents of the page address buffer register 35 or 57 and the chapter buffer register 39 or 61 is obtained from the ROM by a line 11. The field R2 to R8 of the instruction word is loaded into the program counter 19 or 40 from lines 20. All instructions executed while in the call mode perform normal functions, except for the call and branch instructions; execution of a call within a call mode is valid up to three calls; branch is executed within a call mode is valid up to three calls; branch is executed within a call mode may be off the present ROM page or chapter. BRANCH (BR): l0XXXXXX Conditional on status; if status is a logic "0", then the branch instruction is not performed. If the status on line 75 is "1", then the field R2 - R8 of the instruction word is loaded into the program counter 19 or 40 from line 20, and the contents of the page buffer register 35 or 57 become the new page address in the page address register 21 or 42. Likewise, the address in the chapter buffer register 39 or 61 become the new chapter address in the chapter address register 26 or 47. Branch as well as call can be unconditional because of the nature of the status logic 126 or 127. Status is normally in logic "1" which is the proper condition for successfully performing a branch or a call. If the branch immediately preceeding the branch or call does not affect status, then the operation will be successful. The status is only valid for one instruction cycle. It is therefore invalid to perform multiple tests before a branch operation. Only that instruction that immediately preceeds the branch call instruction will determine whether branching calling is successful. Status always returns to a logic "1" after a branch instruction. Return (RETN): 00001111 Changes the pointer of the CLA latch 34 or CLB latch 55. When executed in the call mode, the contents of subroutine register 33 or 54 are transferred into program counter 19 or 40. Simultaneously the contents of the page subroutine register 23 or 44 are transferred into the page address register 21 or 42. The Contents of the chapter subroutine register 24 or 45 is transferred into the chapter address register 26 or 47. This operation will return the system to a proper point after the subroutine has been executed. Load P Register (LDP): 0001XXXX The ROM page buffer register 35 or 57 is loaded with 4 bits of the field of R5 - R8 in the instruction word on lines 56 and 11. This is unconditional and neither carry nor compare go to status. R5 is LSB and R8 is MSB. Transfer Page to Chapter Register (TPC): 00001011 The two lowest significant bits in page buffer register 35 or 57 are loaded via lines 36 or 58 into chapter buffer registers 39 or 61. Transfer ACC to Y Register (TAY): 00100000 Accumulator 150 or 151 is unconditionally transferred into the Y register 148 or 149. Accumulator contents are unaltered. Microinstructions generated are ATN, AUTOY. Transfer Y Register to Accumultor (TYA): 00100011 The Y register 148 or 149 is unconditionally transferred into the accumulator 150 or 151. Contents of the Y register 148 or 149 are not altered. Microiristructions Generated: YTP, AUTOA. Clear Accumulator (CLA): 0111111 The contents of accumulator 150 or 151 are unconditionally set to "on. Microinstructions generated: AUTOA. Transfer Accumulator to Memory (TAM): 00100111 The contents of accumulator 150 or 151 are stored in the RAM memory location address by the X and Y registers 99 and 148 or 149. Accumulator 150 or 151 contents are unaffected. Microinstructions generated: STO. Transfer Accumulator to Memory and Increment Y (TAMIYC): 00100101 The contents of accumulator 150 or 151 are stored in the RAN memory location addressed by the X register 99 and Y register 148 or 149. After completion of the store operation, the Y register 148 or 149 is incremented by "1"; If the initial Y = 15, status is set to ."1". Unconditional. Microinstructions generated: STO, YTP, CIN, C8, AUTOY. Transfer Accumulator to Memory, Decrement Y (TAMDYN): 00100100 The contents of accumulator 150 or 151 are transferred to the currently addressed location in memoy 81, and the Y register 148 or 149 is decremented. If the i n i t i a 1 Y = 0, t h e status i s s e t to " 1 Microinstructions generated: STO, YTP, 15TN, AUTOY, C8. Transfer Accumulator to Memory and Clear Accumulator (TAMZA): 00100110 The contents of accumulator 150 or 151 are stored in the RAM memory location addressed by the X register 99 and Y register 148 or 149. The accumulator 150 or 151 is then reset to "on. Microinstructions generated: STO, AUTOA. Transfer Memory to Y Register (TMY): 00100010 The contents of RAM memory location currently addressed by the X register 99 and Y register 148 or 149 are unconditionally transferred into the Y register 148 or 14 9 . M e m o r y d a t a i n t h e RAM i s unaltered. Microinstructions generated: MTP, AUTOY. Transfer Memory to Accumulator (TMA): 00100001 The four bit contents of the RAM memory location currently addressed by X register 99 and Y register 148 or 149 are unconditionally transferred info the accumulator 150 or 151. Memory data in the RAM Al is unaltered. Unconditional, and carry and compare to do not go to status. Microinstructions generated: MTP, AUTOA. Exchange Memory and Accumulator (XMA): 0000011 The contents of RAM memory location addressed by the X register 99 and Y register 148 or 149 are exchanged with accumulator 150 or 151. That is, the accumulator is stored into memory and memory is stored into the accumulator. Microinstructions generated: MTP, STO, AUTOA. ADD Memory and Accumulator (AMAAC): 0000110 The contents of the accumulator 150 or 151 are added to the contents of the RAM memory 81 location address by X register 99 and Y register 148 or 149 with the resulting sum into the accumulator 150 or 151. Resulting carrying information is input into status 126 or 127. A sum that is greater than 15 will set clear accumulator. The contents of memory location is the RAM 81 are unaltered. Microinstructions generated: ATN, MTP, AUTOA, C8. Subtract Accumulator from Memory (SAMAN): 00111100 The contents of accumulator 150 or 151 are subtracted from the contents of RAM memory location addressed by the X register 99 or Y register 148 or 149 using 2's complement addition with the difference stored in 'the accumulator 150 or 151. To do this, the memory is added to the complement of the accumulator plus 1 (or CIN) and the sum is stored in the accumulator 150 or 151. Result and carry information is input into status 126 or 127. Status will be set to logic "1" if the accumulator is less than 1 or equal to the memory. Microinstructions generated: MTP, NATN, CIN, C8, AUTOA. Increment Memory and Load into Accumulator (IMAC): 00111110 The contents of RAM memory 81 location address by X register 99 and Y register 148 or 149 is incremented by 1 and stored into accumulator 150 or 151. The original contents of the RAM memory 81 are unaltered. resulting carry information is input via line 128 or 129 into status 126 or 127. Status will be set to a logic "1" if the sum is greater than 15. Microinstructions generated: MTP, CIN, C8, AUTA. Decrement Memory and Load into Accumulator (DMAN): 00000111 The contents of RAM memory 81 location currently addressed by X register 99 and Y register 148 or 149 are decremented by 1 and loaded into accumulator 150 or 151. Memory contents are unaltered. Resulting carry information is input into status logic 126 or 127. If memory is greater than or equal to 1, status will be set to logic "1". Microinstructions generated: MTP, 1STN, C8. Increment Accumulator (IAC): 01110000 The contents of the accumulator 150 or 151 is incremented by 1. If the previous contents was 15, then a carry is generated. Status 126 or 127 is set to logic "1". Microinstructions generated CKP, ATN, CIN, CB. Decrement Accumulator (DAN): 01110001 The accumulator 150 or 151 is decremented by -ln. If the previous contents of the accumulator was 0, the st a t u s c i r c u i t r y 1 2 6 and 1 2 7 i s s e t to n Microinstructions generated CKP, ATN, CIN, C8. Accumulator Plus Constant to Accumulator (AXAAC): 0111XXXX The above instruction is actually a set of 13 instructions which load a specific constant into the accumulator 150 or 151. The results are left in the accumulator 150 or 151. If there is a car, a logic "1" is sent to status circuitry 126 or 127. These instructions include A2ACC, A3ACC, A4ACC,. . .Al4ACC with the OP code changing from 01110010 to 01111110, respectively. The actual contents of the OP code is added to the accumulator from the R5 to the R8 field of the instruction words on line 71 via line 91. If a carry is generated, the status circuit 126 or 127 is set to a logic "1". Microinstructions generated: CKP, ATN, CA. Increment Y Register (lYC): 00000101 The contents of the Y register 148 or 149 are incremented by 1. Resulting carry information is input into the status logic 126 or 127. A sum greater than 15 will set status to a logic "1". Microinstructions generated: YTP, CIN, C8, AUTOY. Decrement Y Register (DYN): 00001000 The Y register 148 or 149 is decremented by 1. If there is no need to borrow, then the status circuitry 126 and 127 is set to nln. Complement Accumulator Increment (CPAIZ): 01111101 The contents of accumulator 151 is complemented and incremented by 1. If the contents is 0, then the status circuitry 126 and 127 is set to "1". Accumulator Compare (ALEM): 00000001 If' the accumulator 150 or 151 is less than or equal to memory, the status circuitry 126 and 127 is set to flit. Memory Comparison to Accumulator (MNEA): 0000000 If the memory location is not equal to the accumulator 150 or 151, then the status circuitry 126 and 127 is set to a "1". Memory not Equal to Zero (MNEZ): 00111111 If the memory location specified is not equal to zero, the status circuitry 126 or 127 is set to a "1". Y Register Not Equal to Accumulator (YNEA): 00000010 If the Y register 148 or 149 is not equal to the accumulator 150 or 151, then the status circuitry 126 and 127 is set to a "1". Y Register Not Equal to Constant (YNEC): 0101XXXX 'If the Y register 148 or 149 is not equal to the specified constant, the status circuitry 126 or 127 is set to "1". Test Memory Bit (TSBIT): 00110000 A memory bit is tested and if equal to 1, the status circuitry 126 or 127 is set to nl". The memory bit specified is unconditionally set to a "1". Reset Memory Bit (RBIT): 00111000 A specified memory bit is reset. Test Memory Bit (TBIT): 00111000 A specified memory bit is tested. If equal to 1, the status circuitry 126 or 127 is set to "1". Transfer Constant to Y Register (TCY): 0100XXXX A specified constant is transferred into Y register 148 or 149. Transfer Constant to Memory and Increment Register (PCMIY): 0110XXXX The specified constant is transferred to memory and the Y register 148 or 149 is increment by "1". Test K Inputs (KNEZ): 00001110 If the K inputs from 155 or 104 are not equal to zero, the status circuitry 126 or 127 is set to a Transfer K Inputs to Accumulator (TKA): 00001000 The K inputs from 104 to 155 are transferred to accumulator 150 or 151. Set R Output (SETR): 00001101 The R outputs 77 specified by Y register 1¯8 or 149 is set. Reset R Output (RSTR): 00001100 The R register 77 specified by Y register 148 or 149 is reset. Transfer Data from Accumulator and Status Latch to 0 Outputs (TDO): 00001010 The contents of accumulator 150 and 151 and the contents of status latch 144 or 143 is transferred to the output 162 or 159. Toggle I/O Port of CPU B (IOC): 00001001 The CPU B I/O port 155 is toggled from input to output. Load X with File Address (LDX): 00101000 The X register 99 is loaded with the file address. Complement the MSB of X (COMX): 00001001 The most significant bit of the X register 99 is complemented.

Claims: WHAT IS CLAIMED IS: 1. An electronic digital processor system comprising: memory means for storage of data and commands which define operations on said data; arithmetic and logic means for performing said operations on said data; dual independent and simultaneously operable register means for temporary storage of data from arithmetic and logic means and temporary storage for addressing said memory means; a plurality of data paths which couple said memory means and arithmetic and logic means and said register means; control and timing circuitry for simultaneous and independent execution of commands for accessing said memory means with a register means during execution of commands for operation of said arithmetic and logic means with other register means. 2. An electronic digital processor system according to Claim 1, wherein the memory means consists of read-only memory means and random access memory means. 3. An electronic digital processor system according to Claim 2, wherein said arithmetic and logic means sends data to said register means where reception of data by each register means is independent of reception of data by other register means. 4. An electronic digital processor system according to Claim 3, wherein each register means provides storage of data from said arithmetic and logic means and is coupled to said random access memory means. 5. An electronic digital processor system according to Claim 4, wherein each register means comprises an accumulator register provided to receive data from said arithmetic and logic means which is coupled to the input of said arithmetic and logic means. 6. An electronic digital processor system according to Claim 5, wherein the system is integrated monolithically on a single semiconductor substrate. 7. An electronic digital processor system comprising: memory means for storage of data and commands which define operations of said data; input means; output means; arithmetic and logic means for performing said operations on said data; dual independent and simultaneously operable register means for temporary storage of data from said arithmetic and logic means and temporary storage of data for addressing said memory means; a plurality of data paths which couple said memory means, said input means, said output means, said arithmetic and logicomeans and said register means; control and timing circuitry for simultaneous and independent execution of commands for accessing said memory means with a register means during execution of commands for operation of said arithmetic and logic means with other register means. 8. An electronic digital processor system according to Claim 7, wherein the memory means consists of read-only memory means and random access memory means. 9. An electronic digital processor system according to Claim 7, wherein said arithmetic and logic means receives data fran each register means independently. 10. An electronic digital processor system according to Claim 9, wherein each register means provides storage for receiving data from said arithmetic and logic means and is coupled to said random access memory means. 11. An electronic digital processor system according to Claim 9, wherein each register means includes an accumulator register provided to receive data from said arithmetic and logic means and coupled to input of arithmetic and logic means. 12. An electronic digital processor system according to Claim 7, wherein said input means includes first and second input ports for providing data to said register means. 13. An electronic digital processor system #according to Claim 7, wherein said output means includes first, second and third output terminals, said first output terminal connected to said first and said second register means for outputting data from either said first or said second register means, said second output terminal connected to said first register means for outputting data from said first register means, said third output terminal connected to said second register means for outputting data from said second register means. 14. An electronic digital processor system according to Claim 7, wherein said second input terminal is connected to said third output terminal. 15. An electronic digital processor system according to Claim 14, wherein said system is integrated monolithically on a single semiconductor substrate. 16. An electronic digital processor system comprising: input means for receiving said data, output means for displaying said data, memory means for storage of data and commands which define operations on said data; arithmetic and logic means for performing said operations on said data; dual independent and simultaneously operable register means for temporary storage of data from ¯said arithmetic and logic means and temporary storage of data for address said memory means; a plurality of data paths which couple said memory means, said arithmetic and logic means and said register means; control and timing circuitry for simultaneous and independent execution of commands for accessing said memory means with a register means during execution of commands for operation of said arithmetic and logic means with other register means. 17. A storage register comprising a closed circuit loop having input means, output means, a plurality of pairs of field effect means and a plurality of pairs of clocking means arranged such that a first clocking means of a clocking means pair is connected between first and second field effect means of a field effect means pair, and a second clocking means of a clocking means pair is connected between each pair of field effect means and input means is connected to the field effect means input and said output means is connected to field effect means output. 18. A storage register according to Claim 17, wherein said field effect means comprises inverters. 19. A storage register according to Claim 17, wherein said pairs of clocking means comprises two independent clock signals wherein during operation first clock signal becomes inactive before second clock signal becomes active and said second clock signal becomes inactive before said first clock signal becomes active. 20. An electronic digital processor system comprising: memory means to store instructions, arithmetic and logic means for performing operations under control-of commands derived from said instructions, control circuitry for obtaining from said memory said instructions, a plurality of central processing units which independently and simultaneously process instruction sequences while sharing said memory, said arithmetic and logic means, said control circuitry and data paths which couple said memory means, said arithmetic and logic means and said control circuitry to said central processing units. 21. An electronic digital processor system according to Claim 20, wherein the memory means consists of read-only memory means and random access memory means. 22. A two player game apparatus comprising: keyboard means for providing player inputs; display means for displaying game status; electronic digital processor system further comprising: memory means for storage of data and game commands which define operations on said data; arithmetic and logic means for performing said .operations on said data; first and second independent and simultaned-usly operable central processing units for executing said commands on said data; control circuitry for obtaining from said memories said game commands and said data and transferring said game commands to said first and second central processing units; first input means coupled to said keyboard means for providing player input to said first central processing unit; ; first output means connected to said display means for the transmission of player status from said first central processing unit; second input means coupled to said keyboard means for providing second player input to said second central processing unit; second output means coupled to said display means for transmission of player status from said second central processing unit; third output means coupled to display means for transmission of game status from said first and second central processing unit; a plurality of data paths that couple said first central processing unit to said memory means, said arithmetic and logic means, said first input means, said first output means and said third output means; and couple said second central processing unit to said memory means, said arithmetic and logic means, said second input means, said second output means, and said third output means. 23. An electronic displaying apparatus comprising: input means; display means; an electronic digital processor system further comprising: memory means for storage of data and commands which define operations on said data; arithmetic and logic means for performing said operations on said data; first and second independent and simultaneously operable central processing units for executing said commands on said data; control circuitry for obtaining from said memory means said commands and said data and transferring -said commands to said first and said second central processing units; first processor input means coupled to said input means for providing input to said first central processing unit; first processor output means connected to said input means for acknowledging the reception of input data; ; second output means coupled to said display means for displaying output data from said second central processing unit; a a plurality of data paths that couple said first central processing unit to said memory means, said arithmetic and logic means, said first input means, said first output means; and couple said second central processing unit to said memory means, said arithmetic and logic means, and said second output means. 24. An electronic telephone comprising: keyboard input means; telephone line interface means; message recorder means connected to telephone line interface; speech synthesis means connected to telephone line interface; an electronic digital processor system further comprising: memory means for storage of data and commands which define operation on said data; arithmetic' and logic means for performing said operations on said data; first and second independent and simultaneously operable central processing units for executing said commands on said data; control circuitry for obtaining from said memory said commands and said data and transferring said commands to said first and said second central processing units; -first input means coupled to said keyboard means for providing telephone number inputs to said first central processing unit; ; first output means coupled to said keyboard means for acknowledging the said input telephone numbers; second input means coupled to said telephone line interface to detect incoming telephone calls; second output means connected to said message recorder to active said message recorder to record said incoming. telephone calls; third output means coupled to said speech synthesis means to active speech synthesis audio connection to telephone line interface to answer said incoming telephone calls wth a predetermined speech synthesis message; a plurality of data paths that couple said first central processing unit to said memory means, said arithmetic and logic means, said first input means, said first output means, and said third output means; and couples said second central processing unit to said memory means, said arithmetic and logic means, said second input means , said second output means, and said third output means. 25. An electronic digital processor system comprising: memory means for storage of data and commands which define operations on said data; arithmetic and logic means for performing said operations on said data; first and second independent and simultaneously operable central processing units for executing said commands on said data; control circuitry for obtaining from said memory said commands and said data and transferring said commands to said first and second central processing units; first input means for providing external data to said first central processing unit; first output means for the external transmission of data from said first central processing unit; second input means for providing -external data to said second central processing unit; second output means for the external transmission of data from said second central processing unit; ; third output means for the external transmission of data from said first and said second central processing units; a plurality of data paths that couple said first central processing unit to said memory means, said arithmetic and logic means, said first input means, said first output means, and said third output means; and couples said second central processing unit to said memory means, said arithmetic and logic means, said second input means, said second output means, and said third output means. 26. An electronic digital processor system comprising: internal memory means for storage of data and commands which define operations on said data; external memory means for the external storage of said data and said commands which define operations on said data; arithmetic and logic means for performing said operations on said data; first and second independent and simultaneously operable register means for temporary storage of data from said arithmetic and logic means and temporary storage of data for addressing said internal memory means and said external memory means; a plurality of data paths which couple said internal memory means, said external memory means, said arithmetic and logic means and said register means; ; control and timing circuitry for simultaneous and independent execution of commands for accessing either said internal memory means or said external memory means with a register means during execution of commands for the operation of said arithmetic and logic means with other register means. 27. An electronic digital processor system according to Claim 26, wherein said internal memory means consist of read-only memory means and random-access memory means.

Inventors: BROWN, SAMMY K., KOEPPEN, PETER L., ROGERS, GERALD, SOLIMENO, DUANE
Applicants: TEXAS INSTRUMENTS INCORPORATED
Application year: 1981
Main classification: G06F9
IPC codes: G06F9, H04M1, A63F13, G06F15