A POWER-ON RESET CIRCUIT

Abstract: A power-on reset circuit which resets internal circuits of a semiconductor device such as a microprocessor initially after an operating voltage is switched on to the internal circuits via an operating voltage terminal (Tc) comprising a capacitance circuit (C), a detector means (I₁, I₂, I₃) for detecting the poten­ tial of the capacitance circuit (C) and outputting a reset signal (R) to the internal circuits until the potential on the capacitance circuit (C) reaches a predetermined value. The power-on reset circuit also comprising a resistor circuit (RCT) connected be­ tween one of the terminals (Tc) of the capacitance circuit (C) and the operating voltage terminal (Tp), the resistor circuit (RCT) consisting of a first resistor element (R′₁) and a second resistor element (R₂) connected in parallel with the first resis­ tor element (R′₁). The second resistor element (Ra) has a re­ sistance the value of which reduces after the potential of the capacitance circuit (C) has reached the predetermined value. This change in resistance of the second resistor element (R₂) ensures that the reset signal (R) is output from the detector means (I₁, I₂, I₃) for a sufficient time to reset all the internal cir­ cuits of the semiconductor device even if the operating voltage (V DD ) applied to the operating voltage terminal (Tc) only builds up slowly.

Description: A POWER-ON RESET CIRCUIT The present invention relates to a power-on reset circuit, and particularly to a reset circuit which resets internal circuits of a semiconductor device initially when an operating voltage is supplied to the semiconductor device. In general, a semiconductor device, such as a microprocessor, formed on a semiconductor chip includes a poweron reset circuit which initially rests the internal circuits of the semiconductor chip automatically when an operating voltage is switched on to the semiconductor chip, to set the internal circuits to a predetermined initial condition. A power supply to a conventional semiconductor device includes an integrating circuit to prevent the generation of current surges. As a result of this the power supply to components forming part of the device builds up gradually. Equally, the potential supplied to the clear signal terminal of the conventional power-on reset circuit also builds up gradually. In a conventional device the reset output is emitted from the reset circuit before the voltage on the clear signal terminal reaches a threshold value. When the voltage applied to the clear signal terminal and the power supply to the power-on reset circuit build up at a similar rate it is possible for errors to occur in the delivery of the reset signal because there is insufficient delay between the powering up of the power-on reset circuit and the attainment of the threshold value on the clear signal terminal. Attempts have been made to prevent this by increasing the capacitance connected to the clear signal terminal or by increasing the resistance of the path leading to the clear signal terminal. Neither of these have been successful as will be explained in more detail subsequently. According to this invention a power-on reset circuit to reset internal circuits in a semiconductor device initially after an operating voltage is switched on, comprises an operating voltage terminal for the internal circuits, a capacitor, detector means for detecting a potential of one of the terminals of the capacitor and sending a reset signal to the internal circuits until the potential reaches a predetermined value after the operating voltage is switched on to the operating voltage terminal and a resistor circuit connected between the one of the terminals of the capacitor and the operating voltage terminal of the internal circuits, ani is characterised in that the resistance value of the resistor circuit decreases after the potential of the one of the terminals of the capacitor has reached the predetermined value. The circuit in accordance with this invention operates effectively even when the potential of the operating voltage rises slowly. Moreover, the circuit is not affected by noise induced in the power-on reset circuit and also it does not occupy a large space on a semiconductor chip. Three examples of a circuit in accordance with this invention will now be described and contrasted with those used previously with reference to the accompanying drawings; in which: Figures 1A and 1B are circuit diagrams of conventional power-on reset circuits; Figures 2A and 2B are graphs illustrating the operation of the conventional power-on reset circuits; Figure 3 is a circuit diagram of a first example of the present invention; Figure 4 is a graph illustrating the operation of the first example; Figure 5 is a circuit diagram of a second example of the present invention; Figure 6 is a graph illustrating the operation of the second example; and, Figure 7 is a circuit diagram of a third example of the present invention. Figures 1A and 1B illustrate conventional power-on reset circuits used in a semiconductor device. C is a capacitor which is usually disposed outside the semiconductor device and is connected between a clear signal terminal Tc of the semiconductor device and a low voltage source Vss, for example, the ground whose potential is O V. I1 and 12 are two stage inverters and an output signal R from the second inverter 12 is used as a reset signal R supplied to the internal circuits of the semiconductor device. In Figure 1A, a resistor R1 is connected between the clear signal terminal Tc and an operating voltage terminal Tp of the semiconductor device, the terminal Tp being connected to an operating voltage VDD. The resistor R1 and the capacitor C make up an integrating circuit whose time constant is CRI. In Figure 1B, the resistor. RI shown in Figure 1A is replaced by a p-channel MOS transistor Ol whose gate electrode is connected to the low potential voltage V55 and whose source and drain electrodes are connected to the operating voltage terminal Tp and the clear signal terminal Tc, respectively. Figures 2A and 2B illustrate the operation of the conventional power-on reset circuits. In the circuit shown in Figure 1A, when an operating voltage VDD is switched on to the operating voltage terminal Tp, the capacitor C is gradually charged up to the operating voltage VDD through the resistor R1 and the potential of of the clear signal terminal Tc rises as shown in Figure 2A. When the potential of the terminal Tc reaches a threshold potential VTR of the fi#rst inverter I1, i.e., at the time t2, an output potential of the inverter I1 changes from high to low so that the output potential of the second inverter 12, i.e. the reset signal R changes from low to high. Assuming that the reset of the internal circuits connected to the power-on reset circuit shown in Figure 1A occurs when the potential of the reset signal R is low, then the reset of the internal circuits is effected within a time period RI between a power-on time to and the time t2, more particularly after the operating voltage VDD has risen enough to operate the internal circuits and within the time period T1. If the potential of the operating voltage VDD rises rapidly as shown by a solid line VDD , the reset of the internal circuits occurs within the time period T1. However, if the potential of the operating voltage VDD rises gradually as shown by the dotted line VDD the reset occurs within a time period T2 between a time tl when the potential of the operating voltage VDD has reached a minimum potential voltage V1 enough to operate the internal circuits and the aforementioned time t2. With regard to the power-on reset circuit shown in Figure 1B, the operation is the same as that of the poweron reset circuit shown in Figure 1A, except that the potential of the clear signal terminal Tc starts to rise from 0 V at a time tl as shown in the dotted line (Tc) when the potential of the operating voltage VDD rises gradually. as shown by the dotted line VDD. The time tl is the time when the potential of the operating voltage VDD has reached a threshold voltage V2 of the transistor Q1 so that the transistor QI is turned on. When the potential of the operating voltage VDD rises rapidly as shown by the solid line VDDt, the potential of the clear signal terminal Tc rises in approximately the same manner as shown by the solid line Tc. In the power-on reset circuit shown in Figure 1B, the reset of the internal circuits also occurs within the time period T1 when the potential of the operating voltage VDD rises rapidly as shown in the solid line VDD' or within the time period T2 when the potential of the operating voltage VDD rises gradually as shown in the dotted line VDD. However, the operating voltage for an integrated circuit formed on a semiconductor chip is usually supplied through an integrating circuit to a power supply terminal of the integrated circuit in order to avoid destruction of the integrated circuit by a surge current. Therefore, the potential of the operating voltage terminal Tp usually rises slowly as shown by the dotted lines VDD, and the time interval between the power-on time to and the time tl when the potential of the operating voltage terminal Tp reaches V1 becomes long, so that the time interval T2 within which the reset of the internal circuits of the semiconductor device has to occur is reduced. The time interval T2 becomes shorter and shorter in accordance with the increase of the rise time of the potential of the operating voltage terminal Tp. If the potential of the operating voltage terminal Tp rises very slowly, the potential of the clear signal terminal Tc rises almost in the same manner as the potential of the operating voltage terminal Tp. Therefore, in the worst case, there is a possibility of failure of the reset of the internal circuits due to an extreme decrease in the time interval T2. Especially in a semiconductor device whose operating voltage is relatively low, the operating speed of the internal circuits of the semiconductor device is low, so that the probability of the failure of the reset of the internal circuits is large. To solve this problem, the time t2 when the potential of the reset signal R changes from low to high is delayed by increasing the time constant CR1¯ The time constant CR1 can be increased by increasing the capacitance of the capacitor C or by increasing the resistance of the resistor RI or of the main current path of the transistor 91. However, to increase the capacity of the capacitor C, it is necessary to increase the size of the capacitor C, so that the capacitor C then occupies a larger space. Therefore, it is difficult to use the power-on reset circuit when the space is limited. Moreover, enlarging the capacity which necessitates an increase in the size of the capacitor C, leads to an increase in the cost of the power-on reset circuit. With regard to the increase in the resistance of the resistor E or the drain source resistance of the transistor 91, for example, to a value of about one megaohm, there occurs a problem that the internal circuit is reset by a noise pulse induced in the clear signal terminal Tc of the power-on reset circuit. This is because the resistor RI or the drain source resistance of the transistor 91 is a pull-up resistor which holds the potential of the clear signal terminal Tc high, during a steady state operation of the internal circuit, and if the resistance of the pull-up resistor is too large, its pull-up operation is not effected completely. For example, when a noise pulse of negative polarity is induced to the clear signal terminal Tc during the steady state operation and positive charges of the capacitor C are discharged, the capacitor C cannot be recharged immediately through the resistor E , because the resistance of the resistor RI is large. Therefore, the reset signal R from the second inverter 12 includes a negative pulse N as illustrated by a dotted line in Figures 2A and 2B, so that an undesirable reset pulse is generated. Figure 3 illustrates a first example of a power-on reset circuit in accordance with the present invention. The power-on reset circuit shown in Figure 3 comprises a capacitor C, a resistor circuit RCT consisting of p-channel MOS transistors Q1 and Q2, a first inverter I1 and a second inverter 12 The capacitor C is connected between a low voltage source Vss, for example the ground, and a clear signal terminal Tc which is connected to the input of the first inverter Il The source electrodes of the transistors Q1 and Q2 are commonly connected to an operating voltage terminal Tp, to which an operating voltage VDD is connected. The drain electrodes of the transistors h and Q2 are commonly connected to the clear signal terminal Tc. The gate electrode of the transistor Q1 is connected to the drain electrode of the same transistor Q1, i.e. to the clear signal terminal Tc. The gate electrode of the transistor Q2 is connected to the output of the first inverter 11 which is connected to the input of the second inverter I2. The output signal from the second inverter 12 is supplied to internal circuits of a semiconductor chip, (Not shown in Figure 3), as a reset signal R. Therefore, the power-on reset circuit of Fig. 3 is the same as that of Fig. 1A, except that the resistor R1 of Fig. 1A is replaced by the resistor circuit RCT. With reference to Fig. 4, operation of the power-on reset circuit of Fig. 3 will now be explained. Assume that the potential of the operating voltage VDD starts to rise from the time to of Fig. 4. In this condition, the potential of the clear signal terminal Tc does not change and is equal to Vss until the time tl' when the potential of the operating voltage VDD becomes equal to the threshold voltage VTHp of the p-channel transistor Q1 At the time t = tl' , the transistor Q1 is turned on and the potential of the clear signal terminal Tc starts to rise gradually with a time constant CRl' toward the potential of the operating voltage VDD , where R1' is the resistance of the main current path of the transistor Q1 Since the gate electrode of the transistor Q1 is connected to the drain electrode of the same transistor Q1 , i.e., to the clear signal terminal Tc t the resistance R11 , therefore, the time constant CR1 varies according to the potential rise of the clear signal terminal Tc. It should be noted that the gate electrode of the transistor Q1 can be connected to the low voltage source V55 , or the transistor Q1 used as the first resistor element whose resistance is always high can be replaced by a resistor R1 having a constant resistance as used in the power-on reset circuit of Fig. 1A. At the time t = t2 when the potential of the clear signal terminal T is equal to the threshold voltage of the c first inverter I1 , for example VDD/2 as shown by the chain line in Fig. 4, the potential of the output signal from the first inverter I1 changes from high to low and thus the reset signal R from the second inverter 12 changes from low level to high level, so that the transistor Q2 is turned on. Since the transistor Q2 , which operates as the second resistor element, receives the output signal from the first inverter I1 at the gate electrode thereof, the transistor Q2 is in the turned off condition when the reset signal R is low and the output signal from the first inverter I1 is high. When the reset signal R becomes high and the transistor Q2 is turned on as mentioned above, the resistance of the source-drain path, i.e., the main current path of the transistor Q2 is equal to the low resistance value R 2 Therefore, after the time t = t2 , a combined resistnace value of the resistor circuit RCT decreases and becomes R1'//R2 , where R1'//R2 designates a resistance value of a parallel connection of the resistance R1' and the resistance R2 , so that the potential of the clear signal terminal T rises rapidly toward VDD with a time constant c CR1 R2/(R1 + R2). The reset of the internal circuits of the semiconductor chip, not shown in Fig. 3, is effected within a time period when the reset signal R is low, and more particularly within a time period T2' from the time tl when the potential of the operating voltage VDD reaches a minimum operating voltage of the internal circuits, corresponding to V1 of Fig. 2A or 2B, to the time t2. The minimum operating voltage of the internal circuits is equal to 2VTH , when the internal circuits consists of C-MOS circuits and minimum operating voltages of a p-channel MOS transistor and a n-channel MOS transistor are both approximately equal to VTH. TH The time period T2' can be elongated by increasing the resistance of the resistor R1' even when the capacitance of the capacitor C is not increased or when it is decreased. Therefore, the reset or clear of the internal circuits is perfectly effected by the power-on reset circuit of Fig. 3. After the time t = t2 , the reset of the internal circuits is not necessary and generally are not effected. In the power-on reset circuit of Fig. 3, the resistance R1'//R2 of the resistor circuit RCT becomes very small compared with the resistance R1' of the main current path of the transistor Q1 Therefore, even if the positive charges of the capacitor C are discharged by the noises having a negative polarity, the capacitor C is rapidly charged again and, therefore, the potential of the clear signal terminal T c is almost constant, so that the potential of the clear signal terminal T is tightly pulled up. In order to C decrease the turned-on resistance R2 of the transistor for example the channel width of the transistor Q2 is made larger than that of the transistor Q1 In the power-on reset circuit of Fig. 3, the undesirable reset due to the temporary decrease of the potential of the clear signal terminal T in the steady state operation is prevented, even c if the noise pulses of negative polarity are induced to the terminal T from a noise source, for example, an automobile c engine. Fig. 5 illustrates another power-on reset circuit as the second embodiment of the present invention. The power-on reset circuit of Fig. 5 is the same as that of Fig. 3, except that the first resistor element of the resistor circuit RCT consists of a series connection of two p-channel MOS transistors Q1 and Q12 instead of the single p-channel MOS transistor Q1 of Fig. 3. The gate electrode of each of the transistors Qll and Q12 is connected to the drain electrode of the same one of the transistors Qll and Q12 so that the series connection of two transistors Qll and Q12 is turned on in the condition that the operating voltage VDD is equal to 2VTHp , where VTHp designates the threshold voltage of the p-channel MOS transistor Qll or Q12 The turned-on resistance of the series connection of two transistors Qll and Q12 is set to a value h" which is, for example, approximately equal to the turned-on resistance a1' of the transistor Ol of Fig. 3. With reference to Fig. 6, operation of the power-on reset circuit of Fig. 5 will now be explained. Assume that the operating voltage VDD starts to rise from the time to as shown in Fig. 6. At the time t = tl when the potential of the operating voltage VDD reaches to 2vTHp , the potential of the clear signal terminal T starts to rise with a time c constant RI" C toward VDD At the time t = t2' when the potential of the clear signal terminal T reaches VDD/2, the c potential of the output signal from the first inverter Il changes from high to low and the potential of reset signal R from the second inverter 12 changes from low to high. Since the minimum operating voltage of the internal circuits is approximately equal- to 2VTHp which is approximately equal to 2VTH of Fig. 4, the reset of the internal circuits is effected within a time period T2" from the time tl when the potential of the operating voltage VDD reaches 2VTHp to the time t21 when the reset signal R changes from low level to high level. In the power-on reset circuit of Fig. 5, the time period T2" can be longer than that of the power-on reset circuit of Fig. 3, because the potential of the clear signal terminal T starts to rise at the time t = tl which c is later than the time tl' when the potential of the terminal T of the power-on reset circuit of Fig. 3 starts C to rise. Fig. 7 illustrates still another power-on reset circuit as the third embodiment of the present invention. The power-on reset circuit of Fig. 7 is the same as that of Fig. 5, except that the power-on reset circuit of Fig. 7 further comprises the third inverter I3 which inverts the reset signal R from the second inverter 12 and applies the inverted signal to the gate electrode of the transistor Since the potential of the output signal of the third inverter I3 changes from high to low after the potential of the reset signal R has changed from low to high, i.e., after the time period T2" of Fig. 6 has finished, the power-on reset circuit of Fig. 7 can effect a more reliable reset of the internal circuits than the power-on reset circuit of Fig. 5. In the above-mentioned embodiments, the capacitor C is disposed outside of the semiconductor chip and connected between the clear signal terminal T of the semiconductor c chip and the low potential voltage Vss. However, it should ss be noted that the capacitor C can be formed on the semiconductor chip on which the power-on reset circuit and the internal circuits are formed, or, the substantial capacitance, for example stray capacitance, existing between the clear signal terminal T and the low potential voltage Vss c can be used for forming the time constant circuit instead of the capacitance-of the capacitor C. As mentioned above, according to the present invention, it is not necessary to increase the capacitance of the capacitor C, so that the capacitor C does not occupy a large space, for example, in electronic equipment and the cost of the power-on reset circuit does not increase. The resistance of the resistor circuit of the power-on reset circuit according to the present invention is high only for a short time after the operating voltage is supplied to the power-on reset circuit and is low in steady state, so that the clear signal terminal Tc is tightly pulled up to the operating voltage VDD and the operation of the power-on reset circuit is not affected by noise. Therefore, the power-on reset circuit according to the present invention is suitable, for example, for use in automobile equipment which receives severe electrical noise and whose size is limited.

Claims: CLAIMS 1. A power-on reset circuit to reset internal circuits in a semiconductor device initially after an operating voltage is switched on, the power-on reset circuit comprising an operating voltage terminal (Tp) for the internal circuits, a capacitor (C), detector means (Il, 12) for detecting a potential of one of the terminals (Tc) of the capacitor (C) and sending a reset signal to the internal circuits until the potential reaches a predetermined value after the operating voltage is switched on to the operating voltage terminal (Tp) and a resistor circuit (RCT) connected between the one of the terminals (Tc) of the capacitor (C) and the operating voltage terminal (Tp) of the internal circuits, characterised in that the resistance value of the resistor circuit (RCT) decreases after the potential of the one of the terminals (Tc) of the capacitor (C) has reached the predetermined value. 2. A power-on reset circuit according to claim 1, further characterised in that the resistor circuit (RCT) comprises a first resistor element (R'1) and a second resistor element (R2) which is connected in parallel with the first resistor element '1) and the resistance value of which decreases after the potential of the one of the terminals (Tc) of the capacitor (C) has reached the predetermined value. 3. A power-on reset circuit according to claim 2, further characterised in that the second resistor element (R2) comprises a transistor (Q2) connected between the operating voltage terminal (Tp) and the one of the terminals of the capacitor (C), the transistor (Q2) being turned on after the potential of the one of the terminals (Tc) of the capacitor(C) reaches the predetermined value. 4. A power-on reset circuit according to claim 3, further characterised in that the detector means comprises an inverter (I1) whose input terminal is connected to the one of the terminals (Tc) of the capacitor (C) the output signal of the inverter (I1) changing between a high potential level and a low potential level when the potential of the one of the terminals (Tc) of the capacitor (C) reaches the predetermined value, the output signal of the inverter (I1) also being supplied to the gate electrode of the transistor (Q2) forming the second resistor element. 5. A power-on reset circuit according to claim 4, further characterised in that the detector means also comprises a second inverter (I2) which inverts the output signal of the inverter (I1) and the output signal of which is used as the reset signal to the internal circuits. 6. A power-on reset circuit according to claim 3, further characterised in that the detector means comprises a first inverter (I1) whose input terminal is connected to the one of the terminals (Tc) of the capacitor (C), the output signal of the first inverter (I1) changes between a high potential level and a low potential level when the potential of the one of the terminals (Tc) of the capacitor (C) reaches the predetermined value, a second inverter (I2) which inverts the output signal of the first inverter (I1) and the output signal of the second inverter (I2) is used as the reset signal to the internal circuits, and a third inverter (I3) which inverts the output signal of the second inverter (12), the output signal of the third inverter (I ) being supplied to the gate electrode of the transistor (Q2) forming the second resistor element (R2). 7. A power-on reset circuit according to any one of the preceding claims, further characterised in that the first resistor element (R1') comprises a MOS tran#sistor (Q1) whose source electrode is connected to the operating voltage terminal (Tp) of the internal circuits and whose drain and gate electrodes are commonly connected to the one of the terminals (Tc) of the capacitor (C). 8. A power-on reset circuit according to any one of claims 1 to 6, further characterised in that the first resistor element (R1') comprises a MOS transistor (Q1) whose source electrode is connected to the operating voltage terminal (Tp) of the internal circuits, whose drain electrode is connected to the one of the terminals (Tc) of the capacitor (C), and whose gate electrode is grounded. 9. A power-on reset circuit according to any one of claims 1 to 6, further characterised in that the first resistor element (R1) comprises a resistor having a constant resistance. 10. A power-on reset circuit according to any one of claims 1 to 6, further characterised in that the first resistor element (R1'') comprises a plurality of gatedrain connected MOS transistors ( 1 Q12) connected in series.

Inventors: MONMA, HIDEO, TAKAHASHI, MASAYUKI
Applicants: FUJITSU LIMITED
Application year: 1981
Main classification: H03K17
IPC codes: G06F1, H03K17, H03K3