METHOD AND CIRCUIT FOR CLOCK RECOVERY

Abstract: In order to recover the clock signal from a Manchester encoded serial data stream which is resistant to phase variations arising between the data bit signals in the data stream, the data stream is delayed by a one-quarter bit period and a three-quarter bit period to provide signals (QBT, TQBT) which are combined in a circuit (1, 2, 3) to provide a clock signal (RF). The circuit includes a latch (1) which is actuated by signals (QBT, TQBT) and a signal (LLF) representing decoded data combined in logic gates (2) and applied to the inputs of the latch.

Description: ETHOD AND CIRCUIT FOR CLOCK RECOVERY Technical Field This invention relates to digital data trans¬ mission systems and, more particularly, to a circuit for recovering clock signals from a serial digital data stream and a method therefor whereby the timing signals may be subsequently utilized by a receiver to decode and deserialize the received data stream. Background Art In transmitting serial digital data, it is necessary to provide a series of clock pulses in addition to the data pulses in order to synchronize the coding of the transmitted serial digital data at a receiving terminal or the receiver. In prior-known transmitting schemes, two transmission lines or paths or two channels were required for this purpose, one for the data signal and one for the clocking signal. In attempting to avoid the requirement for a dual trans¬ mission path (or two channels), self-clocking codes evolved as a result of combining the clock and data signals. The Manchester code is one such self-clocking code. Manchester encoders accept clock and data and combine them into a single output which may be trans¬ mitted by a single transmission line to the receiving terminal. When the self-clocking data (i.e., the serial digital data stream) arrives at the receiving terminal, it is processed by a decoder which extracts separately both data and clock from the input self-clocking code. The clock recovery circuits of the prior art generally are formed by directing the serial digital data stream into AND or NAND gates causing a clock output, and when the conditions for setting disappear, the output resets. U.S. Patent No. 4,185,273 discloses a circuit for recovering a clock signal from a Manchester encoded signal, comprising a combination of delay lines, AND, NAND and NOR gates. A problem which arises with the above clock recovery circuits is that the operation of the logic gates is sensitive to phase variations caused by delay line tap to tap variations, data bit distortion and data bit skew of high or low times of the raw input serial digital data stream; this can lead to faulty operation. Disclosure of the Invention It is an object of the present invention to provide a circuit and method for recovering a clock signal from a serial digital data stream, the method and circuit being relatively insensitive to phase variations between the data bit signals in the data stream and pro¬ viding a fast clock recovery resolution. The present invention provides a clock re¬ covery circuit, having an input terminal adapted to receive a serial data stream having a defined bit time, said serial data stream being the resultant combination of a data signal and a clock signal, said clock recovery circuit being characterized by first means for shifting said serial data stream by one-quarter bit time thereby providing a second input signal, second means for shifting said serial data stream by three-quarters of a bit time thereby providing a third input signal, and means for detecting transitions in said second input signal and said third input signal to provide an output signal having a transition occurring at each of said detected transitions, said output signal being the clock signal recovered from said serial data stream. In another aspect, the invention provides from an inputted serial data stream having a defined bit time, said serial data stream being the resultant com¬ bination of a data signal and a clock signal, a method for recovering said clock signal, characterized by the steps of shifting said serial data stream by one-quarter bit time thereby providing a second input signal, shift¬ ing said serial data stream by three-quarters of a bit time thereby providing a third input signal, and detec¬ ting transitions in said second input signal and said third input signal to provide an output signal having a transition occurring at each of said detected transi- tions, said output signal being the clock signal recover¬ ed from said serial data stream. Preferably, said means for detecting transi¬ tions includes a latch circuit. A specific set of conditions are required to set the latch and another set of conditions are required to reset the latch, yielding a symmetrical recovered clock. Brief Description of the Drawings A preferred embodiment of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of the clock recovery circuit of the present invention; Fig. 2 is a logic diagram of the preferred embodiment of the last low frequency generator circuit utilized in the clock recovery circuit of the present invention; Fig. 3 is a timing diagram of specified signals inputted to, and generated by, the clock recovery circuit of the present invention; and Fig. 4 is a logic diagram of the preferred embodiment of the latch triggering logic and latch circuits. Best Mode for Carrying Out the Invention The clock recovery circuit of the present invention is shown in block diagram form in Fig. 1. The clock signal (RF) is recovered from a serial digital data stream as the output of a latch 1. ~ • Within a receiving terminal there is included within the clock recovery circuit of the present inven- tion, a signal generator 4 which generates three digital signals and their respective complement (or bar) signals. these digital signals being derived from a raw serial data input signal which combines the data and clock signals. The digital signals comprise the bit serial data signal (BSD) which is a demodulated, shaped, version of the raw 'serial data input signal using regeneration techniques w.ell known in the art, the quarter bit time signal (QBT). which is a version of BSD delayed by a quarter of "a' bit time, the three-quarter bit time signal (TQBT) which is a version of BSD delayed by three- quarters of a"bit time, and the respective complement or inverted signals BSD, QBT, and TQBT (the inverted sig¬ nals also denoted herein by a slash following the signal designation,- e.g. BSD/, QBT/, and TQBT/). Techniques for generating the digital signals and the respective complement signals are well known in the art; hence, the signal generator 4 will not be discussed further herein. In order to achieve the high speed of operation (i.e., data rates in the order of 24 MHz. which, due to the double frequency encoding, can result in pulse widths in the order of 15 ns), the respective complement signals must be symmetrical in time in order to avoid glitches in the clock. That is, when the QBT signal starts going high, QBT starts going low within approximately 1 ns, i.e. less than one gate delay. The same symmetry also applies in the opposite direction for the QBT signal, and also for the TQBT signal. The digital signals BSD, BSD, QBT, QBT, TQBT, and TQBT are inputted to a last low frequency (LLF) generator 3, together with the complement of the recovered clock signal RFx/. The output of LLF generator 3 is the last low frequency (LLF) signal and its complement signal LLF. The LLF signal indicates, by a change of state, when a low ^ ■ re uency of the BSD signal has occurred within a bit time. The operation of LLF generator 3 will be des- cribed in further detail hereinunder. The LLF signal is also applicable for and facilitates the decoding of, an inputted serial digital data stream coded in either Manchester code or diphase code. In such an application, - the LLF signal can then be transmitted to the data recovery circuits (not shown) within the receiving subsystem in order to recover the data. The latch 1 is set or reset by the output of latch triggering logic 2. Digital signals QBT, QBT, TQBT, and TQBT are combined by latch triggering logic 2 with the LLF and LLF signals, and the complement of the recovered clock RFx/, for generating the set and reset signals of latch 1. The operation of the latch triggering logic 2 will be ex- plained in detail hereinunder. The LLF signal is derived by the last low frequency generator 3 and will be described in conjunc¬ tion with Figs. 2 and 3. The last low frequency gener¬ ator 3 combines the BSD and BSD signals with the QBT and TQBT signals and their complement signals simultaneously while the recovered clock RF is a logic one (high). The. last low frequency generator 3 of the preferred embodi¬ ment is shown in Fig. 2 , An LLF latch 31 is set and re¬ set in accordance with the following equations: LLF = RFx/ (BSD QBT TQBT) • LLF a RFx/ (BSD QBT TQBT) When the signals BSD, QBT are a logic one (high), and RFx/ is a logic zero (low), the output of NOR-gate 32 is a logic zero (or low) . Inverter 33 will invert the output of NOR-gate 32 resulting in a logic one input to NOR-gate 34. When the TQBT signal is low, the output of NOR-gate 34 is low, the LLF latch 31 being reset, i.e. LLF = 0, due to LLF/ being high. At the same time, the QBT and BSD inputs to NOR-gate 36 are low, the RFx/ signal still is low, which results in the output of NOR- gate 36 being a logic one; hence, the output of inverter 37 and the input to NOR-gate 38 is low. Since TQBT is low, TQBT is high, yielding a low output from NOR-gate 38. This condition is shown in Fig. 3 just prior to time T, . At time T, , TQBT goes high and TQBT goes low. This results in the output of NOR-gate 38 going high, causing LLF/ to go low and LLF to go high, thereby set- ting LLF latch 31. As can be seen from the above con¬ dition, NOR-gates 32 and 34 together with inverter 33 yield the resultant AND function for the TQBT, QBT and BSD signals for setting LLF latch 31, and NOR-gates 36 and 38 together with inverter 37 give the AND function for the TQBT, QBT, and BSD signals for resetting the LLF latch 31. The setting and resetting of LLF latch 31 is performed in accordance with the above equations, the conditions being satisfied at discrete times T, through Tg as shown in Fig. 3. An examination of the waveforms of Fig. 3 shows the BSD waveform having a low frequency during bit times 1, 4, 5, 7, 9 and 10. A low frequency is said to occur when, at the three-quarter bit time mark, no change of state of the BSD signal has occurred during that bit time period. LLF transitions therefore occur during the corresponding bit times. This is shown by the LLF waveform at times T, , T~, T-,, T, f T 5 , and g and is consistent with the above equations. Every change in the state of LLF indicates a low frequency of the data has occurred in the current bit time, the LLF signal making a transition at the three-quarter point within the bit time. The latch 1 and latch triggering logic 2 will now be described in conjunction with Figs. 3 and 4. The latch 1 and latch triggering logic 2 of the preferred embodiment is shown in Fig. 4. The latch 1 is an R-S latch comprised of NOR-gates 11 and 12 in a cross-coup¬ led configura ion. The output of NOR-gate 11 is inverted by inverter 13, the output of inverter 13 being the recovered clock signal, RF. The output of NOR gate 12 is fed through a NOR-gate 14, the output of NOR-gate 14 being the inverted recovery clock signal RFx/, the x denoting a slight delay from the RF clock signal. The RESET input to NOR-gate 14 is low in normal operation, (a logic zero), thereby enabling NOR-gate 14 for the normal clock recovery function. The latch triggering logic 2 is comprised of NOR-gate 21 through NOR-gate 26. The outputs of NOR- gates 21, 22 are coupled to the inputs of NOR-gate 11 for providing a set signal of latch 1. The output of NOR-gates 23, 24, 25, 26 are coupled to NOR-gate 12 for providing a reset signal for latch 1. The latch 1 is set and reset by the combined LLF, QBT and TQBT signals and their inverted signals by NOR-gate 21 through NOR- gate 24. A change of state in the LLF signal while RF is high forces RF low. This function is accomplished by NOR-gates 25, 26. The setting and resetting of latch 1 is per¬ formed by the NOR-gate 21 through NOR-gate 26 in accord¬ ance with the equations set forth in Table 1. TABLE 1 TIME OCCURRENCE EQUiTION SHOWN IN FIG. 3 1. RF QBT TQBT LLF 2. RF s QBT TQBT LLF T C T E' 3. RF LLF TQBT QBT 4. RF — LLF TQBT QBT 5. RF LLF TQBT QBT L H 6. RF = LLF TQBT QBT "B Table 1 correlates all the combinations of the set-reset conditions with a time occurrence through T. J . shown in Fig. 3. For example, equation 1 in Table 1 specifies the RF signal will be high (i.e., the latch 1 • will be set) when QBT is high, and TQBT and LLF are low. Referring to Fig. 3, just prior in time to T at time A « , QBT, TQBT, and LLF are low, yielding RF low. At time T A , QBT has gone high resulting in RF going high. Examination of the waveforms of Fig. 3 can be similarly performed to correlate the condition of the signals at times T β through T- with the equations of Table 1. Further, the set-reset of latch 1 for times not speci- fically delineated between times T„ and T, can be corre¬ lated to one of the equations of Table 1. By further examination of the waveforms of Fig. 3, it will be obvious to one skilled in the art that due to the quarter bit time and three-quarter bit time delay utilized in the generation of the recovered clock signal by the present invention, the maximum amount of bit distortion allowable in the serial digital data input is in a range of +25% to -25% of a bit time. Although the above discussion is specifically directed to Manchester encoded data, it will be recognized by those skilled in the art that the circuit of the present invention is applicable to double frequency encoded data streams, including Manchester and diphase encoded data streams. While there has been shown what is considered to be the preferred embodiment of the invention, it will be manifest that many changes and modifications can be made therein without departing from the essential spirit and scope of the invention. It is intended, therefore, in the annexed claims, to cover all such changes and modifications which fall within the true scope of the invention. "£JR£__Λ OMPI ■ WIPO ^

Claims: CLAIMS : 1. A clock recovery circuit, having an input terminal adapted to receive a serial data stream having a defined bit time, said serial data stream being the resultant combination of a data signal and a clock signal, said clock recovery circuit being characterized by: a) first means for shifting said serial data stream by one-quarter bit time thereby providing a second input signal; b) second means for shifting said serial data stream by three-quarters of a bit time thereby providing a third input signal; and c) means for detecting transitions in said second input signal and said third input signal to provide an output signal having a transition occurring at each of said detected transitions, said output signal being the clock signal recovered from said serial data stream. 2. A clock recovery circuit according to claim 1, characterized by means for deriving a shaped serial data stream from said serial data stream thereby providing a first input signal, said first and second means being coupled to receive said first input signal. 3. A clock recovery circuit according to claim 2, characterized in that said means for detecting comprises: a) a latch, having an output terminal for providing- the output signal; and b) means for operating said latch, said means for operating having a first, second, and third input terminal adapted to receive said first, second, and third input signal, respectively, and further having a fourth, fifth, and sixth input terminal adapted to OMPI 3 . ( concluded ) receive the respective complement signals of the first, second, and third input signals, wherein the respective complement signals are symmetrical in time, said means for operating operatively connected to said first, second, third, fourth, fifth, and sixth input terminals and to said latch, said means for operating generating a trigger signal upon detection of a transition in the second input signal and in the third input signal, there¬ by causing a transition in the output signal of said latch, the output signal being the clock signal. 4. A clock recovery circuit according to claim 3, characterized in that said means for operating comprises: a) means for generating a first signal, said means for generating a first signal operatively connected to said first, second, third, fourth, fifth, and sixth input terminals, and operatively connected to said latch, said first signal indicating whether a low frequency of the first input signal has occurred during the bit time just about to expire; and b) means for triggering said latch, said means for triggering operatively connected to said second, third, fifth, and sixth input terminals, to said latch, and to said means for generating a first signal, said means for triggering combining said second input signal, said third input signal, said first signal, their respective complement signals, and said output signal, for generating setting and resetting signals of said latch, the output signal of said latch being the clock signal. 5. A clock recovery circuit according to claim 4, characterized in that said means for generating comprises: a) a first signal latch having a first signal output terminal; and OMFI 5. ( concluded ) b) a first plurality of NOR-gates, operatively connected to said first signal latch, com¬ bining said first, second, and third input signals, their respective complement signals, and said output signal, for generating setting and resetting signals of said first signal latch, thereby ' causing said irst signal latch to provide said first signal at the first signal output terminal. 6. A clock recovery circuit according to claim 5, characterized in that the first plurality of NOR-gates comprises: a) a first and second inverter, each inverter having an input and an output; b) a first and second NOR-gate, said first NOR-gate having a first, second, and third input, and an output, and said second NOR-gate having a first and second input, and an output, the first input of said first NOR-gate adapted to receive said first input signal, the second input of said first NOR-gate adapted to receive said second input signal, the third input of said first NOR-gate adapted to receive said output signal, the output of said first NOR-gate operatively connected to the input of said first inverter, the output of said first inverter operatively connected to the second input of said second NOR-gate, the first input of said second NOR-gate adapted to receive said third input signal, and the output of said second NOR- gate operatively connected to the first signal latch; and c) a third and fourth NOR-gate, said third NOR-gate having a first, second, and third input, and an output, and said fourth NOR-gate having a first and second input, and an output, the first input of said third NOR-gate adapted to receive said output signal, the second input of said third NOR-gate adapted to OMPI 6. ( concluded ) receive the complement of the second input signal, the third input of said third NOR-gate adapted to receive the complement of said first input signal, the output of said third NOR-gate operatively connected to the input of said second inverter, the output of said inverter operatively connected to the first input of said fourth NOR-gate, the second input of said fourth NOR-gate adapted to receive the complement of said third input signal, and the output of said fourth NOR-gate operative¬ ly connected to said first signal latch. 1. A clock recovery circuit according to claim 6, characterized in that the means for triggering comprises: a) a fifth NOR-gate having a first, second, and third input and an output, the first input of said fifth NOR-gate adapted to receive said first signal, the second input of said fifth NOR-gate adapted to receive the complement of said second input signal, the third input of said fifth NOR-gate adapted to receive said third input signal, and the output of said fifth NOR-gate operatively connected to said latch; b) a sixth NOR-gate having a first, second, and third input and an output, the first input of said sixth NOR-gate adapted to receive a complement of said first signal, the second input of said sixth NOR-gate adapted to receive said second input signal, the third input of said sixth NOR-gate adapted to receive the complement of said third input signal, and the output of said sixth NOR-gate operatively connected to said latch; c) a seventh NOR-gate having a first, second, and third input, and an output, the first input -" " of said seventh NOR-gate adapted * to receive said first signal, the second input of said seventh NOR-gate adapted to receive said second input signal, the third input of O PI 7. (concluded) , said seventh NOR-gate adapted to receive the complement of said third input signal, and the output of said seventh NOR-gate operatively connected to said latch; d) an eighth NOR-gate having a first, second, and third input and an output, the first input of said eighth NOR-gate adapted to receive the complement of said first signal, the second input of said eighth NOR-gate adapted to receive the complement of said second input signal, the third input of said eighth NOR- gate adapted to receive said third input signal, and the output of said eighth NOR-gate operatively connected to said latch; e) a ninth NOR-gate having a first, second, third and fourth input and an output, the first input of said ninth NOR-gate adapted to receive said second input signal, the second input of said ninth NOR- gate adapted to receive said third input signal, the third input of said ninth NOR-gate adapted to receive the complement of said first signal, the fourth input of * said ninth NOR-gate adapted to receive said output signal, and the output of said ninth NOR-gate operatively connected to said latch; and f) a tenth NOR-gate having a first, second, third, and fourth input and an output, the first input of said tenth NOR-gate adapted to receive said output signal, the second input of said tenth NOR-gate - ^ -adapted to receive said first signal, the third input of said tenth NOR-gate adapted to receive the complement of said third input signal, the fourth input of said tenth NOR-gate adapted to receive the complement of said second input signal, and the output of said tenth NOR- gate operatively connected to said latch. 8. A clock recovery circuit according to claim 7, characterized in that said latch comprises: a) an eleventh NOR-gate having a first, second, and third input and an output; and O PI 8 . ( concluded ) b) a twelfth NOR-gate having a first, second, third,' fourth, and fifth input and an output, the eleventh and twelfth NORrgates being cross-coupled such that the output of the eleventh NOR-gate is coupled to the first input of said twelfth NOR-gate and the output of the twelfth NOR-gate is coupled to the third input of said eleventh NOR-gate, the first and second input of said eleventh NOR-gate being operatively connec¬ ted to the output of the fifth and sixth NOR-gate re¬ spectively, thereby providing a setting signal for said latch, and the second, third, fourth, and fifth input of said twelfth NOR-gate being operatively connected to the output of the seventh, eighth, ninth and tenth NOR-gates respectively, thereby providing a resetting signal for said latch. 9. A clock recovery circuit according to claim 8, characterized in that the first signal latch comprises: a) a thirteenth NOR-gate having a first and second input and an output; and b) a fourteenth NOR-gate having a first and second input and an output, the thirteenth and fourteenth NOR-gates being cross-coupled such that the output of the thirteenth NOR-gate is coupled to the first input of the fourteenth NOR-gate and the output of the fourteenth NOR-gate is coupled to the second input of the thirteenth NOR-gate, the first input of said thirteenth NOR-gate being operatively connected to the output of said second NOR-gate, and the second input of said fourteenth NOR-gate being operatively connected to said fourth NOR-gate, the output of said thirteenth- NOR- gate being coupled to the first signal output terminal thereby providing said first signal to the first signal output terminal, and the output of said fourteenth NOR- gate providing the complement of said first signal. -15- 10. From an inputted serial data stream having a defined bit time, said serial data stream being the resultant combination of a data signal and a clock signal, a method for recovering said clock signal char- 5 acterized by the steps of: a) shifting said serial data stream by one-quarter bit time thereby providing a second input signal; ■ b) shifting said serial data stream by 10 three-quarters of a bit time thereby providing a third input signal; and c) detecting transitions in said second input signal and said third input signal to provide an output signal having a transition occurring at each of 15 said detected transitions, said output signal being the clock signal recovered from said serial data stream.

Inventors: COOK DONALD M
Applicants: NCR CO, NCR CORP
Application year: 1981
Main classification: H04L27
IPC codes: H04L7, H04L25