DATA TRANSMISSION ARRANGEMENT

Abstract: A data transmission arrangement for bi-directional transmission of bit-sequences between a central unit (CCU) and a plurality of terminal units (TU1, TU2, ...) is provided which is particularly adapted for data acquisition and feedback signaling of messages, and for process control. In the arrangement the data transmission can occur simultaneously with the power supply of the terminal units over a two-lead cable (L), to which a large number of terminal units can be connected in parallel. The method of operation of the arrangement permits an advantageously simple construction of the transmission and reception equipment in the central unit and the terminal units.

Description: Data Transmission Arrangement This invention relates to an arrangement for bi-directional trans¬ mission of bit-sequences between a central control unit and a plura¬ lity of terminal units connected to the central control unit by means of a transmission line, over which the terminal units can be supplied with power from a direct current power source located at the central control unit. An arrangement in accordance with the above is useful, for in¬ stance, in data acquisition and feedback of messages, as well as for process control. Previous, known arrangements for such a type of data transmission have limitations in various respects. One such limitation in previous arrangements is the capability of transmission in only one direction on a single line, for example, to acquire measurement data from a number of sensors. In many appli¬ cations, however, there is a demand for signaling in the other direc¬ tion as well, such as to manuever an actuator, after processing a signal received from a temperature sensor. In previous arrangements this can be done by providing special lines for feedback signaling. In this case, each sensor with accom¬ panying actuator requires two pairs of wires. One of the problems with such data transmission arrangements is supplying power for sensors, indicators, etc. For these types of components, as well as others with relatively low power consumption, it is desirable to be able, when necessary, to supply power via the transmission line from a central power source. This is usually achieved by the use of an additional pair of wires for power supply. The transmission distances in data transmission applications can be as long as 5 km or more. It will readily be seen that the cable installation will form a dominant part of the total costs of the data transmission arrangement. In addition, modification or extension, of the system can be difficult, in which case it may be necessary to ad new pairs of wires and to re-plan the exploitation of the lines. In data transmission applications, where large quantities of dat are transfered between, for example, a central computer and a numbe of terminal computers, the transmission is accomplished via a line t which the communicating units are connected by means of accompanyin modulator-demodulator circuitry (so-called modems). The constructio and operation of such modems are optimized among other things wit respect to a high transmission capacity. In, for example, dat aquisition (data logging) applications, there is a demand for onl relatively low transmission capacities, for instance 300 bauds, i which case modems are not interesting. Also, for reasons of costs modem circuitry is not considered in the applications for which thi invention is best suited. In order to function well, a data transmission arrangement for th above field of application ought to fulfill the following conditions - bi-directional transmission - simple cable installation - power supply if necessary via the transmission line - insensitivity to disturbances - simple overall installation - simple construction of integral units One of the goals of this invention is, by proper choice of trans mission method and its realization, to obtain an arrangement a described above, which fulfills all the above conditions, and i which the disadvantages, both in usage and in cost, of previous know data transmission arrangements are eliminated. This goal is achieved with an arrangement in accordance with wha has been specified in the preamble of the present invention, which i characterized in that the transmission line consists of a two-lea cable to which a plurality of terminal units are connected i parallel: in that the central control unit is connected to sai two-lead cable via a central line unit which, for transmission, consists in part of a generator, controllable by bit-sequences, fo producing a bit-sequence modulated transmission frequency signal, an in part of an output stage for superimposing said transmissio O PI WIPO frequency signals upon a constant voltage signal derived from a direct current power supply: in that each terminal unit is connected to said two-lead cable via a central line unit which, for reception, consists of means for reconstructing bit-sequences from said trans¬ mission frequency signal, and, for transmission, consists of a cur¬ rent sink, controllable by bit-sequences, for producing a bit-se¬ quence modulated current variation in said two-lead cable: in that said central line unit consists, for reception, in part of a detec¬ tor, connected in series with said two-lead cable, for sensing a current variation in said two-lead cable, and in part of means for reconstructing bit-sequences from the output signal of said detector: in that the input and output circuits, connecting said central line unit and said terminal line units to said two-lead cable, have high impedance for both frequency signals and constant voltage: and in that a terminal line unit, in appropriate cases, consists of means for reception of direct current power and, for reception, with high input impedance, of frequency signals so that transmission is effec¬ ted in one direction by superimposing a frequency signal upon an essentially stable direct voltage level on the transmission line and, in the other direction, by a variation in the direct current drawn from the transmission line, with the retained capability of supplying power to the terminal units. In a preferred embodiment of the invention, frequency-shift modu¬ lation is used for transmission from the central control unit to the terminal units, while bit-sequences in phase-shift modulated form control a current sink for transmission in the other direction. Since the terminal units have high input and output impedances, the number of terminal units can easily be increased upon need. The two-lead cable, besides being relatively inexpensive in itself, allows for savings in necessary space and in installation. The chosen combination of transmission and reception methods makes it easy to avoid interference without the use of expensive filtering arrange¬ ments. Transmission from the terminal units requires very little power, which power easily can be supplied via the two-lead cable. Without taking any special measures, such as the use of a line amplifier, 40-50 terminal units can be connected to a two-lead cable OMPI . with a length of 5 km. That which limits the possible number o terminal units is partly the voltage drop in the transmission lin when simultaneously transmitting and supplying power, and partly th time necessary for the central control unit to address all th terminal units ( ) . Galvanic insulation between the termina units and the transmission line can easily be accomplished. Other features and advantages of the invention will be set fort in, or are apparent from the claims. The invention will hereinafter be more fully described, by way o example, with reference to the accompanying drawings, in which Fig. shows a block diagram over a transmission arrangement in accordanc with the invention: Fig. 2 shows a detailed block diagram over th central line unit CLU in Fig. 1: Fig. 3 shows a detailed bloc diagram for a terminal line unit TLU in Fig. 1: Fig. 4 shows signa wave forms at indicated positions in Fig. 2 and Fig. 3: Fig. 5 show a schematic circuit diagram over the output stage A3 in Fig. 2 Fig. 6 shows a schematic circuit diagram for the demodulator A10 i Fig. 2: Figs. 7 and 8 show the blocks uD and SAU+SPU in Fig. 1 Fig. 9 shows a schematic circuit diagram for the blocks B9 and BIO i Fig. 3: Fig. 10 shows a schematic circuit diagram for the demodulato B7 in Fig. 3 and Fig. 11 shows a schematic circuit diagram over th phase-shift modulator B8 in Fig. 3. The data transmission arrangement according the invention, whic is depicted in Fig. 1, consists of a central control unit CCU, whic normally comprises a minicomputer with a signal-processing capacit in accordance with the size of the data transmission arrangement together with accompanying periferal equipments, such as displa terminal, keyboard, etc., chosen in accordance with the intende usage of the arrangement. The CCU is connected to a central line uni CLU, which comprises means for the transmission and reception o bit-sequences to and from CCU, as well as means for supplying powe to the transmission line L. The transmission line consists of two-lead cable, to which an arbitrary number of terminal units TU1 TU2, are connected in parallel. The transmission line L is itsel terminated with a termination unit IAU for impedance adaption or lin amplification. O Π The terminal units are connected as shown to the desired means (TU21, TU22, ... ,TU24 at TU2) for measurement, indication, or control, such as temperature sensors, indicator lamps, or control relays. Messages between these means and CCU can be exchanged over the trans- mission line, the supply of power to these means also is provided over the transmission line. TU1 is shown in greater detail and, seen from the transmission line L, comprises a terminal line unit TLU, comprising means for transmission and reception of bit-sequences to and from CCU as well as means for the reception of power. TLU further comprises means for logic-signal adaption of information signals according to RS 232 standard (V24-interface) . In this way, TLU can be connected to a microcomputer uD which has the task of selecting relevant information for the terminal concerned and of controlling the exchange of in- formation with the sensors, indicators, etc. at that terminal. The blocks TLU and uD are general for the entire arrangement, with the exception of certain programming of the microcomputer which is speci¬ fic for each terminal, and are a part of each TU. For the communi¬ cation of uD with its sensors, indicators, etc., the signals are adapted in a signal adaption unit SAU. These signals are further processed in a signal processing unit SPU, in which the signals are given a suitable form and, after possible amplification, are fed on to, for example, a control relay (R). In the other direction, a signal from a sensor (S) is given a suitable form for transfer to SAU. It will be seen that SAU and SPU must be constructed with respect to the sensors, indicators, etc. connected to that terminal. As is shown in greater detail in Fig. 3, TLU further comprises a circuit for the reception of direct current power from CLU. The signal transmission method in the preferred embodiment, with frequency-shift modulation in the direction from CCU to TU1, TU2... and with phase-shift modulation in the opposite direction makes possible an especially advantageous and simple construction of the blocks CLU and TLU. For the sake of completeness, it should be stated that the current variations mentioned above can be level-shift modu- lated, frequency-shift modulated, or similarly modulated. Phase-shift modulation, however, permits greater insensitivity to disturbances. The blocks mentioned above will be described in more detail in th following: Fig. 2 shows a detailed block diagram of CLU. Closest to th central control unit CCU is a block Al which at 5 receives bit-se quences according to RS 232 standard. In Al a bit-sequence passes an inverter and continues thereafte to control input 1 of a sine-wave generator A2. The sine-wave gene rator includes an integrated circuit Intersil 8038 connected accor ding to Fig. 10, page 42 of Intersil Semiconductor, Analog Handbook the control input of which being fed from Al via a resistor and level controlling transistor. When the control input 1 receives high-level signal, a sine-wave signal is delivered, during the sam time, at output 2„ A low-level signal at input 1, causes zer voltage at output of A2.This will be described in more detail i connection with Fig. 4. The output signal from A2 continues to an output stage A3, arran ged to deliver direct current power, together with the modulate signal from A2, to the line L. A detailed circuit diagram for A3 i shown in Fig. 5. At output 2 of A3, a direct voltage signal, upo which an information signal is superimposed, is obtained from A2. Th output signal from A3 continues to a current variation detector A4 arranged to sense the variations in current from A3 to the line L. I this example A4 includes a low ohm resistor R j connected in serie with output 2 of A3. The output of A4 is connected to the line L via a block A6 whic includes conventional protection circuitry with voltage dependen resistance VDR. The described blocks Al, A2, A3, A4 and A6 form th path of a signal for transmission from CCU to TU1, TU2,.. Connected in parallel with the sensing resistor in A4 is high-pass filter A5, at the output of which a signal is obtained, representating the significant high-frequency voltage variations ove A4. The output signal of A5 is amplified in a differential amplifie A7, and then passes a low pass filter A8. The cut-off frequencies for A5 and A8 are chosen so that A5 sup presses frequencies lower than the signal frequencies for trans mission and reception, while A8 suppresses frequencies higher tha those signal frequencies obtained from the line L. The transmission frequency of the frequency-shift modulation from A2 is preferably chosen at a factor of at least 3 times higher than the bit-frequency of reception. These frequencies can be, for in- stance, 5 kHz and 300 Hz, respectively. Such a choice demands less of the filters to be used, the construction of which is thereby simplified. It will be seen that the bit-frequency for transmission need not be the same as that for reception. The output signal from A8 continues to a pulse generator A9 which includes a zero-crossing detector for converting the essentially sine-wave formed current pulses, after filtering in A5 and A8, from the line L, to square wave pulses. A detailed circuit diagram for such a zero-crossing detector can be found in Linear Applications, Vol. 2, National Semiconductor, Sept. 1976, page AN 87-6. The output signal from A9 continues to a demodulator signal con¬ verter A10, which demodulates the phase-shift modulated current pulse signal, and converts the signal according to RS 232 standard. A detailed circuit diagram for A10 is shown in Fig. 6. Before continuing to CCU, the RS-232 output signals from A10 pass an inverter/level adapter located in Al. The blocks A6, A4, A5, A7, A8, A9, A10, and Al form the path for reception of a signal. Fig. 3 shows a detailed block diagram for a TLU. Closest to the two-lead cable L is a block Bl which includes protection circuitry and disturbance damping circuitry to protect the electronic compo¬ nents in the terminal from inadvertent reversals of polarity during the connection of a terminal to L, as well as to dampen the distur¬ bance frequencies which may appear on L. Especially advantageous is the light-emitting diode LED which glows in case of an improper connection. The direct voltage on the line L is an unregulated voltage input to block B2 which includes a reactive coil and a capacitance, which are chosen so that B2 has a high input impedance for the signal frequencies. B2 further includes a direct voltage converter DC/DC, which permits galvanic insulation from L, the output of which is a regulated direct voltage for the supply of power for the terminal. The path for reception of a signal from L is formed by the block B4, B5, B6, and B7. B4 comprises a low-pass filter, a series resisto with high resistance, and a transformer for galvanic insulation fro L. These components are chosen so that B4 has high input impedanc for both signal frequencies and the direct voltage. B5 comprises low-pass filter with a cut-off frequency somewhat higher than th signal frequencies. Essentially sine-wave formed pulses are obtaine from B5, which represent the sine-wave pulses from A2 with th intervening intervals of zero voltage. These pulses are converted i B6 to square-wave pulses using the same type of zero-crossin detector as in A9. These square-wave pulses are demodulated in B which includes a two-frequency discriminator (see Fig. 10) fo producing binary signals in accordance with RS 232 standard. Th logic signals so obtained continue to the microcomputer uD (see Fig 1) for further conveyance to SAU and SPU (see Fig. l). This part o the signal processing will be described below in more detail i connection with Figs. 7 and 8. The path for transmission in a TU of RS 232 signals from uD to th line L is B8, B9, and B10. In B8 (see Fig. 11) RS 232 pulses are phase-shift modulated an continue thereafter to the opto-switch B9 for galvanic insulation The outputs of the opto-switch are connected to the control inputs o a controllable current sink BIO, the current drawn being made t alternate between 0 mA and, for example, 20 mA depending upon th control signals, and thus the information obtained from uD. When th phase-shift modulated signal from B8 is at a low level, the curren sink draws no current from L. This also applies when TU is no transmitting. As such, B10 provides no additional load on the line when transmitting from CCU to TU. A detailed circuit diagram of B and B10 is shown in Fig. 9 Seen from the line L, B4 and B10 present a high impedance for bot signal frequencies and direct voltage (when B10 is inactive). Curren flows via B2 only to the units to be supplied with power from th line L. It will be readily seen that by the appropriate design of th input circuits B2 and B4, it will be possible to connect a larg number of terminal units in parallel to the line L, while retainin O PI low transmission power usage from CLU: Also contributing to this end, are that the chosen methods of modulation permit a certain diminishing of amplitude, as well as the moderate demand on the rate of transmission (for example 300 Bauds). Fig. 4 shows the signal waveforms at indicated positions in Figs. 2 and 3. For transmission from CCU to a terminal TU, a bit-sequence B5 is produced by CCU and appears at Al on input 5. From Al the bit-se¬ quence is presented in inverted form UA2:1. The sine-wave generator A2 is activated in pace with UA2:1 and produces sine-wave pulses when UA:1 is high, otherwise: zero voltage. The output signal from A2 is superimposed upon a direct voltage VDC in A3 which outputs the signal UA3:2 which, by way of A4 and A6, is fed to the line L. The transmission signal thus produced is received by all the ter- inal units. Since the input and output circuits of the terminal line units have a high impedance for the transmission frequency, as well as the direct current signal, the transmission power can be held at a low level, as can the power losses in the series resistor in A4. The transmitted signal is received (see Fig. 3) at the terminal line unit in the block B4, which presents the signal UB4:2 on output 2, the signal representing an amplitude damped version of UA3:2, superimposed possibly with higher frequency disturbances which will be removed in the filter B5. The signal UB4:2 is converted to square wave pulses in B6, producing the signal UB6:2 which is demodulated in B7 to give the signal UB7:2. It can be seen from the signal diagram that UB7:2 is a somewhat phase-displaced version of the control voltage UA:1 presented to the sine-wave generator A2. The signal UB7:2 continues to uD (see Fig. l) for further processing. For transmission from a TU to CCU, the bit-sequence to be trans- mitted is delivered from uD to B8, at input 1 of which the signal UB8:1, in accordance with RS 232 standard, is received. In B8, the signal UB8:1 is phase-shift modulated, producing the signal UB8:2, where the relevant changes in phase are marked with arrows, The signal UB8:2 controls the opto-switch B9, which in turn controls the current sink B10 in which the current drawn from the line L is made to vary according to the signal UB8:2. OMPI The varying current drawn from the line Lproduces a varying vol tage drop over the sensing resistor in A4 in the central line uni CLU. The voltage signal from A4 passes the high-pass filter A5, i then amplifiedin the amplifier A7, is low-pass filtered in A8, and i converted to a square-way signal by the zero-crossing detector in A9 This part of the signal processing corresponds to that which occur in TU in the blocks B5 and B6. At the output of A9, there is obtaine a signal which is a version of the phase-shift modulated signa UB8:2. This signal is demodulated finally in AlO, and is there give RS 232-form. The signal UA10:2 is obtained at the output of AlO, thi signal being a delayed version of that signal originally from th terminal unit. According to the above description, a simplified frequency-shif signal, in which one of the frequencies is zero, is sent from CCU t TU. It can be seen that modulation with two frequencies from A2 i equally possible, as is controlling A2 with a phase-shift modulate version of the transmission bit-sequence. It is equally possible t use various transmission frequencies, to be used for group-addressin of the terminals. Such procedures lead, however, to a complicate construction of A2, input filters, input and output circuits, as wel as demodulators. Fig. 5 shows a detailed circuit diagram for the output stage A3 i CLU. A differential amplifier DAI is connected to the base of PNP-transistor Tl, the emitter of which is connected to a positiv reference voltage +U. The transmission signal, superimposed upon direct voltage VDC (see Fig. 4, UA3:2), is obtained at the collecto of Tl. When no signaling is taking place, this circuit functions as constant voltage source with the output voltage VDC for supplyin power to the connected terminals. Fig. 6 shows a detailed circuit diagram for the demodulator AlO i CLU. The demodulator is constructed using integrated circuits, wher the nomenclature given for the inputs and outputs used on th integrated circuit package is in agreement with the manufac turers'data sheets. As such, there is included two Schmitt-trigger of the type CD 4093 B, en exclusive OR circuit (=1) of the type C 4030 B, a monostable multivibrator (FF) of the type CD 4047 b, and D Flip-Flop of the type CD 4013 B, connected as shown in Fig. 6. The integrated circuits named above are manufactured by RCA Semi¬ conductor. The changes in phase in the signal from A9, that is a signal representing the signal UB8:2 in Fig. 4, is detected by a first Schmitt-trigger and exclusive OR circuit, the output signal of which is presented at the control input of the multivibrator FF, which is then activated. By proper choice of the components connected to the 10 multivibrator, the time for returning to the stable state can be set at about 3/4 of the bit-time. The signal at the Q-output of the multivibrator and the output signal from the exclusive OR circuit controls the second Schmitt trigger, which thereby produces an output signal with a time-distar.ee that is greater - than half of the . j . bit-time, thereby suppressing the non-relevant changes in phase of the input signal. The output signal from the second Schmitt trigger finally is used to control the D flip-flop, which provides the demodulated bit-sequence at its Q-output. Figs. 7 and 8 show simplified block diagrams for the blocks uD, 2_ SAU, and SPU in Fig. 1. As the invention does not primarily concern these parts of the data transmission arrangement, they will only be briefly described, reference being made instead to the extensive literature in this field. As such, the microcomputer uD includes a microprocessor uP with »c accompanying data memory M ' , program memory P , and terminal addressing means ADDR. The terminal address can be obtained by strapping. A timing circuit T and a monitoring circuit WD are also connected to uP. In addition, there is included a decoder DEC with the task of giving information the proper form for communication _ 0 between uP and the block SAU. As is shown in Fig. 8, input and output control in the signal adaption unit SAU occurs through I/O of information to input and output ports PI, P2, , P3,... which preferably work with 8 bits. In the signal processing unit SPU the signals to and from the connected 35 indicator lamps, control relays, sensors, monitoring contactors, etc., are given suitable form for communication with the ports PI, P2 , P3 , in SAU . Fig. 9 shows a detailed circuit diagram for the opto-switch B9 an the current sink BIO in Fig. 3. The signal from the phase-shif modulator B8 (UB8:2 in Fig. 4) is fed, via an output stage, construc ted around a PNP-transistor, to the input of the opto-switch OP. O includes, as shown, a light emitting diode and a photo-transistor The output signal from OP controls the current sink BIO, which i constructed of diodes, resistors and an NPN-transistor. Due to th effect of the opto-switch upon the base voltage of the transistor the current can be drawn over the path D, T, R. The magnitude of th diminished current is determined by R and Z. It will be noticed tha this in no way implies a short-circuiting of the two-lead cable L This is a demand, as L must be capable of supplying power to th terminal units. Fig. 10 shows a detailed circuit diagram for the demodulator B7 i Fig. 3. The demodulator is constructed as a two-frequency dis criminator and includes a differential amplifier with the inpu components connected as shown. During the time intervals when th discriminator receives pulse groups in the input signal UB6:2 in Fig 4, the differential amplifier produces a high-level signal, while zero-level signal is produced during the intervals with no pulses, whereby the output signal receives the form of UB7:2 in Fig. 4. Fig. 11 shows a detailed circuit diagram for the phase-shif modulator B8 in Fig. 3. This is constructed of integrated circuit where the nomenclature for the inputs and outputs used on the respec tive integrated circuit package has been indicated. This circuit o the type CD 4030, 2D flip-flops of the type CD 4013, an AND circui of the type CD 4011, an OR circuit of the type CD 4011, and a inverter of the type CD 40106. All of these components are manu factured by RCA Semiconductor, and are connected as shown in Fig. 11. From ι_JD bit-sequences in accordance with RS 232 standard ar obtained, which are presented to B9 in phase-modulated form from th Q-output of the D flip-flop, Dl. The counter is fed at 10 with clock signal, the frequency FCL of which is 16 times the bit-fre quency. For producing necessary control conditions, FCL scaled dow by factors of 8, 16, 64, and 256, respectively, is derived from th OMPI counter. The output signal from the exclusive OR circuit is presented at the D-input of Dl and is high when either the bit-sequency or FCL/16 is high. Dl is triggered at input 11 by FCL/8. The D flip-flop D2 has the task of giving the counter and Dl the correct starting signal, depending upon the bit-sequence. As such, the Q-output is connected to the reset-inputs RST1 of these components. The AND circuit receives FCL/64 and FCL/256, its output signal, via the OR circuit, being presented at the reset-input RST2 of D2, which thereby is periodically reset in accordance with a chosen message length. D2 can even be reset, via the OR circuit by a special main reset signal MR. OMH

Claims: CLAIMS 1. An arrangement for bi-directional transmission of bit-sequence between a central control unit (CCU) and terminal units (TU) connec ted to said central control unit by a transmission line (L), ove which said terminal units can, upon need, be supplied with power fro a direct current power source at said central control unit, c h a r a c t e r i z e d in that said transmission line comprising two-lead cable to which a plurality of terminal units (TU1, TU2,,, are connected in parallel, and to which said central control uni (CCU) is connected via a central line unit (CLU), said central lin unit comprising, for transmission, a generator (A2), controlled b said bit-sequences (BS, Fig. 4), for producing a bit-sequenc modulated transmission frequency signal, and an output stage (A3) fo superimposing said transmission frequency signal upon a direc voltage signal (VDC) produced by said direct current power source each of said terminal units being connected to said two-lead cabl via a terminal line unit (TLU) which, for reception, comprises mean (B4, B5, B6, B7) for reconstructing transmitted bit-sequences fro said transmission frequency signal, and which, for transmission comprises a current sink (BiO), controlled by bit-sequences, fo producing a bit-sequence modulated current variation in said two-lea cable, said central line unit (CLU) comprising, for reception, detector (A4) , connected in series with said two-lead cable, fo sensing said current variations, and further comprising means (A7, A8, A9, AlO) for reconstructing bit-sequences from the output signa of said detector, wherein the input and output circuits of sai central line unit and said terminal line units which are connected t said two-lead cable have high impedance for both frequency signal and direct voltages, and in that a terminal line unit, in certai cases, comprises means for reception of direct current power, havin high impedance for frequency signals, whereby transmission occurs i one direction with a frequency signal superimposed upon a essentially stable direct voltage level on said transmission line, retaining the possibility of supplying power to said terminal units. 2. The arrangement according to Claim 1, Λ. IPO c h a r a c t e r i z e d in that said generator (A2) comprises a sine-wave generator for producing a sine-wave transmission frequency signal, the frequency of which alternates, dependent upon bit-se¬ quence information. 3. The arrangement according to Claim 2, c h a r a c t e r i z e d in that said sine-wave generator I s made to alternate between a sine-wave signal and an absence of said sine-wave signal, whereby said transmission frequency signal receives the form of a frequency-shift signal, the frequency of which alternates between a predetermined frequency and zero frequency. 4. The arrangement according to Claim 2 or 3, c h a r a c t e r i z e d in that said sine-wave generator, dependent upon control information with respect to a group of terminal units, produces a transmission frequency signal containing at least one specific frequency for said group, whereby selective addressing of said group is made possible. 5. The arrangement according to any of the preceding Claims, c h a r a c t e r i z e d in that said detector (A4) comprises a resistor (F) , connected in series with said two-lead cable, over which is produced a voltage, which varies according to the current drawn from said two-lead cable, and which is fed to said reconstruc¬ tion means (A7, A8, A9, AlO). 6. The arrangement according to any of the preceding Claims, c h a r a c t e r i z e d in that said current sink (BIO) comprises a current loop, connected in parallel to said two-lead cable, in which the conductibility can be made to alternate between zero and a value which gives a current of appropriately predetermined magnitude for the detectability of said current variation, whereby the direct voltage level on said two-lead cable can be retained essentially unchanged. 7. The arrangement according to Claim 6, c h a r a c t e r i z e d in that said current loop comprises the emitter-collector path in a transistor (T), connected in series with a current limiting resistor (R.) , whereby the base of said transistor receives a voltage which varies according to a bit-sequence signal. 8. The arrangement according to Claim 6 or 7, c h a r a c t e r i z e d in that said terminal line unit (TLU comprises a modulator (B8) for phase-shift modulation of a bit-se quence signal prior to conveyance to said current sink, wherein sai conveyance occurs, preferably via an opto-switch (OP), by mean permitting galvanic insulation from said transmissi * on line. 9. The arrangement according to any of the preceding Claims, c h a r a c t e r i z e d in that said transmission frequency signal have a frequency which is at least a factor of 3 times higher tha the bit frequency of said bit-sequences. 10. The arrangement according to any of the preceding Claims, c h a r a c t e r i z e d in that said means for reconstruction o bit-sequences in said central line unit (CLU) comprise, in order fro the output of said detector (A4) , a high-pass filter (A5) wit cut-off frequency somewhat higher than the signal frequencies used, differential amplifier (A7) for amplifying pulse signals, a low pas filter (A8) with cut-off frequency somewhat higher than the frequenc of the pulses produced by said current variation, means (A9) fo restoring the square-wave character of said pulses, and a demodulato (AlO) for reconstructing transmitted, preferably phaseshif modulated, bit-sequences. 11. The arrangement according to any of the preceding Claims, c h a r a c t e r i z e d in that said means for reconstructin bit-sequences in said terminal line unit (TLU) comprise, as seen fro said two-lead cable, an input stage (B4) for level adaption o frequency signals received from said central line unit (CLU) and fo suppression of signals with lower frequency, said input stage furthe comprising means for galvanic insulation from said transmission line a low-pass filter (B5) with cut-off frequency somewhat higher tha said frequency signals, means (B6) for restoring the square-wav character of received pulses, and a demodulator (B7), preferably two-frequency discriminator, for demodulating a frequency-shif modulated transmission frequency signal.

Inventors: RUUS J, THERN R
Applicants: DIANTEK HB, RUUS J, THERN R
Application year: 1980
Main classification: H04Q9
IPC codes: H04B3, H04L5, H04L27, H04Q9