METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WHEREIN FIRST AND SECOND LAYERS ARE FORMED

Abstract: A layer of photoresist 16 having a generally flat surface is formed on a layer of PSG 15 having a projection thereon. A non-selective dry etching process using a reaction gas is effected in which a layer 16 and 15 are etched at equal rates. The etching process may be plasma etching using a mixture of a flouride compound gas and oxygen gas. Reactive sputter etching or reactive ion etching can also be used. The photoresist of layer 16 could be replaced by polyimide or liquid glass. PSG layer 15 could alternatively be a layer of polycrystal line silicon or wiring conductor. In each case, the use of a reaction gas mixture which ensures equal etching rates provides a flat surface at the finish of etching.

Description: Methodsof Manufacturing Semiconductor Devices This invention relates to methods of manufacturing semiconductor devices. In recent years, efforts have been made to make semiconductor chips and wiring conductors on such chips minutely small and to arrange the conductors in multiple layers for the purpose of increasing compactness and packing density of semiconductor devices such as large scale integration circuits (LSI). In addition, there is a need to increase the reliability of semiconductor devices, certainly reliability should never be reduced, even when effecting such miniaturization of components and realizing multiple layer conductors. Figure 1 of the accomapnying drawings shows in cross-section a part of a semiconductor device with a conventional multiple layer conductor structure. The device of Figure 1 comprises a silicon substrate 1, a diffusion layer 2, an electrode 3 of aluminium which is also used as an interconnection wiring conductor, an aluminium conductor 4, an insulating layer 5 of SiO2 on the semiconductor substrate, an insulating layer 6 of phospho-silicate glass (PSG) which is between other layers and a surface protection layer 7 of PSG. With such multiple layer wiring conductors as are illustrated in Figure 1, there is a danger of conductor disconnection at steps A, indicated in the Figure indicated in the Figure/a anger of a short-circuit at step B indicated in the Figure due to cracking of the insulating layer interposed between conductor layers (this insulating layer will be called hereinafter an an interposed insulator). In particular, the more layers of conductors there are the greater the possibility of disconnection of conductors. Japanese Patent Application No. 122559 of 1974 filed on 25th October 1974 and published without examination on 9th June 1976 under Publication No. 66778 of 19i6 discloses a method of making even and flat the surface of a semiconductor substrate having projections and dents. The method includes a step of forming on the substrate a film of a material which has an etching rate substantially equal to that of the semiconductor substrate and a step of etching to remove simultaneously the film and at least a part of a projection to make the surface of the semiconductor substrate flat. The use of sputter etching is proposed. Japanese Patent Application No. 25752 of 1975 filed on 18 October 1975, which was published on 21 April 1977 without examination under Publication No. 49772 of 1977, makes a similar disclosure which differs from the disclosure mentioned above only in that etching is effected by means of a physical etching process utilizing ions. The two documents mentioned above are particularly directed to a means of making flat a surface of semiconductor substrate having projections and dents. For such a substrate, etching is effected in a manner not only sufficient to remove projections, but is carried out further so that the surface of semiconductor substrate is etched until the substrate surface reaches the bottom of the deepest dent thereby to remove the dents. According to the present invention there is provided a method of manufacturing a semiconductor device, device, wherein first and second layers are formed, the second layer on the first, the first layer having the projections or indentations and/stehceondlayer being such that a generally flat top surface is provided thereby despite the projections and or indentaions of the first layer, wherein a non-selective dry etching process is effected wherein the first and second layers are etched at substantially equal rates. Embodiments of this invention use dry etching processes which involve the use of a mixture of gases as reactive gas. The mixture is such that the first and second layers, of different materials or properties, are etched at substantially equal rates. The present invention is concerned with methods of manufacturing semiconductor devices which reduce, and if possible eliminate altogether, dangers of disconnection and short-circuiting of wiring conductors in the device. This invention is concerned with avoiding the dangers of disconnection by eliminating steps or differences of levels of layers in a multiple layer wiring conductor structure. Briefly in one method embodying this invention a multiple layer conductor structure is formed by the steps of forming, on an insulation layer and a metal conductor layer already formed, an interposed insulator layer which is thicker than the metal conductor layer, forming on the interposed insulator layer a layer, for example of resinous coating material, having a flat surface, Ihen etching the interposed insulator and coating material. For the etching a gaseous mixture is used as a reactive gas. In the mixture partial pressures of a gas of a fluoride compound (such gas to be called hereinafter a fluoride gas) and i eiaSso that in a plasma etching process the etching rate of interposed insulator and that of the resinous coating material are equal, and plasma etching is carried out to expose the surface of said interposed insulator layer in a flat condition. - Furthermore, for the resinous coating material, a photoresist or a polymer resinoid such as a resin in the inter-related group of polyimide (such resin to be called hereinafter a polyimide resin) is preferable. As an interposed insulator, phospho-silicate glass (PSG) silicon dioxide (so4) or silicon nitride (Si3N4) are preferable. CF4, F. 2 and CF5.-Clare preferable as the fluoride compound used in the aforementioned plasma etching process. Neither of the two Japanese patent documents mentioned above discloses plasma etching. The present invention is also concerned with the formation of V-groove (or U-groove) isolation regions with a polycrystal (VIP) structure. Briefly, in an embodiment of this invention a layer of, for example, resinous coating material having a flat surface is formed over a layer of polycrystal silicon and plasma etching, for example, is effected with a flouride gas/oxygen gas mixture as reactive gas, with partial pressure of the gases in the mixture set so that the etching rates of the polycrystal silicon and the resinous coating material are equal. The present invention is further concerned with methods wherein.an electrode or wiring metal layer and a layer of, for example, resinous coating material which is formed over the electrode or wiring layer are etched by a dry etching process, such that the wiring layer and the coating material layer are etched at equal rates. The etching may be, for example, reactive sputter etching or plasma etching using a reactive gas which is a gaseous. mixture of hydrogen and carbon tetrachloride (CCl4) for example.- Reference is made, by way of example, to the accompanying drawings, in which: Figure 1,:as mentioned above, is a crosssectional view generally depicting a part of a. conventional semiconductor device with a multiple layer conductor structure, Figure 2 is a graph illustrating the relationship between the etching rates of an interposed insulator layer and a resinous coating material and partial pressure of oxygen gas in a gaseous mixture of fluoride gas and oxygen gas, Figures 3 to 5 are respective cross-sectional views generally illustrating steps involved in forming multiple layer conductors by a method embodying the present invention, Figure 6 is a schematic representation of a plasma etching device used to carry out a method embodying the present invention, Figure 7 is a schematic cross-sectional view illustrating a V-groove Isolation Polycrystal (VIP) structure, Figure 8 is a cross-sectional view schematically illustrating the VIP structure before plasma etching according to a method embodying the present invention has been carried out, with a layer of resinous coating material formed thereon, Figures 9 to 11 are respective graphs, similar to the graph of Figure 2, the resinous coating material with which the graph of Figure 11 is concerned being different. from that with which the graphs of Figures 2, 9 and 10 are concerned, and Figures 12 to 15 are respective cross-sectional a views illustrating/further embodiment of the present invention. In order to select a suitable partial pressure of oxygen gas in gaseous mixture of fLuoride gas and oxygen gas, experiments were conducted first to determine etching rates of materials to be used in one method embodying this invention; namely etching rates of an interposed insulator and a resinous coating material, under various partial pressures were studied. For example, r C2F6 gas, a negative photoresist known by the brand name OMR-83, a product of Tokyo Oka Co., Ltd. of Kawasaki City, Kanagawa Prefecture, Japan, and phospho-silicate glass (PSG) were picked respectively as examples of fluoride gas, resinous coating material and interposed insulator to be used, and etching rates were determined in plasma etching conditios set up as follows: C2F6 gas pressure within a reactor tube: 0.5 Torr etching time: 3 minutes applied high frequency power: 300 watt temperature within the reactor tube when etching commenced: 1200C phosphor (us) concentration of PSG: 14% The results of the experiments are reflected in the graph of Figure 2 in which the line A relates to the PSG, the line B relates to the negative resist, and the ratio of the partial pressure of oxygen gas to the total pressure of the mixture of fluoride gas and oxygen gas corresponding to a point where the lines A and B intersect indicates the condition under which the etching rates of the interposed insulator and the resinous coating material are equal. The resinous coating material is etched through an oxidation reaction by the plasma of the oxygen gas. The term "etching" herein includes such an oxidation process of a resinous material to remove a layer of the material gradually. Next, the steps involved in forming multiple layer wiring conductors in a semiconiictor device by a method according to the present invention will be explained. As shown in Figure 3, on a semiconductor substrate 11 and a diffusion layer 12 formed therein, an insulation layer 13 approximately 0.5 pm thick (which is a layer of SiO2 where the semiconductor substrate is of single-crystal silicon) and an electrode/interconnection wiring conductor layer 14 of aluminium for example approximately 1.0 m thick are formed. Thereafter, an interposed insulator 15 of PSG for example approximately 2.0 yum thick, thicker than the conductor layer 14, is formed by chemical vapour deposition or an evaporation process. On said interposed insulator 15, a layer of resinous coating material, for example negative photoresist, approximately 1.5 cm thick, is so formed by a conventional spin coating process that its surface becomes flat. Thereafter, the substrate 11 is placed in a conventional plasma etching apparatus to effect plasma etching under the conditions specified above, with fluoride gas and oxygen gas being supplied under various partial pressures as described before. The etching apparatus is schematically depicted in Figure;)6. In this apparatus C2F6, CF4 or C2F5Cl and 2 are supplied via flow meters 31 to a quartz furnace tube 32 provided with gas nozzles 35 and sealed by a lid 37. A generator 33 of r.f. power of for example 13.56 il{z is connected to a plasma generator 34. An exhaust 36 is connected to a vacuum pump (not shown) to keep the pressure within the tube at a predetermined value, for example 1 Torr. Details of the device and explanation thereof are omitted because the structure and operation of such a device are generally known in the art. In such an etching apparatus; plasma etching is carried out under the predetermined partial pressure values of the oxygen gas and the fluoride gas, both of which are about 0.5 Torr as shown in Figure 2. The etching rates of the PSG and the photoresist are equal under these conditions. There are two ways in which the abovedescribed plasma etching can be terminated. One way is to end the etching at exactly the moment at which the surface of the conductor 14 is exposed. Thereafter, PSG is deposited again until the PSG layer is about 1.0 fim thick. The condition of the surface of the interposed insulator 15 at this time is as shown in Figure 4. The other way is to conclude etching when a condition as shown in Figure 4 is reached wherein the surface of the interposed insulator 15 is flat. By this time, the interposed insulator 15 would have been etched off to approximately 1.0yam in thickness. Termination of the etching is determined in either case by first calculating the length of time that will be required for etching off the interposed insulator to 1.0 sm in thickness, then confirming the actual etching off thereof. In a similar manner, a second conductor layer 17 and an interposed insulator layer 18 are formed to produce multiple layer wiring conductors as shown in Figure 5, devoid of steps such as A and B in Figure 1 whichare present in the conventional art. In order to interconnect the conductors 14 and 17 of Figure 5, the conductor 17 is formed after a window (not shown) has been opened in the interposed insulator 15. Reverting to the relationship between the etching rates of PSG and the resinous coating material and the partial pressures of the gaseous mixture used, further experiments were conducted. In one experiment, the results of which are shown in Figure 10, the negative photoresist OMR-83 mentioned above, and PSG were again selected, but a gaseous mixture of CF4 and O2 was used. Total pressure of the gaseous mixture was set at 1 Torr and r.f. power at 300W. In another experiment, the results of which are shown in Figure 11, PSG and a negative photoresist known by the brand name of OFPR-800, a product of Tokyo Oka Co., Ltd. were selected, using the same gaseous mixture ,as in the experiments of Figure 10. Total pressure of the gaseous mixture was set at 1 Torr, and r.f. power at 300V1. The horizontal axis of the graphs in Figure 10 and 11 represents the ratio of the partial pressure of oxygen gas to the total pressure given by the oxygen gas and fluoride compound gas in the etching apparatus, as in Figure 2. This invention is concerned also with plasma etching of polycrystal silicon in the manufacture of semiconductor devices. A most preferable application of the method of plasma etching with which this invention is concerned is found in the formation of V-groove isolation regions with a polycrystal (VIP) structure which are known in the art. Such a VIP structure is shown in the crosssectional view of Figure 7, and in general terms such a structure is one in which a V-groove is formed by means of anisotropic etching of silicon, whereafter polycrystal silicon is buried in the V-groove. First, a P-type single crystal silicon substate 21 is prepared, and an n-type silicon epitaxial layer 22 is grown thereon. The surface of the silicon substrate is then oxidized by thermal oxidation to form a layer 23 of silicon dioxide (SiO2) on which is formed thereafter a layer 24 of silicon nitride (Si3N4). By a conventional etching technique, windows are opened to the silicon nitride layer 24 and the silicon dioxide layer 23 after which etching is effected using anisotropic etching solution so that etching progresses to form a V-shaped groove until the tip of the V-shaped groove reaches the substrate 21. Thereafter, a layer 23' of silicon dioxide is formed in the V-groove and polycrystal silicon 25 is deposited thereon to fill up the V-groove to form a VIP structure which serves for the purpose of isolation. When burying the polycrystal silicon in the V-groove according to a conventional technique, polycrystal silicon forming the polycrystal silicon layer 25 was polished or ground by a chemical solution for example of polishing acids and by mechanical grinding to remove polycrystal silicon outside the V shaped groove to produce a flat surface as shown in Figure 7. An embodiment of the present invention offers a dry etching method instead of the conventional wet polishing described above. Such an embodiment uses plasma etching as explained hereinafter. In the method used the following steps are taken:- in the process of forming an isolation region by filling a,V-groove after a layer of polycrstal silicon with polycrystal silicon/has been formed on the surface of the V-groove, a layer of resinous coating material having a flat surface is formed on the layer of polycrystal silicon, then plasma etching is carried out by setting a partial pressure of oxygen gas in a gaseous mixture of fluoride gas,and oxygen gas used in the plasma etching such that etching rates of polycrystal silicon and the resinous coating material are equal. As to the resinous coating material mentioned above, photoresist or polymer resin such as polyimide resin is preferable. As for the groove, this may be formed as a V-groove made by anisotropic etching or as a U-shaped groove formed by an ordinary etching process. First, in-order to determine a suitable partial pressure of oxygen in the gaseous mixture of fluoride gas and oxygen gas, an experiment was carried out to investigate etoking-rates of the materials used, namely polycrystal silicon and resinous coating material under various partial presssures. A C F gas and a negative resist OMR-83, mentioned above, were selected respectively as fluoride gas and resinous coating material, and the condition for plasma etching was set as follows for obtaining etching rates: pressure of C276 gas within a reactor tube: 0.5 Torr etching time: 2 minutes applied r.f. power: 150W ratio of the area covered by the photoresist layer to the total area of test piece: 1/2 The results of the experiment are shown in Figure 9 in whioh the line A respresentsthe polycrystal silicon, and the line B the negative photoresist. The ratio of oxygen partial pressure corresponding to a point wherethe lines A and B intersect represent the condition wherein etching rates of the polycrystal silicon and resinous coating material are equal. As shown in Figure 8, on a layer 25 of polycrystal silicon, a layer 26 of resinous coating material, namely negative resist OMR-83, is formed by a well known spin coating method so that its surface becomes flat. Plasma etching is then carried out with the substrate 21 in a condition as shown in Figure 8, under plasma etching conditions described above with fluoride gas and oxygen gas being supplied at the determined rates in order to remove polycrystal silicon outside the V-groove as shown in Figure 7. The time at which such plasma etching should be ended is determined by calculating the thickness of polycrystal silicon relative to the etching rate. Etching is terminated when thatlayerof Si N Etchin than one third that of polycrysgai silicon, damage Since the etching rate of Si3N4/layer is negligible. to Si N Embodiments of the present invention also provide methods for obtaining a flat surface on a substrate wherein an electrode or wiring metal layer is etched by a dry etching process similar to the aforementioned process simultaneously with a resinous coating material so that finally the metal layer remains only in dents or grooves on the substrate, thereby to form an electrode or wiring pattern. Figures, 12 to 15 are cross-sectional views illustrating such an embodiment of the invention. In Figure 12 there are shown a silicon substrate 41, an SiO2 film 42, another SiO2 film 44 of a thickness of 0.8 Am formed by chemical vapour deposition with a window opened therethrough in accordance with a predetermined pattern (such film to be called CVD SiO2 film hereinafter), and a wiring conductor layer 43 of for example aluminium approxi al mately 1pm thick formed by a convention/evaporation technique on the entire surface of the silicon substrate including the surface of the films described above. The surface of said wiring conductor layer 43 forms a concave face at a opening (window) formed in the CVD SiO2 film 44. In this embodiment also, a photoresist by a brand name AZ 1870, a product of Tokyo Oka Co., Ltd. is applied by a well known spin coating method and baked at 120 C to form a photoresist film 45 of the thickness of approximately 0.5m and having a flat surface. To the silicon substrate 41 so far worked, reactive sputter etching or plasma etching is carried out for 21 minutes under reaction pressure of 0.25 Torr using a reactive gas which is a gaseous mixture of hydrogen (H2) and carbon tetrachloride (CCl4) mixed at a rate of 3/5. Under the above specified conditions, rates at which the photoresist film 45 and the aluminium layer 43 are etched are approximately in the same order of 600 A /minute and 650 A0/minute respectively, so that etchings of the film and layer progress substantially uniformly all over the surface to provide a structure shown in Figure 13 wherein the aluminium layer 43 remains only as a thin covering on the CVD SiO2 film. Thereafter, the mixing rate of the reactive gas mixture of H2 and CCl4 is changed to 4/5 and etching is carried out for approximately 7 minutes. Under such conditions rates at which the aluminium layer 43 and the CVD SiO2 layer are etched are substantially equal, so that etchings progress substantially uniformly all over the surface to produce a structure shown in Figure 14 wherein the wiring conductor 43 is buried in the CVD SiO2 film 44 with the surface of both being substantially the same height, thus providing a wiring conductor layer approximately 0.7yLAIn thick and which has a flat surface. With this embodiment, patterning of the aluminium wiring conductor layer 43 is effected simultaneously with the formation of a buried wiring layer having a flat surface, without resorting to a masking process, so that manufacturing steps are drastically simplified. After the steps described so far are finished, an insulation layer 46 is formed on top of which a wiring conductor layer 47 is formed, on top of which is formed a further insulation layer 48 as shown in Figure 15. The structure of Figure 15 is essentially equivalent to that shown in Figure 5. In order to provide an electrode which serves as outgoing connection wiring similarly to the conductor 14 of Figure 5, a window may be formed to the insulation layer 46 to interconnect the aluminium layer 43 and the conductor layer 47 by a conventional technique. In forming multiple layer wiring conductors according to embodiments of the present invention, the fi-rst described embodiment and the last described embodiment may be carried out alternately, or after a buried layer is formed as a first wiring conductor layer, second and subsequent layers may be formed by using the second embodiment. The present invention is not limited to the embodiments descr,ibed above, but may be modified and worked in various manners. For example, the material of the wiring conductors need not be aluminium, any wiring material generally used in the art may be utilized. Further, the insulation layers are not limited to a combination of CVD SiO2 film as a lower layer and the photoresist film as an upper layer. The lower layer may suitably be selected from PSG film and the like in order to realize insulation between layers of multiple layer wiring conductors, or passivation, or the upper layer may be made of such material as would make the surface of the layer flat. Therefore, a resinous coating material (e.g. photoresist) may be used as may high molecular weight materials such as polyimide or liquid galss, and as may a method in which covering by a film of phospho-silicate glass (PSG) is effected, and then the film heated and melted to make it flat. Polyimide, liquid glass or PSG may also be used in place of resinous coating material in embodiments as illustrated in Figs 2 -to 5 and 7 to 8. With respect to the manner of etching of the abovedescribed insulation film and wiring conductor, it is also possible to carry out reactive ion etching or plasma etching as alternatives to reactive sputter etching. Further, the reactive gas is not limited to a mixture of hydrogen (H2) and carbon tetrachloride (CCl4) > a mixture of hydrogen and a compound of chlorine containing hydrogen (H2) such as CHCl3 and CH2Cl2 or a gaseous mixture of carbon tetrachloride (CCl4) and oxygen (02) may serve the same purpose if the wiring conductor is aluminium. It may be possible to use a compound of chlorine containing hydrogen in a mixture with oxygen. As has been described, conventional wet etching is replaced by the dry etching because of the plasma etching so that there is no need to use a chemical solution, for polishing. There will be no need therefore to be concerned about the problems of contamination by alkaline metals contained in such solution, and a device and process for grinding and polishing will become unnecessary in the process of the invention. It should be appreciated that it may be possible to substitute for oxygen 2 in a gaseous mixture used as reaction gas in etching in embodiments of this invention. For example, other types of oxidising gases containing non-essential ingredients could be 1Phus, considered/an insulator layer and a metal conductor are formed in advance, an interposed insulator is formed on the insulator layer and the metal conductor with the thickness of the interposed insulator layer thicker than that of the metal conductor , a layer of resinous coating material, for example, is formed flat on the interposed insulator layer, and after selecting a partial pressure of oxygen gas in gaseous mixture of a fluoride gas and an oxygen gas such that etching rates of the interposed insulator layer and the resinous coating material are equal, plasma etching is carried out to expose the interposed layer with a flat surface. In another method embodying this invention, a layer of polycrystal silicon is formed in a V-groove in the process of forming an isolation region in a semiconductor substrate, a layer of coating material is formed flat on the layer of polycrystal silicon, and plasma etching is carried out after selection of a partial pressure of oxygen gas in the mixture of fluoride gas and oxygen gas such that etching rates of polycrystal silicon and the coating material are equal. Further, in another embodiment of this invention a wiring conductor is formed on the surface of a semiconductor substrate, an insulation film is formed to cover the entire surface of the semiconductor substrate (including the wiring conductor), and the insulation film and unnecessary conductor portions are then removed by a non-selective dry etching process which preserves the flatness of the surface being etched.

Claims: CLAIMS 1. A method of manufacturing a semiconductor device, wherein first and second layers are formed, the second layer on the first, the first layer having projections or indentations and the second layer being such that a generally flat top surface is provided thereby despite the projections and or indentations of the first layer, wherein a non-selective dry etching process is effected wherein the first and second layers are etched at substantially equal rates. 2. A method as claimed in claim 1, wherein the non-selective dry etching process involves the use of a gaseous mixture as a reactive gas. 3. A method as claimed in claim 1 or 2, wherein the said first layer is an interposed insulator layer and is formed on an insulator layer and a wiring conductor layer on a semiconductor substrate, the said first layer being thicker than the wiring conductor layer. 4. A method as claimed in claim 3, further comprising the step of forming another conductor layer on the flat surface of the first layer left after the first and second layers have been etched. 5. A method as claimed in any preceding claim, wherein the first layer comprises either phospho-silicate glass, silicon dioxide or silicon nitride. 6. A method as claimed in claim 1 or 2, wherein the said first layer is of polycrystal silicon and is so formed as to fill a groove in a semiconductor substrate, thereby to provide an isolation region. 7. A method as claimed in claim 6, comprising a preliminary step in which a silicon nitride layer is formed on the semiconductor substrate prior to formation of the said first layer of polycrystal silicon, and wherein etching is terminated when the silicon nitride layer is exposed. 8. A method as claimed in any preceding claim lasmathenon-selective dry etching plasma or wherein the non-selective dry etenlng process/ln welch a gaseous mixture of a flouride compound gas and an oxygen gas is employed, the partial pressures of the gases in the mixture being so selected that the first and second layers are etched at substantially equal rates. 9. A method as claimed in claim 8, wherein the flouride compound gas is C2F6 or CF4 or C2F5Cl. 10. A method as claimed in claim 1, 2 or 3, wherein the said first layer is a wiring conductor layer. 11. A method as claimed in claim 10, wherein the wiring conductor layer is of aluminium. 12. A method as claimed in claim 10 or 11, read appended to claim 1 or 2, wherein the etching process comprises reactive sputter etching, reactive ion etching or plasma etching. 13. A method as claimed in claim 12, wherein a reactive gas used in the etching process comprises a gaseous mixture of hydrogen with either carbon tetrachloride (CC14) or CHIC13 or CH2Cl2, or comprises a gaseous mixture of CCl4 and oxygen. 14. A method as claimed in any one of claims 10 to 13, wherein the said first layer is formed on a layer of phosphosilicate glass, or -on a layer of SiO2 deposited by chemical vapour deposition. 15. A method as claimed in any preceding claim, wherein the said second layer is of a resinous material. 16. A method as claimed in any one of claims 1 to 14, wherein the' said second layer is of photoresist, or polyimide, or liquid glass. 17. A method as claimed in any one of claims 1 to 14, wherein the second layer is of phospho-silicate glass heated and melted.

Inventors: ABE, RYOJI, TOKITOMO, KAZUO
Applicants: FUJITSU LIMITED
Application year: 1980
Main classification: H01L21
IPC codes: H01L21, H01L23