SEMICONDUCTOR DEVICE

Abstract: A bipolar transistor as operates reversely having a first conductivity type base region (9a, 9b) is formed in a second conductivity type semiconductor region (7) at its main sur­ face side. A second conductivity type collar region (18) is formed in contact with or close to the base region (9a). The collar region (18) contains phosphorus and arsenic at high concentration, which are injected thereinto by diffusion pro­ cess.

Description: Semiconductor Device and its Manufacturing Method The present invention relates to a semiconductor device and its manufacturing method and, more particularly, to a semiconductor device having a bipolar transistor with an improved current amplification factor as reversely operates with respect to the conventional transistor and its manufacturing method. An integrated injection logic (I2L) circuit is known as an integrated circuit including a bipolar transistor as reversely operates. Part of the integrated circuit of this type is illustrated in cross section in Fig. 1 and is disclosed in IEEE, J, of Solid-State circuits, SC-9, PP, 206 to 283, 1971. In Fig. 1, an I 2L gate 3 and a linear npn transistor 4 are formed on a p + type semiconductor substrate 1, with a p isolation region 2 disposed therebetween. Only the 12 L gate will be described for simplicity. On the p-type substrate 1 are formed an n -type buried region 5, an n -type collar region 6 and an n-type region 7. Within the n-type region 7 are formed a p-type injector region 8, a p-type base region 9, and an n -type collector region 10 formed within the p-type base region 9. In the figure, INJ, B, C and E represent injector, base, collector and emitter terminals, respectively. Those semiconductor regions 7, 9 and 10 cooperate to form a bipolar transistor as operates reversely. Here, "bipolar transistor as operates reversely" means a transistor of the type in which the base current flows into the collector and will often be referred to as a upside-down transistor. + The n collar region 6 prevents holes injected from the base region 9 from flowing laterally, thereby to increase a current amplification factor of an npn transistor of the reverse-operation type. To prevent the lateral injection of the holes, it is more desirable as the impurity concentration of the n collar region 6 is higher. Further, it is necessary that the region 6 is diposed closest to the base region 9. Conventionally, the collar region 6 was formed in a manner that phosphorus is diffused at high concentration from the main surface of the semiproduct by using phosphorus oxychloride (POC23). When the concentration of phosphorus is excessively increased in the surface region of the collar region 6, a number of lattice defects are produced in the surface region, and the lattice defects extend from the n collar region 6 to the base region 9 of the upside-down npn transistor. As a result, the current amplification factor of the upside-down npn transistor descreases contrary to expectation. Therefore, the surface concentration of the n collar region 6 can not be increased sufficiently and the current amplification factor of the upside-down npn transistor can not be increased. Accordingly, an object of the present invention is to provide a semiconductor device including the upsidedown bipolar transistor of which the reverse-directional current amplification factor is remarkably increased by completely removing the lattice defects in the n collar region, and a manufacturing method of the semiconductor device. A semiconductor device according to the present invention comprises a semiconductor region of a second conductivity type; a bipolar transistor as reversely operates which is formed in the semiconductor region of the second conductivity type at main surface side thereof, and has a first conductivity base region; and a collar region of the second conductivity type which is deeper than the base region, contacts with or is close to the base region, and extends opposite to the main surface of the second conductivity type region; the collar region being formed by diffusing phosphorus and arsenic at high concentration. According to another aspect of the invention, there is provided a method of fabricating a semiconductor device comprising steps of forming a bipolar transistor as operates reversely having a first conductivity type base region in a semiconductor region of a second conductivity type of which the main surface has the crystalline direction of < 111 > , and forming a collar region, which is in contact with or is close to the base region and extends opposite to the main surface of the second conductivity type semiconductor region, by diffusing phosphorus and arsenic. Other object and features of the present invention will be apparent from the following description taken in connection with the accompanying drawings, in which: This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: : Fig. 1 shows a cross sectional view of a conven 2 tional semiconductor device including an I2L gate and an npn transistor as operates normally; Fig. 2 shows a cross sectional view of an embodiment of a semiconductor device including an I2L gate and an npn linear transistor as operates normally according to the present invention; Figs. 3A to 3F show a sequence of steps for manufacturing the semiconductor device shown in Fig. 2; Figs. 4A and 4B show a manufacturing process for manufacturing another embodiment of the semiconductor device according to the invention; Fig. 5A shows a photograph for showing lattice 2 defects occurring in the I2L gate to which the conven- tional technique is applied in its fabrication; ; Fig. 5B shows a photograph for showing lattice defects occurring in the I2L gate to which the present invention is applied in its fabrication; and Fig. 6 shows characteristic curves of the current amplification factor ( up) of the I2L gate with respect to the collector current, in which a curve 35 represents the characteristic when the present invention is used and a curve 36 represents the characteristic when the prior art is used. Reference is made to Fig.2 illustrating in cross section an embodiment of the semiconductor device including the I 2L gate 3 and the npn linear transistor 4, which are formed on the p-type substrate 1, like Fig. 1. In Fig. 2, like reference numerals are used for designating like portions in Fig. 1, for simplicity. The I 2L gate 3 includes the n region 5, the injector region 8 formed in the n-type region 7 enclosed by the + + n region 5 and n collar region 18, an external base region 9a, an internal base region 9b, and the + n collector region 10 enclosed by the external base region 9a and the internal base region 9b. Those regions 5, 18, 7, 9a, 9b and 10 cooperate to form the upside-down bipolar transistor. The npn linear tansistor 4 is electrically separated from I 2L gate 3 by the p isolation region 2, and is comprised of the + + n region 5, an n high concentration collector region 21, the n-type region 7, a p-type base region 19, and an emitter region 20 enclosed by the base region 19. The regions, 8, 9a, 10 and 18 are connected to its related circuit by electrodes INT, B, C and E. The regions 20, 19 and 21 are connected to its related circuit by the electrodes E, B and C. The n collar region 18 of the + I L gate extends to the n region 5 in contact with or close to the base region 9a. The feature of the present invention resides in that the collar region 18 is formed by diffusing phosphous and arsenic at high concentration. In the present embodiment, the n high concentration collector region 21 of the npn linear transistor 4 is also formed in the same manner. Reference numeral 17 designates an insulating layer. An example of the manufacturing method of the semiconductor deivce shown in Fig. 2 will be described referring to Figs. 3A to 3F. Although the fan-out of the 12 L gate 3 of the device shown in Fig. 2 is one, two or more fan outs, npn linear transistors, resistors and capacitors and the like may be formed on the same chip. As shown in Fig. 3A, impurity material such as Sb, As and P is diffused from the main surface of the P type substrate 1 having a specific resistance of 10 Q cm, of which the crystalline direction is < 111 > thereby to from + the n buried region 5 and then the n-type epitaxial region 7. As a matter of course, there arises no problem when the crystalline direction of the main surface of the semiconductor substrate 1 is < 100 > . When the breakdown voltage between the emitter and the collector of the linear transistor 4 is demanded to be 10 V or more, it is preferable to use the semiconductor substrate 1 with the (111) surface as the inversion voltage of a field region can be raised. The specific resistance and the thickness of the n-type epitaxial region 7 are determined by considering the breakdown voltage necessary for the linear transistor 4 coexisting with the 12 L gate. Normally, those are selected to be 0.5 ¯cm to 2 Q ##cm for the specific resistance and 5 pm to 20 m for the thickness. Then, as shown in Fig. 3B, a thermal oxidation layer 22 (six2 layer) is formed on the surface of the epitaxial region 7, holes 23 are formed at the locations corresponding to regions to be + p isolation regions 2, an insulating layer 24 con- taining boron is formed on the oxidation layer 22, and the p isolation regions 2 are formed by diffusing boron. Boron silicate glass (BSC) containing boron at high concentration is generally used for the insulating layer 24. After forming the isolation regions 2, the entire thermal oxidation layer 22 and the BSG layer 24 are removed and the thermal oxidation layer (SiO2 layer) 25 is again formed with the thickness from about 1000 A to 3000 A, as shown in Fig. 3C. Further, a resist pattern 26 is formed on the layer 25. An intrinsic base region 11 is formed by injecting boron ions into an instrinsic base region (the region for forming the internal base region 9b shown in Fig. 2) of the I 2L gate 3, by using the resist pattern as a mask. At this time, if necessary, boron is also injected into another region 12 form a high resistor, at the dosage of 5 x 1O12 -2 to form a high resistor, at the dosage of 5 x 1012 cm to 3 x 1013 cm 2. The acceleration voltage of the injecting ions depends on the thickness of the thermal oxidation layer 25, usually 50 keV to 200 keV. The depth of the intrinsic base region 11 is selected to be aprroximately 2.5 to 4 pm. Then, the resist pattern 26 is removed and a silicon dioxide layer 27 is formed, as shown in Fig. 3D, by a chemical vapor deposition process (CVD) using a chemical reaction of SiH4 and 02. At the locations where the collar region 18 and the high concentration collector region 21 are formed, holes 28a and 28b are formed in the thermal oxidation layer 25 and the CVD silicon dioxide layer 27. On the CVD layer 27 formed another silicon dioxide layer 29 preferred to as a (P + As) layerj containing phosphorus and arsenic. The (P + As) layer may be formed by mixing a mixed gas containing PH3 and AsH3 at the flow rate ratio of 4 : 1, into the gas containing SiH4 and 2 when they are ther + mally decomposed. The n collar region 18 and the high concentration collector region 21 may be formed by diffusing P and As at about ll00 C by using the (P + As) layer as a diffusion source. The depth of the n collar region 18 must be deeper than the depth of the intrinsic base region 11. As well known, the diffusion coefficient phophorus is larger than that of arsenic. Therefore, the n collar region 18 contains the phosphorus diffused deeply from the surface thereof and arsenic diffused shallowly from the surface. In this way, by simultanenously diffusing phosphorus and arsenic, the lattice defects (dislocation and the like) may be minimized which occurs in the collar region 18. Indivisual diffusion of phosphorus and arsenic may also effect the restriction of the lattice defect occurence. A preferable ratio of arsenic to phosphorus ranges 3 % to 40 % in the number of atoms. In the experiment conducted, when when the surface impurity concentration of the n collar 20 region 18 was set to 5 x 10 cm or more, the number -2 of the lattice deffects was 10# cm . Such number of 3 -2 lattice defects of 10 cm 2 were negligible in practical use. When only phosphorus was diffused by using phosphorus oxychloride POCK3, as described above, the number of the lattice defects (dislocation densitty) in 5 -2 the surface of the collar region 18 was 10 cm 2. From the experimental results, it will be seen that the pre sent invention may improve the lattice defects density of the n collar region 18 by two or more orders when compared to the conventional method. When the con current diffusion of phosphorus and arsenic is applied to a region to be a high concentration n collector region 21 of the linear transistor 4, as shown in Fig. 3D, the saturation voltage VCE(SAT) of the npn tran- sistor 4 may be decreased. In case where the silicon substrate is used, the dislocation is most likely to occur in the crystalline direction of < 110 > in the equivalent surfaces of (111). When only phosphorus is duffused into a region to be the n collar region 18 and a region to be the high concentration collector region 21 by the conventional process, a number of the disloca tions take place in those regions. In this case, the dislocation extends into the equivalent surfaces of (111) in the peripheral semiconductor region. The rate of the extension of the dislocation is specially accelerated near the surface of the semiconductor region. If the low saturation voltage is not required for the linear npn transistor 4 in its operation, there is no need of the high concentration for the collector region 21. When a pnp transistor (not shown) is provided on the chip on which the I2L gate 3 is formed, it is very effective to diffuse at high concentration phosphorus and arsenic in the base region of the pnp transistor. Specailly in the pnp transistor with a large current, the reduction of the base resistance is remarkably important and it is possible to prevent reduction of the current amplification factor in a large current range. After the diffusion of phosphorus and arsenic is + made into the region to be the n collar region 18 and the region to be the collector region 21, the (P + As) layer 29, the CVD silicon dioxide layer 27, and the thermal oxidation layer 25 are removed. In the next step, a thermal silicon dioxide layer 30 is formed, as shown in Fig. 3E and a resist pattern 31 is further formed as an ion injection mask on the layer 30. Through the pattern 31, boron ion is injected into the external base region 9a of the I2L gate 3, the injector region 8, and the base region 19 of the npn transistor 4. The concentration of the boron in the base region 19 is selected higher than that of the boron in the intrinsic base region 11, for the purpose of decreasing the specific resistance of the base region 19. The dosage of 14 -2 boron to be injected is selected to be 1 x 10 cm 2 and the acceleration voltage is selected to be 50 keV to 300 keV. The depth of the base region 19 is approxiamtely 2 m to 3.5 m, slightly shallower than the intrinsic base region 11. Afterward, the resist pattern 31 is removed and a CVD silicon dioxide layer 32 is deposited on the thermal silicon dioxide layer 30, as shown in Fig. 3F. In the next step holes are provided through the thermal silicon dioxide layer 30 and the CVD silicon dioxide layer 32 at the portions corresponding to the collector region 12 of the I2L gate 3 and the emitter region 20 of the npn transistor 4, as shown in Fig. 3F. A layer 33 like the (P + As) layer 33 used as the diffusion source when the n collar region is formed on the CVD silicon dioxide layer 32 and phosphorus and arsenic are simultaneously diffused on the collector region 12 of the I L gate 3 and the emitter region 20 of the linear npn transistor 4. Also in this case, phosphorus is diffused deeply while the arsenic is diffused shallowly into the near surface layer, so that no lattice defects take place in the collector region 12 and the emitter region 20. Also in this diffusion process, the ratio of arsenic to phosphorus in the number of stoms is selected to be 3 to 40 %. After the diffusion process to the collector region 12 and the emitter region 20 is completed, the insulating layer 30, 32 and 33 are holed at the portions corresponding to the regions 8, 9a, 12 and 18 of the I L gate 3 and the regions 20, 19 and 21 of the npn transistor 4 and electrodes for interconnections denoted as IN, B, C and E are formed. At this step, the fabrication process of the semiconductor device is completed. Figs. 4A and 4B illustrate a manufacturing process of another embodiment of the present invention. In the -l present embodiment, an epitaxial layer n 1 7 with a specific resistance of 2 ¯cm to 10 iZ ##cm is formed on a p- type substrate 1. By using the thermal difusion process for forming the p isolation region 2, phosphorus is deeply diffused into only one epitaxial layer of the 2 epitaxial layers on which the I L layer is formed thereby to form an n well region 7a. As a result, the impurity concentrations in the regions 5, 7a and 7 are decreased in this order. The specific resistance of the n well region 7a may be reduced to approximately 0.1 S-cm. In this way, when the I2L gate is formed within the n well region 7a, the switching speed of the I2L gate is increased to be about two times that when no n well region 7a is provided. Following the step shown in Fig. 4A, the steps shown in Figs. 3C to 3D are performed to form the semiconductor device shown in Fig. 4B. In semiconductor device shown in Fig. 4B, the reverse gain of or the reverse operation transistor was 30; an input frequency of a T-type flip-flop formed by the I L gate was 3 MHz; the power delay time product of the I 2L gate was 0.18 pJ (pico joule), the emitter-collector breakdown voltage (VCEO) was 40 V or more. Those values can not be obtained by the conventional device. Fig. 5A is a microscopic photograph for illustrating lattice detects when the collar region 18 is formed by using phosphorus oxychloride POC±3. Fig. 5B is a microscopic photograph for #illustrating the lattice defects when the collar region 18 is formed by diffusing phosphorus and arsenic according to this invention in place of POX3¯ The semiconductor devices of the both are fabricated by the same process except for the diffusion process of the collar region 18. The chips of the I2L gates of the both were etched by the Wright etching solution. As observed in the photograph shown in Fig. 5A, triangular etch pits arising from the disclocation occuring in the collar region overflows + into the active region other than the n collar region. Because of its high impurity concentration, the etching speed of the n collar region 18 is high. For this 5 -2 reason, the triangular etch pits were 10 cm or more, although those are hardly observed. Such lattice defects provide the recombination center of electrons and holes thereby to remarkably increase the base current of the upside-down transistor. Therefore, the current amplification factor of the reverse operation transistor is degraded. In the photograph shown in Fig. 5B, there were observed no etch pits due to the dislocation occuring in the collar region 18. When comparing the photographs in Figs. 5A and 5B, it is seen that the lattice defects occuring in the n collar + region may be restrained when the n collar region is formed by diffusing phosphorus and arsenic. As + described above, the lattice defects of the n collar region extends up to the active element region other than the I 2L gate. Therefore, in order to increase the current amplification factor of the reverse operation transistor, it is essential to prevent the lattice + defects from occuring in the n collar region. Turning now to Fig. 6, there is a graph representing a relation between a current amplification factor Sup of the reverse operation transistor and the collector current Ic. In the graph, a curve 35 represents the bup ¯ Ic relation of the upside-down transistor fabricated by the present invention. A curve 36 represents that of the transistor formed by the conventional process. In the curve 35, the maximum value of the is 45, which is about three times of the maximum up up in the curve 36. In the region where the Ic is small, the bup is decreased in the curve 36 while it is not decreased in the curve 35. It is apparent that the increase of the #up improves the operation speed of the I 2L gate and the noise margin is increased. The present invention which has been described by using the embodiment having the reverse operation npn transistor coexisting with the injector region, may of course be applied for the upside-down npn transistor not coexisting therewith. Also in the prior art linear npn transistor, the lattice defects in the high concentration collector region enters the base region, so that phosphorus is abnormaly diffused into the emitter region of the linear transistor. Because of this, the breakdown voltage between the emitter and collector of the linear npn transistor was reduced. The present invention solves this problem by forming the high concentration region of the linear npn transistor by diffusing phosphorus and arsenic. As a result, the yield of products is improved about two times compared to the conventional technique.

Claims: Claims: 1 A semiconductor device comprising a semiconductor region (7) of a second conductivity type; a bipola transistor as reversely operates (upside-down bipolar transistor) which is formed in said semiconductor region(7) of said second conductivity type at the main surface side thereof, and has a first conductivity type base region (9a, 9b); and a collar region (18) of the second conductivity type which is deeper than said base region (9b), contacts with or is close to said base region (9a), and extends opposite to the main surface of said second conductivity type region (7); characterized in that said collar region (18) is formed by diffusing phosphorus and arsenic at high concentration. 2. A semiconductor device according to claim 1, characterized in that the crystalline direction of said main surface of said second conductivity type semiconductor region (7) is < 111 > and the number of atoms of arsenic contained in said collar region (18) is 3 % to 40 % of that of phosphorus contained in said collar region. 3. A semiconductor device according to claim 1, characterized in that a first conductivity type injector region (8) is further formed at said main surface side of said second conductivity type semiconductor region (7), said injector region facing said upside-down bipolar transistor with part of said second conductivity type semiconductor region (7) intervening therebetween; said upside-down bipolar transistor includes a second conductivity type collector region (12) and said base region (9a, 9b) in contact with the surfaces of said collector region other than the surface thereof coincident with said main surface of said second conductivity type semiconductor region (7); and said injector region (8), said collector region (12), said base region (9a, 9b), said second conductivity type semiconductor region (7) and said collar region (18) cooperate to form an I 2L (integrated injection logic) gate. 4. A method of fabricating a semiconductor device characterized by comprising steps of forming a bipolar transistor as operates reversely (upside-down bipolar transistor) having a first conductivity type base region (9a, 9b) in a semiconductor region (7) of a second conductivity of which the main surface has the crystalline direction of < 111 > , and forming a collar region (18), which is in contact with or is close to said base region (9a) and extends opposite to said main surface of said second conductivity type semiconductor region, by diffusing phosphorus and arsenic. 5. A method of fabricating a semiconductor device characterized by comprising steps of forming a second conductivity type first semiconductor region (5, 7) on a main surface of a first conductivity type semiconductor substrate (1) of which the main surface has the crystalline direction of < 111 > ; forming a first conductivity type internal base region (9b) of a upside-down bipolar transistor in said first semiconductor region (5, 7), at its main surface side; forming a first conductivity type external base region (9a) enclosing the side wall of said internal base region (9b); forming a second conductivity type collector region (12) on said internal base region (9b); and forming a second conductivity type high concentration collar region (18) in contact with or close to said external base region (9a) by diffusing phosphorus and arsenic.

Inventors: OZAWA, OSAMU, SASAKI, YOSHITAKA
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1980
Main classification: H01L21
IPC codes: H01L21, H01L29, H01L27