PRINTER SUBSYSTEM WITH DUAL MICROPROCESSOR CONTROL

Abstract: A printer subsystem is interconnected with a host sys­ tem (1) from which it receives command and data informa­ tion and to which it provides status information. The printer subsystem has two microprocessors (200, 210), one of which communicates (200) with the host system for trans­ fer of command, data, and status signals and the other of which (210) directly controls the printer unit in the subsys­ tem especially with respect to the print assembly forms feed assembly, ribbon drive assembly, and print wire ac­ tuators. Interconnecting means (225, 226, 228) are provided between the first and the second microprocessors to re­ ceive command and data signals from the first micropro­ cessor to produce control signals and character image signals for use by the printer unit. Register means (225, 226) between the first and the second microprocessors are accessible by either microprocessor for entry of informa­ tion pertaining to operation of the printer subsystem and for intercommunication purposes between the two micro­ processors.

Description: PRINTER SUBSYSTEM WITH MICROPROCESSOR CONTROL Technical Field to which the invention relates This invention relates to a printer subsystem with microprocessor control and more particularly to printer control units for such subsystems. The printer subsystem is interconnected with a host system for receipt of command signals from such host system to perform various printing functions and of data signals to print characters of information cn a form. Two microprocessors are incorporated in the printer subsystem for controlling the printing operations. Relevant Background Art It has been customary in such printer subsystems to rel heavily on the host system for operational and printing control of the printer unit. In some cases, a limited amount of control capability is incorporated in the printer subsystem itself. In those subsystems where local control is provided in the form of control logic or local processor control, such control logic or processor control ordina--ly handles tasks in the printer subsystem in a sequential fashion resulting in somewhat slower response times and in some cases overloading of the control facility. In other printer subsystems, asynchronous operations are performed between two microprocessors sharing a common storage where various printer control blocks are queued. Such subsystems are described in an article published in the IBM Technical Disclosure Bulletin of June 1979 Vol. 22, No.1, p. 269j 270, 271 and entitled "Standard printer or I/O adapter control method and apparatus", b D.O. Hays, A.W. Maholick and N.N. Mize. A first microprocessor acts as a system adapter and loads received information in PCB (Printer Control Blocks). This micro processor puts a printer to a PCB on a work queue which allows asynchronous operation to take place with the various PCB's being queued in a random access memory. A second microprocessor operating as a printer adapter accesses the work queue PCBs in the random-access memory. In these previous printer subsystems, software and hardware mean must be provided to handle and queue the PCB in asynchronous operation. Disclosure of the Invention In accordance with the present invention, a printer subsystem is provided with a least two microprocessors, each being operable relatively independently of the other, being able to communicate with the other as the need arises and each having its assigned functions. Both of the microprocessors can operate concurrently to accomplish its assigned functions. In the preferred embodiment described herein, one of the microprocessors serves in a communications function to receive data and command information from a host system and to provide status information back to the host system, while the other microprocessor serves more directly to control the printer functions such as forms feed, ribbon feed, print drive, and the like. First interconnecting means between the first microprocessor and the host system receive command and data signals from said host system and transmits status signals back to said host system representation of various conditions in the printer subsystem. Second interconnecting means between the first and the second microprocessors are responsive to command and data signals received from the first micro process-or to produce control signals -and charact images signals for use by the printer unit during printing operations. Register means are also interconnected between the first and the second microprocessors, said register means being accessible by either microprocessor for entry of information pertaining to operation of the printer sybsystem and for intercommunication purposes between the two microprocessors. Third interconnecting means between the printer unit and the second microprocessor transfer command and data signals from the second microprocessor to the printer unit and transfer station signals from the printer unit to the second microprocessor. Each of the microprocessors has some diagnostic capability in its assigned area of functional responsibility. The dual microprocessor control system herein is described in conjunction with a high speed wire matrix printer that is provided with print heads in which print wires are located in a slanted wire image configuration in relation to the print line. This dual microprocessor control system allows functions in the printer to be handled concurrently. It also enables the display of the firing and/or misfiring of the print wires. Principles set forth herein are applicable to wire matrix printers, other print head structures and printers of a nonmatrix character, as well. Description of one way of carrying out the invention For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the description taken in connection with the accompanying drawings which illustrate only one specific embodiment. Brief Description of the Drawings Referring to the drawings Figure l is a simplified system diagram for the printer subsystem. Figures 2, 3 and 4 illustrate various systems in which the printer subsystem may be connected. Figure 5 illustrates a stream of information between the host system and the printer subsystem. Figure 6 illustrates significance of bits in the frames during a receive mode when infoimation is transferred from the controller to the printer subsystem. Figure 7 illustrates bit significance for the frames during a transmit mode when information is transferred from the printer subsystem to the controller. Figure 8 illustrates the bit configurations for printer addressing. Figure 9 shows command and data arrangements in the information stream. Figure 10 is a chart illustrating atypical transfer of data to be printed. Figures 11 and 12 illustrate representative operational and formatting commands. Figures 13 and 14 illustrate frame layout for status-reports during a Poll operation. Figure 15 illustrates the printer console and a number of printer components as well as forms feeding. Figure 16 illustrates an operator panel useful with the printer of figures 1 and 2. Figure 17 shows a mode switch for control of on-line, offline conditions. Figure 18 is an overhead view of the printer slightly from the rear of the unit showing the forms feed open. Figure 19 illustrates a print wire block assembly and associated guide. Figures 20 and 21 illustrate front and rear faces of the guide shown in figure 14. Figure 22 illustrates the arrangement of print wires in groups relative to a left margin in the printer unit. Figure 23 illustrates printing of characters at 10 characters per inch and 15 characters per inch. Figures 24 and 25 illustrate the print emitter and its operating scheme. Figure 26 is a generalized block diagram of the printer control unit shown in figure 1. Figures 27 and 28 further illustrate the arrangement of dots to form characters and the relationship of the print wires to the various character locations. Figure 29 is a block diagram of various circuit components used in the printer subsystem of Figures 1 and 2. Figures 30A and 30B, when arranged as shown in Figure 31, comprise a block diagram of the printer control unit including a Communications Microprocessor (CMM) and a Control Microprocessor (CTM) as well as a number of elements in the printer unit. Figure 32 illustrates a typical data transfer and printing operation in the printer subsystem. Figure 33 is a generalized flowchart of the operations performed by the Communications Microprocessor (CMM) shown in figure 3OA. Figure 34 is a generalized flowchart of the operations performed by the Control Microprocessor (CTM) shown in Figure 30B. Figures 35A-35P, when arranged as shown in Figure 36, represent a printer control unit that is generally based on the printer control unit shown in Figures 30A and 30B but which does have differences in some of the details of implementation. Figure 37 shows the assignment of the Read Only Storage and Random Access Memory modules in the Communications Storage of Figures 35L-35N. Figure 38 is a flowchart illustrating the diagnostic operation for the wire fire mapping. Figure 39 represents a possible printout of wire firing and misfiring somewhat modified to more clearly illustrate the operations involved in wire fire mapping. Description of Printer Subsystem and Printer Mechanisms In order to best illustrate the utility of the represent invention, it is described in conjunction with a high speed matrix printer, typically capable of printing in a high range of lines per minute on continuous forms. The particular printer subsystem described herein is associated with a host system or processor, responds to command and data signals from the host to print on the forms and in turn provides status signals to the host during operations. The printer itself is an output line printer designed to satisfy a variety of printing requirements in data processing, data collection, data entry, and communications systems. It can be used as a system printer or a remote work station printer. The following printer highlights are of interest: Print density of 10 or 15 characters per inch (25,4 mm) selectable by the operator or by the using system program; Condensed print mode, 15 characters per inch saves paper costs and makes report handling, mailing, re production, and storage easier; Line spacing of 6, or 8 lines per inch or any other line density selectable by the operator or by the using system program; Incremental and reverse forms movement selectable by the using system program; Sixteen selfcontained character sets selectable by the using system program with a base language selected by hardware jumpers. Special graphics ability (special characters, yraphs, plotting, etc.) selectable by the using system program; Matrix printing technology; Built-in diagnostics for problem determination by the operator; Microprocessor control unit; Maximum print line width - 330,2 mm. Maximum print positions for 10 characters per inch 132; Maximum print positions for 15 characters per inch 198; Adjustable forms width - 76,2 to 450 mm. Maximum forms length - 76,2 to 317,5 mm. Fig. 1 illustrates a representative system configuration including a host system 1 and the printer subsystem 2 which includes a printer control unit 3 and printer electronics 4. Command and data signals are provided by the host system by way of interface 5, and command and control signals are provided from printer control unit 3 to the printer electronics 4 by way of bus 6. Status signals are supplied by printer control unit 3 to host system 1 by way of interface 5. Typically, the host system 1 generates information including commands and data and monitors status. Printer control unit 3 receives the commands and data, decodes the commands, checks for errors and generates status information, controls printing and spacing, and contains printer diagnostics. Printer electronics 4 executes decoded control unit commands, monitors all printer operations, activates print wires, drives motors, senses printer emitters, and controls operator panel lights and switching circuitry. It controls the tractor/platen mechanism, the ribbon drive, the print head (i.e., actuator group) carrier, the operator panel, and the printer sensors. The elements of the system, such as the printer control unit and printer electronics, incorporate one or more microprocessors or microcomputers to analyze commands and data and to control operations. Printer Attachment The printer subsystem may be connected by an interface cable to a controlling device (controller). The printer can be connected to the controlling device itself, or to another printer (or work station unit) with additional cabling. Controlling Device The controlling device to which the printer subsystem 2 is attached may be a host computer system 1, Fig. 2 or a controller at a remote work station, Fig. 3. In either case, all information transfers (exchanges) between the controlling device and the printer control unit are started from the controlling device by a command. Information transfers ordinarily are not initiated by the printer. In some applications, the printer subsystem may be directly connected to a host computer system 1, as in Fig. 2. In such applications, all commands (operational and formatting) are supplied by the computer, along with the data to be printed. Responses from the printer are sent directly to the computer from the printer control unit. In other applications, Fig. 3, the printer subsystem 2 may be connected to a work station controller, which in turn is remotely connected to a host computer system 1 by a communications network - such as Systems Network Architecture/ Synchronous Data Link Control (SNA/SDLC). In such applica tions, information (data) to be printed and printer formatting commands are transferred from the computer system to the work station controller. The work station controller then generates the operational commands and transfers all this information to the printer. Responses from the printer are sent to the work station controller then to the computer system by the communications network. Cable Through Connector The Cable Through Connector feature, Fig. 4, connects multiple printers or other work station units on the same interface cable line to the system or controller. Units with this feature have address-setting switches and an additional cable connector. The customer assigns a unique address to each unit on the cable connector line and sets the address switches at installation time. The feature is not needed on the last unit on the line. The number of units that can be connected to the same line depends on the capability of the controlling device. With this feature, the maximum cable length restriction is from the controlling device to the last unit on the line. Audible Alarm The optional alarm produces a tone that alerts the operator to conditions that require operator attention. Interface Cable The interface cable may be either coaxial or twinaxial. Representative maximum cable lengths from the controller to the last device on the interface are: Coaxial cable - 610 m Twinaxial cable - 1525 m The type of cable selected depends on the requirements of the controlling device to which the printer subsystem is attached. Information Transfer Data Stream All information transferred between the controlling device and the printer subsystem is in the form of a serial "stream" of information bits 7, Fig. 5 Contained in this stream are: Bit synchronization patterns Frame synchronization patterns Data frames The bit and frame synchronization (sync) patterns establish timing control between the controlling device and the printer. The data frame is the unit of information used to transfer all commands, data to be printed, and status information. The data stream can flow in either direction on the interface cable - but only in one direction at a time (halfduplex). The controlling device always initiates the data stream flow for either direction. Only one device on the interface can be communicating with the controlling device at a time. The data stream flows on the interface for each transfer of single or multiple frames of information. The cable carries no signal between information transfers. In a typical information transfer from controller to printer, the information stream may be a mixture of operational commands, formatting commands, and data to be printed. Blocks of up to 256 frames may be included in the information stream for a given transfer. The information stream for any information transfer always begins with the bit-sync and frame-sync patterns, and ends with an end-of-message code in the last frame of the sequence. The end-of-message code causes turnaround on the cable, allowing status information to be transferred in the opposite direction on the cable on the next sequence. Information Frame The basic unit of information transfer is a 16-bit information frame. The information frame is used for transferring all commands, data, and status information between the controlling device and the printer. A Receive mode from controller to printer is illustrated in Fig. 6 and a Transmit mode from printer to controller is illustrated in Fig. 7. The 16 bits of the information frame are assigned the following significance: Bits 0 through 2, the fill bits, always 000, are for timing control. Bit 3, the parity bit, is set to maintain an even bit count (even parity) in each frame. Bits 4, 5, and 6 are the address bits for selecting a specific printer (or other work station unit) attached to the interface. Up to seven units can be addressed by combinations of these bits (000 through 110 are valid addresses). A bit combination of 111 indicates an end-of-message and causes line turnaround. Bits 7 through 14 are for commands, data or status information. Bit 15, always on, is a synchronization bit. Printer Addressing Printer addresses are coded in bits 4, 5, and 6 of the information frame 8, Fig. 8. The address for a single printer on the interface cable is 000. With the Cable Connector feature, addresses can range from 000 through 110. Addresses of printers attached with the Cable Connector feature are set with switches by the customer. A bit combination of 111 is used as an end-of-message indicator in the last frame of a transfer sequence and, therefore, cannot be used as a valid address. The first frame following any signal turnaround on the cable is a command frame containing a valid printer address (000 through 110) for selecting a specific printer on the interface cable. Each successive frame following a command frame is then checked for the end-of-message code (Ill). All response frames from the printer to the controlling device, except the end-of-message frame, contain the address of the selected printer. Printer Responses All information transfers between the controlling device and the printer are initiated from the controlling device by command frames. The printer, however, does transfer information to the controller on request. These transfers are called printer "responses". In general, printer response frames are requested by the controller to determine the readiness (or "status") of a printer for accepting data from the controller. A variety of printer operational and error conditions are reported to the controller by means of printer response frames. ese conditions are described in detail in the section below entitled 11Status and error Information". Printer Control Unit The printer control unit 3 connects the printer to the interface cable from the controlling device, controls the flow of information to and from the controlling device and controls all internal printer functions. When data is received for printing, the printer control unit formats the data into print lines, using formatting commands (control codes) embedded in the data stream. Two printline format buffers are used so one line can be printed while the next line is being formatted. This comprises a "lookahead" function which allows bidirectional printing for maximum throughput. Information Codes All 256 8-bit codes of the Extended Binary Coded Decimal Interchange Code (EBCDIC) are recognized by the printer control unit. In a data stream hexadecimal codes of 00 through 3F represent formatting commands, 40 through FE represent data (FF is always a blank character.) All of these codes may be used to represent characters. Operational Commands Operational commands, listed in Table I below, determine the printer functions to be performed, such as Write Data, Read Status, etc. (also, see Figs. 9 and 11). Fig. 11 illustrates a representative operational command: "Poll." Some operational commands require an additional command or data frame. In these cases, the next frame transmitted must contain that command or data frame. Operational commands are embedded in the data stream wherever required for proper control of tae printer. Operational Command Sequence The diagram in Fig. 10 illustrates a representative sequence of events between a controlling unit and the printer subsystem to effect printing of data. TABLE I OPERATIONAL COMMAND SUMMARY Hex Command Name Code* Function Poll X0 Poll causes a one-frame status response from the printer until a Set Mode command is issued; thereafter, Poll initiates a two-frame status response. Bit 8 set to 1 resets line parity error indication. Bit 9 noti fies the printer to send current status frames. Read Device OC Initiates the transfer of the ID ID (Identifier) frame from the printer to the controlling de vice. Must be followed by an Activate Read command. Read Status 88 Initiates the transfer of one frame of outstanding status from the printer. Must be followed by an Activate Read Command. TABLE I - continued Hex Command Name Code* Function Activate 00 Required to complete Read Read Device ID or Read Status opera tions. This command signals the hardware that data is to start a transfer and is not placed in the command queue. Write lE Causes the printer to store all Data data frames after the Activate Write. Activate Ol Causes printing of data frames Write that follow this command. This command signals the hardware that data is to start a transfer. This is not placed in the com mand queue. Write 05 Resets exception or outstanding Control Data status. Set Mode 13 Must be issued before the printer accepts any other com mand except Poll and Reset. Followed by a data frame that defines the interval between frames. Reset 02 Resets printer to a power-on reset condition. TABLE I - continued Hex Command Name Code* Function Clear 12 Clears all print data buffers. End-of-Queue 62 Marks end of command queue (EOQ) loading. * Bits 7 through 14 of a data frame Formatting Commands Formatting Command Function Formatting commands, shown in Table II below, control forms movement and line length. They are embedded in the information stream that follows the Write Data commande, Fig. 9. Also, See Fig. 12 which illustrates a representative formatting command :"New Line." Some formatting commands require more than one frame. A code in the first frame identifies multiple frame commands. In some cases the code in the second or third frame further defines the total number of frames to be used. The formatting command codes are also referred to as "standard character string" (SCS) codes. SCS is an SNA controlcharacter subset. Command Name Frame Sequence and (Hex Code/Parameter) Abbreviation 1 2 3 4 5 6 Description Null (NUL) 00 No Operation performed. Carriage OD Moves the print Return position to the first position of the current line. New Line 15 Moves the print position to the first position of the next line. Interchange lE Same as New Line. Record Separator (IRS) Line Feed 25 Moves the print (LF) position to the same horizontal position of the next line. Form Feed OC Moves the print (FF) position to the first position of the next page. TABLE II - continued Command Name Frame Sequence and (Hex Code/Parameter) Abbreviation 1 2 3 4 5 6 Description Bell (BEL) 2F Turns off Ready, turns on Attention and the audible alarm, and stops printing. Absoolute 34 CO NN Moves the print Horizontal position to the Position horizontal (AH) position specified in the parameter frame. The para meter frame NN immediately follows the AH command. Absolute 34 C4 NN Moves the print Vertical position specified Position in the parameter (AV) frame. The para meter frame NN immediately fol lows the AV command. Relative 34 C8 NN Moves the print Horizontal position hori Print Position zontally towards (RH) the end of the line from the current print TABLE II - continued Command Name Frame Sequence and (Hex Code/Parameter) Abbreviation 1 2 3 4 5 6 Description position the num ber of columns specified in the parameter frame. The parameter frame NN immedi ately follows the RH command frame. Relative 34 4C NN Moves the print Vertical position verti Print cally towards the Position bottom of the (RV) page from the cur rent print posi tion the number of lines speci fied in the para meter frame. The parameter frame NN immediately follows the RV command frame. Set 2B Cl NN HH Sets the print Horizontal line length to Format (SHF) the value speci fied in the parameter frames. The parameter frames NN and HH TABLE II - continued Command Name Frame Sequence and (Hex Code/Parameter) Abbreviation 1 2 3 4 5 6 Description immediately fol low the Cl com mand frame. Set 2B C2 NN W Sets the page Vertical length to the Format value specified (SVF) in the parameter frames. The parameter frames NN and W immedi ately follow the C2 command frame. Set 2B C8 NN GG UU Sets the unprint Graphic able character Error option and de Action fines the default (SGEA) graphic that is specified in the parameter frames. The parameter frames NN, GG, and UU immediate ly follow the C8 command frame. Transparent 35 NN Permits the codes (TRN) normally used as control charac ters to be used TABLE II - continued Command Name Frame Sequence and (Hex Code/Parameter) Abbreviation 1 2 3 4 5 6 Description as printable characters. The parameter frame NN specifies the number of frames that follows the 35 command frame. Subscript 38 Line feeds 1,41 mm (SBS) to print Not available subscript dot 4ingLe characters. diitactZo n popes deed; Superscript 09 Reverse line (SBS) feeds down 1,41 mm Not available to print dot 4engBe superscript detection characters. paper deed; Set 2B D2 04 29 Pl P2 Sets the charac Character acter density to Distance 10 or 15 characters (SCD) per inch as specified in the Pl and P2 para meter frames. TABLE II - continued Command Name Frame Sequence and (Hex Code/Parameter) Abbreviation 1 2 3 4 5 6 Description Set Baseline 2B D2 04 15 Pl P2 Sets the depth Increment of one line of (SBI) print to 0,176 mm Not available dah single direction pap at 6ead; Set CGCS 2B Dl 03 81 Pl Loads 1 of 16 through graphic charac Local ID acter sets speci (SCL) fied in the Pl CGCS - Coded parameter frame. GJaphec Character Se Absolute 2B D3 04 D2 PI P2 Moves the print Move Base- position forward line (AMB) in the vertical Not available direction from for single the current direction print position paper seed to the new print position speci fied in the Pl and P2 parameter frames. TABLE II - continued Command Name Frame Sequence and (Hex Code/Parameter) Abbreviation 1 2 3 4 5 6 Description Relative 2B D3 04 D4 Pl P2 Moves the print Move Baseline position forward (RMB) or backward in Not avaetabè the vertical for single direction from dexection the current print paper deed; position to the new print posi tion specified in the Pl and P2 parameter frames. Load 2B FE NN MM Data allows cus Alternate tomer designed Characters fonts or charac (LAC) ters to be loaded for printing. Set Line 2B C6 NN Pl Selects vertical Density line density of (SLD) 6 or 8 lines per inch or any distance in multiples of 0,35 mm up to 255. Status and Error Information Poll Response Frames Following a power-on reset (POR), the printer subsystem responds to controller polling with a single status frame, Fig. 13. The printer continues to respond to controller polling with a single status frame until the printer receives a Set Mode command. After receiving a Set Mode command, the printer responds to polling with two status frames, the second of which is shown in Fig. 14. Status information described in frame 1, Fig. 13, is the same in either case. Bits 0, 1, 2 -Fill These bits are always set to 000 and are used for timing control. Bit 3 - Parity. This bit is used to maintain an even bit count (even parity). Bits 4, 5, 6 - Printer address. These bits are used for selecting a specific printer attached to the interface. Up to seven printers can be addressed by the combinations (000 through 110). A bit combination of 111 indicates an end-of-message and causes line turnaround. Bit 7 - Busy. 0 = Not busy when operational command queue is Bit 8 - Line parity. 0 = No line parity error is detected in a received frame. 1 = Line parity error is detected in a received frame. Bit 9 - Unit not available. 0 = Unit available (the Ready light is on). 1 = Unit not available. Bit 10 - Outstanding status. 0 = No outstanding status. 1 = Outstanding status (available by using the Read status command). Bits 11, 12, and 13 indicate a variety of exception status conditions. Until the exception status is reset, only Poll, Set Mode, and Reset commands are processed. The Write Control Data Command (if the exception status is not poweron transition) is also processed. The power-on transition exception status is reset by the Set Mode command. The exception status conditions are reset by the Write Control command (see "Write Control Data"). Bit Bit Bit 11 12 13 Meaning 0 0 0 No exception status exists. 0 0 0 Activate lost - caused by a line parity error following a Write Data, Read Status, or Read Device ID. Bit Bit Bit 11 12 13 Meaning (continued) 0 1 0 Invalid activate command - caused when a Write Activate follows a Read Status or Read Device ID or, a Read Activate following a Write Data. 0 1 1 Reserved. 1 0 0 Invalid command - caused when a command is outside the operational command set or more than 240 micro second interframe interval has been specified. 1 0 1 Input queue or input buffer overrun caused when more than 16 commands and associated data frames or more than 256 data frames have been sent. 1 1 1 Power-on transition-causes only status frame l to be sent in response to a Poll command. Bit 14 - - Current/Previous response level. When bit 14 goes from 0 to 1 or 1 to 0, the using system determines that the response frame is current status. When bit 14 is unchanged from the previous response, the using system determines that the response frame is previous status. Any change in the response frame changes bit 14 from its previous state. Bit 14 is set to 0 after power-on. Bit 15 - Sone . A synchronization bit that is always set to 1. Frame 2 contains information shown in Fig. 14. Bit 0 through 6 - Same as Poll status frame 1. Bit 7 - Invalid SCS (standard character string) control. 0 = No Invalid SCS Control Code is detected. 1 = Invalid SCS Control Code is detected. Reset by a Reset or Clear command. Bit 8 - Invalid SCS (standard character string) parameter. 0 = No Invalid SCS parameter is detected. 1 = Invalid SCS parameter is detected. Reset by a Reset or Clear command. Bit 9 - Receive buffers full. Used by the using system to determine when data can be sent to the printer. 0 = Receive buffers are not full. 1 = Receive buffers are full. Bit 10 - Print complete. The print complete bit is set to 0 when the printer detects an Active Write command. The print complete bit is set to l by Power-on reset, a Clear command, a Reset command, or when all input data is printed. 0 = Printing is in progress. 1 = Printing is completed. Bit 11 - Cancel Request. The Cancel request bit is set to 1 when the operator presses the Cancel key on the Operator Panel. This bit is reset by the next Poll command (with Acknowledge bit set to 1), a Reset or Power-On reset. 0 = No cancel request. 1 = Cancel request. Bit 12 - Not used Bit 13 - Not used. Bit 14 - Graphic check. This bit set to 1 indicates that an undefined character has been detected in the data stream. This bit is reset by the next Poll command (with Acknowledge bit set to 1), a Reset or Power-On reset. 0 = No graphic error is detected. 1 = Graphic error is detected. Bit 15 - Same as Poll status frame 1 Read Status Response Frame One response frame is sent for every Read Status command. The response frame, sent only after the Activate Read command is received, contains a hex code that defines the status condition within the printer. The hex code corresponds to the last two digits of the error code that may be available as a system error message (depending on the using system). The first digits of these hex codes are also automatically displayed on the printer operator panel 26 (Fig. 16) when the error occurs. The defined conditions are: Hex Code Error Condition 11 Printer controller error 12 Cable adapter error 31 Head drive problem 32 Margin emitter not detected 34 Turnaround emitter not detected 35 Print emitter not detected 36 Head busy (cannot be reset) 37 Printer control unit 38 Overcurrent 41 Forms drive problem (undetermined area) 42 Forms busy (cannot be reset) 43 Forms emitter B not detected 44 Forms emitter A not detected 45 Run latch failure (printer control unit) 46 Printer control unit 47 Overcurrent 48 Emitter sequence wrong 80 Ribbon jam 81 Ribbon jam (diagnostic mode) 82 Ribbon problem 83 Head Image Generator error Fig. 15 illustrates various components of the printer all of which are housed in the console 10. Various access panels or covers such as those designated 11, 12, and 13 are provided. Top cover 11 has a window 14 that enables an operator to observe forms movement during operation of the printer and when the cover is closed. Forms (documents) 15 are provided from a stack 16 and can be fed in one embodiment upwardly or downwardly as viewed in Fig. 15 by means of a forms feed assembly 20 which includes one or more sets of forms tractors such as the upper set comprising tractors 90 and 91. A forms guide 28 guides the forms after printing to a takeup stack, not shown but positioned below the printing mechanism and to the rear of the printer console. The printer incorporates a print assembly 30 that is positioned generally in a horizontal relationship with respect to forms 15 at a print station 32. Print assembly 30 is more clearly visible in other views. This is also true of the printer ribbon drive assembly 40 which is located in closer proximity to the front of the printer. Printer control unit 3 and its associated microprocessors are generally located behind the side cover 13. The printer includes an operator panel 26 (shown in greater detail in Fig. 16) that consists of several operator control keys (pushbuttons 51-55 and 60), two indicator lights 56, 57, a power on/off switch 58, and an operator panel display 59. By using various combinations of the keys in conjunction with the shift key 55 the operator can:start or stop printing and view the last line printed, set print density, position the forms up or down one page or one line at a time, move the forms incrementally up or down for fine adjustment, and start or stop the diagnostic tests when selected by a mode switch, to be described. The indicator lights on the operator panel display notify the operator that:the printer is ready to print data from the using system (indicator light 57), the printer requires attention (indicator light 56), the current print density setting (operator panel display 59), errors, if any, have been detected, and the results of the diagnostic tests (indicator panel display 59). A 16-position mode switch 65 is located behind the front door 12 and is shown in greater detail in Fig. 17. The on line position permits printing to be controlled by the using system. All other positions are off-line and do not allow printing to be initiated from the using system. The first two switch positions are used by the operator to select these modes: Online. The normal operating position. With the switch in this position, the printer accepts commands from the using system. The operator panel display 59 indicates any detected error conditions. Buffer Print. An additional on-line position which prints the EBCDIC values (hexadecimal codes) sent from the host and the associated character images. No control characters are interpreted. This feature allows the user to view the data stream sent to the printer. Test. For off-line checkout and problem determination. In test mode, when Start key 53 is pressed, the Atten tion indicator 56 stays on and Ready indicator 57 is turned on until the diagnostic tests that are stored in the printer control unit are finished or the Stop key is pressed. If an error is detected, the printer stops and displays an error code in the operator pannel display 59. The remaining thirteen (13) positions of the mode switch designated "2-9" and "A-E" are used by service personnel to select a variety of diagnostic tests to aid in off-line problem determination and confirmation of service requirements. Overview of printer mechanisms Fig. 18 is an assembly view of the printer including forms feed assembly 20, printer assembly 30, and ribbon drive assembly 40. Ribbon drive assembly 40 includes the two ribbon spools 42 and 43 which alternatively serve as supply and takeup spools. If spool 42 is serving as the supply spool, ribbon 41 will be supplied past posts 125 and 126, through the ribbon shield 46 past posts 127 and 128 and thence to the takeup spool 43. Shield 46, and ribbon 41, are illustrated slightly on the bias relative to horizontal which is their more normal relationship in the printer. Shield 46 has slits 46b and 46c at opposite extremities to permit easy mounting in the printer on pring members 130 and 131 of the ribbon drive assembly. The ribbon drive assembly 40 is also positioned on a slight bias relative to horizontal to accommodate the bias of shield 46 and ribbon 41. In this condition aperture 46a assumes a horizontal relationship with respect to the print wires 33 and forms 15. Thus, in Fig. 18, the rightmost end of shield 46 is somewhat elevated in relation to the leftmost end in order that aperture 46a is maintained in a relatively horizontal position with respect to the print actuators in print mechanism 30. A few of the groups of print wires 33 are indicated at a breakaway section of shield 46. As previously noted, the print wires are reciprocated back and forth laterally in relation to a form, not shown in Fig. 18, in order to effect the printing of characters. The reciprocation is by means of drive mechanisms activated from motor 76. The activating signals for the actuators in print mechanisms 21 are supplied through cabling indicated at 73. Actuator Block, Guide, and Actuators Enlarged views of the actuator block 77, guide 79, print wire actuators 35, lubricating assemblies 134, and various related mechanisms are shown in Figs. 19, 20 and 21. Referring to Fig. 19, this better illustrates the arrangement of apertures 133 in actuator block 77 which can accominodate eight print heads with eight print wire actuators. Apertures 133a are used to mount actuators 35 while apertures 133b allow passage of barrels 136 of actuators 35 through actuator block 77 and guide 79 up to the print line. A typical lubricating assembly 134 comprises a cover 140, felt element 141, wick assembly 142, and housing 143 that contains lubricating oil. Fig. 20 illustrates a portion of face 79a of guide 79 while Fig. 21 illustrates a portion of face 79b of guide 79. Barrels 136 of actuators 35 pass through apertures 145 on face 79a of guide 79 and are retained by bolts such as bolt 146 passing through apertures 147 from the opposite side of guide 79. Individual actuator barrels 136 and print wires 33 project through apertures 148 Figs. 18 and 21. Printing of Characters, Relationships of Print Wires, Character Locations and Emitters Characters that are printed are formed by printing dots on the paper. These dots are printed by wires that are mounted in groups of eight on a carrier bar that moves back and forth adjacent to the print line. Printing is bidirectional with complete lines of print formed right-to-left and leftto-right (see Figs. 22 and 23). A character is formed in a space that is eight dots high by nine dots wide. As shown in Fig. 23, two of the nine horizontal dot columns (1 and 9) are for spacing between characters. Any one wire can print a dot in four of the seven remaining horizontal dot positions (2 through 8). The printer can print 10 characters per inch or 15 characters per inch. Most of the characters printed use the top seven wires in the group to print a character in a format (or matrix) that is seven dots high and seven dots wide. The eighth (bottom) wire is used for certain lower case characters, special characters, and underlining. The number of print wire groups varies according to the printer model, and typically can be 2, 4, 6 or 8 groups. Printing speed increases with each additional wire group. There are 16 character sets stored in the printer control unit. Any of these sets may be specified for use by the using system program. Fig. 24 is a representation of the emitter glass associated with the print mechanism 21 included in a print emitter assembly. Glass 71 is vertically positioned with respect to a sensor assembly and is mechanically attached to print mechanism 30 so that as the print heads, print actuators, end print wires move back and forth left to right and conversely, glass 71 alos moves in the same manner with respect to the sensor assembly to indicate horizontal position of the print wires. Emitter glass 71 sections called "Ramp", "Home", and "Left Margin". These are coded sections, designated Track A, Track B, and Track C. Track B is sometimes referred to as the "Turnaround" track. "Home" is indicated by all three tracks being clear. "Ramp" is when Track A and Track C are clear, but Track B is opaque. "Left Margin" is when only Track C is clear, and Tracks A and B are opaque. Left Margin can be told from Right Margin because Track B is clear on Right Margin whereas Track B is opaque on Left Margin. For convenience, glass 71 is shown in a more normal representation with the left margin areas to the left and the right margin areas to the right. In actuality, the emitter glass 71 is physically located in the machine with the right-hand part in Fig. 24 toward the left and the left-hand part in Fig. 24 toward the right. This is due to the fact that the associated optical sensor is physically located at the rightmost area of the strip when the print mechanism is in home position, and glass 71 actually is moved past the optical sensor assembly from left to right as the print mechanism moves from left to right away from home position. Fig. 25 illustrates the development of emitter pulses from the emitter strip shown in Fig. 24, the signals being termed "real emitters" when actually sensed from Track A. "Option" emitters (sometimes referred to as "false" emitters) are developed electronically in the printer control unit. The emitter tells the electronics when the wires are in a proper position to be fired to print the dots in correct locations. It essentially divides the print line into columnar segments, each one of which is available to the electronics to lay down a print dot. Track A, the basic track which controls the printing of dots has spacings of 0,56 mm. This corresponds to two print columns distance on the emitter in a normal print cycle and for ten characters per inch one option is inserted halfway in between. *Each emitter track actuates one pair of light emitting diode-photo transistor (LEDPTX) sensors within the sensor assembly. Track A provides print initiation pulses, Track B provides signals for turnaround (reversal of print motor 76 direction), and Track C indicates if the print heads are in either left or right margin. To keep track of the print head position, the number of emitters of Track A are counted. The A sensor keeps increasing the count regardless of whether the print assembly moves to the right or left. In order to indicate the true position of the print assembly, provision is made electronically to convert this count so that the count increases when the print assembly moves in one direction and the count decreases when moving in the opposite direction. System and control unit components Fig. 26 is a highly diagrammatic block diagram of the general relationship of various system and control unit components including the two microprocessors 200 and 210 (also designated MPA and MPB), the Head Image Generator 220 and the random access memory 217 and indicates how the information is transferred that is generated by the Head Image Generator to print dots on the paper by actuation of the actuators. Microprocessor 200 handles communications;microprocessor 210 handles the control of the subsystems. Microprocessor 200 sets up in memory 217 the count and the text buffer that is to be printed at a selected addressable location. The information is then passed over to microprocessor 210 or the buffer that is to be used. The count is passed to a signal generator (Head Image Generator 220) and also the address in memory 217 which is the text buffer to be printed. Head Image Generator (HIG) 220, knowing the buffer to be printed, accesses memory 217 and defines the dots for the characters to be printed at each of the successive columns assigned to each print head as the print carrier moves during printing. Signal generator HIG passes the data to the Control microprocessor 210 giving it all the dots to be printed at that particular time. This is represented in Fig. 28 which includes a portion of head 1 and all of head 2. Fig. 28 illustrates printing at ten characters per inch. A string of "H's" is assumed to require printing. The darkened dots of the "H's" represent the wires above them that will actually print that dot. For example, in print head 1, wire 4 prints the fourth dot down in the first column of the leftmost "H". This is the second slice of firing for that particular character with another three wire fires being required for wire 4 to complete the horizontal bar portion of the "H". The other seven wires in print head 1 fire at appropriate times to complete their assigned horizontal rows in that character. At head 2, wire 1 is over an "H"; there is no wire over the next "H";and wire 5 is over the third "H". If printing was at fifteen characters per inch, there would be no wires over two characters between wires 1 and 5 of head 2, rather than just one character as illustrated. The wire layout of "1 5 2 6 3 7 4 8" in Fig. 28 relates to the layout in Fig. 27 where it is shown how an "H" is laid out in relation to the actual wire slices. Printer General Block Diagram Fig. 29 illustrates various printer blocks of interest. A power supply 245 supplies the unit with all the power to drive and to control. The on/off switch 240 controls power supply 245 being on and off. From the power supply the cover interlock switch 242 enables and disables the 48-volt drive which controls much of the printer logic 243. Logic 243, once enabled, looks at operator panel 26 for information as to the operations to be performed. Mode switch 65 tells the logic which type of operation in testing procedures should be run. Print assembly 30 is controlled by the printer logic along with the forms assembly 20. Emitter devices 24 and 70 supply positional information to the printer logic. The printer logic also controls and talks with the interface panel 247 and passes information on the other parts of the printer. The ribbon motors 49 and 50 are controlled in an on/off fashion by printer logic 243 which accepts inputs from the ribbon assembly to determine when the end of ribbon has occurred. Head servo 252 is a control block that insures that the print head is in the proper position at the proper time for the actuators to fire Forms servo 253 is a control block that moves the forms to desired locations. Fans 254-258 are used to control temperature within the machine. As indicated in connection with Fig. 26, printer logic 243 includes two microprocessor adapter blocks 200 and 210. The first one included is the Communications adapter CMA which accepts input and passes it to the second one which is the Control adapter CTA that actually controls the printer. These will be discussed in connection with Figs. 30a and 30b. Microprocessor Control - Printer Subsystem Two microprocessors are provided for the printer subsystem, each having its assigned functions and both can operate concurrently to accomplish the required functions. Figs. 30A and 30B join together as shown in Fig. 31 to illustrate the details of the Printer Control Unit 3 and Electronics 4, Fig. 1. Various abbreviations used herein are listed in Table III below: TABLE III ABO - Address Bus Out CMA - Communications Adapter Card CTA - Control Adapter Card CTL - Control D - Data DI - Data In DBI - Data Bus In DBO - Data Bus Out HIG - Head Image Generator MODE/OP - Mode/Operation ROS - Read Only Storage SAR - Storage Address Register STG - Storage Bus In There are actually seven main blocks comprising the Printer Control Unit representing seven printed circuit cards. The first block is the Communications Interface 201 between the host system and digital printer electronics. That interface communicates with the Communications Adapter (CMA) 202 which is a microprocessor card that takes the host information and compiles it into a form that can be used by the rest of the printer. The CMA includes Communications microprocessor CMM 200. From there, the information is passed on a signal generator (Head Image Generator 220) card for building images for the printer. There is another micropocessor card that is the Control Adapter Card (CTA) 211. The CTA includes Control microprocessor CTM 210. The Control Adapter handles the processed information from the Communications Adapter, controls, all the mechanical elements of the printer, such as the motors, and receives emitter signals indicating positions of the mechanical elements. This Adapter handles communication with the actual hardware through the Control and Sense card 212 and the Head Latch card 213 that stores the data to be outputted to the wire actuators. Within the Communications Interface are two blocks. One is the Interface Control block 203; the other is the Interface Storage block 204. The Interface Control block 203 interprets the information coming from the host system in an analog signal form, processes it into digital form, and generates the necessary timing signals to be able to store this information in the Interface Storage 204. The Interface Storage 204 is a Functional Storage Unit (FSU) random access memory which is sized at one K (1K or 1024 ) bytes. All data and commands from the host system, go into this Interface Storage; it acts as a buffer for the Communications Adapter 202. Within the Communications Adapter card, there are five blocks. There is the Communications Mmicroprocessor 200 (CMM) and its corresponding storage 205 designated "A" which includes both random access memory and read only storage (ROS). There is a Mode/Op Panel and Sense block 206 that can read the panel 26, a Mode Op Panel Output block 207 to output displays to the panel, and Decode Logic 208 for these functions. The Communications Adapter 202 translates the information that the host has sent over through highlevel or hand-shaking type procecedures and translates it into much more simple terms such as characters to be printed or carriage returns, or line feeds - any other mechanical type control that needs to be performed. Its program is stored in the Read Only Storage (ROS) of the CMA "A" storage. There are 6K bytes in this ROS. The CMA also handles Hardware Operator commands involving printing the printer on-line, taking it off-line and displaying any type of status information through the display on the Mode Operator Panel 26. The Communications Storage card 215 has two blocks entitled CMA Storage "B" designated 216 and Head Image Generator (HIG) Storage 217. Storage "B" block 216 contains up to 14K bytes of ROS storage in FSU (Functional Storage Unit) technology for the Communications Adapter microprocessor 200. The random access memory storage 217 has 3K bytes for the Head Image Generator and is where the Communications Microprocessor stores character images to be printed. The character images in this storage are used by the Head Image Generator to generate actual images for the slanted heads. Also, in the block of Random Access Memory are two text buffers and some scratch pad storage. Because of the staggered slant geometry of the print head assembly and the multiple head configuration, a fairly complex Head Image Generator 220 (HIG) is required to convert conventional character dot format to a slanted format. HIG processes the character images as they would normally appear in a "straight-up" format, but slants them for the Head Latch block 213 to supply to the print wire actuators. This is done through hardware routines that are performed in the Head Image Generator 220. There are basically two blocks in the Head Image Generator, one block being the Control block 221 that actually performs the hardware routines to take the unslanted image and slant it. There is also a Data block 222 that is a small storage unit in which the Head Image Generator stores the slanted infor mation currently being worked on. The Control Adapter 211 can then read this storage and output to the wire actuators through Head Latch 213. This is the slanted data. The Control Adapter (CTA) 211 has six blocks within it. The Control Microprocessor (CTM) 210 receives inputs from various sensors, e.g., ribbon reverse/jam, forms jam, head position, linear encoder, forms position encoder, as well as print commands and data from CMM 200 and HIG 220 and generates print wire firing signals and various control signals to control the ribbon drive, print head drive, print wire actuators, and forms drive. The Control Microprocessor (CTM) 210 has a ROS storage 232 that is 12K bytes of FSU ROS to contain its programs or routines. Certain communication registers including Status register 225 and Command register 226 allow the Communications Adapter 202 and the Control Adapter 211 to communicate with one another. Through these registers go commands such as Print commands, Forms commands, Carriage Returns, and the actual decoded messages that the host has sent over. An Input/Output stack 227 is used as a local storage, that is, it is a small random access memory for the Control Adapter to store intermediate data and there is some associated decoding. The Decode block 228 handles the timing relationships for the Communications Adapter and Control Adapter to be able to talk to one another asynchronously. The Control and Sense card 212 handles the information from the Control Adapter card 211 and interfaces with the actual printer electronics to control by way of Decode block 233 and Printer Control block 234 the head motor, the forms motor, and the ribbon motors represented by block 235. Through blocks 236 and 237 it senses the positional state of printer electronics and mechanics such as the print emitters, forms emitters, etc. The Head Latch card 213 is another interface card from the Control Adapter that latches up the wire image data, the slanted data that is received from the Head Image Generator 220, and outputs it at the correct time to the print wire actuators so that the dots get printed in the correct place on the form. A typical print operation is now described. It is assumed that a single print line is provided by the host with a Forms Feed and Carriage Return at the end which is a typical situation. This information comes over in a serial stream from the host as analog signals into the Communications Interface 201 which digitizes the analog signal and stores it in its Interface Storage 204 in the form of characters to be printed. A command informs the Communications Adapter 202 that this is a line to be printed and that it has Line Feed and Carriage Return commands. The Communications Adapter 202 seeing this information appear, will take the characters to be printed out of the Interface Storage 204 and put them into a selected text buffer in CMA Storage "B" on Communications Storage card 215. It then tells the Control Adapter 211 that it has information in a text buffer to be printed. The Control Adapter, after receiving the information initially tells the Head Image Generator 220 (HIG) that there is data in the selected text buffer that needs to be slanted. Head Image Generator 220 then slants this information, while the Control Adapter card 211 starts the printer in motion; that is, i The Control Adapter 211 for each print emitter that it sees, asks the Head Image Generator for a new set of slanted data. This is outputted to the Head Latch card 213 and is repeated until the entire text buffer has been printed, that is, all the information that the host sent over. Once the Communications Adapter 202 has seen that this has taken place, that is, the printing has been done, it passes the Forms command to the Control Adapter 211. Control Adapter 211 decodes this command and gives a command to the Control and Sense card 212 to move forms a certain number of forms emitters. It senses these forms emitters through the Control and Sense card again. This is further illustrated in Fig. 32. A typical operation is assumed to come from the host to the printer controller unit. [Steps (paths) are illustrated by numbers in circles.] Path 1 represents receipt of the data and commands by interface 201. By path 2, the interface prepares it and passes it on to the CMA 202. CMA 202, essentially in two operations, strips off printable characters and by the path labeled 3A transfers the characters to the text buffers in CMA Storage 216. Initially, font information is stored in HIG Storage 217. At the same time essentially by path 3B, the CMA 202 supplies print commands to the CTA 211 to start the operation. Next are two operations 4A and 4B. CTA 211 initiates operation 4A to HIG 220 which simply says there is data in the text buffer at a certain address, begin HIG operations. At the same time, the path 4B is effective to tell the Control and Sense card 212 to start any of a number of possible operations of the printer, such as:to move the heads off the ramp, move the forms as necessary, do not move the forms, move the head to a cerrain absolute position or relative position, etc. Item 5 is a path from HIG 220, a flow from the HIG to the storage blocks 216 and 217 which essentially fetches the data and the font information, that is the hexadecimal representation of the data that is supposed to operate on to start its wire image generation. Path 6A represents verification by CTA 211 of electromechanical printer operations. This involves checking out the emitters, for example, timing out on the print emitters, etc. to determine that the printer is prepared to print and ready to fire reported back by path 6B. Item 7 (two paths, 7A and 7B) represents fetching of data from the HIG 220 which is the head latch image that is transferred to the head latch card 213 and some checking is done on it at that point by the CTM. Item 8 represents CTA 211 signalling the head latch block 213 to fire. This is a pedestal signal to fire the wires. Prior to that point, CTA 211 has to have received a print emitter at step 6B in order to issue the pedestal firing signal. Step 9 represents a feedback signal from the Control and Sense Card 212 and from the head latch card back to CTA 211. CTA 211 will recheck the Control and Sense Card 212 verifying that the operation was performed that was expected to be performed. Step 10 is communications from the CTA 211 to the CMA 202 indicating that the operation that the CMA initiated was accomplished without errors. If there were errors, CMA will be so advised. CMA 202 then compiles status or error information and presents it at Step 11 to the Interface 201 as a poll response to the host. Communications Microprocessor (CMM) Operations The Communications Microprocessor 200 (CMM) Flowchart, Fig. 33, represents its general operation and starts with the Power On Diagnostics being run. At the conclusion of the Power On Diagnostics, the selected language is loaded into the font Memory for processing and printing. A decision is now made as to whether the Mode Switch is in the off-line or on-line position. If it is in the online position, then the interface data is processed, or information coming from the host or going to the host, is processed and prepared. If an off-line operation was indicated, then this process is skipped. In any case, the chart continues to the next block no matter which off-line operation is processed. This block represents communication with the Control Microprocessor 210 (CTM). This allows the CMM to receive any error or information that needs to be passed to the host and it allows the CMM to pass data and commands such as data to be printed, forms, spacing, etc. on to the CTM. Next, the Operator Panel is accessed to determine whether the Start button, Stop button, or other buttons have been depressed for entry information from the Operator Panel. Next, the Process forms or Control data block is checked to determine the movement of forms resulting from commands sent to the CTM. Next is to Process the text buffers which includes SNA commands or the off-line routines. The CMM places them in the proper text buffer to be printed by the CTM and directs the CTM to pick this information up and place it on the paper as dots. All of these operations have a means of communicating with the error processing routine. At the end of the operation, the CMM checks for on-line or off-line status and continues the process again. Control Microprocessor (CTM) Operations Fig. 34 is an overall block diagram of the Control Microprocessor 210 (CTM) operations. The CTM goes through Power on D1agnostit:s upon Power Up and then upon successful completion of that proceeds to. Program Controls. The function of this is to look for and analyze commands from the Communications Microprocessor (CMM) and start or continue forms operation. When a command is determined, if it is a Print Command, CTM starts the print head motor and looks for the first print emitter. Upon finding the first print emitter, CTM goes into the Print block and stays in that area printing the line of data until it reaches Print Complete representing complete printing of the line. Then CTM goes into the margin operation to find the margins or a turnaround emitter. Once the margins or the turnaround emitter are determined, CTM stops the print head, starts the forms and returns to Program Control to look for and analyze further commands, If CTM receives additional commands from the CMM, upon completion of the forms operation, it starts the next print operation. Out of any of these blocks, if an error is detected, CTM exits and goes into an error operation to determine what and where the error is. It notifies the CMM of the error. The CMM, based on the type of error, will either retry the command or stop the operation of the printer and notify the host. Detailed Description of Printer Control Unit - A Detailed Embodiment Figs. 35A-35P represent detailed circuits for a printer control unit useful in the printer subsystem described herein and which is generally based on the block diagrams of the printer control unit shown in Figs. 30A and 30B but which differs in some of the details of implementation. Figs. 35A-35P should be arranged as shown in Fig. 36 (on same sheet of drawings as Fig. 35B). As with the version shown in a general way in Figs. 30A and 30B the printer control unit of Figs. 35A-35P is assumed to be arranged on seven printed circuit cards having the same general headings as previously discussed in connection with Figs. 30A and 30B. Table IV lists the seven circuit card titles and their figure number locations. TABLE IV PRINTER CONTROL UNIT FIGURE NUMBERS ITEM 35A, 35B COMMUNICATIONS INTERFACE 35C, 35D COMMUNICATIONS ADAPTER (CMA) 35Ew 35F CONTROL ADAPTER (CTA) 35G, 35H HEAD LATCH 35I, 35J, 35K HEAD IMAGE GENERATOR (HIG) 35L, 35M, 35N COMMUNICATIONS STORAGE 350, 35P CONTROL s SENSE In addition, for convenience, reference numbers similar to those used in Figs. 30A-30B will be used in the present description with an appropriate suffix to indicate that there are some differences in the circuit components and arrangements between the two embodiments described. The circuit groups are used mainly when the related circuit lines are located on drawings that are located some distance away within the collection of drawings 35A-35P. When circuit data or control lines are located in such a manner that they readily interconnect when the drawings are lined up as shown in Fig. 36, then the circuit group designations are not used since the circuit connections may be readily seen by such arrangement. Abbreviations Used A variety of abbreviations are used in the drawings particularly in Figs. 35A-35P, and these abbreviations are set forth in Table V below: TABLE V Abbreviation Definition ABO Address Bus Out ADDR W ADD Address ADDR Address Bus AHS Address High Storage ALT Alternate ATTN Attention B Buffer (no invert) BB Bit - Byte CH Check CHAR Character CK Clock CLK Clock CMA Communications Adapter CMD Command CMPR Compare COAX Coaxial CPI Characters Per Inch CS Control Strobe CTA Control Adapter CTL or CNTL Control Microprocessor CTM Cycle DB Data Bus DBBM Diagnostic Bit Byte Mark DBI Data Bus In DBO Data Bus Out DBX Data Bit "X" DEC Decode DET Detect DIAG Diagnostic DR Driver ENBL or EN Enable EOF End of Forms TABLE V (continued) FF Flip Flop FMS Forms GTE Gate HI High HIG Head Image Generator HL Head Latch H/W Hardware I/F Interface INC Increment INIT Initialize INV Inverter K 1000 LANG Language LD Load LO Low LTH or LTCH Latch MAR Memory Address Register MDB Memory Data Bus MEM REQ Memory Request MHZ Megahertz MPLX or MUX Multiplex MTR Motor N Inverter/Buffer NO Number O.C. Open Collector P CHECK Parity Check PG Page POR Power On Reset POS Position R2FO Two Times Receive Clock RBD Receive Binary Data RCV Receive RCVD Received RD Read REG Register ROS Read Only Storage RST Reset RV Reverse R/W Read/Write SAR Storage Address Register SEL Select SING Single SPD Speed SS Sense Strobe ST Start STAT Station STG Storage SW Switch SYNC Synchronization SYS System T COMP T Complete TXTB Text Buffer WH Write High WL Write Low WR Write X2FO Two Times Transmit Clock XBD Transmit Binary Data XMIT Transmit X/R Transmit/Receive XRBC Transmit/Receive Bit Clock Circuit Terminology To the extent that they are the same as the block diagram in Figs. 30A-30B, the same reference numerals will be applied to those circuit modules in Figs. 35A-35P. However, a number of additional circuit elements are shown in Figs. 35A-35P not previously discussed before in connection with Figs. 30A and 30B. In contrast with the circuit diagram of Figs. 30A and 30B where individual cables are shown interconnecting the various blocks, Figs. 35A-35P have a single bus structure which accommodates all cabling in the printer control unit shown in those figures. This is simply designated by the term "BUS". The inclusion of the single bus structure in Figs. 35A-35P is done for convenience in presentation of the printer control unit described therein, it being understood that a single bus structure in actual hardware would not necessarily be as desirable as separate cabling or buses as may be required to route the wiring to the different components of the printer subsystem. Also as a convenience, groups of circuit connections for data and/or control signals that are somewhat related have been arranged into circuit groups A-Z in Figs. 35A-35P. Thus, the cabling designated "B", To Operator Panel, in Fig. 35A is routed through the primary bus and is found connected to the logic in/out wrap block in Fig. 35D. Some of the circuit groups may be found on more than one sheet of the drawings. The circuit groups, their definitions, and locations in the figure numbers is indicated in the following Table VI. TABLE VI CIRCUIT INTERCONNECTIONS - FIGS. 35A-35P Circuit Definition Found In Group ¯¯¯¯¯¯¯¯¯ Figure No. A From Mode Switch 35A, 35D B To Operator Panel 35A, 35D C From Operator Panel 35A, 35D D Power On Reset 35A, 35C, 35E 35G, 35I, 35L 350 E Interface Diagnostics 35A, 35N F CMM Storage 35B, 35C, 35N G CMM Write Low 35B, 35E CMM Write High 35I, 35L TABLE VI (continued) Circuit Definition Found In Group ¯¯¯¯¯¯¯¯¯ Figure No. CMM Address High Storage (AHS) CMM Storage Address Register 5SAR= CMM Data Bit X (DBX) H CMM DBO 35B, 35D, 35L I CMM Storage Address 35D, 35L Register (SAR) J 16 MHz Oscillator 35D, 35E, 351 K CMM Data Bus In 35C, 35E (DBI) L CMM Address Bus Out 35D, 35E, 35L (ABO) M CMM Select 35D, 35L 001, 110, 111 STG MD Main Page Disable 35C, 35N N CTM Reset Storage 35E, 35P (RST STG) O CTM Error 35E, 35G P CTM Control Strobe 35E, 35G, 35P Q CTM Address Bus 35E, 35L, 35K OUT (ABO) 0-7 R HIG Head Data 0-7 35E, 35K, 35L S HIG Error 35E, 35K HIG Print Feedback T CTM Data Bus Out 35F, 35H (DBO) 0-7 35K, 35L, 35P U CTM Data Bus In 35F, 35H (DBI+ 0-7 35P V HIG Load Character No. 35f, 35G, 35K HIG Load Control 35L HIG Print Mode Head Latch (HL) Enable W HIG Select 110 351, 35L HIG Select 111 HIG Reset Storage VVLIV// TABLE VI (continued) Circuit Definition Found In Group ¯¯¯¯¯¯¯¯¯ Figure No. X HIG Storage 56I, 56N Y HIG Storage 56I, 56L Address Register (SAR) z Head/Forms 35D, 350 Overcurrent and Reset Data Flow and Communications - Printer Control Unit As mentioned, the printer control unit is divided into two primary sections, one being the control section and one the communications section. In the control section, most of the operations performed are on an Input/Output (I/O) basis. On the other hand, the communications side of the printer control unit, that is, Communications Interface 201a, Communications Adapter 202a, Communications Storage 215a, and the Head Image Generator 220a all perform communications on a memory basis, that is through a memory module. In this regard, Communications Adapter 202a can request information from the Communications Interface 201a, and the Communications Interface thereupon searches through its memory 204a, Fig. 35B, looking for that information and presents it back to the Communications Adapter. The Head Image Generator 220a operates somewhat in the same manner. It can request information from the Communications Storage Random Access Memory (217a and 217b, Fig. 35N) and is timesharing the memory with the Communications Adapter. The Communications Interface 2G1a shares its memory with the Communications Adapter 202a in a more asynchronous manner; that is, the Communications Interface accesses its buffer Random Access Memory 204a at a higher speed than the Communications Adapter accesses it and is not synchronized with it in any way except when the Communications Interface requests some information from this memory. At that moment, the Communications Interface syncs up with the Communications Adapter until the information has been passed. Then, the Communications Interface reverts back to its own speed and its own synchronization to interface with this buffer. With regard to the Head Image Generator 220a, there is a more synchronous type of information transfer. The Head Image Generator is synchronized with every memory cycle that the Communications Adapter takes, whether or not it is to the Head Image or the Wire Image or Text Buffers in Memories 217a, 217b, Fig. 35N. Just prior to the Communications Adapter 202a taking any memory cycle, the Communications Storage 215a detects if the Communications Adapter 202a is going to the Wire Image memory or Text Buffer memory or whether it is not. If the Communications Adapter 202a is not going to these memory locations, it passes control to the Head Image Generator to use if the Head Image Generator needs it, at which time the Head Image Generator will take two memory cycles, then stop and wait to see if the Communications Adapter will require these memories on its next memory cycle. If the Communications Adapter card does require these memories including text buffers and wire images, then the Communications Storage 215a allocates them to the Communications Adapter and locks out the Head Image Generator for one Communications Adapter storage access interval. Printer Control Unit Circuit Blocks and Operation Communications Interface The Communications Interface 201a, Figs. 35A and 35B, consists of six major blocks. The first block is the Discrete Interface 260 between the host input on twinaxial cable 261 and the digital portion of the card. This discrete hardware consists of drivers and receivers of an analog nature that receive and buffer the analog signals coming from the host and that drive the analog signals going back to the host on cable 261. Out of this driver-receiver network the signals that are obtained are phase encoded. These go to the Link Control Module 262. Link Control Module 262 decodes the encoded data, that is, separates out the clock and the data information into separate lines that can now be used by the Coaxial Master Slice block 263. Master Slice block 263 is a digital control block that controls the writing of information to Random Access Memory 204a and that controls the receiving and transmitting of data to and from the host. It obtains all its inputs from Link Control Module 262. It receives input from Random Access Memory 204a and supplies outputs to the Random Access Memory 204a. The Access Control and Timing block 264 exists to interface this Random Access Memory between the Coaxial Master Slice and the Communications Microprocessor on a time-shared basis. Random Access Memory 204a has 1K bytes of storage and is a buffer for information coming over from the host system and is written to and read by the Coaxial Master Slice block 263. It can also be written to and read by the Communications Microprocessor 200a. The Diagnostic Hardware and Sense block 265 controls diagnostic hardware within Coaxial Master Slice 263 that can be used at card tasks and also may be used in online operations within the printer (note connection by way of the Bus and cable group E to Fig. 35N). Communications Adapter The Communications Adapter 202a, Figs. 35C and -35D, has four major blocks within it. Two blocks 200b and 200c comprise the microprocessor 200a. The microprocessor obtains its program from the FSU Read Only storage (ROS) Module 205a, Fig. 35D. There are six K bytes of program storage on this module. Microprocessor 200a fetches its instructions from this ROS storage and communicates with the Communications Interface 201a and the Control Adapter 210a in the Communications Storage card through the Logic Input/Output 208a. This has on it diagnostic hardware so the card is able to self-diagnose and also contains the logic required to output information to the operator's panel and receive information from the printer subsystem. There are several major cables on the Communications Adapter card that cross card boundaries and that are of interest. The Storage Address Register (SAR) lines are memory address lines that originate from the Communications Adapter card. The CMA goes to its own memory 205a and also addresses the Communications Storage card 215a memories and the Communications Interface memory 204 a. The Data Bus Out (DBO), Cable H, is the bus on which all information to memory travels. It originates on the Communications Adapter 202a, travels to block 208a on that card, travels to Memories 217a and 217b on the Communications Storage card 215a, Fig. 35N, and to Memory 204a on the Communications Interface card 201a, Fig. 358. The Communications Storage Cable F, Figs. 35B and 35C, as examples, has many sources, but just one control source, the Communications Adapter card. This is the output of all storage. The output of the Communications Storage card, Fig. 35N, drives this cable. Also the output of the Communications Interface Memory 204a drives this cable. The Address Bus Out (ABO) cable L, Fig. 35D, from the Communications Adapter card supplies input/ output addresses to Communications storage 215a and to Control Adapter 211a. Also emanating from the Communications Adapter by way of cable B are various control type signals that go to the operator panel such signals as turning the Attention light on and turning the Ready light on, latching the display, blanking the display, turning the alarm on. There are also inputs from the operator panel by way of cable C so that the Communications Adapter card can tell when an operator panel button has been pushed. It also can sense by way of cable A the Mode switch for various diagnostic routines that are to be run on the printer. There are also some general control type signals;that is, Select Storage, Control Storage, Write High and Low Storage, Reset Storage, Data Bit X and Address High Storage (AHS) signals that emanate from the Communications Adapter by way of cable G that aid in the control of the memory read and write operations. These signals go to Communications Interface 201a, Communications Storage 215a and also to the Head Image Generator 220a. The Data Bus In (DBI) cable K has many sources, but only one control and that is the Communications Adapter 202a. This is the input line for I/O devices to pass information to the Communications Adapter. It is driven by the Control Adapter 211a, Fig. 35E, and various other devices on the Communications Adapter itself. Control Adapter The Control Adapter 211a, Figs. 35E and 35F, includes a microprocessor 210a comprising blocks 210b and 210c. It has 12K bytes of FSU Read Only Storage (ROS) modules 232a232c that are dedicated to program and data that do not change. Within the card there exists communications registers 226a, 226b, 225a, 225b, and 225c that allow the Communications Adapter 202a, Figs. 35C and 35D, to talk to the Control Adapter 211a or to pass on information as to commands, such as print commands and forms commands. The status registers for the Control Adapter enable it to store information concerning printer status - if there has been an error out in the printer, mechanical or an electrical error, or at what stage a command may be in. Controlling all of this are two address decode blocks 228a and 228b. Block 228a generates the signals to enable the use of the communications registers and allows the Control Adapter to use a small scratch pad memory 227a. Memory 227a has 64 locations by 9 bits wide (that includes parity checking). Block 228a enables the Control Adapter to input head data from the Head Image Generator (HIG) and to read the Head Image Generator status (225c) as to whether or not there has occurred a Head Image Generator error, which is a parity error. This may occur while the Head Image Generator is reading from the Communications Storage card 215a, Figs. 35L-35N, or in what is called a "print mode". This allows printing of every dot, whereas the Head Image Generator normally only prints every other dot. In summary, Decode block 228a controls the Communication Adapter's access to these communication registers. The Command Register 226a and Command Data Register 226b are the two registers through which commands pass from the Communications Adapter to the Control Adapter. The Status Register 225a and Status Data Register 225b pass the error codes or status information from the Control Adapter to the Communications Adapter. These registers have hand-shaking logic so that each processor can asynchronously talk or pass information from one to the other. There are many cables originating and returning to Control Adapter 211a, Figs. 35E and 35F. There are Storage Address lines that are not used by any other card, but are for diagnostic purposes. These include Storage Address lines (See Fig. 35F, for example) going to the FSU ROS 232a-232c on the Control Adapter. Also, it is the Control Adapter Data Bus Out (DBO) cable T that contains the information going to output devices such as the Control and Sense card (Fig. 35P), Head Latch card (Fig. 35H), and the Head Image Generator (Fig. 35K). This cable is also used by devices on the Control Adapter card itself for purposes such as accessing the Communications Registers. The Control Adapter Data Bus In (DBI), cable U, is a cable on which information is given to the Control Adapter by various cards such as the Control and Sense card (Fig. 35P) and the Head Latch Card (Fig. 35H). Also, devices on the Control Adapter card use it. The Control Adapter Address Bus Out (ABO), cable Q, carries the device address which the Control Adapter is presently working with. Also present on the Control Adapter Card are various control signals on cable V that are routed to devices such as the Head Image Generator to tell the Head Image Generator which character it should start looking for in the Text Buffer or for loading control lines into the Head Image Generator for the ten or fifteen characters per inch or the head direction. Other signals going to the Head Latch card enable it to perform operations at the specific times it is supposed to. The CMM Select Storage, cable G, is a gating signal that is specifically used after the Control Adapter has received a Hardware Reset on cable D from the Communications Adapter and after activation of the Address Decode 228b by signals on cable L. The signal releases the Hardware Reset to the Control Adapter thus allowing it to start executing instructions at Address 0. Control Strobe coming from the Communications Adapter, cable G, is a gating signal that controls when data is written into the Command Register 226a and Command Data Register 226b and also controls which register is chosen depending upon the state of the Address Bus Out, cable L. Head Latch The function of Head Latch 213a, Figs. 35G and 35H, is to interface between the Control Adapter 211a and the Actuator Driver cards. It contains three modules 266a-266c that contain registers in the form of latches. Control Adapter 211a receives the head data information from the Head Image Generator 220a, Figs. 35I-35K, and passes it directly to the Head Latch card 213a into the individual latches by cable 267. The Address Bus Out, cable Q, coming into the Head Latch card, Fig. 35G, comes from the Control Adapter card. This is the address information to control which head is getting which head register within the head latch modules, Fig. 35H, which are provided information off of the Data Bus Out, cable T, coming from the Control Adapter also. There can be up to eight heads;so the procedure starts with head 1. Head 1 address is supplied to the head latch decode block 268 and head 1 wire data is provided on the Data Bus Out cable T. Data Bus Out Bit 0 is the information for wire 1; Data Bus Out Bit 1 is the information for wire 2 within the head selected on the Address Bus cable Q. A gating pulse called Control Strobe coming from the Control Adapter, cable P, tells the Head Latch modules when to latch the data information. Outputs go directly to the Actuator Driver cards and on command from Control Adapter 211a, the Head Latch card decodes the command by way of Decode block 268 to fire the actuators or not fire them so that the dots are printed in the proper character positions. There is, in addition, a Pedestal Drive signal on line 285 that is used to start all actuators at the same time. For diagnostics, there is a feedback by way of cable U from the output of all of these latches controlled by blocks 269 and 270 so that all latches can be reset. This one feedback will tell if any latches are still on. From there, one latch is turned on at a time in this feedback check to be sure that one latch does come on. Head Image Generator The signal general or Head Image Generator 220a, Figs. 35F35K, has many subblocks within it. Its major function is to take unslanted character information and slant it and distribute it across all heads to be able to print it in the slanted head and image format. It consists of a master HIG cycle counter 271, Fig. 35I, and it also has some internal registers and counters that keep control of which character it is dealing with and at what time and at what location in the printline it is generating the information for. HIG 220a accesses the Communications Memories (217a and 217b) twice for each single memory cycle that the Communications Adapter 202a will take. Thus, storage access is interleaved with the Communications Adapter. The HIG can only access this memory when the Communications Adapter is not going to access it. It makes these decisions through logic on the Communications Interface, and the timing is controlled by the HIG cycle counter. Basically, the HIG pulls out information from the text buffer in Memories 217a or 217b first to find out what character it needs to look up the information, and then it will obtain information from the wire images in 217a or 217b. It takes this information, selects the one wire, or one bit worth of information, that it needs to load for a particular wire within a particular head and stores this in a small scratch pad Memory 272, Fig. 35K. Memory 272 is of information that is necessary for the Head Image Generator is the number of heads or actually the character spacing between heads for each printer configuration. These are Head Spacing jumpers that are on the card that are prewired. They are in the "X" control line to block 283, Fig. 35J. Once these jumpers have been selected, then the Head Image Generator will always build character information, that is, slanted information, for the pre-wired number of heads and the particular distance between the heads. The HIG Head Data, cable R, carries slanted wire information coming from the Head Image Generator to the Control Adapter card. The HIG cable S contains two lines coming from the Head Image Generator which are the HIG Error and HIG Print Feedback. Communications Storage The Communications Storage 215a, Figs. 35L-35N, mainly consists of program storage in Read Only Storage (ROS) modules (216a-216d) and some Random Access Memory (217a, 217b) for scratch pad type information and control signals interfacing the Communications Adapter 202a with the Head Image Generator 220a. The layout of these modules is shown in Fig. 37. Modules 216a-216d have 14K bytes of storage. Memories 217a and 217b have 3K bytes of storage. The memory is paged and page select logic 275, Fig. 35M, can select any unit of 2K bytes out of the 14K bytes to be used at any one time, that is, not all of memory is available constantly. The way the memory pages are selected is on an Address Bus Out (ABO) type configuration; that is, the first page of ROS has a particular address value assigned to it and when that address is present from the Communications Adapter card and the Communications Adapter card Control Strobe becomes active, it will select the particular page that is assigned to that address number. The Communications Adapter 202a keeps track of which page it is in, and advises when another page of memory is needed. The highest 2K bytes in ROS 216d store all font images that are available for use by the printer. The Communications Adapter (CMA) HIG Control block 276, Fig. 35M, allows the HIG to access the wire image memories 217a and 217b that contain the unslanted character information and also the text buffers which have the characters to be printed. This is done by Select block 284, Fig. 35M, which selects the HIG storage address lines in this case and which otherwise selects the Communications Adapter Storage Address lines. It allows the HIG to select Memories 217a, 217b as needed without interfering with the Communications Adapter. The Communications Adapter can write or read from these memories at any time it is necessary, and the HIG is interleaved within these accesses with the Communications Adapter. Interface Diagnostic block 277 allows the Communications Adapter to run diagnostics on-line or off-line, by way of cable E, Figs. 35N and 35A, any mode that it wishes, referring against the Communications Interface diagnostics, block 265, to determine if there are any problems. storage, cable X, carries data going to the Head Image Generator. This is the output from the wire image and text buffer memories 217a and 217b transferred to the Head Image Generator when the Head Image Generator requests information for its wire image operation. Input from the Head Image Generator to the Communications Storage card is by way of the HIG SAR cable Y, Figs. 35L and 35M, which are the Address Lines for Memory when HIG has access, and the HIG Select Storage lines, cable W, which informs the Communications Storage which of the two memories 217a or 217b the Head Image Generator needs to access. Control and Sense The major function of Control and Sense 212a, Figs. 350 and 35P, is to interface between the Control Adapter 211a and printer electronics listed in Fig. 350. It performs control and sense functions in that it can read status information from the printer, from the power supply, from the mechanics (such as the covers) and also electrical information (such as linear emitters and forms emitters and busy signals or ribbon error). Such signals are fed through the Control and Sense card back to the Control Adapter card through the Multiplexer 233a. Control and Sense also handles command information from the Control Adapter going out to the electromechanical parts of the printer. These include commands telling the head to move, at what direction and what speed; telling the forms to move, at what direction and what speed; and also telling the ribbon to run or to reset an error condition. Within Control and Sense there are two interval timers 280 and 281. Timer 280 steps and counts on a three microsecond clock speed, for example, that is, at three microsecond intervals. It can be loaded from the Control Adapter, and it can be read by the Control Adapter. This is to aid in the Control Adapter's realtime functions, such as error detection of emitters (are they too soon or too late or are they just at the right time). It also aids in scheduling functions before it has to perform another function. The second counter 281 is a slower counter. It steps and counts at a millisecond rate, for example. It is for other functions such as timing the head off of the ramp. Signals emanating from the Control and Sense card, Figs. 350 and 35P, go to two different cards. For the Head and Forms Drive card there exist signals to tell the electronics to turn the head on, the character per inch speed to run the head, in which direction, or if it is going on to the ramp, any information as far as forms to run, whether forms should be in high speed and in which direction. As to the ribbon control card, there exist basically just two signals. One advises the ribbon to run, the other to reset an error if the ribbon card reported one. Signals coming in and terminating at the Control and Sense card, Fig. 350 come from various sources such as the Frame Hardware and include Tractor Open or Cover Open. The emitter card presents signals from the Head location emitters. From the Head Forms Drive card comes feedback information on the head drive phases advising that the head is busy, Head Busy. Forms Busy advises that forms are in movement and Forms and Head Overcurrent occurs if mechanical binding or some failure has occurred. The overcurrent status is reported back to the Control Adapter. From the Forms Amplifier card are presented three signals to forms emitters and then there is one End of Forms (EOF) emitter which advises that the printer needs more paper. From the Ribbon Control card is reported Ribbon Error and/or Ribbon Busy if the ribbon is currently running. On the Control and Sense card, the Data Bus Out contains individual bits of information that are latched up and that go out to the electronics. As an example, for a particular Address Bus Out (ABO) address on cable Q indicating Print Motor 234a the corresponding data on cable T is entered in Buffer 290 to indicate head run information, character density information, head direction, or head ramp. The Control Logic 292 recognizes the occurrence of a Control Strobe Signal, cable P and controls the Print Motor block 234a to latch the information when it is all present. The same applies to the Forms Motor block 234b which has a different ABO address. The Control Logic operates in a similar way for blocks 234b and 234c. Information coming back from the electronics cards is grouped according to an address on the ABO lines again. The Control Adapter presents a particular address on cable Q. This gates the information from either the Emitter card or the Head Forms Drive card or the Forms Amplifier card through Multiplexer 233a whichever device is specifically selected by the address on the Address Bus Out lines. This information is transferred through the Isolation Buffer 293 to the Control Adapter Data Bus In cable U so that the Control Adapter can read the status. The Address Bus Out lines, in this case, are not gated by any special signal, but become effective as aoon as they are activated. Figure 37 shows the layout of the Read Only storage (ROS) and Random Access Memory locations in the Communications Adapter. On the left part addresses are shown as they would apply in the machine. These are four-digit hexadecimal (Base 16) addresses. The microprocessor uses the three low order digits. The first addresses are 0000 to 0800 which would indicate a 2K or 2048-byte segment of memory. This is executable code containing the main program entry point. From 0800 to 1000, there are multiple segments of code by the same address called "overlays". Each overlay is accessed by an OUT command with a number associated with it. There are five separate overlays that can be accessed within the addresses 0800 to 1000, the first overlay being the main overlay of 80;the second one, overlay 81;the third one, 82; the fourth one, 83; and the fifth one, 84. Only one of these overlays may be accessed at a specific time until another OUT command selects another overlay. The addresses 1000 to 1800 are basically still addresses 000 to 800, but serve as data memory versus executable memory. This is where the 2K (2048) bytes of wire image ROS are placed. This is the compressed images used for printing and is where all 16 fonts, or representative images, are stored in the compressed mode to be uncompressed later into Random Access Memory. From 1800 to 1BFF is where the Interface Random Access Memory Buffers are located, Buffer 1 being at 1800, Buffer 2 at 1900. Each buffer is 256 bytes long. No memory is located in locations 1C00 to 3000. A select byte called the X-byte, if off, will select locations 0000 to 2000, and if on, will select locations 2000 to 4000. There are data bytes and instruction bytes in the machine, with the X-byte affecting both data and instructions. With this capability, the Interface Buffer is selected with the X-byte off;the Text Buffer is selected with the X-byte on. By internal wiring, any access to any memory in locations 2000 to 3000 will access locations 0000 to 1000. This prevents having to duplicate code when the X-byte changes. Otherwise, it would be necessary to have another Read Only Storage with exactly the same code in both places. By wiring one ROS as if it were in both places, the microprocessor executes this code independently of the X-byte. Starting at 3000, there are 3K (3072) bytes of Random Access Memory in which the wire images are built from the 2K bytes of wire image ROS located at 1000. The addresses from 3000 to 38FF are the addresses used for all wire images. In effect, the subsystem is using three digits, which would be 000 to 8FF in this wire image random access memory. All images are stored as 9 slices. By using the first of the three digits to indicate the slice, the next two digits represent the EBCDIC or Extended Binary Coded Decimal Interchange Code value of the characters as sent over by the host or other source. For example, if the first slice of the letter "C" is required, which is an EBCDIC C3, then the subsystem looks in location 0C3 for the first slice of the image, 1C3 for the second slice of the image, etc. for the letter "C". From 3B00 to 3FFF, no memory is used. This is basically the layout of memory, both Random Access and Read Only Memory for the Communications microprocessor. Detailled Operation of Head Image Generator The Head Image Generator functions to generate wire images at high speeds for the printer previously described having the slanted serrated wire arrangement. A printer of this nature typically will have anywhere from two to eight print heads, each with a plurality of print wires, such as eight in number. Reference is again made to Figure 26 which depicts generally the relationship of the Head Image Generator 220 with respect to the two microprocessors 200 and 210 as well as a Random Access Memory 217. Memory 217 in a representative system is 3K bytes in size. The Head Image Generator 220 interface with the two microprocessors and receives all its control data for initializing and loading the necessary information in order to start the cycles to create unique wire images for the slanted print wire head configuration. In order to grasp the nature of the Head Image Generator (HIG) function, it is important to understand the transition from the traditional concept of matrix printing to the slanted group configuration. Conventionally, the print head is moved one step at a time horizontally across the character matrix with the option of firing all wires within each vertical slice of that character4s image. Therefore, in order to print the character H (Fig. 27), the head carrier sweeps along the print line and leaves 7 dots on slices 2 and 8 and 1 dot on slices 4 and 6. Other characters such as those in Fig. 23 are handled in a similar fashion. To describe the same character with the slanted group, there is a much wider sweep accross the character. Instead of having all the wires within each character slice, each wire is two characters apart, as illustrated in Fig. 28. Therefore, the printer fires only one wire at a time within any given character. To implement this function and considering Figs. 35A-35P, but especially considering Figs.35I-35K, the Head Image Generator goes through two storage access cycles to generate each individual dot or option. In order to keep track of the different characters on a given line, wire matrix positions and number of groups, the Head Image Generator uses a diversity of counters. The final slanted wire image data corresponding to one machine wire fire is stored in the small memory 217a and 217b, Fig. 35N, and finally addressed by Control microprocessor 210a, Fig. 35E, to later command the firing of the wires. HIG Initialization First, the Communications Microprocessor 200a loads the information into text buffers contained within the 3K memory area, Figs. 35N and 36. Control Microprocessor 210a has the task of loading the Head Image Generator with two bytes of information provided on the CTM Data Bus Out cable group T, Figs. 35F, 35J and 35K. The first byte goes to register 291, Fig. 35K, and contains information as to character density, head direction, and the number of groups found in that machine. The second byte loads the Head Image Generator with the rightmost character to be printed, which always corresponds to wire 8 of the rightmost group (the Head Image Generator works from right to left). The loading of these characters is controlled by load control and load character signals in the cable group V, Figs. 35F, 35K and 35J. A signal on the Head Image Generator Load Control line, cable group V, Fig. 35K, also sets the Run HIG Latch 294 and in turn through And circuit 295 in Fig. 35J sets HIG Cycle Flip Flop 296 which by way of the NAND circuit 297 and line 298 resets the HIG cycle counter 271, Fig. 35I, in readiness for a complete HIG operating cycle. After these two bytes are loaded, the HIG waits for the Communications Microprocessor 200a to allow it to start the memory cycles under control of Cycle counter 271, Fig. 35I and CMA"HIG Control 276, Fig. 35M. The operating cycles of the Head Image Generator and the cycle counter are as follows: OPERATING CYCLES HIG CYCLE COUNTER Cycle Action 1 or A Both of these pulses turn "on" Random Access Memory Reset and Select to initiate the HIG memory cycles. 3 or D Both pulses turn off Random Acess Memory Reset. 6 or 10 Pulses turn off Random Access Memory Select. 7 or 11 Pulses gate valid data to buffer to generate memory addressing. 8 Pulse sets the HIG to start second memory cycle. 9 Pulse gates wire image address to bus. 12 Pulse stores the masked bit in the Hold Register and decrements wire counter by one. 13 This pulse gates Text Address to bus by setting the HIG back to Memory cycle 1 and decrements character counter by 2, for 10 CPI and 3 for 15 CPI. 14 Pulse gates hold register to buffer or branch to start (0). 15 Pulse decrements group counter by "1" and resets Hold Register. uuL r o77 OPERATING CYCLES -continued16 Pulse loads "8" in wire counter, decrements character counter by X (depending on group spacing and character density). 17 Assuming group counter equals zero, the pulse increments wire position counter if groups are moving to the right and decrements the counter if movement is to the right. Also, resets the rest of the logic. Memory Cycles The Head Image Generator cycles memories 217a, 217b using an oscillator pulse, cable J, Fig. 35I, and control lines from the Communications Microprocessor 200a, Fig. 35C, and decides whether or not a particular wire is fired for a given print option. In a first cycle, it fetches the EBCDIC value of the character in which the wire is positioned. This address is created from the character number on the print line. In the second cycle, the Head Image Generator finds the corresponding wire image slice for that character. A vertical slice now has only one possible wire. Using a masking technique, one of the eight possible wires is selected and stored in the Hold Register 282, Fig. 35K, and transferred subsequently to the small stack 272, Fig. 35K. The masking technique involves the decode portion of the wire counter and decode block 287, Fig. 35I, which supplies outputs on cable 249 to activate one of eight AND circuits in block 250 which in turn controls entry of the data representing each of eight wires in sequence and only one at a time into the Hold Register 282. The memory access cycles repeat until all wires in all of the groups are loaded in stack 272, Fig. 35k. Some clock pulses during these cycles are used for loading, incrementing, setting or resetting the logic in Figs. 35I-35K which constitutes the Head Image Generator. HIG Counters From Fig. 28 it can be seen that to describe any of the print wires in the print head, such as print head 2, four pieces of information are needed. Referring to Figs. 35I and 35J, the Head Image Generator needs to know which group it is working with, Head or group counter 286; which wire within the group, wire counter portion of wire counter and decode block 287, Fig. 35I; to which character that wire is pointing to on the print line, character counter 288, Fig. 35I; and finally in which slice of that character is the wire positioned, wire position counter 289, Fig. 35J. All counters, except the wire position counter, are loaded by Control Microprocessor 210a for every machine print Option. The Head (group) counter 286 is loaded with the total number of print head groups and decremented by one after the wire counter decrements, from wire 8 down to wire 1 and gets ready to start on wire 8 of the adjacent print head (group). At the same time that the wire counter is decremented, the character counter is also decremented. As illustrated in Fig. 28, the distance between the wires is two characters, so every time the Head Image Generator moves from one wire to the newt wire, the character counter is decremented by two. Also from Fig. 28, the space between wire 8 of one print head (group) and wire 1 of its adjacent group is four characters, so the character counter must be decremented by four between groups. Both decrements to the character counter are dependent on character density and group spacing. These are hardware programmable by ise of the Head Spacing Jumper and block 283, Fig. 35J, and output 16 of the HIG cycle counter 271 as well as output 13 which controls decrementing of two (2) or three (3) characters and all other selected combinations of group spacings for the printer, depending on how many print heads it has. Decrementing the counters in the manner described enables the Head Image Generator in stack 272, Fig. 35K, to obtain the information from wire to wire and from group to group until all wires are optioned, masked and stored for one machine print option. Wire Fire Mapping Diagnostics Mode switch 65, Fig. 17, is positioned in an appropriate test location to initiate the wire fire mapping diagnostic tests. During servicing of the printer subsystem, many times it is desirable to know which print wires are firing and which ones are misfiring. A quick printout is provided for this purpose. The operation is described in connection with Figs. 38 and 39. In Fig. 38, the operation starts by skipping to a new page in memory and then asks the question, "Have any of the character images been modified?". If the answer is "Yes", then the character font is reloaded; if "No", the operation continues down and blanks the next text buffer. In that text buffer a character that will fire only the wire under test is stored in that buffer; that is, one of the wires 1 through 8 for a particular print head. After the text buffer is loaded, the identifiers as to wire and head are stored on top of the buffer. As an example, an "XY" is stored where "X" indicates the head number and "Y" indicates the wire number. Thus, the start of this information indicates head and wire for printing purposes. The text buffer, as stored, is printed twice. A representative printout is shown in Fig. 39 for a printer unit having four print head groups of eight print wires each. The question is now asked, "Was wire 8 printed?!. If the answer is "No", the operation goes back, increments to the next wire, stores the image for that particular wire and continues as previously. If the answer is "Yes". the operation has completed the mapping of wire fire test as printed by the printer and returns to the offline operation. The mapping printout that is received from the printer, Fig. 39, indicates the number of heads that the particular printer under test is presently using. Starting on the left, there is, for example, a one-one (11), followed by a two-one (21) and continuing accross the page until the last head and wire (41) is indicated. If it is an eight-headed machine, the last will be an eight-one (81). Between these numbers appears a dashed line which is printed only by that wire under test. The first line, starting one-one (11), would have a short distance of dashes indicating that wire 1, head 1 is firing. If the dashes are missing that indicates that there is a problem with head 1, wire 1. The printout continues down the page from head 1, wire 1 to head 1, wire 2 to head 1, wire 3 and so one until it reaches head 1, wire 8. This goes across the page in a matrix type form that shows all wires and all heads at a glance. In the exemplary printout of the mapping of the wire fire test in Fig. 39, head 2, wire 8 is not firing. If head 2, wires 5, 6 and 7 did not fire then the following results would be noticed. The lower half of the following character images would be missing (27), (24), (28), and (31) as wires 5, 6 and 7 print these. Character images (25), (22), (26), (23), (35), (32), (36) and (33) would have portions missing to a lesser degree since wires 5, 6 and 7 help print those. The number in each line merely indicates the start of that particular wire and that particular head, and because the wires themselves are physically offset, some of the numbers are printed by one head and the rest of the numbers are printed by another head, While a preferred embodiment of the invention has been illustrated and described, it is to be understood that there is no intention to limit the invention to the precise constructions herein disclosed and the right is reserved to all changes and modifications coming within the scope of the invention as defined in the appended claims. APPENDIX Operation Codes A number of operation codes are utilized by the microprocessors. These are listed below. ALU OP CODES -- MODE VALUE - REG TO REG 0 DAR TO DAR 1 REG TO DAR 2 DAR TO REG 3 MSK TO REG 4 MSK TO DAR 5 Function OP Codes Add A ¯0 ¯ Add Carry AC 1 Move M 2 Clear (0) CLR 2 Subtract/Borrow SB 3 Subtract S 4 Compare C 5 Subtract Summary SS 6 Compare Summary CS 7 And N 8 Set Bit Off SBF 8 Test T 9 And Summary NS ¯A ¯ Test Summary TS ¯B ¯ Or O ¯C ¯ Set Bit On SBN ¯C ¯ Shift Right SR ¯D ¯ Exclusive Or X ¯E ¯ Shift Right Circular SRC F ¯ Conditional Branches Branch Not Carry, Branch High BNC,BH C ODD Branch Carry, Branch Less Than Or Equal BC,BLE D ¯ EVEN Branch Not Zero, Branch Not Equal, Branch True BNZ,BNE,BT E ¯ ODD Branch Zero, Branch Equal, Branch False BZ,BE,BF F ¯ EVEN Unconditional Branches Branch and Wait BAW C EVEN Branch B D ¯ ODD Branch and Link BAL E EVEN Branch Via Link RTN F001 Return and Link RAL F201 Branch Via DAR BVD F301 Select Data Address Registers (DAR's) and Storage (STG) Select Memory Data Low SDL FC0l Select Memory Data High SDH FEO1 Select Memory Inst Low SIL F481 Select Memory Inst High SIH F489 Select Data Bit X Off SXF F441 Select Data Bit X On SXN F445 Select Main DARS SMD F5Ol Select Aux DARS SAD F701 Input/Output, Load/Store Ops Input From Device IN 68 Sense Device SNS- 69 Output To Device OUT 78 Direct Input and Output DIO 7A Load Registers LDR 89XY Load Registers and DAR+1 LDRP 8BXY Load DAR LDD 84XY Load DAR and DAR+1 LDDP 86XY Load Memory Indexed LDI 8AO Memory to I/O Device MIO 8C Memory to I/O Device and DAR+1 MIOP 8E Load Link Register LDL 8000 E Load Link Register and DAR+1 LDLP 8200 E Load Absolute Address LDA 9 Store Registers ST A9XY Store Registers and DAR+1 STRP ABXY Store DAR STD A4XY Store DAR and DAR+1 STDP A6XY I/O Data To Memory IOM AC I/O Data To Memory and DAR+1 IOMP AE Store Memory Indexed STI AAO Store Link High Order (Even Byte) SLH A000 Store Link High Order and DAR+1 SLHP A200 Store Link Low Order (Odd Byte) SLL A100 Store Link Low Order and DAR+1 SLLP A300 Store In Absolute Address STA B Microprocessor Registers Each of the microprocessors 200 and 210 has a number of internal registers that are used for various purposes such as work registers. The register layout for the Control microprocessor 210 is shown below EMI80.1 <tb> <SEP> RO <SEP> Rt <SEP> R2 <SEP> R3 <SEP> R4 <SEP> R5 <SEP> R6 <tb> <SEP> PERT <SEP> PF <SEP> FLY <SEP> 1 <tb> 8 <SEP> 8 <tb> 4 <SEP> 4 <tb> 2 <SEP> 2' <tb> I <SEP> t <tb> <SEP> R8 <SEP> R9 <SEP> RtO <SEP> Ril <SEP> R12 <SEP> R13 <SEP> R14 <SEP> R15 <tb> <SEP> FLC2 <SEP> WIPOS <SEP> FELT <SEP> PRERR <SEP> CMDFL <SEP> ENACT1 <SEP> ENCT2 <SEP> ENCT3 <tb> 8 <SEP> 8 <tb> 4 <SEP> 4 <tb> 2 <SEP> 2 <tb> <SEP> D3 <SEP> D4 <SEP> 04 <SEP> D5 <SEP> 04 <SEP> 05 <SEP> D6 <SEP> DI <tb> <SEP> DO, <SEP> Dl <SEP> '02 <SEP> RMi <SEP> RM2 <SEP> RM3 <SEP> EOFI <SEP> FMCTI <tb> S <SEP> I <SEP> S <tb> 4 <SEP> 4 <tb> 1. <tb> D8 <SEP> 'DII' <SEP> 014 <tb> <SEP> D8 <SEP> D9 <SEP> DID <SEP> Oll <SEP> D12 <SEP> 013 <SEP> D14 <SEP> D1S <SEP> D15 <tb> <SEP> fGT2 <SEP> FACT3 <SEP> FACT4 <SEP> ESTAT <SEP> FLECT <SEP> ERECT <SEP> PT1 <tb> S <SEP> 8 <tb> 4 <SEP> 4 <tb> 1 <SEP> 2 <tb> As a convenience, the register assignments are listed below. Communications Microprocessor Registers WORKO EQU RO Work Register WORK1 EQU R1 Work Register WORK2 EQU R2 Work Register WORK3 EQU R3 Work Register WORK4 EQU R4 Work Register WORKS EQU R5 Work Register WORK6 EQU R6 Work Register WORK7 EQU R7 Work Register WORK8 EQU R8 Work Register WORK9 EQU R9 Work Register WORKA EQU R10 Buffer Indicator Register WORKB EQU Rll Work Register WORKC EQU R12 ,Work Register POINT EQU R13 Pointers Not in Load Mode EBC EQU X'8' Switch Set to Print EBCDIC PASS2 EQU X'4' Pass Count for Dummy Forms in SBI DHOLD EQU X'2' Hold LED Display COVER EQU X'1' Cover Platen Open Indicator HOST1 EQU R13 (Alternate (Use) Host Selected Switch Communications Microprocessor Registers (Continued) HARD1 EQU R14 Hardware Country Selected Switch LOAD1 EQU R15 Random Access Memory Type of Load Switch 0 Nothing Loaded to Random Access Memory and IPL Mode 1 Multinational Loaded to Random Access Memory 2 Country Overlay of Multinational 4 Mode Switch Modification to Character Set 8 Modification to Character Set DATAO EQU D0,D0 Aux Address Registers DATA1 EQU Dl,Dl Aux Address Registers DATA2 EQU D2,D2 Aux Address Registers DATA3 EQU D3 Buffer Pointer DAR DATA4 EQU D4 Work DAR DATAS EQU D5 Work DAR DATA6 EQU D6 Work DAR DATA7 EQU D7 Work DAR DATA8 EQU D8 Work DAR DATA9 EQU D9 Work DAR BFNUM EQU D10 Buffer Pointer Indicator GECK EOU X'8' In Graphic Error Mode Indicator BFUSE EQU <RT Communications Microprocessor Registers (Continued) LSCON EQU Dll Last Console Setting /F = In Load Mode FMIND EQU D12 Forms Indicator PGUP EQU X'8' Page Up for Display Indicator D2LD EQU X'4' Mask To Test for 2nd Data Load CAN EQU X'2' Cancel Button Held Indicator TRANS EQU X'1' In Transparent Mode Indicator IND EQU D13 Indicators NEG EQU X'8' Negative Skip Indicator XSKIP EQU X'4' More To Skip Indicator PTHLD EQU X'2' Print One Line and Hold PTDON EQU X'1' Print of One Line Done PTRST EQU X'3' Above Two Bits Together CMCTL EQU D14 Command Control Byte D1LD EQU X'8' Mask To Test for 1st Data Load D2LD EQU X'4' Mask To Test for 2nd Data Load D3LD EQU X'C' Mast To Test 1st and 2nd Data Load RESN1 EQU X'1' Mask To Test for 1st Resend RESN2 EQU X'2' Mask To Test for 2nd Resend RESND EQU X'3' Mask To Test for Either Resend NOLD EQU X'F' Mask To Test for No Command MVADJ EQU <RTI ID=83.3> D15 Adjustment Control Byte RLRD1 EQU X'9' Roll and Ready Indicator Together ROLLD EQU X'8' Roll Display Indicator CHGD EQU X'4' Change To Next Sequence Indicator ADJP1 EQU X'2' Change Density Mask RDY1 EQU X'1' Software Ready Indicator RAMIN EQU X'OFFB End of Random Access Memory in ROS Slot Control Microprocessor Registers I00 EQU RO Input/Output Register I01 EQU R1 Input/Output Register R2 Work Register R3 Work Register R4 Work Register PETIT EQU R5 Indicates Previous Emitters PHF EQU R6 Print Head Flags FRMST EQU X'1' Forms Start Flag DNSCH EQU X'2' Density Change Flag PARK EQU X'4' Ramp Command Flag PRCMP EQU X'8' Printing is Complete FLG1 EQU R7 Indicator Flags CD15 EQU X'1' Character Density Equals 15 CPI RV EQU X'2' Print Head is Going Left (Reverse) TXBUF EQU X'4' Head Image Generator Is to Use Text Buffer 2 HIGST EQU X'8' Head Image Generator Is to Start Print Lines FLG2 EQU R8 Ribbon Flags FBFLG EQU X'1' Wire Feedback Flag RBMON EQU X'2' Ribbon Motor Is On FMSTM EQU X'4' Forms Time Flag TOK EQU X'8' Turn Around Is OK WIPOS EQU R9 Wire Position Counter Control Microprocessor Registers (Continued) FECT EQU R10 False Emitter Counter DIAGF EQU X'1' Diagnostic Flag FDRCT EQU X'2' Direction of Forms Movement FE2 EQU X'4' False Emitter 2 FE1 EQU X'8' False Emitter 1 PRERR EQU Rll Printer Error Flags EQU X'8' Not Used HHOME EQU X'4' Head Home Flag TEDGE EQU X'2' Turnaround Edge Flag HATNA EQU X'1' Head Stopped At Turnaround Flag CMDFL EQU R12 Command Flags PRCMD EQU X'1' Print Command Flag PRPND EQU X'2' Print Command Is Pending FMCMD EQU X'4' Forms Command Flag TSCMD EQU X'8' Test Command Flag EMCT1 EQU R13 Emitter Counters Used To Determine EMCT2 EQU R14 Head Position by EMCT3 EQU R15 the Number of Emitters From Left Margin MAIN/AUX EQU D0,D0 Aux Address Registers MAIN/AUX EQU Dl,Dl Aux Address Registers MAIN/AUX EQU D2, D2 Aux Address Registers RM1 EQU D3 Indicates Right Margin RM2 EQU D4 When the Emitter RM3 EQU D5 Counter Attains This Value End of Forms Indicators EOFI EQU D6 End of Forms Indicators LASTED EQU X'8' Last Forms Direction, 1 = Forward; 0 = Reverse LUSY EQU X'4' Busy History Indicator FBSEQ EQU X'2' Busy Sequence Flag EOFER EQU X'1' End of Forms Detected Indicator F: Tl EQU D7 16 Bit Forms AB Emitter Counter FMCT2 EQU D8 FMCT3 EQU D9 FMCT4 EQU D10 SIGN EQU X'8' Counter Sign Bit Emitter Status Register ESTAT EQU Dll LASTE EQU X'4' Last End-of-Forms Emitter Value LASTA EQU X'2' Last Forms A Emitter Value LASTB EQU X'1' Last Forms B Emitter Value EQU D12 FLECT EQU D13 Forms Lost Emitter Counter FECT EQU D14 Forms Missing Emitter Counter PT1 EQU D15 Program Timer 1/Forms Command Count FLAST EQU X'8' 8 or More Forms Commands Flag Equates - Communications Microprocessor the following equivalent expressions, that is, "equates", are used in connection with Communications microprocessor program listings. These are used by an Assembler to fill in a number for the English-type expressions. Name Definition ADRAM Start of Data in Random Access Memory CMDT1 Data for Command Data &num;1 Latches CMLAT Data for Command Latches D1LD Mask to Test for 1st Data Load D3LD Mask to Test for 2nd Data Load HDSP Head Space for DA03 Routine HEADS Number of Heads Switch OVLYM Select Main Overlay Memory OVLY3 Select Overlay 3 Memory PASS2 Pass Count for Dummy Forms in SBI RDYI Software Ready Indicator TBF1S Data in Text Buffer 1 (15 CPI) Labels - Communications ::icrorocessor The following labels are used by the Communications microprocessor. These serve, for example, as pointers for addressing or for branching purposes. Labels Labels AGN MODEX BFBLK NEWPG BFILL NLFWD CONWI OPPNL FILL RELOD FRMEN RTNMP GETBF SAVOV HD2 SDAT1 HD4 SVHDS HD6 TFRE1 HD8 TOCTL LOWER WIDTA XCOMM Proqram Listings Program listings (sourze statements) that relate to the flowcharts ani operations described herein are presented below: Set Up Bit to Fire ires 1-8 Which Are Stored in Hex ovations 0O-OF of Wire Image Random Access Memory Label Op Code Arguments Comment DA03 EQU BAL SAVOV SAVE POINTER TO RETURN THIS OVERLAY OUT OVLY3 POINT TO OVERLAY BAL NEWPG SET NEW PAGE T X'8',LOAD, RELOAD NEEDED IF HOST MODIFIED BF CONWI GO CONTINUE WIRE SETUP IF NOT BAL SAVOV SAVE POINTER TO RETURN THIS OVERLAY BAL RELOD GO RELOAD IF NEEDED Set Us Bit to Fire ires 1-8 Which Are Stored in Hex locations 00-0F of Wire Imaae Random Access Memory (Continued) Label Op Code Arguments Comment CONWI M X'4',LOAD1 INDICATE HARDWARE MODIFIED RANDOM ACCESS MEMORY M X'0', hORK2 INITIAL COUNT OF WIRES M X'0',WORK3 INITIAL COUNT OF FRAMES M X'0',WORK4 ZERO FOR STORING LDAR ADRAM GET RANDOM ACCESS MEMORY ADDRESS M ADRAM,D2,4 SET UP ADDRESS IN DAR'S M ADRAM,D1,3 M ADRAM,D0,2 M X'8',WORK0 SET BIT TO PRINT WIRE M X'0',WORK1 REST OF BYTE BLANK Set Up Bit to Fire Wires 1-8 Which Are Stored in Hex Locations 00-OF of Wire Image Random Access Memory (Continued) Label Op Code Arguments Comment WIDTA ST WORKO,WORKl STORE 2 NIBBLES A X'l',D0 POINT TO NEXT SLICE ST WORK4,WORK4 STORE A BLANK A X'1',DO POINT TO NEXT SLICE A X'1',WORK3 COUNT FRAMES C X'7', WORK3 CHECK FOR END OF 2ND FRAME BE FRMEN AND GO SET UP FOR NEXT FRAME C X'4'WORK3 CHECK FOR END OF 1ST FRAME BNE WIDTA CONTINUE IF NOT STRP WORK4 ,WORK4 STORE AND INCREMENT M X'0',D0 POINT TO NEXT FRAME ST WORK4 ,WORK4 STORE A BLANK A X'1',D0 POINT TO NEXT SLICE B WIDTA GO DO IT AGAIN FRMEN ST WORK4 ,WORK4 POINT TO NEXT CHARACTER A X'1',DO POINT TO NEXT SLICE STRP WORK4' ,WORK4 STORE AND INCREMENT M X'0',W0RX3 SET COUNT IN FRAME SR WORK0,WORKO MOVE BIT THROUGH BYTE SR WORKl,WORKl MOVE BIT THROUGH BYTE M X'0',DC POINT TO NEXT FRAME A X'2', WORK2 POINT TO NEXT WIRE BNC WIDTA GO SET NEXT ONE Set Up Pointers to Text Buffers Label Op Code Arguments Comment M X3',tlORK8 SET TO COUNT UPPER WIRES M X'0',DATA4 INITIAL SPACE VALUES M X'4',DATAS INITIAL SPACE VALUES M X'1',DATA6 INITIAL SPACE VALUES M X'9',DATA7 INITIAL SPACE VALUES LDA HEADS FIND NUMBER OF HEADS C X'3',WORK0 CHECK FOR 2 BH HD2 GO GET VALUE FOR THESE HEADS C X'5',WORKO CHECK FOR 4 BH HD4 GO GET VALUE FOR THESE HEADS C X'7',WORKO CHECK FOR 6 BH HD6 GO GET VALUE FOR THESE HEADS B HD8 GO GET VALUE FOR 8 HEADS Set Up Pointers to Text Buffers (Cont'd.) Label Op Code Arguments Comment HD2 A X'8',DATA5 INITIAL VALUE WHEN ENTERED HERE AC X'1', DATA4 2ND HEAD X'2B' NEXT HEAD X'--' HD4 A X'9',DATAS 13 28 AC X'0',DATA4 A X'9',DATA7 .. .. AC X'0',DATA6 .. .. HD6 A X'6',DATAS OA 1F AC X'0',DATA4 .. .. A X'6',DATA7 .. .. HD8 EQU 04 19 VALU1 M X'0',DATA8 INITIAL DATA TO X'00' AND X'01' M X'l',DATA9 M DATA4,WORKO SET UP TO SAVE DIS PLACEMENT VALUE M DATAS,WORKl STA HDSP Fill Random Access Memory Buffer (198) With Image for One Wire Label Op Code Arguments Comment BFILL EQU BAL SAVOV SAVE POINTER TO RE TURN THIS OVERLAY BAL BFBLK GO BLANK AND GET BUFFER ADDRESS M TBF15,D1,3 POINT TO DATA IN TEST BUFFER (15 CPI) M TBF15,D2,4 POINT TO DATA IN TEST BUFFER (15 CPI) FILL M X'0',WORK2 M DATA8,WORKO M DATA9,WORK1 STRP WORK2,W0RK0 STORE ALTERNATE IMAGES STRP WORK2,W0RK1 FOR EACH WIRE C X'D',D1 COUNT FOR 63 (LOW ORDER) CS X'B',D2 COUNT FOR 63 (HIGH ORDER) BNE FILL Fill in Head and Wire Number for Start of Each Head Label Op Code Arents Comment BAL SAVOV SAVE POINTER TO RE TURN THIS OVERLAY BAL GETBF POINT TO START OF BUFFER M TBFlS,Dl,3 POINT TO DATA IN TEST BUFFER (15 CPI) M TBFlS,D2,4 POINT TO DATA IN TEST BUFFER (15 CPI) M X'F',WORK4 SET START OF EBCDIC NUMBER M X'1',WORK5 SET NUMBER 1 FOR START OF HEAD STRP WORK4,WORKS STORE IN FIRST COLUMN M DATA8, WORK6 GET WIRE NUMBER SR WORK6,WORK6 A X'1',WORK6 STRP WORK4,'.,0RK6 STORE IT IN BUFFER A X'2',DATA8 POINT TO NEXT IMAGE A X'2',DATA9 POINT TO NEXT IMAGE A X'l',WORK5 SET FOR SECOND HEAD LDA HEADS GET NUMBER OF HEADS M WORKO,WORK7 SET FOR COUNTER S X'1', WORK7 DECREMENT LDA HDSP A WORK1,D2 ADD START OF NEXT HEAD AC WORXO,Dl Fi: in Head and Wire Number for Start of Each Head (Continued) Label Op Code Arguments Comment AGN STRP WORK4,WORK5 STORE NEXT HEAD NUMBER START STRP WORK4,WORK6 STORE THIS WIRE NUMBER A X'l',WORK5 SET FOR NEXT HEAD A DATA7,92 INCREMENT TO NEXT HEAD AC DATA6,Dl S X'1',WORK7 COUNT DOWN BNZ AGN DO IT AGAIN IF MORE HEADS SBF PASS2,POINT PREPARE SECOND TILDE THROUGH SWITCH TYRE1 T D3LD, CMCTL TEST FOR COMMAND IN CONTROL ATOM BF SDAT1 OK NOW LOAD NEN COMMAND BAL SAVOV SAVE POINTER TO RE TURN THIS OVERLAY OUT OVLY3 POINT TO PROPER OVERLAY BAL ATOM2 ALLOW LOAD TO CONTROL ATOM IF READY BAL SAVOV SAVE POINTER TO RE TURN THIS OVERLAY OUT OVLYM POINT TO MAIN OVERLAY MEMORY BAL OPPNL GO CHECK OPERATOR PANEL B TFREl GO TEST FOR OK TO GO AGAIN Fill in Head and wire Number for Start of Each Head (Continued) Label Op Code Arguments Comment SDAT1 EQU BAL SAVOV SAVE POINTER TO RE TURN THIS OVERLAY OUT OVLYM POINT TO MAIN OVERLAY MEMORY BAL PTPRT GO CHECK FOR PAPER IN PRINT POSITION T D3LD,G1CTL TEST FOR COMMAND TO TRANSFER BT TFRE1 GO WAIT IF STACK FULL T RDYI, MVADJ TEST FOR STOP BUTTON PRESSED BF MODEX RETURN TO WAIT LOOP IF STOP M X'F',WORKO SET TO PRINT 198 (198+42=240) M X'0',WORK1 STA CMDT1 AND SET FOR DATA LATCHES CLR WORKO PREPARE PRINT COMMAND M X'0',WORK0 SET REG/DAR TO ZERO M BFNUM,WORK1 SET BUFFER INDICATOR SBF X'D',WORK1 REMOVE ALL BUT BUFFER BIT SBN X'9',wORK1 SET PRINT AND 15 CPI INDICATORS STA CMLAT AND SAVE THE STATUS LATCHES Fill in Head and Wire Number for Start of Each Head (Continued) Label Op Code Arguments Comment SBN D1LD,CMCTL INDICATE DATA READY TO TRANSFER M X'0',WORK0 SET UP FOR LINE FEED M X'1',WORKl BAL SAVOV SAVE POINTER TO RE TURN THIS OVERLAY OUT OVLY3 POINT TO OVERLAY BAL NLFWD GO TO FORMS X PASS2,POINT COUNT NUMBER OF LINES PRINTED T PASS2, POINT TEST FOR SECOND PASS BT TFRE1 IF FIRST GO PRINT AGAIN Prepare to Set Up Next Buffer Label O Code Arguments Comment C X'0',DATA8 IS TEST SET UP COMPLETE BE RTNMP RETURN TO MODE CONTROL OR ROUTINE 1 LDA HDSP GET THE HEAD SPACE VALUE C X'8',DATA8 CHECK WHICH WIRE WE ARE ON BE LOWER ARE WE STARTING LOWER 4 WIRES A X'6',WORK1 SET HEAD 2 TO START POSITION AC X'0',WORY0 SVHDS STA HDSP SAVE NEW VALUE B BFILL GO SET NEXT LINE LOWER S X'F',WORK1 SET HEAD 2 TO START POSITION SB X'0',WORKO B SVHDS GO SET NEXT LINE

Claims: CLAIMS 1. Printer subsystem interconnected with a host system for receipt of commands and data information from said host system and transmission of status conditions back to said host system, said printer subsystem including a print assembly, a forms feed assembly, and a ribbon drive assembly and operable to print characters on forms as well as perform other operations in connection with printing. This printer subsystem comprises two microprocessors, the first microprocessor converting the commands and data information received from the host system into a form that can be used by the printer and the second microprocessor handling the converted commands and data information from the first micro processor to control the mechanical elements of the printer. This printer subsystem is characterized in that it further comprises: first means (201) interconnecting said first micro processor (200) with said host system (1) for receipt of said command and data signals from said host system and for transmission of status signals back to said host system representative of various conditions in said printer subsystem; second means (215, 220, 228) interconnecting said second microprocessor (210) with said first micro processor (200) and responsive to command and data signals received from said first microprocessor to produce control signals and character image signals for use by said printer unit during printing operations; third means (212, 213) interconnecting said printer' unit (235, 236, 3.5) with said second microprocessor (210) for transfer of command and data signals from said second microprocessor to said printer unit and for transfer of status signals from said printer unit to said second microprocessor unit; and register means (225, 226) interconnected between said first microprocessor (200) and said second microproces sor (210), said register means being accessible by either microprocessor for entry of information pertai ning to operation of said printer subsystem and for intercommunication purposes between said two micro processors. 2. Printer subsystem according to claim 1 characterized in that it further comprises: means in said host system (1) for producing command signals and data signals in accordance with a high level language format (7); means in said first microprocessor (200) for converting said high level language format to a second format for use by said second microprocessor (210) and said prin ter unit (35, 235), said second format (in 212-213) being more directly representative of functions and information required during printing operations. 3. Printer subsystem according to claim 1 characterized in that it further comprises: means in said host system (1) for providing data signals to said first microprocessor (200) representative of characters to be printed, said data signals being in a first more conventional format (in 217) that differs from the character format utilized by said printer unit; and image generation means (220) interconnected with said first and second microprocessors (200-210) and res ponsive to said data signals in said first format to convert such signals to signals in the second format (in 212, 213) for use by said printer unit. 4. Printer subsystem according to claim 1, 2 or 3 characterized in that it further comprises: storage means (217) associated with said first and second microprocessor means (200-210) t said storage means including space for accommodating at least two text buffers each of which is capable of accommodating an entire line of information to be printed, the first microprocessor (200) entering line information into said text buffers on an alternate basis in such a way that a first text buffer can be filled up with a print line information from said first microprocessor and the image generation means (220) start pulling out charac ters from that first text buffer while said first microprocessor (200) stores characters in another text buffer, this operation alternating back and forth. 5. Printer subsystem according to claim 4, characterized in that the second microprocessor (210) accesses text buffer information in said storage means (217) in response to control signals from said first micro processor (200). 6. Printer subsystem according to any of the preceding claims characterized in that it further comprises: operator facilities (26) for entering control infor mation, said facilities including display means (59) for displaying condition information to an operator; and means (202) for accessing said operator facilities to determine entry of control information by an operator and further operable to provide signals for operating said display means (59) to indicate conditions of said printer subsystem. 7. Printer subsystem according to any of the preceding claims characterized in that it further comprises: emitter means (236) incorporated in said printer unit for indicating positional conditions of a print head assembly (225-30), a forms feed assembly (235-20), and a ribbon drive assembly (235-20); and means (211) for receiving emitter signals from said emitter means and for minotoring position of various assemblies in said printer unit. 8. Printer subsystem according to any of the preceding claims characterized in that it comprises wire matrix means (213, 35) for printing characters on a form in said printer unit by means of dot images. 9. Printer subsystem according to claim 8 characterized in that it further comprises print wires mounted in a slanted pattern (150) with respect to a print line or to a slanted serrated pattern (152). 10. Printer subsystem according to claim 8 or 9 charac terized in that it incorporates a plurality of print heads, each of which comprises a plurality of print wires. 11. Printer subsystem according to claim 8, 9 or 10 charac terized it further comprises: selection means (65) to select a plurality of diagnos tic test operations for said printer unit; storage means (217) for storing print wire images for test purposes; and wire fire mapping means (202, 211, 220, 213) for enter ing test data in said storage means and for supplying actuating signals to said print wire actuators (35) in accordance with a predetermined test pattern to display on a record medium the actual firing and misfiring condition of said print wire actuators and associated print wires. 12. Printer subsystem according to the preceding claims characterized it further comprises: head/wire designation means (286, 287) incorporated in said wire fire mapping means for entering data in said storage means (217) that will actuate said print wire actuators (35) and associated print wires (33) to provide identifying indicia on said record medium indicative of the print heads and print wires in order that wire firings and misfiring may be readily dia gnosed. 13. Printer subsystem according to claim 12 characterized in that said wire fire mapping means (202, 211, 220, 213) are operable to activate said print wire actuators (35) and print wires (33) in accordance with a sequen tial pattern to display the wire firings and misfiring in a matrix format arranged sequentially in accordance with the numbering of print heads and print wires utilized in the printer. 14. Printer subsystem according to claim 13 characterized in that the control means incorporated in said wire fire mapping means (202, 211, 220, 213) enter data in said storage means (217) pertaining to said print wires (33) on a sequential basis with data concerning a particular print wire being printed prior to the entry of data for the next succeeding print wire, said data including information to be printed, such as head number and wire number, said wire fire mapping means controlling the printing of the wire fire data in said storage means at least twice in order to enable quicker analysis of the wire fire mapping printout.

Inventors: BARE, GARY THOMAS, BOYNTON, WILLIAM WARREN, WEBER, CHARLES JOSEPH, ZIMMERMAN, LEE TYRRELL
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1980
Main classification: G06F3
IPC codes: G06K15, G06F3