TRANSISTOR-TRANSISTOR LOGIC CIRCUIT

Abstract: A transistor-transistor logic circuit comprises an input means (10) for receiving an input logic signal (IN), a phase-­ splitting transistor (13) having its base connected to the input means (10), an output transistor (16) having its base con­ nected to the emitter of the phase-splitting transistor (13), wherein the output transistor (16) supplies an output logic signal responsive to the input logic signal from its collector, and a capacitive element (19) having one terminal connected to the collector of the phase-splitting transistor (13) and another terminal maintained at a predetermined potential. The turn-on-time of the output transistor (16) is shortened by the capacitive element (19).

Description: Transistor-transistor logic circuit This invention relates to transistor-transistor logic circuits (hereinafter referred to as TTL circuits), and more particularly, although not exclusively, to an open-collector type TTL circuit which operates at high speed. As is well known, a logic IC (Integrated Circuit) capable of operating at high speed, and being a type of an integrated circuit of a large scale, can be obtained by employing TTL circuits. Accordingly, TTL circuits are used in a variety of small to medium scale digital ICs. As described above, a logic IC which uses TTL circuits is capable of performing high-speed operation. However, due to the recent demand for an even faster highspeed data processing , a logic IC which is capable of operating at an even higher speed is desirable. Therefore, the realisation of a TTL circuit which is capable of performing an even faster highspeed operation is highly desired. Accordingly, preferred embodiments of the present invention aim to provide a novel and useful TTL circuit which meets the above described demands. More generally, according to the present invention, there is provided a transistor-transistor logic circuit comprising: an input means for receiving an input logic signal; a phase-splitting transistor having its base connected to the input means; an output transistor having its base connected to the emitter of said phase-splitting transistor , and being arranged to supply on its collector an output logic signal responsive to said input logic signal; and a capacitive element having one terminal connected to the collector of said phase-splitting transistor, and another terminal connected to a point of predetermined potential. Due to the provision of the capacitive element the turn-on-time of the output transistor may be reduced, and preferred embodiments of the invention may operate at an even higher operating speed, compared to conventional TTL circuits. Preferred embodiments of the invention aim to provide a TTL circuit which is of an open-collector type, capable of operating at high speed. In such circuits, the turn-off-time of the output transistor may be unchanged, and only the turn-on-time reduced, compared to conventional circuits. Other embodiments of the invention aim to provide a TTL circuit which is of a totem pole type, capable of operating at high speed. In such circuits, the turn-off-time of the output transistor may be increased, but its turn-on-time reduced. The turn-on-time and the turn-off-time of the output transistor can be made equal, by selecting a suitable capacitance for the capacitive element which is connected to the collector of the phasesplitting transistor. For a better understanding of the invention and to show how the same may be carried into effect, reference will be made, by way of example only, with reference to the accompanying diagrammatic drawings in which: FIG. 1 is a circuit diagram showing a first embodiment of a TTL circuit according to the present invention; FIGS. 2A and 2B are circuit diagrams respect ively showing modified embodiments of the essential part of the TTL circuit of FIG.1; FIG. 3 is a graph showing a first operational characteristic of the TTL circuit of FIG. 1, wherein a capacitance versus operation time characteristic is shown; FIG. 4 is a graph showing a second operational characteristic of the TTL circuit of FIG.1 , wherein an emitter current versus elapsed time characteristic is shown; ; FIG.5 is a circuit diagram showing a further embodiment of a TTL circuit according to the present invention; and FIGS. 6A and 6B are graphs respectively showing capacitance versus operation time characteristics of the further embodiment. FIG. 1 is a circuit diagram showing a first embodiment ¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ of a TTL circuit of the present invention, of an open-collector type, An input transistor 10 comprises two emitters connected to input terminals Ila and lib which are fed with an input logic signal IN. The base of the input transistor 10 is connected to a voltage source Vcc through a base resistor 12, and its collector is connected to the base of a phase-splitting transistor 13. The collector of the transistor 13 is connected to the voltage source Vcc through a collector resistor 14, and its emitter is connected to the base of an output transistor 16 as well as to ground through a resistor 15. The emitter of the transistor 16 is grounded. The collector of the transistor 16 is only connected to an output terminal 17 which supplies an output logic signal OUT as output, to form a so-called open-collector. However, upon use of this circuit, the collector of the transistor 16 is connected to the voltage source Vcc through a collector resistor 18. Accordingly, the above circuit elements as a whole construct a two-input NAND TTL circuit. A capacitor 19 which is used as the capacitive element which forms the essential part of the circuit of the present invention, is connected in parallel with the resistor 14, between the collector of the transistor 13 and the voltage source Vcc. This capacitor 19 is provided to reduce the turn-on-time of the output transistor, as will be described in the following. The operation of the circuit of the above construction will now be described. When an input logic signal IN of high level is applied to the input terminals 11a and' 11b of the input transistor 10, a base current flows to the phase-splitting transistor 13, to turn the transistor 13 ON. Accompanied by this turning ON of the transistor 13, the output transistor 16 also becomes ON. The above base current which turns the transistor 16 ON is equal to (I1+I2-I3), where I1 is the current which flows to the transistor 16 through the resistor 12 and the transistorsl0 and 13, I2 is the current which flows to the transistor 16 through the resistor 14 and the transistor 13, and I3 is the bypassed current which flows through the resistor 15. Hence, the turn-on-time (that is, the propagation delay time tpHL from the high level to low level) of the output transistor 16 is determined by the magnitude of this current (I1+I2-I3). During the period in which the transistor 13 is OFF, the capacitor 19 is fully charged up to the voltage Vcc of the voltage source. And, when the transistor 13 is turned ON, the collector impedance of the transistor 13 is greatly decreased. Accordingly, all the electrical charge which was charged in the capacitor 19, is added and superposed at once with the above current I2. Accordingly, the base current during the transient period in which the output transistor is turned ON, instantly becomes of a relatively high current. As a result, the turn-on-time of the output transistor 16 becomes quite short, and the operational speed of the TTL circuit is substantially increased. The capacitor 19 which has one of its terminal connected to the collector of the transistor 13, is connected to the voltage source Vcc at its other terminal. In the present embodiment, however, the connection of the capacitor 19 is not limited to the above connection, and can be a connection in which the other terminal of the capacitor 19 is connected to ground. Moreover, this other terminal of the capacitor 19 can be connected to an intermediate voltage Vm between the voltage Vcc add ground potential. The point is, as long as the capacitor 19 is charged up to the source voltage Vcc at one of its terminals during the period in which the phase-splitting transistor 13 is OFF, the other terminal of the capacitor 19 can be of any connection. Furthermore, the stray capacitance formed between the substrates of a semiconductor device, a transistor, a resistor, or a diode can be used as the capacitor 19. In the case where a diode or a transistor is used as the capacitor 19, the capacitance of the corresponding PN-junction diode is used. However, since the capacitance of the PN-junction generally comprises a large voltage dependency factor, it is desirable to keep the capacitance at a maximum value, by making the electrical potential at the two terminals equal. Therefore, in this case, the anode of a diode 20a is connected to the collector of the transistor 13, and the cathode of the diode 20a is connected to the voltage source Vcc, as shown in Figure 2A. On the other hand, in the case where one terminal of the diode is grounded, the cathode and the anode of a diode 20b are respectively connected to the collector of the transistor 12 and ground, as shown in Figure 2B. Generally, when the turn-on-time tpHL of the circuit operation is reduced, this reducing of the turn-on-time accompanies a reverse effect in which the turn-off-time tpLH is increased. However, in the present embediment, the turn-off-time of the output transistor 16 does not increase. The reason why the turn-off-time of the transistor 16 does not increase is that, when the transistor 13 is turned ON, the transistor 16 is also turned ON. However, the turn-off-time of the transistor 16 is independent of the construction of the circuit at the collector side of the transistor 13, and simply only dependent on the time the electrical charge charged at the base of the transistor 16 takes to discharge through the base resistor 15. Hence, according to the present embodiment of the invention, only the turn-on-time of the transistor 16 is reduced without accompanying increase in the turn-off-time of the transistor 16. A first operational characteristic of the TTL circuit of Figure 1 is shown in Figure 3. In Figure 3, the horizontal-axis indicates the capacitance of the capacitor 19 in pico-farads (pF), and the vertical-axis indicates the turn-on and turnoff times T in nano-seconds (ns). A curve I shows the turn-on-time tpHL. As clearly seen from the curve I, as the capacitance increases, the turn-on-time is reduced, and the operational speed is accordingly increased. A curve II shows the turn-off-time tpLH. As clearly seen from the curve II, the turn-off-time is substantially constant no matter what the capacitance is, for the reasons described above. A second operational characteristic of the TTL circuit of Figure 1 is shown in Figure 4. In Figure 4, the horizontal-axis indicates the elapsed time, and the vertical-axis indicates the emitter current IE of the transistor 13. Curves I, II, and III respectively show the emitter current variation for when the capacitance of the capacitor 19 is 3 pF, lpF, or 0 pF. As clearly seen from the curves I, II, and III, as the capacitance of the capacitor 19 is increased, the peak amplitude of the emitter current IE is increased. Furthermore, the rise-time of the emitter current IE decreases, and the rising characteristic becomes one in which the rise is very sharp. In Figure 4, a time tO indicates the time when the input logic signal IN becomes 1.3 volts, and the times ta, tb, and tc respectively show the times when the emitter current 1E shown by the curves I, II, and III reaches a certain current value IA. The time between the times tO and ta (tOta), the time between the times tO and tb (tots), and the time between the times tO and tc (tO tc) respectively are proportional to the turn-on-time in each of the curves I, II, and III. That is, to tacts tb < tO tc, and therefore, the turn-on-time is inversely proportional to the increase in the capacitance, and decreases. A second embodiment of a circuit of the present invention will now be described in conjunc:ion with Figure 5. In Figure 5, those parts which are the same as those corresponding parts in Figure 1 are designated by the like reference numerals, and their description will be omitted. This embodiment of the invention comprises a totem pole type T3L circuit. One terminal of the capacitor 19 is connected to the collector of the transistor 13, and the other terminal is connected to a voltage source Vm. The base and the collector of a transistor 21 are respectively connected to the collector of the transistor 13 and the resistor 18. The base of a transistor 22 is connected to the emitter of the transistor 21 as well as to ground through a resistor 23. The emitter and the collector of the transistor 22 are respectively connected to the collector of the transistor 16 and the collector of the transistor 21. According to the circuit of the present embodiment, when the phase-splitting transistor 13 is turned OFF, the collector of the transistor 13 charges the stray capacitance of the collector through the resistor 14. Hence, the rise-time of the collector potential of the transistor 13 is determined by a time constant formed by the resistor 14 and the capacitor 19. The rise in the collector potential of the transistor 13 is visible at the output side, after being shifted of its level by the two transistors 21 and 22. By providing the capacitor 19, the turn-on-time tpHL is reduced.as shown by a curve I of Figure 6A, for the same reason as that described above for the first embodiment. However, since the capacitor 19 is provided, the turn-off-time tpLH becomes long as shown by a curve II of Figure 6A, because the time constant determined by the resistor 14 and the capacitor 19 is increased. As shown by the curves I and II of Figure 6A, hazards can be decreased by letting a difference exist between the turn-on-time tpHL and the turn-offtime tpLH. Furthermore, due to the recent developments in the processing techniques, the stray capacitance of recent transistors is small, and therefore, a circuit can be obtained in which the turn-off-time tpLH is shorter than the turn-on-time tpHL. Hence, when the circuit of the present invention is applied to this type of a circuit, and the capacitance of the capacitor 19 is selected to a suitable value, a characteristic such as that shown in Figure 6B can be obtained in which the turn-on-time characteristic curve Ia and the turn-off time characteristic curve IIa intersect at one point. Accordingly, the turn-on-time tpHL and the turn-off-time tpLH can be selected so that they are equal.

Claims: CLAIMS 1. A transistor-transistor logic circuit comprising: an input means (10) for receiving an input logic signal; a phase-splitting transistor (13) having its base connected to the input means (10); an output transistor (16) having its base connected to the input means (10); an output transistor (16) having its base connected to the emitter of said phase-splitting transistor (13) , and being arranged to supply on its collector an output logic signal responsive to said input logic signal; and a capacitive element (19) having one terminal connected to the collector of said phase-splitting transistor (13), and another terminal connected to a point of predetermined potential. 2. A circuit as claimed in claim 1, in which said capacitive element is a capacitor (19). 3. A circuit as claimed in claim 1, in which said capacitive element is a PN-junction diode (20a, 20b). 4. A circuit as claimed in claim 1,2 or 3, in which said predetermined potential is the power source potential (Vcc) of the circuit. 5. A circuit as claimed in claim 1, 2 or 3, in which said predetermined potential is ground potential. 6. A circuit as claimed in claim 1, 2 or 3, in which said predetermined potential is an intermediate potential (Vm) between the power source potential (Vcc) of the.circuit and ground potential. 7. A circuit as claimed in claim 3, in which the anode of said diode (20a) is connected to the collector of said phase-splitting transistor (13) , and the cathode of said diode is connected to a voltage source. 8. A circuit as claimed in claim 3, in which the cathode of said diode (20b) is connected to the collector of said phase-splitting transistor (13) , and the anode of said diode (20b) is connected to ground. 9. A circuit as claimed in any preceding claim, which further comprises a first transistor (21) having its base connected to the collector of said phasesplitting transistor, and a second transistor (22) having its base, collector, and emitter respectively connected to the emitter of said first transistor (21), the collector of said first transistor (21), and the collector of said output transistor (16). 10. A circuit as claimed in any preceding claim, wherein said input means comprises an input transistor (10) arranged to receive said input logic signal at its emitter, and having its collector connected to the base of said phase-splitting transistor (13).

Inventors: ENOMOTO, HIROMU, IMAIZUMI, TAKETO, MITONO, YOSHIHARU, OHTA, HIROSHI, YASUDA, YASUSHI
Applicants: FUJITSU LIMITED
Application year: 1980
Main classification: H03K19
IPC codes: H03K19, H03K17