INTERFACE UNIT BETWEEN A COMPUTER AND A HARDCOPY OUTPUT DEVICE

Abstract: An interface unit for connection between computers having a timed transfer output interface and hardcopy output devices operating on a parallel handshaking principle comprises a microprocessor (1) connected between the computer and the output device by respective hardware units. The hardware unit connected to the computer includes a Status Buffer (4) divided into two parts (9) and (10) one of which (10) is an intermediate transfer area between the microprocessor and the computer interrogated Status Buffer (9). Transfer from part (10) to part (9) is controlled so that the computer can control status and so that timing restrictions are met. Means are provided for avoiding loss of data when the output device is rendered inoperable.

Description: INTERFACE UNIT BETWEEN A COMPUTER AND A HARDCOPY OUTPUT DEVICE DESCRIPTION This invention relates to interface units far connection between computers and hardcopy output devices. There is a class of computers, for example the ICL 1900, that have a standard output interface based on a principle of a timed transfer and response. Such an output interface requires an output device to transmit certain signal responses to output signals from the computer within fixed time periods. There is a class of output devices which operate on a different principle: they have an input interface operating on the so called 'handshake' principle whereby the computer sends instruction to the output device and then waits for a response before initiating the next step; there being no rigid time control of the signalling. OMPI / WIIPPOO To allow such output devices to function with such computers an interface unit is called for which can emulate the respective interfaces to the computer and output device. To construct such a unit from hardware alone generally would require an excessive number of components, and so it is to be preferred to use a microprocessor in combination with hardware. However, this then presents a problem because the time periods in which microprocessor operations take place are longer thanthose required in the timed transfer operation of the types of computers likely to benefit from such a unit. More specifically the types of devices to which interface units according to the present invention are connected are as follows:- Computers of the kind having an output interface including output paths which comprise respectively, a dat path along which is transmitted instructional and command data for an output hardcopy device, an address line along which is transmitted the address of the output device and a line along which timing signals are trans¬ mitted, and including respective input paths along the first of which data is transmitted indicating the present status condition of the output device, the second compris an interrupt path for data indicating that the output device is ready for service and the third a request path indicating that data is required from the computer by the output device. OMPI IPO The. computer output interface operates on a timed transfer basis wherein once information is requested by the computer from the output device it must be actioned in a predetermined short time period and an appropriate response sent back to the computer. The status of the output device is transmitted along said line and this status information must not be changed during the period of transmission. Such computers are hereinafter referred to as computers of the kind specified. Hardcopy output devices of the kind including input paths which respectively include a print data path and a strobe path along which signals indicative that data is available are sent, and including output paths which respectively include an acknowledgement path along which signals are transmitted acknowledging that data has been utilised by the output device, and a status path along which the status of the printer is indicated. The status indicated on this path may change without reference to timing constraints that may be present in the computer. The output device is characterised in that it acts on a handshake principle with regard to print data transfer, that is to say that it utilises data sent along the print data ' path in its own time and then acknowledges the data. Upon such acknowledgement it can then be sent more print data. Such hardcopy output devices are hereinafter referred to as of the kind soecified. According to the present invention there is provided an interface unit for connection between a computer of the kind specified and a hardcopy output device of the kind specified, the interface unit including a microprocessor and first and second hard¬ ware units connected between the microprocessor and respectively, the computer and the hardcopy output device, characterised in that:- the first hardware unit includes a status buffer store for storing data indicative of the actual or proposed operational status of the hardcopy output device, the status buffer store having first and second parts, the first part being interrogatable by both the microprocessor and the computer but updatable directly on by the computer, and the second part being updatable by the microprocessor, the second part of the status buffer store being operative to transfer the status information stored therein to the first part except when it is prevented from doing so by a disenabling signal produced by the first hardware unit when the first part of the status buffer unit is interrogated by the computer; the first hardware unit further including a status change detection means operative to detect that the first part of the status buffer store has been updated by the OMPI computer and to transmit to the microprocessor the new status information stored in the first part of the status buffer store. An embodiment of the invention will o be described, by way of example only, with reference to the accompanying drawings. In the drawings Figure 1 is a block diagram of the functional elements included in the interface unit, and Figure 2 is a circuit diagram of part of a status buffer unit included in the interface unit. In this embodiment the interface unit will be described with reference to the connections of a typical computer of the kind specified, the ICL 1900, and a typical hardcopy output device of the kind specified, a parallel, handshaking interfaced printer. The CoETDuter Outout Interface The required information transfer characteristics across the output interface of the ICL 1900 computer will now be illustrated by a description of the steps undertaken during a transfer of a single line of print from the computer to a printer. The terminology used in the ensuing description is as ollows:- (i) 1900 INTERFACE The Interface associated with a Main Central Processing Unit that operates on a timed transfer principle, e.g. the ICL 1900. (ϋ) PRINTER INTERFACE An Interface which is able to communicate with the 19*00 INTERFACE. (iϋ) WRITE COMMAND A data transfer to the PRINTER INTERFACE requesti the initiation of printer action. (iv) PAPER MOVEMENT A data transfer to the PRINTER INTERFACE requesti carriage movement. (v) PRINT CONTROL A data transfer to the PRINTER INTERFACE requesti printing action. (vi) WRITE STATUS Information relating to th acceptability of a WRITE COMMAND to the PRINTER INTERFACE. (vii) OPERATIONAL STATUS Information relating to th operational status of the PRINTER INTERFACE. (viii) DISCONNECT COMMAND A data transfer to the PRINTER INTERFACE specifyi it logical disconnection. OMP WIP The steps undertaken during a single line transfer between the 1900 INTERFACE and the PRINTER INTERFACE are as follows:- (i) The 1900 INTERFACE interrogates the printer WRITE STATUS for permission to issue a WRITE COMMAND which initiates printer action, (ii) The PRINTER INTERFACE must respond within 750 nano seconds-, (iii) If the WRITE STATUS is acceptable then the 1900 INTERFACE issues the WRITE COMMAND, The PRINTER INTERFACE must update the OPERATIONAL STATUS within 400 nano seconds, (iv) After a minimum delay of 2.4 micro seconds from the issue of the WRITE COMMAND, the 1900 INTERFACE sends PAPER MOVEMENT and PRINT CONTROL information to the PRINTER INTERFACE, (v) If the PRINT CONTROL specifies that no printing is required then the OPERATIONAL STATUS must be reset within 400 nano seconds. The 1900 INTERFACE may optionally send a DISCONNECT COMMAND after a minimum delay of 2.4 micro seconds from the transfer of PAPER MOVEMENT and PRINT CONTROL information. (vi) If the PRINT CONTROL specifies that printing is required then the PRINTER INTERFACE requests data one character at a time at its own nace. OMPI_ /,, W W I 1 P0 U ■ ■ £\> _ Each individual character transfer, however, must be completed within 750 nano seconds once the request has been serviced by the 1900 INTERFACE.- (vii) At the termination of print data transfer the PRINTER INTERFACE must reset the WRITE STATUS within 400 nano seconds of the last character transfer. Additional timing and communication problems occur between the 1900 INTERFACE and the PRINTER INTERFACE and these are outlined below: (i) The 1900 INTERFACE may request the OPERATIONAL STATUS at any time. The PRINTER INTERFACE mus respond within 750 nano seconds, (ii) The 1900 INTERFACE may request the updating of the OPERATIONAL STATUS between single line transfers. The PRINTER INTERFACE must respond within 750 nano seconds and must further update the OPERATIONAL STATUS within an additional 400 nano seconds, (iii) The ' DISCONNECT COMMAND requires the 1900 INTERFACE to interrogate the OPERATIONAL STATUS for acceptability: Response is require within 750 nano seconds. If acceptance is OMPI l WIPO given the DISCONNECT COMMAND is issued and the OPERATIONAL STATUS must be reset within 400 nano seconds, (iv) Before transfer of any data character the request which has been issued from the PRINTER INTERFACE must withdrawn -immediately * upon the start of service by the 1900 INTERFACE. (v) The WRITE STATUS ' and the OPERATIONAL STATUS cannot be updated during interrogation. Changes to the status must, therefore, be held until interrogation is complete. (vi) There is a requirement to generate an interrupt request to the 1900 INTERFACE whenever certain status information is reset. The interrupt request must, however, be withdrawn 'immediately' upon the start of interrupt service by the 1900 INTERFACE. The Parallel Handshaking Printer Interface The operation of a typical printer interface based upon a handshaking transfer principle will now be described. Information concerning the actual status of the printer may be passed via independent channels with no associated handshaking or timing restrictions. The following describes the transfer of data to the printer and the generation of status information by the printer. OMPI fj, WIPO ΛΛ The terminology used in the ensuing discussion as follows:- (i) PARALLEL INTERFACE A Printer Interface operating on a hand¬ shaking principle. (ϋ) COMPUTER INTERFACE Any computer interface which* is able to communicate with the PARALLEL INTERFACE. (iii) PRINTING DΞVICϊ That part of the Printe which implements the printing action trans¬ ferred to it by the PARALLEL INTERFACE. (iv) DATA BUS A combination of commun cation lines used to transfer information fr the COMPUTER INTERFACE to the PARALLEL INTERFA (v) PRINTER STROBE LINE A communication line us to indicate to the PARALLEL INTERFACE the presence of information on the DATA BUS, OM W w IP (vi ) ACK/RΞQUEST LINE A communication line used to indicate to the COMPUTER INTERFACE that the information on the DATA BUS has been fully actioned. (vii ) ENVIRONMENTAL STATUS Information relating to operational capability ■ of the PRARLLEL INTERFACE. (viii) STATUS LINI A single independent communication line associated with one condition of the ENVIRONMENTAL STATUS. The PARALLEL INTERFACE does not need to distinguish between the types of data character sent by the COMPUTER INTERFACE. It is the PRINTING DEVICE which actions each character in its context. In general each data character is transferred by a handshaking protocol as follows:- (i) The COMPUTER INTERFACE sets the DATA BUS to the required character value. (ii) The COMPUTER INTERFACE actions the PRINTER STROBE LINE for a period of not less than 1.0 micro seconds after a delay of not less than 1.0 micro seconds after the DATA BUS has ^U REΛ? OMPI been set to the required value. This indicates to the PARALLEL INTERFACE the ~ preser.ee of data on the DATA BUS. (iii) The PARALLEL INTERFACE accepts the character from the DATA BUS during the 1.0 micro second period. >._, * . (iv) The PARALLEL INTERFACE does not take any further action until the data has been successfully utilised by the PRINTING DEVICE. (v) The PARALLEL INTERFACE actions the ACK/REQUEST L to indicate to the COMPUTER INTERFACE that the data character has been successfully utilised. This indication may take the form of an acknowledgment strobe or a request for more data. A single exception to the handshaking protocol outlined above is the reception by the PARALLEL INTERFACE of a 'Deselect' Command. This is an instruction to logically disconnect the PRINTING DEVICE from the PARALLEL INTERFACE.. The effect of this action inhibits the ACK/RΞQ LINE response to. the COMPUTER INTERFACE. The ENVIRONMENTA STATUS is, however, reset to reflect this condition. Parallel Hankshaking Interface Status Information The PARALLEL INTERFACE permanently holds information relating to the availability and operational capability of the -PRINTING DEVICE. .The information is held in the ENVIRONMENTAL STATUS, whose components when set in isolation or in combination reflect the following conditions:- (i) The logical connection of the PRINTING DEVICE to the PARALLEL INTERFACE, i.e. SELECT status. (ii) The fully operational capability of the PRINTING DEVICE, i.e. READY status, (iii") The status of physical conditions of- the PRINTING DEVICE with regard to e.g. paper availability and position, character set utilisation and vertical form Unit condition. Each component of the ENVIRONMENTAL STATUS is available for interrogation by the COMPUTER INTERFACE on an independent STATUS LINE. These STATUS LINES permanently hold the Operational Status of the PRINTING DEVICE. The present invention illustrated in the Figures comprises an interface unit that enables the 1900 INTERFACE to be connected to the PARALLEL INTERFACE so that the two interfaces see respectively appropriate printer and computer interfaces. The interface unit includes a microprocessor 1 which is able both to communi¬ cate and interact with the hardware necessary to implement OMPI _ WIPO both the COMPUTER INTERFACE and the PRINTER INTERFACE. In addition it is capable of manipulating and storing a complete line of print data between the two interfaces in such a way as to emulate an appropriate printer. The microprocessor 1 is suitably an INTEL 8748 single chip microprocessor and together with a number of support devices forms the interface unit. The functions of the support devices are twofold:- (i) Provision of basic microcomputer functions, e.g. bulk storage and standard bus communicatio (ii) Standard hardware functions associated with the implementation of the COMPUTER INTERFACE and the PRINTER INTERFACE. The microprocessor 1 provides the major intelligence for the Interface unit both by virtue of its hardware capability and the software implemented within it. The software drives not only the microprocessor 1 but also the other support devices to provide the complete simulation of a printer appropriate to the timed transfe computer interface. The object codes of the programme for the microprocessor are set out on the following pages Each page represents one memory page within the micro¬ processor and the description is in hexadecimal. As will be appreciated by those skilled in the art this provides complete instructions enabling the microprocessor to run the interface unit. OMPI IPO OBJECT MAP SO-PO 0 1 8 B D E OO 00 44 08 D5 AE 04 10 D5 AE 23 80 4A AA 65 FE 93 00 10 B8 28 OA AO • 36 FD 76 2D 09 72 F5 B2 F9 D2 FB 52 10 20 F3 12 36 32 D7 92 F7 B8 28 FO 3A FE 93 09 92 F7 20 30 B2 F9 D2 FB 04 19 23 10 3A 08 AF D2 8A B6 41 04 30 40 27 B8 2D FO 96 C7 23 01 3A FF 53 3F A8- C5 FC D5 40 50 12 77 F8 C5 97 03 05 E6 7D 03 5C B3 7D 61 67 6D 50 60 7D BC 00 BD 00 04 88 BC 40 BD 40 04 88 BC 80 04 60 70 88 53 CO 48 A8 04 85 32 71 C5 53 DO AC FD 20 D5 70 80 48 E3 A8 C6 B2 F8 91 19 D5 FF F2 Λ4 B6 18 C5 AC 80 90 D5 B8 2C BO 41 23 01 4A AA 23 DO 3Λ 23 08 90 23 90 ΛO OC 90 04 27 23 01 3A B8 2C BO 00 B8 29 FO 91 19 ΛO BO 04 95 FF F2 85 F9 03 FA 96 85 B8 23 FO 53 1F 96 BO CO 88 B8 2D BO 01 04 18 23 DO 3A 23 08 90 23 OC 90 CO DO B8 2D BO 00 FF 04 DC 23 50 3A 08 AF D5 AD D5 F2 DO ' EO ED 23 02 4A AΛ 23 DO 3A 23 04 90 04 27 B8 2C BO EO FO 00 04 E1 24 00 24 02 24 04 24 06 24 08 44 06 00 FO 0 3 7 8 A B D E F OBJECT MAP SO-P1 0 8 A B D E 00 24 OC 24 51 24 6B 24 BA 24 E3 24 F4 23 20 3A 85 00 10 FB F2 19 5C 4D F2 26 24 36 5C 4D B8 31 40 F2 26 10 20 53 45 B8 2C 40 95 AB B2 4B 90 09 52 2F 24 2A B8 20 30 2B 46 36 FO 96 FC BC FF BD 00 BO 00 23 EO 3A 23 30 40 OC 90 B6 46 24 FC 18 B8 00 24 FC 92 29 53 CE 24 40 50 26 23 60 3A FB F2 5B 08 ΛB 24 FC 08 AB F2 FC 23 50 60 DO 3A 23 OC 90 23 04 4A ΛA 24 FC 76 86 A5 C5 FE 60 70 53 EF AE 23 03 3A FE D5 B8 00 90 18 C5 FB BB 00 70 80 D5 C6 FC 90 24 FC 23 01 3A 81 19 C6 A9 AF 23 03 80 90 3A B8 01 FF 90 00 00 00 46 A1 C9 23 10 4A AA 24 90 ΛO 6E B8 26 FO D9 96 FE 24 6D 81 37 96 A1 19 23 EO AO BO 3Λ 23 OD 90 B8 2B BO 01 24 Λ1 23 03 3A B8 02 80 BO CO 00 00 00 00 00 00 00 09 B2 CC 24 FC 80 C5 53 07 CO DO AA FE 53 DF AE D5 B8 00 90 65 27 62 55 23 08 4A DO EO AA 24 FC 23 03 3A C5 FE 43 CO D B8 00 90 23 DO EO FO 3A 23 OF 90 23 EO 3A 23 OD 90 24 FC 04 27 04 2D FO 0 8 A B D E / OBJECT MAP S0-P2 0 8 A B D E '00 44 OA 44 14 44 1F 44 69 44 9A 23 - 08 3A B8 00 80 00 10 B8 20 AO 83 B8 21 AO 2^ 08 3Λ FO - B8 01 90 83 C5 10 20 AF 5 OA F2 5F 53 1F C6 5F A8 D3 - 02 C6 36 D3 01 20 30 C6 36 F8 DF 96 5F 35 15 D5 B8 07 - 54 17 54 OA F2 30 40 43 44 3D D2 60 53 3F A8 FO ΛF B8 - 1F 54 17 09 AF 40 50 54 OA F2 43 53 1F C5 D8 C6 38 27 - 54 14 05 25 83 50 60 53 3F A8 23 01 3A 80 44 9 FB F2 - 7A BD 00 BC 02 60 70 23 DO 3A 23 OE 90 36 76 44 BC B6 - 80 BD BO 44' 6E 70 80 FA 12 7C 23 01 3Λ B8 29 FO 91 19 ' - 23 01 4Λ AA 23 80 90 DO 3A 23 08 90 23 OC 90 44 7C 27 - 62 55 16 A1 44 90 A0 9D 23 FF 39 16 Λ8 44 A4 23 7F 39 - 16 AF 44 AB 23 AO BO 08 3A 27 B8 02 90 37 18 90 F5 04 - 00 24 OA 00 00 BO CO 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 CO DO 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 DO EO 00 00 00 00 00 00 00 0.0 00 00 00 - 00 00 00 00 00 EO FO 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 FO 0 8 A B D E (OBJECT MAP SO-P3 0 1 8 A B D E F ,00 4F 31 32 33 3 35 36 37 38 39 3A 3B 3C 3D 3E 3F 00 10 20 21 22 23 5C 25 26 27 28 29 2Λ 2B 2C 2D 2E 2F 10 20 40 41 42 3 44 45 46 47 8 49 4A 4B 4C 4D 4E 30 20 30 50 51 52 53 54 55 56 57 58 59 5A 5B 24 5D 5E 5F 30 40 4F 31 32 33 34 35 36 37 38 39 3Λ 3B 3C 3D 3E 3F 40 50 20 21 22 23 5C 25 26 27 28 29 2A 2B 2C 2D 2E 2F 50 60 60 61 62 63 64 65 66 67 68 69 6Λ 6B 6 ' C 6D 6E 6F 60 70 70 71 72 73 74 75 76 77 78 79 7Λ 7B 00 00 00 5F 70 80 10 11 12 13 14 15 16 ' 17 18 19 1A 1B 1C 1D 1E 1F 80 90 00 01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF 90 AO 20 21 22 23 24 25 26 27 28 29 2Λ 20 2C 2D 2E 2F ΛO BO 20 20 20 20 24 5D 5E 5F 7C 7D 7E 7F 00 00 00 5F BO CO 4F 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F CO DO 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F DO EO 40 41 42 43 44 45 46 47 48 49 4Λ 4B 4C 4D 4E 30 EO FO 50 51 52 53 54 55 56 57 58 59 5A 28 5B 29 5D 5F FO 0 8 A D E o *- CM r-Λ r vo o- oo σ\< fflϋf^Wfa II II II u II II II II II II Ii II II II I En I l l l l l l l I I I I t I I I H W fΛ< fΛCO-d- CO Q CM P <VθvO C-— - O M O CM m M En CM P P En E£J K 00 CJi n O O I l l l l l l l I t l l l l l l P i OO o co comi -5--d" O M o-d-o- O CM CTWO O T- CQ CM CM E r- P fΛ< r-VO O I I I I t 1 I I I I I I t I I t I l l l l l l l 1 I I I I 1 I I o too o r-P P -d- < IOΓ O - -«d- P o CM -o*- σ- CM cq Eϋ o En CM P O En CnVOvO I I I I t t I t I 1 1 I i 1 t 1 fΛ < NO NO-ϊ 'A mvo P co o-d- o o CM 1-Λ V CO O O - P P CO P P 1- τ- O O I l l l l l l l I I I I t I I C7> c o < moo -d- o P O fΛ CO En-d"-d- J. ζ\ K fΛ M PQ CQ o σ> -5 cτ»En mm r^-vovo I 1 I I ' I I I I 1 I I I 1 I I I 00 I I 1 I I 1 I 1 I I I I I I I I I t t I t I t I I t l l l l l l VO O CM O O CM < m ' -d- in in -d- -d- vo co vO fΛ r σ-i-d- σ-o En m CM P En O τ- O CO O I I I t I I I t I t l l l l l l m o O CM-d * CO T- O-d-d- m P o in Ot CΛM CM Pσ Eιθ E CTvEn <r u W< OVO 1 l l l l l l l I I I t I I 1 t fΛ mm- - co CQ-d- NΛ m« o CM P r>-pvo CM CM CM O T- E-l r- CM O En C P POEn O I I I I I I I I I I I I I t I I t p co o co ω-d- < t - O o mvo«d--d- m c-~ o nm < T- in CM En P P CO τ-vθ I I t I I I I I I I I I I I I I CM -d * p < En P O-d" O CM En-d- Ov 00 -d" M o O fΛO r-ΛfΛ-d; P v- CJMA M O O O En I I l l l l l l l I t l l l l l l CO -d- O fΛ Λ ΛVO 00 T- Cn En CO O O O fΛO- o T- CM O O- r- O O W P σ^P En CM CM < I l l l l l l l I 1 I I 1 I I I s -d- fΛO mo O CM O t-Λ CM P E-l En COVO O EH O CM CT\ CM CT * f" P CM v- O O CM O CO O . W II II II II II II II I 11 11 11 11 11 II II II >-o p o ooooooo O O O O O o o T- CM m-d- vo c-~ co σ--< P o 8 o c< EQ En OBJECT MAP S1-P1 0 1 8 A B D E F "00 24 2A 24 7B 24 08 24 5A 23 FB 34 - EF - 23 08 34 E5 00 10 C5 B8 31 BO 00 FA 32 E7 BB 13 34 F1 - 34 F3 D5 FA 10 20 C5 72 25 24 1E FA 32 E7 24 1C 23 07 - 34 E5 23 FE 20 30 34 EF C5 FC B8 22 53 7F AO D3 5C C6 - 41 B9 25 F1 30 40 AO D5 FA 72 54 F2 4B 32 5Λ 24 41 23 - 7F 34 EF C5 40 50 34 F3 24 41 23 08 34 F9 24 41 23 OΛ - 34 E5 23 FD 50 60 34 EF FB F2 6E FA 52 6E C5 FD F2 6E - 24 E7 C5 FD 60 70 53 BF B8 23 AO 92 89 B2 E9 34 F7 53 - OF C6 9E' 72 70 80 83 24 9F 53 07 C6 9E 24 A1 53 1F 03 - 7E B3 9E 9E 80 90 B2 9E 9E 9E 9E 9E CD D3 D9 DF 9E 9E - 9E 9E 27 43 90 ΛO 10 34 FB B8 23 FO F2 AD BO 20 FO 24 - E9 D5 BD 31 AO BO 24 ED FD F2 9E 23 43 ΛC AD D5 B9 00 - 23 01 3A 23 BO CO 1D 91 19 C5 Bέ 29 BO 1E 18 BO 00 24 - EB B8 25 BO CO DO 5A 24 9E B8 25 BO 5C 24 9E B8 2E BO - 00 24 9E B8 DO EO 2E BO CO 24 9E 64 04 04 02 44 00- 44 - 02 44 04 64 EO FO 06 64 08 64 OA 64 oc 64 OE 64 10 64 - 12 00 00 00 FO 0 1 7 8 A B D E 'OBJECT MAP S1-P2 0 7 8 A B D E OO 44 06 44 2A 44 5E AF F2 E7 B8 29 BO OD 18 B9 20 00 10 F1 03 8A AO B8 22 FO 77 53 01 C6 1F B8 2E 60 AC 10 20 AD FF 72 26 43 10 53 17 54 F5 85 95 23 DO 3A 23 20 30 OD 90 23 09 90 D5 FA 72 49 F2 4F 12 58 32 41 44 30 40 35 C5 FD 43 20 AD D5 44 E5 23 08 54 F3 44 35 23 40 50 7F 54 EB C5 54 EF 44 35 23 FE 54 EB BD 11 85 F9 50 60 B9 00 C5 B8 26 AO 37 17 97 B8 2Λ 60 F6 72 FO B8 60 VO 26 AO B5 54 ED D5 FΛ F2 7F 92 88 76 75 44 E3 23 70 80 7F 54 EB C5 54 EF 44 75 72 8C 44 75 23 OC 54 E9 80 90 23 DO 3A 23 09 90 23 05 90 23 08 54 F3 23 EO 3A 90 AO 23 OA 90 A5 C5 BB 11 54 ED D5 FA F2 ΛF 44 A9 23 AO BO 67 54 EB 23 EO 3A 23 OB 90 C5 54 EF FA 96 C1 44 BO CO 72 23 00 54 F3 D5 FΛ F2 CB 44 C5 23 67 54 EB C5 CO DO 54 EF. FA 96 C5 BB 7F 54 ED D5 B9 00 C5 23 OE 54 DO EO E9 44 72 04 02 24 06 24 02 64 04 64 06 64 08 64 EO FO OA 64 OC 64 10 64 12 00 00 00 00 00 00 00 00 00 FO 0 1 8 B D E OBJECT MAP S1-P3 0 8 B D E F 00 64 14 64 1E 64 29 64 2E - 64 - 41 - 64 - 45 64 - 4B - 64 52 = 00 10 64 67 64 A2 23 08 3A B8 - 00 - 80 - B8 - 20 ΛO - 83 - B8 21 = 10 20 AO 23 08 3A FO B8 01 90 - 83 - E5 - 54 - 0 F5 - 93 - 35 15 « 20 30 5Λ AA 05 25 83 15 4E AE - 05 - 23 - 03 - 3Λ FE - B8 - 00 90 = 30 /-ι0 83 23 10 64 35 23 20 BΛ - 00 - 64 - 35 - 23 EO - 3Λ - 23 OD = 40 50 90 83 FO F2 66 43 80 AO - B9 - 2B - B1 - 01 19 - B1 - 00 D5 = 50 60 BD 41 74 4B C5 FO 83 C5 - ΛF - D5 - 23 - F7 74 - 2E - C5 B9 ■= 60 70 2B B1 01 FA 6F 03 92 A3 - B9 - 31 - F2 - 86 Λ1 - D5 - 15 4D = 70 80 AD BC F9 05 64 8E B1 ' 00 - D5 - BC - 71 - 53 7F - ΛD - 74 4B 80 90 C5 83 85 85 85 85 87 87 - 87 - 87 - 09 - 09 09 - 09 - OB OB 90 A0 OB OB ΛF 23 01 3Λ D5 B9 - 2F - F1 - C6 - ΛF 27 - 64 - B1 23 ΛO B0 OD B9 00 91 19 91 19 27 - 91 - 19 - - 91 - 19 37 - 91 - 19 27 BO CO 91 C5 FF 53 07 06 FO FF - D5 - 92 - - DΛ - 52 D3 - 32 - D3 23 CO DO OC 64 E9 91 B9 02 23 1F - 64 - E9 - - 52 - D3 32 - EO - 64 E7 DO EO 12 D3 23 OA 91 B9 02 23 - OA - 91 - 23 - DO 3A - 23 - OE 90 EO FO D5 B9 06 C5 83 00 00 00 - 00 - 00 - 00 - 00 00 - 00 - 00 00 FO 0 7 8 Λ B D E F Whilst the hardware support device are in general standard blocks such s can be implemented by a skilled person in this art, their interconnections and arrangement have been devised in the present invention to overcome the difficulties which are present even with micropro¬ cessor control. A major difficulty in this area is the relatively slow instruction time of the microprocessor 1 in relation to the time periods required by the PRINTER INTERFACE. The minimum instruction time for the -INTEL 8748 microcomputer is 2.5 microseconds. Instruction times may be further extended in cases where communication with standard support devices is concerned. The printer interface presented by the interface unit is formed from the following functional elements:- a Main Character Buffer 2, an Auxilliary Character Buffer 3, a Status Buffer 4, a Command Recognition Unit 5-* an Interface Control Unit 6, a Data Transfer Control Unit 7, a Status Control Unit 8. The computer sends two types of data to the inter¬ face unit, firstly there is Command Data which is inform¬ ation which is a directive to the interface unit and is not printed. In general the commands recognised are: WRITE COMMAND, STATUS INTERROGATION COMMAND and DISCONNECT OMPI COMMAND. Secondly there is Print Data which is that data which is to be transferred to paper by the PRINTING DEVICE. The Main Character Buffer 2 is the primary characte input buffer which receives both Command Data and Print Data from the computer interface. Control information from the Interface Control Unit 6 or the Data Transfer Control Unit 7 defines the. validity of the character being input from the computer interface. Information -from the Main Character Buffer 2 to both the Interface Control Unit and the Data Transfer Control Unit 7 specifies the completion of processing of that character by the microprocessor 1. Until such processing is complete input to the Main Character Buffer 2 is inhibite The Main Character Buffer 2 has the capability to accept a character from the computer interface within 400 nano seconds of receipt of the request from either the Interface Control Unit 6 or the Data Transfer Contro Unit 7. The Auxilliary Character Buffer 3 is the secondary character input buffer which is used for the receipt of PAPER MOVEMENT and PRINT CONTROL information directly from the computer interface. These are combined as single character called a Qualifier, Control informatio from the Interface Control Unit 6 determines the validit ' of such a transfer reαuest. The Data Transfer Control /,, W Unit 7 inhibits the Auxilliary Character Buffer 3 during Print Data transfer. This buffer is required because the time necessary ^ for processing the Command Data accepted by the Main Character Buffer 2 may exceed the minimum time imposed by the protocol of the 1900 INTERFACE. The protocol allows the completion of both Command Data processing from the Main Character Buffer 2 and Qualifier processing from the Auxilliary Character Buffer 3 before "any data transfers are initiated. With the exception of 'DISCONNECT' the Command Data transfers are also inhibited. These transfers are discussed fully below. The Auxilliary Character Buffer 3 like the Main Character Buffer 2 has the capability to accept a character from .the computer interface within 400 nano seconds of receipt of the request from the Interface Control Unit 6. The Status Buffer 4 holds all status information pertinent to the total Operational Environment of the Interface Unit and the Printer. Due to the problems associated with the fact that status information cannot be updated while it is being interrogated, the Status Buffer 4 is divided into two sub-buffers. The first sub-buffer, the Current Status Buffer 9 is used for two purposes:- (i) Interrogation by the computer interface via a Status Control Unit 8. OMPI (ii) Interrogation by the microprocessor 1 whenever the Interface Control Unit 6 updates the Current Status Buffer 9. This process is calle Status Feedback. The Status Feedback process is fully controlled by the Interface Control Unit 6. Further more it may reset certain status information when directed by the Command Recognition Unit 5 as is further described below. This is necessary because the processing time required by the microprocessor to update the Status Buffer 4 directly would exceed the timing limitations imposed by the protocol of the 1900 INTERFACE. The second sub-buff the New Status Buffer 10, is used as an intermediate transfer area. Its major purpose is to hold the latest Status as issued by the microprocessor while the Current Status Buffer 9 is under interrogation. The content of the New Status Buffer 10 is copied into the Current Status Buffer 9 only if the Current Status Buffer 9 remains unmodfied or is not under interrogation by the . 1900 INTERFACE. A change -in the status of the Current Status Buffer 9 is recorded in a Buffer Store 1 a locate in a Feed Back Path 13 to the microprocessor. Provided that no change is recorded in the Buffer Store 1 and interrogation by the computer has ceased, - indicated by the removal of the address from the address line to the Interface Control Unit 6 then transfer of informatio fro the New Status Buffer 10 to the Current Status Buffer 9 occurs. If the Current Status Buffer 9 is modified by the computer via the Command Recognition Unit 5 and the Interface Control Unit 6 while the New Status Buffer 10 is attempting to update the Current Status Buffer 9, this updating is inhibited by a lock-out mechanism in the Status Buffer Store. The lock-out also causes the updated status to be fed from the Buffer Store 13a to the microprocessor which releases lock-out and enables the microprocessor to choose between what may be conflicting requirements of the computer and microprocessor for the status to be registered. Referring to Figure 2, the mechanism whereby transfer between the•new and current status buf ers, 10 and 9 is controlled includes an AND gate 40 having inverters on both input terminals. One input terminal is connected to the line A from the Interface Control Unit β. This line has a logic '1' signal when the computer is interrogating or updating the current status buffer, i.e. when the dressing signal is present on the line from the computer to the Interface Control Unit. The other input terminal to the AND gate 40 is an output line 41 from the new status buffer which registers a logic '0* when data is present in the new status buffer for transfer. OMPI /_, WIPO ,^ -£8-,- Thus, when the computer is updating or interrogatin the current status buffer the '1 ' signal on line A cause the output of AND gate 40 to be at logic '0' irrespectiv of the signal on line 41. . Thus data transfer is inhibited during interrogation. The output terminal ' of the AND gate 40 is connected to an inverting gate 42, whose output is connected to an inverted input of a further AND gate 43 ' and back along a line 44 to the new status buffer. * The output of the AND gate 40 is only at logic '1' when data is present and there is no computer interrogation, when this happens th inverter produces a logic '0' output signal. This outpu signal indicates to the new status buffer that the new status has been used and the output on line 41 will be reset after 500 nano seconds. The other input terminal to the AN gate 43 also has an inverter and is connected to a line 45 from the status feedback buffer. A logic '1* signal is put on this line when the feed back buffer registers that the computer has updated the current status buffer. The output of the AND gate 43 is connected to an input to the Current Status Buffer 9. When the output of the inverter 42 is a logic '0' - indicating data and no computer interrogation, and the signal on line 45 is a logic l 0* indicating no computer update then a logic '1' signal is transmitted from the AND gate 43 to the Curren Status Buffer in the form of a 500 nano second pulse which constitutes a signal to transfer status. However when the Current Status Buffer has been updated by the computer a logic '1' signal occurs in line 45 thus locking the AND gate 43 to a '0' output. It will be appreciated that when the computer ceases to interrogate the ' ' on line 45 remains even though the output from the inverter 42 is a logic- '0' when data is available. This causes that data to be lost since the signal on 'line 44 will now be sent to reset. In this way the computer is given priority over the Current Status Buffer so that other status directives are now removed. When the Status Feedback Buffer 13a communicates the new status information to the microprocessor the signal on line 45 is removed thereby removing the lock¬ out condition. Status information from the Current Status Buffer to the Command Recognition Unit and Interface Control Unit can inhibit relevant operations within these units. The Command Recognition Unit 5 performs six functions:- (1) Recognises and validates Commands and Qualifiers from the computer interface. (ii) Informs the Main Character Buffer 2 of the availability of the valid WRITE COMMAND to be transferred at the discretion of the Interface Control Unit 6. (iii) Informs the Auxilliary Character Buffer 3 that an available Qualifier is not invalid. The validity of the Qualifier relative to the operational environment can only be determined by the microprocessor. (iv) Informs the Interface Control Unit 6 of the availability and type of valid Command Data and this includes a DISCONNECT Command. (v) Informs both the Data Transfer Control Unit 7 and the Interface Control Unit 6 that the final character of a line of Print Data is available for transfer. (vi) Informs the Current Status Buffer 9 that status information may be updated under the control of the Interface Control Unit 6. The Command Recognition Unit 5 operates under the control of the Interface Control Unit 6. .The Data Transfer Control Unit 7 may, however, override the Interface Control Unit 6 by inhibiting the Command Recognition Unit 5 during Print Data Transfer described below. The Current Status Buffer 9 inhibits the Command Recognition Unit 5 whenever either the previous transfer is complete but remains unprinted or the PRINTING DEVICE is inoperable. O WI The Interface Control Unit 6 contains the main hardware intelligence of the units simulating the Printer interface and as such has overriding control over all other functions in this part of the unit. The Control Unit 6 is responsible for the resolution of the disparity in operational requirement between the 1900 interface protocol and the hardware comprising the Printer interface. Its specific functions are discussed in detail below:- (i) Receipt of Information from the computer interface via an Address Line 11. This alerts the Interface Control Unit 6 to the presence of information from the computer. The Interface Control Unit passes this information in turn to the Status Control Unit 8. (ii) Interrogation of the Command Recognition Unit 5, the Current Status Buffer and the Data Transfer Control Unit 7 to determine the operational requirements of the available data. (iii) If a Command or Qualifier is detected by the Command Recognition Unit 5, whether valid or otherwise, the Interface Control Unit 6 informs the Status Control Unit 8 to transmit a suitable status from the Status Buffer 4 to the 1900 interface. OMPI , WIPO - (iv) In the case of a valid WRITE COMMAND the Interface Control Unit β informs the Main Character Buffer 2 of the presence of valid Command Data. Invalid Commands are ignored. (v) In the case of a valid Qualifier the - Interface Control Unit in orms the Auxilliary Character Buffer 3 of the presence of a valid Qualifier, only if the previous Command Data transfer was an acceptable WRITE COMMAND input to the Main Character Buffer 2. Invalid Qualifiers are ignored although the presence of a previously accepted WRITE COMMAND is still maintained, (vi) In the case of a Operational Status Request no further action is required. This is also true in the case of a valid DISCONNECT COMMAND. (vii) In the case where the Data Transfer Control Unit 7 indicates the requirement for Print Data transfer to the Main Character Buffer 2 the Interface Control Unit informs the Data Transfer Control Unit 7 of a pending transfer, (viii) The 1900 Interface upon receipt of an acceptabl response from the Status Control Unit 8, issues a request for either Command Data transfer or Print Data transfer. The request is sent via a Strobe Line 12 from the computer to the Interface Control Unit 6. (ix) In the case of a valid WRITE COMAND the Interface Control Unit directs the Main Character Buffer 2 to accept the Command Data. At the same time the Interface Control Unit directs the Status Buffer to reset the appropriate status conditions. (x) In the case of a valid Qualifier the Interface Control Unit directs the Auxilliary Character Buffer 3 to accept the Qualifier. In addition, if the Command Recognition Unit indicates that this is the last character (no print data transfer is required in this context) the appropriate status conditions are reset in the Status Buffer 4. (xi) In the case of. an Operational Status request the only action is the resetting of the appropriate status conditions in the Status Buffer 4. This is also true in the case of a valid DISCONNECT COMMAND. The microprocessor 1 detects the acceptance of a DISCONNECT COMMAND via the change in Status recorded in the Current Buffer 9. As previously described this change is regis¬ tered in the Buffer Store 13a in the Feedback Line 13 and is transmitted automatically to the microprocessor during the lock-out process. ' KEATt OMPI WIPO The appropriate part of the OPERATIONAL STATUS is only reset-by a hardware condition initiated by the acceptance of a valid DISCONNECT COMMAND and thus the microprocessor is informed and the status changed by hardware only so that the timing constraints of the 1900 Interface can be accommodated, (xii) In the case of a- Print Data transfer the Interface Control Unit 6 directs the Main Character Buffer 2 to accept the print character. If the data character has been recognised as the last to be transferred then the Interface Control Unit directs the Status Buffer 4 to reset the appropriate status conditions.. Throughout that part of the Operation comprising functions (i) to (vii) above the total response time of the Printer Interface does not exceed 750 nano seconds. This conforms to the protocol requirements of the 1900 Interface. The function of the Data Transfer Control Unit 7 is the co-ordination of the actual Print Data transfers within the control of the Interface Control Unit 6. The Data Transfer Control Unit 7 performs no relevant function until it is informed by the microprocessor 1 that Print Data transfers are required. The functions performed during this period are as follows:- (i) The request to the 1900 INTERFACE for Print Data transfer. • (ii) The request to the Interface Control Unit 6 for Print Data transfer, (iii) The request to the Main Character Buffer 2 for Print Data transfer, (iv) The inhibition of all requests to the Auxilliary Character Buffer 3. (v) The inhibition of the Command Recognition Unit 5 in order to simulate the rejection of all WRITE and DISCONNECT COMMANDS, (vi). The acceptance by the Interface Control Unit 6 of information relating to the servicing of any Print Data transfer request. Receipt of this information causes the Data Transfer Control Unit 7 to temporarily withdraw the request to the 1900 Interface. -The Print Data transfer request to the 1900 Interface is not reset until the Main Character Buffer 2 informs the Data Transfer Control Unit 7 that the micro¬ processor has completed processing of the previous Print Data character. (vii) The Acceptance from the Command Recognition Unit 5 of information specifying that the current Print Data character is the last transfer required for the print line. The Dat Transfer Control Unit 7 permanently withdraws the request to "the 1900 Interface. The reques is reset only by specific instruction from the microprocessor 1 as discussed below. . The Data Transfer Control Unit 7 has the capability of withdrawing the Print Data transfer request to the 1900 Interface within 20 nano seconds of the receipt of the information relating to the servicing of the request by the Interface Control Unit 6, and its subsequent transfer to the Data Transfer Control Unit 7. This time delay is suf iciently short to be termed 'immediate'. The Status Control Unit 8 co-ordinates the various Status Conditions which are sent to the 1900 Interface under the control of the Interface Control Unit 6. The Unit 8 is in effect a switching system which selects the appropriate status information from the Status Buffe and channels it to the computer. The precise status information transferred is controlled by the Interface Control Unit 6 as previously described. An additional capability of the Status Control Unit is the co-ordination of an Interrupt Line 14 to the O 1900 Interface. The Interrupt Line 14 is activated under independent control of the Status Control Unit 8. This occurs only when the operational environment, in conjunction with the current status, demands an interrupt request to be sent to the 19OO Interface in order to satisfy the protocol requirements. At any point where the Status Control Unit 8 receives information from the Interface Control Unit 6 relating to the servicing of any function of the PRINTER INTERFACE, -the Status Control Unit withdraws the interrupt request from the 1900 Interface. The interrupt request is, however, reinstated by the Status Control ' .Unit 8 provided that the circumstances which gave rise to the original interrupt have not been adequately handled during the service period. The Status Control Unit has the capability of with¬ drawing the interrupt request to the 1900 Interface within 20 nano seconds of the receipt of the information relating to the servicing of the request by the Interface Control Unit and its subsequent transfer to the Status Control Unit. This time delay is again sufficiently short to be termed 'immediate'. The Blocks illustrated in Figure 1 which constitute the hardware content of the COMPUTER INTERFACE OMPI WIPO are as follows:- a Printer Data Buffer 20, a Strobe Control Unit 21, an Ack Control -Unit 22, a Printer Status Buffer 23, a Status Sense Unit 24. The Printer Data Buffer 20 is an intermediate Buffe between the microprocessor- 1 and the PARALLEL interface. The microprocessor writes any data to the Printer Data -Buffer 20 from whence it is placed on a DATA BUS 25 to the PARALLEL interface. At this point the Printer Data Buffer 20 indicates to the Strobe Control Unit 21 that the data is available. .The Strobe Control Unit is used to construct a correctly timed strobe via a Printer Strobe Line 26 to the PARALLEL interface. This is actioned by the indicat of available data from the Printer Data Buffer 20. The timing sequence consists of a delay of at least 1.0 microseconds followed by a strobe of at least 1.0 microseconds. The Strobe Control Unit 21 may be inhibited from operating by a strobe lock-out signal from the Ack Control Unit 22 as will be described. The function of the Ack Control Unit 22 is to infor the microporcessor that the data it has transferred to the Printer Data Buffer 20 has been fully utilised by th PARALLEL interface. The Ack Control Unit 22 realises this condition in one of two ways:- (i) The PARALLEL interface indicates via an Ack Line 27 that it has utilised the current data. (ii) The ENVIORNMENTAL STATUS from the PRINTING DEVICE indicates that the device is inoperable. In additionthe Ack Control Unit 22 interrogates the ENVIRONMENTAL STATUS to determine the operational capa¬ bility of the PRINTING DEVICE. If the PRINTING DEVICE is not operational any further strobes are inhibited by a strobe lock-out signal along the line 29 and the micro¬ processor is informed via a strobe lock-out status line 30 if a transfer via the Printer Data Buffer is attempted. The exception is the circumstance where the microprocessor decides that a transfer to the PARALLEL INTERFACE is required even if the PRINTING DEVICE is inoperable. To achieve this the microprocessor directs the Ack Control Unit 22, via a printer strobe force line 3 to withdraw any strobe lock-out that may exist. In this manner data sent from the computer is completed before the hardcopy output device is rendered finally inoperative. That is to say the microprocessor forces the output device to become operative and print, say if the operator switches if off line, whereas if the output device runs 0- out of paper, say, the microprocessor cannot force the output device to be operative and data may be lost. The Printer Status Buffer 23 accepts the ENVIRONMENTAL STATUS from the PARALLEL interface on an indication ' from the Status Sense Unit 24. The ENVIRONMENTAL STATUS is transferred to the microprocessor as required. The Printer Status Buffer 23 inhibits the Status Sense Unit 24 during the period it holds an ENVIRONMENTAL STATUS which has not been transferred to th microprocessor. The Status Sense Unit 24 detects an adverse ENVIRONMENTAL STATUS condition from the printer interface This indication is passed to the Printer Status Buffer 23 The Status Sense Unit 24 may be inhibited by the Printer Status Buffer 23 as is discussed above. The microprocessor 1 is the centre of intelligence for the whole unit and in this embodiment is a basic INTEL 8748 chip. It is programmed in a fully interrupt driven fashion to provide three general functions:- (i) The Data Path from the 1900 Interface to the PARALLEL Interface. (ii) The Status Path from the PARALLEL Interface to the 1900 Interface. (iϋ) Self Test Routines. O The Data Path from the 1900 Interface to the PARALLEL Interface passes first through the PRINTER INTERFACE and after processing within the microprocessor it then passes to the COMPUTER INTERFACE. The following description is of the Data Path of a single print line and also of a DISCONNECT COMMAND through the microprocessor. The basic ' sequence of events for the processing of a single print line of data is as follows:- (i) A WRITE COMMAND from the PRINTER INTERFACE is accepted and recognised by the microprocessor, (ii) . A Qualifier is then accepted and recognised by the microprocessor, (iii) Due to the Interrupt Driven mode of operation of the microprocessor the following events occur in parallel: (a) Data Transfer to the PRINTER INTERFACE is requested by the microprocessor. A line of data is then transferred into the internal storage of the microprocessor. (b) The Qualifier is interpreted and the PARALLEL Interface directed to carry out the appropriate operation. (iv) The microprocessor translates and sends the internally stored line of data to the PARALLEL Interface for printing. This transfer may be locked out as aforesaid due to changes in the - TREΛ - OMPI Λ. WIPO * < 42- ENVIRONMENTAL STATUS. The microprocessor is however notified via the line 30. Appropriate action is taken within the status path upon interrogation of the ENVIRONMENTAL STATUS. (v) The microprocessor adjusts the OPERATIONAL STATUS and the WRITE STATUS as appropriate during the events (i) and (iv) above. If the hardware determines a timing conflict within the Status Buffer 4 then the microprocessor is informed via the transfer lock-out status line and the updating of the appropriate status is re-evaluated upon interrogation of the Current Status Buffer via status feedback line 13 and the buffer 1 a. If the Qualifier specifies 'No Printing' then the operation (iii (a) and (iv) are not actioned. The basic sequence of events actioned during the processing of a DISCONNECT COMMAND is as follows:- (i) The DISCONNECT COMMAND from the PRINTER INTERFACE is accepted and recognised by the microprocessor, (ii) The microprocessor sends a 'Deselect' Command to the PARALLEL Interface. The Status Path from the PARALLEL Interface to the 1900 Interface passes first through the COMPUTER INTERFACE under the control of the microprocessor. After processing within the microprocessor it then passes to the 1900 Interface. The overall sequence of events for Status processing is as follows:- (i) The microprocessor accepts an ElVIRONMENTAL STATUS from the.PARALLEL Interface. (ii) The microprocessor interprets the ENVIRONMENTAL STATUS and adjusts the processing of the Data Path accordingly. (iii) The WRITE STATUS and the OPERATIONAL STATUS of the PRINTER INTERFACE are reset to reflect the current condition of the PRINTING DEVICE. Full Software Driven hardware test routines are provided by the microprocessor. These routines have the following capabilities:- (i) Testing of the Main Data Paths within the microprocessor. (ii) Testing of the Main Data Paths within the PRINTER INTERFACE. (iii) Testing of most Functional Blocks within the PRINTER INTERFACE. (iv) The Driving of the PARALLEL Interface with Standard Test Patterns. This provides test data for both the PRINTING DEVICE and the •COMPUTER INTERFACE to PARALLEL Interface link. ^ ΈE I OMPI There is a man-machine interface which needs to be actioned in order to activate the Self Test Routines. Several hardware links need to be manually changed for some Self Test facilities. A set of eight switches and eight associated LED's are provided on the unit in order to allow the operator to select the required tests and observe the results. • The full listings for the programming of the microprocessor have been given previously..

Claims: CLA3JMS 1. An interface unit or connection between a com¬ puter of the kind specified and a hardcopy device of the kind specified, the interface unit including a microprocessor and first and second hardware units connected between the micro¬ processor and respectively, the computer and the hardcopy out¬ put device, characterised in that:- the * irst hardware unit includes a status buffer store for storing data indicative o the actual or proposed operational status of the hardcopy output device, the status * buffer store having first and second parts, the first part being interrogatable by both the microprocessor and the computer but updatable directly only by the computer, and the second part being updatable by- the microprocessor, the second part of the status buffer store being operative to transfer the status in information stored therein to the first part except when it is prevented from so doing by a disenabling signal produced by the first hardware unit when the first part of the status buffer unit is interrogated by the computer; the first hardware unit further including a status change detection means operative to detect that the first part of the status buffer store has. been updated by the computer and to transmit to the microprocessor the new status information stored in the first part of the status buffer store. OMPI /_, WIPO _ 2. An interface unit for- connection between a computer of the kind specified and a hardcopy output device of the kind specified, the interface unit including a micro¬ processor and first and second hardware units, connected between the microprocessor and respectively the computer and the hardcopy output device, characterised in that:- the first hardware unit comprises:- bu£fer storage means connected to receive said instructional and command data from the computer, recognition means connected to receive said instructional and command data and operative to distinguish between types of command; a control unit for controlling the timing of th activities of the components in the first hardware unit and connected to said address line and strobe line from the com¬ puter; a data trans er unit controlling the ransfer o data from the computerj a status buffer store for storing data indicati of the actual or proposed status of the output device, the status buffer having first and second parts, the first part being interrogatable by both the microprocessor and computer but updatable directly only by the computer and the second part being updatable by the microprocessor, the second part of the status buffer store being operative to transfer the status information stored therein to the first part provided - that it is not prevented from so doing by a disenabling signal produced by the first hardware unit, this disenabling signal being produced when information addressing the output device is transmitted along said address line from the computer indic¬ ating that said first part is being interrogated by the com¬ puter; status change detection means operative to register that the first part of status buffer store has been updated and to transmit to the microprocessor the new status information stored in the first part of the status buffer; the second hardware unit of the interface unit including:- a printer data buffer for storing data between the microprocessor and hardcopy output device for transmission along said print data path; a timing control unit for supplying a timing s signal along said strobe path indicating the presence of data in the printer data buffer; an acknowledgement control unit operative to - REACT- OMPI_ receive signals from said hardcopy output device along said acknowledgement path and to signal the printer data buffer in response; a printer status buffer operative to receive information as to the current capability of the hardcopy outpu device along said status path. 3. An interface unit as claimed in claim 2 char¬ acterised in that detection of a change in the status inform¬ ation held in the first part of the status buffer caused by updating by the computer results in a signal to the status buffer preventing -transfer of status information from the second part, the transfer facility being re-enabled by the transmission of the new status information to the micropro¬ cessor. 4, An interface unit as claimed in claim 3 charac¬ terised in that a signal to the first part of the status buffe to transfer data from the second part, is produced by first gating means when both a signal from second gating means occur and said means for detecting a change in the status informati in the first part of the status buffer does not produce a sign indicating that there has been a change, the signal from the second gating means occurring when both a signal from the second part of the status buffer occurs indicating data for transfer and said disenabling signal indicating that interro¬ gation is occurring does not occur; said signal from the second gating means also being fed to the second part of the status buffer to remove that said signal from the second part of the data buffer which indicates that data is available. 5. An interface unit as claimed in any one of claims 2 to 4 characterised in that, an instruction from the computer for the hardcopy output device to be put in a state of logical disconnection from the computer, is recognised in said recognition means which then updates said first part of the status buffer store; the presence of this instruction being solely communicated to the microprocessor by means of said trans¬ mission of the new status information stored in the first part of the status buffer. 6. An interface unit as claimed in any one of claims 2 to 5 characterised in that:- the second hardware unit includes means for locking the timing control unit to prevent " -further transmission of said timing signals; _ OMPI the acknowledgement control unit is connected to-receive the signals from said hardcopy output device along said status path and is operative to transmit a signal to the means for locking the timing control unit to effect said locking the timing control unit to effect said locking when th hard copy output device is rendered inoperative and data is presented to the printer data buffer; the acknowledgement control unit further being arranged to transmit, a signal to the microprocessor indicating that the signal to the means for locking the timing control unit has been transmitted. 7. An interface unit as claimed in claim 6 charac¬ terised in that said signal from the acknowledgement control unit is transmitted to the means for locking the timing contro unit whenever the hardcopy output device is rendered inoperati 8. An interface control unit as claimed in claim 6 or claim 7 characterised in that:- the microprocessor is connected to the acknow¬ ledgement control unit such that a signal from the micropro¬ cessor can inhibit the acknowledgement control unit so as to remove said signal from the timing control unit thereby enabli timing signals to be sent to the hardcopy output device indi¬ cates that it is inoperable. ^Zn

Inventors: NEAVE T
Applicants: MICRONOLOGY LTD, NEAVE T
Application year: 1980
Main classification: G06F13
IPC codes: G06F3, G06F13