METHOD OF PRODUCING A SEMICONDUCTOR DEVICE

Abstract: In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermaloxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal exidation.

Description: METHOD OF PRODUCING A SEMICONDUCTOR DEVICE¯ BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for producing a semiconductor device comprising at least one semiconductor element and an isolation region which are formed in an epitaxial layer formed on a semiconductor substrate. More particulary, the present invention relates to a method for forming both a silicon oxide layer which lies on and around the semiconductor element, and an isolation region which lies around the semiconductor element and has an opposite conductivity type to that of the epitaxial layer. Description of the Prior Art In a case where a semiconductor integrated circuit is produced by forming semiconductor elements, such as transistors, and passive elements, such as diffused transistors, in an epitaxial layer formed on a silicon semiconductor substrate, generally, after a silicon oxide layer is formed as a protecting layer on the surface of the integrated circuit, connecting lines of a conductor, such as aluminum, are formed on the silicon oxide layer. In this case, in order to decrease the parasitic capacity between the epitaxial layer and the aluminum connecting lines, the above-mentioned silicon oxide layer is made thick. Furthermore, in order to prevent a so-called parasitic effect from occuring between the semiconductor elements, an isolation region between the semiconductor elements is formed by introducing impurities having an opposite conductivity type to that of the epitaxial layer into a predetermined portion of the epitaxial layer. A semiconductor element (e.g. an npn-type bipolar transistor) of an integrated circuit is illustrated in the schematic sectional view of Fig. 1. Such bipolar transistor is illustrated in Fig. 2 of United States Patent No. 3,911,471. In Fig. 1, reference numerals 1, 2, 2' and 3 indicate a p-type silicon substrate, an n-type silicon epitaxial layer, an isolated region and an n-type buried layer, respectively. The electrical resistance of the epitaxial layer 2 is high and, consequently, the breakdown voltage between the collector and the base of the bipolar transistor is high. The buried layer 3 can reduce the series resistance of the collector. Reference numerals 4, 5, 6 and 7 indicate a p-type base region, an n-type emitter region, an n-type collector connecting region and an isolation region, respectively. These regions 4, 5, 6 and 7 are formed in the epitaxial layer 2. Since the isolation region 7 has the opposite conductivity type to that of the epitaxial layer and surrounds the isolated region 2', it is possible to electrically isolate the bipolar transistor from other transistors and passive elements (not shown). Reference numerals 8, 8A through 8C, 9, 10 and 11 indicate a silicon oxide layer, thick portions of the silicon oxide layer, a colllector electrode, a base electrode and an emitter electrode, respectively. The thick portions 8A, 8B and 8C of the silicon oxide layer 8 decrease the parasitic capacitance between the epitaxial layer and the connecting lines of the electrodes 9, 10 and 11. According to Fig. 1 the thick portions of the silicon oxide layer are separated, but the thick portions combine at a place not shown in Fig. 1. The bipolar transistor illustrated in Fig. 1 is produced in the following manner. Referring to Fig. 2, the starting material is a p-type silicon semiconductor substrate 1. N-type impurities are introduced into a predetermined portion of the silicon substrate 1 by ion-implantation or thermal diffusion to form a buried layer 3. An n-type silicon epitaxial layer 2 is formed on the silicon substrate 1 by epitaxial growth and, at the same time, some impurities diffuse out of the buried layer 3 into the epitaxial layer 2, so that the buried layer 3 expands up to a broken line in Fig. 2. A silicon nitride layer serving as an anti-oxidation masking layer is formed on the epitaxial layer 2 by chemical vapor deposition and, then, is selectively removed by photoetching, so that portions 12A, 12B and 12C of the silicon nitride layer remain, as illustrated in Fig. 2. If desired, a thin oxide layer may be provided under the silicon nitride layer. Next, the semiconductor body comprising the silicon substrate 1 and the silicon epitaxial layer 2 is thermally oxidized at 10000C for approximately 2 hours. Since the silicon nitride layer portions 12A, 12B and 12C serve as an anti-oxidation mask during the oxidation period, a silicon dioxide (SiO2) layer 13 having a thickness of approximately 700 nm is formed, as illustrated in Fig. 3. The formed silicon dioxide layer 13 is removed by etching to expose a portion of the epitaxial layer 2. Then, the semiconductor body is also thermally oxidized at 10000C for approximately 8 hours to form a thick silicon dioxid layer 14 having a thickness of approximately 1.4 Pm, as illustrated in Fig. 4. Next, a photo resist layer (not shown) is applied on the entire surface and, then, a portion of the resist layer which lies on the silicon nitride layer portion 12A is removed. P-type impurities are introduced through the silicon nitride layer portion 12A into the epitaxial layer 2 by ion-implantation to form a high concentration region 15 of p-type impurities, as illustrated in Fig. 5. After the applied resist layer is removed, another photo resist layer is applied onto the entire surface, and then, a portion of the resist layer which lies on the silicon nitride layer portion 12B is removed. N-type impurities are introduced through the silicon nitride layer portion 12B into a portion of the epitaxial layer 2 by ion-implantation to form a high concentration region 16 of n-type impurities, as illustrated in Fig. 5. The obtained semiconductor body is heated at 11000C for approximately 1 hour, whereby the p-type impurities in the high concentration regions 15 diffuse into the epitaxial layer 2 and arrive at the silicon substrate 1 to form an isolation region 7 for isolating semiconductor elements from each other and, at the same time, the n-type impurities in the high concentration region 16 diffuse and arrive at the buried layer 3 to form a collector connecting region 6, as illustrated in Fig. 6. Next, the remaining silicon nitride layer portions 12A, 12B and 12C are removed to expose portions of the epitaxial layer 2. The obtained semiconductor body is thermally oxidized at 9000C for approximately 30 minutes to form a thin silicon dioxide layer 8, having a thickness of approximatelly 50 nm, on the surfaces of the exposed portions the epitaxial layer 2 including the isolation region 7 and the collector connecting region 6, as illustrated in Fig. 7. A patterned photo resist layer 17 is formed on the thin and thick silicon dioxide layers 8 and 14, as illustrated in Fig. 7. P-type impurities are introduced through a portion of the thin silicon dioxide layer 8 into a portion of the isolated region 2' of the epitaxial layer 2 by ion-implantation to form a high concentration region 18 of the p-type impurities. The obtained semiconductor body is annealed by heating at l0000C for approximately 10 minutes, whereby the impurities in the high concentration region 18 diffuse to a predetermined depth in the epitaxial layer 2, so that a base region 5 is formed, as illustrated in Fig. 8. Then, N-type impurities are introduced into a portion of the base region 5 by ion-implantation subsequent to etching of a portion of the thin silicon dioxide layer lying on the base region 5 by photoetching. An annealing treatment is carried out at 10000C for approximately 20 minutes to form an emitter region 4, as illustrated in Fig. 1. Openings for the collector electrode 9 and for the base electrode 11 are formed in the thin silicon dioxide layer above the collector connecting region 6 and the base region 5, respectively, by photoetching, as illustrated in Fig. 1. Finally, a conductor layer of aluminum is formed on the entire surface by vapour deposition and, then, is selectively removed by photoetching to form the collector, base and emitter electrodes 9, 11 and 10, respectively. In the above described manner, an npn-type bipolar transistor isolated from other elements is produced, as illustrated in Fig. 1. However, when the thick silicon dioxide layer 14 (Fig. 4) is formed prior to the introduction of impurities into the epitaxial layer 2, a portion of the epitaxial layer lying under the silicon nitride layer portions 12A, 12B and 12C is oxidized into silicon dioxide. Namely, a portion of the thick silicon dioxide layer 14 enters under the silicon nitride layer portions to form a so-called bird's beak, as illustrated in Fig. 4. Since the bird's beak of silicon dioxide prevents the impurities from entering into the epitaxial layer 2, for example, in order to form the isolation region 7 having a width of 1 cm, it is necessary to make the width of the silicon nitride layer portion 12A approximately 3 Vm. As the width of the silicon nitride layer portion 12A increases, on the one hand, its area increases, and on the other hand, the area for semiconductor elements and passive elements of the integrated circuit decreases. Therefore, it is difficult to increase the degree of integration of the semiconductor elements and the passive elements in the integrated circuit. Furthermore, according to the above-mentioned production method, the method comprises the step of forming the thick silicon dioxide layer, and the step of diffusing the impurities for forming the isolation region and the collector connecting region, namely, a heat-treatment is carried out at least two times. When the heat-treatment is repeated, the impurities in the buried layer diffuse upward in the epitaxial layer. As the result of this, the breakdown voltage between the collector and the emitter decreases. SUMMARY OF THE INVENTION It is an object of the present invention is to increase the degree of integration of semiconductor elements and passive elements in an integrated circuit over that of the prior art and to prevent the breakdown voltage between the collector and the base of a bipolar transistor from decreasing, by providing an improved method for producing a semiconductor device comprising at least one semiconductor element and an isolation region which are formed in an epitaxial layer formed on a semiconductor substrate. The present invention is based on recognition of the fact that, in a case where impurities are introduced into the epitaxial layer prior to the step of forming a thick oxide layer by thermal oxidation, an integrated circuit design (i.e. the shapes and dimensions of the semiconductor elements, the passive elements and the isolation region) can be determined without taking a bird's beak of the thick oxide layer into consideration, and that a formation step of the thick oxide layer and a formation step of the isolation region can be carried out in one heat-treatment. According to the present invention, a method of producing a semiconductor device comprising at least one semiconductor element and an isolation region, which are formed in an epitaxial layer formed on a semiconductor substrate having a buried layer, comprises the steps of: forming a mask pattern for preventing impurities from entering the epitaxial layer; introducing the impurities into a predetermined portion of the epitaxial layer; forming a patterned anti-oxidation masking layer for selective thermal-oxidation of the epitaxial layer, and; thermal-oxidizing the epitaxial layer to form a thick oxide layer, at the same time the introduced impurities are diffused into the epitaxial layer to form the isolation region. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic sectional view of a bipolar transistor of an integrated circuit; Figs. 2 through 8 are schematic sectional views of the bipolar transtor of Fig. 1 in intermediate stages of production in accordance with prior art techniques; Figs. 9 through 13 are schematic sectional views of a bipolar transistor in intermediate stages of production in accordance with an embodiment A of the present invention; Figs. 14 and 15 are schematic sectional views of a bipolar transistor in intermediate stages of production in accordance with an embodiment B of the present invention; Figs. 16 and 17 are schematic sectional views of a bipolar transistor in intermediate stages of production in accordance with the embodiment C of the present invention; ; Figs. 18 and 19 are schematic sectional views of a bipolar transistor in intermediate stages of production in accordance with an embodiment D of the present invention; Figs. 20 through 22 are schematic sectional views of a bipolar transistor in intermediate stages of production in accordance with combinations of the embodiments; Fig. 23 is a schematic sectional view of a bipolar transistor in an intermediate stage of production in accordance with a variant combination of the embodiments; Figs. 24 through 31 are schematic sectional views of a bipolar transistor in intermediate stages of production in accordance with an embodiment E; Figs. 32 and 33 are schematic sectional views of a bipolar transistor in intermediate stages of production in accordance with an embodiment F; ; Figs. 34 and 35 are schematic sectional views of a bipolar transistor in intermediate stages of production in accordance with an embodiment G; Figs. 36 through 42 are schematic sectional views of a bipolar transistor in accordance with an embodiment H, and; Fig. 43 is a schematic sectional view of a bipolar transistor in an intermediate stage of production in accordance with an embodiment I. DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a first preferable embodiment of a method of producing a semiconductor device comprising at least one semiconductor element and an isolation region, which are formed in an epitaxial layer formed on a semiconductor substrate having a buried layer, comprises the steps of: : forming an anti-oxidation masking layer on the epitaxial layer; selectively removing the masking layer by photoetching to expose portions of the epitaxial layer; thermal-oxidizing the exposed portions of the epitaxial layer to form a thin oxide layer; forming a patterned resist layer; introducing impurities into a predetermined portion of the epitaxial layer which is covered by the masking layer and is not under the resist layer; removing the patterned resist layer, and; thermal-oxidizing the epitaxial layer by using the remaining anti-oxidation masking layer as a mask to form a thick oxide layer. The above-mentioned first embodiment will now be explained in detail by the following embodiments A through D with reference to the drawings. Embodiment A Referring to Fig. 9, the starting material is a p-type silicon semiconductor substrate 21. N-type impurities (e.g. antimony) are introduced into a predermined portion of the silicon substrate 21 to form an n -type buried layer 22. An n-type silicon epitaxial layer 23, having a high resistance, is formed on the silicon substrate 21 and, at the same time, some n-type impurities diffuse out of the buried layer 22 into the epitaxial layer 23, so that the buried layer 22 expands up to a broken line in Fig. 9. A silicon nitride layer having a thickness of approximately 50 nm and serving as an anti-oxidation masking layer is formed on the epitaxial layer 23 by chemical vapor deposition, and then, is selectively removed by photoetching so that portions 24A, 24B and 24C of the silicon nitride layer remain, as illustrated in Fig. 9. Next, the semiconductor body comprising the silicon substrate 21 and the epitaxial layer 23 is heated at 10000C, for appriximately 2 hours, in an oxidizing atmosphere. As the result, the portion of the epitaxial layer 23 which is not covered by the silicon nitride layer portions 24A, 24B and 24C is oxidized to form a thin silicon dioxide layer 25 having a thickness of approximately 700 nm, as illustrated in Fig. 10. A photo resist layer 26 is applied on the entire surfaces of the silicon nitride layer portions 24A, 24B and 24C, and the thin silicon dioxide layer 25, and then, is selectively etched to remove a portion of it which lies on the silicon nitride layer portion 24A, as illustrated in Fig. 11. P-type impurities (e.g. boron) are introduced through the silicon nitride layer portion 24A into the epitaxial layer 23 by ion-implantation to form a high concentration region 27 (Fig. 11) of p-type impurities. After the photo resist layer 26 is removed, another photo resist layer 28 is applied onto the entire surfaces of the layer portions 24A, 24B and 24C, and the layer 25, and then, is selectively etched to remove a portion of it which lies on the silicon nitride layer portion 24B, as illustrated in Fig. 12. N-type impurities (e.g. phosphorus) are introduced through the silicon nitride layer 24B into the epitaxial layer 23 by ion-implantation to form a high concentration region 29 (Fig. 12) of p-type impurities. The photo resist layer 28 is then removed. Next, the obtained semiconductor body is heated at l0000C,#for approximately 6 hours, in the oxidizing atmosphere. As a result of the heaOt-treatment, i.e. a thermal oxidation treatment, the thickness of the thin silicon dioxide layer 25 increases to form a thick silicon dioxide layer 30 having a thickness of approximately 1.4 pm, the p-type impurities in the high concentration region 27 diffuse into the epitaxial layer 23 and arrive at the silicon substrate 21 to form an isolation region 31 and, simultaneously, the n-type impurities in the high concentration region 29 diffuse and arrive at the buried layer 22 to form a collector connecting region 32, as illustrated in Fig. 13. Thus, since the formation of the thick silicon dioxide layer, the isolation region and the collector connecting region are simultaneously carried out, the number of heattreatments is decreased as compared with the above-mentioned prior art method of producing a semiconductor device. Therefore, the decrease in the breakdown voltage between the collector and the base caused by diffusing the n-type impurities out of the buried layer into the epitaxial layer is smaller than in the prior art. In order to complete a bipolar transistor, a base region, an emitter region, a collector electrode, a base electrode, an emitter electrode and a required thin silicon dioxide layer are formed in the same manner as in the above -mentioned prior art method. Embodiment B Prior to the step of forming the thin silicon dioxide layer 25 (Fig. 10) of the embodiment A of the present invention, a portion of the epitaxial layer 23 can be etched by an etchant (e.g. HF:HNO3:AgNO3 =5:40:1), as illustrated in Fig. 14. In this case, the silicon nitride layer portions 24A, 24B and 24C serve as a mask, and the etching depth is approximately 300 nm. Furthermore, the etching of the epitaxial layer can be carried out by a plasma etching process. In this case, a photo resist layer (not shown) is applied onto the silicon nitride layer subsequent to formation of the silicon nitride layer and, then, is exposed and developed. Since ali of the silicon nitride layer, except for its portions 24A, 24B and 24C, is exposed, the exposed portion of the silicon nitride layer and the portion of the epitaxial layer thereunder can be etched by plasma. Then, the obtained semiconductor body is treated in the same manner as in method of the embodiment A to obtain the semiconductor body in the state illustrated in Fig. 15. The difference between the levels of the surface of the thick silicon dioxide layer 30 (Fig. 15) and the surface of the epitaxial layer 23 (Fig. 15) is smaller as compared with that of the semiconductor body in the state illustrated in Fig. 13, in case of the embodiment A. Embodiment C Subsequent to the step of forming the photo resist layer 26 (Fig. 11) and prior to the step of introducing the impurities of the embodiment A, the silicon nitride layer portion 24A can be etched by as illustrated in Fig. 16. Therefore, the p-type impurities can be directly introduced into an exposed portion of the epitaxial layer 23. The procedure for producing a semiconductor device in this embodiment, except for the above-mentioned etching step is same as that of the embodiment A. As the result, the semiconductor body in the state illustrated in Fig. 17 is obtained. A portion of the thick silicon dioxide layer 29 is formed on the isolation region 31, whereby the parasitic capacitance between a connecting line and the isolation region can be decreased. Embodiment D Subsequent to the step of removing the photo resist 28 (Fig. 12) of the embodiment A, the thin silicon dioxide layer 25 (Fig. 12) can be etched by an aqueous solution of hydrofluoric acid, as illustrated in Fig. 18. Then, the obtained semiconductor body is heated under the same conditions as those of the heating step of the embodiment A, so that an exposed portion of the epitaxial layer 23 is oxided to form a thick silicon dioxide layer 33 having a thickness of approximately 1.4 Pm, as illustrated in Fig. 19. At the same time, the isolation region 31 and the collector connecting region 32 are formed. Since the surfaces of the epitaxial layer 23 and the thick silicon dioxide layer 33 are almost flat, it is possible to produce a planar type bipolar transistor. Furthermore, it is possible to combine the abovementioned embodiments B, C and D. For example, a combination of the embodiments B and C and a combination of the embodiments C and D can be carried out. In a case where the embodiments 3 and C are combined, subsequent to the step of forming the high concentration region 27 and prior to step of forming the photo resist layer 28 of the embodiment A, the semiconductor body in the state illustrated in Fig. 20 is obtained. As a result, after the thermal oxidation for the thick silicon dioxide layer 30 is carried out, the semiconductor body in the state illustrated in Fig. 21 is obtained. In a case where the embodiments C and D are combined, the semiconductor body in the state illustrated in Fig. 21 is also obtained via the state illustrated in Fig. 22. The above-mentioned combinations of the embodiments can further include the step of etching a portion of the epitaxial layer corresponding to the isolation region subsequent to the step of etching the silicon nitride layer portion of the embodiment C. As a result, the semiconductor body in the state illustrated in Fig. 23 is obtained. According to the present invention, a second preferable embodiment of a method of producing a semiconductor device comprising at least one semiconductor element and an isolation region which are formed in an epitaxial layer formed on a semiconductor substrate having a buried layer comprises the steps of: forming an anti-oxidation masking layer on the epitaxial layer; forming an insulating layer on the anti-oxidation masking layer; forming a patterned resist layer; introducing the impurities into the predetermined portion of the epitaxial layer which is not under the patterned resist layer; removing the patterned resist layer; making a pattern mask out of the anti-oxidation masking layer, and; selectively thermal-oxidizing the epitaxial layer to form a thick oxide layer. The above-mentioned second embodiment will now be explained in detail by the following embodiments E through J with reference to the drawings. Embodiment E Referring to Fig. 24, the starting material is a p-type silicon semiconductor substrate 41 having an n -type buried layer 42. An n-type silicon epitaxial layer 43, having a high resistance, is formed on the silicon substrate 41 and, at the same time, some n-type impurities diffuse out of the buried layer 42 into the epitaxial layer 43, so that the buried layer 42 expands up to a broken line in Fig. 24. A silicon nitride layer 44 having a thickness of approximately 50 nm and serving as an anti-oxidation masking layer is formed on the epitaxial layer 43 by chemical vapor deposition. A silicon oxide layer (i.e. an insulating layer) 45 having a thickness of approximately 500 nm is formed on the silicon nitride layer 44 by chemical vapor deposition. Furthermore, a negative photo resist layer 46 is applied onto the silicon oxide layer 45. The negative photo resist layer 46 is exposed and developed to form a patterned negative resist layer 46. Then, using the patterned negative resist layer 46 as a mask, the silicon oxide layer 45 is selectively etched by an aqueous solution of hydrofluoric acid, as illustrated in Fig. 24. Next, a positive photo resist layer 47 is applied onto the entire surfaces of the exposed portions of the silicon nitride layer 44 and the patterned negative resist layer 46. The positive resist layer 47 is exposed and developed to form an opening 48, as illustrated in Fig. 25. P-type impurities (e.g. boron) are introduced through a portion of the silicon nitride layer exposed within the opening 48 into the epitaxial layer 43 by ion-implantation to form a high concentration region 49 (Fig. 25) of p-type impurities. After the positive photo resist layer 47 is removed, another positive photo resist layer 50 is applied onto the entire surfaces of the exposed portions of the silicon nitride layer 44 and the patterned negative photo resist layer 46 and, then, is exposed and developed to form another opening 51, as illustrated in Fig. 26. N-type impurities (e.g. phosphorus) are introduced through a portion of the silicon nitride layer 44 exposed within the opening 51 into the epitaxial layer 43 by ion-implantation to form a high concentration region 52 (Fig. 26) of n-type impurities. Next, the positive photo resist layer 50 is removed but the patterned negative photo resist layer 46 remains. A metal layer 53 is formed on the entire surfaces of the exposed portion of the silicon nitride layer 44 and the remaining negative photo resist layer 46 by vapor deposition, as illustrated in Fig. 27. The metal layer 53 is made of molybdenum (Mo), chromium (Cr), platinum (Pt) or polysilicon, preferably molybdenum, and has a good corrosion resistance against an etching solution of pyro-phosphoric acid for silicon nitride or of hydrofluoric acid for silicon oxide or against plasma etching. The patterned negative photo resist layer 46 is removed by a suitable remover, and, at the same time, a portion of the metal layer 53 lying on the patterned resist layer 46 is removed, as illustrated in Fig. 28. Such removing process of a portion of the metal layer is generally a so-called lift off process. Next, using the remaining metal layer 53 as a mask, the remaining silicon oxide layer 45 is etched by a solution of hydrofluoric acid, as illustrated in Fig. 29. It is possible to carry out a lift off process which comprises the steps of: removing the negative photo resist layer 46 prior to the step of forming the possitive photo resist layer 47; forming a metal layer on the exposed portion of the silicon nitride layer 44 and the remaining silicon dioxide layer 45 subsequent to the impurity introducing step, and; removing the silicon dioxide layer 41 together with a portion of the metal layer thereon. Using also the remaining metal layer 53 as a mask, a portion of the silicon nitride layer 44 is selectively etched by a solution of pyro phosphoric acid to expose a portion of the epitaxial layer 43, as illustrated in Fig. 30. After the remaining metal layer 53 is removed by a mixed solution of nitric acid and hydrochloric acid, the obtained semiconductor body comprising the substrate 41 and the epitaxial layer 43 is heated at 1100 C, for approximately 2 hours, in an oxidizing atmosphere. As a result of the heat-treatment, i.e. a thermal oxidation treatment, the exposed portion of the epitaxial layer 43 is oxidized to form a thick silicon oxide layer 54 having a thickness of approximately 1 pm, the p-type impurities in the high concentration region 49 diffuse into the epitaxial layer 43 and arrive at the silicon substrate 41 to form an isolation region 55 and, simultaneously, the n-type impurities in the high concentration region 52 diffuse and arrive at the buried layer 42 to form a collector connecting region 56, as illustrated in Fig. 31. Thus, since the formation of the thick silicon oxide layer, the isolation region and the collector connecting region are simultaneously carried out, the number of heat -treatments is decreased as compared with the above-mentioned prior art method of producing a semiconductor device. Therefore, the decrease in the breakdown voltage between the collector and the base caused by diffusing the n-type impurities out of the buried layer into the epitaxial layer is smaller than in the prior art. In order to complete a bipolar transistor, a base region, an emitter region, a collector electrode, a base electrode, an emitter electrode and a required thin silicon oxide layer are formed in the same manner as in the abovementioned prior art method. In this embodiment, a photo etching technique (i.e. photo lithography) is used, but, an electron beam lithography, an ion beam lithography or an X-ray lithography may be used. Embodiment F Subsequent to the step of forming the opeing 48 (Fig. 25) and prior to the step of introducing the p-type impurities of the embodiment E, a portion of the silicon nitride layer 44 exposed within the opening 48 can be etched by plasma etching, as illustrated in Fig. 32. The procedure for producing a semiconductor device in this embodiment, except for the above-mentioned etching step, is the same as that of the embodiment E. As a result, the semiconductor body in the state illustrated in Fig. 33 is obtained. The thick silicon oxide layer 54 is formed on the isolation region 55, whereby the parasitic capacity between a connecting line and the isolation region can be decreased. Embodiment G Subsequent to the step of etching the portion of the silicon nitride layer 44 (refer to Fig. 30) of the embodiment E, a portion of the epitaxial layer 43 can be etched by plasma etching, as illustrated in Fig. 34. Then, the metal layer 53 is etched by the above-mentioned etchant. The obtained semiconductor body is treated in the same conditions as those of the heat-treating step of the embodiment E to obtain the semiconductor body in the state illustrated in Fig. 35. The difference between the levels of the surface of the thick silicon oxide layer 54 (Fig. 35) and the surface of the epitaxial layer 43 (Fig. 35) is smaller as compared with that of the semiconductor body in the state illustrated in Fig. 31, in the case of the embodiment E. Furthermore, it is possible to combine the above -menti#oned embodiments F and G, as the result, the semiconductor body which has a similar structure to that illustra-ted in Fig. 21 can be obtained. The combination of the embodiments F and G can further include the step of etching a portion of the epitaxial layer corresponding to the isolation region prior to the step of introducting p-type impurities, as the result, the semiconductor body which has a similar structure to that illustrated in Fig. 23 can be obtained. Embodiment H Referring to Fig. 36, the starting material is a p-type silicon semiconductor substrate 61 having an n -type buried layer 62. A n-type silicon epitaxial layer 63, having a high resistance, is formed on the silicon substrate 61 and, at the same time, some n-type impurities diffuse out of the buried layer 62 into the epitaxial layer 63, so that the buried layer 62 expands up to a broken line in Fig. 36. A silicon nitride layer 64 having a thickness of approximately 50 nm and serving as an anti-oxidation masking layer is formed on the epitaxial layer 63 by chemical vapor deposition. A silicon oxide layer (i.e. an insulating layer) 65 having a thickness of approximately 50 nm is formed on the silicon nitride layer 64 by chemical vapor deposition. Furthermore, an negative photo resist layer 66 is applied onto the silicon oxide layer 45 and, then, is exposed and developed to form a patterned negative resist layer 66, as illustrated in Fig. 36. Next, a positive photo resist layer 67 is applied onto the entire surfaces of the exposed portions of the silicon dioxide layer 65 and the patterned negative resist layer 66. The positive resist layer 67 is exposed and developed to form an opening 68, as illustated in Fig. 37. P-type impurities (e.g. boron) are introduced through the opening 68, through the silicon dioxide layer 65 and through the silicon nitride layer 64 into the epitaxial layer 63 by ion-implantation to form a high concentration region 69 (Fig. 37) of p-type impurities. After the positive photo resist layer 67 is removed, another positive photo resist layer 70 is applied onto the exposed silicon dioxide layer 65 and the patterned negative resist layer 66 and, then, the positive photo resist layer 70 is exposed and developed to form another opening 71, as illustrated in Fig. 38. N-type impurities (e.g. phosphorus) are introduced through the opening 71, through the silicon dioxide layer 65 and through the silicon nitride layer 64 into the epitaxial layer 63 by ion-implantation to form a high concentration region 72 (Fig. 38) of n-type impurities. After the positive resist layer 70 is removed, the obtained semiconductor body comprising the silicon substrate 61 and the epitaxial layer 63 is placed in a reaction tube (not shown) heated at 1500C. Hydrogen fluoride (HF) gas flows through the reaction tube at the flow rate of approximately 10 #min for approximately 30 minutes. Since the hydrogen fluoride reacts with the water content of the patterned negative resist layer 66 to produce hydrofluoric acid, the hydrofluoric acid etches a portion the silicon dioxide layer 65 lying under the patterned negative resist layer 66, as illustrated in Fig. 39. Such etching process is a so-called "DryOx process" (ref. Reichard L. Bersin and Reichard F. Reichelderfer, "The DryOx Process For Etching Silicon Dioxide", Solid State Technology, April (1977), pp 78-90). Next, the negative photo resist layer 66 is removed, thus, the patterned silicon dioxide layer 65 remains, as illustrated in Fig. 40. Using the patterned silicon dioxide layer 65 as a mask, the silicon nitride layer 64 is selectively etched by a pyro phosphoric acid solution to expose a portion of the epitaxial layer 63, as illustrated in Fig. 41. After the patterned silicon dioxide layer 65 is removed by an etchant, i.e. a solution of hydrofluoric acid, the obtained semiconductor body is heated at 11000C, for approximately 2 hours, in an oxidizing atmosphere. As a result of this thermal oxidation treatment, the exposed epitaxial layer 63 is oxidized to form a thick silicon dioxide layer 73 having a thickness of approximately 1 lim, the p-type impurities in the high concentration region 69 diffuse into the epitaxial layer 63 and arrive at the silicon substrate 61 to form an isolation region 74 and, simultaneously. The n-type impurities in the high concentration region 72 diffuse and arrive at the buried layer 62 to form a collector connecting region 75, as illustrated in Fig. 42. The obtained semiconductor body illustrated in Fig. 42 is the same as that illustrated in Fig. 31 in the case of the embodiment E. Therefore, the merit mentioned in the embodiment E is also obtained in this embodiment H. Embodiment I Subsequent to the step of forming the opening 68 (Fig. 33) and prior to the step of introducing the p-type impurities of the embodiment H, portions of the silicon dioxide layer 65 and silicon nitride layer 64 within the opening 68 can be etched by plasma etching, as illustrated in Fig. 43. The procedure of treating steps in this embodiment, except for the above-mentioned etching step, is same as that of the embodiment H. As a result, the semiconductor body in the state illustrated in Fig. 33 can be obtained. Embodiment J Subsequent to the step of etching the silicon nitride layer 64 (refer to Fig. 41) of the embodiment H, a portion of the epitaxial layer 63 can be etched by plasma etching to obtain the semiconductor body having a structure is similar to that of the semiconductor body illustrated in Fig. 26. Then, the steps of removing the patterned silicon dioxide layer 65 and heating in the oxidizing atmosphere of the embodiment H are carried out to obtain the semiconductor body in the state illustrated in Fig. 35. Furthermore, in a case where the length of the thick silicon dioxide portion 8C (Fig. 1), namely, the distance between the isolation region 7 and the base region 4 (Fig. 1) is 2 Wm and below, the punch through phenomenon after occurs, when a depletion layer extending from the base region-epitaxial layer interface into the isolated region 2' (Fig. 1) is joined to a depletion layer extending from the isolation region-epitaxial layer interface into the isolated region 2'. The punch through phenomenon generates an undesirable leakage current. In order to prevent the punch through phenomenon from occuring, it is preferable to intro 12 2 duce n-type impurities (a dose of 5 x 1012 atoms/cm2 at an energy of 60 KeV) into a portion of the epitaxial layer 2 lying under the silicon dioxide layer portion 8C by ion -implantation priot to the step of forming the thick silicon dioxide layer portion 8C. It will be obvious that the present invention is not restricted to the above-mentioned embodiments, and that many variations are possible for those skilled in the art without departing from the scope of the present invention. For example, it is possible to produce a pnp-type bipolar transistor instead of the npn-type bipolar transistor. An anti-oxidation masking layer may be made of silicon carbide instead of silicon nitride.

Claims: CLAIMS 1. A method of producing a semiconductor device comprising at least one semiconductor element and an isolation region which are formed in an epitaxial layer formed on a semiconductor substrate having a buried layer, said method comprising, in sequence, the steps of: forming a mask pattern for preventing impurities from entering said epitaxial layer; introducing the impurities into a predetermined portion of said epitaxial layer; forming a patterned anti-oxidation masking layer for selective thermal-oxidation of the epitaxial layer, and; thermal-oxidizing said epitaxial layer to form a thick oxide layer at the same time said introduced impurities are diffused into said epitaxial layer to form said isolation region. 2. A method as claimed in claim 1, comprising the steps of: forming an anti-oxidation masking layer on said epitaxial layer; selectively removing said masking layer by photoetching to expose portions of said epitaxial layer; thermal-oxidizing said exposed portions of the epitaxial layer to form a thin oxide layers; forming a patterned resist layer; introducing the impurities into the predetermined portion of said epitaxial layer which is covered by said masking layer and is not under said resist layer; removing said patterned resist layer, and; thermal-oxidizing said epitaxial layer by using said remaining anti-oxidation masking layer as a mask to form a thick oxide layer. 3. A method as claimed in claim 2 comprising the step of etching said exposed portions of the epitaxial layer prior to formation of the thin oxide layers. 4. A method as claimed in claim 2 comprising the step of removing a portion of said masking layer which is not covered by said patterned resist layer by etching subsequent to formation of the patterned resist layer. 5. A method as claimed in claim 2 comprising the step of removing said thin oxide layer prior to formation of the thick oxide layer. 6. A method as claimed in claim 3 further comprising the step of removing the portion of said masking layer which is not covered by said patterned resist layer by etching subsequent to formation of the patterned resist layer. 7. A method as claimed in claim 6 further comprising the step of etching a portion of said epitaxial layer subsequent to removal of said portion of the masking layer. 8. A method as claimed in claim 4 further comprising the step of removing said thin oxide layer prior to formation of the thick oxide layer. 9. A method as claimed in claim 4 further comprising the step of etching the portion of said epitaxial layer subsequent to removal of the portion of said masking layer. 10. A method as claimed in claim 1 comprising the steps of: forming an anti-oxidation masking layer on said epitaxial layer; forming an insulating layer on said anti-oxidation masking layer; forming a patterned resist layer; introducing the impurities into the predetermined portion of said epitaxial layer which is not under said resist layer; removing said patterned resist layer; making a pattern mask out of said anti-oxidation masking layer, and; selectively thermal-oxidizing said epitaxial layer to form a thick oxide layer. 11. A method as claimed in claim 10 comprising the steps of: forming an anti-oxidation masking layer on said epitaxial layer; forming an insulating layer on said antioxidation masking layer; forming a patterned negative resist layer on said insulating layer; selectively etching said insulating layer by using said negative resist layer as a mask; forming a patterned positive resist layer on said negative resist layer and portions of said anti-oxidation masking layer; introducing the impurities into the predetermined portion of said epitaxial layer which is not under said positive resist layer; removing said patterned positive resist layer; forming a metal layer over all of the surfaces of said patterned negative resist layer and said anti-oxidation masking layer; removing said negative resist layer and the portion of said metal layer lying thereon; ; etching the remaining insulating layer and the portion of said anti-oxidation layer lying thereunder by using the remaining metal layer as a mask; removing said remaining metal layer, and; selectively thermal-oxidizing said epitaxial layer by using the remaining anti-oxidation masking layer as a pattern mask to form said thick oxide layer. 12. A method as claimed in claim 11, wherein said method comprises the step of removing said negative resist layer prior to said step of forming the patterned possitive resist layer, when the remaining insulating layer is removed, the portion of said metal layer laying on said insulating layer is simultaneously removed. 13. A method as claimed in claim 11 or 12, wherein, prior to said step of introducing the impurities into the predetermined portion of said epitaxial layer, said method further comprises the step of removing the portion of said anti-oxidation layer which lies on said predetermined portion of the epitaxial layer. 14. A method as claimed in claim 11, 12 or 13 comprising the step of etching a portion of said epitaxial layer prior to said step of removing the remaining metal layer. 15. A method as claimed in claim 13 further comprising the step of etching a portion of said epitaxial layer prior to said step of introducing the impurities. 16. A method as claimed in claim 15 comprising the step of etching a portion of said epitaxial layer prior to said step of removing the remaining metal layer. 17. A method as claimed in claim 10, wherein said step of forming the patterned resist layer compriese the steps of: forming a patterned negative resist layer on said insulating layer, and; forming a patterned positive resist layer on said negative resist layer and portions of said insulating layer, and said step of making the pattern mask comprises the steps of: etching the portion of said insulating layer which is covered with said patterned negative resist layer by using a reaction between the water content in said negative resist and hydrogen fluoride gas; removing said negative resist layer; etching said anti-oxidation masking layer by using the remaining insulating layer as a mask, and; removing said remaining insulating layer. 18. A method as claimed in claim 17 further comprising the step of etching a portion of said epitaxial layer subsequent to said step of removing the remaining insulating layer. 19. A method as claimed in claim 17 further comprising the steps of etching portions of said insulating layer and said anti-oxidation masking layer subsequent to said step of forming the patterned positive resist layer. 20. A method as claimed in claim 1, wherein the conductivity type of said introduced impurities for the isolation region is the same as that of said semiconductor substrate.

Inventors: ABE, RYOJI, HATAISHI, OSAMU, MOMMA, YOSHINOBU
Applicants: FUJITSU LIMITED
Application year: 1980
Main classification: H01L21
IPC codes: H01L21