APPARATUS FOR SAMPLING,FILTERING AND MULTIPLEXING DATA

Abstract: The apparatus accepts n analog input signals, on an essentially continuous basis, at respective n input terminals each of which is connected to a "second" electrode of a respective one of n capacitors (26) of a semiconductor structure (20).The respective "first" capacitor electrode is connected to a respective region of semiconductor material which has a conductivity opposite to that of a substrate of the semiconductor structure (20), which structure further comprises an n-stage charge transfer shift register (21). A clocking wave form generator (56) introduces serially n packets of fixed charge-content (due to a fixed voltage source 55) for storage in the n shift register stages. This forms an initial first sequence of charge packets. A gating circuit (74) then enables simultaneous alteration of the n stored fixed charge-content packets, each one in accordance with its respective analog input signal. This forms an initial second sequence of charge packets, which is read out serially. The first and second sequences are formed repetitively in such manner that a new first sequence is formed while the thereto previous second sequence is concurrently read out.

Description: APPARATUS FOR SAMPLING, FLTEHTNG AND MULTIPLEXING DATA The present invention relates in general to switched capacitor sampled data filters which provide a high-pass frequency response, and in particular relates to charge transfer apparatus incorporating a plurality of such switched capacitor high-pass filters for sampling, filtering and multiplexing a plurality of data input signals. The present invention has particular application in infrared signal processing systems. pi such systems an array of detectors are provided ,for sensing the radiation of a scene to be scanned. The scanning of the scene produces a plurality of signals, one from each of the detectors. Each of the signals is sampled and filtered to remove the DC or background component thereof. Thereafter corresponding samples of each of the signals are multiplexed to provide sequences of sampled signals. These sequences are further processed to provide video signals corresponding to the scene scanned. The present invention is directed to the provision of improvements in apparatus providing these functions. An object of the present invention is to provide a data sampling, filtering and multiplexing apparatus which has high rejection for background noise components or DC components in the input signals applied thereto, as well as so-called "pattern-noise" signals, and which filters the desired signals in improved manner. Ih the subsequent description reference will be made to the following literature: U. S. Patent Specification No. 4,125, 786 MacLennan, and the corresponding published British Patent Application 2, 002, 960A, published-in-piint on 28 February 1979, hereinafter collectively referred to as MacLennan I. U. S. Patent Specification No. 4, 172, 983 MacLennan, hereinafter referred to as MacLennan II. MacLennan I describes utilization of apparatus of the general class to which the apparatus of this invention belongs. However MacLennan I is directed to the demultiplexing of already sampled and multiplexed data,, The present invention,is directed to the sampling and multiplexing of input data signals. The apparatus of the present invention is similar to that -of MacLennan π up to a certain point, and to this extent it comprises: A semiconductor structure, which is formed of: (1) a substrate of semiconductor material of one conductivity type having a major surface. (2) a charge transfer shift register which includes n stages plus a charge o:- * ~ -3- input stage and a charge output stage, each stage liaving a respective storage electrode which provides a charge storage region adjacent the major surface; (3) n capacitors. (4) n regions of opposite conductivity type each 5 situated adjacent a respective storage region and connected to a first electrode of a respective capacitor. The apparatus common to M-acLennan II and the present invention further includes clocking means which transfer charge from stage to stage of the shift register, an initial charge input 10 circui and an ultimate charge output circuit, and gating means which establishes a charge transfer channel between each storage . region and its respective region of opposite conductivity type. At this point the present invention departs from MacLennan π. The present invention provides for parallel 15 sampling of plural data input signals, and accelerates the sampling and multiplexing operations in other respects. S ce parallel operation tends to render the apparatus more sensitive to noise, the present invention provides measures which result in appreciable noise reduction and improved filtering. Accordingly the apparatus of the invention further comprises n signal input terminals , each connected to the second electrode of a respective capacitor, and to which are applied on an essentially continuous basis, n analog input signals respectively. For the purpose of sampling, there is introduced serially for storage into the respective n stages, the same number n of packets of fixed quantities of charge, to form an initial first s-equence of n such stored packets. The gating means is actuated to alter simultaneously the charge-contents of the n packets, each content in accordance with its respective analog input signal, thereby forming an initial second sequence of charge packets. The formation of first and second sequences is repetitive. The charge output circuit senses in succession the charge packets of each said second sequence. Moreover, in the interest of accelerating the sampling and multiplexing process, a new first sequence is formed even while the thereto previous second sequence is read out. CΪ..PI The invention, together with further objects and advantages thereof may best be understood by reference to the following description taken in connection with the accompanying drawings wherein: FIGURE 1 shows a schematic diagram of a switched capacitor high -pass filter. FIGURE 2 illustrates apparatus in accordance with an embodiment of the present invention, partly as structural plan view, and partly as electrical block diagram. FIGURE 3 is a sectional view of the embodiment of Figure 2 taken along section lines 3-3 thereof. FIGURES 4A to 4E show diagrams of voltage waveforms useful in explaining the operation of the apparatus of the present invention. Reference is now made to Figure 1 which shows a conventional switched capacitor high pass filter. The circuit comprises two capacitors C. -and C Q -and two switches S- and S 0 . 1 _5 1 Δ The capacitor C , switch S 1 and capacitor C are connected in series in the order named between an input terminal 11 and ground terminal 13. -Switch S 2 is connected across capacitor C-. An output terminal 12 is connected to the ungrounded electrode of capacitor C„ . The switches S. and S 2 are operated synchronously but in a manner such that both switches are not closed at the same time. An input signal. V- to be filtered is applied between terminal 11 and ground. A filtered output signal is obtained between output terminal 12 and ground. In operation, the capacitor C„ is prechargedto azero level by closing switch S„ . On the next part of the cycle, switch S. is closed and couples the input signal v\ through C^ to the output terminal 12 where it appears as V„. The charge q^ stored on C. prior to closing S 1 is determined fay the values of V^. and V at the end of the last [(i-l) th ] switching cycle, and is given by the equation: q L (i-i) - [V 2 (i-l)-V 1 (i-l)]C 1 (1) The new charge on C becomes [V * 2 (i) - V.(i)]C.. and the charge on C„ becomes V (i)C 2 . Since the action of closing switch S. can only redistribute charge, the total charge before and after switch S is closed must be equal, i.e. [v 2 (i-i)-v 1 (i-i)]c 1 - [v 2 (i)-v 1 (i)]c 1 +v 2 (i)c 2 or -V 2 (i-l) (2) Taking the z-transform of equation 2 and solving for the transfer function yields: H(z) = V^/V^z) = a ^ , (3) where a = c 1+ c. It is evident from equation (3) the filter has a high pass characteristic as there is a zero at z=l and a pole at C, 5 z » c..c 2 The frequency response of the filter is obtained by the +j<UT substitution of e for z in equation 3 2 ( l-cos(tfT) H(jto) — a (4) l-2acosWT+a' where W represents the frequency of the input s igna l and T 0 is the period of the switching cyc le . The frequency response at id - 0 is 0 and at the Nyquist rate, Lύ = fr/T, the response is given by the following : Reference is now made to Figures 2 and 3 which show lδ appara tus 20 in accordance with the present invention in which a plura lity of switched capacitor high pass filters such as shown in Figure 1 are provided and in which the outputs thereof are multiplexed. The apparatus inc ludes a cha rge trans fer shift register 2 1 having n stages. The shift D register 2 1 is formed on a subs tra te 22 of semiconductor material o f o n e conductivity type having a major surface 23. Each of the stages of the shift register includes a respective first storage region 24 adjacent the major surface 23 and a first storage electrode 25 insulatingly overlying the first storage region. The apparatus 20 also includes a plurality of switched capacitor high-pass filters 26, such as shown in Figure 1, only two of which are shown completely. Each of the filters 26 includes an input terminal 27, a first capacitor 30, a second capacitor 25a and a gating stage 28 corresponding to input terminal 11, capacitor C-, capacitor C 2 , and -switch S^, respectively, of Figure 1. The first capacitor 30 includes a first electrode 31 connected to a region 32 of opposite conductivity type, situated adjacent a respective first storage region 24 of the shift regis ter and a second electrode 33 connected to the input termina l 27. The second capacitor 25a comprises the capacitance of the first storage electrode 25 with respect to the subs trate 22 and the depletion capacitance o f the storage region 24. An auxiliary electrode 29 is provided insulatingly overlying the surface adj acent region of th e subs tra te contiguous the region 32 of oppos ite conduc tivity type . The electrode 29 is connected to the potentia l of the electrode 25 and establishes an inversion layer as conduction channel in the surface adjacent region of the substrate lying thereunder. The ga ting stage 28 comprises a gating electrode 34 insulating ly overlying the surface adj acent region of the substrate 22 between the first storage O ΓI v, IF region 24 and the surface a dj acent region underlying the auxiliary electrode 29 for controlling conduction between the firs t electro de 31 of the firs t capacitor and the first storage region 24 underlying electrode 25 of the s econd capacitor. 5 The provision of such an electrode facilitates the fabrication of the appara tus and, if desired, may be elimina ted , in such case the region 32 of opposite conductivity type would be contiguous with the surface a dj acent region underlying the gating electrode 34. 10 The substra te 22 may be constituted of silicon s emiconductor materia l of N-type conductivity and of suitable res is tivity, for example, 4 ohm centimeters . The substrate is provided with a channel portion 41 over which the shift lδregis ter 21 is formed. Overlying maj or surface 23 of the subs trate 22 is a thick insulating member 42 of silicon dioxide having a thin portion 43 therein lying in registry with the channel portion 41. In Figure 2 the thick portions of the insula tor 42 are indicated by sha ding . A plurality of first 0 storage electrodes 25 are provided on the insulating member 42 overlying the thin portion 43. Each of the first storage e lectrodes is of uniform length in the direction of the length dimension of the channel portion 41, i. e. in the direction of -— _ ■ charge transfer. Each of the first storage electrodesextends across both the thin insulating portion 43 and the bordering thick insulating portions of the insulating member 42. A plurality of second storage electrodes 45 is provided on the insulating member 42 overlying the thin portion 43. Each of the electrodes 45 is of uniform length in the direction of the length dimension of the channel portion41 and equal tothe uniform length of the first storage electrodes 25. Each of the electrodes 45 extends across both the thin insulating portion 43 and the bordering thick insulating portions of insulating member 42. An insulating layer 46isprovidedover the electrodes 25 and 45. A plurality of first transfer electrodes 47 are provided over the insulating layer46. Each of the first transfer electrodes 47 is insulatingly spaced between a respective second storage electrode 45 and an adjacent succeeding first storage electrode 25 ' and overlying these electrodes. A plurality of second transfer electrodes 48 are provided over the insulating layer 46. Each of the second transfer electrodes 48 is insulatingly spacedbetween a respective first storage electrode 25 and anadjacentsuccee-d- Ing second storage electrode 45 and overlying these electrodes. Each of the transfer electrodes 47 and 48 is of substantially - _ REA^ OMPI uniform extent in the direction of the length of the channel portion 41 and extends over the thin insulating portion 41 of the insulating member 42 as well as the bordering thick in¬ sula ing portions thereof. All of the first storage electrodes 25 of the shift register 21 are connected to a line 51 to which a ø_ voltage is supplied from a fixed voltage source 55. All of the second storage electrodes 45 of the shift register 21 are connected to line 52 to which a ø_ voltage is supplied from a clocking waveform generator 56. The clocking waveform generator 56 is under the control of the timing generator 57. All of the first transfer electrodes 47 of the shift register 21 are connected to a ø ' line 53 to which a ø ' voltage is supplied from fixed voltage source 55. All of the second transfer electrodes 48 of the shift register 21 are connected to a ø c ' line 54 to which a ø ' voltage is applied from a clocking waveform generator 56. The ø_, ø D , ø ' and the ø ' voltage waveforms are shown in Figs. 4A through 4D, respectively. The filter stages 26 are formed on the semiconductor substrate 22. A plurality of second electrodes 33 of first capacitors 30 is provided, each overlying a portion of thick insula tor 42 . A thin insulating layer 61 is provided over electrodes 33 . A plura lity of first electrodes 31 of capacitors 30 is provided, each overlying thin insulating 5 layer 61. A plura lity of third or auxiliaiy electrodes 29 is provided, each overlying thin insulating layer 62 which in turn overlies a respective surface adj acent portion 29a of the substrate and forming a third capacitor therewith. A plurality of regions 32 o f opposite conductivity type indicated by stiple 10 shading in Figure 2 is provided in the substrate adjacent the maj or surface 23 thereof, each contiguous with a respective surface adj acent portion 29a . Each region 32 of opposite conduc tivity type is connected to a respective first electrode 31 by a respec tive conductor 63 . A plura lity conductive 15 connections 64 are provided, each between a respective second electrode 33 of capacitor 30 and a respective input terminal 27. A conductive connec tion 65 is provided to a ll of the third elec trodes 29 which is connected to the ø_ line 51 of the fixed voltage source 55. Thus , with the application of the ^ indicated potentia l to a third electrode 29 ,. a third capacitance OMPI is provided between the third electrode and the substrate. The ø D electrodes 25 of the shift register 21 form second capacitors with the surface adjacent regions of the substrate lying thereunder. A plurality of thin recesses 71 are provided in the thick insulating member 42 underlying which are thin insulating portions 72, each connecting a respective part of the thin insulating portion 43 with a respective part of the thin insulation portion 62. The first or ø D electrodes 25 of the shift register 21 extend into the recesses 71 and each overlie a first part of a respective thin insulating portion 72.A parallel transfer gate or line 34 is provided on the insulating portion 42 between the thin insulating portions 43 and 62 overlying the recesses 71 between the ø_ electrodes 25 and the third electrodes 29. The parallel transfer gate 34 is connected to a parallel transfer gate control 74 which provides a parallel transfer gate voltage ø & , as shown in Figure 4E. The parallel transfer gate control 74 is synchronized with the timing generator 57. When a suitable gate potential is applied to the gate electrode 34 a conductive channel is formed θ_'. •// " WH in the underlying surface adj acent region of the subs trate 22 which enables trans fer of charge from the storage regions 2 4 underlying the ø n electrodes of the shift register 21 to the firs t s torage regions 29a underlying the third electrodes 29 of the filter s tages and to the firs t electrode 31 of first capacitor 30. Each stage of the shift regis ter 21 includes a ø storage region underlying a ø electrode 25 and a ø_ s torage region underlying a cp electrode 45 . The ø_ voltage applied to the ø_ electrode is fixed . The ø-, voltage applied to the φ„ electrode cycles between a high level and a low level above and below the ø_ voltage. When the <p„ voltage is at its high level, charge trans fer is enabled from the ø_ storage region to the ø_. storage region and conversely when the ø_ voltage is at its low level, charge trans ferred from the D storage region to the ø c s torage region is enab led . Each stage also includes a ø ' elec trode 47 to which is applied a ø ' voltage of fixed va lue which produces a surface potentia l in the substrate underlying the e lectrode which is smaller in absolute magnitude u C -PI 4 IPO than the surface potential underlying a ø_ electrode. Each stage a lso inc ludes a ø ' electrode 48 to which is applied a ø ' voltage having two levels . At the upper level a surface potentia l is produced in the substra te underlying the electrode which inhibits the transfer of charge from a ø_ stor.age region to a ø r storage region. At the lower level a surface potential is produced enabling the trans fer charge from a Q s torage region to a ø_ s torage region. Packets of charge of fixed va lue for insertion into the shift regis ter 21 are genera ted by a bias charge input circuit 58 under the contro l of the clocking waveform generator 56 and in response to bias charge setting controls. One input circuit for developing sequence of packets of charge and for inserting the packets into a charge transfer shift register is described in connection with Figs . 2 and 3 of U. S. Patent No. 4,126, 852 Baertsch, incorporated herein by reference. After charge packets have been clocked into the shift regis ter 21 and have been equilibrated and hence modified by the various filter stages 26 of the apparatus in a manner to be explained below , the resultant packets of charge are contained in the storage regions underlying the ø D electrodes 25. The resultant packets of charge are then clocked out of the shift regis ter and sens ed in an output circuit 59 from which an output signa l is obta ined . One output circuit suitable for OMPI WIIPPOO -17- providing an output in accordance with the sequence of packets of charge clocked thereinto is described in connection with Figure 1 of MacLennan I. The operation of the apparatus of Figures 2 and 3 will 5 now be explained in connection with the waveform diagrams of Figures 4A to 4E. It will be recalled that n is the number of stages of the shift register 21, and also of the filters provided. Furtherm re, it is also the number of analog signals to be sampled and multiplexed, each being applied on an essentially 10 continuous basis to a respective input terminal 27. During a first period of time t to L , an initial first sequence of n packets of charge, each including a fixed quantity of charge, are generated and clocked serially into the shift register 21; in consequence, the packets are stored in the respective ones of 15 the n first storage regions or C storage regions. After charge has thus been transferred into the 0 storage regions, during a second time-period L to t — this occurs during the short interval of the 0 clock cycle when the < voltage 'H «Λ ( - / Λ- V, irU is high --, a gating pulse 75 (Figure 4E) is provided to the parallel transfer gate 34 enabling the charges underlying the ø-y electrodes concurrently to flow into the respective surface adjacent portions of the substrate underlying the respective third electrodes 29 and equilibrate therewith as well as with the potential on the respective first electrodes 31 of the respective first capacitors 30. During this second period the charge-contents (fixed quantity) of the n stored packets are simultaneously modified, each charge-content in accordance with its respective analog signal applied to its respective input terminal 27. Thus an initial second sequence of modified packets of charge are contained in the storage regions underlying the 0 electrodes of the shift register 21. During a third period of time t ~ to t . , subsequent to time t > » the initial second sequence packets of modified charge-content, which are stored in the storage regions underlying the (Z» electrodes, is clocked out sequentially or serially into the output circuit 59 where these n packets are sensed sequentially so that multiplexed output signals are read out from the circuit 59. During the third period of time while the initial second sequence is clocked out of the shift register 21, a new first sequence of packets of fixed value is clocked serially into the shift register 21 for processing in the same manner as the initial first sequence of packets. Thus, successive first sequences of packets of fixed charge-content are processed into successive second sequences, which are read out. The second sequences of multiplexed samples may be utilized directly to provide a display. Also, corresponding output samples of the successive second sequences may be demultiplexed, if desired, to provide a plurality of demultiplexed or "third" sequences of output samples, each corresponding to a respective one of the n analog input signals. It should be noted that the formation of a second sequence occurs essentially without any interruption in the clocking of charge in the shift register 21 ; so that the formation of a new first sequence takes place concurrently with the readout of a thereto previous second sequence. Thus, the rate at which an input signal is sampled, is equal to the rate at which the gating pulses 75 are generated. The rate of transfer of charge from stage to stage of the shift register is n times the rate of sampling of an input signal, i. e. n times the rate of generation of the gating pulses 75. The function of the second switch S« of Figure 1 is implemented In the apparatus ' of Figure 2 by the dynamic oper¬ ation of the shift register 21. The transfer of a fixed packet of charge into a storage region corresponds to a closing and 5 opening of the switch S- and the actuation of the transfer channel to that storage region by gating voltage applied to the gating electrode 34 corresponds to a closing and opening of switch S . The high-pass multiplexed charge transfer apparatus D described offers several advantages . A primary' advantage is that the zero in the transfer function of each of the filter stages 26 is inherent in the capacitive coupling provided fay the first capacitors to the first storage regions of the shift register. Thus , the DC rej ection is limited only by the signal dependent leakage currents appearing across the input capaci tors 30. The second- advantage is that low pattern noise is achieved in this apparatus . The principle source of pattern noise in this apparatus is the non- uniformity in leakage current to the first electrode 31 of capacitor 30. When the OMPI apparatus is operated at cryogenic temperatures, this leakage becomes extremely small. The third advantage of the apparatus is that the frequency response of the filter sections is determined only by the clock frequency and by the ratio of 5 the first capacitance 30 and the second capacitance 25a of the stages of the shift registers. Since the ratio of these capacitances is determined by the ratio of two areas, the frequency response may be accurately predicted and controlled. While in the apparatus described in connection with D Figures 2 and 3, third storage electrodes 29 were provided in the gating stages of each of the filter stages in order to facilitate fabrication and to enable each filter stage to be designed with precision particularly with respect to the location of the regions of opposite conductivity type with 5 respect to the gating electrode 34. Such third electrodes 29 could be eliminated, if desired, and each of the regions 32 of opposite conductivity type of each of the filter stages made contiguous with the surface adjacent region underlying each of the gate electrodes 34. In the design shown the third electrodes provide in effect a small third capacitance connec¬ ted between the first electrode of the first capacitor 30 and the ground or reference terminal of the filter. The third capacitance adds a small capacitance to the capacitance 30 and increases the time constant of the filter stage 26 while decreasing the gain thereof . While the invention has been described in connection with the apparatus constituted of N-type conductivity substrates, P- type conductivity substrates could as well be used. Of course, in such case the applied potentials would be reversed in polarity. o:.*:? WIP

Claims: C LA IMS lo Apparatus for sampling, filtering and multiplexing input data signals, comprising: a semiconductor structure formed of: a substrate of semiconductor material of one conductivity type having a major surface (23), a charge transfer shift register(21) comprised of n stages plus a charge input stage and a charge output stage, each of said stages having a respec¬ tive storage electrode insulatingly overlying said major surface to provide a respective first charge storage regiαπ(24) adjacent said major surface ( 23 ) , n capacitors ( 30 ), each capacitor including a first electrode and a second electrode (31,33) n re ions (32)o f opposite conductivity type adjacent said major surface, each situated adjacent a respective first storage region, the first (31) electrode of each capacitor connected to a respective region of opposite conductivity type, 0: ;: Claim 1 ( continued ) said apparatus further comprising: clocking means for transferring charge from stage to stage of said shift register (56), a charge input circuit for generating and transferring charge into said input stage and a charge outpu circuit for sensing charge transferred out of said output stage (58,59), gating means for establishing a charge transfer channel between each of said first storage regions and a respective region of opposite conductivity type (74), characterized by n signal input terminals ( 27 ) each connected to the second electrode of a respective one of said capacitors (30), means for applying on an essentially continuous basis, n analog input signals, each to a respective one of said input terminals (27 ) means for introducing sequentially into the respective n stages of the shift register (21) for storage therein, via said input circuit (58) and under control of said clocking means (56), O.V Claim 1 (continued) packets of fixed charge -content, thereby to form an initial sequence of such stored packets of fixed charge-content, and for subsequently re-introducing in like manner such n packets of fixed charge-content, to form similar such first sequences, means for initially actuating said gating means after the n packets σf the initial first sequence are stored in the n first storage regions of said shift register (21) , for an interval less than the interval of storage therein-, whereby to alter the charge-content of each packet then stored, concurrently with the alteration of the charge -content of each other packet then stored, each in accordance with its respective analog input signal applied through its respective capacitor, whereby to form an initial second sequence of packets of modified charge-content, and for subsequently repeatedly re-actuating said gating means in like manner, to form similar such second sequences, said charge output circuit (59) sensing serial¬ ly the charge -content of each said second sequence. 2. Apparatus as claimed in Claim 1, wherein the formation of a new first sequence takes place substantially concurrently with the s-ensing of the thereto preceding second sequence. 3. Apparatus as claimed in Claim 1 or 2, in which the rate of transferring charge from stage to stage of said shift register is n times the rate of actuation of said gating means . 4. Apparatus as claimed in Claim 1 or 2, in which said n capacitors are situated on said subs tra te. 5. Apparatus as claimed in Claim 1 or 2, in which the capaci¬ tance of each of said capacitors is subs tantia lly greater than the capacitance of a respec tive s torage electrode with respect to said substra te. 6. Apparatus as claimed in Claim 1 or 2, in which a plurality of auxiliary electrodes are provided, each insulatingly overlying a respective surface adj acent conduction channel region of said, subs tra te , each of said conduction channe l regions being contiguous to a respective charge trans fer channel established by sa id gating means and a respective region of opposite conductivity type , and in which means are provided for establishing conduction in each said conduction channel region. OM Λ W IP

Inventors: QUICK M
Applicants: GEN ELECTRIC, GENERAL ELECTRIC CO
Application year: 1980
Main classification: G11C19
IPC codes: G11C27