DIFFERENTIAL AMPLIFIER

Abstract: A differential amplifier, preferably comprised of N-channel MOS devices and having a high ratio of differential gain to common mode gain, has an input stage (6, 8, 14, 16) which receives first and second potentials (4, 2) and amplifies the difference therebetween. Additional amplifying stages each include a depletion input load device having a gate which is coupled to the second potential for balancing the switching points of each additional stage over the common mode range. By coupling a reference voltage and an A.C. signal to the inputs (4, 2), an A.C. zero crossover detection circuit is achieved. A reference voltage generator (54) applies a reference voltage to the first input of the amplifier. An output (56) of the amplifier is coupled to the gate of an MOS switch (74) which, when turned on, reduces the reference voltage by a predetermined amount to compensate for early crossover detection resulting from the phase lead.

Description: DIFFERENTIAL AMPLIFIER BACKGROUND OF THE Il#VJ#NTION FIELD OF THE INVENTION This invention relates generally to differential amplifiers, and more particularly to a metal-oxide- semiconductor (MOS) differential amplifier exhibiting hint, differential qain over wide common mode range. DESCRIPTION Or THE PRIOR ART The advantaqes offered by NMOS technology are well known; e.g. higher density, greater yield, etc. Thus, smaller NMOS device qeometries permit a greater number of devices to be produced per unit area or, stated another way, a single NMOS device will occupy Jesus space. This characteristic is extremely important in the design and fabrication of complex dicital inteqrated circuits; for example, single chip microprocessors. Whereas digital circuitry i generally characterized by its "ON/OFF" or "ONE/@FRO" nature, most measurements in the real world are inherently analoq; eq., temperature, pressure, speed, voltage, etc. Therefore, it is necessary that microprocessors and other digital circuitry communicate or interface with analog circuitry such as amplifiers, buffers, cotnparators, etc., in order to permit digital processing of the analog signals. The required interfacing may be accomplished by providing analog components which are external to the microprocessor chip. However, such arrangements generally require more current, a larger power supply at comply present more opportunities for design and manufacturing errors. To avoid these disadvantaqes, complex analog circuits such as differential amplifiers and voltage crossover detectors are heinq manufactured integrally with the digital circuitry; e.g., on the microprocessor chip itself, and due to the complex feature of microprocessors, the inclusion of analog devices on the same chip requires that the same manufacturing process be employed. Thus, a differential amplifier or voltage crossover detector included on an NMOS microprocessor chip must be fabricated in accordance with NMOS processing techniaues, and their design must he tailored to such processing technioues. Previous MOS implementations of differential amplifiers have been very similar functionally to bipolar implementations. That is, both employ a current source, level shifters, integrator output buffers, etc. Furthermore, the prior art devices generally require an input stage having a high differential gain and a low common mode gain since each additional stage amplifies the common- mode signal; i.e., errors produced in the first stage are further amplified in subsequent stages. Thus, the device is complex, requires a large number of components and is both costly and more difficult to fabricate. In addition, the use of enhancement devices at the inputs limits the maximum swing of the amplifier since these devices will turn off if the input becomes too low. A detailed discussion of such prior art differential amplifiers can be found in the "IEEE Spectrum," February, 1979; pages 24-32 and in the 11IEEE-Journal of Solid State Circuits; December, 1978, pages 760-766. It is well known that a resistor/capacitor (RC) circuit will cause an applied A.C. signal to be phase shifted thus producing an error in the detection of the zero crossovers of the A.C. signal. This phase shift can be reduced by increasing the resistance; however, this substantially increases the time necessary to charge the capacitor. To avoid this time loss, a controlled amount of hysteresis has been employed to partially compensate for the resulting phase shift. While this enabled detection of the positive going zero crossover point to within +5 degrees, an offset error of 100mu resulted in the detection of the negative going zero crossover point. Known zero crossover detection circuits suffer additional disadvantages. First, variations in VR will cause errors to be introduced into the zero crossover detection process. Second, additional errors will be introduced if the controlled amount of hysteresis does not track variations in the biasinq circuit due to minor processing and fabrication variations. SUGARY OF THE INVENTION It is an object of. the present- invention to provide a differential amplifier having large differential gain over a wide common mode range. It is a further object of the invention to provide an MOS differential amplifier having a common mode gain which is not substantially increased by additional stages of amplification. It is a still further object of the invention to provide an MOS differential amplifier having an improved input voltage swing. These objects are achieved, in part, by using depletion devices as input loads and coupling the load gates to. the amplifier input to balance their switching points over the common mode range. Accord inn to a broad aspect of the invention there is provided a differential amplifier circuit for receiving first and second potentials and amplifyinq the difference therebetween, comprising: an input stage for receiving said first and second potentials; and at least one additional amplifying stage coupled to said input stage for amplifying said difference, said at least one additional amplifying stage having a first input coupled to one of said first and second potentials for reducing common mode gain. According to a further object of the invention there is provided an NMOS differential an,pSifier for amplifying the difference between first and second input vo#tac'es, comprising: an input stage comprised of NMOS devices for receivinq said first and second voltages and amplifying the difference therebetween; and at least one additional amplifying staqe coupled to the output of said input stage, said additional amplifier stage including a depletion device having a qate coupled to one of said first and second input voltages. Yet another object of the present invention is to provide an improved A.C. zero crossover detector. It is a further object of the invention to provide a circuit which accurately detects both the positive and negative going zero crossover points of an applied A.C. signal. It is a still further object of the invention to provide a zero crossover detection circuit employing a controlled amount of hysteresis to substantially cancel errors created by RC phase shift. Yet another object of the invention is to provide a zero crossover detector requiring a single power supply. Finally, it is an object of the invention to provide an MOS zero crossover detection circuit wherein biasing changes due to minor processing and fabrication variations are tracked by the hysteresis control circuit. Accordinq to a broad aspect of the invention there is provided apparatus for compensating for phase shift in an applied A C. input signal which would result in incorrect detection of crossover points of said A.C. input signal with a reference voltage, comprising: comparing means having a first input, a second input coupled to said reference voltage and an output responsive to said crossover points; and first means coupled to said comparing means for compensating for said phase shift at each of said crossover points. According to a further object of the invention there is provided an A.C. zero crossover detection circuit of the type wherein an A.C. input signal is phase shifted by a capacitor in combination with an internal resistor, comprising: first means for generating a reference voltage; comparing means for comparing said reference voltage with an A.C. signal to detect the crossover points thereof; and second means coupled to said first means and to said comparing means for adjusting said reference voltage to compensate for phase shift at each of said crossover points, said resistor coupled between said first means and said comparing means. The above and other objects, features and advantages of the invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings, in which: BRIEF DESCRIPTION OF THE DHA > JINGS Figure 1 is a schematic diagram of the inventive differential amplifier circuit; Figure 2 illustrates in graphical form the differential gain of the inventive circuit as a function of the input voltage; Figures 3a and 3b illustrate, in graphical form, the problem and solution with which the resent invention is concerned; Figure 4 is a functional block diagram of the inventive zero crossover detection circuit; and Figure 5 is a detailed schematic diagram of the arrangement shown in Figure 4. DESCRIPTION OF THE PREFERRED EMEODIT Figure 1 is a schematic diagram of the inventive differential amplifier circuit. While N-channel MOS devices are preferred, it should be clear that other processinq techniques (P.G. P-channel, COS) could he used to implement the circuit. Referrinq to Figure 1, the amplifier is comprised of a first leg including depletion device 6 and enhancement device 8 and a second leg including depletion load device 16 and enhancement device 14. Each of these legs are coupled between a source of supply voltage VDD and ground as are the additional stages to be discussed hereinbelow. The gate of depletion device 6 is coupled to a negative input voltage terminal 2, and the gate of depletion device 16 is coupled to a positive input voltage terminal 4. The junction of the source of device 5 and the drain of device 8 (node 10) is coupled to the qates of enhancement devices 8 and 14 at node 12. The circuit includes four additional stages each comprised of a depletion load device in series with an enhancement device coupled between VDD and ground. The gate of each depletion load device in each stage is coupled to the gate of device 16, and the gate of each enhancement device is coupled to the drain of the enhancement device of the previous stage. Thus, the first additional stage is comprised of depletion device 20 and enhancement device 22, the second additional stage is comprised of depletion device 26 and enhancement device 28, the third additional stage includes depletion device 32 and enhancement device - 34 and the final or fifth stage comprises depletion device 38 and enhancement device 40. The gates of devices 20, 26, 32 and 38 are all coupled to the gate of device 16, and the gates of devices 22, 28, 34 and 40 are coupled to node 18, 24, 30 and 36 respectively. The output voltage Vo is available at node 42 and output terminal 44. As in the case of prior art differential amplifiers it is desirable to increase the ratio of differential gain to common mode gain. This is accomplished with the instant inventive circuit because only the differential signal is amplified in subsequent stages while the common mode signal remains substantially constant. To illustrate this, assume that terminals 2 and 4 are coupled together rendering the gate potentials of devices 6 and 16 ecua ] . The current through the first leg (devices 6 and 8) is dependent only on the voltage at terminal 2 and the voltage at node 10 is a function of that current. Since node 10 is coupled to the gates of devices 8 and 14 at node 12, and since the voltages at the gates of devices 6 and 16 are equal, the voltage at node 18 is substantially equal to the voltage at node 10 (approximately one enhancement threshold voltage above ground) if devices 6 and 16 are substantially identical and devices 8 and 14 are substantially identical. Thus, there is substantially no common-mode amplification. Referring now to the second stage, the same voltage is applied to the gate of device 20 as is applied to the gate of device 16, and the same voltage is applied to the gate of device 22 as is applied to the gate of device 14. Thus, the voltage at node 24 is substantially equal to the voltage at node 18. Using the same analysis, the voltages at nodes 30, 36 and 42 are equal to the voltage at nodes 20, 18 and 24 if devices 6, 16, 20, 26, 32 and 38 are identical and if devices 12, 14, 22, 28, 34 and 40 are identical. Thus, theoretically there is no amplification of the common mode signal in the additional stages. Suitable results are obtained if the depletion devices used have a width of eight microns and a length of twenty microns, and the enhancement devices have a width of 130 microns and a length of eight microns. With these geometries, the output voltage was found to vary about 10mv over the entire range of input voltages. To illustrate the differential gain behavior of the circuit, assume that the voltage at terminal 4 remains constant and the voltage on terminal 2 approaches VDD. This will cause the current through depletion device 6 to increase thus increasing the voltage at nodes 10 and 12, which voltage is applied to the gates of devices 8 and 14. The increased drive to device 14 causes it to conduct more current. Since the voltage at the gate of device 16 remains the same, the voltage at node 18 will decrease reducing the drive to device 22. Since, however, the drive to device 20 is unchanged, the voltage at node 24 increases. Using the same analysis, the voltage at node 30 decreases, the voltage at node 36 increases and the voltage at node 42 decreases. Since each stage of the amplifier imparts a differential gain of approximately five on the input signal with negligible common mode gain, the differential signal is substantially amplified at o. Figure 2 is a graphical representation of the voltage gain as a function of input voltage. It can be seen that over a common mode range of approximately 0.2 to 4.5 volts, a gain in excess of 60db is achieved. Figure 3a illustrates the phase lead error induced by a standard RC network. The solid waveform represents an A.C. signal applied to the input of a typical RC network, and the dashed waveform represents the output of the RC network. The input signal actually crosses a reference voltage VR at points A and B. However, the zero crossover points actually detected correspond to points C and D. Thus, there results an offset error tl for each zero crossover point; i.e. early detection of the crossover points. Assuming that an A.C. signal is applied to an ideal zero crossover detection circuit, adding hysteresis to the reference voltage will cause late detection of the zero crossovers This is illustrated in Figure 3b wherein an A.C. signal has superimposed thereon both a constant reference voltage VR and a hysteresis altered reference voltage VRHYST. The A.C. signal crosses VR at points E and F; however, the A.C. signal crosses VRHysT at points G and H (i.e. late detection by an amount t2). If the offset due to phase shift could be made equal to the hysteresis offset (t1=t2), accurate detection of the zero crossover points would occur. This is accomplished by the inventive detection circuit in a manner to be described below. Figure 4 is a functional block diagram of the inventive zero crossover detection circuit. A comparator 46 such as the differential amplifier shown in FIGURE 1 has a first input coupled to an external capacitor 48 via node 50, which capacitor is also coupled to an A.C. input signal. The second input of amplifier 46 is coupled to node 52 at which there appears a reference voltage Vp produced by reference voltage generator 54. The output of amplifier 46 (terminal 56) is fed back to a hysteresis control circuit 58 the output of which is in turn applied to generator 54 for adding or subtracting a controlled amount of hysteresis to the reference voltage VR. The first input of amplifier 46 is also coupled to VR via biasing resistor 60. As stated previously, with the proper application of hysteresis to the reference voltage VR, the phase lead imparted to the input A.C. input signal (terminal 62) by the combination of capacitor 48 and resistor 60 can be fully compensated for. Figure 5 is a detailed schematic diagram of an A.C. zero crossover detection circuit in accordance with the present invention implemented with MOS field effect transistors. Functional units shown in Figure 4 have been enclosed by dashed lines and are denoted with similar numerals in Figure 5. Thus, voltage reference generator 54 comprises depletion device 64 and enhancement devices 66 and 68. Amplifier 46 comprises an input stage including depletion device 6 having a gate coupled to node 50, depletion device 16 havinq a gate coupled to node 52 and enhancement devices 8 and 14. Three additional ampiifyin stages each comprise the series combinaticn of a depletion device having a gate coupled to node 52 and an enhancement device having a gate coupled to the output of the previous stage. Thus, the three additional stages include devices 20 and 22, 26 and 28, and 32 and 34 respectively. It should he clear that amplifier 46 is substantially identical to that shown in FIGURE 1 with the exception that the last stage (devices 38 and 40 have been eliminated and the output terminal 56 is coupled to the junction of devices 32 and 34. Input terminals 2 and 4 (FIGURE 1) are coupled to nodes 50 and 52 respectively (FIGURE 5). Resistor 60 comprises resistor connected depletion devices 70 and 72 coupled between node 52 (V) and node 50, and hysteresis control circuit comprises enhancement device 74 havinq a gate coupled to the amplifier output (terminal 56) and depletion device 76 connected as a resistor and having a drain coupled to reference voltaqe generator 5. Resistor 78 and enhancement device 80 form a standard input protection circuit. Referring now to voltaqe reference generator 54, field effect transistor 64 is a depletion device having its drain connected to a voltage supply terminal Vdd and having its gate electrode connected to a second voltage power supply terminal 23. Power supply terminal 23 is illustrated as being a ground or reference point since for purposes of illustration all the transistors used herein are assumed to he N-channel field effect transistors. The source electrode of field effect transistor 64 is connected to node 82. Field effect transistors 56 and 68 are enhancement devices connected in series between node 82 and power supply terminal 23. Transistors 66 and 68 each have their gate electrodes connected to their drain electrodes. The source electrode of transistor 66 is connected to the drain electrode of transistor 68 while the source electrode of transistor 68 is connected to terminal 23. Transistors 6t, 66 and 68 form a constant voltage reference generator which provides a constant voltaae 57R at output node 82. Once the power supply voltage applied to terminals Vdd and 23 exceeds a certain level the voltage appearing at node 82 remains constant even thollgh the power supply voltage continues to rise. This reference voltage circuit is more fully described in copending patent application S/N 939,725 filed September 7, 1978 and therefore will not be further described herein. The output of amplifier 46 is fed back to the gate of enhancement device 74 which functions as a switch. When "ON", device 74 enables depletion device 76 to pull current from node 84 causing the voltage at node 84 to decrease. This results in a corresponding decrease in VR at node 82. When device 74 is switched "OFF" by amplifier 46, device 76 ceases pullinq current and the voltage at node 82 (VR) rises to its original value. Resistor 12 is comprised of depletion devices 70 and 72 connected as resistors and having their current carryinq electrodes coupled in series between nodes 50 and 52. Two important features of the invention should be noted at this time. First, the same source of voltage VR is used to supply one input of amplifier 6 directly and also biases the second input. Second, since devices 70, 72 and 76 are all of the same type, process variations which affect resistor 60 will correspondingly affect device 76. Thus, these devices will track each other; i.e. if devices 70 and 72 turn on harder producing a larger phase lead, device 76 will likewise turn on harder providing more hysteresis to compensate for the additional phase lead. It should be further appreciated that the addition of hysteresis not only compensates for the RC phase lead, but also provides noise immunity at the switching or zero crossover points. For the sake of completeness, the following indicates suitable lengths and widths of the various MOS devices illustrated in Figure 5. Element Width/Length (Microns) 64 lug0/10 66, 68 80/10 6,16,20,26,32,76 8/20 8,14,22,28,34 130/8 70,72 7/20 7t 30/6 The foregoing description of the embodiment of the invention is by way of example only and is not intended to limit the scope of the appended claims. No attempt has been made to illustrate all possible embodiments of the invention but rather only to illustrate its principles in the best manner presently known to practice them. For example, the circuit may be implemented in NMOS, PMOS, CMOS, etc. The use of depletion type load devices serves to increase the overall input voltage swing. If this were not a critical requirement, enhancement devices could be employed. Further, the beneficial characteristics of the circuit will be achieved if the gates of the depletion devices in each additional stage are coupled to the positive or negative input. These and other modifications of the present invention as may occur to one skilled in the art are within the spirit and scope of the invention. It is therefore intended that this invention include all modifications and equivalents which fall within the scope of the appended claims.

Claims: Claims 1. A circuit for receiving first and second potentials (4 and 2) and amplifying the difference therebetween, comprising: an input stage (6, 8, '14, 16) for receiving said first and second potentials; and at least one additional amplifying stage i201 22) coupled to said input stage for amplifying said difference, said at least one additional amplifying stage having a first input coupled to one of said first and second potentials for reducing common mode gain. 2. A circuit according to claim 1 wherein said circuit includes a plurality of additional amplifying stages coupled in sequence wherein each has a first input coupled to one of said first and second potentials and a second input coupled to an output of a previous one o said amplifying stages. 3. A circuit according to claim 2 wherein each of said additional amplifier stages comprises: first a second series connected MOS devices, saic first device having a gate coupled to said first potential and said second device having a gate coupled to the output of a previous one of said amplifying stages. 4. A circuit according to claim 3 wherein said input stage comprises first and second pairs of series connected MOS devices (6, 8 and 14, 16) each pair coupled across a source of supply voltage and ground, said first potential coupled to one of said devices in said second pair and said second potential coupled to one of said devices in said first pair. 5. A circuit according to claim 4 wherein said first pair of devices comprises: a depletion device (6) having a gate coupled to said second potential; and a first enhancement device (8) whose drain is coupled to its gate. 6. A circuit according to claim 5 wherein said second pair of devices comprises: a depletion device (16) having a gate coupled to said first potential; and an enhancement device (14) having a gate coupled to the gate of said first enhancement device. 7. A circuit according to claim 6 wherein said first device in each of said plurality of additional stages is a depletion device and wherein said second device in each of said plurality of additional staqes is an enhancement device. 8. A circuit according to claim 7 wherein the enhancement devices in each of said plurality of additional stages and in each of said first and second pairs are substantially identical and wherein the depletion devices in each of said plurality of additional stages and in said first and second pairs are substantially identical. 9. A circuit according to claim 8 wherein the resistance of the depletion devices is greater than that of the enhancement devices. 10. A circuit according to claim 9 wherein said MOS devices are N-channel MOS devices. 11. A circuit for amplifying the difference between first and second input voltages, comprising: an input stage (6, 8, 14, 16) coupled to said first and second voltages; and a plurality of amplifying stages coupled in sequence each including first and second MOS devices, said first device having a gate coupled to one of said first and second voltages and said second device having a gate coupled to the output of the previous stage. 12. A circuit according to claim 11 wherein said first device is a depletion device and said second device is an enhancement device. 13. An NMOS amplifier for amplifying the difference between first and second input voltages (2 and 4), comprising: an input stage (6, 8, 14, 16) comprised of NMOS devices for receiving said first and second voltages and amplifying the difference therebetween; and at least one additional amplifying stage coupled to the output of said input stage, said additional amplifier stage including a depletion device (20) having a gate coupled to said first input voltage (4). 14. A circuit according to claim 11 wherein said first potential is a reference voltaqe and said second potential is an A.C. signal, said circuit having an output (56) indicative of the crossover points of said A.C. signal and said reference voltage. 15. A circuit according to claim 14 further including first means (64, 68, 82) for generating said reference voltage and second means (70, 72, 74, 76) coupled to said circuit and to said first means for altering said reference voltage to compensate for phase shift in said A.C. signal at each of said crossover points. 16. A circuit according to claim 15 wherein said second means comprises: switching means (74) coupled to the output of said circuit and responsive thereto; and first resistive means (76) coupled to said first means and responsive to said switching means for reducing said reference voltage when said switching means is in a first state. 17. A circuit according to claim 16 wherein said switching means comprises a first MOS device (74) having a gate electrode coupled to an output of said circuit, a source coupled to ground and a drain coupled to said first resistive means. 18. A circuit according to claim 17 wherein said first resistive means is a second MOS device (76) having source, drain and gate electrodes, said gate electrode coupled to its source electrode and to the drain of said first MOS device and said drain electrode coupled to said first means. 19. A circuit according to claim 18 wherein said second MOS device (76) is of a depletion type. 20. A circuit according to claim 19 further including second resistive means (70, 72) coupled between said reference voltage and said second input. 21. A circuit according to claim 20 wherein said second resistive means comprises third (70) and fourth (72) series coupled MOS devices. 22. A circuit according to claim 21 wherein said third (70) and fourth (72) MOS devices are of the depletion type. 23. A circuit according to claim 22 wherein said first (74), second (76), third (70) and fourth (72) devices are N-channel field effect transistors.

Inventors: ECKERT, KIM HUNTER
Applicants: MOTOROLA, INC.
Application year: 1980
Main classification: H03F3
IPC codes: H03F3, G01R19