SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A DOUBLE INTERCONNECTION LAYER

Abstract: A semiconductor integrated circuit device including a substrate (1) of semiconductor having an insulation layer (2) formed on it, a first layer (3) of semiconductive material form­ ing a wiring layer on the insulation layer, and a second layer (7) of semiconductive material forming a further wiring layer connected in parallel with the first wiring layer via contact holes (5, 6) in an intervening insulation layer (4).

Description: Semiconductor Integrated Circuit Device" This invention relates to a semiconductor integrated circuit device with a double interconnection layer consisting of semiconductive material. Interconnections hava been formed in prior semiconductor integrated circuit device by means of meta layers diffusion regions formed in the semiconductive substrate, polycrystalline silicon layers and so on. Generally, the resistance value of the interconnection means or "wiring layer" is preferred to be smaller, so metal layers for example aluminium layers are preferred. However, when the semiconductor integrated circuit is constructed in high density form, the interconnections cannot be formed by a single metal layer, because it may be necessary for several wiring layers to cross at one point. In such a case one layer may comprise for example a polycrystalline silicon layer as a wiring means: at the crossing point, whilst a second wiring layer made of metal is formed over the first wiring layer with an insulating layer interleaved between the two layers. Using this technique, it is easy to produce a semi conductive integrated circuit which includes crossing points of the wiring layers. Further, the polycrystalline silicon layer may be used as the electrode of a metal oxide semiconductor field effect? transistor (herein after called MOS FET). Iten the gate electrode is constructed with polycrystalline silicon material, the MOS FET can be manufactured by a self-alignment process so that it will be formed compactly, and its operating characteristics will be improved. Thus recently polycrystalline silicon has frequently been used to form the wiring layers and electrodes. However, the sheet resistance of the polycrystalline silicon is very high and so doped poly crystalline silicon has come to be used instead, and has i asheet resistance of the order of several tens of EMI1.1 The sheet resistance can be lowered by increasing the level of doping, but as the doping level increases it becomes more difficult to control the etching process. Thus the quantity of impurity which can be introduced into the polycrystalline silicon as dopant is restricted by the precision of the etching process, so the most commonly used form of doped polycrystalline silicon has a sheet resistance of about EMI2.1 which is much higher than that of metal layers for example aluminium layers, so the operating speed and flexibility of design of the circuit will be limited. Another method of decreasing the resistance of the polycrystalline silicon layer is to increase its thickness and width. However this can give rise to the disadvantage that the aluminium layer thereover may be pierced by-the sharp edge of the thick polycrystalline silicon layer, and the increase of width will result in an increase the increase of the total area of the device. Accordingly the present invention seeks to provide a semiconductor integrated circuit device which can be constructed in high density form and which can operate at high speed. The invention also seeks to provide a semi conductor integrated circuit device including wiring layers whose resistance is kept low. According to one aspect of the present invention there is provided a semiconductor integrated circuit device including a main wiring layer and a secondary wiring layer connected in parallel therewith. Another aspect of this invention is to provide a semiconductor integrated circuit device which includes two semiconductor wiring layers, one layer operating as a gate electrode of a MOS FET and the other layer being connected in parallel to said one layer so as to decrease the total resistance. A further aspect of the present invention is the provision of a semiconductor integrated circuit device comprising a semiconductor substrate on which an insulation layer is formed, a first wiring layer made of semiconductive material and positioned on said insulation layer and a second wiring layer made of semiconductive material formed over said first layer and connected in parallel to said first wiring layer. Some embodiments of the invention will now be described by way of example with reference to the accompanying drawings, wherein: Figure 1 is a partial plan view of one embodiment of this invention. Figure 2 is a vertical cross-section on line 11-11 of Figure 1, Figure 3 is a partial plan view of another embodiment of this invention, Figure 4 is a vertical cross-section on line IV-IV of Figure 3 Figure 5 is a partial plan view of another embodiment of this invention, Figure 6 is a vertical cross-section on line VI-VI of Figure 5; and Figure 7 is z vertical cross-section on line VIl-VIl of Figure 5. Referring now to the drawings, wherein like reference numerals designate identical of corresponding parts throughout the several views, and more particularly to Figures 1 and 2 thereof, one embodiment of the semiconductor integrated circuit device of this invention is illustrated. In Figure 1 and Figure 2, on the upper surface of the n-type semiconductor substrate (1) is provided an insulation layer (2). The substrate (1) is of silicon (Si) and the layer (2) is made of silicon oxide (SiO2). The insulation layer (2)- has a thickness of about seven or eight thousand angstroms and is formed by chemical vapour deposition technique, and the polycrystalline silicon layer (3) covers selected portions thereof with a thickness of about three thousand angstroms. Initially the polycrystalline silicon layer (3) is formed to cover the whole surface of the insulation layer (2), and subsequently it is partially etched away by a photoengraving process. The addition of an impurity, such as phosphorus, boron, or the like, to the polycrystalline silicon layer (3), reduces its sheet resistance to about EMI5.1 The surface of the polycrystalline silicon layer (3) is then oxidized using a thermal oxidation process to form a silicon oxide layer (4). The silicon oxide layer (4) has a thickness of about one thousand angstroms and has two contact holes (5) and (6). The holes (5) and (6) are formed by the photo-engraving process. Thereafter a second polycrystalline silicon layer (7) is formed over the silicon oxide layer (4) with a thickness of about three of four thousand angstroms and makes contact with the first polycrystalline silicon layer (3) through the contact holes (5) and (6). The second polycrystalline silicon layer (7) is formed in substantially the same pattern as the first polycrystalline silicon layer (3) and operates as the main wiring layer. An insulation layer (8) is formed to cover them. The insulation layer (8) is made of silicon oxide and has a thickness of 1.3 micron. In this embodiment, the insulation layer (8) is formed by a chemical vapour deposition technique. After the covering process, two contact holes (9) and (10) are formed by photo engraving process. Through the two contact holes (9) and (10), aluminium layers (11) and (12) applied over selected portions of the insulator layer (8) make contact with the second polycrystalline silicon layer (7). The aluminium layers (11) and (12) are connected through the polycrystalline silicon layers (3) and (7) to circuit elements formed on the substrate. Further, the aluminium layer (13) positioned on the insulator layer (8) crosses over the first and second polycrystalline silicon layer (3) and (7). As the aluminium layers (11) and (12) and the polycrystalline silicon layers (3) and (7) operate together as wiring layers, their total resistance is low. The resistance of the aluminium is very low, but that of the polycrystalline silicon is higher than the aluminium. Therefore the polycrystalline silicon layers (3) and (7) are connected in parallel, so that their resistance is about one half of that of one polycrystalline silicon layer alone. Further, as the change in level at the edge of the two polycrystalline silicon layers is made less abrupt by the existence of the silicon oxide layer (4), the aluminium layers (11) and (12) will not be pierced by the edge. In order to further reduce the abruptness of the change of level, the layer 7 can be made slightly smaller so that its edge does not coincide with that of layer 4. Figures 3 and 4 show a second embodiment of this invention. On a P type semiconductive substrate (21), a thick film silicon oxide layer (22) is formed by using a selective oxidation process. Next, the first polycrystalline silicon layer (24) is formed on the selected portion of the silicon oxide layer (22). This layer (24) operates as the secondary wiring layer for a further polycrystalline silicon layer (25) formed thereover. The polycrystalline silicon layers (24) and (25) become conductive by doping with an impurity such as phosphorus, boron or the like. The polycrystalline silicon layer (24) is covered by a silicon oxide layer (26). The silicon oxide layer (26) has two contact holes (27) and (28) formed by a photo-engraving process and is formed by thermal oxidation of the surface of the polycrystalline silicon layer (24). A silicon oxide layer (23) forming the gate of a MOS FET and having a thickness of 10002 is formed at the same time, simplifying the manufacturing process. The second polycrystalline silicon layer (25) is then formed over the layer 26 and the exposed portions of layers 22 and 24. The polycrystalline silicon layer (25) thus operates as the gate electrode of the MOS FET and as a wiring layer, being connected in parallel with the first polycrystalline silicon layer (24) through the two contact holes (27) and (28) in order to decrease the resistance. The source region (29) and the drain region (30) of the NOS FET are formed in the substrate (21) by diffusing phosphorus as an N-type impurity using the gate silicon oxide layer (23) and the polycrystalline silicon layer (25) as a mask. Figures 5 and 6 show the third embodiment of this invention. In this embodiment, a plurality of NOS FETs are regularly arranged in the semiconductor substrate (31), and constitute a memory array. They are formed in the following way: A thick film silicon oxide layer (52) is formed on the selected portion of the p-type semiconductor substrate (51) by using a selective oxidation process. The thickness thereof is about seven or eight thousand angstroms. Next, the gate silicon oxide layer (33) of the MOS PETs is formed using a thermal oxidation process. The thickness thereof is of about one thousand angstroms. After that, the first polycrystalline silicon layer (34) operating both as a set of gate electrodes and as a wiring layer, is formed on the selective portion of the silicon oxide layers (32) and (33). The first polycrystalline silicon layer (34) is then covered by silicon oxide layer (35). The silicon oxide layer (35) has contact holes (36) and is formed by thermal oxidation of the first polycrystalline silicon layer (54). Then, the second crystalline silicon layer (37) is formed over the first polycrystalline silicon layer (34) in order to decrease the resistance of the wiring layer. These two layers (34) and (37) are connected through the holes (36). The polycrystalline silicon layers (34) and (37) are made conductive by doping with a suitable impurity. Next the silicon oxide layer (35), the first polycrystalline silicon layer (34) and the gate silicon oxide layer (33) are etched using the second polycrystalline silicon layer (37) over the channel region of the MOS FETs as the mask so as to leave suitable portions positioned over the channel region of MOS FET to form masks for forming the source and drain regions. In this way these layers (33), (34) and (35) will be formed with the same width as the second polycrystalline silicon layer (37). Thereafter, an n-type impurity is doped into the p-type substrate (31), and the source regions (38) and the drain regions (39) are formed therein. In this way, as the layers (33), (34), (35) and (37) with the same width are used as the mask, the length between source and drain regions (38) and (39) is equal to the width of the layers (34) and (37), (see Figure 7) so the electric field of the gate electrode (34) and (37) will be uniformly applied to the channel region. This method of construction, avoids the possibility of the layer (37) being formed out of register with the layer (34), which could cause the length of the channel region to be non-uniform because of the gap between the two layers (34) and (37), so that the electric field of the gate electrode (34) and (37) would become non-uniform and the characteristics of the MOS FETs would become inferior. According to this embodiment of the invention the channel length of MOS FET is made more uniform and the resistance of the wiring layer and the gate electrode is kept very low, so that the circuit will be able to operate at high speed and the whole device will be of compact construction and have superior electrical characteristics. Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. For example, the connection between the first and second polycrystalline silicon layers can be accomplished by a greater number of contact holes or they may be laminated directly on one another. Then the connecting resistance may be made smaller, but the positioning of two layers and the whole process will become more critical, because the wiring pattern is generally very complicated. Another possibility is that the contact holes for connecting the two layers can be formed at the same time that the direct contact holes, connecting the polycrystalline silicon layer and the diffusion layer in the substrate, are formed. Then the process will be simplified. Further, the thermal oxidation process can be substituted by a chemical vapour deposition process, and a predoped polycrystalline silicon layer may be used instead of doping impurity into the polycrystalline layer during the manufacturing process.

Claims: CThAI#±S 1. A semiconductor integrated circuit device comprising: a semiconductor substrate (1) on which an insulation layer (2) is formed; a first wiring layer (3) formed of semiconductive material and positioned on said insulation layer; and a second wiring layer (7) formed of semiconductive material, formed over said first semiconductor layer, and connected in parallel to said first wiring layer. 2. A semiconductor integrated circuit device according to claim 1 wherein the first wiring layer is covered by a second insulation layer (4) which has at least two contact holes (5, 6). A Asemiconductor integrated circuit device according to claim 2 which comprises a third insulation layer (8) formed on the second wiring layer (7) and a conductive layer (11, 12) positioned on said third insulation layer. 4. A semiconductor integrated circuit device according to claim 3 wherein the first wiring layer (3) forms the gate electrode of a field effect transistor which is formed in the semiconductor substrate. 5. A semiconductor integrated circuit device according to claim 3 wherein the second wiring layer is operated as a gate electrode of a field effect transistor which is formed in the semiconductor substrate. 6. A semiconductor integrated circuit device according to claim 3 wherein the first wiring layer (3) has substantially the same configuration as the second wiring layer (7). 7. A semiconductor integrated circuit device comprising: a semiconductor substrate (31) incorporating source and drain regions (58,39) of a plurality of field effect transistors; an insulation layer (32) formed on said semiconductor substrate; a first semiconductor wiring layer (34) positioned on said insulation layer and forming a set of gate electrodes for said plural field effect transistors, and a second semiconductive wiring layer 37 formed over said first semiconductive wiring layer and connected in parallel with said first semiconductive wiring layer. 8. A semiconductor integrated circuit device according to claim 7 which comprises a second insulation layer (35) covering the first semiconductive layer (L) and having at least two contact holes (36). 9. A semiconductor integrated circuit device according to claim 8 wherein the first wiring layer (34) forming the gate electrodes has the same width as the second wiring layer thereover (37). 10. A semiconductor integrated circuit device according to claim 8 wherein the channel length of the plural field effect transistors is the same length as the width of the first and second semiconductor layers formed over the channel regions of the field effect transistors. 11. A semiconductor integrated circuit device according to claim 10 wherein the first wiring layer 34 has substantially the same configuration as the second wiring layer (37).

Inventors: ASANO, MASAMICHI, IWAHASHI, HIROSHI
Applicants: TOKYO SHIBAURA DENKI KABUSHIKI KAISHA
Application year: 1980
Main classification: H01L23
IPC codes: H01L21, H01L23, H01L29, H01L27