INTEGRATED SEMICONDUCTOR DEVICES

Abstract: The device has a chip (A) with a functional circuit (FUN) in a central area and input (li) and output (lo) interface circuits in peripheral areas. Each interface circuit (li, lo) is built up by a group of circuit elements. The circuit elements are the same for each group and provide an input stage (F₁) an intermediate amplifying stage (F₂) and an output stage (F₃). By connecting the circuit elements of a group in different ways either an input (li) or an output (lo) interface circuit can be provided. Also, different threshold values for signals incoming to the interface circuit can be provided.

Description: INTEGRATED SEMICONDUCTOR DEVICES. This invention relates to integrated semiconductor devices. Generally, in an integrated semiconductor device a functional circuit which is responsible for providing the various functions which the device can perform is disposed in the central area of the chip of the device and an interface circuit responsible for signal transfer between the functional circuit and circuits external to the chip is disposed in a peripheral area of the chip. Figure 1 of the accompanying drawings illustrates schematically an integrated semiconductor device as previously provided. In Figure 1, A indicates a chip of an integrated semiconductor device, for example, a large scale integrated circuit (LSI). In the central area of the chip, functional circuit FUN is arranged, whilst interface circuits Ii, 10 are arranged in peripheral areas. The interface circuits Ii, I and the 0 functional circuit FUN are connected. In Figure 1, Ii is an input interface circuit which transfers a signal sent from a circuit external to the chip to the functional circuit FUN, whilst 10 is an output interface circuit which transfers a signal from the functional circuit FUN to a circuit external of the chip. In this existing semiconductor device the interface circuits are fixedly arranged and are each structured so as to provide either input or output functions exclusively. For example, input interface circuits are all fixed to the left side of the chips in Figure 1, whilst the output interface circuits are all at the right side. In such an integrated semiconductor device, since the input and output interface circuits are fixedly arranged and since only specified numbers of each type of circuit are available only at specified areas, locations of input/output terminals, the number of such terminals and the ratio of the number of input/ output terminals are subject to limitations which reduce the degree of freedom available. Moreover, when considering such a chip from the standpoint of customers who will design systems incorporating such integrated semiconductor devices, difficulties of designing a printed circuit board (PCB), which may depend on the combination of device circuits and peripheral circuits offered by a relevant device, is a very important problem, and various factors such as the limited number of input/output terminals of the device and the limited arrangement of such terminals may add extra difficulty in the design stage of the PCB and system. According to the present invention there is provided an integrated semiconductor device including a semiconductor chip having a functional circuit, an input interface circuit, for transferring a signal sent from a circuit external of the device to the functional circuit, and an output interface circuit, for transferring a signal sent from the functional circuit to a circuit external of the device, characterised in that a plurality of circuit element groups are provided on the chip, each group comprising circuit elements that can be selectively connected in different ways within that group, so that each group can provide either the input interface circuit or the output interface#circuit. An integrated semiconductor device embodying this invention can provide interface circuits which can be modified in circuit structure to adapt to a variety of input and output conditions, arranged in a peripheral area of the chip. An integrated semiconductor device embodying this invention is such that input and output interface circuits can be arranged at desired locations around the peripheral area of the chip of the device An integrated semiconductor device embodying this invention is such that input interface circuits having various threshold values can be located at desired locations around the peripheral area of the chip. Reference is made, by way of example, to the accompanying drawings, in which: Figure 1, as mentioned above, illustrates schematically an integrated semiconductor device as previously provided; Figure 2 illustrates schematically an interface circuit in a device embodying this invention before wiring connections are established; Figure 3 is a schematic diagram of an input interface circuit in an integrated semiconductor device embodying this invention; Figure 4 is a schematic diagram of an input interface circuit in an integrated semiconductor device embodying this invention; Figure 5 is a schematic diagram of an input interface circuit in an integrated semiconductor device embodying this invention; Figure 6 is a schematic diagram of an output interface circuit in an integrated semiconductor device embodying this invention; ; Figure 7 is a schematic diagram of a logical input interface circuit in an integrated semiconductor device embodying this invention; Figure 8 is a schematic diagram of a logical input interface circuit of an integrated semiconductor device embodying this invention; Figure 9 is a schematic diagram of a logical output interface circuit of an integrated semiconductor device embodying this invention; Figure 10 is a schematic diagram of a logical output interface circuit of an integrated semiconductor device embodying this invention; Figure 11 is a block diagram indicating an interface circuit and bonding pad arrangement of an integrated semiconductor device embodying this invention; Figures 12 to 16 are respective block diagrams indicating modifications in which connections between the interface circuits and bonding pads of Figure 11 are altered; and Figure 17 illustrates schematically an integrated semi-conductor device embodying this invention. Figure 2 shows an interface circuit of a device embodying this invention. In Figure 2, l1 is a power line; 12 is a ground line; F1 is an input stage of the circuit; F2 is an intermediate amplifier stage of the circuit; F3 is an output stage of the circuit. R1 to R6 are resistors belonging to these circuits; Q3 to Q6' Q8' Q9 are transistors; Q1' Q2' Q7 Transistors and diodes bearing the symbol are diodes. EMI4.1 are Schottky clamp type transistors and Schottky type diodes respectively. When these resistors, transistors and diodes are used in the ways indicated in the following table (i.e. when elements indicated by their symbols are actively employed in the circuits) and wiring connections are established as shown in Figure 3 to Figure 10, various kinds of input levels and output profiles can be attained, for the interface circuit. EMI5.1 <tb> <SEP> Element <tb> <SEP> Variations <tb> M;¸¸#{eQ3(}{; ;¸¸¸¸Q7Q8Q9#R{R3R##5R6F###5 <tb> <SEP> 2 <SEP> 0 <tb> <SEP> 3 <SEP> ¯ <SEP> Co <SEP> D <SEP> C) <SEP> O <SEP> oo <SEP> C) <SEP> O <SEP> iso <SEP> 5 <tb> <SEP> 4 <SEP> 000000000 <SEP> 006 <tb> <SEP> 5 <SEP> X <SEP> O' <SEP> o <SEP> 0 <SEP> O <SEP> 0 <SEP> = <SEP> 0 <SEP> 0 <SEP> ¯ <SEP> 7 <tb> <SEP> 6 <SEP> o <SEP> oo <SEP> QO <SEP> 8 <tb> <SEP> 7 <SEP> Qo <SEP> 000000 <SEP> o <SEP> O <SEP> 009 <tb> <SEP> 8 <SEP> 0 <SEP> 0 <SEP> O <SEP> OO- <SEP> O <SEP> O <SEP> O <SEP> O <SEP> O <SEP> O <SEP> O <SEP> O <SEP> O <SEP> 10 <tb> The circuit of Figure 3, which corresponds to variation 1 in the table, employs an input threshold voltage Vth of 1.5V, and can receive an input of conventional TTL (hereinafter referred to as C-TTL) level from an external circuit and realise signal transmission to the internal (function) circuit of a large scale integrated circuit (LSI) on the same substrate as the interface circuit. The circuit of Figure 4, corresponding to variation 2, employs an input threshold voltage Vth of 1.3V, just suitable for receiving an input of Schottky TTL (S-TTL) level and can realise signal transmission to the internal circuit of an LSI on the same substrate as the interface circuit. Further, the circuit of Fig. 5 employs an input threshold voltage Vth of 1.2V, suitable for receiving an input of LS-TTL level and can realise signal transmission to the internal circuit of an LSI on the same substrate as the interface circuit. The circuit operation of Figure 3 will now be explained. When the input terminal is at an L (low) level, the transistor Q3 comes ON. Thereby, since the base current of the transistor Q5 is cut off and Q5 turns OFF, followed by Q6 becoming OFF, setting the output terminal to H (high) level. In addition, when the input terminal is at an II (high) level, the transistor Q3 becomes OFF and base current for Q5 is supplied via the C-B (collector-base) shorted Q4 and thereby Q5 turns ON. As a result Q6 turns ON, setting the output terminal to L level. The reason why the threshold voltage is 1.5V will be explained below. VBE (base-emitter voltage) of transistor Q6 in the output stage is approx. 0.8V, VBE of transistor Q5 in the amplifier stage is approx. 0.7V, VBE of the transistor Q4 in tte input stage is approx. 0.7V. Therefore whether the base current is supplied to the transistors Q5 and Q6 via the route Power supply (11) - Resistor R1 - Q4 or not is determined by the fact that the sum of VBE .- 0.7V of the transistor Q3 and the input voltage Vx applied on the input terminal is 2.2V or higher or lower. For this reason, the threshold voltage becomes equal to Vx = 2.2 - 0.7 = 1.5V. The threshold voltages of the interface circuits illustrated in the other schematic diagrams of Figures 3 to 10 are determined in the same way. The circuit of Figure 6, which corresponds to variations 4 in the table, has an input threshold voltage Vth of 0.8V and transfers an input from an internal circuit of the LSI on which the circuit is provided to a circuit external of the LSI. The circuit of Figure 7, corresponding to variation 5 of the table, has a couple of inputs respectively for an input from an external S-TTL circuit with an input threshold voltage Vth of 1.3V, and for an input from an LSI internal circuit with Vth of 0.8V and transfers input signals to the internal circuit of LSI. The circuit of Figure 8, corresponding to variation 6, has a couple of inputs respectively for an input from an LSI internal circuit with V Vthof 0.8V, and from an external LS-TTL circuit with Vth of 1.2V, and transfers the input signals to the LSI internal circuit. The circuit of Fig. 9, corresponding to variation 7, has a couple of inputs, one for inputs from an external S-TTL circuit with Vth of 1.3V and one for inputs from LSI internal circuit with Vth Of O.8V, and transfers the input signals to the LSI external circuit. The circuit of Figure 10, corresponding to variation 8, has a couple of inputs, one for inputs from LSI internal circuit with Vth of 0.8V, and one for inputs from an LS-TTL external circuit with Vth of 1.2V, ¯th and transfers the input signals to an LSI (for example) external circuit. In the case of interface circuits of the two inputs type, when the inputs are H, H level, the output is L. In every other case the output is H level. tamely, these circuits operate as NAND gates. Figure 11 shows an interface circuit and bonding pad layout of an integrated semiconductor device embodying this invention. In this Figure, F1 is the input stage of Figure 2, F2 is the intermediate amplifying stage, F3 is the output stage, P is a bonding pad. As is apparent from the Figure, the input stage F1, the intermediate amplifying stage F2 and the output stage F3 are arranged in the shape of the character "L", and the bonding pad BP is located inside the arms of the L-shape layout. As shown in Figure 12, such a layout can be very convenient when the above circuits function as input interface circuits as shown in Figure 3, 4 and 5, by connecting the bonding pad BP and the input stage F1 with wire lead 1, such as aluminium lead etc. Namely, a signal coming to the bonding pad BP from outside the chip is transferred to an internal gate from the output stage. On the other hand, as shown in Figure 13, the layout is convenient for bonding pad BP and output stage F3 to function in an output interface circuit as shown in Figure 6 by connecting them with lead 1. Namely a signal sent from an internal gate of the LSI device passes through input stage F1, intermediate amplifying stage F2, output stage F3 and is transferred to the outside of the chip from the bonding pad BP. Moreover, as illustrated in Figure 14, following functions can be attained by using a couple of interface circuits I1, I2 adjacent to one another on the chip of the LSI device. Namely, interface circuit I1 is structured as an output interface and interface circuit I2 as an input interface circuit. In addition, the output stage F3 of the interface circuit 11 and the bonding pad BP, and this bonding pad BP and the input stage F1 of the interface circuit I2 are respectively connected by the wire lead 1. Thereby, the signal sent from an internal gate of the LSI is transferred to a circuit external of the chip of the LSI from the bonding pad BP via the input stage F1 of the interface circuit I1, intermediate amplifying stage F2 and output stage F3, and simultaneously transferred again to an internal gate of the LSI via the input stage F1 of the interface circuit I2, intermediate amplifying stage F2 and output stage F3. Moreover, as shown in Figure 15, interface circuits structured as in Figure 7 or Figure 8 can be provided with bonding pad BP and input stage F1 connected by wire lead 1. Thereby, the result of a logical operation between an input signal transferred via the bonding pad BP from a circuit external of the chip of the LSI and the signal sent from an internal circuit of the LSI is transferred to an internal circuit of the LSI Then, as shown in Figure 16, an interface circuit structured as in Figure 9 or Figure 10 can be provided; bonding pad BP' of an adjacent interface circuit and its input stage F1, and a bonding pad BP and the output stage F3 of another interface circuit are respectively connected by wire lead 1. Thereby, the result of logical operation between a signal sent from a circuit external of the chip of the LSI and a signal sent from an internal circuit of the LSI is transferred (to a circuit external of the chip). According to this invention, as explained above, input interface circuits and output interface circuits are not arranged fixedly as in the case of existing interface circuits as shown in Figure 1. Figure 17 illustrates schematically one possible desired layout which can be adopted by wiring, peripheral areas of an LSI device chip in accordance with an embodiment of this invention.

Claims: CLAIMS 1. An integrated semiconductor device including a seiconductor chip having a functional circuit, an input interface circuit, for transferring a signal sent from a circuit external of the device to the functional circuit, and an output interface circuit, for transferring a signal sent from the functional circuit to a circuit external of the device, characterised in that a plurality of circuit element groups are provided on the chip, each group comprising circuit elements that can be selectively connected in different ways within that group, so that each group can provide either the input interface circuit or the output interface circuit. 2. An integrated semiconductor device including a semiconductor chip, having a functional circuit disposed in a central area of the chip, and an input interface circuit, for transferring a signal sent from a circuit external of the device to the functional circuit, and an output interface circuit, for transferring a signal sent from the functional circuit to a circuit external of the device, disposed in a peripheral area of the chip, characterised in that a plurality of circuit element groups are provided on the chip, each group comprising circuit elenents that can be selectively connected in different ways within that group, so that each group can provide either the input interface circuit or the output interface circuit. 3. A device as claimed in claim 1 or 2, wherein the circuit elements of each group can be connected in different ways within that group to provide respective interface circuit configurations (either input or output) having respective different threshold values for signals incoming thereto. 4. A device as claimed in claim 1, 2 or 3, wherein the circuit elements of each group can be connected to provide an input stage, an intermediate amplifying stage and an output stage. 5. A device as claimed in any preceding claim, wherein the circuit elements of each group are disposed in a generally L-sbaped pattern, and each group is provided with a bonding pad disposed between the arms of the L-shaped pattern. 6. A device as claimed in claim 5, when read as appended to claim 4, wherein the bonding pad provided for a group is connected to the input stage when the elements of the group are connected to provide an input interface circuit, and the bonding pad is connected to the output stage when the elements of the group are connected to provide an output interface circuit

Inventors: OHBA, OSAMU, YOSHIDA, MAKOTO
Applicants: FUJITSU LIMITED
Application year: 1980
Main classification: H03K19
IPC codes: H01L21, H01L27, H03K19