SEQUENCE CONTROL DATA CONVERSION APPARATUS

Abstract: Sequence controller for writing data into an EPROM and a film on which the data to be written are recorded. Film (1) is provided by printing clock marks (2) and R W lines (3) on a transparent body and pasting opaque tapes onto data lines (4) according to a time chart to be written into the EPROM. Accordingly, the resultant data records are visible and it is easy to renew the data. In the sequence controller, a sync­ hronous clock pulse generator and gate devices operate so that the data are photoelectrically read out to be recorded in a RAM (59) in a short period of time as the film is passed along a path (20) after the EPROM (30) has been mounted. Thereafter, the data are written into the EPROM. Thus, the sequence controller can be of a small size and easy to operate.

Description: SPECIFICATION PFOTOE1±CTRIC WRITE-ONLY SEQUENCE CONTROLLER TECHINCAL FIELD The present invention relates to a photoelectric write-on; sequence controller provided with a program fìlm or sheet as input means. BACKGROUND ART A conventional sequence controller having a writing means and a reading means is very unreasonable and expensive although it ie used only for reading after the write-in of data. In order to remove such disadvantages, it should be attempted to provide a sequence controller having a single function. DISCLOSURE OF THE INVENTION In accordance with the present invention, the sequence ftcj troller is divided into a write-only sequence controller and a read-only sequence controller. The write-only sequence control- is provided to write data in the read-only memory (EPROM) and t; read-only sequence controller is provided with the EPROM and aod to produce an output of data in the EPROM. Since data may be written in a plurality of EPROM by one write-only sequence controller, an economical control system may be provided. Further, the conventional sequence controller is complicated to deal with control objects in great variety and a shieled person is necessary for programming and modifying the data. In addition, the handling operation of the system is complicated, a plurality of handling operations are required. For example, in order to program the data of 100 words X 8 bits, key switches must be operated at least 200 times. Accordingly, it is an object of the present invention to provide a sequence controller in which data programmings and mt fications are very simple and easy for anybody having no special technical knowledge, consequently secrets of the programming and modification being maintained. It is a further object of the present invention to provide a sequence controller which is of high fidelity, structured compactly and manufactured at an inexpensive cost. To this end, a sequence control system of the present invention comprises a transparent program sheet bearing a plurality of data lines which are formed by any means such as adhesive attachment of opaque material and arranged in the longitudinal direction of the sheet. The sequence controller allows a simple procedure of cutting and attaching opaque tape onto the transparent program sheet, and hence initial programming as well as modification of the program for any control sequence in extremely simple and easy. The program sheet is inserted into the read-only sequence controller from one side, whereby machines may be controlled. The sheet has a time chart formed by opaque adhesive tapes. The sheet is inserted into the devise of the present invention and extracted. The data of 100 words X 8 bits are written in a memory RAM built in the device, then the written data in the RAM is programmed automatically in an EPROM, after which the EPROM is removed The programmed EPROM is set in a read-only sequence controller whereby various machines may be controlled. The photoelectric write-only sequence controller of the preset invention may be made into a light device having a weight of 450 gr ,, neo a compact size. Thus, economical controller may be provided for automatization of machine and for energy saving. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a transparent program sheet of 5 sequence controller according to the present invention; Fig. 2 shows a time chart attached an opaque tape onto the transparent program sheet; Fig. 3 shows a front view of the sequence controller; Fig. 4 shows a back view of the sequence controller; Fig. 5 shows a transverse cross-sectional view of the sequence controller; Fig. 6 is a perspective view of the sequence controller; Fig. 7 shows a circuit of a photo-electric switching array of a sheet reader: : Fig. 8 shows a circuit of the present invention using an EPROM operated by three power supply sources; Fig. 9 is a timing diagram of program pulses; Fig. 10 shows another embodiment of the program pulse gen orator; Fig. 11 shows a timing diagram of a program pulse according to the circuit of Fig. 10; Fig. 12 shows another embodiment of the present invention; Fig. 13 shows a circuit having an EPROM operated by a single power source; Fig. 14 shows a timing diagrom of clock pulses. BEST MODE FOR EMBODYING THE INVENTION Referring to Fig. 1, numeral 1 is a transparent sheet, 2 are a plurality of write clock marks and 3 is an R/w line for generating signals for writing and reading which are printed by Q#que ink. 4 designates a plurality of parallel data lines and 5 is a scale having one hundred indications. A plurality of indications 6 correspond to the scale 5. Each indication 6 is in a central position between write clock marks 2, which aims to prevent any erroneous counting of data pulses. 8 is an index for positioning the sheet in a device bods and 9 is an arrow showing an insertion direction of the sheet. Fig. 2 shows a sheet in which eight steps time charts are provided by adhering opaque tapes. A dotted line a-a is an operational start line when the sheet is inserted into a sheet resit device as described herein after. Fig, 3 is a front view of the sequence controller of the present invention. Numeral 10 is a front panel, 11 is a power switch, 12 is a program sheet extracting slot, 13 is a pilot lamp, 14 is a supply cord, 15 is a fuse and 16 is a fastening screw. Fig. 4 is a back view of the sequence controller. 17 is a back panel, 18 is a program sheet inserting slot and 19 is o tening screw. As shown in Fig. 5, a sheet reader 20 comprises a light emitting panel 21 having a plurality of light emitting elements 22 and a light receiving panel having a plurality of light receiving elements 24 and both panels are engaged with a sliding inserting engagement so as to be faced with each other and supporter in grooves provided in panels 10, 17 to form a gap 25 for passing the program sheet. # printed wiring board 26 is secured to the light emitting panel 21, on which a resistor 27 for light emitting elements 22 is provided. Secured to the light receiving board 23, is a printed-wiring board 28 on which a memory , a gate, a crystal oscillator 29, a capacitance, resistors and an EPROM 30 having connector 31 are provided. The EPROM 30 is detachably fixed to the connector 31 by a lock lever 32 (Fig. 6). As shown in Fig. 5, a pair of supporting projections 33 for the board 28 and projections 35 for covers 34 are formed in panels 10 and 17. Opposite end portions of each cover 34 are outwardly inclined and bent at ends 36 to reinforce the portions. Both covers are abutted at bent ends 36 and supported between the supporting projections 35 and secured by L-shaped members 37 and screws 16 and 19. Referring to Fig. 7, the photo-electric switch array comprises a photo-electric switch unit R/W corresponding to the R/W line 3 in Fig. 1, photo-electric switch unit X corresponding to the write clock mark 2 and eight photo-electric switch units Y1, Y2 .. .Y8 corresponding to data lines 4. Output of each photo-electric switch unit is shaped by a Schmitt trigger 38. A photo-transistor 24 of each of the photo-electric switch unit R/w and photo-elet switch unit X is turned off when the light from the light emitti diode 22 to the photo-transistor 24 is interrupted by the opaque portion of the program sheet 1, so that the output of the circuit goes to a 1 and the output of the Schmitt trigger 38 goes to a O. The photo transistor opposite the transparent portion of the sheet is turned on, so that the output of the Schmitt trigger 38 becomes a 1. Each of the photo transistor of photo-electric switch units Y1, Y2 ... Y8 is emitter follower. Accordingly, the output of the Schmitt trigger 38 opposite the opaque portion is 1 and the output corresponding to transparent portion is 0. When the program sheet 1 is inserted into the device up to the indication 8, the light to light emitting diodes is interrupted, so that the output of the photo-electric switch unit R/W becomes 1 and the output of the Schmitt trigger 38 becomes 0. Thus, the device is changed to write-in mode. When the program sheet is retracted and the photo-transistor 24 of the switch unit R/W receives the light, the output of the switch unit R/W goes to 0 and the output of the Schmitt trigger 38 goes to 1, so that the device is automatically changed to programming mode to EPROM as hereinafter described. Feferring to Fig. 8, system supply voltage VCC is obtained by an AC/DC converter 40 and supply voltages VBB (-5V), VDD (+12V) and VPRG (+26V) are applied to an EPROM 30 from#DC/DC converters 41, 42 and 43 through a control circuit 44. When a signal "1" is applied to the input 45 of the control circuit 44, program pulses to the EPROM is cut off, and when the signal is 0, program pulses are supplied to the VpRG of the EPROM. When the power switch 10 is turned on, entire circuit is reset byadifferentiation pulse from a differentiating circuit comprising a capacitance 46 and a resistor 47. More particularly, a differentiation pulse "1" is applied to a set input S of a flip-flop 50 through a 2-input NAND gate 49, so that the output Q goes to 1. Thus: A. Since a 1 is applied to a reset R of a binary counter 53 through an inverter 51 and 2-input NAND gate 52, all outputs are Outs. (When reset R = 0, the binary counter 53 divides the output of the crystal oscillator 29 to produce a read clock pulse train from On and to produce a program pulses from Qn-1.) Therefore, the read clock pulse train and program pulses are disappeared. B. A 1 is applied to a reset R of a binary counter 58 through a 2-input NAND gate 57 to clear it. C. A O is inputted in a chip-enable CE2 to cause it to the non-selected state. D. The program lamp 13 is turned off. Under such a condition, the EPROM 30 is inserted into the connector 31 and secured by the lock lever 32. Although the auto-reset circuit of Fig. 8 uses the differentiation pulse by the differentiating circuit, a differntiation pulse by an integrating circuit may be used. Then, the program sheet 1 is inserted into the device from the opening 18 to the indication 8. The output of the photoelectric switch unit R/W is 0, which is write-in mode. That is, a 1 is inputted in the reset R of the flip-flop 50 through an invertor 60. Thus, the output of the invertor 51 changes to 1: A. The input of CE2 of the RAM 59 is change to 1 to keep it in the selection state. B. Inputs of a gate 57 are l's, a reset R of a binary counter 58 is 0. C. A 1 is inputted in a reset R of the binary counter 53 through a gate 52, so that outputs of the clock pulse train and program pulses are stopped during the write-in mode. D. Inputs of NOR gate 62 ofa differentiation pulse generating circuit 61 are changes to O's, so that the gate is opened. Thus, the write-in mode is completed. Then, the program sheet is retracted from the device. One hundred of clock pulses are inputted in the clock terminal C of the binary counter 58 through a gate 55 to address the corresponding address cells of the RAM 59 through address lines Q1, Q2 . .07. On the other hand, the output of the gate 55 is applied to an input R/W of the RAM 59 through the differentiation pulse generating circuit 61 in synchronism with the clock pulse. By the R/W signal, eight steps data (Fig. 2) from photo-electric switch units are written in address cells of the RAM 59 which are addressed by the binary counter 58. When one hundred clock pulses is counter in binary counter 58s the output of a 3-input NAND gate 63 will go to 0. That is, since binary number of one hundred is 1100100, address lines Q3, Q6, Q7 are l's, so that the output of the 3-input NAND gate 63 goes to 0. Thus, a 1 is inputted the reset R of the binary counter 5 through the gate 57 to clear it. When the R/W line 3 of the program sheet 1 passes the opert rsg line of the photo-electric switch unit R/W, the output of the switch unit R/W will go to 1 to convert the system into the pro- gramming mode. More particularly, A. The output of the photo-electric switch unit X goes to 1 to thereby open the gate of the clock pulse control gate 55. B. Since a 1 is inputted in the gate 62 of the differ entiation pulse generating circuit 61, the R/W line of the RAM 59 is changed to 1 to close the data input DIN and to open the data output Dolt. C. inputs of the gate 52 to to l's and the reset R of the binary counter 53 goes to 0. Accordingly, read clock pulses are generated from the gate 55 and program pulses are generated from the gate 56. The read clock pulses are inputted in the binary counter 58 through the gate 55, so that address cells in the RAM 59 and EPROM 30 corresponding to address lines Q1, Q2 ...Q7 are addressed. Data having been-previously written in the RAM 59 are programmed in address cells in the EPROM 30 in synchronism with the program pulse. When the binary counter 58 counts one hundred clock pulses the output of the gate 63 will go to 0. Thus, a binary counter 64 counts one. Since a O is applied to the gate 57, the binary counter 58 is cleared. Accordingly, the binary counter 58 counts again the read clock pulses. At every cycle end, the binary counter 64 counts one. For example, in the case that the program loop number from the RAM 59 to the EPROM 29 is 384, the binary number of 384 is 11000000. In this case, two inputs of the 2-input NAs-D gate 65 are connected to terminals Q7,Q8 of the binary counter 64. By such the connection, when the binary counter 64 counts 384 program loops, the output of the gate 65 will go to 0 which is inputted in the set input S of the flip-flop 50 through the gate 49. Thus, the output Q of the flip-flop 50 goes to a 1 : A. The input of the gate 52 goes to O so taht clock pulses and program pulses are stopped. B. The binary counter 58 is cleared. C. The CE2 of the RAM 59 goes to O, so that the RAM 59 becomes to non-slected state. D. The pilot lamp 13 is turned off to indicate the completion of the program in the EPROM 30. Then the EPROM 30 is extracted. Fig. 3 shows the timing diagram of the program pulse generating circuit. The program pulse shown by the hatching line is generated from the gate 56 in synchronism with the clock pulse On and with 1/4 cycle advance phase difference. Accordingly, data is written in the address 0 of the EPROM. Fig. 10 shows an example of the program pulse genarating circuit using a type-D flip-flop, timing diagram of which is shown in Fig. 11. The output Qn-1 of the binary counter 53 is generated through the type-D flip-flop 69 in synchronism with the output On and with 1/4 cycle advanced phase difference. As will be seen from Fig. 11, the width of the program pulse is twice as long as the program pulse of Fig. 9. Therefore, the number of the program loop necessary to write-in from the RAM to EPROM is half as much as Fig. 9 and hence the time is half. Fig. 12 shows an example in which a RAM 66 having a common input and outout is used. Input data buses are connected to the I/O lines of the RAM 66 through 3-state buffers 67 and output data buses are connected to data inputs D1, D2 ...D8 of the EPROM 30. Each 3-state buffer 67 is controlled by a disable line 68. More particularly, when the disable line 68 is 1, the gate of the 3-state buffer 67 is closed and when the disable line 68 is 0, the gate of the 3-state buffer 67is opened. Thus, in the write-in mode, data is written in memory cells in the RAM 66 through I/O lines in synchronism with the differentiation pulse synchronized with the write-in clock pulse. In the program mode, since the R/W line of the RAM 66 is held to 1, the gate of the 3-state buffer 67 is closed. Data written in the RAM 66 are programmed in addressed cells of the EPROM 30 in synchronism with the program pulse. g. 13 shows another example of write-only sequence con roller in which data are programmed in a read-only memory EPROM 30' operated by a single power source of +5v. The system power source VCC is obtained by an AC/DC convertor and +25V supplied to Vpp of the EPROM 30' is obtained by a DC/DC convertor 70. When the input 71 of the convertor 70 is 0, +25V is supplied to the Vpp terminal, when the input is 1, the supply is stopped. In the EPROM 30', a N-bit program is added at every addressing and the program is completed upon one loop. At that time, the width of the program pulse added to the termianl CE/PRG is about 50ms per one address. Frequency of the crystal oscillator 29 is decided so as to obtain the program pulse of 50ms. The frequency is divided by 2-stage binary counters 53 (not always two stages), divider outputs QA, QB, QC, and QD of the binary counter are inputted in a 4-input NAND gate 72. In the write-in mode, the divider outputs are stopped, and in the program mode, pulses are generated from the outputs QAF QB, QC, and QD. As shown in Fig. 14, a read clock pulse is generated from the 4-input NAND gate 72 at every eight counts of QA. The output of the gate 72 is connected to one of inputs of a 2-input NAND gate 73 and a line 74 is connected to the other input of the 2-input NAND gate 73. The output of the gate 73 is applied to reset R of a flip-flop 75. Also, divider outputs QAT QB QC and QD are inputted in a 4-input NAND gate 76. The QA is connected to the gate 76 through an invertor 77. Therefore, during the term in which the divider outputs QA, QB, QC and QD change from 1111 to 1000, which is equal to one cycle of the output QAF the gate 76 produces output 0. When the power is supplied, a differentiation pulse generated from integrating circuit comprising the capacitance 46 and resistor 47 is applied to the flip-flop 50 through the Schmitt trigger 48 and the invertor 49 to reset all of circuits. Then, when program sheet is inserted into the sheet reader, the system is converted to the write-in mode. While the program sheet passes through the sheet reader, data are written in the RAM in synchronism with the write-in pulse. When the program sheet has passed the sheet reader, the system is automatically changed to the program mode. Since both inputs of the 2-input NAND gate 52 are l's and the reset R of the binary counter 53 is 0, divider outputs QA, QB, QC and QD generate pulses . Read cloc pulses are produced from the gate 72, program pulses are inputted in the terminal CE/PRG of the EPROM through the gate 76, flip-flop 75 and invertor 78. Read clock pulses are inputted in the binary counter 58 through the gate 55, so that address cells of the RAM 9 and EPRt 30' corresponding to address lines Q1, Q2 ... Q7 are addressed. And data written in the RAM are programmed in address cells of the EPROM 30' in synchronism with the program pulse. When the binary counter counts one hundred of read clock pulses, the output of the gate 63 will go to 0. Thus, a 1 is applied to the flip-flop 50 through the gate 49 to reset all of circuits. Since the line 74 goes to 0, a 1 is applied to the reset R of the flip-flop 75 through the gate 73. Thus, aOis inputted in the CE/PRG, so that the EPROM may be extracted for that period. PROBABILITY OF INDUSTRIAL EXPLOITATION In the write-only photo-electric sequence controller according to the present invention, programming and modifying of data may be easily carried out. By inserting the program sheet into the controller and extracting the sheet from it, a plurality of data may be written in the EPROM. The controller may be made into a light weight, for example 450gr and into a compact sizes Thus, the controller is contributory to the automatization and energy saving for machines and apparatus in the wide industrial field.

Claims: What is claimed is: 1. A photo-electric write-only sequence controller comprising a transparent program sheet bearing a series of write clock marks and a plurality of data lines which are formed of opaque material and arranged in the longitudinal direction of said sheet, a sheet reading device; said sheet reading device comprising; means for passing said sheet along a path, a plurality of light-emitting elements disposed in the lateral direction at the entrance of said path, and a plurality of light-receiving elements each of which is corresponding to each of said light-emitting elements and arranged to generate data when light from the corresponding light-emitting elements is interrupted by said write clock marks and data lines of said sheet, memory means (RAM) for memorizing said data in synchronism with said write clock marks: : means for generating read clock pulses for reading said data; gate means for applying program pulses to a read-only memory (EPROM) in synchronism with said read clock pulses for programming of the data; gate means for programming said data written in said RAM in said EPROM; and gate means for controlling said data and pulses. 2. A photo-electric write-only sequence controller according to claim 1 wherein said program sheet has a scale of one hundred indications, said R/W line is used for changing the write to the read of data, said write clock mark is used for write clock pulse, aid data line forms a time chart with adhesive opaque tapes, and indications on one side of the data line is aligned on a central line between the clock marks. 3. A photo-electric write-only sequence controller to claim 1 further comprising gate means in which the output of a differentiation pulse generating circuit in applied toaflip-flop (50), the output of which is connected to a gate (57) for controlling a chip enable of a RAM (59) and binary counter (58) and to a frequency divider (53), so that said RAM (59) is changed to the non-selected state, the binary counter (58) and the frequency divider are cleared to reset all of the circuits. 4. A photo-electric write-only sequence controller to claim 1 further comprising a photo-electric switch unit R/W, the output of which is connected to a differentiation pulse generating circuit (61), read clock pulse control gate (52) and reset of a flip-flop (50), the circuit is changed to a write mode in to RAM (59) and to a program mode into an EPROM (30) according to the level of the output of the photo-electric switch unit, and the photoelectric swithc unit R/W is controlled by opaque lines of the program sheet. 5. A photo-electric write-only sequence controller to claim 1 further comprising gate means characterized in that when the photo-electric switch unit R/W is cut off, A. the input of CE2 of the RAM (59) is change to 1 to keep it in the selection state, B. a reset of a binary counter (58) is 0 through a gate (57) C. the output of the binary counter (53) goes to 0, D. inputs of a NOR gate (62) of a differentiation pulse generating circuit are changes to O s, so that the gate is opened. 6. A photo-electric write-only sequence controller to claim 1 further comprising gate means characterized in that when the photo-electric switch unit R/W is on, A. a read clock pulse gate (55) is opened, B. a R/W line of the RAM (59) is fixed to 1 through the differentiation pulse generating circuit (61), C. a frequency divider (53) is activative through a gate (52). 7. A photo-electric write-only sequence controller to claim 1 further comprising gate means characterized in that outputs of a plurality of photo-electric data switch units are connected tc I/O bus line of a RAM(66) and to data input bus lines of an EPROM (30) through a 3-state buffer (67) and the output of a differentiation pulse generating circuit (61) is connected to an R/W line of a RAM (66) and to a disable line (68) for controlling the 3-state buffer. 8. A photo-electric write-only sequence controller to claim 1 further comprising a case comprising a pair of shells, each lonai- tudinal end portion of shells is outwardly inclined and has an inwardly bent end, opposite ends of the shells are abutted to each other and engaged in guide grooves formed in opposite front and back panel. 9. A photo-electric write-only sequence controller to claim 1 further comprising a sheet reader comprising a light emitting pannel having a plurality of light emitting elements and light receiving panel having plurality of light receiving elements, both panels are provided with printed-wiring board and are engaged with a sliding insertion engagement so as to be faced with each other to form a gap for passing the program sheet. 10. A photo-electric write-only sequence controller to claim 1 further comprising gate means characterized in that power sources Vcc, VBB, VDD, obtained by a switch regulator system are directly applied to corresponding terminals of a EPROM (30), VPRG obtained by setting-up the VCC is applied to a control circuit 44, and program pulses are inputted to VPRG of an EPROM (30) through the control circuit (44) in synchronism with the read clock pulse and in advance of it. 11. A photo-electric write-only sequence controller to claim 1 further comprising gate means characterized in that the output of a gate (72) having divider output Q As QB , QC , and QD as input is connected to the first input of a 2-input NAND gate (73) the output line (74) of an invertor (51) is connected to the second input of the 2-input NAND gate, the output of 2-input the RAND gate (73) is connected to the reset terminal of a flip-flop (75) divider outputs QB, QC, QD are connected to a gate (76), QA is connected to the gate (76) through an invertor, the output of the gate (76) is applied to CE/PRG of an EPROM through the flip-flop (75), a clock pulse is supplied from the gate (72) to a binary counter through gates (72) and (55) in the program mode so that a RAM(59) and EPROM (30') are addressed by corresponding address lines, and program pulses are applied to the CE/PRG of the EPROM through the gate (76) and flip-flop (75) for programming the data written in the RAM to the EPROM. 12. A photo-electric write-only sequence controller to claim 1 further comprising gate means characterized in that a control input of a DC/DC convertor (70) is connected to an output of a gate (52) for controlling a binary counter (53), a signal 0 is inputted in the DC/DC convertor (70) during the program mode for supplying the voltage to Vpp of an EPROM (30'), a signal 1 is inputted to the DC/DC convertor (70) during the write-in mode and after programming for cutting the voltage to Vpp of the EPROM (30').

Inventors: KUZE, YOSHIKAZU
Applicants: KUZE, YOSHIKAZU
Application year: 1980
Main classification: G11C7
IPC codes: G11C16, G05B19, G11C17, G11C11