SEMICONDUCTOR MEMORY DEVICE

Abstract: A memory device is disclosed forming a high-density semiconductor device, which comprises a semiconductor substrate (202) of a first conductivity type, first and second semiconductor regions (203) (204) of a second conductivity provided in the semiconductor substrate, the first and second semiconductor regions defining a channel region (213) therebetween at the surface of the substrate, an insulator film (206) disposed on the channel region, a conductive layer (210) formed on the insulator film, means for producing depletion layers (211) (2 from the first and second semiconductor regions in such a manner that the depletion layers contact with each other to isolate the channel region from the substrate, means for operatively shrinking and thereby separating the depletion layers for selectively feeding majority carriers of the substrate to the channel region at a density higher than that of the substrate, and a means for detecting the existence of the accumulation of the majority carriers in the channel region representing the stored information.

Description: Semiconductor memory device The present invention relates to memories, and more particularly to semiconductor memories that can be realized in the form of an integrated circuit. At present, the so-called one-transistor memory in which a memory cell consis-ts- of a single transfer-gate transistor and a single capacitor is ntidelytutilized as a randon access memory (RAM) - having the largest integration density on a semiconductor chip. In such a one transistor memory, a metal-insulator- semiconductor (MIS) structure is employed to form the transfer-gate transistor and the capacitor. In this type of memory, whether an electric charge is stored in the capacitor or not is made to correspond to the information of either TIOWI or "1". In order to hold the state of either "O" or "1" a voltage corresponding to that state is periodically applied to the MIS capacitor to perform refresh operation, since the charges stored in the capacitor tend to be leaked out. The state of charge storage or non- storage in the capacitor can be changed and established in an extremely short time period. In such a prior art RAM, a signal read out on a bit line is detected as a potential charge -- bV on the bit line caused by the capacitive division of the charge stored in the MIS capacitor between the bit line capacitance and the MIS capacitor. Where the bit line capacitance has no charge, the change oV in voltage of the bit line is larger when a charge is stored in the MIS capacitor than when a charge is not stored, so that the states of "O" and "1" can be distinguished. However, the prior art RAM has a big disadvantage, based on the fact that the electric charge used for causing the potential change in the bit line is only the charge which has been stored in the MIS capacitor. If the capacitance of this MIS capacitor is too small as compared to the capacitance of the bit line, then the potential change & appearing on the bit line upon read-out would be indetectably small. While, if it is intended to increase the capacitance of the MIS capacitor to increase the potential change #V, then it is necessary to enlarge the area of the MIS capacitor, to reduce the thickness of the gate insulating film, or to increase the capacitance per unit area by employing a material having a large dielectric constant as the gate insulating film. However, enlargement of the area of the MIS capacitor will result in wide lowering of the degree of circuit integration, and if the gate insulating film is made thin, the withstand voltage of the gate insulating film is lowered, resulting in damage of a large amount of MIS capacitors. Furthermore, if alumina or silicon nitride having a large dielectric constant is used for the insulating film, there occurs a problem in the stability of the electric performance of the MIS capacitor. As described above, the increase in the capacitance of the MIS capacitor is, in any event, accompanied by various disadvantages. Therefore, it is one object of the present invention to provide a memory in which reading of information can be achieved with high stability. Another object of the present invention is to provide an integrated memory circuit in which a high degree of circuit integration can be achieved. The memory according to the present invention comprises a semiconductor substrate of one conductivity type, first and second regions of the opposite conductivity type provided in the semiconductor substrate, a channel region between the first and second regions, an insulating film on the channel region, a control electrode provided on the channel region, means for producing a depletion layer extending from the first region towards the second region, means for producing a depletion layer extending from the second region towards the first region, and means coupled to the control electrode for inducing excessive majority carriers to a portion of the channel region at the surface of the channel region to make the density of majority carriers in that portion higher than that in the semiconductor substrate. The excessive majority carriers are retained, or stored, in the induced portion except which the depletion layer extends into the channel region, and existence or non-existence of the excessive majority carriers corresponds to the information stored in the memory cell. The existence or non-existence can be detected by the value of the current flowing between the first and second regions. More particularly, when the excessive majority carriers exist in the channel region, a punch-through current is suppressed, while when the excessive majority carriers do not exist, the punch-through current is generated between the first and second region. The first and second regions are coupled respectively to a word line and a digit line. The fabrication of the memory cell of the present invention can be realized by the well-known technique to form a usual insulated-gate field effect transistor (IGFET), wherein the first and second regions of the memory cell correspond to a source and a drain of IGFET and the control electrode to a gate electrode of IGFET. It is favorable for the purpose of retaining the excessive majority carriers to form one of the first and second regions in a ring- shaped pattern surrounding the other and the other in an island pattern disposed within the ring- shaped pattern. In this case the aforementioned control electrode takes a ring- shaped configuration covering the ring- shaped channel region between the two regions. According to the present invention, an advantage is attained that a capacitor to be used for storing a large amount of electric charges, such as the prior art MIS memory capacitor, is unnecessary, because storage of information is effected by either accumulating or depleting the majority carriers of the substrate in the channel region and on the other hand reading of the stored information is effected by the current flowing between the first and second regions which correspond to the source and the drain of the MIS transistor. In other words, the memory cells can be made small, so that it is possible to realize a high degree of circuit integration. Also a further advantage is attained that since the read current can be chosen large, even if the bit line capacitance is large, it is possible to make a sufficiently large potential change arise on the bit line, so that detection of the read signal becomes very easy. Therefore, the memory cell of this invention is suitable for a large capacity memory. In the memory according to the present invention, by extending depletion layers from the first and second regions to the channel region, a pocket region defined by the depletion layers can be formed in the vicinity of the surface of the channel region. Information is stored by accumulating the majority carriers in this pocket region or depleting the majority carriers. Upon reading, assuming that the majority carriers are not accumulated in the pocket regions, when a voltage is applied to one of the first and second regions (a backward voltage), the depetion layer extending from this region applied with the voltage would further extend largely towards the other region until it reaches the other region, and thereby the so-called punch-through current flows. This punch-through current is caused by injection of minority carriers from the other region. On the contrary, if the majority carriers ae accuiii#'Iated in the pocket region, then the punchthrough current would not arise or would arise only a little. As described above, according to the present invention, the existence of the excessive majority carriers in the pocket region is detected in an punch-through mode, and therefore reading can be achieved at a high speed. According to the present invention, as a source of the mojirity carriers the substrate may be used. Instead, a region of one conductivity type may be formed within one of the first and second regions so that the majority carriers may be supplied therefrom. Other features and advantages of the present invention will become apparent from the following description of embodiments, taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a cross-section view showing a memory cell according to a preferred embodiment of the present invention. Fig. 2 is a schematic circuit diagram showing a memory circuit composed of the memory cells illustrated in fig. 1. Fig. 3 is a cross-sectional-view. showing a modification of the memory cell in fig. 1. Fig. 4(A) to 4(F) are schematic cross-sectional views to be used for explaining the operation of the memory cell in fig. 3. Fig. 5 is a plan view showing one example of the semiconductor integrated circuit memory devices which realizes the memory circuit of fig. 2 and Fig 6(A) to 6(D) are cross-sectional views of the# integrated circuit memory device of fig. 5 taken in the positions and directions indicated by arrows a to d in fig. 5. Now one preferred embodiment of the present invention will be described with reference to fig. 1. Referring to Fig. 1, a MOS memory cell 201 has a MOS transistor structure comprising a P-type silicon substrate 202, an N-type source 203, an N-type drain 204, a gate insulating film 205, a gate 208, and metal wirings 206 and 207. The substrate 202 contains 3 a P-type impurity at a concentration of 3 x 1014/cm . The source region 203 and drain region 204 are formed by diffusion or ion implantation of phosphorus, and they have an impurity concentration of 1021/cm3 and a junction depth of 2.0 p. The channel length of the channel region 209 between the source region 203 and the drain region 204 is equal to 3.0 Ir, and the gate insulating film is formed of a SiOz film of 1000 g in thickness. While the gate 208 as well as the metal wirings 206 and 207 are made of aluminum, they could be made of any arbitrary wiring material. ¯ The depletion layers 211 and 212 formed by the source region 203 and the drain region 204, respectively, are made to have a width of 1.7 ,u by the built-in potential due to the PN-junctions per se when the respective regions are held at the ground level, and they can isolate the channel region 209 from the substrate 202. In this memory cell 201, when a backward voltage is applied between the source 203 and drain 204 and the substrate 202 or when they are held at an equal potential, that is a forward voltage is not applied between them, the depletion layers 211 and 212 are extended from the source 203 and drain 204 so that they can be connected at a position under the insulating film 205. Accordingly, the state of the majority carriers in the channel region 209 can be retained. Reading of the stored information can be effected by further extending the depletion layer 212 from the drain 204 until it reaches the source 203 and detecting either existence or non-existence of the punch-through current which corresponds respectively to non-existence or existence of majority carriers in the channel region. Fig. 2 shows MOS memory device including z memory cell in Fig. 1. In this diagram, gate electrodes (208) and substrate electrodes, respectively, of all the memory cells are respectively connected in common. Digit lines DI, D2 .... are respectively connected to the drain electrodes of the MOS transistors Mlls M12 ¯-..... M21 M22, ..... .... in the corresponding rows, whilewordlinesW1, lines are respectively connected to the source electrodes of the MOS transistors M11 M22 ¯ ..,.... in the thencorresponding columns. In Fig. 3 is illustrated one modification of the memory cell 201 shown in Fig. 2 . In this modification a source region 203' is formed in a ring shape. A drain region 204' is formed in a circular shape nearly at the center of the region of the substrate 202' surrounded by the source region 203'. On a channel region 209' between the source region 203' and the drain region 204' is formed a ring- shaped gate electrode 208' via a gate insulating film 205'. In this modified construction, the impurity concentrations in the substrate 202', source region 203' and drain regions 204' are apprdximately equal to those in the memory cell 201 in Fig. 1. Also the thickness of the gate insulating film is 1000 i and the channel lengthis 3.0 p. In this modification, since the majority carriers are preserved while being enclosed in the ring- shaped channel region, the state of the majority carriers can be stably retained for a long period. Now the operation of the memory cell shown in Fig. 3 will be described with reference to Fig. 4, in connection to the case where the memory cell is applied to the memory device in Fig. 2 as one memory cell M11. At first description will be made on write-hole-read of the information "0". It is to be noted that in the following operation the substrate terminal SUB is always rounded. Upon writing the information "0" in the memory cell Mull, the digit line D1, the word line W1 and the gate electrode terminal G are respectively brought to -3 V. At this moment, as shown in Fig. 4(A), the depletion layer 211' extending from the source 2031 and the depletion layer 212' extending from the drain 204' shrink, so that the isolation between the channel region 209' and the substrate 2022 is removed. Then, by the effect of the negative potential at the gate 208', positive holes 220 in the substrate 202' are accumulated in the channel region 209' as shown by arrows. In this way, writing of the information "0" is achieved. During this write operation, in the remaining memory cells other than the memory cell Mll, since both the word line and digit line are held at the ground potential or either one of the word line and digit line is held at -3 V, the overlap between the two depletion layers 211' and 212' cannot be released. Therefore, the state of the majority carriers in the channel region 209' can be retained, that is, the stored information can be preserved. Subsequently, when the writl:en information lloll is to be held, at first the word line W1 and the digit line D1 are returned to the ground level to again isolate the channel region 209' from the substrate 202' by means of the depletion larders 2111 and 212', and thereafter the gate electrode terminal G is returned to the ground level. Thus the accumulated positive holes 220 c ln be preserved in the channel region 209', as shown in Fig. 4(B). When the information "0" stored in the memory cell M11 is to Be read, the word line W1 is brought to +3 V, while maintaining the gate electrode terminal G at the ground level (or at a positive potential). Then the digit line D1 is held at the ground level. At this moment, as shown in Fig. 4(c), the depletion layer 212' extending from the drain 204' expands towards the source region 203'. However, since the positive holes are accumulated in the channel region 209' in this case, a punch-through current would not occur, or even if it occurs, the magnitude of the current is very small. This state is detected through the digit line D1 and interpreted that the information "0" has been stored in the memory -cell M1l. Thus reading of the information "0" can be achieved. Now description will be made on write-hold- read of the information "1". In this case also the substrate terminal is always held at the ground level. In this case, in response to the information "1" to be stored, the gate electrode terminal G is brought to +3 V which depletes the majority carrier in the channel region 209' while the digit line D1 and the word line W1 are respectively brought to -3 V similarly to the case of writing the information "1". At this moment, similarly to the case shown in Fig. 4(A), the depletion layers 211' and 212' shrink, so that the channel region 209' is coupled to the substrate 202'. However, at this time since the gate potential is a positive potential, the positive holes 220 in the channel region 209' are pushed back to the substrate 202' as shown in Fig. 4(D). Thus the channel region becomes a depletion state of positive holes, and thus writing of the information "1" is effected. During the above-mentioned write operation to the memory cell Mll, the other memory cells have only one of the source and the drain brought to -3 V or have both the source and the drain held at the ground level. In the former case, one of the depletion layers extending from the source and drain, shrinks. However, with the degeneration of only one depletion layer, the contact between the depletion layers 211' and 212' is still maintained, and hence the channel region 209' cannot be coupled to the substrate toy'. In the memory cell having both the source and the drain held at the ground level, of course, the channel region 209' is kept isolated from the substrate 202t. Therefore, when the information "1" is written in one particular memory ccli M11, the information stored in the other memory cells can be preserved. Subsequently, the digit line D1 and the word line W1 are returned to the ground potential to bring the depletion layers 211' and 212' into contact for isolating the channel region 209' from the substrate 202', thereafter the gate electrode terminal G is returned to the ground level. Thus a holding state of the memory cell M11 can be established as shown in Fig. 4(E). When the information "1" stored in the memory cell M11 is to be read out, the word line W1 is brought to +3 V while maintaining the gate electrode terminal G and the digit line D1 at the ground level. At this moment, as shown in Fig.4 (F), the depletion layer 212' extending from the drain 204' expands till the source region 203'. Consequently, by injection of electrons 221 from the source 203' to the channel region 209t, a punch-through current is produced between the drain 204' and source 203', and hence, reading of the stored information "1" can be achieved by detecting this punch-through current via the digit line D1. With reference to Figs. 5 and 6 , one example of a semiconductor integrated circuit structure of the memory circuit of Fig. 2 will be described. Digit lines D1, D2 are made of N-type semiconductor regions elongated in column directions provided in P-type semiconductor substrate 300. These digit lines have their depth of 2 microns as shown in Fig. 6 (A). Digit lines D1, D2 also serve as sources (S) of the memory cell such as Mull. A plurality of N-type regions 303 arranged in the column directions also serve as drains (D) of the memory cells. The N-type regions 303 have the same junction depth as those of digit lines D1, D2. The digit lines and N-type regions are fabricated at the same time by thermal diffusion of impurities or ion-implantation technique. A plurality of thick oxide regions 301 elongated in row and column directions and partially embedded in the surface portion of the substrate 300 are formed by selectively oxidizing the surface of the substrate 300. The thick oxide regions 301 isolate the respective rows of the memory cell matrix in the row directions. The thickness of the thick oxide regions 301 are about 1.5 micron. These thick oxide regions 301 especially surround channel regions 310 with the depletion layers extending from the drain (D) and source (S) so that the channel regions, especially the surface of the channel regions can be perfectly isolated from the substrate both in vertical and lateral directions. Word lines W1 - W4 are made of highly conductive metal layer such as aluminum layer elongated in the row directions and disposed on the thick oxide regions 301. These word lines W1 - W4 are connected to the drains (D) i. e. N-type region 303, via contact holes 306 as shown in Fig. 6 (C). Gates are made of polycrystalline silicon wiring layers 302 elongated in the column directions in parallel with the digit lines, as shown in Fig. 6 (B). The polycrystalline silicon wiring layers have a thickness of about 0.6 micron. The surface of the polycrystalline silicon wiring layers are thermally converted into its oxide to provide an insulator layer 307' for the word lines. The polycrystalline silicon wiring layers 302 are electrically connected in common. The thick oxide region 301 also isolates the column from neighbouring columns as well as the row directions as shown in Fig. 6 (D). In this connection, it may be possible to provide highly doped P-type region 320, i. e. the so-called channel stopper region, under the thick oxide region 301 for further inhibiting leakage between the columns. This channel stopper region is located so as not to electrically contact with the channel regions. While the present invention has been described above in connection to its preferred embodiments, it is a matter of course that the invention should not be limited only to the illustrated embodiments but it can be realized in various forms under various conditions of an impurity concentration and under various voltage conditions. In addition, while the channel region is isolated from the substrate by the depletion layers produced by the built-in potential in the above-described embodiments, the channel region may be isolated by producing depletion layers by an external electric field.

Claims: Claims 1. A memory comprising a semiconductor substrate (202) of one conductivity type, fist and second regions (203,204) of the opposite conductivity type provided in said semiconductor substrate, a channel region (213) located between said first and second regions, a control electrode (210) provided on said channel region via an insulating film (206), and means for extending depletion layers (211, 212) from said first and second regions so as to isolate said channel region from said semiconductor substrate, and means for selectively accumulating majority carriers of said semiconductor substrate in said channel region, the existence or non-existence of accumulation of said majority carriers in said channel region being made to correspond to the stored information, c h a r a c t e r i z e d by further comprising means for operatively shrinking the depletion layers from said first and second semiconductor regions in such a manner that both the depletion layers are separated from each other thereby to provide a carrier path between said channel region and said substrate, and that the accumulation of the majority carriers is performed through said carrier path. 2. The device according to claim 1 , c h a r a c t e r i z e d in that one of said first and second regions is formed in a ring-shape pattern and the other of said first and second semiconductor regions is formed in an island pattern surrounded by said ring-shape pattern. 3. The device according to claim 1, c h a r a c t e r i z e d in that said control electrode is formed of polycrystalline silicon. 4. The device according to claim 1, c h a r a c t e r i z e d in that said shrinking means includes means for controlling voltage between said semiconductor substrate and at least one of said first and second semiconductor regions.

Inventors: HAMANO, KUNIYUKI, OHTA, TOSHIYUKI
Applicants: NEC CORPORATION
Application year: 1980
Main classification: G11C11
IPC codes: H01L27, H01L21, G11C11, H01L29