CIRCUIT FOR ELECTRICALLY CONNECTING A VOLATILE MEMORY TO A POWER SUPPLY INPUT TERMINAL

Abstract: Backup power for the volatile cells (12) of a memory array is provided by an auxiliary backup battery power source which is automatically connected to the memory array power input node (14) in response to loss of power from the primary external power source. Primary operating current for the volatile cells (12) of the memory array is conducted through a first field effect transistor switch (20) having its gate (20 G) and drain (20 D) electrically connected to an external power input pin (18) and its source (20 S) electrically connected to the memory array power input node (14). Auxiliary operating current for the volatile cells (12) of the memory array is provided by a second field effect transistor switch (34) having its drain (34 D) and gate (34 G) electrically connected to an external control signal input pin (26) and its source (34 S) electrically connected to the memory array power input node (14). The first transistor switch (20) automatically establishes a conductive path from the external power input pin (18) to the memory array power input node (14) in response to the voltage of the power input pin (18) relative to the voltage of the memory array power input node (14) rising above the threshold voltage of the transistor (20), and automatically interrupts the conductive path in response to the voltage of the external power input pin (18) relative to the voltage of the memory array power input node (14) falling below the threshold voltage. The second transistor switch (34) automatically establishes and interrupts a conductive path from the control signal input pin (26) to the memory array input power input node (14) in response to the rise and fall of voltage on the control signal input pin (26) relative to the voltage of the memory array power input node (14).

Description: BATTERY BACKUP CIRCUIT FOR AN INTEGRATED MEMORY DEVICE BACKGROUND OF THE INVENTION Field of Invention: This invention relates generally to integrated circuit memory systems, and in particular to a data retention circuit for a volatile memory array. Description of the Prior Art: The generation of valid logic signals and the retention of data in integrated memory circuits having volatile memory cells depend in part on maintenance of power supply voltages within specified limits. In conventional integrated circuit memory devices, internal circuits sense the external voltage being applied to determine if it is sufficient for reliable operation. In response to a low voltage condition, control signals are generated which cause active chips to be de-selected and maintained in standby condition. This is usually carried out by means of true and complement chip select signals, CS and CS, respectively, which inhibit read/write operations until the low voltage condition has been corrected. During the period that a chip is in an unselected condition it is necessary to maintain the charge levels of the storage capacitors in the volatile memory cells so that stored data will be retained. Complementary MOS memories will hold state at reduced power supply voltage levels, but require additional processing steps. Some NMOS memories also limit power dissipation in the memory power circuit to approximately leakage levels, but unfortunately, significant power is dissipated in the peripheral drive circuits. Other data retention approaches require an additional external connector pin thereby rendering the assembly incompatible with industry standard connector sockets. SUMMARY OF THE INVENTION The claimed invention is intended to provide auxiliary power for volatile memory cells and a remedy to the significant power drain in the peripheral drive circuits during the standby mode of operation, without increasing the number of external connector pins required. According to the claimed invention, power drain in the peripheral drive circuits is totally eliminated in the standby operating condition by decoupling the memory array power input node with respect to the external power input pin whereby only the volatile memory cells are supplied by the auxiliary source, while the peripheral control circuits remain connected to the external power source. Auxiliary power for the volatile memory cells is conducted to the memory cell power input node through an existing external control signal pin, such as the CTS input pin, thereby eliminating the need for additional connector pins. The auxiliary power source is coupled to the external control signal pin through a diode which is forward biased only when the primary power source potential drops below the auxiliary power source level, thereby avoiding masking of the applied control signal CS. The control signal input pin is coupled to the memory array power input node through a field effect transistor switch which is turned on only when the voltage level at the control signal input pin exceeds the voltage on the memory array power input node by a predetermined threshold voltage level. The external power input pin is similarily coupled to the memory array power input node through a field effect transistor switch which is turned on only when the voltage applied to the external power input pin exceeds the memory array power input node voltage by a predetermined threshold value. While operating power is being conducted through the external power input pin from the primary power source, the control signal input to which the auxiliary power source is coupled will function normally since the auxiliary source is blocked by the back-biased diode. However, when the primary power source falls below the level required for reliable operation, the memory array power input node is.automatically disconnected from the external power input pin by the operation of the field effect transistor switch, which is turned off. This simultaneously decouples the memory array power input node from the peripheral drive circuit. At the same time, the diode becomes forward biased as the voltage level of the primary source drops, thereby applying the auxiliary power source to the control circuit input pin. Data retention operating current is conducted from the auxiliary source to the memory array power input node through the second transistor switch which turns on in response to the reduced potential at the memory array power input node. DESCRIPTION OF THE DRAWING One way of carrying out the invention is described in detail below with reference to a drawing which illustrates a preferred embodiment, in which: the sole figure of the drawing is a circuit diagram which illustrates a specific embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawing, an integrated circuit memory system, forming a part of a micro-processor, is indicated generally by the reference numeral 10. The system 10 is preferrably fabricated using conventional LSI process technology to produce enhancement mode MOS-FET devices on a semiconductor substrate chip. The integrated circuit memory system is a random access memory having a total of n binary volatile storage cells arrayed in an MXN matrix of rows and columns. Each storage cell,for example volatile cell 12 ,comprises a field effect transistor and a capacitor (not shown). Each memory cell is coupled to row and column lines in the usual manner, and includes read/write circuitry (not shown) and precharge circuitry (not shown) which conducts operating current to the storage capacitor of each cell through a power input node 14, which is common to each cell of the array. Primary operating power is supplied by an external power source 16 and delivers a nominal operating voltage Vcc to an external power input pin 8. The nominal value of Vcc is plus 5 volts DC. According to an important feature of the invention, the memory peripheral drive circuits which do not involve volatile storage devices are connected directly to the external power input pin 18, and the volatile components, e.g. the memory cells 12, are coupled indirectly to the external power input pin 18 through an enhancement mode field effect transistor 20. The field effect transistor 20 is connected to operate as a switch, with its gate 20G and drain 20D both being connected to the external power input pin 18. Its source 20S is connected to the memory array power input node 14. To understand the operation of the field effect transistor switch 20, assume that a potential of Vcc equal to +5 volts is applied to the external power input pin 18, and that the operating threshold of the enhancement mode transistor 20 is about 2 volts. Therefore the potential on the source 20S and also on the memory array power input node 14 will be 3 volts, a level which is sufficient to insure reliable operation of the volatile memory cells. According to an important feature of the invention, memory peripheral drive circuits (not shown) are energized by direct connection to the external power input pin 18. The memory peripheral drive circuits are each connected directly to the external power input pin 18 by a power conductor 22. By this arrangement, the memory peripheral drive circuits are connected in parallel electrical circuit relation with the transistor switch 20, whereby the memory peripheral drive circuits are automatically disconnected with respect to the memory array power input node 14 when the transistor switch 20 turns off in response to to a low voltage condition. This allows the memory cells 12 to be supplied from an auxiliary power source 24 without imposing an unnecessary drain on the capacity of the auxiliary power source. To be compatible with industry standard pin socket connectors, the auxiliary power source 24 must be coupled to the memory array power input node 14 without requiring an addition external connector pin. This is achieved in to the present invention by utilizing an existing pin, for example pin 26 which is connected to the chip select complement signal CS, which is generated in some other part of the micro-processor. The auxiliary power source 24 must be coupled to the CS pin 26 in such a manner that it is decoupled with respect to the pin except during the data retention backup mode of operation. The chip select complement signal 5 will assume the logic high condition (V ) when the cc chip 10 is "unselected" ,and will assume the logic low (ground or zero potential: when the chip 10 is selected. It should be noted that three distinct operating conditions can exist with respect to the state of the external power source 16 and the logic state of the chip select complement signal 3. One condition is, of course, that the chip is selected ( low) with adequate power available from the primary external power supply 16. This condition will not be considered further since adequate power is available for data retention in the volatile memory cells 12. The other two significant cases are (1) the chip 10 is unselected ( high) with adequate power available from the external power source 16 and (2) the chip is unselected (G high) with V below the level required for reliable operation. It is only cc under the latter condition that auxiliary power is required for maintaining the data state of the volatile memory cells. Under ordinary operating conditions, the complement chip select signal CS is generated in some other portion of the the micro-processor and is applied to the control circuit input pin 26 through a logic circuit 28 and bi-polar transistor 32. The logic circuit 28 develops a gate signal 30 which turns the bipolar transistor 32 off and on as CUSS assumes the logic 1 and logic 0 conditions, respectively. The collector of the bi-polar transistor 32 is coupled to V cc through a load resistor R, and the collector is also connected directly to the control circuit input pin 26 so that the potential on the collector of the bi-polar transistor 32 will swing from Vcc to ground potential as the complement chip selects signal CS changes state from logical to logic 0, respectively. The auxiliary power source 24 is connected in parallel circuit relation with the primary external power source so that it can supply operating current upon failure of Vcc. Connected in series electrical relation with the auxiliary power source 24 is a junction diode D. The nominal voltage level of the auxiliary power source 24 is deliberately chosen to be less than the nominal voltage level of Vvac,whereby the junction diode D is back-biased during ordinary operating conditions. However, when the Vcc voltage level drops below the voltage level of the battery 24, the diode D becomes forward biased and conducts current from the auxiliary battery 24 through the load resistor R. Recalling that the only operating condition of interest is the case with the chip 10 unselected and Vcc below the minimum level required for reliable operation, the bi-polar transistor 32 will be turned off, thereby causing its collector to rise to the voltage level E of the auxiliary power source 24. Assuming that V c has a nominal voltage level of 5 volts DC, and that E equals cc 4.5 Volts, as the Vcc drops below 4.5 volts, the diode D will conduct and a voltage of E = 4.5 volts will be impressed across the control circuit input pin 26. Current from the auxiliary power source 24 is conducted to the memory array power input node 14 through a second enhancement mode field effect transistor 34 which has its drain 34D and gate 34G connected to the control signal CS input pin 26, and its source 34S connected to the memory array power input node 14. Assuming that the threshold potential of the field effect transistor 34 is approximately 2 volts, it will turn on when the voltage of the memory array power input node 14 falls below 2.5 volts. Thus the transistor switch 34 will turn on and supply data retention current to the memory cell 12 well in advance of the point that the field effect transistor 20 turns off, thereby assuring continuity of data retention operating current. Moreover, as the field effect transistor 20 turns off, the peripheral drive circuits are decoupled from the memory array.

Claims: What is claimed is: 1. An integrated circuit memory system having an array of volatile memory cells and a control circuit coupled to the volatile memory array, a power input pin being provided for conducting operating current from a primary external power source to the integrated circuit memory system, a control signal input pin being provided for conducting a control signal to the integrated circuit memory system, and the memory array having a power input node for conducting operating current to the volatile cells of the array, characterized in that: : first switching means connected between the power input pin and the memory array power input node for automatically establishing a conductive path from the power input pin to the memory array power input node in response to the voltage of the power input pin relative to the voltage of the memory array power input node rising above a first predetermined threshold level, and for automatically interrupting the conductive path in response to the voltage of the power input pin relative to the voltage of the memory array power input node falling below the first predetermined threshold level; and, second switching means connected between the control signal input pin and the memory array power input node for automatically establishing a conductive path from the control signal input pin to the memory array power input node in response to the voltage of the control signal input pin relative to the voltage of the memory array power input node rising above a second predetermined threshold level, and for automatically interrupting the conductive path in response to the voltage of the control signal input pin relative to the memory array power input node falling below the second predetermined threshold level. 2. An integrated circuit memory system as defined in Claim 1, in which the first switching means comprising a field effect transistor having its gate and drain electrically connected to the power input pin and its source electrically connected to the memory array power input node; and, the second switching means comprising a field effect transistor having its gate and drain electrically connected to the control signal input pin and its source electrically connected to the memory array power input node. 3. The integrated circuit memory system as defined in Claim 2, in which an auxiliary power source is coupled to the control signal input pin, and the nominal voltage level of the primary power source less the first predetermined threshold voltage is greater than the nominal voltage level of the auxiliary power source less the second predetermined threshold voltage. 4. An integrated circuit memory system as defined in Claim 1 or Claim 2 in which an auxiliary power source is coupled to the control signal input pin, and the nominal voltage level of the auxiliary power source is less than the nominal voltage level of the primary power source. 5. An integrated circuit memory system as defined in Claim 1 or Claim 2, in which operating current for memory peripheral drive circuits is provided by a power conductor connected directly to the external power input pin in parallel ciruit relation with the first switching means.

Inventors: DONNELLY, ROBERT MURRAY
Applicants: MOSTEK CORPORATION
Application year: 1980
Main classification: H02H7
IPC codes: G06F1, G11C11, H02J9, H02H3