CCD READ-ONLY MEMORY

Abstract: The specification describes a high capacity non-volatile CCD read only memory system that includes a plurality of memory cells. Selected ones of the memory cells include a double-diffused region (34) having a first (36) and second (38) implant or diffusion under a clocked electrode (24) whereby the first implant or diffusion (36) provides a fixed charge required for ROM operation, and the charge and polarity of said second implant or diffusion (38) provides a neutralizing effect on the surface potential under the clocked electrode (24) and above the double implanted or double diffused region (34).

Description: CCD READ-ONLY MEMORY AND METHOD OF FABRICATION THEREOF The invention relates to a CCD (chearge-coupled device) read-only memory (ROM). There are two basic classes of solid state read-only memories (hereinafter reffered tzo as ROMs)namely, random access memories and serial access memories. Random access MOS ROMs are generally well known. They typically consist of a matrix of Metal-Oxide Silicon-Field-Effect Transistors (MOSFETs) that have been constructed with an alterable threshold voltage which is used to electrically indicate the storage of a binary "1" or "0". The second class of ROMs i.e., serial access memories are not known to be presentlycommercially available as MOS devices. A typical solid-state rondom access ROM is a MNOS (Metal Nitride Oxide Semiconductor) memory device such as described by Frohman and Dentchowsky in Procoedings IEBE, Vol. 58, August 1970 pages 1207 - 1219. The MNOS structure describd in this publicationis configured in the form of a field-effect transistor fabricated on a semiconductor substrate having an insulated gate electrode and source and drain terminals that "current access" the stored charge in the transistors. A composite insulating layer disposed between the gate electrode and the semiconductor substance of the transistor consists of a thin layer of silicon oxide on er of silicon nitride has been applied. By voltage pulse on the gate electrode, charge carriers are transported from the semiconductor substrate to to the thin silicon oxide layer by meaiis of a phenomena known as tunnelling. The number of charge carriers trapped at the interface of the silicon oxide layer and the silicon nitride layer detemines the threshold voltage of tiie transistor, which voltage I. turn controls the magnitude cf +'e current flow between the source and drain trials for a specified read voltage on the gate electrode. However, the problem encountered with this prior MNOS structure is that it requires at least one transistor per bit of binary information, so that the packing density is very small and limited. Another method of determining the threshold voltage of a field-effect transistor gate in the above type of MNOS structure is by injection of charge created during an avalanche breakdown In the seniconductor substrate of the transistor. A semiconductor memory device using this principle is known in the art as a FAMOS (Floating-Gate Avalanche Metal Oxide Semiconductor) structure, and one such structure of this typ is described by Dov Frohman and Bentchowsky in IEEE Journal of Solid-State Circuits, Vol So6, October, 1971i pages 301-306. The device described in he latter publication is a field-effect transistor with a source, a drain, and an insulated floating gate e) ectrode in the form of a nonconnected conductive layer which is usually surrounded by insulating material and disposed above the surface of the semiconductor substrate. By applying a reverse bias of sufficient magnitude across the source substrate PN junction or the drain-supstrate PN junction to produce avalanche breakdown, charge carriers are generated at the junction. On account of the electrical field applied across the PN junction at reverse breakdown, the energy of these charge carriers reaches a @ level suclu that these carriers are capable of travelling from their energy hand in the semiconductive substrate to a corresponding energy band in the insulating layer below the gate electrode. Such charges travelling in the insulating layer near the floating gate electrode will therefore charge this electrode. Thus, during operation of this FAMOS type device, electrons can move from the conduction band in the semiconductor substrate to the conduction band in the insulating layer. Contersely, holes of the valance band in the semiconductor substrate may sift to the falarce band in the insulating layer. However, once again the important drawback of this latter avalanche injection structure is the inefficient packing density which results from the requirement of one transistor per bit to be stored in the structure. An alternate method of cell operation frequently used in connection with a MNOS memory device of the above type is charge addressing the MNOS structure This operation is accomplished by controlling the silicon oxide electric field strength and current density of the device which is dependent upon the magnitude of signal charge beneath a deep depleted MNOS capacitor formed by e device. In operation, the surface potential of this capacitor is collapsed and the silicon oxide electric field strength increases with an increase in silicon oxide tunnelling current. The transfer of signal charce from the device is typically acconplished using an output charge-coupled device (CCD). The combination of charge transfer and MNOS principles for signal control, address, and nonvolatile storage for this latter type of device has been set forth ny j Goser and K. Knaver in IEEE Journal of Solid-State Ciurguits, SC-9, pages 148-150, dune 1974 and by Y. T. Chan et al in Appliei Physics Letters, Vol. 22, pages 650-652, 15 June 1973. The charge storage cites of these MNOS structores are located inside a stepped dielectric 2 phase or 3 phase CCD shift register. This latter MNOS device also has a poor packing density and an inadequate charge handling capability, both of which result in poor write characteristics and ineffective write/inhibit operation for the device. Additionally high voltage clocks required for gocd transfer efficiency in these devices cause spurious write operation and poor read operation due to the large access time to the first stored bit, and these characteristics tend to degrade memory retention caused by small write and read disturb effects. A A RO4. CCD device that has a higher packing density than all of the above-identified prior art structures is a nonvolatile charge-addressed memory (NOVCAM) ceil with parallel write and read-out injection for block-oriented random-access memory (BORAM) applica tion as set of forth for example, by irite ct 1 in the TELL Jourral Solid-State Circuits, Vol. SC19, No. 5, October 1975. The NOVCAM cell described in this publication comprises a combined CCD shift register and a thin-oxide MNOS memory structure to provide a higher packing density 'i'o'ever, the charge transfer efficiency of this latter device is severely degraded by the thin oxide at the NMOS surface, and therefore this circuit is nov well suited for ROM CCD operation with high charge transfer efficiency. The general purpose of this invention is to provide a new and improved CCD ROM structure that has a higher packing density than the NMOS AND FAMOS static ROM and the charge addressed CCD deseribed above, and further has improved operating characteristics (e.g., higher transfer efficiency) relative to the NOVCAM cell described above. This general purpose is accomplished by a CCD ROM structure which comprises a series of COD memory cells defined by adjacent surface portions of a semiconductor substrate and associated charge transfer electrodes, and wherein, in accordance with the invention, selected ones of the memory cells further include an opposite conductivity type region defined by diffusion or ion-implantation of the requisite conductivity type impurity into the substrate directly beneath the last electrode within a memory cell and a second region likewise formed by diffusion or ion-implantation, directly adjacent to the first-mentioned region and of the same conductivity type as t-)ie substrate though of higher charge carrier concentration. In operation of such a CCD ROM structure, the electrodes are responsive to clocking signals so as to produce and define, when energized, a series of selectively spiced regions of fixed charge in the semiconductor substrate and the flrst-mentioned diffusion or implantation region provides a fixed charge representative of bInary information required for read only melnory operation. The second region produced by the second diffusion or implantation provides a neutralizing effect on the first diffusion or implantation region such that the first region does not significantly and adversely affect the suriace potential of the CCD under the last electrode of any given memory cell. The first diffused or ion-implanted region thus provides a fixed charge representative of certain RON information and tile second diffused or ion-implanted region provides a neutralizing effect on the surface potential of the CCD above the first aitd second regions defined above, and thus tends to offset the effect that the charge of the first diffused or implanted region has on this s'j1'±c" potential, The ROM structure of the present invention may be utilized in a system having an input circuit which supplies charge representative of an input signal to the <RTI ID=6.1> input cci ] , and also having an output circuit which converis the charge from the output cell into an appropriate output signal. The system further includes a refreshing means for feeding baci the output signal to the input circus t thereof. The invention can provide a nonvolatile CCD memory structure of the type described uliich is capable of a hih charge storage density while maintaining a relatively high charge transfer efficicncs, and which can perform as a non-memory, linear CCD when It Is not Connected with feedback as a read only memory. In order that the invention might be clearly urrlerstood, several embodiments thereof ill now be described with reference to the accompanying drawings wherein: Figure la is a partial plan view of a nonvolatIle CCD iWM fabricated in accordance with the present invention: : Figure 1b is a schematic diagram of clocking circuitry which may be used in combination with the device of Figure la; Figure 2 is an enlarged cross section view of one COD ROM cell used in Figures 1a aid Ib; Figur 3a is a cross-sectional view of a CCD with one implant of a conductivity-type opposite to that of the substrate; Figure 3b is a plot of the surface ptitentiai beneath the electrode o"er- the plant of two positions in Figure 3a for an applied voltage; Figure 3c Is a plot of the surface potential beneath the electrode of the CCD of Figure 3b to which a larger voltage than in Figure 3b has been applied; ; Figure 4a is an equivalent circnit of the CCD of Figure 3a; Figure 4b is a plot of the potential beneath the electrode as a function of distance into the substrate, with the presence of two implants; Figure 5a is a plot of the doping concentrati on of the CCD ROM cell in Figure 2 versus distance into the semiconductor substrate in which the cell is formed; figure 5b is a plot of tfle electric field profile for the cCn ROM cell in Figure 2; Figure 5 is a plot of the surface potential beneath the clocking electrode for the CCD ROM cell of Figure 2 versus distance into the semiconductor sub strata; ; Figure 5 is a plan view of a charge transfer system incorporating a plurality of non-volatile CCD ROMS constructed in accordance with Figures 1b and 2 above; and Figure 7 is a clocking diagram illustrating the voltages applied to the electrodes of Figures tb, 2, 3a and G. Referring first to Figures ta, ib and 2, a CCD shift register is formed in a semiconductor substrate 12 having a thin layer of oxide 14 deposited on its top surface Buried in the oxide layer 14 and distributed along its surface are a plurality of indiv idual clocking or addressing electrodes 18, 22, 26 and 30 to which potentials are applied to move charges from left to right, from one potential well (not shown) in the substrate 12 to the next. Tijo charges are introduced (injected) into th.e CCD 10 by suitable input circuitry (not sbown); and these injected charges are confined within a channel 13 formed in the substrate 12 and bouiided by a pair of '+ channel stops 15. A clocking signal from a suitable clock source is applied to electrodes 18 and 26, a #2 clocking signal is applied from a second appropriate clock source to electrodes 20 and 28, a #3 clocking signal is applied to electrodes 22 and 30, and a #4 clocking signal is applied to electrodes 16, 24 and 32. The exact phase relationships of clocking signals #1 - #4 are shown in Figure 7 which is described in more detail below. While the CCD device of t0e above-descl-i.bed embodiment has been structured so as to respond to four separate clocking signals , it may be suitably modified to respond to any number of clocking signals. Referring more specifically to Figures Ib and 2 the CCD 10 further includes a double implanted or double diffused region 34 directly beneath the last; clocked electrode 24 (in a clock cycle) for one ROM ccll in the substrate 12. The doping (impurity concentration) of the first implant or diffusion 36 of the fixed charge region 34 is chosen such that it is opposite in polarity (conductivity-type) to both the polari y of th± subsrate 12 and the polarity or conductivity-type of a second implant or diffusion 38. ore specifically, if a p type material is chosen for the substrate 12, then the implant 36 will have an N type conductivity and the implant 38 will have a P type conductivity. the first N planar region 36 stores binary informattion in the form of a fixed charge whicii has been Introduced by impurity diffusion or ion- implantation into the substrate 12 using conventional MOS planar processing procedures including well-known lithographie masking and etching techniques which form no part of this invention. Of course, the conductivity types can be reversed with the substrate 12 having an N type conductivity and implants or diffusions 36 and 38 being p+ type and N- type respectively. The first or upper doped region 36 has a certain amount of electron charge, Q, corresponding to the stored binary information in the COD. or proper CCD operation, this charge must be serially clocked from gate to gate along the length of the CCD structure and bencath the clocking electrodes thereof. However, the first implant or diffusion 3G altcrs tie electrical potential profile underneath gate electrode 24 (in a manner to be described) such that if only a single diffusion or implant 36' were used, as indicated in Figurc 3a, there cell be an intolerable impedance to charge transport laterally across the COD structure. Thus, if a voltage V1 is applied to the gate electrode 24 in Figure 3", the surface potential along the dimension X1 under the gate electrode 24 and through the region 36' into the substrate is illustrated by curve 90 ill Figure 3b. The adjacent potential beneath the outer edge of gate electrode 24 along the dimension and exterior to region 36' is illustrated by curve 92 in Figure 3b. In order to clock the charge Q laterally across the CCD structure in the standard CCD mode of operation, the point 94 at which the potential curve 92 intersects the SiO2 interface should be equal to the point 96 at which ourve 90 intersects the SiO2 inter face. However, using only a single implant 36' there will be an energy barrier of height C,E preventing the flow of charge from the implant region 36' to a substrate region beneath an adjacent gate 26. This energy barrier #E occurs because the implant 36' cause the CCD structure to act like a buried chaiinel CCD (BCCD), whereas the remaining portions of the CCD structure function as a surface channel CCD (SCCD). As is known in this art, chargetransfer from a buried channel to a surface channel is not possible using standard gating schemes. This principle o is set forth in a publication entitled "Liquid-Crystal Electro-Optical Modulators for Optical Processing of Two-Dimensional Data" by J. Grinberg et al, SPiL' Vol. i28, Efiective Utillzatjoij of Optic. in Radar Systems, 1977, pp. 253-266. One method for transferring charge between a buried chunnel CCD and a surface channel CCD is to apply a relatively large voltage V2 to the electrode 24 of Figure 3a and thus substantiallr alser the potential profiles in the underlying semiconductor material. This principle is discussed in some detail in a publication entitled Design Considerations for a Two-Phase, Buried Channel, Charge-Coupled Device", The Bell System Technical Journal, Vol. 53, No. 8, October 1974, pp. 1581-1597. Using this technique, a relatively large voltage V2 which is higher than V1 may be applied to the same COD electrode 24 to thereby raise the potential 90 under the electrode 24 until the charge Q reaches the surface of the semiconductor substrate 12 as illustrated by curve 98 in Figure Sc, At this time, the charge in the buried channel 36' will flow alon, the surface of the substrate 12. This alteration in substrate potential profiles ill overcome the abovedescribed charge transfer problems between the buried and surface channels of the CCD structure. On thc other hand, the voltage required to transfer charge from a single implant 36' and along the surface of the substrate 12 is quit large for all conventionally doped CCD structures and therefore renders this latter technique an impractical solution to the above charge transfer problem. To illustrate this point, the CCD structure in Figure 3a can be represented by two capacitors Cox and Cdepl which are connected in series as shown in Figure Xa. Tile capacitor Cox corresponds to the CCD exide capacitance and is relatively large, since the oxide thickness is small. The second capacitor, Cdepl' models the back biascö PN junction at the region 36' - substrate interference and this latter capacitance is relatively small because the depletion width of this PN junction is very large. Thus, the total capacitance Ctotal of the series combination Cox and Cdepl is also very small and hcnce a large voltage ( 100 volts) 15 s necessary to pull the electrrn charge to the surface, i.e.: EMI11.1 and overcome the above described charge transfer problem. However, in accordance with the present invention, it has been discovered that the abovc-describc-d problems o buried channel to surface channel energy barriers and their respective impendances to charge transfer may be alleviated by the creation of the second, P implanted or diffused region 38 directly beneatb the N surface region 36 as shown in Figure 4b Now, rather than having the PN junction depletion region capacitance Cdepl determined by a N P junction (where the P doping is that of the substrate), it is instead determined by a junction which, as a result of tie increased P doping concentration adjacent to the ; type region, has a significantly increased juction capacitance, Cdepl'. This increase in Cdepl to a new value of Cdepl' as indicated in Figure 4b causes the profile of charge (Q) versus distance into the semiconductor substrate to assume the new contour indicated in the latter Figure. Thus, with the two doped regions 36 and 38 present in the substrate 12, a much smaller voltage V1' typically on the order of 6 volts, is sufficient to pull all of the charge Q to the s11con- silicon oxide interface and enable the structure to be operated as a surfect channel CCD. Thus, there has been described a novel double diffused or double implanted CCD memory which is operable as a surface channel device, and this new and improved structure overcomes the problems described above associated with buried-to-surface cllannel types of charge transfer In order to optimize charge transfer efficiency in the CCD ROM cell, the above dose and position of the second doped region 38 is adjusted to produce the same net surface potential for the composite double-implanted region 34 as would have been the case without either of the two implants 36 and 38. Referring now to Figure 5a, a hypothetical doping concentration pof the CCD cell in Figure 2 is illustrated as a function of distance X into the substrate 12 under the electrode 24. The doping profiles for the doped regions 36 and 38 are represented by the dashed lines 6 and 48. The solid line 44 represent the background doping concentration in the surrounding portions of the substrate 12. As previously described, the doping concentration of the implantation 38 is chosen to counterbalance any effect on the CCD operation caused by the N impurity concen traction of the implantation 36. The implant 38 is of the same cenductivity-type as the substrate 12, but much higher in doping concentration. Both of the ionimplants 36 and 30 arc concentrated near the surface of tie substrate 12. Figure 5b illustrates the contour of the electric ficld, L, (i.e., E-field profile) produced by the applicatioii of a fixed voltage to the clock electrode 24 above the doped regions 3(, and 38.. As shows n in Figure 5b, the E-fie3d varies ns a function of the integral of the doping concentration p, and alone a dimension tl0rough tulle doped regions 36 and 38 and the underlying substrate 12. The solid line profile 50 illustrates the plot of the electrie field in the absence of the implants 36 and 38. and the dashed line 52 is an integral of the rclatively constant N and P typo doping concentrations 46 and 48 in Figure 5a. The substrate surface poten@ial is illustrated in Figure 5c and is an integral of the electric field, E, i.e., V = # E (X) dX, where "X" is the distance into the substrate. The purpose, of Figure 5 is to show that the effect of the total integration represented by the dashed line 52 in Figure 5b on the surface potential V of the COD memory cell is represented by the dashed line 56 in Figure 5c. Thus, whereas the surface potential V in Figure 5c for an undoped substrate 12 varies along the parabolic contour of the solid line 5 and into the substrate, the double doped substrate ill now have a surface potential V which varies along the inverted parabolie contour 56 which is the integral of the E field profile 52 in the doped regions 36 and 38. The net rest is that the integration represented by the curve portion 56 has a negligible effect on be surface potential V of the CCD memory cell, and this is a desirable featur provided by the present invention Referring nov to Figure 6, a charge injection input circuit 42 of a type known and available in the art, such as in the publication of Charge Transfer Device, by C. Siquin and N. Tompett, Academic Press, inc. New York, 1975 pp. 47-61, supplies charge which is fed into a first ROM cell 50 of the CCD ROM structure The The serially connected COD cells 50-72 are ad:ipted to receive the clocking signals #1-#4 of the four different phases ieldicated in Figure 7, and these clock signals are available from a clocking source 74. During fabrication of the serially connected CCD cells 50 through 72 on a single substrate, bits of binary information were stored as full potential wells of charge in predetermined ones of these CCD cells. cells 52, 60-68 contain an "x" representing stored binary "I's", and these cells are similar to the CCD cell in Figure 2 and contain the double implanted or double diffused region 34 which store the charge representative of a binary "1". The remaining cells 50, 54-58 and 70-72 that contain no fixed charge represent the binary "0' s" for the charge processing circuitry of Figure 6. The start up procedure for the CCD memory system 46 in Figure 6 is to apply the #1-#4 voltages from the clocking source 74 in the phase relationship shown in Figure 7, so that four electrodes in each COD memory cell will receive one of the four #1-#4 clocking signals. During each cycle of the clocking voltages #1-#4, charge is transferred from one CCD cell 50-72 to the adjacent CCD cell to the right as shown in Figure 6 The output circuit 44 senses th- charge in the last or output COD cell 72 and converts it to a signal <RTI ID=14.18> which is then applied to the input circuit 45 by feedback means 80. The feedback moans 80 i preferably a bus line which serves to connect a refresh signal back into the first COD memory cell 50. There- fore, the input circuit 42 is also a charge refreshing circuit in that it respends to both a feedback signal as well as a plurality of input signals 48. The signal from the output circuit t 44 is also supplied to all output bus 7u so that it can be further processed by an output out, lization circuit 78 such as Ibid., pp. 47-61. The eleven bit binary number 00111... 1100010 is read out in the sequence indicated in the output circuit 44, which receives this sequential binary information from the last (eleventh) CCD cell 72. This binary number is dependent upon the fixed charge (or absence thereof) state of each of the eleven cell shown in Figure 6, and the number of bits in the binary number arid the nuiiiber of CCD cells will be the same. The duration of each binary bit, which may be digital information visible on a crt or the like, i.e., block 44, corresponds to the duration of each clock cycle which is defined, for example, as time @ 1 in Figure 7. Thus, the read-out of the above eleven bit binary number completed after eleven successive clock cycles, i.e, at time t11' and then the cycle starts over after the information is refreshed. This COD structure and clocking circuitry shown in Figure 6 is connected for use as a RON. Once the stored data as begun to circulate (using the refresher feedback connection 80), the CCD functions in a known manner by transferring charge from one potential well to an adjacent potential well. In some instances, however, it may be desirable to disconnect the fixed charge RON cells from the eircuitry of Figure 6 and operate this circuitry as a standard serial COD. This may be accomplished by applying an external da:ta signal to the input circuit 42 rather than applying the signal from the refresher. During this tire the original stored Information will be temporarily lost. When the original stored information needs to be retrieved from tl3e RON memory of Figure 6, either because the structure has been processing new charge or because the power has heen turned off, it may be done by either one of two methods. The first method is to turn the CCD structure in Figure 6 off by shuttnng don the power applied thereto and allowing charge to thermally accumulate in the device, During this period, the potential wells that had been originally filled with charge will return to their eqqulibrium state i.e., xill with charge. This action is due to the excess electrons that are created by heat generation that are floating around in ttie system. The only requirement for turning on the system again is to allow enough time to pass after the iM COD i 5 de-energized so that the implanted or diffused regions therein can fill up with the thermally induced charge. After such sufficient length of time 'has passed, charge will become concentrated only ill the double implanted or double diffused regions and the CCD can be turned on again, containing the original stored information The other way to retrieve the ROM information in the structure of Figure 6 is to apply a momentary input signal to all of the COD cells." The charge in the structure of Figure 6 will instantly concentrate in the double doped regions in the ROM COD cells therein This second method is preferred in cases where the stored information is needed instantaneously, particularly since the thermal relaxation rate is relatively slow in the first method described above fcr information retrieval. An example of an N channel silicon ROM cell, in accordance with the invention, may have (and is not limited to) the following parameters. The substrate would have a resistivity between 0.1 and 104 ohm cm and a P type don of I x 1015 cm 3. The first inplant would have an N type arsenie implantation (the dose being X1 x 1012 cm-2) leaving a doping concentration of 1 x 1016 cm-3 from the silicon-silicon oxide interface to 1000 deep in the substrate. The second implant would have a p type boron Implantation (the dose being X1 x 1012 cm-2) leaving a doping concentration of IG 1 cm 3 ¯roSE 1000 to 2000 deep in the substrate The lateral dimensions cf these :implants would cor-espond to the area of the storage gate 24. (The alignment of the implant with respect to the storage gate is not critical). The silicon wafer orientation should be (100) as used for standard NMOS technology. Thus, there has been described a dynamic serial CCD ROM cell a@@ associated structure and clocking structure which has an inherently larger packing density than known pric art solid statc random access memories such as the MNOS and FAMOS memories described above. In addition, the present ROM CCD memory exhibits certain improved operating characteristics and can function as a standard serial 1 CCD without memory if df sired.

Claims: Claims: 1. A non-volatile CCD read-only memory (ROM) comprising a semiconductor substrate of a predetermined conductivity type and a plurality of charge transfer electrodes selectively spaccd above, and insulaied from, a major surface of the substrate and arranged to define a series of memory cells in the substrate, characterized in that selected ones of the memory cells include a double conductivity type region (34) consisting of a first region (38) adjacent said or surface and of a first conductivity type which is different fro said predetermined conductivity type of the substrate (12), and a second region (38) adjacent said first region (36) and of a second conductivity type which is the sa-.-.e as the conductivity type of th2 substrate (12) but has a higher impurity concentration 2. A read-only memory according to claim 1, characterized in that said series of memory cells (50 to 72) includes input (50), output (72) and intermediate (52-70) cells, and there are provided input means (42) coupled to the input cell (50), output means (44) coddled to the output cell (72), a feedback connection (80) from the output means (44) to the input means (42j, and a clocking signal source (74) coupled to said electrodes (16 to 32) to transfer charges between successive ones of said memory cells, whereby said first region (36) provides a fixed charge representative of R0' information, while said second region (38) has a nentralizing effect on the surface potential of said double conductivity type region (34). 3. A read-only memory according to claim 1 or 2, characterized in that the semiconductor substrate (12) has E resistivity of between O.i and 1014 ohm cm, the first region (36) has an ir--qurity conce.,tration of between 1012 and 1020 charge carriers per cubic centireter, and the second region (38) has approximately the same impurity concentration 8; ; the first region (36) but an opposite polarity. whereby the resulting neutralizing effect enables the substrate (12) to receive a fixed charge as necessary for ROM operation withour significantly chanping the surface potential of the substrate and thus the clocked CCD operation. 4. A read-only-memory (ROM) structure for providing nonvolatile storage of binary information, said structure comprising: a) a semiconductive substrate of a first conductivity-type, having first and second major surfaces, b) 2 plurality of adjacent charge-coupled-device (CCD) memory cell Including input, output and inte-- mediate COD cells cascaded therebetween, each ccii including predefined adjacent surface portions of said substrate and being further defined by separate plurali- ties of clocked electrodes selectively spaced above and insulated from said substrate to define, when energized1 a series of charge storage sites in said substrate , and c) selective ones of said cells including fixed charge areas defined by: i) a first region of a second conductivity- type adjacent to said first major surface, of said sub strate, ii) a second region of the same conductivity- type Or said substrate, and of higher impurity concentration than said substrate, directly adjacent to said first region, whereby when clocking signals are applied to said pluralities of electrodes so as to step charge packets between successive ones of said cells, including said storage sites, said first region provides a fled charge required for memory in RO operation, and the charge and polarity of said second region provides a neutralizing .ffct on the surface potential of said substrate above said first and second regions. 5. A nenvolatile read-only-memory (ROM) structure having selectively spaced regions that store charge in a substrate, comprising: a) a pemiconductive substrate of a first conductivity-type, having first and second major surfaces, b) a plurality of adjacent charge-coupled- device (CCD) memory cells including input, output and intermediate CCD cells cascaded therebetween, each CCD cell including redefined adjacent surface portions of said substrate and being further defined by scparate pluralities of clocked electrodes selectively spiced above said substrate portions, so as to define, when energized, a series of charge storage sites in said substrate 1 and c) selective ones of said cells including a fixed charge region defined by: i) a first ion-implanted or diffused region of a second conductivity-type adjacent to one of said surface portions of said substrate and directly beneath a selected one of said clocked electrodes1 ii) a second ion-implanted or diffused region of the same conductivity-type of said substrate, and higher in impurity concentration than said substrate, directly adjacent to said first region, whereby when clocking signals are applied to said clocked electrodes so as to step charge packets between successive ones of said storage sites, said first region provides a fixed charge representative of ROM non-volatile memory information and the charge and polarity of said second region or provides a neutralizing effect on the surface potcl,tial of said substrate portions directly beneath one of said clocked clectrodes and above safd first and second regions. 6 , A system for providing nonvolatile storage of information, said system comprising: a) a se-miconduetive substrate of a first conductivity-type having first and second major surfaces, b) a plurality of adjacent charge-coupled device (CCD) memory cells including input, output and intermediate CCD cells cascaded therebetween, each cell including predefined adjacent surface portions Or said substrate and being further defined by separate pluralities of clocked electrodes selectively spaced above said substrate to define, when energized, a series of charge storage sites in said substrate, c) input circuit means coupled @@ said Input cell for providing charge thereto 1 d) output circuit means coupled to said output cell for converting binary in2ormation therefrom1 e) means for feeding back t)e information from said output circuit means to said input circuit means, and f) selected ones of said cells including fixed charge regions defined by: : i) a first ion-implanted or diffused region of a second conductivity-type adjacent to une of said surface porectly of said substrate and directly beneath a selected one of said clocked electrodes, ano ii) a second ion-implanted or diffused region of the same conductivity-type of said substrate but higher in Impurity concentration than paii suostrate, directly adjacent to said first region, whereby when clocking signals are applieC-' to said clocked electrodes so as to step charge packets between successive ones of said storage zites, said first region provides a fixed charge representative of ROM memory information and the charge and polarity of said second region provides a neutralizing effect or; the surface potential of said substrate portions directly beneath selected ones of said clocked electrodes and above said first ard second regions. 7. A method of fabricating a nonvolatile read-only memory (ROM) cell having selectively spaced regions of fixed stored charge in a substrate, comprising the steps of: : a) providing a semiconductor substrate of a first conductivity-type having first and second major surfaces, b) forming a first region of 2 second coluduc- tivity-type adjacent to said first major surface, c) forming a second region of the same conduct tivity-type as said substrate directly adjacent to said first region, whereby said first region provides a fixed charge required for RON operation, and the opposite charge of said second region provides a neutralizing effect on the surface potential of said substrate above said first and second regions. 8. A method of fabricating a nonvelatile read-only- memory (ROM) cell having a line¯ array of charge transfer electrodes selectively distributed above the surface of a semiconductor substrate to define, when energized, a series of charge storage sites in said substrate, and having means for applying clocking signals to said electrodes so as to step charge packets between successive ones of said storage sites, comprising the steps of: : a) providing a semiconductive substrate of a first conductivity-type having first and second major surfaces, b) providing said 1 linear array of electrodes selectively distributed adjacent to and electrically insulated from said first mawol- surface of said scnli- conductive substrate, c) forming a first region of a second conduc- tivity-type adjacent to said first major surface and underneath one of said electrodes d) forming a second region of the same conductivity-type as said substrate adjacent said first region, whereby said first region piovides a fixed charge required for a desired non-vo tile memory in ROM operation and t3)e electrical charge of said second region which is opposite in polarity to said fixed charge provides a neutralizing effect on the surface potentia ] of said substrate above said first and second regions

Inventors: NASH, GREG
Applicants: HUGHES AIRCRAFT COMPANY
Application year: 1980
Main classification: H01L27
IPC codes: H01L21, G11C27, H01L29, H01L27, G11C17