A SEMICONDUCTOR MEMORY DEVICE IN WHICH SOFT ERRORS DUE TO ALPHA PARTICLES ARE PREVENTED

Abstract: A semiconductor device having a function of preventing a soft error due to alpha particles. The device comprises a semiconductor substrate (1), a thin surface layer (2) formed on said semiconductor substrate (1) and a charge accumulation region (2a) formed in said surface layer (2). The conduction type of the surface layer (2) is opposite to the conduction type of the substrate (1) so that a potential barrier for electrons is formed between the surface layer (2) and the substrate (1). By the potential barrier, electrons derived from electron-hole pairs produced in the substrate by alpha particles can be interrupted from entering into the charge storage region (2a) so that a soft error can be prevented.

Description: A SEMICONDUCTOR DEVICE HAVING A FUNCTION OF PREVENTING A SOFT ERROR DUE TO ALPHA PARTICLES BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a semiconductor device having a function of preventing a soft error due to stray minority carriers generated by alpha particles or cosmic rays, or injected by forword bias of the neighbouring P-N junctions, and more particularly to such a device having a function of minimizing the soft error by improving the structure of the device. Description of the Prior Art In recent years, large scale integrated semiconductor devices, such as 64K or 256K random access memories (R#i), CCDs, etc, have been developed. In such a semiconductor device, the size of each cell and the amount of charges capable of being stored in each cell are very small. When alpha particles are radiated on the surface of the semiconductor device, soft errors may often occur because of the small charge storage. The soft error mechanism is as follows. That is, low levels of alpha particles ( < 0.1 counts/cm2 h) are emitted from a very small amount of uranium (U) or thorium (Th) included in the immediate chip environment, such as found in a package of the semiconductor device. Each of the incident alpha particles interacts with silicon (Si) in the semiconductor device to create a track of electron-hole pairs along the straight -line path of the particles. Therefore, electron-hole pairs are produced in a charge storage region at the surface of the substrate and also in the silicon substrate itself. When the substrate is of a P type, electrons derived from the electron-hole pairs produced in the substrate are thermally diffused isotropically and the electrons thus diffused and which have fallen into the depletion layer are injected, by an electric field, into the charge storage region at the surface of the substrate or into a diffusion region connected to a bit sense line. If there is no electron in the charge storage region, that is, if the information stored in the charge storage region is "0", the electrons injected into the charge storage region destruct the information "0" so that the information 11011 is changed to "1". Thus, a soft error is produced. The depth of penetration or range of the alpha particles in the silicon substrate is about 25 pm and the width of the substrate is usually wider than 200 pm. Therefore, the alpha particles, which may cause these soft errors, are those injected from the front surface of the substrate where active regions of the semiconductor device are present. The alpha particles injected from the back surface of the substrate are not of real problem. Another cause of the soft error is high-energy cosmic rays which penetrate the silicon substrate and generate the hole-electron pairs The mechanism of the soft error is the same as that in the -particles. Still another cause is minority carriers injected from the neighbouring P-N junctions which are forward biased by an under shoot of the input voltage. These minority carriers (electrons in a P-type substrate) may migrate laterally and eventually reach the charge storage region. Thus, it may result in the soft error. These soft errors can be repaired by rewriting correct data and thus are different from hard errors, which are due to defects in the structure of the semiconductor device. However, in order to eliminate the rewriting process, it is preferable that such a soft error does not occur. As a counterplan for suppressing the influence of the alpha particles injected from the surface of the semiconductor substrate, a film made of, for example, lead or resin, for stopping the injection of the alpha particles, may be coated over the surface of the semiconductor device. However, if such a stopping film is used, it is required that the film satisfy various conditions, as follows: (1) the film must have a function of stopping sufficiently the injected particles, (2) the film itself must not include any source of the alpha particles, (3) the film must adhere closely to the chip of the semiconductor device without exfoliation and without making distortion on the chip, (4) the film must be sufficiently insulated electrically from lead wires, and (5) the coating of the film must be inexpensive. Because of these conditions, it is not easy to form a lead film capable of stopping the injected alpha particles. In addition, the film coating on the silicon chip such as a lead or resin film generally is not effective in its stopping power against the high-energy cosmic rays. The film coating also does not help little suppression of the soft error caused by the stray electrons, which are injected by the under shoot voltage. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device having a charge storage region, in which device the structure has been improved for preventing a soft error from occurring due to stray minority carriers generated by alpha particles or cosmic rays, or injected by forward bias of the neighbouring P-N junctions. It is another object of the present invention to make it easy to prevent a soft error from occurring due to such stray minority carriers by improving the structure of a semiconductor device having a charge storage region. It is still another object of the present invention to ensure the prevention of a soft error from occurring due to such minority carriers by improving the structure of a semiconductor device having a charge accumulation region. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a memory cell, including one transistor and one MOS capacitor, in a dynamic Rr## according to one embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the memory cell of Fig. 1, Fig. 3 is a graph diagram illustrating an electric potential distribution in the RAiM of Fig. 1, for explaining the function of preventing a soft error due to alpha particles, Fig. 4 is a cross-sectional view of a memory cell including one transistor, in a buried-storage type RE5-' according to another embodiment of the invention, and, Fig. 5 is a cross-sectional view of a charge-coupled device (CCD), according to still another embodiment of the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 1, a cross section of a memory cell of a dynamic R## according to one embodiment of the invention is illustrated. In Fig. 1, the dynamic RE > t includes a silicon substrate 1. The substrate 1 is of an N type and has a thickness of about 300 through 600 lpm. The specific resistance of the substrate 1 is about 10 R¯cm. -At the surface of the silicon substrate 1, a P-type surface layer 2 having a thickness of about 1 Wm and a specific resistance of about 3 Q-cm is formed by diffusing a large amount of P-type impurities sufficient to form the P-type layer 2, and, in this embodiment, boron ions are diffused into the surface of the substrate 1. By this diffusion of boron ions, the concentration of the boron ions [ B+ is highest at the surface of the surface layer 2 and gradually decreases along the depth L of the surface layer 2, as illustrated in the graph on the left hand side of Fig. 1. The concentration curve of boron ions corresponds to the potential energy curve of an electron. As a result, a potential barrier is formed between the P-type surface layer 2 and the N-type silicon substrate 1. After forming the surface layer 2, P channel cut regions, an insulating layer 6 made of silicon dioxide, diffusion layers 3a and 3b which are drain and source regions of an MOS FET which is a so called transfer gate TG, gate oxide layers 4a and 4b, and N+ polysilicon layers Sa and Sb are formed by conventional MOS technology. The layer Sa is the gate electrode of the FET. The oxide layer 4b and the N polysilicon layer 5b constitute an MOS capacitor MC. When a plus voltage VDD of, for example, 5 V is applied to the N+ polysilicon layer 5b, the conductivity of the surface of the P-type surface layer 2 directly under the oxide layer 4b is inverted. As a result, a charge storage region 2a for storing electrons is formed at that surface of the surface layer 2. Between the inverted N-type region, or, in other words, the electron storage region 2a, and the P-type surface layer 2, a depletion layer 2b is formed, according to the well known principle of PN junction. The depletion layer 2b extends to the region between the N+ diffusion region 3b and the surface layer 2. The N diffusion region 3b, or, in other words, the source of the FET, is connected to the charge storage region 2b. The gate electrode 5a and the drain electrode 3a are connected respectively to the word line WL and the bit line BL. Since an electron from an electron-hole pair produced by an alpha particle has a thermal energy of about 0.024 eV, the amount of borons diffused to form the surface layer 2 must be sufficient for forming a potential barrier which has a highest potential energy more than 0.024 eV. By this potential barrier, electrons having an energy of about 0.024 eV cannot reach the active region, as hereinafter described in detail. In order to ensure the function of the potential barrier, it is preferable to apply a low voltage VBB to the surface layer 2 and a high voltage VDD to the silicon substrate 1, so that the P-N junction between the surface layer 2 and the substrate 1 is reversely biased. Fig. 2 is an equivalent circuit diagram of the memory cell of Fig. 1. As shown in Fig. 2, the source 3b, the gate 5a and the drain 3a are connected respectively to the electrode of the MOS capacitor MC, the word line WL and the bit line 3L. The electrode of the MOS capacitor MC is also connected to the high voltage VDD Another electrode of the MOS capacitor is connected to the substrate 1 (Fig. 1). The operation of the memory cell of Fig. 2 is well known in the prior art and, to explain briefly, when the transfer gate TG is opened, charges are stored into the MOS capactor MC in a programing process and these charges are read out in reading out process. Fig. 3 is a graph diagram illustrating a potential distribution across the MOS capactor MC in the cell of Fig. 1, and explains the function of preventing a soft error due to alpha particles. In Fig. 3, the ordinate ° represents the electric polential of an electron and the abscissa L represents the distance from the surface of the N+ polysilicon layer 5b foward the back surface of the silicon substrate 1. As illustrated in Fig. 3, the electric potential is relatively low in the charge storage region 2a. The potential gradually increases through the depletion layer 2b and reaches its highest value at the surface of the P-type surface layer 2 directly under the depletion layer 2b. Because the concentration of the impurities (boron ions) in the surface layer 2 decreases along with the increase of the distance L, the potential gradually decreases, as illustrated by a solid curve in Fig. 3, from the highest level to the lowest level in the surface layer 2. The lowest potential is maintained in the N-type silicon substrate 1. The potential barrier for electrons is thus obtained. Referring to Fig. 1 and Fig. 3, the function of preventing a soft error due to alpha particles will now be described. Since the penetration depth of alpha particles in a silicon semiconductor is about 25 pm and the depth of the source region 3a or drain region 3b is only about 0.5 pm and the thickness of the surface layer 2 is only about i pm, an alpha particle radiated onto the front surface of the semiconductor device of Fig. 1 can reach thrcugh the sorce region 3a or drain region 3b and the surface layer 2 into the inside of the silicon substrate 1. Along the track of the alpha particle, electron-hole pairs are produced. The produced electrons and holes are thermally diffused isotropically. Most of the electron-hole pairs are produced in the substrate 1, because the thickness (1 pm) of the surface layer 2 is much thinner than the penetration depth (25 pm) of the alpha particles. When there are almost no electrons in the charge storage region 2a, in other words, when the memory cell represents the information lOfT,, and if a part of the produced electrons reaches the charge storage region 3, a soft error will occur. However, since the potential barrier for electrons is formed in the surface layer 2, electrons produced in the substrate 1 cannot reach the charge storage region 2a. A small amount of electron-hole pairs may be produced in the depletion layer 2b. These electrons produced in the depletion layer 2b are#attracted by the electric field and are injected into the charge storage region 2a. However, as described above, since the thickness of the surface layer 2 is much thinner than the penetration depth of the alpha particles, the thickness (0.5 pm) of the depletion layer 2b in the surface layer 2 is also much thinner than the penetration depth of the alpha particles. Therefore, the amount of electrons injected from the depletion layer 2b to the charge storage region 2a is extremely small, so that the injected electrons do not cause a soft error as long as the minimum amount of electrons stored in the charge storage region 2a when the memory cell stores information "1" is not extremely small. Consequently, a soft error due to alpha particles can practically be prevented. If the P-N junction between the N-type substrate 1 and the P-type surface layer 2 is reversely biased, the height of the potential barrier is increased. That is, as illustrated in Fig. 3, the height of the potential barrier is Vex plus vg, t where V represents the external voltage ex difference between VDD and VBB r and VBi represents the component of the potential barrier due to the P-N junction or, in other words, a built-in potential. Therefore, by applying the reversely bias voltage Vex , the potential barrier is increased by the voltage Vex. If the thermal energy of an electron is greater than the potential barrier component due to the P-N junction, the electron can go over the potential barrier when the reversely bias voltage is not applied to the P-N junction. In general, the external voltage Vex , the potential difference VBi due to the P-N junction and the thermal energy of an electron KT must satisfy the relation: Vgi +Vex > KT/q where K represents the Boltzman constant, T represents the absolute temperature and q represents the charge of an electron. Fig. 4 is a cross-sectional view of a part of a buried-storage type RMl according to another embodiment of the invention. As such a buried-storage type RA##, there is a V-MOS RAM or a BO-MOS RATS. The difference between the structure of the RAi4 of Fig. 4 and the structure of the RAM of Fig. 1 is that the REM of Fig. 4 does not include the MOS capacitor MC but, alternatively1 the N -type buried layer 7 is buried in the P-type surface layer 2. By this construction, the integration degree is increased in comparison with the RAM of Fig. 1. In this embodiment, the charge storage region 2a is formed in the depletion layer 2b between the N -type buried layer 7 and the P-type surface layer 2. The equivalent circuit of the RAiM of Fig. 4 is also illustrated in Fig. 2. The operation of the RAiM of Fig. 4 is equivalent to that of the RAM of Fig. 1, and, thus is not described here. Fig. 5 is a cross-sectional view of a charge-coupled device (CCD) according to still another embodiment of the invention. In this embodiment, the thin P-type surface laYer 2 is also formed on the N-type silicon substrate 1. An insulating layer 4 is formed on the surface layer 2. Transfer electrodes 8a, 8b, 8c, ... are formed on the insulating layer 4. Three phase clock pulses, 91 2 t are applied to these transfer electrodes for transferring charges by a well known conventional method. The description with respect to the production of an electron-hole pair due to an alpha particle, the prevention of the thermally diffused electron of the electron-hole pair from injecting into the charge storage by means or the P-N junction between the P-type surface layer 2 and the N-type silicon substrate 3, and the effect of the reverse bias mentioned before regarding to the RAiM of Fig. 1 can also be adapted to the RAM of Fig. 4 and to the CCD of Fig. 5. Instead of forming the surface layer 2 in the REM of Fig. 1, in the #i of Fig. 4 or in the CCD of Fig. 5 by diffusing P-type impurities, the surface layer 2 may be formed by means of the epitaxial growth method. When the epitaxial growth method is employed, the potential barrier is not gradually decreased along with the depth of the surface layer 2, as illustrated in Fig. 3 by the solid curve, but, is decreased as illustrated by a dashed curve in Fig. 3, whereby the level of the potential barrier is highest and substantially constant throughout the surface layer 2 and then suddenly decreases to the lowest level at the surface of the N-type silicon substrate. Therefore, if an electron-hole pair is produced in the surface layer 2, the possibility of the electron falling into the charge storage region 2a to cause a soft error is substantially the same as the possibility of the electrons being diffused into the N-type substrate 1. In contrast to this, when the surface layer 2 is formed by the diffusion method, the electron produced in the surface layer 2 is certain to fall into the N-type substrate 1. Accordingly, the effi- ciency of the function of preventing a soft error due to an alpha particle in the case of employing the epitaxial r#th method is slichili lower than in the case of employing the diffusion method. However, since most of the electron-hole pairs are produced in the substrate 1, as mentioned above, prevention by employing the epitaxial growth method is practical and satisfactory. Although the potential barrier is formed by the P-N junction between the P-type surface layer 2 and the N-type substrate 1 in the above described embodiments, the potential barrier may alternatively be formed by means of formi ng a concentration difference of impurities of the same conduction type. For example, a P-type semiconductor material may be used as the substrate 1 and a P -type surface layer 2 having a higher concentration than a P-type ray be formed on the substrate 1 by means of diffusion or epitaxial growth. Also for example, a P-type surface layer 2 may be formed on the P -type substrate 1 hazing a lower concentration than a P type. It should be noted that, when the concentration difference is utilized for forming the potential barrier, the external voltage V cannot be applied. However, the built-in potential ex , can be obtained between the P'- or P-type surface layer 2 and the P- or P -type substrate 1. As long as the built-in potential VBi satisfies the condition Vgi > KT/q, the built-in potential satisfactorily acts as a potential barrier for electrons produced by alpha particles. From the foregoing description, it will be understood that, according to the present invention, charges produced not only by alpha particles but also by cosmic rays or charges injected by forword bias of the neighbouring P-N junctions can considerably be prevented from being diffused into the charge storage region of a semiconductor device without preparing a special film. Consequently, in a se:niccnductor ice having a charge storage region, such as in a dynamic REr or a CCD, a soft error can be prevented easily and with certainty.

Claims: CLAIMS 1. A semiconductor device having a function of preventing a soft error, comprising: a semiconductor substrate (1), a surface layer (2) formed on the surface of said semiconductor substrate, the conduction type (P) of said surface layer being opposite to the conduction type (N) of said semiconductor substrate (1) so that a potential barrier is formed between said semiconductor substrate (1) and said surface layer (2), and a charge storage region (2a) formed in said surface layer (2), whereby, minority carriers derived from said semiconductor substrate (1) are interrupted from entering by thermal diffusion into said charge storage region (2a) by said potential barrier. 2. A semiconductor device as claimed in Claim 1 wherein said semiconductor substrate (1) is of an N type and said surface layer (2) is of a P type, so that a potential barrier for electrons is formed between said N-type semiconductor substrate (1) and said P-type surface layer (2). 3. A semiconductor device as claimed in Claim 1 wherein said surface layer (2) is formed by diffusing impurities of the opposite conduction type to said semiconductor substrate (1) on the surface of said semiconductor substrate (1). 4. A semiconductor device as claimed in Claim 1 wherein said surface layer (2) is formed by the epitaxial growth method. 5. A semiconductor device as claimed in Claim 1 wherein said semiconductor device is a dynamic random access memory having memory cells, each of said memory cells being comprised of one transistor and one MOS capacitor. 6. A semiconductor device as claimed in Claim 2 wherein said semiconductor device is a buried-strage type random access memory having memory cells, each of said memory cells being comprised of an N+-type buried layer (7) buried in said P-type surface layer (2). 7. A semiconductor device as claimed in Claim 1 wherein said semiconductor device is a charge-coupled device. 8. A semiconductor device as claimed in Claim 2 wherein the P-N junction between said P-type surface layer (2) and said N-type semiconductor substrate (1) is reversely biased by applying an external voltage. 9. A semiconductor device as claimed in Claim 1 wherein the thickness of said surface layer (2) is practically negligible in comparison with the thickness of said semiconductor substrate (1). 10. A semiconductor device as claimed in Claim 1 or 9 wherein the thickness of said surface layer (2) is less than 1/300 of the thickness of said semiconductor substrate (1). 11. A semiconductor device as claimed in Claim 2 wherein the potential difference between the highest potential in said surface layer (2) and the potential in said semiconductor substrate (1) is greater than the thermal energy of electrons. 12. A semiconductor device having a function of preventing a soft error, comprising: a semiconductor substrate (1) a surface layer (2) formed on the surface of said semiconductor substrate, the conduction type (P) of said surface layer being equal to the conduction type (P) of said semiconductor substrate (1), the concentration of the inpurities in said surface layer (2) being higher than said semiconductor substrate (1) so that a built-in potential is formed between said semiconductor substrate (1) and said surface layer (2), and a charge storage region (2a) formed in said surface layer (2), whereby, minority carriers derived from said semiconductor substrate (1) are interrupted from entering by thermal diffusion into said charge storage region (2a) by said built-in potential. 13. A semiconductor device as claimed in Claim 12 wherein said semiconductor substrate (1) is of a P-type and said surface layer (2) is of a P type. 14. A semiconductor device as claimed in Claim 12 wherein said semiconductor substrate (1) is of a P -type and said surface layer (2) is of a P-type. 15. A semiconductor device as claimed in Claim 12 wherein the thickness of said surface layer (2) is practically negligible in comparison with the thickness of said semiconductor substrate (1). 16. A semiconductor device as claimed in Claim 12 or 15 wherein the thickness of said surface layer (2) is less than 1/300 of the thickness of said semiconductor substrate (1). 17. A semiconductor device as claimed in Claim 12 wherein said built-in potential is greater than the thermal energy of electrons. 18. A semiconductor device as claimed in Claim 12 wherein said semiconductor device is a dynamic random access memory having memory cells, each of said memory cells being comprised of one transistor and one MOS capacitor. 19. A semiconductor device as claimed in Claim 13 or 14 wherein said semiconductor device is a buried-storage type random access memory having an N+-type buried layer (7) buried in said surface layer (2). 20. A semiconductor device as claimed in Claim 12 wherein said semiconductor device is a charge-coupled device.

Inventors: SAKURAI, JUNJI
Applicants: FUJITSU LIMITED
Application year: 1980
Main classification: H01L27
IPC codes: G11C11, H01L29, H01L23, H01L21, H01L27