DEVICE MANUFACTURE INVOLVING PATTERN DELINEATION IN THIN LAYERS

Abstract: Etch procedures are monitored electrically by initiation of current flow upon baring of conducting surface (19) to etching fluid (11). Procedures include photoresist development in which current flow is through the usual aqueous ionic developing solution. In an exemplary use, a specifically designed monitoring wafer (10) serves for detection of end point for a batch of wafers undergoing processing.

Description: DEVICE MANUFACTURE INVOLVING PATTERN DELINEATION IN THIN LAYERS Background of the Invention As integrated circuits have become more complex, it has become more important to control the photolithographic processes used to define such circuits. Typically a wafer to be processed is covered with a thin layer of photosensitive resist material and is selectively exposed to light of a proper wavelength. The resist layer is then developed by exposing it to an etchant that selectively etches it according to a pattern defined during the light exposure step. It is important that this development or etching be monitored so as to assure that neither over-etching nor under-etching produces inaccuracies in the final pattern. In particular, it has been recognized that it is desirable to monitor development to assure linewidth control. In ED-25, IEEE Trans. Elec. Dev. , 419 (1978), the author describes an optical monitoring procedure. End point development is detected by sensing a control region on the production wafer undergoing processing. The region is exposed to blanket exposure energy E β , and the important observation is made that an optimal value of E β bears a relationship to the desired patterning energy, E_, which is relatively insensitive to expected variations in processing parameters. The optical technique which depends upon variation in reflectivity of bared regions (regions underlying the resist layer which have been revealed by the selective etching) . While representing a significant advance, this technique may be difficult to implement on a production line. Linewidth control is important also during device processing levels following resist development. Fabrication depends heavily on etching, and adherence to prescribed tolerances is critical here as well. Summary of the Invention y> '/ An electrical test for detecting resist development end point or, more generally, for- detecting etch end point, is described. It depends upon a change in conductivity or other electrical parameters in a circuit which includes in series a counter electrode, an ionic fluid, and one or more regions which are exposed to the fluid when bared. In an embodiment, conducting regions on a monitoring wafer, initially hidden from the fluid by resist or other relatively low conductivity material to be removed (e.g. by resist "developing" or by process "etching"), when bared results in an increase in current or, alternatively, in a decrease in voltage drop which is sensed to indicate end point. The electrical indication yielded by the monitoring wafer is then used to control processing of a plurality of production wafers. It is convenient to discuss the invention in terms of a particular embodiment in which the etch procedure being monitored is development of a widely used positive acting photoresist. The material to be removed during etching is primarily a phenol formaldehyde—a novolac— while the fluid is a liquid—aqueous sodium hydroxide developer. A preferred embodiment involves use of a ' specifically designed monitoring wafer provided with a plurality of conducting stripes with circuit means for detecting baring of one or some greater number of stripes. Useful information which may be derived from this embodiment relates to uniformity of clearing—in turn, dependent on such factors as uniformity of exposure, of resist thickness, of development. Selection of positive resist monitoring as a preferred embodiment is based on exposing monitoring. Since material removed is exposed (rather than unexposed as in negative resist processing) , this variable is inherent in the control data. Brief Description of the Drawing FIG. 1 is a plan view of a specifically designed monitoring wafer usefully employed for monitoring development or other etching of a batch of production wafers; FIG. 2 is a sectional view in cross-section of a portion of the structure of FIG. 1; FIG. 3 includes a circuit representation and cross-sectional view of a monitoring wafer similar to that of FIG. 2 to result in an also depicted electrical output, in this instance, in terms of voltage-time coordinates; and FIG. 4 and 5 are plots, the first in coordinates of blanket exposure energy E β on the ordinate, and clearing time t c on the abscissa; and the second in coordinates of production wafer feature size on the ordinate and development time t D on the abscissa, which are useful for establishing the relationship between end point detection and the desired lithographic dimension as used manually or by computer in a preferred embodiment. Detailed Description ___• Terminology A. Etching: Removal of material to bare a substrate whether in lithographic- patterning or actual fabrication; contemplated removal is by fluid medium, usually by liquid medium. B_. Development: That species of etching specifically involving removal of resist material to produce a lithographic pattern. Since description is largely in terms of a preferred embodiment directed to resist development, the term should be understood as representative of the genus, "etching". C_. Delineation Material : Generic to resist but includes other material to be patterned in the course of which underlying surface of relatively high conductivity is bared to result in intimate contact with etching fluid. Delineation material other than resist includes material which is native to underlying surface material such as thermally oxidized silicon oxide, as well as material independent of underlying surface such as CVD-produced silicon nitride. Monitoring of removal of native products generally proceeds by use of a production wafer as a test wafer, although specific monitoring wafers may be used. D. Resist; Overlying material imbued with differential ease of removability as usually realized by uniform exposure to a developer by wetting. Resist, as so contemplated, is usually, but not necessarily, sensitive to patterning radiation. Resist material is generally organic or organo-metallic but may be inorganic, as well. Organics are represented by the common novolacs, while inorganics are represented by germanium selenium glasses with insoluble regions defined by silver introduced via photomigration. While resist layers may be retained, they are generally removed after having served to delineate regions to be processed both when used to fabricate separated masks and as used on devices undergoing processing. _E. Test Wafer: A generic term for a wafer provided with at least a surface region of requisite conductivity which is covered by delineation material of low conductivity relative to such region so that removal of such delineation material by etching results in baring of the region to the etchant, thereby increasing conductivity of a test circuit involving the region and an etching fluid. The test wafer may be either a production wafer or a specifically designed monitoring wafer. In either instance, it serves to indicate an etching end point for a batch of production wafers which are not part of the test circuit. F_. Monitoring Wafer; A wafer provided with one or more conducting regions generally in the form of conducting stripes explicitly designed for test purposes with measurements serving to monitor etching of an accompanying batch of production wafers. G_. Production Wafer: A wafer undergoing processing in the concerned stage, by removal of delineation material, to ultimately result in one or more devices. In this connection, "device" is used in its generic sense as encompassing individual devices, as well as integrated circuits. H. Test Circuit; A circuit including at least one conducting region on a test wafer as well as etching fluid so that an electrical parameter of the circuit— generally conductivity—is altered upon baring of such region by etching to remove overlying delineation material. _I. End Point: This term signifies desired termination of processing. Such processing is directed to removal of material to reveal features which are generally continuous over regions to be bared and which are of very closely controlled dimension. The end point of a process may correspond with clearing time (i.e., initial clearing of the first or n t-n region on the monitor) but as contemplated does not generally correspond with initial clearing on the production wafer. *_..• Clearing Time: This term relates to the electrically measured event signifying termination of the concerned interval. First baring of a conductive region results in the electrically detected change denoted "clearing time". This differs from "end point" which signifies the end of processing. 2_. The Drawing The figures are discussed in terms of a preferred embodiment in which monitoring is of development of a positive photoresist. FIG. 1 and 2: The test wafer is exemplified by an explicit monitoring wafer design useful for LSI fabrication. Silicon wafer 1 is a standard production wafer, in this instance, 7.62 cm. in diameter by 0.0508 millimeters thick. The substrate wafer surface is covered by insulating thermally produced silica (SiC^) layer 2 which is, in turn, covered by Si3N 4 layer 3. The six conducting paths or stripes 4 are platinum, deposited by sputtering. Complete fabrication of stripes 4 in¬ volves first deposition of titanium which acts as a "glue" layer but for these underlying layers are omitted. During fabrication of this monitoring wafer, an insulating layer 5 of silicon nitride (SiN) is deposited over the entirety of the now composite surface and is subsequently selectively removed so as to result in openings 6 in layer 5, one near the lower extremity of each stripe 4, and the other at enlarged contact regions of the stripes 4—the latter to permit a clip or wiping connection to complete a circuit external to the etching cell. Removal of nitride to produce openings 6 is by plasma etching. Layer thicknesses shown are exaggerated with layers 2, 3, 4, and 5 of approximate thicknesses 0.5 μm,.0.08 μm, 0.06 μm, and 1.0 μm, respectively. Resist layer 7 may be a novolac positive—acting resist and is identical in composition and in thickness to that on accompanying production wafers to be monitored. .FIG. 3 is a simple circuit representation which, in effect, is repeated for each of stripes 4. Depicted is a wafer 10 provided with coatings as shown in FIG. 2 immersed in developer 11 to the level shown and clamped in a probe fixture 12 designed to break through the resist in the enlarged region 13 (corresponding with regions 6 of FIG. 1). Counter electrode 14 is maintained at a predetermined potential by means of biasing means 15. Circuitry external to developer 11 is completed by means of dropping resistor 16 and test lead 17. Initially, there is no electrical connection between the immersed electrode 14 and the conducting path 18 (corresponding with stripes 4 on FIG. 1). Baring of regions 19 (corresponding with regions 6 of FIG. 1) results in current flow from counter electrode 14 through the developer to conductive paths 18. This current is sensed for each path 18 perhaps in terms of a developed voltage as sensed at lead 17 relative to ground or some other convenient circuit point, as illustrated in the plot which is on coordinates of output voltage and development time. On this plot, development end point is sensed as a steep rise in voltage to a threshold value v threshold* FIG. 4 and 5 are representative of data developed for calibration purposes for a preferred embodiment in which positive resist development is monitored. This data may subsequently be used in a computerized monitoring circuit to give an automatic cessation of etching (as by removal of production wafers from etchant, e.g. acqueous developer) . The plot of FIG. 4 is in coordinates of blanket exposure energy in millijoules/cm 2 (mj/cm 2 ) and clearing time (t c ) . Abscissa units have a typical value of the order of tens of seconds for the mid-point of the curve form. Plot 5 is on coordinates of feature size (minimum line width of a cleared line) in micrometers, μm, and development time. FIG. 4 relates to development (or, more generally, etching) of the test wafer, while FIG. 5 is concerned with the production wafer. _3. Procedure This section is largely in terms of the preferred positive resist embodiment. Applicability to other embodiments is similar. A. Calibration (determination of .E p /E β ) : The procedure contemplated may take a variety of forms. Common to all is a test wafer provided with a layer usually identical in nature to layers undergoing patterning. Under the layer to be patterned, there is at least one region of material, generally more electrically conductive than that of the overlying layer, which, upon being bared, results in an electrical signal. Alternatives include sensing of decreased conductivity upon removal of.relating conductive material as well as sensing of capacitance possibly in terms of a.c. measurement of diminishing thickness of dielectric being etched. The electrical signal which may be sensed, in terms of any of a variety of parameters, is directly or indirectly indicative of desired end point. A procedure, which has found considerable experimental use, is set forth. 8. The exemplary procedures depend upon a specifically designed monitoring wafer used as a processing control for a batch of production waters. The monitoring wafer design is that of FIG. 1, and consists of a silicon substrate of the same size and configuration as that of the production wafers. Isolation of the six platinum stripes is provided by insulation, first by native silica, and, finally, by a thin, deposited Si3N 4 . After fabrication of the stripes, the wafer is covered with a nonconductive SiN layer. The top insulating material is selectively removed in two regions of each stripe. The first is a small region to be exposed to etching fluid and the other is a large region near the edge of the wafer to facilitate electrode connection. In this procedure, the composite platinum-SiN surface is coated with positive novolac photoresist of the type in popular worldwide use in LSI -fabrication. Resist composition, thickness, etc., are identical to resist layers on production wafers to be monitored. At each processing step to be monitored—in this instance, at each lithographic step—a series of monitoring wafers are exposed at various blanket exposure energies E β and development clearing time t c is plotted as a function of Etø resulting in a curve of the form of FIG. 4. It is desirable to specify monitor regions (regions to be removed responsive to radiation in the instance of positive photoresist) of a size such that required exposure is independent of diffraction effects. For these purposes it is convenient to specify a least dimension of 25 ym which is sufficiently large relative to contemplated radiation wavelength to avoid this complication. Resist coated production wafers are exposed at a fixed pattern exposure energy E p , and feature size corresponding with least dimension -of cleared features is determined and plotted for various development times t D . The resulting plot is of the form of FIG. 5. The choice of desired feature size permits selection of a value of. required blanket exposure Eg for which monitoring wafer clearing time t c equals production wafer development time t D . This equivalency is set forth in FIG. 4 and 5 by the vertical broken line joining the two FIGS. This graphical determination, in turn, identifies a unique E p /E B ratio for each step. £5. Monitoring; When the production wafers are ready for processing, the monitoring wafer is clamped ' to a probe fixture which breaks through the resist in the large insulator-free areas near the edge of the monitoring wafer, thereby making electrical contact to the conducting paths on the wafer. The clamped monitoring wafer is lowered into the resist developer with the batch of production wafers to a sufficient depth to expose the lower extremities of- the stripes. Probe fixtures which are not immersed are maintained at potential V relative to a counterelectrode, for example, in accordance with the arrangement of FIG. 3. There is no electrical connection between the counterelectrode and the stripes until resist is developed away from the small platinum regions which are not protected by SiN. Upon clearing of each stripe region, an electrical path through the etch fluid is established. This condition is sensed for each stripe, and end point of production wafers being monitored is defined upon clearing of the desired fraction of stripes presented. Sensing of the desired stripe may be signalled in any manner or may initiate an automated step, such as withdrawal of the production wafers from the fluid and rinsing. C_. Variations on the monitoring procedure may take a variety of forms as discussed in Section 4 below. Aside from processing variations, i.e., monitoring of etching of layers which remain part of the device, response to sensed clearing time may be otherwise programmed. A significant variation is based on uniform blanket and production exposure with cessation of processing designed I i/ϋ - to occur at some multiple of monitoring wafer clearing time. Integrity of this alternative is, again, based on the invariant nature of the fraction E p /E B now expressed in terms of t D /t c . . Variants Many variants are usefully employed. These include: (1) Use of a specifically designed monitoring wafer in lieu of a production wafer serving as test wafer. (2) Use of a monitoring wafer as in (1) which is generally unmasked at least in terms of design dimensions (concerned area is of minimum dimension many times that of the design rules of production wafers) . This gives rise to the "blanket exposure"—Eg of a preferred embodiment. (3) Use of a monitoring wafer provided with a plurality of isolated conducting regions which are separately sensed. This gives rise to an increased degree of sophistication so that factors in addition to clearing time are made available. An example is measure of homogeneity of clearing due, e.g., to radiation uniformity, resist thickness uniformity, etc. (4) Use of monitoring wafers with added structure to minimize the likelihood of false readings. The prime example here is a masking layer between the conductive regions and the material to be etched. Minimal openings in such masking layer lessen the likelihood of false readings due to pinholes in the material to be etched. (5) Monitoring wafer regions may be of noble metal or other conductive metal which is unaffected in contemplated ambients. (6) Conductive regions may be designedly reactive to simulate a corresponding structure in a production wafer—e.g., such region may be silicon which is oxidized in situ to yield an overlying passivating layer which in the production wafer, itself, becomes the material to be etched. (7) While contemplated monitoring is in terms of /"V- that quantum change in electrical property due to initial baring, the measured interval of primary concern may be made to correspond with the initial baring of some conductive region after baring of the first region—e.g., reported work herein includes results obtained by use of the monitoring wafer of FIG. 1 in which "averaging" results from sensing of the third stripe to be bared. (8) Electrical sensing may make direct use of circumstances inherent in processing—e.g., the etching fluid may be the aqueous alkaline ionic developer commonly used for commercial positive photoresist so that the ionic current generally contemplated is at a readily measurable level. (9) Other types of fluids, even basically organic, may have sufficient itinerant conductivity to permit sensing or, alternatively, ionic material may be added primarily for monitoring purposes. Additions may include organic salts or acids, as well as inorganic ionic material. (10) Monitoring measurement may proceed across a gaseous or plasma etching fluid. (11) The test wafer may be a production wafer with portions of the circuitry themselves serving as sensed conducting regions. (12) The production wafer serving as a test wafer may be provided with a specifically designed region serving as monitor. Such a "hybrid" production-monitoring wafer may be identical to or different from other production wafers which are in the batch being monitored. With appropriate design, the monitor region may be unmasked (in terms of design rule dimensions) so that blanket exposure Eg is meaningful in terms, for example, of the discussion relating to FIG. 4 and 5. (13) Interpretation of data may be based on adjustment of exposure and other parameters to result in identical monitor and production etch time—for resist development or other procedures requiring exposure to radiation. Blanket exposures may be shortened to accommodate a larger integrated dose due to proximity effects. (14) Still assuming exposure to radiation, although other practice may be analogous, the monitor/production ratio of required etch time, essentially invariant for a given etching procedure, may be made part of the programming. In this example, the end point is indicated, not simultaneously with clearing of a monitor region, but at some multiple of this interval. (15) Sensing may be of any electrical parameter which shows a quantum change upon clearing. Examples include AC effects, as well as DC current, DC voltage, and DC capacitance. In the instance of plasma etching, ionic current flow resulting in charging may, itself, be sensed without separate external power supply.

Claims: Cla ims 1. A process for device fabrication on a batch of production wafers including the selective removal of first layered material simultaneously from said production wafers by means of etching fluid to define patterns in the first layered material, CHARACTERIZED IN THAT a test wafer (1) is included with said batch, said test wafer is provided with at least one monitor region (19) explicitly designed for monitoring underlying a second layered material (6) of composition and thickness resembling said first layered material, said second layered material being removed by said etching fluid (11) simultaneously with said selective removal of the first material to bare said monitor region, and a monitor means (12, 14, 15, 16, 17) is provided for electrically sensing a change in an electrical characteristic directly resulting from baring of said monitor region to yield information for determining an end point of selective removal of the first material. 2. The process of claim 1 CHARACTERIZED IN THAT said monitor region is at least 25 ym in any dimension parallel to a major wafer face. 3. The process of claim 2 CHARACTERIZED IN THAT said monitor region is a region of a production wafer. 4. The process of claim 2 CHARACTERIZED IN THAT said test wafer is a specifically designed monitoring wafer and is not a production wafer. 5. The process of claim 2 CHARACTERIZED IN THAT there is a plurality of said monitor regions. 6. The process of any of claims 1-5, CHARACTERIZED IN THAT said monitor region includes at least one conductive portion (18, 4) which has an electronic conductivity greater than that of the said monitor layered material. 7. The process of claim 6 CHARACTERIZED IN THAT said monitor region includes a plurality of conductive portions. 8. The process of claim 7 CHARACTERIZED IN THAT said plurality of conductive portions includes at least a pair of said conductive portions which are electrically isolated. 9. The process of claims 6, 7, or 8 CHARACTERIZED IN THAT said monitor means includes a counter¬ electrode (14) spaced from the said test wafer and biasing means (15) for biasing said counter-electrode relative to said conductive portion and in which at least a portion of both the said counter-electrode and the said conductive portion are below a surface of the said etching fluid (11) . 10. The process of claim 9 CHARACTERIZED IN THAT the said etching fluid is an aqueous ionic solution. 11. The process of claim 9 CHARACTERIZED IN THAT both the said first layered material and the second layered material are a resist with selective removal resulting in aperture delineation of a masking layer designed to limit subsequent processing to material underlying the resist in regions corresponding with apertures in the said masking layer. 12. The process of claim 11 CHARACTERIZED IN THAT the said resist is a radiation-sensitive resist with selective removal resulting from variation in solubility of the said resist as between irradiated and nonirradiated resist portions. 13. The process of claim 12 CHARACTERIZED IN THAT the first layered material is exposed to a patterning radiation of a patterning dose and in which the second layered material is exposed to a monitor radiation of a monitor dose and in which said patterning dose and said monitor dose are designedly different to accommodate a difference in etching rate due primarily to a difference in dimension as between said monitor region and the said patterns of the first layer. 14. The process of claim 6 CHARACTERIZED IN THAT the end point is determined from baring of an isolated conductive portion subsequent to baring of the said conductive portion. 15. The process of claims 3 or 4 CHARACTERIZED IN THAT the said first layered material consists essentially of a silicon compound. 16. The process of claim 15 in which the said silicon compound is a native compound produced by in situ reaction of silicon. 17. The process of claim 1 CHARACTERIZED. IN THAT the etching is terminated upon the said baring. 18. The process of claim 17 CHARACTERIZED IN THAT etching is terminated automatically in response to said electrical sensing. 19. The process of claim 1 in which etching is terminated after a prescribed period following baring. 20. Process of claim 19 in which etching is terminated automatically in response to said electrical sensing. 21. A device produced in accordance with the process of claim 1.

Inventors: MCGILLIS D
Applicants: WESTERN ELECTRIC CO, WESTERN ELECTRIC CO INC
Application year: 1980
Main classification: H01L21
IPC codes: G01N17, G01R31, G03F7, H01L21