APPARATUS FOR USE IN TELEPHONE COMMUNICATION

Abstract: A time assignment speedch interpolation communication system for interconnecting a transmission trunk link having a first plurality of communication channels to a second plurality of telephone communication lines, the second plurality exceeding the first plurality, each of said second plurality of telephone communication lines comprising sepa­ rate voice transmission means and signalling transmission means and each of the first plurality of communication channels comprising separate trunk voice transmission means and trunk signalling transmission means, said system including apparatus for carrying out time assignment inter­ polation of signalling information carried on said signalling transmission means and comprising: first signalling detection means coupled to said signall­ ing transmission means, first switching means operated by said signalling detec­ tion means for selectively connecting signalling transmis­ sion means carrying signalling information to available trunk signalling transmission means, and second switching means coupled to said trunk signalling transmission means for coupling said trunk signalling transmission means carrying signalling information to avail­ able siganlling transmission means at a remote location in accordance with received assignment information. To provide assignment information indicating activity of said first switching means to said second switching means, said apparatus comprises transmission apparatus located at a first end of said transmission trunk link and operative for transmitting assignment information over said first plurality of communication channels to said trunk signalling transmis­ sion means. Second signalling detection means are coupled to said trunk signallung transmission means to provide an output indication of receipt of signalling information at said second switching means. Delay means are coupled to said signalling transmission means and are operative to delay signalling information carried thereon until said second switching means is opera­ tive to complete a connection therefor.

Description: "APPARATUS FOR USE IN TELEPHONE (DOERJNICATION n The present invention relates to telephone switching apparatus and more particularly to a TASI ( Time Assignment Speech Interpolation) communications system. Time Assignment Speech Interpolation (TASI) communication systems have been known for approximately twenty years. Their function, stated in general terms, is to exploit the fact that during a normal telephone conversation, information is being transmitted only about 35X of the time. TASI communication systems serve to connect a speaker to a transmission line only during those portions of a conversation when speech is actually present. During the other portions of the conversation, the transmission line is connected to another speaker, currently speaking in another conversation. By using time assignment speech interpolation a given number of transmission lines, say 24 can usually carry about 48 simultaneous conversations. Most of the prior art patents known to applicants relate to systems in which assignment, synchronization and acknowledgement messages between TASI apparatus on opposite ends of a transmission trunk link are passed along control lines, separate from the voice carrying lines, This arrangement involves a number of disadvantages, principal among which is the vulnerability of the entire transmission trunk link to failure of the control lines, Another disadvantage is the inability of the conventional TASI systems to readily sense and bypass inoperative voice lines. Although the use of digital telephone trunks is increasing rapidly in the U.S., the majority of telephone trunks in the U.S. and throughout the world will remain analog during the coming few decades. There Is therefore a need for TASI-type equipment capable of use with both analog and digital telephone trunks. There is also need for apparatus capable of operation with analog trunks which overcomes the design disadvantages of the prior art analog apparatus which is described in many of the prior art patents. No such apparatus presently exists. It is also noted that no TASI-type equipment is presently available for use with out of band signalling. The present invention seeks to provide a TASI communication system which is capable of use with both analog one or more of and digital telephone trunks and which overcome 4 the disadvantages described hereinaboveanor of other disadvantages. one aspectof There is thus provided in accordance within embodiment of the present invention a time assignment speech interpolation communication system capable of interconnecting a transmission trunk link having a plurality of digital or analog communication channels to a second plurality of telephone communication lines, the second plurality exceeding the first plurality, and comprising: transmission apparatus at a first end of the transmission trunk link including means for detecting signals on said second plurality of telephone coni: :unication lines and means for assigning each telephone communication line on which signals are present to an available one of the first plurality of communication channels; receiving apparatus at a second end of the tratismission l,k including means for assigning each of the first plurality of communication channels carrying signals to a corresponding one of said second plurality of telephone communication lines in accordance with assignment information received from said transmission apparatus; and apparatus for communicating messages including assignment information between said transmission apparatus and said receiving apparatus; said transmission apparatus, receiving apparatus and message communicating apparatus busing operative for selectable analog and digital signal transmissions along sai, transmission trunk link. In accordance with another aspect of an embodiment of. the present invention there is provided: a, tlme.asslgnment speech interpolation communication system for Interconnecting a transmission trunk link having a first plurality of communtcatton channels with a defined signal transmission frequency band to a second plurality of telephone communication lines, the second plurality exceeding the first plurality, and comprising; transmission apparatus at a first end of the transmission trunk link Including means for detecting signals on said second plurality of telephone communication lines and means for assigning each telephone communication line on which signals are present to Mn available one of the first plurality of communication channels; ; receiving apparatus at a second end of the transmission link including means for assigning each of the first plurality of communication channels carrying signals to a corresponding one of said second plurality of telephone communication lines In accordance with assignment information received from said transmission apparatus; and apparatus for communicating messages including assignment information between said transmission apparatus and said receiving apparatus in said signal trans mission band in serial data form along said first plurality of con nication channels. In accordance with still another embodiment of this invention there i3 provided: a time assignment speech interpolation communication system for interconnecting a transmission trunk link having a first plurality of communication channels to a second plurality of telephone communication lines, the second plurality exceeding the first plurality, each of said second plurality of telephone communication lines comprising separate voice transmission means and signalling transmission means and each of the first plurality of communication channels comprising separate trunk voice transmission means and trunk signalling transmission means, said system including apparatus for carrying out time assignment interpolation of signalling information carried on said signalling transmission means and comprising: : first signalling detection means coupled to said signalling transmission means; and first switching means operated by said signalling detection means for selectively connecting signalling transmission means carrying signalling information to available trunk signalling transmission means; and second switching means coupled to said trunk signalling transmission means for couplina said trunk signalling transmission means carrying signalling information to available signallinq transmission means at a remote location in accordance with received assignment information. Preferably said apparatus also comprises means for providing assignment information indicating activity of said first switching means to said second switching means. Advantageously said means for providing assig-w-ent information comprises-transmission apparatus located at a first end of said transmission trunk link and operative for transmitting assignment information over said first plurality of co=nuni- cation channels. Preferably said transmission apparatus is operative for transmitting assignment information to said trunk signalling transmission means. Preferably said system also comprises second signalling detection means coupled to said trunk signalling transmission means for providing an output indication of receipt of signalling information at said second switching means. Preferably said system also comprises delay means coupled to said signalling transmission means and operative to delay signalling information carried thereon until said second switching means is operative to complete a connection therefor. The present invetnion will be more fully understood and appreciated from the following detailed description taken in conjunction with the drawings in which: Fig. 1 is a block diagram illustrating the orientation of the apparatus of the invention in a telephone system; Fig. 2 is a block diagram illustration of the apparatus of the system except for out of band signalling apparatus; Fig. 3 is a timing diagram indicating various timing frames employed in the apparatus of the invention; Fig. 4 is a block diagram of transmit timing circuitry; Fig. 5 is a main timing diagram of the ystem; Fig. 6 is a timing diagram of the transmit synchronization timing; Fig. 7 is a block diagram of receive timing circuitry; .Fig. 8 is a timing diagram of the receive synchronization timing; Fig. 9 is a block diagram of interface circuitry; ; Fig. 10 is a block diagram of the transmit speech flow in the circuitry of Fig. 2; Fig. 11 is a timing diagram of the transmit speech flow timing; Fig. 12 is a block diagram of the receive speech flow in the circuitry of Fig. 2; Fig. l3 is a timing diagram of the receive speech flow timing; Fig. 14 is a block diagram of speech detection circuitry; Fig. 15 is a simplified illustration of a portion of the circuitry of Fig. 14; Fig. 16 is a simplified illustration of echo suppression circuitry forming part of the circuitry of Fig. 14; Fig. 17 is a functional block diagram of the CPU; Fig. 18 is a flow chart indicating operation of message interrupt operations of the CPU; Figs. 19- 22 are flow charts illustrating monitor operations of the CPU; Fig. 23 is a flowchart illustrating operation of the interrupt function of the CPU; ; Fig. 24 is a flowchart illustrating the acknowledge subroutine of the CPU; Fig. 25 is a flowchart illustrating the system synchronization protocol; Fig. 26 is a flowchart illustrating the synchronization routine of the system; Fig. 27 is a flowchart illustrating the main routine of the system; Fig. 28 is a block diagram of the transmitter control memory; Fig. 29 is a block diagram of the receive control memory; Fig. 30 is a block diagram of the modem transmitter; Fig. 31 is a block diagram of the modem receiver; Fig. 32 is a block diagram of transmit signalling circuitry; Fig. 33 is a block diagram of receive signalling circuitry; Fig. 34 is a block diagram illustrating the placement of a concentrator of the present invention in a remote switching configuration; ; Fig. 35 is a block diagram illustrating the component portions of theconcentrator of the present invention at one end of a remote switching configuration; Fig. 36 is a schematic illustration of interface circuitry coupling a 2-wire telephone line with a 6-wire telephone channel at a subscriber end of a remote switching configuration; and Fig. 37 is a schematic illustration of interface circuitry coupling a 2-wire telephone line with a 6-wire telephone channel at a C.O. end of a remote switching configuration. Reference is now made to Fig. 1 which illustrai 9 4 2 6 communications system including time assignment speech interpolation (TASI) apparatus constructed and operative in accordance with an embodiment of the invention. The communications system comprises a transmission trunk 100 including a microwave radio portion 102 having a pair of transceivers 104 linked by relay apparatus 106. The transmission link may additionally or alternatively comprise a coaxial cable portion'l08 which may operate in parallel to the microwave link and which is provided with suitable amplification apparatus 110. At both ends of the transmission link 100 there are provided Frequency Division Multiplexers 112 and 114 of conventional construction and operation and each of which is connected to a plurality of carrier multiplexers 116 of conventional construction and operation, such as and Z - 12 or System 7 of Siemens. The total number of terminals of each of the carrier multiplexers 116 at each end of the transmission link represents the total number of communications channels available over the transmission link In the exemplary embodiment illustrated herein, TASI apparatus 120 and 122 is connected to each group of 24 terminals of the carrier multiplexers at respective ends of the link. transmission trunk. Each TASI apparatus of the invention is also connected to a respective relay set 124, 126 which is connected, in turn via suitable exchange equipment (not shown) to 48 active subscriber lines. By " active subscriber line 2' is meant a line which is currently assigned by exchange equipment to the relay set and which is potentially in use for carrying a conversation. In fact only about 85% of the active subscriber lines are actually carrying conversations at any given time during peak load periods under normal conditions. It is appreciated that in the illustrated embodiment,' TASI apparatus suitable for use with 48 active subscriber lines and 24 communications channels is shown. It is within the scope of the invention to provide larger capacity TASI apparatus or smaller capacity units. It is noted that the unit must have a sufficient number of communications channels available to it to enable it to operate at a 2 to 1 ratio of active subscriber lines to communications channels without an unacceptable incidence of freeze-out, i.e. denying service to a given subscriber line during voice transmission thereby. Reference is now made to Fig. 2 which is a block diagram illustration of the portion of the TASI apparatus which deals with voice transmissions over communications channels. For the purposes of background and definition, it is to be understood that a conventional telephone with out of band signalling is coupled to an exchange normally by two wires. Circuitry in the exchange converts the two wire connection to a six wire connection including two wires for passing dialling and billing information, for example, and four wires, two in each direction for carrying voice or other information. It is appreciated that the six wire telephone connection is used only with out of band signalling. In band signalling requires only a four wire connection which carries only audio signals. The apparatus illustrated in Fig. 2 receives only the four voice connections. The signalling channels are dealt with by apparatus illustrated in block diagram form in Pigs. 32 and 33. The term "communication channels" used throughout the specification and claims refers to trunk channels which carry voice communications. Trunk channels which carry only signalling are referred to herein as trunk signalling lines. It is noted that the TASI apparatus of the present invention need not necessarily be associated with relay sets or with any other particular type of interconnecting or switching circuitry. The term " telephone communication line " will be used hereinafter and in the claims to denote one of the, typically 48, lines which may carry signals, voice, or otherwise, which it is desired to communicate via one of the communication channels. The term Inactive subscriber line " defined hereinabove refer to a telephone communication line which is associated with the use of a relay set. Referring now to Fig. 2 there is seen a block diagram illustration of a time assignment speech interpolation communications unit constructed and operative in accordance with an embodiment of the invention. Forty -eight analog input lines are each connected to a relay set (not shown) and are received at respective inputs of 48 audio transformers 10. The outputs of the audio transformers 10 are supplied to AF 133 (National) low pass filters and amplifiers 12, also 48 in number. The outputs of the low pass filters and amplifiers 12 are supplied to 48 MK 5116 coders (Mostek) 14 which convert the audio inputs into 8 bit serial digital signals. The outputs of the 48 coders 14 are supplied, via a switch 16, to a serial to parallel converter 18. It is a particular feature of the embodiment of the invention illustrated herein that switch 16 is operative to input to the serial to parallel converter either thecutputs from coders 14 or digital inputs such as a standard PCM (Pulse Code Modulation) output. Thus the versatility of the time assignment speech interpolation communications unit is greatly increased, enabling it to operate with analog or diqital signal transmissions or a combination thereof. Where digital outputs from standard PCM apparatus such as a T 1 trunk are received, the received digital signal is supplied to synchronization circuitry 20 and thence to the serial to parallel converter 18. The synchronization circuitry 20 is operative to process the normal 193 bit frame timing such that only the 192 information bits are dealt with by the circuitry that follows the serial to parallel converter* and the additional bit is used to define the signalling bit timing, and is described later In detail. The circuitry described above, comprising low pass filters and amplifiers 12 and coders 14 will be referred to hereinafter as coder circuitry, it being appreciated that coders 14 and decoders 66 described hereinafter are embodied in a MK 5116 CODEC chip. The output of serial to parallel converter 18 is supplied to a peak detector 22 and to a transmitter delay memory 24, which are illustrated in Fig. 10 which will be described hereinafter. The operation of the transmitter delay memory 24 is entirely digital and provides a delay of 48 ms and supplies an output to a transmitter buffer memory 26, such as a Motorola 6810. The output of transmitter buffer memory 26 is supplied to a parallel to series converter 28, whose output is provided via a switch 30 either to syncrhonization circuitry 31 or to 24 decoders 32, each embodied in a MK 5116 chip, depending on whether analog or digital signal transmissions are involved. The output of each decoder is to an AF 134 low pass filter and amplifier 34. The output of each filter and amplifier 34 is supplied via an audio transformer 36 to one of 24 communications channels in the transmission trunk link. The output of synchronization circuitry 31 is supplied as a 193 bit digital output to a digital transmission trunk such as a T 1 trunk. Considering now the received signals from the transmission trunk link received on the 24 communications channels, these are supplied via coder circuitry comprising 24 audio transformers 40, 24 AF 133 low pass filters and amplifiers 42 and 24 MK 5116 coders 44 , embodied together with decoders 32 in MK 5116 CODEC chips, and via a switch 46 to a serial to parallel converter 48. The output of the serial to parallel converter 48 is supplied to a receiver delay memory 50 (Fig.12) and thence to a receiver buffer memory 52. Synchronization circuitry 47 receives a digital input such as standard PCM from the transmission trunk and operates similarly to synchronization circuitry 20. It is noted that switches 30 and 46 may be controlled together with switch 16 such that when digital information is being supplied, the coder and decoder circuitry is bypassed and the signals pass via the synchronization circuitry which deals with the 193'rd bit of the PCM format. The output of receiver buffer memory 52 is supplied to a parallel to serial converter 56 which also receives an input from blanking logic circuitry 58 which operates in response to an output from a receiver control memory 60. The output of parallel to serial converter 56 is supplied via a switch 62 either to digital outputs such as a standard PCM via synchronization circuitry 64 similar to syncrhonization circuitry 31, or alternatively to decoder circuitry comprising 48 MK 5116 decoders 66, mentioned above, each followed by an AF 134 low pass filter and amplifier 68 and an audio transformer 70. The outputs of the 48 audio transformers are supplied each to a line of a 48 line analog output which may interface with a relay set. It is noted that in accordance with an alternative embodiment of the invention, switches 16, 30, 46 and 62 may be independently controlled so as to enable digital transmissions received from a telephone communication line to be transmitted along an analog trunk and vice versa. It is also appreciated that the telephone communication lines and the communication channels may be selectably divided between analog and digital lines, as required by the intended use of the system. The proportion can be changed readily, should use requirements change over time. The output of peak detector 22 is supplied to one input of a comparator 53 which also receives an input from Expected Echo Arithmetic Logic Unit 55. Unit 55 determines the threshold of comparator 53 in response to the output of the receiver buffer memory 52 which indicates the signal amplitude of the 48 telephone communication lines, and which will be described in detail hereinafter. The output of comparator 53 is supplied to SPD Arithmetic Logic Unit circuitry 57, which will be described in detail hereinafter. The output of circuitry 57 is supplied to a Central Processing Unit 59, which will be described hereinafter in detail. The output of the receiver delay memory 50 is supplied to a receiver modem 61, which in turn provides an output to the CPU 59. The receiver modem scans the delay memory 50 to detect received messages in the contents of memory 50 and to transfer the contents thereof to the CPU. The receiver modem operates in association with a speed up counter 63 which addresses the delay memory 50 during scanning thereof by the receiver modem. In response to a change in the output of the SPD ALU circuitry 57, the CPU 59 provides control inputs to z transmit control memory 65. Memory 65 contains the data which defines which of the 48 telephone communication lines are coupled to which of the 24 communication channels. This information is defined by the dynamic assignment of communication channels to telephone communication lines and is indicated by an output of the control memory 65 to transmit buffer memory 26, which is selectably read in accordance with the output of the control memory 65. The CPU also provides control inputs to a transmit modem 67 which indicate the contents of the message to be transmitted as well as the communication channel on which the message is to be transmitted. The message is transmitted by an output of the transmitter modem 67 to parallel-serial converter 28 In accordance with timing signals provided by transmitter timing circuitry 69. Timing circuitry 69 will be described hereinafter in detail and provides an output to serial to parallel converter 18 and an output to parallel to serial converter 28 in addition to providing timing signals to transmitter modem 67, and providing timing signals to the transmitter delay memory 24 and the transmitter control memory 65 in order to synchronize the operation thereof4 The various elements of the transmitter circuitry described hereinabove will be described hereinafter in greater detail with reference to detailed block diagrams and schematic illustrations. It is noted that a variety of control functions are assigned to the CPU and appreicated that alternatively these control functions may be carried out by discrete dedicated circuitry. Simplicity of design and economy are achieved by use of the CPU as described herein. The receiver circuitry will be described hereinafter in greater detail with reference to Fig. . Receiver control memory 60 is updated by inputs from the CPU 59 in response to messages received at the modem receiver 61. Receiver timing circuitry 71 provides an address to the receiver control memory 60 for governing the read/write cycle thereof in a sequential manner and also provides outputs to receiver buffer memory 52, receiver delay memory 50, speed up counter 63, parallel to serial converter 56, serial to parallel converter 48 and receiver modem 61, for synchronizing the operation thereof. Reference is now made to Fig. 3 which is a diagram illustrating the relationship between the various timing periodicities employed in the embodiment of the invention presently described. Since the apparatus of the invention operates in association with digital or analog transmission trunks, T 1 timing, used in digital transmissions is adopted as the timing base of the system so as to enable straightforward connection to T 1 transmission links. The basic timing frame comprises 193 data bits representing 24 channels, each represented by 8 PCM coded bits and a 193'rd framing bit. As the standard sampling rate is 8 KHz, the duration of each basic timing frame is 125 microseconds. A synchronization frame comprises 12 basic frames and is of duration 1500 microseconds. The 193'rd bits of each basic timing frame indicate the signalling synchronization phase. Singalling information is transmitted during the sixth and 12th basic timing frames of each syncrhonization frame. Each data bit is of duration 0.65 microseconds approximately. The duration of each channel data period is 5.18 microseconds, such that the 8 PCM coded bits which it comprises each are of duration 0.65 microseconds. Each channel data period is divided into 8 timing pulses t A - t H each of duration 0.65 microseconds and is also divided into two cycles, each comprising 8 timing pulses each of puration 0.32 microseconds approximately and identified as P 1 - P 8. Each timing pulse t.A - t H includes 9 timing pulses t 1 - t 9, each of duration 62 nanoseconds. It will be noted that two independent timing sources are employed in the apparatus of the invention. Both produce pulses of the periodicities described hereinabove. The pulses are distinguished from each other by subscripts T and R which refer to either the transmitter or receiver timing respectively. Reference is now made to Fig. 4 which is a block diagram of transmitter timing circuitry 69 mentioned in connection with Fig. 2. A phase lock loop 200 receives an oscillator input at 1.544 MHz via a switch 202 from either an oscillator 204 such as a Tadiran OTIS or from an external source such as a T 1 digital clock source. The phase lock loop 200 is typically an XR 215 and provides an output to a frequency divider 206, such as an LS 161 whose output is fed back to a second input of the phase lock loop. The phase lock loop thus operates as a frequency synthesizer, producing an output signal of frequency 15.4,4 MHz which is the basic frequency used in the circuitry. The output of divider 206 is supplied via an AND gatejand an OR gate 210 to a synchronous "192 + 1 counter" 212, typically comprising a divide by 8 counter 214 and a divide by 24 counter 216 both of which are typically LS 161 chips. The counter 214 provides CLB, CLA and CAO outputS, while counter 216 provides outputs CA 1 - CA 5. A four input AND gate 218, which receives inputs from Counter 212 provides an output signal every 192nd and 193rd pulse. This output signal is supplied to the SET input of a flip-flop 220, which provides an output to AND gate 208. the output of AND gate 218 is also supplied to a flip-flop 222, whose output is supplied as a reset input to counters 214 and 216. OR gate 210 also receives an input from an AND gate 224 which receives an input from synchronization circuitry 20 (Fig. 2) which a T 1 digital input is received. This connection enables synchronization of the operation of counter 212 with the T 1 timing input signals. The output of the phase-lock loop 200, hereinafter referred to as CL is supplied to a shift register 226 comprising LS 74 and LS 164 chips and which provides t 1 - t 9 timing outputs. The CLC output of AND gate 208 is supplied to a clock generator for codecs 228 which provides TXC and RXC outputs and comprises an LS 164 chip. The CLC, CLB and CLA outputs are supplied to a decoder 230 such as an LS 138 and which provides timing outputs P1 - P 8. The CLB, CLA and CAO outputs are supplied to a decoder 232 such as an LS 138 which provides timing outputs t A - t H. The output of flip-flop 222 is supplied as an initiate pulse together with clock pulse CAO to a synchronization pulses generator 234, comprising 3 LS 164 chips and which provides synchronization pulses SYNC 1 - SYNC 24. The output of flip-flop 222 will be referred to hereinafter as the " 193 " pulse. The synchronization circuitry 20, 47 (input) 31, 64 (output) shown in Fig. 2 will now be described. It is understood that this circuitry is required only when a T 1 carrier is connected to the system, and provides the necessary synchronization between the system timing and the external PCH apparatus. A counter 236 receives the 193 pulse and counts the basic timing frames in cycles of 12. A pair of AND gates 238 and 240 code the 6th and 12th states of the counter to identify signalling frames. A shift register 242 shifts in the 193 bit from each of the 12 basic timing frames and an AND gate 244 decodes the synchronization pattern at the output of shift register 242. The output of AND gate 244 is coupled to a flip-flop 246 via an AND gate 248 and is also coupled directly to a flip-flop 250. The 193 pulse is supplied as a clock input directly to flip-flop 246 and via an AND gate 252 to flip-flop 250 as a clock input. AND gate 252 multiplies the 193 pulse by the output of AND gate 240. When the apparatus is in the state of synchronization acquisition, both flip-flops 246 and 250 are reset. When a synchronization pattern appears at the output of shift register 242, flip-flop 246 is set. The synchronization is verified by checking the apparance of the synchronization pattern at the output of shift register 242 at the end of the next cycle of 12 basic timing frames. If during synchronization acquisition, no synchronization pattern appears at the output of shift register 242 during 12 basic timing frames, an additional clock input is provided to AND gate 224 from an AND gate 254 which receives the output of AND gate 240 and the inverted output of flip-flop 246. The additional clock input causes a shift in system timing by one data bit period. When synchronization Is achieved, flip-flop 250 is set and an error counter 256 is preset every basic timing frame via an AND gate 258 which also receives the 193 pulse. When synchronization is lost the preset is terminated and the error counter is incremented by the 193 pulse. When the counter reaches eight error counts it resets flip-flops 246 and 250 and the apparatus returns to a synchronization acquisition state. The above circuitry is comprised in the synchronization input circuits 20 and 47 of Fig. 2. The synchronization output circuitry additionally comprises a 12/1 multiplexer 260 which has a hard wired input representing a predetermined synchronization pattern, and is addressed by a four bit output from counter 236. The output of multiplexer 260 is supplied to an input of a 2/1 multiplexer 62 which receives the OUT DATA output from the parallel to serial converter (28 or 56 in Fig. 2). Multiplexer 260 inserts the synchronization pattern bit by bit in the 193rd time slot of the basic timing frame. The output of multiplexer 262 is supplied to an external PCM device. Fig. S is a timing diagram of the tilting circuitry of Figs. 4 and 8 and will not be described in the text in detail for purposes of conciseness. Fig. 6 is a timing diagram of the interrelationship of the outputs of szunchronization pulse generator 234 (Fig. 4). Fig. 7 is a block diagram of receiver timing circuitry which corresponds exactly to the timing circuitry of Fig. 4 and which will not be described here for the sake of conciseness. Fig. 8 is a timing diagram of the interrelationship of the outputs of the synchronization pulse generator shown in Fig. 7. Reference is now made to Fig. 9 which is a block diagram of the interface circuitry for use with analog transmissions. 48 of these circuits interconnect the apparatus with 48 telephone communication lines and 24 of these circuits interconnect the apparatus with 24 communication channels in the illustrated embodiment. An audio input from either a telephone communication line or a communication channel is supplied to a protection circuit 75 whose output is supplied to a transformer 77 (10 or 40 in Fig. 2). The center tap of the transformer 77 is connected to the input of a detector 79 which detects a ground potential provides by multiplex equipment external of the apparatus and indicating a busy status. The output of transformer 77 is supplied to an input amplifier 81 for adjusting the signal level at the input to that required by the coder. The output of amplifier 81 is supplied via a low-pass filter 83 to a coder 85 (14 or 44 in Fig. 2), which receives timing and clock inputs from timing circuitry described hereinabove. In response to receipt of a code synchronization signal from the timing circuitry, the coder provides an 8 bit serial channel data output. Decoder 87 (32 or 66 in Fig. 2) receives 8 bit serial input data from parallel to serial converter 28 or 56 (Fig. 2) and clock and timing inputs from the timing circuitry and provides an analog output to a low pass filter 89. The output of filter 89 is supplied to an output amplifier 91 which receives an input from a noise generator and a 6 dB attenuation command signal from SPD/ALU circuitry 57 (Fig. 2). The output of amplifier 91, being a combination of the input from filter 89 and from the noise generator, is supplied to a transformer 93 (70 or 36 in Fig. 2). The output of transformer 93 is supplied via a protection circuit 95 to the audio output to either a telephone communication line or a communication channel. A BUSY OUT signal from signalling circuitry is supplied via a buffer 97 to a relay 99. When relay 99 is activated, a BUSY signal is applied to the audio output via the center tap of transformer 93. Out of band signalling input signals M or E are supplied via an optocoupler 99Xto an input of the signalling circuitry. A buffer 101 receives a signalling output from the signalling circuitry and drives relay 103 which when activated transmits an E or M signal. A regulator 105 supplies reference voltages for,the coder and decoder. Reference is now made to Fig. 10 which illustrates the transmit speech flow apparatus which comprises the serial to parallel converter 18, transmit delay memory 24, transmit buffer memory 26 and parallel to serial converter 28 illustrated in Fig. 2 and described hereinabove. A pair of serial to parallel converters 111 and 113 each receive via switches 115 and 117 24 digital inputs either from the outputs from coders 14 (Fig. 2) or directly from the T 1 output of PCM apparatus, via synchronization circuitry 20. The serial to parallel converters 111 and 113 are each typically embodied in a single LS 164 chip, and are arranged to receive alternatively numbered telephone communication line outputs. Thus, while multiplex information from lines1, 3, 5 etc is received at converter 111, multiplex information from lines 2, 4, 6, etc. is received at converter 113. The two serial to parallel converters 111 and 113 operate on the same time base. The output of converter 111 is supplied directly to a 2/1 multiplexer 119 while the output of converter 113 is supplied to the multiplexer 119 via a latch 121 such as a LS 374 which holds the data for an additional half cycle in order to enable the multiplexer to pass the data alternatively from converter 111 and 113. The output of multiplexer 119 is held temporarily in a latch 123, such as an LS 374. The output of latch 123 is supplied to peak detector 22(Fig. 2) and to transmit delay memory 125. The datatransfer rate at the outputs of converters 111 and 113 is an 8 bit parallel output every 5.18 microseconds per converter. Thus the rate at which data enters the delay memory is an 8 bit parallel couput every 2.59 microseconds. The transmit delay memory typically comprises 16 Mostek 4116 chips having a capacity of 384 bytes for each of the 48 telephone communication lines and thus providing a delay of 384 125 microseconds delay per byte at 8 KHz sampling rate = 48 msec. Counters 127 and 129 provide addressing for the delay memory 125. Counter 127 provides the identification of the telephone communication lines and counter 129 provides sequencing through the bytes of the delay memory. The basic operation of the delay memory is reading out to latch 131 the oldest sample and inserting the most recently received sample in the memory. from latch 123. Delay memory 24 (Fig. 2) comprises delay memory 125 , counters 127 and 129, and latch 131. The output of latch 131 is supplied to a buffer memory 133, typically a Motorola 6810 and having a 48 byte capacity. The function of the buffer memory is to accomodate the cyclically operative decoders 32 (Fig. 2) provided at the output of the circuitry to interface with analog transmission apparatus. The buffer memory 133 operates cyclically on its WRITE cycle corresponding to receipt of information from 48 telephone communication lines being controlled by the CAT O - CAT 5 outputs from counter 127. On its READ cycle, the buffer memory is controlled by the CMT O - CMT 5 control memory outputs which run cyclically along 24 communication channels but randomly with respect to the control memory contents. This operation effects switching of 24 out of the 48 telephone communication lines onto the 24 communication channels. In the case of equipment malfunction a command for 1-1 operation of the buffer memory is generated in the CPU causing the the same 24 telephone communication lines to be continuously connected to the 24 communication channels. Multiplexer 135 controls the address to the buffer memory and thereby determines its mode of operation. The output of buffer memory 133 is supplied to a 2/1 multiplexer 137 such as an LS 157. Multiplexer 137 is operative in response to control signals from modem transmitter 67 (Fig. 2) to transmit via a latch 139 , such as an LS 374) either the output of buffer memory 133 or alternatively message samples from the modem transmitter to parallel to serial converter 141 (28 in Fig. 2). The output of converter 141 is supplied via a switch 143 (13 in Fig. 2) to the 24 communication channels or to T 1 digital apparatus. Fig. llis a detailed timing diagram of the circuitry illustrated in Fig 10. Reference is now made to Fig.12 which illustrates the receive speech flow apparatus which comprises serial to parallel converter 48, RX delay memory 50, speed up counter 63, RX buffer memory 52, parallel to serial converter 56 and blanking logic 58. Twenty-four communication channels are connnected via s switch 151 to a serial to parallel converter 153, such as an LS 164. If communication channels carry digital data such as the output of PCM apparatus, synchronization circuitry 47 (Fig. 2) is interposed before switch 151. If analog signals are carried by the communication channels, the outputs of coders 44 (Fig. 2) are connected to the terminals of switch 151. The output of converter 153 is supplied via a latch 155 such as an LS 374 to a receiver delay memory 157 comprising 8 4116 Mostek chips having a 16K byte capacity and providing a 24 millisecond delay for each of 24 communication channels. The operation of memory 157 is controlled by the output of a multiplexer 159 such as an LS 153, having two inputs. One input is the output of a 13 bit CAR counter 161, such as an LS 161 which sequences the delay memory through its cyclic read/write operations, as described hereinabove in connection with the transmit delay memory. The second input is the combined output of a sample counter 163 such as an LS 161 and channel counter 165, such as an LS 161, which together function as speed up counter 63 of Fig. 2. The function of the speed up counter is to scan rapidly the contents of the receiver delay memory 157 for each channel to detect messages which may be contained therein. Multiplexer 159 is operative to permit addressing by the speed up counter between read and write cycles controlled by the CAR counter 161. The multiplexer 159 and the read/write operation of the delay memory 157 are controlled by signals from timing circuitry 166. The sample counter 163 is incremented by an OR gate 167 which receives CLB and CLE from the timing circuitry 71 (Fig. 2) and modem receiver 61 (Fig. 2). The CLB input increments the sample counter for scanning within a given channel, while the CLE input increments the sample counter by two at the end of each channel scan. Increment logic 169 provides increment inputs to channel counter 165 and receives the RM output and the SYNC DECISION outputs from modem receiver 61 (Fig. 2). It produces a single increment pulse at the end of each channel scan when no time correction is required, two increment pulses at the end of each channel scan when a forward time correction is required, anc no increment pulses at the end of each channel scan when a reverse time correction is required. Thus it may be appreciated that timing corrections are here carried out either by skipping a channel scan or scannning a channel twice. The output of receiver delay memory 157 is supplied via a latch 171 to a receiver buffer memory 173 and via a latch. 175 and an expander 177 to modem receiver 61 (Fig. 2). The expander converts the logarithmically coded signal samples to a linear code. The input to buffer memory 173 comprises in addition to the output of latch 171, the output of a three state gate 179, which inserts a code 11011 for blanking purposes. A multiplexer 181, such as an LS 365, provides addressing to the buffer memory 173. It has three inputs, as follows: a six bit input CAR O - CAR 5 from the CAR counter 161, for memory readout; CAR 1 - CAR 5 from CAR counter 161 for memory write in in the 1: 1 operation mode; and CMR O - CMR 5 from the RX control memory and blank logic 183 (.60, 58 respectively)for selective write. The operational sequence of the buffer memory 173 is as follows: The buffer memory first sequentially reads out in the sequence of the 48 telephone communication lines in response to receipt of the output from counter 161. Since thebuffer memory contains information for only 24 of the 48 telephone communication lines, the blank logic, blank logic 183 together with gate 179 writes in a code zero for those subscribers for which buffer memory 173 contains no information, by means of a BLRX output. At the same time the contents of the receive buffer memory 173 are updated sequentially according to the 24 communication channels and randomly into the buffer memory, in response to addresses received from the CAR counter 161. The output of buffer memory 173 is supplied to latch 185 for transmission to eco ALU circuitry 55 (Fig. 2). The output of buffer memory 173 to a pair of parallel to serial converters 187 and 189 via respective latches 191 and 193. The timing of parallel to serial converters 187 and 189 is the same but the output to the converters from the buffer memory takes place in an alternating sequence. Thus the latches 191 and 193 synchronize the parallel data outputs. The serial outputs of converters 187 and 189 are supplied via switches 195 and 197 either to decoders 66 (Fig. 2) for analog telephone communication lines or via synchronization circuitry 64 (Fig. 2) to PCM apparatus. Fig. 13 is a detailed timing diagram of the circuitry described in Fig 12. The signal detection circuitry will now be described with reference to Figs.14 -16. . The operation of the signal detection circuitry may be described in summary form as the comparison of signals received from telephone communication lines with a minimum threshold plus an added variable threshold provided for echo suppression. Should the signal received from the telephone communication lines exceed this threshold, it is passed along to integration circuitry which provides a desired amount of hangover and establishes a minimum signal duration for line assignment. Reference is now made to Fig.l4which illustrates in block diagram form the signal detection circuitry constructed and operative in accordance with an embodiment of the present invention. The output of serial to parallel converter 18 is supplied to-an expander 400 which provides an 8-bit linear parallel output to a peak detector 402. The structure of the peak detector will be described hereinafter in detail. Its function is to preserve the highest peak level and it is reset every 5 ms to enable it to drop to the then current signal level. Counters 404 provide inputs to the peak detector 402 for resetting thereof. The output of peak detector 402 is supplied to comparator circuitry 53 . Comparator circuitry 53 also receives an input signal from expected echo suppression circuitry 5 and a minimum threshold control signal THmin from threshold memory and control circuitry 410. Echo suppression circuitry 55 comprises an expander 412 which receives signal inputs from the output of receiver buffer memory 52 and provides an 8 bit linear parallel output to a peak detector 414. Peak detector 414 is operative to hold a peak level until 50 ms following cessation of the signal and is also operative to ignore the first 4 ms of a received signal, in order to provide protection against noise spikes. Peak detector 414 receives control inputs from read-write control circuitry 416 which in turn receives control inputs from counter circuitry 418 which provides the timing for the 50 ms hangover and the 4 ms suppression. It is noted that the hangover and suppression times given here are those considered preferred and may be adjusted. The output of peak detector 414 is supplied to comparator 53 via viable attenuation circuits 420 and 422, typically a hybrid loss compensator and a 6db Hysteresis insertion loss circuit respectively. These circuits will be described in detail as to structure and function hereinafter. The output of comparator 53 is supplied to SPD Arithmetic Logic Unit circuitry 57. Circuitry 57 comprises ALU control and timing circuitry 424 which receives the comparator output and which supplies output signals to switches 426 and to an adder 428. A SPD-ALU memory 430 is associated with the adder 428. Circuitry 57 is operative in response to each indication of signal presence to add a predetermined amount to a memory until a predetermined threshold is reached and in response to each indication of signal absence to subtract a smaller amount from the memory. It establishes a minimum signal duration for line assignment and provides a variable amount of line assignment hangover during signal absence and displays certain hysteresis characteristics. The structure and function of circuitry 57 will be described in detail hereinafter. Reference is now made to Fig.15 which is a simplified schematic illustration of peak detector circuitry 22 and comparator circuitry 53 shown in Fig. 2 and which includes elements 400, 402, 404, 53 and 410 of Fig. 14. Expander 400 receives the output from the serial to parallel converter 18 (Fig. 2) and provides an output to a memory 430 via an inverter 432. Expander 400 comprises 4 LS 151 and 2 LS 153 multiplexers and associated control logic. Memory 430 comprises an 82S09 chip of Signetics which receives the output of expander 400 as well as a six-bit address input from timing circuitry (CA O -CA 5) which indicates which of the 48 telephone communication lines is presently connected to the memory. The output of expander 400 is also supplied to a comparator 434, typically comprising two LS 85 comparator chips. Comparator 434 also receives the output of memory 430 and thus compares the signal level currently received with the peak signal level received since the last 5 ms reset. If the current signal level is higher than that in the memory, comparator 434 provides an output signal to an AND gate 436 which provides a WRITE signal via a NOR gate 438 to the WE input of memory 430 at a time determined by a timing signal P 1 ' T 5 supplied by the timing circuitry to AND gate 436. In response to this WRITE signal the current sample level is intered into the memory1 and becomes the new peak level. If the current signal level does not exceed that in the memory, no WRITE signal is generated. Reset counters 404 comprise a LS 191 up-down counter 440 and a CA 7 timing signal from the timing circuitry having a 500 microsecond periodicity. Counter 440 is controlled by toggle switches (not shown) to provide an output every 5 msecs. The MIN output of counter 440 is connncted via an inverter 442 to the preset input of a Flip-Flop 444, typically an LS 74 chip. The Q output of Flip-Flop 444 is coupled to the LD input'of counter 440 and the Q output of Flip-Flop 444 is supplied to an input of an AND gate 446 which also receives a CA t timing signal from the timing circuitry. AND gate 446 supplies an output to the clock input of a Flip-Flop 448. The Q output of Flip-Flop 448 is supplied to its own D input and to the Clock input of Flip-Flop 444. The Q output of Flip-Flop 448 is supplied to an AND gate 450 which also receives a timing signal P 1 T 5 timing signal. The output of AND gate 450 is supplied via NOR gate 438 to the WE input of memory 430. It may be understood that output of Flip Flop 448 is provided for one sampling cycle following each 5 ms reset to AND gate 450. The P 1 T 5 timing signal sequences through the 48 telephone communications lines, such that the write signal is provided for each of the 48 telephone communications lines one time immediately following the 5 ms reset, independent of the operation of comparator 434. The output of memory 430 is supplied in parallel to two comparator circuits, 452 and 454, each comprising two LS 85 comparators. Comparator 452 compares the output of memory 430 with the output of echo circuitry 55 (RX O - RX 7) and provides an output a NAND gate 456 if if the output of memory 430 exceeds the output of circuitry 55. Comparator 454 compares the output of memory 430 with the output of threshold memory and control circuitry 410. Threshold memory and control circuitry 410 comprises an 82S09 memory 460 which stores minimum threshold values for each of the 48 telephone communication lines in response to inputs from the CPU. The address input to memory 460 receives an input from a 2: 1 multiplexer 462. This input is either the address of the telephone communication line currently being received by the peak detector 402 indicated by timing signals CA O - CA 5 or another telephone communication line address specified by the CPU, depending on the select signal provided at the select input to the multiplexer. The output of memory 460 is supplied to a latch 464 leading to comparator 454. The latch 464 is clocked by timing signals P 1 : T 5. The memory output is also supplied to a tristate latch 466 which interfaces with the CPU data bus, for readout from memory 460 to the CPU. It is to be understood here that memory 460 is under the control of the detector circuitry and is also under control of the CPU. Circuitry to be described immediately hereinafter is provided for governing the priority between the sequenced activities of the detector circuitry and the random activities of the CPU, so as not to interfere with the activities of the detector circuitry. The detector circuitry may instruct the memory to read out via latch 464 and the CPU may instruct the memory to write or to read out via latch 466. A write command from the CPU is supplied to an input of a NOR gate 468. A chip select input CS is supplied from the CPU to Nor gate 468 and a NOR gate 470. A DBIN input from the CPU, representing a read request is supplied via an inverter 472 to a second input of NOR gate 470. The outputs of NOR gates 468 and 470 are routed to the clock input of a Flip Flop 474 via an OR gate 476. The Q output of Flip-Flop 474 is supplied to an input of a NOR gate 472 zilch receives a P 1 timing signal at its second input. The output of NOR gate 478 to the data input of a Flip-Flop 480 which receives a 60 ns clock input. The Q output of Flip-Flop 480 is supplied to aninput of an AND gate 482 which also receives Åa P 1 timing input from the transmitter timing circuitry. The output of AND gate 482 provides the select signal to multiplexer 462 insuring that the multiplexer will pass the CPU-determined address to the memory 460 at all times except for a period of time preceding and including receipt of the detector circuitry READ command P 1 T 5. The Q output of Flip-Flop 480 is also supplied to the CLEAR input of Flip-Flop 474. The Q output of Flip-Flop 480 is supplied to a first input of a NAND gate 484 which also receives the output of NOR gate 468. The output of NAND gate 484 supplies a WRITE signal to memory 460 at its WE input. The Q output of Flip-Flop 480 is also supplied to an input of an AND gate 486 which also receives the output of NOR gate 470. The output of NOR gate 470 is also supplied via an inverter 488 to the output control of tristate latch 466. The clock input to latch 466 is supplied by the output of.AND gate 486. Comparator 454 provides an output to an inverter 490. The output of inverter 490 provides a signal when the signal in memory 430 is greater than or equal to the minimum threshold level indicated by the output of latch 464. The output of inverter 490 is supplied to a NAND gate 456. The output of NAND gate 456 is a COMP signal which is supplied to the ALU control and timing circuitry 424. This signal is low only when the contents of the memory 430 are equal to or greater than the minimum threshold established at comparator 454 and greater than the expected echo theshold established at comparator 452. The output of NAND gate 456 is supplied to an AND gate 492 which also receives the output of inverter 490. AND gate 492 provides an output when the contents of memory 430 are greater than the minimum threshold but do not exceed the expected echo threshold. A flip-flop 494 stores the output of AND gate 492 and is clocked by the output of an AND gate 496 which receives timing inputs t 7 and P 5. The Q output of the flip-flop 494 is supplied to the ALU control and timing circuitry 424 for indicating whether echo suppression is taking place. Circuitry for determining whether the failure to detect a signal results from echo suppression of extended duration is provided by an adder 498 whicb adds either one or zero to a memory output (not shown) in response to the presence of an echo signal at each sample. The output of the adder is supplied to a latch 500 which in turn supplies the new total to the memory. When the memory reaches a predetermined threshold an AND gate 502 which receives the memory outputs ( M 1 - M 5) provides an output signal which terminates further adding and also provides an output indication to the CPU indicating extended duration echo suppression. The latch and thereby the memory is reset to zero in response to signal detection. The input to the adder for addition is connected via an AND gate 504 which receives the ECHO signal and also receives, via an inverter 506 the output from AND gate 502. Reference is now made to Fig. 16 which is a detailed block diagram-simplified schematic illustration of the expected echo suppression circuitry 55. An 8-bit parallel signal (R O - R 7) from the buffer memory 52 is supplied to expander 412 which is identical to expander 400 and represents the level of the received signal. The output of expander 412 is supplied to the A input of a comparator 510 comprises of a pair of LS 85 chips, and to a memory 512 such as a 82S09 chip via a 2:1 multiplexer 514, such as a pair of LS 157 chips. Alternatively supplied to memory 512 via multiplexer 514 is a signal representing an average noise level less than the minimum threshold level for signal detection, which signal may be zero, and which signal is applied to the memory by the multiplexer during the reset of the peak detector. The output of memory 512 is supplied via an inverter 516 to the B input of comparator 510. Comparator 510 provides an output when the received signal level at its A input exceeds the level stored in memory 512 which represents the peak value of the currently received signal sensed so far. The output of comparator 510 is supplied to an input of an OR gate 518 and is one of the factors determining whether a WRITE signal will be generated at memory 512, for introducing a new peak value into the memory. A memory 520, such as a 82S09 chip serves as 48 individual individual counters, one for each of the 48 telephone communication channels, and in association with an adder 522 used in a subtracting mode,counts both the 4ms suppression period at the onset of signal detection and the 50 ms hangover time following the termination of signal detection. A comparator 524 receives at its A input the output from expander 412 and receives at its B input a TH min signal which determines the minimum signal threshold for detection. Comparator 524 provides an output whenever the signal level exceeds the minimum threshold. The comparator output is supplied to a control logic network 526 which is associated with the select input to a 4: 1 multiplexer 528 which selects one of four data inputs to memory 520. Prior to receipt of a signal exceeding TH min the multiplexer 528 provides zeros on the eight least significant data inputs to memory 520, which comprise the counter portion of the memory. The most significant bit (MSB) which serves as a status bit is set to one. The first time that the output of comparator 524 indicates receipt of a signal greater than TH min, following reset of memory 512, the multiplexer 528 supplies to the eight least significant data bits, hereinafter termed memory counter bits, a data input specified as by toggle switches, (not shown), which will result in a memory countdown of 4 ms. The state of the MSB is determined by a 2: 1 multiplexer 530 whose output is routed via multiplexer 528. During the 4 ms memory countdown the MSB is zero. The in: write input to memory 520 receives signals via a NAND gate 532 from the output of a flip-flop 534. NAND gate 532 also receives a timing signal which sequences at the sample rate for the telephone communication lines, this signal being provided by the receiver timing circuitry. Flip-flop 534 changes state at the end of each complete cycle of sampling 48 communication lines and as a result a write cycle is produced for each telephone communication line, every second sampling cycle. As soon as the 4 ms data input is entered into the memory by the WRITE signals to the in input, the memory 520 and associated circuitry begins operation in a countdown mode.Hereinafter and until the memory reaches zero, the multiplexer 528 supplies memory counter bits which represent the current contents of the memory minus one. The multiplexer 528 receives inputs from adder 522, operating in a subtraction mode via an inverter 536. The adder 522 receives as its inputs the eight least signficant output bits from memory 520.The MSB remains zero. During the entire 4 ms period operation of the peak detector memory 512 is disabled. When the output of memory 520 reaches zero, as detected by a conventional zero detector 538, typically comprising four logic gates , multiplexer 528 again passes on to the memory counter bits the values for a 4 ms countdown. In this case, however, the MSB is set to one rather than to zero, as specified by multiplexer 530. Hereinafter, every time that the output of comparator 524 indicates a received signal greater than TH min, multiplexer 528 supplies memory counter bits corresponding to a 50 ms countdown, as set by toggle switches, (not shown) for example. The MS8 remains at one. Alternatively, each time that the comparator 524 indicates receipt of a signal not exceeding the minimum threshold, multiplexer 528 supplies to the memory counter bits the output of adder 522, thereby causing the memory 520 to count down by one. It is appreciated that in the manner described hereinabove, the absence of a signal exceeding TH min during a period of 50 consecutive milliseconds causes the counter memory to count down to zero. At this point, the peak detector memory 512 is set to the noise level, the MSB is set to one and the memory has returned to its initial state and is ready to receive a new signal and to begin the 4 ms suppression. Until memory 520 reaches zero, WRITE signals to memory 512 are enabled and the peak detector is operational. The 50 ms countdown provides the desired hangover for peak detector operation. It is to be noted that in the event that no signal exceeding TH min is received following the 4 ms suppression then the hangover time will be 4 ms instead of 50 ms. Control logic network 526 comprises an AND gate 540 which receives the output of comparator 524 and the MSB of the counter memory 520 output and which provides an output to a NOR gate 542. NOR gate 542 also receives an input from a second AND gate 544. AND gate 544 receives an input from the output of zero detector 538 and also receives the MSB from memory 520 via an inverter 546. The output of NOR gate 542 is supplied to the SELECT 2 input of multiplexer 528 via an OR gate 548. The SELECT 1 input of multiplexer 528 is provided by the output of an OR gate 550 which receives an input from the output of zero detector 538. Both OR gates 548 and 550 receive a system SYNC signal, to initialize memory 512 to the noise level. The output of peak detector memory 512 is also supplied via inverter 516 to the inputs of a latch 552, typically an LS 175 chip. Latch 552 receives a clock input from the output of a NOR gate 554. The clock of the latch 552 is controlled by the transmitter timing circuitry which determines the inputs to NOR gate 554. This is required because the outputs of latch 552 are utilized by the SPD circuitry which operates on transmitter timing, in contrast to the echo circuitry which operates predominantly on receiver timing. For the same reason, when information is entered into latch 552 the address determined by the transmitter timing circuitry must be presented to the address lines of memory 512. At all other times the address determined by the receiver timing is presented to the address lines of memory 512. A 2: 1 multiplexer 556 comprising a pair of LS 157 chips selects between the two addresses in response to a select signal provided by the output of a NOR gate 558. In order to give priority to the transmitter timing over the receiver timing in addressing and also to delay the provision of a WRITE signal to memory 512 in the event of simultaneous requests for WRITE and READ thereto, a circuit is provided comprising a pair of flip flops 560 and 562 and an AND gate 564. The clock input to flip-flop 560 representing a write request is supplied from the output of an AND gate 566 which receives as its inputs the output of OR gate 518, the MSB of memory 520 and a receiver timing signal which occurs once per telephone communication line sample. The Q output of flip-flop 560 is supplied to an input of AND gate 564, which also receives an input from P rW , a transmitter timing signal. The output of AND gate 564 is supplied to the D input of flip-flop 562 which receives a clock input of 65 ns periodicity. The Q output of flip-flop 562 provides a WRITE signal to the WE input of memory 512. The Q output is also supplied to the CLEAR input of flip-flop 560. The Q output of flip-flop 562 is supplied to one input of NOR gate 558 which also receives the P 4 transmitter timing signal. An AND gate 568 receives as its inputs the MSB of memory 520 and the output of zero detector 538. The output of AND gate 568 controls the SELECT input of multiplexer 514, and also provides the second input to OR gate 518. The outputs of latch 552 are provided to a hybrid loss compensator 420 comprising an adder 570 formed of 2 LS 83 chips. The inputs to adder 570 are received via a pair of selectable 572 and 574 plug in jumper sets/which provide desired amounts of attenuation. This delectable attenuation factor is provided to compensate for inconsistencies in loss characteristics found in the hybrid circuits found in telephone interface circuitry. The outputs of adder 570 are supplied to hysteresis insertion loss circuitry 422 comprising a 2: 1 multiplexer 576,comprising a pair of LS 157 chips, both directly and via a divide by two connection 578. The outputs of multiplexer 576 are supplied to B inputs of comparator 452 located in the SPD circuitry. Reference is now made to Fig.17 which is a function diagram of the CPU 59. The heart of the CPU is a conventional Intel 8080 microprocessor associated with 3K bytes of program, and 1 K of RAM workspace. It is appreciated that the CPU is embodied in the preferred embodiment of the invention for purposes of design simplicity and economy and may be replaced in an alternative embodiment of the invention by conventional logic circuitry. The CPU receives interrupt inputs INT 1 - INT 3 from blank logic 58, receive modem 61 and timing circuit 69 respectively. There is also supplied to the CPU SPD data inputs CA O - CA 5 which indicate the number of the telephone communication line being received, SPD n status bit ; SPD change bit ; and ECHO bit. Timing signals P 1 and P 8 control the entry of the SPD data into the CPU. The CPU also receives a manual reset signal RESIN from the frcnt panel and 4 wait signals WTR 1 - WTR 4 from the following sources respectively: control memory 65, signalling transmitter control circuitry 714, control memory receive 60 and signalling receiver control circuitry 746. The CPU provides the following outputs 0 - DB 7 bidirectional data bus, AO - A9 address bus, CSM 5 - CSM 7 memory signals to the following elements: CSM 5 to control memory 65 control memory 60 and modem transmitter 67 CSM 6 to signalling control circuitry 714 and 746 CSM 7 to SPDthresholdmemory 410 The CPU also provides input output commands I/O 1 I/O 6 to the following elements: I/O 1 to the modem receiver 61 I/O 4 I/O 5 to blank logic 58 I/O 6 to control memories 60 and 65 ( 1: 1 command) In addition the CPU provides a control bus comprising the following control signals: WR - write DBIN Data Bus Input Pulse MEMR Memory Read Command WAIT wait acknowledge RESET reset pulse for initialization. Fig. 18 is a flowchart illustrating the message interrupt function of the CPU. Figs. 19-22 are flowcharts illustrating the monitor function of the CPU. Fig.23 is a flow-chart illustrating the 50 millisecond interrupt cycle. Fig. 24 is a flow chart of the acknowledge subroutine. Fig. 25 is an illustration in flow chart fJ^m of the system synchronization procedure. Fig. 26 is a flowchart illustrating the synchronization routine. Fig. 27 is flow chart of the main routine, summarizing operation of the TASI apparatus constructed and operative in accordance with a preferred embodiment of the present invention. At A, the system lrquires whether there is a free communication channel. if the answer is YES, the system inquires whether there are any active subscriber lines waiting for an available communication channel. If there are no waiting active subscriber lines, the system waits until there is an active subscriber line which requires assignment to a communication channel, i.e. an active subscriber line on which voice is detected. To do this, the system at B inquires whether there is any change in the SPD of the various active subscriber lines. If the SPD change is termination of speech, the system then checks if the communications channel is required by another active subscriber line. If it is not, the active subscriber line which had been connected to the communications channel remains connected thereto for the time being. If voice is again detected on that active subscriber line while it is still connected, no further assignment is required. If however the active subscriber line has in the mean time been disconnected from the communications channel, and if a communications channel is available, the assignment takes place beginning at C. If, on the other hand, no communication channel is available when voice is detected on an active subscriber line, the line is put in a queue indicated at D. This queue normally represents the lines that are frozen out. It is an additional feature of the circuitry described herein that in the event that due to long term conversations messages are not sent for a relatively long period of time, a message whose purpose is to maintain synchronization between the TASI installations on the opposite ends of the communication channels is transmitted. Reference is now made to Fig. 28 which is a detailed block diagram of the transmit control memory 65 illustrated in Fig. 2. Transmit control memory 65 receives from the CPU assignment information indicating which of the 48 telephone communication lines is to be matched with each of the 24 communication channels. This information is randomly updated by the CPU along the CPU bus. The readout of this information is done cyclically and sequentially according to the order of the 24 communication channels in real time as the assignment is taking place. The heart of the control memory is a 6810 chip 75 which contains 24 bytes, each of which contains information referring to one of the 48 telephone communication lines. Control memory chip 75 is addressed via an LS 365 multiplexer 77, which receives two alternative address inputs, CAT 1 - CAT 5 from timing circuitry 69 which sequences the control memory serially through the 24 bytes, and address inputs from the CPU address bus, which indicate CPU interaction with the control memory. Since the CPU operates asynchronously, timing and control logic circuitry 79 is provided for providing a WTR 1 signal to the CPU instructing it to wait until the CAT 1 - CAT 5 addressing is completed. In practice, eight time slots t AT - t HT are provided and during the first three of these, the control memory is engaged in its "routine operations" in response to CAT 1 - CAT 5 addressing. During the next five time slots of each sample, the control memory is free for interaction with the CPU. In response to each address indicated by CAT 1 - CAT 5, the control memory provides an 8 bit output, six bits of which are supplied to an LS 174 latch 81, which supplies them as signals CMT O - CMT 5 in response to timing signals indicating time t AT t 8T. These signals are supplied to the buffer memory 26 (Fig. 2) and to a tristate buffer 83 such as an 81 LS 244. The most significant bit is supplied to an LS 74 latch 85 and is supplied to the buffer memory and the tristate buffer 81 as a B signal and the next most significant bit is supplied to an LS 74 latch 87 and is supplied to the buffer memory and the tristate buffer 81 as an M signal. The B and M signals are used and updated in response to signals supplied to respective latches 85 and 87 by the TX Hodem 67 during the t BT time slot. During time slot t CT immediately following time slot t BT the entire 8 bits, as updated by the TX modem are fed back to the control memory via tristate buffer 83 in response to timing signal tc T received at buffer 83. Interface with the CPU is via a bidirectional tristate buffer 89, such as LS 244 chips which operate during the t DT- t HT time slots. Reference is now made to Fig. 29 which illustrates the receiver control memory 60 and blank logic 58 of Fig. 2. The principal function of the receiver (RX) control memory is to cyclically read out its contents to the receiver buffer memory. It has an additional function, that of blanking the output to the buffer memory upon detection of a message in the received signal, so as to prevent the message beeps being heard by the subscriber. The contents of the receive control memory is updated by the CPU asynchronously in response to received assignment messages. Similarly to the transmitter control memory described above, the heart of the receiver control memory is a 6810 memory chip 91 which receives a six bit address via a LS 365 multiplexer 93 which receives three alternative address inputs: CAR 1 - CAR 5 for sequencing through the addresses cyclically during normal operation; CB 1 - CB 5 for. presetting blanking counter during message receipt and the CPU address bus. Timing and control logic circuitry 95 coordinates the operation of multiplexer 93 and memory 91 and provides a WTR 3 wait signal to the CPU when the control memory is engaged in routine sequencing operations. The most significant bit of the output of control memory 91 is supplied to a BLRX latch 97, while the six least significant bits are supplied to a latch 99 which outputs its contents to the RX buffer memory address bus in response to a timing signal indicating t B-t 8, i.e. the last eight of the t By time slot. The output of the BLRX latch 97, hereinafter referred to as the BLRX signal is operative to blank the output of RX buffer memory 52 in order to prevent the message being passed on to the audio output to the telephone communication line. Upon receipt of a message by the RX Modem 61 (Fig. 2) multiplexer 93 of the control memory provides the address of the communication channel which received the message and the control memory content at that address is changed to all ones. Thus the most significant bit of the content of control memory 91, which is the input to BLRX latch 97 is 1, and BLRX becomes 1 for 25 milliseconds which is the length of'the message, thereby preventing the received message from reaching the audio output. While BLRX is high, the contents of the memory for that channel represent the remaining blanking time, and are suppliedvia latch 99 to delay counter 103. Delay counter 103 is incremented during time slot t C for every second sample to achieve the required delay. The output of delay counter 103 is supplied via a tristate buffer 105, back to control memory 91 for updating thereof. Tristate buffer /OS is enabled by an AND gate 101 which is controlled by time signal t DR and BLRX. When counter 103 reaches the end of its count, it provides an output signal to a latch 107 and to a latch 109. Latch 107 provides the address of the channel whose delay count has been completed to the CPU via a tristate buffer 111. The CPU inserts in the control memory 91 the identification of the telephone communication line which is assigned to that channel, via a bidirectional tristate buffer 113. It is appreciated that control messages including assignment information are transmitted over the communication channels serially using DPSK modulation, generated by a modem transmitter and received by a modem receiver. The modem transmitter provides digital samples of an analog waveform. Thus the message transmission may employ either analog or digital transmission facilities. Each message comprises 24 data bits, each of which comprises eight digital samples. The modem transmitter operates cyclically in a time sharing mode for the 24 communication channels. For each time slot corresponding to a comnunication channel, the modem transmitter checks the message status of the channel, computes the digital value of the message sample to be transmitted and outputs it to the transmit speech flow unit. Message transmission is synchronous and each communication channel has a predetermined time slot for commencement of message transmission. Message transmission is initiated by setting B (blank) and M (message) bits in the transmit control memory. A blank code is outputed from the modem transmitter until the designated time slot occurs. The 24 data bits of the message are then transmitted serially followed by a blanking period. Modem transmitter 67 of Fig. 2 Is illustrated in block diagram form in Fig. 3n. The heart of the modem transmitter is a message memory 502 such as two 82soy. Message memory 502 receives inputs from a CPU data bus and contains the message to be transmitted along each of the 24 communication channels following a blank bit: 13 bits of Barker code, 8 bits of message data, one bit of parity and one reference bit required for DPSK transmissions for a total of 24 bits per channel arranged in three eight bit memory locations. A second memory 504, such as an 82s09 serves to monitor all of the 24 communication channels to indicate the bit number for each channel to be transmitted and the state of transmission of the message at each channel. For each channel there is a location having 5 bits indicating which of the 24 communication channels is being transmitted and a phase bit used in DPSK coding. The output of counter 216 (Fig. 2) is supplied to a divide by 48 sample counter 506 which provides a 6 bit output, the 3 most significant bits thereof indicating which communication channel is to be transmitted. By comparing the outputs of counters 216 and 506 the required matching between each channel and its predetermined time slot is achieved for enabling transmission. The three most significant bits of the outputs of counters 216 and 506, which identify the channel are supplied to a comparator 508 which provides an output signal in response to sensed equality. The three least significant bits of the output of counter 506 are supplied to a subtractor 510. These bits represent the 8 DPSK samples of each data bit. The second input to the subtractor 510 comprises the two least significant bits of the output of counter 216 and a zero bit. It may thus be appreciated that the output of the subtractor is zero only at the beginning of the 8 sample sequence of a message bit for each channel. A transmit enable signal RBC 1 is provided by an AND gate which receives the output from comparator 508, a zero output from subtractor 510, a t 8 timing signal indicating that blanking was just completed and M and B signals from transmit control memory 65 (Fig. 2). The RBC 1 signal is supplied as reset to a bit counter 514 such as an LS 161 which also receives an increment signal from an AND gate 516 which receives the zero result signal from subtractor 510 as well as the combined timing signal t A t t 6. Bit counter 514 receives a 5 bit output from memory 504 which sequences through the memory contents channel by channel. The appearance of an RBC 1 signal at the counter during a given channel indicates the occurance of a timeslot for commencement of message transmission. The updated output of a bit counter 514 is supplied back to memory 504, Message memory 502 is addressed via a 2/1 multiplexer 518 such as an LS 365 which receives inputs from the CPU address bus and also the CA 1 - CA 5 outputs from counter 216. During the write cycle it receives the CPU address bus input and during the read cycle, the CA 1 - CA 5 outputs which indicate the channel number. In a second operation cycle, message data is read out from message memory 502. In this cycle the memory 502 is addressed by the CA 1 - CA 5 signals together with the two most significant bits of the output of the bit counter which indicate which of the three lines of data corresponding to each channel is to be read out to a latch 520 such as an LS 373. The output of latch 520 is connected to a digital multiplexer 522 such as an LS 151 which is controlled by the three least significant bits of the output of bit counter 514, thereby to select one of the 8 data bits for transmission. An exclusive OR gate 524 receives the output of digital multiplexer 522 and also receives the output of the memory 504 which indicates the phase of the previous bit. The output of exclusive OR gate is supplied to the A 3 input of a programmable read only memory (PROM) 526 which stores sixteen samples, being the eight samples which comprise each of the two DPSK phases. Memory 526 also receives the B blanking output from a flip-flop 528. A flip-flop 530 provides the M message signal which is supplied to AND gate 512 together with the B signal. The reset input of flip-flop 530 and the set input of flip-flop 528 receive the RM input indicating completion of the 24th message bit transmission. A signal RB is generated seven message bit durations afterwards to terminate the blanking. Reference is now made to Fig.31 which illustrates in block diagram form message receiver circuitry comprising a EMI53.1 delay memory610kwhich contains 240 samples for each of 24 communication channels. It is appreciated that control messages including assignment information are transmitted in TASI apparatus such as that described in EMI53.2 Israel Patent Application 57146 over the communication channels serially using DPSK modulation, generated by a modem transmitter and received by a modem receiver. The modem transmitter provides digital samples of an analog waveform. Thus the message transmission may employ either analog or digital transmission facilities. Each message comprises 24 data bits, each of which comprises eight digital samples. The modem transmitter operates cyclically in a time sharing mode for the 24 communication channels. For each time slot corresponding to a communication channel, the modem transmitter checks the message status of the channel, computes the digital value of the message sample to be transmitted and outputs it to the transmit speech flow unit. Message transmission is initiated by setting B (blank) and M (message) bits in the transmit control memory. A blank code is outputed from the modem transmitter until the designated time slot occurs. The 24 data bits of the message are then transmitted serially followed by a blanking period. In accordance with a preferred embodiment of the invention, the message format comprises: 1. one bit period - internal blank 2. one bit period - DPSK reference 3. 12 bit period - Barker code 4. one bit period - parity 5. nine bit period- message data subdivided as follows: 3 bits - message type 6 bits line number Returning now to the description of the receive delay memory10, it is noted that the contents of the memory represent the last 240 samples for each communication channel. A speed up counter612 causes the contents of delay memory to be scanned rapidly, such that each channel is scanned during 250 microseconds, i.e. 2 real time sampling intervals. Thus all 24 communication channels are scanned during a total of 48 real time sampling intervals. Since the message length of 192 samples plus the total 24 channel scanning period of 48 samples exactly equals the 240 sample capacity of the memory for each channel, scanning of the delay memory0 by the speed up counter612 enables detection of the entire message irrespective of the timing relationship between the receiver timing and the incoming messages. A samples counter614 counts 240 samples for each channel. The samples counter includes a channel number section output which is incremented by one, to the next channel, each 240 samples, and also includes a sample counter section which is incremented by two, since each channel scan period is the length of two real time sampling intervals. It is a particular feature of the modem receiver circuitry described in Fig. 31 that it enables the receiver circuitry to operate with communication channels having different propagation times. Receive delay memory 610 stores the samples in logarithmic form in accordance with the companding @ law. The samples are cor.verted to a linear code by an expander616 and the eight most s"cnificaflt bits of the linear output of the expanderC16 are supplied to a 1 message bit delay circuitGl8, typically comprising a memory which dlas the eight DPSK samples forming each message bit by one messsage bit. The output of delay circuit618 is supplied to a multiplier 620 which multiplies the value of each sample by the value of each delayed sample. The output xn of multiplier 620 is supplied to a digital low pass filter 622. Digital low pass filter622 comprises an adder624, which outputs to an accumulatorS26, whose output is supplied directly and also via an inverterZ28 to a second adder630. The output of adder 630 is supplied as a second input to adder 624. Filter 622 is of first order with a 3dB frequency of 2 KHz. It executes the following function: yn +1 = yn + · ( xn - Yn) where Yn is the output of filter 22 for the n'th sample. The yn output of filter622 at the output of accumulator 626 is supplied to a magnitude comparator632 which compares it with a predetermined threshold. The output of the magnitude comparator32 is supplied via an AND gate 634 which receives the sign bit of If the magnitude of Yn is less than the predetermined threshold, then the output of AND gate 634, hereinafter termed So, is zero.The SO output is supplied to a memory 636. Memory 636 stores the last 96 samples of SO and provides outputs S1 - S12. The tie relationship between outputs So - S12 is such that there is an interval of 8 sampling intervals between adjacent outputs Sn and Sn-1. Since each message bit comprises 8 samples, the outputs S1 -S12 are each samples of a corresponding message bit. The outputs S1 - S12 are supplied to a 12-bit Barker code detector 638 . In the preferred embodiment the Barker code is selected to be EMI56.1 When the Barker code is detected for three consecutive sampling intervals, a nine-bit counter40 is enabled. Counter 640 counts 9 bit periods, which are equivalent to 72 samples. When counter640 completes its count, outputs So - 59 comprise nine message bits and a parity bit. A parity check circuit 642 receives outputs S0 - S9 from the memory 636 and determines if parity is present. If parity is present, circuitry 642 rovides an output to an AND gate which also receives the output from counterS40. The output of AND gate 644, referred to hereinafter as RM is supplied as a CPU interrupt signal to indicate receipt of a message and is also supplied to a message register 646, causing register 646 to store outputs S0 - S8 of the output of memory 636. Message register64 also interfaces with the CPU data bus of TASI tvDe apparatus as described hereinabove. Reference is now made to Fig. 32 which illustrates in block diagram form apparatus for treatment of out of band signalling in accordance with the embodiment of the invention here described. The apparatus shown here and in Fig. 33 is combined with the apparatus of Fig. 2 when out of band signalling is involved. Where in band signalling is used, the apparatus described here may be omitted. A transmission signalling input interface 698, which may be the same for example as the interface circuitry described above in connection with Fig. 12 provides 48 parallel signalling inputs, each corresponding to a telephone communication line to a 48 to 1 multiplexer 700 which may comprise 7 93L12 chips. The multiplexer is controlled by a 48 counter 702, which may comprise 2 LS-163 chips and which also controls a signalling control memory 704 such as a 6810 which governs the operation of an addressable latch 706, which may comprise 3 LS259 chips, operating as a 1 to 24 demultiplexer. Thus during a given time slot, one of 48, multiplexer 700 couples a predetermined one of the 48 telephone communication line signalling wire to the signalling wire of a communication channel determined by the control memory 704. A delay memory 708, typically 3 N-5058 static shift registers, is interposed between the output of multiplexer 700 and the input of addressable latch 706 in order to provide a delay (typically 64 milliseconds) which is sufficient to enable signalling detection circuitry 710 to determine whether signalling information is present and if so to effect assignment of a signalling wire corresponding to a communication channel to be assigned to the signalling wire carrying signalling information. The output of multiplexer 700 is supplied to signalling detection circuitry 710, also referred to as signalling detector ALU circuitry, at the input of control logic circuitry 712, comprising Tm gates. The control logic receives timing signals from timing and control circuitry 714 and also receives an STD n-l input which indicates the previous status of the given telephone communication line switching wire. The output of control logic circuitry 712 is supplied to the negative input of a subtractor 716, typically 3 LS 83 chips and which provides an output to a signal detection charging memory 718 which together with a S.D.T. memory 720 comprises 2 6810 chips. The output of memory 718 is supplied to the positive input of subtractor 716. The S.D.T. memory receives an input from logic circuitry 712 which indicates whether the current sample contains signalling information, based on the criteria established by the control logic circuitry. It may be appreciated that the signalling detection circuitry 710 provides integration of the input samples so as to establish a minimum threshold for duration and also to provide hangover time after termination in order to prevent loss of signalling information. The control memory 704 operates in two modes in response to timing signals from circuitry 714. As described above, it outputs to addressable latch 706 in response to inputs from counter 702 supplied via a multiplexer 722, which is also controlled by circuitry 714. When it is not outputing to addressable latch 706, the control memory 704 is available for being updated by the CPU via a CPU data bus and a bidirectional tristate buffer 724, which receives the SDT n-l signal from memory 720 and control signals from circuitry 714 and from the CPU. When the control memory 704 is being updated by the CPU, multiplexer 722 passes addresses from the CPU address bus to the control memory. The output of addressable latch 706 is supplied along 24 parallel signalling wires corresponding to 24 communication channels via a transmit signalling output interface 726, which may be similar to that illustrated in Fig. 9 hereinabove or any other suitable interface circuitry. It is noted that the control memory operates cyclically in outputing to the addressable latch and is approached by the CPU in an asynchronous manner. When the CPU addresses the control memory when it is engaged in outputing to the addressable latch, timing circuitry 714 provides a WTR 2 wait signal to the CPU until the cyclic operation is completed. When there Is a change in assignment of signalling the CPU searches for a communication channel having both signal and data portions free. Upon finding an available communication channel, the CPU transmits over the data carrying channel, as opposed to the signalling wire, assignment information regarding the new assignment. Reference is now made to Fig 33which illustrates In block diagram form apparatus for treatment of out of band signalling at the receive end, as opposed to the transmit end described hereinabove. The circuitry shown here is similar in many respects to that of the transmit end described above but differs therefrom in that it does not contain a delay memory which is not required since the receive signalling circuitry merely monitors proper operation of the signalling wires and does not provide new assignments. An RX signalling input interface 730 and an RX signalling output interface 732 each receive timing signals from timing circuitry 71 (Fig. 2) and may be similar in construction to the interface circuitry illustrated in Fig. 9 hereinabove. Interface 730 interconnects signalling wires corresponding to 24 communication channels to a multiplexer 734, typically 4 93L12 chips. The output of multiplexer 734 is supplied directly to an addressable latch 736, such as 6 LS 259 chips, which outputs along 48 parallel lines via interface 732 to signalling wires corresponding to the 48 telephone communication lines. The output of multiplexer 734 is also supplied to control logic circuitry comprising TTL gates 738 which together with an adder 740 , a signal detector charging memory 742 and a SDR memory 744 comprises signalling detection circuitry. Adder 740 receives an input from control logic circuitry 738 and provides an output to memory 742 and a SDR n signal to memory 744. Memory 742 provides an output to a second input of adder 740 and SDR memory 744 provides an SDR n-l signal to circuitry 738. Circuitry 738 and SDR memory 744 both receive signals from timing and control circuitry 746 which receives timing signals from circuitry 71 (Fig. 2). A counter 748 provides a six bit output to latch 736, memories 742 and 744 and to a signalling control memory 750, the latter via a multiplexer 752. Control memory in turn provides a five bit output which operates multiplexer 734 for matching the received signalling information to the signalling wire indicated by the control memory 750. Both control memory 750 and multiplexer 752 receive timing inputs from circuitry 746 and operate in two modes, one in which the cyclic addressing of counter 748 provides cyclic, synchronized operation of latch 736 and multiplexer 734 and the second, which occurs when the cyclic operation is not taking place, in which the CPU interacts with the control memoryivia the CPU data bus and a bidirecitonal tristate buffer 754 for updating thereof in an asynchronous manner. 754 Bidirectional tristate buffer/receives a five bit output from control memory 750 and the SDR n-l output from memory 744 , as well as control signals from the CPU and circuitry 746 and provides a six bit output to the CPU, which instructs the CPU to send an acknowledge signal in response to the received signalling information. This acknowledge signal is sent over a data channel. When the CPU 7so attempts to interact with the control memory/during cyclic operation thereof, control circuitry 746 provides a WTR 4 wait signal to the CPU. In summary it may be understood that the receive signalling circuitry described hereinabove provides the necessary matching between incoming signalling information and the appropriate signalling wires and also senses the presence of signalling information in order to provide an acknowledge signal indicating receipt thereof. The present invention also provides a concentrator which conveniently interfaces between the 2-wire subscriber connection and the 6-wire multiplex link and which, by use of Time Assignment Speech Interpolation techniques, enables twice the number of subscribers to be connected over a given number of multiplex link channels as would otherwise be possible using conventional concentrators inserted on the 2-wire connections. The concentrator benefits from significant economies in that it employs common control circuitry and power supplies for operating the concentrator matrix as well as the TASI circuitry. The concentrator. provides a particular advantage in rural applications where the alternatives thereto are installation of additional multiplex links or even additional central offices. There is thus provided in accordance with an embodiment of the present invention a concentrator comprising a first switching matrix coupled to a central office, 2-wire - 4-wire interface circuitry1 coupled to the first matrix, time assignment speech interpolation apparatus having subscriber terminals coupled to the interface circuitry and communication channel terminals couplable to a multiplex telephone link, and control circuitry governing the operation of the first switching matrix and of the time assignment speech interpolation apparatus. Normally, on the subscriber end of the multiplex link a similar concentrator unit to the above is employed, the only difference being that the switching matrix is coupled to the individual subscriber lines rather than to the central office. Reference is now made to Fig.34 which is a block diagram illustration of a remote switching link comprising a concentrator constructed and operative in accordance with an embodiment of the present invention. A central office±10, such as for examPle an Albis model A-50, provides a desired number of 2-wire subscriber lines. For the purposes of illustrationl92 lines are illustrated herein, it being understood that any suitable number of lines may be provided, depending gio on subscriber demand. The 192 lines from the central officekare connected to 192 corresponding 2-wire CO terminals of a concentrator 812, which is the subject of the present application. Concentrator glg is provided with 24 communication channel terminals which are coupled to a standard conventional multiplex transmission link!/+ which extends from the central office to a remote location. At the remote location the multiplex transmission link (24 channels) is coupled to communication channel terminals of a concentratorS/t which is paired with concentrator21 and identical thereto except for interfaces. Concentrator 816 is provided with 192 subscriber line terminals which are coupled to 192 2-wire subscriber lines. The concentrator units Fl2 and ±/6 are described in greater detail with reference to Fig.35, which is common to units 812 and 816. The 192 lines from a C.O. or from subscribers, depending on whether the unit described is unit 812 or 816 respectively are coupled to 820 a 2-wire switching matrixusing for example Clare relays 851A-48-B2A or alternatively any other suitable relays, or crossbar or any other type of electromechanical switching. As a further alternative, purely electronic switching may be employed. Switching matrix 820 is provided with 48 2-wire line terminals which are connected to corresponding terminals of a 2-wire/6-wire interface card 23. Interface card 822 differs for units 812 and 816 and will be described hereinafter in detail with reference to Figs 36 and 37. The 48 6-wire terminals of interface card ±22 are connected to the subscriber inputs of a TASI unit multiplexer g2f having 24 communication channel terminals which are connected va a 6-wire channel interface card ±26 to multiplex 8/4 (Fig. 34). TASI multiplexer 824 and matrix !2care controlled by control circuitry TASI multiplexer 824, interface card iS: and control circuitry ±z8 are preferably embodied in TASI apparatus described hereinabove. It is appreciated that the ratio of subscriber lines to communication channels in the apparatus described hereinabove is based on a concentration ratio of 4: 1. That is to say that matrix 21 is operative to connect a number of subscriber lines to one-fourth that number of communications channels based on the statistical fact that the subscribers served use their telephones less than one fourth of the time. The ratio of subscriber lines to communication channels- i.e. the concentration ratio may vary-depending on the type of subscribers in the general range of 4:1 up to 10:1. Reference is now made to Fig.36 which illustrates in block diagram form interface circuitry coupling a 2-wire line to a 6-wire channel, such as at the subscriber terminal of TASI multiplex apparatus. Legs 1 and 2 of a 2-wire subscriber line are coupled either to a 110 VAC 17 HZ source, ready to receive a ringing impulse, when the telephone is not in use, or when the telephone is in use, they are coupled across the primary of a hybrid transformer T 1. A relay B having contacts b 1 and b 2 governs the connection status of the 2-wire subscriber line. A relay A is connected across the primary of transformer T 1 and converts dialing pulses generated by the telephone over the 2-wire subscriber line to on-off pulses for transmission. The secondary windings of transformer T 1 are coupled to respective transmit and receive-wire pairs which may be connected to a multiplex or to subscriber terminals of TASI apparatus as aforesaid. The remainder of the circuitry of Fig.36 will be described hereinafter in connection with a functional description thereof. Referring now to Fig. 37 there is seen in block diagram form interface circuitry which couples a 6-wire channel such as at the output of TASI apparatus as aforesaid with a 2-wire line as at a C.O. terminal. Transmit and receiver wire pairs from a 6-wire channel are coupled across secondary coils of a transformer T 2, whose primary is coupled via a relay C te the two wire line. A relay D and a capacitor C 1 coupled in parallel thereto are inserted along one leg of the 2-wire line connected to the primary. The remainder of the circuitry will now be described in the overall functional description which follows: hEEN A SUBSCRIBER WISHES TO RECEIVE A LINE When a subscriber wishes to receive z line he lifts the receiver causing activation of relay A. Relay contact a 1 energises a circuit C I at input L. Circuit C I provides a pulse at output U of 100 msec. This pulse is transmitted along the M wire via TASI apparatus or any other transmission link to the E wire'on the C.O. side (Fig.37). The appearance of the 100 msec pulse on the E wire causes energization of relay C which, by virtue of the action of contact c 1 remains closed notwithstanding disappearance of the pulse on the E wire. Contacts c 2 and c3 on the 2-wire line are thus closed, connecting the primary loop of transformer T 2 to the C.O. and causing the C.O. to provide a dial tone. The dial tone provided by the C.O. is transmitted via transformers T 2 and T 1 to the subscriber as an audio signal. DIALING Dialing by the subscriber causes relay A to respond to the pulses generated by the telephone. The dialing pulses pass via circuit CI but do not pass via circuit C II, since that circuit only passes pulses of duration at least 150 msec. Thus the dialing pulses are supplied to the M wire from terminal U of circuit C 1. These pulses are received on the E wire at the C.O. side (Fig.37) at a time when relay C is already closed. As a result these pulses cause energization of relay D. Contact d 1, by opening and closing in accordance with the dialing pulses received on the E wire, such that the C.O. alternatively senses the loop resistance of the primary of transformer T 2 with and without the capacitor C 1 in series. This causes the selectors in the C.O. to make connection in accordance with the received dialing pulses, establishing audio contact between the dialing and the dialed subscribers. TERMINATION OF THE CONVERSATION When the subscriber hangs up, relay A (Fig.36) is deenergized, causing contact a 2 to couple circuit C II to ground at terminal G. Once 150 msecs. have passed circuit C II couples terminal N to ground, so long as contact b 3 is open. Thus the M wire is coupled to ground, resulting in energization of the Z relay. As a result contacts z 1 and z 2 disconnect the ringing current from the subscriber line. Grounding of the M wire causes grounding of the E wire on the C.O. side. A circuit C III is responsive to grounding of the E wire for at least 150 msec to ground its terminal F. This results in energization of an E relay, causing contact e 1 to de-energize relay C. As a result contacts c 2 and c 3 are opened disconnecting the C.O. from transformer T 2. The grounding of the M wire at the CO side, as a result of the grounding of terminal F causes grounding of the E wire at the subscriber side (Fig.36). This results in energization of the B relay, causing contact b 3 to close, thereby terminating the grounding of terminal N of circuit C II. This terminates the grounding of the M wire at the subscriber side. The removal of this grounding is communicated to the C.O. side to the E wire on the C.O. side removing the grounding thereof and as a result circuit C III terminates the grounding at terminal F causing E relay to be de-energized. The M wire at the C.O. side is no longer coupled the ground. causing the E wire on the subscriber side to be decoupled from ground. The energization of the B relay causes de-energization of the Z relay. The decoupling of the E wire on the subscriber side from ground causes de-energrzation of the B relay. At this point the relays and other-circuitry are prepared for commencement of a new conversation by the action of a subscriber in lifting the receivr. WHEN A SUBSCRIBER RECEIVES RINGING FROM THE CENTRAL OFFICE At the central office (C.O.) side there appears on the 2-wire line a ringing current. This current is received by a circuit C IV which converts the ringing current to ground pulses. The ground pulses appear at a terminal P and are supplied to the M wire at the C.O. side and thus appear on the E wire at the subscriber side. The appearance of these pulses on the E wire causes energization of the B relay in accordance with the ringing pulses. Contacts b 1 and b 2 are thus operative to periodically connect the 2-wire subscriber line to the ringing current to produce ringing. Once the subscriber lifts the receiver, the sequence described hereinabove for initiation of a conversation takes place. It will be appreciated that the circuitry of Figs.96 and37 is not necessarily limited in its application to use with TASI apparatus bit may be employed for 2-wire/6-wire or 2-wire/ 4-wire conversion in any telephone system. It is noted that the circuitry provided is designed for a 6-wire conversion. A 4-wire conversion, for in-band signalling can also be achieved using similar, simpler circuitry. It will be appreciated that there may be applications where a separate switching matrix is not required, because of the relatively low number of subscriber lines required. In such a case, the TASI apparatus is provided with interface cards equal to the number of subscriber lines and the switching is done internally on the same principles by circuitry on the interface cards controlled by the CPU of the TASI apparatus. The invention is not limited to what has been particularly shown and described hereinabove and in the drawings. Rather the scope of the invention is defined only by the claims which follow:

Claims: C L A I M S 1. In a time assignment speech interpolation communication system for interconnecting a transmission trunk link having a first plurality of communication channels to a second plurality of telephone communication lines, the second plurality exceeding the first plurality, each of said second plurality of telephone communication lines comprising separate voice transmission means and signalling transmission means and each of the first plurality of communication channels comprising separate trunk voice transmission means and trunk signalling transmission means, apparatus for carrying out time assignment interpolation of signalling information carried on said signalling transmission means comprising: first signalling detection means coupled to said signalling transmission means; and first switching means operated by said signalling detection means for selectively connecting signalling transmission means carrying signalling information to available trunk signalling transmission means. second switching means coupled to said trunk signalling; and transmission means for coupling said trunk signalling transmission means carryinq signalling information to available signallinq transmission means at a remote location in accordance with received assignment information. 2. Apparatus according to claim 1 and also comprising means for providing assignment information indicating activity of said first switching means to said second switching means. 3. Apparatus according to claim 2 and wherein said means for providing assignment information comprises transmission apparatus located at a first end of said transmission trunk link and operative for transmitting assignment information over said first plurality of communication channels. 4. Apparatus according to claim 3 and wherein said transmission apparatus is operative for trinsmitting assignment information trunk signalling transmission means. one 5. Apparatus according to any/of the preceding claims and also comprising second signalling detection means coupled to said trunk signalling transmission means for providing an output indication of receipt of signalling information at said second switching means. one 6. Apparatus according to any/of the preceding claims and also comprising delay means coupled to said signalling transmission means and operative to delay signalling information carried thereon until said second switching means is operative to complete a connection therefor.

Inventors: HENQUIN, TEODOR, PIASECKI, JOSHUA, SEGEV, AHARON, ZELINKOVSKY, REUVEN
Applicants: E C I TELECOM LTD.
Application year: 1979
Main classification: H04J3
IPC codes: H04Q11, H04J3