CONTROL CIRCUIT FOR REFRESHING A DYNAMIC MEMORY

Abstract: A circuit which efficiently controls the refresh operation of a dynamic memory. The refresh control circuit operates such that a dynamic memory (28) coupled to a processing means responds to a memory access signal (BMREQ) for a read/write operation and a first refresh control signal (BMREF) for a memory refresh operation. First circuits (30, 32) provide a second periodic refresh control signal (REFREQ), and second circuits (34, 40) refresh the memory under the control of either of the first (BMREF) or second (REFREQ) refresh control signals. A third circuit (20) responsive to the memory access signal (BMREQ) and the second refresh control signal (REFREQ) awards priority of access to the memory (28) in accordance with the first active signal which it receives. A fourth circuit (20) puts the processing means in a hold condition when priority is awarded to the second refresh control signal (REFREQ). In a power down condition a (BRST) signal enables gates (42) having a battery back up to permit the dynamic memory to be refreshed.

Description: C0NTR0L CIRCUIT FOR REFRESHING A DYNAMIC MEMORY Technical Field The present invention relates to a circuit for controlling the refresh operation of a dynamic mem- ory. Background Art Dynamic memories which are semiconductor de¬ vices having charge-storing elements for storing data are presently employed in data processing systems and have advantages as compared with static memories of higher speed of access, lower power dissipation and higher den¬ sity. However, dynamic memories have the disadvantage of relatively fast charge leakage therefrom, requiring that the charge therein be refreshed at frequent inter- vals in order to ensure that data is not lost. This brings the concomitant problem of ensuring that refresh¬ ing operations do not interfere with memory read or write operations. Different techniques are known for dealing with this problem. For example, U. S. Patent No. 3,858,184 discloses a system in which refresh operations are permitted to take place in a selected part of the machine cycle, or in selected machine cycles, in which memory access operations are not taking place. With such a technique, known as transparent refresh, the re¬ fresh operations are synchronized with the memory opera¬ tions. However, this system has the disadvantage that problems can arise when the central processor is in a hold condition for any reason, since in such conditions refresh may not occur. Another technique of refresh control is dis¬ closed in U. S. Patent No. 3,760,379. In this technique refresh signals are generated periodically independently of the central processor. The controller provides a system of priority in the event of a refresh signal and a memory access request occurring at the same time. This is known as asynchronous access and has the capability to cater for a variety of operating conditions. However, the system discussed in U. S. Patent No. 3,760,379 has the disadvantage of overall slower speed of memory ac¬ cess, since memory access may be prevented when a refresh operation is taking place. Disclosure of the Invention It is an object of the invention to provide a circuit for controlling the refresh operation of a dy¬ namic memory in which the above-mentioned disadvantages of known systems are alleviated. The present invention provides a circuit for controlling the refresh operation of a dynamic memory, said memory being coupled to a processing means which generates a memory access signal for a read or write operation, and a first refresh control signal for re¬ freshing the memory, characterized in that said circuit comprises first circuit means for generating a second, periodic, refresh control signal, second circuit means adapted to refresh said dynamic memory under the control of said first and second refresh control signals, third circuit means responsive to said memory access signal and said second refresh control signal to award priority of access to the memory in accordance with which active sig¬ nal it receives first; and fourth circuit means for dis¬ abling said processing means from accessing the memory when priority is awarded to said second refresh control signal and enabling said processing means to access the memory at the completion of the refresh operation. Since in accordance with the invention, said second circuit means operates to refresh the dynamic memory in response to the- first refresh control signal generated by the processing means, ' the memory can be refreshed in a transparent mode of operation which does not interfere with memory access operations of the OMP processing means. In conditions where said first refresh control signal is unavailable, said second refresh con¬ trol signal acts to refresh the memory and in this mode of refresh operation said third circuit means provides a system of priority between the memory access signal and the second refresh control signal. In a preferred arrangement, there are provided gate means with a battery back up responsive to a power down condition and to a memory access signal and said first and second refresh control signals in order to enable a memory access or refresh operation; the gate means provides enabling signals to permit memory refresh or memory access in a power down condition. Brief Description- of the Drawings An embodiment of the invention will now be described in more detail with reference to the accom¬ panying drawings, in which: Figs. 1A and 1B taken together constitute Fig. 1 and define a block diagram of a preferred embodiment of the memory refresh control circuit according to the invention; Fig. 2 is a detailed schematic diagram of the logic circuit for controlling whether a memory request or a memory refresh operation is to occur; Fig. 3 is a detailed schematic diagram of the logic circuits for providing a transparent refresh clock which enables the row address strobe signals to perform a refresh operation; Fig. 4 is a detailed schematic diagram of the logic circuitry for controlling -the contention refresh operation where a memory request signal and a memory re¬ fresh signal overlap. Fig. 5 is a detailed schematic diagram of the logic circuitry for generating the refresh cycle; Fig. 6 is a detailed schematic diagram of the logic circuitry for generating row address strobes during a power up or power down condition of the memory system; Fig. 7 is a timing diagram of the control signals for accessing the memory during a memory access operation; and Fig. 8 is a timing diagram of the control signals generated during a refresh operation. Best Mode For Carrying Out the Invention The preferred memory refresh control circuit of the invention is shown in Fig. 1 which includes a dynamic RAM (DRAM) control circuit 20 (Fig. 1A) coupled to a common bus over whose lines are transmitted from a central processing unit (CPU) well-known control signals for accessing a semiconductor memory such as a MOS dynamic random access memory. Included in these signals are a bus memory request BMREQ which signals the memory system that the processor is trying to access the memory, a bus read signal BRD, a bus write signal BWR, a system clock BCLK, a bus reset BRST and a signal BRDY generated in the control circuits 20 for transmission over the bus to the CPU putting the CPU into a wait mode. The DRAM control circuits 20 generate the appropri¬ ate control signals for transmission to the row address strobe RAS driver 24 and the column address strobe CAS driver 26, each of which outputs the appropriate strobe signal to a 16K RAM memory 28 (Fig. 1B) enabling the memory to be accessed. An example of such a memory that is commercially available is the M0STEK MK411GP- 2/3 RAM memory manufactured by the Mostek Corporation of Carrollton, Texas. Further included in the control system is a CMOS timer circuit 30 (Fig. 1A) which outputs control signals after a predetermined time period to a CMOS refresh circuit 32 to initiate a refresh operation of the RAM memory 28. In the present embodiment, the timer circuit 30 will output the necessary control O P • signals to the refresh circuit 32 every 27 microseconds. The refresh circuit 32 in response to receiving the control signals will generate the refresh clock CREFCLK used in initiating a refresh operation. The operation of the timer circuit 30 is asynchronous with the operation of the memory system. Associated with the refresh circuit 32 is an address counter driver 34 (Fig. 1A) which, when enabled by operation of the refresh circuit 32, will output 128 counts for use in the addressing of the column structure in the RAM memory 28 (Fig. 1B). The RAM memory 28 is a 128x128 cell matrix, the operation of which requires strobe signals to occur in both 128 rows and columns in a manner that is well known in the art. The output of the address counter drivers 34 is transmitted over bus 36 to a multiplex address driver 38 which also receives the address bits BA0-BA13 of the data to be accessed over the common bus 22 from the CPU. The selection of the address that is to be transmitted from the multiplexer 38 to the RAM memory 28 is controlled by a transparent refresh circuit 40 which determines the priority between a refresh operation and a memory request operation when they occur simul¬ taneously. Other circuits in the memory system of Fig. 1 include memory select circuits 42 (Fig. 1A) for genera¬ ting the row address strobes RAS during either a memory request operation or a memory refresh operation, data bus drivers and receivers 44 (Fig. 1B) for outputting data over the common bus 22 to the CPU as the result of a read operation and for receiving data to be written into the RAM memory 28 as a result of a write operation, a static RAM matrix memory SRAM 46 (Fig. 1B) which is nonvolatile in its construction for storing data which is to be retained by the system, a battery-supported charging system 48 (Fig. 1B) for supporting the operation of the SRAM matrix memory 46 and a battery supported power down voltage driver 50 (Fig. 1B) for outputting a OMPI , plurality of voltage signals to the memory select circuit 42, the voltage signals supporting a refresh operation or an access operation of the memory system when the RAM memory 28 is involved in a power down condition wherein all power is lost to the memory system. Referring now to Fig. 2, there is shown a schematic diagram of a memory interface circuit which controls the type of operation that is to be initiated in the memory system, which may include a memory request operation or a memory refresh operation. This circuit is located in the DRAM control circuit 20 (Fig. 1A) and the transparent refresh circuit 40 (Fig. 1A). Included in the circuits are a pair of D-type flip-flops 52 and 54 which may be part no. LS74 manufactured by Texas Instruments, Inc. Hereinafter, certain of the logical elements disclosed in the circuits described will be identified by their part numbers, which are manufactured by a number of companies, such as Texas Instruments, Inc. , for example. If the designation refers to a manufacturer other than Texas Instruments, Inc., the manufacturer of the part will be identified. The signals are illustrated in the accompanying drawings in their active state. Also included in the circuit of Fig. 2 are a pair of SN54LS109 J-K flip-flops 56 and 58. Coupled to the clock input of the flip-flop 52 through an inverter 60 is the bus memory request signal BMREQ transmitted from the CPU over the common bus line 22 notifying the memory system of a memory access operation. The D input, of flip-flop 52 is coupled over line 61 to the refresh circuit 32 (Fig. 1A) over which is transmitted the bus memory refresh signal REFREQ (Fig. 5) which is active low when a refresh operation is requested as a result of the operation of the timer circuit 30. If at this time the signal BMREQ is low, indicating a memory request operation, the clocking of the flip-flop 52 by the signal BMREQ going from low to high will result in O P IF a high signal ' appearing at the J input of flip-flop 56 and subsequently the Q output signal row address strobe clear RASCR of flip-flop 58 will go high, thereby becoming active. The signal RASCR is also transmitted over line 62 through an inverter 64 to produce the active low signal RASCR which is transmitted over line 66 to one input of AND gate 68 (Fig. 2), thereby disabling the AND gate 68 from clearing the flip-flop 52 until the signal RASCR goes high. This latter condition occurs when the signal BMREQ goes high at the end of a memory access operation. The signal BMREQ going high also resets the flip-flop 56 and 58 due to the high signal appearing on the output of the NOR gate 70, which signal is transmitted over line 72 to the clear inputs of the flip-flops 56 and 58. The NOR gate 70 receives the BMREQ signal and a power on reset signal BRST which becomes active high at the start of a power on condition as will be described more fully hereinafter. The flip-flops 54-58 inclusive (Fig. 2) are clocked by the bus clock BCLK transmitted through the inverter 74 resulting in the inverted signal being transmitted over line 76 to the flip-flops. As shown in Fig. 7, the clock signal BCLK synchronizes the operation of the flip-flops 52-58 inclusive with the generation of the bus signals BMREQ, BWR and BRD used in accessing the RAM memory 28 (Fig. 1B) for a read or write operation in a manner that is well-known in the art. Setting of the flip-flop 56 as the result of - the clocking of flip-flop 52 results in the presence of a high signal at the Q output which signal is transmitted over line 78 to the AND gate 80 whose other input is coupled over line 82 to the NAND gate 84 which outputs a high signal when either the bus read signal BRD or the bus write signal BWR is active low indicating the type of access that is being requested by the CPU. Assuming for purposes of illustration that the CPU is requesting a write and access operation, the active low signal BWR enables the AND gate 80 to output a high signal to the D input of the J-K flip-flop 54 whose Q output will go high and its Q ~ output will go low. The Q output signal is transmitted over line 86 to the CAS-WRITE drivers 26 (Fig. 1A) which circuits include the NAND gate 88 (Fig. 2) whose output signal memory column address strobe MCAS is transmitted over line 92 to the RAM memory 28 (Fig. 1B). As is well- known in the art, the signal MCAS is used for clocking into the column section of the RAM memory 28 the address bits BA0-BA13 transmitted from the multiplexer address drivers 38 (Fig. 1A) over bus 36 for accessing the memory. The RAM memory 28 is enabled by the cycle clock signal CYCLK (Fig. 2) which appears on the Q output of flip-flop 52 and which is active low when the flip-flop 52 is set at the start of a memory request operation. The bus write signal BWR is also transmitted over the bus line 22 to an inverter 94 (Fig. 2) whose high output signal is transmitted over line 96 to one input of the NAND gate 90. The other input of both NAND gates 88 and 90 (Fig. 2) will have present thereon the high inactive CMOS refresh signal CREF1 (Fig. 5), allowing the NAND gate 90 to output the active low memory write signal MWR over line 98 to the RAM memory 28 (Fig. 1B) enabling a write operation to occur. Other signals being transmitted to the RAM memory 28 include the column address enable signal CAENA which appears on the output of the AND gate 80 (Fig. 2) and which controls the switching of the address bits BA0- BA13 from the row portion of the RAM memory to the column portion of the memory in a manner that is well- known in the art. The setting of the flip-flop 54 (Fig. 2) produces on its 0? output an internal column address strobe TCAS used in addressing the RAM memory 28. If the bus write signal BWR is active, the data bus driver and receiver circuit 44 (Fig. 1B) will OMP input the data bits BD0-BD7 inclusive into the RAM memory 28 and the SRAM matrix memory 46 if required, the data bits being transmitted over bus 100 (Fig. 1B). Likewise, if a read operation is to occur, the bus read signal BRD will be active low, thereby setting the flip-flop 54 in the manner described above and enables the NAND gate 88 to output the active low signal MCAS. The data bits BD0-BD7 will be outputted from the RAM memory 28 and the matrix memory 46 over bus 102 (Fig. 1B) through the driver circuits 44 and over the common bus 22 to the CPU under the control of a data bus enable signal D BUS ENA generated in the control circuits 28 (Fig. 1A). If at the time the signal BMREQ (Fig. 2) goes low, the refresh request signal REFREQ. appearing on line 61 is low, the flip-flop 52 will remain in a reset condition allowing a refresh operation to occur. At the end of the refresh operation, a cycle preset signal CYPR (Fig. 4) is generated in a manner to be described hereinafter which presets the flip-flop 52. If the signal BMREQ is low at this time indicating that a memory request operation is still to occur, the flip- flop 52 will be set, thereby initiating a memory request operation in the manner described above. Referring now to Fig. 3, there is shown the circuitry for performing a transparent refresh operation of the RAM memory 28 (Fig. 1B) in response to the generation of a system refresh signal BMREF (Fig. 1A) by the CPU. Included in the circuit is a SN54LS109 J- flip-flop 102 which is located in the transparent refresh circuit 40 (Fig. 1A) and a two-to-one data selector 104 which may be a SN54LS157 multiplexer available from Texas Instruments, Inc. The data selector 104 is located in the multiplexer address drivers 38 (Fig. 1A). Also included in the circuit is a SN54LS393 address counter 106 and a SN54LS196 address driver 108 located in the address counter driver circuit 34 (Fig. OMPI _ 1A). The system will output an active low bus memory refresh signal BMREF every four-five microseconds during a normal access operation. The active low signal BMREF is transmitted through an inverter 110 (Fig. 3) to one input of an AND gate 112 (Fig. 3) whose other input includes the signal RASCR generated from the Q output of flip-flop 58 (Fig. 2) and the signal TCAS which is the Q output of flip-flop 86 (Fig. 2). Upon the signal BMREF going low, the AND gate 112 is conditioned to output a high signal upon both the signals RASCR and TCAS going high. This latter condition occurs at the end of a memory request operation, thereby allowing the refresh operation to occur at the end of the memory request operation. It will be appreciated that this allows the refresh operation to be transparent to the system. The outputting of a high signal from the AND gate 112 will set the J-K flip-flop 102 producing at its Q output a high signal which becomes the active low transparent refresh clock signal TREFCLK after being inverted by the inverter 114. The flip-flop 102 is clocked by the clock signal CCLK which appears on the output of the inverter 74 (Fig. 2). Also inputted into the clear input of the flip-flop 102 is the cycle clear signal CYCR which is generated on the output of the NOR gate 70 (Fig. 2) and which becomes active low when a system reset signal BRST becomes active high. The transparent refresh clock signal TREFCLK is transmitted to one input of the NAND gate 116 (Fig. 3) whose other input signal CREF (Fig. 5) is active low at this time, thereby resulting in the NAND gate 116 outputting a high signal which enables the address counter 106 to output counts 0-127 to the address driver 108 which in turn outputs the counts over bus line 36 and the memory address lines MA0-MA7 for refresh¬ ing 128 rows in the RAM memory 28 in a manner that is well-known in the art. O During the memory request operation, the signals RASCR, CREF and CAENA (Fig. 2) will be active low, thereby enabling the data selector 104 to output over the memory address lines MA0-MA6 the address bits BAO¬ BAB appearing on the bus line 22 to the RAM memory 28. Upon the completion of the memory request operation, the data selector 104 is disabled by the above signals as described previously. The active low signals RASCR and CAENA will enable the AND gate 118 (Fig. 3) to output a low signal which disables the operation of the address driver 108. Both the data selector 104 and the address driver 108 are tri-state devices which will float when disabled. Referring now to Fig. 4, there is shown circuitry for disabling the CPU during a contention re¬ fresh operation when both a memory request signal and a contention refresh signal generated as a result of the operation of the timer circuit 30 (Fig. 1A) occur simul¬ taneously. When this condition occurs, the refresh operation is given priority. Included in this circuit are four LS74 D-type flip-flops 120-126. Upon the timer circuit 30 (Fig. 1A) outputting the refresh request signal REFREQ (Fig. 5) in a manner that will be described more fully hereinafter, a refresh operation occurs which requires that the CPU be put into a wait mode until the coexisting memory request operation is carried out. When the CPU is transmitting a memory request instruction, the bus memory request signal BMREQ (Fig. 4) will be high, which signal is transmitted over line 128 from the output of the inverter 60 (Fig. 2) to one input of the AND gate -130. The other input of the AND gate 130 is coupled to the Q output of the flip-flop 120 which becomes high at the time of completing the previous refresh cycle by the presence of the pull- up signal PUP being high. These signals enable the AND gate.130 to output a high signal to the D input of the flip-flop 122 thereby setting the flip-flop on the rising edge of the next clock signal CCLK (Fig. 2). The setting of the flip-flop 122 will output the preset signal CYPR which is transmitted to the flip-flop 52 (Fig. 2) presetting the flip-flop. If at this time the bus memory request signal BMREQ (Fig. 2) is still active low indicating that.a memory request is still pending, the presetting of the flip-flop 52 will initiate a memory request cycle in the manner described previously. As will be described more fully hereinafter, the signal REFREQD (Figs. 4 and 5) is generated 50 nanoseconds after the generation of the signal REFREQ. The active low signal REFREQD (Fig. 4) is transmitted over line 132 to the D input of flip-flop 124 setting the flip-flop thereby producing a low signal on its Q~ output, which signal is transmitted over line 134 to the NAND gate 136 whose, output signal BRDY will become active high. This signal is transmitted over the bus line 22 to the CPU indicating that the RAM memory 28 (Fig. 1B) is ready for access. This condition addresses a problem generated when the memory request signal is raised after a refresh cycle has been initiated or where both cycles are generated simultaneously and priority has been given to the refresh cycle. Since the CPU has no way of knowing that such a condition is in existence, the CPU must be put into a wait mode until the memory refresh cycle is completed. To put the CPU into a wait mode, the signal BRDY must go low. This is accomplished when the refresh signal REFREQ (Fig. 4) becomes active low (Fig. 8), which signal is transmitted over line 138 to the inverter 140. The inverter 140 will output a high signal over line 142 to the clock input of the flip-flop 126 setting the flip-flop which results in the Q output of the flip-flop going high because of the high signal PUP being present at the D input of the flip-flop. The Q output signal of the flip-flop 126 is applied to one input of the AND gate 144 whose other input receives OMPI the memory request signal BMREQ which becomes high when a memory request signal is generated by the CPU. When this condition occurs, the AND gate 144 will output the low signal BRDY (Fig. 8) over line 146 and the bus 22. At the end of the refresh cycle, the signal REFREQ will go high which raises the signal BRDY allowing the CPU to complete the memory request cycle. Referring now to Fig. 5, there is shown details of the timer circuit 30 and the refresh circuit 32 (Fig. 1A) which provides the control signals for carrying out a contention refresh operation. Included in the circuit is a MC14520 binary counter 148 manufactured by Motorola, Inc. of Phoenix, Arizona, which is operated by a 502 kilocycle clock generator located in an oscillator (not shown) located in the timer circuit 30 (Fig. 1A). When enabled, the counter 148 will output a binary count for a period of 27 microseconds, the count appearing on the outputs of Q Q -Q O inclusive. At the end of the 27 microsecond period, the output signals appearing on the outputs Q^ and Q will be high, which signals when applied to the AND gate 150 will enable the AND gate to output a high signal to the J input of a MC4.027 J-K flip-flop 152 setting the flip-flop. The Q output signal of flip-flop 152 will go high upon the setting of the flip- flop which signal is transmitted over line 154 to the J input of a second MC4027 J- flip-flop 156, thereby setting the flip-flop 156. Both flip-flops 152 and 156 are manufactured by Motorola, Inc. The setting of- the flip-flop 152 at the end of the 27 microsecond time period initiates a refresh cycle request in a manner that will now be described. The high Q output signal of flip-flop 152 is transmitted over line 158 to the inverter 160 whose active low refresh request signal REFREQ is transmitted over line 61 to the D input of flip-flop 52 (Fig. 2) disabling the flip-flop from initiating a memory request cycle in the manner described previously. The REFREQ signal is also clocked into the flip-flop 120 (Fig. 4) thereby conditioning the ΑND gate 130 to control the generation of the cycle preset signal CYPR for presetting the flip-flop 52 at the end of the refresh cycle if there is present an active low memory request signal BMREQ as described previously. The output signal REFREQ of the inverter 160 (Fig. 5) is also transmitted to an amplifier 162 whose delayed output signal REFREQD sets the flip-flop 124 (Fig. 4) resulting in the signal BRDY appearing on the Q " output going high, notifying the CPU that the RAM memory 28 (Fig. 1B) is available for access at this time. The Q output signal of flip-flop 152 is also transmitted to one input of an AND gate 164 whose output contention refresh signal CREFI will become active low when the binary pulses appearing on the Q 2 output of the counter 140 becomes high. The active low signal CREFI is transmitted over line 166 (Fig. 5) through the amplifier 168 to produce a delayed active low contention refresh signal CREF, which signal is transmitted to one input of the NAND gate 105 (Fig. 3) enabling the gate to output a high signal, this condition occurring during a memory request operation. It will be appreciated that the output signal of the NAND gate 105 (Fig. 3) controls whether the address bits trans¬ mitted over the bus 36 will comprise the output of the address counter 106 (Fig. 3) which is required during a refresh cycle or the address bits BA0-BA13 appearing on the bus 22 and which is required for a memory request cycle. When the gate 105 (Fig. 3) outputs a high signal, the data selector 104 is disabled from trans¬ mitting the address bits BA0-BA13 over the input lines MA0-MA6 of bus 36 to the RAM memory 28 (Fig. 1B) thereby enabling a refresh operation to occur in the manner de¬ scribed previously. The contention refresh signal CREFI (Fig. 5) is transmitted to .NAND gate 116 (Fig. 3) enabling the gate to output a high enabling pulse if either of the input signals CREFI or TREFCLK is active low. The active high output pulse of gate 116 enables the address counter 106 to output the 128 counts from the bus counter 106 which are used in refreshing the RAM memory 28 (Fig. 1A) in a manner that is well-known in the art. The contention refresh signal CREFI is further transmitted over line 166 to one input of NAND gates 88 and 90 (Fig. 2) disabling the NAND gates 88 and 90 thereby preventing the occurrence of a memory write cycle during a refresh cycle. The signal CREFI is also trans¬ mitted over line 166 through an inverter 170 (Fig. 5) whose output signal will clock the flip-flop 156. The setting of the flip-flop 156 will produce at its Q output a high signal which is transmitted through a NAND gate 172 by the 502 kilocycle clock resulting in the output signal contention refresh clock CREFCLK being transmitted through an amplifier 174 to the memory select circuits 42 (Fig. 1 and 6) for selecting certain circuits for a refresh operation as will be described hereinafter. The setting of the flip-flop 156 (Fig. 5) will also produce at its Q " output the active low contention refresh enable strobe signal CRAENA, which signal is coupled to the AND gate 118 (Fig. 3) thereby enabling the gate to output a high signal to the address driver 108 enabling the driver to output the counts transmitted from the address counter 106 over bus 36 during a refresh operation in the manner described previously. The 502 kilocycle clock pulse signal appearing on the input line 176 (Fig. 5) of the counter 148 is also transmitted over line 178 to one input of the AND gate 180 whose other input is connected to the Q 1 output of the counter 148. During the 27 microsecond output count, the AND gate 180 will output a high signal to one input of an AND gate 182 whose other inputs are connected to the Q 2 and Q output of counter OMPI 148. At the end of a refresh cycle which occurs from four nanoseconds after the 27 microsecond time period has elapsed, the AND gate 182 will be enabled by the high signals Q« and Q, to output a high- signal to an inverter 184 whose active low output refresh end signal REFEND is transmitted to a NAND gate 186 (Fig. 5) enabling the gate to output a high signal. The high output signal of NAND gate 186 will reset the counter 148 and the flip-flop 152, thereby allowing the counter to start another 27 microsecond counting period. The other input signal TREFCLK appearing at the AND- gate 186 will become active low during a transparent refresh cycle, thereby resetting the timer 148. It will thus be seen that during a ,normal request operation by the CPU, the timer 148 will be reset during a transparent refresh operation. The resetting of the flip-flop 152 (Fig. 5) will also produce on its Q " output a high signal which is transmitted to a NAND gate 188 (Fig. 5) enabling the gate to output an active low refresh clear signal REFCR which signal will reset the flip-flop 120 (Fig. 4). The timing out of the counter 1.48 will also enable an AND gate 190 (Fig. 5) to output a high signal for resetting the flip-flop 156. Referring now to Fig. 6, there is shown the circuitry located in the memory select circuit 42 (Fig. 1 ) which provides the memory row address strobes MRAS0-MRAS2 inclusive for a number of banks in the RAM memory 28 (Fig. 1A). .The RAM memory 28 comprises three 16K memory banks, each of which is strobed by one of the MRASO-2 signals (Fig. 6). Included in the circuit is a logic array of OR gates 192, a first set of NAND gates 194 and a second set of NAND gates 196. Each of the OR gates 192 has one input coupled to one of a number of select lines CS0-CS2 inclusive coming from a decoder (not shown) located in the memory select circuit 42 (Fig. 1A). Whenever one of the select lines CS0-CS2 O inclusive becomes active low during a memory request cycle, the signal will be transmitted through its corresponding OR gates 192 upon the occurrence of a cycle clock pulse CYCLK (Fig. 2), the selected OR gates 192 outputting a low signal to its corresponding NAND gate 194 whose other input contains a transparent refresh clock signal TREFCLK (Fig. 3) and contention refresh clock signal CREFCLK (Fig. 5), both of which at this time are high. With these signals present, the NAND gate 194 will output a high signal to an associated NAND gate 196 whose other input is high at this time. The selected NAND gate 196 will output the active low memory row address strobe MRASO for its associated bank in the RAM memory 28 enabling an access to occur in that bank of the memory 28. When a refresh operation occurs, entry of the refresh clocks TREFCLK and CREFCLK will be active low enabling each of the NAND gates 194 to output a high signal, which coupled with the low output signal from the OR gate 192 will output active low MRAS0-MRAS2 inclusive signals enabling the refreshing of the rows of the RAM memory 28 to occur simultaneously during a transparent or contention refresh operation. Since the reset signal BRST will be active low during a power up or a power down condition, the NAND gates 196 will be enabled by the active low BRST signal via gate 200 to output the MRAS0-MRAS2 signals until a refresh cycle is completed. This condition is accomplished since each of the gates 192-196 inclusive are coupled over line 202 to the power down driver 50 (Fig. 1B) and thereby battery-supported enabling the gates to continue operation until the refresh cycle is completed. This condition is necessary in order not to shorten the MRAS signals which could occur if a power failure occurred during the generation of the signals. Shortening of the MRAS signals could conceivably result in the loss of data stored in the RAM memory 28. OMPI

Claims: CLAIMS : 1. A circuit for controlling the refresh opera¬ tion of a dynamic memory (28), said memory being coupled to a processing means which generates a memory access signal (BMREQ) for a read or write operation, and a first refresh control signal (BMREF) for refreshing the memory, charac¬ terized in that said circuit comprises: first circuit means (148, 152) for generating a second, periodic, refresh control signal (REFREQ); second circuit means (104-108, 192-196) adapted to refresh said dynamic memory (28) under the control of said first (BMREF) and second (REFREQ) re¬ fresh control signals; third circuit means (52) responsive to said memory access signal (BMREQ) and said second re¬ fresh control signal (REFREQ) to award priority of access to the memory (28) in accordance with the first active sig- nal which it receives; and fourth circuit means (126, 144) for disabling said processing means from accessing the memory (28) when priority is awarded to said second refresh control signal (REFREQ) and enabling said processing means to access the memory (28) at the completion of the refresh operation. 2. A circuit according to claim 1, character¬ ized in that said fourth circuit means (126, 144) is re¬ sponsive to said memory access signal (BMREQ) and said second refresh control signal (REFREQ) for said disabling of said processing means. 3. A circuit according to claim 2, character¬ ized in that said third circuit means includes a first bi¬ stable means (52), said bistable means being coupled to said first circuit means (148, 152) and said processing means for receiving said memory access signal (BMREQ) and said refresh control signal (REFREQ), said bistable means (52) being arranged to be switched to a first state when an active memory access signal (BMREQ) is received before OM W WIIPP 3. ( concluded ) an active second refresh control signal (REFREQ) whereby to prevent enabling a refresh operation occurring until a mem¬ ory access operation is completed. 4. A circuit according to claim 3, character¬ ized in that said first bistable means (52) is arranged to be switched to a second state when an active second re¬ fresh control signal (REFREQ) is received before an active memory access signal (BMREQ) whereby said second circuit means (104-108, 192-196) is enabled to refresh the memory (28); and said fourth circuit means (126, 144) includes a second bistable means (120, 122) coupled to said first circuit means (148, 152)- and said processing means for re- ceiving said memory access signal (BMREQ) and said refresh control signal (REFREQ), said second bistable means (120, 122) being arranged to be swit.ched to a first state by an active second refresh control signal (REFREQ) to output a control signal (CYPR) to said first bistable means (52) thereby to switch said first bistable means (52) to said first state at the conclusion of the refresh operation to initiate a memory access operation of the memory (28). 5. A circuit according to claim 4, character¬ ized in that said fourth circuit means (124, 144) further includes gate means (144) coupled to receive said memory access signal (BMREQ) and coupled to a third bistable means (126) being arranged to receive said memory refresh signal (REFREQ) to switch said third. bistable means to a first state, said gate means (144) being adapted to gener¬ ate a second control signal (BRDY) disabling the proces¬ sing means from accessing the memory (28) when said third bistable means (126) is switched to said first state. 6. A circuit according to claim 3, character¬ ized in that said first bistable means is a D flip-flop whereby, in the event of a simultaneous active memory OMPI 6. ( concluded ) access (BMREQ) and refresh control (REFREQ) signals, pri- ority is awarded to said refresh control signal (REFREQ). 7. A circuit according to claim 1, character¬ ized by logic means (112, 102) coupled to the processing means and said third circuit means (82), said logic means (112, 102) being arranged to be enabled by said first re- fresh control signal (BMREF) and by signals (RASCR, TCAS) which are generated by said third circuit means (52) and which become active at the completion of a memory access operation to output a first clock signal (TREFCLK) to said second circuit means (104-108, 192-196) enabling said second circuit means to refresh said memory (28) at the completion of a memory access operation. 8. A circuit according to claim 7, character¬ ized by a battery-powered power supply (48), and further characterized in that said second circuit means includes first gating means (194, 196) coupled by coupling means- (202, 50) to said power supply, said gating means (194, 196) being further coupled to said logic means (112, 102, Fig. 3) and said first circuit means (148, 152, Fig. 5) and being arranged to be enabled by either of said first clock signal (TREFCLK) or said second refresh control signal (REFREQ, CREFCLCK) to output enabling signals (MRAS0-2) to the memory (28) for refreshing the memory. 9. A circuit according to claim 6, character¬ ized in that said processing means generates a reset sig¬ nal (BRST) in response to a loss of power in said memory, said second circuit means (104-108, 192-196) further in- eluding second gating means (200) coupled to receive said reset signal (BRST) and coupled to each of said first gating means (196), said second gating means (200) being enabled by the reset signal (BRST) to output a second control sig¬ nal to said first gating means (196) enabling the battery- supported first gating means to output said enabling sig- 9. ( concluded) nals (MRAS0-2) to the memory (28) for refreshing the memory (28) after a loss of power in the memory has occurred. OMPI

Inventors: PATEL N
Applicants: NCR CO, NCR CORP
Application year: 1979
Main classification: G11C7
IPC codes: G06F13, G11C11