CYCLIC DIGITAL-TO-ANALOG CONVERSION SYSTEM

Abstract: This invention relates to digital-to-analog conversion, for the conversion of digital signals into corresponding analog signals. It is particularly applicable to high resolution digital-to-analog conversion. In a particular form of the invention, a cascaded series of individual voltage dividers (20-23; 38-41; and 56-60) is used to divide a voltage reference signal with successively finer resolution. Voltage follower amplifiers (33, 36, 51, 54) are used between the individual divider stages to substantially eliminate any loading effects upon the outputs of the individual divider stages. The connection pattern is such that only one connection within one divider stage will be switched for a transition between two adjacent digital signals, and two adjacent analog signals levels. The result is a useful resolution which will normally correspond to the number of divider stages, even though the component accuracy and matching, and the absolute conversion accuracy, may not be that precise. The invention is also applicable to analog-to-digital measurement or conversion via the adjustment of a digital signal so that a generated analog signal corresponds to an analog signal which is to be measured.

Description: CYCLIC DIGITAL-TO-ANALOG CONVERSION SYSTEM BACKGROUND OF THE INVENTION When a digital computer is connected to a physical system for purposes such as measurement and/or automatic control, it is often desirable to provide analog outputs from the computer (variable in small steps over a given range) in addition to the usual digital outputs (e.g., simple on/off signals). For example, one may wish to draw graphs with an analog chart plotter, or provide analog signals which will be used to control valves, motors, visual indicators, or for other purposes. A common way of doing this is to employ one or more digital-to-analog converters which generate analog voltages corresponding to digital data words transmitted from the computer. Digital-to-analog converters are also used as signal sources in test instruments, as components in analog-to-digital converters, and for many other purposes. In a common form of binary parallel digital-to-analog converter, a parallel resistor network is driven by a number of voltage or current switches, with each switch being controlled by one bit of a binary number to be converted. The resistor network is adjusted so that the relative weight given to the output of each voltage or current switch, except the most significant bit switch, is one-half the weight given to the output of the switch corresponding to the next more significant bit. The network output is then an analog signal corresponding to the input binary number. The analog output of a digital-to-analog converter should have a monotonic and approximately uniform interval relationship to the digital input signal. That is, whenever the digital input signal changes by one increment in a particular direction, the analog output signal should change by approximately one increment in a corresponding direction. In an actual converter, this may not be the case. Using an eight-bit binary converter as an example, a possible pτoblem in a conventional parallel digital-to-analog converter is that the voltage developed by the converter in response to, for example, a binary digital input of 1000 0000 (128 in decimal) may not be substantially one increment larger than the voltage developed for a binary digital input of 0111 1111 (127 in decimal). If the effective weighting values of the resistor network and/or the inaccuracies of the voltage or current switches are such that the effective weight given to the most significant bit is slightly low, the voltage generated for the conversion of 1000 0000 may actually be less than the voltage generated for the conversion of 0111 1111. Adjustments are usually provided to set the weights given to some number of the most significant bits to overcome this problem. Unfortunately, resistor networks tend to drift with variations in temperature and with time, and the characteristics of semiconductor voltage or current switches may also drift, so that readjustment may be required from time to time. At the present time, 15 or 16 bits is about the practical limit for parallel resistor network type digital- to-analog converters. In general, a conventional parallel type digital-to-analog converter can provide a high resolution only by providing a ' correspondingly high absolute accuracy. Simply extending the number of bits in a parallel type converter by adding additional circuits is generally of no utility, as the value of the analog output signal will have no particularly significant relationship to the values of the less significant bits of the input digital number, except perhaps over limited segments of the full converter range. As an example, the resolution and accuracy situation in regard to conventional parallel type digital-to-analog converters is similar to the use of a balance and a set of weights of 16 ounces, 8 ounces, 4 ounces, 2 ounces and 1 ounce for weighing. Measuring a change of weight from 15 ounces to 16 ounces requires going from using the combination of the 8, 4, 2 and 1 ounce weights to using the 16 ounce weight. The accuracy of the 16 ounce weight must generally be better than the desired resolution. In contrast, a simple spring type scale may have an absolute error of several ounces when weighing an object of approximately 16 ounces. However, it is still capable of indicating a change of, say, one ounce and thus providing a usable resolution which is significantly finer than its absolute accuracy. Conventional parallel digital-to-analog converters are, in general, not capable of providing useful resolutions finer than their absolute accuracies. In some applications, it may be desirable to provide digital-to-analog conversions with a high resolution, but not necessarily with a correspondingly high accuracy. For example, a digital-to-analog converter may be used as an element in a closed loop control system. In such systems, there will typically be an oscillation or noise component with a magnitude corresponding to a few steps of the digital number signals. To reduce the magnitude of this system noise, it is necessary to perform the digital-to-analog conversion with a finer resolution. In some instances, it may be desirable to maintain a low system noise without necessarily providing a correspondingly high overall accuracy for the digital-to-analog conversion. In such instances, a digital-to-analog converter providing a high resolution, but not necessarily a correspondingly high accuracy, may be useful. An analog-to-digital converter can be constructed using a digital-to-analog converter and appropriate comparison and feedback control circuits. Hence, the subject invention is also related to analog-to-digital conversion. Such analog-to-digital converters are sometimes referred to as comparison type analog-to-digital converters. Their accuracy and resolution of analog-to-digital conversion will correspond to the accuracy and resolution of the digital-to-analog conversion. In conventional comparison type analog-to-digital converters, as in conventional digital-to-analog converters, the accuracy and resolution are normally quite closely tied together. That is, in order to provide a high resolution it is also necessary to provide a correspondingly high accuracy. In some applications, it may be desirable to provide digital measurements of analog signals with a high resolution, but not necessarily a correspondingly high absolute accuracy. For example, suppose one wishes to measure the temperature of a chemical reaction vessel. It may be desirable to measure a rate of change of temperature by measuring changes of (say) a few hundredths of a degree over a short period of time, while it is not necessary to measure the temperature itself with a similar accuracy. In such applications, the ability to measure small differences or changes with a high resolution, but without necessarily a correspondingly high absolute accuracy, can be useful. It is sometimes desirable to convert analog voice, music or other signals into digital form for transmission and/or recording. The signals may then be converted back into analog form after transmission and/or recording. An advantage of digital transmission and/or recording is that digital signals can be transmitted and/or recorded with complete accuracy so that there is no distortion introduced by the transmission and/or recording process. Digital transmission may also be used as a means of transmitting a number of individual analog signal streams over a single path via multiplexing techniques. In such instances, it may be desirable to be able to process signals with a wide dynamic range, that is, both loud and soft signals, without necessarily processing the loud signals with an accuracy corresponding to the amplitude of the soft signals. In such instances, digital-to-analog conversions and analog-to-digital conversions with high resolution, but not necessarily with a correspondingly high, absolute accuracy, may be useful. BU O SUMMARY OF THE INVENTION The subject invention is conceptually related to voltage dividers such as the Kelvin-Varley voltage divider. In a particular form of the invention, a series of individual voltage divider stages is used to divide a voltage reference signal with successively finer resolution. Voltage follower amplifiers are used between successive stages to substantially eliminate any loading effects upon the outputs of individual divider stages. The switching sequence is related to a cyclic or Gray digital code, in that only one connection within one divider stage is normally changed for a transition between two adjacent digital signals, and two adjacent analog signal levels. The result is that there will be no large discontinuous changes of the analog output signal between any two adjacent digital values, thereby providing a high effective resolution. As with conventional digital-to-analog converters, the overall conversion accuracy is a function of the accuracies of the individual divider resistors and other circuit components. However, the useful resolution of a digital-to-analog converter, or a comparison type analog-to-digital converter, constructed in accordance with the subject invention can provide high resolution conversions without the difficulty and expense which might be incurred if a correspondingly high overall conversion accuracy were also required. An object of the subject invention is to provide a novel means of digital-to-analog conversion for the conversion of digital signals into corresponding analog signals. A further object is to provide high resolution digital-to- analog conversions. A further object is to provide high resolution analog-to- digital conversions. Additional objects and advantages may be seen by reference to the drawings and to the following specification. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagrammatic illustration of a first form of the invention showing a three-stage series resistor string voltage divider circuit for the digital-to-analog conversion of a six-bit binary number signal into an analog voltage signal, in which each circuit stage is associated generally with a group of two bits of the binary number; Figure 2 is a diagrammatic illustration of a read-only memory for the conversion of a six-bit binary number signal from a normal binary code into a fourteen-bit code, which may be used in connection with the system of Figure 1; and Figure 3 is a diagrammatic illustration of a second form of the invention showing a two-stage circuit for the digital-to-analog conversion of a six-bit binary number signal into an analog voltage signal, in which each stage is associated generally with a group of three bits of the binary number and illustrating the use of individual ladder network digital-to-analog converters in both stages. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 is a diagrammatic illustration of a first form of the invention showing a three-stage series resistor string voltage divider circuit for the digital-to-analog conversion of a six-bit binary number signal into an analog voltage signal, in which each circuit stage is associated generally with a group of two bits of the binary number. In Figure 1, digital data register 11 is connected via data path 12 to switch control 13, which is connected via link 14 to switches 27, 28, 29, 30, 31, 45, 46, 47, 48, 49, 65, 66, 67 and 68. A first side of voltage reference 15 is connected to line 16, and a second side is connected via line 17 to ground 18 and line 19. The series combination of resistors 20, 21, 22 and 23 is connected from line 16 to line 19. The junction of resistors 20 and 21 is connected to line 24. Similarly, the junction of resistors 21 and 22 is connected to line 25, and the junction of resistors 22 and 23 is connected to line 26. Lines 16, 24, 25, 26 and 19 are connected to inputs of switches 27, 28, 29, 30 and 31, respectively. The outputs of switches 28 and 30 are connected via line 32 to the input of voltage follower amplifier 33, whose output is connected to line 34. The outputs of switches 27, 29 and 31 are connected via line 35 to the input of voltage follower amplifier 36, whose output is connected to line 37. The series combination of resistors 38, 39, 40 and 41 is connected from line 34 to line 37. The junction of resistors 38 and 39 is connected to line 42. Similarly, the junction of resistors 39 and 40 is connected to line 43, and the junction of resistors 40 and 41 is connected to line 44. Lines 34, 42, 43, 44 and 37 are connected to inputs of switches 45, 46, 47, 48 and 49, respectively. The outputs of switches 46 and 48 are connected via line 50 to the input of voltage follower amplifier 51, whose output is connected to line 52. The outputs of switches 45, 47 and 49 are connected via line 53 to the input of voltage follower amplifier 54, whose output is connected to line 55. The series combination of resistors 56, 57, 58, 59 and 60 is connected from line 52 to line 55. The junction of resistors 56 and 57 is connected to line 61. Similarly, the junction of resistors 57 and 58 is connected to line 62, the junction of resistors 58 and 59 is connected to line 63, and the junction of resistors 59 and 60 is connected to line 64. Lines 61, 62, 63 and 64 are connected to inputs of switches 65, 66, 67 and 68, respectively. The outputs of switches 65, 66, 67 and 68 are connected via line 69 to the input of voltage follower amplifier 70, whose output is connected to terminal 71. Digital data register 11 is a source of a six-bit binary number signal which is to be converted into an analog voltage signal on terminal 71. Switch control 13 controls the states of switches 27 through 31, 45 through 49, and 65 through 68, in accordance with the digital value in digital data register 11. The logical functions of switch control 13 may be implemented via a read-only memory, a network of logical gates, a combination thereof, or such other means as may be desired. The operation of switch control 13 will be described subsequently in greater detail. Switches 27 through 31, 45 through 49, and 65 through 68 are single pole, single position switches. They may be semiconductor switches, such as field effect transistor switches, electro-mechanical relay switches, manually operated switches, or other type switches that may be appropriate for the application. In normal operation, two adjacent switches of the group of switches 27 through 31 will be on or closed, and the remaining three switches will be off or open. Similarly, in normal operation, two adjacent switches of the group of switches 45 through 49 will be closed, and the remaining switches of that group will be open. One of the switches of the group of switches 65 through 68 will normally be closed, and the remaining three switches of that group will be open. Voltage reference 15 is a source of a reference voltage signal which will normally be of a substantially constant value. In the subsequent description of the operation of the system of Figure 1, it will be assumed that the output of voltage reference 15 on line 16, relative to line 17 and ground 18, is +6.4 volts. Resistors 20, 21, 22 and 23 are a matched set of resistors whose resistance values are substantially equal and which will tend to vary in a similar manner with changes in temperature. The individual resistance values will typically be in the range of from a few hundred ohms to perhaps 100,000 ohms. Individual resistance values of the order of 1,000 ohms would be suitable for the 6.4 volt reference value, which will be assumed in the subsequent description. The set of resistors 38, 39, 40 and 41 is a similar matched set with substantially equal individual resistance values. Individual resistance values of the order of a few hundred to a few thousand ohms may be used for resistors 38 through 41 in the specific example being given. The set of resistors 56, 57, 58 and 60 is a matched set of resistors in which the individual resistance values of resistors 57, 58 and 59 are substantially equal. The individual resistance values of resistors 56 and 60 are substantially equal to half of the individual resistance values of resistors 57, 58 and 59. Individual resistance values of the order of a few hundred to a few thousand ohms may be used for resistors 56 through 60 in the specific embodiment being described. Amplifiers 33, 36, 51, 54 and 70 are voltage follower amplifiers of substantially unity gain and provide output signals which are substantially equal to their input signals. The analog voltage output signal of the system of Figure 1 appears on terminal 71. An analog load may be connected to the circuit of Figure 1 by connecting it between output terminal 71 and ground 18. In operation, the system of Figure 1 will provide analog voltage output signals on terminal 71 over a range of .05 volts through 6.35 volts, in steps of 0.1 volt, for digital signals in digital data register 11 from zero through 63 in steps of 1. In analyzing the operation of the system of Figure 1, it will be assumed that the output of voltage reference 15 on line 16 relative to line 17 and ground 18 is +6.4 volts, that the resistor sets 20-23, 38-41 and 56-60 are accurately matched, and that voltage follower amplifiers 33, 36, 51, 54 and 70 are of substantially unity gain and without significant input currents or voltage offsets. The states of switches 27 through 31, 45 through 49, and 65 through 68 are controlled by switch control 13 in accordance with a 14-bit binary control word which is a predetermined function of a six-bit binary data word within digital data register 11. For a digital signal of zero within digital data register 11 (binary 000 000), switches 30, 31, 48, 49 and 68 will be closed, and the other switches will be open. The line 19 voltage is zero. Since switch 31 is closed, the line 35 and line 37 signals will also be zero. Resistor set 20-23 functions as a voltage divider so that the line 26 signal if one-quarter of the 6.4 volt reference signal on line 16, or 1.6 volts. Since switch 30 is closed, the line 32 and line 34 signals will also be 1.6 volts. The voltage across lines 34 and 37 is divided by resistor set 38-41 so that the line 44 signal is 0.4 volts. Switch 49 is closed so that the line 53 and line 55 signals are zero volts. Switch 48 is closed so that the line 50 and line 52 signals are 0.4 volts. With the previously stated resistance values for the set of resistors 56-60, the voltage across resistor 56 will be .05 volts, the voltages across each of resistors 57, 58 and 59 will be 0.1 volts, and the voltage across resistor 60 will be .05 volts. Hence, the line 64 signal will be .05 volts. Since switch 68 is closed, the line 69 and terminal 71 signals will also be .05 volts. Hence, for a digital signal of zero in digital data register 11 (binary 000 000) , the analog voltage output signal on terminal 71 relative to ground 18 will be .05 volts. Table 1 further illustrates the operation of the system of Figure 1. Table 1 lists the 64 digital signal values from zero through 63 which may be contained within digital data register 11, a cyclic base 4 representation corresponding to the digital signal values, the switches within each of dividers 1, 2 and 3 which are closed for each digital signal value, and selected circuit voltages for each digital signal value, including the terminal 71 analog output voltage. Divider stage 1 includes resistors 20 through 23 and switches 27 through 31. Divider stage 2 includes resistors 38 through 41, and switches 45 through 49. Divider stage 3 includes resistors 56 through 60 and switches 65 through 68. For example, . , for a digital signal value of 12, Table 8 indicates that switches 30, 31, 45, 46 and 65 will be on or closed. Switches 27, 28, 29, 47, 48, 49, 66, 67 and 68 will be off or open. The selected circuit voltages given in Table 1 are the voltages on lines 34, 42, 43, 44, 37, 61, 62, 63 and 64, and terminal 71, all relative to ground 18. As may be seen from Table 1, the terminal 71 output voltage varies from 0.05 volts through 6.35 volts in steps of 0.1 volt, for digital signal values of zero through 63 in steps of 1. The pattern of the switch settings is related to the cyclic base 4 code. The state of the switches of stage 1, switches 27 through 31, corresponds to the value of the left digit of the cyclic base 4 code. Similarly, the state of the switches of divider stage 2, switches 45 through 49, corresponds to the value of the middle digit of the OM Switches Closed Circuit Voltages Digital Cyclic Signal Base 4 divider divider divider line line line line line line line line line 1 2 3 34 42 43 44 37 61 62 63 64 0 000 30-31 48-49 68 1.6 1.2 0.8 0.4 0.0 0.35 0.25 0.15 0.05 1 001 II II 67 " II II II II It II II It 2 002 II II 66 II II II II II II II II II 3 003 II II 65 II II II II II It II tl It 4 013 30-31 47-48 65 1.6 1.2 0.8 0.4 0.0 0.45 0.55 0.65 0.75 5 012 II II 66 II II II II II It II II tl 6 Oil II II 67 II II II II II II II It tl 7 010 II II 68 II II II II II II II II II 8 020 30-31 46-47 68 1.6 1.2 0.8 0.4 0.0 1.15 1.05 0.95 0.85 9 021 II II 67 II II II II II II II " II 10 022 It II 66 II II II II II II II II II 11 023 II II 65 II II II II II II II tl tt 12 033 30-31 45-46 65 1.6 1.2 0.8 0.4 0.0 1.25 1.35 1.45 1.55 13 032 II II 66 II II II II II II II II II 14 031 II II 67 II II II II II II II II II 15 030 II II 68 II II II II II II II II tl Table 1, Switches Closed Circuit Voltages Digital Cyclic Signal Base 4 divider divider divider line line line line line line line line line t 1 2 3 34 42 43 44 37 61 62 63 64 16 130 29-30 45-46 68 1.6 2.0 2.4 2.8 3.2 1.95 1.85 1.75 1.65 1 17 131 It It 67 It II II n ii It II It II 1 18 132 It It 66 II II It II II II II It II 1 19 133 II II 65 II II It II It II II It II 1 20 123 29-30 46-47 65 1.6 2.0 2.4 2.8 3.2 2.05 2.15 2.25 2.35 2 21 122 II II 66 II II II It II II tt It II 2 22 121 II II 67 II It II II II II II II II 2 23 120 It II 68 II II It II tl It II tl II 2 24 110 29-30 47-48 68 1.6 2.0 2.4 2.8 3.2 2.75 2.65 2.55 2.45 2 25 111 II II 67 It II II II It II II II II 2 26 112 II II 66 II II II II II It II II II 2 27 113 II II 65 II II II II II II II II tt 2 28 103 29-30 48-49 65 1.6 2.0 2.4 2.8 3.2 2.85 2.95 3.05 3.15 2 29 102 II II 66 II tl II II II II II II It 2 30 101 II II 67 II II tl II II It II II II 3 31 100 II II 68 II It II II tl II II II II 3 Switches Closed Circuit Voltages Digital Cyclic Signal Base 4 divider divider divider line line line line line line line line line 1 2 3 34 42 43 44 37 61 62 63 64 32 200 28-29 48-49 68 4.8 4.4 4.0 3.6 3.2 3.55 3.45 3.35 3.25 33 201 It II 67 II It II II II II II It II 34 202 II II 66 It II It II II II II n II 35 203 II II 65 II II II II It II II II II 36 213 28-29 47-48 65 4.8 4.4 4.0 3.6 3.2 3.65 3.75 3.85 3.95 37 212 It II 66 II It It II II II It It tl 38 211 II II 67 II II II II II II It II II 39 210 II It _»*' 68 II II II II II tl II It II 40 220 28-29 46-47 68 4.8 4.4 4.0 3.6 3.2 4.35 4.25 4.15 4.05 41 221 It II 67 tl II II II II II II II II 42 222 II II 66 It II II II It II II II II 43 223 It tl 65 II II II II II tl II 1" II 44 233 28-29 45-46 65 4.8 4.4 4.0 3.6 3.2 4.45 4.55 4.65 4.75 45 232 II II 66 II II II II It tl II It II 46 231 II II 67 II II II It II II II II II 47 230 It II 68 It tl II tl II II II II tl Table 1 (cont.), Switches Closed Circuit Voltages Digital Cyclic Signal Base 4 divider divider divider line line line line line line line line line t 1 2 3 34 42 43 44 37 61 62 63 64 48 330 27-28 45-46 68 4.8 5.2 5.6 6.0 6.4 5.15 5.05 4.95 4.85 4 49 331 it ιι 67 II II It II tl II II II It 4 50 332 11 " 66 II It It II It " II II II II 5 51 333 " „.• " 65 II II II It It It II II tl 5 52 323 27-28 46-47 65 4.8 5.2 5.6 6.0 6.4 5.25 5.35 5.45 5.55 5 53 322 " " 66 tl II II II II It It II II 5 54 321 it it 67 It II II II tl II It tl It 5 55 320 " " 68 II II II tl II II II II It 5 56 310 27-28 47-48 68 4.8 5.2 5.6 6.0 6.4 5.95 5.85 5.75 5.65 5 57 311 ., 67 It II '» II tl II II II II 5 58 312 " " 66 II II It It II II II II II 5 59 313 " 65 II It tl II II II II II tl 5 60 303 27-28 48-49 65 4.8 5.2 5.6 6.0 6.4 6.05 6.15 6.25 6.35 6 61 302 " " 66 II II II tt II II II II II 6 62 301 ιι n 67 II II tl II It It tl II tt 6 63 300 " " 68 tl II II II It II II II II 6 Table 1 (cont.), cyclic base 4 code, and the state of the switches of divider stage 3, switches 65 through 68, corresponds to the value of the right digit of the cyclic base 4 code. A characteristic of the cyclic base 4 code is that the value of only one digit changes between any two successive digital signal values. Similarly, the pattern of the switch settings of the system of Figure 1 is such that the switch settings in only one of the three dividers is changed between any two adjacent signal values. A result is a high useful resolution, which is not necessarily limited by the accuracies of the individual components within the system of Figure 1. Figure 2 is a diagrammatic illustration of a read-only memory for the conversion of a six-bit binary number signal from a normal binary code into a 14-bit code which may be used to control the switches of the system of Figure 1. Figure 2 includes read-only memory 81. Terminals 82, 83, 84, 85, 86 and 87 are connected to six word address inputs of read-only memory 161. Fourteen data bit outputs of read-only memory 81 are connected to terminals 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100 and 101. Read-only memory 81 may be used as part of switch control 13 to control the states of switches 27 through 31, 45 through 49, and 65 through 68 of Figure 1 in accordance with a six-bit binary number coded in normal binary form in digital data register 11. Read-only memory 81 is a six-bit input (64 word) , 14-bit output read-only memory. Read¬ only memories of this general type are available as standard commercial products. If so desired, read-only memory 81 may be constructed as a set of two or more individual read-only memories, each providing some number of the total of 14 output bit signals. The six-bit binary register within digital data register 11 is connected to terminals 82 through 87, the word selection inputs of read-only memory 81. The most significant bit signal may be connected, for example, to terminal 82, the least significant bit signal to terminal 87, and the intermediate bit signals to terminals 83 through 86. Terminals 88 through 101 are the 14 individual bit outputs of read-only memory 81. For each of the 64 combinations of binary signal values which may be applied to terminals 82 through-87, corresponding to digital signal values of zero through 63, read-only memory 81 generates a predetermined pattern of 14 logical signals on terminals 88 through 101. Semiconductor switches are commercially available which can be used for the individual switches of Figure 1, and which can be connected, either directly or through suitable buffer circuits, to logic level signal outputs such as from read-only memory 81. The signals on terminals 88 through 92 control the states of switches 27 through 31, respectively. The signals on terminals 93 through 97 control the states of switches 45 through 49, respectively, and the signals on terminals 98 through 101 control the states of switches 65 through 68, respectively. In each case, a logical low or zero signal will cause the corresponding switch to be in an off or open state, and a logical high or one signal will cause the corresponding switch to be in a closed or on state. Table 2 illustrates the operation of read-only memory 81 in greater detail. Table 2 lists the digital signal values of zero through 63, the corresponding six-bit binary code signals which are applied to input terminals 82 through 87, and the corresponding switch control output signals for switches 27 through 31, 45 through 49, and 65 through 68. For convenience, the 14-bit output of read-only memory 81 is shown as two five-bit control words and one four-bit control word, which are used to control the corresponding groups of switches. The switch 27-31 column shows the five control bits on terminals 88 through 92, which control the states of switches 27 through 31. The terminal 88, switch 27 control bit is the leftmost bit of the five bits shown in the switch 27-31 column, and the terminal 92, switch 31 control bit is the rightmost bit shown in the switch 27-31 column. For example, for a digital signal value of zero, the control bit values of 00011 in the switch 27-31 column show that the terminal 88, 89 and 90 signals are logical low or zero signals, and the terminal 91 and 92 signals are logical high or one signals. This corresponds to switches 27, 28 and 29 being off or open, and switches 30 and 31 being on or closed, and corresponds to the listing for a OMP iP Switch Settings Digital Binary Signal Code 27-31 45-49 65-68 0 000 000 00011 00011 0001 1 000 001 II II 0010 2 000 010 It It 0100 3 000 Oil II II 1000 4 000 100 00011 00110 1000 5 000 101 II II 0100 6 000 110 II It 0010 7 000 111 II II 0001 8 001 000 00011 01100 0001 9 001 001 II II 0010 10 001 010 It II 0100 11 001 Oil It II 1000 12 001 100 00011 11000 1000 13 001 101 It 11 0100 14 001 110 It II 0010 15 001 111 II 1? 0001 16 010 000 00110 ■ 11000 0001 17 010 001 It II 0010 18 010 010 II II 0100 19 010 Oil II II 1000 20 010 100 00110 01100 1000 21 010 101 II II 0100 22 010 110 II II 0010 23 010 111 . II II 0001 24 Oil 000 00110 00110 0001 25 Oil 001 II II 0010 26 Oil 010 II It 0100 27 Oil Oil II It 1000 28 Oil 100 00110 00011 1000 29 Oil 101 It II 0100 30 Oil 110 II II 0010 31 Oil 111 II II 0001 Table 2, Operation of Read-Only Memory 81 of Figure 2. Switch Settings Digital Binary Signal Code 27-31 45-49 65-68 32 100 000 01100 00011 0001 33 100001 tl II 0010 34 100010 II 11 0100 35 100 Oil It 11 1000 36 100 100 01100 00110 1000 37 100 101 It 11 0100 38 100110 It tl 0010 39 100 111 II II 0001 40 101 000 01100 01100 0001 41 101 001 It 11 0010 42 101 010 II II 0100 43 101 Oil II II 1000 44 101 100 01100 11000 1000 45 101 101 11 II 0100 46 101 110 II II 0010 47 101 111 It II 0001 48 110 000 11000 11000 0001 49 110001 II II 0010 50 110010 It 11 0100 51 110 Oil li II 1000 52 110 100 11000 01100 1000 53 110 101 II II 0100 54 110 110 It II 0010 55 110 111 II 11 0001 56 111 000 11000 00110 0001 57 111 001 II II 0010 58 111010 tl It 0100 59 111 Oil II II 1000 60 111 100 11000 00011 1000 61 111 101 M tl 0100 62 111 110 II II 0010 63 111 111 11 tl 0001 Table 2 (cont.), Operation of Read-Only Memory 81 of Figure 2. digital signal value of zero in Table 1. Similarly, the switch 45-49 column of Table 2 shows the five control bit signals on terminals 93 through 97, which control the states of switches 45 through 49 and the switch 65-68 column shows the four control bit signals on terminals 98 through 101, which control the states of switches 65 through 68. Multi-stage cascaded voltage dividers, with and without isolation amplifiers between the stages, have been known and used for many years. The Kelvin-Varley potentiometer circuit is an example of a multi-stage cascaded voltage divider set, in which all resistors are precisely matched. More recently, with the availability of suitable electronic isolation amplifiers, such amplifiers have been used between the stages to reduce or substantially eliminate the effects of the loading of one divider stage upon another. However, such conventional non-cyclic multi-stage dividers have a problem which is shared generally by non-cyclic digital-to-analog converters. The problem is that the converter output is a sum of a number of signals controlled by a number of switches and, for at least some transitions between adjacent digital values, two or more of the switch circuits must change state. The result is that the particular analog output step is a sum or partial cancellation of several signals, all of which must be accurately matched if the analog step size and effective converter resolution are to be maintained. If the circuit accuracy is not sufficiently precise, this leads to discontinuous breaks in the digital input/analog output relationship, so that the effective converter resolution may be well under the number of bits implemented in the converter circuitry. In some cases, at such multiple switch transition points, the analog output may actually change in an opposite direction for an increase in digital signal value. A novel feature of the system of Figure 1 is the cyclic switching pattern, such that only one switching transition in one divider stage is made for a transition between any two adjacent digital signal values. In the cyclic converter system of Figure 1, component and circuit inaccuracies will cause errors in the overall conversion ^{j K y _ C...PI ^ accuracy and individual analog output step sizes, but will in general not introduce the type of discontinuous breaks in the digital input/ analog output relationship that may occur with conventional non-cyclic converters. As an example, with substantial component errors, the converter of Figure 1 might have an absolute error of several tenths of a volt at midscale. However, the size of each analog output step would still be within a few percent of the nominal 0.1 volt step size, and the converter would still have a useful resolution of 0.1 volts per step, even though the absolute conversion error in midscale might be several times that amount. In contrast, a conventional converter with an absolute conversion error of several tenths of a volt would probably have discontinuous breaks in its digital input/analog output relationship, so that the useful resolution would be no better than the size of those discontinuous breaks. ' Figure 3 is a diagrammatic illustration of a second form of the invention showing a two-stage circuit for the digital-to-analog conversion of a six-bit binary number signal into an analog voltage signal, in which each stage is associated generally with a group of three bits of the binary number and illustrating the use of individual ladder network digital-to-analog converters in both stages. In Figure 3, digital data register 111 is connected via data path 112 to switch control 113, which is connected via link 114 to switches 127, 128, 136, 137, 138, 155, 156 and 157. A first side of voltage reference 115 is connected via line 116 to a first side of converter section 117, and via line 118 to a first side of converter section 119. A second side of voltage reference 115 is connected via line 120 to ground 121, via line 122 to a second side of converter section 117, and via line 123 to a second side of converter section 119. Within converter section 117, line 116 is connected to a first side of resistor 124 and to a first side of each of switches 127 and 128. The second side of τesistor 124 is connected to line 125. Line 122 is connected to a first side of resistor 126 and to a second side of each of switches 127 and 128. The second side of resistor 126 is ^. A O. connected to line 125. The common point of switch 127 is connected via line 129 and resistor 130 to line 125. The common point of switch 128 is connected via line 131 and resistor 132 to line 133. Resistor 134 is connected between line 125 and line 133. Within converter section 119, line 118 is connected to a first side of each of switches 136, 137 and 138. Line 123 is connected to a second side of each of switches 136, 137 and 138. The common point of switch 136 is connected via line 139 and resistor 140 to line 141. The common point of switch 137 is connected via line 142 and resistor 143 to line 141, and the common point of switch 138 is connected via line 144 and resistor 145 to line 146. Resistor 147 is connected between line 141 and line 146. Line 133 is connected to the input of voltage follower amplifier 135, whose output is connected to line 149. Line 146 is connected to the input of voltage follower amplifier 148, whose output is connected to line 151. Line 149 is connected to a first side of interpolation section 150 and line 151 is connected to a second side of interpolation section 150. Within interpolation section 150, line 149 is connected to a first side of resistor 152 and to a first side of each of switches 155, 156 and 157. Line 151 is connected to a first- side of resistor 154 and to a second side of each of switches 155, 156 and 157. The second side of resistor 152 and the second side of resistor 154 are connected to line 153. The common point of switch 155 is connected via line 158 and resistor 159 to line 153. The common point of switch 156 is connected via line 160 and resistor 161 to line 162, and the common point of switch 157 is connected via line 164 and resistor 165 to line 166. Resistor 163 is connected between line 153 and line 162, and resistor 167 is connected between line 162 and line 166. Line 166 is connected to the input of voltage follower amplifier 168, whose output is connected to terminal 169. Digital data register 111 is a source of a six-bit binary number signal which is to be converted into an analog voltage signal on terminal 169. Switch control 113 controls the states of switches 127 and 128, 136 through 138, and 155 through 157 in accordance with the digital value in data register 111. Switch control 113 may be a read-only memory as illustrated in the system of Figures 1 and 2, a network of logical gates, a combination thereof, or such other control means as may be appropriate. Switches 127 and 128, 136 through 138, and 155 through 157 are single-pole two-position switches. They may be semiconductor switches, such as field effect transistor switches, electromechanical relay switches, manually operated switches, or such other type switches as may be appropriate for the application. Each of switches 127 and 128, 136 through 138, and 155 through 157 are shown in a position that will be identified as a 0 (zero) position. The alternate position will be identified as a 1 (one) position. Voltage reference 115 is a source of a reference voltage signal which will normally be of substantially constant value. In the subsequent description of the operation of the system of Figure 3, it will be assumed that the output of voltage reference 115 on line 116, relative to line 120 and ground 121, is +6.4 volts. The set of resistors 124, 126, 130, 132 and 134 within converter section 117 is a matched set whose individual resistance values are related substantially in accordance with predetermined ratios. The resistance values of resistors 130 and 132 are each substantially equal to twice the resistor 134 value, and the resistance values of resistors 124 and 126 are each substantially equal to four times the resistor 135 value. The resistor 134 value will typically be in the range of a few hundred to a few tens of thousands of ohms. A resistor 134 value of the order of one to a few thousand ohms would be suitable for use with a 6.4 volt reference value. The set of resistors 140, 143, 145 and 147 within converter section 119 is a similar matched set whose individual values are related substantially in accordance with predetermined ratios. The resistance values of resistors 140, 143 and 145 are each substantially equal to twice the resistor 147 value. As in the case of resistor 134, the resistance value of resistor 147 will typically be in the range of a few hundred to a few tens of thousands of ohms, and a value of one to a few thousand ohms would be suitable for use with a 6.4 volt reference value. The set of resistors 152, 154, 159, 161, 163, 165 and 167 within interpolation section 150 are also a matched set whose individual values are related substantially in accordance with predetermined ratios. The resistance value of resistor 163 is substantially equal to resistance value of resistor 167. The resistance values of resistors 159, 161 and 165 are each substantially equal to twice the resistor 167 value, and the resistance values of resistors 152 and 154 are each substantially equal to four times the resistor 167 value. As in the case of resistors 134 and 147, the resistance value of resistor 167 will typically be in the range of a few hundred to a few tens of thousands of ohms, and a value of one to a few thousand ohms would be suitable for the present example. Amplifiers 135, 148 and 168 are voltage follower amplifiers of substantially unity gain, and provide output signals which are substantially equal to their input signals. The analog voltage output signal of the system of Figure 3 appears on terminal 169, An analog load may be connected to the system by connecting it between terminal 169 and ground 121. The operation of the system of Figure 3 is generally similar to the operation of the system of Figure 1. Converter sections 117 and 119 function as a first voltage divider stage, dividing the voltage reference 115 signal and providing signals on lines 133 and 146 which generally resemble the signals on lines 32 and 35 of Figure 1. Converter section 150 acts as a final divider or interpolation stage, performing a function generally similar to that of the third divider stage of Figure 1 between lines 52 and 55 and terminal 71. In operation, the system of Figure 3 will provide analog output voltage signals on terminal 169 over a range of 0.05 through 6.35 volts, in steps of 0.1 volts, for digital signals in digital data register 111 from zero through 63 in steps of 1. In analyzing the operation of the system of Figure 3, it will be assumed that the output of voltage reference 115 on line 116, relative to line 120 and ground 121 is +6.4 volts, that the resistor sets within converter sections 117 and 119 and interpolation section 150 are accurately of the previously described ratios, and that voltage follower amplifiers 135, 148 and 168 are of substantially unity gain and without significant input currents or voltage offsets. The states of switches 127, 128, 136, 137, 138, "BUREAU PA'.?! _ A. ' U'O >,' 155, 156 and 157 are controlled by switch control 113 in a manner which is a predetermined function of a six-bit binary data word within digital data register 111. For a digital signal of zero within digital data register 111 (binary 000 000) , the eight switches in the system of Figure 3 will be in the positions shown. The output signal of converter section 119 on lines 146 and 151 will be zero volts. Converter section 117 will generate a line 133 and 149 signal of one-eighth of the line 116 signal relative to line 122 or 0.8 volts. Interpolation section 150 will provide an output signal on line 166 and terminal 169 of one- sixteenth of the line 149 signal relative to the line 151 signal or 0.05 volts. Converter section 117 is a two-bit ladder network digital- to-analog converter which will generate line 133 signals of 0.8, 2.4, 4.0, or 5.6 volts, depending on the settings of switches 127 and 128. Converter section 119 is a modified two-bit ladder network digital- to-analog converter which will generate line 146 signals of 0.0, 1.6, 3.2, 4.8, or 6.4 volts, depending on the settings of switches 136, 137 and 158. Interpolation section 150 is a three-bit ladder network digital-to-analog converter which generates line 166 and terminal 169 output voltage signals from one-sixteenth to fifteen-sixteenths of the line 149 signal relative to the line 151 signal, in steps of one-eighth, depending upon the settings of switches 155, 156 and 157. Table 3 further illustrates the operation of the system of Figure 3. Table 3 lists the 64 digital signal values, from zero through 63, which may be contained within digital data register 111, a cyclic octal representation corresponding to the digital signal values, the states of the eight switches, 127, 128, 136, 137, 138, 155, 156 and 157, and selected circuit voltages, including the terminal 169 analog output signal, for each digital signal value. The "Switch Settings" columns of Table 3 indicate the positions of the eight switches of the system of Figure 3 for each digital signal value. The "section 117" column lists a 2-bit control word which indicates Table 3, Operation of the System of Figure 3. Table 3 (cont.), Operation of the System of Figure 3. the positions of switches 127 and 128. The left bit of the 2-bit control word indicates the position of switch 128 and the right bit indicates the position of switch 127. The "section 119" column lists a 3-bit control word which indicates the positions of switches 136, 137 and 138. The left bit of the 3-bit control word indicates the position of switch 138, the middle bit indicates the position of switch 137 and the right bit indicates the position of switch 136. The "section 150" column lists a 3-bit control word which indicates the positions of switches 155, 156 and 157. The left bit of the 3-bit control word indicates the position of switch 157, the middle bit indicates the position of switch 156 and the right bit indicates the position of switch 155. In each case, a 0 (zero) value for a particular bit indicates that the corresponding switch is in the position shown in Figure 3. A 1 (one) value indicates that the corresponding switch is in a position opposite to that shown in Figure 3. For example, for a digital signal value of 20, Table 3 lists a section 117 control word of 01. The left bit of this control word is 0, indicating that switch 128 is in the position shown in Figure 3. The right bit of the control word is 1, indicating that switch 127 is in the position opposite to that shown in Figure 3. The section 119 control word is 010. The left bit of this control word is 0, indicating that switch 138 is in the position shown. The middle bit is 1, indicating that switch 137 is in the position opposite to that shown, and the right bit is 0, indicating that switch 136 is in the position shown. The section 150 control word is 100. The left bit of this control word is 1, indicating that switch 157 is in the position opposite to that shown. The middle and right bits are both 0, indicating that switches 156 and 155 are in the positions shown in Figure 3. The circuit voltages listed in Table 3 are all relative to ground 121. As may be seen from Table 3, the terminal 169 output voltage varies from 0.05 volts through 6.35 volts, in steps of 0.1 volt, for digital signal values of zero through 63, in steps of one. The pattern of the switch settings is related to the cyclic octal code. The states of the switches within converter sections 117 and 119 correspond to the value of the left digit of the cyclic octal code. Similarly, the states of the switches within interpolation section 150 correspond to the value of the right digit of the cyclic octal code. A characteristic of the cyclic octal code is that the value of only one digit changes between any two successive digital signal values. Similarly, the pattern of the switch settings of the system of Figure 3 is such that the switch settings in only one of sections 117, 119 and 150 will change between any two adjacent digital signal values. As before, this provides a high resolution which is not necessarily limited by the accuracies of the individual components within the system of Figure 3. In an ideal digital-to-analog converter, when the digital input signal is changed from a first value to a second value, the analog output signal will make a smooth transition from a first value corresponding to the first digital signal to a second value corresponding to the second digital signal. In an actual digital-to- analog converter, spurious signals, sometimes called glitches, may occur. These spurious signals are momentary signals during a transition which are outside of the range defined by the first and second analog signal values. Certain types of conventional digital-to-analog converters, such as ladder network converters, are particularly subject to this spurious signal problem. A reason for this is that in such conventional converters it may be necessary to simultaneously make several switching transitions for a digital signal change between two adjacent values. For example, consider a 6-bit conventional ladder network binary digital-to-analog converter. The transition from 011111 (31) to 100000 (32) requires a change of all six circuit switches. If the six switching transitions do not occur effectively simultaneously, there may be momentary transient states corresponding to anything from 000000 (0) to 111111 (63) , and the generation of corresponding momentary spurious signals. Systems constructed in accordance with O?,; τ i? the present invention will generally be less subject to this spurious signal problem, as they generally do not require such simultaneous switching. However, it may still be of interest to consider means for the control and reduction of such spurious signals. Such spurious signals may be reduced or eliminated by a variety of techniques. One such technique is to use an output voltage follower amplifier whose response characteristics are such that it simply does not respond to a momentary spurious signal. For example, in the circuit of Figure 1, output voltage follower amplifier 70 may be such a slow response amplifier. However, the use of such a slow response output amplifier may not be acceptable in applications where a rapid response of the analog output signal to the digital signal value is desired. Another technique which may be used to reduce or eliminate such spurious signals is the use of a form of sample-and-hold circuit as part of the output amplifier stage. A typical sample-and-hold circuit consists of a switch between an input signal line and the input of a voltage follower amplifier, with a capacitor being connected between the amplifier input and a suitable ground. When the switch is closed, the voltage follower amplifier follows the input signal and operates as a normal voltage follower amplifier. If the switch is opened momentarily, the output of the voltage follower amplifier remains at approximately the value just before the switch was opened. In the circuit of Figure 1, the sample-and-hold switch would be connected between line 69 and the input of amplifier 71, in place of a direct connection between line 69 and amplifier 71. The sampling switch would be controlled by switch control 13, so that it would be opened momentarily whenever the states of any of the switches of the system were changed. The sampling switch would then be closed shortly thereafter, after any spurious signals had passed. An additional technique which may be used to reduce or eliminate spurious signals in converters constructed in accordance with the present invention is to limit and/or filter some number of the switch output voltages. For example, the voltages on lines 32 and 35 of Figure 1 during the transitions of switches 27 through 31 may be limited and filtered by connecting a small capacitor between line 32 and a circuit ground point, and one between line 35 and a ground point, and/or by other means as may be desired. Similar transient limiting and/or filtering may be applied to other switches of the circuit of Figure 1, and to other switches of other forms of the invention. The switches and switch groups shown in various figures of this specification may be either break-before-make or make-before- break type switches, depending upon the application. In the circuit of Figure 3, the switches should, in general, be break-before-make type switches to avoid placing momentary short circuits across voltage reference 115 or various voltage follower amplifiers when the switches are operated. In certain other forms of the invention, it may be desirable to use make-before-break type switches. For example, within the switch groups shown in Figure 1, it may be appropriate to use make-before-break type switches. For example, in the group of switches 27-31, when making a transition from switches 30 and 31 being closed to switches 29 and 30 being closed, the transition pattern may be a break-before-make pattern in which the three states are switches 30 and 31 closed, switch 30 only closed, and switches 29 and 30 closed. Alternately, the switch group may be controlled so as to operate in a make-before-break pattern. In that case, the transition would be, for example, switches 30 and 31 closed, switches 29, 30 and 31 closed, and switches 29 and 30 closed. Similarly, the other groups of switches in Figure 1 may be controlled so as to operate in a break-before-make pattern or a make-before-break pattern, as may be appropriate for the application. The use of make-before-break switching in certain forms of the invention, such as shown in Figure 1, may aid in reducing or eliminating spurious signals such as were mentioned previously. The preceding disclosure has shown particular forms and combinations of the subject invention. Other forms and combinations may be devised to meet particular requirements. Some of the possible variations of the subject invention are described below. These variations may be applied to the subject invention individually and/or in combination. Figure 1 shows the use of three cascaded potentiometer- type voltage divider stages, while Figure 3 shows two cascaded ladder network-type voltage divider stages. ' These and other foτms of voltage dividers may be used in various combinations. For example, a ladder network interpolation stage such as section 150 of Figure 3 may be substituted for the third divider stage in a circuit otherwise resembling that of Figure 1. In that case, lines 52 and 55 of Figure 1 could be connected to lines 149 and 151 of interpolation section 150. Similarly, the first divider stage of Figure 3, including converter sections 117 and 119, may be substituted for the first divider stage in the system of Figure 1. In that case, lines 133 and 146 of Figure 3 could be connected to lines 32 and 35 of Figure 1. For convenience and clarity of illustration, the digital-to- analog conversion systems shown and described herein have generally been limited to short digital word lengths and correspondingly low conversion accuracies and resolutions. The general techniques may be readily adapted for the design and construction of converters for other digital word lengths and, in particular, may be extended for longer digital word lengths and correspondingly high conversion accuracies and resolutions. The preceding disclosure has shown a number of systems for the digital-to-analog conversion of digital signals coded in a binary or closely related form, base 4 and octal (base 8) codings being closely related to binary codings. The general features of the subject invention may be used for the digital-to-analog conversion of digital signals coded in other radices as may be desired. For example, the general arrangement of Figure 1 may be used as a guide for the design of a digntal-to-analog converter providing an analog output signal corresponding to a three-digit decimal digital signal. In that case, the first two divider stages would each contain 10 series connected resistors and 11 switches. The last divider stage would contain 11 series connected resistors and 10 switches. The preceding disclosure has shown a number of digital-to- analog conversion systems with two or more divider stages and with the same division ratio or number of steps per stage. For example, - Figure 1 shows a system with three base 4 stages, for a total of 64 steps, and Figure 3 shows a system with two octal stages for a total of 64 steps. Similar systems may be devised in which the individual stages do not have the same dividion ratio or number of steps. For example, a three stage system may be devised generally along the lines of the system of Figure 1, but with an octal divider stage substituted for the first divider stage which includes resistors 20 through 23. The modified system would then include one octal and two base 4 stages, for a total of 128 steps. The preceding disclosure has shown a number of digital-to- analog conversion systems in which the digital input values are described as coded in a normal binary or similar form, and in which the digital input values may vary over a range from zero through some upper limit. Similar systems may be devised in which the digital input values are coded in some other form, for example, a Gray code, a 4-2-2-1 code, an excess three code, a two out of five code or a bi¬ quinary code. Similar systems may be devised in which the digital input values may vary through a range of negative values, in addition to or in place of a range of positive values, or a range which does not include zero. The preceding disclosure has shown a number of digital-to- analog conversion systems in which the analog output signal may vary over a range from near zero through some maximum positive value. Similar systems may be devised in which the analog output signal range includes a range of negative values, in addition to or in place of a range of positive values, or is a range which does not include or is not adjacent to zero. For example, lines 16 and 19 of Figure 1 may be connected to sources of two reference voltages. The system of Figure 1 will then provide analog output signals over a range from near the line 19 reference voltage value to near the line 16 reference voltage value. In some instances, it may be desirable to generate analog signals of either polarity about a ground or zero reference potential, and to connect a center or internal point of a digital-to-analog conversion system to the ground or zero reference potential to aid in maintaining the precision of signals near the ground or zero reference value. For example, the system of Figure 1 may be arranged in such a anneT by connecting line 16 to a source of a first reference potential, line 19 to a source of a second reference potential, and one or more of lines 24, 25 and/or 26 to other sources of reference potentials. In that case, any one of lines 16, 19, 24, 25 or 26 may be connected to a ground or zero reference potential point and the system will operate substantially as previously described. If reference potentials are supplied to both sides of one or more of resistors 20, 21, 22 and/or 23, those resistors may be deleted if desired. In some instances, such as the conversion of audio voice signals to and from digital form, it may be desirable to perform non-linear conversions in which the relationship of the analog and digital signals is intentionally non-linear. For example, analog-to- digital and digital-to-analog converters are sometimes arranged such that the analog increments are smaller near a ground or zero reference value to give finer resolution for low amplitude signals. Systems incorporating the subject invention may be arranged in a similar manner. For example, in the system of Figure 1, resistors 20 and 23 may be of a first value, and resistors 21 and 22 may be of a second, smaller value. The system of Figure 1 would then provide non-linear conversions with 16 steps between the line 16 and line 24 voltages, 16 steps between the line 24 and line 25 voltages, 16 steps between the line 25 and 26 voltages, and 16 steps between the line 26 and line 19 voltages. In a bipolar conversion system incorporating such a non¬ linear feature, it may be desirable to also incorporate the center or internal point grounding variation described above. In the preceding descriptions of the operation of the systems of Figures 1 and 3, it was assumed that each system included a source of a reference voltage of substantially constant value. As previously described, the system of Figure 1 may be considered as a system which generated terminal 71 analog output signals of from 1/128 through 127/128 of the line 16 voltage, in steps of 1/64. In some applications, it may be desirable to employ a variable voltage signal as a reference voltage. Conventional digital-to-analog converters are sometimes operated with variable reference voltage signals to generate an analog output signal corresponding to a product of an analog input signal and a digital value. Such converters are sometimes referred to as multiplying digital-to-analog converters. Digital-to-analog conversion systems constructed in accordance with the present invention may be operated in similar manners. For example, the system of Figure 1 may be operated with a variable analog signal source substituted for voltage reference source 15. The terminal 71 analog output signal would then be from 1/128 through 127/128 of the line 16 voltage, in steps of 1/64, for digital signal values of zeτo through 63 in digital data register 11. The preceding disclosure has shown digital-to-analog conversion systems which generate an analog voltage corresponding to a digital data word. Similar systems may be constructed in which an analog output is in the form of a current into a low or moderate impedance load. For example, a series combination of a resistor and a low impedance analog load could be connected between terminal 71 and ground 18 of Figure 1. The analog output signals of a digital-to- analog converter constructed in accordance with the present invention may be used to control other electronic circuits so as to provide an analog output which is a frequency, phase, or such other signal as may be desired, or to control other quantities such as pressure, mechanical motion, or such other quantities as may be desired. The preceding disclosure and the drawings have described and shown the use of voltage follower amplifiers as isolation amplifiers between converter stages. In such voltage follower amplifiers, the wip output voltage will normally be substantially equal to the input voltage. A principal function of such isolation amplifiers is to provide a voltage signal to a load circuit, while reducing the loading effects of the load circuit upon the signal source circuit. In some instances, it may be desirable to use other forms of isolation amplifiers for some or all of the isolation amplifiers in a particular system. For example, pairs of isolation amplifiers, whose outputs are related to their input signals by a gain factor other than unity, either positive or negative, may be substituted for one or more of the between converter stage amplifier pairs in the systems shown in the drawings. A non-unity gain isolation amplifier may be used as a system output amplifier to drive an analog load. The individual between converter stage amplifier pairs and/or the system output amplifier, in a particular system, need not all have the same gain. The drawings and the preceding specification have shown and described the use of certain types of semiconductor, electromechanical and manually operated switches in the subject invention. These and/or other types of switches may be used to perform switching functions in various forms of the invention. The preceding disclosure has mentioned data registers, switch control circuits, logical gate networks and read-only memories which may be used for various logical and digital elements in implementations of the subject invention. The specific circuit elements and devices may be, for example, 7400 series TTL (transistor transistor logic) integrated circuit devices, MOS (metal oxide semiconductor) devices, or such other type devices as may be appropriate for the application. ; , The subject invention is not limited to implementations with these or any other specific circuit elements and devices, and may be implemented with various types of present and/or future logical and digital elements and devices as may be appropriate. At the present time, logical and digital elements and devices are predominantly of a binary or two state nature. That is, the input and output signals are normally of one of two possible values and, in general, not of intermediate or other values. Some logical elements and devices have been devised which operate with more than two possible normal signal values. The concepts of the subject invention may be implemented with non-binary or non-two-state logical and digital elements and devices as so desired. The preceding disclosure has shown and described the use of particular voltage follower amplifier elements. Other present and/or future analog circuit elements and devices may be used to provide analog signal operations for the subject invention. Figure 2 shows the use of a read-only memory for converting a normal binary coded representation of an input digital signal into another representation. In general, networks of logical gates, read¬ only memories and/or other means as may be desired may be used for such code conversions. Given a set of input data lines to a logical gate network or device, a set of output data lines thereof and a desired relationship between the input and output data values, there are, in general, many gate networks and/or logical devices that can provide the desired relationship. A gate network could be used in place of read-only memory 81 of Figure 2. The gate network would have six data input lines, 14 data output lines and would implement the data relationships shown in Table 2. Combinations such as a combination of a network of logical gates and read-only memory or other devices may also be used for such purposes. In the system of Figure 1, a six-bit digital signal is converted into a 14-bit representation of the same number for the control of 14 switches. In the system of Figure 3, a six-bit digital signal is converted into signals for the control of eight two-position switches. The exact form of the desired switch code representation will depend on the particular circuit employed and its desired manner of operation. In some instances, the digital data from a digital signal source may already be in a cyclic, Gray or other suitable switch control code, so that no further code conversion is required. In the claims, the term logical as in logical signal is intended to imply a signal which will normally have one of a predetermined number of values except for transitions between those values. The term digital as in digital signal is intended to generally imply a signal representing a digital value which may correspond to one or more logical signals. The term analog as in analog signal is intended to generally imply a signal whose value may vary more or less continuously over a range. In a particular application, an analog signal generated by a signal source may possess this characteristic to a greater or lesser extent. For example, the analog signal output of a digital-to-analog converter will generally vary in distinct steps. A particular signal may have a combination of analog, logical and/or digital properties. For example, the polarity of an analog signal relative to a reference value may be a logical signal and/or a binary digital signal. The term subset is intended in a broad sense. A particular subset, unless otherwise stated, may be empty and/or may include an entire set of which it is a subset. Two subsets of a set may or may not overlap.

Claims: CLAIMS 1. In a digital-to-analog conversion system, the combination of a digital signal source, a reference voltage source, a plurality of successively arranged voltage dividers, and an output terminal, including means connecting said reference voltage source to a first of said voltage dividers, amplification means connecting each of said dividers subsequent to said first divider to the preceding divider, means connecting the last of said dividers to said output terminal, and control means connecting said digital signal source to each of said dividers and controlling the states of said dividers in accordance with a digital signal value of said digital signal source. 2. The combination of Claim 1 further characterized by the arrangement of said combination being such that the state of only one of said dividers is changed for a transition between any two adjacent signal values. 3. The combination of Claim 1 further characterized by the states of said dividers corresponding to a cyclic code representation of a digital signal value of said digital signal source, with each individual digit of said cyclic code representation corresponding to the state of one of said dividers, a cyclic code being one in which the value of only one digit changes between any two adjacent signal values. 4. The combination of Claim 2 further characterized by said amplification means being voltage output amplification means generating voltage output signals which are substantially predetermined linear functions of the input voltage signals thereto. 5. The combination of Claim 2 further characterized by said amplification means being voltage follower amplification means generating voltage output signals which are substantially equivalent to the voltage input signals thereto. 6. The combination of Claim 1 further characterized by said amplification means being voltage output amplification means generating voltage output signals which are substantially predetermined linear functions of the input voltage signals thereto. 7. The combination of Claim 1 further characterized by said amplification means being voltage follower amplification means generating voltage output signals which are substantially equivalent to the voltage input signals thereto. 8. The combination of Claim 1 further characterized by each of a non-empty subset of said dividers being connected to a pair of divider input terminals for said divider and to first and second divider output terminals for said divider, said divider connecting one of a first set of voltage signals to said first divider output terminal and one of a second set of voltage signals to said second divider output terminal, said first and second sets of voltage signals being sets of voltage signals within a voltage range whose end points are substantially the voltage signals on said divider input terminals. 9. The combination of Claim 8 further characterized by said first and second sets of voltage signals including no equivalent voltage signals in common. 10. The combination of Claim 1 further characterized by each of a subset of said dividers including a pair of divider input terminals, a plurality of resistance elements connected in series from one of said divider input terminals to the other, a plurality of intermediate terminals connected to said divider input terminals and to the junctions between said resistance elements, first and second divider output terminals, means connecting said first divider output terminal to a selected one of a first subset of said intermediate terminals in accordance with a digital signal value of said digital signal source, and means connecting said second divider output terminal to a selected one of a second subset of said intermediate terminals in accordance with a digital signal value of said digital signal source. IJURE OMPI .Ay WIPO ' 11. The combination of Claim 10 further characterized by said first and second intermediate terminal subsets having a minority of said intermediate terminals in common. 12. The combination of Claim 10 further characterized by said first and second intermediate terminal subsets having none of said intermediate terminals in common.

Inventors: LODE T
Applicants: LODE T
Application year: 1979
Main classification: H03K13
IPC codes: H03M1