SELF-ALIGNED MESFET AND METHOD OF MAKING SAME

Abstract: The method includes a sequence of deposition, mask­ ing, and etching steps, and produces an improved self-­ aligned MESFET. The MESFET has a light acceptor (or donor) impurity doped substrate (65), and light donor (or acceptor) region (55) with a graded doping profile disposed over the substrate (65) for operation as a gate channel region. First and second heavy donor (or acceptor) regions (50, 60) are disposed over the substrate (65) and are adjacently stepped down on either side of the light donor (or acceptor) region (55) for operation as source and drain regions. A schottky contact (35) is disposed over the light donor (or acceptor) region (55), and first and second ohmic contacts (25, 30) are disposed over parts of the first and second heavy donor (or acceptor) regions (50, 60) as source and drain connections. First and second oxide regions (40, 50) are disposed between the schottky contact (35) and each of the ohmic contacts (25, 30), the oxide regions (40, 45) being disposed respectively over part of the heavy donor (or acceptor) regions (50, 60) for inter-layer isolation relative to the light donor (or acceptor) region (55).

Description: SELF-ALIGNED MESFET AND METHOD OF MAKING SAME This invention rela tes to a self-aligned MESFET and a method of making a self-aligned MESFET. The MESFET comprises a substrate lightly doped with an acceptor (or donor) impurity, overlaid with relatively thin first and second areas alternating with areas of thick field oxide, with a heavy donor (or acceptor) impurity introduced into the substrate below the areas of thick oxide for enhancement switch and depletion load devices. European patent application No. 79300721.2 describes and claims a method of making a MESFET upon which the present invention is an improvement. Although MESFETs have high device gain relative to MOSFETs and do not require a thin gate oxide which limits the ultimate advancement of MOS devices, MESFET devices have been relatively unnoticed in the past asa result of their large series source and drain resistances which tend to degrade the actual device gain more severely than MOSFET devices. MESFET structures would only become attractive if the series resistance could be reduced by advanced photolithographic techniques which have not been well developed for practical use. Therefore, it is highly desirable to devise means to minimize these undesirable resistances in MESFET structures without requiring advanced photolithographic techniques to thus make MESFETs competitive with MOSFETs, and the present invention is intended to achieve this. The invention accordingly provides a method of making a self-aligned MESFET which is characterised by the steps of: a) introducing a relatively shallow donor (or acceptor) impurity in the substrate below the first and second thin oxide areas to define with graded profiles first and second light donor (or acceptor) areas therein; b) masking to expose only the second thin oxide area for a relatively deep donor (or acceptor) impurity introduction in the second light donor (or acceptor) area so that the depletion load device will be normally-on; c) layering of an etch resistant over the surface of the first and second thin oxide areas to form a sandwich thereof, and masking away the thin oxide areas to expose the first and second light donor (or acceptor) areas except for narrowly defined first and second gate sandwiches defined to be over gate channel regions; ; d) etching away the exposed first and second light donor (or acceptor) areas to a predetermined depth, and introducing a relatively heavy donor (or acceptor) impurity to define, within each of the light donor (or acceptor) areas, first and second heavy donor (or acceptor) areas as source and drain regions; e) depositing polysilicon and etching away, through masking, all but areas that are adjacent to a heavy donor (or acceptor) area and a thick oxide area, for defining source and drain ohmic contacts, and reoxidizing over the polysilicon areas and part of first and second heavy donor (or acceptor) areas for inter-layer isolation; and f) etching away first and second gate sandwiches thereby exposing first and second light donor (or acceptor) areas, and depositing schottky metal thereon for reaction into a schottky barrier for use as a schottky contact. The method of the invention produces a MESFET with the advantages of improved high device gain as a result of the elimination of series resistance, increased circuit integration density, and improved speed capability due to the elimination of spacings between gate and drain and gate and source and the improved high device gain. A MESFET, and a method of making a MESFET, in accordance with the invention, will now be described, by way of example, with reference to the accompanying drawings, in which Figure 1 is a cross-sectional view of a selfaligned MESFET device having reduced series resistance. Figure 2 is a cross-sectional view of a conventional MESFET prior art device. Figure 3 is a diagram comparing the degradation effects of source resistance and drain resistance on a self-aligned MESFET of Figure 1 and a conventional prior art MESFET of Figure 2. Figure 4A-H shows the processing steps involved in creating a self-aligned MESFET structure having reduced series resistance as shown in Figure 1. In Figure 1 we see a cross-sectional view of a self-aligned MESFET including a source electrode 10, gate electrode 15 and drain electrode 20. The ohmic contacts for the source electrode 10 and drain electrode 20 are of polysilicon (poly) or platinum-silicon compound 25 and 30 respectively. The gate schottky contact 35 is composed of a reacted platinum-silicon compound. Separating the source ohmic contact 25 from the gate schottky contact 35 is a field oxide barrier of silicon dioxide 40. Likewise, separating the gate schottky contact 35 from the drain ohmic contact 30 is a field oxide barrier of silicon dioxide 45. Underneath the oxide barrier 40 and the source electrode contact 25 is a N plus (+) conductive source region or area 50 implanted using the heavy dopant arsenic. Likewise, under the gate schottky contact 35 is a N minus (-) gate channel region or area 55 implanted.using the dopant arsenic. Finally, under the oxide barrier 45 and the drain ohmic contact 30 is an N plus (+) conduc tive drain region or area 60 implanted using the heavy dopant arsenic. It will be noted that the schottky contact 35 is disposed to be stepped-up and over the N- gate channel region 55 relative to the Ns source and drain conductive regions 50 and 60 thereby allowing the silicon dioxide areas 40 and 45 to electrically isolate the contact 15 from the regions 50 and 60. This isolation allows the contact 15 to function effectively as a schottky barrier. All the above areas are supported by a P minus (-) or Pi substrate 65. It will be further noted that the R5 or source resistance and the or on drain resistance approximate zero in the selfaligned MESFET and as such are not shown as in Figure 2 (prior art). In Figure 2 (prior art) there is shown a source electrode 70 connected to an ohmic contact 75 of polysilicon or platinum-silicon compound, a gate electrode 80 connected to a schottky contact 85 composed of a platinum-silicon compound, a drain electrode 90 connected to an ohmic contact 95 of polysilicon or platinumsilicon compound. Interposed between the source ohmic contact 75 and the gate schottky contact 85 is a silicon dioxide barrier 100 and likewise disposed between the gate schottky contact 85 and the drain ohmic 95 is also a silicon dioxide barrier 105. In the conductive channel region is a N plus (+) area 110 below the source ohmic contact 75, an N minus (-) area 115 below the silicon dioxide barriers 100 and 105 and the gate schottky contact 85, and an N plus (+) area 120 beneath the drain ohmic contact 95. Supporting all the above is a P minus (-) substrate 125. It will be noted that the source resistance R5 is shown as 130 and the drain resistance RD is shown as 135 and is relatively substantial as compared to that of the inventive self-aligned MESFET of Figure 1. Referring to Figure 3, there is shown the comparison of the degradation effect of source resistance R5 and drain resistance RD on a MESFET, (gd/c9) where is isdevice gain and cg is gate capacitance. The Y coordinate of Figure 3 is gdJcg(GHZ) which represents the high speed or high frequency capability of the device and the X coordinante is (Vgs-Vth) where Vgs is the gate source voltage and Vth is the threshold voltage. It will be noted that the gd/c9 is 86 percent higher in the self-aligned MESFET (where RS=RD=O) than the conventional prior art MESFET. European Patent Application. No. 79300721.2 shows and describes the conventional process required to get to the structural state shown in Figure 4A. In particular, the selfaligned MESFET process having double-layer interconnections comprises the following detailed steps. It should be noted as indicated supra that in the proposed fabrication process, an enhancement switching device and the depletion load device (basic inverter building block) are fabricated simultaneously. The enhancement switching device is indicated as the E switch 140 and the depletion load device is indicated as the D-load 145. In the first step as shown in Figure 4A, an acceptor minus (P- or Pi) substrate 170, is overlaid with thick field oxidation or relatively thick areas 155A-C of field oxide alternating with thin areas 160A-B of field oxide with donor (P) implants 150A-C, or introduced by other means, underlying the thick oxide 155A-C to prevent undesirable field inversion. The dopant arsenic is implanted, or introduced by other means, as an impurity through a 400A thin oxide or area of relatively thin oxide 160A-B to form the light donor N- areas 165A-B. It will be noted that the light donor or N- layer 165A-B has a graded doping profile, as shown in Figure 4B, where the device behaves similarly to a two step channel - doping MESFET. The main conduction channel ND2(175) is at the bottom layer where doping is the heaviest and the lighter doping being at NDl(180). In the second step, as shown in Figure 4C, a depletion mask is operative to expose the depletion device 145 for a relatively deep donor (N-) or arsenic implant, or introduced by other means, shown as 165B' to make a normally-on load device 145. In the third step as shown in Figure 4D, a gate mask is used to define the narrow gate region to be protected by the silicon nitride 185A-B deposition which is previously applied. The unprotected silicon dioxide areas 160A-B are then etched away leaving only the protected areas, mainly silicon dioxide areas 160A' and 160B' under the silicon nitride areas 185A-B to form a spatially predetermined sandwich thereof. In the fourth step as shown in Figure 4E, silicon etching is applied using a plasma-etch process or ROH (or poly-etch) solution to the unprotected areas 187A-D of the N- channel region 165A-B' for removal thereof to approximately a depth of 2000A. In the fifth step as shown in Figure 4F, source and drain heavy implants or introduction of arsenic dopant is used in the N- channel region 165A-B' to create N+ regions in selected areas therein at 190A-B and 195 A-B. Subsequently, a polysilicon mask is used to define the circuit pattern in conductive poly-silicon (poly) at areas 200A and 200B as source ohmic contacts and 205A and 205B as drain ohmic contacts through the processes of poly deposition through diffusion then selective poly etching using polysilicon mask. In step six there is shown in Figure 4G, a second oxidation or reoxidation indicated as 210 over the polysilicon areas 200A-B and 205A-B and also the N+ areas 190A-B and 195A-B and is operative to produce interlayer isolation. Next, the silicon nitride 185A-B and thin silicon oxide 160A'-B' sandwiches are etched away. Replacing the silicon nitride and silicon dioxide, is platinum which is sputteringly deposited at 215A and 215B. Finally, a platinum silicon compound or schottky or barrier is reactively formed as a schottky contact at a predetermined temperature for a predetermined time which in this embodiment is 550 degrees C for 15 minutes in the sputtering vacuum chamber at the same areas 215A-B. A chemical solution is then used that will etch off the unreacted platinum while the platinum silicon 215A-B is unaffected. In the seventh step as shown in Figure 4H, a second layer of metal interconnection which in this embodiment is aluminum is deposited and masked away over the platinum silicon schottky barrier 215A-B at 220A-B to leave a top metal of 220A-B. The passivation and contact-pad opening steps may be done afterwards as in a normal MOS-LSI process. The above process results in fabrication of high-speed, high density, low power LSI circuits with improved high gain MESFET devices using conventional lithographic techniques. The advantages thereof include much improved high device gain as a result of the eli mation of series resistances increased circuit integration density and improved speed capability due to the elimination of gate to source and gate to drain spacings and improved high device gain. Note that the silicon etching step may be done by using plasma dry etching process, KOH chemical etching solution or polysilicon etching solution. The starting silicon wafers may be of 100, 110, or 111 orientations. It will be noted that the supra self-aligned MESFET will also function in an equivalent manner if acceptors were to be used where donors are, and donors where acceptors are which is to say that the use of P or N material is equivalent as long as consistent with the above description.

Claims: Claims: 1. A method of making a self-aligned MESFET having a substrate (170) lightly doped with an acceptor (or donor) impurity, overlaid with relatively thin first and second areas (160A-B) alternating with areas of thick field oxide (155A-C), with a heavy donor (or acceptor) impurity (150A-C) introduced into the substrate below the areas of thick oxide for enhancement switch and depletion load devices, characterised by the steps of: : a) introducing a relatively shallow donor (or acceptor) impurity in the substrate (170) below the first and second thin oxide areas (160A-B) to define with graded profiles first and second light donor (or acceptor) areas (165A-B) therein; b) masking to expose only the second thin oxide area (160B) for a relatively deep donor (or acceptor) impurity introduction in the second light donor (or acceptor) area (165B) so that the depletion load device will be normally-on; c) layerThg of an etch #istant (185A-B) over the surface of the first and second thin oxide areas (160A-B) to form sandwich thereof, and masking away the thin oxide areas to expose the first and second light donor (or acceptor) areas (165A-B) except for narrowly defined first and second gate sandwiches (160A1-B1) defined to be over gate channel regions; ; d) etching away the exposed first and second light donor (or acceptor) areas to a predetermined depth (187A-D), and introducing a relatively heavy donor (or acceptor) impurity to define, within each of the light donor (or acceptor) areas (165A, 165B 1), first and second heavy donor (or acceptor) areas (190A-B, 195A-B) as source and drain regions; e) depositing polysilicon (200A-B, 205A-B) and etching away, through masking} all ou areas that are adjacent to a heavy donor (or acceptor, area and a thick oxide area, for defining source and drain ohmic contacts, and reoxidizing (210) over the polysilicon areas and part of first and second heavy donor (or acceptor) areas for inter-layer isolation; and f) etching away first and second gate sandwiches (160A1-B1, 185A-B) thereby exposing first and second light donor (or acceptor) areas (165A-B), and depositing schottky metal (215A-B) thereon for reaction into a schottky barrier for use as a schottky contact. 2. The method of Claim 1 including the additional step of depositing top metal over all exposed surfaces of the substrate, and masking away all of the top metal except that (220A-B) over the surface of the schottky contact for defining a gate electrode pattern. 3. The method of Claim 1 or Claim 2 wherein the masking of the second thin oxide area (step (b)) is through depletion masking. 4. The method of any one of Claims 1 to 3 wherein the etching used to form the drain and source regions (step (d)) is plasma etching. 5. The method of any one of Claims 1 to 4 wherein the masking used to define the deposited polysilicon (step (e)) is a polysilicon masking step. 6. The method of any one of Claims 1 to 5 wherein the metal used in the schottky metal depositing step (step (f)) is platinum and the reaction is between the platinum and silicon to form a compound thereof. 7. The method of Claim 6 including the additional step of removing unreacted schottky metal from the schottky metal and silicon compound. 8. A self-aligned MESFET having a light acceptor (or donor) impurity doped substrate (65) characterised in that it comprises: light donor (or acceptor) means (55) with a graded doping profile disposed over the substrate (65) for operation as a gate channel region; first and second heavy donor (or acceptor) means (50, 60) disposed over the substrate (65) and adjacently stepped down on either side of said light donor (or acceptor) means (55) for operation as source and drain regions; schottky contact means (35) disposed over said light donor (or acceptor) means (55) for operation as a schottky barrier; first and second ohmic contact means (25, 30) disposed over a predetermined portion of said first and second heavy donor (or acceptor) means (50, 60) for source and drain connections; and first and second oxide means (40, 45) disposed laterally between said schottky contact means (35) and each of said first and second ohmic contact means (25, 30), and disposed over a predetermined portion of said first and second heavy donor (or acceptor) means (50, 60) for inter-layer isolation relative to said light donor (or acceptor) means (55). 9. The self-aligned MESFET of Claim 8 wherein the graded doping profile of said light donor (or acceptor) means (55) has a concentration spatially directly proportional to the substrate surface.

Inventors: YEH, KEMING W.
Applicants: XEROX CORPORATION
Application year: 1979
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27