PROGRAMMABLE MODE OF OPERATION SELECT BY RESET AND DATA PROCESSOR USING THIS SELECT

Abstract: A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches (90, 92, 96) are coupled to terminals (6) normally used as an input/output port for the data processor and the latches are clocked with a signal (88) generated by a lever detector circuit (108) which senses the reset signal (98). The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode (100) from a terminal (6) of the input/output port to the reset terminal (98) of the data processor in order to program a low logic level into the corresponding mode detection latch.

Description: tr IrATTLE PROGRAMMABLE MODE SELECT BY RESET This invention relates generally to a data processor and more particularly to circuitry for selecting the mode of operation for a data processor. Applications for integrated circuit data processors are rapidly increasing. Various applications for these data processor devices may require varying configurations of the input-output circuitry associated with a data processor device. In order for a single data processor device to be employed within these varying applications, the input-output circuitry of a data processor must be flexible such that it can be programmed to satisfy the needs of any particular applications. One prior art approach for providing various configurations of the input-output circuitry for a data processor is to provide a plurality of mask options which vary the integrated circuit metal interconnections during processing such that a particular metal mask is used to provide an integrated circuit data processor of the desired configuration. However, this approach results in higher costs for processing, testing, and inventory control since each mask option results in a unique integrated circuit. Another prior art approach is to make the configuration of the processor device software programmable such that instructions are stored in a program memory which must be executed by the processor to achieve the desired configuration of the input-output circuitry for the data processor device. However, this approach increases the number of storage locations required for the program memory. A third prior art approach is to hardware-program the mode of operation by providing separate program selection inputs to the data processor for configuring the inputoutput circuit. This approach is also costly in that additional package pins are required for the integrated circuit device in order to determine the mode of operation. It is an object of the present invention to provide circuitry for selecting the mode of operation for a data processor while avoiding the need for mask options, additional software, or extra integrated circuit package pins. It is a further object of the present invention to provide circuitry which selects the mode of operation for a data processor whenever the data processor is powered-up or restarted. According to one aspect of the present invention there is provided a data processor of the type which includes storage elements for storing digital information, the data processor including reset circuitry (106) for receiving a reset signal, (98) the reset circuitry being responsive to the reset signal for causing the storage elements to store predetermined digital information and for initiating execution of instructions stored in a memory, the data processor also including input-output circuitry (2) having at least one terminal (6) for transmitting at least one digital signal, the at least one digital signal having first and second logic states characterized by: : mode selection circuitry (4,108) coupled to the at least one terminal (6) and being responsive to the reset signal for storing the logic state of the at least one digital signal immediately prior tó the initiation of execution of the instructions stored in the memory. According to a further aspect of the invention there is provided a circuit adapted for implementation within an integrated circuit data processor and suitable for selecting a mode of operation for the data processor, including a first terminal (98) for receiving a reset signal, the reset signal having a voltage ranging between a first and a second voltage level; and first circuitry (106) coupled to the first terminal and responsive to the reset signal for generating a control signal when the reset signal voltage reaches a first predetermined voltage, the control signal being operative to initialize the data processor; characterized by: a) a second terminal (6) capable of receiving a mode selection signal as a voltage, the mode selection signal having first and second logic states; and b) second circuitry (4,108) coupled to the first terminal and coupled to the second terminal, the second circuitry including a level detector for generating an output signal when the reset signal voltage equals a second predeterin voltage, and the second circuitry also including storage circuitry (90,92,96) responsive to the output signal for storing the logic state of the mode selection signal when the output signal is generated. In one embodiment of the invention there is provided a circuit adapted for implementation within an integrated circuit data processor, the circuit including a reset terminal for receiving a reset signal, circuitry responsive to the reset signal for causing initialization of the data processor, one or more input-output terminals which are generally used to transmit digital information to and from the data processor but receive one or more mode selection signals when the data processor is being reset, a level detector responsive to the reset signal which generates an output signal when the reset voltage reaches a predetermined level, and storage circuitry adapted for storing the one or more mode selection signals when the level detector generates the output signal. In the preferred embodiment, level shifting circuitry is included which shifts the voltage level of the mode selection signal such that the mode selection signal may be generated by either connecting a diode between the input-output terminal and the reset terminal for causing a mode selection signal to assume a first logic state or omitting the diode and causing the mode selection signal to assume the second logic state. The invention will now be described by way of example only with particular reference to the accompanying drawings wherein: Fig. 1 is a circuit schematic including a block of circuitry conventionally associated with an input-output pin of a data processor together with a block of circuitry for storing a mode selection signal; Fig. 2 is a circuit schematic of circuitry associated with the reset terminal including a block of circuitry for generating a control signal to initialize the data processor, a block of circuitry used to implement the mode selection feature, and a bias chain block; Fig. 3 illustrates timing waveforms for various signals generated by the circuitry shown in Figs. 1 and 2 and Fig. 4 is a block diagram illustrating an application of the mode selection circuitry for selecting the configuration of a data processor. Fig. 1 is a circuit schematic of circuitry associated with an input-output terminal of a data processor including conventional input-output circuitry within dashed block 2 and mode selection circuitry within dashed block 4. Inputoutput terminal 6 is coupled to node 8, and node 8 is coupled to node 10 by resistor 12. MOSFET device 14 has its drain coupled to node 10 while the gate and source are coupled to ground potential. Since the operation of MOSFETs (metaloxide-semiconductor field-effect transistors) is well-known by those skilled in the art, it will not be described in further detail herein. For an explanation of the operation of MOSFETs, see "Physics and Technology of Semiconductor Devices" by A.S. Grove, John Wiley and Sons, Inc., 1967. MOSFET device 14 serves as an input protection device so as to prevent the potential at node 10 from becoming so negative as to cause damage to other devices within the circuit. Node 10 is coupled to the input of inverter 16 which has an output coupled to one terminal of MOSFET device 18. The gate terminal of MOSFET 18 is coupled to control signal R102 such that MOSFET 18 is conductive when control signal R102 is at a high level. A third terminal of MOSFET 18 is coupled to the input of inverter 20. The output of inverter 20 is coupled to PDBO conductor 22 by MOSFET 24. The gate terminal of NOSFET 24 is coupled to conductor 26 which conducts a control signal R102 such that MOSFET 24 is conductive when R102 is at a high level. Conductor 22 corresponds to the least significant bit of a data bus within the data processor in the preferred embodiment of the invention. PDBO conductor 22 may be used to transfer digital information between input/output circuitry block 2 and working registers (not shown) within the data processor. In order to transfer digital information from input/output pin 6 to PDBO conductor 22, control signal R102 is initially at a high level while control signal R102 is initially at a low level. The signal received by input/output pin 6 is coupled to the input of inverter 16 by resistor 12, and the inverted output signal is coupled to the input of inverter 20 by MOSFET 18. Subsequently, control signal R102 switches to a low level while control signal R102 switches to a high level such that MOSFET 18 turns off while MOSFET 24 becomes conductive. The inverted signal initially coupled to the input of inverter 20 by MOSFET 18 is dynamically stored on the input of inverter 20 after MOSFET 18 is turned off. The output of inverter 20 is then coupled by MOSFET 24 to PDBO conductor 22 in order to complete the transfer of the digital information to the internal data bus. PDBO conductor 22 is also coupled to the input of inverter 28 by MOSFET 30. The gate terminal of MOSFET 30 is coupled to conductor 32 which conducts control signals #1P2 such that MOSFET 30 is conductive when AS2 is at a high level. The output of inverter 28 is coupled to node 34 by MOSFET 36 and is also coupled to node 38 by MOSFET 40. The gate terminal of MOSFET 36 is coupled to conductor 42 which conducts control signal W102 such that MOSFET 36 is conductive when W102 is at a high level. The gate terminal of MOSFET 40 is coupled to conductor 44 which conducts control signal DDR2 such that MOSFET 40 is conductive when DDR2 is at a high level. Node 34 is coupled to the input of inverter 46 which has an output coupled to the input of inverter 48 and to a first input of NOR gate 50. The output of inverter 48 is coupled to node 34 by MOSFET 52 which has its gate terminal coupled to positive supply voltage VDD. Inverter 46, inverter 48, and MOSFET 52 form a feedback latching circuit. Node 38 is coupled to a first input of NOR gate 54 while the second input of gate 54 is coupled to conductor 56 which conducts control signal RESET. The output of gate 54 is coupled to the input of inverter 58 which has an output coupled to node 60. Node 60 is coupled to node 38 by MOSFET 62 which has a gate terminal coupled to the positive supply voltage VDD. NOR gate 54, inverter 58, and MOSFET 62 form a feedback latching circuit which may be a portion of a data direction register as will be explained later. Node 60 is coupled to the second input of gate 50 and is also coupled to a first input of NOR gate 64. The output of gate 50 is coupled to the second input of gate 64 and to the gate terminal of MOSFET 66. The source of MOSFET 66 is coupled to ground potential while the drain of MOSFET 66 is coupled to node 8. The output of gate 64 is coupled to the gate terminal of enhancement mode MOSFET 68 which has its drain terminal coupled to the positive supply voltage VDD and its source coupled to node 8. A depletion mode MOSFET 70 has a drain terminal coupled to the positive supply voltage VDD while its gate and source terminals are coupled to node 8. When input/output pin 6 is to function in the input mode, then MOSFET 66 and MOSFET 68 are turned off such that node 8 is allowed to appear as a high impedance. When node 60 is at a high level or logic "1", then gate 64 and gate 50 both output a low level such that MOSFET devices 66 and 68 are cut off. When the data processor is first powered-up or when the RESET input pin 98 is strobed, the RESET control signal coupled to conductor 56 assumes a logic "1" level which causes the data direction register latch formed by gates 54, 8 and MOSFET 62 to store a logic "1" on node 60. Thereafter, in order to allow input/output pin 6 to function as an output, the data direction register must be caused to store a logic "O" on node 60. This may be accomplised by providing a logic "1" level on conductor 22 and enabling MOSFET 30 and MOSFET 40 by causing control signal WP2 and control signal DDR2 to be at a high level. Once the data direction register is programmed for the output mode, the logic state of input/output pin 6 is determined by the logic state stored by the latch formed by gates 46, 48 and MOSFET 52. The logic state on PDBO conductor 22 will be copied into the latch by enabling MOSPETs 30 and 36 by forcing control signal WP2 and W102 to a high level. The decoder circuitry for generating the various control signals is conventional and will not be described herein. Node 10 is also coupled to enhancement mode MOSFET 72 within dashed block 4. The drain of MOSFET 72 is coupled to the positive supply voltage VDD and the source is coupled to node 74. Node 74 is coupled to the input of inverter 76 and is also coupled to the drain of MOSFET 78. The source of MOSFET 78 is coupled to ground potential while the gate terminal is coupled to conductor 80 which conducts a bias voltage which will be later discussed with reference to Fig. 2. MOSFET 72 acts as a level shifter or source-follower while MOSFET 78 acts as a current source. The output of inverter 76 is coupled to the input of inverter 82. The output of inverter 82 is coupled to node 84 by MOSFET 86. The gate terminal of MOSFET 86 is coupled to conductor 88 which conducts a control signal VMODL which will be later discussed with reference to Fig. 2. Node 84 is coupled to the input of inverter 90, and the output of inverter 90 is coupled to the input of inverter 92. The output of inverter 92 is coupled to node 94, and node 94 is coupled to node 84 by feedback MOSFET 96. The gate terming of MOSFET 96 is coupled to the positive supply voltage VDD such that inverter 90, inverter 92, and MOSFET 96 form a feedback latching circuit. The logic state stored by the latching circuit can be initialized by causing control signal VMODL to be a high level such that MOSFET 86 is made conductive. At such time, the voltage at input/output pin 6 will determine the logic state stored by the latching circuit. As will be later explained, the mode programming latch¯ register formed by inverter 90, inverter 92 and MOSFST 96 is initialized when the data processor is reset. Showr in Fig. 1 is RESET input pin 98 and a diode 100 having its anode coupled to input/output pin 6 and its cathode coupled to RESET pin 98. Diode 100 would be included if it is desired to store a logic "O" in the mode programming latcl register. In this event, when RESET pin 98 goes to a low level in order to reset the data processor, then diode 130 pulls pin 6 to within .7 volt of a low logic level. Level shifting MOSFET 72 translates the voltage on pin 6 Dy one MOSFET threshold drop to a more negative voltare such that the input of inverter 76 recognizes the vltage on pin 6 as a low level. If it is desired for th mode programming latch register to latch a logic "1" level, then diode 100 is omitted and depletion mode pullup MOSFET 70 establishes a high level on pin 6. In the preferred embodiment, the output of mode programming latch register node 94 is coupled to decoder circuitry for controlling the configuration of the data processor circuit. Also, the output of mode programming latch register node 94 is coupled to PDB5 conductor 102 by MOSFET 104 such that the status of the mode programming latch register can be accessed by the internal data bus of the data processor. The gate terminal of MOSFET 104 is coupled to conductor 26 such that MOSFET 104 is conductive when control signal R102 is at a high level. In Fig. 2, circuitry for generating a reset signal to initialize the data processor is shown within block 106. Within block 108, circuitry is shown for generating the control signal VMODL already referred to within Fig. 1. Also within dashed block 110, bias circuitry is shown for generating various bias points. RESET input pin 98 is coupled to node 112 by input resistor 114. Node 112 is coupled to the gate and source terminals of enhancement mode MOSFET 116 which has its drain terminal coupled to the positive supply voltage VDD. Node 112 is also coupled to the drain terminal of enhancement mode MOSFET 118 which has its gate and source terminals coupled to ground potential. MOSFETs 116 and 118 are input protection devices and serve to limit the magnitude of the voltage on node 112 so as to protect other MOSFET devices coupled to this node. Node 112 is coupled to the gate terminal of MOSFET 120 which has its drain terminal coupled to node 122 and its source terminal coupled to node 124. Node 124 is coupled to the source terminal of depletion mode MOSFET 126 and to the drain terminal of MOSFET 128. MOSFET 128 has its gate terminal coupled to the positive supply voltage VDD and its source terminal coupled to ground potential such that OSFET 128 functions as a current source. MOSFET 126 has its drain coupled to the positive supply voltage VDD and its gate terminal coupled to node 122. Node 122 is also coupled to the source and gate terminals of depletion mode MOSFET 130 which has its drain terminal coupled to the source terminal of enhancement mode MOSFET 132. The gate and drain terminals of MOSFET 132 are coupled to the positive supply voltage VDD. MOSFET 120 and 126' form a differential amplifier connected as a Schmidt trigger circuit. The voltage on the gate terminal of MOSFET 126 varies as the drain current from MOSFET 128 is switched between MOSFET 120 and MOSFET 126 so as to provide hysteresis. Node 122 is also coupled to the input of inverter 134, which has an output coupled to the input of inverter 136. The output of inverter 136 is coupled to terminal 137 by conductor 138. Terminal 137 may be coupled to synchronization circuitry (not shown) such that the asynchronous reset signal provided by terminal 137 may by sychronized with clock signals generated within the data processor to provide a synchronized RESET signal. The synchronized RESET signal may then be used to clear the registers within the data processor and to initiate execution of instruction stored in the program memory. As shown in Fig. 1, the synchronized RESET signal may also be used to initialize the data direction register which controls input/output circuitry. Node 112 is also coupled to the gate terminal of MOSFET 140 within dashed block 108. The source terminal of MOSFET 140 is coupled to the source terminal of l,OSFET 142 and to the drain terminal of IOSFET 144. The gate terminal of l;CSF¯T 144 is coupled to conductor 80 which provides a first bias voltage VREIAS. The source of 1 FET 144 is coupled to ground potential such that IrOSFET 144 functions as a current source. The gate terminal of MOSFET 142 is coupled to conductor 146 which provides a second bias voltage. MOSFET 140 and ;;CSFED 142 function as a differential comparator circuit for comparing the voltage on node 112 to the bias voltage provided by conductor 145. The drain of FiOSFET 140 is coupled to the source terminal of enhancement mode t;OSFET 148 which has its gate and drain terminals coupled to the positive supply voltage VDD such that MOSFET 148 functions as a load impedance. The drain of MOSFET 140 is also coupled to the gate terminal of MOSFET 150. The drain terminal of MOSFET 142 is coupled to the source terminal of enhancement mode MOSFET 152 which has its gate and drain terminals coupled to the positive supply voltate VDD. The drain terminal of MOSFET 142 is also coupled to the gate terminal of MOSFET 154. MOSFET 154 has its drain terminal coupled to the positive supply voltage VDD, and its source terminal is coupled to the gate and drain terminals of OET 156 as well as to the gate terminal of MOSFET 158. The source terminal of MOSFET 156 and the source terminal of MOsFET 158 are coupled to ground potential such that OSFET 156 and MOSFET 158 form a current mirror arrangement. The drain terminal of MOSFET 158 is coupled to the source of MOSFET 150 and to the input of inverter 160. The drain of MOSFET 150 is coupled to the positive supply voltage VDD. The output of inverter 160 is coupled to the input of inverter 162, and the output of inverter 162 is coupled to conductor 88 for providing the control signal VNODL. Within block 110 is a bias chain formed by a plurality of series connected MOSFET devices coupled between positive supply terminal VDD and ground. MOSFET 164 has its gate and drain terminals coupled to the positive supply voltage VDD, wnile the source terminal of tOSFET 164 is coupled to the gate and drain terminals of MOSFET 166. The source of L'OSFDT 166 is coupled to conductor 80 for providing bias voltage VRSIAS. The source of I;GsFET 166 is also coupled to the gate and drain terminals of NOSFET 168, and the source of MOSFET 168 is coupled to conductor 146 for providing a second bias voltage. The source of NOSFET 16S is also coupled to the gate and drain terminals of MOSFET 170 and the source of i#O#FET 170 is coupled to ground potential. The comparator circuit or level detector shown within dashed block 108 functions in the following manner. If the voltage on RESET pin 98 is less than the bias voltage provided by conductor 146, then MOSFET 140 will be non-conductive, while the drain terminal of MOSFET 142 will conduct the current provided by FET 144. The current conducted by MOSFET 142 pulls the source of l'iOSFE' 152 to a low level, thereby cutting off COSFET 154. The source terminal of MOSFET 148 pulls the gate of SET 150 to a high level, thereby allowing MC-RET 150 to conduct. Since MOSFET 154 is non-conductive, no bias current is provided to MOSFET 156, and OSFT 158 is non-conductive. Thus, the input to inverter 150 is a high level. however, when the voltage on the RESET input pin 98 rises above the bias voltage on conductor 146, MOSFET 140 is conductive and MCSFET 142 is non-conductive. In this case, the gate terminal of YOSFET 150 is pulled down to a low level, while the gate terminal of OSFST 154 is pulled up to a high level. MOSFET 156 is made conductive by the current supplied by MOSFET 154, and MOSFET 158 is made conductive by the gate to source voltage developed across tOSFET 156. The input to inverter 160 is now a low level. In Fig. 3, timing waveforms are shown for the voltage at the RESET input pin as well as voltages for other points in the circuit. Two cases are shown for the RESET input voltage. In the first case, an input pulse with relatively fast rising and falling edges is shown which may correspond to the voltage produced by the output of a TTI (transistortransistor logic) logic circuit. In the second case, a slowly rising inrut voltage is shown which may correspond to the voltage produced on the RESET input pin when this input pin is coupled to the positive supply voltage VDD by an appropriate XC network. Such a connection might be desired to automatically reset the data processor whenever the data processor is initially coupled to the power supply voltage. As the RESET input pin voltage rises, the Schmidt trigger circuit shown within dashed block 106 (Fig. 2) will switch when the input voltage reaches a predetermined voltage. In Fig. 3, this predetermined voltage (VRR) is roughly 3.3 volts in the preferred embodiment. The waveform labeled RESET in Fig. 3 shows the voltage provided by terminal 137 in the Schmidt trigger circuitry of Fig. 2, and it will be noted that this voltage switches to a low level when the RESET input voltage reaches the VRR Prior to the time that the RESET input voltage reaches VRR, the input/output circuitry associated with pin 6 (Fig. 1) is forced to be in the input mode. However, once the RESET input voltage surpasses V. the software instructions executed by the data processor may change the input/output circuitry associated with pin 6 to select the output mode of operation. Thus, it is necessary to latch the logic state on pin 6 into the mode programming latch register before the data processor begins execution of the restart software routine. The level detector circuit within dashed block 108 of Fig. 2 functions to latch the mode programming latch register prior to the time that the data processor reset signal VREJET switches to a low level. The waveform labelled VMODL shows the voltage produced on conductor 88 by the level detector circuitry within dashed block 108 in Fig. 2. The bias voltage provided by conductor 146 is selected such that VMODL switches to a low level when the RESET input voltage reaches voltage VRL which, in the preferred embodiment, is roughly 1 volt. When VI50DL switches to a low level, the input to the mode programming latch register is disabled such that the mode of operation is selected before the restart software routine can alter innut/output pin 6 to assume the output mode of operation. As previously mentioned, one method of programming input/output pin 6 to be a low level during mode selection is to connect a diode from pin 6 to the RESET input pin 98. This feature imposes the constraint that the mode programming latch register must latch the low logic level on pin 6 before the RESET input voltage rises sufficiently positive to make the voltage on pin 6 approach a high logic level. The waveform labeled VpGM in Fig. 3 corresponds to the voltage output by inverter 82 in Fig. 1 assuming that a diode has been connected as suggested. In this case, the level shifting circuitry formed by MOSFET 72 and MOSFET 78 in Fig. 1 is selected such that the VpGM voltage does not switch to a high level until the RESET input voltage has reached VRp which, in the preferred embodiment, is roughly 2.8 volts. Since VMODL switches to a low level prior to the time that VPGM switches to a high level, the mode programming latch register properly latches a low logic level. Fig. 4 is a block diagram illustrating an application of the preferred embodiment of the invention. A plurality of input/output circuit blocks 172, 174, 176, and 178 are coupled to a plurality of input/output terminals 180, 182, 184, and 186 respectively. Input/output blocks 172, 174, 176, and 178 are coupled to conductors 188, 190, 192 and 194, respectively, which form an internal digital bus within the data processor. Three mode programming latches 196, 198, and 200 are coupled to terminals 180, 182, and 184 in order to form a three bit mode programming latch register. The output of the mode programming latch register is coupled to a mode select decode block 202 by conductors 204, 206 and 208. Mode select decode block 202 decodes one of eight possible modes of operation and generates a plurality of control signals for configuring the data processor into the selected mode. However, those skilled in the art will realize that mode select decode block 202 may also be used to control various other functions within a data processor such as modifying the instruction set of a data processor by controlling the decoding of instructions in the data processor instruction register.

Claims: Claims 1. A data processor of the type which includes storage elements for storing digital information, the data processor including reset circuitry (106) for receiving a reset signal (98), the reset circuitry being responsive to the reset signal for causing the storage elements to store predetermined digital information and for initiating execution of instructions stored in a memory, the data processor also including input/output circuitry (2) having at least one terminal (6) for transmitting at least one digital signal, the at least one digital signal having first and second logic states, characterized by: mode selection circuitry (4,108) coupled to the at least one terminal (6) and being responsive to the reset signal for storing the logic state of the at least one digital signal immediately prior to the initiation of execution of the instructions stored in the memory. 2. A data processor as claimed in claim 1 wherein the mode selection circuitry is characterized by at least one latch circuit (90, 92, 96) coupled to the at least one terminal and being suitable for storing a logic state. 3. A data processor as claimed in claim 2 wherein the mode selection circuitry is further characterized by a voltage level detector (108) coupled to the reset circuitry and responsive to the reset signal for detecting the receipt of the reset signal and for selectively coupling the latch circuit to the at least one terminal when the receipt of the reset signal is detected such that the latch circuit is caused to store the logic state of the at least one digital signal. 4. A circuit adapted for implementation within an integrated circuit data processor and suitable for selecting a mode of operation for the data processor, including; a first terminal (98) for receiving a reset signal, the reset signal having a voltage ranging between a first and a second voltage level; and first circuitry (106) coupled to the first terminal and responsive to the reset signal for generating a control signal when the reset signal voltage reaches a first predetermined voltage, the control signal being operative to initialize the data processor; characterized by: a) a second terminal (6) capable of receiving a mode selection signal as a voltage, the mode selection signal having first and second logic states; and b) second circuitry (4,108) coupled to the first terminal and coupled to the second terminal, the second circuitry including a level detector for generating an output signal when the reset signal voltage equals a second predetermined voltage, and the second circuitry also including storage circuitry (90, 92, 96) responsive to the output signal for storing the logic state of the mode selection signal when the output signal is generated. 5. A circuit as claimed in claim 4 characterized in that the second terminal is adapted for transmitting digital information between the data processor and external circuitry. 6. A circuit as claimed in claim 5 characterized in that the first and second predetermined voltages are selected such that the output signal is generated before the control signal is generated during transitions of the reset signal from the first to the second voltage level. 7. A circuit as claimed in claim 6 wherein the level detector is characterized by a differential amplifier and a source of a reference voltage, (146),the differential amplifier including first and second MOSFET devices (140, 142) each having at least a source terminal and a gate terminal, the gate terminal of the first flOSFET device (140) being coupled to the first terminal, the gate terminal of the second MOSFET device being coupled to the source of the reference voltage, and the source terminals of the first and second MOSFET devices being coupled in common with each other. 8. A circuit as claimed in claim 7 characterized in that the reference voltage is substantially equal to the second predetermined voltage. 9. A circuit as claimed in claim 5 characterized in that the second circuitry further includes level-shifting circuitry (72, 78) coupled to the second terminal for generating a shifted selection signal having a voltage which is offset from the voltage of the mode selection signal, and circuitry (86) for selectively coupling the shifted selection signal to the storage circuitry. 10. A circuit as claimed in claim 9 further characterized by a diode (100) coupled between the first and second terminals for causing the logic state of the mode selection signal to correspond to the voltage of the reset signal.

Inventors: SHAW, PERN, TIETJEN, DONALD LOUIS, WILES, MICHAEL FREDERICK
Applicants: MOTOROLA, INC.
Application year: 1979
Main classification: G06F1
IPC codes: G06F9, G06F7, G06F15, G06F1