CIRCUIT FOR CONTROLLING A RECEIVING FREQUENCY AND A CHANNEL DISPLAY IN A SUPERHETERODYNE RECEIVER

Abstract: A superheterodyne receiver employs as a local oscillator a VCO (125) included in a PLL (115). Upon depression of a station selecting switch (200), a pulse is generated and counted by a trinary counter (311) and two decimal counters (313, 315). The count value in the trinary counter is deter­ mined to indicate the channel index. The count value in the two decimal counters is subjected to the first addition (320) of "2" and the sum thereof is indicated as channel number data, while the same is subjected to multiplication (321) by 3 and the product thereof is subjected to the second addition (323) of a numerical value corresponding to the lowest channel frequency, whereupon the sum thereof is added in the third addition (327) to the count value in the trinary counter and the sum thereof is set in the PLL, while the same is indicated as the receiving frequency.

Description: Superheterodyne Receiver The present invention relates to a superheterodyne receiver. More specifically, the present invention relates to a superheterodyne receiver employing as a local oscillator a voltage controlled oscillator included in a phase locked loop, adapted to indicate a channel number and a channel index of a receiving channel. Recently an electronic tuning apparatus has been employed in place of mechanical tuning apparatus in a superheterodyne receiver. Such an electronic tuner usually employs a voltage controlled oscillator as a local oscillator. A phase locked loop including a voltage controlled oscillator has also been developed and such a voltage controlled oscillator has also been employed as a local oscillator of a superheterodyne receiver. A digital frequency display has also been proposed which displays in a digital manner the frequency of a broadcasting station now in reception by the use of the digital data based on the data available in a phase locked loop. Typically such a digital frequency indication is made by the use of the numerals of four digits. In spite of the fact that the frequency of a broadcasting station now in reception is displayed with accuracy by a digital frequency display, a problem is encountered by a user that it in often difficult for him to correctly memorize the frequencies of a large number of broadcasting stations. In order to avoid such difficulty, it has been proposed that in a given frequency band, such as an FM band, channel numbers are allotted to the respective broadcasting stations so that a desired broadcasting station can be identified by a corresponding channel number of a decreased number of digits. On the other hand, historically in Europe a broadcasting standard was employed in the FM band until before 1962 in which 56 broadcasting frequencies were determined with the interval frequency of 300 kHz between two adjacent broadcasting frequencies. However, thereafter the standard was revised to a new one in which 168 FM broadcasting frequencies were determined with the interval frequency of 100 kRz between two adjacent broadcasting frequencies. Particularly, the broadcasting frequencies allotted after 1962 were additionally allotted such that two additional broadcasting frequencies come in the vicinity of the broadcasting frequency allotted before 1962. Therefore, one of the broadcasting frequencies allotted after 1962 is 100 kRz lower than the broadcasting frequency allotted before 1962 and the other of the broadcasting frequency allotted after 1962 is 100 kHz higher.than the broadcasting frequency allotted before 1962. Nevertheless, as far as the channel number indication is concerned, the broadcasting frequencies allotted after 1962 have been identified by the channel numbers asscociated with the channel allotted before 1962, but with an additional channel index. For example, the broadcasting frequency of 93.3. NRz 0 is identified as Channel No. 21 or Channel No. 21 in the above described channel indication, wherein the notation "O" indicates that the broadcasting frequency of 93.3 MHz is a broadcasting frequency allotted before 1962. On the other hand, the frequency of 93.2 MHz is identified as Channel No. 21 , wherein the notation "-' indicates that the channel of the frequency 93.2 NHz was allotted after 1962 and is of the frequency 100 kHz lower than that of the channel of the same channel number allotted before 1962. The frequency of 93.4 z is identified as Channel No. 21+, wherein the notation " indicates that the channel was allotted after 1962 and is of the frequency 100 kHz higher than the frequency of tbe channel of the same channel number allotted before 1962. Therefore, according to the channel number indication with the additional channel indexes, a digital indication of the channel number need be followed by an additional indication of the channel indexes such as "-n and "+. A prior art apparatus of interest for indicating both the channel number and the channel index to correctly identify the channel of a given broadcasting station is seen in German patent application, Serial No. P 2362853.7, filed December 18, 1973 and British patent application, Serial No. 33212/1977, filed August 8, 1977. The apparatus disclosed in the above referenced German patent application, Serial No. 2362853.7 is structured such that a local oscillation frequency is counted and a channel number is evaluated based on the count value, whereby the channel number is displayed in a digital manner, while the channel index is simultaneously displayed. On the other hand, the apparatus disclosed in the above referenced British patent application, Serial No. 33212/1977 is structured such that a local oscillation frequency is counted and a corresponding one of light emitting diodes disposed in a line associated with the channel numbers is selectively lighted, while the channel index is also displayed. The apparatuses disclosed in both the above referenced applications are structured such that the local oscillations frequency is counted for a predetermined time period, whereupon the receiving frequency is evaluated, while the channel number is further evaluated from the receiving frequency and the channel number is thus displayed. According to the present invention, a channel number is displayed based on the data set in a channel number setting means, and the local oscillation frequency is then controlled based on the data of the channel number as set such that the broadcasting frequency of the channel number as set in the channel number setting means is received. In a preferred embodiment of the present invention, the channel number is eet by performing an arithmetic operation with respect to a channel mumber associated numerical value as set and a given specified numerical value. The above described specified numerical value is selected such that when the local oscillation frequency is controlled based on the set channel number associated numerical value the broadcasting frequencies of one or more channels at one or the other extremity of the receiving frequency band cannot be selected or received. Accordingly, such channels, for example, Channel No. 0 and Channel No. 1, allotted to the police wireless communication reception of which by the general public is not very much desired can be readily rendered unreceivable. On the other hand, according to the prior art disclosed in the above referenced two patent applications, in order to render unreceivable such channels reception of which by the general public is not desired, it was necessary to select the values of various components of a local oscillator, for example, 8o that the frequency of the local oscilla tor does not becomes lower or higher than a predetermined frequency value. By contrast, according to a preferred embodiment of the present invention, only the channel numbers, i.e. those channel numbers exceeding Channel No. 2, excluding Channel Nos. 0 and 1, can only be set, so that the broadcasting frequencies corresponding to only the channels of the channel numbers exceeding Channel No. 2 can be rendered receivable. According to a preferred embodiment of the present invention, a voltage controlled oscillator included in a phase locked loop is employed as a local oscillator. A programmable frequency divider connected to receive the output of the voltage controlled oscillator is provided in the phase locked loop. In case of an electronic tuner employing such a frequency synthesizer, the local oscillation frequency or the oscillation frequency of the voltage controlled oscillator can be adjusted by simply setting a frequency division ratio corresponding to the broadcasting frequency of a desired channel in the above described programmable frequency divider. In a preferred embodiment of the present invention, the data as obtained by performing a prescribed arithmetic operation with respect to channel number data as set in a channel number setting means is utilized as a frequency division ratio to be set in the programmable frequency divider. Accordingly, a prior art superheterodyne receiver employing a frequency synthesizer including a conventional phase locked loop has required a specific scheme such as a memory for setting a frequency division ratio to be set in the programmable frequency divider. According to a preferred embodiment of the present invention, however, such a specific memory can be dispensed with for that purpose and in this context the present invention is particularly advantageous in a superheterodyne receiver employing a frequency synthesizer. According to a further preferred embodiment of the present invention, a receiving frequency received by a superheterodyne receiver is displayed in a digital manner. Conventionally, a tuning state to a receiving frequency was first established and then a digital indication of the receiving frequency was made by counting the oscillation frequency of the local oscillator. By contrast, according to a preferred embodiment of the present invention, channel number data is first set in a channel number setting means and a prescribed arithmetic operation is performed based on the channel number data as set so that data associated with the receiving frequency is obtained, whereupon a receiving state is established and the receiving frequency is displayed in a digital manner Therefore, according to the embodiment of the present invention, any specific counter for counting the local oscillation frequency signal can be dispensed with, while complicated control therefor is neither required. Furthermore, in displaying the receiving frequency in a digital manner, both the channel number and the receiving frequency can be displayed switchably and selectively by means of a common display. In displaying both the channel number and the receiving frequency by the use of a common display as described previously, a decimal point indicating means for use in indication of the receiving frequency and a channel index indicating means for use in indicating the channel number can be commonly connected to the same line, while the indicating timings are selected to be different. As a result, an additional display control required for the channel index indicating means can be simply performed. Accordingly, a principal object of the present invention is to provide a superheterodyne receiver, wherein channel number data is set and a local oscillation frequency is controlled based on the channel number data as set, while a novel channel number display scheme for displaying the channel numbers ia provided. Fig. 1 is a block diagram showing one embodiment of the present invention; Fig. ld is a block diagram showing another embodiment of the present invention, wherein the control circuit 300 is implemented by a microcomputer Fig. 2 is a flow diagram for explaining the operation of the present invention; Fig. 3 is a schematic diagram showing in more detail the major portion of another embodiment of the present invention; Fig. 4 is a graph showing waveforms of timing signals in case of the Fig. 3 embodiment; and Fig. 5 is a graph showing waveforms of various signals for explaining the operation of the Fig. 3 embodiment. Fig. 1 is a block diagram showing one embodiment of the present invention. A high frequency signal received by an antenna 101 is amplified by a high frequency amplifier 103 and the output therefrom is applied to a mixer 105. The mixer 105 is connected to receive as a local oscillation signal the oscillation output obtained from a voltage controlled oscillator 125 included in a phase locked loop 115. Accordingly, in the mixer 105 the high frequency signal thus amplified is mixed with the local oscillation signal obtained from the voltage controlled oscillator to be converted into an intermediate frequency signal, which is then applied to an intermediate frequency amplifier 107. The output of the intermediate frequency amplifier 107 is detected by a detector 109 and a low frequency signal or an audio signal thus obtained is applied to a low frequency amplifier 111. The low frequency amplifier drives a speaker 113 in association with the audio signal applied thereto. An FM band radio receiver 100 is thus structured. The phase locked loop 115 comprises a reference oscillator 117. The reference oscillator 117 comprises a crystal, for example, the output of which is applied to a phase comparator 119. The phase oomparator 119 is further connected to receive at the other input thereto the output of a probrammable frequency divider 123 connected to receive the oscillator output of the voltage controlled oscillator 125. Accordingly, the phase oomparator 119 serves to compare the phases of the signal obtained from the reference oscillator 117 and the signal obtained from the programmable frequency divider 123, thereby to provide a voltage signal associated with the phase difference therebetween, which is applied through a low pass filter 121 to the above described voltage controlled oscillator 125 as a control voltage. The data to be set in the programmable frequency divider 123 as a frequency division ratio is obtained from an addition circuit 327 included in a control circuit 300. The control circuit 303 is connected to an upward switch 201 for commanding an upward automatic scanning and a downward switch 203 for commanding a downward automatic scanning included in a station selecting switch group 200 and is also connected to a channel display 400 and a receiving frequency display 500. The upward switch 201 and the downward switch 203 are structured to provide a signal of the high level or the logic one upon depression or operation thereof. The signal obtained from the upward switch 201 and the signal obtained from the downward switch 203 are applied to an OR gate 301 included in the control circuit 300 and is also applied to the set input and the reset input of a flipflop 307, respectively. The output of the OR gate 301 is applied to the set input of'a flip-flop 303. The reset input of the flip-flop 303 is connected to receive a signal representative of a tuning state by the above described radio receiver 100 obtained from the intermediate frequency amplifier 107 thereof. Accordingly, the flip-flp 303 is set responsive to operation of either the upward switch 201 or the downward switch 203 and is reset responsive to the signal representative of a tuning state by the radio receiver 100. The non-inverted output of the flip-flop 303 is applied to one input of an AND gate 309. The other input of the AND gate 309 is connected to receive a pulse obtained from a pulse generator 305. The pulse generator 305 may comprise an astable multivibrator, for example, the output pulse of which is applied to the AND gate 309. The pulse obtained through the iND gate 309 from the pulse generator 305 serves as a station selecting pulse and is applied to a count input of a trinary counter 311. A count up or carry signal of the trinary counter 311 is applied to a count input of a decimal counter 313 and the count up or carry output of the decimal counter 313 is applied to a decimal counter 315 as a count input. These counters 311, 313 and 315 are each structured as an up/down counter and, in order to command each of these as an up count mode or a down count mode, the non-inverted output of the above described flip-flop 307 is applied to these counters 311, 312 and 315. More specifically, if and when the non-inverted output of the flip-flop 307 is the high level or the logic one, these counters 3n1, 313 and 315 operate in än up count mode and, if and when the non-inverted output of the flip-flop 307 is the low level or the logic zerot these counters 311, 313 and 315 operate in a down count mode. The count value in the trinary counter 311 is applied to a numerical value determining circuit 317 in a bit parallel fashion. The numerical value determining circuit 317 determines the channel index responsive to the count value in the trinary counter 311. More specifically, if and when the numerical value in the trinary counter 311 is "O", the numerical value determining circuit 317 determines the numerical value as the channel index "-n, and if and when the count value in the trinary counter 311 is "2" the numerical value determining circuit 317 determines the numerical value as the channel index "+". The determined output of the numerical value determining circuit 317 is applied to the channel index display 401 of the channel display 400, with the result that either of the indexes 401 and 401 of the channel index display portion 401 is driven to display the same or neither is driven. The count values in the two decimal counters 313 and 315 are applied to an addition circuit 320 in a bit parallel fashion, respectively. The other input of the addition circuit 320 is connected to receive in a bit parallel fashion a code signal representative of a specified numerical value, "2" as preset in a specified number setting circuit 319. The numerical value "2' set in the specified number setting circuit 319 is selected to render the Channel Nos. 0 , 0, 0+, 1-, 1, and 1+ at the lower extremity of the FM band unreceivable. The output of the addition circuit 320, i.e. the sum obtained by addition of the numerical values in the decimal counters 313 and 315 and the above described specified numerical value "2", is applied to a channel number display portion 403 of the channel display 400 as channel number data. Simultaneously, the channel number data obtained from the addition circuit 320 is applied to a multiplication circuit 321. The multiplication circuit 321 serves to multiply the channel number data thus obtained by the number "3". The channel number data i8 multiplied by 3 by the multiplication circuit 321, because the broadcasting frequencies of three independent channels habe been allotted to each one channel number as described previously. The result or the product of the above described multiplication by the multiplication circuit 321 is applied to an addition circuit 323. The other input of the addition circuit 323 is connected to receive the date "869" associated with the lowest frequency obtained from a lowest frequency data setting circuit 325. The lowest frequency data is determined in consideration of the fact that the Channel No. O of the FM band is 86.9 MHz. The result or sum of the addition of the addition circuit 323 is further applied to an addition circuit 327. The other input of the addition circuit 327 is connected to receive the count value in the above described trinary counter 311. The addition circuit 327 serves to make addition of these two inputs to provide as the output therefrom date associated with receiving frequency. The receiving frequency associated data obtained from the addition circuit 327 is set, as a frequency division ration, in the programmable frequency divider 123 included in the above described phase locked loop 115 and is also applied to a frequency display 500 to display the receiving frequency. Meanwhile, in case of a lower side superheterodyne receiver, the local oscillation frequency is lower than the receiving frequency by a frequency difference commensurate with the intermediate frequency and therefore the programmable frequency divider performs in actually a frequency dividing operation at the value of the receiving frequency associated data minus the intermediate frequency associated date. Now the operation of the Fig. 1 embodiment will be described. In an initial condition, the count values in the trinary counter 311 and the decimal counters 313 and 315 included in the control circuit 300 are all "O". At that time one input of the addition circuit 320 has been supplied with the numerical value "2" from the specified number setting circuit 319. Accordingly, the output of the addition circuit 320 is 2 in the initial condition. Accordingly; the numerical value "2" is obtained as channel number data and the numerical value "2" is displayed in a digital manner by the channel number display portion 403 of the channel display 400 in the initial condition. Since at that time the count value in the trinary counter 311 is "O", the numerical value determining circuit 317 determines the numerical value as nill and accordingly the channel index 401 included in the index display portion 401 of the channel display 400 is driven to display the index. Thus, in the initial condition Channel No. 2 is displayed by the channel display 400. On the other hand, the channel number data obtained from te the addition circuit 320 is multiplied by 3. Accordingly, one input of the addition circuit 323 is supplied with the numerical value "6". Therefore, the result or the sum of the addition obtained from the addition circuit 323 becomes "875". Since in the initial condition the count value in the trinary counter 311 is "or', the result or the sum of the addition obtained from the addition circuit 327 is also obtained as "875". Accordingly, the programmable frequency divider 123 included in the phase locked loop 115 is loaded with a frequency division ratio of the above described data "875". At the same time, the frequency display 500 makes a digital display of 87.5 MHz. Thus, it is indicated that the frequency 87.5 MHz is Channel No. 2 Now consider a case where the upward switch 201 is operated in the abvoe described initial condition. Upon manual operation of the upward switch 201, the flip-flop 307 is set responsive to the signal obtained from the upward switch 201 and the flip-flop 303 is set responsive to the signal obtained from the upward switch 201 through the OR gate 301. As the flip-flop 307 is set, the non-inverted output thereof becomes the high level or the logic one, whereby the trinary counter 311 and the decimal counters 313 and 315 are all rendered in an up count mode. Since at the same time the non-inverted output of the flip-flop 303 becomes the high level or the logic one, the pulse obtained from the pulse generator 305 is applied through the AND gate 309 to the count input of the trinary counter 311 as a station selecting pulse. When the first station selecting pulse is received, the trinary counter 311 counts t!1". However, since there occurs no change in the decimal counters 313 and 315, the channel number data obtained from the addition circuit 320 remains "2". Accordingly, the channel number display portion 403 of the channel display 400 still displays the channel number "2". However, since the trinary counter 311 counts the first pulse and the count value therein becomes "1", the numerical value determining circuit 317 determines the numerical value to the effect, whereby display of the index 401 of the index display portion 401 of the channel display 400 is disabled or extinguished. Therefore, upon receipt of the above described first station selecting pulse, the channel display 400 display Channel No. 2 or 20. On the other hand, since the count value in the trinary counter 311 becomes "1", the output of the addition circuit 327 as the frequency associated data becomes "876". Accordingly, the frequency division ratio of the programmable frequency divider 123 included in the phase locked loop 115 is set on the basis of the above described frequency associated date "876", while the frequency of 87.6 MHz is displayed by the receiving frequency display 500. Thus, upon receipt of the first station selecting pulse, a display is made of Channel No.2 and the frequency of 87.6 MEz. Thereafter the second pulse is applied from the pulse generator 305 through the AND gate 309 to the trinary counter 311 aa a station selecting pulse. Then the trinary counter 311 counts the eame and the count value in the trinary counter 311 becomes "2". However, the count values in the decimal counters 311 and 315 still remain "O", and accordingly the channel number display portion 403 included in the channel display 400 still displays "2" as the channel number. Since the count value in the trinary counter 311 becomes "2", the numerical value determining circuit 317 determines the same and the plus index 401 included in the channel index display portion 401 of the channel display 400 is driven or enabled. On the other hand, the output of the addition circuit 327 becomes "877", whereby the frequency of 87.7 MRz is displayed by the frequency display 500, while the numerical value "877" is set in the programmable frequency divider 123 as a frequency division ration. Thus, upon receipt of the second station selecting pulse, indication is made of Channel No. 2 and the broadcasting frequency of 87.7 MHz. Then the third station selecting pulse is applied from the station selecting pulse generator 305 to the trinary counter 311, when the count value in the counter 311 again becomes "0" while the carry pulse is applied to the decimal counter 313. Accordingly, the count value in the decimal counter 313 becomes "1". Therefore, the output of the addition circuit 310 becomes "3" and the numerical value "3" is obtained as the channel number data. Therefore, channel number 3 is displayed by the channel display 400. On the other hand, since the channel number data has become t3', the output of the multiplication circuit 321 becomes "g" and accordingly the output of the addition circuit 323 becomes "878". On the other hand, since the count value in the trinary counter 311 is "O", the output of the addition circuit 327 becomes "878". Accordingly, the frequency of 87.8 MRz is displayed by the frequency display 500 and the corresponding data is set in the programmable frequency divider 123. Thus, upon each application of the pulse from the pulse generator 305 as a station selecting pulse, the channel number is sequentially renewed for every kHz and the channel index is sequentially renewed for every 100 kHz in the display, while the frequency division ratio in the programmable frequency divider 124 of the phase locked loop 115 and thus the oscillation frequency of the voltage controlled oscillator 125 is sequentially changed. At the same time, the frequency display by the receiving frequency display 500 is also renewed for every 100 kHz. Thereafter, in a similar manner, each time a station selecting pulse is obtained from the pulse generator 305, the data displayed by the frequency display 500 and the channel display 400 is renewed. Now description is made of a case where the downward switch 203 is temporarily operated in the initial condition, i.e. when the count values in the trinary counter 311 and the decimal counters 313 and 315 are no". In such a case, as in case of operation of the upward switch 201, the flipflop 303 is set. On the other hand, the flip-flop 307 is reset, so that the non-inverted output becomes the low level or the logic zero. Accordingly, the trinary counter 311 and the decimal counters 313 and 315 are brought to the down count mode. The pulse obtained fromthe pulse generator 305 is applied through the AND gate 309 to the trinary counter 311. However, since the count values in the counters 311, 313 and 315 are all "O", no further down count can occur. Accordingly, even if the station selecting pulse obtained from the pulse generator 305 is applied, the count values in the counters remain "0", with the result that the channel number data obtained from the addition circuit 317 remains "2". This means that Channel No.s 0 and 1 of the FM band cannot be received by the radio receiver 100 in discussion. In case where such Channel Nos. 0 and 1 are allotted to police wireless communication, it is desired such channels are unreceivable. In this context, it would be appreciated that if and when a radio receiver is structured to make addition of a predetermined specified number such as "2" and a channel number associated numerical value in setting the channel number data, as in case of the embodiment shown, it is simply possible to render unreceivable the broadcasting frequencies of the channels at the extremity of a frequency band reception of which channels is not desires. Meanwhile, if and when a radio receiver is structured as shown in the embodiment such that the local oscillator of the receiver 100 is implemented by a frequency synthesizer and the output of the addition circuit 327 is utilized as a frequency division ratio to be set in the programmable frequency divider 123 and generation of the station selecting pulse is discontinued responsive to a tuning state representing signal obtained from the intermediate frequency amplifier 107, then an automatic tuning operation can be readily performed. In case where a voltage controlled oscillator is utilized as a local oscillator of the radio receiver 100, the receiver may be structured such that the frequency data obtained from the addition circuit 327 is once converted to an analog voltage, which is applied to the voltage controlled oscillator. Furthermore, although the Fig. 1 embodiment was structured such that depression of either the upward switch 201 or the downward switch 203 causes continual supply of the station selecting pulse form the AND gate 309, alternatively the embodiment may be structured such that only one station selecting pulse is generated upon each depression of either the upward switch 201 or the downward switch 203, so that the flip-flop 305, the pulse generator 305 and the AND gate 309 may be omitted. However, in such a modification, it might be required to provide a wave shaping circuit to ensure that one station selecting pulse is surely generated upon each depression of the upward switch 201 or the downward switch 203. Although in the Fig. 1 embodiment the control circuit 300 was described as implemented by discrete hardware schemes, it is clear that such control circuit can be implemented by using a microprocessor or a microcomputer now commercially available. Fig. IA is a block diagram showing another embodiment of the present invention, wherein the control circuit 300 is implemented by a microcomputer. The microcomputer shown comprises a processing unit 331, a read only memory 333 for storing an operation program of the prooessing unit 331, and a random access memory 335 structured such that data obtained from the processing unit is written in addresses thereof and the data is read out from the addresses responsive to addressing by the processing unit 331. The read only memory 333 is in advance loaded with the operation program as shown in Fig. 2 to be described subsequently, so that the instructions are obtained from the addresses thereof and are applied to the processing unit 331 responsive to addressing by the processing unit 331. Those counters similar to the counters 311, 313 and 315 shown in Fig. 1 may be implemented by predetermined address portions in the random access memory 335, for example. Fig. 2 is a flow diagram showing the operation program in case where the control circuit 300 shown in Fig. 1 is implemented by a microprocessor. First of all the control circuit 300 is responsive to depression of the upward switch 201 or the downward switch 203 to step up a counter which may be structured as shown in Fig. 1 including a trinary counter and decimal counters formed in predetermined regions of a random access memory 335 provided operatively coupled to the contro circuit 300. The channel index is determined based on the count value in the trinary counter. To that end, first it is determined whether or not hte channel index is "-I' and, if so, the index 401 included in the channel index display portion 401 of the channel display 400 as shown in Fig. 1 is enabled. If and when the channel index is not "-I', then it is further determined whether or not the channel index is "+". If and when the channel index is "+" then the index 401+ of the channel index display portion 401 is enabled. After the channel index is enabled, or if and when the channel index is neither n-" nor "+", then addition is made of the count value A in the decimal counter included in the above described counter and the specified number "2", thereby to evaluate the channel number data B. The channel number display portion 403 included in the channel display 400 is enabled based on the channel number data B thus evaluated. Then the data C is obtained by multiplying the channel number data B by 3. The data C is further subjected to addition to the minimum frequency date "869". The result or the sum D of the addition of the data C and the minimum frequency date "869" ie further added to the count value in the trinary counter. The sum E of the data D and the count value in the trinary counter is ueed as data associated with the receiving frequency and the receiving frequency display 500 shown in Fig. 1 is enabled responsive thereto, for example. The above described receiving frequency associated data E is also applied to the programmable frequency divider 123 included in the phase locked loop. Accordingly, the voltage controlled oscillator of the receiver 100 is controlled such that the same receives the broadcasting frequency corresponding to the above described receiving frequency data E and thus the channel number data B. Thereafter the control circuit 300 determins whether or not a tuning state representing signal shown in Fig. 1 is obtained. If the above described tuning state representing signal is obtained, the upward switch 201 or the downward switch 203 is reset. If the tuning state representing signal is not obtained the counters continue to effect a counting operation . Thus, the present invention can also be achieved by employing a microprocessor or a microcomputer as the above described control circuit. Fig. 3 is a schematic diagram showing another embodiment of the present invention. The Fig. 3 embodiment is different from the Fig. 1 embodiment in that the Fig. 1 embodiment comprises separately the channel display 400 and the receiving frequency display 500 whereas the Fig. 3 embodiment comprises a common display 700 which is controlled to selectively display the channel number and the receiving frequency. Since the radio receiver 100 and the control portion 300 of the Fig. 3 embodiment are substantially the same as those shown in the embodiments of Figs. 1, IA and 2, a detailed description thereof is omitted. The common display 700 comprises a numerical display portion 703 including a fivedigit display portion, indexes 701+ and 702 for displaying channel indexes, and a decimal point display portion 705 for use in displaying a receiving frequency in the numerical value display portion 703. The indexes 701 and 701 and the decimal point displaying portion 705 are adapted to make display by light emission from light emitting diodes 701 701a and 705a. In order to switchably display a receiving frequency or a channel by the common display 700, a channel display switch 205 and a frequency display switch 207 are provided in the station selecting switch group 200 as manual operable switches in addition to the upward switch 201 and the downward switch 203 shown in Fig. 1. An FM band selection switch 209 is necessary in the station selecting switch group 200 in case where a radio receiver 100 is structured to receive not only an FM band but also an LW band, MW band and/or SW band. These switches 205, 207 and 209 are structured to provide a signal of the high level or the logic one responsive to operation thereof which signal is applied to the control portion 300. The signal obtained from the FM band selection switch 209 is applied to the radio receiver 100 thereby to switch the receiver 100 to the FM band. The embodiment shown further comprises a display control circuit 600 for enabling the indexes 701+ and 701 of the common display 700 and the decimal point display portion 705. The display control circuit 600 comprises a timing signal generator 605. The timing signal generator 605 is adapted to sequentially and cyclically generate timing signals TI to T5 as shown in Fig. 4, for example. The timing signals TI to T5 are applied to the common display 700 as digit driving signals. The timing signals T1, T2 and T3 obtained from the timing signal generator 605 are applied to AND gates 607, 609 and 611, respectively. The signal obtained from the channel display switch 205 is applied to and AND gate 601 and the signal obtained from the frequency display switch 207 is applied to an AND gate 603. The AND gates 601 and 603 are also connected to commonly receive at the other input of each of them the signal obtained from the FM band selecting signal 209. The output of the AND gate 601 is applied to one input of each of the above described AN gates 607 and 609. The output of the AND gate 603 is applied to the other input of the AND gate 611. The AND gate 607 is structured as a three-input gate and is further connected to receive at the remaining input the signal representing the channel index being "+" obtained from the control circuit 300 (the numerical value determining circuit 317 in case of the Fig. 1 structure). Similarly, the AND gate 619 is also structured as a three-input gate and is connected to receive at the remaining input the signal representing the channel index being Wt¯l. The outputs of these AND gates 607, 609 and 611 are applied to an OR gate 613. The output of the OR gate 613 is commonly connected to the anodes of the light emitting diodes 701+a, 701-a and 705a of the common display 700. The cathode of the light emitting diode 701 a is connected through a transistor 615 to the ground, the cathode of the light emitting diode 701 a is connected through a transistor 617 to the ground, and the cathode of the light emitting diode 705a is connected through a transistor 619 to the ground. The bases of these transistors 615, 617 and 619 are connected to receive the timing signals T1, T2 and T3 obtained from the timing signal generator 605, respectively, as the switching control signals thereof. Now that the structural features of the embodiment shown were described in the foregoing, an operation of the embodiment will be described with reference to the waveforms shown in Fig. 5. At the outset, the FM band selecting signal 209 is operated in order to receive a broadcasting signal in the FM band by means of the radio receiver 100 and then the upward switch 201 or the downward switch 203 as shown in Fig. 1 is operated. Then, as described previously, the channel number data and the receiving frequency associated data are obtained from the control circuit 300 and applied to the common display 700. It is needless to say that the common display 700 additionally comprises a well known circuit such as a segment decoder for selectively driving the associated segments in the numerical value display portion 703 responsive to the above described data. At the same time, the receiving frequency associated data obtained from the control circuit 300 is applied to the programmable frequency divider 123 (Fig. 1) included in the phase locked loop 115 of the radio receiver 100. Now consider a case where the frequency display switch 207 is operated for the purpose of displaying the receiving frequency by the common display 700. Then the output of the AND gate 603 becomes the high level or the logic one and the output of the AND gate 611 becomes the high level or the logic one in synchronism with the timing signal T3 obtained from the timing signal generator 605. At the same time the transistor 619 is rendered conductive responsive to the timing signal T3 and accordingly the light emitting diode 705a is energized to be lighted in synchronism with the timing signal T3. Accordingly, the receiving frequency associated data obtained from the control circuit 300 is displayed in a digital manner by means of the numerical value display -portion 703 of the common display 700. At that time the decimal point displaying portion 705 has been displayed by the light emitting diode 705a, while the receiving frequency in the FM band is displayed by the numerical value display portion 703 in terms of the unit of MRz. See Fig. 5A. Now consider a case where the channel display switch 205 is operated to display the channel number. Then the output of the AND gate 601 becomes the high level or the logic one. Assuming that the signal representing the channel index being tut+" has been obtained from the control circuit 300 as shown in Fig. 53, then the output of the AND gate 607 provides the high level or the logic one in synchronism with the timing signal T1 as shown in Fig. 5C. Since the timing signal T1 renders the transistor 615 conductive, the light emitting diode 701+a is energized to be lighted in synchronism with the timing signal T1. Accordingly, the index 701+ of the common display 700 is displayed. At that time the channel number data has been obtained from the control circuit 300. Since the light emitting diode 705a is not energized and thus is not lighted when the channel number data is to be displayed, the decimal point display portion 705 is not displayed. Assuming that the signal representing the channel index being "-" has been obtained from the control circuit 300 as shown in Fig. 5D when the channel display switch 205 is operated, the index 701 of the common display 700 is energized to be displayed as shown in Fig. 5E in synchronism with the timing signal T2 obtained from the timing signal generator 605. If and when it is desired that in the Fig. 3 embodiment the frequency of the SW band is also displayed, a switch for selecting the SW band may be provided, while a decimal point display portion may be provided at a digit position one digit less significant than that of the decimal point display portion 705 in the common display 700, so that the above des cribbed additional decimal point display portion may be selectively enabled on the occasion of display of the frequency of the SW band. Thus, according to the Fig. 3 embodiment, in making display of a receiving frequency, the channel and the receiving frequency can be selectively displayed using a single common display. Furthermore, the Fig. 3 embodiment may be implemented in a simple structure, since the same was structured such that the decimal point display portion on the occasion of display of a receiving frequency and the indexes for displaying channel indexes are driven in a time sharing manner. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by way of terms of the appended claims.

Claims: Fatent claims 1. A superheterodyne receiver including a local oscillator (125) with varyable frequency, control means (123, 119) for controlling the frequency of said oscillator and channel display means (400) for displaying a channel number related to the frequency of the local oscillator, characterized in that channel number data setting means (300) are provided for setting channel number data.controlling the channel number to be displayed, and that the control means (123 119) for the local oscillator (125) are controlled by signals converted from said set channel number data. 2. A superheterpdyne receiver in accordance with claim 1, characterized in that said channel number data setting means (300) comprises specified number presetting means (319) for presetting a specified number, channel number associated numerical value setting means (200, 301 to 315) for setting a numerical value associated with said channel number, and operation means (320) responsive to said preset specified number and said numerical value for making an operation for providing said data concerning a channel number. 3. A superheterodyne receiver in accordance with claim 2, characterized in that said numerical value setting means (200, 301 to 305) comprises manual operable means (200) for setting said channel number associated numerical value, channel number setting signal providing means (301 to 309) operatively coupled to said manual operable means for providing a signal for setting said channel number responsive to manual operation of said manual operable means, and counting means (311 to 315) for counting the number of said signal for setting said channel number. 4. A superheterodyne receiver in accordance with claim 3, characterized in that said superheterodyne receiver is adapted for use in an environment wherein channel numbers have been allotted such that each channel number includes a plurality (m) of independent channels the frequencies of which are different, whereby each said channel number represents a channel group including the plurality (m) of channels and that said counting means comprises an m-nary counter (311) corresponding to said plurality (m) number of the channels in one channel group, and said superheterodyne receiver further comprises channel index display means (401) for displaying channel indexes for indentifiying said plurality (m) of independent channels included in said one channel group represented by said one channel number, and channel index display control means (317) responsive to the count value in said m-nary counter for controlling said channel index display means for displaying a corresponding one channel index. 5. A superheterodyne receiver in accordance with claim 2, characterized in that said channel numbers have been allotted as a series of numbers in one frequency band, said specified number preset in said presetting means is seleoted such that a predetermined channel at the extremity of said frequency band is rendered unreceivable when the frequency of said local oscillation signal is varied by said local oscillation frequency varying means. 6. A superheterodyne receiver in accordance with claim 5, characterized in that said specified number is selected such that a predetermined channel at the lowest frequency end portion of said frequency band is rendered unreceivable, and said operation means comprises addition means (320)- for making additicn of said specified number preset in said specified number presetting means and said channel number associated numerical value in said channel number associated numerical value setting means. 7. A superheterodyne receiver in accordance with claim 6, characterized in that said specified number is "2". 8. A superheterodyne receiver in accordance with claim 4, characterized in that said plurality (m) is "3". 9. A superheterodyne receiver in accordance with claim 1, characterized in that said superheterodyne receiver further comprises frequency data converting means (321 to 327) for converting said channel number data into frequency data concerning a corresponding receiving frequency, and frequency display means (500) responsive to said frequency data for displaying said corresponding receiving frequency. 10. A superheterodyne receiver in accordance with claim 9, characterized in that said superheterodyne receiver is adapted for use in an environment wherein said channel numbers have been allotted as a series of the channel numbers in a given frequency band such that one channel number stands for a plurality (m) of independent channels commonly grouped in said one channel number, and that said channel number data setting means comprises manual operable means (200) for setting a channel number, channel number setting signal providing means (301 to 309) operatively coupled to said manual operable means for providing a signal for setting said channel number responsive to manual operation of said manual operable means, and counting means (311 to 315) for counting the number of said signal for setting said channel number, and that said frequency data convertin means comprises multiplication means (321) for multiplying said data concerning a channel number set in said channel number data setting means by the factor commensurate with said plurality (m), first addition means (323) for adding data associated with' the frequency of a channel at one extremity of said frequency band to the product obtained by said multiplication means, and second addition means (327) for adding the count value in said counting means to the sum of said first addition'means. 11. A superheterodyne receiver in accordance with claim 19, characterized in that said channel number display means and said frequency display means are structured by a common dieplay (200), and said superheterodyne receiver further comprises display switching means (205, 207) for selectively providing to said common display as display data said data concerning the channel number or said data concerning the receiving frequency. 12. A superheterodyne receiver in accordance with claim 11, characterized in that said common display comprises a decimal point display portion for displaying said data concerning the receiving frequency and a channel index display portion (701+, 701-) for making display for eepoifying one of said plurality (m) of channels grouped in said one channel number, and said superheterodyne receiver further comprises timing signal generating means (605) for generating timing signals, and enabling means (607 to 613, 615, 617) responsive to said timing signals for enabling said decimal point display portion and said channel index display portion at different timing. 13. A superheterodyne receiver in accordance with claim 12, characterized in that said superheterodyne receiver further comprises common connecting means (613) for connecting said decimal point display portion and said channel index display portion to a common signal line, and synchronizing means (607 to 619) for controlling said enabling means for synchronizing enabling of said decimal point display portion and enabling of said channel index display portion with said different timing signals, respectively. 14. A superheterodyne receiver in accordance with claim 13, characterized in that said enabling means comprises selecting signal generating means (601, 603) for generating a selecting signal for selecting said decimal point display portion and a selecting signal for selecting said channel index display portion, and said synchronizing means comprises signal converting means (607 to 613) for converting said selecting signal for selecting said decimal point display portion and said selecting signal for selecting said channel index portion into driving signals synchronized with said different timing signals, respectively, and display control means (613, 615 to 619) responsive to said driving signals of said signal converting means for controlling said decimal point display portion and saidchannel index display portion. 15. A superheterodyne receiver in accordance with claim 1, characterized in that said local oscillating means comprises voltage controlled oscillating means, and said contsm signal converting means comprises frequency division ratio converting means (321 to327) for converting said data concerning a channel number set in said channel number data setting means into data concerning a frequency division ratio, and that said superheterodyne receiver further comprises a phase locked loop (115) including said voltage controlled oscillating means (125), said phase locked loop including programmable frequency dividing means. ('123), said data concerning a frequency division ratio obtained from said frequency division ratio converting means being applied to said programmable frequency dividing means. 16. A superheterodyne receiver in accordance with claim 1, characterized in that said local oscillating means comprises voltage controlled oscillating means, analog voltage converting means for converting said data concerning a channel number set in said channel number data setting means into an analog voltage associated therewith, and means for supplying said analog voltage to said controlled oscillating means as a control voltage. 17. A superheterodyne receiver in accordance with claim 3, characterized in that said channel number setting signal providing means comprises variation causing means for causing said signal for setting the channel number to automatically vary responsive to manual operation of said manual operable means, and said superheterodyne receiver further comprises tuning state representing signal providing means (107) for providing a signal representing a tuning state of said superheterodyne receiver, and variation stopping means (303) responsive to said tuning state representing signal for stopping said automatic variation of said setting signal obtained by said channel number setting signal providing means. 18. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver including local oscillator with variable frequency, control means for controlling the frequency of said oscillator and channel display means for displaying a channel number corresponding to said receiving frequency, characterized in that said method comprises the steps of setting channel number data controlling the channel number to be displayed, controlling said control means for the local oscillator by signals converted from sais set channel number data, and displaying said channel number responsive to said channel number data. 19. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 18, characterized in that said step of setting data concerning channel number comprises the steps of presetting a specified number, setting a numerical value associated with said channel number, and making a arithmetic operation with respect to said preset specified number and said set channel number associated numerical value for providing said data concerning a channel number. 20. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 19, characterized in that said step of setting said channel number associated numerical value comprises the steps of manually setting said channel number associated numerical value, providing a signal for setting said channel number responsive to said manual setting of said channel number associated numerical value, and counting the number of said signal for setting said channel number. 21. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 20, which is adapted for use in an environment whre- in channel numbers have been allotted such that each channel number includes a plurality (m) of independent channels the frequencies of which are different, whereby said each channel number represents a channel group including the plurality (m) of channels, characterized in that said counting step comprises the step for making the counting operation in an m-nary counting manner corresponding to said plurality (m) number of the channels in one channel group, and said method further comprises the steps of displaying channel indexes for identifiying said plurality (m) of independent channels included in said one channel group represented by said one channel number, and controlling said channel index displaying step for displaying a corresponding one channel index. 22. A method for controlling a receiving frequency and a channel display in accordance with a superheterodyne receiver in accordance with claim 19, characterized in that said channel numbers have been allotted as a series of numbers in one frequency band, said specified number is selected such that a predetermined channel at the extremity of said frequency band is rendered unreceivable when the frequency of said local oscillation signal is varied by said variation of the frequency of said local oscillation signal. 23. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 22, characterized in that said specified number is selected such that a predetermined channel at the lowest frequency end portion of said frequency band is rendered unreceivable, and said arithmetic operation step comprises the step of making addition of'said specified number and said channel number associated numerical value. 24. A method for controlling a receiving frequency and a channel display in accordance with claim 17, characterized in that said method further comprises the steps of converting said data concerning a channel number into data concerning a corresponding receiving frequency, and displaying said corresponding receiving frequency. 25. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 19, which is adapted for use in an environment wherein said channel numbers have been allotted as a series of the channel numbers in a given frequency band such that one channel number stands for a plurality (m) of independent channels commonly grouped in said one channel number, characterized in that said channel number data setting step comprises the steps of manually setting a channel number, providing a signal for setting said channel number responsive to manual setting of said channel number, and counting the number of said signal for setting said channel number, and said frequency data converting step comprises multiplying step for multiplying said data concerning a channel number by the factor commensurate with said plurality (m), first adding step for adding data associated with the frequency of a channel at one extremity of said frequency band to the product obtained by said multiplaying step, and second addingstep for adding the count value by said counting step to the sum of said first adding step. 26. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 25, characterized in that said channel number displaying step and said frequency displaying step are performed by the use of a common display, and said method further comprises the step of selectively providing to said common display as display data said data concerning the channel number or said data concerning the receiving frequency. 27. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 26, characterized in that said common display comprises a decimal point display portion for displaying said data concerning the receiving frequency and a channel index display portion for making display for specifying one of said plurality (m) of channels grouped in said one channel number and said method further comprises the steps of generating timing signals, and enabling said decimal point display portion and said channel index portion responsive to said timing signals at different timing. 28. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 27, characterized in that said method further comprisee the steps of connecting said decimal point display portion and said channel index display portion to a common signal line, and synchronizing said enabling step with said different timing signals. 29. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 28, characterized in that said enabling step comprising the step of generating a selecting signal for selecting said decimal point display portion and a selecting signal for selecting said channel index display portion, and said synchronizing step comprises the steps of converting said selectingsignal for selecting said decimal point display portion and said selecting signal for selecting said channel index display portion into driving signals synchronized 'with different timing signals, respectively, and controlling said decimal point display portion and said channel index display portion responsive to said converted driving signals synchronized with said different timing signals, respectively. 30. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 18, characterized in that said local oscillating means comprises voltage controlled oscillating means, said controll signal converting means comprises frequency division ratio converting means for converting said data concerning a channel number into data concerning a frequency division ratio, and said superheterodyne receiver further comprises a phase lockes loop including said voltage controlled oscillating means, said phase locked loop including a programmable frequency dividing means, sais data concerning a frequency division ratio being applied to said programmable frequency dividing means. 31. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 18,characterized in that said local oscillating means comprises voltage controlled oscillating means, and said method further comprises the step of converting said channel number data into a analog voltage associated therewith, and supplying said analog voltage to said voltage controlled oscillating means as a control voltage. 32. A method for controlling a receiving frequency and a channel display in a superheterodyne receiver in accordance with claim 20, said channel number setting signal providing step comprises the step of genrating setting signals to cause sais signals for setting the channel number to automatically vary responsive to manual setting of said channel number associated numerical value, and said method further comprises the steps of providing a signal representing a tuning state by said superheterodyne receiver, and stopping said automatic variation of said setting signal obtained by said channel number setting providing step responsive to said tuning state representing signal.

Inventors: SUMI, YASUAKI
Applicants: SANYO ELECTRIC CO., LTD., TOTTORI SANYO ELECTRIC CO., LTD.
Application year: 1979
Main classification: H03J5
IPC codes: H03J7, H03J1, H03J5