PUBLIC TELEPHONE SETS

Abstract: In a public telephone set there are provided a coin pro­ cessing unit (CCC) for sorting coins inserted into the tele­ phone set, a coin box (15) for collecting inserted coins, a control unit for collecting the sorted coins in the coin box and sending an origination from the telephone set a plurality of coin detectors (DA, CR, CC, CK) for detecting clogging by coins of coin passageways to the coin box (15), a control circuit (MCC) for detecting a fault in accordance with the outputs of the coin detectors, a memory device which stores a program for causing the control circuit (MCC) to detect a fault, and a switch interlocked with a hook switch (H) for starting the operation of the control circuit (MCC) and the memory device. There are also provided display devices (DIS) connected to the control devices for displaying a faulty part. According to this invention presence or absence of a fault is automatically detected by hooking off operation and the location of the fault is displayed. Accordingly the user is informed of the fact that telephone set can not be used and its use is automatically prevented and a maintainance man can note the faulty part.

Description: Public Telephone Sets. This invention relates to a public telephone set, more particularly a public telephone set capable of detecting or locating a faulty portion. A prior art public telephone set is generally constructed to enable a user to talk by merely inserting a coin or coins and can not detect by itself presence or absence of a fault, so that the user becomes aware of the presence of the fault only after he starts to use the telephone set. Thus, the user could not aware of a fault until he dials, thus wasting time. More particularly, among the fault are included a case in which even when a coin is inserted after hook-off, a loop circuit is not closed with the result that a dial tone is not received, a case wherein the inserted coin is returned at once, a case in which notwithstanding accumulation of the coins and a normal dial tone is transmitted, the loop circuit is interrupted, and a case in which remaining coins are not returned after termination of the speech. Especially, the last case causes loss of money. Most of these faults are caused by clogging by coins of coin passageways between a coin inserting slot and a coin storage vessel or between the coin storage vessel and a coin returning opening. For this reason, it is important to supervize the condition of the coin storage vessel for detecting presence or absence of a fault. In addition to these faults, there are such faults as failure of closing a loop circuit due to incorrect contact of the hook switch and incapability of collecting coins due to a fault of a rate signal receiving circuit. These faults result not only in the incapability of a speecn but also damage to Xne owner of the public te- phone set. However, each of these faults can not be detected from outside of the telephone set thus causing inconvenience. To repair a fault a maintenance man must successively inspect various parts according to a maintenance manual which is extemely troublesome. Even when a fault is detected, certain type of fault is impossible to repair at the field so that the maintenance man must carry the faulty telephone set to a repair shop. Such inconvenience also occurs at the stage of the finaltest in a manufacturing factory of public telephone sets. Thus, it is necessary to manually check faulty which increases the cost of manufacturing. For the reason described above, it has long been desired to provide effective means that can clearly display faulty parts. Summary of the Invention Accordingly, it i1s the principal object of this invention to provide an improved public telephone set capable of effecting self diagnosis of a fault. Another object of this invention is to provide a public telephone set which is simple in construction and easy to maintain and capable of effecting self diagnosis of a fault. Still another object of this invention is to provide a public telephone set consuming less power. According to this invention there is provided a public telephone set comprising a telephone circuit connected to office lines and including a handset having a transmitter and a receiver, a dial tone transmitter, and a hook switch adapted to complete a speech loop; a first processing means for sorting coins inserted through a coin slot of the telephone set; a coin box for collecting inserted coins; control means for controlling collection of the inserted coins passed through the first processing means into the coin box, and for controlling origination of the telephone circuit; a plurality of sensors for detecting clogging of a coin passageway extending from the coin slot to the coin box; second processing means for detecting faults at points to be examined in accordance with the outputs of the sensors; a memory device storing a program for supplying an output signal to the second processing means to cause the same to detect faulty points, and means operated by the operation of the hook switch for controlling start of the second processing means and the memory means. Brief Description of the Drawings Further objects and advantages of the invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which: Fig. 1 is a diagrammatic sectional view showing the construction of a coin collecting unit of a public telephone set embodying the invention; Fig. 2 is a block diagram showing the basic construction of a public telephone set system embodying the invention; Fig. 2A is a connection diagram of a speech circuit and a speech control circuit. Fig. 3 is a block diagram showing the construction of the control circuit shown in Fig. 2 and the relationship between the control circuit and an input/output circuit associated therewith; Fig. 4 is a flow chart showing execution steps of detecting a fault by the control circuit; Fig. 5 is a block diagram showing the construction of a coin processing circuit shown in Fig. 2 and the input/ output circuit associated therewith; Fig. 6 is a flow chart showing the execution steps of detecting a fault by the coin processing circuit; Fig. 7 through 14 are flow charts showing the execution steps of detecting a fault according to another embodiments of this invention. Description of the Preferred Embodiments A coin collecting unit shown in Fig. 1 utilized in a public telephone set embodying the present invention in designed to use low, medium and high price coins such as 10 Yen, 50 Yen and 100 Yen coins of the Japanese currency, for example. Coins inserted into a slot I.pass through a first inclined passageway 2 with a material discriminator Co and coin detectors DA1 and DA2 which detect the outer diameter of the coins and disposed on both sides, then through a second inclined passageway 3, When accumulation levers 4,5 and 6 driven by the outputs of the material discriminator CO and the coin detectors DA1 and DA2 which discriminate whether the coin is a genuine or a counterfeit one and determine the outer diameter of the coins are moved laterally with respect to-the second inclined passageway 3, low price coins drop into a low price pocket 7, medium price coins into a medium price pocket 8 and high price coins into a high price pocket 9 respectively. These coins are piled up on collecting levers 10,11 and 12 respectively and accumu lated according to the type of the coins. When inproper or counterfeit coins are detected, the accumulating levers 4,5 and 6 would not be operated so that these coins roll on the accumulating levers 4,5 and 6 and returned to a coin returning opening 13. By a hook-on operation made at the time of termination of a speech, returning levers 14a, 14b and 14c are operated to shift toward left the coins accumulated on the accumulating levers 10 to 12 thereby returning these coins through the returning opening 13. As a detector of the material discriminator CO may be used an electric coil connected to an oscillation circuit. With this arrangement, the coil is influenced by the permeability or transmittivity corresponding to the material of the coin so that the output of the oscillation circuit varies which is used to discriminate the material of the coins. Such discriminator is well known in the art. The coin detectors DA1 and DA2 are constructed such that luminous element, a photodiode for example, and a light receiving element, for example a photo-transistor are disposed to confront each other so as to detect a coin depending upon the presence or absence of impinging upon the light receiving element caused by the presence or absence of the coin. The diameter of the coin can be detected by the following equations S = t1 (1), or L = t2 (2) S where S = tl'V, V represents the rolling speed of the coins passing by the coin detectors DA1 and DA2, tl the time necessary for the coins to pass by the coin detector DA1, t2 the time required for the coins to pass between the coin detectors DA1 and DA2, and L the distance between the coin detectors DA1 and DA2. Since S is deter mined by the size of the ssizzs and the inclination C the first inclined passageway 2, and L is predetermined, it is necessary to calculate only the righthand terms of equations (1) and (2). In addition to the elements described above, there are also provided coin detectors CR1 to CR3, Cci to CC3 and MR similar to the coin detectors DA7 to DA2. Coin detectors CR1 to CR3 detect the number of the accumulated coins, the coin detectors Cci to CC3 detect the coins prior to the collection, while the coin detectors CK1 to CK3 detect the collected coins. The coin detector MR detects the returned coins. As the collecting levers 10 to 12 are moved laterally to collect only one waiting coin, the outputs of the coin detector CC1 to CC3 disappear whereas the coin detectors CK1 to CX3 produce output whereby the fact that the coins have been collected in a coin collecting box 15 can be confirmed. The number of the remaining coins is determined by the difference between the outputs of the coin detectors CR1 to CR3 which represent the number of the accumulated coins and the outputs of the coin detectors CKl to CK3 which represent the number of the collected coins. The sum of the number of returned coins determined by the coin detector MR and the total number of the accumulated coins should be equal to the number of inserted coins detected by the coin detector DAl or DA2. The purpose of the coin detector MR is to confirm the number of the accumulated coins based on this calculation. The coin collecting unit is constructed such that it preferentially collects low price coins in response to a rate signal from a telephone exchange, and when it collects medium and high price coins it will collect the next coin after elapse of a speed time detenrrind by the value of the collected coins in response to a rate signal. The coin box 15 is provided wltb an electromagnetic accumulating counter CUT which in response ta the outputs of the coin detectors CK1 to C3 counts the number of count pulses sent from a control circuit MCC to be described later. When the count of the counter CUT reaches a value showing that the coin box is filled with coins, the counter CUT produces a full signal ScF. It is to be understood that the counting operation of the accumulating counter CUT is performed in terms of a ratio of the volume of the medium and high price coins to that of the low price coins. For example, when the ratio of volumes of the low, high and medium price coins is 1:4:6 the counting is made once for a low price coin, but 4 and 6 times for medium and high price coins respectively. The accumulating counter is automatically reset when the coin box 15 is removed. A switch CB is provided near the coin box 15 to check the same. Fig. 2 is an entire block diagram of a public telephone set including the material discriminator CO, various coin detectors DA1, DA2, CR1 to CR3, CC1 to CC3, CK1 to CK3 and MR, accumulating magnets SM1 to SM3 for driving levers 4 to 6, 10 to 12 and 14 respectively, collection magnets CKl to CM3, and a return magnets RM of the coin collecting unit. The control device comprises a coin processing circuit CCC and a control circuit MCC. To provide inherent performance of the telephone set, as shown in Fig. 2A, there are provided a speech circuit SPC including an induction coil, a handset etc., and a speech control circuit TCC connected between the speech circuit and line terminals LTB and including a relay GS for actuating a loop closing contact gsl, a relay SS for short circuiting a dial impulse contact sus1, a luminous diode LED and a light receiving element RD which are used to detect loop currents, a diode bridge DB for supplying unidirectional current to the luminous element and a paging processing circuit TM. A push button dial Dii is connected in-parallel with the speech control circuit. Across the time terminals LTB is connected a rate signal receiving circuit CP (see Fig. 2) including a band pass filter and an amplifying filter, not shown, to detect a rate signal having a frequency of 500 Hz or 16KHz and sent from the telephone exchange at each end of a unit speech time thus producing a pulse signal. An alarm tone send out circuit WT is provided to produce an alarm tone having a frequency of 250 Hz. It is constructed to start an oscillation circuit when it receives a coin insertion request signal SWT and a fault detection signal ST for sending the alarm tone to a receiver of the handset in the speech circuit SPC via a matching transformer thus urging the user to insert coins by sound and a detection informing of a fault to the user. In this example, the coin insertion demand signal is an interrupted tone, whereas the information of the fault detection is made by a continuous tone. The control circuit MCC is started when the hook switch H is closed by hook-off, and the power circuit PW is closed by the closure of the hook switch H to supply power to all devices. When supplied with signals CDA and CDEN, the control circuit MCC and the coin processing circuit CCC exchange fault detection in formations in their respective ranges. The control circuit MCC drives a display unit DIS1 on the telephone set comprising a charactor display device and a display lamp in then form of a luminous diode. The charactor display device displays the number of remaining speech time units determined by the value of the collected coins, whereas the display lamp displays not usable state in response to a fault detection and a full state of the coin state. When a fault is detected, a latch type maintenance switch SW is manually operated to display a code corresponding to a faulty part as a digit or alphabet on the charactor display device. Also the coin processing circuit CCC drive a display unit DIS2 utilizing a charactor display device and mounted on the telephone set, and when a fault is detected in a range allocated thereto, a code corresponding to the faulty part is displayed thus correctly informing the the faulty part to the maintenance man. The construction of the control circuit MCC and input and output of various signals to and from the control device are shown in the block circuit shown in Fig. 3. The control circuit MCC is constituted by a processor CPU1 such as a microprocessor or the like, a memory device ROM1, an auxiliary memory device RAM1, an input/output circuit I/O, and a timer TIMi. As the memory device ROM1 is used a fixed.memory device which stores a program for detecting faults of a predetermined part. As the auxiliary memory device RAM1 is used a randam access memory device for sequentially storing various in formations necessary to operate the control circuit MCC. When the handset is hooked off prior to the use of the telephone set, the hook switch H applies a hook-off signal SH to the processor CPU1 via the input/output circuit I/o. At the same time, as the source circuit PW produces an output in response to the hook-off signal SH' the control circuit MCC is rendered operative. At this time, the processor CPU1 clears all addresses of the auxiliary memory device RAM1 and changes various signals SpW' WT SRM, CM1 to ScM3, SAGS SSS' S SDIS1 and S passing through the input/output circuit I/01 to reset states, for example to low level states "0", thus settan initial state. At the same time, the processor CPU1 applies a set signal SET1 to the timer TIM1 to start the same. Further, the processor CPU1 designates an address iNDO of the auxiliary memory device RAM1. The parts to be examined are the speech control circuit TCC, the rate signal receiving circuit ep, the coin detectors CC1 to CC3, CKl to CK3, the accumulating counter CUT of the coin box, a reed switch CB mounted on the coin box and operated when the coin box 15 is mounted on a predetermined position and the fault signal CDEN produced by the coin processing circuit CCC. Immediately after setting the initial state, the processor CPU1 begins to read out the program from the memory device ROM1 so as to sequentially detect faults of the parts to be examined according to the program. Transmission and reception of various signals are effected through a suitable drive circuit or a buffer circuit, not shown. Fig. 4 is a flow chart showing execution steps of detecting faults effected by the control circuit MCC. When a hook-off signal is supplied to the control circuit MCC, this signal makes an access to CPU1 via the input/output circuit I/01 to commence the following processing operations. More particularly, at step 101, all addresses of the auxiliary memory device RAM are cleared and an address iNDO is designated to set the input and output signals SPW' SWT' SRM' SSM1 to SCM3' SGS' SSS' SDIS1 and SCU to the initial states (low levels "0") through the input/ output circuit I/01. Further, the processor CPU1 sends a set signal SET to the timer TIM to cause it to begin to count time. Then the program is advanced to step 102 to send a signal SGS to the relay GS of the speech control circuit TCC via the input/output circuit I/01. Thus, the relay GS is energized to switch the contact gsl shown in Fig. 2A to establish a loop circuit to the telephone exchange thus forming a speech circuit. In this manner, a speech channel loop is closed by the hook-off operation. As shown in Fig. 2A, since the luminous diode LED is included in the loop circuit, the luminous diode luminesces when the loop circuit is closed. In response to the light emitted by the luminous diode, the light receiving element RD sends a speech loop current detection signal S to MCC, Then, at step 103, the CPU1 checks the signal SCF sent from the accumulating counter CUT via the input/output circuit I/01, and when it is "0., the program is advanced to step 104 to judge that the coin box 15 is not yet filled thereby storing a code rOJ in the address iND1 of the auxiliary memory device RAM1. If the signal SCF is "1" it is judged that the coin box 15 is full and this condition is deemed as a fault and the program is advanced to step 105 at which a code r1 > is stored in the address iND1 of the auxiliary memory device RAM1 as a fault signal. Then, at step 106, the signal SCB sent from the coin box mounting switch CB via the input/output circuit I/01 is checked, and if this signal is t0X, it is judged that there is no fault and the program is advanced to step 107 where á code rOJ is stored in the address iND2 of the auxiliary memory device RAM1. On the other hand, if the signal SCB is "1", at step 108 it is judged that the relay CB is not operated, that is the coin box 15 has not yet been mounted. This condition is also deemed as a fault and a code r2 would be stored in the address iND2 of the auxiliary memory device RAM1. A signal SCC1 from the coin detector CC1 is also checked However, this state is the state appearing immediately after setting the initial state and since no coin has been inserted, if the signal 5cci is "0", it is judged that the telephone set is normal and the program is advanced to step 110 where a code #O# is stored in the address iND2 of the auxiliary memory device RAM1. If the signal SCC1 is "1", the detector CC1 judges that the luminous element or the light receiving element disposed along the coin passageway is faulty or there is a fault caused by the clogging of the passageway by coins, thereby storing r12 in address iND3 of the auxiliary memory device RAM1 as a fault signal. Another coin detectors CC2, CC3, cK1 to CK3 are checked in the same manner according to an order just mentioned. These steps are shown by steps 112 through 122 shown in Fig. 4. When the outputs of the detectors CC2, CC3, CK1 to CK3 are "0" that is normal, codes #O# are stored in addresses iND4 to iND8 of the auxiliary memory device RAM1 at steps 113, 116, 119, 122 and 125 respectively. If the outputs are "1", codes r1 > are stored in the addresses iND4 to iND8 at steps 114, 117, 120, 123 and 126 respectively. Then the program is advanced to step 127 to check a rate signal SCp sent from the rate signal receiving circuit CP. However, when the rate signal is not received and when it is "0", the condition is judged normal and the step is advanced to step 128 where code rOJ is stored in the address iND9 of the auxiliary memory device RAM1. On the other hand, if the rate signal is "1" it is judged that there is a fault and the step is advanced to step 129 where a code r9 is stored as a fault signal. At step 130 the loop current detection signal STS is produced by the light receiving element RD which receives the light from the luminous element LED. When the signal STS is "0" it is judged that current is flowing through the loop that is that the speech circuit has been closed by relay GS and the program is advanced to step 131 where a normal code rO, is stored in the address iNDA of the auxiliary memory device RAM1. On the other hand, if the signal STS is "1" it is judged that there is a fault of nonestablishment of the speech circuit caused by the fault of the relay GS and the program is advanced to step 132 where a code rAJ is stored in the address iNDA in the same manner as above described. When fault detection is made as above described by checking various parts to be examined, the program is advanced to step 133 where the contents of respective addresses iND1 to iNDA are read out and where all codes are r0 it is judged that there is no fault. Then the program is advanced to step 134. If the codes are anyone of r1 > through rA , it is judged that there is a fault and the program is transferred to a "fault mode", that is step 135 and the succeeding steps. Where it is judged that there is no fault, the step is advanced to step 134 to send a signal CDA to the coin processing circuit CCC as a code #O#. Thereafter the step is advanced to step 136 to check the signal CDEN from the coin processing circuit CCC. If the signal CDEN is a code #O# it is judged that there is no fault in the coin processing circuit CCC thus transferring the mode to the "normal mode" to execute various control operations necessary for the inherent performance of the telephone set. If at step 136, the signal CDEN is a code r1 , it is judged that there is a fault in the coin processing circuit and the program is advanced to step 137 where a code #B# is stored in the address iND3 of the auxiliary memory device RAM1 as a fault signal. Then this information is handled as a portion of the "fault mode" and the program is advanced to step 135. At the fault mode, at step 134a, the CPU1 sends a signal CDA of rl, to the coin processing circuit CCC Then at step 135, the processor CPU1 sends a signal SD3S1 to the display unit DIS1 via the input/output circuit I/01 according to the program of the memory device ROM1 thus causing the display "not usable" to indicate a fault. Concurrently therewith the control circuit MCC produces a signal SWT which operates the alarm tone send out circuit WT thus causing the receiver of the handset in the speech circuit SPC to generate an alarm tone. Thus, due to the self diagnosis described above, a fault is informed to the user by the informing circuit including the display unit DIS1 and the alarm tone send out circuit WT. At the "normal mode", insertion of a coin by the user produces a signal Sss which operates relay SS to break the shorting circuit for the dial impulse contact SS1 of the speech control circuit TCC shown in Fig. 2A thus sending a dial tone. However, during the "fault mode" signal is is not produced and shorting circuit is not interrupted so that it is impossible to transmit the dial tonethus preventing use of telephone set. Furthermore, during the "fault mode" by the manipulation of the maintenance switch SW, the charactor display device of the display unit DIS1 displays codes corresponding to the faulty parts according to the content of the auxiliary memory device RAM1 in the following steps. More particularly, as shown in Fig. 4, at step 136 following the alarm tone sending step 135, a check is made as to whether the switch SWO is closed or not. If the switch SWO is closed, the program is advanced to step 138. If the switch SWO is open, the step is returned to step 103 to execute the same processing as above described. At step 138, a check is made as to whether the timer TIM1 has counted a predetermined time or not, that whether the timer has produced an output T1 or not. At step 138, when the processor CPU1 receives the out put T1 of the timer TIM1 an idle address iNDO of the auxiliary memory device RAM1 is used as a count out address and the a digital rlz is sequentially added to the content N of the idle address at step 139 to form new content N. At step 140, this operation is repeated until the content N becomes equal to a value B of the address number representing the address iNDB of the auxiliary memory device RAM1. When the content N becomes equal to the value of the address number B, the content N is changed again the a value 71 at step 141 and a value r1 is sequentially added at step 142. Accordingly, at step 142, the contents of addresses iND1 to iNDB in which in formations regarding the presence and absence of a fault have been stored are sequentially read out by using the content N of the counter address. If one of the codes #1# to #B# is of the fault signal in any one of the addresses, at step 143 a signal SDIS1 corresponding to the code is read out to display a code representing a fault of a smallest address number by the charactor display device of the display unit DIS1. The display time is the same as the operating time of the timer, about one second, for example. At step 143, the timer is started again to return the program to the step 103 and the following steps to display a faulty part of the next address number and all stored fault signals are sequentially and repeatedly displayed. This display is continued as long as the maintenance switch is in the closed state. Although in the display unit DIS1, faults of various parts to be inspected and allocated for the control circuit MCC are displayed independently, and the faults allocated for the coin processing circuit CCC are displayed simultaneously, by allocating the check points of the fault to respective segments of a letter 8 shaped display element and then extinguishing segments corresponding to the faulty parts. The operation described above is repeated during a definite interval and if a fault is recovered its display is immediately stopped. If the timer TIM1 does not generate the signal T1 at step 138, the program is returned to the initial step 103 to repeat the same processing. Fig. 5 is a block diagram showing the construction of the coin processing circuit CCC and the signal inputted to and outputted therefrom. Like Fig. 3, the coin processing circuit CCC is constituted by a processor CPU2, such as a microprocessor, a memory device ROM2, an auxiliary memory device RAM2, an input/output circuit I/02 and a timer TIM2. The operations of the memory devices ROM2 and RAM2 are the same as those shown in Fig. 3. The parts to be examined are the material discriminator CO, the coin detector DA1, DA2, MR and CR1 to CR3 and the signal CDA generated by the control circuit MCC,and program stored in the memory device ROM2 corresponds to the parts or point to be examined. When the source circuit PW is energized an initial state like that of the control circuit MCC is set and immediately thereafter, the processor CPU2 starts to read out the program of the memory device ROM2 to sequentially detect faults at respective points to be examined according to the program. Fig. 6 shows the flow chart of successive steps of detecting faults effected by the coin processing circuit CCC. Thus, at step 151, the processor CPU2 initializes the setting to the initial state. More particularly, when the source circuit PW is closed, the processor CPU2 of the coin processing circuit CCC clears all addresses of the auxiliary memory device RAM2 and at the same time the outputs 5SM1 to SSM3 and SDIS2 to the reset state that is "0" state through the input/output circuit I/02, thus establishing the initial state. Also the processor CPU2 sends a set signal SET2 to the timer TM2 to cause it to start. Furthermore, at this time, the processor CUP2 designates an address iNDO of the auxiliary memory device RAM2. After the CPU2 has initialized to the initial state at step 151, the states of respective coin detectors DA1, DA2, MR and CR1 to CR3 are sequentially latched at steps 152 to 169. More particularly at step 152, the CPU2 is supplied with the output SDA1 of the coin detector DA1 via the input/ output circuit I/02 and latches the output SDAl Since the initial state has just been set at this time, any coin has not yet been inserted so that the output of this detector DA1 would be "O". Then, the program is advanced to step 153 to store a code #O# in the address iND1 of the auxiliary memory device RAM2 by judging the state as the normal state. On the other hand, when the detector output SDA1 is "1", it is judged that a fault exists showing the clogging of the coin passageway, or a fault of the luminous or light receiving element comprising the detector DA1. Then the program is advanced to step 154 to store #1# in the address iND1. Upon completion of this storing operation, the program of CPU2 is advanced to step 155 to latch the output SDA2 of the coin detector DA2 just in the same manner as the output SDA1 of the coin detector DA1. Thereafter, the outputs of coin detectors MR, CR1 to CR3 are latched at steps 158, 161, 164, and 167 respectively. At this time, the judgement is made by considering that the outputs of all coin detectors are "0" because no coin has been inserted immediately after the setting of the initial state and so long as the signals SDA2' SMR, SCR1 to SCR3 produced by the coin detectors DA2, MR, CR1 to CR3 are "0", codes rOJ are stored in addresses iND1 to iND6 of the auxiliary memory device RAM2 at steps 156, 159, 162, 165 and 168 respectively under the normal state. If there is a code detector output of "1" it is judged that luminous elements or light receiving elements comprising the coin detectors DA1, DA2, MR, CR1 to CR3 are defective, or a coin passageway is logged by coins and codes r2 to r6 are stored as fault signals in addresses iND2 to iND6 at steps 157, 160, 163, 166 and 169 respectively. Then at step 170, the signal ScO from the material discriminator CO is checked, and the condition in which there is no coin judged as the normal state. When the signal SCO is "O", at step 171, a code "O" is stored in the address iND7 of the auxiliary memory device RAM2, whereas when the signal SCO is "1", it is judged that there is a fault and a code r7 is stored in the address iND2 as a fault signal at step 171. Then at step 172, the signal CDA from the control circuit MCC is checked and when it is "0" a code r0 is stored in the address iND8 of the auxiliary memory device RAM2 whereas when the signal CDA is "1", a code is stored in the address iND8 at step 174 in the same manner as above described. As above described, after detecting faults by checking various points to be examined, at step 175, the contents in respective addresses iND1 to iND8 are read out. When all codes are 0 it is judged that there is no fault and the program is advanced to step 176. If there is any one of the codes r 1J through 8D , it is judged that there is a fault and the mode is transferred to the "fault mode". At step 175, if it is judged that there is a fault, the program is advanced to step 179 to send a signal CDEN of rlJ to the control circuit MCC. Then, at step 180 a judgement is made as to whether the timer TIM2 is sending a signal T2 or not. If the signal T2 is not being sent out the program is returned to step 152, whereas when the imer TIM2 sends out the signal T2, the program is advanced to step 181. The processings made at steps 181 to 184 are the same as those of the steps 139 to 142 shown in Fig. 4 except that at step 182 a judgement is made as to whether N is larger than 8 or not. At step 184, the contents of addresses iND1 to iND8 which the information regarding the presence or absence has been stored are read out sequentially by using the contents N of the counter address. If there is any one of the codes r1 to r8 | regarding the fault in any one of the addresses a signal 5DIS2 corresponding to the code is sent out to display the fault by the display unit DIS2 at step 185. The display unit DIS2 sequentially and individually displays the faults at various points to be examined allocated to the coin processing circuit CCC at each definite time, but the faults allocated to the control circuit MCC are displayed simultaneously by a digit corresponding to code #8#. This display unit DIS2 is usually used for the purpose of maintenance, so that it should be understood that it is incorporated into a telephone set. Where it is judged that there is no fault, the mode is transferred to the normal mode, and at step 176 after sending a signal CDEN to the control circuit MCC as a code #O# , the step is advanced to step 177 to accomplish the sorting and the accumulation of the coins. The display of the fault of the coin processing circuit CCC on the side of the control circuit MCC is performed only when any one of the codes r 1I 1¯1 to rAJ of the fault signals is not stored in any one of the addresses iND1 to iNDA of the auxiliary memory device RAM1 of the control circuit MCC so that when a fault occurs on only the side of the control circuit MCC but no fault occurs on the side of the coin processing circuit CCC the fault information on the side of the control circuit MCC is transmitted to the side of the coin processing circuit CCC and judged as a portion of the fault. As a consequence, the signal CDEN is sent to the control circuit MCC from the coin processing circuit CCC whereby the control circuit MCC is prevented from displaying a fault when there is no fault on the side of the coin processing circuit CCC. This operation is repeated during a predetermined interval in the same manner as in the control circuit. After the mode has been transferred to the "normal mode" the processor CPU2 judges the genuine or counterfeit of the coins according to the coin sorting and accumulating programs of the memory device ROM2 and based on the signals SCO' SDA1' SDA2 and SMR generated by the material discriminator CO and the coin detectors DA1, DA2, MR and CR1 to CR3 respectively to send signals SSM1 to SSM3 to the accumulating magnets SM1 to SM3 to energize the same to drive the accumulating levers 4 to 6 thus storing the coins according to their type. After transferring to the "normal mode" the control circuit MCC sends signals SRM, SCM1 to ScM3 shown in Fig. 3 and to the return preventing magnet RM and the collecting magnets CM1 to CM3 in accordance with the signals SCP' SCR1 to SCR3' SCC1 to SCC3t SCK1 to SCK3 from the rate signal receiving circuit CP, and the coin detectors CR1 to CR3, CC1 to CC3 and CK1 to CK3. Consequently magnets RM and CMI to CM3 are energized to preferentially collect the low price coins according to a signal Scp produced by detecting the rate signal and to send a signal Scu to operate the accumulating counter CUT. The hook switch H produces a "0" signal SH when the handset is hooked-on at the time of termination of the speech to return the remaining coin. The confirmation of the coin collection operation and the calculation of the number of the accumulated coins are made by the processor CPU1 of the con rol circuit MCC according to the coin collection program of the memory device ROM1. A signal S@@ is sent to the source circuit PW to apply power for a predetermined interval after hook-on thus continuing the operation of @arious circuits. @igs. 7 and 8 are flow charts caowing varlous steps for detecting faults. Like Fig. 4, @t step @@l shown in Fig Fig. 3 is made and then @he speech C circuit is closed at step 202. Then at steps 203, 205, 207, 209, 211, 213, 215, 217, 219 and 221 outputs SCF' SCB' SCC1' SCC2' SCC3' SCK1' SCK2' SCK3' SCP and STS produced at respective examination points are checked sequentially. When it is judged that any one of the examination points is faulty, a corresponding one of the codes #1# to #A# is stored in one of the addresses iND1 to iNDA of the auxiliary memory device RAM1 at steps 204, 206, 208, 210, 212, 214, 216, 218, 220 and 222. Then the mode is transferred to the "fault mode" without checking the next examination points At step 224, the CPU1 sends a signal CDA of code #1 to the coin processing circuit CCC. At step 225, a signal SDIS1 is sent to cause the displa unit DIS2 to display the not usable state. Then at st 226 the display @nit DIS1 is c@used to display cnly the firstly detected faulty point. Thereafter, at step 227. a signal ST is sent to the alarm tone bend out circuit WT to operate ar alarm. Then the program is advanced to step 203 to repeat the operation described above Where the loop carrent detection signal STS was found to be normal at ste@ 221, the program is advanced to step 228 to send a si @@al CDA to the coin processing circuit CCC as a code rC . Then, at step 229, the signal from the coin process@ng circuit CCC is checked and when it is a code #O# it is judged that there is no fault on the cid@ @f the @@@@ processing cireuit so as to transfer the @@de t@ the "@@@mal mode" to @@@@@te various control @@@@@@@@@ @@@@@@@@@@@ @@ the @@@@rent performances of the @@@ @@@@@@@@@@@@@@@@@@@ @@@ @@@ @@gnal CDEN is judged as cod@ @@@@@@ @@@ @udyed that th@@ - is a fault on the side of the coin processing circuit and the step is advanced t@ step @@@@ to stare c@d@ B i@ the address iNDB of the aux@@@a@v m@m@@@ davice RAM1 as a fault signal. This information is also used as a portion of the "fault mode" so that the step is transferred to step 224, With the processing described above, only when the first fault is recovered the check of the next examination point is performed. Fig. 8 shows a flow chart showing steps of detecting faults on the side of the coin processing circuit CCC in which only the firstly detected fault is displayed like Fig. 7 When the source is connected, the processor CPU2 of the coin processing circuit CCC initializes the control circuit at step 240, and then the states of various examining points that is the outputs SDA1' SDA2' SMR' SCR1' SCR2' SCR3' SCO and SCUA are checked successively at steps 241, 243, 245, 247, 249, 251, 253 and 255. When any one of these outputs is judged a fault, corresponding codes #1# @@ #@# are s@pred in addresses iND1 to iND8 of the auxil@@@y @@@@@y device RAM2 at steps 242, 244, 246, 248, 250, @@ @@@@@@@, a@ the mode is immediately transferred to @@@ @@@@@@@@ mode@ without executing the step of the next ex@@ @@@ng point, @@ step 258, the CPU2 sends a signal CDEN of code #1# to the MCC, and at step 592, a signal 3D1S2 is sent to the display unit DIS2 to display the @@@@@, point. Thereafter the step is returned to step 241 Fig. 9 is a flow chart showing the steps of executing the detection of faults of the control circuit MCC just in the same manner as in Fig. 7. The basic operation of the flow chart is the same as that of Fig. 7, and like parts are designated by the same reference numerals. However, once the mode is transferred to the Hfault mode" this mode is maintained, the display of the faulty point is continued irrespective of the revovering of the fault, and the display is reset only when the power source is disconnected by hook-off. More particularly, during the "fault mode" the step is advanced to step 281 so that CPO1 sends a signal CDA of code #1# to the coin processing circuit CCC and then at step 281 not usable state is displayed by the display device DIS1. Then the step is advanced to step 282 to display a fault by the display unit DIS1. Then at step 283 an alarm tone is sent out from the handset of the SPC via circuit WT and the step is returned to step 280. The programs shown in Figs. 7, 8 and 9 can reduce the number of steps than those shown in Figs. 4 and 6 can simplify the programs as well as the capacities of ROM1 and ROM2. Fig. 10 shows a modification of Fig. 7 and in which as the processings up to the "fault mode" is the same as those shown in Fig. 7 they are omitted. Upon occurence of a fault at any point to be examined the mode is transferred to the "fault mode" so that the CPU1 sends a signal COA of code r 1J to the coin processing circuit and then at step 290 the not usable state is displayed by the display unit DIS1. Then, at step 291 the handset of the speech circuit SPC sends an alarm tone via the alarm tone send out circuit WT. Then the program is advanced to step 292 to check the state of the manually operated switch SWO and when this switch is open the step is returned to step 290, whereas when the switch SWO is closed, at step 293, the relay GS is deenergized to interrupt and restore the speech circuit for the purpose of preventing the dial tone from being mixed with a fault tone as will be described hereinafter. Then the program is advanced to step 294 and a predetermined interval after restoring the speech circuit, the urging tone oscillator in the alarm tone send out circuit WT is driven to cause the handset in the speech channel to send out a fault tone. At this time, the signal CF is code r1 . At this time, the number of fault tones varies as the Cci to CDEN and the faulty portion vary. For example, when signal CF is "1", a tone having a duty ratio is 1 and a period of 2 second is generated once, while when the signal CB is "1", the tone is generated twice. With this system it is possible to identify the faulty point by the number of the generated tone. Fig. 11 is a flow chart of a program wherein the coin processing unit DIS2 of the coin procession unit CCC comprises such luminous elements as luminous diodes for respective bits of the display drive signal SDIS2' This flow chart is analogue to that shown in Fig. 6 except that the steps for displaying the fault is simplified. More particularly, in the flow chart shown in Fig. 6, the contents in the addresses iND1 to iND8 at the auxiliary memory RAM1, are read out and where there is a fault the mode is transferred to the "fault mode" at step 300 the r CPU2 sends a signal CDEN of code 1 > to the control de- vice MCC and then at step 301 the display unit DIS2 displays the faulty point. Thereafter, the program is returned to step 156 shown in Fig. 6 to repeat the same operation. Fig. 12 is a flow chart of a program in which the fault display device of the coin processing circuit CCC is operated by the nonlooking type manual switch SW1. Thus, when the switch SW1 is closed, a display flag FLG is set to perform the same display of a faulty point just in the same manner as in Fig. 6, whereby the drive power of the display unit DIS2 can be reduced. More particularly, by executing the steps corresponding to those shown in Fig. 6 the contents of the addresses iND1 to iND8 of the auxiliary memory devices iND1 to iND8 are read out. If there is a fault, the mode is transferred to the fault mode and the step is advanced to the step 310 shown in Fig. 12, and the CPU2 sends a signal CDEN of code r1 to the control circuit MCC. Then at step 311 a judgement is made as to whether the display flag FLG has been set or not. If the flag FLG is set ("1") the step is advanced to step 313, whereas if the flag is not set the step is advanced to step 312 to check whether the switch SW1 is open or closed. At this time, if the switch SW1 is open, the program is returned to step 152 shown in Fig. 6, whereas if the switch SW1 is closed the flag is set to "1" and the step is advanced to step 313 to check whether the timer TIM2 is producing a signal T2 or not. The succeeding steps 315 to 320 correspond to steps 181 to 186 shown in Fig. 6 so that their description is believed unnecessary. Fig. 13 shows a flow cahrt of a program in which the display of the faults on the side of the coin processing circuit CCC is renewed each time the manually operated not latch type switch SW2 is closed. With this program, whenever the switch is closed a fault is displayed and since this display is continued until the switch is closed again it is convenient to check and repair the faulty points successively. More particularly, when a fault occurs at step 175 shown in Fig. 6, the mode is transferred to the "fault mode". Then at step 320, the CPU2 sends a signal CDEN of code #1# to advance to step 321 at which the not latched type switch SW2 (see Fig. 2) is closed or not. When the switch S2 is open the step is advanced to step 326 whereas if it is closed the step is advanced to step 322, and processings corresponding to those of step 181 through 184 shown in Fig. 6 are executed at steps 322 through 325. When a fault is detected at step 325, it is displayed by the display unit DIS2 at step 326. Thereafter the step is advanced to step 152. Fig. 14 shows a portion of the program of the control circuit MCC in when a point to be examined is judged normal, no check would be made thereafter and when only a point is judged faulty it is checked repeatedly. This modification can decrease the check time than a program in which respective points are checked repeatedly to display faulty points. More particularly, like Fig. 4, the CPU of the control circuit MCC performs initialization and after closing the speech circuit at step 331, the signal SCF from the accumulating counter are checked at step 332. At this time, since the coin may be inserted, if the signal is HOft, the signal SCB from the coin box mounting switch CB is checked at step 333. If the circuit is normal the same points to be examined as those of Fig. 4 are checked. When all points are normal a signal CDA of code #O# is sent to the coin processing circuit CCC. Thereafter, the same process steps as in Fig. 4 are executed. On the other hand when signal ScF of "1" were obtained at step 332, the mode is transferred to the "fault mode" and the step is advanced to step 340. After the CpU1 has sent a signal CDAof Ti to the processing circuit CCC at step 340, a faulty point is displayed by the display unit DIS1 at step 341. Then the program is advanced to step DIS1 to display the faulty point. THen at step 332, the check is repeated. Only after the fault has been cleared, the step is advanced to the next step 333. At this step when a fault occurs, the CPU1 sends a signal CDA of code r1 to display the fault at step 344. Then the step is returned to step 333 to execute the checking operation described above. Although in Figs. 6 to 14, only the side of the control circuit MCC of the coin control circuit was shown, similar execution operation can also be made on the other side. As above described, according to this invention, since the handset is hooked-off self diagnosis is made according to a prescribed program and since a fault is informed to the user by the display unit DIS1 or by sending out an alarm tone when the user hooks off prior to the use of the public telephone set he is immediately informed of the presence or absence of the fault. In addition, display or different faulty points are made independently, the maintainance and inspection of the faulty points can be made very easily. Furthermore, detection of the fault is made concurrently with the closure of a loop circuit closed by hooking-off, breakage or short circuiting of all circuit including telephone lines and a telephone exchange can also be detected. While in the foregoing description, conventional material discriminator CO, the coin detectors DA1, DA2, CR1 to CR3, CC1 to CC3, CX1 to CK3 and MR have been used, sensors exclusively used for examination can also be provided. Although a preloop type telephone set in which a loop circuit is immediately formed when the handset is hooked off, the invention is also applicable to a poit loop type telephone set in which the loop circuit is closed when a coin is inserted. The same operation can also be made when the source is constantly connected to various circuit and when the operations of the processor CPU1 and CPU2 are initiated upon hook-off. However, when the source circuit PW is energized when the handset is hooked off, the power consumption can be reduced. Although it is usual a extinguish the display of the faulty portion and the not usable state by hook-on operation, these displays may be made only for a definite interval. When the not usable state is displayed by a display device provided with such holding means as a permanent magnet or a latch mechanism, the not usable state is displayed when a first user hooks-off so that the next and succeeding users can know the faulty state without hooking off. If desired, instead of providing the display devices DIS1 and DIS2 for the telephone set, a plugin type display device may be used. With this modified display system, the fault at any point can be displayed by inserting a plug into a jack. Instead of utilizing independent control circuit MCC and a coin processing circuit CCC, where a microprocessor is used as processors CPU1 and CPU2, two processors may be used in parallel if their number of terminals and the processing capacity permit. This is advantageous to simplify the peripheral circuits and reduce the cost of manufacturing. Where a large processor is used only one is suffice. As can be noted from the foregoing description, according to this invention, the presence or absence of a public telephone set can be self diagnosed by mere hooking off operation to display fault to the user as well as the faulty point to the maintainance man and operator, thus preventing use of a faulty telephone set. Moreover, as the maintainance man can readily know faulty points by hooking off and closing of the maintenance switch, the faulty point can be confirmed at once, whereby it is possible to make suitable repair without performing any inspection. For this reason, the repair man can judge at once whether he can repair at the field or should bring the faulty telephone set to a repair shop. The same advantage can also be realized in the examination of completed telephone sets in a manufacturing factory. It should be understood that the invention is not limited to the specific embodiments described above and that many changes and modifications will occur to one skilled in the art.

Claims: What we claim is: 1. A public telephone set comprising a thelephone circuit connected to office lines and including a handset hav ing a transmitter and a receiver, a dial tone trans mitter, and a switch adapted to complete a speech loop; a first processing means for sorting coins inserted through a coin slot of the telephone set; a coin box for collecting inserted coins; control means for controlling collection of the inser ted coins passed through said first processing means into said coin box and for controlling origination of said telephone circuit; a plurality of sensors for detecting clogging of a coin passageway extending form said coin slot to said coin box; a second processing means for detecting faults at points to be examined in accordance with the outputs of said sensors; ; a memory device storing a program for supplying an out put signal to said second processing means to cause the same to detect faulty points; and means operated by the operation of said hook switch for controlling start of said second processing means and said memory device. 2. The public telephone set according to claim 1 which further includes means for disabling the telephone set when said second processing means detect a fault. 3. The public telephone set according to claim 2 wherein said disabling means comprises means for closing said coin slot. 4. The public telephone set according to claim 2 wherein said disabling means comprises means for stopping the sorting operation of said first processing means and for discharing the inserted coins to the outside. 5, The public telephone set according to claim 2 wherein said disabling means operates to control said control means for disenabling it to originate. 6. The public telephone set according to claim 1 or 2 which further comprises display means which displays a fault when said processing means detects a fault. 7. The public telephone set according to claim 6 wherein said display means comprises alarm means. 8. The public telephone set according to claim 6 wherein said second processing means comprises means for pro ducing a signal which maintains a fault display over a definite interval. 9. A public telephone set according to claim 6 wherein said second processing means comprises means for operat ing said display means while said handset is being hooked-off. 10. The public telephone set according to claim 6 which further comprises means for continuing said fault dis play after hooking on of said handset. 11. The public telephone set according to claim 1 which further comprises a second memory device which stores an information regarding a detected fault, and another display means for displaying a faulty point according to an output of said second memory device. 12. The public telephone set according to claim 11 which further comprises a manually operated switch for con trolling display of said another display means. 13. The public telephone set according to claim 1 which further comprises a source of power for applying opera ting power to said second processing means, said sen sors and said memory device and means interlocked with said hook switch for controlling said source of power. 14. The public telephone set according to claim 1 wherein said first and second processing means are constituted by discrete processors. 15. The public telephone set according to claim 1 wherein said first and second processing means are constituted by the same processor. 16. The public telephone set according to claim 1 which further comprises another memory device for storing an information regarding a detected fault, and means for producing a tone that can discriminate the detected fault in accordance with the output of said another memory device.

Inventors: HAYAMIZU, HITOSHI, KINOSHITA, TOSHIHARU, KUNIL, SHUJI
Applicants: TAMURA ELECTRIC WORKS, LTD.
Application year: 1979
Main classification: H04M17
IPC codes: H04M17, G07F5, G07F9