Khomenkova et al. Nanoscale Research Letters 2011, 6:172 http://www.nanoscalereslett.com/content/6/1/172 The decomposition process usually completes faster for thinner SRSO layer, resulting in the formation of Si-ncs and SiO2 phase (instead of SiOx one). So, the formation of Si-ncs/SiO2 barrier instead of Si-ncs/SiOx is more probable for thinner layers. Additionally, such layers are more preferable for obtaining better electrical properties. Based on the abovementioned results, the deposition and postdeposition conditions elaborated for single HfO-based layers and for SRSO/SiO2 MLs were adopted for the fabrication of trilayer structures, in which SRSO layer plays the role of charge storage layer. Low thermal budget was applied for the SRSO layers to form Si-ncs accompanied by the conservation of the amorphous nat- ure of HfO-based layer. The electrical properties of the structures HfSiO/SRSO/HfSiO First of all, let us consider electrical properties of HfSiO/SRSO/HfSiO (or SiO2) structures. As it was men- tioned above, these structures can be fabricated at higher temperatures since HfSiO layers conserve their amorphous structure at TS = 400°C to 500°C and TA = 950°C. Thus, the annealing was performed at TA = 800°C to 1,100°C for TA = 15 min in nitrogen flow to obtain the information about memory effect caused by Si-ncs. As one can see from the Figure 3a, C-V curves of Al/HfSiO/Si capacitor structures show a sharp transi- tion from accumulation to inversion, indicating a low density of interface states in the samples under study. The MIS structures show negligible hysteresis loop. In contrast, Al/HfSiO/SRSO/HfSiO/p-Si memory structures exhibit significant counterclockwise hysteresis loop, and Page 5 of 8 the memory window (ΔVfb) was estimated to be approximately 1.7 V from flat-band voltage values. The counterclockwise nature of C-V curves is generally attributed to charge storage through substrate injection mechanism. When a positive bias voltage is applied, electrons are being injected from the inversion layer of the Si substrate into the gate dielectric matrix. When a negative voltage is applied, electrons are ejected back into the Si substrate (equivalent to hole injection from the deep accumulation layer of the substrate), resulting in a shift of the C-V curve towards negative voltages. It is interesting to note that the C-V curves of Al/HfSiO/ SRSO/HfSiO/p-Si memory structures shift towards more positive bias with decreasing frequency, and the shift is more prominent in the low frequency region. The shift is marked by minimal frequency dispersion in accumulation, capacitance indicating minimal influence of series resistance, and dielectric constant variation with altering the measurement frequency. From the inset of Figure 3b, it is noteworthy that the same amount of hysteresis and stored charge was obtained irrespective of the measurement frequency. Hence, the capacitance shift can be attributed to the presence of fast traps and/or border traps (near-interfacial traps), which can have a rapid communication with the under- lying Si substrate [24]. From all these observations, we can ascertain that the observed memory window is pre- dominantly due to the formation of Si-ncs. It should be noted that an annealing at 950°C for 15 min was found to provide the highest ΔVfb value, whereas the increase or decrease of TA results in the essential decrease of ΔVfb. For lower annealing temperatures, this effect can Figure 3 C-V data of single HfSiO layer and HfSiO/SRSO/HfSiO structure measured at different frequencies. Comparison of C-V data for single HfSiO layer (a) and HfSiO/SRSO/HfSiO structure (b) measured at different frequencies. RSi = 12%. Annealing treatment at TA = 950°C, tA = 15 min, N2 flow. Inset of figure (b) demonstrates variation of ΔVfb versus applied frequency at 6 V sweep voltage.