Dehzangi et al. Nanoscale Research Letters 2012, 7:381 http://www.nanoscalereslett.com/content/7/1/381 Page 6 of 9 Figure 7 Schematic operations (a,b) of the SG and DG (c,d) for positive and negative gate voltage. In Figure 8, the schematic profile view of holes loca- tion transmission path and comparison of accumulation mode device with SG and DG device are shown. For the DGJLT the neutral wire locates in the center of the channel and close to the bottom, as shown in Figure 8, c and f. It is worth to mention that in SGJLT, the neutral or depleted wire will be formed not exactly in the center. Due to the specific shape of the device and having only one interface with BOX at the bottom, the neutral wire must be formed near to the bottom of the channel and away from the side gate sidewall (Figure 8, b and e). By further increasing the VDS in the on state, the depletion will be starting near to the drain due to high electric field in this area in region III, and this is the reason for having saturation for the current [51]. The high electric field in the drain gives rise to the full depletion in nano- wire near to the drain area acting as a buffer against the Figure 8 Profile view of holes location transmission path in different devices (modified from [10]). high electric field in the drain, which accordingly, will lead the current to be saturated. However, by negatively raising the gate voltage, it is prob- able to have a little increasing of the current due to some accumulated charges, which were injected from the source (region I) to the channel (red color areas in Figure 7). The drain current mainly flows through a bulk channel. An additional small conduction likely originated from a lightly accumulated channel in sidewalls facing the gates, when the gate voltage is large enough. The influence of the gate on the channel is not very effective to induce an accumula- tion mode due to the device configuration, low doping concentration, and the lack of oxide layer between the gate and the channel. Accordingly, increasing the gate voltage cannot help to make an effective accumulation layer and we do not expect to have the accumulation mode for high gate voltage. Normally in high doping JLTs in on state, after increasing the gate voltage, the device is able to be con- verted into the accumulation mode with significant in- creasing of the current (mostly is not desired to reach) [9,47]. Actually, another reason that we interpret the devices as JLT and not in accumulation mode is the inef- fective negative increasing gate voltage on the channel. In the accumulation mode, in on state condition, the subthreshold current flows through the bulk of the device near the center of the nanowire just like the JLTs (Figure 7a). But the magnitude of this current is less than ten percent of the whole current achievable. By increasing the gate voltage, the majority of the holes are confined in inversion layers at the sidewalls, with marked peaks at the corners (Figure 7d). In the reported and high doping JLTs, we can increase the gate voltage in order to have accumu- lation charge and raise the current after reaching the flat- band. But still, the largest part of the current is due to bulk conduction. The formation of a surface accumulation channel is also observed at high VG. In comparison to the trigate FETs, Fin FETs, gate-all-around (GAA) FETs or