Yap et al. Nanoscale Research Letters 2012, 7:105 http://www.nanoscalereslett.com/content/7/1/105 Waals force interactions [11]. However, no work using the CNT interconnection bump was reported for CNT bump pitches below 150 μm which is a requirement for the future flip chip technology. For the first time, we demonstrated the CNT inter- connection bump joining methodology for pitches smal- ler than 150 μm. The fabrication methodology can be divided into two parts: (1) the growth of CNT bumps on both sides of the substrate using the PECVD approach and (2) the alignment and ‘insertion’ of the CNT bumps into each other using a flip chip bonder machine. Moreover, we discuss the technological aspects of developing the test structure and present the initial DC behavior of small-scale CNT interconnection bumps. Methods Design and fabrication of test structure and CNT bumps The flip chip test structure used in this experiment con- sisted of a carrier and a die structure as shown in Figure 1. The dimension of the carrier is approximately 6 × 5 mm, while the die is 4 × 4 mm. The choice of barrier layer to grow CNTs on Au metallization and the detailed fabrication details were described elsewhere [12]. Briefly, e-beam evaporation was used to deposit Au (1 μm) onto what would serve as the metallization layer while a sec- ond layer of TiN (50 nm) barrier and Ni (15-nm metal catalyst for CNT growth) were deposited onto the prede- fined patterns above the Au metallization using a lift-off technique. The wafers were diced to their specified dimensions and cleaned in deionized water before they were trans- ferred to a PECVD chamber where the CNT growth will Page 2 of 8 be performed. The CNT growth was conducted at 750°C with a plasma power of 85 W for 30 min. The growth pressure was at 6 mbars with a gas ratio of 1:5 (C2H2/ NH3). CNT bumps with a height of approximately 20 μm were obtained as shown in Figure 2. Each of these CNT bumps comprised multiwall CNTs [MWCNTs] with an average diameter of around 100 nm. Subse- quently, a Panasonic flip chip bonder machine (Panaso- nic Factory Solutions Company, Rolling Meadows, IL, USA) was use to perform the die alignment and attach- ment. A load setting of 0.5 kg with a bonding time of 30 s was used as the bonding parameter. No bonding temperature was used in our experiment. In order to compensate for the alignment accuracy of +/-10 μm of the bonder machine, the CNT bumps on the metallization lines were deliberately fabricated to be rectangular. For example, the size of one bump on the carrier is 120 × 100 μm, while that on the die is 100 × 120 μm. This enlarged bump area helped to decrease the occurrence of open circuitry and reduced the connection resistance due to misalignment [13]. In order to improve the mechanical support between CNTs and metal con- tacts, nonconducting adhesives are usually employed [4]. In contrast, we introduced rows of dummy CNT bumps positioned at the sides of the chip and die to increase the densities of CNT bumps. The dummy bumps provided additional mechanical support to hold the weight and leveled the attached die. Another area of concern is that the growth tempera- ture of CNTs used in this work is higher than that in the typical CMOS backend process (400°C) [14]. Lower- ing the growth temperature of the CNTs increased the defects and decreased the degree of crystallinity of the Figure 1 Schematic of the flip chip test structure used in this experiment. (a) The carrier and (b) the die designs. Au metal is used as the metallization material and Ni as the catalyst for the CNT growth. At the sides of each structure, two rows of square patches are also patterned and deposited with the Ni catalyst on Au for CNT growth. These additional CNT bumps serve as dummy bumps to increase bump densities for mechanical supports.