Khomenkova et al. Nanoscale Research Letters 2011, 6:172 http://www.nanoscalereslett.com/content/6/1/172 The annealing temperature was further increased to 950°C (keeping the same annealing time as 15 min), and significant charge storage was achieved at relatively lower sweep voltages. The frequency dependent C-V curves were found to be almost constant within the fre- quency range of 1 MHz to 10 kHz. All of them show a sharp transition from accumulation to inversion region, indicating less number of interfacial traps. The memory window value increases from ΔVfb = 1 V to ΔVfb = 7 V with increasing the sweep voltage from ± 1 to ± 7 V. It is worth noting that with annealing temperature increas- ing from 800°C to 950°C, the ΔVfb value increases from 2.3 to 6.8 V at a sweep voltage of ± 6 V. This can be due to the increase of the Si-ncs number and to the bet- ter performance of surrounding SiO2 matrix. The latter favors the formation of the higher barrier for carrier tunneling from gate contact. However, annealing at TA > 950°C results in a decrease of ΔVfb value to 0.05 V (Figure 4f). This can be caused by complete oxidation of SRSO layer without formation of Si-ncs and by Si out- diffusion from the SRSO layer through the HfO2 layer [22,23]. Considering the results presented above, the investiga- tion of the structures by means of ATR and XRD meth- ods was performed to obtain the information about transformation of SRSO layer as well as about the nat- ure of HfO2 tunnel layer. In the last case, this was impacted by the fact that an annealing at temperatures higher than 800°C could not favor the stability of HfO2 amorphous structure. It is more probable that the crys- tallization of HfO2 layer occurred. However, the ATR spectra did not reveal any formation of monoclinic HfO2 phase, since HfO vibration band was found to be featureless. At the same time, the XRD study showed that at TA > 900°C, the formation of tetragonal HfO2 phase occurs, while at lower TA, the tunnel layer con- serves its amorphous structure (not shown here). How- ever, the determination of Si-ncs by this method met some difficulties due to overlapping of the peaks from tetragonal HfO2 phase and Si-ncs. The TEM observation of the abovementioned samples is currently under inves- tigation to get a clear picture about the evolution of Si- ncs and HfO2 layers. However, we can conclude that for TA = 950°C, the memory effect is predominantly due to Si-ncs formation. Conclusion The application of pure HfO2 and HfSiO layers fabri- cated by RF magnetron sputtering as alternative tunnel layers for high-k/Si-ncs-SiO2/SiO2 memory structures is demonstrated. The effect of the Si incorporation of the electrical properties of high-k layers was investigated. It is shown that there is an optimal Si content allowed to obtain desirable C-V parameters for single layers. Page 7 of 8 The Si-rich SiO2 layers were used as charge storage layers, and their properties were studied versus deposi- tion conditions and annealing treatment. The C-V mea- surements of fabricated stack structures show that with specific deposition conditions and annealing treatment, a large memory window (about 6.8 V) is achievable at a sweeping voltage of ± 6 V, indicating the utility of these stack structures for low-operating-voltage NVM devices. Acknowledgements This work is supported by the French National Research Agency (ANR) through the Nanoscience and Nanotechnology Program (NOMAD Project no. ANR-07-NANO-022-02) and, for one of the author (L.K.), by the Region Basse Normandie through the CPER project - Nanoscience axe (2007-2013). Author details 1CIMAP, UMR CNRS/CEA/ENSICAEN/UCBN 6252, Ensicaen, 6 Bd Mal Juin, 14050 Caen Cedex 4, France 2InESS/UDS-CNRS, 23 rue du Loess, 67037 Strasbourg, France Authors’ contributions LK designed the study, fabricated the samples investigated and performed post-fabrication treatment, carried out the characterization studies and analyzed the results, and prepared the draft of the manuscript. BSS carried out electrical characterization of the samples and performed the analysis of the results. AS and FG participated in the coordination of study. All authors read and approved the final manuscript. Competing interests The authors declare that they have no competing interests. Received: 23 September 2010 Accepted: 24 February 2011 Published: 24 February 2011 References 1. Aaron VY, Leburton JP: Flash memory: towards single-electronics. IEEE Potentials 2002, 21:35. 2. Tiwari S, Rana F, Hanafi H, Hartstein A, Crabbe EF, Chan K: A silicon nanocrystals based memory. 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