Dehzangi et al. Nanoscale Research Letters 2012, 7:381 http://www.nanoscalereslett.com/content/7/1/381 N A N O E X P R E S S Open Access Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography Arash Dehzangi1*, A Makarimi Abdullah2, Farhad Larki1, Sabar D Hutagalung2, Elias B Saion1, Mohd N Hamidon3, Jumiah Hassan1 and Yadollah Gharayebi4 Abstract The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal. Keywords: Atomic force microscopy, Junctionless transistors, Local anodic oxidation, Silicon-on-insulator, Double gate, Single gate junctionless silicon nanowire transistor Background The aggressive trend of scaling transistors requires a new and more effective device to catch up with this rapid trend for modern transistors. Several innovations in fabrication process such as high κ dielectrics [1], metal gate electrodes [2], stressors [3], and new transis- tor architectures based on silicon-on-insulator (SOI) such as Fin field-effect transistors (FETs) [4], multigate FETs [5], omega-gate FETs [6], gate-all-around FETs [7], or developed non-epitaxial raised metal Schottky source drain [8] have been introduced. In the recent years, junc- tionless transistors (JLTs) appeared to be the promising alternative for new generation of transistors [9]. All existing transistors contain semiconductor junctions. Contemporary transistors with ultrasmall size need * Correspondence: arashd53@hotmail.com 1Department of Physics, Faculty of Science, Universiti Putra Malaysia, Serdang, Selangor 43400, Malaysia Full list of author information is available at the end of the article ultrasharp doping concentration gradients in junctions. The doping must switch from ultra high concentration n-type to p-type along the very small area in size of some nanometers, which imposes severe limitations on the processing thermal budget and requires the develop- ment of costly millisecond annealing techniques. In JLT the doping concentration in the channel source and drain is uniform with high concentration profile for the channel in order to have a reasonable amount of current flow when the device is turned on [10]. The lack of dop- ing concentration gradients provides the smaller size and cancels the need for costly ultrafast annealing techniques. In the last two years, the research in JLTs was focused in design and property [11-13], simulation [14-16], high temperature performance [17], and new fabrication method with higher mobility and better per- formance [18-20]. The principle of atomic force microscopy (AFM) nanolithography, using local anodic oxidation (LAO) on © 2012 Dehzangi et al.; licensee Springer. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.