Sahu et al. Nanoscale Research Letters 2011, 6:178 http://www.nanoscalereslett.com/content/6/1/178 centers is an essential requirement for increasing the radiative yield without affecting the emission mechan- ism. In this regard, some previously annealed samples are subjected to an additional rapid thermal annealing in forming gas at 900°C for 1 min. Figure 5d shows the PL spectra of the sample S2, which has been subjected to annealing at 1100°C in N2, and subsequently in form- ing gas (10% H2 + 90% N2). The PL peak intensity increases about 28% due to this additional forming gas annealing step, indicating passivation of some non-radia- tive recombination centers. It is noteworthy that the overall behavior of the PL band remains unchanged, indicating no change in the emission mechanism. Opti- mization of this hydrogen passivation process is cur- rently under investigation. C-V and G-V measurement results Figure 6a,b shows the typical high-frequency (100 kHz) C- V curves of Al/Si3N4/SRSN/SiO2/Si (MNNOS) capacitors with different excess amount of Si (33 and 25 at.%), and subjected to a post-thermal annealing at 1100°C in N2 ambient. All the capacitors show well-defined accumula- tion, depletion, and inversion regions in the C-V curves. Except S4 (33 at.% of excess Si), all other capacitors exhibit a sharp transition from accumulation and depletion to inversion, indicating the presence of less number of inter- face traps in the samples. In contrast, small irregularities or smear-out effect have been observed in the depletion region capacitance of sample S4, indicating the presence of some border (near-interfacial) traps in the MNNOS capacitor. All the capacitors show clockwise hysteresis, indicating a net positive charge (hole) trapping in the MNNOS capacitors [43]. The clockwise nature of C-V curves is generally attributed to charge storage through gate-injection mechanism. In fact, owing to rather thicker SiO2 interfacial layer, the substrate injection of carriers has been suppressed, which otherwise gives counterclockwise hysteresis loop. Under the influence of a positive bias vol- tage, holes are injected into the SRSN film from the top Al Page 7 of 10 gate electrode, creating an abundance of holes in the SRSN charge-trapping layer. This promotes the injection of holes from the SRSN layer to the citrated Si-nps and/or defects inside the SRSN matrix, leading to a net hole trap- ping. Upon applying a negative bias voltage, the holes are subsequently flushed out (equivalent to injection of elec- trons) from the SRSN charge-trapping layer to the gate electrode, resulting in a negative flatband voltage shift and clockwise hysteresis loop. In addition, the presence of mobile ions and/or dielectric polarization can always give rise to a clockwise hysteresis. However, such a large amount of hysteresis window obtained at room tempera- ture cannot be attributed to mobile charges, as their con- tribution is negligible at room temperature. In addition, the presence of mobile ions in the dielectric films leads to clockwise hysteresis, but no flatband shift in the positive sweep direction. This is inconsistent with the above results of C-V hysteresis, where a huge positive shift of flatband voltage has been noticed. Thus, the observed memory win- dow can be safely assigned to charge storage in Si-nps and/or deep traps inside SRSN matrix. Contrary to what was expected, the sample S4 with the highest content of Si excess exhibits the lowest hysteretic effect, even though EFTEM images clearly indicate the existence of Si-nps. It is speculated that the reduced memory window is due to lateral charge loss through leakage paths introduced by insufficiently localized Si-nps and defect sites. It has been observed that the sample S2 with 25 at.% of Si excess exhi- bits the highest hysteretic effect, even though no Si-np was detected in our EFTEM analysis. An estimated memory window of 4.45 V was obtained at a sweep voltage of ± 8 V. The memory effect in the absence of Si-nps can be attributed to charge storage in deep level traps in the SRSN matrix and/or excess of Si at SRSN/SiO2 interface. Such type of charge storage has been obtained for SONOS-type memory structure having a SRSN charge- trapping layer [44,45]. Different models of electron and hole traps have been proposed for silicon nitride films. First, the model of dangling Si bonds as a capturing center Figure 6 (Color online) High-frequency (100 kHz) C-V characteristics of Al/Si3N4/SRSN/SiO2/Si (MNNOS) memory capacitors of (a) the sample S4 containing 33 at.% of excess silicon, (b) the sample S2 containing 25 at.% of excess silicon, (c) evolution of memory window (calculated from flat-band shifts) versus excess silicon at two different annealing temperatures (1000 and 1100°C).