Dehzangi et al. Nanoscale Research Letters 2012, 7:381 http://www.nanoscalereslett.com/content/7/1/381 SOI, has been described for the first time by Snow and Campbell et al. [21,22], and they astutely expanded AFM nanolithography for fabrication of nanostructures. Ionica et al. [23] have remarkably reported the electrical char- acteristics of the devices made by AFM nanolithography. In the recent years, some new works have been per- formed to improve the method of AFM nanolithography [24,25]. However, the lack of sufficient explanation or in- terpretation for the behavior of these structures is still an interesting issue and worth for further investigation. In fact, fabrication of nanotransistors by AFM nanolitho- graphy with similar structure has been developed with prominent result in the last decade, but recent rising of the JLTs theory and fabrication can bring up the AFM nanolithography as the extra alternative. We already reported the fabrication of the p-type single gate (SG) JLT device with a simple structure, low doping concen- tration, and no gate oxide layer [26-29]. The most im- portant advantage of AFM nanolithography is that it impedes damage of the crystalline structure of silicon due to highly energetic electrons which are normally introduced to the structure by techniques such as elec- tron beam lithography. In this paper we report the fabrication of a double gate structure with improved method by implementing the advantages of AFM nanolithography in contact mode with a simple structure. We used the SOI technology to ensure a very sharp interface top silicon layer-silicon di- oxide and used buried oxide layer as an etch stop layer during fabrication. Low doping concentration p-type SOI was used in order to have less scattering effect and low ‘off ’ current. Also, the electrical property of both double gate (DG) and single gate JLT will be compared; the charge transmission, according to the JLTs’ principal with the glance of accumulation mode transistors func- tion, will be investigated. Methods Device fabrication The AFM nanolithography process was performed by using scanning probe microscope machine (SPI3800N/ 4000, SII Nanotechnology Inc., Chiba-shi, Chiba, Japan) in contact mode. Low doped (1015 cm−3) p-type (100) SOI wafer was prepared using Unibond™ (Unibond International Ltd., Uxbridge, Middlesex, UK) processed with a 145-nm buried oxide (BOX) thickness, 90-nm top Si layer thickness, and a resistivity ρ of 13.5 to 22.5 Ω cm used as the substrate [30]. Prior to use, the SOI wafer was cut into small sizes (1 × 1 cm), cleaned by modified standard Radio Corporation of America clean- ing process and then dipped in hydrofluoric acid (HF) (1% water solution) for 30 s in order to replace the Si-O bonds by low energy Si-H bonds. After sample prepar- ation, AFM nanolithography with LAO method was Page 2 of 9 applied to provide etching of the stop layer on top of SOI substrate. Finally, KOH anisotropic etching and HF oxide removal etching completed the fabrication of de- vice (Figure 1). Local anodic oxidation An AFM tip (Cr/Pt conductive coating) was used to draw oxide patterns on top of the SOI substrate. The hydrogen atoms can be locally removed on the surface of the substrate with AFM when a negative tip voltage provides a local oxidation by means of field-enhanced oxidation process. The voltage pulse was applied to form a liquid bridge between the tip and the sample; mean- while, another voltage was applied to the silicon sub- strate to induce nano-oxidation, and the absorbed water layer on the surface provided the required electrolyte under this ambient condition. During the oxidation, the force reference was −0.1 N, also the writing speed, scan speed, and applied tip voltage were held at 0.5 μm/s, 1.0 μm/s, and 9 V, respectively (all parameters were opti- mized). All mentioned parameters with the relative hu- midity percentage of 65% to 68% provided the thickness of 3 nm for oxide layer, which is an acceptable range, and the patterned structure is well-shaped. The air am- bient humidity is essential to achieve the oxidation [31,32]. In Figure 2, the LAO process is schematically shown. Figure 3a,b,c,d shows the DG and SG structures after the LAO with the best gate symmetry and the smallest re- producible dimensions we had achieved. In the SG struc- ture the nanowire moved towards the side gate to avoid of leakage current appeared in the previous work [27]. Wet etching process KOH wet etching is a very significant part in the fabrication of SG and DGJLT. In fact, having contamination, ill-etched, or over etching structures were hardly avoidable in wet Figure 1 Schematic of SG-JLSNWT fabrication steps.