Defforge et al. Nanoscale Research Letters 2012, 7:375 http://www.nanoscalereslett.com/content/7/1/375 electrical characterizations demonstrated a low resist- ance of the conductive paths (32 mΩ/via). These values are coherent with the copper theoretical resistivity and explained by the slow copper growth into the macro- pores. This study proves the feasibility of TSV formation employing electrochemistry for the two main steps of the process (i.e., the pores etching and their filling with conductive material). Indeed, the ordered macropore electrochemical etching technique becomes a viable, low-cost alternative to DRIE for 3D integration. Abbreviations 3D: three dimensional; DRIE: deep reactive ion etching; HAR: high aspect ratio; JGB: Janus Green B; PEG: polyethylene glycol; POE: polyoxyethylene lauryl ether; SEM: scanning electron microscope; SiO2: silicon dioxide; SPS: sodium sulfopropyldisulfite; TSV: through-silicon via. Competing interests The authors declare that they have no competing interests. Author details 1Université François Rabelais de Tours, GREMAN UMR CNRS 7347, 16 Rue Pierre et Marie Curie, BP 7155, Tours Cedex 2 37071, France. 2Université François Rabelais de Tours, Laboratoire de Physico-Chimie des Matériaux et des Electrolytes pour l'Energie, E.A. 6299, Parc de Grandmont, Tours 37200, France. Authors' contributions TD wrote the manuscript and deposited the copper. TD and MD electrochemically etched the silicon substrate. JB performed the electrical characterizations of the TSV. FT-V and GG participated in the conception of the study and revised the manuscript. All authors read and approved the final manuscript. Received: 24 April 2012 Accepted: 12 June 2012 Published: 9 July 2012 References 1. Ramm P, Klumpp A, Merkel R, Weber J, Wieland R, Ostmann A, Wolf J: 3D system integration technologies. Mat Res Soc Symp Proc 2003, 766:E5.6.1–E5.6.12. 2. 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