Peng et al. Nanoscale Research Letters 2012, 7:559 http://www.nanoscalereslett.com/content/7/1/559 Recently, the existence of conductive bridges/paths has been confirmed and observed by different methods. Pan et al. used transmission electron microscopy (TEM) to ob- serve the formation of the conductive bridge/path after a couple of set/rest processes [8-12]. Takimoto et al. used conducting atomic force microscopy to locate the forma- tion of the conducting filament [13,14]. However, these methods for the observation of the conducting filament formation can only be considered as ex situ observations. Some controversies regarding resistive switching mechan- isms remain, and the underlying physical mechanism of the resistive switching is still not fully understood. Consequently, a direct observation of conductive bridge/path formation in real time is imperative. In this regard, we demonstrate a real-time observation of a con- ductive bridge/path formation in the Au/ZnO/Au system inside the TEM to clarify how the conducting bridge/path formed between two electrodes, including set and reset processes when the resistance is changed from high resist- ance to low resistance states in the Au/ZnO/Au system. To realize this goal, it is important to directly observe in situ images in real time [15-17]. The switching mechan- isms of the Au/ZnO/Au device in ultrahigh vacuum and air conditions were investigated for comparison. Methods Fabrication of TEM chip for in situ observation Si substrates were cleaned by standard processes. Si3N4/ SiO2 thin film layers with thicknesses of 80/20 nm were deposited on both sides of a Si substrate with a low- pressure chemical vapor deposition (LPCVD) system at 780 °C in a vacuum of 350 mTorr. Position of the mem- brane area was defined by photolithography on the back side of the chips, and the Si3N4 and SiO2 layers were etched away by reactive ion etching process to expose the Si sub- strate, followed by KOH solution etching from the back side to fabricate a freestanding Si3N4 membrane which is transparent to electron beam in TEM. The etching time and temperature are kept at 1 hr and 80 °C, respectively. After etching, we cleaned the sample with D.I. water. A 25-nm-thick ZnO layer was then deposited on the top side of the chips by radio frequency magnetron sputtering at room temperature with pressure kept at 10 to 6 Torr and with an Ar/O ratio of 0.1. Subsequently, Au contact elec- trodes with a gap approaching 100 nm were fabricated by electron beam lithography with poly(methyl methacrylate) (PMMA) as photoresist, followed by metal deposition, and lift-off process. Finally, the TEM chip was loaded into the specially designed TEM holder, with which a bias can be directly applied through the Au electrodes inside the TEM. Measurements and characterizations Crystal structures of the ZnO films was characterized with a Shimadzu X-ray diffractometer (XRD; Shimadzu, Page 2 of 6 Kyoto, Japan), and grazing incident angle XRD with Cu Ka (λ = 0.154 nm) as the radiation source. In situ oper- ation of the ReRAM devices, including forming, set, and reset processes, was investigated in an ultrahigh vacuum TEM (JEM-2000 V, JEOL Ltd., Tokyo, Japan) with a spe- cially designed holder which is capable of applying elec- tric current directly on the electrodes. Morphologies of the device and microstructures were investigated by field-emission scanning electron microscopy (FE-SEM; JSM-6500 F, JEOL) and transmission electron micros- copy (JEM-3000 F, JEOL). The I-V characteristics of the MIM structure were measured with a Keithley 4200 semiconductor parameter analyzer (Keithley Instruments Inc., Cleveland, OH, USA) at room temperature in air. Results and discussion Figure 1 shows the schematic fabrication processes of in situ TEM chip for the observation of the conducting bridge formation (See ESI in Additional file 1 for more details). Si3N4/SiO2 thin films with thicknesses of 80/ 20 nm were deposited on one side of a Si substrate by a LPCVD system. Position of the membrane area was defined by photolithography on the back side of chips. Si3N4 and SiO2 thin films were then etched away by re- active ion etching processes to expose the Si substrate for the subsequent KOH etching. A 25-nm-thick ZnO layer was then deposited on the top side of the chips by radio frequency magnetron sputtering at room temperature in order to obtain a smooth layer. X-ray spectrum with a sharp peak corresponding to (002) plane indicates that the ZnO film is of good crystallinity (ESI, Additional file 1: Figure S1). Au contact electrodes with a gap of approximately 190 nm were fabricated by electron beam lithography with PMMA as photoresist, followed by metal deposition and lift-off processes (Figure 1c). The overall configuration of the chip is shown in Figure 1d, for which the electron beam in the TEM can penetrate through the ZnO and Si3N4 layers to form images. The fabricated chip was loaded into the in situ TEM holder with a controllable bias applied in- side the TEM, as shown in Figure 1e. The corresponding SEM and TEM images of the Au/ZnO/Au device are shown in Figure 1f and inset, respectively. For the ReRAM operation, the bias is applied to form the conducting bridge to turn the device from HRS to LRS, which is called a forming process. Figure 2a,b shows the TEM images of the Au/ZnO/Au device before and after the forming bias was applied in an ultrahigh vacuum <10−9 Torr. The corresponding I-V behaviors are shown in Figure 2c. The current increases with the increasing of bias and reaches a maximum current of approximately 1.8 mA at a bias of approximately 2 V, while a sudden breakdown of the current occurs once bias is >2 V. The high conductivity of the ZnO film