Sahu et al. Nanoscale Research Letters 2011, 6:178 http://www.nanoscalereslett.com/content/6/1/178 [46,47]. Second, the presence of three fold coordinated negatively (K- center) and positively (K+ center) charged silicon atoms as traps for holes and electrons, respectively [48], and third to Si-Si bond or nitrogen vacancy possibly being responsible for electron and hole localization [49]. According to Robertson and Powell [36], SRSN films sub- jected to high-temperature annealing contain a significant amount of ≡ Si° defects, which behave as memory trap because it is amphoteric, deep, and energetically aligned with the gap of Si. These traps can trap either electrons or holes during programming, and release them during erase process. However, the trapping phenomena in silicon nitride are rather complicated and detailed investigation is in progress. As evident from Figure 6a,b, the conductance peak position in the samples are situated close to the flat- band voltage of the C-V curves. The separation of the con- ductance peak position during bidirectional sweep agrees well with the memory window values obtained from C-V measurements. Except the sample S4, all other samples exhibit single conductance peak in both forward and reverse sweep directions, indicating single electron char- ging effect. However, the sample S4 exhibits two peaks in bidirectional sweep, indicating sequential trapping and detrapping of two electrons [50]. The difference in peak heights during forward and reverse sweep can be attribu- ted to different charge states of the traps in both sweep directions. Thus, we can conclude that the charge storage properties of SRSN layers can be enhanced by suitably tuning the Si excess content and annealing conditions. Fig- ure 6c exhibits the variation of memory window for all the samples at two different annealing temperatures of 1000 and 1100°C. In our study, 1000°C was found to be the optimum annealing temperature for getting larger charge storage capacity in the MNNOS memory capacitors. For a better understanding of the results obtained from C-V measurements, frequency-dependent G-V measurements were further carried out in the fre- quency range of 10-500 kHz. Frequency-dependent G- V curves for the sample S2 are shown in Figure 7. G-V measurement is considered to be a more sensitive approach than C-V measurement technique, and provides the dynamic information related to trap density. In fact, conductance is related directly to the energy loss in response to the applied ac signal during the capture and emission of charge carriers by interface states. This method is quite effective even at high frequencies. The G- V curves exhibit a small parallel shift of 0.2 V along the voltage axis on decreasing the frequency from 500 to 10 kHz. This negligible shift of G-V curves can be due to the presence of a small quantity of fast traps in the memory capacitor. However, our frequency-dependent C-V curves remain almost constant with a change in measurement frequency (not shown here). Moreover, no distortion in C- V characteristics due to slow traps and/or large surface Page 8 of 10 Figure 7 (Color online) Frequency-dependent G-V characteristics of Al/Si3N4/SRSN/SiO2/Si (MNNOS) structure containing 25 at.% of Si excess in the range 10-500 kHz. density (flat step) was observed in the samples with a change in frequency. It was noticed that the full width at half maxima (FWHM) of the conductance peak is small and almost constant in the frequency range of 10-500 kHz, indicating that the hysteresis and conductance peak are of the same origin. Furthermore, the conductance peak, where energy loss is maximum, increases with mea- surement frequency as more interface states at higher fre- quency could not respond to the change in ac signal resulting in a greater loss. From the above discussions, it can be ascertained that the charge storage is predomi- nantly in deep traps inside the SRSN matrix and at SiO2/ SRSN interface. Conclusions In summary, a wide range of a-SiNx:H films with an excess of silicon (20 to 50%) with MW-PECVD system under the flows of NH3 and SiH4 have successfully been deposited. In addition, the silicon-rich a-SiNx:H films were sandwiched between a bottom thermal SiO2 and a top Si3N4 layer, and subsequently annealed within the temperature range of 500-1100°C in N2 ambient. A strong visible PL at room temperature has been observed for all the stack structures. The PL in the stack layers are predominantly due to defect states within the bandgap of silicon nitride. The highest PL intensity was obtained at an annealing temperature of 700°C. The decrease in PL intensity after 700°C is due to breaking of hydrogen bonds and effusion of hydro- gen, which creates non-radiative centers. Amorphous Si quantum dots with an average size of about 3 to 3.6 nm were formed for the silicon nitride layer containing 33 at.% of silicon excess at an annealing temperature of 1100°C. The SRSN layer containing 25 at.% of excess silicon exhibits the highest memory window of