Khomenkova et al. Nanoscale Research Letters 2011, 6:172 http://www.nanoscalereslett.com/content/6/1/172 Page 6 of 8 be due to noncompleted phase separation within the SRSO layer. For higher annealing temperatures, com- plete oxidation of SRSO layer should occur. Besides, the phase separation inside HfSiO layers can occur as it was demonstrated in [25]. HfO2/SRSO/SiO2 structures The trilayer structures with the fixed thicknesses of tunnel (4 nm) and control (10 nm) layers and different thick- nesses of SRSO layer (from 2 to 4 nm) were studied versus annealing treatment. As it was shown above, for all of them, the formation of Si-ncs is expected upon annealing. Going further, it is worth to note that the best electrical properties were demonstrated by the structures with 2-nm-thick SRSO layers, and they will be discussed below. Figure 4a shows the C-V curves of HfO2/SRSO/SiO2 stack structures annealed at 800°C for 15 min in the MIS structure taken at various sweep voltages. The hys- teresis memory window increases from approximately 1 V to approximately 6 V with increasing the sweep vol- tage from ± 4 to ± 10 V. The counterclockwise nature of the hysteresis loop indicates net electron trapping in the MIS capacitor. However, frequency-dependent C-V curves show nonparallel shifts with varying measure- ment frequency, indicating the presence of some interfa- cial traps and/or border tarps in the MIS capacitor. We speculate that the charge trapping is due to near interfa- cial traps and excess of silicon at SRSO/SiO2 and SRSO/ HfO2 interfaces rather than Si-ncs. Figure 4 C-V characteristics of annealed HfO2/SRSO/SiO2. C-V characteristics of HfO2/SRSO/SiO2 annealed at 800°C for 15 min (a, b) and at 950°C for 15 min (c, d) measured at 1 MHz (a, c) and versus frequency measured at 6 V sweep voltage (b, d). (e) The variation of ΔVfb versus sweep voltage for two annealing temperatures; (f) the comparison of C-V curves measured at 1 MHz versus annealing temperature. Annealing time is 15 min for all the figures.