Defforge et al. Nanoscale Research Letters 2012, 7:375 http://www.nanoscalereslett.com/content/7/1/375 density TSV, a low-doped (ρ > 0.5 Ω cm) n-type (100)- oriented substrate can be employed. For example, HAR macropores (aspect ratios can reach 250 to 300) [9] with ultra-high densities (>108 pores/cm²) [10] can be achieved homogeneously on 6-in. wafers [11]. These values are much higher than those reached by DRIE and very promis- ing for the future TSV density increasing needs. Most of the time, TSV are filled with copper because this metal owns one of the highest electrical conductiv- ity. Copper thin films are often obtained by electrochem- ical deposition. This technique is a low-cost way to achieve large area, high conductivity copper layers. Cop- per electrochemical deposition into through holes is thus studied for almost two decades because conformal de- position into confined media is much more difficult than on flat surfaces [12]. The chemistry of the electrolyte needs to be adapted to this constraint. Thus, several additives are commonly added to the H2SO4-CuSO4 electrolytic mixture during the copper deposition to en- sure void-free, high conductivity copper filling even into HAR structures [13]. The first part of the present paper describes the different strategies to achieve conductive TSV from ordered macroporous silicon. Then, the conditions of HAR macro- pore array etching by silicon anodization were developed. After anodization, ‘almost’ through-silicon macropores were locally opened by backside photolithography. The through-silicon macropores were then filled with copper. Finally, these TSV were electrically characterized to deter- mine the resistance of the conductive paths. Page 2 of 7 Different strategies of conductive through-silicon via localization To achieve localized TSV, four strategies can be explored. Either the macropores or the seed layer can be localized on the sample in order to select the conductive regions. The simplest way would be the ordered macro- pore array localization (such as DRIE technique) because this technique leads to the formation of local, through- silicon macropore regions depending on the mask design (cf. Figure 1a). After anodization, a simple backside seed layer deposited on the whole surface of the wafer ensures the metal electrochemical bottom-up filling (Figure 1b,c) [14]. However, this process is very difficult to perform be- cause of macropore localization issues. Inert masking layers may be employed to protect some areas against the porous silicon formation, but over-etching is observed at the edge of unmasked regions [15,16]. A second option could be the formation of macropore array on a whole sample and the localization of copper electrolyte penetration in the macropores by photolithog- raphy as described by Föll et al. [17]. Figure 2 illustrates the process flow. After the through-silicon macropore etching (Figure 2a), a masking layer is locally deposited on the pores to stop the penetration of the electrolyte (see Figure 2b). During the copper electrochemical de- position, the macropores in contact with the electrolyte are selectively filled with copper (Figure 2c). After the pore filling, the backside seed layer can be removed by a polishing technique (Figure 2d). The main issue of this process is the technique employed to locally mask a Figure 1 Selective TSV formation by macropore array localization. (a) Through-silicon macropores are locally etched by electrochemical etching through an inert mask. (b) The seed layer is deposited on the backside of the substrate. (c) The macropores are filled with copper by bottom-up electrochemical deposition.