Dehzangi et al. Nanoscale Research Letters 2012, 7:381 http://www.nanoscalereslett.com/content/7/1/381 have the same trend compared to the reported cases fabri- cated by AFM nanolithography with nearly similar struc- ture [21,39,40]. In fact, in none of the reported cases, the devices were used as the pinch off device. Normally, high doping SOI was implemented and was never checked to use in a reverse bias to investigate the pinch off effect. Also in our work, we do not have remarkable increase in the current due to the negative gate voltage, while some previous works have shown a higher rate for increasing the current under the gate voltage (mostly positive voltage for the n-type case), and also a higher current value (due to the higher doping concentration). In Figure 6a, we can recognize the effect of the gate on channel in a DG structure which is more effective than SG due to the asymmetry of SG. In the DG struc- ture the pinch off effect was achieved in VG = +2, while this value cannot provide the same current value in SG. This required higher voltage to approach pinch off effect in SG structure which was in VG = +3 V (Figure 5). Figure 6b shows the drain conductance for SG and DG structures under the different gate voltage. By increasing the gate voltage, the drain conductance for both struc- tures will be decreased. For comparing DG structure to SG device, we have a more effective gate voltage in the channel approaching the pinch off effect (off state) with lowest drain conductance, which is consistent to the out- put characteristics and our expectation about the DG structure. The trend for drain conductance is the same with MOSFETs [41] and JLTs [42], yet the slope is smal- ler here which can be explained by low doping concen- tration and current value. Subthreshold swing Although the SS value is relatively higher than the best value in single crystal silicon devices [15] and recent JLTs [20,43,44], it is still comparable with the lowest reported value of vertical silicon nanowire array devices [45]. In general, the degradation of SS is due to the increase in the interface state density, decrease of oxide capacitance, and increase in the doping con- centration of metal oxide silicon transistor’s channel [46]. However, in our work the interface state density probably cannot play an important role since we have only one interface with the channel (channel/BOX interface), and the current value is low. The most im- portant reason for higher SS value in our case could be explained by the lack of oxide layer between the gate and the channel. It lacks the fixed potential drop in cross section of the nanowire (perpendicular to the current flow), which is necessary for inducing sufficient potential to change current linearly with the gate volt- age [44]. In SGJLT device, the asymmetry of the gate location provides higher SS value compare to DGJLT device with the symmetric gate locations. Page 5 of 9 Model description In recent reports on experimental JLTs [18,47], we did not encounter any case of on state condition under the zero gate voltage due to having an opposite doping concentra- tion for the gate and the channel, unless for the simulation cases and for very small gate lengths [48]. The charge transmission in DG and SGJLT operates quite differently from the conventional MOSFETs and also slightly differ- ent from the JLT description in recent literature. The devices are working in on state for nonzero VDS and VG = 0 V. The reason can arise from the fact that the field effects from the different work function of the gate and channel cannot cause the device to be turned off at VG = 0 V due to the same doping concentration of the channel and gate contact, and no oxide layer for the gate. Basically, regardless of the gate work function differ- ence between the gate electrode and channel, JLTs are ‘gated resistor’ which is in the on state at VG = 0 V [16]. According to the JLT’s principal, when the device is turned on, it approaches the flat band condition. It ba- sically behaves as a resistor, and the electric field perpen- dicular to the current flow is equal to zero in the ‘bulk’ channel. In fact, as the advantage of our fabrication method, the AFM lithography keeps the surface and the body of the upper Si layer of the SOI intact and un- touched. So we expect to find more bulk property, for example, higher mobility and less surface scattering ef- fect for the channel under the gate. Immediately after applying VSD, the device goes to an on state. The on current is controlled by the semiconductor doping concentration and not by the gate capacitance. The operation of devices is outlined in Figure 7, and the three regions I, II, and III are denoted. The structures are a gated resistor turned off by depleting the channel (region II), when essential positive gate voltage is applied. It will be turned off based on the pinch off effect principle, when VG provides a sufficiently large barrier in the gating re- gion; the highest depletion occurs near to the drain side of the channel due to the stronger electric field in the drain side (Figure 7b,d). Figure 7a,c schematically show the devices in the on state. In this condition, the subthreshold current flows by increasing the VDS until the saturation current will be reached at region II, even for VG = 0 V. Since the system is in on state from VG = 0, one can say that the threshold voltage is shifted into the positive volt- age, and the neutral wire is instantaneously shaped when the bias is applied to the source/drain contacts (Figure 7a, c). That is the reason one can claim that the devices are already in flatband condition like the pinch off transistors [49,50]. In the on state condition, the holes concentration in the channel increases, and the neutral or undepleted channel forms between the source and the drain until the peak of the holes concentration in the channel reaches the doping concentration NA.