sentences: A 12-bit low-power successive approximation register analog-to-digital converter (SAR ADC) is presented using dynamic latch comparator to realize power consumption of 47.86μW under 1.8V supply voltage. Fully differential structure and hybrid 9-bit charge-redistribution capacitive and 3-bit resistor string DAC techniques are adopted to achieve balance between high precision and small area. Fabricated in SMIC 0.18-μm 1P6M mixed-signal CMOS technology, the ADC only occupies 0.39mm active area and the DNL/INL achieve 0.6LSB and 0.8LSB respectively.