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Title: Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks

Paper content:
Efforts to reduce the numerical precision of computations in deep learning training have yielded systems that aggressively quantize weights and activations, yet employ wide high-precision accumulators for partial sums in inner-product operations to preserve the quality of convergence.
The absence of any framework to analyze the precision requirements of partial sum accumulations results in conservative design choices.
This imposes an upper-bound on the reduction of complexity of multiply-accumulate units.
We present a statistical approach to analyze the impact of reduced accumulation precision on deep learning training.
Observing that a bad choice for accumulation precision results in loss of information that manifests itself as a reduction in variance in an ensemble of partial sums, we derive a set of equations that relate this variance to the length of accumulation and the minimum number of bits needed for accumulation.
We apply our analysis to three benchmark networks: CIFAR-10 ResNet 32, ImageNet ResNet 18 and ImageNet AlexNet.
In each case, with accumulation precision set in accordance with our proposed equations, the networks successfully converge to the single precision floating-point baseline.
We also show that reducing accumulation precision further degrades the quality of the trained network, proving that our equations produce tight bounds.
Overall this analysis enables precise tailoring of computation hardware to the application, yielding area- and power-optimal systems.
Over the past decade, deep learning techniques have been remarkably successful in a wide spectrum of applications through the use of very large and deep models trained using massive datasets.
This training process necessitates up to 100's of ExaOps of computation and Gigabytes of storage.
It is, however, well appreciated that a range of approximate computing techniques can be brought to bear to significantly reduce this computational complexity -and amongst them, exploiting reduced numerical precision during the training process is extremely effective and has already been widely deployed BID5 .There
are several reasons why reduced precision deep learning has attracted the attention of both hardware and algorithms researchers. First
, it offers well defined and scalable hardware efficiency, as opposed to other complexity reduction techniques such as pruning BID7 a) ,
where handling sparse data is needed. Indeed
, parameter complexity scales linearly while multiplication hardware complexity scales quadratically with precision bit-width BID20 . Thus,
any advance towards truly binarized networks BID10 corresponds to potentially 30x -1000x complexity reduction in comparison to single precision floating-point hardware. Second
, the mathematics of reduced precision has direct ties with the statistical theory of quantization BID18 . In the
context of deep learning, this presents an opportunity for theoreticians to derive analytical trade-offs between model accuracy and numerical precision BID12 BID16 . The terminology
FPa/b denotes an FPU whose multiplier and adder use a and b bits, respectively. Our work enables
convergence in reduced precision accumulation and gains an extra 1.5× ∼ 2.2× area reduction.Most ongoing efforts on reduced precision deep learning solely focus on quantizing representations and always assume wide accumulators, i.e., ideal summations. The reason being
reduced precision accumulation can result in severe training instability and accuracy degradation, as illustrated in FIG0 (a) for ResNet 18
(ImageNet) model training. This is especially
unfortunate, since the hardware complexity in reduced precision floating-point numbers (needed to represent small gradients during training) BID17 BID14 ) is dominated by the accumulator bit-width. To illustrate this
dominance we developed a model underpinned by the hardware synthesis of low-precision floating-point units (FPU) , that translates precision into area complexity of the FPU. Comparisons obtained
from this model are shown in FIG0 (b). We observe that
accumulating
in high precision severely limits the hardware benefits of reduced precision computations. This presents a new angle to
the problem of reduced precision deep learning training which concerns determining suitable accumulation precision and forms the basis of our paper. Our findings are that the accumulation
precision requirements in deep learning training are nowhere near 32-b, and in fact could enable further complexity reduction of FPUs by a factor of 1.5 ∼ 2.2×.
We have presented an analytical method to predict the precision required for partial sum accumulation in the three GEMM functions in deep learning training.
Our results prove that our method is able to accurately pinpoint the minimum precision needed for the convergence of benchmark networks to the full-precision baseline.
Our theoretical concepts are application agnostic, and an interesting extension would be to consider recurrent architectures such as LSTMs.
In particular, training via backpropagation in time could make the GRAD accumulation very large depending on the number of past time-steps used.
In such a case, our analysis is of great relevance to training precision optimization.
On the practical side, this analysis is a useful tool for hardware designers implementing reduced-precision FPUs, who in the past have resorted to computationally prohibitive brute-force emulations.
We believe this work addresses a critical missing link on the path to truly low-precision floating-point hardware for DNN training.

assistant: text: We present an analytical framework to determine accumulation bit-width requirements in all three deep learning training GEMMs and verify the validity and tightness of our method via benchmarking experiments.