# Patent

## Title
Processor having frequency of operation information for guaranteed operation under high temperature events

## Abstract

A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event.

## Background
FIELD OF INVENTION
The field of invention pertains generally to computing systems and more specifically to a processor having maximum temperature information for guaranteed operation.
BACKGROUND
As the power consumption of computing systems has become a matter of concern, most present day systems include sophisticated power management functions. A common framework is to define both “performance” states and “power” states for a computer system's processor (which may include multiple processing cores). A processor's performance is its ability to do work over a set time period. The higher a processor's performance the more work it can do over the set time period. As such, a processor's power consumption increases as its performance increases.
A processor's performance can be adjusted during runtime by changing its internal clock speeds and voltage levels. Thus, a processor's different performance states correspond to different clock settings and internal voltage settings so as to effect a different performance vs. power consumption tradeoff. According to the Advanced Configuration and Power Interface (ACPI) standard the different performance states are labeled with different “P numbers”: P0, P1, P2 . . . P_R, where, P0 represents the highest performance and power consumption state and P_R represents the lowest level of power consumption that a processor is able to perform work at. The term “R” in “P_R” represents the fact that different processors may be configured to have different numbers of performance states.
In contrast to performance states, power states are largely directed to defining different “sleep modes” of a processor. According to the ACPI standard, the C0 state is the only power state at which the processor can do work. As such, for the processor to enter any of the performance states (P0 through P_R), the processor must be in the C0 power state. When no work is to be done and the processor is to be put to sleep, the processor can be put into any of a number of different power states C1, C2 . . . C_S where each power state represents a different level of sleep and, correspondingly, a different amount of time needed to transition back to the operable C0 power state. Here, a different level of sleep means different power savings while the processor is sleeping.
A deeper level of sleep therefore corresponds to slower internal clock frequencies and/or lower internal supply voltages and/or more blocks of logic that receive a slower clock frequency and/or a lower supply voltage. Increasing C number corresponds to a deeper level of sleep. Therefore, for instance, a processor in the C2 power state might have lower internal supply voltages and more blocks of logic that are turned off than a processor in the C1 state. Because deeper power states corresponds to greater frequency and/or voltage swings and/or greater numbers of logic blocks that need to be turned on to return to the C0 state, deeper power states also take longer amounts of time to return to the C0 state.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
FIG. 1 shows a process that characterizes a processor;
FIG. 2 shows a process for keeping operation of a processor in a guaranteed state;
FIG. 3 shows a table that articulates maximum processor performance state to guarantee processor operation as a function of ambient temperature and cooling system state;
FIG. 4 shows a process that utilizes tabular information such as the tabular information of FIG. 3;
FIG. 5 shows a processor having characterization information embedded therein.



DETAILED DESCRIPTION
System designers are currently having trouble resolving a tradeoff between “guaranteed” processor performance and thermal system cost. Specifically, over the course of the lifetime of a computing system, unlikely yet nevertheless possible extreme ambient temperature events may be presented to the system's processor(s). For example, a cooling fan may fail on an unusually hot day, or, the system may be operated in a desert without air conditioning. System designers are currently faced with a quandary designing a cooling system for such possibilities. A cooling system that is able to keep the processor “cool enough” under such circumstances will be too expensive given the reality that the number of systems that will experience such circumstances will be few and far between and/or such periods of extreme temperature will be brief if experienced.
Complicating the problem is the notion of guaranteed processor operation, particularly under extreme thermal conditions (such as the sudden breakdown of a fan). Currently, processor manufacturers provide maximum rated supply voltage, operating frequency and temperature specifications. Here, “guaranteed operation” means that the processor is not expected to incur unacceptable operational errors. However, these ratings have some margin in them and/or are somewhat conservative. As such, at least some shipped parts may be able to properly operate beyond such ratings. The “true” maximum ratings for a specific processor, where that processor's operation is guaranteed, is simply unknown to the system designer.
Accordingly, at least some system designers may wish to entertain the idea of only building a nominal cooling system (to keep cooling system costs down) but enhance the power management control of the processor so as to drop the performance state of the processor in response to an extreme thermal event, where, the processor's operation remains guaranteed at the reduced state. Here, to the extent some margin may exist between what the part is formally rated for versus the operating conditions the part may actually be able to withstand for at least a limited amount of time, e.g., in the case of a sudden thermal event, it may be permissible to run the part beyond its formal ratings yet still provide guaranteed operation.
As a matter of physics, a processor's operation can be guaranteed as a function of its die temperature. Here, operational failure mechanisms are understood to be largely related to changes within the semiconductor chip's physical composition that arise when the chip becomes too hot. The temperature of the processor die is a function of the die's power consumption, the die's packaging, the cooling system applied to the packaging and the ambient temperature. The power consumption of the processor die (which largely corresponds to the “performance” of the die) is the current drawn by the die multiplied by its supply voltage. The current drawn by the die at a specific supply voltage is a function of the clock frequency and workload of the processor die.
Thus, when a specific supply voltage, clock frequency and workload are applied to the die, the temperature of the die will rise to some level that is lessened as the cooling system becomes more advanced and the ambient temperature decreases. Said another way, if a specific supply voltage, clock frequency and workload are applied to the die and no cooling of any kind is applied to the die's package, the temperature of the die will rise to some level that is dictated by the physics of the die, its packaging without cooling and the ambient temperature. As more advanced/capable cooling is applied to the die's packaging and/or as the ambient temperature decreases, the temperature of the die will only reach lower and lower levels for the same applied supply voltage, clock frequency and workload.
It would be useful therefore for a processor manufacturer to provide one or more operational frequencies with each processor that can be applied to the processor under extreme thermal conditions where the processor's performance remains guaranteed. Conceivably such operational frequencies may cause the processor to exceed its formal maximum ratings. In an embodiment, these special operational frequencies are understood to be applied only temporarily (e.g., a few hours or days) if they correspond to operation beyond the processor's nominal maximum ratings. In practice then, system designers design their power management functions to place a ceiling on the processor's operational frequency to one of these frequencies in response to an extreme thermal event. In a further embodiment, different frequencies are provided as a function of different ambient temperatures so that an appropriate operational frequency is effectively specified for different thermal ambient excursions.
In an embodiment, the processor manufacturer, in order to provide such operational frequencies, determines a die temperature for each processor at which the specific processor's operation would be guaranteed and determines the maximum permissible power consumption for the specific processor when operating at that maximum permitted temperature. A nominal supply voltage and cooling system is then assumed by the processor manufacturer to translate these parameters into specific processor operational frequencies as a function of specific ambient temperatures. System designers can adjust these operational frequencies and/or temperatures based on their own supply voltages and cooling system technology. For example, a system designer who chooses a cooling system that is more advanced than the assumed one may use a higher operational frequency than the one provided by the processor manufacturer for a particular ambient temperature, or, may identify a higher ambient temperature. With this information, system designers can implement a power management scheme that automatically drops processor operating frequency, e.g., in response to an extreme thermal event, so as to cause the die to operate at its maximum permissible temperature and power consumption so as to keep the die within a guaranteed operational realm.
FIG. 1 shows a process to be performed by processor manufacturer that essentially characterizes 101 each shipped processor with maximum operating frequency information as a function of ambient temperature information where operation of the processor is still guaranteed. In various embodiments such characteristic information is specific to each processor on a processor-by-processor basis.
Such characteristic information may be obtained, for example, by running characterization testing on each manufactured processor. Here, a singular die may be tested before packaging, and/or, a packaged die that forms the completed processor may be characterized. Die temperature may be measured outright (e.g., in the case of an unpackaged die, or, through readouts provided by the (packaged or unpackaged) die of any of its one or more embedded thermal sensors) or calculated (e.g., by measuring case and ambient temperatures of a packaged die and determining die temperature based on the theoretical thermal characteristics of the die's packaging).
A second body of characterization data that effectively maps the die's temperature to its power consumption may also be collected. Here, for example, a number of data points may be collected that, e.g., start at the maximum permissible die temperature and the maximum permissible power consumption for guaranteed operation, and, gradually drop in power consumption and die temperature. Alternatively, a formula can be determined and provided that articulates the drop in die temperature with decreasing power consumption.
A third body of characterization data that effectively maps the die's power consumption to its clock frequency (e.g., at maximum supply voltage and when all logic blocks within the processor die are enabled) across a range of clock frequencies and corresponding die power consumption levels may also be provided. Here, for example, a number of data points may be collected that, e.g., at maximum supply voltage and under a workload that enables all logic blocks within the processor, start at the maximum permissible power consumption and clock frequency and gradually drop the clock frequency and corresponding power consumption. Alternatively, a second formula can be determined and provided that articulates the drop in die power consumption with decreasing clock frequency.
The characterization data is then analyzed in conjunction with an assumed system supply voltage and cooling system external to the die's package to determine specific operational frequencies for the processor as a function of die package ambient temperature. In the alternative, the operational frequencies may be provided in the form of maximum performance states.
The information is then correlated with the specific processor 102. In one embodiment, the frequency and ambient temperature information is embedded in the die of the processor. For example, the data may be written into non-volatile storage circuitry of the die (e.g., fuse storage circuitry embedded on the die where fuses are blown to digitally store the characterization data). Alternatively, the frequency and ambient temperature information may be correlated to the die rather than being embedded within it. For example, the customer of a volume of processors may download or otherwise receive the information for each of the die identified by their respective serial numbers.
The customer/system designer, with knowledge of the system's actual cooling system and theoretical operation thereof is able to determine how well its cooling system can cool the processor die in the face of extreme ambient temperatures relative to the processor manufacturer's assumed cooling system. If the two are substantially similar, the system manufacturer may be able to use the processor manufacturer supplied operational frequencies directly for any particular extreme ambient temperature. Said another way, with the manufacturer having supplied information that describes maximum processor operational frequency as a function of ambient temperature where operation remains guaranteed, the system designer 103 can use the manufacturer provided operational frequencies directly in response to a particular extreme ambient temperature (if the assumed cooling and supply voltages are comparable) or “tweak” them (if the actual system departs from the assumed one).
The system designer/manufacturer configures the system's power management function 104 to reduce the clock frequency of the processor as a function of ambient temperature based on the manufacturer supplied information, where, the reduced clock frequency keeps the operation of the processor in the guaranteed operational realm.
As such, for example, referring to FIG. 2, if an extreme thermal event is detected 201, the clock frequency of the processor is reduced 202 in response to an operational frequency based on the processor manufacturer supplied one so as to effectively lower the die temperature to keep the processor in an operationally guaranteed state. If the processor manufacturer has specified a time limit for this operational frequency at this particular ambient temperature the system designer can again lower processor frequency if the time limit is approached.
According to one possible implementation, the system designer further resolves the information directly into the processor's power state management tables. The power state management tables can be further resolved to identify a specific power state for the processor for a specific failure event (or lack thereof) and ambient temperature.
FIG. 3 shows an example. As observed in FIG. 3, specific maximum permissible processor performance states to maintain guaranteed operation are articulated for particular states of the cooling system 301 and ambient temperature 302. According to this exemplary illustration, the system designer has determined that, even if the processor operates at the P1 performance state (and its maximum number of logic blocks are enabled and operates at the P1 state's maximum clock frequency), processor operation will still be guaranteed if the ambient temperature is less than or equal to 35° and at least one fan is working. If a second fan fails however, the processor's maximum permissible performance state needs to be dropped to the P3 state.
Likewise, the maximum permissible power state of the processor is lowered further as the ambient temperature increases and then again if one or more fans fail.
FIG. 4 shows a process for constructing and utilizing a table such as the table observed in FIG. 3. As observed in FIG. 4, entries are determined for a table that outline maximum permissible processor performance state where processor operation is guaranteed as a function of cooling system state and ambient temperature 401. Here, the processor manufacturer supplied information is combined with the designer's knowledge of the cooling system's design and individual processor performance state definitions to articulate the different processor performance states for the different conditions. Thus, the tabular information is determined on a die-by-die basis for the specific system that a die is being integrated into. As such, systems with same model numbers having processors with same model numbers may none the less have different tabular entries owing to the die specific information provided by the processor manufacturer.
Once the entries for the table are determined they are stored, for example, in non volatile memory where the BIOS system firmware of the system is kept. Upon each power up of the system, the table information is loaded 402 into the power management intelligence of the system which may be realized in software, hardware or a combination thereof. As such, the tabular entries may be loaded into register space of the processor or a region of system memory of the system (or even remain in firmware).
During runtime of the system, sensors collect various information that indicate the ambient temperature and the state of the cooling system 403. Based on the current state of the cooling system and ambient temperature, the table information indicates the maximum performance state of the processor where operation of the processor is guaranteed 404. Power management logic is made aware of the maximum performance state under the current conditions and refuses to raise the performance state of the processor beyond the maximum specified by the tabular information (but may lower it depending on other power management protocols).
The collection of information by the sensors 403 is continuous and any change in cooling system state or ambient temperature that corresponds to a change in the applicable table location is identified and any resulting change in maximum permissible processor performance state is communicated to power management logic intelligence. If the performance state of the processor needs to change immediately (e.g., reducing it from its current performance state to a lower performance state), the power management logic intelligence may do so, for example, by writing into register space of the processor (such as model specific register space) to effect the power state change. The information written into the register space may specify the performance state outright, or, corresponding to one or more settings (e.g., clock frequency settings, logic block enable/disable settings) that correspond to the new processor performance state.
If the maximum operating frequency supplied by the processor manufacturer also has an associated time limit (e.g., days, hours), the methodology of FIG. 4 will automatically drop the processor operating frequency (e.g., by lowering to an even lower power state) if the extreme ambient temperature event approaches the time limit.
FIG. 5 shows the architecture of an exemplary multi-core processor 500. As observed in FIG. 5, the processor includes: 1) multiple processing cores 501_1 to 501_N; 2) an interconnection network 502; 3) a last level caching system 503; 4) a memory controller 504 and an I/O hub 505. Each of the processing cores contain one or more instruction execution pipelines for executing program code instructions. The interconnect network 502 serves to interconnect each of the cores 501_1 to 501_N to each other as well as the other components 503, 504, 505. The last level caching system 503 serves as a last layer of cache in the processor before instructions and/or data are evicted to system memory 506. The individual cores typically include their own one or more caching levels.
The memory controller 504 reads/writes data and instructions from/to system memory 506. The I/O hub 505 manages communication between the processor and “I/O” devices (e.g., non volatile storage devices and/or network interfaces). Port 507 stems from the interconnection network 502 to link multiple processors so that systems having more than N cores can be realized. Graphics processor 508 performs graphics computations. Power management circuitry 509 manages the performance and power states of the processor as a whole (“package level”) as well as aspects of the performance and power states of the individual units within the processor such as the individual cores 501_1 to 501_N, graphics processor 508, etc. Other functional blocks of significance (e.g., phase locked loop (PLL) circuitry) are not depicted in FIG. 5 for convenience.
Notably, the processor of FIG. 5 also has embedded storage circuitry 550 where information pertaining to the processor's maximum operating temperature for a particular extreme ambient temperature where operation of the processor is guaranteed is stored.
As any of the processes taught by the discussion above may be implemented with software such processes may be implemented with program code such as machine-executable instructions that cause a machine that executes these instructions to perform certain functions. Processes taught by the discussion above may also be performed by (in the alternative to the execution of program code or in combination with the execution of program code) by electronic circuitry designed to perform the processes (or a portion thereof).
It is believed that processes taught by the discussion above may also be described in source level program code in various object-orientated or non-object-orientated computer programming languages. An article of manufacture may be used to store program code. An article of manufacture that stores program code may be embodied as, but is not limited to, one or more memories (e.g., one or more flash memories, random access memories (static, dynamic or other)), optical disks, CD-ROMs, DVD ROMs, EPROMs, EEPROMs, magnetic or optical cards or other type of machine-readable media suitable for storing electronic instructions. Program code may also be downloaded from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a propagation medium (e.g., via a communication link (e.g., a network connection)).
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

## Claims

1. A processor comprising:
a non-volatile storage circuitry to store information identifying a maximum operational frequency of said processor at which said processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event and a time limit for guaranteed operation at the maximum operational frequency, wherein the extreme thermal event comprises a failure of one or more fans; and
a power management circuitry to manage performance and power states of the processor by accessing the non-volatile storage circuitry and configuring an operating frequency of the processor to be the maximum operational frequency upon an occurrence of the extreme thermal event for a time period not to exceed the time limit.

2. The processor of claim 1 wherein said maximum operational frequency corresponds to a maximum die temperature of a semiconductor chip housing the processor.

3. The processor of claim 1 wherein said processor's operation is guaranteed for a limited time.

4. The processor of claim 3 wherein said time limit is at least two hours.

5. The processor of claim 1 wherein said non-volatile storage circuitry is also to store nominal maximum ratings and said maximum operational frequency at said ambient temperature to correspond to exceeding said nominal maximum ratings.

6. The processor of claim 1, wherein the non-volatile storage circuitry is to store information for at least three fan states.

7. The processor of claim 1, wherein the configuring is lowering the operating frequency.

8. The processor of claim 7, wherein the power management circuitry is to further lower the operating frequency when the time limit is approached.

9. A method comprising:
obtaining information for a processor that identifies a maximum operating frequency for said processor at an ambient temperature at which said processor's operation is guaranteed and a time limit for guaranteed operation at the maximum operational frequency, said ambient temperature corresponding to an extreme thermal event, wherein the extreme thermal event comprises a failure of one or more fans; and
determining from said information performance states of said processor as a function of ambient temperature and a state of a cooling system where said processor's operation is guaranteed.

10. The method of claim 9 wherein the time limit is at least two hours.

11. The method of claim 9 wherein said information is incorporated into a non-volatile storage of said processor.

12. The method of claim 11 wherein said information is read from said non-volatile storage and loaded into system memory of said processor upon power on of said processor.

13. The method of claim 11 wherein said information is read from said non-volatile storage and loaded into a register space of said processor upon power on of said processor.

14. A method comprising:
determining an ambient temperature of a processor and a state of a cooling system of a processor, said ambient temperature corresponding to an extreme thermal event, wherein the extreme thermal event comprises a failure of one or more fans;
determining a performance state of said processor at which said processor's operation is guaranteed by referring to information that identifies performance states of said processor at which said processor's operation is guaranteed as a function of said processor's ambient temperature and said cooling system's state and a time limit for guaranteed operation at the performance state; and
configuring said processor to be in said performance state.

15. The method of claim 14 wherein said information is within system memory of a computing system that said processor is integrated into, and said configuring is performed by power management intelligence of said computing system.

16. The method of claim 14 wherein the time limit is at least two hours.

17. The method of claim 15 further comprising loading said information into system memory upon power up of said computing system.

18. A non-transitory machine readable storage medium having stored program code that when processing by a computing system causes the computing system to perform a method comprising:
determining an ambient temperature of a processor and a state of a cooling system of a processor, said ambient temperature corresponding to an extreme thermal event, wherein the extreme thermal event comprises a failure of one or more fans;
determining a performance state of said processor at which said processor's operation is guaranteed by referring to information that identifies performance states of said processor at which said processor's operation is guaranteed as a function of said processor's ambient temperature and said cooling system's state and a time limit for guaranteed operation at the performance state; and
configuring said processor to be in said performance state.

19. The non-transitory machine readable storage medium of claim 18 wherein said information is within system memory of a computing system that said processor is integrated into, and said configuring is performed by power management intelligence of said computing system.

20. The non-transitory machine readable storage medium of claim 19 wherein the time limit is at least two hours.

21. The non-transitory machine readable storage medium of claim 18 wherein said method further comprises loading said information into system memory of said computing system upon power up of said computing system.

22. The non-transitory machine readable storage medium of claim 18 wherein one of said determined ambient temperature and state of said cooling system is one of a changed ambient temperature and a changed state of said cooling system and said determining a performance state includes identifying a new performance state at which said processor's operation is guaranteed.