# Patent

## Title
Integrated thermoelectric generator

## Abstract

An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.

## Background
This is a continuation application of U.S. application Ser. No. 13/549,248, entitled “Integrated Thermoelectric Generator,” which was filed on Jul. 13, 2012 and is incorporated herein by reference to the maximum extent allowable by law. This application also claims the priority benefit of French patent application number 1156417, filed on Jul. 13, 2011, which is hereby incorporated by reference to the maximum extent allowable by law.


TECHNICAL FIELD
The invention relates to thermoelectric generators and, in particular embodiments, to thermoelectric generators produced in CMOS technology within an integrated circuit, e.g., thermoelectric generators totally compatible with technologies for the manufacture of so-called “Embedded Non-Volatile Memory.”
BACKGROUND
Thermoelectric generators conventionally comprise a support and a set of thermocouples electrically connected in series and thermally connected in parallel. Thermocouples thermally connected in parallel are understood as being thermocouples intended to all be subjected to the same temperature gradient, for example, when a heat source is disposed at one of the ends of the thermocouples and when a cold source is disposed at the other end.
A potential difference which is due to the Seebeck effect is then created between the two terminals of the set of thermocouples electrically connected in series.
Thermoelectric generators have been the subject of numerous publications. Examples of these publications include:

    Vullers et al., “Micropower energy harvesting”, Solid-State Electronics 53 (2009) 684-693,
    Yang et al., “Design and verification of a thermoelectric energy harvester with stacked polysilicon thermocouples by CMOS process”, Sensors and actuators A157 (2010) 258-266,
    Pin-Hsu Kao et al., “Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators”, Sensors 2010, 10, 1315-1325,
    Joao Paulo Carmo et al., “A planar thermoelectric power generator for integration in wearable microsystems”, Sensors and Actuators A161 (2010), 199-204,
    S. M. Yang et al., “Development of a thermoelectric energy harvester with thermal isolation cavity by standard CMOS process”, Sensors and Actuators A153 (2009), 244-250,
    Ziyang Wang et al., “Realization of a wearable miniaturized thermoelectric generator for human body applications”, Sensors and Actuators A156 (2009), 95-102,
    Hélène Lhermet et al., “Efficient Power Management Circuit: From Thermal Energy Harvesting to Above-IC Microbattery Energy Storage”, IEEE Journal of Solid-State Circuits, vol. 43, no 1, January 2008,
    Till Huesgen et al., “Design and fabrication of MEMS thermoelectric generators with high temperature efficiency”, Sensors and Actuators A145-146 (2008), 423-429,
    David Koester et al., “Embedded thermoelectric coolers for semiconductor hot spot cooling”, 2006 IEEE,
    Hiromichi Ohta et al., “Critical thickness for giant thermoelectric Seebeck coefficient of 2DEG confined in SrTiO3/SrTi0.8Nb0.2O3 superlattices”, Thin Solid Films 516 (2008), 5916-5920.


All of these articles describe either the general principles of thermoelectric generators based on the Seebeck effect, using ceramic supports for example, or they describe generators using materials that are not compatible with CMOS technologies, such as piezoelectric materials, or generators based on technological methods of the MEMS (Micro Electro Mechanical System) type having cavities in the substrate under the thermocouples.
SUMMARY
According to one embodiment, a thermoelectric generator is compatible with the manufacturing methods and technologies already widely used in the microelectronics field, in particular for the manufacture of embedded non-volatile memories, well known as “Embedded Memory” by those skilled in the art. Embedded memories are memories that are produced on the same integrated circuit as that containing another component, for example a processor, unlike external memory modules that are produced on a specific integrated circuit different from the one containing a processor.
According to one embodiment, it is proposed to use layers of material, for example, made of polysilicon, which is already available for producing the memory cells, and without the generator requiring the addition of supplementary masks or supplementary process steps in comparison with the existing memory cell manufacturing methods.
In a variant, a generator is proposed whose manufacturing method, whilst being included in a conventional method of manufacturing memory cells, nevertheless requires the addition of some supplementary process steps, which are particularly simple to implement.
According to one aspect, there is proposed an integrated thermoelectric generator, comprising a support and at least one set of thermocouples electrically connected in series and thermally connected in parallel.
According to a general feature of this aspect, the support comprises a semiconductor substrate (for example, made of silicon) and isolating regions (for example shallow trenches known to those skilled in the art as STI for Shallow Trench Isolation). The at least one set of thermocouples comprises parallel semiconductor regions, for example regions of N-doped or P-doped polysilicon, each one having one type of conductivity from among two opposite types of conductivity. At least some of these parallel semiconductor regions are able to extend in the substrate between parallel isolating regions. Alternatively, at least some of these parallel semiconductor regions being able to straddle over a part of the substrate whilst being electrically isolated from the part of substrate, and over at least a part of the isolating regions. Alternatively, at least some of these parallel semiconductor regions are coated with an isolating material and can extend totally over parallel isolating regions, or totally over the regions of substrate situated between the parallel isolating regions.
Whatever the configuration may be, the semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.
According to one embodiment, the generator also comprises electrically conductive connections providing the electrical link between the semiconductor regions. These connections are situated above the substrate and connect an end zone of a semiconductor region having one of the two types of conductivity, for example, N-type conductivity, to an end zone of a semiconductor region having the other type of conductivity, for example P-type conductivity.
For example, the connections are coated with an isolating material and comprise metal tracks parallel with the semiconductor regions and connected to the end zones by vertical electrical links, known to those skilled in the art as “vias” or “contacts.”
Several structures are possible for producing the set of thermocouples.
It is also possible for the generator to comprise at least one other set of thermocouples electrically connected in series and thermally connected in parallel, all of the sets being mutually electrically and thermally connected in parallel.
According to another aspect, an integrated circuit comprises a semiconductor substrate and, above the substrate, layers of metallization. According to a general feature of this other aspect, the integrated circuit comprises a thermoelectric generator such as defined above, whose substrate is a part of the substrate of the integrated circuit and some of whose electrical connections between the thermocouples comprise metal tracks extending over at least one level of metallization. The integrated circuit comprises structure capable of generating a temperature gradient between the first similar end zones and the second similar end zones of all the parallel semiconductor regions of the thermocouples, and an electrically conductive output structure coupled to the generator in order to deliver the electrical energy produced by the generator.
It is also possible for the integrated circuit to comprise an electrical energy storage unit, electrically coupled to the electrically conductive output structure.



BRIEF DESCRIPTION OF THE DRAWINGS
Other advantages and features of the invention will become apparent on examination of the detailed description of embodiments, which are in no way limiting, and of the appended drawings in which:
FIG. 1 is a diagrammatic illustration of an embodiment of an integrated circuit according to the invention incorporating an example of a generator according to the invention;
FIG. 2 is a diagrammatic illustration of another example of a generator according to the invention;
FIGS. 3 to 15 show, in greater detail but still diagrammatically, different embodiments of integrated electric generators according to the invention; and
FIG. 16 is a diagrammatic illustration of still another example of a generator according to the invention.



DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
In FIG. 1, the reference CI denotes an integrated circuit comprising a semiconductor substrate SB, for example made of silicon. A thermoelectric generator GEN is disposed within or upon the substrate SB. The thermoelectric generator GEN comprises a set ENS1 of thermocouples THi.
Each thermocouple THi here comprises a semiconductor region in the shape of a bar of N-type conductivity, referenced RSNi, and a semiconductor region of P-type conductivity, referenced RSPi, also in the shape of a bar
The two semiconductor regions of the thermocouple THi are parallel and electrically connected at one of their ends, and the set of thermocouples THi are electrically connected in series so as to form a chain of parallel bars alternately having N-type and P-type conductivity.
Electrically conductive output structure MSE is connected to the respective and similar ends of the bars RSN1 and RSPn, belonging to the first thermocouple TH1 and to the last thermocouple THn respectively. The electrically conductive output structure MSE can be, for example, metal tracks or an extension of the corresponding bars.
The integrated circuit also comprises a structure capable of generating a temperature gradient between the first similar end zones ZX1 of all the parallel semiconductor regions of the thermocouples and the second similar end zones ZX2 of these parallel semiconductor zones.
By way of indication, the structure can comprise a hot source SH and a cold source SF disposed facing the end zones ZX1 and the end zones ZX2, respectively.
By way of example, the hot source SH can be a part of an integrated circuit generating heat whilst operating whereas the cold source can be another part of the integrated circuit generating less heat, or an absence of a component likely to generate heat.
Because of the Seebeck effect, the pairs PN subjected to this temperature difference or gradient will generate an electric current which will be delivered by the output structure MSE in order, for example, to be stored in electrical energy storage structure MSTK, comprising for example a capacitor connected to the terminals of the output structure MSE in order to form a closed electric circuit.
In a variant, the output structure MSE can be connected to another part of the integrated circuit in order also to form a closed circuit and to be able to supply this other part of the integrated circuit directly with electrical energy.
The output power of the generator GEN depends principally on the number of pairs PN, on the area of the generator, on the value of the temperature gradient and on the type of materials, that is to say, on their Seebeck coefficient.
The thermocouples of the set ENS1 are thermally connected in parallel, that is to say, they are connected so as to be all subjected together to the same temperature gradient.
In a variant, it is possible, as shown in FIG. 2, for the generator to comprise at least one other set of thermocouples, in this case a second set of thermocouples ENS2, having a structure which is identical to or different from that of the first set ENS1. Here again, the thermocouples of the other set ENS2 are electrically connected in series and thermally connected in parallel.
Moreover, the two sets ENS1, ENS2 are mutually electrically connected in parallel. They are moreover also thermally connected in parallel. That is to say, in the present case, the hot source SH and the cold source SF make it possible to apply the temperature difference created by the hot and cold sources SH and SF to all of the thermocouples of all of the sets.
This makes it possible to provide a higher electrical power at the level of the electrically conductive output means MSE.
Several examples of generators GEN structures will now be described with reference to FIGS. 3 to 15.
In FIG. 3, the support of the generator GEN comprises a semiconductor substrate SB, for example made of silicon. Parallel isolating regions RIS are formed within the substrate SB. The parallel isolating regions RIS can be, for example, regions of the STI (Shallow Trench Isolation) type.
The set of thermocouples ENS1 is situated in the substrate SB and comprises parallel semiconductor regions RSN, RSP extending in the substrate. Two adjacent semiconductor regions RSN, RSP respectively have one and the other of the two types of conductivity. In this case, the two types are N-type conductivity and P-type conductivity. The parallel semiconductor regions RSN, RSP are separated by an isolating region RIS.
The whole is covered by an isolating layer CS1, for example a layer of silicon nitride. In this example, the isolating layer is itself covered by an isolating coating, for example, silicon dioxide SiO2.
The production of such a generator is perfectly compatible with the conventional method of manufacturing embedded memories and does not necessitate any modification of the method or any additional mask level.
The insulating coating ENR is, for example, the layer in which the metallization levels of the printed circuit are produced.
In this respect, and in general, whatever the structure of the thermocouple set may be, the generator comprises electrically conductive connection structures providing the electrical connection between the semiconductor regions of the thermocouples. These connections are situated above the substrate and connect an end zone of a semiconductor region having one of the two types of conductivity, for example N-type conductivity, to an end zone of a semiconductor region having the other type of conductivity, for example P-type conductivity.
For example, these connections are coated with an isolating material ENR and comprise metal tracks parallel with the semiconductor regions and connected to the end zones by vertical electrical links, for example, contacts or vias.
Furthermore, in order to be perfectly compatible with conventional methods of manufacturing components, for example embedded memories, the metal tracks of the connection means are situated on at least one of the metallization levels of the integrated circuit CI.
This is illustrated more particularly in FIG. 4, which shows the connection means of the generator shown in FIG. 3.
Thus, the end zone ZX1 of the semiconductor region RSN1 is electrically connected to the similar end zone ZX1 of the region RSP1 by a metal track PM straddling the isolating region RIS separating these two regions RSN1 and RSP1. This metal track is connected to the end zones ZX1 by vias V.
Similarly, the end zones ZX2 of the regions RSN1 and RSP2 are also connected together by a metal track PM straddling the region RIS separating these two regions RSN1 and RSP2. This metal track PM is connected to the end zones ZX2 by vias V.
Similarly, the two end zones ZX1 of the regions RSP2 and RSN2 are connected in the same way by a metal track PM straddling the isolating region RIS. This metal track is connected to the zones ZX1 by the intermediary of vias V.
The embodiment shown in FIG. 5 differs from that of FIG. 3 and of FIG. 4 in that the set ENS1 of thermocouples comprises, on the one hand, first parallel semiconductor regions RSP all extending in the substrate SB and all having one of the two types of conductivity, in this case P-type conductivity. Two adjacent first semiconductor regions RSP are separated by an isolating region RIS.
On the other hand, the set of thermocouples comprises second parallel semiconductor regions RSN all extending respectively within isolating regions RIS and all having the other type of conductivity, in this case N-type conductivity.
It is appropriate to note here that this embodiment has the advantage of providing a generator having a greater number of pairs PN, for the same overall surface dimensions as those of FIG. 3, which makes it possible to increase the delivered electrical power.
The method of manufacturing the generator is slightly modified in comparison with a conventional manufacturing method of the embedded memory type. More precisely, after formation of the trenches in the silicon and formation on the walls of the trenches of an oxide layer cladding the latter, the doped polysilicon is deposited in situ. The silicon overflowing the trenches is subsequently etched in a conventional way, for example, by dry etching.
In the embodiment shown in FIGS. 6 and 7, the substrate upon which the generator GEN is formed comprises, between the parallel isolating regions RIS, regions of substrate RSB all having the same type of conductivity, namely in this case for example N-type conductivity.
Moreover, the set ENS1 of thermocouples here comprises, above each region of substrate RSB, at least one pair of semiconductor regions RSP, RSN, coated with an isolating material ENR and respectively having the two types of conductivity.
More precisely, in this example, the lower semiconductor regions RSP of the pairs have P-type conductivity and are surmounted by the regions RSN which have N-type conductivity.
The isolating coating comprises, in a conventional way, silicon nitride and silicon dioxide and corresponds to the conventional coating of non-volatile memories having two gates, (one of which is floating). In this respect, the method of manufacturing the thermocouple of the generator GEN in FIG. 6 is similar to the method of manufacturing a memory plane with floating gates.
Here again, as shown in FIG. 7, metal tracks and vias make it possible to electrically connect the thermocouples in series. More precisely, a first end zone ZX1 of a first semiconductor region RSP1 is connected to the first similar end zone ZX10 of the semiconductor region RSN2 of the adjacent pair by vias V1 and V2 and a portion of metal track PM1.
Moreover, the second end zones ZX20 of the regions RSN1 and RSN2 are connected to the second similar end zones ZX2 of the regions RSP1 and RSP2 by vias V3, V4, V5, V6 and portions of metal tracks PM2, PM3.
It is appropriate to note here that, just as in the embodiment shown in FIG. 3, the portion PM1 straddles the isolating region RIS separating the two pairs of semiconductor regions RSP1, RSN1 and RSP2, RSN2.
It would also be possible, as a variant, for the pairs of semiconductor regions to be situated not above the regions of substrate but above the isolating regions RIS.
This is the case in the embodiment shown in FIG. 8. In this embodiment, the set ENS1 of thermocouples of the generator GEN comprises parallel semiconductor regions RSNA, RSPA extending in the substrate and having, respectively and alternatingly, one and the other of the two types of conductivity (N and P) and being separated by parallel isolating regions RIS.
Furthermore, as mentioned above, in addition to these regions of substrate RSNA, RSPA, the set ENS1 comprises, above each isolating region, a pair of semiconductor regions RSPBi and RSNBi coated with an isolating material ENR and respectively having the two types of conductivity N and P.
Thus, in comparison with the embodiment shown in FIG. 6, and for the same overall surface dimensions, the generator GEN shown in FIG. 8 has a greater number of pairs PN than the number of pairs PN of the generator shown in FIG. 6.
Here again, the generator shown in FIG. 8 is perfectly compatible with the methods of manufacturing embedded non-volatile memory.
The means of electrical connection between the various components of the various thermocouples are shown diagrammatically in FIG. 9.
More precisely, a first end zone ZX1 of the semiconductor region RSPB1 situated above the isolating region RIS is connected to the first similar end zone ZX10 of the region RSNB1 by vias V1 and V2 and a portion of the metal track PM1.
The second end zone ZX20 of the region RNSB1 is connected to the second end zone ZX2A of the region of substrate RSPA by vias V3 and V4 and by a portion of metal track PM2.
The electrical continuity between the region RSPA and the region RSNB2 is provided by vias V5 and a portion of metal track PM3, connecting the first two similar end zones ZX1A and ZX10 of the region RSPA and the region RSNB2.
The electrical continuity between the regions RSNB2 and RSPB2 is provided by vias V6 and V7 and a portion of metal track PM4 connection the two similar ends ZX20 and ZX2 of these two regions.
The electrical continuity between the region RSPB1 and the adjacent region of substrate RSNA is provided, at the level of their respective second end zones ZX2 and ZX2A, by vias V8 and V9 and a portion of metal track PMS.
Similarly, the electrical continuity between this region RSNA and the semiconductor region RSPB of the adjacent pair is provided by a via V10 and a portion of metal track PM6 at the level of the end zone ZX1A of the region RSNA.
The embodiment of the generator GEN shown in FIG. 10 differs from the one shown in FIG. 8 in that the set ENS1 of thermocouples furthermore comprises parallel semiconductor regions extending within the isolating regions RIS.
More precisely, the set ENS1 of thermocouples comprises parallel regions of substrate RSNA all having the same type of conductivity, in this case N-type conductivity, semiconductor regions RSPA extending within the isolating regions RIS separating these regions of substrate RSNA and all having the other type of conductivity, namely, P-type conductivity, and, above each region of substrate RSNA, pairs of parallel semiconductor regions RSPBi and RSNBi coated with an isolating material ENR.
Thus, such an embodiment, perfectly compatible with the technology of embedded non-volatile memories, comprises, in comparison with the embodiment shown in FIG. 3, a greater number of pairs PN for the same surface imprint, which makes it much more efficient in terms of produced electrical energy.
The electrical connections between the various parts of the various thermocouples of the generator shown in FIG. 10 are shown diagrammatically in FIG. 11. This time, some of these connections extend over both of two metallization layers of the integrated circuit, namely the metal level 1 MET1 and the metal level 2 MET2.
Just as in the preceding embodiments, the electrical continuity between the various components of the various thermocouples connected in series is carried out by vias and portions of metal track connecting two end zones of two semiconductor regions having the two opposite types N and P.
Moreover, whilst the electrical connection between the region RSPB1 and the region RSNA is carried out by a portion of metal track PM1 situated at the metal level MET1, the electrical connection between the region RSNB1 and the region RSPA encapsulated in the isolation region RIS is carried out in particular by three portions of metal track PM2, PM3, PM4 situated at the metallization levels MET1 et MET2.
The lower right hand side of FIG. 11 shows the connection between a portion of metal track PM and a semiconductor region RSPA encapsulated in a region RIS by the intermediary of a via V traversing the region RIS in order to contact the region RSPA.
The other electrical continuities of the regions shown in FIG. 11 comprise in particular portions of metal track PM4, PMS, PM6, PM7, PM8.
As mentioned above with reference to FIG. 2, it is possible to electrically connect two sets of thermocouples in parallel. An example of such an embodiment is shown in FIG. 12.
In this figure, the generator GEN comprises for example the set of thermocouples ENS1 shown in FIGS. 3 and 4, and the set of thermocouples ENS2 shown in FIGS. 6 and 7.
Silicon is a very good conductor of heat, such that the two temperature levels present at the two ends of the thermocouples respectively and initially different can rapidly become equal, which then stops the generation of electrical power.
Whereas, in the prior art, solutions have been proposed not using silicon or using technologies of the MEMS type in such a way as to create cavities, the embodiment shown in FIG. 13 makes it possible, in general, in particular by the use of polysilicon, to delay the equalizing of the temperatures whilst remaining compatible with conventional CMOS manufacturing technologies.
More precisely, as shown very diagrammatically in FIG. 13, a part of the set of thermocouples ENS of the generator GEN extends over a part of the substrate SB covered with an isolating layer CS1, for example a thin layer of silicon dioxide, whilst the other part of the set of thermocouples extends over an isolating region RIS, thicker than the isolating layer covering the silicon substrate, this layer RIS being able to be a shallow isolating trench of the STI type.
Because of this, considering that the isolating material, generally silicon dioxide, is a very poor conductor of heat, the equalizing of the temperatures between the two ends of the thermocouples is delayed, which improves the efficiency of the generator.
A more precise example of embodiment is shown in FIGS. 14 and 15.
In FIG. 14, the substrate SB is covered by a thin isolating layer CS1 of silicon dioxide.
The set ENS1 of thermocouples comprises several parallel pairs of parallel semiconductor regions RSNi, RSPi respectively having the two types of conductivity N and P, these pairs straddling over the isolating layer CS1 and over the isolating region RIS, thicker than the isolating region CS1.
In FIG. 16, an integrated circuit CI includes a semiconductor substrate SB, a thermoelectric generator GEN, a hot source SH, a cold source SF, an electrical energy storage structure MSTK, and an array of non-volatile memory cells NVM. Description included hereinabove in reference to commonly identified elements applies to FIG. 16 and will not be repeated in the interests of brevity. Any of the embodiments described hereinabove may be applied to elements of FIG. 16. In various embodiments, hot source SH and cold source SF generate a temperature gradient along a region of the semiconductor substrate SB. Thermoelectric generator GEN generates electrical power located in the region of the semiconductor substrate SB. Thermoelectric generator GEN includes at least one set of thermocouples integrated at a surface of the semiconductor substrate SB. Electrical energy storage structure MSTK is disposed in the semiconductor substrate SB and stores the generated electrical power. The array of non-volatile memory cells NVM is disposed in the semiconductor substrate SB.

## Claims

1. An integrated circuit comprising:
a semiconductor substrate comprising a first zone and a second zone; and
a thermoelectric generator formed at a surface of the semiconductor substrate, the thermoelectric generator comprising:
a plurality of trenches in the semiconductor substrate extending along parallel lines between the first zone and the second zone,
a plurality of ridges in the semiconductor substrate extending along parallel lines between the first zone and the second zone, each ridge of the plurality of ridges being separated from a nearest ridge of the plurality of ridges by a trench of the plurality of trenches and having a doped conductivity,
a first insulating layer in the plurality of trenches and on a top surface of the plurality of ridges,
a second insulating layer on a top surface of the first insulating layer,
an insulating coating on a top surface of the second insulating layer,
a first plurality of vias extending to the plurality of ridges in the first insulating layer, the second insulating layer, and the insulating coating, and
a patterned metallization overlying the insulating coating and electrically coupled to the plurality of ridges through the first plurality of vias, wherein
each ridge of the plurality of ridges has a current path from a first end adjacent the first zone to a second end adjacent the second zone, and
the current path of each ridge of the plurality of ridges is coupled in electrical series through the first plurality of vias and the patterned metallization.

2. The integrated circuit of claim 1, wherein the thermoelectric generator further comprises:
a plurality of semiconductor lines extending along parallel lines between the first zone and the second zone, each semiconductor line of the plurality of semiconductor lines having a first conductivity type and being formed in a trench of the plurality of trenches and separated from the semiconductor substrate by the first insulating layer, wherein the doped conductivity of the plurality of ridges comprises a second conductivity type that is opposite the first conductivity type; and
a second plurality of vias extending to the plurality of semiconductor lines in the first insulating layer, the second insulating layer, and the insulating coating, wherein
the patterned metallization is electrically coupled to the plurality of semiconductor lines through the second plurality of vias,
each semiconductor line of the plurality of semiconductor lines has a current path from a first end adjacent the first zone to a second end adjacent the second zone, and
the current path of each ridge of the plurality of ridges and the current path of each semiconductor line of the plurality of semiconductor lines are coupled in electrical series, alternating between the current path of a semiconductor line of the plurality of semiconductor lines and the current path of a ridge of the plurality of ridges, through the first plurality of vias, the second plurality of vias, and the patterned metallization.

3. The integrated circuit of claim 1, wherein:
the doped conductivity of the plurality of ridges comprises a first conductivity type and a second conductivity type that is opposite the first conductivity type;
each ridge of the plurality of ridges has either the first conductivity type or the second conductivity type; and
for each ridge of the plurality of ridges with the first conductivity type, a nearest ridge of the plurality of ridges has the second conductivity type.

4. The integrated circuit of claim 1, further comprising a plurality of non-volatile memory cells disposed in the semiconductor substrate.

5. The integrated circuit of claim 1, wherein the first insulating layer comprises an oxide.

6. The integrated circuit of claim 5, wherein the second insulating layer comprises a nitride.

7. The integrated circuit of claim 6, wherein the insulating coating comprises an oxide.

8. An integrated circuit comprising:
a semiconductor substrate comprising a first zone and a second zone; and
a thermoelectric generator formed at a surface of the semiconductor substrate, the thermoelectric generator comprising:
a plurality of trenches in the semiconductor substrate extending along parallel lines between the first zone and the second zone,
a plurality of ridges in the semiconductor substrate extending along parallel lines between the first zone and the second zone, each ridge of the plurality of ridges being separated from a nearest ridge of the plurality of ridges by a trench of the plurality of trenches and having a doped conductivity,
a first insulating layer in the plurality of trenches and on a top surface of the plurality of ridges,
a plurality of thermocouple structures on the first insulating layer, each thermocouple structure of the plurality of thermocouple structures comprising
a first semiconductor line having a first conductivity type,
a second semiconductor line having a second conductivity type opposite the first conductivity type, the first semiconductor line and the second semiconductor line extending along parallel lines between the first zone and the second zone, and
an insulating encasement separating the first semiconductor line from the second semiconductor line, the insulating encasement in contact with sidewalls of the first semiconductor line and in contact with sidewalls of the second semiconductor line,

a first plurality of vias extending to the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures,
a second plurality of vias extending to the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures, and
a patterned metallization overlying the plurality of thermocouple structures and electrically coupled to the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures through the first plurality of vias and to the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures through the second plurality of vias, wherein
the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures has a current path from a first end adjacent the first zone to a second end adjacent the second zone,
the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures has a current path from a first end adjacent the first zone to a second end adjacent the second zone, and
the current path of the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures and the current path of the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures are coupled in electrical series, alternating between the current path of a first semiconductor line of a thermocouple structure of the plurality of thermocouple structures and the current path of a second semiconductor line of a thermocouple structure of the plurality of thermocouple structures, through the first plurality of vias, the second plurality of vias, and the patterned metallization.

9. The integrated circuit of claim 8, wherein the first semiconductor line is directly above the second semiconductor line.

10. The integrated circuit of claim 8, wherein:
each trench of the plurality of trenches comprises a third semiconductor line extending between the first zone and the second zone, having the second conductivity type, and being separated from the semiconductor substrate by the first insulating layer, wherein the doped conductivity of the plurality of ridges comprises the first conductivity type; and
the thermoelectric generator further comprises
a third plurality of vias extending to the plurality of ridges, and
a fourth plurality of vias extending to the third semiconductor line of each trench of the plurality of trenches, wherein
each ridge of the plurality of ridges has the first conductivity type,
each ridge of the plurality of ridges has a current path from a first end adjacent the first zone to a second end adjacent the second zone,
the third semiconductor line of each trench of the plurality of trenches has a current path from a first end adjacent the first zone to a second end adjacent the second zone,
each ridge of the plurality of ridges has a current path from a first end adjacent the first zone to a second end adjacent the second zone, and
the current path of each ridge of the plurality of ridges, the current path of the third semiconductor line of each trench of the plurality of trenches, the current path of the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures, and the current path of the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures are coupled in electrical series through the first plurality of vias, the second plurality of vias, the third plurality of vias, the fourth plurality of vias, and the patterned metallization, wherein the current path of a first semiconductor line of a thermocouple structure of the plurality of thermocouple structures, the current path of a second semiconductor line of a thermocouple structure of the plurality of thermocouple structures, the current path of a third semiconductor line of a trench of the plurality of trenches, and the current path of a ridge of the plurality of ridges are alternatingly coupled in electrical series.

11. The integrated circuit of claim 10, wherein each thermocouple structure of the plurality of thermocouple structures is directly above either a trench of the plurality of trenches or a ridge of the plurality of ridges.

12. The integrated circuit of claim 10, wherein the first conductivity type is an N-type conductivity and the second conductivity type is a P-type conductivity.

13. The integrated circuit of claim 8, wherein the thermoelectric generator further comprises a third plurality of vias extending to the plurality of ridges, wherein:
the doped conductivity of the plurality of ridges comprises the first conductivity type and the second conductivity type;
each ridge of the plurality of ridges has either the first conductivity type or the second conductivity type;
for each ridge of the plurality of ridges with the first conductivity type, a nearest ridge of the plurality of ridges has the second conductivity type;
each ridge of the plurality of ridges has a current path from a first end adjacent the first zone to a second end adjacent the second zone; and
the current path of each ridge of the plurality of ridges, the current path of the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures, and the current path of the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures are coupled in electrical series through the first plurality of vias, the second plurality of vias, the third plurality of vias, and the patterned metallization, wherein the current path of a first semiconductor line of a thermocouple structure of the plurality of thermocouple structures, the current path of a second semiconductor line of a thermocouple structure of the plurality of thermocouple structures, and the current path of a ridge of the plurality of ridges are alternatingly coupled in electrical series.

14. The integrated circuit of claim 13, wherein each thermocouple structure of the plurality of thermocouple structures is directly above a trench of the plurality of trenches.

15. The integrated circuit of claim 8, wherein:
the doped conductivity of the plurality of ridges comprises the first conductivity type;
each ridge of the plurality of ridges has the first conductivity type; and
each ridge of the plurality of ridges has a current path from a first end adjacent the first zone to a second end adjacent the second zone.

16. The integrated circuit of claim 15, wherein each thermocouple structure of the plurality of thermocouple structures is directly above a ridge of the plurality of ridges.

17. The integrated circuit of claim 8, further comprising a plurality of non-volatile memory cells disposed in the semiconductor substrate.

18. An integrated circuit comprising:
a semiconductor substrate comprising a first zone and a second zone, the first zone comprising substrate material and the second zone comprising insulating material; and
a thermoelectric generator formed at a surface of the semiconductor substrate, the thermoelectric generator comprising:
a first insulating layer on a top surface of the semiconductor substrate,
a plurality of thermocouple structures on the first insulating layer, each thermocouple structure of the plurality of thermocouple structures comprising
a first semiconductor line having a first conductivity type,
a second semiconductor line having a second conductivity type opposite the first conductivity type, the first semiconductor line and the second semiconductor line extending along parallel lines between the first zone and the second zone, and
an insulating encasement separating the first semiconductor line from the second semiconductor line, the insulating encasement in contact with sidewalls of the first semiconductor line and in contact with sidewalls of the second semiconductor line,

a first plurality of vias extending to the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures,
a second plurality of vias extending to the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures, and
a patterned metallization overlying the plurality of thermocouple structures and electrically coupled to the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures through the first plurality of vias and to the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures through the second plurality of vias, wherein
the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures has a current path from a first end adjacent the first zone to a second end adjacent the second zone,
the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures has a current path from a first end adjacent the first zone to a second end adjacent the second zone, and
the current path of the first semiconductor line of each thermocouple structure of the plurality of thermocouple structures and the current path of the second semiconductor line of each thermocouple structure of the plurality of thermocouple structures are coupled in electrical series, alternating between the current path of a first semiconductor line of a thermocouple structure of the plurality of thermocouple structures and the current path of a second semiconductor line of a thermocouple structure of the plurality of thermocouple structures, through the first plurality of vias, the second plurality of vias, and the patterned metallization.

19. The integrated circuit of claim 18, wherein the first semiconductor line is directly above the second semiconductor line.

20. The integrated circuit of claim 19, wherein the first conductivity type is an N-type conductivity and the second conductivity type is a P-type conductivity.

21. The integrated circuit of claim 18, further comprising a plurality of non-volatile memory cells disposed in the semiconductor substrate.