# Patent

## Title
Semiconductor transistor having a stressed channel

## Abstract

A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

## Background
This is a continuation of U.S. patent application Ser. No. 12/269,829 filed on Nov. 12, 2008 (U.S. Publication No. 2009-0065808), which is a continuation of Ser. No. 11/233,854 filed on Sep. 9, 2005 (U.S. Pat. No. 7,492,017), which is a continuation of Ser. No. 11/107,141 filed on Apr. 14, 2005 (Abandoned), which is a continuation of Ser. No. 10/626,257 filed on Jul. 23, 2003 (U.S. Pat. No. 6,885,084), which is a continuation of Ser. No. 10/002,465 filed on Nov. 1, 2001 (U.S. Pat. No. 6,621,131).


BACKGROUND OF THE INVENTION
Integrated circuits are often manufactured in and on silicon and other semiconductor wafers. Such integrated circuits include literally millions of metal oxide semiconductor (MOS) field effect transistors, having gate lengths on the order of 0.05 microns. Such MOS transistors may include p-channel MOS (PMOS) transistors, and n-channel MOS (NMOS) transistors, depending on their dopant conductivity types.
Wafers are obtained by drawing an ingot of silicon out of a liquid silicon bath. The ingot is made of monocrystalline (single-crystal) silicon, and is subsequently sawed into individual wafers. A layer of silicon is then deposited over each wafer. Because the wafer is made of monocrystalline silicon, the deposition conditions can be controlled so that the layer of silicon deposits “epitaxially” over the wafer. “Epitaxy” refers to the manner in which the silicon layer deposits on the wafer—the layer of silicon has a lattice which has a structure which follows a structure of a lattice of the monocrystalline silicon of the wafer. The layer of silicon is also substantially the same material as the monocrystalline silicon of the wafer, so that the lattice of the silicon layer also has substantially the same spacing as the spacing of the lattice of the monocrystalline silicon of the wafer.
A gate dielectric layer, a gate electrode, and spacers are subsequently formed on the layer of silicon. Ions are also implanted into the layer of silicon, which form source and drain regions on opposing sides of the gate electrode. A voltage can be applied over the source and drain regions. Current flows from the source region to the drain region through a channel below the gate dielectric layer when a voltage is applied to the gate electrode.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described by way of example, with reference to the accompanying drawings, wherein:
FIG. 1 is a cross-sectional side view of a partially manufactured PMOS transistor, including a gate electrode and lightly doped regions on opposing sides of the gate electrode;
FIG. 2 is a view similar to FIG. 1, after the formation of spacers on opposing sides of the gate electrode;
FIG. 3 is a view similar to FIG. 2, after the formation of deeper source and drain regions;
FIG. 4 is a view similar to FIG. 3, after diffusion of the doped regions in a thermal step;
FIG. 5 is a view similar to FIG. 4, after a selective etch to form recesses in the source and drain regions;
FIG. 6 is a view similar to FIG. 5, after depositing source and drain films epitaxially in the recesses; and
FIG. 7 is an enlarged view of a portion of FIG. 6, illustrating stresses that are created by the films.



DETAILED DESCRIPTION OF THE INVENTION
A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon, germanium, and boron incorporated during deposition. By incorporating boron during deposition, a higher active dopant concentration can be obtained than with implantation techniques. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress, together with reduced resistivity due to the higher active dopant concentration, increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress. The present invention will be described with respect to the formation of a PMOS transistor. One skilled in the art will appreciate that an NMOS transistor may be manufactured in a similar manner, except that doping conductivity types and lattice spacing will be reversed.
FIG. 1 of the accompanying drawings illustrates an epitaxial silicon layer 10 which is epitaxially formed on a monocrystalline wafer substrate. Because the silicon layer 10 is epitaxially formed, it follows the monocrystalline crystal structure of the wafer substrate. The silicon of the layer 10 is thus also monocrystalline. The silicon layer 10 includes an n-type dopant, which can be formed by implanting phosphorous and arsenic ions to produce an n-well, having an n-type dopant concentration of approximately 5.0×1018/cm3 (an N+ film is thus created.)
A plurality of field isolation regions 12 are formed in the layer 10. The field isolation regions 12 isolate wells of different conductivity types, and isolate adjacent transistors. The field isolation regions 12 may, for example, be shallow trench isolation (STI) regions formed by etching a trench into the layer 10, and then filling the trench with deposited oxide.
A gate dielectric layer 14 is formed on a top surface 16 of the layer 10. The gate dielectric layer 14 may be a nitrided oxide layer formed to a thickness of between 5 and 30 Angstroms (Å), preferably approximately 8 Å.
A gate electrode 18 is formed on the gate dielectric layer 14. The gate electrode 18 is preferably between 1,000 and 3,500 Å thick. The gate electrode 18 may be formed by blanket deposition of polysilicon, and patterning the polysilicon into the gate electrode 18 utilizing known photolithographic techniques. In the exemplary embodiment, the gate electrode 18 has a width 20 of approximately 89 nm.
P-dopant ions are subsequently implanted from the top into an exposed upper surface of the layer 10, and into an exposed upper surface of the gate electrode 18. The dopant ions may, for example, be boron ions. The ions form conductive p-doped regions 22A and 22B. The regions 22A and 22B are located on opposing sides of the gate electrode 18, and are spaced from one another by the width 20. A conductive p-doped region 24 is also formed in an upper portion of the gate electrode 18.
FIG. 2 illustrates that spacers 26A and 26B are formed on opposing sides of the gate electrode 18. The spacers 26A and 26B cover sides of the gate electrode 18, and also cover portions of the surface 16 adjacent and on opposing sides of the gate electrode 18. In the present example, the spacers 26A and 26B are L-shaped spacers, the formation of which is known in the art.
As shown in FIG. 3, upper surfaces of the gate electrode 18 and the surface 16 are then again implanted with p-dopant ions, typically boron ions as in the implantation step of FIG. 1. The implantation energy is increased, compared to the implantation step of FIG. 1, so that the boron ions implant deeper into the layer 10. The spacers 26A and 26B form a mask which prevents implantation of the ions into the layer 10 below the spacers 26A and 26B. P-doped conductive regions 28A and 28B are formed by the ions in the layer 10 to a depth deeper than the regions 22A and 22B. However, a shallow channel 30 is defined between inner edges of the doped regions 22A and 22B resulting from the implantation step of FIG. 1. The doped region 24 in the gate electrode 18 is also deeper after the second implantation step.
A heat treatment or “annealing” step is subsequently carried out, wherein the structure of FIG. 3 is heated. Heating causes diffusion of the regions 22A, 22B, 28A, and 28B into the layer 10. As shown in FIG. 4, inner tips 34A and 34B are then located below the gate electrode 18. Lower edges of the regions 28A and 28B move downward into the layer 10. The regions 22A and 22B are epitaxial silicon with a p-dopant concentration of approximately 1×1019/cm3 (the regions 22A and 22B are thus doped P−). No other materials are present in the regions 22A and 22B, except silicon, arsenic, phosphorous, and boron. The doped region 24 in the gate electrode 18 also diffuses down to the gate dielectric layer 14.
FIG. 5 shows the structure of FIG. 4 after a selective etch step. An anisotropic etchant is used which selectively removes silicon over the other exposed materials of the structure of FIG. 4. Recesses 36A and 36B are thereby etched into the regions 28A and 28B. Inner edges of the recesses 36A and 36B are aligned with outer edges of the spacers 26A and 26B. Outer edges of the recesses 36A and 36B are at the field isolation regions 12. It should be noted that surfaces 38 of the recesses 36A and 36B are monocrystalline epitaxial silicon. Epitaxial silicon has a lattice with a known structure and spacing. An upper portion of the gate electrode 18 is also etched out.
As shown in FIG. 6, source and drain films 40A and 40B are subsequently formed in the recesses 36A and 36B. The films 40A and 40B are epitaxially formed on the surfaces 38. The films 40A and 40B include silicon, germanium, and boron. The films can be formed in a 200 mm chemical vapor deposition chamber with the following processing conditions: dichlorosilane of 20 sccm, diborane of 70 sccm at 1% concentration, and germane of 50 sccm, at a temperature of 740° C.
The silicon and the germanium form an alloy having a lattice which has the same structure as the structure of the lattice of the epitaxial silicon of the surfaces 38. The lattice of the alloy of silicon and germanium, however, has a larger spacing than the spacing of the lattice of the epitaxial silicon of the surfaces 38, at least in a relaxed state. Because the lattice of the alloy has the same structure as the surfaces 38, the films 40A and 40B form epitaxially on the surfaces 38. However, because of the larger spacing of the lattice of the alloy, the films 40A and 40B create a compressive stress in the channel 30. The germanium is present in the combination of the silicon and the germanium in about 15 atomic percent. It has been found that epitaxy can be maintained with a germanium concentration of up to 20 atomic percent of the combination of the silicon and germanium by volume. Epitaxy thus tends to break down at an atomic percentage of germanium of above 20 percent. A further advantage of depositing the films 40A and 40B is that a relatively large boron concentration can be included. The boron concentration is preferably approximately 3×1020/cm3 (the films 40A and 40B are thus doped P+). The relatively large concentration of boron creates a relatively low resistance of approximately 0.9 mOhm-cm. A conductive p-doped film 42 also deposits on the etched-back gate electrode 18. Suitable results can be obtained with dopant concentrations of 0.5×1020/cm3 and above. The resistivity is preferably less than 1.1 mOhm-cm.
FIG. 7 illustrates the direction of compressive stresses created by the films 40A and 40B. The directions of the compressive stresses are along the lines 50. A more dense spacing between the lines 50 indicates a larger stress, and a larger spacing between the lines 50 indicates a smaller stress. It can be seen that the largest stress is created at or near the channel 30. The films 40A and 40B extend to a depth 52 into the layer 10, and are spaced from one another by a width 54. A smaller ratio between the depth 52 and the width 54 will result in a smaller stress in the channel 30, and a larger ratio between the depth 52 and the width 54 will result in a larger stress in the channel 30. A ratio between the depth 52 and the width 54 is preferably at least 0.12, more preferably 0.15, more preferably 0.2, and more preferably 0.35. In the present example, the depth 52 is 92 nm, and the width 54 is 215 nm.
The compressive stress reduces the effective mass in the channel, which in turn increases hole mobility. It has been found that a compressive stress in the channel 30 increases the IDSAT of the PMOS transistor 60 by approximately 20 percent. The IDLIN is increased by approximately 40 percent.
In the present example, the layer 10 is epitaxial silicon, and the films 40A and 40B are silicon with a germanium additive. It may be possible to create similar structures utilizing additives other than germanium. The present example has also been described with reference to a PMOS transistor. An NMOS transistor may be manufactured in a similar manner. In an NMOS transistor, doping conductivity types would be reversed. Furthermore, a tensile stress will be created in the channel. A tensile stress can be created utilizing source and drain films of silicon which includes carbon. The silicon and carbon form an alloy which has a lattice with the same structure as the structure of the lattice of the epitaxial silicon, but with a smaller spacing. The source and drain films will tend to contract, and create a tensile stress in the channel.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.

## Claims

1. A transistor comprising:
a silicon layer disposed directly on a monocrystalline substrate, the silicon layer having a first lattice constant;
a silicon channel region disposed in said silicon layer;
a gate dielectric layer over the silicon channel region, wherein the gate dielectric layer includes an oxide and a nitride and is formed to a thickness of between 5 Angstroms and 30 Angstroms;
a gate electrode on the gate dielectric layer;
a pair of spacers on opposing sides of the gate electrode; and
source and drain regions on opposite sides of the silicon channel region and above a portion of said silicon layer, the source and drain regions each having a first portion comprising a boron doped portion of said silicon layer and a second portion above the first portion, the second portion comprising a boron doped epitaxial silicon germanium layer having a second lattice constant that is different than the first lattice constant of the silicon layer, wherein:
the second portion creates a compressive stress in the silicon channel region;
the first portion extends to a first depth below the second portion, which extends to a second depth, separating the second portion from the silicon layer; and
the first portion extends to a third depth, less than the second depth, beneath the pair of spacers and beneath a portion of the gate dielectric layer, separating the second portion from the channel region.

2. The transistor of claim 1, wherein the gate dielectric comprises an oxynitride layer.

3. The transistor of claim 1, further comprising a shallow trench isolation region adjacent to the source region or the drain region.

4. The transistor of claim 1, wherein the silicon channel region further comprises an n-type dopant.

5. The transistor of claim 4, wherein the silicon layer comprises the n-type dopant.

6. The transistor of claim 5, wherein the silicon layer and channel region have the substantially the same n-type dopant concentration.

7. The transistor of claim 1, wherein the n-type dopant comprises one or both of phosphorous and arsenic.

8. The transistor of claim 1, wherein the boron dopant concentration in the first portion disposed below the spacers is less than the boron dopant in the second portion.

9. A transistor comprising:
a silicon layer disposed directly on a monocrystalline substrate, the silicon layer having a first lattice constant matching that of the substrate;
a silicon channel region disposed in said silicon layer;
a gate dielectric layer disposed over the silicon channel region and having a thickness of between 5 Angstroms and 30 Angstroms;
a gate electrode disposed over the gate dielectric layer;
a pair of dielectric spacers disposed on opposing sides of the gate electrode; and
source and drain regions disposed on opposite sides of the silicon channel region and disposed over a portion of said silicon layer, the source and drain regions each having a first portion comprising boron doped silicon separating the silicon layer from a second portion of the source and drain regions comprising a boron doped epitaxial silicon germanium layer having a second lattice constant that is different than the first lattice constant, wherein:
the second portion creates a compressive stress in the silicon channel region; and
the first portion extends to a depth less than that of the second portion within a region of the silicon layer beneath the pair of spacers and beneath a portion of the gate dielectric layer, laterally separating the second portion from the channel region.

10. The transistor of claim 9, wherein the gate dielectric comprises and oxide and nitride.

11. The transistor of claim 9, further comprising a shallow trench isolation region adjacent to the source region or the drain region.

12. The transistor of claim 9, wherein the silicon channel region further comprises an n-type dopant.

13. The transistor of claim 9, wherein the n-type dopant comprises one or both of phosphorous and arsenic.

14. The transistor of claim 9, wherein the silicon layer comprises the n-type dopant.

15. The transistor of claim 14, wherein the silicon layer and channel region have the substantially the same n-type dopant concentration.

16. The transistor of claim 9, wherein the boron dopant concentration in the first portion disposed below the spacers is less than the boron dopant in the second portion.