# Patent

## Title
Integrated circuit interconnects and methods of making same

## Abstract

A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.

## Background
This application is a continuation of U.S. application Ser. No. 13/559,107, filed on Jul. 26, 2012, entitled “Integrated Circuit Interconnects and Methods of Making Same,” which application is incorporated by reference herein.


BACKGROUND
Since the mid-1990's so-called damascene processes have been the dominant technology for forming conductive interconnect in integrated circuits. Those skilled in the art recognize that damascene processing involves forming opening (via and trenches) in a dielectric layer and then filling the openings with a conductive, typically copper. The copper is typically deposited by initially depositing a thin seed layer within the openings and then filling the opening by electroplating copper.
One disadvantage of the prior art is that forming openings in the dielectric layer requires etching the dielectric layer. This etch process may damage the dielectric layer, particularly as the industry trends progress toward lower dielectric constant (low k) dielectric layers, which are more vulnerable to damage from the etching process. Increased leakage current, reduced dielectric constant, and reduced performance and reliability may result from the etch-induced damage to the dielectric layer.
Another disadvantage of the traditional damascene approach is that the etching processes can also damage a barrier layer that is frequently used to line the opening prior to deposition of the copper. Furthermore, subsequent thermal processing may sometimes cause the copper features within the openings to deform, such as to form a hump in the center, which can negatively impact the device performance and reliability.
What is needed then is a interconnect structure and method of forming same that overcomes or reduces the disadvantages of the prior art.



BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGS. 1a through 1g are cross-sectional views of an illustrative method of forming an integrated circuit interconnect structure; and
FIG. 2 is a cross-sectional view of a multi-chip structure manufactured according to an illustrative embodiment.



DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.
Embodiments will be described with respect to a specific context, namely an interconnect structure for an integrated circuit. Other embodiments may also be applied, however, to other semiconductor devices and feature. For instance, the present teachings could be applied to structures other than an integrated circuit, such as an interposer device, a printed circuit board, a package substrate, and the like.
With reference now to FIG. 1, there is shown an illustrative integrated circuit (structure) 100 shown in highly simplified cross-sectional views. Various features not necessary for understanding of the invention have been omitted for sake of clarity and brevity. Integrated circuit 100 includes a substrate 2 upon which has been formed an etch stop layer 4. Substrate 2 refers generally to any structures or materials underlying etch stop layer 4. In some applications, substrate 2 includes a semiconductor wafer such as a bulk silicon wafer or a silicon (or other semiconductor material) layer formed atop a bulk wafer and separated therefrom by, e.g., a buried oxide layer in a so-called silicon on insulator (SOI) arrangement. One or more active or passive devices, such as transistors or capacitors, could be formed in substrate 2. In another application, substrate 2 could be an underlying metal (or other conductor) layer in a multi-metal interconnect scheme. For instance, substrate 2 could be an underlying metal layer (or several stacked metal layers) manufactured according to the steps illustrated in FIGS. 1a through 1g. 
A dielectric layer, preferably a low k dielectric layer 6 is formed on the etch stop layer. Low k generally refers to a dielectric layer having a dielectric constant of less than about 3.9. Materials such as porous silicon oxide, doped silicon oxide, silicon carbide, silicon oxynitride, and the like could be employed for dielectric layer 6, although these are examples only and are not intended to be exhaustive or limiting.
Hard mask 8 is formed atop dielectric layer 6. In a case where dielectric layer 6 is an oxide, hard mask 8 could be, for example, silicon nitride or another material that has a high degree of resistance to etchants typically employed to etch oxides. Other materials, such as SiCN, SiOC, and the like could also be employed for hard mask 8.
Mask 10 is formed atop hard mask 8. In the illustrated embodiment, mask 10 is a tri-layer mask comprising three separate layers. While a conventional mask layer, such as a single polymer photoresist layer, could be employed, a tri-layer mask 10 allows for the formation of finer features having smaller dimensions and pitch. In the illustrated embodiment, bottom layer 12 of tri-layer mask 10 is a carbon organic layer, similar to a conventional photoresist layer. Middle layer 14 is a silicon containing carbon film, employed to help pattern bottom layer 12. Top layer 16 is a photoresist material, such as for instance, a photoresist material designed for exposure to 193 nm wavelengths, and preferably designed for immersion photolithography, for instance.
As shown in FIG. 1a, an opening is formed in mask 10, using known lithography techniques, such as for instance, immersion photolithography. This opening will be transferred to all layers of mask layer 10, through hard mask stop layer 8 and then to dielectric layer 6 and etch stop layer 4, resulting in an opening 20, sometimes referred to herein as a via opening, being formed in dielectric layer 6 and etch stop layer 4, as shown in FIG. 1b. Note that opening 20 exposes an underlying portion of substrate 2 which, as described above, could be an underlying conductive interconnect, a transistor contact, or the like. Mask 10 is removed using known ashing and/or etching techniques, the details of which are omitted herein.
Turning now to FIG. 1c, a metal interconnect material 22 is deposited over structure 100. In illustrated embodiments, metal interconnect material is a copper alloy. Examples of a suitable copper alloy include CuMn, CuCr, CuV, CuNb, and CuTi. The copper alloy may be in the range of from about 90% copper to about 99.8% copper. Other suitable alloys and percentages will be apparent to those skilled in the art upon undertaking routine experimentation once informed by the present disclosure. By using a copper alloy material, it is possible to manufacture copper interconnects without the need to form barrier liners, such as Ta/, TaN, and the like, that are commonly employed in conventional damascene processes. That being said, it is within the contemplated scope of the present invention that a barrier liner could be employed in some applications.
In one embodiment, metal interconnect material 22 is formed by a plasma vapor deposition (PVD) that completely fills opening 20 and forms a blanket coating over a top surface of dielectric layer 6, or more accurately over the top surface of hard mask 8 overlying dielectric layer 6. In some embodiments, hard mask 8 may be omitted, in which case metal interconnect material 22 would be formed on dielectric layer 6. Metal interconnect material 22 may be formed to a thickness above dielectric layer 6 of from about 500 A to about 2 um, depending upon the desired application and the technology node employed.
In another embodiment, metal interconnect material 22 is formed by first depositing a seed layer by, e.g., PVD deposition techniques. The seed layer could be formed to a thickness of perhaps about 20 Å to about 100 Å, although other thicknesses could be employed depending upon the application and the desired process. Then a copper alloy material is formed on the seed layer using, e.g., an electro-plating or electro-less plating technique.
Etch stop layer 24 is formed on metal interconnect material 22, as also shown in FIG. 1c. In one embodiment, etch stop layer 24 is formed of silicon nitride, silicon carbon nitride, or another material that provides sufficient etch selectivity relative to the metal material.
Turning now to FIG. 1d, a second mask 27 is formed. In the illustrated example, mask 27 is a tri-layer mask similar to mask 10 illustrated in FIG. 1a. As with the previously described steps, it is not necessary to use a tri-layer mask, unless the particular application and feature size calls for such an approach. Regardless of the mask type employed, a pattern is formed in mask layer 27 as shown in FIG. 1d. Next, as shown in FIG. 1e, the pattern is transferred to metal interconnect material 22 using known lithography techniques. Metal interconnect material is preferably etched anisotropically etched to form nearly vertical sidewalls. In some embodiments, a chlorine plasma etch is employed to pattern metal interconnect material 22. Other plasma etches, including reactive ion etching (RIE), could also be employed.
The result of the etching step is that metal interconnect material 22 is patterned into various wires or interconnects 26. These interconnects run across the major surface of device 100 and are sometimes referred to herein as horizontal interconnects to distinguish from the vertical interconnects (vias) 28 formed in the openings 20. Because metal is formed in the via openings 20 simultaneously with forming the blanket coating, using a single process step, the horizontal and vertical interconnects form a single continuous feature. One skilled in the art will recognize that horizontal interconnect features 26 and vertical interconnect features 28 are functionally equivalent to metal-filled trenches and vias formed using conventional damascene processes. Damage to the surrounding dielectric layers, however, that result from damascene processes is avoided, as is the potential for damage to barrier liners.
Figure if illustrates the results of an anneal step. Structure 100 is subjected to an anneal whereby a self-aligned metal oxide barrier 30 is formed. In one embodiment, structure 100 is placed in an inert environment, such as 95% H2, 5% N2 and annealed at a temperature of from about 200 C to about 400 C for a time period of from about 30 minutes to about 120 minutes, for example. As a result of the anneal, a relatively thin metal oxide barrier is formed around the copper alloy features (e.g., around horizontal interconnects 26 and vertical interconnects 28). It is believed that moisture within the anneal chamber and within materials adjacent the copper alloy features contribute to the process of forming the metal oxide barrier. In illustrative embodiments, metal oxide barrier 30 is formed to a thickness of about 20 Å. Other thicknesses could readily be obtained depending upon the desired application and process parameters. This metal oxide barrier prevents diffusion of copper into the surrounding dielectric materials.
FIG. 1g illustrates the results of a deposition step in which a second dielectric layer 32 is deposited over structure 100. Second dielectric layer 32 is preferably a low k dielectric layer and may be of the same material as dielectric layer 6 or some other material. In one embodiment, dielectric layer 32 is formed of SiOC, as an example. Other materials could also be used. In some embodiments, dielectric layer 32 is formed by CVD deposition. In other embodiments, dielectric layer 32 is formed by a spin on coating process. In either event, it is sufficient that dielectric layer 32 be able to satisfactorily fill gaps between adjacent horizontal interconnect features 26 and cover (and hence electrically insulate) the features. Although shown as a single layer, dielectric layer 32 could be a compound layer comprised of two or more different materials and/or sub-layers.
An advantageous, but not necessary, feature of the illustrated embodiment is the formation of air gaps 34 in the spaces between adjacent horizontal interconnect features. In some embodiments, the spacing between adjacent horizontal interconnect features may be as little as 14 nm or 10 nm. In future applications, it is contemplated the spacing could be even less. Because horizontal interconnect features may be intended to current electrical signals, capacitance between adjacent interconnect features could adversely impact performance. The presence of air gaps 34 between adjacent interconnect features lowers the dielectric constant between the features and hence reduces parasitic capacitance therebetween. One skilled in the art will recognize that deposition parameters can be adjusted to obtain such air gaps, upon routine experimentation once informed by the present disclosure.
Further processing steps could include planarizing a top surface of dielectric layer 32, and/or the formation of additional vertical and horizontal interconnect features. As but one example, additional openings could be formed in dielectric layer 32 and additional vertical and horizontal interconnects formed in and on, respectively, dielectric layer 32, by repeating the above described process steps in which case dielectric layer 32 would be substituted for dielectric layer 6 in the above description. Alternatively, dielectric layer could be thinned down (e.g., via chemical mechanical polish, CMP, by etch back, or the like) and a separate dielectric layer, which would be substituted for dielectric layer 6, could be formed and the above steps repeated thereon. In some embodiments, dielectric layer 32 could be a topmost dielectric layer, which could then be treated for bonding to a corresponding layer of a second integrated circuit device in a so-called direct bonding process. In yet another embodiment, contact pads or the like could be formed atop dielectric layer 32 or in the form of one or more horizontal interconnect features 26, for connecting integrated circuit structure 100 to another device, such as another integrated circuit, an interposer, a circuit board, or the like.
FIG. 2 illustrates an application wherein a first structure 100, such as an integrated circuit, is electrically interconnected to a second structure 200, such as a second integrated circuit, an interposer, an printed circuit board, a package substrate, or the like, by way of a connector element 300, such as a solder bump or solder ball, a copper pillar, a copper bump, or the like. More specifically, a first circuit element 27, such as a transistor, a resistor, a capacitor, or the like, of structure 100 is electrically connected to a first contact pad 29 of structure 100, which in turn electrically connects to a second contact pad 31 of second structure 200 via connector 300. Second contact pad 31 is electrically connected to a second circuit 33 of second structure 200. In this way, first circuit element 27 is electrically connected to second circuit 33 by way of horizontal and vertical interconnects 26 and 28, respectively, which are manufactured according to the above-described embodiments.
Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
As but one example, in some embodiments, an integrated circuit interconnect structure is formed by forming a dielectric layer on a substrate and patterning the dielectric layer to from an opening in the dielectric layer. The opening is filled with a metal and at the same time the dielectric layer is covered with the metal. The metal is patterned to form interconnect features. The interconnect features are annealed, thus forming a metal oxide barrier. A second dielectric material is then deposited around the interconnect features.
As another example, an integrated circuit interconnect structure is formed by forming a via opening in a dielectric layer, and filling the via opening with a copper alloy while at the same time depositing a blanket coating of the copper alloy over a top surface of the dielectric layer. The method includes patterning the blanket coating of the copper alloy to form interconnect features, wherein at least two of the interconnect features are separated by a gap. The interconnect features are covered and the gap is filled with a second dielectric layer.
In yet another embodiment, an integrated circuit interconnect structure comprises a first dielectric layer and a continuous copper alloy feature extending vertically into the first dielectric layer and extending vertically over the first dielectric layer. The structure further includes a second copper alloy feature extending horizontally over the first dielectric layer, and a copper oxide barrier layer substantially surrounding the continuous copper alloy feature. The structure also includes a second dielectric layer as between the continuous copper alloy feature and the second copper alloy feature, and an air gap within the second dielectric layer, the air gap being between the continuous copper alloy feature and the second copper alloy feature.

## Claims

1. An integrated circuit interconnect structure comprising:
a first dielectric layer;
a continuous copper alloy feature extending vertically into and over the first dielectric layer,
a second copper alloy feature extending horizontally over the first dielectric layer;
a continuous copper oxide barrier layer disposed on sidewalls, a top surface, and a bottom surface of the continuous copper alloy feature;
a second dielectric layer between the continuous copper alloy feature and the second copper alloy feature; and
an air gap within the second dielectric layer, wherein the air gap is between the continuous copper alloy feature and the second copper alloy feature.

2. The integrated circuit interconnect structure of claim 1, wherein the continuous copper alloy features comprise a material selected from the group consisting essentially CuMn, CuCr, CuV, CuNb, CuTi, and combinations thereof.

3. The integrated circuit interconnect structure of claim 2, wherein the continuous copper alloy feature comprises from about 90% to about 99.8% copper.

4. The integrated circuit interconnect structure of claim 1, wherein the integrated circuit interconnect structure electrically connects a CMOS transistor formed in a first integrated circuit to an electrical circuit formed in a second integrated circuit.

5. The integrated circuit interconnect structure of claim 1, wherein the air gap does not extend into the first dielectric layer.

6. The integrated circuit interconnect structure of claim 1 further comprising an etch stop layer disposed on a top surface of the continuous copper oxide barrier layer.

7. The integrated circuit interconnect structure of claim 6, wherein sidewalls of the etch stop layer are aligned with sidewalls of the continuous copper oxide barrier layer.

8. The integrated circuit interconnect structure of claim 1 further comprising a hard mask disposed between the first dielectric layer and the second dielectric layer, wherein the hard mask extends under the air gap.

9. The integrated circuit interconnect structure of claim 1 further comprising a substrate, wherein the substrate sits underneath the first dielectric layer.

10. An integrated circuit structure comprising:
a continuous conductive feature comprising:
a vertical interconnect; and
a first horizontal interconnect over and connected to the vertical interconnect;

a first barrier layer disposed on sidewalls, a top surface, and bottom surfaces of the continuous conductive feature;

an etch stop layer disposed on a top surface of the first barrier layer, wherein sidewalls of the etch stop layer and the first barrier layer are substantially aligned;
a second horizontal interconnect disposed adjacent the continuous conductive feature, wherein bottom surfaces of the second horizontal interconnect and the first horizontal interconnect are substantially level;
a second barrier layer disposed on sidewalls, a top surface, and the bottom surface of the second horizontal interconnect;
a dielectric layer over the continuous conductive feature and the second horizontal interconnect, wherein the dielectric layer extends between the first and the second horizontal interconnects; and
an air gap in the dielectric layer.

11. The integrated circuit structure of claim 10, wherein the air gap is disposed between the first and the second horizontal interconnects.

12. The integrated circuit structure of claim 10, wherein the air gap does not extend past a bottom surface of the second barrier layer.

13. The integrated circuit structure of claim 10, wherein the etch stop layer is further disposed on a top surface of the second barrier layer, wherein sidewalls of the etch stop layer and the second barrier layer are substantially aligned.

14. The integrated circuit structure of claim 10 further comprising a second dielectric layer under the dielectric layer, wherein the second dielectric layer is disposed around the vertical interconnect.

15. The integrated circuit structure of claim 10, wherein the continuous conductive feature and the second horizontal interconnect comprise a copper alloy.

16. The integrated circuit structure of claim 15, wherein the copper alloy comprises a material selected from the group consisting essentially CuMn, CuCr, CuV, CuNb, CuTi, and combinations thereof.

17. The integrated circuit structure of claim 10, wherein the continuous conductive feature and the second horizontal interconnect comprise a copper alloy.

18. A device comprising:
a first horizontal interconnect;
a first continuous barrier layer disposed on a top surface, sidewalls, and a bottom surface of the first horizontal interconnect;
a second horizontal interconnect adjacent the first horizontal interconnect;
a second continuous barrier layer disposed on a top surface, sidewalls, and a bottom surface of the second horizontal interconnect;
an etch stop layer disposed on top surfaces of the first and the second continuous barrier layer;
a first dielectric layer over and contacting the etch stop layer, wherein the first dielectric layer extends between the first and the second horizontal interconnects; and
an air gap disposed within the first dielectric layer between the first and the second horizontal interconnects.

19. The device of claim 18, further comprising:
a second dielectric layer under the first dielectric layer; and
a vertical interconnect extending through the second dielectric layer, wherein the vertical interconnect is connected to the first horizontal interconnect with no interface formed therebetween.

20. The device of claim 18, wherein sidewalls of the etch stop layer are substantially aligned with sidewalls of the first continuous barrier layer and the second continuous barrier layer.