# Patent

## Title
Bias circuit for BJT amplifier

## Abstract

The embodiments of the present invention include a bias circuit for a power-amplifying device, which receives and amplifies an input RF signal having a series of RF cycles within a modulation envelop. The bias circuit compensates odd-order distortion processes by detecting the power in the input signal and providing a dynamic adjustment to a bias stimulus for the power-amplifying device within a time scale of the modulation envelope.

## Background
FIELD OF THE INVENTION
The present invention relates to radio-frequency (RF) power amplifier circuits and, in particular, to bias circuits that serve to minimize distortion in the amplifier circuits.
BACKGROUND OF THE INVENTION
Electronic equipment such as computers, wireless devices, broadband devices, radios, televisions and other similar devices communicate with each another by transmitting signals through air, space and guided media such as wire, cable, microstrip, waveguide, and optical fiber. These transmission signals undergo a variety of processes throughout their communication paths, one of which involves amplifying the signals using power amplifiers.
A radio frequency (RF) power amplifier is a circuit that is capable of receiving an RF input signal and amplifying it to produce an RF output signal that is a magnified version of the input signal. RF power amplifiers are frequently used in communications systems such as wireless telephony, satellite links, optical transceivers, and cable television distribution systems. An RF amplifier typically includes at least one power-amplifying device, such as a power-amplifying transistor, and a bias circuit that sets a quiescent operating point of the transistor. The transistor may be a field effect transistor (FET) device, such as a laterally-diffused metal-oxide-semiconductor (LDMOS) transistor, or a bipolar junctions transistor (BJT) device, such as a heterojunction bipolar transistor (HBT).
In a transistor-based RF amplifier, there are tradeoffs between maximizing efficiency and preserving the fidelity of the RF signal. The efficiency of the amplifier is defined as the output RF signal power divided by the power supplied to the amplifier from a power supply. The fidelity of an amplified signal is often described in terms of a deviation from an ideal linear noiseless process and is characterized using a variety of metrics including harmonic distortion, intermodulation distortion, adjacent channel power ratio (ACPR), cross-modulation, error vector magnitude, and bit error rate, etc., most of which are interrelated. For communication systems involving a modulated carrier signal whose modulation frequency is a small fraction of the carrier frequency, odd-order intermodulation distortion (IMD) processes are the primary sources of deleterious signal distortion in power amplifiers. In a given communication system, the contributing effects of such distortion can be related to other performance metrics such as bit error rate and error vector magnitude. Thus, in the following description, odd-order IMD and its related ACPR characteristic are mainly used as the metrics for the fidelity of amplified signals. See Cripps, “Power Amplifiers for Wireless Communications,” Artech House: Norwood, Mass., 1999, and Pedro and Carvalho, “Intermodulation Distortion in Microwave and Wireless Circuits,” Artech House: Norwood, Mass., 2003.
Given the inherent tradeoff between efficiency and linearity (fidelity), practitioners in the art of power amplifier design have developed a broad portfolio of circuit concepts and methods for exercising this tradeoff. One primary technique for increasing the efficiency of a power amplifier is to control the conduction angle of the transistor device. Various classes of amplifiers have been devised to manage the conduction angle, such as class-A, class-AB, class-B, class-C, class-D, class-F, and class-S amplifiers, listed roughly in the order of reduced conduction angle. See Clark and Hess, “Communication Circuits: Analysis and Design,” Wiley: New York, 1971, and H. L. Krauss et al., “Solid State Radio Engineering,” Wiley: New York, 1980.
The reduced conduction angle allows the amplifier to approach the efficiency of a switching device at the expense of signal distortion and gain. Furthermore, BJT operation at high power (e.g., 2-10 W) and high voltage (e.g., >10V) requires substantial thermal ballasting in either or both of the base and emitter terminals of the power-amplifying transistor. See Anholt, “Electrical and Thermal Characterization of MESFETs, HEMTs, and HBTs,” Artech House: Norwood, Mass., 1995. Such thermal ballasting helps to increase the current-handling capability and thermal stability of the power-amplifying device but at the same time degrade the linearity of the amplifier circuit. See Pedro and Carvalho, supra, and Vuolevei and Rahkonen, “Distortion in RF Power Amplifiers,” Artech House: Norwood, Mass., 2003. The engineering challenge in modern RF power amplifier design is to devise circuits with an optimum configuration of transistor device, tuning, conduction angle and bias control to maximize efficiency while controlling odd-order distortion processes to meet the linearity specifications for a particular communication signal or system.
SUMMARY
The embodiments of the present invention include a bias circuit for a power-amplifying device that receives and amplifies an input RF signal having a series of RF cycles within a modulation envelop. The bias circuit compensates odd-order distortion processes by detecting the power in the input signal and providing a dynamic adjustment to a bias stimulus for the power-amplifying device within a time scale of the modulation envelope. The present invention is applicable in general to all reduced conduction angle amplifiers. In the examples described herein, class-B and class-AB amplifiers employing BJT or HBT power-amplifying devices are mainly discussed. For ease of discussion, the terms ‘BJT’ and ‘class-AB’ are used with the understanding that such terms encompass both ‘BJT’ and ‘HBT’ and both ‘class-AB’ and ‘class-B’, respectively, and with the assertion that the techniques described herein can be applied to other reduced conduction angle power amplifiers.
In one embodiment of the present invention, an amplifier circuit for amplifying an input RF signal has an input terminal for receiving the RF input signal, an output terminal for outputting an amplified RF signal, and an RF power-amplifying device having a base coupled to the input terminal and a collector coupled to the output terminal. The amplifier circuit further comprises a bias circuit coupled to the base of the RF power-amplifying transistor through at least one impedance element. The bias circuit is also coupled to the input terminal and configured to couple a portion of the RF input signal into the bias circuitry. The bias circuit thus produces a bias circuit gain that depends on the RF power level in the RF input signal and that compensates for voltage drops along a current path through the power amplifying device by raising the DC voltage at the base of the RF power-amplifying device in response to an increase in the RF power level in the RF input signal.
In one embodiment, the bias circuit includes a PN junction diode having first and second terminals, the first terminal being coupled to the base of the RF amplifying transistor through at least one impedance element, and the second terminal being coupled to a bypass capacitor, which is coupled to an RF ground in the amplifier circuit. The bypass capacitor therefore holds the second terminal at a constant voltage despite fluctuations in the RF signal. As the RF power level in the RF input signal is increased, the average voltage across the PN junction diode is decreased, causing the base voltage of the RF power-amplifying device to increase. The PN junction diode may be the base-emitter (or base-collector) junction of a detecting transistor and the bypass capacitor is coupled to the base of the detecting transistor.
The RF amplifier circuit further comprises a reference voltage terminal for connecting to a reference voltage supply, a bias voltage terminal for connecting to a bias voltage supply, a first bias transistor having a collector coupled to the reference voltage supply through a reference resistor, an emitter coupled to a circuit ground terminal through a first emitter degeneration resistor, and a base, and a second bias transistor coupled with the detecting transistor in a current mirror configuration, the second bias transistor having a base connected to the base of the detecting, transistor at a common connected base node, an emitter coupled to the base of the first bias transistor through a second emitter degeneration resistor, and a collector coupled to the bias voltage terminal. The bypass capacitor is coupled between the common connected base node and the circuit ground.
In some embodiments, the power-amplifying device includes at least one BJT device, and the bias circuit employs BJT components so that the current-mirror serves two functions simultaneously. One function is to provide a current-mirror or level-shifting operation required for setting and controlling the quiescent conditions for the BJT in the power-amplifying device. The second function is to respond to the modulation envelope in the input RF signal by rectifying each negative half cycle in the input RF signal. The charge accumulated in each negative half cycle is deposited in the bypass capacitor and a properly amplified and delayed version of this charge is returned back through the bias circuit to affect, on the time scale of the modulation, the base-to-emitter voltage of the RF amplifying transistor. When this dynamic bias action is adjusted correctly through proper design of the impedance elements, the embodiments of the present invention achieve a substantial reduction in odd-order intermodulation distortion over a useful power range (approximately 6-10 dB) while simultaneously providing the necessary bias isolation, matching, power/phase distribution, and ballasting over the power-amplifying device. In this way, the higher efficiency of reduced conduction angle operation is realized while the linearity requirements of the communication signal are satisfied.
The amplifier circuit may include an array of transistor cells in the power-amplifying device, with some or all of the other components of the amplifier circuit effectively distributed to provide proper RF phasing and ballasting across the array of transistor cells.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a functional block diagram of a bipolar junction transistor (BJT) amplifier circuit employing a reduced conduction angle amplifier, such as class-AB, class-B or class-C amplifier, according to one embodiment of the present invention.
FIG. 2 is a chart illustrating the power gain, base-emitter voltage (VBE) and collector current (ICC) characteristics as a function of input RF signal power commonly associated with a class-AB amplifier.
FIG. 3 is a circuit schematic diagram illustrating a bias circuit in the BJT amplifier circuit according to one embodiment of the present invention.
FIG. 4 is a cross-sectional view of a bipolar junction transistor (BJT) in the amplifier circuit shown in FIG. 3 according to one embodiment of the present invention.
FIGS. 5(a)-5(f) are circuit schematic diagrams illustrating several exemplary embodiments for the impedance elements in the BJT amplifier circuit.
FIG. 6 is a circuit schematic diagram illustrating a modified current mirror bias network according to an alternative embodiment of the present invention.
FIG. 7 is a circuit schematic diagram illustrating a modified current mirror bias network according to yet another alternative embodiment of the present invention.
FIG. 8 is a circuit schematic diagram illustrating a distributed current mirror bias network for a physical BJT array according to embodiments of the present invention.
FIG. 9 is a circuit schematic diagram illustrating a distributed current mirror bias network for a physical BJT array according to alternative embodiments of the present invention.
FIG. 10 is a circuit schematic diagram illustrating a distributed current mirror bias network for a physical BJT array according to yet another embodiment of the present invention.



DETAILED DESCRIPTION
FIG. 1 depicts a simplified block diagram of a single-stage transistor amplifier network (amplifier) 100, according to one embodiment of the present invention. As shown in FIG. 1, amplifier 100 includes an RF power-amplifying device QRF having an input 101 and an output 102, a bias circuit 110 coupled to the input 101 of the power-amplifying device QRF, an input impedance matching section 120 also coupled to the input 101 of the power-amplifying device QRF through a blocking capacitor CIN, an output bias and impedance matching section 130 coupled to the output 102 of the power-amplifying device QRF, and terminals RFIN, RFOUT, VREF, VBIAS, and VCC.
Terminal RFIN is coupled to the input impedance match section 120 for receiving an RF input signal, terminal RFOUT is coupled to the output bias and impedance match section 130 for outputting an amplified RF signal, terminal VCC is for connecting to a primary power supply voltage used to power the amplifier network 100 and is coupled to the output 102 of the power-amplifying device QRF through the output bias and impedance matching section 130, and terminals VREF and VBIAS are input terminals for the bias circuit 110. The input terminals VREF and VBIAS connect with a reference voltage VREF and a bias voltage VBIAS, respectively.
The reference voltage VREF is a well-controlled voltage used to set a quiescent bias condition for the amplifier network 100. It is commonly derived from a specialized bandgap reference circuit to provide a consistent DC voltage over a specified range of current at the output 102 of power-amplifying device QRF and over a specified range of ambient temperature. The bias voltage VBIAS is from a DC voltage source with sufficient voltage amplitude and current capacity to power the bias circuit 110 and feed the input 101 of the power-amplifying device QRF. In common battery-powered applications, VBIAS is often connected to VCC through a suitable network of decoupling capacitors. In high voltage applications associated with high power amplifiers, the bias voltage VBIAS is often derived from VCC but is regulated down to a lower voltage.
In one embodiment, the power-amplifying device QRF includes a bipolar junction transistor (BJT) having a base and a collector coupled to the input 101 and output 102 of the power-amplifying device QRF, respectively, and the amplifier 100 further includes impedance elements Z1, Z2, and Z3. Impedance element Z1 is coupled between the bias circuit 110 and the blocking capacitor CIN, impedance element Z2 is coupled between the impedance element Z1 and the base of the BJT, and impedance element Z3 is coupled between an emitter of the BJT and a circuit ground. Power-amplifying device QRF may include a single transistor device, such as a BJT, or a transistor cell array, as discussed below. In a non-limiting example, the BJT is suitable for connecting to a high voltage (e.g., 10-28 V) VCC power supply can sustain a collector current ICC up to a maximum collector current ICmax of about 100 mA.
Under small-signal operation, the bias circuit 110 provides the necessary bias current, IBIAS, to the base of the power-amplifying device QRF, so as to set the quiescent bias condition of the amplifier network 100 while offering minimal RF loading to the base of the power-amplifying device QRF. The quiescent operating point is associated with a set of direct current (DC) operating conditions without any applied RF stimulus or input signal. In the case that the power-amplifying device QRF includes a BJT, the set of DC operating conditions include such parameters as quiescent collector current ICC, quiescent base current IB, which comes from the bias current IBIAS, quiescent base-emitter voltage VBE, etc., for the power-amplifying BJT device. In addition to providing the bias current IBIAS for the power-amplifying device, the bias circuit 110 also controls the current and temperature compensation for the power-amplifying device.
The input impedance matching section 120 is designed to transform the impedance presented by the series combination of the blocking capacitor CIN and the input 101 of the power-amplifying device QRF to the conjugate of a source impedance ZS. The output bias and match section 130 serves two functions: one is to provide a low-loss path for a DC current to supply power to the power-amplifying device QRF. The second function is to provide a low-loss impedance transformation to maximize the transfer of RF power from the output 102 of the power-amplifying device QRF to a load impedance ZL.
Under large-signal class-AB operation, the RF input power in the RF input signal received at the input terminal RFIN reacts with the base-emitter junction of a BJT in the power-amplifying device QRF to draw additional current from the bias circuit 110. This in turn draws more collector current ICC at the collector of the BJT from the VCC power supply. For a typical class-AB BJT in the power-amplifying device QRF, FIG. 2 demonstrates how the power gain GAIN, base-emitter voltage VBE, and collector current ICC of the BJT responds to varying levels of continuous-wave RF input power (PIN) and includes GAIN(PIN) curves 212, 214, and 216, VBE(PIN) curves 222, 224, and 226, and a ICC(PIN) curve. As discussed above, with increased RF input power PIN, the interaction of the base-emitter junction of the BJT with the RF input power causes the bias circuit 110 to supply additional base current IB. As the bias circuit 110 responds to supply more base current IB, the finite resistance of bias circuit 110, along with Z1, Z2, and Z3, causes the voltage VBE across the base-emitter junction of the power-amplifying device QRF to decrease with increasing amount of RF input power PIN, as shown by VBE(PIN) curves 222, 224, and 226.
The characteristics of the VBE(PIN) curves, along with the initial quiescent and tuning conditions, would determine the nature of the amplifer's gain response GAIN(PIN). In general, a VBE(PIN) function with decreasing VBE at low input power, as shown by the curve 226, would tend to exhibit a GAIN(PIN) characteristic with early gain compression, as shown by the GAIN(PIN) curve 216. A VBE(PIN) function that reasonably maintains VBE over a wider input power range, as shown by curve 222, would tend to exhibit flat gain or even gain expansion, as shown by curve 212. Curves 224 and 214 demonstrate normal situations. The detailed nature of the GAIN(PIN) characteristic and the dynamics of how this function responds to a modulated RF signal is closely related to the odd-order intermodulation distortion generated by the amplifier.
Under modulated RF drive conditions, a modulated RF signal is supplied to the input terminal RFIN. A graphical depiction of a modulated RF signal 140 is also shown in FIG. 1 at the RFIN terminal and indicates the time-varying nature of an RF envelope 142 along with a magnified view of a single RF cycle 144 in an RF carrier. Since the frequency of the modulation is small compared to the frequency of the RF carrier, the time scale for changes to the envelope is long compared to the RF cycle time. Given the relatively slowly varying envelope, a single RF cycle will exhibit a positive half cycle 146 that closely matches its negative half cycle 148.
For a class-AB BJT in the power-amplifying device QRF under large-signal operations, the RF input signal 140 can be viewed as a sequence of positive-half-cycle and negative-half-cycle perturbations to the quiescent bias condition of the BJT. During the positive half-cycle, the RF input signal is sufficient to turn ON the base-emitter junction of the BJT and transfer charge from the blocking capacitor CIN to the BJT with the flow of a first current component iPOS. During the negative half-cycle, the RF input signal is sufficient to turn OFF the base-emitter junction of the BJT, and in the absence of this conduction path, charge is transferred to the blocking capacitor CIN from the bias circuit 110 through impedance element Z1 with the flow of a second current component iNEG. The time integration of these two current components creates an increasing DC base current IB,TOT with increasing RF input power and leads directly to the upward ICC(PIN) curve shown in FIG. 2. These two current components also interact with Z1, Z2, Z3 and the bias circuit 110 to affect other characteristics such VBE(PIN), Gain(PIN) and the odd-order IMD of the amplifier circuit 100.
Impedance elements such as Z2 and/or Z3 are often required for BJT power-amplifying devices because BJT operation at high power (e.g., 2-10 W) and high voltage (e.g., >10 V) requires substantial thermal ballasting in either or both of the base and emitter terminals of the power-amplifying device QRF. Unlike its FET counterpart, a BJT RF power-amplifying device often requires proper base impedance tuning at both the second harmonic frequency as well as the modulation frequency to achieve optimum linear performance. A simple input matching circuit 110 outside the bias current path is unable to satisfy these requirements for RF frequencies near 1 GHz and above. So, when a BJT is used as power-amplifying device QRF, the inclusion of Z1 and/or Z2 is often necessary to provide a combination of emitter and base ballasting with the equivalent effect of:

Rballast≅Z3,DC+(Z1,DC+Z2,DC)/β

where Z1,DC, Z2,DC, and Z3,DC are the DC resistance associated with the impedance elements of Z1, Z2, and Z3, respectively.

Having included the three impedance elements Z1, Z2, Z3 to meet the stated electro-thermal requirements, it is found that these same elements also hinder the flow of iNEG and iPOS under large signal operation and cause VBE(PIN) to drop prematurely with increasing input power PIN. This leads to poor large-signal RF power and linearity performance as depicted by curves 216 and 226 in FIG. 2. The present invention seeks to remedy this problem by constructing the bias circuit 110 that interacts cooperatively with the blocking capacitor CIN, the power-amplifying device QRF, and the three impedance elements Z1, Z2, and Z3 to simultaneously satisfy the electrical and thermal requirements for stable, efficient, and linear class-AB BJT amplifier operation.
In the following descriptions, like reference characters and symbols designate like or corresponding parts in the various embodiments. For example, the circuit element such as CIN or QRF performs similar functions in the illustrated embodiments. It is understood that the exemplary illustrations are for the purpose of describing the preferred embodiments of the present invention and are not intended to limit the invention thereto.
In one embodiment of the present invention, as illustrated in FIG. 3, the bias circuit 110 in the amplifier network 100 includes bias transistors Q1 and Q2, two emitter degeneration resistors RE1 and RE2 associated with the bias transistors Q1 and Q2, respectively, a reference resistor RREF, a buffer transistor Q4, a detecting transistor QDET, and a bypass capacitor CDET associated with the detecting transistor QDET. The bias circuit 110, the power-amplifying device QRF, and the impedance elements Z1, Z2, and Z3 together form a current mirror with the bases of transistor Q4 and QDET connected to a common connected-base node 310, transistor Q1 coupled with transistor Q2 in a Darlington configuration with the emitter of transistor Q2 coupled to the base of transistor Q1, and power-amplifying device QRF coupled with transistor QDET also in a Darlington configuration with the emitter of transistor QDET coupled to the input 101 of power-amplifying device QRF. Thus, DC conducting circuit elements in the amplifier network 100 to the left of the connected-base node 310, such as transistors Q1 and Q2, and resistors RE1 and RE2, form a reference branch 330 of the current mirror, and DC conducting elements to the right of the base node 310, such as transistors QRF and QDET, and DC conducting elements in the impedance elements Z1, Z2, Z3, form an amplifier branch 340 of the current mirror.
Transistor Q4 is a buffer transistor for the current mirror and has its base coupled to the VREF input via the reference resistor RREF, its emitter coupled to the connected-base node 310, and its collector coupled to the VBIAS input. Transistor QDET has its collector coupled to the VBIAS input and its emitter coupled to the input 101 of the power amplifying device QRF through impedance elements Z1 and Z2. Transistor Q2 has its collector coupled to the VBIAS input and its emitter coupled to the base of transistor Q1 via the resistor RE2. Transistor Q1 has its emitter coupled to the circuit ground through resistor RE1 and its collector coupled to the VREF input through resistor RREF. Bypass capacitor CDET is coupled between the base of transistor QDET and an RF ground 312, which can be a circuit ground, or a DC voltage terminal, such as the VREF, VBIAS, or VCC terminal.
In one embodiment, each of the four transistors Q1, Q2, Q4, and QDET is a BJT formed on a same semiconductor die with the power-amplifying device QRF, and shares a common DC current gain factor, β>>1 with the BJT in the power-amplifying device QRF. FIG. 4 is a simplified block diagram of a cross-sectional view of a BJT 400 that can be used as the transistor Q1, Q2, Q4, QDET, or the BJT in the power-amplifying device QRF. As shown in FIG. 4, BJT 400 includes an emitter 410 formed over an emitter layer 412, which is formed over a base layer 422, on which is also formed a base 420. The base layer 422 is formed over a collector layer 432, which is formed over a subcollector layer 434, on which is also formed a collector 430. The subcollector layer is formed near a top surface 452 of a substrate 450.
The BJT 400 can be fabricated using any of the BJT technologies in the art. In one embodiment of the present invention, the BJT 400 is fabricated using a Gallium Arsenide HBT semiconductor processing technology, and the emitter 410 includes a N+ InGaAs contact over a N+ InGaAs graded cap layer over a N+ GaAs cap contact layer. The emitter layer 412 includes a N-type AlGaAs or InGaP layer, the base layer 422 includes a P+ GaAs layer, the collector layer 432 includes a N− GaAs layer, the subcollector layer 434 includes a N+ GaAs layer, and the substrate 450 is a GaAs substrate. The BJT 400 may also be fabricated using an Indium Phosphide (InP) semiconductor process technology with an InP layer in the emitter layer 412, the base layer 422, and/or the collector layer 432. In another embodiment, the BJT 400 is fabricated using a SiGe semiconductor processing technology with SiGe in the emitter layer 412, the base layer 422, and/or the collector layer 432.
Because of the current mirror configuration in the bias circuit 110, as shown in FIG. 3, the bias current IB,TOT drawn by the power-amplifying device QRF from the bias circuit 110 is insensitive to variations in the current gain β of transistor Q1 and current gain βRF of power-amplifying device QRF, so long as β and βRF track one another, a simple requirement that is not difficult to achieve for transistor devices manufactured on a same semiconductor die. The quiescent collector current of transistor QRF can be designed as a scaled ratio of the quiescent collector current of Q1 by adjusting an effective emitter area ratio associated with the two transistors, again a simple requirement for devices on a same semiconductor die. The quiescent base-emitter voltage VBE1 of transistor Q1 sets the quiescent base-emitter voltage VBE of transistor QRF and can provide a nearly constant VBE over increasing RFIN power up to a certain point, as illustrated by the curves 222, 224, and 226 in FIG. 2.
The buffer transistor Q4 amplifies and buffers the reference current through the resistor RREF and effectively decouples the bias current from any limitations of VREF and RREF while maintaining the benefits of the current mirror configuration, as described above.
In one embodiment, transistors Q1 and Q2 in the reference branch 330 of the current-mirror serve as a scaled-down version of transistors QRF and QDET, respectively, in the amplifier-branch 340 of the current mirror. In one embodiment, the effective emitter areas of transistors QRF and QDET are N-times as large as the effective emitter areas of transistors Q1 and Q2, respectively, where N is a scaling factor. The scaling factor N is generally chosen to be large such that the current drawn through transistor Q1 is small compared to the quiescent collector current of the power-amplifying device QRF. If K is the factor by which the collection current ICC of the power-amplifying device QRF would increase over the quiescent collector current ICQ to support a required RF power range, then N should preferably satisfy the inequality, NK<<β2, to ensure that the reference branch of the current mirror is not starved for current during peak RF envelope power excursions. In one embodiment, the emitter area of buffer transistor Q4 is chosen so as not to limit the current into the base of transistor QDET during peak RF operating conditions.
Resistor RREF is designed to set the quiescent collector current of transistor QRF, which is approximately given by,




  
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where VBE1, VBE2, and VBE4 are the forward voltage drops across the base-emitter junctions of Q1, Q2 and Q4, respectively, and the voltage drop across RE2 is assumed to be small. For a given BJT process technology, the magnitude of the voltage VBE across the base-emitter junction of power-amplifying device QRF is relatively insensitive to the forward current and is typically in the range of 0.9-1.0V when power-amplifying device QRF includes a Si-based BJT, or in the range of 1.3-1.4V when power-amplifying device QRF includes a GaAs-based HBT.

Resistors RE1 and RE2 are generally chosen to mirror, in a scaled form, the DC resistance of Z3 and (Z1+Z2), respectively, such that

RE1≅N(Z3,DC), and

RE2≅N(Z1,DC+Z2,DC).

The design constraints pertaining to impedance elements Z1, Z2, and Z3 are numerous. To ensure thermal stability for the transistor or transistor cell array comprised in QRF, an impedance sum of ZBallast=(Z3+Z2/β) should be sufficiently large at DC and up to a frequency roughly equal to 1/τth, where τth is a dominant thermal time constant for the power-amplifying device QRF. In the situation power-amplifying device QRF comprises a transistor array, the impedance sum ZBallast may also include a contribution of Z1/β from impedance element Z1, depending on the exact layout of the QRF transistor cell array. The sum of ZBallast=(Z3+Z2/β+Z1/β) at DC is generally designed to be a minimum value required for thermal stability, as any excess resistance in the amplifier network 100 places increasing demands on the bias circuit 110 to compensate for the voltage drops along the bias current path through the input 101 of the power amplifying device QRF. At the RF carrier frequency, Z1, Z2, and Z3 should cooperate with the input match 120 to provide low reflection at the RFIN terminal. At the modulation frequency and the second harmonic frequency, Z1, Z2, and Z3 are generally designed to provide low IMD distortion when the input signal power is relatively small.

As discussed above, the bias circuit 110 sets a bias current and controls the quiescent condition and temperature compensation for the power-amplifying device QRF. As the RF input power increases, the base-emitter junction of the power-amplifying device QRF begins to rectify as does the base-emitter junction of transistor QDET, and this sets up the sequence of positive-half-cycle and negative-half-cycle perturbations to the quiescent bias condition described above with reference to FIG. 1. In one embodiment of the present invention, a detector function as described below is provided by the detecting transistor QDET and bypass capacitor CDET. The base-emitter junction of the detecting transistor QDET in the bias circuit 110 provides a PN junction diode 320 having a P-terminal coupled to the RF ground 312 through the bypass capacitor CDET and an N-terminal coupled to the terminal RFIN through the impedance element Z1, the blocking capacitor CIN, and the input match section 120. Because the P-terminal is held to a DC voltage through the bypass capacitor, the PN junction diode 320 is allowed to respond to the RF modulation envelope in the input RF signal by rectifying each negative half cycle in the input RF signal. The charge accumulated in each negative half cycle is deposited in the bypass capacitor CDET and a properly amplified and delayed version of this charge is returned back through the emitter of the detecting transistor QDET. The series combination of bypass capacitor CDET, the base-emitter junction of the detecting transistor QDET, impedance element Z1, and blocking capacitor CIN, as shown in FIG. 3, facilitates a charge-pump action to help drive this charge into the base of QRF, resulting, on an average, an effective bias circuit gain depending on the RF input power in the dynamic bias current IB,TOT.
The effective bias circuit gain results in increasing voltage at the base of the power-amplifying transistor QRF with increasing RF power level in the RF input signal. The increasing voltage at the base of the power-amplifying transistor QRF offsets the increasing voltage drops across Z1, Z2, and Z3 as the RF power level increases. Thus, the bias circuit 110 dynamically modifies, on the time scale of the modulation in the RF input signal, the base-to-emitter voltage of the RF amplifying transistor QRF. When this dynamic bias action is adjusted correctly through proper design of the three impedance elements, the embodiments of the present invention achieve a much improved VBE(PIN) curve and, as a result, a substantial reduction in odd-order intermodulation distortion over a useful input power range (approximately 6-10 dB), while at the same time providing the necessary bias isolation, matching, power/phase distribution, and ballasting for the power-amplifying device QRF. In this way, the higher efficiency of reduced conduction angle operation is realized while the linearity requirements of the communication signal is satisfied.
The charge-pump action described above should be slow enough to smooth the individual RF cycle peaks but fast enough to follow the modulation envelope. These requirements can be used to set upper and lower bounds for the values of CDET. As a non-limiting example, the upper and lower bounds of CDET are set to be about




  
    
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  ,




respectively, where FMOD is the highest modulation frequency in the RF input signal 140, FRF is the RF carrier frequency in the RF input signal 140, and ZBASE is the magnitude of the impedance at the base node of detecting transistor QDET when detecting capacitor CDET is removed from the circuit.

FIGS. 5(a)-5(f) are a schematic diagrams illustrating exemplary embodiments of the impedance elements Z1, Z2, and Z3 as two-terminal networks for the sake of illustration. At frequencies near 1 GHz and above, these elements are more accurately described as two-port impedance networks interacting with a circuit ground plane. Elements Z2 and Z3 should be placed in close physical proximity with transistors QRF and QDET and are typically integrated within the same semiconductor die as the transistors. As such, they may be constrained by the integrated circuit fabrication technology and limited to such networks depicted in FIGS. 5(a), 5(b), and 5(c) with the capacitance C typically less than 100 pF, or limited to such networks depicted in 5(d), 5(e), and 5(f) for modest values of inductance L typically less than 5 nH. Element Z1 is generally less constrained and can take any of the forms shown in FIGS. 5(a) through 5(f), or another form as needed to satisfy the electrical and thermal requirements described above with reference to FIG. 3. Z1 can be realized within the same semiconductor die as the transistors, outside the semiconductor die, or as some combination thereof.
The sensitivity of the PN junction diode 320, and thus the sensitivity of the effective bias circuit gain, to the changes in the RF input power, can be adjusted by adjusting the amount of RF impedance in the impedance elements Z1. For a given Z1, the rectifying effect of the PN junction diode 320 in the detecting transistor QDET is about the same, whether Z1 is lumped or distributed among the transistor cells in the power-amplifying device QRF, if power-amplifying device QRF includes an array of transistor cells.
In a non-limiting example, Z2 is not required, Z1 takes the form shown in FIG. 5(a) with R in the range of about 15Ω to about 100Ω, and Z3 also takes the form shown in FIG. 5(a) with R in the range of about 1Ω to about 6Ω. In another example, Z2 is not required, Z3 takes the form shown in FIG. 5(a) with R in the range of about 0.5Ω to about 3Ω, and Z1 takes the form shown in FIG. 5(c) with R1 in the range of about 15Ω to about 100Ω, R2 in the range of about 50Ω to about 300Ω, and C around 10 pF. In a further example, Z1 takes the form shown in FIG. 5(a) with R in the range of about 15Ω to about 100Ω, Z2 takes the form shown in FIG. 5(b) with R in the range of about 50Ω to about 300Ω and C around 10 pF, and Z3 takes the form shown in FIG. 5(a) with R in the range of about 0.5Ω to about 3 Ω.
The circuit topology and design guidelines described above should provide a dynamic bias circuit gain sufficient to overcome, to a first order, the voltage drops across Z1, Z2, and Z3 thus leading to a desirable VBE(PIN) characteristics and linear power gain characteristic, as depicted by the GAIN(PIN) curves 222 and 212 in FIG. 2. Computer simulation can be used to provide a more detailed circuit analysis and to further refine the design of the amplifier network 100 to satisfy the linearity requirements of a particular communication signal or system.
In an alternative embodiment, the bias circuit 110 lacks the buffer transistor Q4, as shown in FIG. 6, and is generally suited to applications requiring a smaller amplifying transistor QRF, or applications having a lower reference voltage, VREF, which is unable to support the voltage drops across the base-emitter junctions of all of the three transistors Q4, QDET, and QRF, as shown in FIG. 3. Without the buffer transistor Q4, the base and collector of transistor Q2 are tied and are coupled to the VREF terminal through the resistor RREF. FIG. 6 also illustrates an example of a negative feedback network 610 including a capacitor CF and a resister RF serially coupled with each other between the VBIAS terminal and the connected bases of transistors Q2 and QDET, and is designed to suppress electrical oscillations within the bias circuit 110.
In yet another embodiment, the bias circuit 110 includes a transistor-resistor tier 710 including a resistor RE1, a transistor Q1, a resistor RE2, a transistor Q2, a resistor RE3, and a transistor Q3 serially connected with each other between RREF and a circuit ground. Transistors Q1, Q2, and Q3 each has its base and collector tied. The bias circuit 110 in FIG. 7 includes an additional transistor Q5 coupled with the transistor Q3 in a current mirror arrangement with their bases connected to a common connected-base node 720. The buffer transistor Q4 is absent and the negative feedback network 610 is provided between the base and collector of transistor Q5. The DC conducting circuit elements in FIG. 7 to the left of the connected-base node 720 form a reference branch 722 of the current mirror, while DC conducting elements to the right of the base node 720 form an amplifier branch 724 of the current mirror. In one embodiment, the reference branch 722 includes transistors Q1, Q2, and Q3, and the amplifier branch 724 includes transistors QRF, QDET, and Q5. As in the previously described embodiments, transistors Q1, Q2, and Q3 in the reference branch 722 of the current-mirror serve as a scaled-down version of transistors QRF, QDET, and Q5, respectively, in the amplifier-branch 724 of the current mirror.
The detector function in FIG. 7 is provided by the detecting transistor QDET, which is configured in the form of a level-shifting diode with its connector and base tied and connected to the emitter of transistor Q5. As in all the previously described embodiments, the bypass capacitor CDET is coupled between the base of the detecting transistor QDET and the circuit ground. The embodiment shown in FIG. 7 offers more flexibility in terms of temperature compensation via transistors Q1 and Q2 and their respective emitter resistors RE1 and RE2. Charge drawn from the bypass capacitor CDET down through the detecting transistor QDET in the amplifier network 100 shown in FIG. 7, however, lacks the current gain exhibited by the embodiments shown in FIGS. 3 and 6. But the basic operating principles of the bias circuit 110 are the same in all of the embodiments described above.
FIG. 8 is a schematic diagram illustrating an amplifying network 800 according to yet another embodiment of the present invention. As shown in FIG. 8, amplifying network comprises an array of n rows by m columns of transistor cells with a total of (m)(n) transistor cells each labeled as QRF. Such transistor cell arrays are common in modern semiconductor RF power devices. The transistor cell array may be large enough to require the three impedance elements Z1, Z2, Z3 and blocking capacitor CIN to be distributed among the transistor cells to satisfy the RF phase and thermal stability requirements. The detecting transistor QDET and its associated bypass capacitor CDET are generally required to be placed in close proximity with the amplifying transistor cells, so these elements are distributed across the m columns in the transistor array but can be lumped within each of the m columns, as shown in FIG. 8. A resistor RSTAB is often included in the bias circuit and is coupled between the emitters of two adjacent detecting transistors QDET to suppress odd-mode oscillations therein. The values of the distribution of parallel elements shown in FIG. 8 are scaled from the respective lumped circuit element values described in FIG. 6, as listed in Table 1.









TABLE 1





(I) Lumped
(II) Equivalent



Circuit Element
Distributed Circuit
Change from


value in FIG. 6
Element Value in FIG. 8
(I) to (II)







RREF
RREF
Unchanged


RE1
RE1
Unchanged


RE2
RE2
Unchanged


(Q1 Area)
(Q1 Area)
Unchanged


(Q2 Area)
(Q2 Area)
Unchanged


(QDET Area)
(QDET Area)/m
Scale Down by m


CDET
(CDET)/m
Scale Down by m


CIN
CIN/(mn)
Scale Down by mn


Z1
Z1(mn)
Scale Up by mn


Z2
Z2(mn)
Scale Up by mn


Z3
Z3(mn)
Scale Up by mn


(QRF Area)
(QRF Area)/(mn)
Scale Down by mn









The input matching section 220 and output bias and matching section 230 need not be changed in going from the lumped circuit depicted in FIG. 6 to the distributed circuit depicted in FIG. 8. It is good RF design practice, however, to match the input and output phase delays to the individual transistor cells QRF to maximize the gain and power combining efficiency of the transistor cell array. Such standard layout practices are common and familiar to those skilled in the art of integrated-circuit power amplifiers and are not explicitly shown in FIG. 8.
FIG. 9 is a schematic diagram illustrating another embodiment of a distributed amplifier network 900 wherein the transistor column length n is short enough and the impedance element Z1 is low enough to allow Z1 to be lumped within each transistor column like the QDET and CDET elements. Thus, amplifier network 900 shown in FIG. 9 is preferred where possible to amplifier network 800 shown in FIG. 8 because a simpler layout is provided in the amplifier network 900. The scaling rules for scaling the values of relevant circuit elements in network 900 from the values of the corresponding lumped circuit depicted in FIG. 6 are similar those for scaling the relevant circuit elements in network 800, as listed in Table 1, except that Z1 is scaled up by a factor of m instead of mn, and the capacitance CIN is unchanged relative to that in FIG. 6.
FIG. 10 is a schematic diagram illustrating yet another embodiment of a distributed amplifier network 1000 wherein the transistor column length, n, is short enough and the impedance elements Z and Z2 are low enough to allow both Z1 and Z2 to be lumped within each column like the QDET and CDET elements. Thus, amplifier network 1000 shown in FIG. 10 is preferred where possible to amplifier network 800 or 900 shown in FIG. 8 or 9, respectively, because a simpler layout is provided in the amplifier network 1000. The scaling rules for scaling the values of relevant circuit elements in network 1000 from the values of the corresponding lumped circuit depicted in FIG. 6 are similar those for scaling the relevant circuit elements in network 800, as listed in Table 1, except that both Z1 and Z2 are scaled up by a factor of m instead of mn, and the capacitance CIN is unchanged relative to that in FIG. 6. With both Z1 and Z2 lumped, however, Z3 needs to provide the full amount of ballasting.
The foregoing discussion and supporting illustrations are for exemplary purposes only and should not be construed as limiting the present invention. Substantial variations and combinations of the exemplary bias circuits may be practiced without departing from the spirit and scope of the present invention. For example, the embodiments described herein may be modified to include additional circuit elements to affect the stability and frequency response or to adjust the temperature or voltage compensation. Those skilled in the art will readily appreciate that these and other similar modifications are well within the scope of the present invention.

## Claims

1. A radio frequency (RF) amplifier circuit having an input terminal for receiving a RF input signal, comprising:
a RF power-amplifying transistor having a base coupled to the input terminal;
a bias circuit coupled to the input terminal and to the RF power-amplifying transistor, the bias circuit including a bypass capacitor and a PN junction diode having first and second terminals, the first terminal being coupled to the base of the RF amplifying transistor through at least one impedance element, the second terminal is coupled to a RF ground in the RF amplifier circuit through the bypass capacitor
wherein the bias circuit is configured to raise a voltage at the base of the RF power-amplifying transistor in response to an increase in an RF power level in the RF input signal; and
the PN junction diode is part of a detecting transistor having a base and a collector, the RF amplifier circuit further comprising:
a reference voltage terminal for connecting to a reference voltage supply;
a bias voltage terminal for connecting to a bias voltage supply;
a first bias transistor having a collector coupled to the reference voltage supply through a reference resistor, an emitter coupled to a circuit ground terminal through a first emitter degeneration resistor, and a base; and
a second bias transistor coupled with the detecting transistor in a current mirror configuration, the second bias transistor having a base connected to the base of the detecting transistor at a common connected base node, an emitter coupled to the base of the first bias transistor through a second emitter degeneration resistor, and a collector coupled to the bias voltage terminal.

2. The RF amplifier circuit of claim 1, wherein each of the at least one impedance element includes a two-port impedance network.

3. The RF amplifier circuit of claim 1, wherein the PN junction diode is part of a detecting transistor having a base and a collector that are tied to each other.

4. The RF amplifier circuit of claim 1, wherein the bypass capacitor is coupled between the common connected base node and the circuit ground.

5. The RF amplifier circuit of claim 1, further comprising a buffer transistor having a base coupled to the reference voltage terminal through the reference resistor, an emitter coupled to the common connected base node, and a collector coupled to the bias voltage terminal.

6. The RF amplifier circuit of claim 1, wherein the PN junction diode is part of a detecting transistor having a base and a collector, the RF amplifier circuit further comprising:
a reference voltage terminal for connecting to a reference voltage supply;
a first bias transistor having an emitter coupled to a circuit ground terminal through a first emitter degeneration resistor, and a base and a collector tied with each other; and
a second bias transistor coupled with the detecting transistor in a current mirror configuration, the second bias transistor having a base connected to the base of the detecting transistor at a common connected base node, an emitter coupled to the tied base and connector of the first bias transistor through a second emitter degeneration resistor, and a collector tied to the base of the second bias transistor and coupled to the reference voltage terminal via a reference resistor.

7. The RF amplifier circuit of claim 6, further comprising
a bias voltage terminal for connecting to a bias voltage supply, wherein the detecting transistor has a collector coupled to the bias voltage terminal; and
a negative feedback network coupled between the collector of the detecting transistor and the common connected base node, the negative feedback network including a resistor and a capacitor serially connected with each other.

8. The RF amplifier circuit of claim 1, further comprising:
a reference voltage terminal for connecting to a reference voltage supply;
a tier of serially connected level-shifting diodes coupled between the reference voltage terminal and a circuit ground;
a bias transistor having an emitter coupled to the PN junction diode, a base coupled to the tier of serially connected level-shifting diodes, and a collector coupled to the base of the bias transistor through a negative feedback network.

9. The RF amplifier circuit of claim 8, wherein the tier of serially connected level-shifting diodes includes first, second and third bias transistors and first, second, and third emitter degeneration resistors, each of the first, second and third bias transistors having a base and a collector tied with each other and an emitter coupled to respective ones of the first, second, and third emitter degeneration resistors.